aic6915.c revision 1.27
1 /* $NetBSD: aic6915.c,v 1.27 2010/04/05 07:19:33 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Adaptec AIC-6915 (``Starfire'') 34 * 10/100 Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aic6915.c,v 1.27 2010/04/05 07:19:33 joerg Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #include <net/bpf.h> 60 61 #include <sys/bus.h> 62 #include <sys/intr.h> 63 64 #include <dev/mii/miivar.h> 65 66 #include <dev/ic/aic6915reg.h> 67 #include <dev/ic/aic6915var.h> 68 69 static void sf_start(struct ifnet *); 70 static void sf_watchdog(struct ifnet *); 71 static int sf_ioctl(struct ifnet *, u_long, void *); 72 static int sf_init(struct ifnet *); 73 static void sf_stop(struct ifnet *, int); 74 75 static bool sf_shutdown(device_t, int); 76 77 static void sf_txintr(struct sf_softc *); 78 static void sf_rxintr(struct sf_softc *); 79 static void sf_stats_update(struct sf_softc *); 80 81 static void sf_reset(struct sf_softc *); 82 static void sf_macreset(struct sf_softc *); 83 static void sf_rxdrain(struct sf_softc *); 84 static int sf_add_rxbuf(struct sf_softc *, int); 85 static uint8_t sf_read_eeprom(struct sf_softc *, int); 86 static void sf_set_filter(struct sf_softc *); 87 88 static int sf_mii_read(device_t, int, int); 89 static void sf_mii_write(device_t, int, int, int); 90 static void sf_mii_statchg(device_t); 91 92 static void sf_tick(void *); 93 94 #define sf_funcreg_read(sc, reg) \ 95 bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg)) 96 #define sf_funcreg_write(sc, reg, val) \ 97 bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val)) 98 99 static inline uint32_t 100 sf_reg_read(struct sf_softc *sc, bus_addr_t reg) 101 { 102 103 if (__predict_false(sc->sc_iomapped)) { 104 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess, 105 reg); 106 return (bus_space_read_4(sc->sc_st, sc->sc_sh, 107 SF_IndirectIoDataPort)); 108 } 109 110 return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg)); 111 } 112 113 static inline void 114 sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val) 115 { 116 117 if (__predict_false(sc->sc_iomapped)) { 118 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess, 119 reg); 120 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoDataPort, 121 val); 122 return; 123 } 124 125 bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val); 126 } 127 128 #define sf_genreg_read(sc, reg) \ 129 sf_reg_read((sc), (reg) + SF_GENREG_OFFSET) 130 #define sf_genreg_write(sc, reg, val) \ 131 sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val)) 132 133 /* 134 * sf_attach: 135 * 136 * Attach a Starfire interface to the system. 137 */ 138 void 139 sf_attach(struct sf_softc *sc) 140 { 141 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 142 int i, rseg, error; 143 bus_dma_segment_t seg; 144 u_int8_t enaddr[ETHER_ADDR_LEN]; 145 146 callout_init(&sc->sc_tick_callout, 0); 147 148 /* 149 * If we're I/O mapped, the functional register handle is 150 * the same as the base handle. If we're memory mapped, 151 * carve off a chunk of the register space for the functional 152 * registers, to save on arithmetic later. 153 */ 154 if (sc->sc_iomapped) 155 sc->sc_sh_func = sc->sc_sh; 156 else { 157 if ((error = bus_space_subregion(sc->sc_st, sc->sc_sh, 158 SF_GENREG_OFFSET, SF_FUNCREG_SIZE, &sc->sc_sh_func)) != 0) { 159 aprint_error_dev(&sc->sc_dev, "unable to sub-region functional " 160 "registers, error = %d\n", 161 error); 162 return; 163 } 164 } 165 166 /* 167 * Initialize the transmit threshold for this interface. The 168 * manual describes the default as 4 * 16 bytes. We start out 169 * at 10 * 16 bytes, to avoid a bunch of initial underruns on 170 * several platforms. 171 */ 172 sc->sc_txthresh = 10; 173 174 /* 175 * Allocate the control data structures, and create and load the 176 * DMA map for it. 177 */ 178 if ((error = bus_dmamem_alloc(sc->sc_dmat, 179 sizeof(struct sf_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 180 BUS_DMA_NOWAIT)) != 0) { 181 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 182 error); 183 goto fail_0; 184 } 185 186 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 187 sizeof(struct sf_control_data), (void **)&sc->sc_control_data, 188 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 189 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 190 error); 191 goto fail_1; 192 } 193 194 if ((error = bus_dmamap_create(sc->sc_dmat, 195 sizeof(struct sf_control_data), 1, 196 sizeof(struct sf_control_data), 0, BUS_DMA_NOWAIT, 197 &sc->sc_cddmamap)) != 0) { 198 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 199 "error = %d\n", error); 200 goto fail_2; 201 } 202 203 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 204 sc->sc_control_data, sizeof(struct sf_control_data), NULL, 205 BUS_DMA_NOWAIT)) != 0) { 206 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 207 error); 208 goto fail_3; 209 } 210 211 /* 212 * Create the transmit buffer DMA maps. 213 */ 214 for (i = 0; i < SF_NTXDESC; i++) { 215 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 216 SF_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 217 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 218 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 219 "error = %d\n", i, error); 220 goto fail_4; 221 } 222 } 223 224 /* 225 * Create the receive buffer DMA maps. 226 */ 227 for (i = 0; i < SF_NRXDESC; i++) { 228 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 229 MCLBYTES, 0, BUS_DMA_NOWAIT, 230 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 231 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 232 "error = %d\n", i, error); 233 goto fail_5; 234 } 235 } 236 237 /* 238 * Reset the chip to a known state. 239 */ 240 sf_reset(sc); 241 242 /* 243 * Read the Ethernet address from the EEPROM. 244 */ 245 for (i = 0; i < ETHER_ADDR_LEN; i++) 246 enaddr[i] = sf_read_eeprom(sc, (15 + (ETHER_ADDR_LEN - 1)) - i); 247 248 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 249 ether_sprintf(enaddr)); 250 251 if (sf_funcreg_read(sc, SF_PciDeviceConfig) & PDC_System64) 252 printf("%s: 64-bit PCI slot detected\n", device_xname(&sc->sc_dev)); 253 254 /* 255 * Initialize our media structures and probe the MII. 256 */ 257 sc->sc_mii.mii_ifp = ifp; 258 sc->sc_mii.mii_readreg = sf_mii_read; 259 sc->sc_mii.mii_writereg = sf_mii_write; 260 sc->sc_mii.mii_statchg = sf_mii_statchg; 261 sc->sc_ethercom.ec_mii = &sc->sc_mii; 262 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 263 ether_mediastatus); 264 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 265 MII_OFFSET_ANY, 0); 266 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 267 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 268 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 269 } else 270 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 271 272 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 273 ifp->if_softc = sc; 274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 275 ifp->if_ioctl = sf_ioctl; 276 ifp->if_start = sf_start; 277 ifp->if_watchdog = sf_watchdog; 278 ifp->if_init = sf_init; 279 ifp->if_stop = sf_stop; 280 IFQ_SET_READY(&ifp->if_snd); 281 282 /* 283 * Attach the interface. 284 */ 285 if_attach(ifp); 286 ether_ifattach(ifp, enaddr); 287 288 /* 289 * Make sure the interface is shutdown during reboot. 290 */ 291 if (pmf_device_register1(&sc->sc_dev, NULL, NULL, sf_shutdown)) 292 pmf_class_network_register(&sc->sc_dev, ifp); 293 else 294 aprint_error_dev(&sc->sc_dev, 295 "couldn't establish power handler\n"); 296 return; 297 298 /* 299 * Free any resources we've allocated during the failed attach 300 * attempt. Do this in reverse order an fall through. 301 */ 302 fail_5: 303 for (i = 0; i < SF_NRXDESC; i++) { 304 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 305 bus_dmamap_destroy(sc->sc_dmat, 306 sc->sc_rxsoft[i].ds_dmamap); 307 } 308 fail_4: 309 for (i = 0; i < SF_NTXDESC; i++) { 310 if (sc->sc_txsoft[i].ds_dmamap != NULL) 311 bus_dmamap_destroy(sc->sc_dmat, 312 sc->sc_txsoft[i].ds_dmamap); 313 } 314 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 315 fail_3: 316 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 317 fail_2: 318 bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_control_data, 319 sizeof(struct sf_control_data)); 320 fail_1: 321 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 322 fail_0: 323 return; 324 } 325 326 /* 327 * sf_shutdown: 328 * 329 * Shutdown hook -- make sure the interface is stopped at reboot. 330 */ 331 static bool 332 sf_shutdown(device_t self, int howto) 333 { 334 struct sf_softc *sc; 335 336 sc = device_private(self); 337 sf_stop(&sc->sc_ethercom.ec_if, 1); 338 339 return true; 340 } 341 342 /* 343 * sf_start: [ifnet interface function] 344 * 345 * Start packet transmission on the interface. 346 */ 347 static void 348 sf_start(struct ifnet *ifp) 349 { 350 struct sf_softc *sc = ifp->if_softc; 351 struct mbuf *m0, *m; 352 struct sf_txdesc0 *txd; 353 struct sf_descsoft *ds; 354 bus_dmamap_t dmamap; 355 int error, producer, last = -1, opending, seg; 356 357 /* 358 * Remember the previous number of pending transmits. 359 */ 360 opending = sc->sc_txpending; 361 362 /* 363 * Find out where we're sitting. 364 */ 365 producer = SF_TXDINDEX_TO_HOST( 366 TDQPI_HiPrTxProducerIndex_get( 367 sf_funcreg_read(sc, SF_TxDescQueueProducerIndex))); 368 369 /* 370 * Loop through the send queue, setting up transmit descriptors 371 * until we drain the queue, or use up all available transmit 372 * descriptors. Leave a blank one at the end for sanity's sake. 373 */ 374 while (sc->sc_txpending < (SF_NTXDESC - 1)) { 375 /* 376 * Grab a packet off the queue. 377 */ 378 IFQ_POLL(&ifp->if_snd, m0); 379 if (m0 == NULL) 380 break; 381 m = NULL; 382 383 /* 384 * Get the transmit descriptor. 385 */ 386 txd = &sc->sc_txdescs[producer]; 387 ds = &sc->sc_txsoft[producer]; 388 dmamap = ds->ds_dmamap; 389 390 /* 391 * Load the DMA map. If this fails, the packet either 392 * didn't fit in the allotted number of frags, or we were 393 * short on resources. In this case, we'll copy and try 394 * again. 395 */ 396 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 397 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 398 MGETHDR(m, M_DONTWAIT, MT_DATA); 399 if (m == NULL) { 400 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n"); 401 break; 402 } 403 if (m0->m_pkthdr.len > MHLEN) { 404 MCLGET(m, M_DONTWAIT); 405 if ((m->m_flags & M_EXT) == 0) { 406 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx " 407 "cluster\n"); 408 m_freem(m); 409 break; 410 } 411 } 412 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 413 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 414 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 415 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 416 if (error) { 417 aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, " 418 "error = %d\n", error); 419 break; 420 } 421 } 422 423 /* 424 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 425 */ 426 IFQ_DEQUEUE(&ifp->if_snd, m0); 427 if (m != NULL) { 428 m_freem(m0); 429 m0 = m; 430 } 431 432 /* Initialize the descriptor. */ 433 txd->td_word0 = 434 htole32(TD_W0_ID | TD_W0_CRCEN | m0->m_pkthdr.len); 435 if (producer == (SF_NTXDESC - 1)) 436 txd->td_word0 |= TD_W0_END; 437 txd->td_word1 = htole32(dmamap->dm_nsegs); 438 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 439 txd->td_frags[seg].fr_addr = 440 htole32(dmamap->dm_segs[seg].ds_addr); 441 txd->td_frags[seg].fr_len = 442 htole32(dmamap->dm_segs[seg].ds_len); 443 } 444 445 /* Sync the descriptor and the DMA map. */ 446 SF_CDTXDSYNC(sc, producer, BUS_DMASYNC_PREWRITE); 447 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 448 BUS_DMASYNC_PREWRITE); 449 450 /* 451 * Store a pointer to the packet so we can free it later. 452 */ 453 ds->ds_mbuf = m0; 454 455 /* Advance the Tx pointer. */ 456 sc->sc_txpending++; 457 last = producer; 458 producer = SF_NEXTTX(producer); 459 460 /* 461 * Pass the packet to any BPF listeners. 462 */ 463 bpf_mtap(ifp, m0); 464 } 465 466 if (sc->sc_txpending == (SF_NTXDESC - 1)) { 467 /* No more slots left; notify upper layer. */ 468 ifp->if_flags |= IFF_OACTIVE; 469 } 470 471 if (sc->sc_txpending != opending) { 472 KASSERT(last != -1); 473 /* 474 * We enqueued packets. Cause a transmit interrupt to 475 * happen on the last packet we enqueued, and give the 476 * new descriptors to the chip by writing the new 477 * producer index. 478 */ 479 sc->sc_txdescs[last].td_word0 |= TD_W0_INTR; 480 SF_CDTXDSYNC(sc, last, BUS_DMASYNC_PREWRITE); 481 482 sf_funcreg_write(sc, SF_TxDescQueueProducerIndex, 483 TDQPI_HiPrTxProducerIndex(SF_TXDINDEX_TO_CHIP(producer))); 484 485 /* Set a watchdog timer in case the chip flakes out. */ 486 ifp->if_timer = 5; 487 } 488 } 489 490 /* 491 * sf_watchdog: [ifnet interface function] 492 * 493 * Watchdog timer handler. 494 */ 495 static void 496 sf_watchdog(struct ifnet *ifp) 497 { 498 struct sf_softc *sc = ifp->if_softc; 499 500 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 501 ifp->if_oerrors++; 502 503 (void) sf_init(ifp); 504 505 /* Try to get more packets going. */ 506 sf_start(ifp); 507 } 508 509 /* 510 * sf_ioctl: [ifnet interface function] 511 * 512 * Handle control requests from the operator. 513 */ 514 static int 515 sf_ioctl(struct ifnet *ifp, u_long cmd, void *data) 516 { 517 struct sf_softc *sc = ifp->if_softc; 518 int s, error; 519 520 s = splnet(); 521 522 error = ether_ioctl(ifp, cmd, data); 523 if (error == ENETRESET) { 524 /* 525 * Multicast list has changed; set the hardware filter 526 * accordingly. 527 */ 528 if (ifp->if_flags & IFF_RUNNING) 529 sf_set_filter(sc); 530 error = 0; 531 } 532 533 /* Try to get more packets going. */ 534 sf_start(ifp); 535 536 splx(s); 537 return (error); 538 } 539 540 /* 541 * sf_intr: 542 * 543 * Interrupt service routine. 544 */ 545 int 546 sf_intr(void *arg) 547 { 548 struct sf_softc *sc = arg; 549 uint32_t isr; 550 int handled = 0, wantinit = 0; 551 552 for (;;) { 553 /* Reading clears all interrupts we're interested in. */ 554 isr = sf_funcreg_read(sc, SF_InterruptStatus); 555 if ((isr & IS_PCIPadInt) == 0) 556 break; 557 558 handled = 1; 559 560 /* Handle receive interrupts. */ 561 if (isr & IS_RxQ1DoneInt) 562 sf_rxintr(sc); 563 564 /* Handle transmit completion interrupts. */ 565 if (isr & (IS_TxDmaDoneInt|IS_TxQueueDoneInt)) 566 sf_txintr(sc); 567 568 /* Handle abnormal interrupts. */ 569 if (isr & IS_AbnormalInterrupt) { 570 /* Statistics. */ 571 if (isr & IS_StatisticWrapInt) 572 sf_stats_update(sc); 573 574 /* DMA errors. */ 575 if (isr & IS_DmaErrInt) { 576 wantinit = 1; 577 aprint_error_dev(&sc->sc_dev, "WARNING: DMA error\n"); 578 } 579 580 /* Transmit FIFO underruns. */ 581 if (isr & IS_TxDataLowInt) { 582 if (sc->sc_txthresh < 0xff) 583 sc->sc_txthresh++; 584 printf("%s: transmit FIFO underrun, new " 585 "threshold: %d bytes\n", 586 device_xname(&sc->sc_dev), 587 sc->sc_txthresh * 16); 588 sf_funcreg_write(sc, SF_TransmitFrameCSR, 589 sc->sc_TransmitFrameCSR | 590 TFCSR_TransmitThreshold(sc->sc_txthresh)); 591 sf_funcreg_write(sc, SF_TxDescQueueCtrl, 592 sc->sc_TxDescQueueCtrl | 593 TDQC_TxHighPriorityFifoThreshold( 594 sc->sc_txthresh)); 595 } 596 } 597 } 598 599 if (handled) { 600 /* Reset the interface, if necessary. */ 601 if (wantinit) 602 sf_init(&sc->sc_ethercom.ec_if); 603 604 /* Try and get more packets going. */ 605 sf_start(&sc->sc_ethercom.ec_if); 606 } 607 608 return (handled); 609 } 610 611 /* 612 * sf_txintr: 613 * 614 * Helper -- handle transmit completion interrupts. 615 */ 616 static void 617 sf_txintr(struct sf_softc *sc) 618 { 619 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 620 struct sf_descsoft *ds; 621 uint32_t cqci, tcd; 622 int consumer, producer, txidx; 623 624 try_again: 625 cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex); 626 627 consumer = CQCI_TxCompletionConsumerIndex_get(cqci); 628 producer = CQPI_TxCompletionProducerIndex_get( 629 sf_funcreg_read(sc, SF_CompletionQueueProducerIndex)); 630 631 if (consumer == producer) 632 return; 633 634 ifp->if_flags &= ~IFF_OACTIVE; 635 636 while (consumer != producer) { 637 SF_CDTXCSYNC(sc, consumer, BUS_DMASYNC_POSTREAD); 638 tcd = le32toh(sc->sc_txcomp[consumer].tcd_word0); 639 640 txidx = SF_TCD_INDEX_TO_HOST(TCD_INDEX(tcd)); 641 #ifdef DIAGNOSTIC 642 if ((tcd & TCD_PR) == 0) 643 aprint_error_dev(&sc->sc_dev, "Tx queue mismatch, index %d\n", 644 txidx); 645 #endif 646 /* 647 * NOTE: stats are updated later. We're just 648 * releasing packets that have been DMA'd to 649 * the chip. 650 */ 651 ds = &sc->sc_txsoft[txidx]; 652 SF_CDTXDSYNC(sc, txidx, BUS_DMASYNC_POSTWRITE); 653 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 654 0, ds->ds_dmamap->dm_mapsize, 655 BUS_DMASYNC_POSTWRITE); 656 m_freem(ds->ds_mbuf); 657 ds->ds_mbuf = NULL; 658 659 consumer = SF_NEXTTCD(consumer); 660 sc->sc_txpending--; 661 } 662 663 /* XXXJRT -- should be KDASSERT() */ 664 KASSERT(sc->sc_txpending >= 0); 665 666 /* If all packets are done, cancel the watchdog timer. */ 667 if (sc->sc_txpending == 0) 668 ifp->if_timer = 0; 669 670 /* Update the consumer index. */ 671 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 672 (cqci & ~CQCI_TxCompletionConsumerIndex(0x7ff)) | 673 CQCI_TxCompletionConsumerIndex(consumer)); 674 675 /* Double check for new completions. */ 676 goto try_again; 677 } 678 679 /* 680 * sf_rxintr: 681 * 682 * Helper -- handle receive interrupts. 683 */ 684 static void 685 sf_rxintr(struct sf_softc *sc) 686 { 687 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 688 struct sf_descsoft *ds; 689 struct sf_rcd_full *rcd; 690 struct mbuf *m; 691 uint32_t cqci, word0; 692 int consumer, producer, bufproducer, rxidx, len; 693 694 try_again: 695 cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex); 696 697 consumer = CQCI_RxCompletionQ1ConsumerIndex_get(cqci); 698 producer = CQPI_RxCompletionQ1ProducerIndex_get( 699 sf_funcreg_read(sc, SF_CompletionQueueProducerIndex)); 700 bufproducer = RXQ1P_RxDescQ1Producer_get( 701 sf_funcreg_read(sc, SF_RxDescQueue1Ptrs)); 702 703 if (consumer == producer) 704 return; 705 706 while (consumer != producer) { 707 rcd = &sc->sc_rxcomp[consumer]; 708 SF_CDRXCSYNC(sc, consumer, 709 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 710 SF_CDRXCSYNC(sc, consumer, 711 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 712 713 word0 = le32toh(rcd->rcd_word0); 714 rxidx = RCD_W0_EndIndex(word0); 715 716 ds = &sc->sc_rxsoft[rxidx]; 717 718 consumer = SF_NEXTRCD(consumer); 719 bufproducer = SF_NEXTRX(bufproducer); 720 721 if ((word0 & RCD_W0_OK) == 0) { 722 SF_INIT_RXDESC(sc, rxidx); 723 continue; 724 } 725 726 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 727 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 728 729 /* 730 * No errors; receive the packet. Note that we have 731 * configured the Starfire to NOT transfer the CRC 732 * with the packet. 733 */ 734 len = RCD_W0_Length(word0); 735 736 #ifdef __NO_STRICT_ALIGNMENT 737 /* 738 * Allocate a new mbuf cluster. If that fails, we are 739 * out of memory, and must drop the packet and recycle 740 * the buffer that's already attached to this descriptor. 741 */ 742 m = ds->ds_mbuf; 743 if (sf_add_rxbuf(sc, rxidx) != 0) { 744 ifp->if_ierrors++; 745 SF_INIT_RXDESC(sc, rxidx); 746 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 747 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 748 continue; 749 } 750 #else 751 /* 752 * The Starfire's receive buffer must be 4-byte aligned. 753 * But this means that the data after the Ethernet header 754 * is misaligned. We must allocate a new buffer and 755 * copy the data, shifted forward 2 bytes. 756 */ 757 MGETHDR(m, M_DONTWAIT, MT_DATA); 758 if (m == NULL) { 759 dropit: 760 ifp->if_ierrors++; 761 SF_INIT_RXDESC(sc, rxidx); 762 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 763 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 764 continue; 765 } 766 if (len > (MHLEN - 2)) { 767 MCLGET(m, M_DONTWAIT); 768 if ((m->m_flags & M_EXT) == 0) { 769 m_freem(m); 770 goto dropit; 771 } 772 } 773 m->m_data += 2; 774 775 /* 776 * Note that we use cluster for incoming frames, so the 777 * buffer is virtually contiguous. 778 */ 779 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), len); 780 781 /* Allow the receive descriptor to continue using its mbuf. */ 782 SF_INIT_RXDESC(sc, rxidx); 783 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 784 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 785 #endif /* __NO_STRICT_ALIGNMENT */ 786 787 m->m_pkthdr.rcvif = ifp; 788 m->m_pkthdr.len = m->m_len = len; 789 790 /* 791 * Pass this up to any BPF listeners. 792 */ 793 bpf_mtap(ifp, m); 794 795 /* Pass it on. */ 796 (*ifp->if_input)(ifp, m); 797 } 798 799 /* Update the chip's pointers. */ 800 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 801 (cqci & ~CQCI_RxCompletionQ1ConsumerIndex(0x7ff)) | 802 CQCI_RxCompletionQ1ConsumerIndex(consumer)); 803 sf_funcreg_write(sc, SF_RxDescQueue1Ptrs, 804 RXQ1P_RxDescQ1Producer(bufproducer)); 805 806 /* Double-check for any new completions. */ 807 goto try_again; 808 } 809 810 /* 811 * sf_tick: 812 * 813 * One second timer, used to tick the MII and update stats. 814 */ 815 static void 816 sf_tick(void *arg) 817 { 818 struct sf_softc *sc = arg; 819 int s; 820 821 s = splnet(); 822 mii_tick(&sc->sc_mii); 823 sf_stats_update(sc); 824 splx(s); 825 826 callout_reset(&sc->sc_tick_callout, hz, sf_tick, sc); 827 } 828 829 /* 830 * sf_stats_update: 831 * 832 * Read the statitistics counters. 833 */ 834 static void 835 sf_stats_update(struct sf_softc *sc) 836 { 837 struct sf_stats stats; 838 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 839 uint32_t *p; 840 u_int i; 841 842 p = &stats.TransmitOKFrames; 843 for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) { 844 *p++ = sf_genreg_read(sc, 845 SF_STATS_BASE + (i * sizeof(uint32_t))); 846 sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0); 847 } 848 849 ifp->if_opackets += stats.TransmitOKFrames; 850 851 ifp->if_collisions += stats.SingleCollisionFrames + 852 stats.MultipleCollisionFrames; 853 854 ifp->if_oerrors += stats.TransmitAbortDueToExcessiveCollisions + 855 stats.TransmitAbortDueToExcessingDeferral + 856 stats.FramesLostDueToInternalTransmitErrors; 857 858 ifp->if_ipackets += stats.ReceiveOKFrames; 859 860 ifp->if_ierrors += stats.ReceiveCRCErrors + stats.AlignmentErrors + 861 stats.ReceiveFramesTooLong + stats.ReceiveFramesTooShort + 862 stats.ReceiveFramesJabbersError + 863 stats.FramesLostDueToInternalReceiveErrors; 864 } 865 866 /* 867 * sf_reset: 868 * 869 * Perform a soft reset on the Starfire. 870 */ 871 static void 872 sf_reset(struct sf_softc *sc) 873 { 874 int i; 875 876 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0); 877 878 sf_macreset(sc); 879 880 sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_SoftReset); 881 for (i = 0; i < 1000; i++) { 882 delay(10); 883 if ((sf_funcreg_read(sc, SF_PciDeviceConfig) & 884 PDC_SoftReset) == 0) 885 break; 886 } 887 888 if (i == 1000) { 889 aprint_error_dev(&sc->sc_dev, "reset failed to complete\n"); 890 sf_funcreg_write(sc, SF_PciDeviceConfig, 0); 891 } 892 893 delay(1000); 894 } 895 896 /* 897 * sf_macreset: 898 * 899 * Reset the MAC portion of the Starfire. 900 */ 901 static void 902 sf_macreset(struct sf_softc *sc) 903 { 904 905 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1 | MC1_SoftRst); 906 delay(1000); 907 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1); 908 } 909 910 /* 911 * sf_init: [ifnet interface function] 912 * 913 * Initialize the interface. Must be called at splnet(). 914 */ 915 static int 916 sf_init(struct ifnet *ifp) 917 { 918 struct sf_softc *sc = ifp->if_softc; 919 struct sf_descsoft *ds; 920 int error = 0; 921 u_int i; 922 923 /* 924 * Cancel any pending I/O. 925 */ 926 sf_stop(ifp, 0); 927 928 /* 929 * Reset the Starfire to a known state. 930 */ 931 sf_reset(sc); 932 933 /* Clear the stat counters. */ 934 for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t)) 935 sf_genreg_write(sc, SF_STATS_BASE + i, 0); 936 937 /* 938 * Initialize the transmit descriptor ring. 939 */ 940 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 941 sf_funcreg_write(sc, SF_TxDescQueueHighAddr, 0); 942 sf_funcreg_write(sc, SF_HiPrTxDescQueueBaseAddr, SF_CDTXDADDR(sc, 0)); 943 sf_funcreg_write(sc, SF_LoPrTxDescQueueBaseAddr, 0); 944 945 /* 946 * Initialize the transmit completion ring. 947 */ 948 for (i = 0; i < SF_NTCD; i++) { 949 sc->sc_txcomp[i].tcd_word0 = TCD_DMA_ID; 950 SF_CDTXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 951 } 952 sf_funcreg_write(sc, SF_CompletionQueueHighAddr, 0); 953 sf_funcreg_write(sc, SF_TxCompletionQueueCtrl, SF_CDTXCADDR(sc, 0)); 954 955 /* 956 * Initialize the receive descriptor ring. 957 */ 958 for (i = 0; i < SF_NRXDESC; i++) { 959 ds = &sc->sc_rxsoft[i]; 960 if (ds->ds_mbuf == NULL) { 961 if ((error = sf_add_rxbuf(sc, i)) != 0) { 962 aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx " 963 "buffer %d, error = %d\n", 964 i, error); 965 /* 966 * XXX Should attempt to run with fewer receive 967 * XXX buffers instead of just failing. 968 */ 969 sf_rxdrain(sc); 970 goto out; 971 } 972 } else 973 SF_INIT_RXDESC(sc, i); 974 } 975 sf_funcreg_write(sc, SF_RxDescQueueHighAddress, 0); 976 sf_funcreg_write(sc, SF_RxDescQueue1LowAddress, SF_CDRXDADDR(sc, 0)); 977 sf_funcreg_write(sc, SF_RxDescQueue2LowAddress, 0); 978 979 /* 980 * Initialize the receive completion ring. 981 */ 982 for (i = 0; i < SF_NRCD; i++) { 983 sc->sc_rxcomp[i].rcd_word0 = RCD_W0_ID; 984 sc->sc_rxcomp[i].rcd_word1 = 0; 985 sc->sc_rxcomp[i].rcd_word2 = 0; 986 sc->sc_rxcomp[i].rcd_timestamp = 0; 987 SF_CDRXCSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 988 } 989 sf_funcreg_write(sc, SF_RxCompletionQueue1Ctrl, SF_CDRXCADDR(sc, 0) | 990 RCQ1C_RxCompletionQ1Type(3)); 991 sf_funcreg_write(sc, SF_RxCompletionQueue2Ctrl, 0); 992 993 /* 994 * Initialize the Tx CSR. 995 */ 996 sc->sc_TransmitFrameCSR = 0; 997 sf_funcreg_write(sc, SF_TransmitFrameCSR, 998 sc->sc_TransmitFrameCSR | 999 TFCSR_TransmitThreshold(sc->sc_txthresh)); 1000 1001 /* 1002 * Initialize the Tx descriptor control register. 1003 */ 1004 sc->sc_TxDescQueueCtrl = TDQC_SkipLength(0) | 1005 TDQC_TxDmaBurstSize(4) | /* default */ 1006 TDQC_MinFrameSpacing(3) | /* 128 bytes */ 1007 TDQC_TxDescType(0); 1008 sf_funcreg_write(sc, SF_TxDescQueueCtrl, 1009 sc->sc_TxDescQueueCtrl | 1010 TDQC_TxHighPriorityFifoThreshold(sc->sc_txthresh)); 1011 1012 /* 1013 * Initialize the Rx descriptor control registers. 1014 */ 1015 sf_funcreg_write(sc, SF_RxDescQueue1Ctrl, 1016 RDQ1C_RxQ1BufferLength(MCLBYTES) | 1017 RDQ1C_RxDescSpacing(0)); 1018 sf_funcreg_write(sc, SF_RxDescQueue2Ctrl, 0); 1019 1020 /* 1021 * Initialize the Tx descriptor producer indices. 1022 */ 1023 sf_funcreg_write(sc, SF_TxDescQueueProducerIndex, 1024 TDQPI_HiPrTxProducerIndex(0) | 1025 TDQPI_LoPrTxProducerIndex(0)); 1026 1027 /* 1028 * Initialize the Rx descriptor producer indices. 1029 */ 1030 sf_funcreg_write(sc, SF_RxDescQueue1Ptrs, 1031 RXQ1P_RxDescQ1Producer(SF_NRXDESC - 1)); 1032 sf_funcreg_write(sc, SF_RxDescQueue2Ptrs, 1033 RXQ2P_RxDescQ2Producer(0)); 1034 1035 /* 1036 * Initialize the Tx and Rx completion queue consumer indices. 1037 */ 1038 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 1039 CQCI_TxCompletionConsumerIndex(0) | 1040 CQCI_RxCompletionQ1ConsumerIndex(0)); 1041 sf_funcreg_write(sc, SF_RxHiPrCompletionPtrs, 0); 1042 1043 /* 1044 * Initialize the Rx DMA control register. 1045 */ 1046 sf_funcreg_write(sc, SF_RxDmaCtrl, 1047 RDC_RxHighPriorityThreshold(6) | /* default */ 1048 RDC_RxBurstSize(4)); /* default */ 1049 1050 /* 1051 * Set the receive filter. 1052 */ 1053 sc->sc_RxAddressFilteringCtl = 0; 1054 sf_set_filter(sc); 1055 1056 /* 1057 * Set MacConfig1. When we set the media, MacConfig1 will 1058 * actually be written and the MAC part reset. 1059 */ 1060 sc->sc_MacConfig1 = MC1_PadEn; 1061 1062 /* 1063 * Set the media. 1064 */ 1065 if ((error = ether_mediachange(ifp)) != 0) 1066 goto out; 1067 1068 /* 1069 * Initialize the interrupt register. 1070 */ 1071 sc->sc_InterruptEn = IS_PCIPadInt | IS_RxQ1DoneInt | 1072 IS_TxQueueDoneInt | IS_TxDmaDoneInt | IS_DmaErrInt | 1073 IS_StatisticWrapInt; 1074 sf_funcreg_write(sc, SF_InterruptEn, sc->sc_InterruptEn); 1075 1076 sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_IntEnable | 1077 PDC_PCIMstDmaEn | (1 << PDC_FifoThreshold_SHIFT)); 1078 1079 /* 1080 * Start the transmit and receive processes. 1081 */ 1082 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 1083 GEC_TxDmaEn|GEC_RxDmaEn|GEC_TransmitEn|GEC_ReceiveEn); 1084 1085 /* Start the on second clock. */ 1086 callout_reset(&sc->sc_tick_callout, hz, sf_tick, sc); 1087 1088 /* 1089 * Note that the interface is now running. 1090 */ 1091 ifp->if_flags |= IFF_RUNNING; 1092 ifp->if_flags &= ~IFF_OACTIVE; 1093 1094 out: 1095 if (error) { 1096 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1097 ifp->if_timer = 0; 1098 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 1099 } 1100 return (error); 1101 } 1102 1103 /* 1104 * sf_rxdrain: 1105 * 1106 * Drain the receive queue. 1107 */ 1108 static void 1109 sf_rxdrain(struct sf_softc *sc) 1110 { 1111 struct sf_descsoft *ds; 1112 int i; 1113 1114 for (i = 0; i < SF_NRXDESC; i++) { 1115 ds = &sc->sc_rxsoft[i]; 1116 if (ds->ds_mbuf != NULL) { 1117 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1118 m_freem(ds->ds_mbuf); 1119 ds->ds_mbuf = NULL; 1120 } 1121 } 1122 } 1123 1124 /* 1125 * sf_stop: [ifnet interface function] 1126 * 1127 * Stop transmission on the interface. 1128 */ 1129 static void 1130 sf_stop(struct ifnet *ifp, int disable) 1131 { 1132 struct sf_softc *sc = ifp->if_softc; 1133 struct sf_descsoft *ds; 1134 int i; 1135 1136 /* Stop the one second clock. */ 1137 callout_stop(&sc->sc_tick_callout); 1138 1139 /* Down the MII. */ 1140 mii_down(&sc->sc_mii); 1141 1142 /* Disable interrupts. */ 1143 sf_funcreg_write(sc, SF_InterruptEn, 0); 1144 1145 /* Stop the transmit and receive processes. */ 1146 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0); 1147 1148 /* 1149 * Release any queued transmit buffers. 1150 */ 1151 for (i = 0; i < SF_NTXDESC; i++) { 1152 ds = &sc->sc_txsoft[i]; 1153 if (ds->ds_mbuf != NULL) { 1154 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1155 m_freem(ds->ds_mbuf); 1156 ds->ds_mbuf = NULL; 1157 } 1158 } 1159 1160 /* 1161 * Mark the interface down and cancel the watchdog timer. 1162 */ 1163 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1164 ifp->if_timer = 0; 1165 1166 if (disable) 1167 sf_rxdrain(sc); 1168 } 1169 1170 /* 1171 * sf_read_eeprom: 1172 * 1173 * Read from the Starfire EEPROM. 1174 */ 1175 static uint8_t 1176 sf_read_eeprom(struct sf_softc *sc, int offset) 1177 { 1178 uint32_t reg; 1179 1180 reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3)); 1181 1182 return ((reg >> (8 * (offset & 3))) & 0xff); 1183 } 1184 1185 /* 1186 * sf_add_rxbuf: 1187 * 1188 * Add a receive buffer to the indicated descriptor. 1189 */ 1190 static int 1191 sf_add_rxbuf(struct sf_softc *sc, int idx) 1192 { 1193 struct sf_descsoft *ds = &sc->sc_rxsoft[idx]; 1194 struct mbuf *m; 1195 int error; 1196 1197 MGETHDR(m, M_DONTWAIT, MT_DATA); 1198 if (m == NULL) 1199 return (ENOBUFS); 1200 1201 MCLGET(m, M_DONTWAIT); 1202 if ((m->m_flags & M_EXT) == 0) { 1203 m_freem(m); 1204 return (ENOBUFS); 1205 } 1206 1207 if (ds->ds_mbuf != NULL) 1208 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1209 1210 ds->ds_mbuf = m; 1211 1212 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1213 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1214 BUS_DMA_READ|BUS_DMA_NOWAIT); 1215 if (error) { 1216 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 1217 idx, error); 1218 panic("sf_add_rxbuf"); /* XXX */ 1219 } 1220 1221 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1222 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1223 1224 SF_INIT_RXDESC(sc, idx); 1225 1226 return (0); 1227 } 1228 1229 static void 1230 sf_set_filter_perfect(struct sf_softc *sc, int slot, const uint8_t *enaddr) 1231 { 1232 uint32_t reg0, reg1, reg2; 1233 1234 reg0 = enaddr[5] | (enaddr[4] << 8); 1235 reg1 = enaddr[3] | (enaddr[2] << 8); 1236 reg2 = enaddr[1] | (enaddr[0] << 8); 1237 1238 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0); 1239 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1); 1240 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2); 1241 } 1242 1243 static void 1244 sf_set_filter_hash(struct sf_softc *sc, uint8_t *enaddr) 1245 { 1246 uint32_t hash, slot, reg; 1247 1248 hash = ether_crc32_be(enaddr, ETHER_ADDR_LEN) >> 23; 1249 slot = hash >> 4; 1250 1251 reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10)); 1252 reg |= 1 << (hash & 0xf); 1253 sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg); 1254 } 1255 1256 /* 1257 * sf_set_filter: 1258 * 1259 * Set the Starfire receive filter. 1260 */ 1261 static void 1262 sf_set_filter(struct sf_softc *sc) 1263 { 1264 struct ethercom *ec = &sc->sc_ethercom; 1265 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1266 struct ether_multi *enm; 1267 struct ether_multistep step; 1268 int i; 1269 1270 /* Start by clearing the perfect and hash tables. */ 1271 for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t)) 1272 sf_genreg_write(sc, SF_PERFECT_BASE + i, 0); 1273 1274 for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t)) 1275 sf_genreg_write(sc, SF_HASH_BASE + i, 0); 1276 1277 /* 1278 * Clear the perfect and hash mode bits. 1279 */ 1280 sc->sc_RxAddressFilteringCtl &= 1281 ~(RAFC_PerfectFilteringMode(3) | RAFC_HashFilteringMode(3)); 1282 1283 if (ifp->if_flags & IFF_BROADCAST) 1284 sc->sc_RxAddressFilteringCtl |= RAFC_PassBroadcast; 1285 else 1286 sc->sc_RxAddressFilteringCtl &= ~RAFC_PassBroadcast; 1287 1288 if (ifp->if_flags & IFF_PROMISC) { 1289 sc->sc_RxAddressFilteringCtl |= RAFC_PromiscuousMode; 1290 goto allmulti; 1291 } else 1292 sc->sc_RxAddressFilteringCtl &= ~RAFC_PromiscuousMode; 1293 1294 /* 1295 * Set normal perfect filtering mode. 1296 */ 1297 sc->sc_RxAddressFilteringCtl |= RAFC_PerfectFilteringMode(1); 1298 1299 /* 1300 * First, write the station address to the perfect filter 1301 * table. 1302 */ 1303 sf_set_filter_perfect(sc, 0, CLLADDR(ifp->if_sadl)); 1304 1305 /* 1306 * Now set the hash bits for each multicast address in our 1307 * list. 1308 */ 1309 ETHER_FIRST_MULTI(step, ec, enm); 1310 if (enm == NULL) 1311 goto done; 1312 while (enm != NULL) { 1313 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1314 /* 1315 * We must listen to a range of multicast addresses. 1316 * For now, just accept all multicasts, rather than 1317 * trying to set only those filter bits needed to match 1318 * the range. (At this time, the only use of address 1319 * ranges is for IP multicast routing, for which the 1320 * range is big enough to require all bits set.) 1321 */ 1322 goto allmulti; 1323 } 1324 sf_set_filter_hash(sc, enm->enm_addrlo); 1325 ETHER_NEXT_MULTI(step, enm); 1326 } 1327 1328 /* 1329 * Set "hash only multicast dest, match regardless of VLAN ID". 1330 */ 1331 sc->sc_RxAddressFilteringCtl |= RAFC_HashFilteringMode(2); 1332 goto done; 1333 1334 allmulti: 1335 /* 1336 * XXX RAFC_PassMulticast is sub-optimal if using VLAN mode. 1337 */ 1338 sc->sc_RxAddressFilteringCtl |= RAFC_PassMulticast; 1339 ifp->if_flags |= IFF_ALLMULTI; 1340 1341 done: 1342 sf_funcreg_write(sc, SF_RxAddressFilteringCtl, 1343 sc->sc_RxAddressFilteringCtl); 1344 } 1345 1346 /* 1347 * sf_mii_read: [mii interface function] 1348 * 1349 * Read from the MII. 1350 */ 1351 static int 1352 sf_mii_read(device_t self, int phy, int reg) 1353 { 1354 struct sf_softc *sc = (void *) self; 1355 uint32_t v; 1356 int i; 1357 1358 for (i = 0; i < 1000; i++) { 1359 v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)); 1360 if (v & MiiDataValid) 1361 break; 1362 delay(1); 1363 } 1364 1365 if ((v & MiiDataValid) == 0) 1366 return (0); 1367 1368 if (MiiRegDataPort(v) == 0xffff) 1369 return (0); 1370 1371 return (MiiRegDataPort(v)); 1372 } 1373 1374 /* 1375 * sf_mii_write: [mii interface function] 1376 * 1377 * Write to the MII. 1378 */ 1379 static void 1380 sf_mii_write(device_t self, int phy, int reg, int val) 1381 { 1382 struct sf_softc *sc = (void *) self; 1383 int i; 1384 1385 sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val); 1386 1387 for (i = 0; i < 1000; i++) { 1388 if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) & 1389 MiiBusy) == 0) 1390 return; 1391 delay(1); 1392 } 1393 1394 printf("%s: MII write timed out\n", device_xname(&sc->sc_dev)); 1395 } 1396 1397 /* 1398 * sf_mii_statchg: [mii interface function] 1399 * 1400 * Callback from the PHY when the media changes. 1401 */ 1402 static void 1403 sf_mii_statchg(device_t self) 1404 { 1405 struct sf_softc *sc = (void *) self; 1406 uint32_t ipg; 1407 1408 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1409 sc->sc_MacConfig1 |= MC1_FullDuplex; 1410 ipg = 0x15; 1411 } else { 1412 sc->sc_MacConfig1 &= ~MC1_FullDuplex; 1413 ipg = 0x11; 1414 } 1415 1416 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1); 1417 sf_macreset(sc); 1418 1419 sf_genreg_write(sc, SF_BkToBkIPG, ipg); 1420 } 1421
Indexes created Mon Sep 29 18:09:42 GMT 2025