aic6915.c revision 1.42
1 /* $NetBSD: aic6915.c,v 1.42 2020/02/07 00:56:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Adaptec AIC-6915 (``Starfire'') 34 * 10/100 Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aic6915.c,v 1.42 2020/02/07 00:56:48 thorpej Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <dev/mii/miivar.h> 63 64 #include <dev/ic/aic6915reg.h> 65 #include <dev/ic/aic6915var.h> 66 67 static void sf_start(struct ifnet *); 68 static void sf_watchdog(struct ifnet *); 69 static int sf_ioctl(struct ifnet *, u_long, void *); 70 static int sf_init(struct ifnet *); 71 static void sf_stop(struct ifnet *, int); 72 73 static bool sf_shutdown(device_t, int); 74 75 static void sf_txintr(struct sf_softc *); 76 static void sf_rxintr(struct sf_softc *); 77 static void sf_stats_update(struct sf_softc *); 78 79 static void sf_reset(struct sf_softc *); 80 static void sf_macreset(struct sf_softc *); 81 static void sf_rxdrain(struct sf_softc *); 82 static int sf_add_rxbuf(struct sf_softc *, int); 83 static uint8_t sf_read_eeprom(struct sf_softc *, int); 84 static void sf_set_filter(struct sf_softc *); 85 86 static int sf_mii_read(device_t, int, int, uint16_t *); 87 static int sf_mii_write(device_t, int, int, uint16_t); 88 static void sf_mii_statchg(struct ifnet *); 89 90 static void sf_tick(void *); 91 92 #define sf_funcreg_read(sc, reg) \ 93 bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg)) 94 #define sf_funcreg_write(sc, reg, val) \ 95 bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val)) 96 97 static inline uint32_t 98 sf_reg_read(struct sf_softc *sc, bus_addr_t reg) 99 { 100 101 if (__predict_false(sc->sc_iomapped)) { 102 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess, 103 reg); 104 return (bus_space_read_4(sc->sc_st, sc->sc_sh, 105 SF_IndirectIoDataPort)); 106 } 107 108 return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg)); 109 } 110 111 static inline void 112 sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val) 113 { 114 115 if (__predict_false(sc->sc_iomapped)) { 116 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoAccess, 117 reg); 118 bus_space_write_4(sc->sc_st, sc->sc_sh, SF_IndirectIoDataPort, 119 val); 120 return; 121 } 122 123 bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val); 124 } 125 126 #define sf_genreg_read(sc, reg) \ 127 sf_reg_read((sc), (reg) + SF_GENREG_OFFSET) 128 #define sf_genreg_write(sc, reg, val) \ 129 sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val)) 130 131 /* 132 * sf_attach: 133 * 134 * Attach a Starfire interface to the system. 135 */ 136 void 137 sf_attach(struct sf_softc *sc) 138 { 139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 140 struct mii_data * const mii = &sc->sc_mii; 141 int i, rseg, error; 142 bus_dma_segment_t seg; 143 uint8_t enaddr[ETHER_ADDR_LEN]; 144 145 callout_init(&sc->sc_tick_callout, 0); 146 callout_setfunc(&sc->sc_tick_callout, sf_tick, sc); 147 148 /* 149 * If we're I/O mapped, the functional register handle is 150 * the same as the base handle. If we're memory mapped, 151 * carve off a chunk of the register space for the functional 152 * registers, to save on arithmetic later. 153 */ 154 if (sc->sc_iomapped) 155 sc->sc_sh_func = sc->sc_sh; 156 else { 157 if ((error = bus_space_subregion(sc->sc_st, sc->sc_sh, 158 SF_GENREG_OFFSET, SF_FUNCREG_SIZE, &sc->sc_sh_func)) != 0) { 159 aprint_error_dev(sc->sc_dev, "unable to sub-region " 160 "functional registers, error = %d\n", error); 161 return; 162 } 163 } 164 165 /* 166 * Initialize the transmit threshold for this interface. The 167 * manual describes the default as 4 * 16 bytes. We start out 168 * at 10 * 16 bytes, to avoid a bunch of initial underruns on 169 * several platforms. 170 */ 171 sc->sc_txthresh = 10; 172 173 /* 174 * Allocate the control data structures, and create and load the 175 * DMA map for it. 176 */ 177 if ((error = bus_dmamem_alloc(sc->sc_dmat, 178 sizeof(struct sf_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 179 BUS_DMA_NOWAIT)) != 0) { 180 aprint_error_dev(sc->sc_dev, 181 "unable to allocate control data, error = %d\n", error); 182 goto fail_0; 183 } 184 185 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 186 sizeof(struct sf_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 188 aprint_error_dev(sc->sc_dev, 189 "unable to map control data, error = %d\n", error); 190 goto fail_1; 191 } 192 193 if ((error = bus_dmamap_create(sc->sc_dmat, 194 sizeof(struct sf_control_data), 1, 195 sizeof(struct sf_control_data), 0, BUS_DMA_NOWAIT, 196 &sc->sc_cddmamap)) != 0) { 197 aprint_error_dev(sc->sc_dev, "unable to create control data " 198 "DMA map, error = %d\n", error); 199 goto fail_2; 200 } 201 202 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 203 sc->sc_control_data, sizeof(struct sf_control_data), NULL, 204 BUS_DMA_NOWAIT)) != 0) { 205 aprint_error_dev(sc->sc_dev, "unable to load control data " 206 "DMA map, error = %d\n", error); 207 goto fail_3; 208 } 209 210 /* 211 * Create the transmit buffer DMA maps. 212 */ 213 for (i = 0; i < SF_NTXDESC; i++) { 214 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 215 SF_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 216 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 217 aprint_error_dev(sc->sc_dev, 218 "unable to create tx DMA map %d, error = %d\n", i, 219 error); 220 goto fail_4; 221 } 222 } 223 224 /* 225 * Create the receive buffer DMA maps. 226 */ 227 for (i = 0; i < SF_NRXDESC; i++) { 228 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 229 MCLBYTES, 0, BUS_DMA_NOWAIT, 230 &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 231 aprint_error_dev(sc->sc_dev, 232 "unable to create rx DMA map %d, error = %d\n", i, 233 error); 234 goto fail_5; 235 } 236 } 237 238 /* 239 * Reset the chip to a known state. 240 */ 241 sf_reset(sc); 242 243 /* 244 * Read the Ethernet address from the EEPROM. 245 */ 246 for (i = 0; i < ETHER_ADDR_LEN; i++) 247 enaddr[i] = sf_read_eeprom(sc, (15 + (ETHER_ADDR_LEN - 1)) - i); 248 249 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 250 ether_sprintf(enaddr)); 251 252 if (sf_funcreg_read(sc, SF_PciDeviceConfig) & PDC_System64) 253 printf("%s: 64-bit PCI slot detected\n", 254 device_xname(sc->sc_dev)); 255 256 /* 257 * Initialize our media structures and probe the MII. 258 */ 259 mii->mii_ifp = ifp; 260 mii->mii_readreg = sf_mii_read; 261 mii->mii_writereg = sf_mii_write; 262 mii->mii_statchg = sf_mii_statchg; 263 sc->sc_ethercom.ec_mii = mii; 264 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 265 ether_mediastatus); 266 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 267 MII_OFFSET_ANY, 0); 268 if (LIST_FIRST(&mii->mii_phys) == NULL) { 269 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 270 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 271 } else 272 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 273 274 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 275 ifp->if_softc = sc; 276 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 277 ifp->if_ioctl = sf_ioctl; 278 ifp->if_start = sf_start; 279 ifp->if_watchdog = sf_watchdog; 280 ifp->if_init = sf_init; 281 ifp->if_stop = sf_stop; 282 IFQ_SET_READY(&ifp->if_snd); 283 284 /* 285 * Attach the interface. 286 */ 287 if_attach(ifp); 288 if_deferred_start_init(ifp, NULL); 289 ether_ifattach(ifp, enaddr); 290 291 /* 292 * Make sure the interface is shutdown during reboot. 293 */ 294 if (pmf_device_register1(sc->sc_dev, NULL, NULL, sf_shutdown)) 295 pmf_class_network_register(sc->sc_dev, ifp); 296 else 297 aprint_error_dev(sc->sc_dev, 298 "couldn't establish power handler\n"); 299 return; 300 301 /* 302 * Free any resources we've allocated during the failed attach 303 * attempt. Do this in reverse order an fall through. 304 */ 305 fail_5: 306 for (i = 0; i < SF_NRXDESC; i++) { 307 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 308 bus_dmamap_destroy(sc->sc_dmat, 309 sc->sc_rxsoft[i].ds_dmamap); 310 } 311 fail_4: 312 for (i = 0; i < SF_NTXDESC; i++) { 313 if (sc->sc_txsoft[i].ds_dmamap != NULL) 314 bus_dmamap_destroy(sc->sc_dmat, 315 sc->sc_txsoft[i].ds_dmamap); 316 } 317 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 318 fail_3: 319 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 320 fail_2: 321 bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_control_data, 322 sizeof(struct sf_control_data)); 323 fail_1: 324 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 325 fail_0: 326 return; 327 } 328 329 /* 330 * sf_shutdown: 331 * 332 * Shutdown hook -- make sure the interface is stopped at reboot. 333 */ 334 static bool 335 sf_shutdown(device_t self, int howto) 336 { 337 struct sf_softc *sc; 338 339 sc = device_private(self); 340 sf_stop(&sc->sc_ethercom.ec_if, 1); 341 342 return true; 343 } 344 345 /* 346 * sf_start: [ifnet interface function] 347 * 348 * Start packet transmission on the interface. 349 */ 350 static void 351 sf_start(struct ifnet *ifp) 352 { 353 struct sf_softc *sc = ifp->if_softc; 354 struct mbuf *m0, *m; 355 struct sf_txdesc0 *txd; 356 struct sf_descsoft *ds; 357 bus_dmamap_t dmamap; 358 int error, producer, last = -1, opending, seg; 359 360 /* 361 * Remember the previous number of pending transmits. 362 */ 363 opending = sc->sc_txpending; 364 365 /* 366 * Find out where we're sitting. 367 */ 368 producer = SF_TXDINDEX_TO_HOST( 369 TDQPI_HiPrTxProducerIndex_get( 370 sf_funcreg_read(sc, SF_TxDescQueueProducerIndex))); 371 372 /* 373 * Loop through the send queue, setting up transmit descriptors 374 * until we drain the queue, or use up all available transmit 375 * descriptors. Leave a blank one at the end for sanity's sake. 376 */ 377 while (sc->sc_txpending < (SF_NTXDESC - 1)) { 378 /* 379 * Grab a packet off the queue. 380 */ 381 IFQ_POLL(&ifp->if_snd, m0); 382 if (m0 == NULL) 383 break; 384 m = NULL; 385 386 /* 387 * Get the transmit descriptor. 388 */ 389 txd = &sc->sc_txdescs[producer]; 390 ds = &sc->sc_txsoft[producer]; 391 dmamap = ds->ds_dmamap; 392 393 /* 394 * Load the DMA map. If this fails, the packet either 395 * didn't fit in the allotted number of frags, or we were 396 * short on resources. In this case, we'll copy and try 397 * again. 398 */ 399 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 400 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 401 MGETHDR(m, M_DONTWAIT, MT_DATA); 402 if (m == NULL) { 403 aprint_error_dev(sc->sc_dev, 404 "unable to allocate Tx mbuf\n"); 405 break; 406 } 407 if (m0->m_pkthdr.len > MHLEN) { 408 MCLGET(m, M_DONTWAIT); 409 if ((m->m_flags & M_EXT) == 0) { 410 aprint_error_dev(sc->sc_dev, 411 "unable to allocate Tx cluster\n"); 412 m_freem(m); 413 break; 414 } 415 } 416 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 417 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 418 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 419 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 420 if (error) { 421 aprint_error_dev(sc->sc_dev, 422 "unable to load Tx buffer, error = %d\n", 423 error); 424 break; 425 } 426 } 427 428 /* 429 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 430 */ 431 IFQ_DEQUEUE(&ifp->if_snd, m0); 432 if (m != NULL) { 433 m_freem(m0); 434 m0 = m; 435 } 436 437 /* Initialize the descriptor. */ 438 txd->td_word0 = 439 htole32(TD_W0_ID | TD_W0_CRCEN | m0->m_pkthdr.len); 440 if (producer == (SF_NTXDESC - 1)) 441 txd->td_word0 |= TD_W0_END; 442 txd->td_word1 = htole32(dmamap->dm_nsegs); 443 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 444 txd->td_frags[seg].fr_addr = 445 htole32(dmamap->dm_segs[seg].ds_addr); 446 txd->td_frags[seg].fr_len = 447 htole32(dmamap->dm_segs[seg].ds_len); 448 } 449 450 /* Sync the descriptor and the DMA map. */ 451 SF_CDTXDSYNC(sc, producer, BUS_DMASYNC_PREWRITE); 452 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 453 BUS_DMASYNC_PREWRITE); 454 455 /* 456 * Store a pointer to the packet so we can free it later. 457 */ 458 ds->ds_mbuf = m0; 459 460 /* Advance the Tx pointer. */ 461 sc->sc_txpending++; 462 last = producer; 463 producer = SF_NEXTTX(producer); 464 465 /* 466 * Pass the packet to any BPF listeners. 467 */ 468 bpf_mtap(ifp, m0, BPF_D_OUT); 469 } 470 471 if (sc->sc_txpending == (SF_NTXDESC - 1)) { 472 /* No more slots left; notify upper layer. */ 473 ifp->if_flags |= IFF_OACTIVE; 474 } 475 476 if (sc->sc_txpending != opending) { 477 KASSERT(last != -1); 478 /* 479 * We enqueued packets. Cause a transmit interrupt to 480 * happen on the last packet we enqueued, and give the 481 * new descriptors to the chip by writing the new 482 * producer index. 483 */ 484 sc->sc_txdescs[last].td_word0 |= TD_W0_INTR; 485 SF_CDTXDSYNC(sc, last, BUS_DMASYNC_PREWRITE); 486 487 sf_funcreg_write(sc, SF_TxDescQueueProducerIndex, 488 TDQPI_HiPrTxProducerIndex(SF_TXDINDEX_TO_CHIP(producer))); 489 490 /* Set a watchdog timer in case the chip flakes out. */ 491 ifp->if_timer = 5; 492 } 493 } 494 495 /* 496 * sf_watchdog: [ifnet interface function] 497 * 498 * Watchdog timer handler. 499 */ 500 static void 501 sf_watchdog(struct ifnet *ifp) 502 { 503 struct sf_softc *sc = ifp->if_softc; 504 505 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 506 if_statinc(ifp, if_oerrors); 507 508 (void) sf_init(ifp); 509 510 /* Try to get more packets going. */ 511 sf_start(ifp); 512 } 513 514 /* 515 * sf_ioctl: [ifnet interface function] 516 * 517 * Handle control requests from the operator. 518 */ 519 static int 520 sf_ioctl(struct ifnet *ifp, u_long cmd, void *data) 521 { 522 struct sf_softc *sc = ifp->if_softc; 523 int s, error; 524 525 s = splnet(); 526 527 error = ether_ioctl(ifp, cmd, data); 528 if (error == ENETRESET) { 529 /* 530 * Multicast list has changed; set the hardware filter 531 * accordingly. 532 */ 533 if (ifp->if_flags & IFF_RUNNING) 534 sf_set_filter(sc); 535 error = 0; 536 } 537 538 /* Try to get more packets going. */ 539 sf_start(ifp); 540 541 splx(s); 542 return (error); 543 } 544 545 /* 546 * sf_intr: 547 * 548 * Interrupt service routine. 549 */ 550 int 551 sf_intr(void *arg) 552 { 553 struct sf_softc *sc = arg; 554 uint32_t isr; 555 int handled = 0, wantinit = 0; 556 557 for (;;) { 558 /* Reading clears all interrupts we're interested in. */ 559 isr = sf_funcreg_read(sc, SF_InterruptStatus); 560 if ((isr & IS_PCIPadInt) == 0) 561 break; 562 563 handled = 1; 564 565 /* Handle receive interrupts. */ 566 if (isr & IS_RxQ1DoneInt) 567 sf_rxintr(sc); 568 569 /* Handle transmit completion interrupts. */ 570 if (isr & (IS_TxDmaDoneInt | IS_TxQueueDoneInt)) 571 sf_txintr(sc); 572 573 /* Handle abnormal interrupts. */ 574 if (isr & IS_AbnormalInterrupt) { 575 /* Statistics. */ 576 if (isr & IS_StatisticWrapInt) 577 sf_stats_update(sc); 578 579 /* DMA errors. */ 580 if (isr & IS_DmaErrInt) { 581 wantinit = 1; 582 aprint_error_dev(sc->sc_dev, 583 "WARNING: DMA error\n"); 584 } 585 586 /* Transmit FIFO underruns. */ 587 if (isr & IS_TxDataLowInt) { 588 if (sc->sc_txthresh < 0xff) 589 sc->sc_txthresh++; 590 printf("%s: transmit FIFO underrun, new " 591 "threshold: %d bytes\n", 592 device_xname(sc->sc_dev), 593 sc->sc_txthresh * 16); 594 sf_funcreg_write(sc, SF_TransmitFrameCSR, 595 sc->sc_TransmitFrameCSR | 596 TFCSR_TransmitThreshold(sc->sc_txthresh)); 597 sf_funcreg_write(sc, SF_TxDescQueueCtrl, 598 sc->sc_TxDescQueueCtrl | 599 TDQC_TxHighPriorityFifoThreshold( 600 sc->sc_txthresh)); 601 } 602 } 603 } 604 605 if (handled) { 606 /* Reset the interface, if necessary. */ 607 if (wantinit) 608 sf_init(&sc->sc_ethercom.ec_if); 609 610 /* Try and get more packets going. */ 611 if_schedule_deferred_start(&sc->sc_ethercom.ec_if); 612 } 613 614 return (handled); 615 } 616 617 /* 618 * sf_txintr: 619 * 620 * Helper -- handle transmit completion interrupts. 621 */ 622 static void 623 sf_txintr(struct sf_softc *sc) 624 { 625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 626 struct sf_descsoft *ds; 627 uint32_t cqci, tcd; 628 int consumer, producer, txidx; 629 630 try_again: 631 cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex); 632 633 consumer = CQCI_TxCompletionConsumerIndex_get(cqci); 634 producer = CQPI_TxCompletionProducerIndex_get( 635 sf_funcreg_read(sc, SF_CompletionQueueProducerIndex)); 636 637 if (consumer == producer) 638 return; 639 640 ifp->if_flags &= ~IFF_OACTIVE; 641 642 while (consumer != producer) { 643 SF_CDTXCSYNC(sc, consumer, BUS_DMASYNC_POSTREAD); 644 tcd = le32toh(sc->sc_txcomp[consumer].tcd_word0); 645 646 txidx = SF_TCD_INDEX_TO_HOST(TCD_INDEX(tcd)); 647 #ifdef DIAGNOSTIC 648 if ((tcd & TCD_PR) == 0) 649 aprint_error_dev(sc->sc_dev, 650 "Tx queue mismatch, index %d\n", txidx); 651 #endif 652 /* 653 * NOTE: stats are updated later. We're just 654 * releasing packets that have been DMA'd to 655 * the chip. 656 */ 657 ds = &sc->sc_txsoft[txidx]; 658 SF_CDTXDSYNC(sc, txidx, BUS_DMASYNC_POSTWRITE); 659 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 660 0, ds->ds_dmamap->dm_mapsize, 661 BUS_DMASYNC_POSTWRITE); 662 m_freem(ds->ds_mbuf); 663 ds->ds_mbuf = NULL; 664 665 consumer = SF_NEXTTCD(consumer); 666 sc->sc_txpending--; 667 } 668 669 /* XXXJRT -- should be KDASSERT() */ 670 KASSERT(sc->sc_txpending >= 0); 671 672 /* If all packets are done, cancel the watchdog timer. */ 673 if (sc->sc_txpending == 0) 674 ifp->if_timer = 0; 675 676 /* Update the consumer index. */ 677 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 678 (cqci & ~CQCI_TxCompletionConsumerIndex(0x7ff)) | 679 CQCI_TxCompletionConsumerIndex(consumer)); 680 681 /* Double check for new completions. */ 682 goto try_again; 683 } 684 685 /* 686 * sf_rxintr: 687 * 688 * Helper -- handle receive interrupts. 689 */ 690 static void 691 sf_rxintr(struct sf_softc *sc) 692 { 693 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 694 struct sf_descsoft *ds; 695 struct sf_rcd_full *rcd; 696 struct mbuf *m; 697 uint32_t cqci, word0; 698 int consumer, producer, bufproducer, rxidx, len; 699 700 try_again: 701 cqci = sf_funcreg_read(sc, SF_CompletionQueueConsumerIndex); 702 703 consumer = CQCI_RxCompletionQ1ConsumerIndex_get(cqci); 704 producer = CQPI_RxCompletionQ1ProducerIndex_get( 705 sf_funcreg_read(sc, SF_CompletionQueueProducerIndex)); 706 bufproducer = RXQ1P_RxDescQ1Producer_get( 707 sf_funcreg_read(sc, SF_RxDescQueue1Ptrs)); 708 709 if (consumer == producer) 710 return; 711 712 while (consumer != producer) { 713 rcd = &sc->sc_rxcomp[consumer]; 714 SF_CDRXCSYNC(sc, consumer, 715 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 716 SF_CDRXCSYNC(sc, consumer, 717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 718 719 word0 = le32toh(rcd->rcd_word0); 720 rxidx = RCD_W0_EndIndex(word0); 721 722 ds = &sc->sc_rxsoft[rxidx]; 723 724 consumer = SF_NEXTRCD(consumer); 725 bufproducer = SF_NEXTRX(bufproducer); 726 727 if ((word0 & RCD_W0_OK) == 0) { 728 SF_INIT_RXDESC(sc, rxidx); 729 continue; 730 } 731 732 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 733 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 734 735 /* 736 * No errors; receive the packet. Note that we have 737 * configured the Starfire to NOT transfer the CRC 738 * with the packet. 739 */ 740 len = RCD_W0_Length(word0); 741 742 #ifdef __NO_STRICT_ALIGNMENT 743 /* 744 * Allocate a new mbuf cluster. If that fails, we are 745 * out of memory, and must drop the packet and recycle 746 * the buffer that's already attached to this descriptor. 747 */ 748 m = ds->ds_mbuf; 749 if (sf_add_rxbuf(sc, rxidx) != 0) { 750 if_statinc(ifp, if_ierrors); 751 SF_INIT_RXDESC(sc, rxidx); 752 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 753 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 754 continue; 755 } 756 #else 757 /* 758 * The Starfire's receive buffer must be 4-byte aligned. 759 * But this means that the data after the Ethernet header 760 * is misaligned. We must allocate a new buffer and 761 * copy the data, shifted forward 2 bytes. 762 */ 763 MGETHDR(m, M_DONTWAIT, MT_DATA); 764 if (m == NULL) { 765 dropit: 766 if_statinc(ifp, if_ierrors); 767 SF_INIT_RXDESC(sc, rxidx); 768 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 769 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 770 continue; 771 } 772 if (len > (MHLEN - 2)) { 773 MCLGET(m, M_DONTWAIT); 774 if ((m->m_flags & M_EXT) == 0) { 775 m_freem(m); 776 goto dropit; 777 } 778 } 779 m->m_data += 2; 780 781 /* 782 * Note that we use cluster for incoming frames, so the 783 * buffer is virtually contiguous. 784 */ 785 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), len); 786 787 /* Allow the receive descriptor to continue using its mbuf. */ 788 SF_INIT_RXDESC(sc, rxidx); 789 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 790 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 791 #endif /* __NO_STRICT_ALIGNMENT */ 792 793 m_set_rcvif(m, ifp); 794 m->m_pkthdr.len = m->m_len = len; 795 796 /* Pass it on. */ 797 if_percpuq_enqueue(ifp->if_percpuq, m); 798 } 799 800 /* Update the chip's pointers. */ 801 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 802 (cqci & ~CQCI_RxCompletionQ1ConsumerIndex(0x7ff)) | 803 CQCI_RxCompletionQ1ConsumerIndex(consumer)); 804 sf_funcreg_write(sc, SF_RxDescQueue1Ptrs, 805 RXQ1P_RxDescQ1Producer(bufproducer)); 806 807 /* Double-check for any new completions. */ 808 goto try_again; 809 } 810 811 /* 812 * sf_tick: 813 * 814 * One second timer, used to tick the MII and update stats. 815 */ 816 static void 817 sf_tick(void *arg) 818 { 819 struct sf_softc *sc = arg; 820 int s; 821 822 s = splnet(); 823 mii_tick(&sc->sc_mii); 824 sf_stats_update(sc); 825 splx(s); 826 827 callout_schedule(&sc->sc_tick_callout, hz); 828 } 829 830 /* 831 * sf_stats_update: 832 * 833 * Read the statitistics counters. 834 */ 835 static void 836 sf_stats_update(struct sf_softc *sc) 837 { 838 struct sf_stats stats; 839 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 840 uint32_t *p; 841 u_int i; 842 843 p = &stats.TransmitOKFrames; 844 for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) { 845 *p++ = sf_genreg_read(sc, 846 SF_STATS_BASE + (i * sizeof(uint32_t))); 847 sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0); 848 } 849 850 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 851 852 if_statadd_ref(nsr, if_opackets, stats.TransmitOKFrames); 853 854 if_statadd_ref(nsr, if_collisions, 855 stats.SingleCollisionFrames + 856 stats.MultipleCollisionFrames); 857 858 if_statadd_ref(nsr, if_oerrors, 859 stats.TransmitAbortDueToExcessiveCollisions + 860 stats.TransmitAbortDueToExcessingDeferral + 861 stats.FramesLostDueToInternalTransmitErrors); 862 863 if_statadd_ref(nsr, if_ierrors, 864 stats.ReceiveCRCErrors + stats.AlignmentErrors + 865 stats.ReceiveFramesTooLong + stats.ReceiveFramesTooShort + 866 stats.ReceiveFramesJabbersError + 867 stats.FramesLostDueToInternalReceiveErrors); 868 869 IF_STAT_PUTREF(ifp); 870 } 871 872 /* 873 * sf_reset: 874 * 875 * Perform a soft reset on the Starfire. 876 */ 877 static void 878 sf_reset(struct sf_softc *sc) 879 { 880 int i; 881 882 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0); 883 884 sf_macreset(sc); 885 886 sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_SoftReset); 887 for (i = 0; i < 1000; i++) { 888 delay(10); 889 if ((sf_funcreg_read(sc, SF_PciDeviceConfig) & 890 PDC_SoftReset) == 0) 891 break; 892 } 893 894 if (i == 1000) { 895 aprint_error_dev(sc->sc_dev, "reset failed to complete\n"); 896 sf_funcreg_write(sc, SF_PciDeviceConfig, 0); 897 } 898 899 delay(1000); 900 } 901 902 /* 903 * sf_macreset: 904 * 905 * Reset the MAC portion of the Starfire. 906 */ 907 static void 908 sf_macreset(struct sf_softc *sc) 909 { 910 911 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1 | MC1_SoftRst); 912 delay(1000); 913 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1); 914 } 915 916 /* 917 * sf_init: [ifnet interface function] 918 * 919 * Initialize the interface. Must be called at splnet(). 920 */ 921 static int 922 sf_init(struct ifnet *ifp) 923 { 924 struct sf_softc *sc = ifp->if_softc; 925 struct sf_descsoft *ds; 926 int error = 0; 927 u_int i; 928 929 /* 930 * Cancel any pending I/O. 931 */ 932 sf_stop(ifp, 0); 933 934 /* 935 * Reset the Starfire to a known state. 936 */ 937 sf_reset(sc); 938 939 /* Clear the stat counters. */ 940 for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t)) 941 sf_genreg_write(sc, SF_STATS_BASE + i, 0); 942 943 /* 944 * Initialize the transmit descriptor ring. 945 */ 946 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 947 sf_funcreg_write(sc, SF_TxDescQueueHighAddr, 0); 948 sf_funcreg_write(sc, SF_HiPrTxDescQueueBaseAddr, SF_CDTXDADDR(sc, 0)); 949 sf_funcreg_write(sc, SF_LoPrTxDescQueueBaseAddr, 0); 950 951 /* 952 * Initialize the transmit completion ring. 953 */ 954 for (i = 0; i < SF_NTCD; i++) { 955 sc->sc_txcomp[i].tcd_word0 = TCD_DMA_ID; 956 SF_CDTXCSYNC(sc, i, BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE); 957 } 958 sf_funcreg_write(sc, SF_CompletionQueueHighAddr, 0); 959 sf_funcreg_write(sc, SF_TxCompletionQueueCtrl, SF_CDTXCADDR(sc, 0)); 960 961 /* 962 * Initialize the receive descriptor ring. 963 */ 964 for (i = 0; i < SF_NRXDESC; i++) { 965 ds = &sc->sc_rxsoft[i]; 966 if (ds->ds_mbuf == NULL) { 967 if ((error = sf_add_rxbuf(sc, i)) != 0) { 968 aprint_error_dev(sc->sc_dev, 969 "unable to allocate or map rx buffer %d, " 970 "error = %d\n", i, error); 971 /* 972 * XXX Should attempt to run with fewer receive 973 * XXX buffers instead of just failing. 974 */ 975 sf_rxdrain(sc); 976 goto out; 977 } 978 } else 979 SF_INIT_RXDESC(sc, i); 980 } 981 sf_funcreg_write(sc, SF_RxDescQueueHighAddress, 0); 982 sf_funcreg_write(sc, SF_RxDescQueue1LowAddress, SF_CDRXDADDR(sc, 0)); 983 sf_funcreg_write(sc, SF_RxDescQueue2LowAddress, 0); 984 985 /* 986 * Initialize the receive completion ring. 987 */ 988 for (i = 0; i < SF_NRCD; i++) { 989 sc->sc_rxcomp[i].rcd_word0 = RCD_W0_ID; 990 sc->sc_rxcomp[i].rcd_word1 = 0; 991 sc->sc_rxcomp[i].rcd_word2 = 0; 992 sc->sc_rxcomp[i].rcd_timestamp = 0; 993 SF_CDRXCSYNC(sc, i, BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE); 994 } 995 sf_funcreg_write(sc, SF_RxCompletionQueue1Ctrl, SF_CDRXCADDR(sc, 0) | 996 RCQ1C_RxCompletionQ1Type(3)); 997 sf_funcreg_write(sc, SF_RxCompletionQueue2Ctrl, 0); 998 999 /* 1000 * Initialize the Tx CSR. 1001 */ 1002 sc->sc_TransmitFrameCSR = 0; 1003 sf_funcreg_write(sc, SF_TransmitFrameCSR, 1004 sc->sc_TransmitFrameCSR | 1005 TFCSR_TransmitThreshold(sc->sc_txthresh)); 1006 1007 /* 1008 * Initialize the Tx descriptor control register. 1009 */ 1010 sc->sc_TxDescQueueCtrl = TDQC_SkipLength(0) | 1011 TDQC_TxDmaBurstSize(4) | /* default */ 1012 TDQC_MinFrameSpacing(3) | /* 128 bytes */ 1013 TDQC_TxDescType(0); 1014 sf_funcreg_write(sc, SF_TxDescQueueCtrl, 1015 sc->sc_TxDescQueueCtrl | 1016 TDQC_TxHighPriorityFifoThreshold(sc->sc_txthresh)); 1017 1018 /* 1019 * Initialize the Rx descriptor control registers. 1020 */ 1021 sf_funcreg_write(sc, SF_RxDescQueue1Ctrl, 1022 RDQ1C_RxQ1BufferLength(MCLBYTES) | 1023 RDQ1C_RxDescSpacing(0)); 1024 sf_funcreg_write(sc, SF_RxDescQueue2Ctrl, 0); 1025 1026 /* 1027 * Initialize the Tx descriptor producer indices. 1028 */ 1029 sf_funcreg_write(sc, SF_TxDescQueueProducerIndex, 1030 TDQPI_HiPrTxProducerIndex(0) | 1031 TDQPI_LoPrTxProducerIndex(0)); 1032 1033 /* 1034 * Initialize the Rx descriptor producer indices. 1035 */ 1036 sf_funcreg_write(sc, SF_RxDescQueue1Ptrs, 1037 RXQ1P_RxDescQ1Producer(SF_NRXDESC - 1)); 1038 sf_funcreg_write(sc, SF_RxDescQueue2Ptrs, 1039 RXQ2P_RxDescQ2Producer(0)); 1040 1041 /* 1042 * Initialize the Tx and Rx completion queue consumer indices. 1043 */ 1044 sf_funcreg_write(sc, SF_CompletionQueueConsumerIndex, 1045 CQCI_TxCompletionConsumerIndex(0) | 1046 CQCI_RxCompletionQ1ConsumerIndex(0)); 1047 sf_funcreg_write(sc, SF_RxHiPrCompletionPtrs, 0); 1048 1049 /* 1050 * Initialize the Rx DMA control register. 1051 */ 1052 sf_funcreg_write(sc, SF_RxDmaCtrl, 1053 RDC_RxHighPriorityThreshold(6) | /* default */ 1054 RDC_RxBurstSize(4)); /* default */ 1055 1056 /* 1057 * Set the receive filter. 1058 */ 1059 sc->sc_RxAddressFilteringCtl = 0; 1060 sf_set_filter(sc); 1061 1062 /* 1063 * Set MacConfig1. When we set the media, MacConfig1 will 1064 * actually be written and the MAC part reset. 1065 */ 1066 sc->sc_MacConfig1 = MC1_PadEn; 1067 1068 /* 1069 * Set the media. 1070 */ 1071 if ((error = ether_mediachange(ifp)) != 0) 1072 goto out; 1073 1074 /* 1075 * Initialize the interrupt register. 1076 */ 1077 sc->sc_InterruptEn = IS_PCIPadInt | IS_RxQ1DoneInt | 1078 IS_TxQueueDoneInt | IS_TxDmaDoneInt | IS_DmaErrInt | 1079 IS_StatisticWrapInt; 1080 sf_funcreg_write(sc, SF_InterruptEn, sc->sc_InterruptEn); 1081 1082 sf_funcreg_write(sc, SF_PciDeviceConfig, PDC_IntEnable | 1083 PDC_PCIMstDmaEn | (1 << PDC_FifoThreshold_SHIFT)); 1084 1085 /* 1086 * Start the transmit and receive processes. 1087 */ 1088 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 1089 GEC_TxDmaEn | GEC_RxDmaEn | GEC_TransmitEn | GEC_ReceiveEn); 1090 1091 /* Start the on second clock. */ 1092 callout_schedule(&sc->sc_tick_callout, hz); 1093 1094 /* 1095 * Note that the interface is now running. 1096 */ 1097 ifp->if_flags |= IFF_RUNNING; 1098 ifp->if_flags &= ~IFF_OACTIVE; 1099 1100 out: 1101 if (error) { 1102 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1103 ifp->if_timer = 0; 1104 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1105 } 1106 return (error); 1107 } 1108 1109 /* 1110 * sf_rxdrain: 1111 * 1112 * Drain the receive queue. 1113 */ 1114 static void 1115 sf_rxdrain(struct sf_softc *sc) 1116 { 1117 struct sf_descsoft *ds; 1118 int i; 1119 1120 for (i = 0; i < SF_NRXDESC; i++) { 1121 ds = &sc->sc_rxsoft[i]; 1122 if (ds->ds_mbuf != NULL) { 1123 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1124 m_freem(ds->ds_mbuf); 1125 ds->ds_mbuf = NULL; 1126 } 1127 } 1128 } 1129 1130 /* 1131 * sf_stop: [ifnet interface function] 1132 * 1133 * Stop transmission on the interface. 1134 */ 1135 static void 1136 sf_stop(struct ifnet *ifp, int disable) 1137 { 1138 struct sf_softc *sc = ifp->if_softc; 1139 struct sf_descsoft *ds; 1140 int i; 1141 1142 /* Stop the one second clock. */ 1143 callout_stop(&sc->sc_tick_callout); 1144 1145 /* Down the MII. */ 1146 mii_down(&sc->sc_mii); 1147 1148 /* Disable interrupts. */ 1149 sf_funcreg_write(sc, SF_InterruptEn, 0); 1150 1151 /* Stop the transmit and receive processes. */ 1152 sf_funcreg_write(sc, SF_GeneralEthernetCtrl, 0); 1153 1154 /* 1155 * Release any queued transmit buffers. 1156 */ 1157 for (i = 0; i < SF_NTXDESC; i++) { 1158 ds = &sc->sc_txsoft[i]; 1159 if (ds->ds_mbuf != NULL) { 1160 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1161 m_freem(ds->ds_mbuf); 1162 ds->ds_mbuf = NULL; 1163 } 1164 } 1165 1166 /* 1167 * Mark the interface down and cancel the watchdog timer. 1168 */ 1169 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1170 ifp->if_timer = 0; 1171 1172 if (disable) 1173 sf_rxdrain(sc); 1174 } 1175 1176 /* 1177 * sf_read_eeprom: 1178 * 1179 * Read from the Starfire EEPROM. 1180 */ 1181 static uint8_t 1182 sf_read_eeprom(struct sf_softc *sc, int offset) 1183 { 1184 uint32_t reg; 1185 1186 reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3)); 1187 1188 return ((reg >> (8 * (offset & 3))) & 0xff); 1189 } 1190 1191 /* 1192 * sf_add_rxbuf: 1193 * 1194 * Add a receive buffer to the indicated descriptor. 1195 */ 1196 static int 1197 sf_add_rxbuf(struct sf_softc *sc, int idx) 1198 { 1199 struct sf_descsoft *ds = &sc->sc_rxsoft[idx]; 1200 struct mbuf *m; 1201 int error; 1202 1203 MGETHDR(m, M_DONTWAIT, MT_DATA); 1204 if (m == NULL) 1205 return (ENOBUFS); 1206 1207 MCLGET(m, M_DONTWAIT); 1208 if ((m->m_flags & M_EXT) == 0) { 1209 m_freem(m); 1210 return (ENOBUFS); 1211 } 1212 1213 if (ds->ds_mbuf != NULL) 1214 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1215 1216 ds->ds_mbuf = m; 1217 1218 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1219 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1220 BUS_DMA_READ | BUS_DMA_NOWAIT); 1221 if (error) { 1222 aprint_error_dev(sc->sc_dev, 1223 "can't load rx DMA map %d, error = %d\n", idx, error); 1224 panic("sf_add_rxbuf"); /* XXX */ 1225 } 1226 1227 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1228 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1229 1230 SF_INIT_RXDESC(sc, idx); 1231 1232 return (0); 1233 } 1234 1235 static void 1236 sf_set_filter_perfect(struct sf_softc *sc, int slot, const uint8_t *enaddr) 1237 { 1238 uint32_t reg0, reg1, reg2; 1239 1240 reg0 = enaddr[5] | (enaddr[4] << 8); 1241 reg1 = enaddr[3] | (enaddr[2] << 8); 1242 reg2 = enaddr[1] | (enaddr[0] << 8); 1243 1244 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0); 1245 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 4, reg1); 1246 sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 8, reg2); 1247 } 1248 1249 static void 1250 sf_set_filter_hash(struct sf_softc *sc, uint8_t *enaddr) 1251 { 1252 uint32_t hash, slot, reg; 1253 1254 hash = ether_crc32_be(enaddr, ETHER_ADDR_LEN) >> 23; 1255 slot = hash >> 4; 1256 1257 reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10)); 1258 reg |= 1 << (hash & 0xf); 1259 sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg); 1260 } 1261 1262 /* 1263 * sf_set_filter: 1264 * 1265 * Set the Starfire receive filter. 1266 */ 1267 static void 1268 sf_set_filter(struct sf_softc *sc) 1269 { 1270 struct ethercom *ec = &sc->sc_ethercom; 1271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1272 struct ether_multi *enm; 1273 struct ether_multistep step; 1274 int i; 1275 1276 /* Start by clearing the perfect and hash tables. */ 1277 for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t)) 1278 sf_genreg_write(sc, SF_PERFECT_BASE + i, 0); 1279 1280 for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t)) 1281 sf_genreg_write(sc, SF_HASH_BASE + i, 0); 1282 1283 /* 1284 * Clear the perfect and hash mode bits. 1285 */ 1286 sc->sc_RxAddressFilteringCtl &= 1287 ~(RAFC_PerfectFilteringMode(3) | RAFC_HashFilteringMode(3)); 1288 1289 if (ifp->if_flags & IFF_BROADCAST) 1290 sc->sc_RxAddressFilteringCtl |= RAFC_PassBroadcast; 1291 else 1292 sc->sc_RxAddressFilteringCtl &= ~RAFC_PassBroadcast; 1293 1294 if (ifp->if_flags & IFF_PROMISC) { 1295 sc->sc_RxAddressFilteringCtl |= RAFC_PromiscuousMode; 1296 goto allmulti; 1297 } else 1298 sc->sc_RxAddressFilteringCtl &= ~RAFC_PromiscuousMode; 1299 1300 /* 1301 * Set normal perfect filtering mode. 1302 */ 1303 sc->sc_RxAddressFilteringCtl |= RAFC_PerfectFilteringMode(1); 1304 1305 /* 1306 * First, write the station address to the perfect filter 1307 * table. 1308 */ 1309 sf_set_filter_perfect(sc, 0, CLLADDR(ifp->if_sadl)); 1310 1311 /* 1312 * Now set the hash bits for each multicast address in our 1313 * list. 1314 */ 1315 ETHER_LOCK(ec); 1316 ETHER_FIRST_MULTI(step, ec, enm); 1317 if (enm == NULL) { 1318 ETHER_UNLOCK(ec); 1319 goto done; 1320 } 1321 while (enm != NULL) { 1322 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1323 /* 1324 * We must listen to a range of multicast addresses. 1325 * For now, just accept all multicasts, rather than 1326 * trying to set only those filter bits needed to match 1327 * the range. (At this time, the only use of address 1328 * ranges is for IP multicast routing, for which the 1329 * range is big enough to require all bits set.) 1330 */ 1331 ETHER_UNLOCK(ec); 1332 goto allmulti; 1333 } 1334 sf_set_filter_hash(sc, enm->enm_addrlo); 1335 ETHER_NEXT_MULTI(step, enm); 1336 } 1337 ETHER_UNLOCK(ec); 1338 1339 /* 1340 * Set "hash only multicast dest, match regardless of VLAN ID". 1341 */ 1342 sc->sc_RxAddressFilteringCtl |= RAFC_HashFilteringMode(2); 1343 goto done; 1344 1345 allmulti: 1346 /* 1347 * XXX RAFC_PassMulticast is sub-optimal if using VLAN mode. 1348 */ 1349 sc->sc_RxAddressFilteringCtl |= RAFC_PassMulticast; 1350 ifp->if_flags |= IFF_ALLMULTI; 1351 1352 done: 1353 sf_funcreg_write(sc, SF_RxAddressFilteringCtl, 1354 sc->sc_RxAddressFilteringCtl); 1355 } 1356 1357 /* 1358 * sf_mii_read: [mii interface function] 1359 * 1360 * Read from the MII. 1361 */ 1362 static int 1363 sf_mii_read(device_t self, int phy, int reg, uint16_t *data) 1364 { 1365 struct sf_softc *sc = device_private(self); 1366 uint32_t v; 1367 int i; 1368 1369 for (i = 0; i < 1000; i++) { 1370 v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)); 1371 if (v & MiiDataValid) 1372 break; 1373 delay(1); 1374 } 1375 1376 if ((v & MiiDataValid) == 0) 1377 return -1; 1378 1379 if (MiiRegDataPort(v) == 0xffff) 1380 return -1; 1381 1382 *data = MiiRegDataPort(v); 1383 return 0; 1384 } 1385 1386 /* 1387 * sf_mii_write: [mii interface function] 1388 * 1389 * Write to the MII. 1390 */ 1391 static int 1392 sf_mii_write(device_t self, int phy, int reg, uint16_t val) 1393 { 1394 struct sf_softc *sc = device_private(self); 1395 int i; 1396 1397 sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val); 1398 1399 for (i = 0; i < 1000; i++) { 1400 if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) & 1401 MiiBusy) == 0) 1402 return 0; 1403 delay(1); 1404 } 1405 1406 printf("%s: MII write timed out\n", device_xname(sc->sc_dev)); 1407 return ETIMEDOUT; 1408 } 1409 1410 /* 1411 * sf_mii_statchg: [mii interface function] 1412 * 1413 * Callback from the PHY when the media changes. 1414 */ 1415 static void 1416 sf_mii_statchg(struct ifnet *ifp) 1417 { 1418 struct sf_softc *sc = ifp->if_softc; 1419 uint32_t ipg; 1420 1421 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1422 sc->sc_MacConfig1 |= MC1_FullDuplex; 1423 ipg = 0x15; 1424 } else { 1425 sc->sc_MacConfig1 &= ~MC1_FullDuplex; 1426 ipg = 0x11; 1427 } 1428 1429 sf_genreg_write(sc, SF_MacConfig1, sc->sc_MacConfig1); 1430 sf_macreset(sc); 1431 1432 sf_genreg_write(sc, SF_BkToBkIPG, ipg); 1433 } 1434
Indexes created Mon Sep 29 21:09:56 GMT 2025