1 1.70 andvar /* $NetBSD: aic79xx.c,v 1.70 2024/02/02 22:39:10 andvar Exp $ */ 2 1.1 fvdl 3 1.1 fvdl /* 4 1.1 fvdl * Core routines and tables shareable across OS platforms. 5 1.1 fvdl * 6 1.1 fvdl * Copyright (c) 1994-2002 Justin T. Gibbs. 7 1.1 fvdl * Copyright (c) 2000-2003 Adaptec Inc. 8 1.1 fvdl * All rights reserved. 9 1.1 fvdl * 10 1.1 fvdl * Redistribution and use in source and binary forms, with or without 11 1.1 fvdl * modification, are permitted provided that the following conditions 12 1.1 fvdl * are met: 13 1.1 fvdl * 1. Redistributions of source code must retain the above copyright 14 1.1 fvdl * notice, this list of conditions, and the following disclaimer, 15 1.1 fvdl * without modification. 16 1.1 fvdl * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 1.1 fvdl * substantially similar to the "NO WARRANTY" disclaimer below 18 1.1 fvdl * ("Disclaimer") and any redistribution must be conditioned upon 19 1.1 fvdl * including a substantially similar Disclaimer requirement for further 20 1.1 fvdl * binary redistribution. 21 1.1 fvdl * 3. Neither the names of the above-listed copyright holders nor the names 22 1.1 fvdl * of any contributors may be used to endorse or promote products derived 23 1.1 fvdl * from this software without specific prior written permission. 24 1.1 fvdl * 25 1.1 fvdl * Alternatively, this software may be distributed under the terms of the 26 1.1 fvdl * GNU General Public License ("GPL") version 2 as published by the Free 27 1.1 fvdl * Software Foundation. 28 1.1 fvdl * 29 1.1 fvdl * NO WARRANTY 30 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 1.1 fvdl * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 1.1 fvdl * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 1.1 fvdl * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 1.1 fvdl * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 1.1 fvdl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 1.1 fvdl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 1.1 fvdl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 1.1 fvdl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 1.1 fvdl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 1.1 fvdl * POSSIBILITY OF SUCH DAMAGES. 41 1.1 fvdl * 42 1.21 thorpej * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#202 $ 43 1.1 fvdl * 44 1.21 thorpej * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.24 2003/06/28 04:46:54 gibbs Exp $ 45 1.1 fvdl */ 46 1.1 fvdl /* 47 1.1 fvdl * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 1.1 fvdl * - April 2003 49 1.1 fvdl */ 50 1.6 lukem 51 1.6 lukem #include <sys/cdefs.h> 52 1.70 andvar __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.70 2024/02/02 22:39:10 andvar Exp $"); 53 1.1 fvdl 54 1.1 fvdl #include <dev/ic/aic79xx_osm.h> 55 1.1 fvdl #include <dev/ic/aic79xx_inline.h> 56 1.1 fvdl #include <dev/ic/aic7xxx_cam.h> 57 1.1 fvdl 58 1.1 fvdl #include <dev/microcode/aic7xxx/aicasm.h> 59 1.1 fvdl #include <dev/microcode/aic7xxx/aicasm_insformat.h> 60 1.1 fvdl 61 1.1 fvdl 62 1.1 fvdl /******************************** Globals *************************************/ 63 1.1 fvdl struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 64 1.1 fvdl 65 1.1 fvdl /***************************** Lookup Tables **********************************/ 66 1.55 jdolecek const char * const ahd_chip_names[] = 67 1.1 fvdl { 68 1.1 fvdl "NONE", 69 1.1 fvdl "aic7901", 70 1.1 fvdl "aic7902", 71 1.1 fvdl "aic7901A" 72 1.1 fvdl }; 73 1.1 fvdl 74 1.1 fvdl /* 75 1.1 fvdl * Hardware error codes. 76 1.1 fvdl */ 77 1.1 fvdl struct ahd_hard_error_entry { 78 1.43 tsutsui uint8_t errno; 79 1.31 christos const char *errmesg; 80 1.1 fvdl }; 81 1.1 fvdl 82 1.1 fvdl static struct ahd_hard_error_entry ahd_hard_errors[] = { 83 1.1 fvdl { DSCTMOUT, "Discard Timer has timed out" }, 84 1.1 fvdl { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 1.1 fvdl { SQPARERR, "Sequencer Parity Error" }, 86 1.1 fvdl { DPARERR, "Data-path Parity Error" }, 87 1.1 fvdl { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 1.1 fvdl { CIOPARERR, "CIOBUS Parity Error" }, 89 1.1 fvdl }; 90 1.1 fvdl static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 91 1.1 fvdl 92 1.1 fvdl static struct ahd_phase_table_entry ahd_phase_table[] = 93 1.1 fvdl { 94 1.1 fvdl { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 95 1.1 fvdl { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 96 1.1 fvdl { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 97 1.1 fvdl { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 98 1.1 fvdl { P_COMMAND, MSG_NOOP, "in Command phase" }, 99 1.1 fvdl { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 100 1.1 fvdl { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 101 1.1 fvdl { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 102 1.1 fvdl { P_BUSFREE, MSG_NOOP, "while idle" }, 103 1.1 fvdl { 0, MSG_NOOP, "in unknown phase" } 104 1.1 fvdl }; 105 1.1 fvdl 106 1.1 fvdl /* 107 1.68 andvar * In most cases we only wish to iterate over real phases, so 108 1.1 fvdl * exclude the last element from the count. 109 1.1 fvdl */ 110 1.1 fvdl static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 111 1.1 fvdl 112 1.1 fvdl /* Our Sequencer Program */ 113 1.1 fvdl #include <dev/microcode/aic7xxx/aic79xx_seq.h> 114 1.1 fvdl 115 1.1 fvdl /**************************** Function Declarations ***************************/ 116 1.1 fvdl static void ahd_handle_transmission_error(struct ahd_softc *ahd); 117 1.1 fvdl static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 118 1.1 fvdl u_int lqistat1); 119 1.1 fvdl static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 120 1.1 fvdl u_int busfreetime); 121 1.1 fvdl static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 122 1.1 fvdl static void ahd_handle_proto_violation(struct ahd_softc *ahd); 123 1.1 fvdl static void ahd_force_renegotiation(struct ahd_softc *ahd, 124 1.1 fvdl struct ahd_devinfo *devinfo); 125 1.1 fvdl 126 1.1 fvdl static struct ahd_tmode_tstate* 127 1.1 fvdl ahd_alloc_tstate(struct ahd_softc *ahd, 128 1.1 fvdl u_int scsi_id, char channel); 129 1.1 fvdl #ifdef AHD_TARGET_MODE 130 1.1 fvdl static void ahd_free_tstate(struct ahd_softc *ahd, 131 1.1 fvdl u_int scsi_id, char channel, int force); 132 1.1 fvdl #endif 133 1.1 fvdl static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 134 1.1 fvdl struct ahd_initiator_tinfo *, 135 1.1 fvdl u_int *period, 136 1.1 fvdl u_int *ppr_options, 137 1.1 fvdl role_t role); 138 1.1 fvdl static void ahd_update_neg_table(struct ahd_softc *ahd, 139 1.1 fvdl struct ahd_devinfo *devinfo, 140 1.1 fvdl struct ahd_transinfo *tinfo); 141 1.1 fvdl static void ahd_update_pending_scbs(struct ahd_softc *ahd); 142 1.1 fvdl static void ahd_fetch_devinfo(struct ahd_softc *ahd, 143 1.1 fvdl struct ahd_devinfo *devinfo); 144 1.1 fvdl static void ahd_scb_devinfo(struct ahd_softc *ahd, 145 1.1 fvdl struct ahd_devinfo *devinfo, 146 1.1 fvdl struct scb *scb); 147 1.1 fvdl static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 148 1.1 fvdl struct ahd_devinfo *devinfo, 149 1.1 fvdl struct scb *scb); 150 1.1 fvdl static void ahd_build_transfer_msg(struct ahd_softc *ahd, 151 1.1 fvdl struct ahd_devinfo *devinfo); 152 1.1 fvdl static void ahd_construct_sdtr(struct ahd_softc *ahd, 153 1.1 fvdl struct ahd_devinfo *devinfo, 154 1.1 fvdl u_int period, u_int offset); 155 1.1 fvdl static void ahd_construct_wdtr(struct ahd_softc *ahd, 156 1.1 fvdl struct ahd_devinfo *devinfo, 157 1.1 fvdl u_int bus_width); 158 1.1 fvdl static void ahd_construct_ppr(struct ahd_softc *ahd, 159 1.1 fvdl struct ahd_devinfo *devinfo, 160 1.1 fvdl u_int period, u_int offset, 161 1.1 fvdl u_int bus_width, u_int ppr_options); 162 1.1 fvdl static void ahd_clear_msg_state(struct ahd_softc *ahd); 163 1.1 fvdl static void ahd_handle_message_phase(struct ahd_softc *ahd); 164 1.1 fvdl typedef enum { 165 1.1 fvdl AHDMSG_1B, 166 1.1 fvdl AHDMSG_2B, 167 1.1 fvdl AHDMSG_EXT 168 1.1 fvdl } ahd_msgtype; 169 1.1 fvdl static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 170 1.1 fvdl u_int msgval, int full); 171 1.1 fvdl static int ahd_parse_msg(struct ahd_softc *ahd, 172 1.1 fvdl struct ahd_devinfo *devinfo); 173 1.1 fvdl static int ahd_handle_msg_reject(struct ahd_softc *ahd, 174 1.1 fvdl struct ahd_devinfo *devinfo); 175 1.1 fvdl static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 176 1.1 fvdl struct ahd_devinfo *devinfo); 177 1.1 fvdl static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 178 1.1 fvdl static void ahd_handle_devreset(struct ahd_softc *ahd, 179 1.1 fvdl struct ahd_devinfo *devinfo, 180 1.1 fvdl u_int lun, cam_status status, 181 1.31 christos const char *message, 182 1.31 christos int verbose_level); 183 1.1 fvdl #if AHD_TARGET_MODE 184 1.1 fvdl static void ahd_setup_target_msgin(struct ahd_softc *ahd, 185 1.1 fvdl struct ahd_devinfo *devinfo, 186 1.1 fvdl struct scb *scb); 187 1.1 fvdl #endif 188 1.1 fvdl 189 1.1 fvdl static u_int ahd_sglist_size(struct ahd_softc *ahd); 190 1.1 fvdl static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 191 1.1 fvdl static void ahd_initialize_hscbs(struct ahd_softc *ahd); 192 1.1 fvdl static int ahd_init_scbdata(struct ahd_softc *ahd); 193 1.1 fvdl static void ahd_fini_scbdata(struct ahd_softc *ahd); 194 1.1 fvdl static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 195 1.1 fvdl static void ahd_iocell_first_selection(struct ahd_softc *ahd); 196 1.1 fvdl static void ahd_add_col_list(struct ahd_softc *ahd, 197 1.1 fvdl struct scb *scb, u_int col_idx); 198 1.1 fvdl static void ahd_rem_col_list(struct ahd_softc *ahd, 199 1.1 fvdl struct scb *scb); 200 1.1 fvdl static void ahd_chip_init(struct ahd_softc *ahd); 201 1.1 fvdl static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 202 1.1 fvdl struct scb *prev_scb, 203 1.1 fvdl struct scb *scb); 204 1.1 fvdl static int ahd_qinfifo_count(struct ahd_softc *ahd); 205 1.1 fvdl static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 206 1.1 fvdl char channel, int lun, u_int tag, 207 1.1 fvdl role_t role, uint32_t status, 208 1.1 fvdl ahd_search_action action, 209 1.1 fvdl u_int *list_head, u_int tid); 210 1.1 fvdl static void ahd_stitch_tid_list(struct ahd_softc *ahd, 211 1.1 fvdl u_int tid_prev, u_int tid_cur, 212 1.1 fvdl u_int tid_next); 213 1.1 fvdl static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 214 1.1 fvdl u_int scbid); 215 1.1 fvdl static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 216 1.1 fvdl u_int prev, u_int next, u_int tid); 217 1.1 fvdl static void ahd_reset_current_bus(struct ahd_softc *ahd); 218 1.1 fvdl static ahd_callback_t ahd_reset_poll; 219 1.1 fvdl static ahd_callback_t ahd_stat_timer; 220 1.1 fvdl #ifdef AHD_DUMP_SEQ 221 1.1 fvdl static void ahd_dumpseq(struct ahd_softc *ahd); 222 1.1 fvdl #endif 223 1.1 fvdl static void ahd_loadseq(struct ahd_softc *ahd); 224 1.1 fvdl static int ahd_check_patch(struct ahd_softc *ahd, 225 1.56 jdolecek const struct patch **start_patch, 226 1.1 fvdl u_int start_instr, u_int *skip_addr); 227 1.1 fvdl static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 228 1.1 fvdl u_int address); 229 1.1 fvdl static void ahd_download_instr(struct ahd_softc *ahd, 230 1.1 fvdl u_int instrptr, uint8_t *dconsts); 231 1.1 fvdl static int ahd_probe_stack_size(struct ahd_softc *ahd); 232 1.21 thorpej static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 233 1.21 thorpej struct scb *scb); 234 1.21 thorpej static void ahd_run_data_fifo(struct ahd_softc *ahd, 235 1.21 thorpej struct scb *scb); 236 1.21 thorpej 237 1.1 fvdl #ifdef AHD_TARGET_MODE 238 1.1 fvdl static void ahd_queue_lstate_event(struct ahd_softc *ahd, 239 1.1 fvdl struct ahd_tmode_lstate *lstate, 240 1.1 fvdl u_int initiator_id, 241 1.1 fvdl u_int event_type, 242 1.1 fvdl u_int event_arg); 243 1.1 fvdl static void ahd_update_scsiid(struct ahd_softc *ahd, 244 1.1 fvdl u_int targid_mask); 245 1.1 fvdl static int ahd_handle_target_cmd(struct ahd_softc *ahd, 246 1.1 fvdl struct target_cmd *cmd); 247 1.1 fvdl #endif 248 1.1 fvdl 249 1.1 fvdl /************************** Added for porting to NetBSD ***********************/ 250 1.1 fvdl static int ahd_createdmamem(bus_dma_tag_t tag, 251 1.1 fvdl int size, 252 1.1 fvdl int flags, 253 1.1 fvdl bus_dmamap_t *mapp, 254 1.37 christos void **vaddr, 255 1.1 fvdl bus_addr_t *baddr, 256 1.1 fvdl bus_dma_segment_t *seg, 257 1.1 fvdl int *nseg, 258 1.1 fvdl const char *myname, const char *what); 259 1.1 fvdl 260 1.1 fvdl static void ahd_freedmamem(bus_dma_tag_t tag, 261 1.1 fvdl int size, 262 1.1 fvdl bus_dmamap_t map, 263 1.37 christos void *vaddr, 264 1.1 fvdl bus_dma_segment_t *seg, 265 1.1 fvdl int nseg); 266 1.1 fvdl 267 1.1 fvdl /******************************** Private Inlines *****************************/ 268 1.33 perry static inline void ahd_assert_atn(struct ahd_softc *ahd); 269 1.33 perry static inline int ahd_currently_packetized(struct ahd_softc *ahd); 270 1.33 perry static inline int ahd_set_active_fifo(struct ahd_softc *ahd); 271 1.1 fvdl 272 1.33 perry static inline void 273 1.1 fvdl ahd_assert_atn(struct ahd_softc *ahd) 274 1.1 fvdl { 275 1.1 fvdl ahd_outb(ahd, SCSISIGO, ATNO); 276 1.1 fvdl } 277 1.1 fvdl 278 1.1 fvdl /* 279 1.1 fvdl * Determine if the current connection has a packetized 280 1.1 fvdl * agreement. This does not necessarily mean that we 281 1.1 fvdl * are currently in a packetized transfer. We could 282 1.1 fvdl * just as easily be sending or receiving a message. 283 1.1 fvdl */ 284 1.33 perry static inline int 285 1.1 fvdl ahd_currently_packetized(struct ahd_softc *ahd) 286 1.1 fvdl { 287 1.1 fvdl ahd_mode_state saved_modes; 288 1.1 fvdl int packetized; 289 1.1 fvdl 290 1.1 fvdl saved_modes = ahd_save_modes(ahd); 291 1.1 fvdl if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 292 1.1 fvdl /* 293 1.1 fvdl * The packetized bit refers to the last 294 1.1 fvdl * connection, not the current one. Check 295 1.1 fvdl * for non-zero LQISTATE instead. 296 1.1 fvdl */ 297 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 298 1.1 fvdl packetized = ahd_inb(ahd, LQISTATE) != 0; 299 1.1 fvdl } else { 300 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 301 1.1 fvdl packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 302 1.1 fvdl } 303 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 304 1.1 fvdl return (packetized); 305 1.1 fvdl } 306 1.1 fvdl 307 1.33 perry static inline int 308 1.1 fvdl ahd_set_active_fifo(struct ahd_softc *ahd) 309 1.1 fvdl { 310 1.1 fvdl u_int active_fifo; 311 1.1 fvdl 312 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 313 1.1 fvdl active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 314 1.1 fvdl switch (active_fifo) { 315 1.1 fvdl case 0: 316 1.1 fvdl case 1: 317 1.1 fvdl ahd_set_modes(ahd, active_fifo, active_fifo); 318 1.1 fvdl return (1); 319 1.1 fvdl default: 320 1.1 fvdl return (0); 321 1.1 fvdl } 322 1.1 fvdl } 323 1.1 fvdl 324 1.1 fvdl /************************* Sequencer Execution Control ************************/ 325 1.1 fvdl /* 326 1.1 fvdl * Restart the sequencer program from address zero 327 1.1 fvdl */ 328 1.1 fvdl void 329 1.1 fvdl ahd_restart(struct ahd_softc *ahd) 330 1.1 fvdl { 331 1.30 perry 332 1.1 fvdl ahd_pause(ahd); 333 1.1 fvdl 334 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 335 1.1 fvdl 336 1.1 fvdl /* No more pending messages */ 337 1.1 fvdl ahd_clear_msg_state(ahd); 338 1.1 fvdl ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 339 1.1 fvdl ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 340 1.1 fvdl ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 341 1.1 fvdl ahd_outb(ahd, SEQINTCTL, 0); 342 1.1 fvdl ahd_outb(ahd, LASTPHASE, P_BUSFREE); 343 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS, 0); 344 1.1 fvdl ahd_outb(ahd, SAVED_SCSIID, 0xFF); 345 1.1 fvdl ahd_outb(ahd, SAVED_LUN, 0xFF); 346 1.1 fvdl 347 1.1 fvdl /* 348 1.1 fvdl * Ensure that the sequencer's idea of TQINPOS 349 1.1 fvdl * matches our own. The sequencer increments TQINPOS 350 1.1 fvdl * only after it sees a DMA complete and a reset could 351 1.1 fvdl * occur before the increment leaving the kernel to believe 352 1.1 fvdl * the command arrived but the sequencer to not. 353 1.1 fvdl */ 354 1.1 fvdl ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 355 1.1 fvdl 356 1.1 fvdl /* Always allow reselection */ 357 1.1 fvdl ahd_outb(ahd, SCSISEQ1, 358 1.1 fvdl ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 359 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 360 1.1 fvdl ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 361 1.1 fvdl ahd_unpause(ahd); 362 1.1 fvdl } 363 1.1 fvdl 364 1.1 fvdl void 365 1.1 fvdl ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 366 1.1 fvdl { 367 1.1 fvdl ahd_mode_state saved_modes; 368 1.1 fvdl 369 1.1 fvdl #ifdef AHD_DEBUG 370 1.1 fvdl if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 371 1.1 fvdl printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 372 1.1 fvdl #endif 373 1.1 fvdl saved_modes = ahd_save_modes(ahd); 374 1.1 fvdl ahd_set_modes(ahd, fifo, fifo); 375 1.1 fvdl ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 376 1.1 fvdl if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 377 1.1 fvdl ahd_outb(ahd, CCSGCTL, CCSGRESET); 378 1.1 fvdl ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 379 1.1 fvdl ahd_outb(ahd, SG_STATE, 0); 380 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 381 1.1 fvdl } 382 1.1 fvdl 383 1.1 fvdl /************************* Input/Output Queues ********************************/ 384 1.1 fvdl /* 385 1.1 fvdl * Flush and completed commands that are sitting in the command 386 1.4 wiz * complete queues down on the chip but have yet to be DMA'ed back up. 387 1.1 fvdl */ 388 1.1 fvdl void 389 1.1 fvdl ahd_flush_qoutfifo(struct ahd_softc *ahd) 390 1.1 fvdl { 391 1.1 fvdl struct scb *scb; 392 1.1 fvdl ahd_mode_state saved_modes; 393 1.1 fvdl u_int saved_scbptr; 394 1.1 fvdl u_int ccscbctl; 395 1.1 fvdl u_int scbid; 396 1.1 fvdl u_int next_scbid; 397 1.1 fvdl 398 1.1 fvdl saved_modes = ahd_save_modes(ahd); 399 1.21 thorpej 400 1.21 thorpej /* 401 1.21 thorpej * Complete any SCBs that just finished being 402 1.21 thorpej * DMA'ed into the qoutfifo. 403 1.21 thorpej */ 404 1.21 thorpej ahd_run_qoutfifo(ahd); 405 1.21 thorpej 406 1.21 thorpej /* 407 1.64 andvar * Flush the good status FIFO for completed packetized commands. 408 1.21 thorpej */ 409 1.21 thorpej ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 410 1.21 thorpej saved_scbptr = ahd_get_scbptr(ahd); 411 1.21 thorpej while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 412 1.21 thorpej u_int fifo_mode; 413 1.21 thorpej u_int i; 414 1.21 thorpej 415 1.21 thorpej scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 416 1.21 thorpej | ahd_inb(ahd, GSFIFO); 417 1.21 thorpej scb = ahd_lookup_scb(ahd, scbid); 418 1.21 thorpej if (scb == NULL) { 419 1.21 thorpej printf("%s: Warning - GSFIFO SCB %d invalid\n", 420 1.21 thorpej ahd_name(ahd), scbid); 421 1.21 thorpej continue; 422 1.21 thorpej } 423 1.21 thorpej /* 424 1.21 thorpej * Determine if this transaction is still active in 425 1.21 thorpej * any FIFO. If it is, we must flush that FIFO to 426 1.21 thorpej * the host before completing the command. 427 1.21 thorpej */ 428 1.21 thorpej fifo_mode = 0; 429 1.21 thorpej for (i = 0; i < 2; i++) { 430 1.21 thorpej /* Toggle to the other mode. */ 431 1.21 thorpej fifo_mode ^= 1; 432 1.21 thorpej ahd_set_modes(ahd, fifo_mode, fifo_mode); 433 1.21 thorpej if (ahd_scb_active_in_fifo(ahd, scb) == 0) 434 1.21 thorpej continue; 435 1.21 thorpej 436 1.21 thorpej ahd_run_data_fifo(ahd, scb); 437 1.21 thorpej 438 1.21 thorpej /* 439 1.21 thorpej * Clearing this transaction in this FIFO may 440 1.21 thorpej * cause a CFG4DATA for this same transaction 441 1.21 thorpej * to assert in the other FIFO. Make sure we 442 1.21 thorpej * loop one more time and check the other FIFO. 443 1.21 thorpej */ 444 1.21 thorpej i = 0; 445 1.21 thorpej } 446 1.21 thorpej ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 447 1.21 thorpej ahd_set_scbptr(ahd, scbid); 448 1.21 thorpej if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 449 1.21 thorpej && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 450 1.21 thorpej || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 451 1.21 thorpej & SG_LIST_NULL) != 0)) { 452 1.21 thorpej u_int comp_head; 453 1.21 thorpej 454 1.21 thorpej /* 455 1.21 thorpej * The transfer completed with a residual. 456 1.21 thorpej * Place this SCB on the complete DMA list 457 1.21 thorpej * so that we Update our in-core copy of the 458 1.21 thorpej * SCB before completing the command. 459 1.21 thorpej */ 460 1.21 thorpej ahd_outb(ahd, SCB_SCSI_STATUS, 0); 461 1.21 thorpej ahd_outb(ahd, SCB_SGPTR, 462 1.21 thorpej ahd_inb_scbram(ahd, SCB_SGPTR) 463 1.21 thorpej | SG_STATUS_VALID); 464 1.21 thorpej ahd_outw(ahd, SCB_TAG, SCB_GET_TAG(scb)); 465 1.21 thorpej comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 466 1.21 thorpej ahd_outw(ahd, SCB_NEXT_COMPLETE, comp_head); 467 1.21 thorpej if (SCBID_IS_NULL(comp_head)) 468 1.21 thorpej ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, 469 1.21 thorpej SCB_GET_TAG(scb)); 470 1.21 thorpej } else 471 1.21 thorpej ahd_complete_scb(ahd, scb); 472 1.21 thorpej } 473 1.21 thorpej ahd_set_scbptr(ahd, saved_scbptr); 474 1.21 thorpej 475 1.21 thorpej /* 476 1.21 thorpej * Setup for command channel portion of flush. 477 1.21 thorpej */ 478 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 479 1.1 fvdl 480 1.1 fvdl /* 481 1.1 fvdl * Wait for any inprogress DMA to complete and clear DMA state 482 1.1 fvdl * if this if for an SCB in the qinfifo. 483 1.1 fvdl */ 484 1.18 thorpej while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 485 1.1 fvdl 486 1.1 fvdl if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 487 1.1 fvdl if ((ccscbctl & ARRDONE) != 0) 488 1.1 fvdl break; 489 1.1 fvdl } else if ((ccscbctl & CCSCBDONE) != 0) 490 1.1 fvdl break; 491 1.1 fvdl ahd_delay(200); 492 1.1 fvdl } 493 1.1 fvdl if ((ccscbctl & CCSCBDIR) != 0) 494 1.1 fvdl ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 495 1.1 fvdl 496 1.21 thorpej saved_scbptr = ahd_get_scbptr(ahd); 497 1.1 fvdl /* 498 1.1 fvdl * Manually update/complete any completed SCBs that are waiting to be 499 1.1 fvdl * DMA'ed back up to the host. 500 1.1 fvdl */ 501 1.1 fvdl scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 502 1.1 fvdl while (!SCBID_IS_NULL(scbid)) { 503 1.1 fvdl uint8_t *hscb_ptr; 504 1.1 fvdl u_int i; 505 1.30 perry 506 1.1 fvdl ahd_set_scbptr(ahd, scbid); 507 1.1 fvdl next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 508 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 509 1.1 fvdl if (scb == NULL) { 510 1.1 fvdl printf("%s: Warning - DMA-up and complete " 511 1.1 fvdl "SCB %d invalid\n", ahd_name(ahd), scbid); 512 1.1 fvdl continue; 513 1.1 fvdl } 514 1.1 fvdl hscb_ptr = (uint8_t *)scb->hscb; 515 1.1 fvdl for (i = 0; i < sizeof(struct hardware_scb); i++) 516 1.1 fvdl *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 517 1.1 fvdl 518 1.1 fvdl ahd_complete_scb(ahd, scb); 519 1.1 fvdl scbid = next_scbid; 520 1.1 fvdl } 521 1.1 fvdl ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 522 1.1 fvdl 523 1.1 fvdl scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 524 1.1 fvdl while (!SCBID_IS_NULL(scbid)) { 525 1.1 fvdl 526 1.1 fvdl ahd_set_scbptr(ahd, scbid); 527 1.1 fvdl next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 528 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 529 1.1 fvdl if (scb == NULL) { 530 1.1 fvdl printf("%s: Warning - Complete SCB %d invalid\n", 531 1.1 fvdl ahd_name(ahd), scbid); 532 1.1 fvdl continue; 533 1.1 fvdl } 534 1.1 fvdl 535 1.1 fvdl ahd_complete_scb(ahd, scb); 536 1.1 fvdl scbid = next_scbid; 537 1.1 fvdl } 538 1.1 fvdl ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 539 1.21 thorpej 540 1.21 thorpej /* 541 1.21 thorpej * Restore state. 542 1.21 thorpej */ 543 1.1 fvdl ahd_set_scbptr(ahd, saved_scbptr); 544 1.21 thorpej ahd_restore_modes(ahd, saved_modes); 545 1.21 thorpej ahd->flags |= AHD_UPDATE_PEND_CMDS; 546 1.21 thorpej } 547 1.21 thorpej 548 1.21 thorpej /* 549 1.21 thorpej * Determine if an SCB for a packetized transaction 550 1.21 thorpej * is active in a FIFO. 551 1.21 thorpej */ 552 1.21 thorpej static int 553 1.21 thorpej ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 554 1.21 thorpej { 555 1.1 fvdl 556 1.1 fvdl /* 557 1.21 thorpej * The FIFO is only active for our transaction if 558 1.21 thorpej * the SCBPTR matches the SCB's ID and the firmware 559 1.21 thorpej * has installed a handler for the FIFO or we have 560 1.21 thorpej * a pending SAVEPTRS or CFG4DATA interrupt. 561 1.1 fvdl */ 562 1.21 thorpej if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 563 1.21 thorpej || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 564 1.21 thorpej && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 565 1.21 thorpej return (0); 566 1.21 thorpej 567 1.21 thorpej return (1); 568 1.21 thorpej } 569 1.21 thorpej 570 1.21 thorpej /* 571 1.21 thorpej * Run a data fifo to completion for a transaction we know 572 1.21 thorpej * has completed across the SCSI bus (good status has been 573 1.21 thorpej * received). We are already set to the correct FIFO mode 574 1.21 thorpej * on entry to this routine. 575 1.21 thorpej * 576 1.21 thorpej * This function attempts to operate exactly as the firmware 577 1.21 thorpej * would when running this FIFO. Care must be taken to update 578 1.21 thorpej * this routine any time the firmware's FIFO algorithm is 579 1.21 thorpej * changed. 580 1.21 thorpej */ 581 1.21 thorpej static void 582 1.21 thorpej ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 583 1.21 thorpej { 584 1.21 thorpej u_int seqintsrc; 585 1.21 thorpej 586 1.21 thorpej while (1) { 587 1.21 thorpej seqintsrc = ahd_inb(ahd, SEQINTSRC); 588 1.21 thorpej if ((seqintsrc & CFG4DATA) != 0) { 589 1.21 thorpej uint32_t datacnt; 590 1.21 thorpej uint32_t sgptr; 591 1.21 thorpej 592 1.21 thorpej /* 593 1.21 thorpej * Clear full residual flag. 594 1.21 thorpej */ 595 1.21 thorpej sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 596 1.21 thorpej ahd_outb(ahd, SCB_SGPTR, sgptr); 597 1.21 thorpej 598 1.21 thorpej /* 599 1.21 thorpej * Load datacnt and address. 600 1.21 thorpej */ 601 1.21 thorpej datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 602 1.21 thorpej if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 603 1.21 thorpej sgptr |= LAST_SEG; 604 1.21 thorpej ahd_outb(ahd, SG_STATE, 0); 605 1.21 thorpej } else 606 1.21 thorpej ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 607 1.21 thorpej ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 608 1.21 thorpej ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 609 1.21 thorpej ahd_outb(ahd, SG_CACHE_PRE, sgptr); 610 1.21 thorpej ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 611 1.21 thorpej 612 1.21 thorpej /* 613 1.21 thorpej * Initialize Residual Fields. 614 1.21 thorpej */ 615 1.21 thorpej ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 616 1.21 thorpej ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 617 1.21 thorpej 618 1.21 thorpej /* 619 1.21 thorpej * Mark the SCB as having a FIFO in use. 620 1.21 thorpej */ 621 1.21 thorpej ahd_outb(ahd, SCB_FIFO_USE_COUNT, 622 1.21 thorpej ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 623 1.30 perry 624 1.21 thorpej /* 625 1.21 thorpej * Install a "fake" handler for this FIFO. 626 1.21 thorpej */ 627 1.21 thorpej ahd_outw(ahd, LONGJMP_ADDR, 0); 628 1.21 thorpej 629 1.21 thorpej /* 630 1.21 thorpej * Notify the hardware that we have satisfied 631 1.21 thorpej * this sequencer interrupt. 632 1.21 thorpej */ 633 1.21 thorpej ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 634 1.21 thorpej } else if ((seqintsrc & SAVEPTRS) != 0) { 635 1.21 thorpej uint32_t sgptr; 636 1.21 thorpej uint32_t resid; 637 1.21 thorpej 638 1.21 thorpej if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 639 1.21 thorpej /* 640 1.21 thorpej * Snapshot Save Pointers. Clear 641 1.21 thorpej * the snapshot and continue. 642 1.21 thorpej */ 643 1.21 thorpej ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 644 1.21 thorpej continue; 645 1.21 thorpej } 646 1.21 thorpej 647 1.21 thorpej /* 648 1.21 thorpej * Disable S/G fetch so the DMA engine 649 1.21 thorpej * is available to future users. 650 1.21 thorpej */ 651 1.21 thorpej if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 652 1.21 thorpej ahd_outb(ahd, CCSGCTL, 0); 653 1.21 thorpej ahd_outb(ahd, SG_STATE, 0); 654 1.21 thorpej 655 1.21 thorpej /* 656 1.66 andvar * Flush the data FIFO. Strictly only 657 1.21 thorpej * necessary for Rev A parts. 658 1.21 thorpej */ 659 1.21 thorpej ahd_outb(ahd, DFCNTRL, 660 1.21 thorpej ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 661 1.21 thorpej 662 1.21 thorpej /* 663 1.21 thorpej * Calculate residual. 664 1.21 thorpej */ 665 1.21 thorpej sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 666 1.21 thorpej resid = ahd_inl(ahd, SHCNT); 667 1.21 thorpej resid |= 668 1.21 thorpej ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 669 1.21 thorpej ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 670 1.21 thorpej if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 671 1.21 thorpej /* 672 1.21 thorpej * Must back up to the correct S/G element. 673 1.21 thorpej * Typically this just means resetting our 674 1.21 thorpej * low byte to the offset in the SG_CACHE, 675 1.21 thorpej * but if we wrapped, we have to correct 676 1.21 thorpej * the other bytes of the sgptr too. 677 1.21 thorpej */ 678 1.21 thorpej if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 679 1.21 thorpej && (sgptr & 0x80) == 0) 680 1.21 thorpej sgptr -= 0x100; 681 1.21 thorpej sgptr &= ~0xFF; 682 1.21 thorpej sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 683 1.21 thorpej & SG_ADDR_MASK; 684 1.21 thorpej ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 685 1.21 thorpej ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 686 1.21 thorpej } else if ((resid & AHD_SG_LEN_MASK) == 0) { 687 1.21 thorpej ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 688 1.21 thorpej sgptr | SG_LIST_NULL); 689 1.21 thorpej } 690 1.21 thorpej /* 691 1.21 thorpej * Save Pointers. 692 1.21 thorpej */ 693 1.21 thorpej ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 694 1.21 thorpej ahd_outl(ahd, SCB_DATACNT, resid); 695 1.21 thorpej ahd_outl(ahd, SCB_SGPTR, sgptr); 696 1.21 thorpej ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 697 1.21 thorpej ahd_outb(ahd, SEQIMODE, 698 1.21 thorpej ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 699 1.21 thorpej /* 700 1.21 thorpej * If the data is to the SCSI bus, we are 701 1.21 thorpej * done, otherwise wait for FIFOEMP. 702 1.21 thorpej */ 703 1.21 thorpej if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 704 1.21 thorpej break; 705 1.21 thorpej } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 706 1.21 thorpej uint32_t sgptr; 707 1.21 thorpej uint64_t data_addr; 708 1.21 thorpej uint32_t data_len; 709 1.21 thorpej u_int dfcntrl; 710 1.21 thorpej 711 1.21 thorpej /* 712 1.21 thorpej * Disable S/G fetch so the DMA engine 713 1.21 thorpej * is available to future users. 714 1.21 thorpej */ 715 1.21 thorpej if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 716 1.21 thorpej ahd_outb(ahd, CCSGCTL, 0); 717 1.21 thorpej ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 718 1.21 thorpej } 719 1.21 thorpej 720 1.21 thorpej /* 721 1.21 thorpej * Wait for the DMA engine to notice that the 722 1.21 thorpej * host transfer is enabled and that there is 723 1.21 thorpej * space in the S/G FIFO for new segments before 724 1.21 thorpej * loading more segments. 725 1.21 thorpej */ 726 1.21 thorpej if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) == 0) 727 1.21 thorpej continue; 728 1.21 thorpej if ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) == 0) 729 1.21 thorpej continue; 730 1.21 thorpej 731 1.21 thorpej /* 732 1.21 thorpej * Determine the offset of the next S/G 733 1.21 thorpej * element to load. 734 1.21 thorpej */ 735 1.21 thorpej sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 736 1.21 thorpej sgptr &= SG_PTR_MASK; 737 1.21 thorpej if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 738 1.21 thorpej struct ahd_dma64_seg *sg; 739 1.21 thorpej 740 1.21 thorpej sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 741 1.21 thorpej data_addr = sg->addr; 742 1.21 thorpej data_len = sg->len; 743 1.21 thorpej sgptr += sizeof(*sg); 744 1.21 thorpej } else { 745 1.21 thorpej struct ahd_dma_seg *sg; 746 1.21 thorpej 747 1.21 thorpej sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 748 1.21 thorpej data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 749 1.21 thorpej data_addr <<= 8; 750 1.21 thorpej data_addr |= sg->addr; 751 1.21 thorpej data_len = sg->len; 752 1.21 thorpej sgptr += sizeof(*sg); 753 1.21 thorpej } 754 1.21 thorpej 755 1.21 thorpej /* 756 1.21 thorpej * Update residual information. 757 1.21 thorpej */ 758 1.21 thorpej ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 759 1.21 thorpej ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 760 1.21 thorpej 761 1.21 thorpej /* 762 1.21 thorpej * Load the S/G. 763 1.21 thorpej */ 764 1.21 thorpej if (data_len & AHD_DMA_LAST_SEG) { 765 1.21 thorpej sgptr |= LAST_SEG; 766 1.21 thorpej ahd_outb(ahd, SG_STATE, 0); 767 1.21 thorpej } 768 1.21 thorpej ahd_outq(ahd, HADDR, data_addr); 769 1.21 thorpej ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 770 1.21 thorpej ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 771 1.21 thorpej 772 1.21 thorpej /* 773 1.21 thorpej * Advertise the segment to the hardware. 774 1.21 thorpej */ 775 1.21 thorpej dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 776 1.21 thorpej if ((ahd->features & AHD_NEW_DFCNTRL_OPTS)!=0) { 777 1.21 thorpej /* 778 1.21 thorpej * Use SCSIENWRDIS so that SCSIEN 779 1.21 thorpej * is never modified by this 780 1.21 thorpej * operation. 781 1.21 thorpej */ 782 1.21 thorpej dfcntrl |= SCSIENWRDIS; 783 1.21 thorpej } 784 1.21 thorpej ahd_outb(ahd, DFCNTRL, dfcntrl); 785 1.21 thorpej } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) 786 1.21 thorpej & LAST_SEG_DONE) != 0) { 787 1.21 thorpej 788 1.21 thorpej /* 789 1.21 thorpej * Transfer completed to the end of SG list 790 1.21 thorpej * and has flushed to the host. 791 1.21 thorpej */ 792 1.21 thorpej ahd_outb(ahd, SCB_SGPTR, 793 1.21 thorpej ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 794 1.21 thorpej break; 795 1.21 thorpej } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 796 1.21 thorpej break; 797 1.1 fvdl } 798 1.21 thorpej ahd_delay(200); 799 1.1 fvdl } 800 1.1 fvdl /* 801 1.21 thorpej * Clear any handler for this FIFO, decrement 802 1.21 thorpej * the FIFO use count for the SCB, and release 803 1.21 thorpej * the FIFO. 804 1.1 fvdl */ 805 1.21 thorpej ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 806 1.21 thorpej ahd_outb(ahd, SCB_FIFO_USE_COUNT, 807 1.21 thorpej ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 808 1.21 thorpej ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 809 1.1 fvdl } 810 1.1 fvdl 811 1.1 fvdl void 812 1.1 fvdl ahd_run_qoutfifo(struct ahd_softc *ahd) 813 1.1 fvdl { 814 1.1 fvdl struct scb *scb; 815 1.1 fvdl u_int scb_index; 816 1.1 fvdl 817 1.1 fvdl if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 818 1.1 fvdl panic("ahd_run_qoutfifo recursion"); 819 1.1 fvdl ahd->flags |= AHD_RUNNING_QOUTFIFO; 820 1.1 fvdl ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 821 1.1 fvdl while ((ahd->qoutfifo[ahd->qoutfifonext] 822 1.1 fvdl & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 823 1.1 fvdl 824 1.1 fvdl scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 825 1.1 fvdl & ~QOUTFIFO_ENTRY_VALID_LE); 826 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 827 1.1 fvdl if (scb == NULL) { 828 1.1 fvdl printf("%s: WARNING no command for scb %d " 829 1.1 fvdl "(cmdcmplt)\nQOUTPOS = %d\n", 830 1.1 fvdl ahd_name(ahd), scb_index, 831 1.1 fvdl ahd->qoutfifonext); 832 1.1 fvdl ahd_dump_card_state(ahd); 833 1.1 fvdl } else 834 1.1 fvdl ahd_complete_scb(ahd, scb); 835 1.1 fvdl 836 1.1 fvdl ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 837 1.1 fvdl if (ahd->qoutfifonext == 0) 838 1.1 fvdl ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 839 1.1 fvdl } 840 1.1 fvdl ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 841 1.1 fvdl } 842 1.1 fvdl 843 1.1 fvdl /************************* Interrupt Handling *********************************/ 844 1.1 fvdl void 845 1.1 fvdl ahd_handle_hwerrint(struct ahd_softc *ahd) 846 1.1 fvdl { 847 1.1 fvdl /* 848 1.1 fvdl * Some catastrophic hardware error has occurred. 849 1.1 fvdl * Print it for the user and disable the controller. 850 1.1 fvdl */ 851 1.1 fvdl int i; 852 1.1 fvdl int error; 853 1.1 fvdl 854 1.1 fvdl error = ahd_inb(ahd, ERROR); 855 1.1 fvdl for (i = 0; i < num_errors; i++) { 856 1.1 fvdl if ((error & ahd_hard_errors[i].errno) != 0) 857 1.1 fvdl printf("%s: hwerrint, %s\n", 858 1.1 fvdl ahd_name(ahd), ahd_hard_errors[i].errmesg); 859 1.1 fvdl } 860 1.1 fvdl 861 1.1 fvdl ahd_dump_card_state(ahd); 862 1.1 fvdl panic("BRKADRINT"); 863 1.1 fvdl 864 1.1 fvdl /* Tell everyone that this HBA is no longer available */ 865 1.1 fvdl ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 866 1.1 fvdl CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 867 1.1 fvdl CAM_NO_HBA); 868 1.1 fvdl 869 1.1 fvdl /* Tell the system that this controller has gone away. */ 870 1.1 fvdl ahd_free(ahd); 871 1.1 fvdl } 872 1.1 fvdl 873 1.1 fvdl void 874 1.36 christos ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 875 1.1 fvdl { 876 1.1 fvdl u_int seqintcode; 877 1.1 fvdl 878 1.1 fvdl /* 879 1.1 fvdl * Save the sequencer interrupt code and clear the SEQINT 880 1.1 fvdl * bit. We will unpause the sequencer, if appropriate, 881 1.1 fvdl * after servicing the request. 882 1.1 fvdl */ 883 1.1 fvdl seqintcode = ahd_inb(ahd, SEQINTCODE); 884 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSEQINT); 885 1.1 fvdl if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 886 1.1 fvdl /* 887 1.1 fvdl * Unpause the sequencer and let it clear 888 1.1 fvdl * SEQINT by writing NO_SEQINT to it. This 889 1.1 fvdl * will cause the sequencer to be paused again, 890 1.1 fvdl * which is the expected state of this routine. 891 1.1 fvdl */ 892 1.1 fvdl ahd_unpause(ahd); 893 1.1 fvdl while (!ahd_is_paused(ahd)) 894 1.1 fvdl ; 895 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSEQINT); 896 1.1 fvdl } 897 1.1 fvdl ahd_update_modes(ahd); 898 1.1 fvdl #ifdef AHD_DEBUG 899 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 900 1.1 fvdl printf("%s: Handle Seqint Called for code %d\n", 901 1.1 fvdl ahd_name(ahd), seqintcode); 902 1.1 fvdl #endif 903 1.1 fvdl switch (seqintcode) { 904 1.9 thorpej case BAD_SCB_STATUS: 905 1.9 thorpej { 906 1.9 thorpej struct scb *scb; 907 1.9 thorpej u_int scbid; 908 1.9 thorpej int cmds_pending; 909 1.9 thorpej 910 1.9 thorpej scbid = ahd_get_scbptr(ahd); 911 1.9 thorpej scb = ahd_lookup_scb(ahd, scbid); 912 1.9 thorpej if (scb != NULL) { 913 1.9 thorpej ahd_complete_scb(ahd, scb); 914 1.9 thorpej } else { 915 1.9 thorpej printf("%s: WARNING no command for scb %d " 916 1.9 thorpej "(bad status)\n", ahd_name(ahd), scbid); 917 1.9 thorpej ahd_dump_card_state(ahd); 918 1.9 thorpej } 919 1.9 thorpej cmds_pending = ahd_inw(ahd, CMDS_PENDING); 920 1.9 thorpej if (cmds_pending > 0) 921 1.9 thorpej ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); 922 1.9 thorpej break; 923 1.9 thorpej } 924 1.1 fvdl case ENTERING_NONPACK: 925 1.1 fvdl { 926 1.1 fvdl struct scb *scb; 927 1.1 fvdl u_int scbid; 928 1.1 fvdl 929 1.1 fvdl AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 930 1.1 fvdl ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 931 1.1 fvdl scbid = ahd_get_scbptr(ahd); 932 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 933 1.1 fvdl if (scb == NULL) { 934 1.1 fvdl /* 935 1.1 fvdl * Somehow need to know if this 936 1.1 fvdl * is from a selection or reselection. 937 1.19 thorpej * From that, we can determine target 938 1.1 fvdl * ID so we at least have an I_T nexus. 939 1.1 fvdl */ 940 1.1 fvdl } else { 941 1.1 fvdl ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 942 1.1 fvdl ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 943 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS, 0x0); 944 1.1 fvdl } 945 1.1 fvdl if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 946 1.1 fvdl && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 947 1.1 fvdl /* 948 1.1 fvdl * Phase change after read stream with 949 1.1 fvdl * CRC error with P0 asserted on last 950 1.1 fvdl * packet. 951 1.1 fvdl */ 952 1.1 fvdl #ifdef AHD_DEBUG 953 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 954 1.1 fvdl printf("%s: Assuming LQIPHASE_NLQ with " 955 1.1 fvdl "P0 assertion\n", ahd_name(ahd)); 956 1.1 fvdl #endif 957 1.1 fvdl } 958 1.1 fvdl #ifdef AHD_DEBUG 959 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 960 1.1 fvdl printf("%s: Entering NONPACK\n", ahd_name(ahd)); 961 1.1 fvdl #endif 962 1.1 fvdl break; 963 1.1 fvdl } 964 1.1 fvdl case INVALID_SEQINT: 965 1.1 fvdl printf("%s: Invalid Sequencer interrupt occurred.\n", 966 1.1 fvdl ahd_name(ahd)); 967 1.1 fvdl ahd_dump_card_state(ahd); 968 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 969 1.1 fvdl break; 970 1.1 fvdl case STATUS_OVERRUN: 971 1.1 fvdl { 972 1.9 thorpej struct scb *scb; 973 1.9 thorpej u_int scbid; 974 1.9 thorpej 975 1.9 thorpej scbid = ahd_get_scbptr(ahd); 976 1.9 thorpej scb = ahd_lookup_scb(ahd, scbid); 977 1.9 thorpej if (scb != NULL) 978 1.9 thorpej ahd_print_path(ahd, scb); 979 1.9 thorpej else 980 1.9 thorpej printf("%s: ", ahd_name(ahd)); 981 1.9 thorpej printf("SCB %d Packetized Status Overrun", scbid); 982 1.1 fvdl ahd_dump_card_state(ahd); 983 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 984 1.1 fvdl break; 985 1.1 fvdl } 986 1.1 fvdl case CFG4ISTAT_INTR: 987 1.1 fvdl { 988 1.1 fvdl struct scb *scb; 989 1.1 fvdl u_int scbid; 990 1.1 fvdl 991 1.1 fvdl scbid = ahd_get_scbptr(ahd); 992 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 993 1.1 fvdl if (scb == NULL) { 994 1.1 fvdl ahd_dump_card_state(ahd); 995 1.1 fvdl printf("CFG4ISTAT: Free SCB %d referenced", scbid); 996 1.1 fvdl panic("For safety"); 997 1.1 fvdl } 998 1.1 fvdl ahd_outq(ahd, HADDR, scb->sense_busaddr); 999 1.1 fvdl ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1000 1.1 fvdl ahd_outb(ahd, HCNT + 2, 0); 1001 1.1 fvdl ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1002 1.1 fvdl ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1003 1.1 fvdl break; 1004 1.1 fvdl } 1005 1.1 fvdl case ILLEGAL_PHASE: 1006 1.1 fvdl { 1007 1.1 fvdl u_int bus_phase; 1008 1.1 fvdl 1009 1.1 fvdl bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1010 1.1 fvdl printf("%s: ILLEGAL_PHASE 0x%x\n", 1011 1.1 fvdl ahd_name(ahd), bus_phase); 1012 1.1 fvdl 1013 1.1 fvdl switch (bus_phase) { 1014 1.1 fvdl case P_DATAOUT: 1015 1.1 fvdl case P_DATAIN: 1016 1.1 fvdl case P_DATAOUT_DT: 1017 1.1 fvdl case P_DATAIN_DT: 1018 1.1 fvdl case P_MESGOUT: 1019 1.1 fvdl case P_STATUS: 1020 1.1 fvdl case P_MESGIN: 1021 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1022 1.1 fvdl printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1023 1.1 fvdl break; 1024 1.1 fvdl case P_COMMAND: 1025 1.1 fvdl { 1026 1.1 fvdl struct ahd_devinfo devinfo; 1027 1.1 fvdl struct scb *scb; 1028 1.46 christos #ifdef notdef 1029 1.1 fvdl struct ahd_initiator_tinfo *targ_info; 1030 1.1 fvdl struct ahd_tmode_tstate *tstate; 1031 1.46 christos #endif 1032 1.1 fvdl u_int scbid; 1033 1.1 fvdl 1034 1.1 fvdl /* 1035 1.1 fvdl * If a target takes us into the command phase 1036 1.1 fvdl * assume that it has been externally reset and 1037 1.1 fvdl * has thus lost our previous packetized negotiation 1038 1.1 fvdl * agreement. Since we have not sent an identify 1039 1.1 fvdl * message and may not have fully qualified the 1040 1.1 fvdl * connection, we change our command to TUR, assert 1041 1.1 fvdl * ATN and ABORT the task when we go to message in 1042 1.1 fvdl * phase. The OSM will see the REQUEUE_REQUEST 1043 1.1 fvdl * status and retry the command. 1044 1.1 fvdl */ 1045 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1046 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1047 1.1 fvdl if (scb == NULL) { 1048 1.1 fvdl printf("Invalid phase with no valid SCB. " 1049 1.1 fvdl "Resetting bus.\n"); 1050 1.1 fvdl ahd_reset_channel(ahd, 'A', 1051 1.1 fvdl /*Initiate Reset*/TRUE); 1052 1.1 fvdl break; 1053 1.1 fvdl } 1054 1.1 fvdl ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1055 1.1 fvdl SCB_GET_TARGET(ahd, scb), 1056 1.1 fvdl SCB_GET_LUN(scb), 1057 1.1 fvdl SCB_GET_CHANNEL(ahd, scb), 1058 1.1 fvdl ROLE_INITIATOR); 1059 1.46 christos #ifdef notdef 1060 1.1 fvdl targ_info = ahd_fetch_transinfo(ahd, 1061 1.1 fvdl devinfo.channel, 1062 1.1 fvdl devinfo.our_scsiid, 1063 1.1 fvdl devinfo.target, 1064 1.1 fvdl &tstate); 1065 1.46 christos #endif 1066 1.1 fvdl ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1067 1.1 fvdl AHD_TRANS_ACTIVE, /*paused*/TRUE); 1068 1.1 fvdl ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1069 1.1 fvdl /*offset*/0, /*ppr_options*/0, 1070 1.1 fvdl AHD_TRANS_ACTIVE, /*paused*/TRUE); 1071 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE, 0); 1072 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE+1, 0); 1073 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE+2, 0); 1074 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE+3, 0); 1075 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE+4, 0); 1076 1.1 fvdl ahd_outb(ahd, SCB_CDB_STORE+5, 0); 1077 1.1 fvdl ahd_outb(ahd, SCB_CDB_LEN, 6); 1078 1.1 fvdl scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 1079 1.1 fvdl scb->hscb->control |= MK_MESSAGE; 1080 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 1081 1.1 fvdl ahd_outb(ahd, MSG_OUT, HOST_MSG); 1082 1.1 fvdl ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1083 1.1 fvdl /* 1084 1.1 fvdl * The lun is 0, regardless of the SCB's lun 1085 1.1 fvdl * as we have not sent an identify message. 1086 1.1 fvdl */ 1087 1.1 fvdl ahd_outb(ahd, SAVED_LUN, 0); 1088 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS, 0); 1089 1.1 fvdl ahd_assert_atn(ahd); 1090 1.1 fvdl scb->flags &= ~(SCB_PACKETIZED); 1091 1.1 fvdl scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 1092 1.1 fvdl ahd_freeze_devq(ahd, scb); 1093 1.1 fvdl ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1094 1.1 fvdl ahd_freeze_scb(scb); 1095 1.1 fvdl 1096 1.1 fvdl /* 1097 1.1 fvdl * Allow the sequencer to continue with 1098 1.1 fvdl * non-pack processing. 1099 1.1 fvdl */ 1100 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1101 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1102 1.1 fvdl if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1103 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, 0); 1104 1.1 fvdl } 1105 1.1 fvdl #ifdef AHD_DEBUG 1106 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1107 1.1 fvdl ahd_print_path(ahd, scb); 1108 1.1 fvdl printf("Unexpected command phase from " 1109 1.1 fvdl "packetized target\n"); 1110 1.1 fvdl } 1111 1.1 fvdl #endif 1112 1.1 fvdl break; 1113 1.1 fvdl } 1114 1.1 fvdl } 1115 1.1 fvdl break; 1116 1.1 fvdl } 1117 1.1 fvdl case CFG4OVERRUN: 1118 1.1 fvdl { 1119 1.1 fvdl struct scb *scb; 1120 1.1 fvdl u_int scb_index; 1121 1.30 perry 1122 1.1 fvdl #ifdef AHD_DEBUG 1123 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1124 1.1 fvdl printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 1125 1.1 fvdl ahd_inb(ahd, MODE_PTR)); 1126 1.1 fvdl } 1127 1.1 fvdl #endif 1128 1.1 fvdl scb_index = ahd_get_scbptr(ahd); 1129 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 1130 1.1 fvdl if (scb == NULL) { 1131 1.1 fvdl /* 1132 1.1 fvdl * Attempt to transfer to an SCB that is 1133 1.1 fvdl * not outstanding. 1134 1.1 fvdl */ 1135 1.1 fvdl ahd_assert_atn(ahd); 1136 1.1 fvdl ahd_outb(ahd, MSG_OUT, HOST_MSG); 1137 1.1 fvdl ahd->msgout_buf[0] = MSG_ABORT_TASK; 1138 1.1 fvdl ahd->msgout_len = 1; 1139 1.1 fvdl ahd->msgout_index = 0; 1140 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1141 1.1 fvdl /* 1142 1.1 fvdl * Clear status received flag to prevent any 1143 1.1 fvdl * attempt to complete this bogus SCB. 1144 1.1 fvdl */ 1145 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, 1146 1.21 thorpej ahd_inb_scbram(ahd, SCB_CONTROL) 1147 1.21 thorpej & ~STATUS_RCVD); 1148 1.1 fvdl } 1149 1.1 fvdl break; 1150 1.1 fvdl } 1151 1.1 fvdl case DUMP_CARD_STATE: 1152 1.1 fvdl { 1153 1.1 fvdl ahd_dump_card_state(ahd); 1154 1.1 fvdl break; 1155 1.1 fvdl } 1156 1.1 fvdl case PDATA_REINIT: 1157 1.1 fvdl { 1158 1.1 fvdl #ifdef AHD_DEBUG 1159 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1160 1.1 fvdl printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 1161 1.1 fvdl "SG_CACHE_SHADOW = 0x%x\n", 1162 1.1 fvdl ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 1163 1.1 fvdl ahd_inb(ahd, SG_CACHE_SHADOW)); 1164 1.1 fvdl } 1165 1.1 fvdl #endif 1166 1.1 fvdl ahd_reinitialize_dataptrs(ahd); 1167 1.1 fvdl break; 1168 1.1 fvdl } 1169 1.1 fvdl case HOST_MSG_LOOP: 1170 1.1 fvdl { 1171 1.1 fvdl struct ahd_devinfo devinfo; 1172 1.1 fvdl 1173 1.1 fvdl /* 1174 1.1 fvdl * The sequencer has encountered a message phase 1175 1.1 fvdl * that requires host assistance for completion. 1176 1.1 fvdl * While handling the message phase(s), we will be 1177 1.1 fvdl * notified by the sequencer after each byte is 1178 1.26 wiz * transferred so we can track bus phase changes. 1179 1.1 fvdl * 1180 1.1 fvdl * If this is the first time we've seen a HOST_MSG_LOOP 1181 1.1 fvdl * interrupt, initialize the state of the host message 1182 1.1 fvdl * loop. 1183 1.1 fvdl */ 1184 1.1 fvdl ahd_fetch_devinfo(ahd, &devinfo); 1185 1.1 fvdl if (ahd->msg_type == MSG_TYPE_NONE) { 1186 1.1 fvdl struct scb *scb; 1187 1.1 fvdl u_int scb_index; 1188 1.1 fvdl u_int bus_phase; 1189 1.1 fvdl 1190 1.1 fvdl bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1191 1.1 fvdl if (bus_phase != P_MESGIN 1192 1.1 fvdl && bus_phase != P_MESGOUT) { 1193 1.1 fvdl printf("ahd_intr: HOST_MSG_LOOP bad " 1194 1.1 fvdl "phase 0x%x\n", bus_phase); 1195 1.1 fvdl /* 1196 1.1 fvdl * Probably transitioned to bus free before 1197 1.1 fvdl * we got here. Just punt the message. 1198 1.1 fvdl */ 1199 1.1 fvdl ahd_dump_card_state(ahd); 1200 1.1 fvdl ahd_clear_intstat(ahd); 1201 1.1 fvdl ahd_restart(ahd); 1202 1.1 fvdl return; 1203 1.1 fvdl } 1204 1.1 fvdl 1205 1.1 fvdl scb_index = ahd_get_scbptr(ahd); 1206 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 1207 1.1 fvdl if (devinfo.role == ROLE_INITIATOR) { 1208 1.1 fvdl if (bus_phase == P_MESGOUT) 1209 1.1 fvdl ahd_setup_initiator_msgout(ahd, 1210 1.1 fvdl &devinfo, 1211 1.1 fvdl scb); 1212 1.1 fvdl else { 1213 1.1 fvdl ahd->msg_type = 1214 1.1 fvdl MSG_TYPE_INITIATOR_MSGIN; 1215 1.1 fvdl ahd->msgin_index = 0; 1216 1.1 fvdl } 1217 1.1 fvdl } 1218 1.1 fvdl #if AHD_TARGET_MODE 1219 1.1 fvdl else { 1220 1.1 fvdl if (bus_phase == P_MESGOUT) { 1221 1.1 fvdl ahd->msg_type = 1222 1.1 fvdl MSG_TYPE_TARGET_MSGOUT; 1223 1.1 fvdl ahd->msgin_index = 0; 1224 1.1 fvdl } 1225 1.30 perry else 1226 1.1 fvdl ahd_setup_target_msgin(ahd, 1227 1.1 fvdl &devinfo, 1228 1.1 fvdl scb); 1229 1.1 fvdl } 1230 1.1 fvdl #endif 1231 1.1 fvdl } 1232 1.1 fvdl 1233 1.1 fvdl ahd_handle_message_phase(ahd); 1234 1.1 fvdl break; 1235 1.1 fvdl } 1236 1.1 fvdl case NO_MATCH: 1237 1.1 fvdl { 1238 1.1 fvdl /* Ensure we don't leave the selection hardware on */ 1239 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1240 1.1 fvdl ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1241 1.1 fvdl 1242 1.1 fvdl printf("%s:%c:%d: no active SCB for reconnecting " 1243 1.1 fvdl "target - issuing BUS DEVICE RESET\n", 1244 1.1 fvdl ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 1245 1.1 fvdl printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1246 1.1 fvdl "REG0 == 0x%x ACCUM = 0x%x\n", 1247 1.1 fvdl ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 1248 1.1 fvdl ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 1249 1.1 fvdl printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1250 1.1 fvdl "SINDEX == 0x%x\n", 1251 1.1 fvdl ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 1252 1.1 fvdl ahd_find_busy_tcl(ahd, 1253 1.1 fvdl BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 1254 1.1 fvdl ahd_inb(ahd, SAVED_LUN))), 1255 1.1 fvdl ahd_inw(ahd, SINDEX)); 1256 1.1 fvdl printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1257 1.1 fvdl "SCB_CONTROL == 0x%x\n", 1258 1.1 fvdl ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 1259 1.1 fvdl ahd_inb_scbram(ahd, SCB_LUN), 1260 1.1 fvdl ahd_inb_scbram(ahd, SCB_CONTROL)); 1261 1.1 fvdl printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 1262 1.1 fvdl ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 1263 1.1 fvdl printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 1264 1.1 fvdl printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 1265 1.1 fvdl ahd_dump_card_state(ahd); 1266 1.1 fvdl ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 1267 1.1 fvdl ahd->msgout_len = 1; 1268 1.1 fvdl ahd->msgout_index = 0; 1269 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1270 1.1 fvdl ahd_outb(ahd, MSG_OUT, HOST_MSG); 1271 1.1 fvdl ahd_assert_atn(ahd); 1272 1.1 fvdl break; 1273 1.1 fvdl } 1274 1.1 fvdl case PROTO_VIOLATION: 1275 1.1 fvdl { 1276 1.1 fvdl ahd_handle_proto_violation(ahd); 1277 1.1 fvdl break; 1278 1.1 fvdl } 1279 1.1 fvdl case IGN_WIDE_RES: 1280 1.1 fvdl { 1281 1.1 fvdl struct ahd_devinfo devinfo; 1282 1.1 fvdl 1283 1.1 fvdl ahd_fetch_devinfo(ahd, &devinfo); 1284 1.1 fvdl ahd_handle_ign_wide_residue(ahd, &devinfo); 1285 1.1 fvdl break; 1286 1.1 fvdl } 1287 1.1 fvdl case BAD_PHASE: 1288 1.1 fvdl { 1289 1.1 fvdl u_int lastphase; 1290 1.1 fvdl 1291 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 1292 1.1 fvdl printf("%s:%c:%d: unknown scsi bus phase %x, " 1293 1.1 fvdl "lastphase = 0x%x. Attempting to continue\n", 1294 1.1 fvdl ahd_name(ahd), 'A', 1295 1.1 fvdl SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1296 1.1 fvdl lastphase, ahd_inb(ahd, SCSISIGI)); 1297 1.1 fvdl break; 1298 1.1 fvdl } 1299 1.1 fvdl case MISSED_BUSFREE: 1300 1.1 fvdl { 1301 1.1 fvdl u_int lastphase; 1302 1.1 fvdl 1303 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 1304 1.1 fvdl printf("%s:%c:%d: Missed busfree. " 1305 1.1 fvdl "Lastphase = 0x%x, Curphase = 0x%x\n", 1306 1.1 fvdl ahd_name(ahd), 'A', 1307 1.1 fvdl SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1308 1.1 fvdl lastphase, ahd_inb(ahd, SCSISIGI)); 1309 1.1 fvdl ahd_restart(ahd); 1310 1.1 fvdl return; 1311 1.1 fvdl } 1312 1.1 fvdl case DATA_OVERRUN: 1313 1.1 fvdl { 1314 1.1 fvdl /* 1315 1.1 fvdl * When the sequencer detects an overrun, it 1316 1.1 fvdl * places the controller in "BITBUCKET" mode 1317 1.1 fvdl * and allows the target to complete its transfer. 1318 1.1 fvdl * Unfortunately, none of the counters get updated 1319 1.1 fvdl * when the controller is in this mode, so we have 1320 1.1 fvdl * no way of knowing how large the overrun was. 1321 1.1 fvdl */ 1322 1.1 fvdl struct scb *scb; 1323 1.1 fvdl u_int scbindex; 1324 1.1 fvdl #ifdef AHD_DEBUG 1325 1.1 fvdl u_int lastphase; 1326 1.1 fvdl #endif 1327 1.1 fvdl 1328 1.1 fvdl scbindex = ahd_get_scbptr(ahd); 1329 1.1 fvdl scb = ahd_lookup_scb(ahd, scbindex); 1330 1.1 fvdl #ifdef AHD_DEBUG 1331 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 1332 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1333 1.1 fvdl ahd_print_path(ahd, scb); 1334 1.1 fvdl printf("data overrun detected %s. Tag == 0x%x.\n", 1335 1.1 fvdl ahd_lookup_phase_entry(lastphase)->phasemsg, 1336 1.1 fvdl SCB_GET_TAG(scb)); 1337 1.1 fvdl ahd_print_path(ahd, scb); 1338 1.1 fvdl printf("%s seen Data Phase. Length = %ld. " 1339 1.1 fvdl "NumSGs = %d.\n", 1340 1.1 fvdl ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1341 1.1 fvdl ? "Have" : "Haven't", 1342 1.1 fvdl ahd_get_transfer_length(scb), scb->sg_count); 1343 1.1 fvdl ahd_dump_sglist(scb); 1344 1.1 fvdl } 1345 1.1 fvdl #endif 1346 1.1 fvdl 1347 1.1 fvdl /* 1348 1.1 fvdl * Set this and it will take effect when the 1349 1.1 fvdl * target does a command complete. 1350 1.1 fvdl */ 1351 1.1 fvdl ahd_freeze_devq(ahd, scb); 1352 1.1 fvdl ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1353 1.1 fvdl ahd_freeze_scb(scb); 1354 1.1 fvdl break; 1355 1.1 fvdl } 1356 1.1 fvdl case MKMSG_FAILED: 1357 1.1 fvdl { 1358 1.1 fvdl struct ahd_devinfo devinfo; 1359 1.1 fvdl struct scb *scb; 1360 1.1 fvdl u_int scbid; 1361 1.1 fvdl 1362 1.1 fvdl ahd_fetch_devinfo(ahd, &devinfo); 1363 1.1 fvdl printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1364 1.1 fvdl ahd_name(ahd), devinfo.channel, devinfo.target, 1365 1.1 fvdl devinfo.lun); 1366 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1367 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1368 1.1 fvdl if (scb != NULL 1369 1.1 fvdl && (scb->flags & SCB_RECOVERY_SCB) != 0) 1370 1.1 fvdl /* 1371 1.1 fvdl * Ensure that we didn't put a second instance of this 1372 1.1 fvdl * SCB into the QINFIFO. 1373 1.1 fvdl */ 1374 1.1 fvdl ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1375 1.1 fvdl SCB_GET_CHANNEL(ahd, scb), 1376 1.1 fvdl SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1377 1.1 fvdl ROLE_INITIATOR, /*status*/0, 1378 1.1 fvdl SEARCH_REMOVE); 1379 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, 1380 1.21 thorpej ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1381 1.1 fvdl break; 1382 1.1 fvdl } 1383 1.1 fvdl case TASKMGMT_FUNC_COMPLETE: 1384 1.1 fvdl { 1385 1.1 fvdl u_int scbid; 1386 1.1 fvdl struct scb *scb; 1387 1.1 fvdl 1388 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1389 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1390 1.1 fvdl if (scb != NULL) { 1391 1.1 fvdl u_int lun; 1392 1.1 fvdl u_int tag; 1393 1.1 fvdl cam_status error; 1394 1.1 fvdl 1395 1.1 fvdl ahd_print_path(ahd, scb); 1396 1.1 fvdl printf("Task Management Func 0x%x Complete\n", 1397 1.1 fvdl scb->hscb->task_management); 1398 1.1 fvdl lun = CAM_LUN_WILDCARD; 1399 1.1 fvdl tag = SCB_LIST_NULL; 1400 1.1 fvdl 1401 1.1 fvdl switch (scb->hscb->task_management) { 1402 1.1 fvdl case SIU_TASKMGMT_ABORT_TASK: 1403 1.9 thorpej tag = SCB_GET_TAG(scb); 1404 1.51 mrg /* FALLTHROUGH */ 1405 1.1 fvdl case SIU_TASKMGMT_ABORT_TASK_SET: 1406 1.1 fvdl case SIU_TASKMGMT_CLEAR_TASK_SET: 1407 1.1 fvdl lun = scb->hscb->lun; 1408 1.1 fvdl error = CAM_REQ_ABORTED; 1409 1.1 fvdl ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1410 1.1 fvdl 'A', lun, tag, ROLE_INITIATOR, 1411 1.1 fvdl error); 1412 1.1 fvdl break; 1413 1.1 fvdl case SIU_TASKMGMT_LUN_RESET: 1414 1.1 fvdl lun = scb->hscb->lun; 1415 1.51 mrg /* FALLTHROUGH */ 1416 1.1 fvdl case SIU_TASKMGMT_TARGET_RESET: 1417 1.1 fvdl { 1418 1.1 fvdl struct ahd_devinfo devinfo; 1419 1.1 fvdl 1420 1.1 fvdl ahd_scb_devinfo(ahd, &devinfo, scb); 1421 1.1 fvdl error = CAM_BDR_SENT; 1422 1.1 fvdl ahd_handle_devreset(ahd, &devinfo, lun, 1423 1.1 fvdl CAM_BDR_SENT, 1424 1.1 fvdl lun != CAM_LUN_WILDCARD 1425 1.1 fvdl ? "Lun Reset" 1426 1.1 fvdl : "Target Reset", 1427 1.1 fvdl /*verbose_level*/0); 1428 1.1 fvdl break; 1429 1.1 fvdl } 1430 1.1 fvdl default: 1431 1.1 fvdl panic("Unexpected TaskMgmt Func\n"); 1432 1.1 fvdl break; 1433 1.1 fvdl } 1434 1.1 fvdl } 1435 1.1 fvdl break; 1436 1.1 fvdl } 1437 1.1 fvdl case TASKMGMT_CMD_CMPLT_OKAY: 1438 1.1 fvdl { 1439 1.1 fvdl u_int scbid; 1440 1.1 fvdl struct scb *scb; 1441 1.1 fvdl 1442 1.1 fvdl /* 1443 1.1 fvdl * An ABORT TASK TMF failed to be delivered before 1444 1.1 fvdl * the targeted command completed normally. 1445 1.1 fvdl */ 1446 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1447 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1448 1.1 fvdl if (scb != NULL) { 1449 1.1 fvdl /* 1450 1.1 fvdl * Remove the second instance of this SCB from 1451 1.1 fvdl * the QINFIFO if it is still there. 1452 1.43 tsutsui */ 1453 1.1 fvdl ahd_print_path(ahd, scb); 1454 1.1 fvdl printf("SCB completes before TMF\n"); 1455 1.1 fvdl /* 1456 1.1 fvdl * Handle losing the race. Wait until any 1457 1.1 fvdl * current selection completes. We will then 1458 1.1 fvdl * set the TMF back to zero in this SCB so that 1459 1.1 fvdl * the sequencer doesn't bother to issue another 1460 1.1 fvdl * sequencer interrupt for its completion. 1461 1.1 fvdl */ 1462 1.1 fvdl while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1463 1.1 fvdl && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1464 1.1 fvdl && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1465 1.1 fvdl ; 1466 1.1 fvdl ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1467 1.1 fvdl ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1468 1.30 perry SCB_GET_CHANNEL(ahd, scb), 1469 1.9 thorpej SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1470 1.30 perry ROLE_INITIATOR, /*status*/0, 1471 1.1 fvdl SEARCH_REMOVE); 1472 1.1 fvdl } 1473 1.1 fvdl break; 1474 1.1 fvdl } 1475 1.1 fvdl case TRACEPOINT0: 1476 1.1 fvdl case TRACEPOINT1: 1477 1.1 fvdl case TRACEPOINT2: 1478 1.1 fvdl case TRACEPOINT3: 1479 1.1 fvdl printf("%s: Tracepoint %d\n", ahd_name(ahd), 1480 1.1 fvdl seqintcode - TRACEPOINT0); 1481 1.1 fvdl break; 1482 1.1 fvdl case NO_SEQINT: 1483 1.1 fvdl break; 1484 1.1 fvdl case SAW_HWERR: 1485 1.1 fvdl ahd_handle_hwerrint(ahd); 1486 1.1 fvdl break; 1487 1.1 fvdl default: 1488 1.1 fvdl printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1489 1.1 fvdl seqintcode); 1490 1.1 fvdl break; 1491 1.1 fvdl } 1492 1.1 fvdl /* 1493 1.1 fvdl * The sequencer is paused immediately on 1494 1.1 fvdl * a SEQINT, so we should restart it when 1495 1.1 fvdl * we're done. 1496 1.1 fvdl */ 1497 1.1 fvdl ahd_unpause(ahd); 1498 1.1 fvdl } 1499 1.1 fvdl 1500 1.1 fvdl void 1501 1.36 christos ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1502 1.1 fvdl { 1503 1.1 fvdl struct scb *scb; 1504 1.1 fvdl u_int status0; 1505 1.1 fvdl u_int status3; 1506 1.1 fvdl u_int status; 1507 1.1 fvdl u_int lqistat1; 1508 1.1 fvdl u_int lqostat0; 1509 1.1 fvdl u_int scbid; 1510 1.1 fvdl u_int busfreetime; 1511 1.1 fvdl 1512 1.1 fvdl ahd_update_modes(ahd); 1513 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1514 1.1 fvdl 1515 1.1 fvdl status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1516 1.1 fvdl status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1517 1.1 fvdl status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1518 1.1 fvdl lqistat1 = ahd_inb(ahd, LQISTAT1); 1519 1.1 fvdl lqostat0 = ahd_inb(ahd, LQOSTAT0); 1520 1.1 fvdl busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1521 1.1 fvdl if ((status0 & (SELDI|SELDO)) != 0) { 1522 1.1 fvdl u_int simode0; 1523 1.1 fvdl 1524 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1525 1.1 fvdl simode0 = ahd_inb(ahd, SIMODE0); 1526 1.1 fvdl status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1527 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1528 1.1 fvdl } 1529 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1530 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1531 1.1 fvdl if (scb != NULL 1532 1.1 fvdl && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1533 1.1 fvdl scb = NULL; 1534 1.1 fvdl 1535 1.1 fvdl /* Make sure the sequencer is in a safe location. */ 1536 1.1 fvdl ahd_clear_critical_section(ahd); 1537 1.1 fvdl 1538 1.1 fvdl if ((status0 & IOERR) != 0) { 1539 1.1 fvdl u_int now_lvd; 1540 1.1 fvdl 1541 1.1 fvdl now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1542 1.1 fvdl printf("%s: Transceiver State Has Changed to %s mode\n", 1543 1.1 fvdl ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1544 1.1 fvdl ahd_outb(ahd, CLRSINT0, CLRIOERR); 1545 1.1 fvdl /* 1546 1.1 fvdl * A change in I/O mode is equivalent to a bus reset. 1547 1.1 fvdl */ 1548 1.9 thorpej ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1549 1.1 fvdl ahd_pause(ahd); 1550 1.1 fvdl ahd_setup_iocell_workaround(ahd); 1551 1.1 fvdl ahd_unpause(ahd); 1552 1.1 fvdl } else if ((status0 & OVERRUN) != 0) { 1553 1.1 fvdl printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1554 1.1 fvdl ahd_name(ahd)); 1555 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1556 1.1 fvdl } else if ((status & SCSIRSTI) != 0) { 1557 1.1 fvdl printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1558 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1559 1.1 fvdl } else if ((status & SCSIPERR) != 0) { 1560 1.1 fvdl ahd_handle_transmission_error(ahd); 1561 1.1 fvdl } else if (lqostat0 != 0) { 1562 1.1 fvdl printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1563 1.1 fvdl ahd_outb(ahd, CLRLQOINT0, lqostat0); 1564 1.1 fvdl if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1565 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, 0); 1566 1.1 fvdl } 1567 1.1 fvdl } else if ((status & SELTO) != 0) { 1568 1.31 christos u_int scbid1; 1569 1.1 fvdl 1570 1.1 fvdl /* Stop the selection */ 1571 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 1572 1.1 fvdl 1573 1.1 fvdl /* No more pending messages */ 1574 1.1 fvdl ahd_clear_msg_state(ahd); 1575 1.1 fvdl 1576 1.1 fvdl /* Clear interrupt state */ 1577 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1578 1.1 fvdl 1579 1.1 fvdl /* 1580 1.1 fvdl * Although the driver does not care about the 1581 1.1 fvdl * 'Selection in Progress' status bit, the busy 1582 1.53 msaitoh * LED does. SELINGO is only cleared by a successful 1583 1.1 fvdl * selection, so we must manually clear it to insure 1584 1.1 fvdl * the LED turns off just incase no future successful 1585 1.1 fvdl * selections occur (e.g. no devices on the bus). 1586 1.1 fvdl */ 1587 1.1 fvdl ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1588 1.1 fvdl 1589 1.31 christos scbid1 = ahd_inw(ahd, WAITING_TID_HEAD); 1590 1.31 christos scb = ahd_lookup_scb(ahd, scbid1); 1591 1.1 fvdl if (scb == NULL) { 1592 1.1 fvdl printf("%s: ahd_intr - referenced scb not " 1593 1.1 fvdl "valid during SELTO scb(0x%x)\n", 1594 1.31 christos ahd_name(ahd), scbid1); 1595 1.1 fvdl ahd_dump_card_state(ahd); 1596 1.1 fvdl } else { 1597 1.1 fvdl struct ahd_devinfo devinfo; 1598 1.1 fvdl #ifdef AHD_DEBUG 1599 1.1 fvdl if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1600 1.1 fvdl ahd_print_path(ahd, scb); 1601 1.1 fvdl printf("Saw Selection Timeout for SCB 0x%x\n", 1602 1.31 christos scbid1); 1603 1.1 fvdl } 1604 1.1 fvdl #endif 1605 1.1 fvdl /* 1606 1.1 fvdl * Force a renegotiation with this target just in 1607 1.1 fvdl * case the cable was pulled and will later be 1608 1.1 fvdl * re-attached. The target may forget its negotiation 1609 1.1 fvdl * settings with us should it attempt to reselect 1610 1.1 fvdl * during the interruption. The target will not issue 1611 1.1 fvdl * a unit attention in this case, so we must always 1612 1.1 fvdl * renegotiate. 1613 1.1 fvdl */ 1614 1.1 fvdl ahd_scb_devinfo(ahd, &devinfo, scb); 1615 1.1 fvdl ahd_force_renegotiation(ahd, &devinfo); 1616 1.1 fvdl ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1617 1.1 fvdl ahd_freeze_devq(ahd, scb); 1618 1.1 fvdl } 1619 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 1620 1.1 fvdl ahd_iocell_first_selection(ahd); 1621 1.1 fvdl ahd_unpause(ahd); 1622 1.1 fvdl } else if ((status0 & (SELDI|SELDO)) != 0) { 1623 1.1 fvdl ahd_iocell_first_selection(ahd); 1624 1.1 fvdl ahd_unpause(ahd); 1625 1.1 fvdl } else if (status3 != 0) { 1626 1.1 fvdl printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1627 1.1 fvdl ahd_name(ahd), status3); 1628 1.1 fvdl ahd_outb(ahd, CLRSINT3, status3); 1629 1.1 fvdl } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1630 1.1 fvdl ahd_handle_lqiphase_error(ahd, lqistat1); 1631 1.1 fvdl } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1632 1.1 fvdl /* 1633 1.1 fvdl * This status can be delayed during some 1634 1.1 fvdl * streaming operations. The SCSIPHASE 1635 1.1 fvdl * handler has already dealt with this case 1636 1.1 fvdl * so just clear the error. 1637 1.1 fvdl */ 1638 1.1 fvdl ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1639 1.1 fvdl } else if ((status & BUSFREE) != 0) { 1640 1.1 fvdl u_int lqostat1; 1641 1.1 fvdl int restart; 1642 1.1 fvdl int clear_fifo; 1643 1.1 fvdl int packetized; 1644 1.1 fvdl u_int mode; 1645 1.1 fvdl 1646 1.1 fvdl /* 1647 1.1 fvdl * Clear our selection hardware as soon as possible. 1648 1.1 fvdl * We may have an entry in the waiting Q for this target, 1649 1.1 fvdl * that is affected by this busfree and we don't want to 1650 1.1 fvdl * go about selecting the target while we handle the event. 1651 1.1 fvdl */ 1652 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 1653 1.1 fvdl 1654 1.1 fvdl /* 1655 1.1 fvdl * Determine what we were up to at the time of 1656 1.1 fvdl * the busfree. 1657 1.1 fvdl */ 1658 1.1 fvdl mode = AHD_MODE_SCSI; 1659 1.1 fvdl busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1660 1.1 fvdl lqostat1 = ahd_inb(ahd, LQOSTAT1); 1661 1.1 fvdl switch (busfreetime) { 1662 1.1 fvdl case BUSFREE_DFF0: 1663 1.1 fvdl case BUSFREE_DFF1: 1664 1.1 fvdl { 1665 1.31 christos u_int scbid1; 1666 1.31 christos struct scb *scb1; 1667 1.1 fvdl 1668 1.1 fvdl mode = busfreetime == BUSFREE_DFF0 1669 1.1 fvdl ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1670 1.1 fvdl ahd_set_modes(ahd, mode, mode); 1671 1.31 christos scbid1 = ahd_get_scbptr(ahd); 1672 1.31 christos scb1 = ahd_lookup_scb(ahd, scbid1); 1673 1.31 christos if (scb1 == NULL) { 1674 1.9 thorpej printf("%s: Invalid SCB %d in DFF%d " 1675 1.1 fvdl "during unexpected busfree\n", 1676 1.31 christos ahd_name(ahd), scbid1, mode); 1677 1.1 fvdl packetized = 0; 1678 1.1 fvdl } else 1679 1.44 tsutsui packetized = 1680 1.44 tsutsui (scb1->flags & SCB_PACKETIZED) != 0; 1681 1.1 fvdl clear_fifo = 1; 1682 1.1 fvdl break; 1683 1.1 fvdl } 1684 1.1 fvdl case BUSFREE_LQO: 1685 1.1 fvdl clear_fifo = 0; 1686 1.1 fvdl packetized = 1; 1687 1.1 fvdl break; 1688 1.1 fvdl default: 1689 1.1 fvdl clear_fifo = 0; 1690 1.1 fvdl packetized = (lqostat1 & LQOBUSFREE) != 0; 1691 1.1 fvdl if (!packetized 1692 1.1 fvdl && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1693 1.1 fvdl packetized = 1; 1694 1.1 fvdl break; 1695 1.1 fvdl } 1696 1.1 fvdl 1697 1.1 fvdl #ifdef AHD_DEBUG 1698 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 1699 1.1 fvdl printf("Saw Busfree. Busfreetime = 0x%x.\n", 1700 1.1 fvdl busfreetime); 1701 1.1 fvdl #endif 1702 1.1 fvdl /* 1703 1.1 fvdl * Busfrees that occur in non-packetized phases are 1704 1.1 fvdl * handled by the nonpkt_busfree handler. 1705 1.1 fvdl */ 1706 1.1 fvdl if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1707 1.1 fvdl restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1708 1.1 fvdl } else { 1709 1.1 fvdl packetized = 0; 1710 1.1 fvdl restart = ahd_handle_nonpkt_busfree(ahd); 1711 1.1 fvdl } 1712 1.1 fvdl /* 1713 1.1 fvdl * Clear the busfree interrupt status. The setting of 1714 1.1 fvdl * the interrupt is a pulse, so in a perfect world, we 1715 1.1 fvdl * would not need to muck with the ENBUSFREE logic. This 1716 1.1 fvdl * would ensure that if the bus moves on to another 1717 1.1 fvdl * connection, busfree protection is still in force. If 1718 1.1 fvdl * BUSFREEREV is broken, however, we must manually clear 1719 1.1 fvdl * the ENBUSFREE if the busfree occurred during a non-pack 1720 1.1 fvdl * connection so that we don't get false positives during 1721 1.1 fvdl * future, packetized, connections. 1722 1.1 fvdl */ 1723 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1724 1.1 fvdl if (packetized == 0 1725 1.1 fvdl && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1726 1.1 fvdl ahd_outb(ahd, SIMODE1, 1727 1.1 fvdl ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1728 1.1 fvdl 1729 1.1 fvdl if (clear_fifo) 1730 1.1 fvdl ahd_clear_fifo(ahd, mode); 1731 1.1 fvdl 1732 1.1 fvdl ahd_clear_msg_state(ahd); 1733 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 1734 1.1 fvdl if (restart) { 1735 1.1 fvdl ahd_restart(ahd); 1736 1.1 fvdl } else { 1737 1.1 fvdl ahd_unpause(ahd); 1738 1.1 fvdl } 1739 1.1 fvdl } else { 1740 1.1 fvdl printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1741 1.1 fvdl ahd_name(ahd), status); 1742 1.1 fvdl ahd_dump_card_state(ahd); 1743 1.1 fvdl ahd_clear_intstat(ahd); 1744 1.1 fvdl ahd_unpause(ahd); 1745 1.1 fvdl } 1746 1.1 fvdl } 1747 1.1 fvdl 1748 1.1 fvdl static void 1749 1.1 fvdl ahd_handle_transmission_error(struct ahd_softc *ahd) 1750 1.1 fvdl { 1751 1.1 fvdl struct scb *scb; 1752 1.1 fvdl u_int scbid; 1753 1.1 fvdl u_int lqistat1; 1754 1.1 fvdl u_int msg_out; 1755 1.1 fvdl u_int curphase; 1756 1.1 fvdl u_int lastphase; 1757 1.1 fvdl u_int perrdiag; 1758 1.1 fvdl u_int cur_col; 1759 1.1 fvdl int silent; 1760 1.1 fvdl 1761 1.1 fvdl scb = NULL; 1762 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1763 1.1 fvdl lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1764 1.46 christos (void)ahd_inb(ahd, LQISTAT2); 1765 1.1 fvdl if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1766 1.1 fvdl && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1767 1.1 fvdl u_int lqistate; 1768 1.1 fvdl 1769 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1770 1.1 fvdl lqistate = ahd_inb(ahd, LQISTATE); 1771 1.1 fvdl if ((lqistate >= 0x1E && lqistate <= 0x24) 1772 1.1 fvdl || (lqistate == 0x29)) { 1773 1.1 fvdl #ifdef AHD_DEBUG 1774 1.1 fvdl if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1775 1.1 fvdl printf("%s: NLQCRC found via LQISTATE\n", 1776 1.1 fvdl ahd_name(ahd)); 1777 1.1 fvdl } 1778 1.1 fvdl #endif 1779 1.1 fvdl lqistat1 |= LQICRCI_NLQ; 1780 1.1 fvdl } 1781 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1782 1.1 fvdl } 1783 1.1 fvdl 1784 1.1 fvdl ahd_outb(ahd, CLRLQIINT1, lqistat1); 1785 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 1786 1.1 fvdl curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1787 1.1 fvdl perrdiag = ahd_inb(ahd, PERRDIAG); 1788 1.1 fvdl msg_out = MSG_INITIATOR_DET_ERR; 1789 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1790 1.30 perry 1791 1.1 fvdl /* 1792 1.1 fvdl * Try to find the SCB associated with this error. 1793 1.1 fvdl */ 1794 1.1 fvdl silent = FALSE; 1795 1.1 fvdl if (lqistat1 == 0 1796 1.1 fvdl || (lqistat1 & LQICRCI_NLQ) != 0) { 1797 1.43 tsutsui if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1798 1.1 fvdl ahd_set_active_fifo(ahd); 1799 1.1 fvdl scbid = ahd_get_scbptr(ahd); 1800 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 1801 1.1 fvdl if (scb != NULL && SCB_IS_SILENT(scb)) 1802 1.1 fvdl silent = TRUE; 1803 1.1 fvdl } 1804 1.1 fvdl 1805 1.1 fvdl cur_col = 0; 1806 1.1 fvdl if (silent == FALSE) { 1807 1.1 fvdl printf("%s: Transmission error detected\n", ahd_name(ahd)); 1808 1.1 fvdl ahd_lqistat1_print(lqistat1, &cur_col, 50); 1809 1.1 fvdl ahd_lastphase_print(lastphase, &cur_col, 50); 1810 1.1 fvdl ahd_scsisigi_print(curphase, &cur_col, 50); 1811 1.1 fvdl ahd_perrdiag_print(perrdiag, &cur_col, 50); 1812 1.1 fvdl printf("\n"); 1813 1.1 fvdl ahd_dump_card_state(ahd); 1814 1.1 fvdl } 1815 1.1 fvdl 1816 1.1 fvdl if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1817 1.1 fvdl if (silent == FALSE) { 1818 1.1 fvdl printf("%s: Gross protocol error during incoming " 1819 1.1 fvdl "packet. lqistat1 == 0x%x. Resetting bus.\n", 1820 1.1 fvdl ahd_name(ahd), lqistat1); 1821 1.1 fvdl } 1822 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1823 1.1 fvdl return; 1824 1.1 fvdl } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1825 1.1 fvdl /* 1826 1.1 fvdl * A CRC error has been detected on an incoming LQ. 1827 1.1 fvdl * The bus is currently hung on the last ACK. 1828 1.1 fvdl * Hit LQIRETRY to release the last ack, and 1829 1.1 fvdl * wait for the sequencer to determine that ATNO 1830 1.1 fvdl * is asserted while in message out to take us 1831 1.1 fvdl * to our host message loop. No NONPACKREQ or 1832 1.1 fvdl * LQIPHASE type errors will occur in this 1833 1.1 fvdl * scenario. After this first LQIRETRY, the LQI 1834 1.1 fvdl * manager will be in ISELO where it will 1835 1.1 fvdl * happily sit until another packet phase begins. 1836 1.1 fvdl * Unexpected bus free detection is enabled 1837 1.1 fvdl * through any phases that occur after we release 1838 1.1 fvdl * this last ack until the LQI manager sees a 1839 1.1 fvdl * packet phase. This implies we may have to 1840 1.64 andvar * ignore a perfectly valid "unexpected busfree" 1841 1.1 fvdl * after our "initiator detected error" message is 1842 1.1 fvdl * sent. A busfree is the expected response after 1843 1.50 snj * we tell the target that its L_Q was corrupted. 1844 1.1 fvdl * (SPI4R09 10.7.3.3.3) 1845 1.1 fvdl */ 1846 1.1 fvdl ahd_outb(ahd, LQCTL2, LQIRETRY); 1847 1.1 fvdl printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1848 1.1 fvdl } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1849 1.1 fvdl /* 1850 1.1 fvdl * We detected a CRC error in a NON-LQ packet. 1851 1.1 fvdl * The hardware has varying behavior in this situation 1852 1.1 fvdl * depending on whether this packet was part of a 1853 1.1 fvdl * stream or not. 1854 1.1 fvdl * 1855 1.1 fvdl * PKT by PKT mode: 1856 1.1 fvdl * The hardware has already acked the complete packet. 1857 1.1 fvdl * If the target honors our outstanding ATN condition, 1858 1.1 fvdl * we should be (or soon will be) in MSGOUT phase. 1859 1.1 fvdl * This will trigger the LQIPHASE_LQ status bit as the 1860 1.1 fvdl * hardware was expecting another LQ. Unexpected 1861 1.1 fvdl * busfree detection is enabled. Once LQIPHASE_LQ is 1862 1.1 fvdl * true (first entry into host message loop is much 1863 1.1 fvdl * the same), we must clear LQIPHASE_LQ and hit 1864 1.1 fvdl * LQIRETRY so the hardware is ready to handle 1865 1.1 fvdl * a future LQ. NONPACKREQ will not be asserted again 1866 1.1 fvdl * once we hit LQIRETRY until another packet is 1867 1.1 fvdl * processed. The target may either go busfree 1868 1.1 fvdl * or start another packet in response to our message. 1869 1.1 fvdl * 1870 1.1 fvdl * Read Streaming P0 asserted: 1871 1.1 fvdl * If we raise ATN and the target completes the entire 1872 1.1 fvdl * stream (P0 asserted during the last packet), the 1873 1.1 fvdl * hardware will ack all data and return to the ISTART 1874 1.70 andvar * state. When the target responds to our ATN condition, 1875 1.1 fvdl * LQIPHASE_LQ will be asserted. We should respond to 1876 1.1 fvdl * this with an LQIRETRY to prepare for any future 1877 1.1 fvdl * packets. NONPACKREQ will not be asserted again 1878 1.1 fvdl * once we hit LQIRETRY until another packet is 1879 1.1 fvdl * processed. The target may either go busfree or 1880 1.1 fvdl * start another packet in response to our message. 1881 1.1 fvdl * Busfree detection is enabled. 1882 1.1 fvdl * 1883 1.1 fvdl * Read Streaming P0 not asserted: 1884 1.1 fvdl * If we raise ATN and the target transitions to 1885 1.1 fvdl * MSGOUT in or after a packet where P0 is not 1886 1.1 fvdl * asserted, the hardware will assert LQIPHASE_NLQ. 1887 1.1 fvdl * We should respond to the LQIPHASE_NLQ with an 1888 1.1 fvdl * LQIRETRY. Should the target stay in a non-pkt 1889 1.1 fvdl * phase after we send our message, the hardware 1890 1.1 fvdl * will assert LQIPHASE_LQ. Recovery is then just as 1891 1.1 fvdl * listed above for the read streaming with P0 asserted. 1892 1.1 fvdl * Busfree detection is enabled. 1893 1.1 fvdl */ 1894 1.1 fvdl if (silent == FALSE) 1895 1.1 fvdl printf("LQICRC_NLQ\n"); 1896 1.1 fvdl if (scb == NULL) { 1897 1.1 fvdl printf("%s: No SCB valid for LQICRC_NLQ. " 1898 1.1 fvdl "Resetting bus\n", ahd_name(ahd)); 1899 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1900 1.1 fvdl return; 1901 1.1 fvdl } 1902 1.1 fvdl } else if ((lqistat1 & LQIBADLQI) != 0) { 1903 1.1 fvdl printf("Need to handle BADLQI!\n"); 1904 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1905 1.1 fvdl return; 1906 1.1 fvdl } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1907 1.1 fvdl if ((curphase & ~P_DATAIN_DT) != 0) { 1908 1.1 fvdl /* Ack the byte. So we can continue. */ 1909 1.1 fvdl if (silent == FALSE) 1910 1.1 fvdl printf("Acking %s to clear perror\n", 1911 1.1 fvdl ahd_lookup_phase_entry(curphase)->phasemsg); 1912 1.1 fvdl ahd_inb(ahd, SCSIDAT); 1913 1.1 fvdl } 1914 1.30 perry 1915 1.1 fvdl if (curphase == P_MESGIN) 1916 1.1 fvdl msg_out = MSG_PARITY_ERROR; 1917 1.1 fvdl } 1918 1.1 fvdl 1919 1.1 fvdl /* 1920 1.30 perry * We've set the hardware to assert ATN if we 1921 1.1 fvdl * get a parity error on "in" phases, so all we 1922 1.1 fvdl * need to do is stuff the message buffer with 1923 1.1 fvdl * the appropriate message. "In" phases have set 1924 1.1 fvdl * mesg_out to something other than MSG_NOP. 1925 1.1 fvdl */ 1926 1.1 fvdl ahd->send_msg_perror = msg_out; 1927 1.1 fvdl if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1928 1.1 fvdl scb->flags |= SCB_TRANSMISSION_ERROR; 1929 1.1 fvdl ahd_outb(ahd, MSG_OUT, HOST_MSG); 1930 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 1931 1.1 fvdl ahd_unpause(ahd); 1932 1.1 fvdl } 1933 1.1 fvdl 1934 1.1 fvdl static void 1935 1.1 fvdl ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1936 1.1 fvdl { 1937 1.1 fvdl /* 1938 1.1 fvdl * Clear the sources of the interrupts. 1939 1.1 fvdl */ 1940 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1941 1.1 fvdl ahd_outb(ahd, CLRLQIINT1, lqistat1); 1942 1.1 fvdl 1943 1.1 fvdl /* 1944 1.1 fvdl * If the "illegal" phase changes were in response 1945 1.1 fvdl * to our ATN to flag a CRC error, AND we ended up 1946 1.1 fvdl * on packet boundaries, clear the error, restart the 1947 1.1 fvdl * LQI manager as appropriate, and go on our merry 1948 1.1 fvdl * way toward sending the message. Otherwise, reset 1949 1.1 fvdl * the bus to clear the error. 1950 1.1 fvdl */ 1951 1.1 fvdl ahd_set_active_fifo(ahd); 1952 1.1 fvdl if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1953 1.1 fvdl && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1954 1.1 fvdl if ((lqistat1 & LQIPHASE_LQ) != 0) { 1955 1.1 fvdl printf("LQIRETRY for LQIPHASE_LQ\n"); 1956 1.1 fvdl ahd_outb(ahd, LQCTL2, LQIRETRY); 1957 1.1 fvdl } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1958 1.1 fvdl printf("LQIRETRY for LQIPHASE_NLQ\n"); 1959 1.1 fvdl ahd_outb(ahd, LQCTL2, LQIRETRY); 1960 1.1 fvdl } else 1961 1.1 fvdl panic("ahd_handle_lqiphase_error: No phase errors\n"); 1962 1.1 fvdl ahd_dump_card_state(ahd); 1963 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 1964 1.1 fvdl ahd_unpause(ahd); 1965 1.1 fvdl } else { 1966 1.57 andvar printf("Resetting Channel for LQI Phase error\n"); 1967 1.1 fvdl ahd_dump_card_state(ahd); 1968 1.1 fvdl ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1969 1.1 fvdl } 1970 1.1 fvdl } 1971 1.1 fvdl 1972 1.1 fvdl /* 1973 1.1 fvdl * Packetized unexpected or expected busfree. 1974 1.1 fvdl * Entered in mode based on busfreetime. 1975 1.1 fvdl */ 1976 1.1 fvdl static int 1977 1.1 fvdl ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1978 1.1 fvdl { 1979 1.1 fvdl u_int lqostat1; 1980 1.1 fvdl 1981 1.1 fvdl AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1982 1.1 fvdl ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1983 1.1 fvdl lqostat1 = ahd_inb(ahd, LQOSTAT1); 1984 1.1 fvdl if ((lqostat1 & LQOBUSFREE) != 0) { 1985 1.1 fvdl struct scb *scb; 1986 1.1 fvdl u_int scbid; 1987 1.1 fvdl u_int saved_scbptr; 1988 1.1 fvdl u_int waiting_h; 1989 1.1 fvdl u_int waiting_t; 1990 1.1 fvdl u_int next; 1991 1.1 fvdl 1992 1.1 fvdl if ((busfreetime & BUSFREE_LQO) == 0) 1993 1.1 fvdl printf("%s: Warning, BUSFREE time is 0x%x. " 1994 1.1 fvdl "Expected BUSFREE_LQO.\n", 1995 1.1 fvdl ahd_name(ahd), busfreetime); 1996 1.1 fvdl /* 1997 1.1 fvdl * The LQO manager detected an unexpected busfree 1998 1.1 fvdl * either: 1999 1.1 fvdl * 2000 1.1 fvdl * 1) During an outgoing LQ. 2001 1.1 fvdl * 2) After an outgoing LQ but before the first 2002 1.1 fvdl * REQ of the command packet. 2003 1.1 fvdl * 3) During an outgoing command packet. 2004 1.1 fvdl * 2005 1.1 fvdl * In all cases, CURRSCB is pointing to the 2006 1.1 fvdl * SCB that encountered the failure. Clean 2007 1.1 fvdl * up the queue, clear SELDO and LQOBUSFREE, 2008 1.1 fvdl * and allow the sequencer to restart the select 2009 1.1 fvdl * out at its lesure. 2010 1.1 fvdl */ 2011 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2012 1.1 fvdl scbid = ahd_inw(ahd, CURRSCB); 2013 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 2014 1.1 fvdl if (scb == NULL) 2015 1.43 tsutsui panic("SCB not valid during LQOBUSFREE"); 2016 1.1 fvdl /* 2017 1.1 fvdl * Clear the status. 2018 1.1 fvdl */ 2019 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2020 1.1 fvdl if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2021 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, 0); 2022 1.1 fvdl ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2023 1.1 fvdl ahd_flush_device_writes(ahd); 2024 1.1 fvdl ahd_outb(ahd, CLRSINT0, CLRSELDO); 2025 1.1 fvdl 2026 1.1 fvdl /* 2027 1.1 fvdl * Return the LQO manager to its idle loop. It will 2028 1.1 fvdl * not do this automatically if the busfree occurs 2029 1.1 fvdl * after the first REQ of either the LQ or command 2030 1.1 fvdl * packet or between the LQ and command packet. 2031 1.1 fvdl */ 2032 1.1 fvdl ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2033 1.1 fvdl 2034 1.1 fvdl /* 2035 1.1 fvdl * Update the waiting for selection queue so 2036 1.1 fvdl * we restart on the correct SCB. 2037 1.1 fvdl */ 2038 1.1 fvdl waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2039 1.1 fvdl saved_scbptr = ahd_get_scbptr(ahd); 2040 1.1 fvdl if (waiting_h != scbid) { 2041 1.1 fvdl 2042 1.1 fvdl ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2043 1.1 fvdl waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2044 1.1 fvdl if (waiting_t == waiting_h) { 2045 1.1 fvdl ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2046 1.1 fvdl next = SCB_LIST_NULL; 2047 1.1 fvdl } else { 2048 1.1 fvdl ahd_set_scbptr(ahd, waiting_h); 2049 1.1 fvdl next = ahd_inw_scbram(ahd, SCB_NEXT2); 2050 1.1 fvdl } 2051 1.1 fvdl ahd_set_scbptr(ahd, scbid); 2052 1.1 fvdl ahd_outw(ahd, SCB_NEXT2, next); 2053 1.1 fvdl } 2054 1.1 fvdl ahd_set_scbptr(ahd, saved_scbptr); 2055 1.1 fvdl if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2056 1.1 fvdl if (SCB_IS_SILENT(scb) == FALSE) { 2057 1.1 fvdl ahd_print_path(ahd, scb); 2058 1.1 fvdl printf("Probable outgoing LQ CRC error. " 2059 1.1 fvdl "Retrying command\n"); 2060 1.1 fvdl } 2061 1.1 fvdl scb->crc_retry_count++; 2062 1.1 fvdl } else { 2063 1.1 fvdl ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 2064 1.1 fvdl ahd_freeze_scb(scb); 2065 1.1 fvdl ahd_freeze_devq(ahd, scb); 2066 1.1 fvdl } 2067 1.1 fvdl /* Return unpausing the sequencer. */ 2068 1.1 fvdl return (0); 2069 1.1 fvdl } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2070 1.1 fvdl /* 2071 1.1 fvdl * Ignore what are really parity errors that 2072 1.1 fvdl * occur on the last REQ of a free running 2073 1.1 fvdl * clock prior to going busfree. Some drives 2074 1.1 fvdl * do not properly active negate just before 2075 1.1 fvdl * going busfree resulting in a parity glitch. 2076 1.1 fvdl */ 2077 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2078 1.1 fvdl #ifdef AHD_DEBUG 2079 1.1 fvdl if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2080 1.1 fvdl printf("%s: Parity on last REQ detected " 2081 1.1 fvdl "during busfree phase.\n", 2082 1.1 fvdl ahd_name(ahd)); 2083 1.1 fvdl #endif 2084 1.1 fvdl /* Return unpausing the sequencer. */ 2085 1.1 fvdl return (0); 2086 1.1 fvdl } 2087 1.1 fvdl if (ahd->src_mode != AHD_MODE_SCSI) { 2088 1.1 fvdl u_int scbid; 2089 1.1 fvdl struct scb *scb; 2090 1.1 fvdl 2091 1.1 fvdl scbid = ahd_get_scbptr(ahd); 2092 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 2093 1.1 fvdl ahd_print_path(ahd, scb); 2094 1.1 fvdl printf("Unexpected PKT busfree condition\n"); 2095 1.1 fvdl ahd_dump_card_state(ahd); 2096 1.1 fvdl ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 2097 1.1 fvdl SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2098 1.1 fvdl ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 2099 1.1 fvdl 2100 1.1 fvdl /* Return restarting the sequencer. */ 2101 1.1 fvdl return (1); 2102 1.1 fvdl } 2103 1.1 fvdl printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 2104 1.1 fvdl ahd_dump_card_state(ahd); 2105 1.1 fvdl /* Restart the sequencer. */ 2106 1.1 fvdl return (1); 2107 1.1 fvdl } 2108 1.1 fvdl 2109 1.1 fvdl /* 2110 1.1 fvdl * Non-packetized unexpected or expected busfree. 2111 1.1 fvdl */ 2112 1.1 fvdl static int 2113 1.1 fvdl ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 2114 1.1 fvdl { 2115 1.1 fvdl struct ahd_devinfo devinfo; 2116 1.1 fvdl struct scb *scb; 2117 1.1 fvdl u_int lastphase; 2118 1.1 fvdl u_int saved_scsiid; 2119 1.1 fvdl u_int saved_lun; 2120 1.1 fvdl u_int target; 2121 1.1 fvdl u_int initiator_role_id; 2122 1.1 fvdl u_int scbid; 2123 1.1 fvdl u_int ppr_busfree; 2124 1.1 fvdl int printerror; 2125 1.1 fvdl 2126 1.1 fvdl /* 2127 1.1 fvdl * Look at what phase we were last in. If its message out, 2128 1.1 fvdl * chances are pretty good that the busfree was in response 2129 1.1 fvdl * to one of our abort requests. 2130 1.1 fvdl */ 2131 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 2132 1.1 fvdl saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2133 1.1 fvdl saved_lun = ahd_inb(ahd, SAVED_LUN); 2134 1.1 fvdl target = SCSIID_TARGET(ahd, saved_scsiid); 2135 1.1 fvdl initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 2136 1.1 fvdl ahd_compile_devinfo(&devinfo, initiator_role_id, 2137 1.1 fvdl target, saved_lun, 'A', ROLE_INITIATOR); 2138 1.1 fvdl printerror = 1; 2139 1.1 fvdl 2140 1.1 fvdl scbid = ahd_get_scbptr(ahd); 2141 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 2142 1.1 fvdl if (scb != NULL 2143 1.1 fvdl && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2144 1.1 fvdl scb = NULL; 2145 1.1 fvdl 2146 1.1 fvdl ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 2147 1.1 fvdl if (lastphase == P_MESGOUT) { 2148 1.1 fvdl u_int tag; 2149 1.1 fvdl 2150 1.1 fvdl tag = SCB_LIST_NULL; 2151 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 2152 1.1 fvdl || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 2153 1.1 fvdl int found; 2154 1.1 fvdl int sent_msg; 2155 1.1 fvdl 2156 1.1 fvdl if (scb == NULL) { 2157 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 2158 1.1 fvdl printf("Abort for unidentified " 2159 1.1 fvdl "connection completed.\n"); 2160 1.1 fvdl /* restart the sequencer. */ 2161 1.1 fvdl return (1); 2162 1.1 fvdl } 2163 1.1 fvdl sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 2164 1.1 fvdl ahd_print_path(ahd, scb); 2165 1.1 fvdl printf("SCB %d - Abort%s Completed.\n", 2166 1.1 fvdl SCB_GET_TAG(scb), 2167 1.1 fvdl sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 2168 1.1 fvdl 2169 1.1 fvdl if (sent_msg == MSG_ABORT_TAG) 2170 1.1 fvdl tag = SCB_GET_TAG(scb); 2171 1.1 fvdl 2172 1.1 fvdl if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 2173 1.1 fvdl /* 2174 1.1 fvdl * This abort is in response to an 2175 1.1 fvdl * unexpected switch to command phase 2176 1.1 fvdl * for a packetized connection. Since 2177 1.1 fvdl * the identify message was never sent, 2178 1.1 fvdl * "saved lun" is 0. We really want to 2179 1.1 fvdl * abort only the SCB that encountered 2180 1.1 fvdl * this error, which could have a different 2181 1.1 fvdl * lun. The SCB will be retried so the OS 2182 1.1 fvdl * will see the UA after renegotiating to 2183 1.1 fvdl * packetized. 2184 1.1 fvdl */ 2185 1.1 fvdl tag = SCB_GET_TAG(scb); 2186 1.1 fvdl saved_lun = scb->hscb->lun; 2187 1.1 fvdl } 2188 1.1 fvdl found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 2189 1.1 fvdl tag, ROLE_INITIATOR, 2190 1.1 fvdl CAM_REQ_ABORTED); 2191 1.1 fvdl printf("found == 0x%x\n", found); 2192 1.1 fvdl printerror = 0; 2193 1.1 fvdl } else if (ahd_sent_msg(ahd, AHDMSG_1B, 2194 1.1 fvdl MSG_BUS_DEV_RESET, TRUE)) { 2195 1.1 fvdl #ifdef __FreeBSD__ 2196 1.1 fvdl /* 2197 1.1 fvdl * Don't mark the user's request for this BDR 2198 1.1 fvdl * as completing with CAM_BDR_SENT. CAM3 2199 1.1 fvdl * specifies CAM_REQ_CMP. 2200 1.1 fvdl */ 2201 1.1 fvdl if (scb != NULL 2202 1.1 fvdl && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 2203 1.1 fvdl && ahd_match_scb(ahd, scb, target, 'A', 2204 1.1 fvdl CAM_LUN_WILDCARD, SCB_LIST_NULL, 2205 1.1 fvdl ROLE_INITIATOR)) 2206 1.1 fvdl ahd_set_transaction_status(scb, CAM_REQ_CMP); 2207 1.1 fvdl #endif 2208 1.1 fvdl ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 2209 1.1 fvdl CAM_BDR_SENT, "Bus Device Reset", 2210 1.1 fvdl /*verbose_level*/0); 2211 1.1 fvdl printerror = 0; 2212 1.1 fvdl } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 2213 1.1 fvdl && ppr_busfree == 0) { 2214 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 2215 1.1 fvdl struct ahd_tmode_tstate *tstate; 2216 1.1 fvdl 2217 1.1 fvdl /* 2218 1.1 fvdl * PPR Rejected. Try non-ppr negotiation 2219 1.1 fvdl * and retry command. 2220 1.1 fvdl */ 2221 1.1 fvdl #ifdef AHD_DEBUG 2222 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2223 1.1 fvdl printf("PPR negotiation rejected busfree.\n"); 2224 1.1 fvdl #endif 2225 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2226 1.1 fvdl devinfo.our_scsiid, 2227 1.1 fvdl devinfo.target, &tstate); 2228 1.1 fvdl tinfo->curr.transport_version = 2; 2229 1.1 fvdl tinfo->goal.transport_version = 2; 2230 1.1 fvdl tinfo->goal.ppr_options = 0; 2231 1.1 fvdl ahd_qinfifo_requeue_tail(ahd, scb); 2232 1.1 fvdl printerror = 0; 2233 1.16 thorpej } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 2234 1.1 fvdl && ppr_busfree == 0) { 2235 1.1 fvdl /* 2236 1.16 thorpej * Negotiation Rejected. Go-narrow and 2237 1.1 fvdl * retry command. 2238 1.1 fvdl */ 2239 1.1 fvdl #ifdef AHD_DEBUG 2240 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2241 1.16 thorpej printf("WDTR Negotiation rejected busfree.\n"); 2242 1.1 fvdl #endif 2243 1.1 fvdl ahd_set_width(ahd, &devinfo, 2244 1.1 fvdl MSG_EXT_WDTR_BUS_8_BIT, 2245 1.1 fvdl AHD_TRANS_CUR|AHD_TRANS_GOAL, 2246 1.1 fvdl /*paused*/TRUE); 2247 1.16 thorpej ahd_qinfifo_requeue_tail(ahd, scb); 2248 1.16 thorpej printerror = 0; 2249 1.16 thorpej } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 2250 1.16 thorpej && ppr_busfree == 0) { 2251 1.16 thorpej /* 2252 1.16 thorpej * Negotiation Rejected. Go-async and 2253 1.16 thorpej * retry command. 2254 1.16 thorpej */ 2255 1.16 thorpej #ifdef AHD_DEBUG 2256 1.16 thorpej if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2257 1.16 thorpej printf("SDTR negotiation rejected busfree.\n"); 2258 1.16 thorpej #endif 2259 1.1 fvdl ahd_set_syncrate(ahd, &devinfo, 2260 1.1 fvdl /*period*/0, /*offset*/0, 2261 1.1 fvdl /*ppr_options*/0, 2262 1.1 fvdl AHD_TRANS_CUR|AHD_TRANS_GOAL, 2263 1.1 fvdl /*paused*/TRUE); 2264 1.1 fvdl ahd_qinfifo_requeue_tail(ahd, scb); 2265 1.1 fvdl printerror = 0; 2266 1.1 fvdl } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 2267 1.1 fvdl && ahd_sent_msg(ahd, AHDMSG_1B, 2268 1.1 fvdl MSG_INITIATOR_DET_ERR, TRUE)) { 2269 1.1 fvdl 2270 1.1 fvdl #ifdef AHD_DEBUG 2271 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2272 1.1 fvdl printf("Expected IDE Busfree\n"); 2273 1.1 fvdl #endif 2274 1.1 fvdl printerror = 0; 2275 1.1 fvdl } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 2276 1.1 fvdl && ahd_sent_msg(ahd, AHDMSG_1B, 2277 1.1 fvdl MSG_MESSAGE_REJECT, TRUE)) { 2278 1.1 fvdl 2279 1.1 fvdl #ifdef AHD_DEBUG 2280 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2281 1.1 fvdl printf("Expected QAS Reject Busfree\n"); 2282 1.1 fvdl #endif 2283 1.1 fvdl printerror = 0; 2284 1.1 fvdl } 2285 1.1 fvdl } 2286 1.1 fvdl 2287 1.1 fvdl /* 2288 1.1 fvdl * The busfree required flag is honored at the end of 2289 1.1 fvdl * the message phases. We check it last in case we 2290 1.1 fvdl * had to send some other message that caused a busfree. 2291 1.1 fvdl */ 2292 1.1 fvdl if (printerror != 0 2293 1.1 fvdl && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 2294 1.1 fvdl && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 2295 1.1 fvdl 2296 1.1 fvdl ahd_freeze_devq(ahd, scb); 2297 1.1 fvdl ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 2298 1.1 fvdl ahd_freeze_scb(scb); 2299 1.1 fvdl if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 2300 1.1 fvdl ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2301 1.1 fvdl SCB_GET_CHANNEL(ahd, scb), 2302 1.1 fvdl SCB_GET_LUN(scb), SCB_LIST_NULL, 2303 1.1 fvdl ROLE_INITIATOR, CAM_REQ_ABORTED); 2304 1.1 fvdl } else { 2305 1.1 fvdl #ifdef AHD_DEBUG 2306 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2307 1.1 fvdl printf("PPR Negotiation Busfree.\n"); 2308 1.1 fvdl #endif 2309 1.1 fvdl ahd_done(ahd, scb); 2310 1.1 fvdl } 2311 1.1 fvdl printerror = 0; 2312 1.1 fvdl } 2313 1.1 fvdl if (printerror != 0) { 2314 1.1 fvdl int aborted; 2315 1.1 fvdl 2316 1.1 fvdl aborted = 0; 2317 1.1 fvdl if (scb != NULL) { 2318 1.1 fvdl u_int tag; 2319 1.1 fvdl 2320 1.1 fvdl if ((scb->hscb->control & TAG_ENB) != 0) 2321 1.1 fvdl tag = SCB_GET_TAG(scb); 2322 1.1 fvdl else 2323 1.1 fvdl tag = SCB_LIST_NULL; 2324 1.1 fvdl ahd_print_path(ahd, scb); 2325 1.1 fvdl aborted = ahd_abort_scbs(ahd, target, 'A', 2326 1.1 fvdl SCB_GET_LUN(scb), tag, 2327 1.1 fvdl ROLE_INITIATOR, 2328 1.1 fvdl CAM_UNEXP_BUSFREE); 2329 1.1 fvdl } else { 2330 1.1 fvdl /* 2331 1.1 fvdl * We had not fully identified this connection, 2332 1.1 fvdl * so we cannot abort anything. 2333 1.1 fvdl */ 2334 1.1 fvdl printf("%s: ", ahd_name(ahd)); 2335 1.1 fvdl } 2336 1.1 fvdl if (lastphase != P_BUSFREE) 2337 1.1 fvdl ahd_force_renegotiation(ahd, &devinfo); 2338 1.1 fvdl printf("Unexpected busfree %s, %d SCBs aborted, " 2339 1.1 fvdl "PRGMCNT == 0x%x\n", 2340 1.1 fvdl ahd_lookup_phase_entry(lastphase)->phasemsg, 2341 1.1 fvdl aborted, 2342 1.1 fvdl ahd_inb(ahd, PRGMCNT) 2343 1.1 fvdl | (ahd_inb(ahd, PRGMCNT+1) << 8)); 2344 1.1 fvdl ahd_dump_card_state(ahd); 2345 1.1 fvdl } 2346 1.1 fvdl /* Always restart the sequencer. */ 2347 1.1 fvdl return (1); 2348 1.1 fvdl } 2349 1.1 fvdl 2350 1.1 fvdl static void 2351 1.1 fvdl ahd_handle_proto_violation(struct ahd_softc *ahd) 2352 1.1 fvdl { 2353 1.1 fvdl struct ahd_devinfo devinfo; 2354 1.1 fvdl struct scb *scb; 2355 1.1 fvdl u_int scbid; 2356 1.1 fvdl u_int seq_flags; 2357 1.1 fvdl u_int curphase; 2358 1.1 fvdl u_int lastphase; 2359 1.1 fvdl int found; 2360 1.1 fvdl 2361 1.1 fvdl ahd_fetch_devinfo(ahd, &devinfo); 2362 1.1 fvdl scbid = ahd_get_scbptr(ahd); 2363 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 2364 1.1 fvdl seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2365 1.1 fvdl curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2366 1.1 fvdl lastphase = ahd_inb(ahd, LASTPHASE); 2367 1.1 fvdl if ((seq_flags & NOT_IDENTIFIED) != 0) { 2368 1.1 fvdl 2369 1.1 fvdl /* 2370 1.1 fvdl * The reconnecting target either did not send an 2371 1.1 fvdl * identify message, or did, but we didn't find an SCB 2372 1.1 fvdl * to match. 2373 1.1 fvdl */ 2374 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 2375 1.1 fvdl printf("Target did not send an IDENTIFY message. " 2376 1.1 fvdl "LASTPHASE = 0x%x.\n", lastphase); 2377 1.1 fvdl scb = NULL; 2378 1.1 fvdl } else if (scb == NULL) { 2379 1.1 fvdl /* 2380 1.1 fvdl * We don't seem to have an SCB active for this 2381 1.1 fvdl * transaction. Print an error and reset the bus. 2382 1.1 fvdl */ 2383 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 2384 1.1 fvdl printf("No SCB found during protocol violation\n"); 2385 1.1 fvdl goto proto_violation_reset; 2386 1.1 fvdl } else { 2387 1.1 fvdl ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2388 1.1 fvdl if ((seq_flags & NO_CDB_SENT) != 0) { 2389 1.1 fvdl ahd_print_path(ahd, scb); 2390 1.1 fvdl printf("No or incomplete CDB sent to device.\n"); 2391 1.1 fvdl } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2392 1.1 fvdl & STATUS_RCVD) == 0) { 2393 1.1 fvdl /* 2394 1.1 fvdl * The target never bothered to provide status to 2395 1.1 fvdl * us prior to completing the command. Since we don't 2396 1.1 fvdl * know the disposition of this command, we must attempt 2397 1.1 fvdl * to abort it. Assert ATN and prepare to send an abort 2398 1.1 fvdl * message. 2399 1.1 fvdl */ 2400 1.1 fvdl ahd_print_path(ahd, scb); 2401 1.1 fvdl printf("Completed command without status.\n"); 2402 1.1 fvdl } else { 2403 1.1 fvdl ahd_print_path(ahd, scb); 2404 1.1 fvdl printf("Unknown protocol violation.\n"); 2405 1.1 fvdl ahd_dump_card_state(ahd); 2406 1.1 fvdl } 2407 1.1 fvdl } 2408 1.1 fvdl if ((lastphase & ~P_DATAIN_DT) == 0 2409 1.1 fvdl || lastphase == P_COMMAND) { 2410 1.1 fvdl proto_violation_reset: 2411 1.1 fvdl /* 2412 1.1 fvdl * Target either went directly to data 2413 1.1 fvdl * phase or didn't respond to our ATN. 2414 1.1 fvdl * The only safe thing to do is to blow 2415 1.1 fvdl * it away with a bus reset. 2416 1.1 fvdl */ 2417 1.1 fvdl found = ahd_reset_channel(ahd, 'A', TRUE); 2418 1.1 fvdl printf("%s: Issued Channel %c Bus Reset. " 2419 1.1 fvdl "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2420 1.1 fvdl } else { 2421 1.1 fvdl /* 2422 1.1 fvdl * Leave the selection hardware off in case 2423 1.1 fvdl * this abort attempt will affect yet to 2424 1.1 fvdl * be sent commands. 2425 1.1 fvdl */ 2426 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 2427 1.1 fvdl ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2428 1.1 fvdl ahd_assert_atn(ahd); 2429 1.1 fvdl ahd_outb(ahd, MSG_OUT, HOST_MSG); 2430 1.1 fvdl if (scb == NULL) { 2431 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 2432 1.1 fvdl ahd->msgout_buf[0] = MSG_ABORT_TASK; 2433 1.1 fvdl ahd->msgout_len = 1; 2434 1.1 fvdl ahd->msgout_index = 0; 2435 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2436 1.1 fvdl } else { 2437 1.1 fvdl ahd_print_path(ahd, scb); 2438 1.1 fvdl scb->flags |= SCB_ABORT; 2439 1.1 fvdl } 2440 1.1 fvdl printf("Protocol violation %s. Attempting to abort.\n", 2441 1.1 fvdl ahd_lookup_phase_entry(curphase)->phasemsg); 2442 1.1 fvdl } 2443 1.1 fvdl } 2444 1.1 fvdl 2445 1.1 fvdl /* 2446 1.1 fvdl * Force renegotiation to occur the next time we initiate 2447 1.1 fvdl * a command to the current device. 2448 1.1 fvdl */ 2449 1.1 fvdl static void 2450 1.1 fvdl ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2451 1.1 fvdl { 2452 1.1 fvdl struct ahd_initiator_tinfo *targ_info; 2453 1.1 fvdl struct ahd_tmode_tstate *tstate; 2454 1.1 fvdl 2455 1.1 fvdl #ifdef AHD_DEBUG 2456 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2457 1.1 fvdl ahd_print_devinfo(ahd, devinfo); 2458 1.1 fvdl printf("Forcing renegotiation\n"); 2459 1.1 fvdl } 2460 1.1 fvdl #endif 2461 1.1 fvdl targ_info = ahd_fetch_transinfo(ahd, 2462 1.1 fvdl devinfo->channel, 2463 1.1 fvdl devinfo->our_scsiid, 2464 1.1 fvdl devinfo->target, 2465 1.1 fvdl &tstate); 2466 1.1 fvdl ahd_update_neg_request(ahd, devinfo, tstate, 2467 1.1 fvdl targ_info, AHD_NEG_IF_NON_ASYNC); 2468 1.1 fvdl } 2469 1.1 fvdl 2470 1.1 fvdl #define AHD_MAX_STEPS 2000 2471 1.1 fvdl void 2472 1.1 fvdl ahd_clear_critical_section(struct ahd_softc *ahd) 2473 1.1 fvdl { 2474 1.1 fvdl ahd_mode_state saved_modes; 2475 1.1 fvdl int stepping; 2476 1.1 fvdl int steps; 2477 1.1 fvdl int first_instr; 2478 1.1 fvdl u_int simode0; 2479 1.1 fvdl u_int simode1; 2480 1.1 fvdl u_int simode3; 2481 1.1 fvdl u_int lqimode0; 2482 1.1 fvdl u_int lqimode1; 2483 1.1 fvdl u_int lqomode0; 2484 1.1 fvdl u_int lqomode1; 2485 1.1 fvdl 2486 1.1 fvdl if (ahd->num_critical_sections == 0) 2487 1.1 fvdl return; 2488 1.1 fvdl 2489 1.1 fvdl stepping = FALSE; 2490 1.1 fvdl steps = 0; 2491 1.1 fvdl first_instr = 0; 2492 1.1 fvdl simode0 = 0; 2493 1.1 fvdl simode1 = 0; 2494 1.1 fvdl simode3 = 0; 2495 1.1 fvdl lqimode0 = 0; 2496 1.1 fvdl lqimode1 = 0; 2497 1.1 fvdl lqomode0 = 0; 2498 1.1 fvdl lqomode1 = 0; 2499 1.1 fvdl saved_modes = ahd_save_modes(ahd); 2500 1.1 fvdl for (;;) { 2501 1.1 fvdl struct cs *cs; 2502 1.1 fvdl u_int seqaddr; 2503 1.1 fvdl u_int i; 2504 1.1 fvdl 2505 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2506 1.1 fvdl seqaddr = ahd_inb(ahd, CURADDR) 2507 1.1 fvdl | (ahd_inb(ahd, CURADDR+1) << 8); 2508 1.1 fvdl 2509 1.1 fvdl cs = ahd->critical_sections; 2510 1.1 fvdl for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2511 1.30 perry 2512 1.1 fvdl if (cs->begin < seqaddr && cs->end >= seqaddr) 2513 1.1 fvdl break; 2514 1.1 fvdl } 2515 1.1 fvdl 2516 1.1 fvdl if (i == ahd->num_critical_sections) 2517 1.1 fvdl break; 2518 1.1 fvdl 2519 1.1 fvdl if (steps > AHD_MAX_STEPS) { 2520 1.1 fvdl printf("%s: Infinite loop in critical section\n" 2521 1.1 fvdl "%s: First Instruction 0x%x now 0x%x\n", 2522 1.1 fvdl ahd_name(ahd), ahd_name(ahd), first_instr, 2523 1.1 fvdl seqaddr); 2524 1.1 fvdl ahd_dump_card_state(ahd); 2525 1.1 fvdl panic("critical section loop"); 2526 1.1 fvdl } 2527 1.1 fvdl 2528 1.1 fvdl steps++; 2529 1.1 fvdl #ifdef AHD_DEBUG 2530 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 2531 1.1 fvdl printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2532 1.1 fvdl seqaddr); 2533 1.1 fvdl #endif 2534 1.1 fvdl if (stepping == FALSE) { 2535 1.1 fvdl 2536 1.1 fvdl first_instr = seqaddr; 2537 1.43 tsutsui ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2538 1.43 tsutsui simode0 = ahd_inb(ahd, SIMODE0); 2539 1.1 fvdl simode3 = ahd_inb(ahd, SIMODE3); 2540 1.1 fvdl lqimode0 = ahd_inb(ahd, LQIMODE0); 2541 1.1 fvdl lqimode1 = ahd_inb(ahd, LQIMODE1); 2542 1.1 fvdl lqomode0 = ahd_inb(ahd, LQOMODE0); 2543 1.1 fvdl lqomode1 = ahd_inb(ahd, LQOMODE1); 2544 1.1 fvdl ahd_outb(ahd, SIMODE0, 0); 2545 1.1 fvdl ahd_outb(ahd, SIMODE3, 0); 2546 1.1 fvdl ahd_outb(ahd, LQIMODE0, 0); 2547 1.1 fvdl ahd_outb(ahd, LQIMODE1, 0); 2548 1.1 fvdl ahd_outb(ahd, LQOMODE0, 0); 2549 1.1 fvdl ahd_outb(ahd, LQOMODE1, 0); 2550 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2551 1.19 thorpej simode1 = ahd_inb(ahd, SIMODE1); 2552 1.19 thorpej /* 2553 1.19 thorpej * We don't clear ENBUSFREE. Unfortunately 2554 1.19 thorpej * we cannot re-enable busfree detection within 2555 1.19 thorpej * the current connection, so we must leave it 2556 1.19 thorpej * on while single stepping. 2557 1.19 thorpej */ 2558 1.19 thorpej ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2559 1.1 fvdl ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2560 1.1 fvdl stepping = TRUE; 2561 1.1 fvdl } 2562 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2563 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 2564 1.1 fvdl ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2565 1.1 fvdl ahd_outb(ahd, HCNTRL, ahd->unpause); 2566 1.19 thorpej while (!ahd_is_paused(ahd)) 2567 1.1 fvdl ahd_delay(200); 2568 1.1 fvdl ahd_update_modes(ahd); 2569 1.1 fvdl } 2570 1.1 fvdl if (stepping) { 2571 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2572 1.1 fvdl ahd_outb(ahd, SIMODE0, simode0); 2573 1.1 fvdl ahd_outb(ahd, SIMODE3, simode3); 2574 1.1 fvdl ahd_outb(ahd, LQIMODE0, lqimode0); 2575 1.1 fvdl ahd_outb(ahd, LQIMODE1, lqimode1); 2576 1.1 fvdl ahd_outb(ahd, LQOMODE0, lqomode0); 2577 1.1 fvdl ahd_outb(ahd, LQOMODE1, lqomode1); 2578 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2579 1.1 fvdl ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2580 1.43 tsutsui ahd_outb(ahd, SIMODE1, simode1); 2581 1.9 thorpej /* 2582 1.65 andvar * SCSIINT seems to glitch occasionally when 2583 1.9 thorpej * the interrupt masks are restored. Clear SCSIINT 2584 1.9 thorpej * one more time so that only persistent errors 2585 1.9 thorpej * are seen as a real interrupt. 2586 1.9 thorpej */ 2587 1.9 thorpej ahd_outb(ahd, CLRINT, CLRSCSIINT); 2588 1.1 fvdl } 2589 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 2590 1.1 fvdl } 2591 1.1 fvdl 2592 1.1 fvdl /* 2593 1.1 fvdl * Clear any pending interrupt status. 2594 1.1 fvdl */ 2595 1.1 fvdl void 2596 1.1 fvdl ahd_clear_intstat(struct ahd_softc *ahd) 2597 1.1 fvdl { 2598 1.1 fvdl AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2599 1.1 fvdl ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2600 1.1 fvdl /* Clear any interrupt conditions this may have caused */ 2601 1.1 fvdl ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2602 1.1 fvdl |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2603 1.1 fvdl ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2604 1.1 fvdl |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2605 1.1 fvdl |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2606 1.1 fvdl ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2607 1.1 fvdl |CLRLQOATNPKT|CLRLQOTCRC); 2608 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2609 1.1 fvdl |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2610 1.1 fvdl if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2611 1.1 fvdl ahd_outb(ahd, CLRLQOINT0, 0); 2612 1.1 fvdl ahd_outb(ahd, CLRLQOINT1, 0); 2613 1.1 fvdl } 2614 1.1 fvdl ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2615 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2616 1.1 fvdl |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2617 1.1 fvdl ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2618 1.1 fvdl |CLRIOERR|CLROVERRUN); 2619 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 2620 1.1 fvdl } 2621 1.1 fvdl 2622 1.1 fvdl /**************************** Debugging Routines ******************************/ 2623 1.1 fvdl #ifdef AHD_DEBUG 2624 1.1 fvdl uint32_t ahd_debug = AHD_DEBUG_OPTS; 2625 1.1 fvdl #endif 2626 1.1 fvdl void 2627 1.1 fvdl ahd_print_scb(struct scb *scb) 2628 1.1 fvdl { 2629 1.1 fvdl struct hardware_scb *hscb; 2630 1.1 fvdl int i; 2631 1.1 fvdl 2632 1.1 fvdl hscb = scb->hscb; 2633 1.1 fvdl printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2634 1.1 fvdl (void *)scb, 2635 1.1 fvdl hscb->control, 2636 1.1 fvdl hscb->scsiid, 2637 1.1 fvdl hscb->lun, 2638 1.1 fvdl hscb->cdb_len); 2639 1.1 fvdl printf("Shared Data: "); 2640 1.1 fvdl for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2641 1.1 fvdl printf("%#02x", hscb->shared_data.idata.cdb[i]); 2642 1.1 fvdl printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2643 1.1 fvdl (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2644 1.1 fvdl (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2645 1.1 fvdl ahd_le32toh(hscb->datacnt), 2646 1.1 fvdl ahd_le32toh(hscb->sgptr), 2647 1.1 fvdl SCB_GET_TAG(scb)); 2648 1.1 fvdl ahd_dump_sglist(scb); 2649 1.1 fvdl } 2650 1.1 fvdl 2651 1.1 fvdl void 2652 1.1 fvdl ahd_dump_sglist(struct scb *scb) 2653 1.1 fvdl { 2654 1.1 fvdl int i; 2655 1.1 fvdl 2656 1.1 fvdl if (scb->sg_count > 0) { 2657 1.1 fvdl if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2658 1.1 fvdl struct ahd_dma64_seg *sg_list; 2659 1.1 fvdl 2660 1.1 fvdl sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2661 1.1 fvdl for (i = 0; i < scb->sg_count; i++) { 2662 1.1 fvdl uint64_t addr; 2663 1.1 fvdl 2664 1.1 fvdl addr = ahd_le64toh(sg_list[i].addr); 2665 1.1 fvdl printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2666 1.1 fvdl i, 2667 1.1 fvdl (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2668 1.1 fvdl (uint32_t)(addr & 0xFFFFFFFF), 2669 1.1 fvdl sg_list[i].len & AHD_SG_LEN_MASK, 2670 1.1 fvdl (sg_list[i].len & AHD_DMA_LAST_SEG) 2671 1.1 fvdl ? " Last" : ""); 2672 1.1 fvdl } 2673 1.1 fvdl } else { 2674 1.1 fvdl struct ahd_dma_seg *sg_list; 2675 1.1 fvdl 2676 1.1 fvdl sg_list = (struct ahd_dma_seg*)scb->sg_list; 2677 1.1 fvdl for (i = 0; i < scb->sg_count; i++) { 2678 1.1 fvdl uint32_t len; 2679 1.1 fvdl 2680 1.1 fvdl len = ahd_le32toh(sg_list[i].len); 2681 1.1 fvdl printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2682 1.1 fvdl i, 2683 1.20 thorpej (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 2684 1.1 fvdl ahd_le32toh(sg_list[i].addr), 2685 1.1 fvdl len & AHD_SG_LEN_MASK, 2686 1.1 fvdl len & AHD_DMA_LAST_SEG ? " Last" : ""); 2687 1.1 fvdl } 2688 1.1 fvdl } 2689 1.1 fvdl } 2690 1.1 fvdl } 2691 1.1 fvdl 2692 1.1 fvdl /************************* Transfer Negotiation *******************************/ 2693 1.1 fvdl /* 2694 1.1 fvdl * Allocate per target mode instance (ID we respond to as a target) 2695 1.1 fvdl * transfer negotiation data structures. 2696 1.1 fvdl */ 2697 1.1 fvdl static struct ahd_tmode_tstate * 2698 1.36 christos ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2699 1.1 fvdl { 2700 1.1 fvdl struct ahd_tmode_tstate *master_tstate; 2701 1.1 fvdl struct ahd_tmode_tstate *tstate; 2702 1.1 fvdl int i; 2703 1.1 fvdl 2704 1.1 fvdl master_tstate = ahd->enabled_targets[ahd->our_id]; 2705 1.1 fvdl if (ahd->enabled_targets[scsi_id] != NULL 2706 1.1 fvdl && ahd->enabled_targets[scsi_id] != master_tstate) 2707 1.1 fvdl panic("%s: ahd_alloc_tstate - Target already allocated", 2708 1.1 fvdl ahd_name(ahd)); 2709 1.52 chs tstate = malloc(sizeof(*tstate), M_DEVBUF, M_WAITOK | M_ZERO); 2710 1.1 fvdl 2711 1.1 fvdl /* 2712 1.1 fvdl * If we have allocated a master tstate, copy user settings from 2713 1.1 fvdl * the master tstate (taken from SRAM or the EEPROM) for this 2714 1.1 fvdl * channel, but reset our current and goal settings to async/narrow 2715 1.1 fvdl * until an initiator talks to us. 2716 1.1 fvdl */ 2717 1.1 fvdl if (master_tstate != NULL) { 2718 1.1 fvdl memcpy(tstate, master_tstate, sizeof(*tstate)); 2719 1.1 fvdl memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2720 1.1 fvdl for (i = 0; i < 16; i++) { 2721 1.1 fvdl memset(&tstate->transinfo[i].curr, 0, 2722 1.1 fvdl sizeof(tstate->transinfo[i].curr)); 2723 1.1 fvdl memset(&tstate->transinfo[i].goal, 0, 2724 1.1 fvdl sizeof(tstate->transinfo[i].goal)); 2725 1.1 fvdl } 2726 1.1 fvdl } else 2727 1.1 fvdl memset(tstate, 0, sizeof(*tstate)); 2728 1.1 fvdl ahd->enabled_targets[scsi_id] = tstate; 2729 1.1 fvdl return (tstate); 2730 1.1 fvdl } 2731 1.1 fvdl 2732 1.1 fvdl #ifdef AHD_TARGET_MODE 2733 1.1 fvdl /* 2734 1.1 fvdl * Free per target mode instance (ID we respond to as a target) 2735 1.1 fvdl * transfer negotiation data structures. 2736 1.1 fvdl */ 2737 1.1 fvdl static void 2738 1.1 fvdl ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2739 1.1 fvdl { 2740 1.1 fvdl struct ahd_tmode_tstate *tstate; 2741 1.1 fvdl 2742 1.1 fvdl /* 2743 1.1 fvdl * Don't clean up our "master" tstate. 2744 1.1 fvdl * It has our default user settings. 2745 1.1 fvdl */ 2746 1.1 fvdl if (scsi_id == ahd->our_id 2747 1.1 fvdl && force == FALSE) 2748 1.1 fvdl return; 2749 1.1 fvdl 2750 1.1 fvdl tstate = ahd->enabled_targets[scsi_id]; 2751 1.1 fvdl if (tstate != NULL) 2752 1.1 fvdl free(tstate, M_DEVBUF); 2753 1.1 fvdl ahd->enabled_targets[scsi_id] = NULL; 2754 1.1 fvdl } 2755 1.1 fvdl #endif 2756 1.1 fvdl 2757 1.1 fvdl /* 2758 1.1 fvdl * Called when we have an active connection to a target on the bus, 2759 1.1 fvdl * this function finds the nearest period to the input period limited 2760 1.1 fvdl * by the capabilities of the bus connectivity of and sync settings for 2761 1.1 fvdl * the target. 2762 1.1 fvdl */ 2763 1.1 fvdl void 2764 1.1 fvdl ahd_devlimited_syncrate(struct ahd_softc *ahd, 2765 1.1 fvdl struct ahd_initiator_tinfo *tinfo, 2766 1.1 fvdl u_int *period, u_int *ppr_options, role_t role) 2767 1.1 fvdl { 2768 1.1 fvdl struct ahd_transinfo *transinfo; 2769 1.1 fvdl u_int maxsync; 2770 1.1 fvdl 2771 1.1 fvdl if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2772 1.1 fvdl && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2773 1.1 fvdl maxsync = AHD_SYNCRATE_PACED; 2774 1.1 fvdl } else { 2775 1.1 fvdl maxsync = AHD_SYNCRATE_ULTRA; 2776 1.1 fvdl /* Can't do DT related options on an SE bus */ 2777 1.1 fvdl *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2778 1.1 fvdl } 2779 1.1 fvdl /* 2780 1.1 fvdl * Never allow a value higher than our current goal 2781 1.1 fvdl * period otherwise we may allow a target initiated 2782 1.1 fvdl * negotiation to go above the limit as set by the 2783 1.1 fvdl * user. In the case of an initiator initiated 2784 1.1 fvdl * sync negotiation, we limit based on the user 2785 1.1 fvdl * setting. This allows the system to still accept 2786 1.1 fvdl * incoming negotiations even if target initiated 2787 1.1 fvdl * negotiation is not performed. 2788 1.1 fvdl */ 2789 1.1 fvdl if (role == ROLE_TARGET) 2790 1.1 fvdl transinfo = &tinfo->user; 2791 1.30 perry else 2792 1.1 fvdl transinfo = &tinfo->goal; 2793 1.1 fvdl *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2794 1.1 fvdl if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2795 1.1 fvdl maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2796 1.1 fvdl *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2797 1.1 fvdl } 2798 1.1 fvdl if (transinfo->period == 0) { 2799 1.1 fvdl *period = 0; 2800 1.1 fvdl *ppr_options = 0; 2801 1.1 fvdl } else { 2802 1.1 fvdl *period = MAX(*period, transinfo->period); 2803 1.1 fvdl ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2804 1.1 fvdl } 2805 1.1 fvdl } 2806 1.1 fvdl 2807 1.1 fvdl /* 2808 1.1 fvdl * Look up the valid period to SCSIRATE conversion in our table. 2809 1.1 fvdl * Return the period and offset that should be sent to the target 2810 1.1 fvdl * if this was the beginning of an SDTR. 2811 1.1 fvdl */ 2812 1.1 fvdl void 2813 1.36 christos ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2814 1.1 fvdl u_int *ppr_options, u_int maxsync) 2815 1.1 fvdl { 2816 1.1 fvdl if (*period < maxsync) 2817 1.1 fvdl *period = maxsync; 2818 1.1 fvdl 2819 1.1 fvdl if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2820 1.1 fvdl && *period > AHD_SYNCRATE_MIN_DT) 2821 1.1 fvdl *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2822 1.30 perry 2823 1.1 fvdl if (*period > AHD_SYNCRATE_MIN) 2824 1.1 fvdl *period = 0; 2825 1.1 fvdl 2826 1.1 fvdl /* Honor PPR option conformance rules. */ 2827 1.1 fvdl if (*period > AHD_SYNCRATE_PACED) 2828 1.1 fvdl *ppr_options &= ~MSG_EXT_PPR_RTI; 2829 1.1 fvdl 2830 1.1 fvdl if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2831 1.1 fvdl *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2832 1.1 fvdl 2833 1.1 fvdl if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2834 1.1 fvdl *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2835 1.1 fvdl 2836 1.1 fvdl /* Skip all PACED only entries if IU is not available */ 2837 1.1 fvdl if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2838 1.1 fvdl && *period < AHD_SYNCRATE_DT) 2839 1.1 fvdl *period = AHD_SYNCRATE_DT; 2840 1.1 fvdl 2841 1.1 fvdl /* Skip all DT only entries if DT is not available */ 2842 1.1 fvdl if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2843 1.1 fvdl && *period < AHD_SYNCRATE_ULTRA2) 2844 1.1 fvdl *period = AHD_SYNCRATE_ULTRA2; 2845 1.1 fvdl } 2846 1.1 fvdl 2847 1.1 fvdl /* 2848 1.1 fvdl * Truncate the given synchronous offset to a value the 2849 1.1 fvdl * current adapter type and syncrate are capable of. 2850 1.1 fvdl */ 2851 1.1 fvdl void 2852 1.1 fvdl ahd_validate_offset(struct ahd_softc *ahd, 2853 1.1 fvdl struct ahd_initiator_tinfo *tinfo, 2854 1.36 christos u_int period, u_int *offset, int wide, 2855 1.1 fvdl role_t role) 2856 1.1 fvdl { 2857 1.1 fvdl u_int maxoffset; 2858 1.1 fvdl 2859 1.1 fvdl /* Limit offset to what we can do */ 2860 1.1 fvdl if (period == 0) 2861 1.1 fvdl maxoffset = 0; 2862 1.1 fvdl else if (period <= AHD_SYNCRATE_PACED) { 2863 1.1 fvdl if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2864 1.1 fvdl maxoffset = MAX_OFFSET_PACED_BUG; 2865 1.1 fvdl else 2866 1.1 fvdl maxoffset = MAX_OFFSET_PACED; 2867 1.1 fvdl } else 2868 1.1 fvdl maxoffset = MAX_OFFSET_NON_PACED; 2869 1.1 fvdl *offset = MIN(*offset, maxoffset); 2870 1.1 fvdl if (tinfo != NULL) { 2871 1.1 fvdl if (role == ROLE_TARGET) 2872 1.1 fvdl *offset = MIN(*offset, tinfo->user.offset); 2873 1.1 fvdl else 2874 1.1 fvdl *offset = MIN(*offset, tinfo->goal.offset); 2875 1.1 fvdl } 2876 1.1 fvdl } 2877 1.1 fvdl 2878 1.1 fvdl /* 2879 1.1 fvdl * Truncate the given transfer width parameter to a value the 2880 1.1 fvdl * current adapter type is capable of. 2881 1.1 fvdl */ 2882 1.1 fvdl void 2883 1.1 fvdl ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2884 1.1 fvdl u_int *bus_width, role_t role) 2885 1.1 fvdl { 2886 1.1 fvdl switch (*bus_width) { 2887 1.1 fvdl default: 2888 1.1 fvdl if (ahd->features & AHD_WIDE) { 2889 1.1 fvdl /* Respond Wide */ 2890 1.1 fvdl *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2891 1.1 fvdl break; 2892 1.1 fvdl } 2893 1.1 fvdl /* FALLTHROUGH */ 2894 1.1 fvdl case MSG_EXT_WDTR_BUS_8_BIT: 2895 1.1 fvdl *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2896 1.1 fvdl break; 2897 1.1 fvdl } 2898 1.1 fvdl if (tinfo != NULL) { 2899 1.1 fvdl if (role == ROLE_TARGET) 2900 1.1 fvdl *bus_width = MIN(tinfo->user.width, *bus_width); 2901 1.1 fvdl else 2902 1.1 fvdl *bus_width = MIN(tinfo->goal.width, *bus_width); 2903 1.1 fvdl } 2904 1.1 fvdl } 2905 1.1 fvdl 2906 1.1 fvdl /* 2907 1.1 fvdl * Update the bitmask of targets for which the controller should 2908 1.26 wiz * negotiate with at the next convenient opportunity. This currently 2909 1.1 fvdl * means the next time we send the initial identify messages for 2910 1.1 fvdl * a new transaction. 2911 1.1 fvdl */ 2912 1.1 fvdl int 2913 1.1 fvdl ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2914 1.1 fvdl struct ahd_tmode_tstate *tstate, 2915 1.1 fvdl struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2916 1.1 fvdl { 2917 1.1 fvdl u_int auto_negotiate_orig; 2918 1.1 fvdl 2919 1.1 fvdl auto_negotiate_orig = tstate->auto_negotiate; 2920 1.1 fvdl if (neg_type == AHD_NEG_ALWAYS) { 2921 1.1 fvdl /* 2922 1.1 fvdl * Force our "current" settings to be 2923 1.1 fvdl * unknown so that unless a bus reset 2924 1.1 fvdl * occurs the need to renegotiate is 2925 1.1 fvdl * recorded persistently. 2926 1.1 fvdl */ 2927 1.1 fvdl if ((ahd->features & AHD_WIDE) != 0) 2928 1.1 fvdl tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2929 1.1 fvdl tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2930 1.1 fvdl tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2931 1.1 fvdl } 2932 1.1 fvdl if (tinfo->curr.period != tinfo->goal.period 2933 1.1 fvdl || tinfo->curr.width != tinfo->goal.width 2934 1.1 fvdl || tinfo->curr.offset != tinfo->goal.offset 2935 1.1 fvdl || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2936 1.1 fvdl || (neg_type == AHD_NEG_IF_NON_ASYNC 2937 1.1 fvdl && (tinfo->goal.offset != 0 2938 1.1 fvdl || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2939 1.1 fvdl || tinfo->goal.ppr_options != 0))) 2940 1.1 fvdl tstate->auto_negotiate |= devinfo->target_mask; 2941 1.1 fvdl else 2942 1.1 fvdl tstate->auto_negotiate &= ~devinfo->target_mask; 2943 1.1 fvdl 2944 1.1 fvdl return (auto_negotiate_orig != tstate->auto_negotiate); 2945 1.1 fvdl } 2946 1.1 fvdl 2947 1.1 fvdl /* 2948 1.1 fvdl * Update the user/goal/curr tables of synchronous negotiation 2949 1.1 fvdl * parameters as well as, in the case of a current or active update, 2950 1.1 fvdl * any data structures on the host controller. In the case of an 2951 1.1 fvdl * active update, the specified target is currently talking to us on 2952 1.1 fvdl * the bus, so the transfer parameter update must take effect 2953 1.1 fvdl * immediately. 2954 1.1 fvdl */ 2955 1.1 fvdl void 2956 1.1 fvdl ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2957 1.1 fvdl u_int period, u_int offset, u_int ppr_options, 2958 1.1 fvdl u_int type, int paused) 2959 1.1 fvdl { 2960 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 2961 1.1 fvdl struct ahd_tmode_tstate *tstate; 2962 1.1 fvdl u_int old_period; 2963 1.1 fvdl u_int old_offset; 2964 1.1 fvdl u_int old_ppr; 2965 1.1 fvdl int active; 2966 1.1 fvdl int update_needed; 2967 1.1 fvdl 2968 1.1 fvdl active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2969 1.1 fvdl update_needed = 0; 2970 1.1 fvdl 2971 1.1 fvdl if (period == 0 || offset == 0) { 2972 1.1 fvdl period = 0; 2973 1.1 fvdl offset = 0; 2974 1.1 fvdl } 2975 1.1 fvdl 2976 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2977 1.1 fvdl devinfo->target, &tstate); 2978 1.1 fvdl 2979 1.1 fvdl if ((type & AHD_TRANS_USER) != 0) { 2980 1.1 fvdl tinfo->user.period = period; 2981 1.1 fvdl tinfo->user.offset = offset; 2982 1.1 fvdl tinfo->user.ppr_options = ppr_options; 2983 1.1 fvdl } 2984 1.1 fvdl 2985 1.1 fvdl if ((type & AHD_TRANS_GOAL) != 0) { 2986 1.1 fvdl tinfo->goal.period = period; 2987 1.1 fvdl tinfo->goal.offset = offset; 2988 1.1 fvdl tinfo->goal.ppr_options = ppr_options; 2989 1.1 fvdl } 2990 1.1 fvdl 2991 1.1 fvdl old_period = tinfo->curr.period; 2992 1.1 fvdl old_offset = tinfo->curr.offset; 2993 1.43 tsutsui old_ppr = tinfo->curr.ppr_options; 2994 1.1 fvdl 2995 1.1 fvdl if ((type & AHD_TRANS_CUR) != 0 2996 1.1 fvdl && (old_period != period 2997 1.1 fvdl || old_offset != offset 2998 1.1 fvdl || old_ppr != ppr_options)) { 2999 1.1 fvdl 3000 1.1 fvdl update_needed++; 3001 1.1 fvdl 3002 1.1 fvdl tinfo->curr.period = period; 3003 1.1 fvdl tinfo->curr.offset = offset; 3004 1.1 fvdl tinfo->curr.ppr_options = ppr_options; 3005 1.1 fvdl 3006 1.1 fvdl ahd_send_async(ahd, devinfo->channel, devinfo->target, 3007 1.1 fvdl CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3008 1.1 fvdl 3009 1.1 fvdl if (bootverbose) { 3010 1.1 fvdl if (offset != 0) { 3011 1.1 fvdl int options; 3012 1.1 fvdl 3013 1.1 fvdl printf("%s: target %d synchronous with " 3014 1.1 fvdl "period = 0x%x, offset = 0x%x", 3015 1.1 fvdl ahd_name(ahd), devinfo->target, 3016 1.1 fvdl period, offset); 3017 1.1 fvdl options = 0; 3018 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3019 1.1 fvdl printf("(RDSTRM"); 3020 1.1 fvdl options++; 3021 1.1 fvdl } 3022 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3023 1.1 fvdl printf("%s", options ? "|DT" : "(DT"); 3024 1.1 fvdl options++; 3025 1.1 fvdl } 3026 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3027 1.1 fvdl printf("%s", options ? "|IU" : "(IU"); 3028 1.1 fvdl options++; 3029 1.1 fvdl } 3030 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3031 1.1 fvdl printf("%s", options ? "|RTI" : "(RTI"); 3032 1.1 fvdl options++; 3033 1.1 fvdl } 3034 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3035 1.1 fvdl printf("%s", options ? "|QAS" : "(QAS"); 3036 1.1 fvdl options++; 3037 1.1 fvdl } 3038 1.1 fvdl if (options != 0) 3039 1.1 fvdl printf(")\n"); 3040 1.1 fvdl else 3041 1.1 fvdl printf("\n"); 3042 1.1 fvdl } else { 3043 1.1 fvdl printf("%s: target %d using " 3044 1.1 fvdl "asynchronous transfers%s\n", 3045 1.1 fvdl ahd_name(ahd), devinfo->target, 3046 1.1 fvdl (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3047 1.1 fvdl ? "(QAS)" : ""); 3048 1.1 fvdl } 3049 1.1 fvdl } 3050 1.1 fvdl } 3051 1.1 fvdl /* 3052 1.1 fvdl * Always refresh the neg-table to handle the case of the 3053 1.1 fvdl * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3054 1.1 fvdl * We will always renegotiate in that case if this is a 3055 1.1 fvdl * packetized request. Also manage the busfree expected flag 3056 1.1 fvdl * from this common routine so that we catch changes due to 3057 1.1 fvdl * WDTR or SDTR messages. 3058 1.1 fvdl */ 3059 1.1 fvdl if ((type & AHD_TRANS_CUR) != 0) { 3060 1.1 fvdl if (!paused) 3061 1.1 fvdl ahd_pause(ahd); 3062 1.1 fvdl ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3063 1.1 fvdl if (!paused) 3064 1.1 fvdl ahd_unpause(ahd); 3065 1.1 fvdl if (ahd->msg_type != MSG_TYPE_NONE) { 3066 1.1 fvdl if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3067 1.1 fvdl != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3068 1.1 fvdl #ifdef AHD_DEBUG 3069 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3070 1.1 fvdl ahd_print_devinfo(ahd, devinfo); 3071 1.1 fvdl printf("Expecting IU Change busfree\n"); 3072 1.1 fvdl } 3073 1.1 fvdl #endif 3074 1.1 fvdl ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3075 1.1 fvdl | MSG_FLAG_IU_REQ_CHANGED; 3076 1.1 fvdl } 3077 1.1 fvdl if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3078 1.1 fvdl #ifdef AHD_DEBUG 3079 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3080 1.1 fvdl printf("PPR with IU_REQ outstanding\n"); 3081 1.1 fvdl #endif 3082 1.1 fvdl ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3083 1.1 fvdl } 3084 1.1 fvdl } 3085 1.1 fvdl } 3086 1.1 fvdl 3087 1.1 fvdl update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3088 1.1 fvdl tinfo, AHD_NEG_TO_GOAL); 3089 1.1 fvdl 3090 1.1 fvdl if (update_needed && active) 3091 1.1 fvdl ahd_update_pending_scbs(ahd); 3092 1.1 fvdl } 3093 1.1 fvdl 3094 1.1 fvdl /* 3095 1.1 fvdl * Update the user/goal/curr tables of wide negotiation 3096 1.1 fvdl * parameters as well as, in the case of a current or active update, 3097 1.1 fvdl * any data structures on the host controller. In the case of an 3098 1.1 fvdl * active update, the specified target is currently talking to us on 3099 1.1 fvdl * the bus, so the transfer parameter update must take effect 3100 1.1 fvdl * immediately. 3101 1.1 fvdl */ 3102 1.1 fvdl void 3103 1.1 fvdl ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3104 1.1 fvdl u_int width, u_int type, int paused) 3105 1.1 fvdl { 3106 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 3107 1.1 fvdl struct ahd_tmode_tstate *tstate; 3108 1.1 fvdl u_int oldwidth; 3109 1.1 fvdl int active; 3110 1.1 fvdl int update_needed; 3111 1.1 fvdl 3112 1.1 fvdl active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3113 1.1 fvdl update_needed = 0; 3114 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3115 1.1 fvdl devinfo->target, &tstate); 3116 1.1 fvdl 3117 1.1 fvdl if ((type & AHD_TRANS_USER) != 0) 3118 1.1 fvdl tinfo->user.width = width; 3119 1.1 fvdl 3120 1.1 fvdl if ((type & AHD_TRANS_GOAL) != 0) 3121 1.1 fvdl tinfo->goal.width = width; 3122 1.1 fvdl 3123 1.1 fvdl oldwidth = tinfo->curr.width; 3124 1.1 fvdl if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 3125 1.1 fvdl 3126 1.1 fvdl update_needed++; 3127 1.1 fvdl 3128 1.1 fvdl tinfo->curr.width = width; 3129 1.1 fvdl ahd_send_async(ahd, devinfo->channel, devinfo->target, 3130 1.1 fvdl CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3131 1.1 fvdl 3132 1.1 fvdl if (bootverbose) { 3133 1.1 fvdl printf("%s: target %d using %dbit transfers\n", 3134 1.1 fvdl ahd_name(ahd), devinfo->target, 3135 1.1 fvdl 8 * (0x01 << width)); 3136 1.1 fvdl } 3137 1.1 fvdl } 3138 1.1 fvdl 3139 1.1 fvdl if ((type & AHD_TRANS_CUR) != 0) { 3140 1.1 fvdl if (!paused) 3141 1.1 fvdl ahd_pause(ahd); 3142 1.1 fvdl ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3143 1.1 fvdl if (!paused) 3144 1.1 fvdl ahd_unpause(ahd); 3145 1.1 fvdl } 3146 1.1 fvdl 3147 1.1 fvdl update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3148 1.1 fvdl tinfo, AHD_NEG_TO_GOAL); 3149 1.1 fvdl if (update_needed && active) 3150 1.1 fvdl ahd_update_pending_scbs(ahd); 3151 1.1 fvdl 3152 1.1 fvdl } 3153 1.1 fvdl 3154 1.1 fvdl /* 3155 1.1 fvdl * Update the current state of tagged queuing for a given target. 3156 1.1 fvdl */ 3157 1.1 fvdl void 3158 1.1 fvdl ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3159 1.1 fvdl ahd_queue_alg alg) 3160 1.1 fvdl { 3161 1.1 fvdl ahd_platform_set_tags(ahd, devinfo, alg); 3162 1.1 fvdl ahd_send_async(ahd, devinfo->channel, devinfo->target, 3163 1.1 fvdl devinfo->lun, AC_TRANSFER_NEG, &alg); 3164 1.1 fvdl } 3165 1.1 fvdl 3166 1.1 fvdl static void 3167 1.1 fvdl ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3168 1.1 fvdl struct ahd_transinfo *tinfo) 3169 1.1 fvdl { 3170 1.1 fvdl ahd_mode_state saved_modes; 3171 1.1 fvdl u_int period; 3172 1.1 fvdl u_int ppr_opts; 3173 1.1 fvdl u_int con_opts; 3174 1.1 fvdl u_int offset; 3175 1.1 fvdl u_int saved_negoaddr; 3176 1.1 fvdl uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 3177 1.1 fvdl 3178 1.1 fvdl saved_modes = ahd_save_modes(ahd); 3179 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3180 1.1 fvdl 3181 1.1 fvdl saved_negoaddr = ahd_inb(ahd, NEGOADDR); 3182 1.1 fvdl ahd_outb(ahd, NEGOADDR, devinfo->target); 3183 1.1 fvdl period = tinfo->period; 3184 1.1 fvdl offset = tinfo->offset; 3185 1.30 perry memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 3186 1.1 fvdl ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 3187 1.1 fvdl |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 3188 1.1 fvdl con_opts = 0; 3189 1.1 fvdl if (period == 0) 3190 1.1 fvdl period = AHD_SYNCRATE_ASYNC; 3191 1.1 fvdl if (period == AHD_SYNCRATE_160) { 3192 1.1 fvdl 3193 1.1 fvdl if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3194 1.1 fvdl /* 3195 1.1 fvdl * When the SPI4 spec was finalized, PACE transfers 3196 1.1 fvdl * was not made a configurable option in the PPR 3197 1.1 fvdl * message. Instead it is assumed to be enabled for 3198 1.1 fvdl * any syncrate faster than 80MHz. Nevertheless, 3199 1.1 fvdl * Harpoon2A4 allows this to be configurable. 3200 1.1 fvdl * 3201 1.1 fvdl * Harpoon2A4 also assumes at most 2 data bytes per 3202 1.1 fvdl * negotiated REQ/ACK offset. Paced transfers take 3203 1.1 fvdl * 4, so we must adjust our offset. 3204 1.1 fvdl */ 3205 1.1 fvdl ppr_opts |= PPROPT_PACE; 3206 1.1 fvdl offset *= 2; 3207 1.1 fvdl 3208 1.1 fvdl /* 3209 1.1 fvdl * Harpoon2A assumed that there would be a 3210 1.34 lukem * fallback rate between 160 MHz and 80 MHz, 3211 1.1 fvdl * so 7 is used as the period factor rather 3212 1.1 fvdl * than 8 for 160MHz. 3213 1.1 fvdl */ 3214 1.1 fvdl period = AHD_SYNCRATE_REVA_160; 3215 1.1 fvdl } 3216 1.1 fvdl if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 3217 1.1 fvdl iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3218 1.1 fvdl ~AHD_PRECOMP_MASK; 3219 1.1 fvdl } else { 3220 1.1 fvdl /* 3221 1.1 fvdl * Precomp should be disabled for non-paced transfers. 3222 1.1 fvdl */ 3223 1.1 fvdl iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 3224 1.1 fvdl 3225 1.1 fvdl if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 3226 1.1 fvdl && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 3227 1.1 fvdl /* 3228 1.1 fvdl * Slow down our CRC interval to be 3229 1.1 fvdl * compatible with devices that can't 3230 1.1 fvdl * handle a CRC at full speed. 3231 1.1 fvdl */ 3232 1.1 fvdl con_opts |= ENSLOWCRC; 3233 1.1 fvdl } 3234 1.1 fvdl } 3235 1.1 fvdl 3236 1.1 fvdl ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 3237 1.1 fvdl ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 3238 1.1 fvdl ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 3239 1.1 fvdl ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 3240 1.1 fvdl 3241 1.1 fvdl ahd_outb(ahd, NEGPERIOD, period); 3242 1.1 fvdl ahd_outb(ahd, NEGPPROPTS, ppr_opts); 3243 1.1 fvdl ahd_outb(ahd, NEGOFFSET, offset); 3244 1.1 fvdl 3245 1.1 fvdl if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 3246 1.1 fvdl con_opts |= WIDEXFER; 3247 1.1 fvdl 3248 1.1 fvdl /* 3249 1.1 fvdl * During packetized transfers, the target will 3250 1.26 wiz * give us the opportunity to send command packets 3251 1.1 fvdl * without us asserting attention. 3252 1.1 fvdl */ 3253 1.1 fvdl if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3254 1.1 fvdl con_opts |= ENAUTOATNO; 3255 1.1 fvdl ahd_outb(ahd, NEGCONOPTS, con_opts); 3256 1.1 fvdl ahd_outb(ahd, NEGOADDR, saved_negoaddr); 3257 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 3258 1.1 fvdl } 3259 1.1 fvdl 3260 1.1 fvdl /* 3261 1.1 fvdl * When the transfer settings for a connection change, setup for 3262 1.1 fvdl * negotiation in pending SCBs to effect the change as quickly as 3263 1.1 fvdl * possible. We also cancel any negotiations that are scheduled 3264 1.1 fvdl * for inflight SCBs that have not been started yet. 3265 1.1 fvdl */ 3266 1.1 fvdl static void 3267 1.1 fvdl ahd_update_pending_scbs(struct ahd_softc *ahd) 3268 1.1 fvdl { 3269 1.1 fvdl struct scb *pending_scb; 3270 1.1 fvdl int pending_scb_count; 3271 1.20 thorpej u_int scb_tag; 3272 1.1 fvdl int paused; 3273 1.1 fvdl u_int saved_scbptr; 3274 1.1 fvdl ahd_mode_state saved_modes; 3275 1.1 fvdl 3276 1.1 fvdl /* 3277 1.1 fvdl * Traverse the pending SCB list and ensure that all of the 3278 1.1 fvdl * SCBs there have the proper settings. We can only safely 3279 1.1 fvdl * clear the negotiation required flag (setting requires the 3280 1.1 fvdl * execution queue to be modified) and this is only possible 3281 1.1 fvdl * if we are not already attempting to select out for this 3282 1.1 fvdl * SCB. For this reason, all callers only call this routine 3283 1.1 fvdl * if we are changing the negotiation settings for the currently 3284 1.1 fvdl * active transaction on the bus. 3285 1.1 fvdl */ 3286 1.1 fvdl pending_scb_count = 0; 3287 1.1 fvdl LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3288 1.1 fvdl struct ahd_devinfo devinfo; 3289 1.1 fvdl struct hardware_scb *pending_hscb; 3290 1.1 fvdl struct ahd_tmode_tstate *tstate; 3291 1.1 fvdl 3292 1.1 fvdl ahd_scb_devinfo(ahd, &devinfo, pending_scb); 3293 1.46 christos (void)ahd_fetch_transinfo(ahd, devinfo.channel, 3294 1.46 christos devinfo.our_scsiid, 3295 1.46 christos devinfo.target, &tstate); 3296 1.1 fvdl pending_hscb = pending_scb->hscb; 3297 1.1 fvdl if ((tstate->auto_negotiate & devinfo.target_mask) == 0 3298 1.1 fvdl && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 3299 1.1 fvdl pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 3300 1.1 fvdl pending_hscb->control &= ~MK_MESSAGE; 3301 1.1 fvdl } 3302 1.1 fvdl ahd_sync_scb(ahd, pending_scb, 3303 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3304 1.1 fvdl pending_scb_count++; 3305 1.1 fvdl } 3306 1.1 fvdl 3307 1.1 fvdl if (pending_scb_count == 0) 3308 1.1 fvdl return; 3309 1.1 fvdl 3310 1.1 fvdl if (ahd_is_paused(ahd)) { 3311 1.1 fvdl paused = 1; 3312 1.1 fvdl } else { 3313 1.1 fvdl paused = 0; 3314 1.1 fvdl ahd_pause(ahd); 3315 1.1 fvdl } 3316 1.1 fvdl 3317 1.1 fvdl /* 3318 1.1 fvdl * Force the sequencer to reinitialize the selection for 3319 1.1 fvdl * the command at the head of the execution queue if it 3320 1.1 fvdl * has already been setup. The negotiation changes may 3321 1.1 fvdl * effect whether we select-out with ATN. 3322 1.1 fvdl */ 3323 1.1 fvdl saved_modes = ahd_save_modes(ahd); 3324 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3325 1.1 fvdl ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3326 1.1 fvdl saved_scbptr = ahd_get_scbptr(ahd); 3327 1.1 fvdl /* Ensure that the hscbs down on the card match the new information */ 3328 1.20 thorpej for (scb_tag = 0; scb_tag < ahd->scb_data.maxhscbs; scb_tag++) { 3329 1.1 fvdl struct hardware_scb *pending_hscb; 3330 1.1 fvdl u_int control; 3331 1.1 fvdl 3332 1.1 fvdl pending_scb = ahd_lookup_scb(ahd, scb_tag); 3333 1.1 fvdl if (pending_scb == NULL) 3334 1.1 fvdl continue; 3335 1.20 thorpej ahd_set_scbptr(ahd, scb_tag); 3336 1.1 fvdl pending_hscb = pending_scb->hscb; 3337 1.1 fvdl control = ahd_inb_scbram(ahd, SCB_CONTROL); 3338 1.1 fvdl control &= ~MK_MESSAGE; 3339 1.1 fvdl control |= pending_hscb->control & MK_MESSAGE; 3340 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, control); 3341 1.1 fvdl } 3342 1.1 fvdl ahd_set_scbptr(ahd, saved_scbptr); 3343 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 3344 1.1 fvdl 3345 1.1 fvdl if (paused == 0) 3346 1.1 fvdl ahd_unpause(ahd); 3347 1.1 fvdl } 3348 1.1 fvdl 3349 1.1 fvdl /**************************** Pathing Information *****************************/ 3350 1.1 fvdl static void 3351 1.1 fvdl ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3352 1.1 fvdl { 3353 1.1 fvdl ahd_mode_state saved_modes; 3354 1.1 fvdl u_int saved_scsiid; 3355 1.1 fvdl role_t role; 3356 1.1 fvdl int our_id; 3357 1.1 fvdl 3358 1.1 fvdl saved_modes = ahd_save_modes(ahd); 3359 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3360 1.1 fvdl 3361 1.1 fvdl if (ahd_inb(ahd, SSTAT0) & TARGET) 3362 1.1 fvdl role = ROLE_TARGET; 3363 1.1 fvdl else 3364 1.1 fvdl role = ROLE_INITIATOR; 3365 1.1 fvdl 3366 1.1 fvdl if (role == ROLE_TARGET 3367 1.1 fvdl && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3368 1.1 fvdl /* We were selected, so pull our id from TARGIDIN */ 3369 1.1 fvdl our_id = ahd_inb(ahd, TARGIDIN) & OID; 3370 1.1 fvdl } else if (role == ROLE_TARGET) 3371 1.1 fvdl our_id = ahd_inb(ahd, TOWNID); 3372 1.1 fvdl else 3373 1.1 fvdl our_id = ahd_inb(ahd, IOWNID); 3374 1.1 fvdl 3375 1.1 fvdl saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3376 1.1 fvdl ahd_compile_devinfo(devinfo, 3377 1.1 fvdl our_id, 3378 1.1 fvdl SCSIID_TARGET(ahd, saved_scsiid), 3379 1.1 fvdl ahd_inb(ahd, SAVED_LUN), 3380 1.1 fvdl SCSIID_CHANNEL(ahd, saved_scsiid), 3381 1.1 fvdl role); 3382 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 3383 1.1 fvdl } 3384 1.1 fvdl 3385 1.1 fvdl void 3386 1.1 fvdl ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3387 1.1 fvdl { 3388 1.1 fvdl printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3389 1.1 fvdl devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3390 1.1 fvdl } 3391 1.1 fvdl 3392 1.1 fvdl struct ahd_phase_table_entry* 3393 1.1 fvdl ahd_lookup_phase_entry(int phase) 3394 1.1 fvdl { 3395 1.1 fvdl struct ahd_phase_table_entry *entry; 3396 1.1 fvdl struct ahd_phase_table_entry *last_entry; 3397 1.1 fvdl 3398 1.1 fvdl /* 3399 1.1 fvdl * num_phases doesn't include the default entry which 3400 1.1 fvdl * will be returned if the phase doesn't match. 3401 1.1 fvdl */ 3402 1.1 fvdl last_entry = &ahd_phase_table[num_phases]; 3403 1.1 fvdl for (entry = ahd_phase_table; entry < last_entry; entry++) { 3404 1.1 fvdl if (phase == entry->phase) 3405 1.1 fvdl break; 3406 1.1 fvdl } 3407 1.1 fvdl return (entry); 3408 1.1 fvdl } 3409 1.1 fvdl 3410 1.1 fvdl void 3411 1.1 fvdl ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3412 1.1 fvdl u_int lun, char channel, role_t role) 3413 1.1 fvdl { 3414 1.1 fvdl devinfo->our_scsiid = our_id; 3415 1.1 fvdl devinfo->target = target; 3416 1.1 fvdl devinfo->lun = lun; 3417 1.1 fvdl devinfo->target_offset = target; 3418 1.1 fvdl devinfo->channel = channel; 3419 1.1 fvdl devinfo->role = role; 3420 1.1 fvdl if (channel == 'B') 3421 1.1 fvdl devinfo->target_offset += 8; 3422 1.1 fvdl devinfo->target_mask = (0x01 << devinfo->target_offset); 3423 1.1 fvdl } 3424 1.1 fvdl 3425 1.1 fvdl static void 3426 1.36 christos ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3427 1.1 fvdl struct scb *scb) 3428 1.1 fvdl { 3429 1.1 fvdl role_t role; 3430 1.1 fvdl int our_id; 3431 1.1 fvdl 3432 1.1 fvdl our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3433 1.1 fvdl role = ROLE_INITIATOR; 3434 1.1 fvdl if ((scb->hscb->control & TARGET_SCB) != 0) 3435 1.1 fvdl role = ROLE_TARGET; 3436 1.1 fvdl ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3437 1.1 fvdl SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3438 1.1 fvdl } 3439 1.1 fvdl 3440 1.1 fvdl 3441 1.1 fvdl /************************ Message Phase Processing ****************************/ 3442 1.1 fvdl /* 3443 1.1 fvdl * When an initiator transaction with the MK_MESSAGE flag either reconnects 3444 1.1 fvdl * or enters the initial message out phase, we are interrupted. Fill our 3445 1.26 wiz * outgoing message buffer with the appropriate message and begin handing 3446 1.1 fvdl * the message phase(s) manually. 3447 1.1 fvdl */ 3448 1.1 fvdl static void 3449 1.1 fvdl ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3450 1.1 fvdl struct scb *scb) 3451 1.1 fvdl { 3452 1.1 fvdl /* 3453 1.1 fvdl * To facilitate adding multiple messages together, 3454 1.1 fvdl * each routine should increment the index and len 3455 1.1 fvdl * variables instead of setting them explicitly. 3456 1.1 fvdl */ 3457 1.1 fvdl ahd->msgout_index = 0; 3458 1.1 fvdl ahd->msgout_len = 0; 3459 1.1 fvdl 3460 1.1 fvdl if (ahd_currently_packetized(ahd)) 3461 1.1 fvdl ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3462 1.1 fvdl 3463 1.1 fvdl if (ahd->send_msg_perror 3464 1.1 fvdl && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3465 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3466 1.1 fvdl ahd->msgout_len++; 3467 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3468 1.1 fvdl #ifdef AHD_DEBUG 3469 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3470 1.1 fvdl printf("Setting up for Parity Error delivery\n"); 3471 1.1 fvdl #endif 3472 1.1 fvdl return; 3473 1.1 fvdl } else if (scb == NULL) { 3474 1.1 fvdl printf("%s: WARNING. No pending message for " 3475 1.1 fvdl "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3476 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3477 1.1 fvdl ahd->msgout_len++; 3478 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3479 1.1 fvdl return; 3480 1.1 fvdl } 3481 1.1 fvdl 3482 1.1 fvdl if ((scb->flags & SCB_DEVICE_RESET) == 0 3483 1.1 fvdl && (scb->flags & SCB_PACKETIZED) == 0 3484 1.1 fvdl && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3485 1.1 fvdl u_int identify_msg; 3486 1.1 fvdl 3487 1.1 fvdl identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3488 1.1 fvdl if ((scb->hscb->control & DISCENB) != 0) 3489 1.1 fvdl identify_msg |= MSG_IDENTIFY_DISCFLAG; 3490 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3491 1.1 fvdl ahd->msgout_len++; 3492 1.1 fvdl 3493 1.1 fvdl if ((scb->hscb->control & TAG_ENB) != 0) { 3494 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = 3495 1.1 fvdl scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3496 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3497 1.1 fvdl ahd->msgout_len += 2; 3498 1.1 fvdl } 3499 1.1 fvdl } 3500 1.1 fvdl 3501 1.1 fvdl if (scb->flags & SCB_DEVICE_RESET) { 3502 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3503 1.1 fvdl ahd->msgout_len++; 3504 1.1 fvdl ahd_print_path(ahd, scb); 3505 1.1 fvdl printf("Bus Device Reset Message Sent\n"); 3506 1.1 fvdl /* 3507 1.1 fvdl * Clear our selection hardware in advance of 3508 1.1 fvdl * the busfree. We may have an entry in the waiting 3509 1.1 fvdl * Q for this target, and we don't want to go about 3510 1.1 fvdl * selecting while we handle the busfree and blow it 3511 1.1 fvdl * away. 3512 1.1 fvdl */ 3513 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 3514 1.1 fvdl } else if ((scb->flags & SCB_ABORT) != 0) { 3515 1.1 fvdl 3516 1.1 fvdl if ((scb->hscb->control & TAG_ENB) != 0) { 3517 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3518 1.1 fvdl } else { 3519 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3520 1.1 fvdl } 3521 1.1 fvdl ahd->msgout_len++; 3522 1.1 fvdl ahd_print_path(ahd, scb); 3523 1.1 fvdl printf("Abort%s Message Sent\n", 3524 1.1 fvdl (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3525 1.1 fvdl /* 3526 1.1 fvdl * Clear our selection hardware in advance of 3527 1.1 fvdl * the busfree. We may have an entry in the waiting 3528 1.1 fvdl * Q for this target, and we don't want to go about 3529 1.1 fvdl * selecting while we handle the busfree and blow it 3530 1.1 fvdl * away. 3531 1.1 fvdl */ 3532 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 3533 1.1 fvdl } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3534 1.1 fvdl ahd_build_transfer_msg(ahd, devinfo); 3535 1.1 fvdl /* 3536 1.1 fvdl * Clear our selection hardware in advance of potential 3537 1.1 fvdl * PPR IU status change busfree. We may have an entry in 3538 1.1 fvdl * the waiting Q for this target, and we don't want to go 3539 1.1 fvdl * about selecting while we handle the busfree and blow 3540 1.1 fvdl * it away. 3541 1.1 fvdl */ 3542 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 3543 1.1 fvdl } else { 3544 1.1 fvdl printf("ahd_intr: AWAITING_MSG for an SCB that " 3545 1.1 fvdl "does not have a waiting message\n"); 3546 1.1 fvdl printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3547 1.1 fvdl devinfo->target_mask); 3548 1.1 fvdl panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3549 1.1 fvdl "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3550 1.21 thorpej ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3551 1.1 fvdl scb->flags); 3552 1.1 fvdl } 3553 1.1 fvdl 3554 1.1 fvdl /* 3555 1.1 fvdl * Clear the MK_MESSAGE flag from the SCB so we aren't 3556 1.1 fvdl * asked to send this message again. 3557 1.1 fvdl */ 3558 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, 3559 1.1 fvdl ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3560 1.1 fvdl scb->hscb->control &= ~MK_MESSAGE; 3561 1.1 fvdl ahd->msgout_index = 0; 3562 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3563 1.1 fvdl } 3564 1.1 fvdl 3565 1.1 fvdl /* 3566 1.1 fvdl * Build an appropriate transfer negotiation message for the 3567 1.1 fvdl * currently active target. 3568 1.1 fvdl */ 3569 1.1 fvdl static void 3570 1.1 fvdl ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3571 1.1 fvdl { 3572 1.1 fvdl /* 3573 1.1 fvdl * We need to initiate transfer negotiations. 3574 1.1 fvdl * If our current and goal settings are identical, 3575 1.1 fvdl * we want to renegotiate due to a check condition. 3576 1.1 fvdl */ 3577 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 3578 1.1 fvdl struct ahd_tmode_tstate *tstate; 3579 1.1 fvdl int dowide; 3580 1.1 fvdl int dosync; 3581 1.1 fvdl int doppr; 3582 1.1 fvdl u_int period; 3583 1.1 fvdl u_int ppr_options; 3584 1.1 fvdl u_int offset; 3585 1.1 fvdl 3586 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3587 1.1 fvdl devinfo->target, &tstate); 3588 1.1 fvdl /* 3589 1.1 fvdl * Filter our period based on the current connection. 3590 1.1 fvdl * If we can't perform DT transfers on this segment (not in LVD 3591 1.1 fvdl * mode for instance), then our decision to issue a PPR message 3592 1.1 fvdl * may change. 3593 1.1 fvdl */ 3594 1.1 fvdl period = tinfo->goal.period; 3595 1.16 thorpej offset = tinfo->goal.offset; 3596 1.1 fvdl ppr_options = tinfo->goal.ppr_options; 3597 1.1 fvdl /* Target initiated PPR is not allowed in the SCSI spec */ 3598 1.1 fvdl if (devinfo->role == ROLE_TARGET) 3599 1.1 fvdl ppr_options = 0; 3600 1.1 fvdl ahd_devlimited_syncrate(ahd, tinfo, &period, 3601 1.1 fvdl &ppr_options, devinfo->role); 3602 1.1 fvdl dowide = tinfo->curr.width != tinfo->goal.width; 3603 1.16 thorpej dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3604 1.1 fvdl /* 3605 1.1 fvdl * Only use PPR if we have options that need it, even if the device 3606 1.1 fvdl * claims to support it. There might be an expander in the way 3607 1.1 fvdl * that doesn't. 3608 1.1 fvdl */ 3609 1.1 fvdl doppr = ppr_options != 0; 3610 1.1 fvdl 3611 1.1 fvdl if (!dowide && !dosync && !doppr) { 3612 1.1 fvdl dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3613 1.16 thorpej dosync = tinfo->goal.offset != 0; 3614 1.1 fvdl } 3615 1.1 fvdl 3616 1.1 fvdl if (!dowide && !dosync && !doppr) { 3617 1.1 fvdl /* 3618 1.1 fvdl * Force async with a WDTR message if we have a wide bus, 3619 1.1 fvdl * or just issue an SDTR with a 0 offset. 3620 1.1 fvdl */ 3621 1.1 fvdl if ((ahd->features & AHD_WIDE) != 0) 3622 1.1 fvdl dowide = 1; 3623 1.1 fvdl else 3624 1.1 fvdl dosync = 1; 3625 1.1 fvdl 3626 1.1 fvdl if (bootverbose) { 3627 1.1 fvdl ahd_print_devinfo(ahd, devinfo); 3628 1.1 fvdl printf("Ensuring async\n"); 3629 1.1 fvdl } 3630 1.1 fvdl } 3631 1.1 fvdl /* Target initiated PPR is not allowed in the SCSI spec */ 3632 1.1 fvdl if (devinfo->role == ROLE_TARGET) 3633 1.1 fvdl doppr = 0; 3634 1.1 fvdl 3635 1.1 fvdl /* 3636 1.1 fvdl * Both the PPR message and SDTR message require the 3637 1.1 fvdl * goal syncrate to be limited to what the target device 3638 1.1 fvdl * is capable of handling (based on whether an LVD->SE 3639 1.1 fvdl * expander is on the bus), so combine these two cases. 3640 1.1 fvdl * Regardless, guarantee that if we are using WDTR and SDTR 3641 1.1 fvdl * messages that WDTR comes first. 3642 1.1 fvdl */ 3643 1.1 fvdl if (doppr || (dosync && !dowide)) { 3644 1.1 fvdl 3645 1.1 fvdl offset = tinfo->goal.offset; 3646 1.1 fvdl ahd_validate_offset(ahd, tinfo, period, &offset, 3647 1.1 fvdl doppr ? tinfo->goal.width 3648 1.1 fvdl : tinfo->curr.width, 3649 1.1 fvdl devinfo->role); 3650 1.1 fvdl if (doppr) { 3651 1.1 fvdl ahd_construct_ppr(ahd, devinfo, period, offset, 3652 1.1 fvdl tinfo->goal.width, ppr_options); 3653 1.1 fvdl } else { 3654 1.1 fvdl ahd_construct_sdtr(ahd, devinfo, period, offset); 3655 1.1 fvdl } 3656 1.1 fvdl } else { 3657 1.1 fvdl ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3658 1.1 fvdl } 3659 1.1 fvdl } 3660 1.1 fvdl 3661 1.1 fvdl /* 3662 1.1 fvdl * Build a synchronous negotiation message in our message 3663 1.1 fvdl * buffer based on the input parameters. 3664 1.1 fvdl */ 3665 1.1 fvdl static void 3666 1.1 fvdl ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3667 1.1 fvdl u_int period, u_int offset) 3668 1.1 fvdl { 3669 1.1 fvdl if (offset == 0) 3670 1.1 fvdl period = AHD_ASYNC_XFER_PERIOD; 3671 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3672 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3673 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3674 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = period; 3675 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = offset; 3676 1.1 fvdl ahd->msgout_len += 5; 3677 1.1 fvdl if (bootverbose) { 3678 1.1 fvdl printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3679 1.1 fvdl ahd_name(ahd), devinfo->channel, devinfo->target, 3680 1.1 fvdl devinfo->lun, period, offset); 3681 1.1 fvdl } 3682 1.1 fvdl } 3683 1.1 fvdl 3684 1.1 fvdl /* 3685 1.26 wiz * Build a wide negotiation message in our message 3686 1.1 fvdl * buffer based on the input parameters. 3687 1.1 fvdl */ 3688 1.1 fvdl static void 3689 1.1 fvdl ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3690 1.1 fvdl u_int bus_width) 3691 1.1 fvdl { 3692 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3693 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3694 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3695 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3696 1.1 fvdl ahd->msgout_len += 4; 3697 1.1 fvdl if (bootverbose) { 3698 1.1 fvdl printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3699 1.1 fvdl ahd_name(ahd), devinfo->channel, devinfo->target, 3700 1.1 fvdl devinfo->lun, bus_width); 3701 1.1 fvdl } 3702 1.1 fvdl } 3703 1.1 fvdl 3704 1.1 fvdl /* 3705 1.1 fvdl * Build a parallel protocol request message in our message 3706 1.1 fvdl * buffer based on the input parameters. 3707 1.1 fvdl */ 3708 1.1 fvdl static void 3709 1.1 fvdl ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3710 1.1 fvdl u_int period, u_int offset, u_int bus_width, 3711 1.1 fvdl u_int ppr_options) 3712 1.1 fvdl { 3713 1.1 fvdl /* 3714 1.1 fvdl * Always request precompensation from 3715 1.1 fvdl * the other target if we are running 3716 1.1 fvdl * at paced syncrates. 3717 1.1 fvdl */ 3718 1.1 fvdl if (period <= AHD_SYNCRATE_PACED) 3719 1.1 fvdl ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3720 1.1 fvdl if (offset == 0) 3721 1.1 fvdl period = AHD_ASYNC_XFER_PERIOD; 3722 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3723 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3724 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3725 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = period; 3726 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = 0; 3727 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = offset; 3728 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3729 1.1 fvdl ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3730 1.1 fvdl ahd->msgout_len += 8; 3731 1.1 fvdl if (bootverbose) { 3732 1.1 fvdl printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3733 1.1 fvdl "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3734 1.1 fvdl devinfo->channel, devinfo->target, devinfo->lun, 3735 1.1 fvdl bus_width, period, offset, ppr_options); 3736 1.1 fvdl } 3737 1.1 fvdl } 3738 1.1 fvdl 3739 1.1 fvdl /* 3740 1.1 fvdl * Clear any active message state. 3741 1.1 fvdl */ 3742 1.1 fvdl static void 3743 1.1 fvdl ahd_clear_msg_state(struct ahd_softc *ahd) 3744 1.1 fvdl { 3745 1.1 fvdl ahd_mode_state saved_modes; 3746 1.1 fvdl 3747 1.1 fvdl saved_modes = ahd_save_modes(ahd); 3748 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3749 1.1 fvdl ahd->send_msg_perror = 0; 3750 1.1 fvdl ahd->msg_flags = MSG_FLAG_NONE; 3751 1.1 fvdl ahd->msgout_len = 0; 3752 1.1 fvdl ahd->msgin_index = 0; 3753 1.1 fvdl ahd->msg_type = MSG_TYPE_NONE; 3754 1.1 fvdl if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3755 1.1 fvdl /* 3756 1.1 fvdl * The target didn't care to respond to our 3757 1.1 fvdl * message request, so clear ATN. 3758 1.1 fvdl */ 3759 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRATNO); 3760 1.1 fvdl } 3761 1.1 fvdl ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3762 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS2, 3763 1.1 fvdl ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3764 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 3765 1.1 fvdl } 3766 1.1 fvdl 3767 1.1 fvdl /* 3768 1.1 fvdl * Manual message loop handler. 3769 1.1 fvdl */ 3770 1.1 fvdl static void 3771 1.1 fvdl ahd_handle_message_phase(struct ahd_softc *ahd) 3772 1.30 perry { 3773 1.1 fvdl struct ahd_devinfo devinfo; 3774 1.1 fvdl u_int bus_phase; 3775 1.1 fvdl int end_session; 3776 1.1 fvdl 3777 1.1 fvdl ahd_fetch_devinfo(ahd, &devinfo); 3778 1.1 fvdl end_session = FALSE; 3779 1.1 fvdl bus_phase = ahd_inb(ahd, LASTPHASE); 3780 1.1 fvdl 3781 1.1 fvdl if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3782 1.1 fvdl printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3783 1.1 fvdl ahd_outb(ahd, LQCTL2, LQIRETRY); 3784 1.1 fvdl } 3785 1.1 fvdl reswitch: 3786 1.1 fvdl switch (ahd->msg_type) { 3787 1.1 fvdl case MSG_TYPE_INITIATOR_MSGOUT: 3788 1.1 fvdl { 3789 1.1 fvdl int lastbyte; 3790 1.1 fvdl int phasemis; 3791 1.1 fvdl int msgdone; 3792 1.1 fvdl 3793 1.1 fvdl if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3794 1.1 fvdl panic("HOST_MSG_LOOP interrupt with no active message"); 3795 1.1 fvdl 3796 1.1 fvdl #ifdef AHD_DEBUG 3797 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3798 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 3799 1.1 fvdl printf("INITIATOR_MSG_OUT"); 3800 1.1 fvdl } 3801 1.1 fvdl #endif 3802 1.1 fvdl phasemis = bus_phase != P_MESGOUT; 3803 1.1 fvdl if (phasemis) { 3804 1.1 fvdl #ifdef AHD_DEBUG 3805 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3806 1.1 fvdl printf(" PHASEMIS %s\n", 3807 1.1 fvdl ahd_lookup_phase_entry(bus_phase) 3808 1.1 fvdl ->phasemsg); 3809 1.1 fvdl } 3810 1.1 fvdl #endif 3811 1.1 fvdl if (bus_phase == P_MESGIN) { 3812 1.1 fvdl /* 3813 1.1 fvdl * Change gears and see if 3814 1.1 fvdl * this messages is of interest to 3815 1.1 fvdl * us or should be passed back to 3816 1.1 fvdl * the sequencer. 3817 1.1 fvdl */ 3818 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRATNO); 3819 1.1 fvdl ahd->send_msg_perror = 0; 3820 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3821 1.1 fvdl ahd->msgin_index = 0; 3822 1.1 fvdl goto reswitch; 3823 1.1 fvdl } 3824 1.1 fvdl end_session = TRUE; 3825 1.1 fvdl break; 3826 1.1 fvdl } 3827 1.1 fvdl 3828 1.1 fvdl if (ahd->send_msg_perror) { 3829 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRATNO); 3830 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3831 1.1 fvdl #ifdef AHD_DEBUG 3832 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3833 1.1 fvdl printf(" byte 0x%x\n", ahd->send_msg_perror); 3834 1.1 fvdl #endif 3835 1.1 fvdl /* 3836 1.1 fvdl * If we are notifying the target of a CRC error 3837 1.1 fvdl * during packetized operations, the target is 3838 1.1 fvdl * within its rights to acknowledge our message 3839 1.1 fvdl * with a busfree. 3840 1.1 fvdl */ 3841 1.1 fvdl if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3842 1.1 fvdl && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3843 1.1 fvdl ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3844 1.1 fvdl 3845 1.1 fvdl ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3846 1.1 fvdl ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3847 1.1 fvdl break; 3848 1.1 fvdl } 3849 1.1 fvdl 3850 1.1 fvdl msgdone = ahd->msgout_index == ahd->msgout_len; 3851 1.1 fvdl if (msgdone) { 3852 1.1 fvdl /* 3853 1.1 fvdl * The target has requested a retry. 3854 1.1 fvdl * Re-assert ATN, reset our message index to 3855 1.1 fvdl * 0, and try again. 3856 1.1 fvdl */ 3857 1.1 fvdl ahd->msgout_index = 0; 3858 1.1 fvdl ahd_assert_atn(ahd); 3859 1.1 fvdl } 3860 1.1 fvdl 3861 1.1 fvdl lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3862 1.1 fvdl if (lastbyte) { 3863 1.1 fvdl /* Last byte is signified by dropping ATN */ 3864 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRATNO); 3865 1.1 fvdl } 3866 1.1 fvdl 3867 1.1 fvdl /* 3868 1.1 fvdl * Clear our interrupt status and present 3869 1.1 fvdl * the next byte on the bus. 3870 1.1 fvdl */ 3871 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3872 1.1 fvdl #ifdef AHD_DEBUG 3873 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3874 1.1 fvdl printf(" byte 0x%x\n", 3875 1.1 fvdl ahd->msgout_buf[ahd->msgout_index]); 3876 1.1 fvdl #endif 3877 1.1 fvdl ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3878 1.1 fvdl ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3879 1.1 fvdl break; 3880 1.1 fvdl } 3881 1.1 fvdl case MSG_TYPE_INITIATOR_MSGIN: 3882 1.1 fvdl { 3883 1.1 fvdl int phasemis; 3884 1.1 fvdl int message_done; 3885 1.1 fvdl 3886 1.1 fvdl #ifdef AHD_DEBUG 3887 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3888 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 3889 1.1 fvdl printf("INITIATOR_MSG_IN"); 3890 1.1 fvdl } 3891 1.1 fvdl #endif 3892 1.1 fvdl phasemis = bus_phase != P_MESGIN; 3893 1.1 fvdl if (phasemis) { 3894 1.1 fvdl #ifdef AHD_DEBUG 3895 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3896 1.1 fvdl printf(" PHASEMIS %s\n", 3897 1.1 fvdl ahd_lookup_phase_entry(bus_phase) 3898 1.1 fvdl ->phasemsg); 3899 1.1 fvdl } 3900 1.1 fvdl #endif 3901 1.1 fvdl ahd->msgin_index = 0; 3902 1.1 fvdl if (bus_phase == P_MESGOUT 3903 1.1 fvdl && (ahd->send_msg_perror != 0 3904 1.1 fvdl || (ahd->msgout_len != 0 3905 1.1 fvdl && ahd->msgout_index == 0))) { 3906 1.1 fvdl ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3907 1.1 fvdl goto reswitch; 3908 1.1 fvdl } 3909 1.1 fvdl end_session = TRUE; 3910 1.1 fvdl break; 3911 1.1 fvdl } 3912 1.1 fvdl 3913 1.1 fvdl /* Pull the byte in without acking it */ 3914 1.1 fvdl ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3915 1.1 fvdl #ifdef AHD_DEBUG 3916 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3917 1.1 fvdl printf(" byte 0x%x\n", 3918 1.1 fvdl ahd->msgin_buf[ahd->msgin_index]); 3919 1.1 fvdl #endif 3920 1.1 fvdl 3921 1.1 fvdl message_done = ahd_parse_msg(ahd, &devinfo); 3922 1.1 fvdl 3923 1.1 fvdl if (message_done) { 3924 1.1 fvdl /* 3925 1.1 fvdl * Clear our incoming message buffer in case there 3926 1.1 fvdl * is another message following this one. 3927 1.1 fvdl */ 3928 1.1 fvdl ahd->msgin_index = 0; 3929 1.1 fvdl 3930 1.1 fvdl /* 3931 1.1 fvdl * If this message illicited a response, 3932 1.1 fvdl * assert ATN so the target takes us to the 3933 1.1 fvdl * message out phase. 3934 1.1 fvdl */ 3935 1.1 fvdl if (ahd->msgout_len != 0) { 3936 1.1 fvdl #ifdef AHD_DEBUG 3937 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3938 1.1 fvdl ahd_print_devinfo(ahd, &devinfo); 3939 1.1 fvdl printf("Asserting ATN for response\n"); 3940 1.1 fvdl } 3941 1.1 fvdl #endif 3942 1.1 fvdl ahd_assert_atn(ahd); 3943 1.1 fvdl } 3944 1.30 perry } else 3945 1.1 fvdl ahd->msgin_index++; 3946 1.1 fvdl 3947 1.1 fvdl if (message_done == MSGLOOP_TERMINATED) { 3948 1.1 fvdl end_session = TRUE; 3949 1.1 fvdl } else { 3950 1.1 fvdl /* Ack the byte */ 3951 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3952 1.1 fvdl ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3953 1.1 fvdl } 3954 1.1 fvdl break; 3955 1.1 fvdl } 3956 1.1 fvdl case MSG_TYPE_TARGET_MSGIN: 3957 1.1 fvdl { 3958 1.1 fvdl int msgdone; 3959 1.1 fvdl int msgout_request; 3960 1.1 fvdl 3961 1.1 fvdl /* 3962 1.1 fvdl * By default, the message loop will continue. 3963 1.1 fvdl */ 3964 1.1 fvdl ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3965 1.1 fvdl 3966 1.1 fvdl if (ahd->msgout_len == 0) 3967 1.1 fvdl panic("Target MSGIN with no active message"); 3968 1.1 fvdl 3969 1.1 fvdl /* 3970 1.1 fvdl * If we interrupted a mesgout session, the initiator 3971 1.1 fvdl * will not know this until our first REQ. So, we 3972 1.1 fvdl * only honor mesgout requests after we've sent our 3973 1.1 fvdl * first byte. 3974 1.1 fvdl */ 3975 1.1 fvdl if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3976 1.1 fvdl && ahd->msgout_index > 0) 3977 1.1 fvdl msgout_request = TRUE; 3978 1.1 fvdl else 3979 1.1 fvdl msgout_request = FALSE; 3980 1.1 fvdl 3981 1.1 fvdl if (msgout_request) { 3982 1.1 fvdl 3983 1.1 fvdl /* 3984 1.1 fvdl * Change gears and see if 3985 1.1 fvdl * this messages is of interest to 3986 1.1 fvdl * us or should be passed back to 3987 1.1 fvdl * the sequencer. 3988 1.1 fvdl */ 3989 1.1 fvdl ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3990 1.1 fvdl ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3991 1.1 fvdl ahd->msgin_index = 0; 3992 1.1 fvdl /* Dummy read to REQ for first byte */ 3993 1.1 fvdl ahd_inb(ahd, SCSIDAT); 3994 1.1 fvdl ahd_outb(ahd, SXFRCTL0, 3995 1.1 fvdl ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3996 1.1 fvdl break; 3997 1.1 fvdl } 3998 1.1 fvdl 3999 1.1 fvdl msgdone = ahd->msgout_index == ahd->msgout_len; 4000 1.1 fvdl if (msgdone) { 4001 1.1 fvdl ahd_outb(ahd, SXFRCTL0, 4002 1.1 fvdl ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4003 1.1 fvdl end_session = TRUE; 4004 1.1 fvdl break; 4005 1.1 fvdl } 4006 1.1 fvdl 4007 1.1 fvdl /* 4008 1.1 fvdl * Present the next byte on the bus. 4009 1.1 fvdl */ 4010 1.1 fvdl ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4011 1.1 fvdl ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4012 1.1 fvdl break; 4013 1.1 fvdl } 4014 1.1 fvdl case MSG_TYPE_TARGET_MSGOUT: 4015 1.1 fvdl { 4016 1.1 fvdl int lastbyte; 4017 1.1 fvdl int msgdone; 4018 1.1 fvdl 4019 1.1 fvdl /* 4020 1.1 fvdl * By default, the message loop will continue. 4021 1.1 fvdl */ 4022 1.1 fvdl ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4023 1.1 fvdl 4024 1.1 fvdl /* 4025 1.1 fvdl * The initiator signals that this is 4026 1.1 fvdl * the last byte by dropping ATN. 4027 1.1 fvdl */ 4028 1.1 fvdl lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4029 1.1 fvdl 4030 1.1 fvdl /* 4031 1.1 fvdl * Read the latched byte, but turn off SPIOEN first 4032 1.1 fvdl * so that we don't inadvertently cause a REQ for the 4033 1.1 fvdl * next byte. 4034 1.1 fvdl */ 4035 1.1 fvdl ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4036 1.1 fvdl ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4037 1.1 fvdl msgdone = ahd_parse_msg(ahd, &devinfo); 4038 1.1 fvdl if (msgdone == MSGLOOP_TERMINATED) { 4039 1.1 fvdl /* 4040 1.1 fvdl * The message is *really* done in that it caused 4041 1.1 fvdl * us to go to bus free. The sequencer has already 4042 1.1 fvdl * been reset at this point, so pull the ejection 4043 1.1 fvdl * handle. 4044 1.1 fvdl */ 4045 1.1 fvdl return; 4046 1.1 fvdl } 4047 1.30 perry 4048 1.1 fvdl ahd->msgin_index++; 4049 1.1 fvdl 4050 1.1 fvdl /* 4051 1.1 fvdl * XXX Read spec about initiator dropping ATN too soon 4052 1.1 fvdl * and use msgdone to detect it. 4053 1.1 fvdl */ 4054 1.1 fvdl if (msgdone == MSGLOOP_MSGCOMPLETE) { 4055 1.1 fvdl ahd->msgin_index = 0; 4056 1.1 fvdl 4057 1.1 fvdl /* 4058 1.1 fvdl * If this message illicited a response, transition 4059 1.1 fvdl * to the Message in phase and send it. 4060 1.1 fvdl */ 4061 1.1 fvdl if (ahd->msgout_len != 0) { 4062 1.1 fvdl ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4063 1.1 fvdl ahd_outb(ahd, SXFRCTL0, 4064 1.1 fvdl ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4065 1.1 fvdl ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4066 1.1 fvdl ahd->msgin_index = 0; 4067 1.1 fvdl break; 4068 1.1 fvdl } 4069 1.1 fvdl } 4070 1.1 fvdl 4071 1.1 fvdl if (lastbyte) 4072 1.1 fvdl end_session = TRUE; 4073 1.1 fvdl else { 4074 1.1 fvdl /* Ask for the next byte. */ 4075 1.1 fvdl ahd_outb(ahd, SXFRCTL0, 4076 1.1 fvdl ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4077 1.1 fvdl } 4078 1.1 fvdl 4079 1.1 fvdl break; 4080 1.1 fvdl } 4081 1.1 fvdl default: 4082 1.1 fvdl panic("Unknown REQINIT message type"); 4083 1.1 fvdl } 4084 1.1 fvdl 4085 1.1 fvdl if (end_session) { 4086 1.1 fvdl if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 4087 1.1 fvdl printf("%s: Returning to Idle Loop\n", 4088 1.1 fvdl ahd_name(ahd)); 4089 1.19 thorpej ahd_clear_msg_state(ahd); 4090 1.19 thorpej 4091 1.19 thorpej /* 4092 1.19 thorpej * Perform the equivalent of a clear_target_state. 4093 1.19 thorpej */ 4094 1.1 fvdl ahd_outb(ahd, LASTPHASE, P_BUSFREE); 4095 1.19 thorpej ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 4096 1.1 fvdl ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 4097 1.1 fvdl } else { 4098 1.1 fvdl ahd_clear_msg_state(ahd); 4099 1.1 fvdl ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 4100 1.1 fvdl } 4101 1.1 fvdl } 4102 1.1 fvdl } 4103 1.1 fvdl 4104 1.1 fvdl /* 4105 1.1 fvdl * See if we sent a particular extended message to the target. 4106 1.1 fvdl * If "full" is true, return true only if the target saw the full 4107 1.1 fvdl * message. If "full" is false, return true if the target saw at 4108 1.1 fvdl * least the first byte of the message. 4109 1.1 fvdl */ 4110 1.1 fvdl static int 4111 1.1 fvdl ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 4112 1.1 fvdl { 4113 1.1 fvdl int found; 4114 1.1 fvdl u_int index; 4115 1.1 fvdl 4116 1.1 fvdl found = FALSE; 4117 1.1 fvdl index = 0; 4118 1.1 fvdl 4119 1.1 fvdl while (index < ahd->msgout_len) { 4120 1.1 fvdl if (ahd->msgout_buf[index] == MSG_EXTENDED) { 4121 1.1 fvdl u_int end_index; 4122 1.1 fvdl 4123 1.1 fvdl end_index = index + 1 + ahd->msgout_buf[index + 1]; 4124 1.1 fvdl if (ahd->msgout_buf[index+2] == msgval 4125 1.1 fvdl && type == AHDMSG_EXT) { 4126 1.1 fvdl 4127 1.1 fvdl if (full) { 4128 1.1 fvdl if (ahd->msgout_index > end_index) 4129 1.1 fvdl found = TRUE; 4130 1.1 fvdl } else if (ahd->msgout_index > index) 4131 1.1 fvdl found = TRUE; 4132 1.1 fvdl } 4133 1.1 fvdl index = end_index; 4134 1.1 fvdl } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 4135 1.1 fvdl && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 4136 1.1 fvdl 4137 1.1 fvdl /* Skip tag type and tag id or residue param*/ 4138 1.1 fvdl index += 2; 4139 1.1 fvdl } else { 4140 1.1 fvdl /* Single byte message */ 4141 1.1 fvdl if (type == AHDMSG_1B 4142 1.1 fvdl && ahd->msgout_index > index 4143 1.1 fvdl && (ahd->msgout_buf[index] == msgval 4144 1.1 fvdl || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 4145 1.1 fvdl && msgval == MSG_IDENTIFYFLAG))) 4146 1.1 fvdl found = TRUE; 4147 1.1 fvdl index++; 4148 1.1 fvdl } 4149 1.1 fvdl 4150 1.1 fvdl if (found) 4151 1.1 fvdl break; 4152 1.1 fvdl } 4153 1.1 fvdl return (found); 4154 1.1 fvdl } 4155 1.1 fvdl 4156 1.1 fvdl /* 4157 1.1 fvdl * Wait for a complete incoming message, parse it, and respond accordingly. 4158 1.1 fvdl */ 4159 1.1 fvdl static int 4160 1.1 fvdl ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4161 1.1 fvdl { 4162 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 4163 1.1 fvdl struct ahd_tmode_tstate *tstate; 4164 1.1 fvdl int reject; 4165 1.1 fvdl int done; 4166 1.1 fvdl int response; 4167 1.1 fvdl 4168 1.1 fvdl done = MSGLOOP_IN_PROG; 4169 1.1 fvdl response = FALSE; 4170 1.1 fvdl reject = FALSE; 4171 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4172 1.1 fvdl devinfo->target, &tstate); 4173 1.1 fvdl 4174 1.1 fvdl /* 4175 1.1 fvdl * Parse as much of the message as is available, 4176 1.1 fvdl * rejecting it if we don't support it. When 4177 1.1 fvdl * the entire message is available and has been 4178 1.1 fvdl * handled, return MSGLOOP_MSGCOMPLETE, indicating 4179 1.1 fvdl * that we have parsed an entire message. 4180 1.1 fvdl * 4181 1.1 fvdl * In the case of extended messages, we accept the length 4182 1.1 fvdl * byte outright and perform more checking once we know the 4183 1.1 fvdl * extended message type. 4184 1.1 fvdl */ 4185 1.1 fvdl switch (ahd->msgin_buf[0]) { 4186 1.1 fvdl case MSG_DISCONNECT: 4187 1.1 fvdl case MSG_SAVEDATAPOINTER: 4188 1.1 fvdl case MSG_CMDCOMPLETE: 4189 1.1 fvdl case MSG_RESTOREPOINTERS: 4190 1.1 fvdl case MSG_IGN_WIDE_RESIDUE: 4191 1.1 fvdl /* 4192 1.1 fvdl * End our message loop as these are messages 4193 1.1 fvdl * the sequencer handles on its own. 4194 1.1 fvdl */ 4195 1.1 fvdl done = MSGLOOP_TERMINATED; 4196 1.1 fvdl break; 4197 1.1 fvdl case MSG_MESSAGE_REJECT: 4198 1.1 fvdl response = ahd_handle_msg_reject(ahd, devinfo); 4199 1.1 fvdl /* FALLTHROUGH */ 4200 1.1 fvdl case MSG_NOOP: 4201 1.1 fvdl done = MSGLOOP_MSGCOMPLETE; 4202 1.1 fvdl break; 4203 1.1 fvdl case MSG_EXTENDED: 4204 1.1 fvdl { 4205 1.1 fvdl /* Wait for enough of the message to begin validation */ 4206 1.1 fvdl if (ahd->msgin_index < 2) 4207 1.1 fvdl break; 4208 1.1 fvdl switch (ahd->msgin_buf[2]) { 4209 1.1 fvdl case MSG_EXT_SDTR: 4210 1.1 fvdl { 4211 1.1 fvdl u_int period; 4212 1.1 fvdl u_int ppr_options; 4213 1.1 fvdl u_int offset; 4214 1.1 fvdl u_int saved_offset; 4215 1.30 perry 4216 1.1 fvdl if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 4217 1.1 fvdl reject = TRUE; 4218 1.1 fvdl break; 4219 1.1 fvdl } 4220 1.1 fvdl 4221 1.1 fvdl /* 4222 1.1 fvdl * Wait until we have both args before validating 4223 1.1 fvdl * and acting on this message. 4224 1.1 fvdl * 4225 1.1 fvdl * Add one to MSG_EXT_SDTR_LEN to account for 4226 1.1 fvdl * the extended message preamble. 4227 1.1 fvdl */ 4228 1.1 fvdl if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 4229 1.1 fvdl break; 4230 1.1 fvdl 4231 1.1 fvdl period = ahd->msgin_buf[3]; 4232 1.1 fvdl ppr_options = 0; 4233 1.1 fvdl saved_offset = offset = ahd->msgin_buf[4]; 4234 1.1 fvdl ahd_devlimited_syncrate(ahd, tinfo, &period, 4235 1.1 fvdl &ppr_options, devinfo->role); 4236 1.1 fvdl ahd_validate_offset(ahd, tinfo, period, &offset, 4237 1.1 fvdl tinfo->curr.width, devinfo->role); 4238 1.1 fvdl if (bootverbose) { 4239 1.1 fvdl printf("(%s:%c:%d:%d): Received " 4240 1.1 fvdl "SDTR period %x, offset %x\n\t" 4241 1.1 fvdl "Filtered to period %x, offset %x\n", 4242 1.1 fvdl ahd_name(ahd), devinfo->channel, 4243 1.1 fvdl devinfo->target, devinfo->lun, 4244 1.1 fvdl ahd->msgin_buf[3], saved_offset, 4245 1.1 fvdl period, offset); 4246 1.1 fvdl } 4247 1.1 fvdl ahd_set_syncrate(ahd, devinfo, period, 4248 1.1 fvdl offset, ppr_options, 4249 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4250 1.1 fvdl /*paused*/TRUE); 4251 1.1 fvdl 4252 1.1 fvdl /* 4253 1.1 fvdl * See if we initiated Sync Negotiation 4254 1.1 fvdl * and didn't have to fall down to async 4255 1.1 fvdl * transfers. 4256 1.1 fvdl */ 4257 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 4258 1.1 fvdl /* We started it */ 4259 1.1 fvdl if (saved_offset != offset) { 4260 1.1 fvdl /* Went too low - force async */ 4261 1.1 fvdl reject = TRUE; 4262 1.1 fvdl } 4263 1.1 fvdl } else { 4264 1.1 fvdl /* 4265 1.1 fvdl * Send our own SDTR in reply 4266 1.1 fvdl */ 4267 1.43 tsutsui if (bootverbose 4268 1.1 fvdl && devinfo->role == ROLE_INITIATOR) { 4269 1.1 fvdl printf("(%s:%c:%d:%d): Target " 4270 1.1 fvdl "Initiated SDTR\n", 4271 1.1 fvdl ahd_name(ahd), devinfo->channel, 4272 1.1 fvdl devinfo->target, devinfo->lun); 4273 1.1 fvdl } 4274 1.1 fvdl ahd->msgout_index = 0; 4275 1.1 fvdl ahd->msgout_len = 0; 4276 1.1 fvdl ahd_construct_sdtr(ahd, devinfo, 4277 1.1 fvdl period, offset); 4278 1.1 fvdl ahd->msgout_index = 0; 4279 1.1 fvdl response = TRUE; 4280 1.1 fvdl } 4281 1.1 fvdl done = MSGLOOP_MSGCOMPLETE; 4282 1.1 fvdl break; 4283 1.1 fvdl } 4284 1.1 fvdl case MSG_EXT_WDTR: 4285 1.1 fvdl { 4286 1.1 fvdl u_int bus_width; 4287 1.1 fvdl u_int saved_width; 4288 1.1 fvdl u_int sending_reply; 4289 1.1 fvdl 4290 1.1 fvdl sending_reply = FALSE; 4291 1.1 fvdl if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 4292 1.1 fvdl reject = TRUE; 4293 1.1 fvdl break; 4294 1.1 fvdl } 4295 1.1 fvdl 4296 1.1 fvdl /* 4297 1.1 fvdl * Wait until we have our arg before validating 4298 1.1 fvdl * and acting on this message. 4299 1.1 fvdl * 4300 1.1 fvdl * Add one to MSG_EXT_WDTR_LEN to account for 4301 1.1 fvdl * the extended message preamble. 4302 1.1 fvdl */ 4303 1.1 fvdl if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 4304 1.1 fvdl break; 4305 1.1 fvdl 4306 1.1 fvdl bus_width = ahd->msgin_buf[3]; 4307 1.1 fvdl saved_width = bus_width; 4308 1.1 fvdl ahd_validate_width(ahd, tinfo, &bus_width, 4309 1.1 fvdl devinfo->role); 4310 1.1 fvdl if (bootverbose) { 4311 1.1 fvdl printf("(%s:%c:%d:%d): Received WDTR " 4312 1.1 fvdl "%x filtered to %x\n", 4313 1.1 fvdl ahd_name(ahd), devinfo->channel, 4314 1.1 fvdl devinfo->target, devinfo->lun, 4315 1.1 fvdl saved_width, bus_width); 4316 1.1 fvdl } 4317 1.1 fvdl 4318 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4319 1.1 fvdl /* 4320 1.1 fvdl * Don't send a WDTR back to the 4321 1.1 fvdl * target, since we asked first. 4322 1.1 fvdl * If the width went higher than our 4323 1.1 fvdl * request, reject it. 4324 1.1 fvdl */ 4325 1.1 fvdl if (saved_width > bus_width) { 4326 1.1 fvdl reject = TRUE; 4327 1.1 fvdl printf("(%s:%c:%d:%d): requested %dBit " 4328 1.1 fvdl "transfers. Rejecting...\n", 4329 1.1 fvdl ahd_name(ahd), devinfo->channel, 4330 1.1 fvdl devinfo->target, devinfo->lun, 4331 1.1 fvdl 8 * (0x01 << bus_width)); 4332 1.1 fvdl bus_width = 0; 4333 1.1 fvdl } 4334 1.1 fvdl } else { 4335 1.1 fvdl /* 4336 1.1 fvdl * Send our own WDTR in reply 4337 1.1 fvdl */ 4338 1.1 fvdl if (bootverbose 4339 1.1 fvdl && devinfo->role == ROLE_INITIATOR) { 4340 1.43 tsutsui printf("(%s:%c:%d:%d): Target " 4341 1.1 fvdl "Initiated WDTR\n", 4342 1.1 fvdl ahd_name(ahd), devinfo->channel, 4343 1.1 fvdl devinfo->target, devinfo->lun); 4344 1.1 fvdl } 4345 1.1 fvdl ahd->msgout_index = 0; 4346 1.1 fvdl ahd->msgout_len = 0; 4347 1.1 fvdl ahd_construct_wdtr(ahd, devinfo, bus_width); 4348 1.1 fvdl ahd->msgout_index = 0; 4349 1.1 fvdl response = TRUE; 4350 1.1 fvdl sending_reply = TRUE; 4351 1.1 fvdl } 4352 1.16 thorpej /* 4353 1.16 thorpej * After a wide message, we are async, but 4354 1.16 thorpej * some devices don't seem to honor this portion 4355 1.16 thorpej * of the spec. Force a renegotiation of the 4356 1.16 thorpej * sync component of our transfer agreement even 4357 1.16 thorpej * if our goal is async. By updating our width 4358 1.16 thorpej * after forcing the negotiation, we avoid 4359 1.16 thorpej * renegotiating for width. 4360 1.16 thorpej */ 4361 1.16 thorpej ahd_update_neg_request(ahd, devinfo, tstate, 4362 1.16 thorpej tinfo, AHD_NEG_ALWAYS); 4363 1.1 fvdl ahd_set_width(ahd, devinfo, bus_width, 4364 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4365 1.1 fvdl /*paused*/TRUE); 4366 1.1 fvdl if (sending_reply == FALSE && reject == FALSE) { 4367 1.1 fvdl 4368 1.16 thorpej /* 4369 1.16 thorpej * We will always have an SDTR to send. 4370 1.16 thorpej */ 4371 1.16 thorpej ahd->msgout_index = 0; 4372 1.16 thorpej ahd->msgout_len = 0; 4373 1.16 thorpej ahd_build_transfer_msg(ahd, devinfo); 4374 1.16 thorpej ahd->msgout_index = 0; 4375 1.16 thorpej response = TRUE; 4376 1.1 fvdl } 4377 1.1 fvdl done = MSGLOOP_MSGCOMPLETE; 4378 1.1 fvdl break; 4379 1.1 fvdl } 4380 1.1 fvdl case MSG_EXT_PPR: 4381 1.1 fvdl { 4382 1.1 fvdl u_int period; 4383 1.1 fvdl u_int offset; 4384 1.1 fvdl u_int bus_width; 4385 1.1 fvdl u_int ppr_options; 4386 1.1 fvdl u_int saved_width; 4387 1.1 fvdl u_int saved_offset; 4388 1.1 fvdl u_int saved_ppr_options; 4389 1.1 fvdl 4390 1.1 fvdl if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4391 1.1 fvdl reject = TRUE; 4392 1.1 fvdl break; 4393 1.1 fvdl } 4394 1.1 fvdl 4395 1.1 fvdl /* 4396 1.1 fvdl * Wait until we have all args before validating 4397 1.1 fvdl * and acting on this message. 4398 1.1 fvdl * 4399 1.1 fvdl * Add one to MSG_EXT_PPR_LEN to account for 4400 1.1 fvdl * the extended message preamble. 4401 1.1 fvdl */ 4402 1.1 fvdl if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4403 1.1 fvdl break; 4404 1.1 fvdl 4405 1.1 fvdl period = ahd->msgin_buf[3]; 4406 1.1 fvdl offset = ahd->msgin_buf[5]; 4407 1.1 fvdl bus_width = ahd->msgin_buf[6]; 4408 1.1 fvdl saved_width = bus_width; 4409 1.1 fvdl ppr_options = ahd->msgin_buf[7]; 4410 1.1 fvdl /* 4411 1.1 fvdl * According to the spec, a DT only 4412 1.1 fvdl * period factor with no DT option 4413 1.1 fvdl * set implies async. 4414 1.1 fvdl */ 4415 1.1 fvdl if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4416 1.1 fvdl && period <= 9) 4417 1.1 fvdl offset = 0; 4418 1.1 fvdl saved_ppr_options = ppr_options; 4419 1.1 fvdl saved_offset = offset; 4420 1.1 fvdl 4421 1.1 fvdl /* 4422 1.1 fvdl * Transfer options are only available if we 4423 1.1 fvdl * are negotiating wide. 4424 1.1 fvdl */ 4425 1.1 fvdl if (bus_width == 0) 4426 1.1 fvdl ppr_options &= MSG_EXT_PPR_QAS_REQ; 4427 1.1 fvdl 4428 1.1 fvdl ahd_validate_width(ahd, tinfo, &bus_width, 4429 1.1 fvdl devinfo->role); 4430 1.1 fvdl ahd_devlimited_syncrate(ahd, tinfo, &period, 4431 1.1 fvdl &ppr_options, devinfo->role); 4432 1.1 fvdl ahd_validate_offset(ahd, tinfo, period, &offset, 4433 1.1 fvdl bus_width, devinfo->role); 4434 1.1 fvdl 4435 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4436 1.1 fvdl /* 4437 1.1 fvdl * If we are unable to do any of the 4438 1.1 fvdl * requested options (we went too low), 4439 1.1 fvdl * then we'll have to reject the message. 4440 1.1 fvdl */ 4441 1.1 fvdl if (saved_width > bus_width 4442 1.1 fvdl || saved_offset != offset 4443 1.1 fvdl || saved_ppr_options != ppr_options) { 4444 1.1 fvdl reject = TRUE; 4445 1.1 fvdl period = 0; 4446 1.1 fvdl offset = 0; 4447 1.1 fvdl bus_width = 0; 4448 1.1 fvdl ppr_options = 0; 4449 1.1 fvdl } 4450 1.1 fvdl } else { 4451 1.1 fvdl if (devinfo->role != ROLE_TARGET) 4452 1.1 fvdl printf("(%s:%c:%d:%d): Target " 4453 1.1 fvdl "Initiated PPR\n", 4454 1.1 fvdl ahd_name(ahd), devinfo->channel, 4455 1.1 fvdl devinfo->target, devinfo->lun); 4456 1.1 fvdl else 4457 1.1 fvdl printf("(%s:%c:%d:%d): Initiator " 4458 1.1 fvdl "Initiated PPR\n", 4459 1.1 fvdl ahd_name(ahd), devinfo->channel, 4460 1.1 fvdl devinfo->target, devinfo->lun); 4461 1.1 fvdl ahd->msgout_index = 0; 4462 1.1 fvdl ahd->msgout_len = 0; 4463 1.1 fvdl ahd_construct_ppr(ahd, devinfo, period, offset, 4464 1.1 fvdl bus_width, ppr_options); 4465 1.1 fvdl ahd->msgout_index = 0; 4466 1.1 fvdl response = TRUE; 4467 1.1 fvdl } 4468 1.1 fvdl if (bootverbose) { 4469 1.1 fvdl printf("(%s:%c:%d:%d): Received PPR width %x, " 4470 1.1 fvdl "period %x, offset %x,options %x\n" 4471 1.1 fvdl "\tFiltered to width %x, period %x, " 4472 1.1 fvdl "offset %x, options %x\n", 4473 1.1 fvdl ahd_name(ahd), devinfo->channel, 4474 1.1 fvdl devinfo->target, devinfo->lun, 4475 1.1 fvdl saved_width, ahd->msgin_buf[3], 4476 1.1 fvdl saved_offset, saved_ppr_options, 4477 1.1 fvdl bus_width, period, offset, ppr_options); 4478 1.1 fvdl } 4479 1.1 fvdl ahd_set_width(ahd, devinfo, bus_width, 4480 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4481 1.1 fvdl /*paused*/TRUE); 4482 1.1 fvdl ahd_set_syncrate(ahd, devinfo, period, 4483 1.1 fvdl offset, ppr_options, 4484 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4485 1.1 fvdl /*paused*/TRUE); 4486 1.1 fvdl 4487 1.1 fvdl done = MSGLOOP_MSGCOMPLETE; 4488 1.1 fvdl break; 4489 1.1 fvdl } 4490 1.1 fvdl default: 4491 1.1 fvdl /* Unknown extended message. Reject it. */ 4492 1.1 fvdl reject = TRUE; 4493 1.1 fvdl break; 4494 1.1 fvdl } 4495 1.1 fvdl break; 4496 1.1 fvdl } 4497 1.1 fvdl #ifdef AHD_TARGET_MODE 4498 1.1 fvdl case MSG_BUS_DEV_RESET: 4499 1.1 fvdl ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4500 1.1 fvdl CAM_BDR_SENT, 4501 1.1 fvdl "Bus Device Reset Received", 4502 1.1 fvdl /*verbose_level*/0); 4503 1.1 fvdl ahd_restart(ahd); 4504 1.1 fvdl done = MSGLOOP_TERMINATED; 4505 1.1 fvdl break; 4506 1.1 fvdl case MSG_ABORT_TAG: 4507 1.1 fvdl case MSG_ABORT: 4508 1.1 fvdl case MSG_CLEAR_QUEUE: 4509 1.1 fvdl { 4510 1.1 fvdl int tag; 4511 1.1 fvdl 4512 1.1 fvdl /* Target mode messages */ 4513 1.1 fvdl if (devinfo->role != ROLE_TARGET) { 4514 1.1 fvdl reject = TRUE; 4515 1.1 fvdl break; 4516 1.1 fvdl } 4517 1.1 fvdl tag = SCB_LIST_NULL; 4518 1.1 fvdl if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4519 1.1 fvdl tag = ahd_inb(ahd, INITIATOR_TAG); 4520 1.1 fvdl ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4521 1.1 fvdl devinfo->lun, tag, ROLE_TARGET, 4522 1.1 fvdl CAM_REQ_ABORTED); 4523 1.1 fvdl 4524 1.1 fvdl tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4525 1.1 fvdl if (tstate != NULL) { 4526 1.1 fvdl struct ahd_tmode_lstate* lstate; 4527 1.1 fvdl 4528 1.1 fvdl lstate = tstate->enabled_luns[devinfo->lun]; 4529 1.1 fvdl if (lstate != NULL) { 4530 1.1 fvdl ahd_queue_lstate_event(ahd, lstate, 4531 1.1 fvdl devinfo->our_scsiid, 4532 1.1 fvdl ahd->msgin_buf[0], 4533 1.1 fvdl /*arg*/tag); 4534 1.1 fvdl ahd_send_lstate_events(ahd, lstate); 4535 1.1 fvdl } 4536 1.1 fvdl } 4537 1.1 fvdl ahd_restart(ahd); 4538 1.1 fvdl done = MSGLOOP_TERMINATED; 4539 1.1 fvdl break; 4540 1.1 fvdl } 4541 1.1 fvdl #endif 4542 1.1 fvdl case MSG_QAS_REQUEST: 4543 1.1 fvdl #ifdef AHD_DEBUG 4544 1.1 fvdl if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4545 1.1 fvdl printf("%s: QAS request. SCSISIGI == 0x%x\n", 4546 1.1 fvdl ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4547 1.1 fvdl #endif 4548 1.1 fvdl ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4549 1.1 fvdl /* FALLTHROUGH */ 4550 1.1 fvdl case MSG_TERM_IO_PROC: 4551 1.1 fvdl default: 4552 1.1 fvdl reject = TRUE; 4553 1.1 fvdl break; 4554 1.1 fvdl } 4555 1.1 fvdl 4556 1.1 fvdl if (reject) { 4557 1.1 fvdl /* 4558 1.1 fvdl * Setup to reject the message. 4559 1.1 fvdl */ 4560 1.1 fvdl ahd->msgout_index = 0; 4561 1.1 fvdl ahd->msgout_len = 1; 4562 1.1 fvdl ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4563 1.1 fvdl done = MSGLOOP_MSGCOMPLETE; 4564 1.1 fvdl response = TRUE; 4565 1.1 fvdl } 4566 1.1 fvdl 4567 1.1 fvdl if (done != MSGLOOP_IN_PROG && !response) 4568 1.1 fvdl /* Clear the outgoing message buffer */ 4569 1.1 fvdl ahd->msgout_len = 0; 4570 1.1 fvdl 4571 1.1 fvdl return (done); 4572 1.1 fvdl } 4573 1.1 fvdl 4574 1.1 fvdl /* 4575 1.1 fvdl * Process a message reject message. 4576 1.1 fvdl */ 4577 1.1 fvdl static int 4578 1.1 fvdl ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4579 1.1 fvdl { 4580 1.1 fvdl /* 4581 1.1 fvdl * What we care about here is if we had an 4582 1.1 fvdl * outstanding SDTR or WDTR message for this 4583 1.1 fvdl * target. If we did, this is a signal that 4584 1.1 fvdl * the target is refusing negotiation. 4585 1.1 fvdl */ 4586 1.1 fvdl struct scb *scb; 4587 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 4588 1.1 fvdl struct ahd_tmode_tstate *tstate; 4589 1.1 fvdl u_int scb_index; 4590 1.1 fvdl u_int last_msg; 4591 1.1 fvdl int response = 0; 4592 1.1 fvdl 4593 1.1 fvdl scb_index = ahd_get_scbptr(ahd); 4594 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 4595 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4596 1.1 fvdl devinfo->our_scsiid, 4597 1.1 fvdl devinfo->target, &tstate); 4598 1.1 fvdl /* Might be necessary */ 4599 1.1 fvdl last_msg = ahd_inb(ahd, LAST_MSG); 4600 1.1 fvdl 4601 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4602 1.1 fvdl if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4603 1.1 fvdl && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4604 1.1 fvdl /* 4605 1.1 fvdl * Target may not like our SPI-4 PPR Options. 4606 1.1 fvdl * Attempt to negotiate 80MHz which will turn 4607 1.1 fvdl * off these options. 4608 1.1 fvdl */ 4609 1.43 tsutsui if (bootverbose) { 4610 1.1 fvdl printf("(%s:%c:%d:%d): PPR Rejected. " 4611 1.1 fvdl "Trying simple U160 PPR\n", 4612 1.1 fvdl ahd_name(ahd), devinfo->channel, 4613 1.1 fvdl devinfo->target, devinfo->lun); 4614 1.1 fvdl } 4615 1.1 fvdl tinfo->goal.period = AHD_SYNCRATE_DT; 4616 1.1 fvdl tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4617 1.1 fvdl | MSG_EXT_PPR_QAS_REQ 4618 1.1 fvdl | MSG_EXT_PPR_DT_REQ; 4619 1.1 fvdl } else { 4620 1.1 fvdl /* 4621 1.1 fvdl * Target does not support the PPR message. 4622 1.1 fvdl * Attempt to negotiate SPI-2 style. 4623 1.1 fvdl */ 4624 1.43 tsutsui if (bootverbose) { 4625 1.1 fvdl printf("(%s:%c:%d:%d): PPR Rejected. " 4626 1.1 fvdl "Trying WDTR/SDTR\n", 4627 1.1 fvdl ahd_name(ahd), devinfo->channel, 4628 1.1 fvdl devinfo->target, devinfo->lun); 4629 1.1 fvdl } 4630 1.1 fvdl tinfo->goal.ppr_options = 0; 4631 1.1 fvdl tinfo->curr.transport_version = 2; 4632 1.1 fvdl tinfo->goal.transport_version = 2; 4633 1.1 fvdl } 4634 1.1 fvdl ahd->msgout_index = 0; 4635 1.1 fvdl ahd->msgout_len = 0; 4636 1.1 fvdl ahd_build_transfer_msg(ahd, devinfo); 4637 1.1 fvdl ahd->msgout_index = 0; 4638 1.1 fvdl response = 1; 4639 1.1 fvdl } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4640 1.1 fvdl 4641 1.1 fvdl /* note 8bit xfers */ 4642 1.1 fvdl printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4643 1.1 fvdl "8bit transfers\n", ahd_name(ahd), 4644 1.1 fvdl devinfo->channel, devinfo->target, devinfo->lun); 4645 1.1 fvdl ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4646 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4647 1.1 fvdl /*paused*/TRUE); 4648 1.1 fvdl /* 4649 1.1 fvdl * No need to clear the sync rate. If the target 4650 1.1 fvdl * did not accept the command, our syncrate is 4651 1.1 fvdl * unaffected. If the target started the negotiation, 4652 1.1 fvdl * but rejected our response, we already cleared the 4653 1.1 fvdl * sync rate before sending our WDTR. 4654 1.1 fvdl */ 4655 1.1 fvdl if (tinfo->goal.offset != tinfo->curr.offset) { 4656 1.1 fvdl 4657 1.1 fvdl /* Start the sync negotiation */ 4658 1.1 fvdl ahd->msgout_index = 0; 4659 1.1 fvdl ahd->msgout_len = 0; 4660 1.1 fvdl ahd_build_transfer_msg(ahd, devinfo); 4661 1.1 fvdl ahd->msgout_index = 0; 4662 1.1 fvdl response = 1; 4663 1.1 fvdl } 4664 1.1 fvdl } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4665 1.1 fvdl /* note asynch xfers and clear flag */ 4666 1.1 fvdl ahd_set_syncrate(ahd, devinfo, /*period*/0, 4667 1.1 fvdl /*offset*/0, /*ppr_options*/0, 4668 1.1 fvdl AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4669 1.1 fvdl /*paused*/TRUE); 4670 1.1 fvdl printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4671 1.1 fvdl "Using asynchronous transfers\n", 4672 1.1 fvdl ahd_name(ahd), devinfo->channel, 4673 1.1 fvdl devinfo->target, devinfo->lun); 4674 1.1 fvdl } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4675 1.1 fvdl int tag_type; 4676 1.1 fvdl int mask; 4677 1.1 fvdl 4678 1.1 fvdl tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4679 1.1 fvdl 4680 1.1 fvdl if (tag_type == MSG_SIMPLE_TASK) { 4681 1.1 fvdl printf("(%s:%c:%d:%d): refuses tagged commands. " 4682 1.1 fvdl "Performing non-tagged I/O\n", ahd_name(ahd), 4683 1.1 fvdl devinfo->channel, devinfo->target, devinfo->lun); 4684 1.1 fvdl ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4685 1.1 fvdl mask = ~0x23; 4686 1.1 fvdl } else { 4687 1.1 fvdl printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4688 1.1 fvdl "Performing simple queue tagged I/O only\n", 4689 1.1 fvdl ahd_name(ahd), devinfo->channel, devinfo->target, 4690 1.1 fvdl devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4691 1.1 fvdl ? "ordered" : "head of queue"); 4692 1.1 fvdl ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4693 1.1 fvdl mask = ~0x03; 4694 1.1 fvdl } 4695 1.1 fvdl 4696 1.1 fvdl /* 4697 1.1 fvdl * Resend the identify for this CCB as the target 4698 1.1 fvdl * may believe that the selection is invalid otherwise. 4699 1.1 fvdl */ 4700 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, 4701 1.1 fvdl ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4702 1.43 tsutsui scb->hscb->control &= mask; 4703 1.1 fvdl ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4704 1.1 fvdl /*type*/MSG_SIMPLE_TASK); 4705 1.1 fvdl ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4706 1.1 fvdl ahd_assert_atn(ahd); 4707 1.1 fvdl ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4708 1.1 fvdl SCB_GET_TAG(scb)); 4709 1.1 fvdl 4710 1.1 fvdl /* 4711 1.1 fvdl * Requeue all tagged commands for this target 4712 1.26 wiz * currently in our possession so they can be 4713 1.1 fvdl * converted to untagged commands. 4714 1.1 fvdl */ 4715 1.1 fvdl ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4716 1.1 fvdl SCB_GET_CHANNEL(ahd, scb), 4717 1.1 fvdl SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4718 1.1 fvdl ROLE_INITIATOR, CAM_REQUEUE_REQ, 4719 1.1 fvdl SEARCH_COMPLETE); 4720 1.1 fvdl } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4721 1.1 fvdl /* 4722 1.1 fvdl * Most likely the device believes that we had 4723 1.1 fvdl * previously negotiated packetized. 4724 1.1 fvdl */ 4725 1.1 fvdl ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4726 1.1 fvdl | MSG_FLAG_IU_REQ_CHANGED; 4727 1.1 fvdl 4728 1.1 fvdl ahd_force_renegotiation(ahd, devinfo); 4729 1.1 fvdl ahd->msgout_index = 0; 4730 1.1 fvdl ahd->msgout_len = 0; 4731 1.1 fvdl ahd_build_transfer_msg(ahd, devinfo); 4732 1.1 fvdl ahd->msgout_index = 0; 4733 1.1 fvdl response = 1; 4734 1.1 fvdl } else { 4735 1.1 fvdl /* 4736 1.1 fvdl * Otherwise, we ignore it. 4737 1.1 fvdl */ 4738 1.1 fvdl printf("%s:%c:%d: Message reject for %x -- ignored\n", 4739 1.1 fvdl ahd_name(ahd), devinfo->channel, devinfo->target, 4740 1.1 fvdl last_msg); 4741 1.1 fvdl } 4742 1.1 fvdl return (response); 4743 1.1 fvdl } 4744 1.1 fvdl 4745 1.1 fvdl /* 4746 1.1 fvdl * Process an ignore wide residue message. 4747 1.1 fvdl */ 4748 1.1 fvdl static void 4749 1.35 christos ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 4750 1.36 christos struct ahd_devinfo *devinfo) 4751 1.1 fvdl { 4752 1.1 fvdl u_int scb_index; 4753 1.1 fvdl struct scb *scb; 4754 1.1 fvdl 4755 1.1 fvdl printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4756 1.1 fvdl 4757 1.1 fvdl scb_index = ahd_get_scbptr(ahd); 4758 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 4759 1.1 fvdl /* 4760 1.1 fvdl * XXX Actually check data direction in the sequencer? 4761 1.1 fvdl * Perhaps add datadir to some spare bits in the hscb? 4762 1.1 fvdl */ 4763 1.1 fvdl if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4764 1.1 fvdl || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4765 1.1 fvdl /* 4766 1.1 fvdl * Ignore the message if we haven't 4767 1.1 fvdl * seen an appropriate data phase yet. 4768 1.1 fvdl */ 4769 1.1 fvdl } else { 4770 1.1 fvdl /* 4771 1.1 fvdl * If the residual occurred on the last 4772 1.1 fvdl * transfer and the transfer request was 4773 1.1 fvdl * expected to end on an odd count, do 4774 1.1 fvdl * nothing. Otherwise, subtract a byte 4775 1.1 fvdl * and update the residual count accordingly. 4776 1.1 fvdl */ 4777 1.1 fvdl uint32_t sgptr; 4778 1.1 fvdl 4779 1.1 fvdl sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4780 1.1 fvdl if ((sgptr & SG_LIST_NULL) != 0 4781 1.21 thorpej && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4782 1.21 thorpej & SCB_XFERLEN_ODD) != 0) { 4783 1.1 fvdl /* 4784 1.1 fvdl * If the residual occurred on the last 4785 1.1 fvdl * transfer and the transfer request was 4786 1.1 fvdl * expected to end on an odd count, do 4787 1.1 fvdl * nothing. 4788 1.1 fvdl */ 4789 1.1 fvdl } else { 4790 1.1 fvdl uint32_t data_cnt; 4791 1.1 fvdl uint64_t data_addr; 4792 1.1 fvdl uint32_t sglen; 4793 1.1 fvdl 4794 1.1 fvdl /* Pull in the rest of the sgptr */ 4795 1.11 thorpej sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4796 1.11 thorpej data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4797 1.11 thorpej if ((sgptr & SG_LIST_NULL) != 0) { 4798 1.11 thorpej /* 4799 1.11 thorpej * The residual data count is not updated 4800 1.11 thorpej * for the command run to completion case. 4801 1.63 msaitoh * Explicitly zero the count. 4802 1.11 thorpej */ 4803 1.11 thorpej data_cnt &= ~AHD_SG_LEN_MASK; 4804 1.11 thorpej } 4805 1.11 thorpej data_addr = ahd_inq(ahd, SHADDR); 4806 1.1 fvdl data_cnt += 1; 4807 1.1 fvdl data_addr -= 1; 4808 1.11 thorpej sgptr &= SG_PTR_MASK; 4809 1.1 fvdl if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4810 1.1 fvdl struct ahd_dma64_seg *sg; 4811 1.1 fvdl 4812 1.1 fvdl sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4813 1.1 fvdl 4814 1.1 fvdl /* 4815 1.1 fvdl * The residual sg ptr points to the next S/G 4816 1.1 fvdl * to load so we must go back one. 4817 1.1 fvdl */ 4818 1.1 fvdl sg--; 4819 1.1 fvdl sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4820 1.1 fvdl if (sg != scb->sg_list 4821 1.1 fvdl && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4822 1.1 fvdl 4823 1.1 fvdl sg--; 4824 1.1 fvdl sglen = ahd_le32toh(sg->len); 4825 1.1 fvdl /* 4826 1.1 fvdl * Preserve High Address and SG_LIST 4827 1.1 fvdl * bits while setting the count to 1. 4828 1.1 fvdl */ 4829 1.1 fvdl data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4830 1.1 fvdl data_addr = ahd_le64toh(sg->addr) 4831 1.1 fvdl + (sglen & AHD_SG_LEN_MASK) 4832 1.1 fvdl - 1; 4833 1.1 fvdl 4834 1.1 fvdl /* 4835 1.1 fvdl * Increment sg so it points to the 4836 1.1 fvdl * "next" sg. 4837 1.1 fvdl */ 4838 1.1 fvdl sg++; 4839 1.1 fvdl sgptr = ahd_sg_virt_to_bus(ahd, scb, 4840 1.1 fvdl sg); 4841 1.1 fvdl } 4842 1.1 fvdl } else { 4843 1.1 fvdl struct ahd_dma_seg *sg; 4844 1.1 fvdl 4845 1.1 fvdl sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4846 1.1 fvdl 4847 1.1 fvdl /* 4848 1.1 fvdl * The residual sg ptr points to the next S/G 4849 1.1 fvdl * to load so we must go back one. 4850 1.1 fvdl */ 4851 1.1 fvdl sg--; 4852 1.1 fvdl sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4853 1.1 fvdl if (sg != scb->sg_list 4854 1.1 fvdl && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4855 1.1 fvdl 4856 1.1 fvdl sg--; 4857 1.1 fvdl sglen = ahd_le32toh(sg->len); 4858 1.1 fvdl /* 4859 1.1 fvdl * Preserve High Address and SG_LIST 4860 1.1 fvdl * bits while setting the count to 1. 4861 1.1 fvdl */ 4862 1.1 fvdl data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4863 1.1 fvdl data_addr = ahd_le32toh(sg->addr) 4864 1.1 fvdl + (sglen & AHD_SG_LEN_MASK) 4865 1.1 fvdl - 1; 4866 1.1 fvdl 4867 1.1 fvdl /* 4868 1.1 fvdl * Increment sg so it points to the 4869 1.1 fvdl * "next" sg. 4870 1.1 fvdl */ 4871 1.1 fvdl sg++; 4872 1.1 fvdl sgptr = ahd_sg_virt_to_bus(ahd, scb, 4873 1.43 tsutsui sg); 4874 1.1 fvdl } 4875 1.1 fvdl } 4876 1.11 thorpej /* 4877 1.11 thorpej * Toggle the "oddness" of the transfer length 4878 1.11 thorpej * to handle this mid-transfer ignore wide 4879 1.11 thorpej * residue. This ensures that the oddness is 4880 1.11 thorpej * correct for subsequent data transfers. 4881 1.11 thorpej */ 4882 1.11 thorpej ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4883 1.21 thorpej ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4884 1.21 thorpej ^ SCB_XFERLEN_ODD); 4885 1.1 fvdl 4886 1.11 thorpej ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4887 1.11 thorpej ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4888 1.1 fvdl /* 4889 1.1 fvdl * The FIFO's pointers will be updated if/when the 4890 1.1 fvdl * sequencer re-enters a data phase. 4891 1.1 fvdl */ 4892 1.1 fvdl } 4893 1.1 fvdl } 4894 1.1 fvdl } 4895 1.1 fvdl 4896 1.1 fvdl 4897 1.1 fvdl /* 4898 1.1 fvdl * Reinitialize the data pointers for the active transfer 4899 1.1 fvdl * based on its current residual. 4900 1.1 fvdl */ 4901 1.1 fvdl static void 4902 1.1 fvdl ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4903 1.1 fvdl { 4904 1.1 fvdl struct scb *scb; 4905 1.1 fvdl ahd_mode_state saved_modes; 4906 1.1 fvdl u_int scb_index; 4907 1.1 fvdl u_int wait; 4908 1.1 fvdl uint32_t sgptr; 4909 1.1 fvdl uint32_t resid; 4910 1.1 fvdl uint64_t dataptr; 4911 1.1 fvdl 4912 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4913 1.1 fvdl AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4914 1.30 perry 4915 1.1 fvdl scb_index = ahd_get_scbptr(ahd); 4916 1.1 fvdl scb = ahd_lookup_scb(ahd, scb_index); 4917 1.1 fvdl 4918 1.1 fvdl /* 4919 1.1 fvdl * Release and reacquire the FIFO so we 4920 1.1 fvdl * have a clean slate. 4921 1.1 fvdl */ 4922 1.1 fvdl ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4923 1.1 fvdl wait = 1000; 4924 1.19 thorpej while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 4925 1.1 fvdl ahd_delay(100); 4926 1.1 fvdl if (wait == 0) { 4927 1.1 fvdl ahd_print_path(ahd, scb); 4928 1.1 fvdl printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4929 1.1 fvdl ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4930 1.1 fvdl } 4931 1.1 fvdl saved_modes = ahd_save_modes(ahd); 4932 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4933 1.1 fvdl ahd_outb(ahd, DFFSTAT, 4934 1.1 fvdl ahd_inb(ahd, DFFSTAT) 4935 1.1 fvdl | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4936 1.1 fvdl 4937 1.1 fvdl /* 4938 1.1 fvdl * Determine initial values for data_addr and data_cnt 4939 1.1 fvdl * for resuming the data phase. 4940 1.1 fvdl */ 4941 1.1 fvdl sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4942 1.1 fvdl | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4943 1.1 fvdl | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4944 1.1 fvdl | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4945 1.1 fvdl sgptr &= SG_PTR_MASK; 4946 1.1 fvdl 4947 1.1 fvdl resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4948 1.1 fvdl | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4949 1.1 fvdl | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4950 1.1 fvdl 4951 1.1 fvdl if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4952 1.1 fvdl struct ahd_dma64_seg *sg; 4953 1.1 fvdl 4954 1.1 fvdl sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4955 1.1 fvdl 4956 1.1 fvdl /* The residual sg_ptr always points to the next sg */ 4957 1.1 fvdl sg--; 4958 1.1 fvdl 4959 1.1 fvdl dataptr = ahd_le64toh(sg->addr) 4960 1.1 fvdl + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4961 1.1 fvdl - resid; 4962 1.1 fvdl ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4963 1.1 fvdl ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4964 1.1 fvdl ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4965 1.1 fvdl ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4966 1.1 fvdl } else { 4967 1.1 fvdl struct ahd_dma_seg *sg; 4968 1.1 fvdl 4969 1.1 fvdl sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4970 1.1 fvdl 4971 1.1 fvdl /* The residual sg_ptr always points to the next sg */ 4972 1.1 fvdl sg--; 4973 1.1 fvdl 4974 1.1 fvdl dataptr = ahd_le32toh(sg->addr) 4975 1.1 fvdl + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4976 1.1 fvdl - resid; 4977 1.1 fvdl ahd_outb(ahd, HADDR + 4, 4978 1.1 fvdl (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4979 1.1 fvdl } 4980 1.1 fvdl ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4981 1.1 fvdl ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4982 1.1 fvdl ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4983 1.1 fvdl ahd_outb(ahd, HADDR, dataptr); 4984 1.1 fvdl ahd_outb(ahd, HCNT + 2, resid >> 16); 4985 1.1 fvdl ahd_outb(ahd, HCNT + 1, resid >> 8); 4986 1.1 fvdl ahd_outb(ahd, HCNT, resid); 4987 1.1 fvdl } 4988 1.1 fvdl 4989 1.1 fvdl /* 4990 1.1 fvdl * Handle the effects of issuing a bus device reset message. 4991 1.1 fvdl */ 4992 1.1 fvdl static void 4993 1.1 fvdl ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4994 1.31 christos u_int lun, cam_status status, const char *message, 4995 1.1 fvdl int verbose_level) 4996 1.1 fvdl { 4997 1.1 fvdl #ifdef AHD_TARGET_MODE 4998 1.1 fvdl struct ahd_tmode_tstate* tstate; 4999 1.1 fvdl #endif 5000 1.1 fvdl int found; 5001 1.1 fvdl 5002 1.1 fvdl found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5003 1.1 fvdl lun, SCB_LIST_NULL, devinfo->role, 5004 1.1 fvdl status); 5005 1.1 fvdl 5006 1.1 fvdl #ifdef AHD_TARGET_MODE 5007 1.1 fvdl /* 5008 1.1 fvdl * Send an immediate notify ccb to all target mord peripheral 5009 1.1 fvdl * drivers affected by this action. 5010 1.1 fvdl */ 5011 1.1 fvdl tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5012 1.1 fvdl if (tstate != NULL) { 5013 1.1 fvdl u_int cur_lun; 5014 1.1 fvdl u_int max_lun; 5015 1.1 fvdl 5016 1.1 fvdl if (lun != CAM_LUN_WILDCARD) { 5017 1.1 fvdl cur_lun = 0; 5018 1.1 fvdl max_lun = AHD_NUM_LUNS - 1; 5019 1.1 fvdl } else { 5020 1.1 fvdl cur_lun = lun; 5021 1.1 fvdl max_lun = lun; 5022 1.1 fvdl } 5023 1.1 fvdl for (cur_lun <= max_lun; cur_lun++) { 5024 1.1 fvdl struct ahd_tmode_lstate* lstate; 5025 1.1 fvdl 5026 1.1 fvdl lstate = tstate->enabled_luns[cur_lun]; 5027 1.1 fvdl if (lstate == NULL) 5028 1.1 fvdl continue; 5029 1.1 fvdl 5030 1.1 fvdl ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5031 1.1 fvdl MSG_BUS_DEV_RESET, /*arg*/0); 5032 1.1 fvdl ahd_send_lstate_events(ahd, lstate); 5033 1.1 fvdl } 5034 1.1 fvdl } 5035 1.1 fvdl #endif 5036 1.1 fvdl 5037 1.1 fvdl /* 5038 1.1 fvdl * Go back to async/narrow transfers and renegotiate. 5039 1.1 fvdl */ 5040 1.1 fvdl ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5041 1.1 fvdl AHD_TRANS_CUR, /*paused*/TRUE); 5042 1.1 fvdl ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5043 1.1 fvdl /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 5044 1.1 fvdl 5045 1.1 fvdl ahd_send_async(ahd, devinfo->channel, devinfo->target, 5046 1.1 fvdl lun, AC_SENT_BDR, NULL); 5047 1.30 perry 5048 1.1 fvdl if (message != NULL 5049 1.1 fvdl && (verbose_level <= bootverbose)) 5050 1.1 fvdl printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5051 1.1 fvdl message, devinfo->channel, devinfo->target, found); 5052 1.1 fvdl } 5053 1.1 fvdl 5054 1.1 fvdl #ifdef AHD_TARGET_MODE 5055 1.1 fvdl static void 5056 1.1 fvdl ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5057 1.1 fvdl struct scb *scb) 5058 1.1 fvdl { 5059 1.1 fvdl 5060 1.30 perry /* 5061 1.1 fvdl * To facilitate adding multiple messages together, 5062 1.1 fvdl * each routine should increment the index and len 5063 1.1 fvdl * variables instead of setting them explicitly. 5064 1.30 perry */ 5065 1.1 fvdl ahd->msgout_index = 0; 5066 1.1 fvdl ahd->msgout_len = 0; 5067 1.1 fvdl 5068 1.1 fvdl if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5069 1.1 fvdl ahd_build_transfer_msg(ahd, devinfo); 5070 1.1 fvdl else 5071 1.1 fvdl panic("ahd_intr: AWAITING target message with no message"); 5072 1.1 fvdl 5073 1.1 fvdl ahd->msgout_index = 0; 5074 1.1 fvdl ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5075 1.1 fvdl } 5076 1.1 fvdl #endif 5077 1.1 fvdl /**************************** Initialization **********************************/ 5078 1.1 fvdl static u_int 5079 1.1 fvdl ahd_sglist_size(struct ahd_softc *ahd) 5080 1.1 fvdl { 5081 1.1 fvdl bus_size_t list_size; 5082 1.1 fvdl 5083 1.1 fvdl list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5084 1.1 fvdl if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5085 1.1 fvdl list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5086 1.1 fvdl return (list_size); 5087 1.1 fvdl } 5088 1.1 fvdl 5089 1.1 fvdl /* 5090 1.1 fvdl * Calculate the optimum S/G List allocation size. S/G elements used 5091 1.1 fvdl * for a given transaction must be physically contiguous. Assume the 5092 1.1 fvdl * OS will allocate full pages to us, so it doesn't make sense to request 5093 1.1 fvdl * less than a page. 5094 1.1 fvdl */ 5095 1.1 fvdl static u_int 5096 1.1 fvdl ahd_sglist_allocsize(struct ahd_softc *ahd) 5097 1.1 fvdl { 5098 1.1 fvdl bus_size_t sg_list_increment; 5099 1.1 fvdl bus_size_t sg_list_size; 5100 1.1 fvdl bus_size_t max_list_size; 5101 1.1 fvdl bus_size_t best_list_size; 5102 1.1 fvdl 5103 1.1 fvdl /* Start out with the minimum required for AHD_NSEG. */ 5104 1.1 fvdl sg_list_increment = ahd_sglist_size(ahd); 5105 1.1 fvdl sg_list_size = sg_list_increment; 5106 1.1 fvdl 5107 1.1 fvdl /* Get us as close as possible to a page in size. */ 5108 1.1 fvdl while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 5109 1.1 fvdl sg_list_size += sg_list_increment; 5110 1.1 fvdl 5111 1.1 fvdl /* 5112 1.1 fvdl * Try to reduce the amount of wastage by allocating 5113 1.1 fvdl * multiple pages. 5114 1.1 fvdl */ 5115 1.1 fvdl best_list_size = sg_list_size; 5116 1.1 fvdl max_list_size = roundup(sg_list_increment, PAGE_SIZE); 5117 1.1 fvdl if (max_list_size < 4 * PAGE_SIZE) 5118 1.1 fvdl max_list_size = 4 * PAGE_SIZE; 5119 1.1 fvdl if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 5120 1.1 fvdl max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 5121 1.1 fvdl while ((sg_list_size + sg_list_increment) <= max_list_size 5122 1.1 fvdl && (sg_list_size % PAGE_SIZE) != 0) { 5123 1.1 fvdl bus_size_t new_mod; 5124 1.1 fvdl bus_size_t best_mod; 5125 1.1 fvdl 5126 1.1 fvdl sg_list_size += sg_list_increment; 5127 1.1 fvdl new_mod = sg_list_size % PAGE_SIZE; 5128 1.1 fvdl best_mod = best_list_size % PAGE_SIZE; 5129 1.1 fvdl if (new_mod > best_mod || new_mod == 0) { 5130 1.1 fvdl best_list_size = sg_list_size; 5131 1.1 fvdl } 5132 1.1 fvdl } 5133 1.1 fvdl return (best_list_size); 5134 1.1 fvdl } 5135 1.1 fvdl 5136 1.1 fvdl int 5137 1.1 fvdl ahd_softc_init(struct ahd_softc *ahd) 5138 1.1 fvdl { 5139 1.1 fvdl 5140 1.1 fvdl ahd->unpause = 0; 5141 1.30 perry ahd->pause = PAUSE; 5142 1.1 fvdl return (0); 5143 1.1 fvdl } 5144 1.1 fvdl 5145 1.1 fvdl void 5146 1.1 fvdl ahd_set_unit(struct ahd_softc *ahd, int unit) 5147 1.1 fvdl { 5148 1.1 fvdl ahd->unit = unit; 5149 1.1 fvdl } 5150 1.1 fvdl 5151 1.1 fvdl void 5152 1.38 dyoung ahd_set_name(struct ahd_softc *ahd, const char *name) 5153 1.1 fvdl { 5154 1.1 fvdl ahd->name = name; 5155 1.1 fvdl } 5156 1.1 fvdl 5157 1.1 fvdl void 5158 1.1 fvdl ahd_free(struct ahd_softc *ahd) 5159 1.1 fvdl { 5160 1.1 fvdl int i; 5161 1.1 fvdl 5162 1.1 fvdl switch (ahd->init_level) { 5163 1.1 fvdl default: 5164 1.1 fvdl case 2: 5165 1.1 fvdl ahd_shutdown(ahd); 5166 1.1 fvdl TAILQ_REMOVE(&ahd_tailq, ahd, links); 5167 1.1 fvdl /* FALLTHROUGH */ 5168 1.1 fvdl case 1: 5169 1.44 tsutsui bus_dmamap_unload(ahd->parent_dmat, 5170 1.44 tsutsui ahd->shared_data_map.dmamap); 5171 1.44 tsutsui bus_dmamap_destroy(ahd->parent_dmat, 5172 1.44 tsutsui ahd->shared_data_map.dmamap); 5173 1.44 tsutsui bus_dmamem_unmap(ahd->parent_dmat, (void *)ahd->qoutfifo, 5174 1.44 tsutsui ahd->shared_data_size); 5175 1.44 tsutsui bus_dmamem_free(ahd->parent_dmat, 5176 1.44 tsutsui &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); 5177 1.1 fvdl break; 5178 1.1 fvdl case 0: 5179 1.43 tsutsui break; 5180 1.1 fvdl } 5181 1.1 fvdl 5182 1.1 fvdl ahd_platform_free(ahd); 5183 1.9 thorpej ahd_fini_scbdata(ahd); 5184 1.1 fvdl for (i = 0; i < AHD_NUM_TARGETS; i++) { 5185 1.1 fvdl struct ahd_tmode_tstate *tstate; 5186 1.1 fvdl 5187 1.1 fvdl tstate = ahd->enabled_targets[i]; 5188 1.1 fvdl if (tstate != NULL) { 5189 1.1 fvdl #if AHD_TARGET_MODE 5190 1.1 fvdl int j; 5191 1.1 fvdl 5192 1.1 fvdl for (j = 0; j < AHD_NUM_LUNS; j++) { 5193 1.1 fvdl struct ahd_tmode_lstate *lstate; 5194 1.1 fvdl 5195 1.1 fvdl lstate = tstate->enabled_luns[j]; 5196 1.1 fvdl if (lstate != NULL) { 5197 1.1 fvdl xpt_free_path(lstate->path); 5198 1.1 fvdl free(lstate, M_DEVBUF); 5199 1.1 fvdl } 5200 1.1 fvdl } 5201 1.1 fvdl #endif 5202 1.1 fvdl free(tstate, M_DEVBUF); 5203 1.1 fvdl } 5204 1.1 fvdl } 5205 1.1 fvdl #if AHD_TARGET_MODE 5206 1.1 fvdl if (ahd->black_hole != NULL) { 5207 1.1 fvdl xpt_free_path(ahd->black_hole->path); 5208 1.1 fvdl free(ahd->black_hole, M_DEVBUF); 5209 1.1 fvdl } 5210 1.1 fvdl #endif 5211 1.1 fvdl if (ahd->seep_config != NULL) 5212 1.1 fvdl free(ahd->seep_config, M_DEVBUF); 5213 1.1 fvdl if (ahd->saved_stack != NULL) 5214 1.1 fvdl free(ahd->saved_stack, M_DEVBUF); 5215 1.1 fvdl #ifndef __FreeBSD__ 5216 1.1 fvdl free(ahd, M_DEVBUF); 5217 1.1 fvdl #endif 5218 1.1 fvdl return; 5219 1.1 fvdl } 5220 1.1 fvdl 5221 1.1 fvdl void 5222 1.1 fvdl ahd_shutdown(void *arg) 5223 1.1 fvdl { 5224 1.1 fvdl struct ahd_softc *ahd; 5225 1.1 fvdl 5226 1.44 tsutsui ahd = arg; 5227 1.1 fvdl 5228 1.1 fvdl #ifdef AHD_DEBUG 5229 1.1 fvdl printf("%s: ahd_shutdown\n", ahd_name(ahd)); 5230 1.1 fvdl #endif 5231 1.1 fvdl /* 5232 1.1 fvdl * Stop periodic timer callbacks. 5233 1.1 fvdl */ 5234 1.1 fvdl ahd_timer_stop(&ahd->reset_timer); 5235 1.1 fvdl ahd_timer_stop(&ahd->stat_timer); 5236 1.1 fvdl 5237 1.1 fvdl /* This will reset most registers to 0, but not all */ 5238 1.15 thorpej ahd_reset(ahd, /*reinit*/FALSE); 5239 1.1 fvdl } 5240 1.1 fvdl 5241 1.1 fvdl /* 5242 1.1 fvdl * Reset the controller and record some information about it 5243 1.15 thorpej * that is only available just after a reset. If "reinit" is 5244 1.26 wiz * non-zero, this reset occurred after initial configuration 5245 1.15 thorpej * and the caller requests that the chip be fully reinitialized 5246 1.62 msaitoh * to a runnable state. Chip interrupts are *not* enabled after 5247 1.15 thorpej * a reinitialization. The caller must enable interrupts via 5248 1.15 thorpej * ahd_intr_enable(). 5249 1.1 fvdl */ 5250 1.1 fvdl int 5251 1.15 thorpej ahd_reset(struct ahd_softc *ahd, int reinit) 5252 1.1 fvdl { 5253 1.1 fvdl u_int sxfrctl1; 5254 1.1 fvdl int wait; 5255 1.1 fvdl uint32_t cmd; 5256 1.43 tsutsui struct ahd_pci_busdata *bd = ahd->bus_data; 5257 1.1 fvdl 5258 1.1 fvdl /* 5259 1.1 fvdl * Preserve the value of the SXFRCTL1 register for all channels. 5260 1.1 fvdl * It contains settings that affect termination and we don't want 5261 1.1 fvdl * to disturb the integrity of the bus. 5262 1.1 fvdl */ 5263 1.1 fvdl ahd_pause(ahd); 5264 1.1 fvdl ahd_update_modes(ahd); 5265 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5266 1.1 fvdl sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 5267 1.1 fvdl 5268 1.1 fvdl cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 5269 1.1 fvdl 5270 1.1 fvdl if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5271 1.1 fvdl uint32_t mod_cmd; 5272 1.1 fvdl 5273 1.1 fvdl /* 5274 1.1 fvdl * A4 Razor #632 5275 1.1 fvdl * During the assertion of CHIPRST, the chip 5276 1.1 fvdl * does not disable its parity logic prior to 5277 1.1 fvdl * the start of the reset. This may cause a 5278 1.1 fvdl * parity error to be detected and thus a 5279 1.67 andvar * spurious SERR or PERR assertion. Disable 5280 1.1 fvdl * PERR and SERR responses during the CHIPRST. 5281 1.1 fvdl */ 5282 1.44 tsutsui mod_cmd = cmd & 5283 1.44 tsutsui ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 5284 1.44 tsutsui pci_conf_write(bd->pc, bd->tag, 5285 1.44 tsutsui PCI_COMMAND_STATUS_REG, mod_cmd); 5286 1.1 fvdl } 5287 1.1 fvdl ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5288 1.1 fvdl 5289 1.1 fvdl /* 5290 1.1 fvdl * Ensure that the reset has finished. We delay 1000us 5291 1.1 fvdl * prior to reading the register to make sure the chip 5292 1.1 fvdl * has sufficiently completed its reset to handle register 5293 1.1 fvdl * accesses. 5294 1.1 fvdl */ 5295 1.1 fvdl wait = 1000; 5296 1.1 fvdl do { 5297 1.1 fvdl ahd_delay(1000); 5298 1.1 fvdl } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5299 1.1 fvdl 5300 1.1 fvdl if (wait == 0) { 5301 1.1 fvdl printf("%s: WARNING - Failed chip reset! " 5302 1.1 fvdl "Trying to initialize anyway.\n", ahd_name(ahd)); 5303 1.1 fvdl } 5304 1.1 fvdl ahd_outb(ahd, HCNTRL, ahd->pause); 5305 1.1 fvdl 5306 1.1 fvdl if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5307 1.1 fvdl /* 5308 1.1 fvdl * Clear any latched PCI error status and restore 5309 1.1 fvdl * previous SERR and PERR response enables. 5310 1.1 fvdl */ 5311 1.25 fvdl pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd | 5312 1.24 briggs (PCI_STATUS_PARITY_ERROR | PCI_STATUS_TARGET_TARGET_ABORT | 5313 1.24 briggs PCI_STATUS_MASTER_TARGET_ABORT | PCI_STATUS_MASTER_ABORT | 5314 1.24 briggs PCI_STATUS_SPECIAL_ERROR)); 5315 1.1 fvdl } 5316 1.1 fvdl 5317 1.1 fvdl /* 5318 1.43 tsutsui * Mode should be SCSI after a chip reset, but lets 5319 1.43 tsutsui * set it just to be safe. We touch the MODE_PTR 5320 1.1 fvdl * register directly so as to bypass the lazy update 5321 1.1 fvdl * ode in ahd_set_modes(). 5322 1.43 tsutsui */ 5323 1.1 fvdl ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5324 1.1 fvdl ahd_outb(ahd, MODE_PTR, 5325 1.1 fvdl ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5326 1.1 fvdl 5327 1.1 fvdl /* 5328 1.1 fvdl * Restore SXFRCTL1. 5329 1.1 fvdl * 5330 1.1 fvdl * We must always initialize STPWEN to 1 before we 5331 1.1 fvdl * restore the saved values. STPWEN is initialized 5332 1.1 fvdl * to a tri-state condition which can only be cleared 5333 1.1 fvdl * by turning it on. 5334 1.1 fvdl */ 5335 1.1 fvdl ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5336 1.1 fvdl ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5337 1.1 fvdl 5338 1.1 fvdl /* Determine chip configuration */ 5339 1.1 fvdl ahd->features &= ~AHD_WIDE; 5340 1.1 fvdl if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5341 1.1 fvdl ahd->features |= AHD_WIDE; 5342 1.1 fvdl 5343 1.1 fvdl /* 5344 1.1 fvdl * If a recovery action has forced a chip reset, 5345 1.1 fvdl * re-initialize the chip to our liking. 5346 1.1 fvdl */ 5347 1.15 thorpej if (reinit != 0) 5348 1.1 fvdl ahd_chip_init(ahd); 5349 1.1 fvdl 5350 1.1 fvdl return (0); 5351 1.1 fvdl } 5352 1.1 fvdl 5353 1.1 fvdl /* 5354 1.1 fvdl * Determine the number of SCBs available on the controller 5355 1.1 fvdl */ 5356 1.1 fvdl int 5357 1.1 fvdl ahd_probe_scbs(struct ahd_softc *ahd) { 5358 1.1 fvdl int i; 5359 1.1 fvdl 5360 1.1 fvdl AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5361 1.1 fvdl ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5362 1.1 fvdl for (i = 0; i < AHD_SCB_MAX; i++) { 5363 1.1 fvdl int j; 5364 1.1 fvdl int ret; 5365 1.1 fvdl 5366 1.1 fvdl ahd_set_scbptr(ahd, i); 5367 1.1 fvdl ahd_outw(ahd, SCB_BASE, i); 5368 1.1 fvdl for (j = 2; j < 64; j++) 5369 1.1 fvdl ahd_outb(ahd, SCB_BASE+j, 0); 5370 1.1 fvdl /* Start out life as unallocated (needing an abort) */ 5371 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5372 1.1 fvdl ret = ahd_inw_scbram(ahd, SCB_BASE); 5373 1.1 fvdl if (ret != i) { 5374 1.44 tsutsui printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", 5375 1.44 tsutsui ahd_name(ahd), i, ret); 5376 1.1 fvdl break; 5377 1.1 fvdl } 5378 1.1 fvdl ahd_set_scbptr(ahd, 0); 5379 1.1 fvdl ret = ahd_inw_scbram(ahd, SCB_BASE); 5380 1.1 fvdl if (ret != 0) { 5381 1.44 tsutsui printf("ahd_probe_scbs (non zero): returned 0x%x\n", 5382 1.44 tsutsui ret); 5383 1.1 fvdl break; 5384 1.1 fvdl } 5385 1.1 fvdl } 5386 1.1 fvdl return (i); 5387 1.1 fvdl } 5388 1.1 fvdl 5389 1.1 fvdl static void 5390 1.1 fvdl ahd_initialize_hscbs(struct ahd_softc *ahd) 5391 1.1 fvdl { 5392 1.1 fvdl int i; 5393 1.30 perry 5394 1.1 fvdl for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5395 1.1 fvdl ahd_set_scbptr(ahd, i); 5396 1.1 fvdl 5397 1.1 fvdl /* Clear the control byte. */ 5398 1.1 fvdl ahd_outb(ahd, SCB_CONTROL, 0); 5399 1.1 fvdl 5400 1.1 fvdl /* Set the next pointer */ 5401 1.1 fvdl ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5402 1.1 fvdl } 5403 1.1 fvdl } 5404 1.1 fvdl 5405 1.1 fvdl static int 5406 1.1 fvdl ahd_init_scbdata(struct ahd_softc *ahd) 5407 1.1 fvdl { 5408 1.1 fvdl struct scb_data *scb_data; 5409 1.1 fvdl int i; 5410 1.1 fvdl 5411 1.1 fvdl scb_data = &ahd->scb_data; 5412 1.1 fvdl TAILQ_INIT(&scb_data->free_scbs); 5413 1.1 fvdl for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5414 1.1 fvdl LIST_INIT(&scb_data->free_scb_lists[i]); 5415 1.1 fvdl LIST_INIT(&scb_data->any_dev_free_scb_list); 5416 1.1 fvdl SLIST_INIT(&scb_data->hscb_maps); 5417 1.1 fvdl SLIST_INIT(&scb_data->sg_maps); 5418 1.1 fvdl SLIST_INIT(&scb_data->sense_maps); 5419 1.1 fvdl 5420 1.1 fvdl /* Determine the number of hardware SCBs and initialize them */ 5421 1.1 fvdl scb_data->maxhscbs = ahd_probe_scbs(ahd); 5422 1.1 fvdl if (scb_data->maxhscbs == 0) { 5423 1.1 fvdl printf("%s: No SCB space found\n", ahd_name(ahd)); 5424 1.1 fvdl return (ENXIO); 5425 1.1 fvdl } 5426 1.1 fvdl ahd_initialize_hscbs(ahd); 5427 1.1 fvdl 5428 1.1 fvdl /* 5429 1.1 fvdl * Create our DMA tags. These tags define the kinds of device 5430 1.1 fvdl * accessible memory allocations and memory mappings we will 5431 1.1 fvdl * need to perform during normal operation. 5432 1.1 fvdl * 5433 1.1 fvdl * Unless we need to further restrict the allocation, we rely 5434 1.1 fvdl * on the restrictions of the parent dmat, hence the common 5435 1.1 fvdl * use of MAXADDR and MAXSIZE. 5436 1.1 fvdl */ 5437 1.1 fvdl 5438 1.1 fvdl /* Perform initial CCB allocation */ 5439 1.1 fvdl ahd_alloc_scbs(ahd); 5440 1.1 fvdl 5441 1.1 fvdl if (scb_data->numscbs == 0) { 5442 1.1 fvdl printf("%s: ahd_init_scbdata - " 5443 1.1 fvdl "Unable to allocate initial scbs\n", 5444 1.1 fvdl ahd_name(ahd)); 5445 1.1 fvdl goto error_exit; 5446 1.1 fvdl } 5447 1.1 fvdl 5448 1.1 fvdl /* 5449 1.58 andvar * Note that we were successful 5450 1.1 fvdl */ 5451 1.30 perry return (0); 5452 1.1 fvdl 5453 1.1 fvdl error_exit: 5454 1.1 fvdl 5455 1.1 fvdl return (ENOMEM); 5456 1.1 fvdl } 5457 1.1 fvdl 5458 1.1 fvdl static struct scb * 5459 1.1 fvdl ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5460 1.1 fvdl { 5461 1.1 fvdl struct scb *scb; 5462 1.1 fvdl 5463 1.1 fvdl /* 5464 1.1 fvdl * Look on the pending list. 5465 1.1 fvdl */ 5466 1.1 fvdl LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5467 1.1 fvdl if (SCB_GET_TAG(scb) == tag) 5468 1.1 fvdl return (scb); 5469 1.1 fvdl } 5470 1.1 fvdl 5471 1.1 fvdl /* 5472 1.1 fvdl * Then on all of the collision free lists. 5473 1.1 fvdl */ 5474 1.1 fvdl TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5475 1.1 fvdl struct scb *list_scb; 5476 1.1 fvdl 5477 1.1 fvdl list_scb = scb; 5478 1.1 fvdl do { 5479 1.1 fvdl if (SCB_GET_TAG(list_scb) == tag) 5480 1.1 fvdl return (list_scb); 5481 1.1 fvdl list_scb = LIST_NEXT(list_scb, collision_links); 5482 1.1 fvdl } while (list_scb); 5483 1.1 fvdl } 5484 1.1 fvdl 5485 1.1 fvdl /* 5486 1.1 fvdl * And finally on the generic free list. 5487 1.1 fvdl */ 5488 1.1 fvdl LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5489 1.1 fvdl if (SCB_GET_TAG(scb) == tag) 5490 1.1 fvdl return (scb); 5491 1.1 fvdl } 5492 1.1 fvdl 5493 1.1 fvdl return (NULL); 5494 1.1 fvdl } 5495 1.1 fvdl 5496 1.1 fvdl static void 5497 1.1 fvdl ahd_fini_scbdata(struct ahd_softc *ahd) 5498 1.1 fvdl { 5499 1.1 fvdl struct scb_data *scb_data; 5500 1.1 fvdl 5501 1.1 fvdl scb_data = &ahd->scb_data; 5502 1.1 fvdl if (scb_data == NULL) 5503 1.1 fvdl return; 5504 1.1 fvdl 5505 1.1 fvdl switch (scb_data->init_level) { 5506 1.1 fvdl default: 5507 1.1 fvdl case 3: 5508 1.1 fvdl { 5509 1.1 fvdl struct map_node *sns_map; 5510 1.1 fvdl 5511 1.1 fvdl while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5512 1.1 fvdl SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5513 1.1 fvdl ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5514 1.37 christos sns_map->dmamap, (void *)sns_map->vaddr, 5515 1.1 fvdl &sns_map->dmasegs, sns_map->nseg); 5516 1.1 fvdl free(sns_map, M_DEVBUF); 5517 1.1 fvdl } 5518 1.1 fvdl } 5519 1.51 mrg /* FALLTHROUGH */ 5520 1.1 fvdl case 2: 5521 1.1 fvdl { 5522 1.1 fvdl struct map_node *sg_map; 5523 1.1 fvdl 5524 1.1 fvdl while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5525 1.1 fvdl SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5526 1.44 tsutsui ahd_freedmamem(ahd->parent_dmat, 5527 1.44 tsutsui ahd_sglist_allocsize(ahd), 5528 1.37 christos sg_map->dmamap, (void *)sg_map->vaddr, 5529 1.1 fvdl &sg_map->dmasegs, sg_map->nseg); 5530 1.1 fvdl free(sg_map, M_DEVBUF); 5531 1.1 fvdl } 5532 1.1 fvdl } 5533 1.51 mrg /* FALLTHROUGH */ 5534 1.1 fvdl case 1: 5535 1.1 fvdl { 5536 1.1 fvdl struct map_node *hscb_map; 5537 1.1 fvdl 5538 1.1 fvdl while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5539 1.1 fvdl SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5540 1.1 fvdl ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5541 1.44 tsutsui hscb_map->dmamap, 5542 1.44 tsutsui (void *)hscb_map->vaddr, 5543 1.1 fvdl &hscb_map->dmasegs, hscb_map->nseg); 5544 1.1 fvdl free(hscb_map, M_DEVBUF); 5545 1.1 fvdl } 5546 1.1 fvdl } 5547 1.51 mrg /* FALLTHROUGH */ 5548 1.1 fvdl case 0: 5549 1.1 fvdl break; 5550 1.1 fvdl } 5551 1.1 fvdl } 5552 1.1 fvdl 5553 1.1 fvdl /* 5554 1.1 fvdl * DSP filter Bypass must be enabled until the first selection 5555 1.1 fvdl * after a change in bus mode (Razor #491 and #493). 5556 1.1 fvdl */ 5557 1.1 fvdl static void 5558 1.1 fvdl ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5559 1.1 fvdl { 5560 1.1 fvdl ahd_mode_state saved_modes; 5561 1.1 fvdl 5562 1.1 fvdl saved_modes = ahd_save_modes(ahd); 5563 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5564 1.1 fvdl ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5565 1.1 fvdl | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5566 1.1 fvdl ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5567 1.1 fvdl #ifdef AHD_DEBUG 5568 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 5569 1.1 fvdl printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5570 1.1 fvdl #endif 5571 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 5572 1.20 thorpej ahd->flags &= ~AHD_HAD_FIRST_SEL; 5573 1.1 fvdl } 5574 1.1 fvdl 5575 1.1 fvdl static void 5576 1.1 fvdl ahd_iocell_first_selection(struct ahd_softc *ahd) 5577 1.1 fvdl { 5578 1.1 fvdl ahd_mode_state saved_modes; 5579 1.1 fvdl u_int sblkctl; 5580 1.1 fvdl 5581 1.20 thorpej if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 5582 1.20 thorpej return; 5583 1.1 fvdl saved_modes = ahd_save_modes(ahd); 5584 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5585 1.1 fvdl sblkctl = ahd_inb(ahd, SBLKCTL); 5586 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5587 1.1 fvdl #ifdef AHD_DEBUG 5588 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 5589 1.1 fvdl printf("%s: iocell first selection\n", ahd_name(ahd)); 5590 1.1 fvdl #endif 5591 1.1 fvdl if ((sblkctl & ENAB40) != 0) { 5592 1.1 fvdl ahd_outb(ahd, DSPDATACTL, 5593 1.1 fvdl ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5594 1.1 fvdl #ifdef AHD_DEBUG 5595 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 5596 1.1 fvdl printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5597 1.1 fvdl #endif 5598 1.1 fvdl } 5599 1.1 fvdl ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5600 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 5601 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 5602 1.20 thorpej ahd->flags |= AHD_HAD_FIRST_SEL; 5603 1.1 fvdl } 5604 1.1 fvdl 5605 1.1 fvdl /*************************** SCB Management ***********************************/ 5606 1.1 fvdl static void 5607 1.1 fvdl ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5608 1.1 fvdl { 5609 1.1 fvdl struct scb_list *free_list; 5610 1.1 fvdl struct scb_tailq *free_tailq; 5611 1.1 fvdl struct scb *first_scb; 5612 1.1 fvdl 5613 1.1 fvdl scb->flags |= SCB_ON_COL_LIST; 5614 1.1 fvdl AHD_SET_SCB_COL_IDX(scb, col_idx); 5615 1.1 fvdl free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5616 1.1 fvdl free_tailq = &ahd->scb_data.free_scbs; 5617 1.1 fvdl first_scb = LIST_FIRST(free_list); 5618 1.1 fvdl if (first_scb != NULL) { 5619 1.1 fvdl LIST_INSERT_AFTER(first_scb, scb, collision_links); 5620 1.1 fvdl } else { 5621 1.1 fvdl LIST_INSERT_HEAD(free_list, scb, collision_links); 5622 1.1 fvdl TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5623 1.1 fvdl } 5624 1.1 fvdl } 5625 1.1 fvdl 5626 1.1 fvdl static void 5627 1.1 fvdl ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5628 1.1 fvdl { 5629 1.1 fvdl struct scb_list *free_list; 5630 1.1 fvdl struct scb_tailq *free_tailq; 5631 1.1 fvdl struct scb *first_scb; 5632 1.1 fvdl u_int col_idx; 5633 1.1 fvdl 5634 1.1 fvdl scb->flags &= ~SCB_ON_COL_LIST; 5635 1.1 fvdl col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5636 1.1 fvdl free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5637 1.1 fvdl free_tailq = &ahd->scb_data.free_scbs; 5638 1.1 fvdl first_scb = LIST_FIRST(free_list); 5639 1.1 fvdl if (first_scb == scb) { 5640 1.1 fvdl struct scb *next_scb; 5641 1.1 fvdl 5642 1.1 fvdl /* 5643 1.1 fvdl * Maintain order in the collision free 5644 1.1 fvdl * lists for fairness if this device has 5645 1.1 fvdl * other colliding tags active. 5646 1.1 fvdl */ 5647 1.1 fvdl next_scb = LIST_NEXT(scb, collision_links); 5648 1.1 fvdl if (next_scb != NULL) { 5649 1.1 fvdl TAILQ_INSERT_AFTER(free_tailq, scb, 5650 1.1 fvdl next_scb, links.tqe); 5651 1.1 fvdl } 5652 1.1 fvdl TAILQ_REMOVE(free_tailq, scb, links.tqe); 5653 1.1 fvdl } 5654 1.1 fvdl LIST_REMOVE(scb, collision_links); 5655 1.1 fvdl } 5656 1.1 fvdl 5657 1.1 fvdl /* 5658 1.1 fvdl * Get a free scb. If there are none, see if we can allocate a new SCB. 5659 1.1 fvdl */ 5660 1.1 fvdl struct scb * 5661 1.1 fvdl ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5662 1.1 fvdl { 5663 1.1 fvdl struct scb *scb; 5664 1.1 fvdl TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5665 1.1 fvdl if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5666 1.1 fvdl ahd_rem_col_list(ahd, scb); 5667 1.1 fvdl goto found; 5668 1.1 fvdl } 5669 1.1 fvdl } 5670 1.32 bouyer if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) 5671 1.32 bouyer return (NULL); 5672 1.1 fvdl LIST_REMOVE(scb, links.le); 5673 1.1 fvdl if (col_idx != AHD_NEVER_COL_IDX 5674 1.1 fvdl && (scb->col_scb != NULL) 5675 1.1 fvdl && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5676 1.1 fvdl LIST_REMOVE(scb->col_scb, links.le); 5677 1.1 fvdl ahd_add_col_list(ahd, scb->col_scb, col_idx); 5678 1.1 fvdl } 5679 1.1 fvdl found: 5680 1.1 fvdl scb->flags |= SCB_ACTIVE; 5681 1.1 fvdl return (scb); 5682 1.1 fvdl } 5683 1.1 fvdl 5684 1.1 fvdl /* 5685 1.1 fvdl * Return an SCB resource to the free list. 5686 1.1 fvdl */ 5687 1.1 fvdl void 5688 1.1 fvdl ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5689 1.30 perry { 5690 1.1 fvdl 5691 1.1 fvdl /* Clean up for the next user */ 5692 1.1 fvdl scb->flags = SCB_FLAG_NONE; 5693 1.1 fvdl scb->hscb->control = 0; 5694 1.9 thorpej ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5695 1.1 fvdl 5696 1.1 fvdl if (scb->col_scb == NULL) { 5697 1.1 fvdl 5698 1.1 fvdl /* 5699 1.1 fvdl * No collision possible. Just free normally. 5700 1.1 fvdl */ 5701 1.1 fvdl LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5702 1.1 fvdl scb, links.le); 5703 1.1 fvdl } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5704 1.1 fvdl 5705 1.1 fvdl /* 5706 1.1 fvdl * The SCB we might have collided with is on 5707 1.1 fvdl * a free collision list. Put both SCBs on 5708 1.1 fvdl * the generic list. 5709 1.1 fvdl */ 5710 1.1 fvdl ahd_rem_col_list(ahd, scb->col_scb); 5711 1.1 fvdl LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5712 1.1 fvdl scb, links.le); 5713 1.1 fvdl LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5714 1.1 fvdl scb->col_scb, links.le); 5715 1.1 fvdl } else if ((scb->col_scb->flags 5716 1.1 fvdl & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5717 1.1 fvdl && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5718 1.1 fvdl 5719 1.1 fvdl /* 5720 1.1 fvdl * The SCB we might collide with on the next allocation 5721 1.1 fvdl * is still active in a non-packetized, tagged, context. 5722 1.1 fvdl * Put us on the SCB collision list. 5723 1.1 fvdl */ 5724 1.1 fvdl ahd_add_col_list(ahd, scb, 5725 1.1 fvdl AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5726 1.1 fvdl } else { 5727 1.1 fvdl /* 5728 1.1 fvdl * The SCB we might collide with on the next allocation 5729 1.1 fvdl * is either active in a packetized context, or free. 5730 1.1 fvdl * Since we can't collide, put this SCB on the generic 5731 1.1 fvdl * free list. 5732 1.1 fvdl */ 5733 1.1 fvdl LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5734 1.1 fvdl scb, links.le); 5735 1.1 fvdl } 5736 1.1 fvdl 5737 1.1 fvdl ahd_platform_scb_free(ahd, scb); 5738 1.1 fvdl } 5739 1.1 fvdl 5740 1.32 bouyer int 5741 1.1 fvdl ahd_alloc_scbs(struct ahd_softc *ahd) 5742 1.1 fvdl { 5743 1.1 fvdl struct scb_data *scb_data; 5744 1.1 fvdl struct scb *next_scb; 5745 1.1 fvdl struct hardware_scb *hscb; 5746 1.1 fvdl struct map_node *hscb_map; 5747 1.1 fvdl struct map_node *sg_map; 5748 1.1 fvdl struct map_node *sense_map; 5749 1.1 fvdl uint8_t *segs; 5750 1.1 fvdl uint8_t *sense_data; 5751 1.1 fvdl bus_addr_t hscb_busaddr; 5752 1.1 fvdl bus_addr_t sg_busaddr; 5753 1.1 fvdl bus_addr_t sense_busaddr; 5754 1.1 fvdl int newcount; 5755 1.1 fvdl int i; 5756 1.1 fvdl 5757 1.1 fvdl scb_data = &ahd->scb_data; 5758 1.1 fvdl if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5759 1.1 fvdl /* Can't allocate any more */ 5760 1.32 bouyer return (0); 5761 1.1 fvdl 5762 1.7 thorpej KASSERT(scb_data->scbs_left >= 0); 5763 1.1 fvdl if (scb_data->scbs_left != 0) { 5764 1.1 fvdl int offset; 5765 1.1 fvdl 5766 1.1 fvdl offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5767 1.1 fvdl hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5768 1.1 fvdl hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5769 1.1 fvdl hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5770 1.1 fvdl } else { 5771 1.32 bouyer hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_WAITOK); 5772 1.1 fvdl 5773 1.1 fvdl if (hscb_map == NULL) 5774 1.32 bouyer return (0); 5775 1.1 fvdl 5776 1.1 fvdl memset(hscb_map, 0, sizeof(*hscb_map)); 5777 1.1 fvdl 5778 1.1 fvdl /* Allocate the next batch of hardware SCBs */ 5779 1.44 tsutsui if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, 5780 1.44 tsutsui ahd->sc_dmaflags, 5781 1.44 tsutsui &hscb_map->dmamap, 5782 1.44 tsutsui (void **)&hscb_map->vaddr, 5783 1.1 fvdl &hscb_map->physaddr, &hscb_map->dmasegs, 5784 1.30 perry &hscb_map->nseg, ahd_name(ahd), 5785 1.1 fvdl "hardware SCB structures") < 0) { 5786 1.1 fvdl free(hscb_map, M_DEVBUF); 5787 1.32 bouyer return (0); 5788 1.1 fvdl } 5789 1.1 fvdl 5790 1.1 fvdl SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5791 1.1 fvdl 5792 1.1 fvdl hscb = (struct hardware_scb *)hscb_map->vaddr; 5793 1.1 fvdl hscb_busaddr = hscb_map->physaddr; 5794 1.1 fvdl scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5795 1.1 fvdl } 5796 1.1 fvdl 5797 1.1 fvdl scb_data->init_level++; 5798 1.1 fvdl 5799 1.1 fvdl if (scb_data->sgs_left != 0) { 5800 1.1 fvdl int offset; 5801 1.1 fvdl 5802 1.9 thorpej offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5803 1.9 thorpej - scb_data->sgs_left) * ahd_sglist_size(ahd); 5804 1.1 fvdl sg_map = SLIST_FIRST(&scb_data->sg_maps); 5805 1.1 fvdl segs = sg_map->vaddr + offset; 5806 1.1 fvdl sg_busaddr = sg_map->physaddr + offset; 5807 1.1 fvdl } else { 5808 1.32 bouyer sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_WAITOK); 5809 1.1 fvdl 5810 1.1 fvdl if (sg_map == NULL) 5811 1.32 bouyer return (0); 5812 1.1 fvdl 5813 1.41 cegger memset(sg_map, 0, sizeof(*sg_map)); 5814 1.1 fvdl 5815 1.1 fvdl /* Allocate the next batch of S/G lists */ 5816 1.44 tsutsui if (ahd_createdmamem(ahd->parent_dmat, 5817 1.44 tsutsui ahd_sglist_allocsize(ahd), 5818 1.44 tsutsui ahd->sc_dmaflags, 5819 1.37 christos &sg_map->dmamap, (void **)&sg_map->vaddr, 5820 1.1 fvdl &sg_map->physaddr, &sg_map->dmasegs, 5821 1.30 perry &sg_map->nseg, ahd_name(ahd), 5822 1.1 fvdl "SG data structures") < 0) { 5823 1.1 fvdl free(sg_map, M_DEVBUF); 5824 1.32 bouyer return (0); 5825 1.1 fvdl } 5826 1.1 fvdl 5827 1.1 fvdl SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5828 1.1 fvdl 5829 1.1 fvdl segs = sg_map->vaddr; 5830 1.1 fvdl sg_busaddr = sg_map->physaddr; 5831 1.1 fvdl scb_data->sgs_left = 5832 1.1 fvdl ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5833 1.1 fvdl #ifdef AHD_DEBUG 5834 1.1 fvdl if (ahd_debug & AHD_SHOW_MEMORY) 5835 1.44 tsutsui printf("%s: ahd_alloc_scbs - Mapped SG data\n", 5836 1.44 tsutsui ahd_name(ahd)); 5837 1.1 fvdl #endif 5838 1.1 fvdl } 5839 1.1 fvdl 5840 1.1 fvdl scb_data->init_level++; 5841 1.1 fvdl 5842 1.1 fvdl 5843 1.1 fvdl if (scb_data->sense_left != 0) { 5844 1.1 fvdl int offset; 5845 1.1 fvdl 5846 1.1 fvdl offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5847 1.1 fvdl sense_map = SLIST_FIRST(&scb_data->sense_maps); 5848 1.1 fvdl sense_data = sense_map->vaddr + offset; 5849 1.1 fvdl sense_busaddr = sense_map->physaddr + offset; 5850 1.1 fvdl } else { 5851 1.32 bouyer sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_WAITOK); 5852 1.1 fvdl 5853 1.1 fvdl if (sense_map == NULL) 5854 1.32 bouyer return (0); 5855 1.1 fvdl 5856 1.41 cegger memset(sense_map, 0, sizeof(*sense_map)); 5857 1.1 fvdl 5858 1.1 fvdl /* Allocate the next batch of sense buffers */ 5859 1.44 tsutsui if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, 5860 1.44 tsutsui ahd->sc_dmaflags, 5861 1.44 tsutsui &sense_map->dmamap, 5862 1.44 tsutsui (void **)&sense_map->vaddr, 5863 1.1 fvdl &sense_map->physaddr, &sense_map->dmasegs, 5864 1.30 perry &sense_map->nseg, ahd_name(ahd), 5865 1.1 fvdl "Sense Data structures") < 0) { 5866 1.1 fvdl free(sense_map, M_DEVBUF); 5867 1.32 bouyer return (0); 5868 1.1 fvdl } 5869 1.1 fvdl 5870 1.1 fvdl SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5871 1.1 fvdl 5872 1.1 fvdl sense_data = sense_map->vaddr; 5873 1.1 fvdl sense_busaddr = sense_map->physaddr; 5874 1.1 fvdl scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5875 1.1 fvdl #ifdef AHD_DEBUG 5876 1.1 fvdl if (ahd_debug & AHD_SHOW_MEMORY) 5877 1.44 tsutsui printf("%s: ahd_alloc_scbs - Mapped sense data\n", 5878 1.44 tsutsui ahd_name(ahd)); 5879 1.1 fvdl #endif 5880 1.1 fvdl } 5881 1.1 fvdl 5882 1.1 fvdl scb_data->init_level++; 5883 1.1 fvdl 5884 1.1 fvdl newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5885 1.1 fvdl newcount = MIN(newcount, scb_data->sgs_left); 5886 1.1 fvdl newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5887 1.1 fvdl scb_data->sense_left -= newcount; 5888 1.1 fvdl scb_data->scbs_left -= newcount; 5889 1.1 fvdl scb_data->sgs_left -= newcount; 5890 1.1 fvdl 5891 1.1 fvdl for (i = 0; i < newcount; i++) { 5892 1.1 fvdl u_int col_tag; 5893 1.1 fvdl 5894 1.1 fvdl struct scb_platform_data *pdata; 5895 1.1 fvdl #ifndef __linux__ 5896 1.1 fvdl int error; 5897 1.1 fvdl #endif 5898 1.44 tsutsui next_scb = malloc(sizeof(*next_scb), M_DEVBUF, M_WAITOK); 5899 1.1 fvdl if (next_scb == NULL) 5900 1.1 fvdl break; 5901 1.1 fvdl 5902 1.44 tsutsui pdata = malloc(sizeof(*pdata), M_DEVBUF, M_WAITOK); 5903 1.1 fvdl if (pdata == NULL) { 5904 1.1 fvdl free(next_scb, M_DEVBUF); 5905 1.1 fvdl break; 5906 1.1 fvdl } 5907 1.1 fvdl next_scb->platform_data = pdata; 5908 1.1 fvdl next_scb->hscb_map = hscb_map; 5909 1.1 fvdl next_scb->sg_map = sg_map; 5910 1.1 fvdl next_scb->sense_map = sense_map; 5911 1.1 fvdl next_scb->sg_list = segs; 5912 1.1 fvdl next_scb->sense_data = sense_data; 5913 1.1 fvdl next_scb->sense_busaddr = sense_busaddr; 5914 1.10 thorpej memset(hscb, 0, sizeof(*hscb)); 5915 1.1 fvdl next_scb->hscb = hscb; 5916 1.1 fvdl hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5917 1.7 thorpej KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && 5918 1.7 thorpej (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); 5919 1.1 fvdl 5920 1.1 fvdl /* 5921 1.1 fvdl * The sequencer always starts with the second entry. 5922 1.1 fvdl * The first entry is embedded in the scb. 5923 1.1 fvdl */ 5924 1.1 fvdl next_scb->sg_list_busaddr = sg_busaddr; 5925 1.1 fvdl if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5926 1.1 fvdl next_scb->sg_list_busaddr 5927 1.1 fvdl += sizeof(struct ahd_dma64_seg); 5928 1.1 fvdl else 5929 1.1 fvdl next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5930 1.1 fvdl next_scb->ahd_softc = ahd; 5931 1.1 fvdl next_scb->flags = SCB_FLAG_NONE; 5932 1.1 fvdl 5933 1.1 fvdl error = bus_dmamap_create(ahd->parent_dmat, 5934 1.44 tsutsui AHD_MAXTRANSFER_SIZE, AHD_NSEG, 5935 1.44 tsutsui MAXBSIZE, 0, 5936 1.44 tsutsui BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW| 5937 1.44 tsutsui ahd->sc_dmaflags, 5938 1.1 fvdl &next_scb->dmamap); 5939 1.1 fvdl if (error != 0) { 5940 1.1 fvdl free(next_scb, M_DEVBUF); 5941 1.1 fvdl free(pdata, M_DEVBUF); 5942 1.1 fvdl break; 5943 1.1 fvdl } 5944 1.1 fvdl next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5945 1.1 fvdl col_tag = scb_data->numscbs ^ 0x100; 5946 1.1 fvdl next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5947 1.1 fvdl if (next_scb->col_scb != NULL) 5948 1.1 fvdl next_scb->col_scb->col_scb = next_scb; 5949 1.1 fvdl ahd_free_scb(ahd, next_scb); 5950 1.1 fvdl hscb++; 5951 1.1 fvdl hscb_busaddr += sizeof(*hscb); 5952 1.1 fvdl segs += ahd_sglist_size(ahd); 5953 1.1 fvdl sg_busaddr += ahd_sglist_size(ahd); 5954 1.1 fvdl sense_data += AHD_SENSE_BUFSIZE; 5955 1.1 fvdl sense_busaddr += AHD_SENSE_BUFSIZE; 5956 1.1 fvdl scb_data->numscbs++; 5957 1.1 fvdl } 5958 1.32 bouyer return (i); 5959 1.1 fvdl } 5960 1.1 fvdl 5961 1.1 fvdl void 5962 1.31 christos ahd_controller_info(struct ahd_softc *ahd, char *tbuf, size_t l) 5963 1.1 fvdl { 5964 1.1 fvdl const char *speed; 5965 1.1 fvdl const char *type; 5966 1.47 christos size_t len; 5967 1.1 fvdl 5968 1.47 christos len = snprintf(tbuf, l, "%s: ", 5969 1.28 itojun ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5970 1.47 christos if (len > l) 5971 1.47 christos return; 5972 1.1 fvdl speed = "Ultra320 "; 5973 1.1 fvdl if ((ahd->features & AHD_WIDE) != 0) { 5974 1.1 fvdl type = "Wide "; 5975 1.1 fvdl } else { 5976 1.1 fvdl type = "Single "; 5977 1.1 fvdl } 5978 1.47 christos len += snprintf(tbuf + len, l - len, "%s%sChannel %c, SCSI Id=%d, ", 5979 1.1 fvdl speed, type, ahd->channel, ahd->our_id); 5980 1.47 christos if (len > l) 5981 1.47 christos return; 5982 1.47 christos snprintf(tbuf + len, l - len, "%s, %d SCBs", ahd->bus_description, 5983 1.1 fvdl ahd->scb_data.maxhscbs); 5984 1.1 fvdl } 5985 1.1 fvdl 5986 1.55 jdolecek static const char * const channel_strings[] = { 5987 1.1 fvdl "Primary Low", 5988 1.1 fvdl "Primary High", 5989 1.30 perry "Secondary Low", 5990 1.1 fvdl "Secondary High" 5991 1.1 fvdl }; 5992 1.1 fvdl 5993 1.55 jdolecek static const char * const termstat_strings[] = { 5994 1.1 fvdl "Terminated Correctly", 5995 1.1 fvdl "Over Terminated", 5996 1.1 fvdl "Under Terminated", 5997 1.1 fvdl "Not Configured" 5998 1.1 fvdl }; 5999 1.1 fvdl 6000 1.1 fvdl /* 6001 1.1 fvdl * Start the board, ready for normal operation 6002 1.1 fvdl */ 6003 1.1 fvdl int 6004 1.1 fvdl ahd_init(struct ahd_softc *ahd) 6005 1.1 fvdl { 6006 1.1 fvdl uint8_t *next_vaddr; 6007 1.1 fvdl bus_addr_t next_baddr; 6008 1.1 fvdl size_t driver_data_size; 6009 1.1 fvdl int i; 6010 1.1 fvdl int error; 6011 1.1 fvdl u_int warn_user; 6012 1.1 fvdl uint8_t current_sensing; 6013 1.1 fvdl uint8_t fstat; 6014 1.30 perry 6015 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6016 1.1 fvdl 6017 1.1 fvdl ahd->stack_size = ahd_probe_stack_size(ahd); 6018 1.1 fvdl ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 6019 1.52 chs M_DEVBUF, M_WAITOK | M_ZERO); 6020 1.1 fvdl 6021 1.1 fvdl /* 6022 1.67 andvar * Verify that the compiler hasn't over-aggressively 6023 1.1 fvdl * padded important structures. 6024 1.1 fvdl */ 6025 1.1 fvdl if (sizeof(struct hardware_scb) != 64) 6026 1.1 fvdl panic("Hardware SCB size is incorrect"); 6027 1.1 fvdl 6028 1.1 fvdl #ifdef AHD_DEBUG 6029 1.1 fvdl if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 6030 1.1 fvdl ahd->flags |= AHD_SEQUENCER_DEBUG; 6031 1.1 fvdl #endif 6032 1.1 fvdl 6033 1.1 fvdl /* 6034 1.1 fvdl * Default to allowing initiator operations. 6035 1.1 fvdl */ 6036 1.1 fvdl ahd->flags |= AHD_INITIATORROLE; 6037 1.1 fvdl 6038 1.1 fvdl /* 6039 1.1 fvdl * Only allow target mode features if this unit has them enabled. 6040 1.1 fvdl */ 6041 1.1 fvdl if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 6042 1.1 fvdl ahd->features &= ~AHD_TARGETMODE; 6043 1.1 fvdl 6044 1.1 fvdl /* 6045 1.1 fvdl * DMA tag for our command fifos and other data in system memory 6046 1.1 fvdl * the card's sequencer must be able to access. For initiator 6047 1.1 fvdl * roles, we need to allocate space for the qoutfifo. When providing 6048 1.1 fvdl * for the target mode role, we must additionally provide space for 6049 1.1 fvdl * the incoming target command fifo. 6050 1.1 fvdl */ 6051 1.1 fvdl driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 6052 1.1 fvdl + sizeof(struct hardware_scb); 6053 1.1 fvdl if ((ahd->features & AHD_TARGETMODE) != 0) 6054 1.1 fvdl driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6055 1.1 fvdl if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 6056 1.1 fvdl driver_data_size += PKT_OVERRUN_BUFSIZE; 6057 1.1 fvdl ahd->shared_data_size = driver_data_size; 6058 1.1 fvdl 6059 1.7 thorpej memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); 6060 1.1 fvdl ahd->sc_dmaflags = BUS_DMA_NOWAIT; 6061 1.1 fvdl 6062 1.1 fvdl if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 6063 1.1 fvdl ahd->sc_dmaflags, 6064 1.44 tsutsui &ahd->shared_data_map.dmamap, 6065 1.44 tsutsui (void **)&ahd->shared_data_map.vaddr, 6066 1.44 tsutsui &ahd->shared_data_map.physaddr, 6067 1.44 tsutsui &ahd->shared_data_map.dmasegs, 6068 1.44 tsutsui &ahd->shared_data_map.nseg, ahd_name(ahd), 6069 1.44 tsutsui "shared data") < 0) 6070 1.1 fvdl return (ENOMEM); 6071 1.7 thorpej ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; 6072 1.1 fvdl 6073 1.1 fvdl ahd->init_level++; 6074 1.1 fvdl 6075 1.1 fvdl next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 6076 1.44 tsutsui next_baddr = ahd->shared_data_map.physaddr + 6077 1.44 tsutsui AHD_QOUT_SIZE * sizeof(uint16_t); 6078 1.1 fvdl if ((ahd->features & AHD_TARGETMODE) != 0) { 6079 1.1 fvdl ahd->targetcmds = (struct target_cmd *)next_vaddr; 6080 1.1 fvdl next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6081 1.1 fvdl next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6082 1.1 fvdl } 6083 1.1 fvdl 6084 1.1 fvdl if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 6085 1.1 fvdl ahd->overrun_buf = next_vaddr; 6086 1.1 fvdl next_vaddr += PKT_OVERRUN_BUFSIZE; 6087 1.1 fvdl next_baddr += PKT_OVERRUN_BUFSIZE; 6088 1.1 fvdl } 6089 1.1 fvdl 6090 1.1 fvdl /* 6091 1.1 fvdl * We need one SCB to serve as the "next SCB". Since the 6092 1.1 fvdl * tag identifier in this SCB will never be used, there is 6093 1.1 fvdl * no point in using a valid HSCB tag from an SCB pulled from 6094 1.1 fvdl * the standard free pool. So, we allocate this "sentinel" 6095 1.1 fvdl * specially from the DMA safe memory chunk used for the QOUTFIFO. 6096 1.1 fvdl */ 6097 1.1 fvdl ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 6098 1.7 thorpej ahd->next_queued_hscb_map = &ahd->shared_data_map; 6099 1.9 thorpej ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 6100 1.1 fvdl 6101 1.1 fvdl memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 6102 1.1 fvdl 6103 1.1 fvdl /* Allocate SCB data now that parent_dmat is initialized */ 6104 1.1 fvdl if (ahd_init_scbdata(ahd) != 0) 6105 1.1 fvdl return (ENOMEM); 6106 1.1 fvdl 6107 1.1 fvdl if ((ahd->flags & AHD_INITIATORROLE) == 0) 6108 1.1 fvdl ahd->flags &= ~AHD_RESET_BUS_A; 6109 1.1 fvdl 6110 1.1 fvdl /* 6111 1.1 fvdl * Before committing these settings to the chip, give 6112 1.1 fvdl * the OSM one last chance to modify our configuration. 6113 1.1 fvdl */ 6114 1.1 fvdl ahd_platform_init(ahd); 6115 1.1 fvdl 6116 1.1 fvdl /* Bring up the chip. */ 6117 1.1 fvdl ahd_chip_init(ahd); 6118 1.1 fvdl 6119 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6120 1.1 fvdl 6121 1.1 fvdl if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 6122 1.1 fvdl goto init_done; 6123 1.1 fvdl 6124 1.1 fvdl /* 6125 1.1 fvdl * Verify termination based on current draw and 6126 1.1 fvdl * warn user if the bus is over/under terminated. 6127 1.1 fvdl */ 6128 1.1 fvdl error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 6129 1.1 fvdl CURSENSE_ENB); 6130 1.1 fvdl if (error != 0) { 6131 1.1 fvdl printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 6132 1.1 fvdl goto init_done; 6133 1.1 fvdl } 6134 1.1 fvdl for (i = 20, fstat = FLX_FSTAT_BUSY; 6135 1.1 fvdl (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 6136 1.1 fvdl error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 6137 1.1 fvdl if (error != 0) { 6138 1.1 fvdl printf("%s: current sensing timeout 2\n", 6139 1.1 fvdl ahd_name(ahd)); 6140 1.1 fvdl goto init_done; 6141 1.1 fvdl } 6142 1.1 fvdl } 6143 1.1 fvdl if (i == 0) { 6144 1.1 fvdl printf("%s: Timedout during current-sensing test\n", 6145 1.1 fvdl ahd_name(ahd)); 6146 1.1 fvdl goto init_done; 6147 1.1 fvdl } 6148 1.1 fvdl 6149 1.1 fvdl /* Latch Current Sensing status. */ 6150 1.1 fvdl error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 6151 1.1 fvdl if (error != 0) { 6152 1.1 fvdl printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 6153 1.1 fvdl goto init_done; 6154 1.1 fvdl } 6155 1.1 fvdl 6156 1.69 andvar /* Disable current sensing. */ 6157 1.1 fvdl ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 6158 1.1 fvdl 6159 1.1 fvdl #ifdef AHD_DEBUG 6160 1.1 fvdl if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 6161 1.1 fvdl printf("%s: current_sensing == 0x%x\n", 6162 1.1 fvdl ahd_name(ahd), current_sensing); 6163 1.1 fvdl } 6164 1.1 fvdl #endif 6165 1.1 fvdl warn_user = 0; 6166 1.1 fvdl for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 6167 1.1 fvdl u_int term_stat; 6168 1.1 fvdl 6169 1.1 fvdl term_stat = (current_sensing & FLX_CSTAT_MASK); 6170 1.1 fvdl switch (term_stat) { 6171 1.1 fvdl case FLX_CSTAT_OVER: 6172 1.1 fvdl case FLX_CSTAT_UNDER: 6173 1.1 fvdl warn_user++; 6174 1.51 mrg /* FALLTHROUGH */ 6175 1.1 fvdl case FLX_CSTAT_INVALID: 6176 1.1 fvdl case FLX_CSTAT_OKAY: 6177 1.1 fvdl if (warn_user == 0 && bootverbose == 0) 6178 1.1 fvdl break; 6179 1.1 fvdl printf("%s: %s Channel %s\n", ahd_name(ahd), 6180 1.1 fvdl channel_strings[i], termstat_strings[term_stat]); 6181 1.1 fvdl break; 6182 1.1 fvdl } 6183 1.1 fvdl } 6184 1.1 fvdl if (warn_user) { 6185 1.1 fvdl printf("%s: WARNING. Termination is not configured correctly.\n" 6186 1.1 fvdl "%s: WARNING. SCSI bus operations may FAIL.\n", 6187 1.1 fvdl ahd_name(ahd), ahd_name(ahd)); 6188 1.1 fvdl } 6189 1.1 fvdl init_done: 6190 1.1 fvdl ahd_reset_current_bus(ahd); 6191 1.1 fvdl ahd_restart(ahd); 6192 1.1 fvdl ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 6193 1.1 fvdl ahd_stat_timer, ahd); 6194 1.1 fvdl 6195 1.1 fvdl return (0); 6196 1.1 fvdl } 6197 1.1 fvdl 6198 1.1 fvdl /* 6199 1.1 fvdl * (Re)initialize chip state after a chip reset. 6200 1.1 fvdl */ 6201 1.1 fvdl static void 6202 1.1 fvdl ahd_chip_init(struct ahd_softc *ahd) 6203 1.1 fvdl { 6204 1.1 fvdl uint32_t busaddr; 6205 1.1 fvdl u_int sxfrctl1; 6206 1.1 fvdl u_int scsiseq_template; 6207 1.1 fvdl u_int wait; 6208 1.1 fvdl u_int i; 6209 1.1 fvdl u_int target; 6210 1.1 fvdl 6211 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6212 1.1 fvdl /* 6213 1.1 fvdl * Take the LED out of diagnostic mode 6214 1.1 fvdl */ 6215 1.1 fvdl ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6216 1.1 fvdl 6217 1.1 fvdl /* 6218 1.1 fvdl * Return HS_MAILBOX to its default value. 6219 1.1 fvdl */ 6220 1.1 fvdl ahd->hs_mailbox = 0; 6221 1.1 fvdl ahd_outb(ahd, HS_MAILBOX, 0); 6222 1.1 fvdl 6223 1.1 fvdl /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6224 1.1 fvdl ahd_outb(ahd, IOWNID, ahd->our_id); 6225 1.1 fvdl ahd_outb(ahd, TOWNID, ahd->our_id); 6226 1.1 fvdl sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6227 1.1 fvdl sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6228 1.1 fvdl if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6229 1.1 fvdl && (ahd->seltime != STIMESEL_MIN)) { 6230 1.1 fvdl /* 6231 1.1 fvdl * The selection timer duration is twice as long 6232 1.1 fvdl * as it should be. Halve it by adding "1" to 6233 1.1 fvdl * the user specified setting. 6234 1.1 fvdl */ 6235 1.1 fvdl sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6236 1.1 fvdl } else { 6237 1.1 fvdl sxfrctl1 |= ahd->seltime; 6238 1.1 fvdl } 6239 1.30 perry 6240 1.1 fvdl ahd_outb(ahd, SXFRCTL0, DFON); 6241 1.1 fvdl ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6242 1.1 fvdl ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6243 1.1 fvdl 6244 1.1 fvdl /* 6245 1.1 fvdl * Now that termination is set, wait for up 6246 1.1 fvdl * to 500ms for our transceivers to settle. If 6247 1.1 fvdl * the adapter does not have a cable attached, 6248 1.9 thorpej * the transceivers may never settle, so don't 6249 1.1 fvdl * complain if we fail here. 6250 1.1 fvdl */ 6251 1.1 fvdl for (wait = 10000; 6252 1.1 fvdl (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6253 1.1 fvdl wait--) 6254 1.1 fvdl ahd_delay(100); 6255 1.1 fvdl 6256 1.1 fvdl /* Clear any false bus resets due to the transceivers settling */ 6257 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6258 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 6259 1.1 fvdl 6260 1.1 fvdl /* Initialize mode specific S/G state. */ 6261 1.1 fvdl for (i = 0; i < 2; i++) { 6262 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6263 1.1 fvdl ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6264 1.1 fvdl ahd_outb(ahd, SG_STATE, 0); 6265 1.1 fvdl ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6266 1.1 fvdl ahd_outb(ahd, SEQIMODE, 6267 1.1 fvdl ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6268 1.1 fvdl |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6269 1.1 fvdl } 6270 1.1 fvdl 6271 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6272 1.1 fvdl ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6273 1.1 fvdl ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6274 1.1 fvdl ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6275 1.1 fvdl ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6276 1.1 fvdl if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6277 1.1 fvdl ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6278 1.1 fvdl } else { 6279 1.1 fvdl ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6280 1.1 fvdl } 6281 1.1 fvdl ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6282 1.1 fvdl if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6283 1.1 fvdl /* 6284 1.1 fvdl * Do not issue a target abort when a split completion 6285 1.1 fvdl * error occurs. Let our PCIX interrupt handler deal 6286 1.1 fvdl * with it instead. H2A4 Razor #625 6287 1.1 fvdl */ 6288 1.1 fvdl ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6289 1.1 fvdl 6290 1.1 fvdl if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6291 1.1 fvdl ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6292 1.1 fvdl 6293 1.1 fvdl /* 6294 1.1 fvdl * Tweak IOCELL settings. 6295 1.1 fvdl */ 6296 1.1 fvdl if ((ahd->flags & AHD_HP_BOARD) != 0) { 6297 1.1 fvdl for (i = 0; i < NUMDSPS; i++) { 6298 1.1 fvdl ahd_outb(ahd, DSPSELECT, i); 6299 1.1 fvdl ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6300 1.1 fvdl } 6301 1.1 fvdl #ifdef AHD_DEBUG 6302 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 6303 1.1 fvdl printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6304 1.1 fvdl WRTBIASCTL_HP_DEFAULT); 6305 1.1 fvdl #endif 6306 1.1 fvdl } 6307 1.1 fvdl ahd_setup_iocell_workaround(ahd); 6308 1.1 fvdl 6309 1.1 fvdl /* 6310 1.1 fvdl * Enable LQI Manager interrupts. 6311 1.1 fvdl */ 6312 1.1 fvdl ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6313 1.1 fvdl | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6314 1.1 fvdl | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6315 1.1 fvdl ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6316 1.1 fvdl /* 6317 1.1 fvdl * An interrupt from LQOBUSFREE is made redundant by the 6318 1.1 fvdl * BUSFREE interrupt. We choose to have the sequencer catch 6319 1.1 fvdl * LQOPHCHGINPKT errors manually for the command phase at the 6320 1.1 fvdl * start of a packetized selection case. 6321 1.1 fvdl ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 6322 1.1 fvdl */ 6323 1.1 fvdl ahd_outb(ahd, LQOMODE1, 0); 6324 1.1 fvdl 6325 1.1 fvdl /* 6326 1.1 fvdl * Setup sequencer interrupt handlers. 6327 1.1 fvdl */ 6328 1.1 fvdl ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6329 1.1 fvdl ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6330 1.1 fvdl 6331 1.1 fvdl /* 6332 1.1 fvdl * Setup SCB Offset registers. 6333 1.1 fvdl */ 6334 1.1 fvdl if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6335 1.1 fvdl ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6336 1.1 fvdl pkt_long_lun)); 6337 1.1 fvdl } else { 6338 1.1 fvdl ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6339 1.1 fvdl } 6340 1.1 fvdl ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6341 1.1 fvdl ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6342 1.1 fvdl ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6343 1.1 fvdl ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6344 1.1 fvdl shared_data.idata.cdb)); 6345 1.1 fvdl ahd_outb(ahd, QNEXTPTR, 6346 1.1 fvdl offsetof(struct hardware_scb, next_hscb_busaddr)); 6347 1.1 fvdl ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6348 1.1 fvdl ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6349 1.1 fvdl if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6350 1.1 fvdl ahd_outb(ahd, LUNLEN, 6351 1.1 fvdl sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6352 1.1 fvdl } else { 6353 1.13 thorpej ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6354 1.1 fvdl } 6355 1.1 fvdl ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6356 1.1 fvdl ahd_outb(ahd, MAXCMD, 0xFF); 6357 1.1 fvdl ahd_outb(ahd, SCBAUTOPTR, 6358 1.1 fvdl AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6359 1.1 fvdl 6360 1.1 fvdl /* We haven't been enabled for target mode yet. */ 6361 1.1 fvdl ahd_outb(ahd, MULTARGID, 0); 6362 1.1 fvdl ahd_outb(ahd, MULTARGID + 1, 0); 6363 1.1 fvdl 6364 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6365 1.1 fvdl /* Initialize the negotiation table. */ 6366 1.1 fvdl if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6367 1.1 fvdl /* 6368 1.1 fvdl * Clear the spare bytes in the neg table to avoid 6369 1.1 fvdl * spurious parity errors. 6370 1.1 fvdl */ 6371 1.1 fvdl for (target = 0; target < AHD_NUM_TARGETS; target++) { 6372 1.1 fvdl ahd_outb(ahd, NEGOADDR, target); 6373 1.1 fvdl ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6374 1.1 fvdl for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6375 1.1 fvdl ahd_outb(ahd, ANNEXDAT, 0); 6376 1.1 fvdl } 6377 1.1 fvdl } 6378 1.1 fvdl 6379 1.1 fvdl for (target = 0; target < AHD_NUM_TARGETS; target++) { 6380 1.1 fvdl struct ahd_devinfo devinfo; 6381 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 6382 1.1 fvdl struct ahd_tmode_tstate *tstate; 6383 1.1 fvdl 6384 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6385 1.1 fvdl target, &tstate); 6386 1.1 fvdl ahd_compile_devinfo(&devinfo, ahd->our_id, 6387 1.1 fvdl target, CAM_LUN_WILDCARD, 6388 1.1 fvdl 'A', ROLE_INITIATOR); 6389 1.1 fvdl ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6390 1.1 fvdl } 6391 1.1 fvdl 6392 1.1 fvdl ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6393 1.1 fvdl ahd_outb(ahd, CLRINT, CLRSCSIINT); 6394 1.1 fvdl 6395 1.19 thorpej #if NEEDS_MORE_TESTING 6396 1.1 fvdl /* 6397 1.1 fvdl * Always enable abort on incoming L_Qs if this feature is 6398 1.1 fvdl * supported. We use this to catch invalid SCB references. 6399 1.1 fvdl */ 6400 1.1 fvdl if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6401 1.1 fvdl ahd_outb(ahd, LQCTL1, ABORTPENDING); 6402 1.1 fvdl else 6403 1.19 thorpej #endif 6404 1.1 fvdl ahd_outb(ahd, LQCTL1, 0); 6405 1.1 fvdl 6406 1.1 fvdl /* All of our queues are empty */ 6407 1.1 fvdl ahd->qoutfifonext = 0; 6408 1.1 fvdl ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6409 1.1 fvdl ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6410 1.1 fvdl for (i = 0; i < AHD_QOUT_SIZE; i++) 6411 1.1 fvdl ahd->qoutfifo[i] = 0; 6412 1.1 fvdl ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6413 1.1 fvdl 6414 1.1 fvdl ahd->qinfifonext = 0; 6415 1.1 fvdl for (i = 0; i < AHD_QIN_SIZE; i++) 6416 1.1 fvdl ahd->qinfifo[i] = SCB_LIST_NULL; 6417 1.1 fvdl 6418 1.1 fvdl if ((ahd->features & AHD_TARGETMODE) != 0) { 6419 1.1 fvdl /* All target command blocks start out invalid. */ 6420 1.1 fvdl for (i = 0; i < AHD_TMODE_CMDS; i++) 6421 1.1 fvdl ahd->targetcmds[i].cmd_valid = 0; 6422 1.1 fvdl ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6423 1.1 fvdl ahd->tqinfifonext = 1; 6424 1.1 fvdl ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6425 1.1 fvdl ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6426 1.1 fvdl } 6427 1.1 fvdl 6428 1.1 fvdl /* Initialize Scratch Ram. */ 6429 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS, 0); 6430 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS2, 0); 6431 1.1 fvdl 6432 1.1 fvdl /* We don't have any waiting selections */ 6433 1.1 fvdl ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6434 1.1 fvdl ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6435 1.1 fvdl for (i = 0; i < AHD_NUM_TARGETS; i++) { 6436 1.1 fvdl ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6437 1.1 fvdl } 6438 1.1 fvdl 6439 1.1 fvdl /* 6440 1.1 fvdl * Nobody is waiting to be DMAed into the QOUTFIFO. 6441 1.1 fvdl */ 6442 1.1 fvdl ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6443 1.1 fvdl ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6444 1.1 fvdl ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6445 1.1 fvdl 6446 1.1 fvdl /* 6447 1.1 fvdl * The Freeze Count is 0. 6448 1.1 fvdl */ 6449 1.1 fvdl ahd_outw(ahd, QFREEZE_COUNT, 0); 6450 1.1 fvdl 6451 1.1 fvdl /* 6452 1.1 fvdl * Tell the sequencer where it can find our arrays in memory. 6453 1.1 fvdl */ 6454 1.7 thorpej busaddr = ahd->shared_data_map.physaddr; 6455 1.1 fvdl ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6456 1.1 fvdl ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6457 1.1 fvdl ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6458 1.1 fvdl ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6459 1.1 fvdl ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6460 1.1 fvdl ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6461 1.1 fvdl ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6462 1.1 fvdl ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6463 1.1 fvdl /* 6464 1.1 fvdl * Setup the allowed SCSI Sequences based on operational mode. 6465 1.1 fvdl * If we are a target, we'll enable select in operations once 6466 1.1 fvdl * we've had a lun enabled. 6467 1.1 fvdl */ 6468 1.1 fvdl scsiseq_template = ENAUTOATNP; 6469 1.1 fvdl if ((ahd->flags & AHD_INITIATORROLE) != 0) 6470 1.1 fvdl scsiseq_template |= ENRSELI; 6471 1.1 fvdl ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6472 1.1 fvdl 6473 1.1 fvdl /* There are no busy SCBs yet. */ 6474 1.1 fvdl for (target = 0; target < AHD_NUM_TARGETS; target++) { 6475 1.1 fvdl int lun; 6476 1.1 fvdl 6477 1.1 fvdl for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6478 1.1 fvdl ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6479 1.1 fvdl } 6480 1.1 fvdl 6481 1.1 fvdl /* 6482 1.1 fvdl * Initialize the group code to command length table. 6483 1.1 fvdl * Vendor Unique codes are set to 0 so we only capture 6484 1.1 fvdl * the first byte of the cdb. These can be overridden 6485 1.1 fvdl * when target mode is enabled. 6486 1.1 fvdl */ 6487 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE, 5); 6488 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6489 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6490 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6491 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6492 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6493 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6494 1.1 fvdl ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6495 1.30 perry 6496 1.1 fvdl /* Tell the sequencer of our initial queue positions */ 6497 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6498 1.1 fvdl ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6499 1.1 fvdl ahd->qinfifonext = 0; 6500 1.1 fvdl ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6501 1.1 fvdl ahd_set_hescb_qoff(ahd, 0); 6502 1.1 fvdl ahd_set_snscb_qoff(ahd, 0); 6503 1.1 fvdl ahd_set_sescb_qoff(ahd, 0); 6504 1.1 fvdl ahd_set_sdscb_qoff(ahd, 0); 6505 1.1 fvdl 6506 1.1 fvdl /* 6507 1.1 fvdl * Tell the sequencer which SCB will be the next one it receives. 6508 1.1 fvdl */ 6509 1.1 fvdl busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6510 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6511 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6512 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6513 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6514 1.1 fvdl 6515 1.1 fvdl /* 6516 1.5 wiz * Default to coalescing disabled. 6517 1.1 fvdl */ 6518 1.5 wiz ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6519 1.1 fvdl ahd_outw(ahd, CMDS_PENDING, 0); 6520 1.5 wiz ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6521 1.5 wiz ahd->int_coalescing_maxcmds, 6522 1.5 wiz ahd->int_coalescing_mincmds); 6523 1.5 wiz ahd_enable_coalescing(ahd, FALSE); 6524 1.1 fvdl 6525 1.1 fvdl ahd_loadseq(ahd); 6526 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6527 1.1 fvdl } 6528 1.1 fvdl 6529 1.1 fvdl /* 6530 1.1 fvdl * Setup default device and controller settings. 6531 1.1 fvdl * This should only be called if our probe has 6532 1.1 fvdl * determined that no configuration data is available. 6533 1.1 fvdl */ 6534 1.1 fvdl int 6535 1.1 fvdl ahd_default_config(struct ahd_softc *ahd) 6536 1.1 fvdl { 6537 1.1 fvdl int targ; 6538 1.1 fvdl 6539 1.1 fvdl ahd->our_id = 7; 6540 1.1 fvdl 6541 1.1 fvdl /* 6542 1.1 fvdl * Allocate a tstate to house information for our 6543 1.1 fvdl * initiator presence on the bus as well as the user 6544 1.1 fvdl * data for any target mode initiator. 6545 1.1 fvdl */ 6546 1.1 fvdl if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6547 1.1 fvdl printf("%s: unable to allocate ahd_tmode_tstate. " 6548 1.1 fvdl "Failing attach\n", ahd_name(ahd)); 6549 1.1 fvdl return (ENOMEM); 6550 1.1 fvdl } 6551 1.1 fvdl 6552 1.1 fvdl for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6553 1.1 fvdl struct ahd_devinfo devinfo; 6554 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 6555 1.1 fvdl struct ahd_tmode_tstate *tstate; 6556 1.1 fvdl uint16_t target_mask; 6557 1.1 fvdl 6558 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6559 1.1 fvdl targ, &tstate); 6560 1.1 fvdl /* 6561 1.1 fvdl * We support SPC2 and SPI4. 6562 1.1 fvdl */ 6563 1.1 fvdl tinfo->user.protocol_version = 4; 6564 1.1 fvdl tinfo->user.transport_version = 4; 6565 1.1 fvdl 6566 1.1 fvdl target_mask = 0x01 << targ; 6567 1.1 fvdl ahd->user_discenable |= target_mask; 6568 1.1 fvdl tstate->discenable |= target_mask; 6569 1.1 fvdl ahd->user_tagenable |= target_mask; 6570 1.1 fvdl #ifdef AHD_FORCE_160 6571 1.1 fvdl tinfo->user.period = AHD_SYNCRATE_DT; 6572 1.1 fvdl #else 6573 1.1 fvdl tinfo->user.period = AHD_SYNCRATE_160; 6574 1.1 fvdl #endif 6575 1.1 fvdl tinfo->user.offset= MAX_OFFSET; 6576 1.1 fvdl tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6577 1.1 fvdl | MSG_EXT_PPR_WRFLOW 6578 1.1 fvdl | MSG_EXT_PPR_HOLDMCS 6579 1.1 fvdl | MSG_EXT_PPR_IU_REQ 6580 1.1 fvdl | MSG_EXT_PPR_QAS_REQ 6581 1.1 fvdl | MSG_EXT_PPR_DT_REQ; 6582 1.1 fvdl if ((ahd->features & AHD_RTI) != 0) 6583 1.1 fvdl tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6584 1.1 fvdl 6585 1.1 fvdl tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6586 1.1 fvdl 6587 1.1 fvdl /* 6588 1.1 fvdl * Start out Async/Narrow/Untagged and with 6589 1.1 fvdl * conservative protocol support. 6590 1.1 fvdl */ 6591 1.1 fvdl tinfo->goal.protocol_version = 2; 6592 1.1 fvdl tinfo->goal.transport_version = 2; 6593 1.1 fvdl tinfo->curr.protocol_version = 2; 6594 1.1 fvdl tinfo->curr.transport_version = 2; 6595 1.1 fvdl ahd_compile_devinfo(&devinfo, ahd->our_id, 6596 1.1 fvdl targ, CAM_LUN_WILDCARD, 6597 1.1 fvdl 'A', ROLE_INITIATOR); 6598 1.1 fvdl tstate->tagenable &= ~target_mask; 6599 1.1 fvdl ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6600 1.1 fvdl AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6601 1.1 fvdl ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6602 1.1 fvdl /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6603 1.1 fvdl /*paused*/TRUE); 6604 1.1 fvdl } 6605 1.1 fvdl return (0); 6606 1.1 fvdl } 6607 1.1 fvdl 6608 1.1 fvdl /* 6609 1.1 fvdl * Parse device configuration information. 6610 1.1 fvdl */ 6611 1.1 fvdl int 6612 1.1 fvdl ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6613 1.1 fvdl { 6614 1.1 fvdl int targ; 6615 1.1 fvdl int max_targ; 6616 1.1 fvdl 6617 1.1 fvdl max_targ = sc->max_targets & CFMAXTARG; 6618 1.1 fvdl ahd->our_id = sc->brtime_id & CFSCSIID; 6619 1.1 fvdl 6620 1.1 fvdl /* 6621 1.1 fvdl * Allocate a tstate to house information for our 6622 1.1 fvdl * initiator presence on the bus as well as the user 6623 1.1 fvdl * data for any target mode initiator. 6624 1.1 fvdl */ 6625 1.1 fvdl if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6626 1.1 fvdl printf("%s: unable to allocate ahd_tmode_tstate. " 6627 1.1 fvdl "Failing attach\n", ahd_name(ahd)); 6628 1.1 fvdl return (ENOMEM); 6629 1.1 fvdl } 6630 1.1 fvdl 6631 1.1 fvdl for (targ = 0; targ < max_targ; targ++) { 6632 1.1 fvdl struct ahd_devinfo devinfo; 6633 1.1 fvdl struct ahd_initiator_tinfo *tinfo; 6634 1.1 fvdl struct ahd_transinfo *user_tinfo; 6635 1.1 fvdl struct ahd_tmode_tstate *tstate; 6636 1.1 fvdl uint16_t target_mask; 6637 1.1 fvdl 6638 1.1 fvdl tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6639 1.1 fvdl targ, &tstate); 6640 1.1 fvdl user_tinfo = &tinfo->user; 6641 1.1 fvdl 6642 1.1 fvdl /* 6643 1.1 fvdl * We support SPC2 and SPI4. 6644 1.1 fvdl */ 6645 1.1 fvdl tinfo->user.protocol_version = 4; 6646 1.1 fvdl tinfo->user.transport_version = 4; 6647 1.1 fvdl 6648 1.1 fvdl target_mask = 0x01 << targ; 6649 1.1 fvdl ahd->user_discenable &= ~target_mask; 6650 1.1 fvdl tstate->discenable &= ~target_mask; 6651 1.1 fvdl ahd->user_tagenable &= ~target_mask; 6652 1.1 fvdl if (sc->device_flags[targ] & CFDISC) { 6653 1.1 fvdl tstate->discenable |= target_mask; 6654 1.1 fvdl ahd->user_discenable |= target_mask; 6655 1.1 fvdl ahd->user_tagenable |= target_mask; 6656 1.1 fvdl } else { 6657 1.1 fvdl /* 6658 1.1 fvdl * Cannot be packetized without disconnection. 6659 1.1 fvdl */ 6660 1.1 fvdl sc->device_flags[targ] &= ~CFPACKETIZED; 6661 1.1 fvdl } 6662 1.1 fvdl 6663 1.1 fvdl user_tinfo->ppr_options = 0; 6664 1.1 fvdl user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6665 1.1 fvdl if (user_tinfo->period < CFXFER_ASYNC) { 6666 1.1 fvdl if (user_tinfo->period <= AHD_PERIOD_10MHz) 6667 1.1 fvdl user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6668 1.1 fvdl user_tinfo->offset = MAX_OFFSET; 6669 1.1 fvdl } else { 6670 1.1 fvdl user_tinfo->offset = 0; 6671 1.1 fvdl user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6672 1.1 fvdl } 6673 1.1 fvdl #ifdef AHD_FORCE_160 6674 1.1 fvdl if (user_tinfo->period <= AHD_SYNCRATE_160) 6675 1.1 fvdl user_tinfo->period = AHD_SYNCRATE_DT; 6676 1.1 fvdl #endif 6677 1.1 fvdl 6678 1.1 fvdl if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6679 1.1 fvdl user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6680 1.1 fvdl | MSG_EXT_PPR_WRFLOW 6681 1.1 fvdl | MSG_EXT_PPR_HOLDMCS 6682 1.1 fvdl | MSG_EXT_PPR_IU_REQ; 6683 1.1 fvdl if ((ahd->features & AHD_RTI) != 0) 6684 1.1 fvdl user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6685 1.1 fvdl } 6686 1.1 fvdl 6687 1.1 fvdl if ((sc->device_flags[targ] & CFQAS) != 0) 6688 1.1 fvdl user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6689 1.1 fvdl 6690 1.1 fvdl if ((sc->device_flags[targ] & CFWIDEB) != 0) 6691 1.1 fvdl user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6692 1.1 fvdl else 6693 1.1 fvdl user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6694 1.1 fvdl #ifdef AHD_DEBUG 6695 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) 6696 1.1 fvdl printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6697 1.1 fvdl user_tinfo->period, user_tinfo->offset, 6698 1.1 fvdl user_tinfo->ppr_options); 6699 1.1 fvdl #endif 6700 1.1 fvdl /* 6701 1.1 fvdl * Start out Async/Narrow/Untagged and with 6702 1.1 fvdl * conservative protocol support. 6703 1.1 fvdl */ 6704 1.1 fvdl tstate->tagenable &= ~target_mask; 6705 1.1 fvdl tinfo->goal.protocol_version = 2; 6706 1.1 fvdl tinfo->goal.transport_version = 2; 6707 1.1 fvdl tinfo->curr.protocol_version = 2; 6708 1.1 fvdl tinfo->curr.transport_version = 2; 6709 1.1 fvdl ahd_compile_devinfo(&devinfo, ahd->our_id, 6710 1.1 fvdl targ, CAM_LUN_WILDCARD, 6711 1.1 fvdl 'A', ROLE_INITIATOR); 6712 1.1 fvdl ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6713 1.1 fvdl AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6714 1.1 fvdl ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6715 1.1 fvdl /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6716 1.1 fvdl /*paused*/TRUE); 6717 1.1 fvdl } 6718 1.1 fvdl 6719 1.1 fvdl ahd->flags &= ~AHD_SPCHK_ENB_A; 6720 1.1 fvdl if (sc->bios_control & CFSPARITY) 6721 1.1 fvdl ahd->flags |= AHD_SPCHK_ENB_A; 6722 1.1 fvdl 6723 1.1 fvdl ahd->flags &= ~AHD_RESET_BUS_A; 6724 1.1 fvdl if (sc->bios_control & CFRESETB) 6725 1.1 fvdl ahd->flags |= AHD_RESET_BUS_A; 6726 1.1 fvdl 6727 1.1 fvdl ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6728 1.1 fvdl if (sc->bios_control & CFEXTEND) 6729 1.1 fvdl ahd->flags |= AHD_EXTENDED_TRANS_A; 6730 1.1 fvdl 6731 1.1 fvdl ahd->flags &= ~AHD_BIOS_ENABLED; 6732 1.1 fvdl if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6733 1.1 fvdl ahd->flags |= AHD_BIOS_ENABLED; 6734 1.1 fvdl 6735 1.1 fvdl ahd->flags &= ~AHD_STPWLEVEL_A; 6736 1.1 fvdl if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6737 1.1 fvdl ahd->flags |= AHD_STPWLEVEL_A; 6738 1.1 fvdl 6739 1.1 fvdl return (0); 6740 1.1 fvdl } 6741 1.1 fvdl 6742 1.9 thorpej /* 6743 1.9 thorpej * Parse device configuration information. 6744 1.9 thorpej */ 6745 1.9 thorpej int 6746 1.9 thorpej ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6747 1.9 thorpej { 6748 1.9 thorpej int error; 6749 1.9 thorpej 6750 1.9 thorpej error = ahd_verify_vpd_cksum(vpd); 6751 1.9 thorpej if (error == 0) 6752 1.9 thorpej return (EINVAL); 6753 1.9 thorpej if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6754 1.9 thorpej ahd->flags |= AHD_BOOT_CHANNEL; 6755 1.9 thorpej return (0); 6756 1.9 thorpej } 6757 1.9 thorpej 6758 1.1 fvdl void 6759 1.1 fvdl ahd_intr_enable(struct ahd_softc *ahd, int enable) 6760 1.1 fvdl { 6761 1.1 fvdl u_int hcntrl; 6762 1.1 fvdl 6763 1.1 fvdl hcntrl = ahd_inb(ahd, HCNTRL); 6764 1.1 fvdl hcntrl &= ~INTEN; 6765 1.1 fvdl ahd->pause &= ~INTEN; 6766 1.1 fvdl ahd->unpause &= ~INTEN; 6767 1.1 fvdl if (enable) { 6768 1.1 fvdl hcntrl |= INTEN; 6769 1.1 fvdl ahd->pause |= INTEN; 6770 1.1 fvdl ahd->unpause |= INTEN; 6771 1.1 fvdl } 6772 1.1 fvdl ahd_outb(ahd, HCNTRL, hcntrl); 6773 1.1 fvdl } 6774 1.1 fvdl 6775 1.1 fvdl void 6776 1.5 wiz ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6777 1.1 fvdl u_int mincmds) 6778 1.1 fvdl { 6779 1.1 fvdl if (timer > AHD_TIMER_MAX_US) 6780 1.1 fvdl timer = AHD_TIMER_MAX_US; 6781 1.5 wiz ahd->int_coalescing_timer = timer; 6782 1.1 fvdl 6783 1.5 wiz if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6784 1.5 wiz maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6785 1.5 wiz if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6786 1.5 wiz mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6787 1.5 wiz ahd->int_coalescing_maxcmds = maxcmds; 6788 1.5 wiz ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6789 1.5 wiz ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6790 1.5 wiz ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6791 1.1 fvdl } 6792 1.1 fvdl 6793 1.1 fvdl void 6794 1.5 wiz ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 6795 1.1 fvdl { 6796 1.1 fvdl 6797 1.5 wiz ahd->hs_mailbox &= ~ENINT_COALESCE; 6798 1.1 fvdl if (enable) 6799 1.5 wiz ahd->hs_mailbox |= ENINT_COALESCE; 6800 1.1 fvdl ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6801 1.1 fvdl ahd_flush_device_writes(ahd); 6802 1.1 fvdl ahd_run_qoutfifo(ahd); 6803 1.1 fvdl } 6804 1.1 fvdl 6805 1.1 fvdl /* 6806 1.1 fvdl * Ensure that the card is paused in a location 6807 1.1 fvdl * outside of all critical sections and that all 6808 1.1 fvdl * pending work is completed prior to returning. 6809 1.1 fvdl * This routine should only be called from outside 6810 1.1 fvdl * an interrupt context. 6811 1.1 fvdl */ 6812 1.1 fvdl void 6813 1.1 fvdl ahd_pause_and_flushwork(struct ahd_softc *ahd) 6814 1.1 fvdl { 6815 1.9 thorpej u_int intstat; 6816 1.9 thorpej u_int maxloops; 6817 1.9 thorpej u_int qfreeze_cnt; 6818 1.1 fvdl 6819 1.1 fvdl maxloops = 1000; 6820 1.1 fvdl ahd->flags |= AHD_ALL_INTERRUPTS; 6821 1.9 thorpej ahd_pause(ahd); 6822 1.9 thorpej /* 6823 1.9 thorpej * Increment the QFreeze Count so that the sequencer 6824 1.9 thorpej * will not start new selections. We do this only 6825 1.9 thorpej * until we are safely paused without further selections 6826 1.9 thorpej * pending. 6827 1.9 thorpej */ 6828 1.9 thorpej ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); 6829 1.9 thorpej ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 6830 1.1 fvdl do { 6831 1.1 fvdl struct scb *waiting_scb; 6832 1.1 fvdl 6833 1.9 thorpej ahd_unpause(ahd); 6834 1.1 fvdl ahd_intr(ahd); 6835 1.1 fvdl ahd_pause(ahd); 6836 1.1 fvdl ahd_clear_critical_section(ahd); 6837 1.9 thorpej intstat = ahd_inb(ahd, INTSTAT); 6838 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6839 1.1 fvdl if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6840 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 6841 1.1 fvdl ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6842 1.1 fvdl /* 6843 1.1 fvdl * In the non-packetized case, the sequencer (for Rev A), 6844 1.1 fvdl * relies on ENSELO remaining set after SELDO. The hardware 6845 1.1 fvdl * auto-clears ENSELO in the packetized case. 6846 1.1 fvdl */ 6847 1.1 fvdl waiting_scb = ahd_lookup_scb(ahd, 6848 1.1 fvdl ahd_inw(ahd, WAITING_TID_HEAD)); 6849 1.1 fvdl if (waiting_scb != NULL 6850 1.1 fvdl && (waiting_scb->flags & SCB_PACKETIZED) == 0 6851 1.1 fvdl && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6852 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 6853 1.1 fvdl ahd_inb(ahd, SCSISEQ0) | ENSELO); 6854 1.1 fvdl } while (--maxloops 6855 1.1 fvdl && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6856 1.1 fvdl && ((intstat & INT_PEND) != 0 6857 1.9 thorpej || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 6858 1.9 thorpej || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 6859 1.1 fvdl if (maxloops == 0) { 6860 1.1 fvdl printf("Infinite interrupt loop, INTSTAT = %x", 6861 1.1 fvdl ahd_inb(ahd, INTSTAT)); 6862 1.1 fvdl } 6863 1.9 thorpej qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 6864 1.9 thorpej if (qfreeze_cnt == 0) { 6865 1.9 thorpej printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n", 6866 1.9 thorpej ahd_name(ahd)); 6867 1.9 thorpej } else { 6868 1.9 thorpej qfreeze_cnt--; 6869 1.9 thorpej } 6870 1.9 thorpej ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 6871 1.9 thorpej if (qfreeze_cnt == 0) 6872 1.9 thorpej ahd_outb(ahd, SEQ_FLAGS2, 6873 1.9 thorpej ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 6874 1.1 fvdl 6875 1.1 fvdl ahd_flush_qoutfifo(ahd); 6876 1.1 fvdl 6877 1.1 fvdl ahd_platform_flushwork(ahd); 6878 1.1 fvdl ahd->flags &= ~AHD_ALL_INTERRUPTS; 6879 1.1 fvdl } 6880 1.1 fvdl 6881 1.1 fvdl int 6882 1.1 fvdl ahd_suspend(struct ahd_softc *ahd) 6883 1.1 fvdl { 6884 1.1 fvdl 6885 1.1 fvdl ahd_pause_and_flushwork(ahd); 6886 1.1 fvdl 6887 1.15 thorpej if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 6888 1.15 thorpej ahd_unpause(ahd); 6889 1.1 fvdl return (EBUSY); 6890 1.1 fvdl } 6891 1.1 fvdl ahd_shutdown(ahd); 6892 1.1 fvdl return (0); 6893 1.1 fvdl } 6894 1.1 fvdl 6895 1.1 fvdl int 6896 1.1 fvdl ahd_resume(struct ahd_softc *ahd) 6897 1.1 fvdl { 6898 1.1 fvdl 6899 1.15 thorpej ahd_reset(ahd, /*reinit*/TRUE); 6900 1.15 thorpej ahd_intr_enable(ahd, TRUE); 6901 1.15 thorpej ahd_restart(ahd); 6902 1.1 fvdl return (0); 6903 1.1 fvdl } 6904 1.1 fvdl 6905 1.1 fvdl /************************** Busy Target Table *********************************/ 6906 1.1 fvdl /* 6907 1.1 fvdl * Set SCBPTR to the SCB that contains the busy 6908 1.1 fvdl * table entry for TCL. Return the offset into 6909 1.1 fvdl * the SCB that contains the entry for TCL. 6910 1.1 fvdl * saved_scbid is dereferenced and set to the 6911 1.64 andvar * scbid that should be restored once manipulation 6912 1.1 fvdl * of the TCL entry is complete. 6913 1.1 fvdl */ 6914 1.33 perry static inline u_int 6915 1.1 fvdl ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6916 1.1 fvdl { 6917 1.1 fvdl /* 6918 1.1 fvdl * Index to the SCB that contains the busy entry. 6919 1.1 fvdl */ 6920 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6921 1.1 fvdl *saved_scbid = ahd_get_scbptr(ahd); 6922 1.1 fvdl ahd_set_scbptr(ahd, TCL_LUN(tcl) 6923 1.1 fvdl | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6924 1.1 fvdl 6925 1.1 fvdl /* 6926 1.1 fvdl * And now calculate the SCB offset to the entry. 6927 1.1 fvdl * Each entry is 2 bytes wide, hence the 6928 1.1 fvdl * multiplication by 2. 6929 1.1 fvdl */ 6930 1.1 fvdl return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6931 1.1 fvdl } 6932 1.1 fvdl 6933 1.1 fvdl /* 6934 1.1 fvdl * Return the untagged transaction id for a given target/channel lun. 6935 1.1 fvdl */ 6936 1.1 fvdl u_int 6937 1.1 fvdl ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6938 1.1 fvdl { 6939 1.1 fvdl u_int scbid; 6940 1.1 fvdl u_int scb_offset; 6941 1.1 fvdl u_int saved_scbptr; 6942 1.30 perry 6943 1.1 fvdl scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6944 1.1 fvdl scbid = ahd_inw_scbram(ahd, scb_offset); 6945 1.1 fvdl ahd_set_scbptr(ahd, saved_scbptr); 6946 1.1 fvdl return (scbid); 6947 1.1 fvdl } 6948 1.1 fvdl 6949 1.1 fvdl void 6950 1.1 fvdl ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6951 1.1 fvdl { 6952 1.1 fvdl u_int scb_offset; 6953 1.1 fvdl u_int saved_scbptr; 6954 1.30 perry 6955 1.1 fvdl scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6956 1.1 fvdl ahd_outw(ahd, scb_offset, scbid); 6957 1.1 fvdl ahd_set_scbptr(ahd, saved_scbptr); 6958 1.1 fvdl } 6959 1.1 fvdl 6960 1.1 fvdl /************************** SCB and SCB queue management **********************/ 6961 1.1 fvdl int 6962 1.36 christos ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6963 1.36 christos char channel, int lun, u_int tag, role_t role) 6964 1.1 fvdl { 6965 1.1 fvdl int targ = SCB_GET_TARGET(ahd, scb); 6966 1.1 fvdl char chan = SCB_GET_CHANNEL(ahd, scb); 6967 1.1 fvdl int slun = SCB_GET_LUN(scb); 6968 1.1 fvdl int match; 6969 1.1 fvdl 6970 1.1 fvdl match = ((chan == channel) || (channel == ALL_CHANNELS)); 6971 1.1 fvdl if (match != 0) 6972 1.1 fvdl match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6973 1.1 fvdl if (match != 0) 6974 1.1 fvdl match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6975 1.1 fvdl if (match != 0) { 6976 1.1 fvdl #if AHD_TARGET_MODE 6977 1.1 fvdl int group; 6978 1.1 fvdl 6979 1.1 fvdl group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6980 1.1 fvdl if (role == ROLE_INITIATOR) { 6981 1.1 fvdl match = (group != XPT_FC_GROUP_TMODE) 6982 1.1 fvdl && ((tag == SCB_GET_TAG(scb)) 6983 1.1 fvdl || (tag == SCB_LIST_NULL)); 6984 1.1 fvdl } else if (role == ROLE_TARGET) { 6985 1.1 fvdl match = (group == XPT_FC_GROUP_TMODE) 6986 1.1 fvdl && ((tag == scb->io_ctx->csio.tag_id) 6987 1.1 fvdl || (tag == SCB_LIST_NULL)); 6988 1.1 fvdl } 6989 1.1 fvdl #else /* !AHD_TARGET_MODE */ 6990 1.1 fvdl match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6991 1.1 fvdl #endif /* AHD_TARGET_MODE */ 6992 1.1 fvdl } 6993 1.1 fvdl 6994 1.1 fvdl return match; 6995 1.1 fvdl } 6996 1.1 fvdl 6997 1.1 fvdl void 6998 1.1 fvdl ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6999 1.1 fvdl { 7000 1.1 fvdl int target; 7001 1.1 fvdl char channel; 7002 1.1 fvdl int lun; 7003 1.1 fvdl 7004 1.1 fvdl target = SCB_GET_TARGET(ahd, scb); 7005 1.1 fvdl lun = SCB_GET_LUN(scb); 7006 1.1 fvdl channel = SCB_GET_CHANNEL(ahd, scb); 7007 1.30 perry 7008 1.1 fvdl ahd_search_qinfifo(ahd, target, channel, lun, 7009 1.1 fvdl /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 7010 1.1 fvdl CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7011 1.1 fvdl 7012 1.1 fvdl ahd_platform_freeze_devq(ahd, scb); 7013 1.1 fvdl } 7014 1.1 fvdl 7015 1.1 fvdl void 7016 1.1 fvdl ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 7017 1.1 fvdl { 7018 1.1 fvdl struct scb *prev_scb; 7019 1.1 fvdl ahd_mode_state saved_modes; 7020 1.1 fvdl 7021 1.1 fvdl saved_modes = ahd_save_modes(ahd); 7022 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7023 1.1 fvdl prev_scb = NULL; 7024 1.1 fvdl if (ahd_qinfifo_count(ahd) != 0) { 7025 1.1 fvdl u_int prev_tag; 7026 1.1 fvdl u_int prev_pos; 7027 1.1 fvdl 7028 1.1 fvdl prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 7029 1.1 fvdl prev_tag = ahd->qinfifo[prev_pos]; 7030 1.1 fvdl prev_scb = ahd_lookup_scb(ahd, prev_tag); 7031 1.1 fvdl } 7032 1.1 fvdl ahd_qinfifo_requeue(ahd, prev_scb, scb); 7033 1.1 fvdl ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7034 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 7035 1.1 fvdl } 7036 1.1 fvdl 7037 1.1 fvdl static void 7038 1.1 fvdl ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 7039 1.1 fvdl struct scb *scb) 7040 1.1 fvdl { 7041 1.1 fvdl if (prev_scb == NULL) { 7042 1.1 fvdl uint32_t busaddr; 7043 1.1 fvdl 7044 1.1 fvdl busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 7045 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7046 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7047 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7048 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7049 1.1 fvdl } else { 7050 1.1 fvdl prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 7051 1.30 perry ahd_sync_scb(ahd, prev_scb, 7052 1.1 fvdl BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7053 1.1 fvdl } 7054 1.1 fvdl ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 7055 1.1 fvdl ahd->qinfifonext++; 7056 1.1 fvdl scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 7057 1.1 fvdl ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7058 1.1 fvdl } 7059 1.1 fvdl 7060 1.1 fvdl static int 7061 1.1 fvdl ahd_qinfifo_count(struct ahd_softc *ahd) 7062 1.1 fvdl { 7063 1.1 fvdl u_int qinpos; 7064 1.1 fvdl u_int wrap_qinpos; 7065 1.1 fvdl u_int wrap_qinfifonext; 7066 1.1 fvdl 7067 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7068 1.1 fvdl qinpos = ahd_get_snscb_qoff(ahd); 7069 1.1 fvdl wrap_qinpos = AHD_QIN_WRAP(qinpos); 7070 1.1 fvdl wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 7071 1.1 fvdl if (wrap_qinfifonext >= wrap_qinpos) 7072 1.1 fvdl return (wrap_qinfifonext - wrap_qinpos); 7073 1.1 fvdl else 7074 1.1 fvdl return (wrap_qinfifonext 7075 1.1 fvdl + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 7076 1.1 fvdl } 7077 1.1 fvdl 7078 1.1 fvdl void 7079 1.1 fvdl ahd_reset_cmds_pending(struct ahd_softc *ahd) 7080 1.1 fvdl { 7081 1.1 fvdl struct scb *scb; 7082 1.1 fvdl ahd_mode_state saved_modes; 7083 1.1 fvdl u_int pending_cmds; 7084 1.1 fvdl 7085 1.1 fvdl saved_modes = ahd_save_modes(ahd); 7086 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7087 1.1 fvdl 7088 1.1 fvdl /* 7089 1.1 fvdl * Don't count any commands as outstanding that the 7090 1.1 fvdl * sequencer has already marked for completion. 7091 1.1 fvdl */ 7092 1.1 fvdl ahd_flush_qoutfifo(ahd); 7093 1.1 fvdl 7094 1.1 fvdl pending_cmds = 0; 7095 1.1 fvdl LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7096 1.1 fvdl pending_cmds++; 7097 1.1 fvdl } 7098 1.1 fvdl ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 7099 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 7100 1.1 fvdl ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 7101 1.1 fvdl } 7102 1.1 fvdl 7103 1.1 fvdl int 7104 1.1 fvdl ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 7105 1.1 fvdl int lun, u_int tag, role_t role, uint32_t status, 7106 1.1 fvdl ahd_search_action action) 7107 1.1 fvdl { 7108 1.1 fvdl struct scb *scb; 7109 1.1 fvdl struct scb *prev_scb; 7110 1.1 fvdl ahd_mode_state saved_modes; 7111 1.1 fvdl u_int qinstart; 7112 1.1 fvdl u_int qinpos; 7113 1.1 fvdl u_int qintail; 7114 1.1 fvdl u_int tid_next; 7115 1.1 fvdl u_int tid_prev; 7116 1.1 fvdl u_int scbid; 7117 1.1 fvdl u_int savedscbptr; 7118 1.1 fvdl uint32_t busaddr; 7119 1.1 fvdl int found; 7120 1.1 fvdl int targets; 7121 1.1 fvdl int pending_cmds; 7122 1.1 fvdl 7123 1.1 fvdl /* Must be in CCHAN mode */ 7124 1.1 fvdl saved_modes = ahd_save_modes(ahd); 7125 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7126 1.1 fvdl 7127 1.1 fvdl /* 7128 1.1 fvdl * Halt any pending SCB DMA. The sequencer will reinitiate 7129 1.4 wiz * this DMA if the qinfifo is not empty once we unpause. 7130 1.1 fvdl */ 7131 1.1 fvdl if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7132 1.1 fvdl == (CCARREN|CCSCBEN|CCSCBDIR)) { 7133 1.1 fvdl ahd_outb(ahd, CCSCBCTL, 7134 1.1 fvdl ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7135 1.1 fvdl while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7136 1.1 fvdl ; 7137 1.1 fvdl } 7138 1.1 fvdl /* Determine sequencer's position in the qinfifo. */ 7139 1.1 fvdl qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7140 1.1 fvdl qinstart = ahd_get_snscb_qoff(ahd); 7141 1.1 fvdl qinpos = AHD_QIN_WRAP(qinstart); 7142 1.1 fvdl found = 0; 7143 1.1 fvdl prev_scb = NULL; 7144 1.1 fvdl 7145 1.1 fvdl pending_cmds = 0; 7146 1.1 fvdl LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7147 1.1 fvdl pending_cmds++; 7148 1.1 fvdl } 7149 1.46 christos (void)ahd_qinfifo_count(ahd); 7150 1.1 fvdl 7151 1.1 fvdl if (action == SEARCH_PRINT) { 7152 1.1 fvdl printf("qinstart = 0x%x qinfifonext = 0x%x\n", 7153 1.1 fvdl qinstart, ahd->qinfifonext); 7154 1.1 fvdl } 7155 1.1 fvdl 7156 1.1 fvdl /* 7157 1.1 fvdl * Start with an empty queue. Entries that are not chosen 7158 1.1 fvdl * for removal will be re-added to the queue as we go. 7159 1.1 fvdl */ 7160 1.1 fvdl ahd->qinfifonext = qinstart; 7161 1.1 fvdl busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7162 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7163 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7164 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7165 1.1 fvdl ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7166 1.1 fvdl 7167 1.1 fvdl while (qinpos != qintail) { 7168 1.1 fvdl scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7169 1.1 fvdl if (scb == NULL) { 7170 1.1 fvdl panic("Loop 1\n"); 7171 1.1 fvdl } 7172 1.1 fvdl 7173 1.1 fvdl if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7174 1.1 fvdl /* 7175 1.1 fvdl * We found an scb that needs to be acted on. 7176 1.1 fvdl */ 7177 1.1 fvdl found++; 7178 1.1 fvdl switch (action) { 7179 1.1 fvdl case SEARCH_COMPLETE: 7180 1.1 fvdl { 7181 1.43 tsutsui cam_status ostat; 7182 1.43 tsutsui cam_status cstat; 7183 1.1 fvdl 7184 1.1 fvdl ostat = ahd_get_scsi_status(scb); 7185 1.1 fvdl if (ostat == CAM_REQ_INPROG) 7186 1.1 fvdl ahd_set_scsi_status(scb, status); 7187 1.1 fvdl cstat = ahd_get_transaction_status(scb); 7188 1.1 fvdl if (cstat != CAM_REQ_CMP) 7189 1.1 fvdl ahd_freeze_scb(scb); 7190 1.1 fvdl if ((scb->flags & SCB_ACTIVE) == 0) 7191 1.1 fvdl printf("Inactive SCB in qinfifo\n"); 7192 1.45 mrg if ((cam_status)scb->xs->error != CAM_REQ_CMP) 7193 1.44 tsutsui printf("SEARCH_COMPLETE(0x%x):" 7194 1.44 tsutsui " ostat 0x%x, cstat 0x%x, " 7195 1.44 tsutsui "xs_error 0x%x\n", 7196 1.44 tsutsui SCB_GET_TAG(scb), ostat, cstat, 7197 1.44 tsutsui scb->xs->error); 7198 1.1 fvdl ahd_done(ahd, scb); 7199 1.1 fvdl 7200 1.1 fvdl /* FALLTHROUGH */ 7201 1.1 fvdl } 7202 1.1 fvdl case SEARCH_REMOVE: 7203 1.1 fvdl break; 7204 1.1 fvdl case SEARCH_PRINT: 7205 1.1 fvdl printf(" 0x%x", ahd->qinfifo[qinpos]); 7206 1.1 fvdl /* FALLTHROUGH */ 7207 1.1 fvdl case SEARCH_COUNT: 7208 1.1 fvdl ahd_qinfifo_requeue(ahd, prev_scb, scb); 7209 1.1 fvdl prev_scb = scb; 7210 1.1 fvdl break; 7211 1.1 fvdl } 7212 1.1 fvdl } else { 7213 1.1 fvdl ahd_qinfifo_requeue(ahd, prev_scb, scb); 7214 1.1 fvdl prev_scb = scb; 7215 1.1 fvdl } 7216 1.1 fvdl qinpos = AHD_QIN_WRAP(qinpos+1); 7217 1.1 fvdl } 7218 1.1 fvdl 7219 1.1 fvdl ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7220 1.1 fvdl 7221 1.1 fvdl if (action == SEARCH_PRINT) 7222 1.1 fvdl printf("\nWAITING_TID_QUEUES:\n"); 7223 1.1 fvdl 7224 1.1 fvdl /* 7225 1.1 fvdl * Search waiting for selection lists. We traverse the 7226 1.1 fvdl * list of "their ids" waiting for selection and, if 7227 1.1 fvdl * appropriate, traverse the SCBs of each "their id" 7228 1.1 fvdl * looking for matches. 7229 1.1 fvdl */ 7230 1.1 fvdl savedscbptr = ahd_get_scbptr(ahd); 7231 1.1 fvdl tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7232 1.1 fvdl tid_prev = SCB_LIST_NULL; 7233 1.1 fvdl targets = 0; 7234 1.1 fvdl for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7235 1.1 fvdl u_int tid_head; 7236 1.1 fvdl 7237 1.1 fvdl /* 7238 1.1 fvdl * We limit based on the number of SCBs since 7239 1.1 fvdl * MK_MESSAGE SCBs are not in the per-tid lists. 7240 1.1 fvdl */ 7241 1.1 fvdl targets++; 7242 1.1 fvdl if (targets > AHD_SCB_MAX) { 7243 1.1 fvdl panic("TID LIST LOOP"); 7244 1.1 fvdl } 7245 1.1 fvdl if (scbid >= ahd->scb_data.numscbs) { 7246 1.1 fvdl printf("%s: Waiting TID List inconsistency. " 7247 1.1 fvdl "SCB index == 0x%x, yet numscbs == 0x%x.", 7248 1.1 fvdl ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7249 1.1 fvdl ahd_dump_card_state(ahd); 7250 1.1 fvdl panic("for safety"); 7251 1.1 fvdl } 7252 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 7253 1.1 fvdl if (scb == NULL) { 7254 1.1 fvdl printf("%s: SCB = 0x%x Not Active!\n", 7255 1.1 fvdl ahd_name(ahd), scbid); 7256 1.1 fvdl panic("Waiting TID List traversal\n"); 7257 1.1 fvdl break; 7258 1.1 fvdl } 7259 1.1 fvdl ahd_set_scbptr(ahd, scbid); 7260 1.1 fvdl tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7261 1.1 fvdl if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7262 1.1 fvdl SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7263 1.1 fvdl tid_prev = scbid; 7264 1.1 fvdl continue; 7265 1.1 fvdl } 7266 1.1 fvdl 7267 1.1 fvdl /* 7268 1.1 fvdl * We found a list of scbs that needs to be searched. 7269 1.1 fvdl */ 7270 1.1 fvdl if (action == SEARCH_PRINT) 7271 1.1 fvdl printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7272 1.1 fvdl tid_head = scbid; 7273 1.1 fvdl found += ahd_search_scb_list(ahd, target, channel, 7274 1.1 fvdl lun, tag, role, status, 7275 1.1 fvdl action, &tid_head, 7276 1.1 fvdl SCB_GET_TARGET(ahd, scb)); 7277 1.1 fvdl if (tid_head != scbid) 7278 1.1 fvdl ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7279 1.1 fvdl if (!SCBID_IS_NULL(tid_head)) 7280 1.1 fvdl tid_prev = tid_head; 7281 1.1 fvdl if (action == SEARCH_PRINT) 7282 1.1 fvdl printf(")\n"); 7283 1.1 fvdl } 7284 1.1 fvdl ahd_set_scbptr(ahd, savedscbptr); 7285 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 7286 1.1 fvdl return (found); 7287 1.1 fvdl } 7288 1.1 fvdl 7289 1.1 fvdl static int 7290 1.1 fvdl ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7291 1.36 christos int lun, u_int tag, role_t role, uint32_t status, 7292 1.1 fvdl ahd_search_action action, u_int *list_head, u_int tid) 7293 1.1 fvdl { 7294 1.1 fvdl struct scb *scb; 7295 1.1 fvdl u_int scbid; 7296 1.1 fvdl u_int next; 7297 1.1 fvdl u_int prev; 7298 1.1 fvdl int found; 7299 1.1 fvdl 7300 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7301 1.1 fvdl found = 0; 7302 1.1 fvdl prev = SCB_LIST_NULL; 7303 1.1 fvdl next = *list_head; 7304 1.1 fvdl for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7305 1.1 fvdl if (scbid >= ahd->scb_data.numscbs) { 7306 1.1 fvdl printf("%s:SCB List inconsistency. " 7307 1.1 fvdl "SCB == 0x%x, yet numscbs == 0x%x.", 7308 1.1 fvdl ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7309 1.1 fvdl ahd_dump_card_state(ahd); 7310 1.1 fvdl panic("for safety"); 7311 1.1 fvdl } 7312 1.1 fvdl scb = ahd_lookup_scb(ahd, scbid); 7313 1.1 fvdl if (scb == NULL) { 7314 1.1 fvdl printf("%s: SCB = %d Not Active!\n", 7315 1.1 fvdl ahd_name(ahd), scbid); 7316 1.1 fvdl panic("Waiting List traversal\n"); 7317 1.1 fvdl } 7318 1.1 fvdl ahd_set_scbptr(ahd, scbid); 7319 1.1 fvdl next = ahd_inw_scbram(ahd, SCB_NEXT); 7320 1.1 fvdl if (ahd_match_scb(ahd, scb, target, channel, 7321 1.1 fvdl lun, SCB_LIST_NULL, role) == 0) { 7322 1.1 fvdl prev = scbid; 7323 1.1 fvdl continue; 7324 1.1 fvdl } 7325 1.1 fvdl found++; 7326 1.1 fvdl switch (action) { 7327 1.1 fvdl case SEARCH_COMPLETE: 7328 1.1 fvdl { 7329 1.1 fvdl cam_status ostat; 7330 1.1 fvdl cam_status cstat; 7331 1.1 fvdl 7332 1.1 fvdl ostat = ahd_get_scsi_status(scb); 7333 1.1 fvdl if (ostat == CAM_REQ_INPROG) 7334 1.1 fvdl ahd_set_scsi_status(scb, status); 7335 1.1 fvdl cstat = ahd_get_transaction_status(scb); 7336 1.1 fvdl if (cstat != CAM_REQ_CMP) 7337 1.1 fvdl ahd_freeze_scb(scb); 7338 1.1 fvdl if ((scb->flags & SCB_ACTIVE) == 0) 7339 1.1 fvdl printf("Inactive SCB in Waiting List\n"); 7340 1.1 fvdl ahd_done(ahd, scb); 7341 1.1 fvdl } 7342 1.51 mrg /* FALLTHROUGH */ 7343 1.1 fvdl case SEARCH_REMOVE: 7344 1.1 fvdl ahd_rem_wscb(ahd, scbid, prev, next, tid); 7345 1.1 fvdl if (prev == SCB_LIST_NULL) 7346 1.1 fvdl *list_head = next; 7347 1.1 fvdl break; 7348 1.1 fvdl case SEARCH_PRINT: 7349 1.1 fvdl printf("0x%x ", scbid); 7350 1.51 mrg /* FALLTHROUGH */ 7351 1.1 fvdl case SEARCH_COUNT: 7352 1.1 fvdl prev = scbid; 7353 1.1 fvdl break; 7354 1.1 fvdl } 7355 1.1 fvdl if (found > AHD_SCB_MAX) 7356 1.1 fvdl panic("SCB LIST LOOP"); 7357 1.1 fvdl } 7358 1.1 fvdl if (action == SEARCH_COMPLETE 7359 1.1 fvdl || action == SEARCH_REMOVE) 7360 1.1 fvdl ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7361 1.1 fvdl return (found); 7362 1.1 fvdl } 7363 1.1 fvdl 7364 1.1 fvdl static void 7365 1.1 fvdl ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7366 1.1 fvdl u_int tid_cur, u_int tid_next) 7367 1.1 fvdl { 7368 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7369 1.1 fvdl 7370 1.1 fvdl if (SCBID_IS_NULL(tid_cur)) { 7371 1.1 fvdl 7372 1.1 fvdl /* Bypass current TID list */ 7373 1.1 fvdl if (SCBID_IS_NULL(tid_prev)) { 7374 1.1 fvdl ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7375 1.1 fvdl } else { 7376 1.1 fvdl ahd_set_scbptr(ahd, tid_prev); 7377 1.1 fvdl ahd_outw(ahd, SCB_NEXT2, tid_next); 7378 1.1 fvdl } 7379 1.1 fvdl if (SCBID_IS_NULL(tid_next)) 7380 1.1 fvdl ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7381 1.1 fvdl } else { 7382 1.1 fvdl 7383 1.1 fvdl /* Stitch through tid_cur */ 7384 1.1 fvdl if (SCBID_IS_NULL(tid_prev)) { 7385 1.1 fvdl ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7386 1.1 fvdl } else { 7387 1.1 fvdl ahd_set_scbptr(ahd, tid_prev); 7388 1.1 fvdl ahd_outw(ahd, SCB_NEXT2, tid_cur); 7389 1.1 fvdl } 7390 1.1 fvdl ahd_set_scbptr(ahd, tid_cur); 7391 1.1 fvdl ahd_outw(ahd, SCB_NEXT2, tid_next); 7392 1.1 fvdl 7393 1.1 fvdl if (SCBID_IS_NULL(tid_next)) 7394 1.1 fvdl ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7395 1.1 fvdl } 7396 1.1 fvdl } 7397 1.1 fvdl 7398 1.1 fvdl /* 7399 1.1 fvdl * Manipulate the waiting for selection list and return the 7400 1.1 fvdl * scb that follows the one that we remove. 7401 1.1 fvdl */ 7402 1.1 fvdl static u_int 7403 1.1 fvdl ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7404 1.1 fvdl u_int prev, u_int next, u_int tid) 7405 1.1 fvdl { 7406 1.1 fvdl u_int tail_offset; 7407 1.1 fvdl 7408 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7409 1.1 fvdl if (!SCBID_IS_NULL(prev)) { 7410 1.1 fvdl ahd_set_scbptr(ahd, prev); 7411 1.1 fvdl ahd_outw(ahd, SCB_NEXT, next); 7412 1.1 fvdl } 7413 1.1 fvdl 7414 1.1 fvdl /* 7415 1.1 fvdl * SCBs that had MK_MESSAGE set in them will not 7416 1.1 fvdl * be queued to the per-target lists, so don't 7417 1.1 fvdl * blindly clear the tail pointer. 7418 1.1 fvdl */ 7419 1.1 fvdl tail_offset = WAITING_SCB_TAILS + (2 * tid); 7420 1.1 fvdl if (SCBID_IS_NULL(next) 7421 1.1 fvdl && ahd_inw(ahd, tail_offset) == scbid) 7422 1.1 fvdl ahd_outw(ahd, tail_offset, prev); 7423 1.1 fvdl ahd_add_scb_to_free_list(ahd, scbid); 7424 1.1 fvdl return (next); 7425 1.1 fvdl } 7426 1.1 fvdl 7427 1.1 fvdl /* 7428 1.1 fvdl * Add the SCB as selected by SCBPTR onto the on chip list of 7429 1.1 fvdl * free hardware SCBs. This list is empty/unused if we are not 7430 1.1 fvdl * performing SCB paging. 7431 1.1 fvdl */ 7432 1.1 fvdl static void 7433 1.36 christos ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7434 1.1 fvdl { 7435 1.35 christos #ifdef notdef 7436 1.1 fvdl /* XXX Need some other mechanism to designate "free". */ 7437 1.1 fvdl /* 7438 1.1 fvdl * Invalidate the tag so that our abort 7439 1.1 fvdl * routines don't think it's active. 7440 1.35 christos */ 7441 1.1 fvdl ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7442 1.35 christos #endif 7443 1.1 fvdl } 7444 1.1 fvdl 7445 1.1 fvdl /******************************** Error Handling ******************************/ 7446 1.1 fvdl /* 7447 1.1 fvdl * Abort all SCBs that match the given description (target/channel/lun/tag), 7448 1.1 fvdl * setting their status to the passed in status if the status has not already 7449 1.1 fvdl * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7450 1.1 fvdl * is paused before it is called. 7451 1.1 fvdl */ 7452 1.1 fvdl int 7453 1.1 fvdl ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7454 1.1 fvdl int lun, u_int tag, role_t role, uint32_t status) 7455 1.1 fvdl { 7456 1.1 fvdl struct scb *scbp; 7457 1.1 fvdl struct scb *scbp_next; 7458 1.1 fvdl u_int i, j; 7459 1.1 fvdl u_int maxtarget; 7460 1.1 fvdl u_int minlun; 7461 1.1 fvdl u_int maxlun; 7462 1.1 fvdl int found; 7463 1.1 fvdl ahd_mode_state saved_modes; 7464 1.1 fvdl 7465 1.9 thorpej /* restore this when we're done */ 7466 1.1 fvdl saved_modes = ahd_save_modes(ahd); 7467 1.9 thorpej ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7468 1.1 fvdl 7469 1.1 fvdl found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7470 1.1 fvdl role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7471 1.1 fvdl 7472 1.1 fvdl /* 7473 1.1 fvdl * Clean out the busy target table for any untagged commands. 7474 1.1 fvdl */ 7475 1.1 fvdl i = 0; 7476 1.1 fvdl maxtarget = 16; 7477 1.1 fvdl if (target != CAM_TARGET_WILDCARD) { 7478 1.1 fvdl i = target; 7479 1.1 fvdl if (channel == 'B') 7480 1.1 fvdl i += 8; 7481 1.1 fvdl maxtarget = i + 1; 7482 1.1 fvdl } 7483 1.1 fvdl 7484 1.1 fvdl if (lun == CAM_LUN_WILDCARD) { 7485 1.1 fvdl minlun = 0; 7486 1.1 fvdl maxlun = AHD_NUM_LUNS_NONPKT; 7487 1.1 fvdl } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7488 1.1 fvdl minlun = maxlun = 0; 7489 1.1 fvdl } else { 7490 1.1 fvdl minlun = lun; 7491 1.1 fvdl maxlun = lun + 1; 7492 1.1 fvdl } 7493 1.1 fvdl 7494 1.1 fvdl if (role != ROLE_TARGET) { 7495 1.1 fvdl for (;i < maxtarget; i++) { 7496 1.1 fvdl for (j = minlun;j < maxlun; j++) { 7497 1.1 fvdl u_int scbid; 7498 1.1 fvdl u_int tcl; 7499 1.1 fvdl 7500 1.1 fvdl tcl = BUILD_TCL_RAW(i, 'A', j); 7501 1.1 fvdl scbid = ahd_find_busy_tcl(ahd, tcl); 7502 1.1 fvdl scbp = ahd_lookup_scb(ahd, scbid); 7503 1.1 fvdl if (scbp == NULL 7504 1.1 fvdl || ahd_match_scb(ahd, scbp, target, channel, 7505 1.1 fvdl lun, tag, role) == 0) 7506 1.1 fvdl continue; 7507 1.1 fvdl ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7508 1.1 fvdl } 7509 1.1 fvdl } 7510 1.1 fvdl } 7511 1.1 fvdl 7512 1.1 fvdl /* 7513 1.1 fvdl * Don't abort commands that have already completed, 7514 1.1 fvdl * but haven't quite made it up to the host yet. 7515 1.1 fvdl */ 7516 1.1 fvdl ahd_flush_qoutfifo(ahd); 7517 1.1 fvdl 7518 1.1 fvdl /* 7519 1.1 fvdl * Go through the pending CCB list and look for 7520 1.1 fvdl * commands for this target that are still active. 7521 1.1 fvdl * These are other tagged commands that were 7522 1.1 fvdl * disconnected when the reset occurred. 7523 1.1 fvdl */ 7524 1.1 fvdl scbp_next = LIST_FIRST(&ahd->pending_scbs); 7525 1.1 fvdl while (scbp_next != NULL) { 7526 1.1 fvdl scbp = scbp_next; 7527 1.1 fvdl scbp_next = LIST_NEXT(scbp, pending_links); 7528 1.1 fvdl if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7529 1.1 fvdl cam_status ostat; 7530 1.1 fvdl 7531 1.1 fvdl ostat = ahd_get_scsi_status(scbp); 7532 1.1 fvdl if (ostat == CAM_REQ_INPROG) 7533 1.1 fvdl ahd_set_scsi_status(scbp, status); 7534 1.1 fvdl if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7535 1.1 fvdl ahd_freeze_scb(scbp); 7536 1.1 fvdl if ((scbp->flags & SCB_ACTIVE) == 0) 7537 1.1 fvdl printf("Inactive SCB on pending list\n"); 7538 1.1 fvdl ahd_done(ahd, scbp); 7539 1.1 fvdl found++; 7540 1.1 fvdl } 7541 1.1 fvdl } 7542 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 7543 1.1 fvdl ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7544 1.1 fvdl ahd->flags |= AHD_UPDATE_PEND_CMDS; 7545 1.1 fvdl return found; 7546 1.1 fvdl } 7547 1.1 fvdl 7548 1.1 fvdl static void 7549 1.1 fvdl ahd_reset_current_bus(struct ahd_softc *ahd) 7550 1.1 fvdl { 7551 1.1 fvdl uint8_t scsiseq; 7552 1.1 fvdl 7553 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7554 1.1 fvdl ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7555 1.1 fvdl scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7556 1.1 fvdl ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7557 1.19 thorpej ahd_flush_device_writes(ahd); 7558 1.1 fvdl ahd_delay(AHD_BUSRESET_DELAY); 7559 1.1 fvdl /* Turn off the bus reset */ 7560 1.1 fvdl ahd_outb(ahd, SCSISEQ0, scsiseq); 7561 1.19 thorpej ahd_flush_device_writes(ahd); 7562 1.19 thorpej ahd_delay(AHD_BUSRESET_DELAY); 7563 1.1 fvdl if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7564 1.1 fvdl /* 7565 1.1 fvdl * 2A Razor #474 7566 1.1 fvdl * Certain chip state is not cleared for 7567 1.1 fvdl * SCSI bus resets that we initiate, so 7568 1.1 fvdl * we must reset the chip. 7569 1.1 fvdl */ 7570 1.15 thorpej ahd_reset(ahd, /*reinit*/TRUE); 7571 1.1 fvdl ahd_intr_enable(ahd, /*enable*/TRUE); 7572 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7573 1.1 fvdl } 7574 1.1 fvdl 7575 1.1 fvdl ahd_clear_intstat(ahd); 7576 1.1 fvdl } 7577 1.1 fvdl 7578 1.1 fvdl int 7579 1.1 fvdl ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7580 1.1 fvdl { 7581 1.1 fvdl struct ahd_devinfo devinfo; 7582 1.1 fvdl u_int initiator; 7583 1.1 fvdl u_int target; 7584 1.1 fvdl u_int max_scsiid; 7585 1.1 fvdl int found; 7586 1.1 fvdl u_int fifo; 7587 1.1 fvdl u_int next_fifo; 7588 1.1 fvdl 7589 1.1 fvdl 7590 1.1 fvdl ahd->pending_device = NULL; 7591 1.1 fvdl 7592 1.1 fvdl ahd_compile_devinfo(&devinfo, 7593 1.1 fvdl CAM_TARGET_WILDCARD, 7594 1.1 fvdl CAM_TARGET_WILDCARD, 7595 1.1 fvdl CAM_LUN_WILDCARD, 7596 1.1 fvdl channel, ROLE_UNKNOWN); 7597 1.1 fvdl ahd_pause(ahd); 7598 1.1 fvdl 7599 1.1 fvdl /* Make sure the sequencer is in a safe location. */ 7600 1.1 fvdl ahd_clear_critical_section(ahd); 7601 1.1 fvdl 7602 1.1 fvdl #if AHD_TARGET_MODE 7603 1.1 fvdl if ((ahd->flags & AHD_TARGETROLE) != 0) { 7604 1.1 fvdl ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7605 1.1 fvdl } 7606 1.1 fvdl #endif 7607 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7608 1.1 fvdl 7609 1.1 fvdl /* 7610 1.1 fvdl * Disable selections so no automatic hardware 7611 1.1 fvdl * functions will modify chip state. 7612 1.1 fvdl */ 7613 1.1 fvdl ahd_outb(ahd, SCSISEQ0, 0); 7614 1.1 fvdl ahd_outb(ahd, SCSISEQ1, 0); 7615 1.1 fvdl 7616 1.1 fvdl /* 7617 1.1 fvdl * Safely shut down our DMA engines. Always start with 7618 1.1 fvdl * the FIFO that is not currently active (if any are 7619 1.1 fvdl * actively connected). 7620 1.1 fvdl */ 7621 1.1 fvdl next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7622 1.1 fvdl if (next_fifo > CURRFIFO_1) 7623 1.70 andvar /* If disconnected, arbitrarily start with FIFO1. */ 7624 1.1 fvdl next_fifo = fifo = 0; 7625 1.1 fvdl do { 7626 1.1 fvdl next_fifo ^= CURRFIFO_1; 7627 1.1 fvdl ahd_set_modes(ahd, next_fifo, next_fifo); 7628 1.1 fvdl ahd_outb(ahd, DFCNTRL, 7629 1.1 fvdl ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7630 1.1 fvdl while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7631 1.1 fvdl ahd_delay(10); 7632 1.1 fvdl /* 7633 1.1 fvdl * Set CURRFIFO to the now inactive channel. 7634 1.1 fvdl */ 7635 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7636 1.1 fvdl ahd_outb(ahd, DFFSTAT, next_fifo); 7637 1.1 fvdl } while (next_fifo != fifo); 7638 1.9 thorpej 7639 1.1 fvdl /* 7640 1.1 fvdl * Reset the bus if we are initiating this reset 7641 1.1 fvdl */ 7642 1.1 fvdl ahd_clear_msg_state(ahd); 7643 1.1 fvdl ahd_outb(ahd, SIMODE1, 7644 1.1 fvdl ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7645 1.9 thorpej 7646 1.1 fvdl if (initiate_reset) 7647 1.1 fvdl ahd_reset_current_bus(ahd); 7648 1.9 thorpej 7649 1.1 fvdl ahd_clear_intstat(ahd); 7650 1.1 fvdl 7651 1.1 fvdl /* 7652 1.1 fvdl * Clean up all the state information for the 7653 1.1 fvdl * pending transactions on this bus. 7654 1.1 fvdl */ 7655 1.1 fvdl found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7656 1.1 fvdl CAM_LUN_WILDCARD, SCB_LIST_NULL, 7657 1.1 fvdl ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7658 1.1 fvdl 7659 1.1 fvdl /* 7660 1.1 fvdl * Cleanup anything left in the FIFOs. 7661 1.1 fvdl */ 7662 1.1 fvdl ahd_clear_fifo(ahd, 0); 7663 1.1 fvdl ahd_clear_fifo(ahd, 1); 7664 1.1 fvdl 7665 1.1 fvdl /* 7666 1.1 fvdl * Revert to async/narrow transfers until we renegotiate. 7667 1.1 fvdl */ 7668 1.1 fvdl max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7669 1.1 fvdl for (target = 0; target <= max_scsiid; target++) { 7670 1.1 fvdl 7671 1.1 fvdl if (ahd->enabled_targets[target] == NULL) 7672 1.1 fvdl continue; 7673 1.1 fvdl for (initiator = 0; initiator <= max_scsiid; initiator++) { 7674 1.31 christos struct ahd_devinfo dinfo; 7675 1.1 fvdl 7676 1.31 christos ahd_compile_devinfo(&dinfo, target, initiator, 7677 1.1 fvdl CAM_LUN_WILDCARD, 7678 1.1 fvdl 'A', ROLE_UNKNOWN); 7679 1.31 christos ahd_set_width(ahd, &dinfo, MSG_EXT_WDTR_BUS_8_BIT, 7680 1.1 fvdl AHD_TRANS_CUR, /*paused*/TRUE); 7681 1.31 christos ahd_set_syncrate(ahd, &dinfo, /*period*/0, 7682 1.1 fvdl /*offset*/0, /*ppr_options*/0, 7683 1.1 fvdl AHD_TRANS_CUR, /*paused*/TRUE); 7684 1.1 fvdl } 7685 1.1 fvdl } 7686 1.1 fvdl 7687 1.1 fvdl #ifdef AHD_TARGET_MODE 7688 1.1 fvdl max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7689 1.1 fvdl 7690 1.1 fvdl /* 7691 1.1 fvdl * Send an immediate notify ccb to all target more peripheral 7692 1.1 fvdl * drivers affected by this action. 7693 1.1 fvdl */ 7694 1.1 fvdl for (target = 0; target <= max_scsiid; target++) { 7695 1.1 fvdl struct ahd_tmode_tstate* tstate; 7696 1.1 fvdl u_int lun; 7697 1.1 fvdl 7698 1.1 fvdl tstate = ahd->enabled_targets[target]; 7699 1.1 fvdl if (tstate == NULL) 7700 1.1 fvdl continue; 7701 1.1 fvdl for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7702 1.1 fvdl struct ahd_tmode_lstate* lstate; 7703 1.1 fvdl 7704 1.1 fvdl lstate = tstate->enabled_luns[lun]; 7705 1.1 fvdl if (lstate == NULL) 7706 1.1 fvdl continue; 7707 1.1 fvdl 7708 1.1 fvdl ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7709 1.1 fvdl EVENT_TYPE_BUS_RESET, /*arg*/0); 7710 1.1 fvdl ahd_send_lstate_events(ahd, lstate); 7711 1.1 fvdl } 7712 1.1 fvdl } 7713 1.1 fvdl #endif 7714 1.1 fvdl 7715 1.1 fvdl /* Notify the XPT that a bus reset occurred */ 7716 1.1 fvdl ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7717 1.1 fvdl CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7718 1.1 fvdl ahd_restart(ahd); 7719 1.1 fvdl 7720 1.1 fvdl /* 7721 1.1 fvdl * Freeze the SIMQ until our poller can determine that 7722 1.1 fvdl * the bus reset has really gone away. We set the initial 7723 1.1 fvdl * timer to 0 to have the check performed as soon as possible 7724 1.1 fvdl * from the timer context. 7725 1.1 fvdl */ 7726 1.1 fvdl if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7727 1.1 fvdl ahd->flags |= AHD_RESET_POLL_ACTIVE; 7728 1.1 fvdl ahd_freeze_simq(ahd); 7729 1.1 fvdl ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7730 1.1 fvdl } 7731 1.1 fvdl return (found); 7732 1.1 fvdl } 7733 1.1 fvdl 7734 1.1 fvdl 7735 1.1 fvdl #define AHD_RESET_POLL_US 1000 7736 1.1 fvdl static void 7737 1.1 fvdl ahd_reset_poll(void *arg) 7738 1.1 fvdl { 7739 1.1 fvdl struct ahd_softc *ahd; 7740 1.1 fvdl u_int scsiseq1; 7741 1.1 fvdl u_long l; 7742 1.1 fvdl int s; 7743 1.30 perry 7744 1.1 fvdl ahd_list_lock(&l); 7745 1.44 tsutsui ahd = arg; 7746 1.1 fvdl if (ahd == NULL) { 7747 1.1 fvdl printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7748 1.1 fvdl ahd_list_unlock(&l); 7749 1.1 fvdl return; 7750 1.1 fvdl } 7751 1.1 fvdl ahd_lock(ahd, &s); 7752 1.1 fvdl ahd_pause(ahd); 7753 1.1 fvdl ahd_update_modes(ahd); 7754 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7755 1.1 fvdl ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7756 1.1 fvdl if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7757 1.1 fvdl ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7758 1.1 fvdl ahd_reset_poll, ahd); 7759 1.1 fvdl ahd_unpause(ahd); 7760 1.1 fvdl ahd_unlock(ahd, &s); 7761 1.1 fvdl ahd_list_unlock(&l); 7762 1.1 fvdl return; 7763 1.1 fvdl } 7764 1.1 fvdl 7765 1.1 fvdl /* Reset is now low. Complete chip reinitialization. */ 7766 1.1 fvdl ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7767 1.1 fvdl scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7768 1.1 fvdl ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7769 1.1 fvdl ahd_unpause(ahd); 7770 1.1 fvdl ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7771 1.1 fvdl ahd_unlock(ahd, &s); 7772 1.1 fvdl ahd_release_simq(ahd); 7773 1.1 fvdl ahd_list_unlock(&l); 7774 1.1 fvdl } 7775 1.1 fvdl 7776 1.1 fvdl /**************************** Statistics Processing ***************************/ 7777 1.1 fvdl static void 7778 1.1 fvdl ahd_stat_timer(void *arg) 7779 1.1 fvdl { 7780 1.1 fvdl struct ahd_softc *ahd; 7781 1.1 fvdl u_long l; 7782 1.1 fvdl int s; 7783 1.1 fvdl int enint_coal; 7784 1.30 perry 7785 1.1 fvdl ahd_list_lock(&l); 7786 1.44 tsutsui ahd = arg; 7787 1.1 fvdl if (ahd == NULL) { 7788 1.1 fvdl printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7789 1.1 fvdl ahd_list_unlock(&l); 7790 1.1 fvdl return; 7791 1.1 fvdl } 7792 1.1 fvdl ahd_lock(ahd, &s); 7793 1.1 fvdl 7794 1.5 wiz enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7795 1.5 wiz if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7796 1.5 wiz enint_coal |= ENINT_COALESCE; 7797 1.5 wiz else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7798 1.5 wiz enint_coal &= ~ENINT_COALESCE; 7799 1.1 fvdl 7800 1.5 wiz if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 7801 1.5 wiz ahd_enable_coalescing(ahd, enint_coal); 7802 1.1 fvdl #ifdef AHD_DEBUG 7803 1.5 wiz if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 7804 1.5 wiz printf("%s: Interrupt coalescing " 7805 1.1 fvdl "now %sabled. Cmds %d\n", 7806 1.1 fvdl ahd_name(ahd), 7807 1.5 wiz (enint_coal & ENINT_COALESCE) ? "en" : "dis", 7808 1.1 fvdl ahd->cmdcmplt_total); 7809 1.1 fvdl #endif 7810 1.1 fvdl } 7811 1.1 fvdl 7812 1.1 fvdl ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7813 1.1 fvdl ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7814 1.1 fvdl ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7815 1.1 fvdl ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7816 1.1 fvdl ahd_stat_timer, ahd); 7817 1.1 fvdl ahd_unlock(ahd, &s); 7818 1.1 fvdl ahd_list_unlock(&l); 7819 1.1 fvdl } 7820 1.1 fvdl 7821 1.1 fvdl /****************************** Status Processing *****************************/ 7822 1.1 fvdl void 7823 1.1 fvdl ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7824 1.1 fvdl { 7825 1.1 fvdl if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7826 1.1 fvdl ahd_handle_scsi_status(ahd, scb); 7827 1.1 fvdl } else { 7828 1.1 fvdl ahd_calc_residual(ahd, scb); 7829 1.1 fvdl ahd_done(ahd, scb); 7830 1.1 fvdl } 7831 1.1 fvdl } 7832 1.1 fvdl 7833 1.1 fvdl void 7834 1.1 fvdl ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7835 1.1 fvdl { 7836 1.1 fvdl struct hardware_scb *hscb; 7837 1.1 fvdl u_int qfreeze_cnt; 7838 1.1 fvdl 7839 1.1 fvdl /* 7840 1.1 fvdl * The sequencer freezes its select-out queue 7841 1.1 fvdl * anytime a SCSI status error occurs. We must 7842 1.1 fvdl * handle the error and decrement the QFREEZE count 7843 1.1 fvdl * to allow the sequencer to continue. 7844 1.1 fvdl */ 7845 1.30 perry hscb = scb->hscb; 7846 1.1 fvdl 7847 1.1 fvdl /* Freeze the queue until the client sees the error. */ 7848 1.1 fvdl ahd_freeze_devq(ahd, scb); 7849 1.1 fvdl ahd_freeze_scb(scb); 7850 1.1 fvdl qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7851 1.1 fvdl if (qfreeze_cnt == 0) { 7852 1.1 fvdl printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7853 1.1 fvdl } else { 7854 1.1 fvdl qfreeze_cnt--; 7855 1.1 fvdl ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7856 1.1 fvdl } 7857 1.1 fvdl if (qfreeze_cnt == 0) 7858 1.1 fvdl ahd_outb(ahd, SEQ_FLAGS2, 7859 1.1 fvdl ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7860 1.9 thorpej 7861 1.1 fvdl /* Don't want to clobber the original sense code */ 7862 1.1 fvdl if ((scb->flags & SCB_SENSE) != 0) { 7863 1.1 fvdl /* 7864 1.1 fvdl * Clear the SCB_SENSE Flag and perform 7865 1.1 fvdl * a normal command completion. 7866 1.1 fvdl */ 7867 1.1 fvdl scb->flags &= ~SCB_SENSE; 7868 1.1 fvdl ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7869 1.1 fvdl ahd_done(ahd, scb); 7870 1.1 fvdl return; 7871 1.1 fvdl } 7872 1.1 fvdl ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7873 1.1 fvdl ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7874 1.1 fvdl switch (hscb->shared_data.istatus.scsi_status) { 7875 1.1 fvdl case STATUS_PKT_SENSE: 7876 1.1 fvdl { 7877 1.1 fvdl struct scsi_status_iu_header *siu; 7878 1.1 fvdl 7879 1.1 fvdl ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7880 1.1 fvdl siu = (struct scsi_status_iu_header *)scb->sense_data; 7881 1.1 fvdl ahd_set_scsi_status(scb, siu->status); 7882 1.1 fvdl #ifdef AHD_DEBUG 7883 1.1 fvdl if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7884 1.1 fvdl ahd_print_path(ahd, scb); 7885 1.1 fvdl printf("SCB 0x%x Received PKT Status of 0x%x\n", 7886 1.1 fvdl SCB_GET_TAG(scb), siu->status); 7887 1.1 fvdl } 7888 1.1 fvdl #endif 7889 1.1 fvdl if ((siu->flags & SIU_RSPVALID) != 0) { 7890 1.1 fvdl scsipi_printaddr(scb->xs->xs_periph); 7891 1.1 fvdl if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7892 1.1 fvdl printf("Unable to parse pkt_failures\n"); 7893 1.1 fvdl } else { 7894 1.1 fvdl 7895 1.1 fvdl switch (SIU_PKTFAIL_CODE(siu)) { 7896 1.1 fvdl case SIU_PFC_NONE: 7897 1.1 fvdl printf("No packet failure found\n"); 7898 1.1 fvdl break; 7899 1.1 fvdl case SIU_PFC_CIU_FIELDS_INVALID: 7900 1.1 fvdl printf("Invalid Command IU Field\n"); 7901 1.1 fvdl break; 7902 1.1 fvdl case SIU_PFC_TMF_NOT_SUPPORTED: 7903 1.70 andvar printf("TMF not supported\n"); 7904 1.1 fvdl break; 7905 1.1 fvdl case SIU_PFC_TMF_FAILED: 7906 1.1 fvdl printf("TMF failed\n"); 7907 1.1 fvdl break; 7908 1.1 fvdl case SIU_PFC_INVALID_TYPE_CODE: 7909 1.1 fvdl printf("Invalid L_Q Type code\n"); 7910 1.1 fvdl break; 7911 1.1 fvdl case SIU_PFC_ILLEGAL_REQUEST: 7912 1.1 fvdl printf("Illegal request\n"); 7913 1.1 fvdl default: 7914 1.1 fvdl break; 7915 1.1 fvdl } 7916 1.1 fvdl } 7917 1.1 fvdl if (siu->status == SCSI_STATUS_OK) 7918 1.44 tsutsui ahd_set_transaction_status(scb, 7919 1.44 tsutsui CAM_REQ_CMP_ERR); 7920 1.1 fvdl } 7921 1.1 fvdl if ((siu->flags & SIU_SNSVALID) != 0) { 7922 1.1 fvdl scb->flags |= SCB_PKT_SENSE; 7923 1.1 fvdl #ifdef AHD_DEBUG 7924 1.1 fvdl if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7925 1.44 tsutsui printf("Sense data available (%d)\n", 7926 1.44 tsutsui siu->sense_length[0]); 7927 1.43 tsutsui printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7928 1.44 tsutsui ((uint8_t)scb->sense_data[ 7929 1.44 tsutsui SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7930 1.44 tsutsui ((uint8_t)scb->sense_data[ 7931 1.44 tsutsui SIU_SENSE_OFFSET(siu)+12]), 7932 1.44 tsutsui ((uint8_t)scb->sense_data[ 7933 1.44 tsutsui SIU_SENSE_OFFSET(siu)+13])); 7934 1.1 fvdl } 7935 1.1 fvdl #endif 7936 1.1 fvdl } 7937 1.1 fvdl ahd_done(ahd, scb); 7938 1.1 fvdl break; 7939 1.1 fvdl } 7940 1.1 fvdl case SCSI_STATUS_CMD_TERMINATED: 7941 1.1 fvdl case SCSI_STATUS_CHECK_COND: 7942 1.1 fvdl { 7943 1.1 fvdl struct ahd_devinfo devinfo; 7944 1.1 fvdl struct ahd_dma_seg *sg; 7945 1.29 thorpej struct scsi_request_sense *sc; 7946 1.1 fvdl struct ahd_initiator_tinfo *targ_info; 7947 1.1 fvdl struct ahd_tmode_tstate *tstate; 7948 1.1 fvdl #ifdef AHD_DEBUG 7949 1.1 fvdl if (ahd_debug & AHD_SHOW_SENSE) { 7950 1.1 fvdl ahd_print_path(ahd, scb); 7951 1.1 fvdl printf("SCB %d: requests Check Status\n", 7952 1.1 fvdl SCB_GET_TAG(scb)); 7953 1.1 fvdl } 7954 1.1 fvdl #endif 7955 1.1 fvdl 7956 1.1 fvdl if (ahd_perform_autosense(scb) == 0) 7957 1.1 fvdl break; 7958 1.1 fvdl 7959 1.1 fvdl ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7960 1.1 fvdl SCB_GET_TARGET(ahd, scb), 7961 1.1 fvdl SCB_GET_LUN(scb), 7962 1.1 fvdl SCB_GET_CHANNEL(ahd, scb), 7963 1.1 fvdl ROLE_INITIATOR); 7964 1.1 fvdl targ_info = ahd_fetch_transinfo(ahd, 7965 1.1 fvdl devinfo.channel, 7966 1.1 fvdl devinfo.our_scsiid, 7967 1.1 fvdl devinfo.target, 7968 1.1 fvdl &tstate); 7969 1.1 fvdl sg = scb->sg_list; 7970 1.29 thorpej sc = (struct scsi_request_sense *)hscb->shared_data.idata.cdb; 7971 1.1 fvdl /* 7972 1.1 fvdl * Save off the residual if there is one. 7973 1.1 fvdl */ 7974 1.1 fvdl ahd_update_residual(ahd, scb); 7975 1.1 fvdl #ifdef AHD_DEBUG 7976 1.1 fvdl if (ahd_debug & AHD_SHOW_SENSE) { 7977 1.1 fvdl ahd_print_path(ahd, scb); 7978 1.1 fvdl printf("Sending Sense\n"); 7979 1.1 fvdl } 7980 1.1 fvdl #endif 7981 1.1 fvdl scb->sg_count = 0; 7982 1.1 fvdl sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7983 1.1 fvdl ahd_get_sense_bufsize(ahd, scb), 7984 1.1 fvdl /*last*/TRUE); 7985 1.29 thorpej memset(sc, 0, sizeof(*sc)); 7986 1.29 thorpej sc->opcode = SCSI_REQUEST_SENSE; 7987 1.1 fvdl sc->length = ahd_get_sense_bufsize(ahd, scb); 7988 1.1 fvdl 7989 1.1 fvdl /* 7990 1.1 fvdl * We can't allow the target to disconnect. 7991 1.1 fvdl * This will be an untagged transaction and 7992 1.1 fvdl * having the target disconnect will make this 7993 1.26 wiz * transaction indistinguishable from outstanding 7994 1.1 fvdl * tagged transactions. 7995 1.1 fvdl */ 7996 1.1 fvdl hscb->control = 0; 7997 1.1 fvdl 7998 1.1 fvdl /* 7999 1.1 fvdl * This request sense could be because the 8000 1.1 fvdl * the device lost power or in some other 8001 1.1 fvdl * way has lost our transfer negotiations. 8002 1.1 fvdl * Renegotiate if appropriate. Unit attention 8003 1.1 fvdl * errors will be reported before any data 8004 1.1 fvdl * phases occur. 8005 1.1 fvdl */ 8006 1.1 fvdl if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 8007 1.1 fvdl ahd_update_neg_request(ahd, &devinfo, 8008 1.1 fvdl tstate, targ_info, 8009 1.1 fvdl AHD_NEG_IF_NON_ASYNC); 8010 1.1 fvdl } 8011 1.1 fvdl if (tstate->auto_negotiate & devinfo.target_mask) { 8012 1.1 fvdl hscb->control |= MK_MESSAGE; 8013 1.1 fvdl scb->flags &= 8014 1.1 fvdl ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 8015 1.1 fvdl scb->flags |= SCB_AUTO_NEGOTIATE; 8016 1.1 fvdl } 8017 1.1 fvdl hscb->cdb_len = sizeof(*sc); 8018 1.1 fvdl ahd_setup_data_scb(ahd, scb); 8019 1.1 fvdl scb->flags |= SCB_SENSE; 8020 1.1 fvdl ahd_queue_scb(ahd, scb); 8021 1.1 fvdl /* 8022 1.1 fvdl * Ensure we have enough time to actually 8023 1.1 fvdl * retrieve the sense. 8024 1.1 fvdl */ 8025 1.1 fvdl ahd_scb_timer_reset(scb, 5 * 1000000); 8026 1.1 fvdl break; 8027 1.30 perry } 8028 1.1 fvdl case SCSI_STATUS_OK: 8029 1.2 fvdl printf("%s: Interrupted for status of 0? (SCB 0x%x)\n", 8030 1.1 fvdl ahd_name(ahd), SCB_GET_TAG(scb)); 8031 1.1 fvdl /* FALLTHROUGH */ 8032 1.1 fvdl default: 8033 1.1 fvdl ahd_done(ahd, scb); 8034 1.1 fvdl break; 8035 1.1 fvdl } 8036 1.1 fvdl } 8037 1.1 fvdl 8038 1.1 fvdl /* 8039 1.1 fvdl * Calculate the residual for a just completed SCB. 8040 1.1 fvdl */ 8041 1.1 fvdl void 8042 1.1 fvdl ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 8043 1.1 fvdl { 8044 1.1 fvdl struct hardware_scb *hscb; 8045 1.1 fvdl struct initiator_status *spkt; 8046 1.1 fvdl uint32_t sgptr; 8047 1.1 fvdl uint32_t resid_sgptr; 8048 1.1 fvdl uint32_t resid; 8049 1.1 fvdl 8050 1.1 fvdl /* 8051 1.1 fvdl * 5 cases. 8052 1.1 fvdl * 1) No residual. 8053 1.1 fvdl * SG_STATUS_VALID clear in sgptr. 8054 1.1 fvdl * 2) Transferless command 8055 1.1 fvdl * 3) Never performed any transfers. 8056 1.1 fvdl * sgptr has SG_FULL_RESID set. 8057 1.1 fvdl * 4) No residual but target did not 8058 1.1 fvdl * save data pointers after the 8059 1.1 fvdl * last transfer, so sgptr was 8060 1.1 fvdl * never updated. 8061 1.1 fvdl * 5) We have a partial residual. 8062 1.1 fvdl * Use residual_sgptr to determine 8063 1.1 fvdl * where we are. 8064 1.1 fvdl */ 8065 1.1 fvdl 8066 1.1 fvdl hscb = scb->hscb; 8067 1.1 fvdl sgptr = ahd_le32toh(hscb->sgptr); 8068 1.1 fvdl if ((sgptr & SG_STATUS_VALID) == 0) 8069 1.1 fvdl /* Case 1 */ 8070 1.1 fvdl return; 8071 1.1 fvdl sgptr &= ~SG_STATUS_VALID; 8072 1.1 fvdl 8073 1.1 fvdl if ((sgptr & SG_LIST_NULL) != 0) 8074 1.1 fvdl /* Case 2 */ 8075 1.1 fvdl return; 8076 1.1 fvdl 8077 1.1 fvdl /* 8078 1.1 fvdl * Residual fields are the same in both 8079 1.1 fvdl * target and initiator status packets, 8080 1.1 fvdl * so we can always use the initiator fields 8081 1.1 fvdl * regardless of the role for this SCB. 8082 1.1 fvdl */ 8083 1.1 fvdl spkt = &hscb->shared_data.istatus; 8084 1.1 fvdl resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 8085 1.1 fvdl if ((sgptr & SG_FULL_RESID) != 0) { 8086 1.1 fvdl /* Case 3 */ 8087 1.1 fvdl resid = ahd_get_transfer_length(scb); 8088 1.1 fvdl } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 8089 1.1 fvdl /* Case 4 */ 8090 1.1 fvdl return; 8091 1.1 fvdl } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 8092 1.1 fvdl ahd_print_path(ahd, scb); 8093 1.1 fvdl printf("data overrun detected Tag == 0x%x.\n", 8094 1.1 fvdl SCB_GET_TAG(scb)); 8095 1.1 fvdl ahd_freeze_devq(ahd, scb); 8096 1.1 fvdl ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 8097 1.1 fvdl ahd_freeze_scb(scb); 8098 1.1 fvdl return; 8099 1.1 fvdl } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 8100 1.1 fvdl panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 8101 1.1 fvdl /* NOTREACHED */ 8102 1.1 fvdl } else { 8103 1.1 fvdl struct ahd_dma_seg *sg; 8104 1.1 fvdl 8105 1.1 fvdl /* 8106 1.1 fvdl * Remainder of the SG where the transfer 8107 1.30 perry * stopped. 8108 1.1 fvdl */ 8109 1.1 fvdl resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 8110 1.1 fvdl sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 8111 1.1 fvdl 8112 1.1 fvdl /* The residual sg_ptr always points to the next sg */ 8113 1.1 fvdl sg--; 8114 1.1 fvdl 8115 1.1 fvdl /* 8116 1.1 fvdl * Add up the contents of all residual 8117 1.1 fvdl * SG segments that are after the SG where 8118 1.1 fvdl * the transfer stopped. 8119 1.1 fvdl */ 8120 1.1 fvdl while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 8121 1.1 fvdl sg++; 8122 1.1 fvdl resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 8123 1.1 fvdl } 8124 1.1 fvdl } 8125 1.1 fvdl 8126 1.1 fvdl if ((scb->flags & SCB_SENSE) == 0) 8127 1.43 tsutsui ahd_set_residual(scb, resid); 8128 1.1 fvdl /*else 8129 1.1 fvdl ahd_set_sense_residual(scb, resid);*/ 8130 1.1 fvdl 8131 1.1 fvdl #ifdef AHD_DEBUG 8132 1.1 fvdl if ((ahd_debug & AHD_SHOW_MISC) != 0) { 8133 1.1 fvdl ahd_print_path(ahd, scb); 8134 1.1 fvdl printf("Handled %sResidual of %d bytes\n", 8135 1.1 fvdl (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 8136 1.1 fvdl } 8137 1.1 fvdl #endif 8138 1.1 fvdl } 8139 1.1 fvdl 8140 1.1 fvdl /******************************* Target Mode **********************************/ 8141 1.1 fvdl #ifdef AHD_TARGET_MODE 8142 1.1 fvdl /* 8143 1.1 fvdl * Add a target mode event to this lun's queue 8144 1.1 fvdl */ 8145 1.1 fvdl static void 8146 1.1 fvdl ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8147 1.1 fvdl u_int initiator_id, u_int event_type, u_int event_arg) 8148 1.1 fvdl { 8149 1.1 fvdl struct ahd_tmode_event *event; 8150 1.1 fvdl int pending; 8151 1.1 fvdl 8152 1.1 fvdl xpt_freeze_devq(lstate->path, /*count*/1); 8153 1.1 fvdl if (lstate->event_w_idx >= lstate->event_r_idx) 8154 1.1 fvdl pending = lstate->event_w_idx - lstate->event_r_idx; 8155 1.1 fvdl else 8156 1.1 fvdl pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8157 1.1 fvdl - (lstate->event_r_idx - lstate->event_w_idx); 8158 1.1 fvdl 8159 1.1 fvdl if (event_type == EVENT_TYPE_BUS_RESET 8160 1.1 fvdl || event_type == MSG_BUS_DEV_RESET) { 8161 1.1 fvdl /* 8162 1.1 fvdl * Any earlier events are irrelevant, so reset our buffer. 8163 1.1 fvdl * This has the effect of allowing us to deal with reset 8164 1.1 fvdl * floods (an external device holding down the reset line) 8165 1.1 fvdl * without losing the event that is really interesting. 8166 1.1 fvdl */ 8167 1.1 fvdl lstate->event_r_idx = 0; 8168 1.1 fvdl lstate->event_w_idx = 0; 8169 1.1 fvdl xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8170 1.1 fvdl } 8171 1.1 fvdl 8172 1.1 fvdl if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8173 1.1 fvdl xpt_print_path(lstate->path); 8174 1.1 fvdl printf("immediate event %x:%x lost\n", 8175 1.1 fvdl lstate->event_buffer[lstate->event_r_idx].event_type, 8176 1.1 fvdl lstate->event_buffer[lstate->event_r_idx].event_arg); 8177 1.1 fvdl lstate->event_r_idx++; 8178 1.1 fvdl if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8179 1.1 fvdl lstate->event_r_idx = 0; 8180 1.1 fvdl xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8181 1.1 fvdl } 8182 1.1 fvdl 8183 1.1 fvdl event = &lstate->event_buffer[lstate->event_w_idx]; 8184 1.1 fvdl event->initiator_id = initiator_id; 8185 1.1 fvdl event->event_type = event_type; 8186 1.1 fvdl event->event_arg = event_arg; 8187 1.1 fvdl lstate->event_w_idx++; 8188 1.1 fvdl if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8189 1.1 fvdl lstate->event_w_idx = 0; 8190 1.1 fvdl } 8191 1.1 fvdl 8192 1.1 fvdl /* 8193 1.1 fvdl * Send any target mode events queued up waiting 8194 1.1 fvdl * for immediate notify resources. 8195 1.1 fvdl */ 8196 1.1 fvdl void 8197 1.1 fvdl ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8198 1.1 fvdl { 8199 1.1 fvdl struct ccb_hdr *ccbh; 8200 1.1 fvdl struct ccb_immed_notify *inot; 8201 1.1 fvdl 8202 1.1 fvdl while (lstate->event_r_idx != lstate->event_w_idx 8203 1.1 fvdl && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8204 1.1 fvdl struct ahd_tmode_event *event; 8205 1.1 fvdl 8206 1.1 fvdl event = &lstate->event_buffer[lstate->event_r_idx]; 8207 1.1 fvdl SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8208 1.1 fvdl inot = (struct ccb_immed_notify *)ccbh; 8209 1.1 fvdl switch (event->event_type) { 8210 1.1 fvdl case EVENT_TYPE_BUS_RESET: 8211 1.1 fvdl ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8212 1.1 fvdl break; 8213 1.1 fvdl default: 8214 1.1 fvdl ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8215 1.1 fvdl inot->message_args[0] = event->event_type; 8216 1.1 fvdl inot->message_args[1] = event->event_arg; 8217 1.1 fvdl break; 8218 1.1 fvdl } 8219 1.1 fvdl inot->initiator_id = event->initiator_id; 8220 1.1 fvdl inot->sense_len = 0; 8221 1.1 fvdl xpt_done((union ccb *)inot); 8222 1.1 fvdl lstate->event_r_idx++; 8223 1.1 fvdl if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8224 1.1 fvdl lstate->event_r_idx = 0; 8225 1.1 fvdl } 8226 1.1 fvdl } 8227 1.1 fvdl #endif 8228 1.1 fvdl 8229 1.1 fvdl /******************** Sequencer Program Patching/Download *********************/ 8230 1.1 fvdl 8231 1.1 fvdl #ifdef AHD_DUMP_SEQ 8232 1.1 fvdl void 8233 1.1 fvdl ahd_dumpseq(struct ahd_softc* ahd) 8234 1.1 fvdl { 8235 1.1 fvdl int i; 8236 1.1 fvdl int max_prog; 8237 1.1 fvdl 8238 1.1 fvdl max_prog = 2048; 8239 1.1 fvdl 8240 1.1 fvdl ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8241 1.1 fvdl ahd_outb(ahd, PRGMCNT, 0); 8242 1.1 fvdl ahd_outb(ahd, PRGMCNT+1, 0); 8243 1.1 fvdl for (i = 0; i < max_prog; i++) { 8244 1.1 fvdl uint8_t ins_bytes[4]; 8245 1.1 fvdl 8246 1.1 fvdl ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8247 1.1 fvdl printf("0x%08x\n", ins_bytes[0] << 24 8248 1.1 fvdl | ins_bytes[1] << 16 8249 1.1 fvdl | ins_bytes[2] << 8 8250 1.1 fvdl | ins_bytes[3]); 8251 1.1 fvdl } 8252 1.1 fvdl } 8253 1.1 fvdl #endif 8254 1.1 fvdl 8255 1.54 jdolecek static void __noinline 8256 1.1 fvdl ahd_loadseq(struct ahd_softc *ahd) 8257 1.1 fvdl { 8258 1.59 ryo struct cs cs_table[NUM_CRITICAL_SECTIONS]; 8259 1.59 ryo u_int begin_set[NUM_CRITICAL_SECTIONS]; 8260 1.59 ryo u_int end_set[NUM_CRITICAL_SECTIONS]; 8261 1.56 jdolecek const struct patch *cur_patch; 8262 1.1 fvdl u_int cs_count; 8263 1.1 fvdl u_int cur_cs; 8264 1.1 fvdl u_int i; 8265 1.1 fvdl int downloaded; 8266 1.1 fvdl u_int skip_addr; 8267 1.1 fvdl u_int sg_prefetch_cnt; 8268 1.1 fvdl u_int sg_prefetch_cnt_limit; 8269 1.1 fvdl u_int sg_prefetch_align; 8270 1.1 fvdl u_int sg_size; 8271 1.1 fvdl uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8272 1.1 fvdl 8273 1.1 fvdl if (bootverbose) 8274 1.1 fvdl printf("%s: Downloading Sequencer Program...", 8275 1.1 fvdl ahd_name(ahd)); 8276 1.1 fvdl 8277 1.1 fvdl #if DOWNLOAD_CONST_COUNT != 7 8278 1.1 fvdl #error "Download Const Mismatch" 8279 1.1 fvdl #endif 8280 1.1 fvdl /* 8281 1.1 fvdl * Start out with 0 critical sections 8282 1.1 fvdl * that apply to this firmware load. 8283 1.1 fvdl */ 8284 1.1 fvdl cs_count = 0; 8285 1.1 fvdl cur_cs = 0; 8286 1.1 fvdl memset(begin_set, 0, sizeof(begin_set)); 8287 1.1 fvdl memset(end_set, 0, sizeof(end_set)); 8288 1.1 fvdl 8289 1.1 fvdl /* 8290 1.1 fvdl * Setup downloadable constant table. 8291 1.30 perry * 8292 1.1 fvdl * The computation for the S/G prefetch variables is 8293 1.1 fvdl * a bit complicated. We would like to always fetch 8294 1.1 fvdl * in terms of cachelined sized increments. However, 8295 1.1 fvdl * if the cacheline is not an even multiple of the 8296 1.1 fvdl * SG element size or is larger than our SG RAM, using 8297 1.1 fvdl * just the cache size might leave us with only a portion 8298 1.1 fvdl * of an SG element at the tail of a prefetch. If the 8299 1.1 fvdl * cacheline is larger than our S/G prefetch buffer less 8300 1.1 fvdl * the size of an SG element, we may round down to a cacheline 8301 1.1 fvdl * that doesn't contain any or all of the S/G of interest 8302 1.1 fvdl * within the bounds of our S/G ram. Provide variables to 8303 1.1 fvdl * the sequencer that will allow it to handle these edge 8304 1.1 fvdl * cases. 8305 1.1 fvdl */ 8306 1.1 fvdl /* Start by aligning to the nearest cacheline. */ 8307 1.1 fvdl sg_prefetch_align = ahd->pci_cachesize; 8308 1.1 fvdl if (sg_prefetch_align == 0) 8309 1.1 fvdl sg_prefetch_align = 8; 8310 1.1 fvdl /* Round down to the nearest power of 2. */ 8311 1.1 fvdl while (powerof2(sg_prefetch_align) == 0) 8312 1.1 fvdl sg_prefetch_align--; 8313 1.1 fvdl /* 8314 1.1 fvdl * If the cacheline boundary is greater than half our prefetch RAM 8315 1.1 fvdl * we risk not being able to fetch even a single complete S/G 8316 1.1 fvdl * segment if we align to that boundary. 8317 1.1 fvdl */ 8318 1.1 fvdl if (sg_prefetch_align > CCSGADDR_MAX/2) 8319 1.1 fvdl sg_prefetch_align = CCSGADDR_MAX/2; 8320 1.1 fvdl /* Start by fetching a single cacheline. */ 8321 1.1 fvdl sg_prefetch_cnt = sg_prefetch_align; 8322 1.1 fvdl /* 8323 1.1 fvdl * Increment the prefetch count by cachelines until 8324 1.1 fvdl * at least one S/G element will fit. 8325 1.1 fvdl */ 8326 1.1 fvdl sg_size = sizeof(struct ahd_dma_seg); 8327 1.1 fvdl if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8328 1.1 fvdl sg_size = sizeof(struct ahd_dma64_seg); 8329 1.1 fvdl while (sg_prefetch_cnt < sg_size) 8330 1.1 fvdl sg_prefetch_cnt += sg_prefetch_align; 8331 1.1 fvdl /* 8332 1.1 fvdl * If the cacheline is not an even multiple of 8333 1.1 fvdl * the S/G size, we may only get a partial S/G when 8334 1.1 fvdl * we align. Add a cacheline if this is the case. 8335 1.1 fvdl */ 8336 1.1 fvdl if ((sg_prefetch_align % sg_size) != 0 8337 1.1 fvdl && (sg_prefetch_cnt < CCSGADDR_MAX)) 8338 1.1 fvdl sg_prefetch_cnt += sg_prefetch_align; 8339 1.1 fvdl /* 8340 1.1 fvdl * Lastly, compute a value that the sequencer can use 8341 1.1 fvdl * to determine if the remainder of the CCSGRAM buffer 8342 1.1 fvdl * has a full S/G element in it. 8343 1.1 fvdl */ 8344 1.1 fvdl sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8345 1.1 fvdl download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8346 1.1 fvdl download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8347 1.1 fvdl download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8348 1.1 fvdl download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8349 1.1 fvdl download_consts[SG_SIZEOF] = sg_size; 8350 1.1 fvdl download_consts[PKT_OVERRUN_BUFOFFSET] = 8351 1.1 fvdl (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8352 1.1 fvdl download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8353 1.1 fvdl cur_patch = patches; 8354 1.1 fvdl downloaded = 0; 8355 1.1 fvdl skip_addr = 0; 8356 1.1 fvdl ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8357 1.1 fvdl ahd_outb(ahd, PRGMCNT, 0); 8358 1.1 fvdl ahd_outb(ahd, PRGMCNT+1, 0); 8359 1.1 fvdl 8360 1.1 fvdl for (i = 0; i < sizeof(seqprog)/4; i++) { 8361 1.1 fvdl if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8362 1.1 fvdl /* 8363 1.1 fvdl * Don't download this instruction as it 8364 1.1 fvdl * is in a patch that was removed. 8365 1.1 fvdl */ 8366 1.1 fvdl continue; 8367 1.1 fvdl } 8368 1.1 fvdl /* 8369 1.1 fvdl * Move through the CS table until we find a CS 8370 1.1 fvdl * that might apply to this instruction. 8371 1.1 fvdl */ 8372 1.1 fvdl for (; cur_cs < num_critical_sections; cur_cs++) { 8373 1.1 fvdl if (critical_sections[cur_cs].end <= i) { 8374 1.1 fvdl if (begin_set[cs_count] == TRUE 8375 1.1 fvdl && end_set[cs_count] == FALSE) { 8376 1.1 fvdl cs_table[cs_count].end = downloaded; 8377 1.43 tsutsui end_set[cs_count] = TRUE; 8378 1.1 fvdl cs_count++; 8379 1.43 tsutsui } 8380 1.1 fvdl continue; 8381 1.1 fvdl } 8382 1.1 fvdl if (critical_sections[cur_cs].begin <= i 8383 1.1 fvdl && begin_set[cs_count] == FALSE) { 8384 1.1 fvdl cs_table[cs_count].begin = downloaded; 8385 1.1 fvdl begin_set[cs_count] = TRUE; 8386 1.1 fvdl } 8387 1.1 fvdl break; 8388 1.1 fvdl } 8389 1.1 fvdl ahd_download_instr(ahd, i, download_consts); 8390 1.1 fvdl downloaded++; 8391 1.1 fvdl } 8392 1.1 fvdl 8393 1.1 fvdl ahd->num_critical_sections = cs_count; 8394 1.1 fvdl if (cs_count != 0) { 8395 1.1 fvdl 8396 1.1 fvdl cs_count *= sizeof(struct cs); 8397 1.1 fvdl ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8398 1.1 fvdl if (ahd->critical_sections == NULL) 8399 1.1 fvdl panic("ahd_loadseq: Could not malloc"); 8400 1.1 fvdl memcpy(ahd->critical_sections, cs_table, cs_count); 8401 1.1 fvdl } 8402 1.1 fvdl ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8403 1.1 fvdl 8404 1.1 fvdl if (bootverbose) { 8405 1.1 fvdl printf(" %d instructions downloaded\n", downloaded); 8406 1.1 fvdl printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8407 1.1 fvdl ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8408 1.1 fvdl } 8409 1.1 fvdl } 8410 1.1 fvdl 8411 1.1 fvdl static int 8412 1.56 jdolecek ahd_check_patch(struct ahd_softc *ahd, const struct patch **start_patch, 8413 1.1 fvdl u_int start_instr, u_int *skip_addr) 8414 1.1 fvdl { 8415 1.56 jdolecek const struct patch *cur_patch; 8416 1.56 jdolecek const struct patch *last_patch; 8417 1.56 jdolecek u_int num_patches; 8418 1.1 fvdl 8419 1.1 fvdl num_patches = sizeof(patches)/sizeof(struct patch); 8420 1.1 fvdl last_patch = &patches[num_patches]; 8421 1.1 fvdl cur_patch = *start_patch; 8422 1.1 fvdl 8423 1.1 fvdl while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8424 1.1 fvdl 8425 1.1 fvdl if (cur_patch->patch_func(ahd) == 0) { 8426 1.1 fvdl 8427 1.1 fvdl /* Start rejecting code */ 8428 1.1 fvdl *skip_addr = start_instr + cur_patch->skip_instr; 8429 1.1 fvdl cur_patch += cur_patch->skip_patch; 8430 1.1 fvdl } else { 8431 1.1 fvdl /* Accepted this patch. Advance to the next 8432 1.57 andvar * one and wait for our instruction pointer to 8433 1.1 fvdl * hit this point. 8434 1.1 fvdl */ 8435 1.1 fvdl cur_patch++; 8436 1.1 fvdl } 8437 1.1 fvdl } 8438 1.1 fvdl 8439 1.1 fvdl *start_patch = cur_patch; 8440 1.1 fvdl if (start_instr < *skip_addr) 8441 1.1 fvdl /* Still skipping */ 8442 1.1 fvdl return (0); 8443 1.1 fvdl 8444 1.1 fvdl return (1); 8445 1.1 fvdl } 8446 1.1 fvdl 8447 1.1 fvdl static u_int 8448 1.1 fvdl ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8449 1.1 fvdl { 8450 1.56 jdolecek const struct patch *cur_patch; 8451 1.1 fvdl int address_offset; 8452 1.1 fvdl u_int skip_addr; 8453 1.1 fvdl u_int i; 8454 1.1 fvdl 8455 1.1 fvdl address_offset = 0; 8456 1.1 fvdl cur_patch = patches; 8457 1.1 fvdl skip_addr = 0; 8458 1.1 fvdl 8459 1.1 fvdl for (i = 0; i < address;) { 8460 1.1 fvdl 8461 1.1 fvdl ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8462 1.1 fvdl 8463 1.1 fvdl if (skip_addr > i) { 8464 1.1 fvdl int end_addr; 8465 1.1 fvdl 8466 1.1 fvdl end_addr = MIN(address, skip_addr); 8467 1.1 fvdl address_offset += end_addr - i; 8468 1.1 fvdl i = skip_addr; 8469 1.1 fvdl } else { 8470 1.1 fvdl i++; 8471 1.1 fvdl } 8472 1.1 fvdl } 8473 1.1 fvdl return (address - address_offset); 8474 1.1 fvdl } 8475 1.1 fvdl 8476 1.1 fvdl static void 8477 1.1 fvdl ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8478 1.1 fvdl { 8479 1.1 fvdl union ins_formats instr; 8480 1.1 fvdl struct ins_format1 *fmt1_ins; 8481 1.1 fvdl struct ins_format3 *fmt3_ins; 8482 1.1 fvdl u_int opcode; 8483 1.1 fvdl 8484 1.1 fvdl /* 8485 1.1 fvdl * The firmware is always compiled into a little endian format. 8486 1.1 fvdl */ 8487 1.56 jdolecek instr.integer = ahd_le32toh(*(const uint32_t*)&seqprog[instrptr * 4]); 8488 1.1 fvdl 8489 1.1 fvdl fmt1_ins = &instr.format1; 8490 1.1 fvdl fmt3_ins = NULL; 8491 1.1 fvdl 8492 1.1 fvdl /* Pull the opcode */ 8493 1.1 fvdl opcode = instr.format1.opcode; 8494 1.1 fvdl switch (opcode) { 8495 1.1 fvdl case AIC_OP_JMP: 8496 1.1 fvdl case AIC_OP_JC: 8497 1.1 fvdl case AIC_OP_JNC: 8498 1.1 fvdl case AIC_OP_CALL: 8499 1.1 fvdl case AIC_OP_JNE: 8500 1.1 fvdl case AIC_OP_JNZ: 8501 1.1 fvdl case AIC_OP_JE: 8502 1.1 fvdl case AIC_OP_JZ: 8503 1.1 fvdl { 8504 1.1 fvdl fmt3_ins = &instr.format3; 8505 1.1 fvdl fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8506 1.1 fvdl } 8507 1.51 mrg /* FALLTHROUGH */ 8508 1.1 fvdl case AIC_OP_OR: 8509 1.1 fvdl case AIC_OP_AND: 8510 1.1 fvdl case AIC_OP_XOR: 8511 1.1 fvdl case AIC_OP_ADD: 8512 1.1 fvdl case AIC_OP_ADC: 8513 1.1 fvdl case AIC_OP_BMOV: 8514 1.1 fvdl if (fmt1_ins->parity != 0) { 8515 1.1 fvdl fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8516 1.1 fvdl } 8517 1.1 fvdl fmt1_ins->parity = 0; 8518 1.1 fvdl /* FALLTHROUGH */ 8519 1.1 fvdl case AIC_OP_ROL: 8520 1.1 fvdl { 8521 1.1 fvdl int i, count; 8522 1.1 fvdl 8523 1.1 fvdl /* Calculate odd parity for the instruction */ 8524 1.1 fvdl for (i = 0, count = 0; i < 31; i++) { 8525 1.1 fvdl uint32_t mask; 8526 1.1 fvdl 8527 1.1 fvdl mask = 0x01 << i; 8528 1.1 fvdl if ((instr.integer & mask) != 0) 8529 1.1 fvdl count++; 8530 1.1 fvdl } 8531 1.1 fvdl if ((count & 0x01) == 0) 8532 1.1 fvdl instr.format1.parity = 1; 8533 1.1 fvdl 8534 1.27 wiz /* The sequencer is a little endian CPU */ 8535 1.1 fvdl instr.integer = ahd_htole32(instr.integer); 8536 1.1 fvdl ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8537 1.1 fvdl break; 8538 1.1 fvdl } 8539 1.1 fvdl default: 8540 1.1 fvdl panic("Unknown opcode encountered in seq program"); 8541 1.1 fvdl break; 8542 1.1 fvdl } 8543 1.1 fvdl } 8544 1.1 fvdl 8545 1.1 fvdl static int 8546 1.1 fvdl ahd_probe_stack_size(struct ahd_softc *ahd) 8547 1.1 fvdl { 8548 1.1 fvdl int last_probe; 8549 1.1 fvdl 8550 1.1 fvdl last_probe = 0; 8551 1.1 fvdl while (1) { 8552 1.1 fvdl int i; 8553 1.1 fvdl 8554 1.1 fvdl /* 8555 1.1 fvdl * We avoid using 0 as a pattern to avoid 8556 1.1 fvdl * confusion if the stack implementation 8557 1.1 fvdl * "back-fills" with zeros when "poping' 8558 1.1 fvdl * entries. 8559 1.1 fvdl */ 8560 1.1 fvdl for (i = 1; i <= last_probe+1; i++) { 8561 1.43 tsutsui ahd_outb(ahd, STACK, i & 0xFF); 8562 1.43 tsutsui ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8563 1.1 fvdl } 8564 1.1 fvdl 8565 1.1 fvdl /* Verify */ 8566 1.1 fvdl for (i = last_probe+1; i > 0; i--) { 8567 1.1 fvdl u_int stack_entry; 8568 1.1 fvdl 8569 1.1 fvdl stack_entry = ahd_inb(ahd, STACK) 8570 1.1 fvdl |(ahd_inb(ahd, STACK) << 8); 8571 1.1 fvdl if (stack_entry != i) 8572 1.1 fvdl goto sized; 8573 1.1 fvdl } 8574 1.1 fvdl last_probe++; 8575 1.1 fvdl } 8576 1.1 fvdl sized: 8577 1.1 fvdl return (last_probe); 8578 1.1 fvdl } 8579 1.1 fvdl 8580 1.1 fvdl void 8581 1.12 thorpej ahd_dump_all_cards_state(void) 8582 1.1 fvdl { 8583 1.1 fvdl struct ahd_softc *list_ahd; 8584 1.1 fvdl 8585 1.1 fvdl TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8586 1.1 fvdl ahd_dump_card_state(list_ahd); 8587 1.1 fvdl } 8588 1.1 fvdl } 8589 1.1 fvdl 8590 1.1 fvdl int 8591 1.1 fvdl ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8592 1.36 christos const char *name, u_int address, u_int value, 8593 1.1 fvdl u_int *cur_column, u_int wrap_point) 8594 1.1 fvdl { 8595 1.47 christos size_t printed; 8596 1.1 fvdl u_int printed_mask; 8597 1.1 fvdl char line[1024]; 8598 1.1 fvdl 8599 1.1 fvdl line[0] = 0; 8600 1.1 fvdl 8601 1.1 fvdl if (cur_column != NULL && *cur_column >= wrap_point) { 8602 1.1 fvdl printf("\n"); 8603 1.1 fvdl *cur_column = 0; 8604 1.1 fvdl } 8605 1.1 fvdl printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8606 1.47 christos printed = sizeof(line); 8607 1.1 fvdl if (table == NULL) { 8608 1.48 christos if (printed < sizeof(line)) 8609 1.48 christos printed += snprintf(&line[printed], 8610 1.49 christos (sizeof line) - printed, " "); 8611 1.1 fvdl printf("%s", line); 8612 1.1 fvdl if (cur_column != NULL) 8613 1.1 fvdl *cur_column += printed; 8614 1.1 fvdl return (printed); 8615 1.1 fvdl } 8616 1.1 fvdl printed_mask = 0; 8617 1.1 fvdl while (printed_mask != 0xFF) { 8618 1.1 fvdl int entry; 8619 1.1 fvdl 8620 1.1 fvdl for (entry = 0; entry < num_entries; entry++) { 8621 1.1 fvdl if (((value & table[entry].mask) 8622 1.1 fvdl != table[entry].value) 8623 1.1 fvdl || ((printed_mask & table[entry].mask) 8624 1.1 fvdl == table[entry].mask)) 8625 1.1 fvdl continue; 8626 1.48 christos if (printed < sizeof(line)) 8627 1.48 christos printed += snprintf(&line[printed], 8628 1.48 christos (sizeof line) - printed, "%s%s", 8629 1.48 christos printed_mask == 0 ? ":(" : "|", 8630 1.48 christos table[entry].name); 8631 1.1 fvdl printed_mask |= table[entry].mask; 8632 1.30 perry 8633 1.1 fvdl break; 8634 1.1 fvdl } 8635 1.1 fvdl if (entry >= num_entries) 8636 1.1 fvdl break; 8637 1.1 fvdl } 8638 1.48 christos if (printed < sizeof(line)) { 8639 1.48 christos if (printed_mask != 0) 8640 1.48 christos printed += snprintf(&line[printed], 8641 1.48 christos (sizeof line) - printed, ") "); 8642 1.48 christos else 8643 1.48 christos printed += snprintf(&line[printed], 8644 1.48 christos (sizeof line) - printed, " "); 8645 1.48 christos } 8646 1.1 fvdl if (cur_column != NULL) 8647 1.1 fvdl *cur_column += printed; 8648 1.1 fvdl printf("%s", line); 8649 1.1 fvdl 8650 1.1 fvdl return (printed); 8651 1.1 fvdl } 8652 1.1 fvdl 8653 1.1 fvdl void 8654 1.1 fvdl ahd_dump_card_state(struct ahd_softc *ahd) 8655 1.1 fvdl { 8656 1.1 fvdl struct scb *scb; 8657 1.1 fvdl ahd_mode_state saved_modes; 8658 1.1 fvdl u_int dffstat; 8659 1.1 fvdl int paused; 8660 1.1 fvdl u_int scb_index; 8661 1.1 fvdl u_int saved_scb_index; 8662 1.1 fvdl u_int cur_col; 8663 1.1 fvdl int i; 8664 1.1 fvdl 8665 1.1 fvdl if (ahd_is_paused(ahd)) { 8666 1.1 fvdl paused = 1; 8667 1.1 fvdl } else { 8668 1.1 fvdl paused = 0; 8669 1.1 fvdl ahd_pause(ahd); 8670 1.1 fvdl } 8671 1.1 fvdl saved_modes = ahd_save_modes(ahd); 8672 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8673 1.1 fvdl printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8674 1.1 fvdl "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8675 1.30 perry ahd_name(ahd), 8676 1.1 fvdl ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8677 1.1 fvdl ahd_build_mode_state(ahd, ahd->saved_src_mode, 8678 1.1 fvdl ahd->saved_dst_mode)); 8679 1.1 fvdl if (paused) 8680 1.1 fvdl printf("Card was paused\n"); 8681 1.20 thorpej 8682 1.20 thorpej if (ahd_check_cmdcmpltqueues(ahd)) 8683 1.20 thorpej printf("Completions are pending\n"); 8684 1.1 fvdl /* 8685 1.1 fvdl * Mode independent registers. 8686 1.1 fvdl */ 8687 1.1 fvdl cur_col = 0; 8688 1.1 fvdl ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8689 1.1 fvdl ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8690 1.1 fvdl ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8691 1.1 fvdl ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8692 1.1 fvdl ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8693 1.1 fvdl ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8694 1.1 fvdl ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8695 1.1 fvdl ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8696 1.1 fvdl ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8697 1.1 fvdl ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8698 1.1 fvdl ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8699 1.1 fvdl ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8700 1.1 fvdl ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8701 1.1 fvdl ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8702 1.1 fvdl ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8703 1.1 fvdl ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8704 1.1 fvdl ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8705 1.1 fvdl ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8706 1.1 fvdl ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8707 1.1 fvdl ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8708 1.1 fvdl ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8709 1.1 fvdl ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8710 1.1 fvdl ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8711 1.1 fvdl ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8712 1.1 fvdl ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8713 1.1 fvdl ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8714 1.1 fvdl ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8715 1.1 fvdl printf("\n"); 8716 1.1 fvdl printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8717 1.1 fvdl "CURRSCB 0x%x NEXTSCB 0x%x\n", 8718 1.1 fvdl ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8719 1.1 fvdl ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8720 1.1 fvdl ahd_inw(ahd, NEXTSCB)); 8721 1.1 fvdl cur_col = 0; 8722 1.1 fvdl /* QINFIFO */ 8723 1.1 fvdl ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8724 1.1 fvdl CAM_LUN_WILDCARD, SCB_LIST_NULL, 8725 1.1 fvdl ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8726 1.1 fvdl saved_scb_index = ahd_get_scbptr(ahd); 8727 1.1 fvdl printf("Pending list:"); 8728 1.1 fvdl i = 0; 8729 1.1 fvdl LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8730 1.1 fvdl if (i++ > AHD_SCB_MAX) 8731 1.1 fvdl break; 8732 1.9 thorpej /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8733 1.21 thorpej ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 8734 1.1 fvdl ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8735 1.21 thorpej ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 8736 1.21 thorpej &cur_col, 60); 8737 1.21 thorpej ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 8738 1.21 thorpej &cur_col, 60); 8739 1.1 fvdl } 8740 1.1 fvdl printf("\nTotal %d\n", i); 8741 1.1 fvdl 8742 1.1 fvdl printf("Kernel Free SCB list: "); 8743 1.1 fvdl i = 0; 8744 1.1 fvdl TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8745 1.1 fvdl struct scb *list_scb; 8746 1.1 fvdl 8747 1.1 fvdl list_scb = scb; 8748 1.1 fvdl do { 8749 1.1 fvdl printf("%d ", SCB_GET_TAG(list_scb)); 8750 1.1 fvdl list_scb = LIST_NEXT(list_scb, collision_links); 8751 1.1 fvdl } while (list_scb && i++ < AHD_SCB_MAX); 8752 1.1 fvdl } 8753 1.1 fvdl 8754 1.1 fvdl LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8755 1.1 fvdl if (i++ > AHD_SCB_MAX) 8756 1.1 fvdl break; 8757 1.1 fvdl printf("%d ", SCB_GET_TAG(scb)); 8758 1.1 fvdl } 8759 1.1 fvdl printf("\n"); 8760 1.1 fvdl 8761 1.1 fvdl printf("Sequencer Complete DMA-inprog list: "); 8762 1.1 fvdl scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8763 1.1 fvdl i = 0; 8764 1.1 fvdl while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8765 1.1 fvdl ahd_set_scbptr(ahd, scb_index); 8766 1.1 fvdl printf("%d ", scb_index); 8767 1.21 thorpej scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8768 1.1 fvdl } 8769 1.1 fvdl printf("\n"); 8770 1.1 fvdl 8771 1.1 fvdl printf("Sequencer Complete list: "); 8772 1.1 fvdl scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8773 1.1 fvdl i = 0; 8774 1.1 fvdl while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8775 1.1 fvdl ahd_set_scbptr(ahd, scb_index); 8776 1.1 fvdl printf("%d ", scb_index); 8777 1.21 thorpej scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8778 1.1 fvdl } 8779 1.1 fvdl printf("\n"); 8780 1.1 fvdl 8781 1.30 perry 8782 1.1 fvdl printf("Sequencer DMA-Up and Complete list: "); 8783 1.1 fvdl scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8784 1.1 fvdl i = 0; 8785 1.1 fvdl while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8786 1.1 fvdl ahd_set_scbptr(ahd, scb_index); 8787 1.1 fvdl printf("%d ", scb_index); 8788 1.21 thorpej scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8789 1.1 fvdl } 8790 1.1 fvdl printf("\n"); 8791 1.1 fvdl ahd_set_scbptr(ahd, saved_scb_index); 8792 1.1 fvdl dffstat = ahd_inb(ahd, DFFSTAT); 8793 1.1 fvdl for (i = 0; i < 2; i++) { 8794 1.1 fvdl #ifdef AHD_DEBUG 8795 1.1 fvdl struct scb *fifo_scb; 8796 1.1 fvdl #endif 8797 1.1 fvdl u_int fifo_scbptr; 8798 1.1 fvdl 8799 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8800 1.1 fvdl fifo_scbptr = ahd_get_scbptr(ahd); 8801 1.9 thorpej printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8802 1.1 fvdl ahd_name(ahd), i, 8803 1.1 fvdl (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8804 1.9 thorpej ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 8805 1.1 fvdl cur_col = 0; 8806 1.1 fvdl ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8807 1.1 fvdl ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8808 1.1 fvdl ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8809 1.1 fvdl ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8810 1.1 fvdl ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8811 1.1 fvdl &cur_col, 50); 8812 1.1 fvdl ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8813 1.1 fvdl ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8814 1.1 fvdl ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8815 1.1 fvdl ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8816 1.1 fvdl if (cur_col > 50) { 8817 1.1 fvdl printf("\n"); 8818 1.1 fvdl cur_col = 0; 8819 1.1 fvdl } 8820 1.1 fvdl printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8821 1.1 fvdl ahd_inl(ahd, SHADDR+4), 8822 1.1 fvdl ahd_inl(ahd, SHADDR), 8823 1.1 fvdl (ahd_inb(ahd, SHCNT) 8824 1.1 fvdl | (ahd_inb(ahd, SHCNT + 1) << 8) 8825 1.1 fvdl | (ahd_inb(ahd, SHCNT + 2) << 16))); 8826 1.1 fvdl printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8827 1.1 fvdl ahd_inl(ahd, HADDR+4), 8828 1.1 fvdl ahd_inl(ahd, HADDR), 8829 1.1 fvdl (ahd_inb(ahd, HCNT) 8830 1.1 fvdl | (ahd_inb(ahd, HCNT + 1) << 8) 8831 1.1 fvdl | (ahd_inb(ahd, HCNT + 2) << 16))); 8832 1.1 fvdl ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8833 1.1 fvdl #ifdef AHD_DEBUG 8834 1.1 fvdl if ((ahd_debug & AHD_SHOW_SG) != 0) { 8835 1.1 fvdl fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8836 1.1 fvdl if (fifo_scb != NULL) 8837 1.1 fvdl ahd_dump_sglist(fifo_scb); 8838 1.1 fvdl } 8839 1.1 fvdl #endif 8840 1.1 fvdl } 8841 1.1 fvdl printf("\nLQIN: "); 8842 1.1 fvdl for (i = 0; i < 20; i++) 8843 1.1 fvdl printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8844 1.1 fvdl printf("\n"); 8845 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8846 1.1 fvdl printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8847 1.1 fvdl ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8848 1.1 fvdl ahd_inb(ahd, OPTIONMODE)); 8849 1.1 fvdl printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8850 1.1 fvdl ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8851 1.1 fvdl ahd_inb(ahd, MAXCMDCNT)); 8852 1.1 fvdl ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8853 1.1 fvdl printf("\n"); 8854 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8855 1.1 fvdl cur_col = 0; 8856 1.1 fvdl ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8857 1.1 fvdl printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8858 1.1 fvdl ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8859 1.1 fvdl ahd_inw(ahd, DINDEX)); 8860 1.1 fvdl printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8861 1.21 thorpej ahd_name(ahd), ahd_get_scbptr(ahd), 8862 1.21 thorpej ahd_inw_scbram(ahd, SCB_NEXT), 8863 1.21 thorpej ahd_inw_scbram(ahd, SCB_NEXT2)); 8864 1.1 fvdl printf("CDB %x %x %x %x %x %x\n", 8865 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE), 8866 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 8867 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 8868 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 8869 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 8870 1.21 thorpej ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 8871 1.1 fvdl printf("STACK:"); 8872 1.1 fvdl for (i = 0; i < ahd->stack_size; i++) { 8873 1.1 fvdl ahd->saved_stack[i] = 8874 1.1 fvdl ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8875 1.1 fvdl printf(" 0x%x", ahd->saved_stack[i]); 8876 1.1 fvdl } 8877 1.1 fvdl for (i = ahd->stack_size-1; i >= 0; i--) { 8878 1.1 fvdl ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8879 1.1 fvdl ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8880 1.1 fvdl } 8881 1.1 fvdl printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8882 1.1 fvdl ahd_platform_dump_card_state(ahd); 8883 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 8884 1.1 fvdl if (paused == 0) 8885 1.1 fvdl ahd_unpause(ahd); 8886 1.1 fvdl } 8887 1.1 fvdl 8888 1.1 fvdl void 8889 1.1 fvdl ahd_dump_scbs(struct ahd_softc *ahd) 8890 1.1 fvdl { 8891 1.1 fvdl ahd_mode_state saved_modes; 8892 1.1 fvdl u_int saved_scb_index; 8893 1.1 fvdl int i; 8894 1.1 fvdl 8895 1.1 fvdl saved_modes = ahd_save_modes(ahd); 8896 1.1 fvdl ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8897 1.1 fvdl saved_scb_index = ahd_get_scbptr(ahd); 8898 1.1 fvdl for (i = 0; i < AHD_SCB_MAX; i++) { 8899 1.1 fvdl ahd_set_scbptr(ahd, i); 8900 1.1 fvdl printf("%3d", i); 8901 1.1 fvdl printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8902 1.21 thorpej ahd_inb_scbram(ahd, SCB_CONTROL), 8903 1.21 thorpej ahd_inb_scbram(ahd, SCB_SCSIID), 8904 1.21 thorpej ahd_inw_scbram(ahd, SCB_NEXT), 8905 1.21 thorpej ahd_inw_scbram(ahd, SCB_NEXT2), 8906 1.21 thorpej ahd_inl_scbram(ahd, SCB_SGPTR), 8907 1.21 thorpej ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 8908 1.1 fvdl } 8909 1.1 fvdl printf("\n"); 8910 1.1 fvdl ahd_set_scbptr(ahd, saved_scb_index); 8911 1.1 fvdl ahd_restore_modes(ahd, saved_modes); 8912 1.1 fvdl } 8913 1.1 fvdl 8914 1.1 fvdl /**************************** Flexport Logic **********************************/ 8915 1.1 fvdl /* 8916 1.1 fvdl * Read count 16bit words from 16bit word address start_addr from the 8917 1.31 christos * SEEPROM attached to the controller, into tbuf, using the controller's 8918 1.9 thorpej * SEEPROM reading state machine. Optionally treat the data as a byte 8919 1.9 thorpej * stream in terms of byte order. 8920 1.1 fvdl */ 8921 1.1 fvdl int 8922 1.31 christos ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, 8923 1.9 thorpej u_int start_addr, u_int count, int bytestream) 8924 1.1 fvdl { 8925 1.1 fvdl u_int cur_addr; 8926 1.1 fvdl u_int end_addr; 8927 1.1 fvdl int error; 8928 1.1 fvdl 8929 1.1 fvdl /* 8930 1.1 fvdl * If we never make it through the loop even once, 8931 1.1 fvdl * we were passed invalid arguments. 8932 1.1 fvdl */ 8933 1.1 fvdl error = EINVAL; 8934 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8935 1.1 fvdl end_addr = start_addr + count; 8936 1.1 fvdl for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8937 1.9 thorpej 8938 1.1 fvdl ahd_outb(ahd, SEEADR, cur_addr); 8939 1.1 fvdl ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8940 1.30 perry 8941 1.1 fvdl error = ahd_wait_seeprom(ahd); 8942 1.1 fvdl if (error) { 8943 1.44 tsutsui printf("%s: ahd_wait_seeprom timed out\n", 8944 1.44 tsutsui ahd_name(ahd)); 8945 1.1 fvdl break; 8946 1.1 fvdl } 8947 1.9 thorpej if (bytestream != 0) { 8948 1.9 thorpej uint8_t *bytestream_ptr; 8949 1.9 thorpej 8950 1.31 christos bytestream_ptr = (uint8_t *)tbuf; 8951 1.9 thorpej *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 8952 1.9 thorpej *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 8953 1.9 thorpej } else { 8954 1.9 thorpej /* 8955 1.9 thorpej * ahd_inw() already handles machine byte order. 8956 1.9 thorpej */ 8957 1.31 christos *tbuf = ahd_inw(ahd, SEEDAT); 8958 1.9 thorpej } 8959 1.31 christos tbuf++; 8960 1.1 fvdl } 8961 1.1 fvdl return (error); 8962 1.1 fvdl } 8963 1.1 fvdl 8964 1.1 fvdl /* 8965 1.70 andvar * Write count 16bit words from tbuf, into SEEPROM attached to the 8966 1.1 fvdl * controller starting at 16bit word address start_addr, using the 8967 1.1 fvdl * controller's SEEPROM writing state machine. 8968 1.1 fvdl */ 8969 1.1 fvdl int 8970 1.31 christos ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, 8971 1.1 fvdl u_int start_addr, u_int count) 8972 1.1 fvdl { 8973 1.1 fvdl u_int cur_addr; 8974 1.1 fvdl u_int end_addr; 8975 1.1 fvdl int error; 8976 1.1 fvdl int retval; 8977 1.1 fvdl 8978 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8979 1.1 fvdl error = ENOENT; 8980 1.1 fvdl 8981 1.1 fvdl /* Place the chip into write-enable mode */ 8982 1.1 fvdl ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8983 1.1 fvdl ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8984 1.1 fvdl error = ahd_wait_seeprom(ahd); 8985 1.1 fvdl if (error) 8986 1.1 fvdl return (error); 8987 1.1 fvdl 8988 1.1 fvdl /* 8989 1.70 andvar * Write the data. If we don't get through the loop at 8990 1.1 fvdl * least once, the arguments were invalid. 8991 1.1 fvdl */ 8992 1.1 fvdl retval = EINVAL; 8993 1.1 fvdl end_addr = start_addr + count; 8994 1.1 fvdl for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8995 1.31 christos ahd_outw(ahd, SEEDAT, *tbuf++); 8996 1.1 fvdl ahd_outb(ahd, SEEADR, cur_addr); 8997 1.1 fvdl ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8998 1.30 perry 8999 1.1 fvdl retval = ahd_wait_seeprom(ahd); 9000 1.1 fvdl if (retval) 9001 1.1 fvdl break; 9002 1.1 fvdl } 9003 1.1 fvdl 9004 1.1 fvdl /* 9005 1.1 fvdl * Disable writes. 9006 1.1 fvdl */ 9007 1.1 fvdl ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 9008 1.1 fvdl ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 9009 1.1 fvdl error = ahd_wait_seeprom(ahd); 9010 1.1 fvdl if (error) 9011 1.1 fvdl return (error); 9012 1.1 fvdl return (retval); 9013 1.1 fvdl } 9014 1.1 fvdl 9015 1.1 fvdl /* 9016 1.1 fvdl * Wait ~100us for the serial eeprom to satisfy our request. 9017 1.1 fvdl */ 9018 1.1 fvdl int 9019 1.1 fvdl ahd_wait_seeprom(struct ahd_softc *ahd) 9020 1.1 fvdl { 9021 1.1 fvdl int cnt; 9022 1.1 fvdl 9023 1.1 fvdl cnt = 2000; 9024 1.1 fvdl while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 9025 1.1 fvdl ahd_delay(5); 9026 1.1 fvdl 9027 1.1 fvdl if (cnt == 0) 9028 1.1 fvdl return (ETIMEDOUT); 9029 1.1 fvdl return (0); 9030 1.9 thorpej } 9031 1.9 thorpej 9032 1.9 thorpej /* 9033 1.9 thorpej * Validate the two checksums in the per_channel 9034 1.9 thorpej * vital product data struct. 9035 1.9 thorpej */ 9036 1.9 thorpej int 9037 1.9 thorpej ahd_verify_vpd_cksum(struct vpd_config *vpd) 9038 1.9 thorpej { 9039 1.9 thorpej int i; 9040 1.9 thorpej int maxaddr; 9041 1.9 thorpej uint32_t checksum; 9042 1.9 thorpej uint8_t *vpdarray; 9043 1.9 thorpej 9044 1.9 thorpej vpdarray = (uint8_t *)vpd; 9045 1.9 thorpej maxaddr = offsetof(struct vpd_config, vpd_checksum); 9046 1.9 thorpej checksum = 0; 9047 1.9 thorpej for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 9048 1.9 thorpej checksum = checksum + vpdarray[i]; 9049 1.9 thorpej if (checksum == 0 9050 1.9 thorpej || (-checksum & 0xFF) != vpd->vpd_checksum) 9051 1.9 thorpej return (0); 9052 1.9 thorpej 9053 1.9 thorpej checksum = 0; 9054 1.9 thorpej maxaddr = offsetof(struct vpd_config, checksum); 9055 1.9 thorpej for (i = offsetof(struct vpd_config, default_target_flags); 9056 1.9 thorpej i < maxaddr; i++) 9057 1.9 thorpej checksum = checksum + vpdarray[i]; 9058 1.9 thorpej if (checksum == 0 9059 1.9 thorpej || (-checksum & 0xFF) != vpd->checksum) 9060 1.9 thorpej return (0); 9061 1.9 thorpej return (1); 9062 1.1 fvdl } 9063 1.1 fvdl 9064 1.1 fvdl int 9065 1.1 fvdl ahd_verify_cksum(struct seeprom_config *sc) 9066 1.1 fvdl { 9067 1.1 fvdl int i; 9068 1.1 fvdl int maxaddr; 9069 1.1 fvdl uint32_t checksum; 9070 1.1 fvdl uint16_t *scarray; 9071 1.1 fvdl 9072 1.1 fvdl maxaddr = (sizeof(*sc)/2) - 1; 9073 1.1 fvdl checksum = 0; 9074 1.1 fvdl scarray = (uint16_t *)sc; 9075 1.1 fvdl 9076 1.1 fvdl for (i = 0; i < maxaddr; i++) 9077 1.1 fvdl checksum = checksum + scarray[i]; 9078 1.1 fvdl if (checksum == 0 9079 1.1 fvdl || (checksum & 0xFFFF) != sc->checksum) { 9080 1.1 fvdl return (0); 9081 1.1 fvdl } else { 9082 1.1 fvdl return (1); 9083 1.1 fvdl } 9084 1.1 fvdl } 9085 1.1 fvdl 9086 1.1 fvdl int 9087 1.36 christos ahd_acquire_seeprom(struct ahd_softc *ahd) 9088 1.1 fvdl { 9089 1.1 fvdl /* 9090 1.1 fvdl * We should be able to determine the SEEPROM type 9091 1.1 fvdl * from the flexport logic, but unfortunately not 9092 1.1 fvdl * all implementations have this logic and there is 9093 1.61 msaitoh * no programmatic method for determining if the logic 9094 1.1 fvdl * is present. 9095 1.1 fvdl */ 9096 1.1 fvdl 9097 1.1 fvdl return (1); 9098 1.1 fvdl #if 0 9099 1.1 fvdl uint8_t seetype; 9100 1.1 fvdl int error; 9101 1.1 fvdl 9102 1.1 fvdl error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 9103 1.1 fvdl if (error != 0 9104 1.43 tsutsui || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 9105 1.1 fvdl return (0); 9106 1.1 fvdl return (1); 9107 1.1 fvdl #endif 9108 1.1 fvdl } 9109 1.1 fvdl 9110 1.1 fvdl void 9111 1.36 christos ahd_release_seeprom(struct ahd_softc *ahd) 9112 1.1 fvdl { 9113 1.1 fvdl /* Currently a no-op */ 9114 1.1 fvdl } 9115 1.1 fvdl 9116 1.1 fvdl int 9117 1.1 fvdl ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 9118 1.1 fvdl { 9119 1.1 fvdl int error; 9120 1.1 fvdl 9121 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9122 1.1 fvdl if (addr > 7) 9123 1.1 fvdl panic("ahd_write_flexport: address out of range"); 9124 1.1 fvdl ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9125 1.1 fvdl error = ahd_wait_flexport(ahd); 9126 1.1 fvdl if (error != 0) 9127 1.1 fvdl return (error); 9128 1.1 fvdl ahd_outb(ahd, BRDDAT, value); 9129 1.1 fvdl ahd_flush_device_writes(ahd); 9130 1.1 fvdl ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 9131 1.1 fvdl ahd_flush_device_writes(ahd); 9132 1.1 fvdl ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9133 1.1 fvdl ahd_flush_device_writes(ahd); 9134 1.1 fvdl ahd_outb(ahd, BRDCTL, 0); 9135 1.1 fvdl ahd_flush_device_writes(ahd); 9136 1.1 fvdl return (0); 9137 1.1 fvdl } 9138 1.1 fvdl 9139 1.1 fvdl int 9140 1.1 fvdl ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 9141 1.1 fvdl { 9142 1.1 fvdl int error; 9143 1.1 fvdl 9144 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9145 1.1 fvdl if (addr > 7) 9146 1.1 fvdl panic("ahd_read_flexport: address out of range"); 9147 1.1 fvdl ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 9148 1.1 fvdl error = ahd_wait_flexport(ahd); 9149 1.1 fvdl if (error != 0) 9150 1.1 fvdl return (error); 9151 1.1 fvdl *value = ahd_inb(ahd, BRDDAT); 9152 1.1 fvdl ahd_outb(ahd, BRDCTL, 0); 9153 1.1 fvdl ahd_flush_device_writes(ahd); 9154 1.1 fvdl return (0); 9155 1.1 fvdl } 9156 1.1 fvdl 9157 1.1 fvdl /* 9158 1.1 fvdl * Wait at most 2 seconds for flexport arbitration to succeed. 9159 1.1 fvdl */ 9160 1.1 fvdl int 9161 1.1 fvdl ahd_wait_flexport(struct ahd_softc *ahd) 9162 1.1 fvdl { 9163 1.1 fvdl int cnt; 9164 1.1 fvdl 9165 1.1 fvdl AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9166 1.1 fvdl cnt = 1000000 * 2 / 5; 9167 1.1 fvdl while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 9168 1.1 fvdl ahd_delay(5); 9169 1.1 fvdl 9170 1.1 fvdl if (cnt == 0) 9171 1.1 fvdl return (ETIMEDOUT); 9172 1.1 fvdl return (0); 9173 1.1 fvdl } 9174 1.1 fvdl 9175 1.1 fvdl /************************* Target Mode ****************************************/ 9176 1.1 fvdl #ifdef AHD_TARGET_MODE 9177 1.1 fvdl cam_status 9178 1.1 fvdl ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 9179 1.1 fvdl struct ahd_tmode_tstate **tstate, 9180 1.1 fvdl struct ahd_tmode_lstate **lstate, 9181 1.1 fvdl int notfound_failure) 9182 1.1 fvdl { 9183 1.1 fvdl 9184 1.1 fvdl if ((ahd->features & AHD_TARGETMODE) == 0) 9185 1.1 fvdl return (CAM_REQ_INVALID); 9186 1.1 fvdl 9187 1.1 fvdl /* 9188 1.1 fvdl * Handle the 'black hole' device that sucks up 9189 1.1 fvdl * requests to unattached luns on enabled targets. 9190 1.1 fvdl */ 9191 1.1 fvdl if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 9192 1.1 fvdl && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 9193 1.1 fvdl *tstate = NULL; 9194 1.1 fvdl *lstate = ahd->black_hole; 9195 1.1 fvdl } else { 9196 1.1 fvdl u_int max_id; 9197 1.1 fvdl 9198 1.1 fvdl max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 9199 1.1 fvdl if (ccb->ccb_h.target_id > max_id) 9200 1.1 fvdl return (CAM_TID_INVALID); 9201 1.1 fvdl 9202 1.1 fvdl if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9203 1.1 fvdl return (CAM_LUN_INVALID); 9204 1.1 fvdl 9205 1.1 fvdl *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9206 1.1 fvdl *lstate = NULL; 9207 1.1 fvdl if (*tstate != NULL) 9208 1.1 fvdl *lstate = 9209 1.1 fvdl (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9210 1.1 fvdl } 9211 1.1 fvdl 9212 1.1 fvdl if (notfound_failure != 0 && *lstate == NULL) 9213 1.1 fvdl return (CAM_PATH_INVALID); 9214 1.1 fvdl 9215 1.1 fvdl return (CAM_REQ_CMP); 9216 1.1 fvdl } 9217 1.1 fvdl 9218 1.1 fvdl void 9219 1.1 fvdl ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9220 1.1 fvdl { 9221 1.1 fvdl #if NOT_YET 9222 1.1 fvdl struct ahd_tmode_tstate *tstate; 9223 1.1 fvdl struct ahd_tmode_lstate *lstate; 9224 1.1 fvdl struct ccb_en_lun *cel; 9225 1.1 fvdl cam_status status; 9226 1.1 fvdl u_int target; 9227 1.1 fvdl u_int lun; 9228 1.1 fvdl u_int target_mask; 9229 1.1 fvdl u_long s; 9230 1.1 fvdl char channel; 9231 1.1 fvdl 9232 1.1 fvdl status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9233 1.1 fvdl /*notfound_failure*/FALSE); 9234 1.1 fvdl 9235 1.1 fvdl if (status != CAM_REQ_CMP) { 9236 1.1 fvdl ccb->ccb_h.status = status; 9237 1.1 fvdl return; 9238 1.1 fvdl } 9239 1.1 fvdl 9240 1.1 fvdl if ((ahd->features & AHD_MULTIROLE) != 0) { 9241 1.1 fvdl u_int our_id; 9242 1.1 fvdl 9243 1.1 fvdl our_id = ahd->our_id; 9244 1.1 fvdl if (ccb->ccb_h.target_id != our_id) { 9245 1.1 fvdl if ((ahd->features & AHD_MULTI_TID) != 0 9246 1.43 tsutsui && (ahd->flags & AHD_INITIATORROLE) != 0) { 9247 1.1 fvdl /* 9248 1.1 fvdl * Only allow additional targets if 9249 1.1 fvdl * the initiator role is disabled. 9250 1.1 fvdl * The hardware cannot handle a re-select-in 9251 1.1 fvdl * on the initiator id during a re-select-out 9252 1.1 fvdl * on a different target id. 9253 1.1 fvdl */ 9254 1.1 fvdl status = CAM_TID_INVALID; 9255 1.1 fvdl } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9256 1.1 fvdl || ahd->enabled_luns > 0) { 9257 1.1 fvdl /* 9258 1.1 fvdl * Only allow our target id to change 9259 1.1 fvdl * if the initiator role is not configured 9260 1.1 fvdl * and there are no enabled luns which 9261 1.1 fvdl * are attached to the currently registered 9262 1.1 fvdl * scsi id. 9263 1.1 fvdl */ 9264 1.1 fvdl status = CAM_TID_INVALID; 9265 1.1 fvdl } 9266 1.1 fvdl } 9267 1.1 fvdl } 9268 1.1 fvdl 9269 1.1 fvdl if (status != CAM_REQ_CMP) { 9270 1.1 fvdl ccb->ccb_h.status = status; 9271 1.1 fvdl return; 9272 1.1 fvdl } 9273 1.1 fvdl 9274 1.1 fvdl /* 9275 1.1 fvdl * We now have an id that is valid. 9276 1.1 fvdl * If we aren't in target mode, switch modes. 9277 1.1 fvdl */ 9278 1.1 fvdl if ((ahd->flags & AHD_TARGETROLE) == 0 9279 1.1 fvdl && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9280 1.1 fvdl u_long s; 9281 1.1 fvdl 9282 1.1 fvdl printf("Configuring Target Mode\n"); 9283 1.1 fvdl ahd_lock(ahd, &s); 9284 1.1 fvdl if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9285 1.1 fvdl ccb->ccb_h.status = CAM_BUSY; 9286 1.1 fvdl ahd_unlock(ahd, &s); 9287 1.1 fvdl return; 9288 1.1 fvdl } 9289 1.1 fvdl ahd->flags |= AHD_TARGETROLE; 9290 1.1 fvdl if ((ahd->features & AHD_MULTIROLE) == 0) 9291 1.1 fvdl ahd->flags &= ~AHD_INITIATORROLE; 9292 1.1 fvdl ahd_pause(ahd); 9293 1.1 fvdl ahd_loadseq(ahd); 9294 1.15 thorpej ahd_restart(ahd); 9295 1.1 fvdl ahd_unlock(ahd, &s); 9296 1.1 fvdl } 9297 1.1 fvdl cel = &ccb->cel; 9298 1.1 fvdl target = ccb->ccb_h.target_id; 9299 1.1 fvdl lun = ccb->ccb_h.target_lun; 9300 1.1 fvdl channel = SIM_CHANNEL(ahd, sim); 9301 1.1 fvdl target_mask = 0x01 << target; 9302 1.1 fvdl if (channel == 'B') 9303 1.1 fvdl target_mask <<= 8; 9304 1.1 fvdl 9305 1.1 fvdl if (cel->enable != 0) { 9306 1.1 fvdl u_int scsiseq1; 9307 1.1 fvdl 9308 1.1 fvdl /* Are we already enabled?? */ 9309 1.1 fvdl if (lstate != NULL) { 9310 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9311 1.1 fvdl printf("Lun already enabled\n"); 9312 1.1 fvdl ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9313 1.1 fvdl return; 9314 1.1 fvdl } 9315 1.1 fvdl 9316 1.1 fvdl if (cel->grp6_len != 0 9317 1.1 fvdl || cel->grp7_len != 0) { 9318 1.1 fvdl /* 9319 1.1 fvdl * Don't (yet?) support vendor 9320 1.1 fvdl * specific commands. 9321 1.1 fvdl */ 9322 1.1 fvdl ccb->ccb_h.status = CAM_REQ_INVALID; 9323 1.1 fvdl printf("Non-zero Group Codes\n"); 9324 1.1 fvdl return; 9325 1.1 fvdl } 9326 1.1 fvdl 9327 1.1 fvdl /* 9328 1.1 fvdl * Seems to be okay. 9329 1.1 fvdl * Setup our data structures. 9330 1.1 fvdl */ 9331 1.1 fvdl if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9332 1.1 fvdl tstate = ahd_alloc_tstate(ahd, target, channel); 9333 1.1 fvdl if (tstate == NULL) { 9334 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9335 1.1 fvdl printf("Couldn't allocate tstate\n"); 9336 1.1 fvdl ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9337 1.1 fvdl return; 9338 1.1 fvdl } 9339 1.1 fvdl } 9340 1.1 fvdl lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9341 1.1 fvdl if (lstate == NULL) { 9342 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9343 1.1 fvdl printf("Couldn't allocate lstate\n"); 9344 1.1 fvdl ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9345 1.1 fvdl return; 9346 1.1 fvdl } 9347 1.1 fvdl memset(lstate, 0, sizeof(*lstate)); 9348 1.1 fvdl status = xpt_create_path(&lstate->path, /*periph*/NULL, 9349 1.1 fvdl xpt_path_path_id(ccb->ccb_h.path), 9350 1.1 fvdl xpt_path_target_id(ccb->ccb_h.path), 9351 1.1 fvdl xpt_path_lun_id(ccb->ccb_h.path)); 9352 1.1 fvdl if (status != CAM_REQ_CMP) { 9353 1.1 fvdl free(lstate, M_DEVBUF); 9354 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9355 1.1 fvdl printf("Couldn't allocate path\n"); 9356 1.1 fvdl ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9357 1.1 fvdl return; 9358 1.1 fvdl } 9359 1.1 fvdl SLIST_INIT(&lstate->accept_tios); 9360 1.1 fvdl SLIST_INIT(&lstate->immed_notifies); 9361 1.1 fvdl ahd_lock(ahd, &s); 9362 1.1 fvdl ahd_pause(ahd); 9363 1.1 fvdl if (target != CAM_TARGET_WILDCARD) { 9364 1.1 fvdl tstate->enabled_luns[lun] = lstate; 9365 1.1 fvdl ahd->enabled_luns++; 9366 1.1 fvdl 9367 1.1 fvdl if ((ahd->features & AHD_MULTI_TID) != 0) { 9368 1.1 fvdl u_int targid_mask; 9369 1.1 fvdl 9370 1.1 fvdl targid_mask = ahd_inb(ahd, TARGID) 9371 1.1 fvdl | (ahd_inb(ahd, TARGID + 1) << 8); 9372 1.1 fvdl 9373 1.1 fvdl targid_mask |= target_mask; 9374 1.1 fvdl ahd_outb(ahd, TARGID, targid_mask); 9375 1.1 fvdl ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9376 1.30 perry 9377 1.1 fvdl ahd_update_scsiid(ahd, targid_mask); 9378 1.1 fvdl } else { 9379 1.1 fvdl u_int our_id; 9380 1.1 fvdl char channel; 9381 1.1 fvdl 9382 1.1 fvdl channel = SIM_CHANNEL(ahd, sim); 9383 1.1 fvdl our_id = SIM_SCSI_ID(ahd, sim); 9384 1.1 fvdl 9385 1.1 fvdl /* 9386 1.1 fvdl * This can only happen if selections 9387 1.1 fvdl * are not enabled 9388 1.1 fvdl */ 9389 1.1 fvdl if (target != our_id) { 9390 1.1 fvdl u_int sblkctl; 9391 1.1 fvdl char cur_channel; 9392 1.1 fvdl int swap; 9393 1.1 fvdl 9394 1.1 fvdl sblkctl = ahd_inb(ahd, SBLKCTL); 9395 1.1 fvdl cur_channel = (sblkctl & SELBUSB) 9396 1.1 fvdl ? 'B' : 'A'; 9397 1.1 fvdl if ((ahd->features & AHD_TWIN) == 0) 9398 1.1 fvdl cur_channel = 'A'; 9399 1.1 fvdl swap = cur_channel != channel; 9400 1.1 fvdl ahd->our_id = target; 9401 1.1 fvdl 9402 1.1 fvdl if (swap) 9403 1.1 fvdl ahd_outb(ahd, SBLKCTL, 9404 1.1 fvdl sblkctl ^ SELBUSB); 9405 1.1 fvdl 9406 1.1 fvdl ahd_outb(ahd, SCSIID, target); 9407 1.1 fvdl 9408 1.1 fvdl if (swap) 9409 1.1 fvdl ahd_outb(ahd, SBLKCTL, sblkctl); 9410 1.1 fvdl } 9411 1.1 fvdl } 9412 1.1 fvdl } else 9413 1.1 fvdl ahd->black_hole = lstate; 9414 1.1 fvdl /* Allow select-in operations */ 9415 1.1 fvdl if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9416 1.1 fvdl scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9417 1.1 fvdl scsiseq1 |= ENSELI; 9418 1.1 fvdl ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9419 1.1 fvdl scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9420 1.1 fvdl scsiseq1 |= ENSELI; 9421 1.1 fvdl ahd_outb(ahd, SCSISEQ1, scsiseq1); 9422 1.1 fvdl } 9423 1.1 fvdl ahd_unpause(ahd); 9424 1.1 fvdl ahd_unlock(ahd, &s); 9425 1.1 fvdl ccb->ccb_h.status = CAM_REQ_CMP; 9426 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9427 1.1 fvdl printf("Lun now enabled for target mode\n"); 9428 1.1 fvdl } else { 9429 1.1 fvdl struct scb *scb; 9430 1.1 fvdl int i, empty; 9431 1.1 fvdl 9432 1.1 fvdl if (lstate == NULL) { 9433 1.1 fvdl ccb->ccb_h.status = CAM_LUN_INVALID; 9434 1.1 fvdl return; 9435 1.1 fvdl } 9436 1.1 fvdl 9437 1.1 fvdl ahd_lock(ahd, &s); 9438 1.30 perry 9439 1.1 fvdl ccb->ccb_h.status = CAM_REQ_CMP; 9440 1.1 fvdl LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9441 1.1 fvdl struct ccb_hdr *ccbh; 9442 1.1 fvdl 9443 1.1 fvdl ccbh = &scb->io_ctx->ccb_h; 9444 1.1 fvdl if (ccbh->func_code == XPT_CONT_TARGET_IO 9445 1.1 fvdl && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9446 1.1 fvdl printf("CTIO pending\n"); 9447 1.1 fvdl ccb->ccb_h.status = CAM_REQ_INVALID; 9448 1.1 fvdl ahd_unlock(ahd, &s); 9449 1.1 fvdl return; 9450 1.1 fvdl } 9451 1.1 fvdl } 9452 1.1 fvdl 9453 1.1 fvdl if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9454 1.1 fvdl printf("ATIOs pending\n"); 9455 1.1 fvdl ccb->ccb_h.status = CAM_REQ_INVALID; 9456 1.1 fvdl } 9457 1.1 fvdl 9458 1.1 fvdl if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9459 1.1 fvdl printf("INOTs pending\n"); 9460 1.1 fvdl ccb->ccb_h.status = CAM_REQ_INVALID; 9461 1.1 fvdl } 9462 1.1 fvdl 9463 1.1 fvdl if (ccb->ccb_h.status != CAM_REQ_CMP) { 9464 1.1 fvdl ahd_unlock(ahd, &s); 9465 1.1 fvdl return; 9466 1.1 fvdl } 9467 1.1 fvdl 9468 1.1 fvdl xpt_print_path(ccb->ccb_h.path); 9469 1.1 fvdl printf("Target mode disabled\n"); 9470 1.1 fvdl xpt_free_path(lstate->path); 9471 1.1 fvdl free(lstate, M_DEVBUF); 9472 1.1 fvdl 9473 1.1 fvdl ahd_pause(ahd); 9474 1.1 fvdl /* Can we clean up the target too? */ 9475 1.1 fvdl if (target != CAM_TARGET_WILDCARD) { 9476 1.1 fvdl tstate->enabled_luns[lun] = NULL; 9477 1.1 fvdl ahd->enabled_luns--; 9478 1.1 fvdl for (empty = 1, i = 0; i < 8; i++) 9479 1.1 fvdl if (tstate->enabled_luns[i] != NULL) { 9480 1.1 fvdl empty = 0; 9481 1.1 fvdl break; 9482 1.1 fvdl } 9483 1.1 fvdl 9484 1.1 fvdl if (empty) { 9485 1.1 fvdl ahd_free_tstate(ahd, target, channel, 9486 1.1 fvdl /*force*/FALSE); 9487 1.1 fvdl if (ahd->features & AHD_MULTI_TID) { 9488 1.1 fvdl u_int targid_mask; 9489 1.1 fvdl 9490 1.1 fvdl targid_mask = ahd_inb(ahd, TARGID) 9491 1.1 fvdl | (ahd_inb(ahd, TARGID + 1) 9492 1.1 fvdl << 8); 9493 1.1 fvdl 9494 1.1 fvdl targid_mask &= ~target_mask; 9495 1.1 fvdl ahd_outb(ahd, TARGID, targid_mask); 9496 1.1 fvdl ahd_outb(ahd, TARGID+1, 9497 1.43 tsutsui (targid_mask >> 8)); 9498 1.1 fvdl ahd_update_scsiid(ahd, targid_mask); 9499 1.1 fvdl } 9500 1.1 fvdl } 9501 1.1 fvdl } else { 9502 1.1 fvdl 9503 1.1 fvdl ahd->black_hole = NULL; 9504 1.1 fvdl 9505 1.1 fvdl /* 9506 1.1 fvdl * We can't allow selections without 9507 1.1 fvdl * our black hole device. 9508 1.1 fvdl */ 9509 1.1 fvdl empty = TRUE; 9510 1.1 fvdl } 9511 1.1 fvdl if (ahd->enabled_luns == 0) { 9512 1.1 fvdl /* Disallow select-in */ 9513 1.1 fvdl u_int scsiseq1; 9514 1.1 fvdl 9515 1.1 fvdl scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9516 1.1 fvdl scsiseq1 &= ~ENSELI; 9517 1.1 fvdl ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9518 1.1 fvdl scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9519 1.1 fvdl scsiseq1 &= ~ENSELI; 9520 1.1 fvdl ahd_outb(ahd, SCSISEQ1, scsiseq1); 9521 1.1 fvdl 9522 1.1 fvdl if ((ahd->features & AHD_MULTIROLE) == 0) { 9523 1.1 fvdl printf("Configuring Initiator Mode\n"); 9524 1.1 fvdl ahd->flags &= ~AHD_TARGETROLE; 9525 1.1 fvdl ahd->flags |= AHD_INITIATORROLE; 9526 1.1 fvdl ahd_pause(ahd); 9527 1.1 fvdl ahd_loadseq(ahd); 9528 1.15 thorpej ahd_restart(ahd); 9529 1.15 thorpej /* 9530 1.15 thorpej * Unpaused. The extra unpause 9531 1.15 thorpej * that follows is harmless. 9532 1.15 thorpej */ 9533 1.1 fvdl } 9534 1.1 fvdl } 9535 1.1 fvdl ahd_unpause(ahd); 9536 1.1 fvdl ahd_unlock(ahd, &s); 9537 1.1 fvdl } 9538 1.1 fvdl #endif 9539 1.1 fvdl } 9540 1.1 fvdl 9541 1.1 fvdl static void 9542 1.1 fvdl ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9543 1.1 fvdl { 9544 1.1 fvdl #if NOT_YET 9545 1.1 fvdl u_int scsiid_mask; 9546 1.1 fvdl u_int scsiid; 9547 1.1 fvdl 9548 1.1 fvdl if ((ahd->features & AHD_MULTI_TID) == 0) 9549 1.1 fvdl panic("ahd_update_scsiid called on non-multitid unit\n"); 9550 1.1 fvdl 9551 1.1 fvdl /* 9552 1.1 fvdl * Since we will rely on the TARGID mask 9553 1.1 fvdl * for selection enables, ensure that OID 9554 1.1 fvdl * in SCSIID is not set to some other ID 9555 1.1 fvdl * that we don't want to allow selections on. 9556 1.1 fvdl */ 9557 1.1 fvdl if ((ahd->features & AHD_ULTRA2) != 0) 9558 1.1 fvdl scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9559 1.1 fvdl else 9560 1.1 fvdl scsiid = ahd_inb(ahd, SCSIID); 9561 1.1 fvdl scsiid_mask = 0x1 << (scsiid & OID); 9562 1.1 fvdl if ((targid_mask & scsiid_mask) == 0) { 9563 1.1 fvdl u_int our_id; 9564 1.1 fvdl 9565 1.1 fvdl /* ffs counts from 1 */ 9566 1.1 fvdl our_id = ffs(targid_mask); 9567 1.1 fvdl if (our_id == 0) 9568 1.1 fvdl our_id = ahd->our_id; 9569 1.1 fvdl else 9570 1.1 fvdl our_id--; 9571 1.1 fvdl scsiid &= TID; 9572 1.1 fvdl scsiid |= our_id; 9573 1.1 fvdl } 9574 1.1 fvdl if ((ahd->features & AHD_ULTRA2) != 0) 9575 1.1 fvdl ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9576 1.1 fvdl else 9577 1.1 fvdl ahd_outb(ahd, SCSIID, scsiid); 9578 1.1 fvdl #endif 9579 1.1 fvdl } 9580 1.1 fvdl 9581 1.1 fvdl #ifdef AHD_TARGET_MODE 9582 1.1 fvdl void 9583 1.1 fvdl ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9584 1.1 fvdl { 9585 1.1 fvdl struct target_cmd *cmd; 9586 1.1 fvdl 9587 1.1 fvdl ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9588 1.1 fvdl while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9589 1.1 fvdl 9590 1.1 fvdl /* 9591 1.1 fvdl * Only advance through the queue if we 9592 1.1 fvdl * have the resources to process the command. 9593 1.1 fvdl */ 9594 1.1 fvdl if (ahd_handle_target_cmd(ahd, cmd) != 0) 9595 1.1 fvdl break; 9596 1.1 fvdl 9597 1.1 fvdl cmd->cmd_valid = 0; 9598 1.1 fvdl ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9599 1.7 thorpej ahd->shared_data_map.dmamap, 9600 1.1 fvdl ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9601 1.1 fvdl sizeof(struct target_cmd), 9602 1.1 fvdl BUS_DMASYNC_PREREAD); 9603 1.1 fvdl ahd->tqinfifonext++; 9604 1.1 fvdl 9605 1.1 fvdl /* 9606 1.1 fvdl * Lazily update our position in the target mode incoming 9607 1.1 fvdl * command queue as seen by the sequencer. 9608 1.1 fvdl */ 9609 1.1 fvdl if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9610 1.1 fvdl u_int hs_mailbox; 9611 1.1 fvdl 9612 1.1 fvdl hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9613 1.1 fvdl hs_mailbox &= ~HOST_TQINPOS; 9614 1.1 fvdl hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9615 1.1 fvdl ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9616 1.1 fvdl } 9617 1.1 fvdl } 9618 1.1 fvdl } 9619 1.1 fvdl #endif 9620 1.1 fvdl 9621 1.1 fvdl static int 9622 1.1 fvdl ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9623 1.1 fvdl { 9624 1.1 fvdl struct ahd_tmode_tstate *tstate; 9625 1.1 fvdl struct ahd_tmode_lstate *lstate; 9626 1.1 fvdl struct ccb_accept_tio *atio; 9627 1.1 fvdl uint8_t *byte; 9628 1.1 fvdl int initiator; 9629 1.1 fvdl int target; 9630 1.1 fvdl int lun; 9631 1.1 fvdl 9632 1.1 fvdl initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9633 1.1 fvdl target = SCSIID_OUR_ID(cmd->scsiid); 9634 1.1 fvdl lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9635 1.1 fvdl 9636 1.1 fvdl byte = cmd->bytes; 9637 1.1 fvdl tstate = ahd->enabled_targets[target]; 9638 1.1 fvdl lstate = NULL; 9639 1.1 fvdl if (tstate != NULL) 9640 1.1 fvdl lstate = tstate->enabled_luns[lun]; 9641 1.1 fvdl 9642 1.1 fvdl /* 9643 1.1 fvdl * Commands for disabled luns go to the black hole driver. 9644 1.1 fvdl */ 9645 1.1 fvdl if (lstate == NULL) 9646 1.1 fvdl lstate = ahd->black_hole; 9647 1.1 fvdl 9648 1.1 fvdl atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9649 1.1 fvdl if (atio == NULL) { 9650 1.1 fvdl ahd->flags |= AHD_TQINFIFO_BLOCKED; 9651 1.1 fvdl /* 9652 1.1 fvdl * Wait for more ATIOs from the peripheral driver for this lun. 9653 1.1 fvdl */ 9654 1.1 fvdl return (1); 9655 1.1 fvdl } else 9656 1.1 fvdl ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9657 1.1 fvdl #ifdef AHD_DEBUG 9658 1.1 fvdl if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9659 1.30 perry printf("%s: incoming command from %d for %d:%d%s\n", 9660 1.1 fvdl ahd_name(ahd), 9661 1.1 fvdl initiator, target, lun, 9662 1.1 fvdl lstate == ahd->black_hole ? "(Black Holed)" : ""); 9663 1.1 fvdl #endif 9664 1.1 fvdl SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9665 1.1 fvdl 9666 1.1 fvdl if (lstate == ahd->black_hole) { 9667 1.1 fvdl /* Fill in the wildcards */ 9668 1.1 fvdl atio->ccb_h.target_id = target; 9669 1.1 fvdl atio->ccb_h.target_lun = lun; 9670 1.1 fvdl } 9671 1.1 fvdl 9672 1.1 fvdl /* 9673 1.1 fvdl * Package it up and send it off to 9674 1.1 fvdl * whomever has this lun enabled. 9675 1.1 fvdl */ 9676 1.1 fvdl atio->sense_len = 0; 9677 1.1 fvdl atio->init_id = initiator; 9678 1.1 fvdl if (byte[0] != 0xFF) { 9679 1.1 fvdl /* Tag was included */ 9680 1.1 fvdl atio->tag_action = *byte++; 9681 1.1 fvdl atio->tag_id = *byte++; 9682 1.1 fvdl atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9683 1.1 fvdl } else { 9684 1.1 fvdl atio->ccb_h.flags = 0; 9685 1.1 fvdl } 9686 1.1 fvdl byte++; 9687 1.1 fvdl 9688 1.1 fvdl /* Okay. Now determine the cdb size based on the command code */ 9689 1.1 fvdl switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9690 1.1 fvdl case 0: 9691 1.1 fvdl atio->cdb_len = 6; 9692 1.1 fvdl break; 9693 1.1 fvdl case 1: 9694 1.1 fvdl case 2: 9695 1.1 fvdl atio->cdb_len = 10; 9696 1.1 fvdl break; 9697 1.1 fvdl case 4: 9698 1.1 fvdl atio->cdb_len = 16; 9699 1.1 fvdl break; 9700 1.1 fvdl case 5: 9701 1.1 fvdl atio->cdb_len = 12; 9702 1.1 fvdl break; 9703 1.1 fvdl case 3: 9704 1.1 fvdl default: 9705 1.1 fvdl /* Only copy the opcode. */ 9706 1.1 fvdl atio->cdb_len = 1; 9707 1.1 fvdl printf("Reserved or VU command code type encountered\n"); 9708 1.1 fvdl break; 9709 1.1 fvdl } 9710 1.30 perry 9711 1.1 fvdl memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9712 1.1 fvdl 9713 1.1 fvdl atio->ccb_h.status |= CAM_CDB_RECVD; 9714 1.1 fvdl 9715 1.1 fvdl if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9716 1.1 fvdl /* 9717 1.1 fvdl * We weren't allowed to disconnect. 9718 1.1 fvdl * We're hanging on the bus until a 9719 1.1 fvdl * continue target I/O comes in response 9720 1.1 fvdl * to this accept tio. 9721 1.1 fvdl */ 9722 1.1 fvdl #ifdef AHD_DEBUG 9723 1.1 fvdl if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9724 1.1 fvdl printf("Received Immediate Command %d:%d:%d - %p\n", 9725 1.1 fvdl initiator, target, lun, ahd->pending_device); 9726 1.1 fvdl #endif 9727 1.1 fvdl ahd->pending_device = lstate; 9728 1.1 fvdl ahd_freeze_ccb((union ccb *)atio); 9729 1.1 fvdl atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9730 1.1 fvdl } 9731 1.1 fvdl xpt_done((union ccb*)atio); 9732 1.1 fvdl return (0); 9733 1.1 fvdl } 9734 1.1 fvdl 9735 1.1 fvdl #endif 9736 1.1 fvdl 9737 1.1 fvdl static int 9738 1.44 tsutsui ahd_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp, 9739 1.44 tsutsui void **vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg, 9740 1.44 tsutsui const char *myname, const char *what) 9741 1.1 fvdl { 9742 1.1 fvdl int error, level = 0; 9743 1.1 fvdl 9744 1.1 fvdl if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9745 1.32 bouyer seg, 1, nseg, BUS_DMA_WAITOK)) != 0) { 9746 1.1 fvdl printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9747 1.1 fvdl myname, what, error); 9748 1.1 fvdl goto out; 9749 1.1 fvdl } 9750 1.1 fvdl level++; 9751 1.1 fvdl 9752 1.1 fvdl if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9753 1.32 bouyer BUS_DMA_WAITOK|BUS_DMA_COHERENT)) != 0) { 9754 1.1 fvdl printf("%s: failed to map DMA mem for %s, error = %d\n", 9755 1.1 fvdl myname, what, error); 9756 1.1 fvdl goto out; 9757 1.1 fvdl } 9758 1.1 fvdl level++; 9759 1.1 fvdl 9760 1.1 fvdl if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9761 1.32 bouyer BUS_DMA_WAITOK | flags, mapp)) != 0) { 9762 1.43 tsutsui printf("%s: failed to create DMA map for %s, error = %d\n", 9763 1.1 fvdl myname, what, error); 9764 1.1 fvdl goto out; 9765 1.43 tsutsui } 9766 1.1 fvdl level++; 9767 1.1 fvdl 9768 1.1 fvdl 9769 1.1 fvdl if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9770 1.32 bouyer BUS_DMA_WAITOK)) != 0) { 9771 1.43 tsutsui printf("%s: failed to load DMA map for %s, error = %d\n", 9772 1.1 fvdl myname, what, error); 9773 1.1 fvdl goto out; 9774 1.43 tsutsui } 9775 1.1 fvdl 9776 1.1 fvdl *baddr = (*mapp)->dm_segs[0].ds_addr; 9777 1.1 fvdl 9778 1.1 fvdl return 0; 9779 1.1 fvdl out: 9780 1.1 fvdl printf("ahd_createdmamem error (%d)\n", level); 9781 1.1 fvdl switch (level) { 9782 1.1 fvdl case 3: 9783 1.1 fvdl bus_dmamap_destroy(tag, *mapp); 9784 1.1 fvdl /* FALLTHROUGH */ 9785 1.1 fvdl case 2: 9786 1.1 fvdl bus_dmamem_unmap(tag, *vaddr, size); 9787 1.1 fvdl /* FALLTHROUGH */ 9788 1.1 fvdl case 1: 9789 1.1 fvdl bus_dmamem_free(tag, seg, *nseg); 9790 1.1 fvdl break; 9791 1.1 fvdl default: 9792 1.1 fvdl break; 9793 1.1 fvdl } 9794 1.1 fvdl 9795 1.1 fvdl return error; 9796 1.1 fvdl } 9797 1.1 fvdl 9798 1.1 fvdl static void 9799 1.44 tsutsui ahd_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, void *vaddr, 9800 1.44 tsutsui bus_dma_segment_t *seg, int nseg) 9801 1.1 fvdl { 9802 1.1 fvdl 9803 1.1 fvdl bus_dmamap_unload(tag, map); 9804 1.1 fvdl bus_dmamap_destroy(tag, map); 9805 1.1 fvdl bus_dmamem_unmap(tag, vaddr, size); 9806 1.1 fvdl bus_dmamem_free(tag, seg, nseg); 9807 1.1 fvdl } 9808