aic79xx.c revision 1.1
1 /* $NetBSD: aic79xx.c,v 1.1 2003/04/21 00:14:52 fvdl Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * //depot/aic7xxx/aic7xxx/aic79xx.c#170 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.11 2003/03/06 23:58:34 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 * - April 2003 49 */ 50 51 #include <dev/ic/aic79xx_osm.h> 52 #include <dev/ic/aic79xx_inline.h> 53 #include <dev/ic/aic7xxx_cam.h> 54 55 #include <dev/microcode/aic7xxx/aicasm.h> 56 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 57 58 59 /******************************** Globals *************************************/ 60 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 61 62 /***************************** Lookup Tables **********************************/ 63 char *ahd_chip_names[] = 64 { 65 "NONE", 66 "aic7901", 67 "aic7902", 68 "aic7901A" 69 }; 70 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names); 71 72 /* 73 * Hardware error codes. 74 */ 75 struct ahd_hard_error_entry { 76 uint8_t errno; 77 char *errmesg; 78 }; 79 80 static struct ahd_hard_error_entry ahd_hard_errors[] = { 81 { DSCTMOUT, "Discard Timer has timed out" }, 82 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 83 { SQPARERR, "Sequencer Parity Error" }, 84 { DPARERR, "Data-path Parity Error" }, 85 { MPARERR, "Scratch or SCB Memory Parity Error" }, 86 { CIOPARERR, "CIOBUS Parity Error" }, 87 }; 88 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 89 90 static struct ahd_phase_table_entry ahd_phase_table[] = 91 { 92 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 93 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 94 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 95 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 96 { P_COMMAND, MSG_NOOP, "in Command phase" }, 97 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 98 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 99 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 100 { P_BUSFREE, MSG_NOOP, "while idle" }, 101 { 0, MSG_NOOP, "in unknown phase" } 102 }; 103 104 /* 105 * In most cases we only wish to itterate over real phases, so 106 * exclude the last element from the count. 107 */ 108 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 109 110 /* Our Sequencer Program */ 111 #include <dev/microcode/aic7xxx/aic79xx_seq.h> 112 113 /**************************** Function Declarations ***************************/ 114 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 115 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 116 u_int lqistat1); 117 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 118 u_int busfreetime); 119 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 120 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 121 static void ahd_force_renegotiation(struct ahd_softc *ahd, 122 struct ahd_devinfo *devinfo); 123 124 static struct ahd_tmode_tstate* 125 ahd_alloc_tstate(struct ahd_softc *ahd, 126 u_int scsi_id, char channel); 127 #ifdef AHD_TARGET_MODE 128 static void ahd_free_tstate(struct ahd_softc *ahd, 129 u_int scsi_id, char channel, int force); 130 #endif 131 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 132 struct ahd_initiator_tinfo *, 133 u_int *period, 134 u_int *ppr_options, 135 role_t role); 136 static void ahd_update_neg_table(struct ahd_softc *ahd, 137 struct ahd_devinfo *devinfo, 138 struct ahd_transinfo *tinfo); 139 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 140 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 141 struct ahd_devinfo *devinfo); 142 static void ahd_scb_devinfo(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo, 144 struct scb *scb); 145 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 146 struct ahd_devinfo *devinfo, 147 struct scb *scb); 148 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 149 struct ahd_devinfo *devinfo); 150 static void ahd_construct_sdtr(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo, 152 u_int period, u_int offset); 153 static void ahd_construct_wdtr(struct ahd_softc *ahd, 154 struct ahd_devinfo *devinfo, 155 u_int bus_width); 156 static void ahd_construct_ppr(struct ahd_softc *ahd, 157 struct ahd_devinfo *devinfo, 158 u_int period, u_int offset, 159 u_int bus_width, u_int ppr_options); 160 static void ahd_clear_msg_state(struct ahd_softc *ahd); 161 static void ahd_handle_message_phase(struct ahd_softc *ahd); 162 typedef enum { 163 AHDMSG_1B, 164 AHDMSG_2B, 165 AHDMSG_EXT 166 } ahd_msgtype; 167 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 168 u_int msgval, int full); 169 static int ahd_parse_msg(struct ahd_softc *ahd, 170 struct ahd_devinfo *devinfo); 171 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 172 struct ahd_devinfo *devinfo); 173 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo); 175 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 176 static void ahd_handle_devreset(struct ahd_softc *ahd, 177 struct ahd_devinfo *devinfo, 178 u_int lun, cam_status status, 179 char *message, int verbose_level); 180 #if AHD_TARGET_MODE 181 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 182 struct ahd_devinfo *devinfo, 183 struct scb *scb); 184 #endif 185 186 static u_int ahd_sglist_size(struct ahd_softc *ahd); 187 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 188 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 189 static int ahd_init_scbdata(struct ahd_softc *ahd); 190 static void ahd_fini_scbdata(struct ahd_softc *ahd); 191 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 192 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 193 static void ahd_add_col_list(struct ahd_softc *ahd, 194 struct scb *scb, u_int col_idx); 195 static void ahd_rem_col_list(struct ahd_softc *ahd, 196 struct scb *scb); 197 static void ahd_chip_init(struct ahd_softc *ahd); 198 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 199 struct scb *prev_scb, 200 struct scb *scb); 201 static int ahd_qinfifo_count(struct ahd_softc *ahd); 202 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 203 char channel, int lun, u_int tag, 204 role_t role, uint32_t status, 205 ahd_search_action action, 206 u_int *list_head, u_int tid); 207 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 208 u_int tid_prev, u_int tid_cur, 209 u_int tid_next); 210 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 211 u_int scbid); 212 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 213 u_int prev, u_int next, u_int tid); 214 static void ahd_reset_current_bus(struct ahd_softc *ahd); 215 static ahd_callback_t ahd_reset_poll; 216 static ahd_callback_t ahd_stat_timer; 217 #ifdef AHD_DUMP_SEQ 218 static void ahd_dumpseq(struct ahd_softc *ahd); 219 #endif 220 static void ahd_loadseq(struct ahd_softc *ahd); 221 static int ahd_check_patch(struct ahd_softc *ahd, 222 struct patch **start_patch, 223 u_int start_instr, u_int *skip_addr); 224 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 225 u_int address); 226 static void ahd_download_instr(struct ahd_softc *ahd, 227 u_int instrptr, uint8_t *dconsts); 228 static int ahd_probe_stack_size(struct ahd_softc *ahd); 229 #ifdef AHD_TARGET_MODE 230 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 231 struct ahd_tmode_lstate *lstate, 232 u_int initiator_id, 233 u_int event_type, 234 u_int event_arg); 235 static void ahd_update_scsiid(struct ahd_softc *ahd, 236 u_int targid_mask); 237 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 238 struct target_cmd *cmd); 239 #endif 240 241 /************************** Added for porting to NetBSD ***********************/ 242 static int ahd_createdmamem(bus_dma_tag_t tag, 243 int size, 244 int flags, 245 bus_dmamap_t *mapp, 246 caddr_t *vaddr, 247 bus_addr_t *baddr, 248 bus_dma_segment_t *seg, 249 int *nseg, 250 const char *myname, const char *what); 251 252 static void ahd_freedmamem(bus_dma_tag_t tag, 253 int size, 254 bus_dmamap_t map, 255 caddr_t vaddr, 256 bus_dma_segment_t *seg, 257 int nseg); 258 static void ahd_update_xfer_mode(struct ahd_softc *ahc, 259 struct ahd_devinfo *devinfo); 260 261 /******************************** Private Inlines *****************************/ 262 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 263 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 264 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 265 266 static __inline void 267 ahd_assert_atn(struct ahd_softc *ahd) 268 { 269 ahd_outb(ahd, SCSISIGO, ATNO); 270 } 271 272 /* 273 * Determine if the current connection has a packetized 274 * agreement. This does not necessarily mean that we 275 * are currently in a packetized transfer. We could 276 * just as easily be sending or receiving a message. 277 */ 278 static __inline int 279 ahd_currently_packetized(struct ahd_softc *ahd) 280 { 281 ahd_mode_state saved_modes; 282 int packetized; 283 284 saved_modes = ahd_save_modes(ahd); 285 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 286 /* 287 * The packetized bit refers to the last 288 * connection, not the current one. Check 289 * for non-zero LQISTATE instead. 290 */ 291 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 292 packetized = ahd_inb(ahd, LQISTATE) != 0; 293 } else { 294 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 295 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 296 } 297 ahd_restore_modes(ahd, saved_modes); 298 return (packetized); 299 } 300 301 static __inline int 302 ahd_set_active_fifo(struct ahd_softc *ahd) 303 { 304 u_int active_fifo; 305 306 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 307 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 308 switch (active_fifo) { 309 case 0: 310 case 1: 311 ahd_set_modes(ahd, active_fifo, active_fifo); 312 return (1); 313 default: 314 return (0); 315 } 316 } 317 318 /************************* Sequencer Execution Control ************************/ 319 /* 320 * Restart the sequencer program from address zero 321 */ 322 void 323 ahd_restart(struct ahd_softc *ahd) 324 { 325 326 ahd_pause(ahd); 327 328 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 329 330 /* No more pending messages */ 331 ahd_clear_msg_state(ahd); 332 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 333 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 334 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 335 ahd_outb(ahd, SEQINTCTL, 0); 336 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 337 ahd_outb(ahd, SEQ_FLAGS, 0); 338 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 339 ahd_outb(ahd, SAVED_LUN, 0xFF); 340 341 /* 342 * Ensure that the sequencer's idea of TQINPOS 343 * matches our own. The sequencer increments TQINPOS 344 * only after it sees a DMA complete and a reset could 345 * occur before the increment leaving the kernel to believe 346 * the command arrived but the sequencer to not. 347 */ 348 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 349 350 /* Always allow reselection */ 351 ahd_outb(ahd, SCSISEQ1, 352 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 353 /* Ensure that no DMA operations are in progress */ 354 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 355 ahd_outb(ahd, SCBHCNT, 0); 356 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 357 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 358 ahd_unpause(ahd); 359 } 360 361 void 362 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 363 { 364 ahd_mode_state saved_modes; 365 366 #ifdef AHD_DEBUG 367 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 368 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 369 #endif 370 saved_modes = ahd_save_modes(ahd); 371 ahd_set_modes(ahd, fifo, fifo); 372 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 373 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 374 ahd_outb(ahd, CCSGCTL, CCSGRESET); 375 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 376 ahd_outb(ahd, SG_STATE, 0); 377 ahd_restore_modes(ahd, saved_modes); 378 } 379 380 /************************* Input/Output Queues ********************************/ 381 /* 382 * Flush and completed commands that are sitting in the command 383 * complete queues down on the chip but have yet to be dma'ed back up. 384 */ 385 void 386 ahd_flush_qoutfifo(struct ahd_softc *ahd) 387 { 388 struct scb *scb; 389 ahd_mode_state saved_modes; 390 u_int saved_scbptr; 391 u_int ccscbctl; 392 u_int scbid; 393 u_int next_scbid; 394 395 saved_modes = ahd_save_modes(ahd); 396 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 397 saved_scbptr = ahd_get_scbptr(ahd); 398 399 /* 400 * Wait for any inprogress DMA to complete and clear DMA state 401 * if this if for an SCB in the qinfifo. 402 */ 403 while ((ccscbctl = ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) { 404 405 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 406 if ((ccscbctl & ARRDONE) != 0) 407 break; 408 } else if ((ccscbctl & CCSCBDONE) != 0) 409 break; 410 ahd_delay(200); 411 } 412 if ((ccscbctl & CCSCBDIR) != 0) 413 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 414 415 /* 416 * Complete any SCBs that just finished being 417 * DMA'ed into the qoutfifo. 418 */ 419 ahd_run_qoutfifo(ahd); 420 421 /* 422 * Manually update/complete any completed SCBs that are waiting to be 423 * DMA'ed back up to the host. 424 */ 425 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 426 while (!SCBID_IS_NULL(scbid)) { 427 uint8_t *hscb_ptr; 428 u_int i; 429 430 ahd_set_scbptr(ahd, scbid); 431 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 432 scb = ahd_lookup_scb(ahd, scbid); 433 if (scb == NULL) { 434 printf("%s: Warning - DMA-up and complete " 435 "SCB %d invalid\n", ahd_name(ahd), scbid); 436 continue; 437 } 438 hscb_ptr = (uint8_t *)scb->hscb; 439 for (i = 0; i < sizeof(struct hardware_scb); i++) 440 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 441 442 ahd_complete_scb(ahd, scb); 443 scbid = next_scbid; 444 } 445 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 446 447 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 448 while (!SCBID_IS_NULL(scbid)) { 449 450 ahd_set_scbptr(ahd, scbid); 451 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 452 scb = ahd_lookup_scb(ahd, scbid); 453 if (scb == NULL) { 454 printf("%s: Warning - Complete SCB %d invalid\n", 455 ahd_name(ahd), scbid); 456 continue; 457 } 458 459 ahd_complete_scb(ahd, scb); 460 scbid = next_scbid; 461 } 462 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 463 ahd_set_scbptr(ahd, saved_scbptr); 464 465 /* 466 * Flush the good status FIFO for compelted packetized commands. 467 */ 468 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 469 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 470 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 471 | ahd_inb(ahd, GSFIFO); 472 scb = ahd_lookup_scb(ahd, scbid); 473 if (scb == NULL) { 474 printf("%s: Warning - GSFIFO SCB %d invalid\n", 475 ahd_name(ahd), scbid); 476 continue; 477 } 478 ahd_complete_scb(ahd, scb); 479 } 480 481 /* 482 * Restore state. 483 */ 484 ahd_restore_modes(ahd, saved_modes); 485 ahd->flags |= AHD_UPDATE_PEND_CMDS; 486 } 487 488 void 489 ahd_run_qoutfifo(struct ahd_softc *ahd) 490 { 491 struct scb *scb; 492 u_int scb_index; 493 494 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 495 panic("ahd_run_qoutfifo recursion"); 496 ahd->flags |= AHD_RUNNING_QOUTFIFO; 497 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 498 while ((ahd->qoutfifo[ahd->qoutfifonext] 499 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 500 501 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 502 & ~QOUTFIFO_ENTRY_VALID_LE); 503 scb = ahd_lookup_scb(ahd, scb_index); 504 if (scb == NULL) { 505 printf("%s: WARNING no command for scb %d " 506 "(cmdcmplt)\nQOUTPOS = %d\n", 507 ahd_name(ahd), scb_index, 508 ahd->qoutfifonext); 509 ahd_dump_card_state(ahd); 510 } else 511 ahd_complete_scb(ahd, scb); 512 513 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 514 if (ahd->qoutfifonext == 0) 515 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 516 } 517 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 518 } 519 520 /************************* Interrupt Handling *********************************/ 521 void 522 ahd_handle_hwerrint(struct ahd_softc *ahd) 523 { 524 /* 525 * Some catastrophic hardware error has occurred. 526 * Print it for the user and disable the controller. 527 */ 528 int i; 529 int error; 530 531 error = ahd_inb(ahd, ERROR); 532 for (i = 0; i < num_errors; i++) { 533 if ((error & ahd_hard_errors[i].errno) != 0) 534 printf("%s: hwerrint, %s\n", 535 ahd_name(ahd), ahd_hard_errors[i].errmesg); 536 } 537 538 ahd_dump_card_state(ahd); 539 panic("BRKADRINT"); 540 541 /* Tell everyone that this HBA is no longer available */ 542 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 543 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 544 CAM_NO_HBA); 545 546 /* Tell the system that this controller has gone away. */ 547 ahd_free(ahd); 548 } 549 550 void 551 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 552 { 553 u_int seqintcode; 554 555 /* 556 * Save the sequencer interrupt code and clear the SEQINT 557 * bit. We will unpause the sequencer, if appropriate, 558 * after servicing the request. 559 */ 560 seqintcode = ahd_inb(ahd, SEQINTCODE); 561 ahd_outb(ahd, CLRINT, CLRSEQINT); 562 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 563 /* 564 * Unpause the sequencer and let it clear 565 * SEQINT by writing NO_SEQINT to it. This 566 * will cause the sequencer to be paused again, 567 * which is the expected state of this routine. 568 */ 569 ahd_unpause(ahd); 570 while (!ahd_is_paused(ahd)) 571 ; 572 ahd_outb(ahd, CLRINT, CLRSEQINT); 573 } 574 ahd_update_modes(ahd); 575 #ifdef AHD_DEBUG 576 if ((ahd_debug & AHD_SHOW_MISC) != 0) 577 printf("%s: Handle Seqint Called for code %d\n", 578 ahd_name(ahd), seqintcode); 579 #endif 580 switch (seqintcode) { 581 case ENTERING_NONPACK: 582 { 583 struct scb *scb; 584 u_int scbid; 585 586 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 587 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 588 scbid = ahd_get_scbptr(ahd); 589 scb = ahd_lookup_scb(ahd, scbid); 590 if (scb == NULL) { 591 /* 592 * Somehow need to know if this 593 * is from a selection or reselection. 594 * From that, we can termine target 595 * ID so we at least have an I_T nexus. 596 */ 597 } else { 598 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 599 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 600 ahd_outb(ahd, SEQ_FLAGS, 0x0); 601 } 602 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 603 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 604 /* 605 * Phase change after read stream with 606 * CRC error with P0 asserted on last 607 * packet. 608 */ 609 #ifdef AHD_DEBUG 610 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 611 printf("%s: Assuming LQIPHASE_NLQ with " 612 "P0 assertion\n", ahd_name(ahd)); 613 #endif 614 } 615 #ifdef AHD_DEBUG 616 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 617 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 618 #endif 619 break; 620 } 621 case INVALID_SEQINT: 622 printf("%s: Invalid Sequencer interrupt occurred.\n", 623 ahd_name(ahd)); 624 ahd_dump_card_state(ahd); 625 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 626 break; 627 case STATUS_OVERRUN: 628 { 629 printf("%s: Status Overrun", ahd_name(ahd)); 630 ahd_dump_card_state(ahd); 631 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 632 break; 633 } 634 case CFG4ISTAT_INTR: 635 { 636 struct scb *scb; 637 u_int scbid; 638 639 scbid = ahd_get_scbptr(ahd); 640 scb = ahd_lookup_scb(ahd, scbid); 641 if (scb == NULL) { 642 ahd_dump_card_state(ahd); 643 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 644 panic("For safety"); 645 } 646 ahd_outq(ahd, HADDR, scb->sense_busaddr); 647 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 648 ahd_outb(ahd, HCNT + 2, 0); 649 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 650 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 651 break; 652 } 653 case ILLEGAL_PHASE: 654 { 655 u_int bus_phase; 656 657 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 658 printf("%s: ILLEGAL_PHASE 0x%x\n", 659 ahd_name(ahd), bus_phase); 660 661 switch (bus_phase) { 662 case P_DATAOUT: 663 case P_DATAIN: 664 case P_DATAOUT_DT: 665 case P_DATAIN_DT: 666 case P_MESGOUT: 667 case P_STATUS: 668 case P_MESGIN: 669 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 670 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 671 break; 672 case P_COMMAND: 673 { 674 struct ahd_devinfo devinfo; 675 struct scb *scb; 676 struct ahd_initiator_tinfo *targ_info; 677 struct ahd_tmode_tstate *tstate; 678 struct ahd_transinfo *tinfo; 679 u_int scbid; 680 681 /* 682 * If a target takes us into the command phase 683 * assume that it has been externally reset and 684 * has thus lost our previous packetized negotiation 685 * agreement. Since we have not sent an identify 686 * message and may not have fully qualified the 687 * connection, we change our command to TUR, assert 688 * ATN and ABORT the task when we go to message in 689 * phase. The OSM will see the REQUEUE_REQUEST 690 * status and retry the command. 691 */ 692 scbid = ahd_get_scbptr(ahd); 693 scb = ahd_lookup_scb(ahd, scbid); 694 if (scb == NULL) { 695 printf("Invalid phase with no valid SCB. " 696 "Resetting bus.\n"); 697 ahd_reset_channel(ahd, 'A', 698 /*Initiate Reset*/TRUE); 699 break; 700 } 701 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 702 SCB_GET_TARGET(ahd, scb), 703 SCB_GET_LUN(scb), 704 SCB_GET_CHANNEL(ahd, scb), 705 ROLE_INITIATOR); 706 targ_info = ahd_fetch_transinfo(ahd, 707 devinfo.channel, 708 devinfo.our_scsiid, 709 devinfo.target, 710 &tstate); 711 tinfo = &targ_info->curr; 712 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 713 AHD_TRANS_ACTIVE, /*paused*/TRUE); 714 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 715 /*offset*/0, /*ppr_options*/0, 716 AHD_TRANS_ACTIVE, /*paused*/TRUE); 717 ahd_outb(ahd, SCB_CDB_STORE, 0); 718 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 719 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 720 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 721 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 722 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 723 ahd_outb(ahd, SCB_CDB_LEN, 6); 724 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 725 scb->hscb->control |= MK_MESSAGE; 726 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 727 ahd_outb(ahd, MSG_OUT, HOST_MSG); 728 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 729 /* 730 * The lun is 0, regardless of the SCB's lun 731 * as we have not sent an identify message. 732 */ 733 ahd_outb(ahd, SAVED_LUN, 0); 734 ahd_outb(ahd, SEQ_FLAGS, 0); 735 ahd_assert_atn(ahd); 736 scb->flags &= ~(SCB_PACKETIZED); 737 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 738 ahd_freeze_devq(ahd, scb); 739 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 740 ahd_freeze_scb(scb); 741 742 /* 743 * Allow the sequencer to continue with 744 * non-pack processing. 745 */ 746 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 747 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 748 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 749 ahd_outb(ahd, CLRLQOINT1, 0); 750 } 751 #ifdef AHD_DEBUG 752 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 753 ahd_print_path(ahd, scb); 754 printf("Unexpected command phase from " 755 "packetized target\n"); 756 } 757 #endif 758 break; 759 } 760 } 761 break; 762 } 763 case CFG4OVERRUN: 764 { 765 struct scb *scb; 766 u_int scb_index; 767 768 #ifdef AHD_DEBUG 769 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 770 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 771 ahd_inb(ahd, MODE_PTR)); 772 } 773 #endif 774 scb_index = ahd_get_scbptr(ahd); 775 scb = ahd_lookup_scb(ahd, scb_index); 776 if (scb == NULL) { 777 /* 778 * Attempt to transfer to an SCB that is 779 * not outstanding. 780 */ 781 ahd_assert_atn(ahd); 782 ahd_outb(ahd, MSG_OUT, HOST_MSG); 783 ahd->msgout_buf[0] = MSG_ABORT_TASK; 784 ahd->msgout_len = 1; 785 ahd->msgout_index = 0; 786 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 787 /* 788 * Clear status received flag to prevent any 789 * attempt to complete this bogus SCB. 790 */ 791 ahd_outb(ahd, SCB_CONTROL, 792 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 793 } 794 break; 795 } 796 case DUMP_CARD_STATE: 797 { 798 ahd_dump_card_state(ahd); 799 break; 800 } 801 case PDATA_REINIT: 802 { 803 #ifdef AHD_DEBUG 804 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 805 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 806 "SG_CACHE_SHADOW = 0x%x\n", 807 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 808 ahd_inb(ahd, SG_CACHE_SHADOW)); 809 } 810 #endif 811 ahd_reinitialize_dataptrs(ahd); 812 break; 813 } 814 case HOST_MSG_LOOP: 815 { 816 struct ahd_devinfo devinfo; 817 818 /* 819 * The sequencer has encountered a message phase 820 * that requires host assistance for completion. 821 * While handling the message phase(s), we will be 822 * notified by the sequencer after each byte is 823 * transfered so we can track bus phase changes. 824 * 825 * If this is the first time we've seen a HOST_MSG_LOOP 826 * interrupt, initialize the state of the host message 827 * loop. 828 */ 829 ahd_fetch_devinfo(ahd, &devinfo); 830 if (ahd->msg_type == MSG_TYPE_NONE) { 831 struct scb *scb; 832 u_int scb_index; 833 u_int bus_phase; 834 835 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 836 if (bus_phase != P_MESGIN 837 && bus_phase != P_MESGOUT) { 838 printf("ahd_intr: HOST_MSG_LOOP bad " 839 "phase 0x%x\n", bus_phase); 840 /* 841 * Probably transitioned to bus free before 842 * we got here. Just punt the message. 843 */ 844 ahd_dump_card_state(ahd); 845 ahd_clear_intstat(ahd); 846 ahd_restart(ahd); 847 return; 848 } 849 850 scb_index = ahd_get_scbptr(ahd); 851 scb = ahd_lookup_scb(ahd, scb_index); 852 if (devinfo.role == ROLE_INITIATOR) { 853 if (bus_phase == P_MESGOUT) 854 ahd_setup_initiator_msgout(ahd, 855 &devinfo, 856 scb); 857 else { 858 ahd->msg_type = 859 MSG_TYPE_INITIATOR_MSGIN; 860 ahd->msgin_index = 0; 861 } 862 } 863 #if AHD_TARGET_MODE 864 else { 865 if (bus_phase == P_MESGOUT) { 866 ahd->msg_type = 867 MSG_TYPE_TARGET_MSGOUT; 868 ahd->msgin_index = 0; 869 } 870 else 871 ahd_setup_target_msgin(ahd, 872 &devinfo, 873 scb); 874 } 875 #endif 876 } 877 878 ahd_handle_message_phase(ahd); 879 break; 880 } 881 case NO_MATCH: 882 { 883 /* Ensure we don't leave the selection hardware on */ 884 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 885 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 886 887 printf("%s:%c:%d: no active SCB for reconnecting " 888 "target - issuing BUS DEVICE RESET\n", 889 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 890 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 891 "REG0 == 0x%x ACCUM = 0x%x\n", 892 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 893 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 894 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 895 "SINDEX == 0x%x\n", 896 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 897 ahd_find_busy_tcl(ahd, 898 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 899 ahd_inb(ahd, SAVED_LUN))), 900 ahd_inw(ahd, SINDEX)); 901 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 902 "SCB_CONTROL == 0x%x\n", 903 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 904 ahd_inb_scbram(ahd, SCB_LUN), 905 ahd_inb_scbram(ahd, SCB_CONTROL)); 906 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 907 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 908 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 909 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 910 ahd_dump_card_state(ahd); 911 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 912 ahd->msgout_len = 1; 913 ahd->msgout_index = 0; 914 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 915 ahd_outb(ahd, MSG_OUT, HOST_MSG); 916 ahd_assert_atn(ahd); 917 break; 918 } 919 case PROTO_VIOLATION: 920 { 921 ahd_handle_proto_violation(ahd); 922 break; 923 } 924 case IGN_WIDE_RES: 925 { 926 struct ahd_devinfo devinfo; 927 928 ahd_fetch_devinfo(ahd, &devinfo); 929 ahd_handle_ign_wide_residue(ahd, &devinfo); 930 break; 931 } 932 case BAD_PHASE: 933 { 934 u_int lastphase; 935 936 lastphase = ahd_inb(ahd, LASTPHASE); 937 printf("%s:%c:%d: unknown scsi bus phase %x, " 938 "lastphase = 0x%x. Attempting to continue\n", 939 ahd_name(ahd), 'A', 940 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 941 lastphase, ahd_inb(ahd, SCSISIGI)); 942 break; 943 } 944 case MISSED_BUSFREE: 945 { 946 u_int lastphase; 947 948 lastphase = ahd_inb(ahd, LASTPHASE); 949 printf("%s:%c:%d: Missed busfree. " 950 "Lastphase = 0x%x, Curphase = 0x%x\n", 951 ahd_name(ahd), 'A', 952 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 953 lastphase, ahd_inb(ahd, SCSISIGI)); 954 ahd_restart(ahd); 955 return; 956 } 957 case DATA_OVERRUN: 958 { 959 /* 960 * When the sequencer detects an overrun, it 961 * places the controller in "BITBUCKET" mode 962 * and allows the target to complete its transfer. 963 * Unfortunately, none of the counters get updated 964 * when the controller is in this mode, so we have 965 * no way of knowing how large the overrun was. 966 */ 967 struct scb *scb; 968 u_int scbindex; 969 #ifdef AHD_DEBUG 970 u_int lastphase; 971 #endif 972 973 scbindex = ahd_get_scbptr(ahd); 974 scb = ahd_lookup_scb(ahd, scbindex); 975 #ifdef AHD_DEBUG 976 lastphase = ahd_inb(ahd, LASTPHASE); 977 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 978 ahd_print_path(ahd, scb); 979 printf("data overrun detected %s. Tag == 0x%x.\n", 980 ahd_lookup_phase_entry(lastphase)->phasemsg, 981 SCB_GET_TAG(scb)); 982 ahd_print_path(ahd, scb); 983 printf("%s seen Data Phase. Length = %ld. " 984 "NumSGs = %d.\n", 985 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 986 ? "Have" : "Haven't", 987 ahd_get_transfer_length(scb), scb->sg_count); 988 ahd_dump_sglist(scb); 989 } 990 #endif 991 992 /* 993 * Set this and it will take effect when the 994 * target does a command complete. 995 */ 996 ahd_freeze_devq(ahd, scb); 997 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 998 ahd_freeze_scb(scb); 999 break; 1000 } 1001 case MKMSG_FAILED: 1002 { 1003 struct ahd_devinfo devinfo; 1004 struct scb *scb; 1005 u_int scbid; 1006 1007 ahd_fetch_devinfo(ahd, &devinfo); 1008 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1009 ahd_name(ahd), devinfo.channel, devinfo.target, 1010 devinfo.lun); 1011 scbid = ahd_get_scbptr(ahd); 1012 scb = ahd_lookup_scb(ahd, scbid); 1013 if (scb != NULL 1014 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1015 /* 1016 * Ensure that we didn't put a second instance of this 1017 * SCB into the QINFIFO. 1018 */ 1019 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1020 SCB_GET_CHANNEL(ahd, scb), 1021 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1022 ROLE_INITIATOR, /*status*/0, 1023 SEARCH_REMOVE); 1024 ahd_outb(ahd, SCB_CONTROL, 1025 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1026 break; 1027 } 1028 case TASKMGMT_FUNC_COMPLETE: 1029 { 1030 u_int scbid; 1031 struct scb *scb; 1032 1033 scbid = ahd_get_scbptr(ahd); 1034 scb = ahd_lookup_scb(ahd, scbid); 1035 if (scb != NULL) { 1036 u_int lun; 1037 u_int tag; 1038 cam_status error; 1039 1040 ahd_print_path(ahd, scb); 1041 printf("Task Management Func 0x%x Complete\n", 1042 scb->hscb->task_management); 1043 lun = CAM_LUN_WILDCARD; 1044 tag = SCB_LIST_NULL; 1045 1046 switch (scb->hscb->task_management) { 1047 case SIU_TASKMGMT_ABORT_TASK: 1048 tag = scb->hscb->tag; 1049 case SIU_TASKMGMT_ABORT_TASK_SET: 1050 case SIU_TASKMGMT_CLEAR_TASK_SET: 1051 lun = scb->hscb->lun; 1052 error = CAM_REQ_ABORTED; 1053 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1054 'A', lun, tag, ROLE_INITIATOR, 1055 error); 1056 break; 1057 case SIU_TASKMGMT_LUN_RESET: 1058 lun = scb->hscb->lun; 1059 case SIU_TASKMGMT_TARGET_RESET: 1060 { 1061 struct ahd_devinfo devinfo; 1062 1063 ahd_scb_devinfo(ahd, &devinfo, scb); 1064 error = CAM_BDR_SENT; 1065 ahd_handle_devreset(ahd, &devinfo, lun, 1066 CAM_BDR_SENT, 1067 lun != CAM_LUN_WILDCARD 1068 ? "Lun Reset" 1069 : "Target Reset", 1070 /*verbose_level*/0); 1071 break; 1072 } 1073 default: 1074 panic("Unexpected TaskMgmt Func\n"); 1075 break; 1076 } 1077 } 1078 break; 1079 } 1080 case TASKMGMT_CMD_CMPLT_OKAY: 1081 { 1082 u_int scbid; 1083 struct scb *scb; 1084 1085 /* 1086 * An ABORT TASK TMF failed to be delivered before 1087 * the targeted command completed normally. 1088 */ 1089 scbid = ahd_get_scbptr(ahd); 1090 scb = ahd_lookup_scb(ahd, scbid); 1091 if (scb != NULL) { 1092 /* 1093 * Remove the second instance of this SCB from 1094 * the QINFIFO if it is still there. 1095 */ 1096 ahd_print_path(ahd, scb); 1097 printf("SCB completes before TMF\n"); 1098 /* 1099 * Handle losing the race. Wait until any 1100 * current selection completes. We will then 1101 * set the TMF back to zero in this SCB so that 1102 * the sequencer doesn't bother to issue another 1103 * sequencer interrupt for its completion. 1104 */ 1105 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1106 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1107 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1108 ; 1109 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1110 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1111 SCB_GET_CHANNEL(ahd, scb), 1112 SCB_GET_LUN(scb), scb->hscb->tag, 1113 ROLE_INITIATOR, /*status*/0, 1114 SEARCH_REMOVE); 1115 } 1116 break; 1117 } 1118 case TRACEPOINT0: 1119 case TRACEPOINT1: 1120 case TRACEPOINT2: 1121 case TRACEPOINT3: 1122 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1123 seqintcode - TRACEPOINT0); 1124 break; 1125 case NO_SEQINT: 1126 break; 1127 case SAW_HWERR: 1128 ahd_handle_hwerrint(ahd); 1129 break; 1130 default: 1131 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1132 seqintcode); 1133 break; 1134 } 1135 /* 1136 * The sequencer is paused immediately on 1137 * a SEQINT, so we should restart it when 1138 * we're done. 1139 */ 1140 ahd_unpause(ahd); 1141 } 1142 1143 void 1144 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1145 { 1146 struct scb *scb; 1147 u_int status0; 1148 u_int status3; 1149 u_int status; 1150 u_int lqistat1; 1151 u_int lqostat0; 1152 u_int scbid; 1153 u_int busfreetime; 1154 1155 ahd_update_modes(ahd); 1156 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1157 1158 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1159 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1160 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1161 lqistat1 = ahd_inb(ahd, LQISTAT1); 1162 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1163 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1164 if ((status0 & (SELDI|SELDO)) != 0) { 1165 u_int simode0; 1166 1167 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1168 simode0 = ahd_inb(ahd, SIMODE0); 1169 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1170 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1171 } 1172 scbid = ahd_get_scbptr(ahd); 1173 scb = ahd_lookup_scb(ahd, scbid); 1174 if (scb != NULL 1175 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1176 scb = NULL; 1177 1178 /* Make sure the sequencer is in a safe location. */ 1179 ahd_clear_critical_section(ahd); 1180 1181 if ((status0 & IOERR) != 0) { 1182 u_int now_lvd; 1183 1184 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1185 printf("%s: Transceiver State Has Changed to %s mode\n", 1186 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1187 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1188 /* 1189 * A change in I/O mode is equivalent to a bus reset. 1190 */ 1191 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1192 ahd_pause(ahd); 1193 ahd_setup_iocell_workaround(ahd); 1194 ahd_unpause(ahd); 1195 } else if ((status0 & OVERRUN) != 0) { 1196 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1197 ahd_name(ahd)); 1198 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1199 } else if ((status & SCSIRSTI) != 0) { 1200 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1201 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1202 } else if ((status & SCSIPERR) != 0) { 1203 ahd_handle_transmission_error(ahd); 1204 } else if (lqostat0 != 0) { 1205 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1206 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1207 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1208 ahd_outb(ahd, CLRLQOINT1, 0); 1209 } 1210 } else if ((status & SELTO) != 0) { 1211 u_int scbid; 1212 1213 /* Stop the selection */ 1214 ahd_outb(ahd, SCSISEQ0, 0); 1215 1216 /* No more pending messages */ 1217 ahd_clear_msg_state(ahd); 1218 1219 /* Clear interrupt state */ 1220 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1221 1222 /* 1223 * Although the driver does not care about the 1224 * 'Selection in Progress' status bit, the busy 1225 * LED does. SELINGO is only cleared by a sucessfull 1226 * selection, so we must manually clear it to insure 1227 * the LED turns off just incase no future successful 1228 * selections occur (e.g. no devices on the bus). 1229 */ 1230 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1231 1232 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1233 scb = ahd_lookup_scb(ahd, scbid); 1234 if (scb == NULL) { 1235 printf("%s: ahd_intr - referenced scb not " 1236 "valid during SELTO scb(0x%x)\n", 1237 ahd_name(ahd), scbid); 1238 ahd_dump_card_state(ahd); 1239 } else { 1240 struct ahd_devinfo devinfo; 1241 #ifdef AHD_DEBUG 1242 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1243 ahd_print_path(ahd, scb); 1244 printf("Saw Selection Timeout for SCB 0x%x\n", 1245 scbid); 1246 } 1247 #endif 1248 /* 1249 * Force a renegotiation with this target just in 1250 * case the cable was pulled and will later be 1251 * re-attached. The target may forget its negotiation 1252 * settings with us should it attempt to reselect 1253 * during the interruption. The target will not issue 1254 * a unit attention in this case, so we must always 1255 * renegotiate. 1256 */ 1257 ahd_scb_devinfo(ahd, &devinfo, scb); 1258 ahd_force_renegotiation(ahd, &devinfo); 1259 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1260 ahd_freeze_devq(ahd, scb); 1261 } 1262 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1263 ahd_iocell_first_selection(ahd); 1264 ahd_unpause(ahd); 1265 } else if ((status0 & (SELDI|SELDO)) != 0) { 1266 ahd_iocell_first_selection(ahd); 1267 ahd_unpause(ahd); 1268 } else if (status3 != 0) { 1269 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1270 ahd_name(ahd), status3); 1271 ahd_outb(ahd, CLRSINT3, status3); 1272 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1273 ahd_handle_lqiphase_error(ahd, lqistat1); 1274 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1275 /* 1276 * This status can be delayed during some 1277 * streaming operations. The SCSIPHASE 1278 * handler has already dealt with this case 1279 * so just clear the error. 1280 */ 1281 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1282 } else if ((status & BUSFREE) != 0) { 1283 u_int lqostat1; 1284 int restart; 1285 int clear_fifo; 1286 int packetized; 1287 u_int mode; 1288 1289 /* 1290 * Clear our selection hardware as soon as possible. 1291 * We may have an entry in the waiting Q for this target, 1292 * that is affected by this busfree and we don't want to 1293 * go about selecting the target while we handle the event. 1294 */ 1295 ahd_outb(ahd, SCSISEQ0, 0); 1296 1297 /* 1298 * Determine what we were up to at the time of 1299 * the busfree. 1300 */ 1301 mode = AHD_MODE_SCSI; 1302 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1303 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1304 switch (busfreetime) { 1305 case BUSFREE_DFF0: 1306 case BUSFREE_DFF1: 1307 { 1308 u_int scbid; 1309 struct scb *scb; 1310 1311 mode = busfreetime == BUSFREE_DFF0 1312 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1313 ahd_set_modes(ahd, mode, mode); 1314 scbid = ahd_get_scbptr(ahd); 1315 scb = ahd_lookup_scb(ahd, scbid); 1316 if (scb == NULL) { 1317 printf("%s: Invalid SCB in DFF%d " 1318 "during unexpected busfree\n", 1319 ahd_name(ahd), mode); 1320 packetized = 0; 1321 } else 1322 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1323 clear_fifo = 1; 1324 break; 1325 } 1326 case BUSFREE_LQO: 1327 clear_fifo = 0; 1328 packetized = 1; 1329 break; 1330 default: 1331 clear_fifo = 0; 1332 packetized = (lqostat1 & LQOBUSFREE) != 0; 1333 if (!packetized 1334 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1335 packetized = 1; 1336 break; 1337 } 1338 1339 #ifdef AHD_DEBUG 1340 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1341 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1342 busfreetime); 1343 #endif 1344 /* 1345 * Busfrees that occur in non-packetized phases are 1346 * handled by the nonpkt_busfree handler. 1347 */ 1348 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1349 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1350 } else { 1351 packetized = 0; 1352 restart = ahd_handle_nonpkt_busfree(ahd); 1353 } 1354 /* 1355 * Clear the busfree interrupt status. The setting of 1356 * the interrupt is a pulse, so in a perfect world, we 1357 * would not need to muck with the ENBUSFREE logic. This 1358 * would ensure that if the bus moves on to another 1359 * connection, busfree protection is still in force. If 1360 * BUSFREEREV is broken, however, we must manually clear 1361 * the ENBUSFREE if the busfree occurred during a non-pack 1362 * connection so that we don't get false positives during 1363 * future, packetized, connections. 1364 */ 1365 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1366 if (packetized == 0 1367 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1368 ahd_outb(ahd, SIMODE1, 1369 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1370 1371 if (clear_fifo) 1372 ahd_clear_fifo(ahd, mode); 1373 1374 ahd_clear_msg_state(ahd); 1375 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1376 if (restart) { 1377 ahd_restart(ahd); 1378 } else { 1379 ahd_unpause(ahd); 1380 } 1381 } else { 1382 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1383 ahd_name(ahd), status); 1384 ahd_dump_card_state(ahd); 1385 ahd_clear_intstat(ahd); 1386 ahd_unpause(ahd); 1387 } 1388 } 1389 1390 static void 1391 ahd_handle_transmission_error(struct ahd_softc *ahd) 1392 { 1393 struct scb *scb; 1394 u_int scbid; 1395 u_int lqistat1; 1396 u_int lqistat2; 1397 u_int msg_out; 1398 u_int curphase; 1399 u_int lastphase; 1400 u_int perrdiag; 1401 u_int cur_col; 1402 int silent; 1403 1404 scb = NULL; 1405 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1406 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1407 lqistat2 = ahd_inb(ahd, LQISTAT2); 1408 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1409 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1410 u_int lqistate; 1411 1412 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1413 lqistate = ahd_inb(ahd, LQISTATE); 1414 if ((lqistate >= 0x1E && lqistate <= 0x24) 1415 || (lqistate == 0x29)) { 1416 #ifdef AHD_DEBUG 1417 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1418 printf("%s: NLQCRC found via LQISTATE\n", 1419 ahd_name(ahd)); 1420 } 1421 #endif 1422 lqistat1 |= LQICRCI_NLQ; 1423 } 1424 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1425 } 1426 1427 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1428 lastphase = ahd_inb(ahd, LASTPHASE); 1429 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1430 perrdiag = ahd_inb(ahd, PERRDIAG); 1431 msg_out = MSG_INITIATOR_DET_ERR; 1432 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1433 1434 /* 1435 * Try to find the SCB associated with this error. 1436 */ 1437 silent = FALSE; 1438 if (lqistat1 == 0 1439 || (lqistat1 & LQICRCI_NLQ) != 0) { 1440 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1441 ahd_set_active_fifo(ahd); 1442 scbid = ahd_get_scbptr(ahd); 1443 scb = ahd_lookup_scb(ahd, scbid); 1444 if (scb != NULL && SCB_IS_SILENT(scb)) 1445 silent = TRUE; 1446 } 1447 1448 cur_col = 0; 1449 if (silent == FALSE) { 1450 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1451 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1452 ahd_lastphase_print(lastphase, &cur_col, 50); 1453 ahd_scsisigi_print(curphase, &cur_col, 50); 1454 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1455 printf("\n"); 1456 ahd_dump_card_state(ahd); 1457 } 1458 1459 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1460 if (silent == FALSE) { 1461 printf("%s: Gross protocol error during incoming " 1462 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1463 ahd_name(ahd), lqistat1); 1464 } 1465 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1466 return; 1467 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1468 /* 1469 * A CRC error has been detected on an incoming LQ. 1470 * The bus is currently hung on the last ACK. 1471 * Hit LQIRETRY to release the last ack, and 1472 * wait for the sequencer to determine that ATNO 1473 * is asserted while in message out to take us 1474 * to our host message loop. No NONPACKREQ or 1475 * LQIPHASE type errors will occur in this 1476 * scenario. After this first LQIRETRY, the LQI 1477 * manager will be in ISELO where it will 1478 * happily sit until another packet phase begins. 1479 * Unexpected bus free detection is enabled 1480 * through any phases that occur after we release 1481 * this last ack until the LQI manager sees a 1482 * packet phase. This implies we may have to 1483 * ignore a perfectly valid "unexected busfree" 1484 * after our "initiator detected error" message is 1485 * sent. A busfree is the expected response after 1486 * we tell the target that it's L_Q was corrupted. 1487 * (SPI4R09 10.7.3.3.3) 1488 */ 1489 ahd_outb(ahd, LQCTL2, LQIRETRY); 1490 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1491 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1492 /* 1493 * We detected a CRC error in a NON-LQ packet. 1494 * The hardware has varying behavior in this situation 1495 * depending on whether this packet was part of a 1496 * stream or not. 1497 * 1498 * PKT by PKT mode: 1499 * The hardware has already acked the complete packet. 1500 * If the target honors our outstanding ATN condition, 1501 * we should be (or soon will be) in MSGOUT phase. 1502 * This will trigger the LQIPHASE_LQ status bit as the 1503 * hardware was expecting another LQ. Unexpected 1504 * busfree detection is enabled. Once LQIPHASE_LQ is 1505 * true (first entry into host message loop is much 1506 * the same), we must clear LQIPHASE_LQ and hit 1507 * LQIRETRY so the hardware is ready to handle 1508 * a future LQ. NONPACKREQ will not be asserted again 1509 * once we hit LQIRETRY until another packet is 1510 * processed. The target may either go busfree 1511 * or start another packet in response to our message. 1512 * 1513 * Read Streaming P0 asserted: 1514 * If we raise ATN and the target completes the entire 1515 * stream (P0 asserted during the last packet), the 1516 * hardware will ack all data and return to the ISTART 1517 * state. When the target reponds to our ATN condition, 1518 * LQIPHASE_LQ will be asserted. We should respond to 1519 * this with an LQIRETRY to prepare for any future 1520 * packets. NONPACKREQ will not be asserted again 1521 * once we hit LQIRETRY until another packet is 1522 * processed. The target may either go busfree or 1523 * start another packet in response to our message. 1524 * Busfree detection is enabled. 1525 * 1526 * Read Streaming P0 not asserted: 1527 * If we raise ATN and the target transitions to 1528 * MSGOUT in or after a packet where P0 is not 1529 * asserted, the hardware will assert LQIPHASE_NLQ. 1530 * We should respond to the LQIPHASE_NLQ with an 1531 * LQIRETRY. Should the target stay in a non-pkt 1532 * phase after we send our message, the hardware 1533 * will assert LQIPHASE_LQ. Recovery is then just as 1534 * listed above for the read streaming with P0 asserted. 1535 * Busfree detection is enabled. 1536 */ 1537 if (silent == FALSE) 1538 printf("LQICRC_NLQ\n"); 1539 if (scb == NULL) { 1540 printf("%s: No SCB valid for LQICRC_NLQ. " 1541 "Resetting bus\n", ahd_name(ahd)); 1542 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1543 return; 1544 } 1545 } else if ((lqistat1 & LQIBADLQI) != 0) { 1546 printf("Need to handle BADLQI!\n"); 1547 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1548 return; 1549 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1550 if ((curphase & ~P_DATAIN_DT) != 0) { 1551 /* Ack the byte. So we can continue. */ 1552 if (silent == FALSE) 1553 printf("Acking %s to clear perror\n", 1554 ahd_lookup_phase_entry(curphase)->phasemsg); 1555 ahd_inb(ahd, SCSIDAT); 1556 } 1557 1558 if (curphase == P_MESGIN) 1559 msg_out = MSG_PARITY_ERROR; 1560 } 1561 1562 /* 1563 * We've set the hardware to assert ATN if we 1564 * get a parity error on "in" phases, so all we 1565 * need to do is stuff the message buffer with 1566 * the appropriate message. "In" phases have set 1567 * mesg_out to something other than MSG_NOP. 1568 */ 1569 ahd->send_msg_perror = msg_out; 1570 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1571 scb->flags |= SCB_TRANSMISSION_ERROR; 1572 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1573 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1574 ahd_unpause(ahd); 1575 } 1576 1577 static void 1578 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1579 { 1580 /* 1581 * Clear the sources of the interrupts. 1582 */ 1583 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1584 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1585 1586 /* 1587 * If the "illegal" phase changes were in response 1588 * to our ATN to flag a CRC error, AND we ended up 1589 * on packet boundaries, clear the error, restart the 1590 * LQI manager as appropriate, and go on our merry 1591 * way toward sending the message. Otherwise, reset 1592 * the bus to clear the error. 1593 */ 1594 ahd_set_active_fifo(ahd); 1595 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1596 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1597 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1598 printf("LQIRETRY for LQIPHASE_LQ\n"); 1599 ahd_outb(ahd, LQCTL2, LQIRETRY); 1600 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1601 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1602 ahd_outb(ahd, LQCTL2, LQIRETRY); 1603 } else 1604 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1605 ahd_dump_card_state(ahd); 1606 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1607 ahd_unpause(ahd); 1608 } else { 1609 printf("Reseting Channel for LQI Phase error\n"); 1610 ahd_dump_card_state(ahd); 1611 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1612 } 1613 } 1614 1615 /* 1616 * Packetized unexpected or expected busfree. 1617 * Entered in mode based on busfreetime. 1618 */ 1619 static int 1620 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1621 { 1622 u_int lqostat1; 1623 1624 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1625 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1626 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1627 if ((lqostat1 & LQOBUSFREE) != 0) { 1628 struct scb *scb; 1629 u_int scbid; 1630 u_int saved_scbptr; 1631 u_int waiting_h; 1632 u_int waiting_t; 1633 u_int next; 1634 1635 if ((busfreetime & BUSFREE_LQO) == 0) 1636 printf("%s: Warning, BUSFREE time is 0x%x. " 1637 "Expected BUSFREE_LQO.\n", 1638 ahd_name(ahd), busfreetime); 1639 /* 1640 * The LQO manager detected an unexpected busfree 1641 * either: 1642 * 1643 * 1) During an outgoing LQ. 1644 * 2) After an outgoing LQ but before the first 1645 * REQ of the command packet. 1646 * 3) During an outgoing command packet. 1647 * 1648 * In all cases, CURRSCB is pointing to the 1649 * SCB that encountered the failure. Clean 1650 * up the queue, clear SELDO and LQOBUSFREE, 1651 * and allow the sequencer to restart the select 1652 * out at its lesure. 1653 */ 1654 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1655 scbid = ahd_inw(ahd, CURRSCB); 1656 scb = ahd_lookup_scb(ahd, scbid); 1657 if (scb == NULL) 1658 panic("SCB not valid during LQOBUSFREE"); 1659 /* 1660 * Clear the status. 1661 */ 1662 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1663 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1664 ahd_outb(ahd, CLRLQOINT1, 0); 1665 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1666 ahd_flush_device_writes(ahd); 1667 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1668 1669 /* 1670 * Return the LQO manager to its idle loop. It will 1671 * not do this automatically if the busfree occurs 1672 * after the first REQ of either the LQ or command 1673 * packet or between the LQ and command packet. 1674 */ 1675 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1676 1677 /* 1678 * Update the waiting for selection queue so 1679 * we restart on the correct SCB. 1680 */ 1681 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1682 saved_scbptr = ahd_get_scbptr(ahd); 1683 if (waiting_h != scbid) { 1684 1685 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1686 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1687 if (waiting_t == waiting_h) { 1688 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1689 next = SCB_LIST_NULL; 1690 } else { 1691 ahd_set_scbptr(ahd, waiting_h); 1692 next = ahd_inw_scbram(ahd, SCB_NEXT2); 1693 } 1694 ahd_set_scbptr(ahd, scbid); 1695 ahd_outw(ahd, SCB_NEXT2, next); 1696 } 1697 ahd_set_scbptr(ahd, saved_scbptr); 1698 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1699 if (SCB_IS_SILENT(scb) == FALSE) { 1700 ahd_print_path(ahd, scb); 1701 printf("Probable outgoing LQ CRC error. " 1702 "Retrying command\n"); 1703 } 1704 scb->crc_retry_count++; 1705 } else { 1706 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1707 ahd_freeze_scb(scb); 1708 ahd_freeze_devq(ahd, scb); 1709 } 1710 /* Return unpausing the sequencer. */ 1711 return (0); 1712 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1713 /* 1714 * Ignore what are really parity errors that 1715 * occur on the last REQ of a free running 1716 * clock prior to going busfree. Some drives 1717 * do not properly active negate just before 1718 * going busfree resulting in a parity glitch. 1719 */ 1720 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1721 #ifdef AHD_DEBUG 1722 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1723 printf("%s: Parity on last REQ detected " 1724 "during busfree phase.\n", 1725 ahd_name(ahd)); 1726 #endif 1727 /* Return unpausing the sequencer. */ 1728 return (0); 1729 } 1730 if (ahd->src_mode != AHD_MODE_SCSI) { 1731 u_int scbid; 1732 struct scb *scb; 1733 1734 scbid = ahd_get_scbptr(ahd); 1735 scb = ahd_lookup_scb(ahd, scbid); 1736 ahd_print_path(ahd, scb); 1737 printf("Unexpected PKT busfree condition\n"); 1738 ahd_dump_card_state(ahd); 1739 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1740 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1741 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1742 1743 /* Return restarting the sequencer. */ 1744 return (1); 1745 } 1746 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1747 ahd_dump_card_state(ahd); 1748 /* Restart the sequencer. */ 1749 return (1); 1750 } 1751 1752 /* 1753 * Non-packetized unexpected or expected busfree. 1754 */ 1755 static int 1756 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1757 { 1758 struct ahd_devinfo devinfo; 1759 struct scb *scb; 1760 u_int lastphase; 1761 u_int saved_scsiid; 1762 u_int saved_lun; 1763 u_int target; 1764 u_int initiator_role_id; 1765 u_int scbid; 1766 u_int ppr_busfree; 1767 int printerror; 1768 1769 /* 1770 * Look at what phase we were last in. If its message out, 1771 * chances are pretty good that the busfree was in response 1772 * to one of our abort requests. 1773 */ 1774 lastphase = ahd_inb(ahd, LASTPHASE); 1775 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1776 saved_lun = ahd_inb(ahd, SAVED_LUN); 1777 target = SCSIID_TARGET(ahd, saved_scsiid); 1778 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1779 ahd_compile_devinfo(&devinfo, initiator_role_id, 1780 target, saved_lun, 'A', ROLE_INITIATOR); 1781 printerror = 1; 1782 1783 scbid = ahd_get_scbptr(ahd); 1784 scb = ahd_lookup_scb(ahd, scbid); 1785 if (scb != NULL 1786 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1787 scb = NULL; 1788 1789 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1790 if (lastphase == P_MESGOUT) { 1791 u_int tag; 1792 1793 tag = SCB_LIST_NULL; 1794 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1795 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1796 int found; 1797 int sent_msg; 1798 1799 if (scb == NULL) { 1800 ahd_print_devinfo(ahd, &devinfo); 1801 printf("Abort for unidentified " 1802 "connection completed.\n"); 1803 /* restart the sequencer. */ 1804 return (1); 1805 } 1806 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1807 ahd_print_path(ahd, scb); 1808 printf("SCB %d - Abort%s Completed.\n", 1809 SCB_GET_TAG(scb), 1810 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1811 1812 if (sent_msg == MSG_ABORT_TAG) 1813 tag = SCB_GET_TAG(scb); 1814 1815 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1816 /* 1817 * This abort is in response to an 1818 * unexpected switch to command phase 1819 * for a packetized connection. Since 1820 * the identify message was never sent, 1821 * "saved lun" is 0. We really want to 1822 * abort only the SCB that encountered 1823 * this error, which could have a different 1824 * lun. The SCB will be retried so the OS 1825 * will see the UA after renegotiating to 1826 * packetized. 1827 */ 1828 tag = SCB_GET_TAG(scb); 1829 saved_lun = scb->hscb->lun; 1830 } 1831 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1832 tag, ROLE_INITIATOR, 1833 CAM_REQ_ABORTED); 1834 printf("found == 0x%x\n", found); 1835 printerror = 0; 1836 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1837 MSG_BUS_DEV_RESET, TRUE)) { 1838 #ifdef __FreeBSD__ 1839 /* 1840 * Don't mark the user's request for this BDR 1841 * as completing with CAM_BDR_SENT. CAM3 1842 * specifies CAM_REQ_CMP. 1843 */ 1844 if (scb != NULL 1845 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1846 && ahd_match_scb(ahd, scb, target, 'A', 1847 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1848 ROLE_INITIATOR)) 1849 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1850 #endif 1851 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1852 CAM_BDR_SENT, "Bus Device Reset", 1853 /*verbose_level*/0); 1854 printerror = 0; 1855 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1856 && ppr_busfree == 0) { 1857 struct ahd_initiator_tinfo *tinfo; 1858 struct ahd_tmode_tstate *tstate; 1859 1860 /* 1861 * PPR Rejected. Try non-ppr negotiation 1862 * and retry command. 1863 */ 1864 #ifdef AHD_DEBUG 1865 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1866 printf("PPR negotiation rejected busfree.\n"); 1867 #endif 1868 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1869 devinfo.our_scsiid, 1870 devinfo.target, &tstate); 1871 tinfo->curr.transport_version = 2; 1872 tinfo->goal.transport_version = 2; 1873 tinfo->goal.ppr_options = 0; 1874 ahd_qinfifo_requeue_tail(ahd, scb); 1875 printerror = 0; 1876 } else if ((ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1877 || ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)) 1878 && ppr_busfree == 0) { 1879 /* 1880 * Negotiation Rejected. Go-async and 1881 * retry command. 1882 */ 1883 #ifdef AHD_DEBUG 1884 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1885 printf("Negotiation rejected busfree.\n"); 1886 #endif 1887 ahd_set_width(ahd, &devinfo, 1888 MSG_EXT_WDTR_BUS_8_BIT, 1889 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1890 /*paused*/TRUE); 1891 ahd_set_syncrate(ahd, &devinfo, 1892 /*period*/0, /*offset*/0, 1893 /*ppr_options*/0, 1894 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1895 /*paused*/TRUE); 1896 ahd_qinfifo_requeue_tail(ahd, scb); 1897 printerror = 0; 1898 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1899 && ahd_sent_msg(ahd, AHDMSG_1B, 1900 MSG_INITIATOR_DET_ERR, TRUE)) { 1901 1902 #ifdef AHD_DEBUG 1903 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1904 printf("Expected IDE Busfree\n"); 1905 #endif 1906 printerror = 0; 1907 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1908 && ahd_sent_msg(ahd, AHDMSG_1B, 1909 MSG_MESSAGE_REJECT, TRUE)) { 1910 1911 #ifdef AHD_DEBUG 1912 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1913 printf("Expected QAS Reject Busfree\n"); 1914 #endif 1915 printerror = 0; 1916 } 1917 } 1918 1919 /* 1920 * The busfree required flag is honored at the end of 1921 * the message phases. We check it last in case we 1922 * had to send some other message that caused a busfree. 1923 */ 1924 if (printerror != 0 1925 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1926 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1927 1928 ahd_freeze_devq(ahd, scb); 1929 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1930 ahd_freeze_scb(scb); 1931 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1932 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1933 SCB_GET_CHANNEL(ahd, scb), 1934 SCB_GET_LUN(scb), SCB_LIST_NULL, 1935 ROLE_INITIATOR, CAM_REQ_ABORTED); 1936 } else { 1937 #ifdef AHD_DEBUG 1938 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1939 printf("PPR Negotiation Busfree.\n"); 1940 #endif 1941 ahd_done(ahd, scb); 1942 } 1943 printerror = 0; 1944 } 1945 if (printerror != 0) { 1946 int aborted; 1947 1948 aborted = 0; 1949 if (scb != NULL) { 1950 u_int tag; 1951 1952 if ((scb->hscb->control & TAG_ENB) != 0) 1953 tag = SCB_GET_TAG(scb); 1954 else 1955 tag = SCB_LIST_NULL; 1956 ahd_print_path(ahd, scb); 1957 aborted = ahd_abort_scbs(ahd, target, 'A', 1958 SCB_GET_LUN(scb), tag, 1959 ROLE_INITIATOR, 1960 CAM_UNEXP_BUSFREE); 1961 } else { 1962 /* 1963 * We had not fully identified this connection, 1964 * so we cannot abort anything. 1965 */ 1966 printf("%s: ", ahd_name(ahd)); 1967 } 1968 if (lastphase != P_BUSFREE) 1969 ahd_force_renegotiation(ahd, &devinfo); 1970 printf("Unexpected busfree %s, %d SCBs aborted, " 1971 "PRGMCNT == 0x%x\n", 1972 ahd_lookup_phase_entry(lastphase)->phasemsg, 1973 aborted, 1974 ahd_inb(ahd, PRGMCNT) 1975 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 1976 ahd_dump_card_state(ahd); 1977 } 1978 /* Always restart the sequencer. */ 1979 return (1); 1980 } 1981 1982 static void 1983 ahd_handle_proto_violation(struct ahd_softc *ahd) 1984 { 1985 struct ahd_devinfo devinfo; 1986 struct scb *scb; 1987 u_int scbid; 1988 u_int seq_flags; 1989 u_int curphase; 1990 u_int lastphase; 1991 int found; 1992 1993 ahd_fetch_devinfo(ahd, &devinfo); 1994 scbid = ahd_get_scbptr(ahd); 1995 scb = ahd_lookup_scb(ahd, scbid); 1996 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 1997 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1998 lastphase = ahd_inb(ahd, LASTPHASE); 1999 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2000 2001 /* 2002 * The reconnecting target either did not send an 2003 * identify message, or did, but we didn't find an SCB 2004 * to match. 2005 */ 2006 ahd_print_devinfo(ahd, &devinfo); 2007 printf("Target did not send an IDENTIFY message. " 2008 "LASTPHASE = 0x%x.\n", lastphase); 2009 scb = NULL; 2010 } else if (scb == NULL) { 2011 /* 2012 * We don't seem to have an SCB active for this 2013 * transaction. Print an error and reset the bus. 2014 */ 2015 ahd_print_devinfo(ahd, &devinfo); 2016 printf("No SCB found during protocol violation\n"); 2017 goto proto_violation_reset; 2018 } else { 2019 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2020 if ((seq_flags & NO_CDB_SENT) != 0) { 2021 ahd_print_path(ahd, scb); 2022 printf("No or incomplete CDB sent to device.\n"); 2023 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2024 & STATUS_RCVD) == 0) { 2025 /* 2026 * The target never bothered to provide status to 2027 * us prior to completing the command. Since we don't 2028 * know the disposition of this command, we must attempt 2029 * to abort it. Assert ATN and prepare to send an abort 2030 * message. 2031 */ 2032 ahd_print_path(ahd, scb); 2033 printf("Completed command without status.\n"); 2034 } else { 2035 ahd_print_path(ahd, scb); 2036 printf("Unknown protocol violation.\n"); 2037 ahd_dump_card_state(ahd); 2038 } 2039 } 2040 if ((lastphase & ~P_DATAIN_DT) == 0 2041 || lastphase == P_COMMAND) { 2042 proto_violation_reset: 2043 /* 2044 * Target either went directly to data 2045 * phase or didn't respond to our ATN. 2046 * The only safe thing to do is to blow 2047 * it away with a bus reset. 2048 */ 2049 found = ahd_reset_channel(ahd, 'A', TRUE); 2050 printf("%s: Issued Channel %c Bus Reset. " 2051 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2052 } else { 2053 /* 2054 * Leave the selection hardware off in case 2055 * this abort attempt will affect yet to 2056 * be sent commands. 2057 */ 2058 ahd_outb(ahd, SCSISEQ0, 2059 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2060 ahd_assert_atn(ahd); 2061 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2062 if (scb == NULL) { 2063 ahd_print_devinfo(ahd, &devinfo); 2064 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2065 ahd->msgout_len = 1; 2066 ahd->msgout_index = 0; 2067 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2068 } else { 2069 ahd_print_path(ahd, scb); 2070 scb->flags |= SCB_ABORT; 2071 } 2072 printf("Protocol violation %s. Attempting to abort.\n", 2073 ahd_lookup_phase_entry(curphase)->phasemsg); 2074 } 2075 } 2076 2077 /* 2078 * Force renegotiation to occur the next time we initiate 2079 * a command to the current device. 2080 */ 2081 static void 2082 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2083 { 2084 struct ahd_initiator_tinfo *targ_info; 2085 struct ahd_tmode_tstate *tstate; 2086 2087 #ifdef AHD_DEBUG 2088 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2089 ahd_print_devinfo(ahd, devinfo); 2090 printf("Forcing renegotiation\n"); 2091 } 2092 #endif 2093 targ_info = ahd_fetch_transinfo(ahd, 2094 devinfo->channel, 2095 devinfo->our_scsiid, 2096 devinfo->target, 2097 &tstate); 2098 ahd_update_neg_request(ahd, devinfo, tstate, 2099 targ_info, AHD_NEG_IF_NON_ASYNC); 2100 } 2101 2102 #define AHD_MAX_STEPS 2000 2103 void 2104 ahd_clear_critical_section(struct ahd_softc *ahd) 2105 { 2106 ahd_mode_state saved_modes; 2107 int stepping; 2108 int steps; 2109 int first_instr; 2110 u_int simode0; 2111 u_int simode1; 2112 u_int simode3; 2113 u_int lqimode0; 2114 u_int lqimode1; 2115 u_int lqomode0; 2116 u_int lqomode1; 2117 2118 if (ahd->num_critical_sections == 0) 2119 return; 2120 2121 stepping = FALSE; 2122 steps = 0; 2123 first_instr = 0; 2124 simode0 = 0; 2125 simode1 = 0; 2126 simode3 = 0; 2127 lqimode0 = 0; 2128 lqimode1 = 0; 2129 lqomode0 = 0; 2130 lqomode1 = 0; 2131 saved_modes = ahd_save_modes(ahd); 2132 for (;;) { 2133 struct cs *cs; 2134 u_int seqaddr; 2135 u_int i; 2136 2137 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2138 seqaddr = ahd_inb(ahd, CURADDR) 2139 | (ahd_inb(ahd, CURADDR+1) << 8); 2140 2141 cs = ahd->critical_sections; 2142 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2143 2144 if (cs->begin < seqaddr && cs->end >= seqaddr) 2145 break; 2146 } 2147 2148 if (i == ahd->num_critical_sections) 2149 break; 2150 2151 if (steps > AHD_MAX_STEPS) { 2152 printf("%s: Infinite loop in critical section\n" 2153 "%s: First Instruction 0x%x now 0x%x\n", 2154 ahd_name(ahd), ahd_name(ahd), first_instr, 2155 seqaddr); 2156 ahd_dump_card_state(ahd); 2157 panic("critical section loop"); 2158 } 2159 2160 steps++; 2161 #ifdef AHD_DEBUG 2162 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2163 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2164 seqaddr); 2165 #endif 2166 if (stepping == FALSE) { 2167 2168 first_instr = seqaddr; 2169 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2170 simode0 = ahd_inb(ahd, SIMODE0); 2171 simode3 = ahd_inb(ahd, SIMODE3); 2172 lqimode0 = ahd_inb(ahd, LQIMODE0); 2173 lqimode1 = ahd_inb(ahd, LQIMODE1); 2174 lqomode0 = ahd_inb(ahd, LQOMODE0); 2175 lqomode1 = ahd_inb(ahd, LQOMODE1); 2176 ahd_outb(ahd, SIMODE0, 0); 2177 ahd_outb(ahd, SIMODE3, 0); 2178 ahd_outb(ahd, LQIMODE0, 0); 2179 ahd_outb(ahd, LQIMODE1, 0); 2180 ahd_outb(ahd, LQOMODE0, 0); 2181 ahd_outb(ahd, LQOMODE1, 0); 2182 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2183 simode1 = ahd_inb(ahd, SIMODE1); 2184 ahd_outb(ahd, SIMODE1, ENBUSFREE); 2185 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2186 stepping = TRUE; 2187 } 2188 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2189 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2190 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2191 ahd_outb(ahd, HCNTRL, ahd->unpause); 2192 do { 2193 ahd_delay(200); 2194 } while (!ahd_is_paused(ahd)); 2195 ahd_update_modes(ahd); 2196 } 2197 if (stepping) { 2198 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2199 ahd_outb(ahd, SIMODE0, simode0); 2200 ahd_outb(ahd, SIMODE3, simode3); 2201 ahd_outb(ahd, LQIMODE0, lqimode0); 2202 ahd_outb(ahd, LQIMODE1, lqimode1); 2203 ahd_outb(ahd, LQOMODE0, lqomode0); 2204 ahd_outb(ahd, LQOMODE1, lqomode1); 2205 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2206 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2207 ahd_outb(ahd, SIMODE1, simode1); 2208 } 2209 ahd_restore_modes(ahd, saved_modes); 2210 } 2211 2212 /* 2213 * Clear any pending interrupt status. 2214 */ 2215 void 2216 ahd_clear_intstat(struct ahd_softc *ahd) 2217 { 2218 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2219 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2220 /* Clear any interrupt conditions this may have caused */ 2221 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2222 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2223 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2224 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2225 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2226 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2227 |CLRLQOATNPKT|CLRLQOTCRC); 2228 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2229 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2230 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2231 ahd_outb(ahd, CLRLQOINT0, 0); 2232 ahd_outb(ahd, CLRLQOINT1, 0); 2233 } 2234 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2235 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2236 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2237 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2238 |CLRIOERR|CLROVERRUN); 2239 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2240 } 2241 2242 /**************************** Debugging Routines ******************************/ 2243 #ifdef AHD_DEBUG 2244 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2245 #endif 2246 void 2247 ahd_print_scb(struct scb *scb) 2248 { 2249 struct hardware_scb *hscb; 2250 int i; 2251 2252 hscb = scb->hscb; 2253 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2254 (void *)scb, 2255 hscb->control, 2256 hscb->scsiid, 2257 hscb->lun, 2258 hscb->cdb_len); 2259 printf("Shared Data: "); 2260 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2261 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2262 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2263 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2264 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2265 ahd_le32toh(hscb->datacnt), 2266 ahd_le32toh(hscb->sgptr), 2267 SCB_GET_TAG(scb)); 2268 ahd_dump_sglist(scb); 2269 } 2270 2271 void 2272 ahd_dump_sglist(struct scb *scb) 2273 { 2274 int i; 2275 2276 if (scb->sg_count > 0) { 2277 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2278 struct ahd_dma64_seg *sg_list; 2279 2280 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2281 for (i = 0; i < scb->sg_count; i++) { 2282 uint64_t addr; 2283 uint32_t len; 2284 2285 addr = ahd_le64toh(sg_list[i].addr); 2286 len = ahd_le32toh(sg_list[i].len); 2287 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2288 i, 2289 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2290 (uint32_t)(addr & 0xFFFFFFFF), 2291 sg_list[i].len & AHD_SG_LEN_MASK, 2292 (sg_list[i].len & AHD_DMA_LAST_SEG) 2293 ? " Last" : ""); 2294 } 2295 } else { 2296 struct ahd_dma_seg *sg_list; 2297 2298 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2299 for (i = 0; i < scb->sg_count; i++) { 2300 uint32_t len; 2301 2302 len = ahd_le32toh(sg_list[i].len); 2303 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2304 i, 2305 (len >> 24) & SG_HIGH_ADDR_BITS, 2306 ahd_le32toh(sg_list[i].addr), 2307 len & AHD_SG_LEN_MASK, 2308 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2309 } 2310 } 2311 } 2312 } 2313 2314 /************************* Transfer Negotiation *******************************/ 2315 /* 2316 * Allocate per target mode instance (ID we respond to as a target) 2317 * transfer negotiation data structures. 2318 */ 2319 static struct ahd_tmode_tstate * 2320 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2321 { 2322 struct ahd_tmode_tstate *master_tstate; 2323 struct ahd_tmode_tstate *tstate; 2324 int i; 2325 2326 master_tstate = ahd->enabled_targets[ahd->our_id]; 2327 if (ahd->enabled_targets[scsi_id] != NULL 2328 && ahd->enabled_targets[scsi_id] != master_tstate) 2329 panic("%s: ahd_alloc_tstate - Target already allocated", 2330 ahd_name(ahd)); 2331 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 2332 if (tstate == NULL) 2333 return (NULL); 2334 2335 /* 2336 * If we have allocated a master tstate, copy user settings from 2337 * the master tstate (taken from SRAM or the EEPROM) for this 2338 * channel, but reset our current and goal settings to async/narrow 2339 * until an initiator talks to us. 2340 */ 2341 if (master_tstate != NULL) { 2342 memcpy(tstate, master_tstate, sizeof(*tstate)); 2343 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2344 for (i = 0; i < 16; i++) { 2345 memset(&tstate->transinfo[i].curr, 0, 2346 sizeof(tstate->transinfo[i].curr)); 2347 memset(&tstate->transinfo[i].goal, 0, 2348 sizeof(tstate->transinfo[i].goal)); 2349 } 2350 } else 2351 memset(tstate, 0, sizeof(*tstate)); 2352 ahd->enabled_targets[scsi_id] = tstate; 2353 return (tstate); 2354 } 2355 2356 #ifdef AHD_TARGET_MODE 2357 /* 2358 * Free per target mode instance (ID we respond to as a target) 2359 * transfer negotiation data structures. 2360 */ 2361 static void 2362 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2363 { 2364 struct ahd_tmode_tstate *tstate; 2365 2366 /* 2367 * Don't clean up our "master" tstate. 2368 * It has our default user settings. 2369 */ 2370 if (scsi_id == ahd->our_id 2371 && force == FALSE) 2372 return; 2373 2374 tstate = ahd->enabled_targets[scsi_id]; 2375 if (tstate != NULL) 2376 free(tstate, M_DEVBUF); 2377 ahd->enabled_targets[scsi_id] = NULL; 2378 } 2379 #endif 2380 2381 /* 2382 * Called when we have an active connection to a target on the bus, 2383 * this function finds the nearest period to the input period limited 2384 * by the capabilities of the bus connectivity of and sync settings for 2385 * the target. 2386 */ 2387 void 2388 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2389 struct ahd_initiator_tinfo *tinfo, 2390 u_int *period, u_int *ppr_options, role_t role) 2391 { 2392 struct ahd_transinfo *transinfo; 2393 u_int maxsync; 2394 2395 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2396 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2397 maxsync = AHD_SYNCRATE_PACED; 2398 } else { 2399 maxsync = AHD_SYNCRATE_ULTRA; 2400 /* Can't do DT related options on an SE bus */ 2401 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2402 } 2403 /* 2404 * Never allow a value higher than our current goal 2405 * period otherwise we may allow a target initiated 2406 * negotiation to go above the limit as set by the 2407 * user. In the case of an initiator initiated 2408 * sync negotiation, we limit based on the user 2409 * setting. This allows the system to still accept 2410 * incoming negotiations even if target initiated 2411 * negotiation is not performed. 2412 */ 2413 if (role == ROLE_TARGET) 2414 transinfo = &tinfo->user; 2415 else 2416 transinfo = &tinfo->goal; 2417 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2418 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2419 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2420 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2421 } 2422 if (transinfo->period == 0) { 2423 *period = 0; 2424 *ppr_options = 0; 2425 } else { 2426 *period = MAX(*period, transinfo->period); 2427 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2428 } 2429 } 2430 2431 /* 2432 * Look up the valid period to SCSIRATE conversion in our table. 2433 * Return the period and offset that should be sent to the target 2434 * if this was the beginning of an SDTR. 2435 */ 2436 void 2437 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2438 u_int *ppr_options, u_int maxsync) 2439 { 2440 if (*period < maxsync) 2441 *period = maxsync; 2442 2443 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2444 && *period > AHD_SYNCRATE_MIN_DT) 2445 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2446 2447 if (*period > AHD_SYNCRATE_MIN) 2448 *period = 0; 2449 2450 /* Honor PPR option conformance rules. */ 2451 if (*period > AHD_SYNCRATE_PACED) 2452 *ppr_options &= ~MSG_EXT_PPR_RTI; 2453 2454 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2455 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2456 2457 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2458 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2459 2460 /* Skip all PACED only entries if IU is not available */ 2461 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2462 && *period < AHD_SYNCRATE_DT) 2463 *period = AHD_SYNCRATE_DT; 2464 2465 /* Skip all DT only entries if DT is not available */ 2466 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2467 && *period < AHD_SYNCRATE_ULTRA2) 2468 *period = AHD_SYNCRATE_ULTRA2; 2469 } 2470 2471 /* 2472 * Truncate the given synchronous offset to a value the 2473 * current adapter type and syncrate are capable of. 2474 */ 2475 void 2476 ahd_validate_offset(struct ahd_softc *ahd, 2477 struct ahd_initiator_tinfo *tinfo, 2478 u_int period, u_int *offset, int wide, 2479 role_t role) 2480 { 2481 u_int maxoffset; 2482 2483 /* Limit offset to what we can do */ 2484 if (period == 0) 2485 maxoffset = 0; 2486 else if (period <= AHD_SYNCRATE_PACED) { 2487 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2488 maxoffset = MAX_OFFSET_PACED_BUG; 2489 else 2490 maxoffset = MAX_OFFSET_PACED; 2491 } else 2492 maxoffset = MAX_OFFSET_NON_PACED; 2493 *offset = MIN(*offset, maxoffset); 2494 if (tinfo != NULL) { 2495 if (role == ROLE_TARGET) 2496 *offset = MIN(*offset, tinfo->user.offset); 2497 else 2498 *offset = MIN(*offset, tinfo->goal.offset); 2499 } 2500 } 2501 2502 /* 2503 * Truncate the given transfer width parameter to a value the 2504 * current adapter type is capable of. 2505 */ 2506 void 2507 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2508 u_int *bus_width, role_t role) 2509 { 2510 switch (*bus_width) { 2511 default: 2512 if (ahd->features & AHD_WIDE) { 2513 /* Respond Wide */ 2514 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2515 break; 2516 } 2517 /* FALLTHROUGH */ 2518 case MSG_EXT_WDTR_BUS_8_BIT: 2519 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2520 break; 2521 } 2522 if (tinfo != NULL) { 2523 if (role == ROLE_TARGET) 2524 *bus_width = MIN(tinfo->user.width, *bus_width); 2525 else 2526 *bus_width = MIN(tinfo->goal.width, *bus_width); 2527 } 2528 } 2529 2530 /* 2531 * Update the bitmask of targets for which the controller should 2532 * negotiate with at the next convenient oportunity. This currently 2533 * means the next time we send the initial identify messages for 2534 * a new transaction. 2535 */ 2536 int 2537 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2538 struct ahd_tmode_tstate *tstate, 2539 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2540 { 2541 u_int auto_negotiate_orig; 2542 2543 auto_negotiate_orig = tstate->auto_negotiate; 2544 if (neg_type == AHD_NEG_ALWAYS) { 2545 /* 2546 * Force our "current" settings to be 2547 * unknown so that unless a bus reset 2548 * occurs the need to renegotiate is 2549 * recorded persistently. 2550 */ 2551 if ((ahd->features & AHD_WIDE) != 0) 2552 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2553 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2554 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2555 } 2556 if (tinfo->curr.period != tinfo->goal.period 2557 || tinfo->curr.width != tinfo->goal.width 2558 || tinfo->curr.offset != tinfo->goal.offset 2559 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2560 || (neg_type == AHD_NEG_IF_NON_ASYNC 2561 && (tinfo->goal.offset != 0 2562 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2563 || tinfo->goal.ppr_options != 0))) 2564 tstate->auto_negotiate |= devinfo->target_mask; 2565 else 2566 tstate->auto_negotiate &= ~devinfo->target_mask; 2567 2568 return (auto_negotiate_orig != tstate->auto_negotiate); 2569 } 2570 2571 /* 2572 * Update the user/goal/curr tables of synchronous negotiation 2573 * parameters as well as, in the case of a current or active update, 2574 * any data structures on the host controller. In the case of an 2575 * active update, the specified target is currently talking to us on 2576 * the bus, so the transfer parameter update must take effect 2577 * immediately. 2578 */ 2579 void 2580 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2581 u_int period, u_int offset, u_int ppr_options, 2582 u_int type, int paused) 2583 { 2584 struct ahd_initiator_tinfo *tinfo; 2585 struct ahd_tmode_tstate *tstate; 2586 u_int old_period; 2587 u_int old_offset; 2588 u_int old_ppr; 2589 int active; 2590 int update_needed; 2591 2592 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2593 update_needed = 0; 2594 2595 if (period == 0 || offset == 0) { 2596 period = 0; 2597 offset = 0; 2598 } 2599 2600 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2601 devinfo->target, &tstate); 2602 2603 if ((type & AHD_TRANS_USER) != 0) { 2604 tinfo->user.period = period; 2605 tinfo->user.offset = offset; 2606 tinfo->user.ppr_options = ppr_options; 2607 } 2608 2609 if ((type & AHD_TRANS_GOAL) != 0) { 2610 tinfo->goal.period = period; 2611 tinfo->goal.offset = offset; 2612 tinfo->goal.ppr_options = ppr_options; 2613 } 2614 2615 old_period = tinfo->curr.period; 2616 old_offset = tinfo->curr.offset; 2617 old_ppr = tinfo->curr.ppr_options; 2618 2619 if ((type & AHD_TRANS_CUR) != 0 2620 && (old_period != period 2621 || old_offset != offset 2622 || old_ppr != ppr_options)) { 2623 2624 update_needed++; 2625 2626 tinfo->curr.period = period; 2627 tinfo->curr.offset = offset; 2628 tinfo->curr.ppr_options = ppr_options; 2629 2630 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2631 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2632 2633 if (bootverbose) { 2634 if (offset != 0) { 2635 int options; 2636 2637 printf("%s: target %d synchronous with " 2638 "period = 0x%x, offset = 0x%x", 2639 ahd_name(ahd), devinfo->target, 2640 period, offset); 2641 options = 0; 2642 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 2643 printf("(RDSTRM"); 2644 options++; 2645 } 2646 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2647 printf("%s", options ? "|DT" : "(DT"); 2648 options++; 2649 } 2650 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2651 printf("%s", options ? "|IU" : "(IU"); 2652 options++; 2653 } 2654 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2655 printf("%s", options ? "|RTI" : "(RTI"); 2656 options++; 2657 } 2658 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2659 printf("%s", options ? "|QAS" : "(QAS"); 2660 options++; 2661 } 2662 if (options != 0) 2663 printf(")\n"); 2664 else 2665 printf("\n"); 2666 } else { 2667 printf("%s: target %d using " 2668 "asynchronous transfers%s\n", 2669 ahd_name(ahd), devinfo->target, 2670 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2671 ? "(QAS)" : ""); 2672 } 2673 } 2674 } 2675 /* 2676 * Always refresh the neg-table to handle the case of the 2677 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2678 * We will always renegotiate in that case if this is a 2679 * packetized request. Also manage the busfree expected flag 2680 * from this common routine so that we catch changes due to 2681 * WDTR or SDTR messages. 2682 */ 2683 if ((type & AHD_TRANS_CUR) != 0) { 2684 if (!paused) 2685 ahd_pause(ahd); 2686 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2687 if (!paused) 2688 ahd_unpause(ahd); 2689 if (ahd->msg_type != MSG_TYPE_NONE) { 2690 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2691 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2692 #ifdef AHD_DEBUG 2693 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2694 ahd_print_devinfo(ahd, devinfo); 2695 printf("Expecting IU Change busfree\n"); 2696 } 2697 #endif 2698 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2699 | MSG_FLAG_IU_REQ_CHANGED; 2700 } 2701 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2702 #ifdef AHD_DEBUG 2703 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2704 printf("PPR with IU_REQ outstanding\n"); 2705 #endif 2706 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2707 } 2708 } 2709 } 2710 2711 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2712 tinfo, AHD_NEG_TO_GOAL); 2713 2714 if (update_needed) 2715 ahd_update_xfer_mode(ahd, devinfo); 2716 ahd->sc_req = 0; 2717 2718 if (update_needed && active) 2719 ahd_update_pending_scbs(ahd); 2720 } 2721 2722 /* 2723 * Update the user/goal/curr tables of wide negotiation 2724 * parameters as well as, in the case of a current or active update, 2725 * any data structures on the host controller. In the case of an 2726 * active update, the specified target is currently talking to us on 2727 * the bus, so the transfer parameter update must take effect 2728 * immediately. 2729 */ 2730 void 2731 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2732 u_int width, u_int type, int paused) 2733 { 2734 struct ahd_initiator_tinfo *tinfo; 2735 struct ahd_tmode_tstate *tstate; 2736 u_int oldwidth; 2737 int active; 2738 int update_needed; 2739 2740 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2741 update_needed = 0; 2742 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2743 devinfo->target, &tstate); 2744 2745 if ((type & AHD_TRANS_USER) != 0) 2746 tinfo->user.width = width; 2747 2748 if ((type & AHD_TRANS_GOAL) != 0) 2749 tinfo->goal.width = width; 2750 2751 oldwidth = tinfo->curr.width; 2752 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2753 2754 update_needed++; 2755 2756 tinfo->curr.width = width; 2757 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2758 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2759 2760 if (bootverbose) { 2761 printf("%s: target %d using %dbit transfers\n", 2762 ahd_name(ahd), devinfo->target, 2763 8 * (0x01 << width)); 2764 } 2765 } 2766 2767 if ((type & AHD_TRANS_CUR) != 0) { 2768 if (!paused) 2769 ahd_pause(ahd); 2770 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2771 if (!paused) 2772 ahd_unpause(ahd); 2773 } 2774 2775 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2776 tinfo, AHD_NEG_TO_GOAL); 2777 if (update_needed && active) 2778 ahd_update_pending_scbs(ahd); 2779 2780 } 2781 2782 /* 2783 * Update the current state of tagged queuing for a given target. 2784 */ 2785 void 2786 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2787 ahd_queue_alg alg) 2788 { 2789 ahd_platform_set_tags(ahd, devinfo, alg); 2790 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2791 devinfo->lun, AC_TRANSFER_NEG, &alg); 2792 } 2793 2794 static void 2795 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2796 struct ahd_transinfo *tinfo) 2797 { 2798 ahd_mode_state saved_modes; 2799 u_int period; 2800 u_int ppr_opts; 2801 u_int con_opts; 2802 u_int offset; 2803 u_int saved_negoaddr; 2804 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2805 2806 saved_modes = ahd_save_modes(ahd); 2807 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2808 2809 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2810 ahd_outb(ahd, NEGOADDR, devinfo->target); 2811 period = tinfo->period; 2812 offset = tinfo->offset; 2813 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2814 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2815 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2816 con_opts = 0; 2817 if (period == 0) 2818 period = AHD_SYNCRATE_ASYNC; 2819 if (period == AHD_SYNCRATE_160) { 2820 2821 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2822 /* 2823 * When the SPI4 spec was finalized, PACE transfers 2824 * was not made a configurable option in the PPR 2825 * message. Instead it is assumed to be enabled for 2826 * any syncrate faster than 80MHz. Nevertheless, 2827 * Harpoon2A4 allows this to be configurable. 2828 * 2829 * Harpoon2A4 also assumes at most 2 data bytes per 2830 * negotiated REQ/ACK offset. Paced transfers take 2831 * 4, so we must adjust our offset. 2832 */ 2833 ppr_opts |= PPROPT_PACE; 2834 offset *= 2; 2835 2836 /* 2837 * Harpoon2A assumed that there would be a 2838 * fallback rate between 160MHz and 80Mhz, 2839 * so 7 is used as the period factor rather 2840 * than 8 for 160MHz. 2841 */ 2842 period = AHD_SYNCRATE_REVA_160; 2843 } 2844 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2845 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2846 ~AHD_PRECOMP_MASK; 2847 } else { 2848 /* 2849 * Precomp should be disabled for non-paced transfers. 2850 */ 2851 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2852 2853 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2854 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2855 /* 2856 * Slow down our CRC interval to be 2857 * compatible with devices that can't 2858 * handle a CRC at full speed. 2859 */ 2860 con_opts |= ENSLOWCRC; 2861 } 2862 } 2863 2864 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2865 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2866 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2867 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2868 2869 ahd_outb(ahd, NEGPERIOD, period); 2870 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2871 ahd_outb(ahd, NEGOFFSET, offset); 2872 2873 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2874 con_opts |= WIDEXFER; 2875 2876 /* 2877 * During packetized transfers, the target will 2878 * give us the oportunity to send command packets 2879 * without us asserting attention. 2880 */ 2881 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2882 con_opts |= ENAUTOATNO; 2883 ahd_outb(ahd, NEGCONOPTS, con_opts); 2884 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2885 ahd_restore_modes(ahd, saved_modes); 2886 } 2887 2888 /* 2889 * When the transfer settings for a connection change, setup for 2890 * negotiation in pending SCBs to effect the change as quickly as 2891 * possible. We also cancel any negotiations that are scheduled 2892 * for inflight SCBs that have not been started yet. 2893 */ 2894 static void 2895 ahd_update_pending_scbs(struct ahd_softc *ahd) 2896 { 2897 struct scb *pending_scb; 2898 int pending_scb_count; 2899 int i; 2900 int paused; 2901 u_int saved_scbptr; 2902 ahd_mode_state saved_modes; 2903 2904 /* 2905 * Traverse the pending SCB list and ensure that all of the 2906 * SCBs there have the proper settings. We can only safely 2907 * clear the negotiation required flag (setting requires the 2908 * execution queue to be modified) and this is only possible 2909 * if we are not already attempting to select out for this 2910 * SCB. For this reason, all callers only call this routine 2911 * if we are changing the negotiation settings for the currently 2912 * active transaction on the bus. 2913 */ 2914 pending_scb_count = 0; 2915 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2916 struct ahd_devinfo devinfo; 2917 struct hardware_scb *pending_hscb; 2918 struct ahd_initiator_tinfo *tinfo; 2919 struct ahd_tmode_tstate *tstate; 2920 2921 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2922 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2923 devinfo.our_scsiid, 2924 devinfo.target, &tstate); 2925 pending_hscb = pending_scb->hscb; 2926 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2927 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2928 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2929 pending_hscb->control &= ~MK_MESSAGE; 2930 } 2931 ahd_sync_scb(ahd, pending_scb, 2932 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2933 pending_scb_count++; 2934 } 2935 2936 if (pending_scb_count == 0) 2937 return; 2938 2939 if (ahd_is_paused(ahd)) { 2940 paused = 1; 2941 } else { 2942 paused = 0; 2943 ahd_pause(ahd); 2944 } 2945 2946 /* 2947 * Force the sequencer to reinitialize the selection for 2948 * the command at the head of the execution queue if it 2949 * has already been setup. The negotiation changes may 2950 * effect whether we select-out with ATN. 2951 */ 2952 saved_modes = ahd_save_modes(ahd); 2953 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2954 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2955 saved_scbptr = ahd_get_scbptr(ahd); 2956 /* Ensure that the hscbs down on the card match the new information */ 2957 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 2958 struct hardware_scb *pending_hscb; 2959 u_int control; 2960 u_int scb_tag; 2961 2962 ahd_set_scbptr(ahd, i); 2963 scb_tag = i; 2964 pending_scb = ahd_lookup_scb(ahd, scb_tag); 2965 if (pending_scb == NULL) 2966 continue; 2967 2968 pending_hscb = pending_scb->hscb; 2969 control = ahd_inb_scbram(ahd, SCB_CONTROL); 2970 control &= ~MK_MESSAGE; 2971 control |= pending_hscb->control & MK_MESSAGE; 2972 ahd_outb(ahd, SCB_CONTROL, control); 2973 } 2974 ahd_set_scbptr(ahd, saved_scbptr); 2975 ahd_restore_modes(ahd, saved_modes); 2976 2977 if (paused == 0) 2978 ahd_unpause(ahd); 2979 } 2980 2981 /**************************** Pathing Information *****************************/ 2982 static void 2983 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2984 { 2985 ahd_mode_state saved_modes; 2986 u_int saved_scsiid; 2987 role_t role; 2988 int our_id; 2989 2990 saved_modes = ahd_save_modes(ahd); 2991 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2992 2993 if (ahd_inb(ahd, SSTAT0) & TARGET) 2994 role = ROLE_TARGET; 2995 else 2996 role = ROLE_INITIATOR; 2997 2998 if (role == ROLE_TARGET 2999 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3000 /* We were selected, so pull our id from TARGIDIN */ 3001 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3002 } else if (role == ROLE_TARGET) 3003 our_id = ahd_inb(ahd, TOWNID); 3004 else 3005 our_id = ahd_inb(ahd, IOWNID); 3006 3007 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3008 ahd_compile_devinfo(devinfo, 3009 our_id, 3010 SCSIID_TARGET(ahd, saved_scsiid), 3011 ahd_inb(ahd, SAVED_LUN), 3012 SCSIID_CHANNEL(ahd, saved_scsiid), 3013 role); 3014 ahd_restore_modes(ahd, saved_modes); 3015 } 3016 3017 void 3018 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3019 { 3020 printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3021 devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3022 } 3023 3024 struct ahd_phase_table_entry* 3025 ahd_lookup_phase_entry(int phase) 3026 { 3027 struct ahd_phase_table_entry *entry; 3028 struct ahd_phase_table_entry *last_entry; 3029 3030 /* 3031 * num_phases doesn't include the default entry which 3032 * will be returned if the phase doesn't match. 3033 */ 3034 last_entry = &ahd_phase_table[num_phases]; 3035 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3036 if (phase == entry->phase) 3037 break; 3038 } 3039 return (entry); 3040 } 3041 3042 void 3043 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3044 u_int lun, char channel, role_t role) 3045 { 3046 devinfo->our_scsiid = our_id; 3047 devinfo->target = target; 3048 devinfo->lun = lun; 3049 devinfo->target_offset = target; 3050 devinfo->channel = channel; 3051 devinfo->role = role; 3052 if (channel == 'B') 3053 devinfo->target_offset += 8; 3054 devinfo->target_mask = (0x01 << devinfo->target_offset); 3055 } 3056 3057 static void 3058 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3059 struct scb *scb) 3060 { 3061 role_t role; 3062 int our_id; 3063 3064 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3065 role = ROLE_INITIATOR; 3066 if ((scb->hscb->control & TARGET_SCB) != 0) 3067 role = ROLE_TARGET; 3068 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3069 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3070 } 3071 3072 3073 /************************ Message Phase Processing ****************************/ 3074 /* 3075 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3076 * or enters the initial message out phase, we are interrupted. Fill our 3077 * outgoing message buffer with the appropriate message and beging handing 3078 * the message phase(s) manually. 3079 */ 3080 static void 3081 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3082 struct scb *scb) 3083 { 3084 /* 3085 * To facilitate adding multiple messages together, 3086 * each routine should increment the index and len 3087 * variables instead of setting them explicitly. 3088 */ 3089 ahd->msgout_index = 0; 3090 ahd->msgout_len = 0; 3091 3092 if (ahd_currently_packetized(ahd)) 3093 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3094 3095 if (ahd->send_msg_perror 3096 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3097 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3098 ahd->msgout_len++; 3099 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3100 #ifdef AHD_DEBUG 3101 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3102 printf("Setting up for Parity Error delivery\n"); 3103 #endif 3104 return; 3105 } else if (scb == NULL) { 3106 printf("%s: WARNING. No pending message for " 3107 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3108 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3109 ahd->msgout_len++; 3110 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3111 return; 3112 } 3113 3114 if ((scb->flags & SCB_DEVICE_RESET) == 0 3115 && (scb->flags & SCB_PACKETIZED) == 0 3116 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3117 u_int identify_msg; 3118 3119 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3120 if ((scb->hscb->control & DISCENB) != 0) 3121 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3122 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3123 ahd->msgout_len++; 3124 3125 if ((scb->hscb->control & TAG_ENB) != 0) { 3126 ahd->msgout_buf[ahd->msgout_index++] = 3127 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3128 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3129 ahd->msgout_len += 2; 3130 } 3131 } 3132 3133 if (scb->flags & SCB_DEVICE_RESET) { 3134 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3135 ahd->msgout_len++; 3136 ahd_print_path(ahd, scb); 3137 printf("Bus Device Reset Message Sent\n"); 3138 /* 3139 * Clear our selection hardware in advance of 3140 * the busfree. We may have an entry in the waiting 3141 * Q for this target, and we don't want to go about 3142 * selecting while we handle the busfree and blow it 3143 * away. 3144 */ 3145 ahd_outb(ahd, SCSISEQ0, 0); 3146 } else if ((scb->flags & SCB_ABORT) != 0) { 3147 3148 if ((scb->hscb->control & TAG_ENB) != 0) { 3149 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3150 } else { 3151 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3152 } 3153 ahd->msgout_len++; 3154 ahd_print_path(ahd, scb); 3155 printf("Abort%s Message Sent\n", 3156 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3157 /* 3158 * Clear our selection hardware in advance of 3159 * the busfree. We may have an entry in the waiting 3160 * Q for this target, and we don't want to go about 3161 * selecting while we handle the busfree and blow it 3162 * away. 3163 */ 3164 ahd_outb(ahd, SCSISEQ0, 0); 3165 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3166 ahd_build_transfer_msg(ahd, devinfo); 3167 /* 3168 * Clear our selection hardware in advance of potential 3169 * PPR IU status change busfree. We may have an entry in 3170 * the waiting Q for this target, and we don't want to go 3171 * about selecting while we handle the busfree and blow 3172 * it away. 3173 */ 3174 ahd_outb(ahd, SCSISEQ0, 0); 3175 } else { 3176 printf("ahd_intr: AWAITING_MSG for an SCB that " 3177 "does not have a waiting message\n"); 3178 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3179 devinfo->target_mask); 3180 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3181 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3182 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3183 scb->flags); 3184 } 3185 3186 /* 3187 * Clear the MK_MESSAGE flag from the SCB so we aren't 3188 * asked to send this message again. 3189 */ 3190 ahd_outb(ahd, SCB_CONTROL, 3191 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3192 scb->hscb->control &= ~MK_MESSAGE; 3193 ahd->msgout_index = 0; 3194 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3195 } 3196 3197 /* 3198 * Build an appropriate transfer negotiation message for the 3199 * currently active target. 3200 */ 3201 static void 3202 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3203 { 3204 /* 3205 * We need to initiate transfer negotiations. 3206 * If our current and goal settings are identical, 3207 * we want to renegotiate due to a check condition. 3208 */ 3209 struct ahd_initiator_tinfo *tinfo; 3210 struct ahd_tmode_tstate *tstate; 3211 int dowide; 3212 int dosync; 3213 int doppr; 3214 u_int period; 3215 u_int ppr_options; 3216 u_int offset; 3217 3218 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3219 devinfo->target, &tstate); 3220 /* 3221 * Filter our period based on the current connection. 3222 * If we can't perform DT transfers on this segment (not in LVD 3223 * mode for instance), then our decision to issue a PPR message 3224 * may change. 3225 */ 3226 period = tinfo->goal.period; 3227 ppr_options = tinfo->goal.ppr_options; 3228 /* Target initiated PPR is not allowed in the SCSI spec */ 3229 if (devinfo->role == ROLE_TARGET) 3230 ppr_options = 0; 3231 ahd_devlimited_syncrate(ahd, tinfo, &period, 3232 &ppr_options, devinfo->role); 3233 dowide = tinfo->curr.width != tinfo->goal.width; 3234 dosync = tinfo->curr.period != period; 3235 /* 3236 * Only use PPR if we have options that need it, even if the device 3237 * claims to support it. There might be an expander in the way 3238 * that doesn't. 3239 */ 3240 doppr = ppr_options != 0; 3241 3242 if (!dowide && !dosync && !doppr) { 3243 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3244 dosync = tinfo->goal.period != 0; 3245 } 3246 3247 if (!dowide && !dosync && !doppr) { 3248 /* 3249 * Force async with a WDTR message if we have a wide bus, 3250 * or just issue an SDTR with a 0 offset. 3251 */ 3252 if ((ahd->features & AHD_WIDE) != 0) 3253 dowide = 1; 3254 else 3255 dosync = 1; 3256 3257 if (bootverbose) { 3258 ahd_print_devinfo(ahd, devinfo); 3259 printf("Ensuring async\n"); 3260 } 3261 } 3262 /* Target initiated PPR is not allowed in the SCSI spec */ 3263 if (devinfo->role == ROLE_TARGET) 3264 doppr = 0; 3265 3266 /* 3267 * Both the PPR message and SDTR message require the 3268 * goal syncrate to be limited to what the target device 3269 * is capable of handling (based on whether an LVD->SE 3270 * expander is on the bus), so combine these two cases. 3271 * Regardless, guarantee that if we are using WDTR and SDTR 3272 * messages that WDTR comes first. 3273 */ 3274 if (doppr || (dosync && !dowide)) { 3275 3276 offset = tinfo->goal.offset; 3277 ahd_validate_offset(ahd, tinfo, period, &offset, 3278 doppr ? tinfo->goal.width 3279 : tinfo->curr.width, 3280 devinfo->role); 3281 if (doppr) { 3282 ahd_construct_ppr(ahd, devinfo, period, offset, 3283 tinfo->goal.width, ppr_options); 3284 } else { 3285 ahd_construct_sdtr(ahd, devinfo, period, offset); 3286 } 3287 } else { 3288 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3289 } 3290 } 3291 3292 /* 3293 * Build a synchronous negotiation message in our message 3294 * buffer based on the input parameters. 3295 */ 3296 static void 3297 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3298 u_int period, u_int offset) 3299 { 3300 if (offset == 0) 3301 period = AHD_ASYNC_XFER_PERIOD; 3302 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3303 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3304 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3305 ahd->msgout_buf[ahd->msgout_index++] = period; 3306 ahd->msgout_buf[ahd->msgout_index++] = offset; 3307 ahd->msgout_len += 5; 3308 if (bootverbose) { 3309 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3310 ahd_name(ahd), devinfo->channel, devinfo->target, 3311 devinfo->lun, period, offset); 3312 } 3313 } 3314 3315 /* 3316 * Build a wide negotiateion message in our message 3317 * buffer based on the input parameters. 3318 */ 3319 static void 3320 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3321 u_int bus_width) 3322 { 3323 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3324 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3325 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3326 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3327 ahd->msgout_len += 4; 3328 if (bootverbose) { 3329 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3330 ahd_name(ahd), devinfo->channel, devinfo->target, 3331 devinfo->lun, bus_width); 3332 } 3333 } 3334 3335 /* 3336 * Build a parallel protocol request message in our message 3337 * buffer based on the input parameters. 3338 */ 3339 static void 3340 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3341 u_int period, u_int offset, u_int bus_width, 3342 u_int ppr_options) 3343 { 3344 /* 3345 * Always request precompensation from 3346 * the other target if we are running 3347 * at paced syncrates. 3348 */ 3349 if (period <= AHD_SYNCRATE_PACED) 3350 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3351 if (offset == 0) 3352 period = AHD_ASYNC_XFER_PERIOD; 3353 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3354 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3355 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3356 ahd->msgout_buf[ahd->msgout_index++] = period; 3357 ahd->msgout_buf[ahd->msgout_index++] = 0; 3358 ahd->msgout_buf[ahd->msgout_index++] = offset; 3359 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3360 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3361 ahd->msgout_len += 8; 3362 if (bootverbose) { 3363 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3364 "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3365 devinfo->channel, devinfo->target, devinfo->lun, 3366 bus_width, period, offset, ppr_options); 3367 } 3368 } 3369 3370 /* 3371 * Clear any active message state. 3372 */ 3373 static void 3374 ahd_clear_msg_state(struct ahd_softc *ahd) 3375 { 3376 ahd_mode_state saved_modes; 3377 3378 saved_modes = ahd_save_modes(ahd); 3379 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3380 ahd->send_msg_perror = 0; 3381 ahd->msg_flags = MSG_FLAG_NONE; 3382 ahd->msgout_len = 0; 3383 ahd->msgin_index = 0; 3384 ahd->msg_type = MSG_TYPE_NONE; 3385 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3386 /* 3387 * The target didn't care to respond to our 3388 * message request, so clear ATN. 3389 */ 3390 ahd_outb(ahd, CLRSINT1, CLRATNO); 3391 } 3392 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3393 ahd_outb(ahd, SEQ_FLAGS2, 3394 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3395 ahd_restore_modes(ahd, saved_modes); 3396 } 3397 3398 /* 3399 * Manual message loop handler. 3400 */ 3401 static void 3402 ahd_handle_message_phase(struct ahd_softc *ahd) 3403 { 3404 struct ahd_devinfo devinfo; 3405 u_int bus_phase; 3406 int end_session; 3407 3408 ahd_fetch_devinfo(ahd, &devinfo); 3409 end_session = FALSE; 3410 bus_phase = ahd_inb(ahd, LASTPHASE); 3411 3412 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3413 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3414 ahd_outb(ahd, LQCTL2, LQIRETRY); 3415 } 3416 reswitch: 3417 switch (ahd->msg_type) { 3418 case MSG_TYPE_INITIATOR_MSGOUT: 3419 { 3420 int lastbyte; 3421 int phasemis; 3422 int msgdone; 3423 3424 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3425 panic("HOST_MSG_LOOP interrupt with no active message"); 3426 3427 #ifdef AHD_DEBUG 3428 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3429 ahd_print_devinfo(ahd, &devinfo); 3430 printf("INITIATOR_MSG_OUT"); 3431 } 3432 #endif 3433 phasemis = bus_phase != P_MESGOUT; 3434 if (phasemis) { 3435 #ifdef AHD_DEBUG 3436 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3437 printf(" PHASEMIS %s\n", 3438 ahd_lookup_phase_entry(bus_phase) 3439 ->phasemsg); 3440 } 3441 #endif 3442 if (bus_phase == P_MESGIN) { 3443 /* 3444 * Change gears and see if 3445 * this messages is of interest to 3446 * us or should be passed back to 3447 * the sequencer. 3448 */ 3449 ahd_outb(ahd, CLRSINT1, CLRATNO); 3450 ahd->send_msg_perror = 0; 3451 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3452 ahd->msgin_index = 0; 3453 goto reswitch; 3454 } 3455 end_session = TRUE; 3456 break; 3457 } 3458 3459 if (ahd->send_msg_perror) { 3460 ahd_outb(ahd, CLRSINT1, CLRATNO); 3461 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3462 #ifdef AHD_DEBUG 3463 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3464 printf(" byte 0x%x\n", ahd->send_msg_perror); 3465 #endif 3466 /* 3467 * If we are notifying the target of a CRC error 3468 * during packetized operations, the target is 3469 * within its rights to acknowledge our message 3470 * with a busfree. 3471 */ 3472 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3473 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3474 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3475 3476 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3477 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3478 break; 3479 } 3480 3481 msgdone = ahd->msgout_index == ahd->msgout_len; 3482 if (msgdone) { 3483 /* 3484 * The target has requested a retry. 3485 * Re-assert ATN, reset our message index to 3486 * 0, and try again. 3487 */ 3488 ahd->msgout_index = 0; 3489 ahd_assert_atn(ahd); 3490 } 3491 3492 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3493 if (lastbyte) { 3494 /* Last byte is signified by dropping ATN */ 3495 ahd_outb(ahd, CLRSINT1, CLRATNO); 3496 } 3497 3498 /* 3499 * Clear our interrupt status and present 3500 * the next byte on the bus. 3501 */ 3502 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3503 #ifdef AHD_DEBUG 3504 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3505 printf(" byte 0x%x\n", 3506 ahd->msgout_buf[ahd->msgout_index]); 3507 #endif 3508 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3509 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3510 break; 3511 } 3512 case MSG_TYPE_INITIATOR_MSGIN: 3513 { 3514 int phasemis; 3515 int message_done; 3516 3517 #ifdef AHD_DEBUG 3518 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3519 ahd_print_devinfo(ahd, &devinfo); 3520 printf("INITIATOR_MSG_IN"); 3521 } 3522 #endif 3523 phasemis = bus_phase != P_MESGIN; 3524 if (phasemis) { 3525 #ifdef AHD_DEBUG 3526 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3527 printf(" PHASEMIS %s\n", 3528 ahd_lookup_phase_entry(bus_phase) 3529 ->phasemsg); 3530 } 3531 #endif 3532 ahd->msgin_index = 0; 3533 if (bus_phase == P_MESGOUT 3534 && (ahd->send_msg_perror != 0 3535 || (ahd->msgout_len != 0 3536 && ahd->msgout_index == 0))) { 3537 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3538 goto reswitch; 3539 } 3540 end_session = TRUE; 3541 break; 3542 } 3543 3544 /* Pull the byte in without acking it */ 3545 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3546 #ifdef AHD_DEBUG 3547 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3548 printf(" byte 0x%x\n", 3549 ahd->msgin_buf[ahd->msgin_index]); 3550 #endif 3551 3552 message_done = ahd_parse_msg(ahd, &devinfo); 3553 3554 if (message_done) { 3555 /* 3556 * Clear our incoming message buffer in case there 3557 * is another message following this one. 3558 */ 3559 ahd->msgin_index = 0; 3560 3561 /* 3562 * If this message illicited a response, 3563 * assert ATN so the target takes us to the 3564 * message out phase. 3565 */ 3566 if (ahd->msgout_len != 0) { 3567 #ifdef AHD_DEBUG 3568 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3569 ahd_print_devinfo(ahd, &devinfo); 3570 printf("Asserting ATN for response\n"); 3571 } 3572 #endif 3573 ahd_assert_atn(ahd); 3574 } 3575 } else 3576 ahd->msgin_index++; 3577 3578 if (message_done == MSGLOOP_TERMINATED) { 3579 end_session = TRUE; 3580 } else { 3581 /* Ack the byte */ 3582 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3583 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3584 } 3585 break; 3586 } 3587 case MSG_TYPE_TARGET_MSGIN: 3588 { 3589 int msgdone; 3590 int msgout_request; 3591 3592 /* 3593 * By default, the message loop will continue. 3594 */ 3595 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3596 3597 if (ahd->msgout_len == 0) 3598 panic("Target MSGIN with no active message"); 3599 3600 /* 3601 * If we interrupted a mesgout session, the initiator 3602 * will not know this until our first REQ. So, we 3603 * only honor mesgout requests after we've sent our 3604 * first byte. 3605 */ 3606 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3607 && ahd->msgout_index > 0) 3608 msgout_request = TRUE; 3609 else 3610 msgout_request = FALSE; 3611 3612 if (msgout_request) { 3613 3614 /* 3615 * Change gears and see if 3616 * this messages is of interest to 3617 * us or should be passed back to 3618 * the sequencer. 3619 */ 3620 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3621 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3622 ahd->msgin_index = 0; 3623 /* Dummy read to REQ for first byte */ 3624 ahd_inb(ahd, SCSIDAT); 3625 ahd_outb(ahd, SXFRCTL0, 3626 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3627 break; 3628 } 3629 3630 msgdone = ahd->msgout_index == ahd->msgout_len; 3631 if (msgdone) { 3632 ahd_outb(ahd, SXFRCTL0, 3633 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3634 end_session = TRUE; 3635 break; 3636 } 3637 3638 /* 3639 * Present the next byte on the bus. 3640 */ 3641 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3642 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3643 break; 3644 } 3645 case MSG_TYPE_TARGET_MSGOUT: 3646 { 3647 int lastbyte; 3648 int msgdone; 3649 3650 /* 3651 * By default, the message loop will continue. 3652 */ 3653 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3654 3655 /* 3656 * The initiator signals that this is 3657 * the last byte by dropping ATN. 3658 */ 3659 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3660 3661 /* 3662 * Read the latched byte, but turn off SPIOEN first 3663 * so that we don't inadvertently cause a REQ for the 3664 * next byte. 3665 */ 3666 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3667 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3668 msgdone = ahd_parse_msg(ahd, &devinfo); 3669 if (msgdone == MSGLOOP_TERMINATED) { 3670 /* 3671 * The message is *really* done in that it caused 3672 * us to go to bus free. The sequencer has already 3673 * been reset at this point, so pull the ejection 3674 * handle. 3675 */ 3676 return; 3677 } 3678 3679 ahd->msgin_index++; 3680 3681 /* 3682 * XXX Read spec about initiator dropping ATN too soon 3683 * and use msgdone to detect it. 3684 */ 3685 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3686 ahd->msgin_index = 0; 3687 3688 /* 3689 * If this message illicited a response, transition 3690 * to the Message in phase and send it. 3691 */ 3692 if (ahd->msgout_len != 0) { 3693 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3694 ahd_outb(ahd, SXFRCTL0, 3695 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3696 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3697 ahd->msgin_index = 0; 3698 break; 3699 } 3700 } 3701 3702 if (lastbyte) 3703 end_session = TRUE; 3704 else { 3705 /* Ask for the next byte. */ 3706 ahd_outb(ahd, SXFRCTL0, 3707 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3708 } 3709 3710 break; 3711 } 3712 default: 3713 panic("Unknown REQINIT message type"); 3714 } 3715 3716 if (end_session) { 3717 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3718 printf("%s: Returning to Idle Loop\n", 3719 ahd_name(ahd)); 3720 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3721 ahd_clear_msg_state(ahd); 3722 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3723 } else { 3724 ahd_clear_msg_state(ahd); 3725 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3726 } 3727 } 3728 } 3729 3730 /* 3731 * See if we sent a particular extended message to the target. 3732 * If "full" is true, return true only if the target saw the full 3733 * message. If "full" is false, return true if the target saw at 3734 * least the first byte of the message. 3735 */ 3736 static int 3737 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3738 { 3739 int found; 3740 u_int index; 3741 3742 found = FALSE; 3743 index = 0; 3744 3745 while (index < ahd->msgout_len) { 3746 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3747 u_int end_index; 3748 3749 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3750 if (ahd->msgout_buf[index+2] == msgval 3751 && type == AHDMSG_EXT) { 3752 3753 if (full) { 3754 if (ahd->msgout_index > end_index) 3755 found = TRUE; 3756 } else if (ahd->msgout_index > index) 3757 found = TRUE; 3758 } 3759 index = end_index; 3760 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3761 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3762 3763 /* Skip tag type and tag id or residue param*/ 3764 index += 2; 3765 } else { 3766 /* Single byte message */ 3767 if (type == AHDMSG_1B 3768 && ahd->msgout_index > index 3769 && (ahd->msgout_buf[index] == msgval 3770 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3771 && msgval == MSG_IDENTIFYFLAG))) 3772 found = TRUE; 3773 index++; 3774 } 3775 3776 if (found) 3777 break; 3778 } 3779 return (found); 3780 } 3781 3782 /* 3783 * Wait for a complete incoming message, parse it, and respond accordingly. 3784 */ 3785 static int 3786 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3787 { 3788 struct ahd_initiator_tinfo *tinfo; 3789 struct ahd_tmode_tstate *tstate; 3790 int reject; 3791 int done; 3792 int response; 3793 3794 done = MSGLOOP_IN_PROG; 3795 response = FALSE; 3796 reject = FALSE; 3797 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3798 devinfo->target, &tstate); 3799 3800 /* 3801 * Parse as much of the message as is available, 3802 * rejecting it if we don't support it. When 3803 * the entire message is available and has been 3804 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3805 * that we have parsed an entire message. 3806 * 3807 * In the case of extended messages, we accept the length 3808 * byte outright and perform more checking once we know the 3809 * extended message type. 3810 */ 3811 switch (ahd->msgin_buf[0]) { 3812 case MSG_DISCONNECT: 3813 case MSG_SAVEDATAPOINTER: 3814 case MSG_CMDCOMPLETE: 3815 case MSG_RESTOREPOINTERS: 3816 case MSG_IGN_WIDE_RESIDUE: 3817 /* 3818 * End our message loop as these are messages 3819 * the sequencer handles on its own. 3820 */ 3821 done = MSGLOOP_TERMINATED; 3822 break; 3823 case MSG_MESSAGE_REJECT: 3824 response = ahd_handle_msg_reject(ahd, devinfo); 3825 /* FALLTHROUGH */ 3826 case MSG_NOOP: 3827 done = MSGLOOP_MSGCOMPLETE; 3828 break; 3829 case MSG_EXTENDED: 3830 { 3831 /* Wait for enough of the message to begin validation */ 3832 if (ahd->msgin_index < 2) 3833 break; 3834 switch (ahd->msgin_buf[2]) { 3835 case MSG_EXT_SDTR: 3836 { 3837 u_int period; 3838 u_int ppr_options; 3839 u_int offset; 3840 u_int saved_offset; 3841 3842 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3843 reject = TRUE; 3844 break; 3845 } 3846 3847 /* 3848 * Wait until we have both args before validating 3849 * and acting on this message. 3850 * 3851 * Add one to MSG_EXT_SDTR_LEN to account for 3852 * the extended message preamble. 3853 */ 3854 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3855 break; 3856 3857 period = ahd->msgin_buf[3]; 3858 ppr_options = 0; 3859 saved_offset = offset = ahd->msgin_buf[4]; 3860 ahd_devlimited_syncrate(ahd, tinfo, &period, 3861 &ppr_options, devinfo->role); 3862 ahd_validate_offset(ahd, tinfo, period, &offset, 3863 tinfo->curr.width, devinfo->role); 3864 if (bootverbose) { 3865 printf("(%s:%c:%d:%d): Received " 3866 "SDTR period %x, offset %x\n\t" 3867 "Filtered to period %x, offset %x\n", 3868 ahd_name(ahd), devinfo->channel, 3869 devinfo->target, devinfo->lun, 3870 ahd->msgin_buf[3], saved_offset, 3871 period, offset); 3872 } 3873 ahd_set_syncrate(ahd, devinfo, period, 3874 offset, ppr_options, 3875 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3876 /*paused*/TRUE); 3877 3878 /* 3879 * See if we initiated Sync Negotiation 3880 * and didn't have to fall down to async 3881 * transfers. 3882 */ 3883 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3884 /* We started it */ 3885 if (saved_offset != offset) { 3886 /* Went too low - force async */ 3887 reject = TRUE; 3888 } 3889 } else { 3890 /* 3891 * Send our own SDTR in reply 3892 */ 3893 if (bootverbose 3894 && devinfo->role == ROLE_INITIATOR) { 3895 printf("(%s:%c:%d:%d): Target " 3896 "Initiated SDTR\n", 3897 ahd_name(ahd), devinfo->channel, 3898 devinfo->target, devinfo->lun); 3899 } 3900 ahd->msgout_index = 0; 3901 ahd->msgout_len = 0; 3902 ahd_construct_sdtr(ahd, devinfo, 3903 period, offset); 3904 ahd->msgout_index = 0; 3905 response = TRUE; 3906 } 3907 done = MSGLOOP_MSGCOMPLETE; 3908 break; 3909 } 3910 case MSG_EXT_WDTR: 3911 { 3912 u_int bus_width; 3913 u_int saved_width; 3914 u_int sending_reply; 3915 3916 sending_reply = FALSE; 3917 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3918 reject = TRUE; 3919 break; 3920 } 3921 3922 /* 3923 * Wait until we have our arg before validating 3924 * and acting on this message. 3925 * 3926 * Add one to MSG_EXT_WDTR_LEN to account for 3927 * the extended message preamble. 3928 */ 3929 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3930 break; 3931 3932 bus_width = ahd->msgin_buf[3]; 3933 saved_width = bus_width; 3934 ahd_validate_width(ahd, tinfo, &bus_width, 3935 devinfo->role); 3936 if (bootverbose) { 3937 printf("(%s:%c:%d:%d): Received WDTR " 3938 "%x filtered to %x\n", 3939 ahd_name(ahd), devinfo->channel, 3940 devinfo->target, devinfo->lun, 3941 saved_width, bus_width); 3942 } 3943 3944 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3945 /* 3946 * Don't send a WDTR back to the 3947 * target, since we asked first. 3948 * If the width went higher than our 3949 * request, reject it. 3950 */ 3951 if (saved_width > bus_width) { 3952 reject = TRUE; 3953 printf("(%s:%c:%d:%d): requested %dBit " 3954 "transfers. Rejecting...\n", 3955 ahd_name(ahd), devinfo->channel, 3956 devinfo->target, devinfo->lun, 3957 8 * (0x01 << bus_width)); 3958 bus_width = 0; 3959 } 3960 } else { 3961 /* 3962 * Send our own WDTR in reply 3963 */ 3964 if (bootverbose 3965 && devinfo->role == ROLE_INITIATOR) { 3966 printf("(%s:%c:%d:%d): Target " 3967 "Initiated WDTR\n", 3968 ahd_name(ahd), devinfo->channel, 3969 devinfo->target, devinfo->lun); 3970 } 3971 ahd->msgout_index = 0; 3972 ahd->msgout_len = 0; 3973 ahd_construct_wdtr(ahd, devinfo, bus_width); 3974 ahd->msgout_index = 0; 3975 response = TRUE; 3976 sending_reply = TRUE; 3977 } 3978 ahd_set_width(ahd, devinfo, bus_width, 3979 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3980 /*paused*/TRUE); 3981 /* After a wide message, we are async */ 3982 ahd_set_syncrate(ahd, devinfo, /*period*/0, 3983 /*offset*/0, /*ppr_options*/0, 3984 AHD_TRANS_ACTIVE, /*paused*/TRUE); 3985 if (sending_reply == FALSE && reject == FALSE) { 3986 3987 if (tinfo->goal.offset) { 3988 ahd->msgout_index = 0; 3989 ahd->msgout_len = 0; 3990 ahd_build_transfer_msg(ahd, devinfo); 3991 ahd->msgout_index = 0; 3992 response = TRUE; 3993 } 3994 } 3995 done = MSGLOOP_MSGCOMPLETE; 3996 break; 3997 } 3998 case MSG_EXT_PPR: 3999 { 4000 u_int period; 4001 u_int offset; 4002 u_int bus_width; 4003 u_int ppr_options; 4004 u_int saved_width; 4005 u_int saved_offset; 4006 u_int saved_ppr_options; 4007 4008 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4009 reject = TRUE; 4010 break; 4011 } 4012 4013 /* 4014 * Wait until we have all args before validating 4015 * and acting on this message. 4016 * 4017 * Add one to MSG_EXT_PPR_LEN to account for 4018 * the extended message preamble. 4019 */ 4020 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4021 break; 4022 4023 period = ahd->msgin_buf[3]; 4024 offset = ahd->msgin_buf[5]; 4025 bus_width = ahd->msgin_buf[6]; 4026 saved_width = bus_width; 4027 ppr_options = ahd->msgin_buf[7]; 4028 /* 4029 * According to the spec, a DT only 4030 * period factor with no DT option 4031 * set implies async. 4032 */ 4033 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4034 && period <= 9) 4035 offset = 0; 4036 saved_ppr_options = ppr_options; 4037 saved_offset = offset; 4038 4039 /* 4040 * Transfer options are only available if we 4041 * are negotiating wide. 4042 */ 4043 if (bus_width == 0) 4044 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4045 4046 ahd_validate_width(ahd, tinfo, &bus_width, 4047 devinfo->role); 4048 ahd_devlimited_syncrate(ahd, tinfo, &period, 4049 &ppr_options, devinfo->role); 4050 ahd_validate_offset(ahd, tinfo, period, &offset, 4051 bus_width, devinfo->role); 4052 4053 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4054 /* 4055 * If we are unable to do any of the 4056 * requested options (we went too low), 4057 * then we'll have to reject the message. 4058 */ 4059 if (saved_width > bus_width 4060 || saved_offset != offset 4061 || saved_ppr_options != ppr_options) { 4062 reject = TRUE; 4063 period = 0; 4064 offset = 0; 4065 bus_width = 0; 4066 ppr_options = 0; 4067 } 4068 } else { 4069 if (devinfo->role != ROLE_TARGET) 4070 printf("(%s:%c:%d:%d): Target " 4071 "Initiated PPR\n", 4072 ahd_name(ahd), devinfo->channel, 4073 devinfo->target, devinfo->lun); 4074 else 4075 printf("(%s:%c:%d:%d): Initiator " 4076 "Initiated PPR\n", 4077 ahd_name(ahd), devinfo->channel, 4078 devinfo->target, devinfo->lun); 4079 ahd->msgout_index = 0; 4080 ahd->msgout_len = 0; 4081 ahd_construct_ppr(ahd, devinfo, period, offset, 4082 bus_width, ppr_options); 4083 ahd->msgout_index = 0; 4084 response = TRUE; 4085 } 4086 if (bootverbose) { 4087 printf("(%s:%c:%d:%d): Received PPR width %x, " 4088 "period %x, offset %x,options %x\n" 4089 "\tFiltered to width %x, period %x, " 4090 "offset %x, options %x\n", 4091 ahd_name(ahd), devinfo->channel, 4092 devinfo->target, devinfo->lun, 4093 saved_width, ahd->msgin_buf[3], 4094 saved_offset, saved_ppr_options, 4095 bus_width, period, offset, ppr_options); 4096 } 4097 ahd_set_width(ahd, devinfo, bus_width, 4098 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4099 /*paused*/TRUE); 4100 ahd_set_syncrate(ahd, devinfo, period, 4101 offset, ppr_options, 4102 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4103 /*paused*/TRUE); 4104 4105 done = MSGLOOP_MSGCOMPLETE; 4106 break; 4107 } 4108 default: 4109 /* Unknown extended message. Reject it. */ 4110 reject = TRUE; 4111 break; 4112 } 4113 break; 4114 } 4115 #ifdef AHD_TARGET_MODE 4116 case MSG_BUS_DEV_RESET: 4117 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4118 CAM_BDR_SENT, 4119 "Bus Device Reset Received", 4120 /*verbose_level*/0); 4121 ahd_restart(ahd); 4122 done = MSGLOOP_TERMINATED; 4123 break; 4124 case MSG_ABORT_TAG: 4125 case MSG_ABORT: 4126 case MSG_CLEAR_QUEUE: 4127 { 4128 int tag; 4129 4130 /* Target mode messages */ 4131 if (devinfo->role != ROLE_TARGET) { 4132 reject = TRUE; 4133 break; 4134 } 4135 tag = SCB_LIST_NULL; 4136 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4137 tag = ahd_inb(ahd, INITIATOR_TAG); 4138 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4139 devinfo->lun, tag, ROLE_TARGET, 4140 CAM_REQ_ABORTED); 4141 4142 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4143 if (tstate != NULL) { 4144 struct ahd_tmode_lstate* lstate; 4145 4146 lstate = tstate->enabled_luns[devinfo->lun]; 4147 if (lstate != NULL) { 4148 ahd_queue_lstate_event(ahd, lstate, 4149 devinfo->our_scsiid, 4150 ahd->msgin_buf[0], 4151 /*arg*/tag); 4152 ahd_send_lstate_events(ahd, lstate); 4153 } 4154 } 4155 ahd_restart(ahd); 4156 done = MSGLOOP_TERMINATED; 4157 break; 4158 } 4159 #endif 4160 case MSG_QAS_REQUEST: 4161 #ifdef AHD_DEBUG 4162 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4163 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4164 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4165 #endif 4166 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4167 /* FALLTHROUGH */ 4168 case MSG_TERM_IO_PROC: 4169 default: 4170 reject = TRUE; 4171 break; 4172 } 4173 4174 if (reject) { 4175 /* 4176 * Setup to reject the message. 4177 */ 4178 ahd->msgout_index = 0; 4179 ahd->msgout_len = 1; 4180 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4181 done = MSGLOOP_MSGCOMPLETE; 4182 response = TRUE; 4183 } 4184 4185 if (done != MSGLOOP_IN_PROG && !response) 4186 /* Clear the outgoing message buffer */ 4187 ahd->msgout_len = 0; 4188 4189 return (done); 4190 } 4191 4192 /* 4193 * Process a message reject message. 4194 */ 4195 static int 4196 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4197 { 4198 /* 4199 * What we care about here is if we had an 4200 * outstanding SDTR or WDTR message for this 4201 * target. If we did, this is a signal that 4202 * the target is refusing negotiation. 4203 */ 4204 struct scb *scb; 4205 struct ahd_initiator_tinfo *tinfo; 4206 struct ahd_tmode_tstate *tstate; 4207 u_int scb_index; 4208 u_int last_msg; 4209 int response = 0; 4210 4211 scb_index = ahd_get_scbptr(ahd); 4212 scb = ahd_lookup_scb(ahd, scb_index); 4213 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4214 devinfo->our_scsiid, 4215 devinfo->target, &tstate); 4216 /* Might be necessary */ 4217 last_msg = ahd_inb(ahd, LAST_MSG); 4218 4219 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4220 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4221 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4222 /* 4223 * Target may not like our SPI-4 PPR Options. 4224 * Attempt to negotiate 80MHz which will turn 4225 * off these options. 4226 */ 4227 if (bootverbose) { 4228 printf("(%s:%c:%d:%d): PPR Rejected. " 4229 "Trying simple U160 PPR\n", 4230 ahd_name(ahd), devinfo->channel, 4231 devinfo->target, devinfo->lun); 4232 } 4233 tinfo->goal.period = AHD_SYNCRATE_DT; 4234 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4235 | MSG_EXT_PPR_QAS_REQ 4236 | MSG_EXT_PPR_DT_REQ; 4237 } else { 4238 /* 4239 * Target does not support the PPR message. 4240 * Attempt to negotiate SPI-2 style. 4241 */ 4242 if (bootverbose) { 4243 printf("(%s:%c:%d:%d): PPR Rejected. " 4244 "Trying WDTR/SDTR\n", 4245 ahd_name(ahd), devinfo->channel, 4246 devinfo->target, devinfo->lun); 4247 } 4248 tinfo->goal.ppr_options = 0; 4249 tinfo->curr.transport_version = 2; 4250 tinfo->goal.transport_version = 2; 4251 } 4252 ahd->msgout_index = 0; 4253 ahd->msgout_len = 0; 4254 ahd_build_transfer_msg(ahd, devinfo); 4255 ahd->msgout_index = 0; 4256 response = 1; 4257 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4258 4259 /* note 8bit xfers */ 4260 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4261 "8bit transfers\n", ahd_name(ahd), 4262 devinfo->channel, devinfo->target, devinfo->lun); 4263 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4264 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4265 /*paused*/TRUE); 4266 /* 4267 * No need to clear the sync rate. If the target 4268 * did not accept the command, our syncrate is 4269 * unaffected. If the target started the negotiation, 4270 * but rejected our response, we already cleared the 4271 * sync rate before sending our WDTR. 4272 */ 4273 if (tinfo->goal.offset != tinfo->curr.offset) { 4274 4275 /* Start the sync negotiation */ 4276 ahd->msgout_index = 0; 4277 ahd->msgout_len = 0; 4278 ahd_build_transfer_msg(ahd, devinfo); 4279 ahd->msgout_index = 0; 4280 response = 1; 4281 } 4282 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4283 /* note asynch xfers and clear flag */ 4284 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4285 /*offset*/0, /*ppr_options*/0, 4286 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4287 /*paused*/TRUE); 4288 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4289 "Using asynchronous transfers\n", 4290 ahd_name(ahd), devinfo->channel, 4291 devinfo->target, devinfo->lun); 4292 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4293 int tag_type; 4294 int mask; 4295 4296 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4297 4298 if (tag_type == MSG_SIMPLE_TASK) { 4299 printf("(%s:%c:%d:%d): refuses tagged commands. " 4300 "Performing non-tagged I/O\n", ahd_name(ahd), 4301 devinfo->channel, devinfo->target, devinfo->lun); 4302 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4303 mask = ~0x23; 4304 } else { 4305 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4306 "Performing simple queue tagged I/O only\n", 4307 ahd_name(ahd), devinfo->channel, devinfo->target, 4308 devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4309 ? "ordered" : "head of queue"); 4310 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4311 mask = ~0x03; 4312 } 4313 4314 /* 4315 * Resend the identify for this CCB as the target 4316 * may believe that the selection is invalid otherwise. 4317 */ 4318 ahd_outb(ahd, SCB_CONTROL, 4319 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4320 scb->hscb->control &= mask; 4321 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4322 /*type*/MSG_SIMPLE_TASK); 4323 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4324 ahd_assert_atn(ahd); 4325 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4326 SCB_GET_TAG(scb)); 4327 4328 /* 4329 * Requeue all tagged commands for this target 4330 * currently in our posession so they can be 4331 * converted to untagged commands. 4332 */ 4333 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4334 SCB_GET_CHANNEL(ahd, scb), 4335 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4336 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4337 SEARCH_COMPLETE); 4338 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4339 /* 4340 * Most likely the device believes that we had 4341 * previously negotiated packetized. 4342 */ 4343 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4344 | MSG_FLAG_IU_REQ_CHANGED; 4345 4346 ahd_force_renegotiation(ahd, devinfo); 4347 ahd->msgout_index = 0; 4348 ahd->msgout_len = 0; 4349 ahd_build_transfer_msg(ahd, devinfo); 4350 ahd->msgout_index = 0; 4351 response = 1; 4352 } else { 4353 /* 4354 * Otherwise, we ignore it. 4355 */ 4356 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4357 ahd_name(ahd), devinfo->channel, devinfo->target, 4358 last_msg); 4359 } 4360 return (response); 4361 } 4362 4363 /* 4364 * Process an ignore wide residue message. 4365 */ 4366 static void 4367 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4368 { 4369 u_int scb_index; 4370 struct scb *scb; 4371 4372 printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4373 4374 scb_index = ahd_get_scbptr(ahd); 4375 scb = ahd_lookup_scb(ahd, scb_index); 4376 /* 4377 * XXX Actually check data direction in the sequencer? 4378 * Perhaps add datadir to some spare bits in the hscb? 4379 */ 4380 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4381 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4382 /* 4383 * Ignore the message if we haven't 4384 * seen an appropriate data phase yet. 4385 */ 4386 } else { 4387 /* 4388 * If the residual occurred on the last 4389 * transfer and the transfer request was 4390 * expected to end on an odd count, do 4391 * nothing. Otherwise, subtract a byte 4392 * and update the residual count accordingly. 4393 */ 4394 uint32_t sgptr; 4395 4396 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4397 if ((sgptr & SG_LIST_NULL) != 0 4398 && ahd_inb(ahd, DATA_COUNT_ODD) == 1) { 4399 /* 4400 * If the residual occurred on the last 4401 * transfer and the transfer request was 4402 * expected to end on an odd count, do 4403 * nothing. 4404 */ 4405 } else { 4406 uint32_t data_cnt; 4407 uint64_t data_addr; 4408 uint32_t sglen; 4409 4410 /* Pull in the rest of the sgptr */ 4411 sgptr |= 4412 (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4413 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4414 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8); 4415 sgptr &= SG_PTR_MASK; 4416 data_cnt = 4417 (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24) 4418 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+2) << 16) 4419 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+1) << 8) 4420 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT)); 4421 4422 data_addr = (((uint64_t)ahd_inb(ahd, SHADDR + 7)) << 56) 4423 | (((uint64_t)ahd_inb(ahd, SHADDR + 6)) << 48) 4424 | (((uint64_t)ahd_inb(ahd, SHADDR + 5)) << 40) 4425 | (((uint64_t)ahd_inb(ahd, SHADDR + 4)) << 32) 4426 | (ahd_inb(ahd, SHADDR + 3) << 24) 4427 | (ahd_inb(ahd, SHADDR + 2) << 16) 4428 | (ahd_inb(ahd, SHADDR + 1) << 8) 4429 | (ahd_inb(ahd, SHADDR)); 4430 4431 data_cnt += 1; 4432 data_addr -= 1; 4433 4434 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4435 struct ahd_dma64_seg *sg; 4436 4437 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4438 4439 /* 4440 * The residual sg ptr points to the next S/G 4441 * to load so we must go back one. 4442 */ 4443 sg--; 4444 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4445 if (sg != scb->sg_list 4446 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4447 4448 sg--; 4449 sglen = ahd_le32toh(sg->len); 4450 /* 4451 * Preserve High Address and SG_LIST 4452 * bits while setting the count to 1. 4453 */ 4454 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4455 data_addr = ahd_le64toh(sg->addr) 4456 + (sglen & AHD_SG_LEN_MASK) 4457 - 1; 4458 4459 /* 4460 * Increment sg so it points to the 4461 * "next" sg. 4462 */ 4463 sg++; 4464 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4465 sg); 4466 } 4467 } else { 4468 struct ahd_dma_seg *sg; 4469 4470 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4471 4472 /* 4473 * The residual sg ptr points to the next S/G 4474 * to load so we must go back one. 4475 */ 4476 sg--; 4477 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4478 if (sg != scb->sg_list 4479 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4480 4481 sg--; 4482 sglen = ahd_le32toh(sg->len); 4483 /* 4484 * Preserve High Address and SG_LIST 4485 * bits while setting the count to 1. 4486 */ 4487 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4488 data_addr = ahd_le32toh(sg->addr) 4489 + (sglen & AHD_SG_LEN_MASK) 4490 - 1; 4491 4492 /* 4493 * Increment sg so it points to the 4494 * "next" sg. 4495 */ 4496 sg++; 4497 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4498 sg); 4499 } 4500 } 4501 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 3, sgptr >> 24); 4502 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 2, sgptr >> 16); 4503 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 1, sgptr >> 8); 4504 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4505 4506 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 4507 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 4508 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 4509 ahd_outb(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4510 4511 /* 4512 * The FIFO's pointers will be updated if/when the 4513 * sequencer re-enters a data phase. 4514 */ 4515 } 4516 } 4517 } 4518 4519 4520 /* 4521 * Reinitialize the data pointers for the active transfer 4522 * based on its current residual. 4523 */ 4524 static void 4525 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4526 { 4527 struct scb *scb; 4528 ahd_mode_state saved_modes; 4529 u_int scb_index; 4530 u_int wait; 4531 uint32_t sgptr; 4532 uint32_t resid; 4533 uint64_t dataptr; 4534 4535 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4536 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4537 4538 scb_index = ahd_get_scbptr(ahd); 4539 scb = ahd_lookup_scb(ahd, scb_index); 4540 4541 /* 4542 * Release and reacquire the FIFO so we 4543 * have a clean slate. 4544 */ 4545 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4546 wait = 1000; 4547 do { 4548 ahd_delay(100); 4549 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)); 4550 if (wait == 0) { 4551 ahd_print_path(ahd, scb); 4552 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4553 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4554 } 4555 saved_modes = ahd_save_modes(ahd); 4556 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4557 ahd_outb(ahd, DFFSTAT, 4558 ahd_inb(ahd, DFFSTAT) 4559 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4560 4561 /* 4562 * Determine initial values for data_addr and data_cnt 4563 * for resuming the data phase. 4564 */ 4565 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4566 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4567 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4568 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4569 sgptr &= SG_PTR_MASK; 4570 4571 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4572 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4573 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4574 4575 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4576 struct ahd_dma64_seg *sg; 4577 4578 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4579 4580 /* The residual sg_ptr always points to the next sg */ 4581 sg--; 4582 4583 dataptr = ahd_le64toh(sg->addr) 4584 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4585 - resid; 4586 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4587 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4588 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4589 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4590 } else { 4591 struct ahd_dma_seg *sg; 4592 4593 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4594 4595 /* The residual sg_ptr always points to the next sg */ 4596 sg--; 4597 4598 dataptr = ahd_le32toh(sg->addr) 4599 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4600 - resid; 4601 ahd_outb(ahd, HADDR + 4, 4602 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4603 } 4604 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4605 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4606 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4607 ahd_outb(ahd, HADDR, dataptr); 4608 ahd_outb(ahd, HCNT + 2, resid >> 16); 4609 ahd_outb(ahd, HCNT + 1, resid >> 8); 4610 ahd_outb(ahd, HCNT, resid); 4611 } 4612 4613 /* 4614 * Handle the effects of issuing a bus device reset message. 4615 */ 4616 static void 4617 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4618 u_int lun, cam_status status, char *message, 4619 int verbose_level) 4620 { 4621 #ifdef AHD_TARGET_MODE 4622 struct ahd_tmode_tstate* tstate; 4623 #endif 4624 int found; 4625 4626 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4627 lun, SCB_LIST_NULL, devinfo->role, 4628 status); 4629 4630 #ifdef AHD_TARGET_MODE 4631 /* 4632 * Send an immediate notify ccb to all target mord peripheral 4633 * drivers affected by this action. 4634 */ 4635 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4636 if (tstate != NULL) { 4637 u_int cur_lun; 4638 u_int max_lun; 4639 4640 if (lun != CAM_LUN_WILDCARD) { 4641 cur_lun = 0; 4642 max_lun = AHD_NUM_LUNS - 1; 4643 } else { 4644 cur_lun = lun; 4645 max_lun = lun; 4646 } 4647 for (cur_lun <= max_lun; cur_lun++) { 4648 struct ahd_tmode_lstate* lstate; 4649 4650 lstate = tstate->enabled_luns[cur_lun]; 4651 if (lstate == NULL) 4652 continue; 4653 4654 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4655 MSG_BUS_DEV_RESET, /*arg*/0); 4656 ahd_send_lstate_events(ahd, lstate); 4657 } 4658 } 4659 #endif 4660 4661 /* 4662 * Go back to async/narrow transfers and renegotiate. 4663 */ 4664 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4665 AHD_TRANS_CUR, /*paused*/TRUE); 4666 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4667 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4668 4669 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4670 lun, AC_SENT_BDR, NULL); 4671 4672 if (message != NULL 4673 && (verbose_level <= bootverbose)) 4674 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4675 message, devinfo->channel, devinfo->target, found); 4676 } 4677 4678 #ifdef AHD_TARGET_MODE 4679 static void 4680 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4681 struct scb *scb) 4682 { 4683 4684 /* 4685 * To facilitate adding multiple messages together, 4686 * each routine should increment the index and len 4687 * variables instead of setting them explicitly. 4688 */ 4689 ahd->msgout_index = 0; 4690 ahd->msgout_len = 0; 4691 4692 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4693 ahd_build_transfer_msg(ahd, devinfo); 4694 else 4695 panic("ahd_intr: AWAITING target message with no message"); 4696 4697 ahd->msgout_index = 0; 4698 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4699 } 4700 #endif 4701 /**************************** Initialization **********************************/ 4702 static u_int 4703 ahd_sglist_size(struct ahd_softc *ahd) 4704 { 4705 bus_size_t list_size; 4706 4707 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4708 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4709 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4710 return (list_size); 4711 } 4712 4713 /* 4714 * Calculate the optimum S/G List allocation size. S/G elements used 4715 * for a given transaction must be physically contiguous. Assume the 4716 * OS will allocate full pages to us, so it doesn't make sense to request 4717 * less than a page. 4718 */ 4719 static u_int 4720 ahd_sglist_allocsize(struct ahd_softc *ahd) 4721 { 4722 bus_size_t sg_list_increment; 4723 bus_size_t sg_list_size; 4724 bus_size_t max_list_size; 4725 bus_size_t best_list_size; 4726 4727 /* Start out with the minimum required for AHD_NSEG. */ 4728 sg_list_increment = ahd_sglist_size(ahd); 4729 sg_list_size = sg_list_increment; 4730 4731 /* Get us as close as possible to a page in size. */ 4732 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4733 sg_list_size += sg_list_increment; 4734 4735 /* 4736 * Try to reduce the amount of wastage by allocating 4737 * multiple pages. 4738 */ 4739 best_list_size = sg_list_size; 4740 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4741 if (max_list_size < 4 * PAGE_SIZE) 4742 max_list_size = 4 * PAGE_SIZE; 4743 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4744 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4745 while ((sg_list_size + sg_list_increment) <= max_list_size 4746 && (sg_list_size % PAGE_SIZE) != 0) { 4747 bus_size_t new_mod; 4748 bus_size_t best_mod; 4749 4750 sg_list_size += sg_list_increment; 4751 new_mod = sg_list_size % PAGE_SIZE; 4752 best_mod = best_list_size % PAGE_SIZE; 4753 if (new_mod > best_mod || new_mod == 0) { 4754 best_list_size = sg_list_size; 4755 } 4756 } 4757 return (best_list_size); 4758 } 4759 4760 int 4761 ahd_softc_init(struct ahd_softc *ahd) 4762 { 4763 4764 ahd->unpause = 0; 4765 ahd->pause = PAUSE; 4766 return (0); 4767 } 4768 4769 void 4770 ahd_set_unit(struct ahd_softc *ahd, int unit) 4771 { 4772 ahd->unit = unit; 4773 } 4774 4775 void 4776 ahd_set_name(struct ahd_softc *ahd, char *name) 4777 { 4778 if (ahd->name != NULL) 4779 free(ahd->name, M_DEVBUF); 4780 ahd->name = name; 4781 } 4782 4783 void 4784 ahd_free(struct ahd_softc *ahd) 4785 { 4786 int i; 4787 4788 ahd_fini_scbdata(ahd); 4789 switch (ahd->init_level) { 4790 default: 4791 case 2: 4792 ahd_shutdown(ahd); 4793 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4794 /* FALLTHROUGH */ 4795 case 1: 4796 bus_dmamap_unload(ahd->parent_dmat, ahd->shared_data_dmamap); 4797 bus_dmamap_destroy(ahd->parent_dmat, ahd->shared_data_dmamap); 4798 bus_dmamem_unmap(ahd->parent_dmat, (caddr_t)ahd->qoutfifo, ahd->shared_data_size); 4799 bus_dmamem_free(ahd->parent_dmat, &ahd->shared_data_seg, ahd->shared_data_nseg); 4800 break; 4801 case 0: 4802 break; 4803 } 4804 4805 ahd_platform_free(ahd); 4806 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4807 struct ahd_tmode_tstate *tstate; 4808 4809 tstate = ahd->enabled_targets[i]; 4810 if (tstate != NULL) { 4811 #if AHD_TARGET_MODE 4812 int j; 4813 4814 for (j = 0; j < AHD_NUM_LUNS; j++) { 4815 struct ahd_tmode_lstate *lstate; 4816 4817 lstate = tstate->enabled_luns[j]; 4818 if (lstate != NULL) { 4819 xpt_free_path(lstate->path); 4820 free(lstate, M_DEVBUF); 4821 } 4822 } 4823 #endif 4824 free(tstate, M_DEVBUF); 4825 } 4826 } 4827 #if AHD_TARGET_MODE 4828 if (ahd->black_hole != NULL) { 4829 xpt_free_path(ahd->black_hole->path); 4830 free(ahd->black_hole, M_DEVBUF); 4831 } 4832 #endif 4833 if (ahd->name != NULL) 4834 free(ahd->name, M_DEVBUF); 4835 if (ahd->seep_config != NULL) 4836 free(ahd->seep_config, M_DEVBUF); 4837 if (ahd->saved_stack != NULL) 4838 free(ahd->saved_stack, M_DEVBUF); 4839 #ifndef __FreeBSD__ 4840 free(ahd, M_DEVBUF); 4841 #endif 4842 return; 4843 } 4844 4845 void 4846 ahd_shutdown(void *arg) 4847 { 4848 struct ahd_softc *ahd; 4849 4850 ahd = (struct ahd_softc *)arg; 4851 4852 #ifdef AHD_DEBUG 4853 printf("%s: ahd_shutdown\n", ahd_name(ahd)); 4854 #endif 4855 /* 4856 * Stop periodic timer callbacks. 4857 */ 4858 ahd_timer_stop(&ahd->reset_timer); 4859 ahd_timer_stop(&ahd->stat_timer); 4860 4861 /* This will reset most registers to 0, but not all */ 4862 ahd_reset(ahd); 4863 } 4864 4865 /* 4866 * Reset the controller and record some information about it 4867 * that is only available just after a reset. 4868 */ 4869 int 4870 ahd_reset(struct ahd_softc *ahd) 4871 { 4872 u_int sxfrctl1; 4873 int wait; 4874 uint32_t cmd; 4875 struct ahd_pci_busdata *bd = ahd->bus_data; 4876 4877 /* 4878 * Preserve the value of the SXFRCTL1 register for all channels. 4879 * It contains settings that affect termination and we don't want 4880 * to disturb the integrity of the bus. 4881 */ 4882 ahd_pause(ahd); 4883 ahd_update_modes(ahd); 4884 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4885 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4886 4887 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 4888 4889 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4890 uint32_t mod_cmd; 4891 4892 /* 4893 * A4 Razor #632 4894 * During the assertion of CHIPRST, the chip 4895 * does not disable its parity logic prior to 4896 * the start of the reset. This may cause a 4897 * parity error to be detected and thus a 4898 * spurious SERR or PERR assertion. Disble 4899 * PERR and SERR responses during the CHIPRST. 4900 */ 4901 mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 4902 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, mod_cmd); 4903 } 4904 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 4905 4906 /* 4907 * Ensure that the reset has finished. We delay 1000us 4908 * prior to reading the register to make sure the chip 4909 * has sufficiently completed its reset to handle register 4910 * accesses. 4911 */ 4912 wait = 1000; 4913 do { 4914 ahd_delay(1000); 4915 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 4916 4917 if (wait == 0) { 4918 printf("%s: WARNING - Failed chip reset! " 4919 "Trying to initialize anyway.\n", ahd_name(ahd)); 4920 } 4921 ahd_outb(ahd, HCNTRL, ahd->pause); 4922 4923 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4924 /* 4925 * Clear any latched PCI error status and restore 4926 * previous SERR and PERR response enables. 4927 */ 4928 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 0x000000FF); 4929 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 4930 PCI_COMMAND_SERR_ENABLE|PCI_COMMAND_PARITY_ENABLE); 4931 } 4932 4933 /* 4934 * Mode should be SCSI after a chip reset, but lets 4935 * set it just to be safe. We touch the MODE_PTR 4936 * register directly so as to bypass the lazy update 4937 * ode in ahd_set_modes(). 4938 */ 4939 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4940 ahd_outb(ahd, MODE_PTR, 4941 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 4942 4943 /* 4944 * Restore SXFRCTL1. 4945 * 4946 * We must always initialize STPWEN to 1 before we 4947 * restore the saved values. STPWEN is initialized 4948 * to a tri-state condition which can only be cleared 4949 * by turning it on. 4950 */ 4951 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 4952 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 4953 4954 /* Determine chip configuration */ 4955 ahd->features &= ~AHD_WIDE; 4956 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 4957 ahd->features |= AHD_WIDE; 4958 4959 /* 4960 * If a recovery action has forced a chip reset, 4961 * re-initialize the chip to our liking. 4962 */ 4963 if (ahd->init_level > 0) 4964 ahd_chip_init(ahd); 4965 4966 return (0); 4967 } 4968 4969 /* 4970 * Determine the number of SCBs available on the controller 4971 */ 4972 int 4973 ahd_probe_scbs(struct ahd_softc *ahd) { 4974 int i; 4975 4976 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 4977 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 4978 for (i = 0; i < AHD_SCB_MAX; i++) { 4979 int j; 4980 int ret; 4981 4982 ahd_set_scbptr(ahd, i); 4983 ahd_outw(ahd, SCB_BASE, i); 4984 for (j = 2; j < 64; j++) 4985 ahd_outb(ahd, SCB_BASE+j, 0); 4986 /* Start out life as unallocated (needing an abort) */ 4987 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 4988 ret = ahd_inw_scbram(ahd, SCB_BASE); 4989 if (ret != i) { 4990 printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", ahd_name(ahd), i, ret); 4991 break; 4992 } 4993 ahd_set_scbptr(ahd, 0); 4994 ret = ahd_inw_scbram(ahd, SCB_BASE); 4995 if (ret != 0) { 4996 printf("ahd_probe_scbs (non zero): returned 0x%x\n", ret); 4997 break; 4998 } 4999 } 5000 return (i); 5001 } 5002 5003 static void 5004 ahd_initialize_hscbs(struct ahd_softc *ahd) 5005 { 5006 int i; 5007 5008 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5009 ahd_set_scbptr(ahd, i); 5010 5011 /* Clear the control byte. */ 5012 ahd_outb(ahd, SCB_CONTROL, 0); 5013 5014 /* Set the next pointer */ 5015 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5016 } 5017 } 5018 5019 static int 5020 ahd_init_scbdata(struct ahd_softc *ahd) 5021 { 5022 struct scb_data *scb_data; 5023 int i; 5024 5025 scb_data = &ahd->scb_data; 5026 TAILQ_INIT(&scb_data->free_scbs); 5027 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5028 LIST_INIT(&scb_data->free_scb_lists[i]); 5029 LIST_INIT(&scb_data->any_dev_free_scb_list); 5030 SLIST_INIT(&scb_data->hscb_maps); 5031 SLIST_INIT(&scb_data->sg_maps); 5032 SLIST_INIT(&scb_data->sense_maps); 5033 5034 /* Determine the number of hardware SCBs and initialize them */ 5035 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5036 if (scb_data->maxhscbs == 0) { 5037 printf("%s: No SCB space found\n", ahd_name(ahd)); 5038 return (ENXIO); 5039 } 5040 ahd_initialize_hscbs(ahd); 5041 5042 /* 5043 * Create our DMA tags. These tags define the kinds of device 5044 * accessible memory allocations and memory mappings we will 5045 * need to perform during normal operation. 5046 * 5047 * Unless we need to further restrict the allocation, we rely 5048 * on the restrictions of the parent dmat, hence the common 5049 * use of MAXADDR and MAXSIZE. 5050 */ 5051 5052 /* Perform initial CCB allocation */ 5053 ahd_alloc_scbs(ahd); 5054 5055 if (scb_data->numscbs == 0) { 5056 printf("%s: ahd_init_scbdata - " 5057 "Unable to allocate initial scbs\n", 5058 ahd_name(ahd)); 5059 goto error_exit; 5060 } 5061 5062 /* 5063 * Note that we were successfull 5064 */ 5065 return (0); 5066 5067 error_exit: 5068 5069 return (ENOMEM); 5070 } 5071 5072 static struct scb * 5073 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5074 { 5075 struct scb *scb; 5076 5077 /* 5078 * Look on the pending list. 5079 */ 5080 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5081 if (SCB_GET_TAG(scb) == tag) 5082 return (scb); 5083 } 5084 5085 /* 5086 * Then on all of the collision free lists. 5087 */ 5088 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5089 struct scb *list_scb; 5090 5091 list_scb = scb; 5092 do { 5093 if (SCB_GET_TAG(list_scb) == tag) 5094 return (list_scb); 5095 list_scb = LIST_NEXT(list_scb, collision_links); 5096 } while (list_scb); 5097 } 5098 5099 /* 5100 * And finally on the generic free list. 5101 */ 5102 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5103 if (SCB_GET_TAG(scb) == tag) 5104 return (scb); 5105 } 5106 5107 return (NULL); 5108 } 5109 5110 static void 5111 ahd_fini_scbdata(struct ahd_softc *ahd) 5112 { 5113 struct scb_data *scb_data; 5114 5115 scb_data = &ahd->scb_data; 5116 if (scb_data == NULL) 5117 return; 5118 5119 switch (scb_data->init_level) { 5120 default: 5121 case 3: 5122 { 5123 struct map_node *sns_map; 5124 5125 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5126 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5127 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5128 sns_map->dmamap, (caddr_t)sns_map->vaddr, 5129 &sns_map->dmasegs, sns_map->nseg); 5130 free(sns_map, M_DEVBUF); 5131 } 5132 /* FALLTHROUGH */ 5133 } 5134 case 2: 5135 { 5136 struct map_node *sg_map; 5137 5138 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5139 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5140 ahd_freedmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), 5141 sg_map->dmamap, (caddr_t)sg_map->vaddr, 5142 &sg_map->dmasegs, sg_map->nseg); 5143 free(sg_map, M_DEVBUF); 5144 } 5145 /* FALLTHROUGH */ 5146 } 5147 case 1: 5148 { 5149 struct map_node *hscb_map; 5150 5151 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5152 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5153 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5154 hscb_map->dmamap, (caddr_t)hscb_map->vaddr, 5155 &hscb_map->dmasegs, hscb_map->nseg); 5156 free(hscb_map, M_DEVBUF); 5157 } 5158 /* FALLTHROUGH */ 5159 } 5160 case 0: 5161 break; 5162 } 5163 } 5164 5165 /* 5166 * DSP filter Bypass must be enabled until the first selection 5167 * after a change in bus mode (Razor #491 and #493). 5168 */ 5169 static void 5170 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5171 { 5172 ahd_mode_state saved_modes; 5173 5174 saved_modes = ahd_save_modes(ahd); 5175 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5176 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5177 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5178 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5179 #ifdef AHD_DEBUG 5180 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5181 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5182 #endif 5183 ahd_restore_modes(ahd, saved_modes); 5184 } 5185 5186 static void 5187 ahd_iocell_first_selection(struct ahd_softc *ahd) 5188 { 5189 ahd_mode_state saved_modes; 5190 u_int sblkctl; 5191 5192 saved_modes = ahd_save_modes(ahd); 5193 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5194 sblkctl = ahd_inb(ahd, SBLKCTL); 5195 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5196 #ifdef AHD_DEBUG 5197 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5198 printf("%s: iocell first selection\n", ahd_name(ahd)); 5199 #endif 5200 if ((sblkctl & ENAB40) != 0) { 5201 ahd_outb(ahd, DSPDATACTL, 5202 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5203 #ifdef AHD_DEBUG 5204 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5205 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5206 #endif 5207 } 5208 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5209 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5210 ahd_restore_modes(ahd, saved_modes); 5211 } 5212 5213 /*************************** SCB Management ***********************************/ 5214 static void 5215 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5216 { 5217 struct scb_list *free_list; 5218 struct scb_tailq *free_tailq; 5219 struct scb *first_scb; 5220 5221 scb->flags |= SCB_ON_COL_LIST; 5222 AHD_SET_SCB_COL_IDX(scb, col_idx); 5223 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5224 free_tailq = &ahd->scb_data.free_scbs; 5225 first_scb = LIST_FIRST(free_list); 5226 if (first_scb != NULL) { 5227 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5228 } else { 5229 LIST_INSERT_HEAD(free_list, scb, collision_links); 5230 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5231 } 5232 } 5233 5234 static void 5235 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5236 { 5237 struct scb_list *free_list; 5238 struct scb_tailq *free_tailq; 5239 struct scb *first_scb; 5240 u_int col_idx; 5241 5242 scb->flags &= ~SCB_ON_COL_LIST; 5243 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5244 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5245 free_tailq = &ahd->scb_data.free_scbs; 5246 first_scb = LIST_FIRST(free_list); 5247 if (first_scb == scb) { 5248 struct scb *next_scb; 5249 5250 /* 5251 * Maintain order in the collision free 5252 * lists for fairness if this device has 5253 * other colliding tags active. 5254 */ 5255 next_scb = LIST_NEXT(scb, collision_links); 5256 if (next_scb != NULL) { 5257 TAILQ_INSERT_AFTER(free_tailq, scb, 5258 next_scb, links.tqe); 5259 } 5260 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5261 } 5262 LIST_REMOVE(scb, collision_links); 5263 } 5264 5265 /* 5266 * Get a free scb. If there are none, see if we can allocate a new SCB. 5267 */ 5268 struct scb * 5269 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5270 { 5271 struct scb *scb; 5272 int tries; 5273 5274 tries = 0; 5275 look_again: 5276 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5277 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5278 ahd_rem_col_list(ahd, scb); 5279 goto found; 5280 } 5281 } 5282 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5283 5284 if (tries++ != 0) 5285 return (NULL); 5286 ahd_alloc_scbs(ahd); 5287 goto look_again; 5288 } 5289 LIST_REMOVE(scb, links.le); 5290 if (col_idx != AHD_NEVER_COL_IDX 5291 && (scb->col_scb != NULL) 5292 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5293 LIST_REMOVE(scb->col_scb, links.le); 5294 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5295 } 5296 found: 5297 scb->flags |= SCB_ACTIVE; 5298 return (scb); 5299 } 5300 5301 /* 5302 * Return an SCB resource to the free list. 5303 */ 5304 void 5305 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5306 { 5307 5308 /* Clean up for the next user */ 5309 scb->flags = SCB_FLAG_NONE; 5310 scb->hscb->control = 0; 5311 ahd->scb_data.scbindex[scb->hscb->tag] = NULL; 5312 5313 if (scb->col_scb == NULL) { 5314 5315 /* 5316 * No collision possible. Just free normally. 5317 */ 5318 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5319 scb, links.le); 5320 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5321 5322 /* 5323 * The SCB we might have collided with is on 5324 * a free collision list. Put both SCBs on 5325 * the generic list. 5326 */ 5327 ahd_rem_col_list(ahd, scb->col_scb); 5328 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5329 scb, links.le); 5330 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5331 scb->col_scb, links.le); 5332 } else if ((scb->col_scb->flags 5333 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5334 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5335 5336 /* 5337 * The SCB we might collide with on the next allocation 5338 * is still active in a non-packetized, tagged, context. 5339 * Put us on the SCB collision list. 5340 */ 5341 ahd_add_col_list(ahd, scb, 5342 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5343 } else { 5344 /* 5345 * The SCB we might collide with on the next allocation 5346 * is either active in a packetized context, or free. 5347 * Since we can't collide, put this SCB on the generic 5348 * free list. 5349 */ 5350 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5351 scb, links.le); 5352 } 5353 5354 ahd_platform_scb_free(ahd, scb); 5355 } 5356 5357 void 5358 ahd_alloc_scbs(struct ahd_softc *ahd) 5359 { 5360 struct scb_data *scb_data; 5361 struct scb *next_scb; 5362 struct hardware_scb *hscb; 5363 struct map_node *hscb_map; 5364 struct map_node *sg_map; 5365 struct map_node *sense_map; 5366 uint8_t *segs; 5367 uint8_t *sense_data; 5368 bus_addr_t hscb_busaddr; 5369 bus_addr_t sg_busaddr; 5370 bus_addr_t sense_busaddr; 5371 int newcount; 5372 int i; 5373 5374 scb_data = &ahd->scb_data; 5375 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5376 /* Can't allocate any more */ 5377 return; 5378 5379 if (scb_data->scbs_left != 0) { 5380 int offset; 5381 5382 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5383 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5384 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5385 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5386 } else { 5387 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5388 5389 if (hscb_map == NULL) 5390 return; 5391 5392 memset(hscb_map, 0, sizeof(*hscb_map)); 5393 5394 /* Allocate the next batch of hardware SCBs */ 5395 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5396 &hscb_map->dmamap, (caddr_t *)&hscb_map->vaddr, 5397 &hscb_map->physaddr, &hscb_map->dmasegs, 5398 &hscb_map->nseg, ahd_name(ahd), 5399 "hardware SCB structures") < 0) { 5400 free(hscb_map, M_DEVBUF); 5401 return; 5402 } 5403 5404 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5405 5406 hscb = (struct hardware_scb *)hscb_map->vaddr; 5407 hscb_busaddr = hscb_map->physaddr; 5408 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5409 } 5410 5411 scb_data->init_level++; 5412 5413 if (scb_data->sgs_left != 0) { 5414 int offset; 5415 5416 offset = ahd_sglist_allocsize(ahd) 5417 - (scb_data->sgs_left * ahd_sglist_size(ahd)); 5418 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5419 segs = sg_map->vaddr + offset; 5420 sg_busaddr = sg_map->physaddr + offset; 5421 } else { 5422 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5423 5424 if (sg_map == NULL) 5425 return; 5426 5427 bzero(sg_map, sizeof(*sg_map)); 5428 5429 /* Allocate the next batch of S/G lists */ 5430 if (ahd_createdmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), ahd->sc_dmaflags, 5431 &sg_map->dmamap, (caddr_t *)&sg_map->vaddr, 5432 &sg_map->physaddr, &sg_map->dmasegs, 5433 &sg_map->nseg, ahd_name(ahd), 5434 "SG data structures") < 0) { 5435 free(sg_map, M_DEVBUF); 5436 return; 5437 } 5438 5439 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5440 5441 segs = sg_map->vaddr; 5442 sg_busaddr = sg_map->physaddr; 5443 scb_data->sgs_left = 5444 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5445 #ifdef AHD_DEBUG 5446 if (ahd_debug & AHD_SHOW_MEMORY) 5447 printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd)); 5448 #endif 5449 } 5450 5451 scb_data->init_level++; 5452 5453 5454 if (scb_data->sense_left != 0) { 5455 int offset; 5456 5457 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5458 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5459 sense_data = sense_map->vaddr + offset; 5460 sense_busaddr = sense_map->physaddr + offset; 5461 } else { 5462 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5463 5464 if (sense_map == NULL) 5465 return; 5466 5467 bzero(sense_map, sizeof(*sense_map)); 5468 5469 /* Allocate the next batch of sense buffers */ 5470 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5471 &sense_map->dmamap, (caddr_t *)&sense_map->vaddr, 5472 &sense_map->physaddr, &sense_map->dmasegs, 5473 &sense_map->nseg, ahd_name(ahd), 5474 "Sense Data structures") < 0) { 5475 free(sense_map, M_DEVBUF); 5476 return; 5477 } 5478 5479 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5480 5481 sense_data = sense_map->vaddr; 5482 sense_busaddr = sense_map->physaddr; 5483 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5484 #ifdef AHD_DEBUG 5485 if (ahd_debug & AHD_SHOW_MEMORY) 5486 printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd)); 5487 #endif 5488 } 5489 5490 scb_data->init_level++; 5491 5492 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5493 newcount = MIN(newcount, scb_data->sgs_left); 5494 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5495 scb_data->sense_left -= newcount; 5496 scb_data->scbs_left -= newcount; 5497 scb_data->sgs_left -= newcount; 5498 5499 for (i = 0; i < newcount; i++) { 5500 u_int col_tag; 5501 5502 struct scb_platform_data *pdata; 5503 #ifndef __linux__ 5504 int error; 5505 #endif 5506 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5507 M_DEVBUF, M_NOWAIT); 5508 if (next_scb == NULL) 5509 break; 5510 5511 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5512 M_DEVBUF, M_NOWAIT); 5513 if (pdata == NULL) { 5514 free(next_scb, M_DEVBUF); 5515 break; 5516 } 5517 next_scb->platform_data = pdata; 5518 next_scb->hscb_map = hscb_map; 5519 next_scb->sg_map = sg_map; 5520 next_scb->sense_map = sense_map; 5521 next_scb->sg_list = segs; 5522 next_scb->sense_data = sense_data; 5523 next_scb->sense_busaddr = sense_busaddr; 5524 next_scb->hscb = hscb; 5525 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5526 5527 /* 5528 * The sequencer always starts with the second entry. 5529 * The first entry is embedded in the scb. 5530 */ 5531 next_scb->sg_list_busaddr = sg_busaddr; 5532 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5533 next_scb->sg_list_busaddr 5534 += sizeof(struct ahd_dma64_seg); 5535 else 5536 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5537 next_scb->ahd_softc = ahd; 5538 next_scb->flags = SCB_FLAG_NONE; 5539 5540 error = bus_dmamap_create(ahd->parent_dmat, 5541 AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0, 5542 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahd->sc_dmaflags, 5543 &next_scb->dmamap); 5544 if (error != 0) { 5545 free(next_scb, M_DEVBUF); 5546 free(pdata, M_DEVBUF); 5547 break; 5548 } 5549 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5550 col_tag = scb_data->numscbs ^ 0x100; 5551 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5552 if (next_scb->col_scb != NULL) 5553 next_scb->col_scb->col_scb = next_scb; 5554 ahd_free_scb(ahd, next_scb); 5555 hscb++; 5556 hscb_busaddr += sizeof(*hscb); 5557 segs += ahd_sglist_size(ahd); 5558 sg_busaddr += ahd_sglist_size(ahd); 5559 sense_data += AHD_SENSE_BUFSIZE; 5560 sense_busaddr += AHD_SENSE_BUFSIZE; 5561 scb_data->numscbs++; 5562 } 5563 } 5564 5565 void 5566 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5567 { 5568 const char *speed; 5569 const char *type; 5570 int len; 5571 5572 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5573 buf += len; 5574 5575 speed = "Ultra320 "; 5576 if ((ahd->features & AHD_WIDE) != 0) { 5577 type = "Wide "; 5578 } else { 5579 type = "Single "; 5580 } 5581 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5582 speed, type, ahd->channel, ahd->our_id); 5583 buf += len; 5584 5585 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5586 ahd->scb_data.maxhscbs); 5587 } 5588 5589 static const char *channel_strings[] = { 5590 "Primary Low", 5591 "Primary High", 5592 "Secondary Low", 5593 "Secondary High" 5594 }; 5595 5596 static const char *termstat_strings[] = { 5597 "Terminated Correctly", 5598 "Over Terminated", 5599 "Under Terminated", 5600 "Not Configured" 5601 }; 5602 5603 /* 5604 * Start the board, ready for normal operation 5605 */ 5606 int 5607 ahd_init(struct ahd_softc *ahd) 5608 { 5609 uint8_t *next_vaddr; 5610 bus_addr_t next_baddr; 5611 size_t driver_data_size; 5612 int i; 5613 int error; 5614 u_int warn_user; 5615 uint8_t current_sensing; 5616 uint8_t fstat; 5617 5618 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5619 5620 ahd->stack_size = ahd_probe_stack_size(ahd); 5621 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5622 M_DEVBUF, M_NOWAIT); 5623 if (ahd->saved_stack == NULL) 5624 return (ENOMEM); 5625 /* Zero the memory */ 5626 memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); 5627 5628 /* 5629 * Verify that the compiler hasn't over-agressively 5630 * padded important structures. 5631 */ 5632 if (sizeof(struct hardware_scb) != 64) 5633 panic("Hardware SCB size is incorrect"); 5634 5635 #ifdef AHD_DEBUG 5636 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5637 ahd->flags |= AHD_SEQUENCER_DEBUG; 5638 #endif 5639 5640 /* 5641 * Default to allowing initiator operations. 5642 */ 5643 ahd->flags |= AHD_INITIATORROLE; 5644 5645 /* 5646 * Only allow target mode features if this unit has them enabled. 5647 */ 5648 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5649 ahd->features &= ~AHD_TARGETMODE; 5650 5651 /* 5652 * DMA tag for our command fifos and other data in system memory 5653 * the card's sequencer must be able to access. For initiator 5654 * roles, we need to allocate space for the qoutfifo. When providing 5655 * for the target mode role, we must additionally provide space for 5656 * the incoming target command fifo. 5657 */ 5658 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5659 + sizeof(struct hardware_scb); 5660 if ((ahd->features & AHD_TARGETMODE) != 0) 5661 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5662 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5663 driver_data_size += PKT_OVERRUN_BUFSIZE; 5664 ahd->shared_data_size = driver_data_size; 5665 5666 memset(&ahd->shared_data_dmamap, 0, sizeof(bus_dmamap_t)); 5667 memset(&ahd->shared_data_busaddr, 0, sizeof(bus_addr_t)); 5668 memset(&ahd->shared_data_seg, 0, sizeof(bus_dma_segment_t)); 5669 ahd->shared_data_nseg = 0; 5670 ahd->sc_dmaflags = BUS_DMA_NOWAIT; 5671 5672 if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 5673 ahd->sc_dmaflags, 5674 &ahd->shared_data_dmamap, (caddr_t *)&ahd->qoutfifo, 5675 &ahd->shared_data_busaddr, &ahd->shared_data_seg, 5676 &ahd->shared_data_nseg, ahd_name(ahd), "shared data") < 0) 5677 return (ENOMEM); 5678 5679 ahd->init_level++; 5680 5681 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5682 next_baddr = ahd->shared_data_busaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5683 if ((ahd->features & AHD_TARGETMODE) != 0) { 5684 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5685 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5686 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5687 } 5688 5689 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5690 ahd->overrun_buf = next_vaddr; 5691 next_vaddr += PKT_OVERRUN_BUFSIZE; 5692 next_baddr += PKT_OVERRUN_BUFSIZE; 5693 } 5694 5695 /* 5696 * We need one SCB to serve as the "next SCB". Since the 5697 * tag identifier in this SCB will never be used, there is 5698 * no point in using a valid HSCB tag from an SCB pulled from 5699 * the standard free pool. So, we allocate this "sentinel" 5700 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5701 */ 5702 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5703 ahd->next_queued_hscb->hscb_busaddr = next_baddr; 5704 5705 memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 5706 5707 /* Allocate SCB data now that parent_dmat is initialized */ 5708 if (ahd_init_scbdata(ahd) != 0) 5709 return (ENOMEM); 5710 5711 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5712 ahd->flags &= ~AHD_RESET_BUS_A; 5713 5714 /* 5715 * Before committing these settings to the chip, give 5716 * the OSM one last chance to modify our configuration. 5717 */ 5718 ahd_platform_init(ahd); 5719 5720 /* Bring up the chip. */ 5721 ahd_chip_init(ahd); 5722 5723 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5724 5725 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5726 goto init_done; 5727 5728 /* 5729 * Verify termination based on current draw and 5730 * warn user if the bus is over/under terminated. 5731 */ 5732 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5733 CURSENSE_ENB); 5734 if (error != 0) { 5735 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5736 goto init_done; 5737 } 5738 for (i = 20, fstat = FLX_FSTAT_BUSY; 5739 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5740 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5741 if (error != 0) { 5742 printf("%s: current sensing timeout 2\n", 5743 ahd_name(ahd)); 5744 goto init_done; 5745 } 5746 } 5747 if (i == 0) { 5748 printf("%s: Timedout during current-sensing test\n", 5749 ahd_name(ahd)); 5750 goto init_done; 5751 } 5752 5753 /* Latch Current Sensing status. */ 5754 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5755 if (error != 0) { 5756 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5757 goto init_done; 5758 } 5759 5760 /* Diable current sensing. */ 5761 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5762 5763 #ifdef AHD_DEBUG 5764 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5765 printf("%s: current_sensing == 0x%x\n", 5766 ahd_name(ahd), current_sensing); 5767 } 5768 #endif 5769 warn_user = 0; 5770 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5771 u_int term_stat; 5772 5773 term_stat = (current_sensing & FLX_CSTAT_MASK); 5774 switch (term_stat) { 5775 case FLX_CSTAT_OVER: 5776 case FLX_CSTAT_UNDER: 5777 warn_user++; 5778 case FLX_CSTAT_INVALID: 5779 case FLX_CSTAT_OKAY: 5780 if (warn_user == 0 && bootverbose == 0) 5781 break; 5782 printf("%s: %s Channel %s\n", ahd_name(ahd), 5783 channel_strings[i], termstat_strings[term_stat]); 5784 break; 5785 } 5786 } 5787 if (warn_user) { 5788 printf("%s: WARNING. Termination is not configured correctly.\n" 5789 "%s: WARNING. SCSI bus operations may FAIL.\n", 5790 ahd_name(ahd), ahd_name(ahd)); 5791 } 5792 init_done: 5793 ahd_reset_current_bus(ahd); 5794 ahd_restart(ahd); 5795 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5796 ahd_stat_timer, ahd); 5797 5798 /* We have to wait until after any system dumps... */ 5799 ahd->shutdown_hook = shutdownhook_establish(ahd_shutdown, ahd); 5800 5801 return (0); 5802 } 5803 5804 /* 5805 * (Re)initialize chip state after a chip reset. 5806 */ 5807 static void 5808 ahd_chip_init(struct ahd_softc *ahd) 5809 { 5810 uint32_t busaddr; 5811 u_int sxfrctl1; 5812 u_int scsiseq_template; 5813 u_int wait; 5814 u_int i; 5815 u_int target; 5816 5817 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5818 /* 5819 * Take the LED out of diagnostic mode 5820 */ 5821 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 5822 5823 /* 5824 * Return HS_MAILBOX to its default value. 5825 */ 5826 ahd->hs_mailbox = 0; 5827 ahd_outb(ahd, HS_MAILBOX, 0); 5828 5829 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 5830 ahd_outb(ahd, IOWNID, ahd->our_id); 5831 ahd_outb(ahd, TOWNID, ahd->our_id); 5832 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 5833 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 5834 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 5835 && (ahd->seltime != STIMESEL_MIN)) { 5836 /* 5837 * The selection timer duration is twice as long 5838 * as it should be. Halve it by adding "1" to 5839 * the user specified setting. 5840 */ 5841 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 5842 } else { 5843 sxfrctl1 |= ahd->seltime; 5844 } 5845 5846 ahd_outb(ahd, SXFRCTL0, DFON); 5847 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 5848 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5849 5850 /* 5851 * Now that termination is set, wait for up 5852 * to 500ms for our transceivers to settle. If 5853 * the adapter does not have a cable attached, 5854 * the tranceivers may never settle, so don't 5855 * complain if we fail here. 5856 */ 5857 for (wait = 10000; 5858 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 5859 wait--) 5860 ahd_delay(100); 5861 5862 /* Clear any false bus resets due to the transceivers settling */ 5863 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 5864 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5865 5866 /* Initialize mode specific S/G state. */ 5867 for (i = 0; i < 2; i++) { 5868 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 5869 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 5870 ahd_outw(ahd, LONGJMP_SCB, SCB_LIST_NULL); 5871 ahd_outb(ahd, SG_STATE, 0); 5872 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 5873 ahd_outb(ahd, SEQIMODE, 5874 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 5875 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 5876 } 5877 5878 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5879 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 5880 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 5881 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 5882 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 5883 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 5884 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 5885 } else { 5886 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 5887 } 5888 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 5889 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 5890 /* 5891 * Do not issue a target abort when a split completion 5892 * error occurs. Let our PCIX interrupt handler deal 5893 * with it instead. H2A4 Razor #625 5894 */ 5895 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 5896 5897 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 5898 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 5899 5900 /* 5901 * Tweak IOCELL settings. 5902 */ 5903 if ((ahd->flags & AHD_HP_BOARD) != 0) { 5904 for (i = 0; i < NUMDSPS; i++) { 5905 ahd_outb(ahd, DSPSELECT, i); 5906 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 5907 } 5908 #ifdef AHD_DEBUG 5909 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5910 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 5911 WRTBIASCTL_HP_DEFAULT); 5912 #endif 5913 } 5914 ahd_setup_iocell_workaround(ahd); 5915 5916 /* 5917 * Enable LQI Manager interrupts. 5918 */ 5919 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 5920 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 5921 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 5922 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 5923 /* 5924 * An interrupt from LQOBUSFREE is made redundant by the 5925 * BUSFREE interrupt. We choose to have the sequencer catch 5926 * LQOPHCHGINPKT errors manually for the command phase at the 5927 * start of a packetized selection case. 5928 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 5929 */ 5930 ahd_outb(ahd, LQOMODE1, 0); 5931 5932 /* 5933 * Setup sequencer interrupt handlers. 5934 */ 5935 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 5936 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 5937 5938 /* 5939 * Setup SCB Offset registers. 5940 */ 5941 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 5942 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 5943 pkt_long_lun)); 5944 } else { 5945 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 5946 } 5947 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 5948 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 5949 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 5950 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 5951 shared_data.idata.cdb)); 5952 ahd_outb(ahd, QNEXTPTR, 5953 offsetof(struct hardware_scb, next_hscb_busaddr)); 5954 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 5955 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 5956 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 5957 ahd_outb(ahd, LUNLEN, 5958 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 5959 } else { 5960 ahd_outb(ahd, LUNLEN, sizeof(ahd->next_queued_hscb->lun) - 1); 5961 } 5962 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 5963 ahd_outb(ahd, MAXCMD, 0xFF); 5964 ahd_outb(ahd, SCBAUTOPTR, 5965 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 5966 5967 /* We haven't been enabled for target mode yet. */ 5968 ahd_outb(ahd, MULTARGID, 0); 5969 ahd_outb(ahd, MULTARGID + 1, 0); 5970 5971 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5972 /* Initialize the negotiation table. */ 5973 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 5974 /* 5975 * Clear the spare bytes in the neg table to avoid 5976 * spurious parity errors. 5977 */ 5978 for (target = 0; target < AHD_NUM_TARGETS; target++) { 5979 ahd_outb(ahd, NEGOADDR, target); 5980 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 5981 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 5982 ahd_outb(ahd, ANNEXDAT, 0); 5983 } 5984 } 5985 5986 for (target = 0; target < AHD_NUM_TARGETS; target++) { 5987 struct ahd_devinfo devinfo; 5988 struct ahd_initiator_tinfo *tinfo; 5989 struct ahd_tmode_tstate *tstate; 5990 5991 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 5992 target, &tstate); 5993 ahd_compile_devinfo(&devinfo, ahd->our_id, 5994 target, CAM_LUN_WILDCARD, 5995 'A', ROLE_INITIATOR); 5996 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 5997 } 5998 5999 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6000 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6001 6002 /* 6003 * Always enable abort on incoming L_Qs if this feature is 6004 * supported. We use this to catch invalid SCB references. 6005 */ 6006 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6007 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6008 else 6009 ahd_outb(ahd, LQCTL1, 0); 6010 6011 /* All of our queues are empty */ 6012 ahd->qoutfifonext = 0; 6013 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6014 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6015 for (i = 0; i < AHD_QOUT_SIZE; i++) 6016 ahd->qoutfifo[i] = 0; 6017 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6018 6019 ahd->qinfifonext = 0; 6020 for (i = 0; i < AHD_QIN_SIZE; i++) 6021 ahd->qinfifo[i] = SCB_LIST_NULL; 6022 6023 if ((ahd->features & AHD_TARGETMODE) != 0) { 6024 /* All target command blocks start out invalid. */ 6025 for (i = 0; i < AHD_TMODE_CMDS; i++) 6026 ahd->targetcmds[i].cmd_valid = 0; 6027 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6028 ahd->tqinfifonext = 1; 6029 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6030 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6031 } 6032 6033 /* Initialize Scratch Ram. */ 6034 ahd_outb(ahd, SEQ_FLAGS, 0); 6035 ahd_outb(ahd, SEQ_FLAGS2, 0); 6036 6037 /* We don't have any waiting selections */ 6038 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6039 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6040 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6041 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6042 } 6043 6044 /* 6045 * Nobody is waiting to be DMAed into the QOUTFIFO. 6046 */ 6047 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6048 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6049 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6050 6051 /* 6052 * The Freeze Count is 0. 6053 */ 6054 ahd_outw(ahd, QFREEZE_COUNT, 0); 6055 6056 /* 6057 * Tell the sequencer where it can find our arrays in memory. 6058 */ 6059 busaddr = ahd->shared_data_busaddr; 6060 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6061 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6062 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6063 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6064 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6065 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6066 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6067 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6068 /* 6069 * Setup the allowed SCSI Sequences based on operational mode. 6070 * If we are a target, we'll enable select in operations once 6071 * we've had a lun enabled. 6072 */ 6073 scsiseq_template = ENAUTOATNP; 6074 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6075 scsiseq_template |= ENRSELI; 6076 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6077 6078 /* There are no busy SCBs yet. */ 6079 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6080 int lun; 6081 6082 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6083 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6084 } 6085 6086 /* 6087 * Initialize the group code to command length table. 6088 * Vendor Unique codes are set to 0 so we only capture 6089 * the first byte of the cdb. These can be overridden 6090 * when target mode is enabled. 6091 */ 6092 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6093 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6094 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6095 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6096 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6097 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6098 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6099 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6100 6101 /* Tell the sequencer of our initial queue positions */ 6102 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6103 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6104 ahd->qinfifonext = 0; 6105 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6106 ahd_set_hescb_qoff(ahd, 0); 6107 ahd_set_snscb_qoff(ahd, 0); 6108 ahd_set_sescb_qoff(ahd, 0); 6109 ahd_set_sdscb_qoff(ahd, 0); 6110 6111 /* 6112 * Tell the sequencer which SCB will be the next one it receives. 6113 */ 6114 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6115 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6116 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6117 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6118 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6119 6120 /* 6121 * Default to coalessing disabled. 6122 */ 6123 ahd_outw(ahd, INT_COALESSING_CMDCOUNT, 0); 6124 ahd_outw(ahd, CMDS_PENDING, 0); 6125 ahd_update_coalessing_values(ahd, ahd->int_coalessing_timer, 6126 ahd->int_coalessing_maxcmds, 6127 ahd->int_coalessing_mincmds); 6128 ahd_enable_coalessing(ahd, FALSE); 6129 6130 ahd_loadseq(ahd); 6131 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6132 } 6133 6134 /* 6135 * Setup default device and controller settings. 6136 * This should only be called if our probe has 6137 * determined that no configuration data is available. 6138 */ 6139 int 6140 ahd_default_config(struct ahd_softc *ahd) 6141 { 6142 int targ; 6143 6144 ahd->our_id = 7; 6145 6146 /* 6147 * Allocate a tstate to house information for our 6148 * initiator presence on the bus as well as the user 6149 * data for any target mode initiator. 6150 */ 6151 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6152 printf("%s: unable to allocate ahd_tmode_tstate. " 6153 "Failing attach\n", ahd_name(ahd)); 6154 return (ENOMEM); 6155 } 6156 6157 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6158 struct ahd_devinfo devinfo; 6159 struct ahd_initiator_tinfo *tinfo; 6160 struct ahd_tmode_tstate *tstate; 6161 uint16_t target_mask; 6162 6163 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6164 targ, &tstate); 6165 /* 6166 * We support SPC2 and SPI4. 6167 */ 6168 tinfo->user.protocol_version = 4; 6169 tinfo->user.transport_version = 4; 6170 6171 target_mask = 0x01 << targ; 6172 ahd->user_discenable |= target_mask; 6173 tstate->discenable |= target_mask; 6174 ahd->user_tagenable |= target_mask; 6175 #ifdef AHD_FORCE_160 6176 tinfo->user.period = AHD_SYNCRATE_DT; 6177 #else 6178 tinfo->user.period = AHD_SYNCRATE_160; 6179 #endif 6180 tinfo->user.offset= MAX_OFFSET; 6181 tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6182 | MSG_EXT_PPR_WRFLOW 6183 | MSG_EXT_PPR_HOLDMCS 6184 | MSG_EXT_PPR_IU_REQ 6185 | MSG_EXT_PPR_QAS_REQ 6186 | MSG_EXT_PPR_DT_REQ; 6187 if ((ahd->features & AHD_RTI) != 0) 6188 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6189 6190 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6191 6192 /* 6193 * Start out Async/Narrow/Untagged and with 6194 * conservative protocol support. 6195 */ 6196 tinfo->goal.protocol_version = 2; 6197 tinfo->goal.transport_version = 2; 6198 tinfo->curr.protocol_version = 2; 6199 tinfo->curr.transport_version = 2; 6200 ahd_compile_devinfo(&devinfo, ahd->our_id, 6201 targ, CAM_LUN_WILDCARD, 6202 'A', ROLE_INITIATOR); 6203 tstate->tagenable &= ~target_mask; 6204 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6205 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6206 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6207 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6208 /*paused*/TRUE); 6209 } 6210 return (0); 6211 } 6212 6213 /* 6214 * Parse device configuration information. 6215 */ 6216 int 6217 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6218 { 6219 int targ; 6220 int max_targ; 6221 6222 max_targ = sc->max_targets & CFMAXTARG; 6223 ahd->our_id = sc->brtime_id & CFSCSIID; 6224 6225 /* 6226 * Allocate a tstate to house information for our 6227 * initiator presence on the bus as well as the user 6228 * data for any target mode initiator. 6229 */ 6230 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6231 printf("%s: unable to allocate ahd_tmode_tstate. " 6232 "Failing attach\n", ahd_name(ahd)); 6233 return (ENOMEM); 6234 } 6235 6236 for (targ = 0; targ < max_targ; targ++) { 6237 struct ahd_devinfo devinfo; 6238 struct ahd_initiator_tinfo *tinfo; 6239 struct ahd_transinfo *user_tinfo; 6240 struct ahd_tmode_tstate *tstate; 6241 uint16_t target_mask; 6242 6243 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6244 targ, &tstate); 6245 user_tinfo = &tinfo->user; 6246 6247 /* 6248 * We support SPC2 and SPI4. 6249 */ 6250 tinfo->user.protocol_version = 4; 6251 tinfo->user.transport_version = 4; 6252 6253 target_mask = 0x01 << targ; 6254 ahd->user_discenable &= ~target_mask; 6255 tstate->discenable &= ~target_mask; 6256 ahd->user_tagenable &= ~target_mask; 6257 if (sc->device_flags[targ] & CFDISC) { 6258 tstate->discenable |= target_mask; 6259 ahd->user_discenable |= target_mask; 6260 ahd->user_tagenable |= target_mask; 6261 } else { 6262 /* 6263 * Cannot be packetized without disconnection. 6264 */ 6265 sc->device_flags[targ] &= ~CFPACKETIZED; 6266 } 6267 6268 user_tinfo->ppr_options = 0; 6269 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6270 if (user_tinfo->period < CFXFER_ASYNC) { 6271 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6272 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6273 user_tinfo->offset = MAX_OFFSET; 6274 } else { 6275 user_tinfo->offset = 0; 6276 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6277 } 6278 #ifdef AHD_FORCE_160 6279 if (user_tinfo->period <= AHD_SYNCRATE_160) 6280 user_tinfo->period = AHD_SYNCRATE_DT; 6281 #endif 6282 6283 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6284 user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6285 | MSG_EXT_PPR_WRFLOW 6286 | MSG_EXT_PPR_HOLDMCS 6287 | MSG_EXT_PPR_IU_REQ; 6288 if ((ahd->features & AHD_RTI) != 0) 6289 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6290 } 6291 6292 if ((sc->device_flags[targ] & CFQAS) != 0) 6293 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6294 6295 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6296 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6297 else 6298 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6299 #ifdef AHD_DEBUG 6300 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6301 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6302 user_tinfo->period, user_tinfo->offset, 6303 user_tinfo->ppr_options); 6304 #endif 6305 /* 6306 * Start out Async/Narrow/Untagged and with 6307 * conservative protocol support. 6308 */ 6309 tstate->tagenable &= ~target_mask; 6310 tinfo->goal.protocol_version = 2; 6311 tinfo->goal.transport_version = 2; 6312 tinfo->curr.protocol_version = 2; 6313 tinfo->curr.transport_version = 2; 6314 ahd_compile_devinfo(&devinfo, ahd->our_id, 6315 targ, CAM_LUN_WILDCARD, 6316 'A', ROLE_INITIATOR); 6317 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6318 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6319 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6320 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6321 /*paused*/TRUE); 6322 } 6323 6324 ahd->flags &= ~AHD_SPCHK_ENB_A; 6325 if (sc->bios_control & CFSPARITY) 6326 ahd->flags |= AHD_SPCHK_ENB_A; 6327 6328 ahd->flags &= ~AHD_RESET_BUS_A; 6329 if (sc->bios_control & CFRESETB) 6330 ahd->flags |= AHD_RESET_BUS_A; 6331 6332 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6333 if (sc->bios_control & CFEXTEND) 6334 ahd->flags |= AHD_EXTENDED_TRANS_A; 6335 6336 ahd->flags &= ~AHD_BIOS_ENABLED; 6337 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6338 ahd->flags |= AHD_BIOS_ENABLED; 6339 6340 ahd->flags &= ~AHD_STPWLEVEL_A; 6341 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6342 ahd->flags |= AHD_STPWLEVEL_A; 6343 6344 return (0); 6345 } 6346 6347 void 6348 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6349 { 6350 u_int hcntrl; 6351 6352 hcntrl = ahd_inb(ahd, HCNTRL); 6353 hcntrl &= ~INTEN; 6354 ahd->pause &= ~INTEN; 6355 ahd->unpause &= ~INTEN; 6356 if (enable) { 6357 hcntrl |= INTEN; 6358 ahd->pause |= INTEN; 6359 ahd->unpause |= INTEN; 6360 } 6361 ahd_outb(ahd, HCNTRL, hcntrl); 6362 } 6363 6364 void 6365 ahd_update_coalessing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6366 u_int mincmds) 6367 { 6368 if (timer > AHD_TIMER_MAX_US) 6369 timer = AHD_TIMER_MAX_US; 6370 ahd->int_coalessing_timer = timer; 6371 6372 if (maxcmds > AHD_INT_COALESSING_MAXCMDS_MAX) 6373 maxcmds = AHD_INT_COALESSING_MAXCMDS_MAX; 6374 if (mincmds > AHD_INT_COALESSING_MINCMDS_MAX) 6375 mincmds = AHD_INT_COALESSING_MINCMDS_MAX; 6376 ahd->int_coalessing_maxcmds = maxcmds; 6377 ahd_outw(ahd, INT_COALESSING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6378 ahd_outb(ahd, INT_COALESSING_MAXCMDS, -maxcmds); 6379 ahd_outb(ahd, INT_COALESSING_MINCMDS, -mincmds); 6380 } 6381 6382 void 6383 ahd_enable_coalessing(struct ahd_softc *ahd, int enable) 6384 { 6385 6386 ahd->hs_mailbox &= ~ENINT_COALESS; 6387 if (enable) 6388 ahd->hs_mailbox |= ENINT_COALESS; 6389 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6390 ahd_flush_device_writes(ahd); 6391 ahd_run_qoutfifo(ahd); 6392 } 6393 6394 /* 6395 * Ensure that the card is paused in a location 6396 * outside of all critical sections and that all 6397 * pending work is completed prior to returning. 6398 * This routine should only be called from outside 6399 * an interrupt context. 6400 */ 6401 void 6402 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6403 { 6404 ahd_mode_state saved_modes; 6405 u_int intstat; 6406 u_int maxloops; 6407 int paused; 6408 6409 maxloops = 1000; 6410 ahd->flags |= AHD_ALL_INTERRUPTS; 6411 paused = FALSE; 6412 do { 6413 struct scb *waiting_scb; 6414 6415 if (paused) 6416 ahd_unpause(ahd); 6417 ahd_intr(ahd); 6418 ahd_pause(ahd); 6419 paused = TRUE; 6420 ahd_clear_critical_section(ahd); 6421 saved_modes = ahd_save_modes(ahd); 6422 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6423 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6424 ahd_outb(ahd, SCSISEQ0, 6425 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6426 /* 6427 * In the non-packetized case, the sequencer (for Rev A), 6428 * relies on ENSELO remaining set after SELDO. The hardware 6429 * auto-clears ENSELO in the packetized case. 6430 */ 6431 waiting_scb = ahd_lookup_scb(ahd, 6432 ahd_inw(ahd, WAITING_TID_HEAD)); 6433 if (waiting_scb != NULL 6434 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6435 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6436 ahd_outb(ahd, SCSISEQ0, 6437 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6438 6439 intstat = ahd_inb(ahd, INTSTAT); 6440 } while (--maxloops 6441 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6442 && ((intstat & INT_PEND) != 0 6443 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)))); 6444 if (maxloops == 0) { 6445 printf("Infinite interrupt loop, INTSTAT = %x", 6446 ahd_inb(ahd, INTSTAT)); 6447 } 6448 6449 ahd_flush_qoutfifo(ahd); 6450 6451 ahd_platform_flushwork(ahd); 6452 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6453 ahd_restore_modes(ahd, saved_modes); 6454 } 6455 6456 int 6457 ahd_suspend(struct ahd_softc *ahd) 6458 { 6459 #if 0 6460 uint8_t *ptr; 6461 int i; 6462 6463 ahd_pause_and_flushwork(ahd); 6464 6465 if (LIST_FIRST(&ahd->pending_scbs) != NULL) 6466 return (EBUSY); 6467 6468 #if AHD_TARGET_MODE 6469 /* 6470 * XXX What about ATIOs that have not yet been serviced? 6471 * Perhaps we should just refuse to be suspended if we 6472 * are acting in a target role. 6473 */ 6474 if (ahd->pending_device != NULL) 6475 return (EBUSY); 6476 #endif 6477 6478 /* Save volatile registers */ 6479 ahd->suspend_state.channel[0].scsiseq = ahd_inb(ahd, SCSISEQ0); 6480 ahd->suspend_state.channel[0].sxfrctl0 = ahd_inb(ahd, SXFRCTL0); 6481 ahd->suspend_state.channel[0].sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 6482 ahd->suspend_state.channel[0].simode0 = ahd_inb(ahd, SIMODE0); 6483 ahd->suspend_state.channel[0].simode1 = ahd_inb(ahd, SIMODE1); 6484 ahd->suspend_state.channel[0].seltimer = ahd_inb(ahd, SELTIMER); 6485 ahd->suspend_state.channel[0].seqctl = ahd_inb(ahd, SEQCTL0); 6486 ahd->suspend_state.dscommand0 = ahd_inb(ahd, DSCOMMAND0); 6487 ahd->suspend_state.dspcistatus = ahd_inb(ahd, DSPCISTATUS); 6488 6489 if ((ahd->features & AHD_DT) != 0) { 6490 u_int sfunct; 6491 6492 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6493 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6494 ahd->suspend_state.optionmode = ahd_inb(ahd, OPTIONMODE); 6495 ahd_outb(ahd, SFUNCT, sfunct); 6496 ahd->suspend_state.crccontrol1 = ahd_inb(ahd, CRCCONTROL1); 6497 } 6498 6499 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6500 ahd->suspend_state.scbbaddr = ahd_inb(ahd, SCBBADDR); 6501 6502 if ((ahd->features & AHD_ULTRA2) != 0) 6503 ahd->suspend_state.dff_thrsh = ahd_inb(ahd, DFF_THRSH); 6504 6505 ptr = ahd->suspend_state.scratch_ram; 6506 for (i = 0; i < 64; i++) 6507 *ptr++ = ahd_inb(ahd, SRAM_BASE + i); 6508 6509 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6510 for (i = 0; i < 16; i++) 6511 *ptr++ = ahd_inb(ahd, TARG_OFFSET + i); 6512 } 6513 6514 ptr = ahd->suspend_state.btt; 6515 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6516 int j; 6517 6518 for (j = 0;j < AHD_NUM_LUNS_NONPKT; j++) { 6519 u_int tcl; 6520 6521 tcl = BUILD_TCL_RAW(i, 'A', j); 6522 *ptr = ahd_find_busy_tcl(ahd, tcl); 6523 } 6524 } 6525 ahd_shutdown(ahd); 6526 #endif 6527 return (0); 6528 } 6529 6530 int 6531 ahd_resume(struct ahd_softc *ahd) 6532 { 6533 #if 0 6534 uint8_t *ptr; 6535 int i; 6536 6537 ahd_reset(ahd); 6538 6539 ahd_build_free_scb_list(ahd); 6540 6541 /* Restore volatile registers */ 6542 ahd_outb(ahd, SCSISEQ0, ahd->suspend_state.channel[0].scsiseq); 6543 ahd_outb(ahd, SXFRCTL0, ahd->suspend_state.channel[0].sxfrctl0); 6544 ahd_outb(ahd, SXFRCTL1, ahd->suspend_state.channel[0].sxfrctl1); 6545 ahd_outb(ahd, SIMODE0, ahd->suspend_state.channel[0].simode0); 6546 ahd_outb(ahd, SIMODE1, ahd->suspend_state.channel[0].simode1); 6547 ahd_outb(ahd, SELTIMER, ahd->suspend_state.channel[0].seltimer); 6548 ahd_outb(ahd, SEQCTL0, ahd->suspend_state.channel[0].seqctl); 6549 if ((ahd->features & AHD_ULTRA2) != 0) 6550 ahd_outb(ahd, SCSIID_ULTRA2, ahd->our_id); 6551 else 6552 ahd_outb(ahd, SCSIID, ahd->our_id); 6553 6554 ahd_outb(ahd, DSCOMMAND0, ahd->suspend_state.dscommand0); 6555 ahd_outb(ahd, DSPCISTATUS, ahd->suspend_state.dspcistatus); 6556 6557 if ((ahd->features & AHD_DT) != 0) { 6558 u_int sfunct; 6559 6560 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6561 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6562 ahd_outb(ahd, OPTIONMODE, ahd->suspend_state.optionmode); 6563 ahd_outb(ahd, SFUNCT, sfunct); 6564 ahd_outb(ahd, CRCCONTROL1, ahd->suspend_state.crccontrol1); 6565 } 6566 6567 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6568 ahd_outb(ahd, SCBBADDR, ahd->suspend_state.scbbaddr); 6569 6570 if ((ahd->features & AHD_ULTRA2) != 0) 6571 ahd_outb(ahd, DFF_THRSH, ahd->suspend_state.dff_thrsh); 6572 6573 ptr = ahd->suspend_state.scratch_ram; 6574 for (i = 0; i < 64; i++) 6575 ahd_outb(ahd, SRAM_BASE + i, *ptr++); 6576 6577 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6578 for (i = 0; i < 16; i++) 6579 ahd_outb(ahd, TARG_OFFSET + i, *ptr++); 6580 } 6581 6582 ptr = ahd->suspend_state.btt; 6583 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6584 int j; 6585 6586 for (j = 0;j < AHD_NUM_LUNS; j++) { 6587 u_int tcl; 6588 6589 tcl = BUILD_TCL(i << 4, j); 6590 ahd_busy_tcl(ahd, tcl, *ptr); 6591 } 6592 } 6593 #endif 6594 return (0); 6595 } 6596 6597 /************************** Busy Target Table *********************************/ 6598 /* 6599 * Set SCBPTR to the SCB that contains the busy 6600 * table entry for TCL. Return the offset into 6601 * the SCB that contains the entry for TCL. 6602 * saved_scbid is dereferenced and set to the 6603 * scbid that should be restored once manipualtion 6604 * of the TCL entry is complete. 6605 */ 6606 static __inline u_int 6607 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6608 { 6609 /* 6610 * Index to the SCB that contains the busy entry. 6611 */ 6612 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6613 *saved_scbid = ahd_get_scbptr(ahd); 6614 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6615 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6616 6617 /* 6618 * And now calculate the SCB offset to the entry. 6619 * Each entry is 2 bytes wide, hence the 6620 * multiplication by 2. 6621 */ 6622 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6623 } 6624 6625 /* 6626 * Return the untagged transaction id for a given target/channel lun. 6627 * Optionally, clear the entry. 6628 */ 6629 u_int 6630 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6631 { 6632 u_int scbid; 6633 u_int scb_offset; 6634 u_int saved_scbptr; 6635 6636 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6637 scbid = ahd_inw_scbram(ahd, scb_offset); 6638 ahd_set_scbptr(ahd, saved_scbptr); 6639 return (scbid); 6640 } 6641 6642 void 6643 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6644 { 6645 u_int scb_offset; 6646 u_int saved_scbptr; 6647 6648 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6649 ahd_outw(ahd, scb_offset, scbid); 6650 ahd_set_scbptr(ahd, saved_scbptr); 6651 } 6652 6653 /************************** SCB and SCB queue management **********************/ 6654 int 6655 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6656 char channel, int lun, u_int tag, role_t role) 6657 { 6658 int targ = SCB_GET_TARGET(ahd, scb); 6659 char chan = SCB_GET_CHANNEL(ahd, scb); 6660 int slun = SCB_GET_LUN(scb); 6661 int match; 6662 6663 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6664 if (match != 0) 6665 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6666 if (match != 0) 6667 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6668 if (match != 0) { 6669 #if AHD_TARGET_MODE 6670 int group; 6671 6672 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6673 if (role == ROLE_INITIATOR) { 6674 match = (group != XPT_FC_GROUP_TMODE) 6675 && ((tag == SCB_GET_TAG(scb)) 6676 || (tag == SCB_LIST_NULL)); 6677 } else if (role == ROLE_TARGET) { 6678 match = (group == XPT_FC_GROUP_TMODE) 6679 && ((tag == scb->io_ctx->csio.tag_id) 6680 || (tag == SCB_LIST_NULL)); 6681 } 6682 #else /* !AHD_TARGET_MODE */ 6683 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6684 #endif /* AHD_TARGET_MODE */ 6685 } 6686 6687 return match; 6688 } 6689 6690 void 6691 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6692 { 6693 int target; 6694 char channel; 6695 int lun; 6696 6697 target = SCB_GET_TARGET(ahd, scb); 6698 lun = SCB_GET_LUN(scb); 6699 channel = SCB_GET_CHANNEL(ahd, scb); 6700 6701 ahd_search_qinfifo(ahd, target, channel, lun, 6702 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6703 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6704 6705 ahd_platform_freeze_devq(ahd, scb); 6706 } 6707 6708 void 6709 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6710 { 6711 struct scb *prev_scb; 6712 ahd_mode_state saved_modes; 6713 6714 saved_modes = ahd_save_modes(ahd); 6715 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6716 prev_scb = NULL; 6717 if (ahd_qinfifo_count(ahd) != 0) { 6718 u_int prev_tag; 6719 u_int prev_pos; 6720 6721 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6722 prev_tag = ahd->qinfifo[prev_pos]; 6723 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6724 } 6725 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6726 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6727 ahd_restore_modes(ahd, saved_modes); 6728 } 6729 6730 static void 6731 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6732 struct scb *scb) 6733 { 6734 if (prev_scb == NULL) { 6735 uint32_t busaddr; 6736 6737 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6738 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6739 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6740 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6741 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6742 } else { 6743 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6744 ahd_sync_scb(ahd, prev_scb, 6745 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6746 } 6747 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6748 ahd->qinfifonext++; 6749 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6750 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6751 } 6752 6753 static int 6754 ahd_qinfifo_count(struct ahd_softc *ahd) 6755 { 6756 u_int qinpos; 6757 u_int wrap_qinpos; 6758 u_int wrap_qinfifonext; 6759 6760 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6761 qinpos = ahd_get_snscb_qoff(ahd); 6762 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6763 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6764 if (wrap_qinfifonext >= wrap_qinpos) 6765 return (wrap_qinfifonext - wrap_qinpos); 6766 else 6767 return (wrap_qinfifonext 6768 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6769 } 6770 6771 void 6772 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6773 { 6774 struct scb *scb; 6775 ahd_mode_state saved_modes; 6776 u_int pending_cmds; 6777 6778 saved_modes = ahd_save_modes(ahd); 6779 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6780 6781 /* 6782 * Don't count any commands as outstanding that the 6783 * sequencer has already marked for completion. 6784 */ 6785 ahd_flush_qoutfifo(ahd); 6786 6787 pending_cmds = 0; 6788 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6789 pending_cmds++; 6790 } 6791 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6792 ahd_restore_modes(ahd, saved_modes); 6793 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6794 } 6795 6796 int 6797 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6798 int lun, u_int tag, role_t role, uint32_t status, 6799 ahd_search_action action) 6800 { 6801 struct scb *scb; 6802 struct scb *prev_scb; 6803 ahd_mode_state saved_modes; 6804 u_int qinstart; 6805 u_int qinpos; 6806 u_int qintail; 6807 u_int tid_next; 6808 u_int tid_prev; 6809 u_int scbid; 6810 u_int savedscbptr; 6811 uint32_t busaddr; 6812 int found; 6813 int targets; 6814 int pending_cmds; 6815 int qincount; 6816 6817 /* Must be in CCHAN mode */ 6818 saved_modes = ahd_save_modes(ahd); 6819 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6820 6821 /* 6822 * Halt any pending SCB DMA. The sequencer will reinitiate 6823 * this dma if the qinfifo is not empty once we unpause. 6824 */ 6825 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 6826 == (CCARREN|CCSCBEN|CCSCBDIR)) { 6827 ahd_outb(ahd, CCSCBCTL, 6828 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 6829 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 6830 ; 6831 } 6832 /* Determine sequencer's position in the qinfifo. */ 6833 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 6834 qinstart = ahd_get_snscb_qoff(ahd); 6835 qinpos = AHD_QIN_WRAP(qinstart); 6836 found = 0; 6837 prev_scb = NULL; 6838 6839 pending_cmds = 0; 6840 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6841 pending_cmds++; 6842 } 6843 qincount = ahd_qinfifo_count(ahd); 6844 6845 if (action == SEARCH_PRINT) { 6846 printf("qinstart = 0x%x qinfifonext = 0x%x\n", 6847 qinstart, ahd->qinfifonext); 6848 } 6849 6850 /* 6851 * Start with an empty queue. Entries that are not chosen 6852 * for removal will be re-added to the queue as we go. 6853 */ 6854 ahd->qinfifonext = qinstart; 6855 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6856 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6857 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6858 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6859 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6860 6861 while (qinpos != qintail) { 6862 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 6863 if (scb == NULL) { 6864 panic("Loop 1\n"); 6865 } 6866 6867 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 6868 /* 6869 * We found an scb that needs to be acted on. 6870 */ 6871 found++; 6872 switch (action) { 6873 case SEARCH_COMPLETE: 6874 { 6875 cam_status ostat; 6876 cam_status cstat; 6877 6878 ostat = ahd_get_scsi_status(scb); 6879 if (ostat == CAM_REQ_INPROG) 6880 ahd_set_scsi_status(scb, status); 6881 cstat = ahd_get_transaction_status(scb); 6882 if (cstat != CAM_REQ_CMP) 6883 ahd_freeze_scb(scb); 6884 if ((scb->flags & SCB_ACTIVE) == 0) 6885 printf("Inactive SCB in qinfifo\n"); 6886 if (scb->xs->error != CAM_REQ_CMP) 6887 printf("SEARCH_COMPLETE(0x%x): ostat 0x%x, cstat 0x%x, xs_error 0x%x\n", 6888 SCB_GET_TAG(scb), ostat, cstat, scb->xs->error); 6889 ahd_done(ahd, scb); 6890 6891 /* FALLTHROUGH */ 6892 } 6893 case SEARCH_REMOVE: 6894 break; 6895 case SEARCH_PRINT: 6896 printf(" 0x%x", ahd->qinfifo[qinpos]); 6897 /* FALLTHROUGH */ 6898 case SEARCH_COUNT: 6899 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6900 prev_scb = scb; 6901 break; 6902 } 6903 } else { 6904 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6905 prev_scb = scb; 6906 } 6907 qinpos = AHD_QIN_WRAP(qinpos+1); 6908 } 6909 6910 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6911 6912 if (action == SEARCH_PRINT) 6913 printf("\nWAITING_TID_QUEUES:\n"); 6914 6915 /* 6916 * Search waiting for selection lists. We traverse the 6917 * list of "their ids" waiting for selection and, if 6918 * appropriate, traverse the SCBs of each "their id" 6919 * looking for matches. 6920 */ 6921 savedscbptr = ahd_get_scbptr(ahd); 6922 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 6923 tid_prev = SCB_LIST_NULL; 6924 targets = 0; 6925 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 6926 u_int tid_head; 6927 6928 /* 6929 * We limit based on the number of SCBs since 6930 * MK_MESSAGE SCBs are not in the per-tid lists. 6931 */ 6932 targets++; 6933 if (targets > AHD_SCB_MAX) { 6934 panic("TID LIST LOOP"); 6935 } 6936 if (scbid >= ahd->scb_data.numscbs) { 6937 printf("%s: Waiting TID List inconsistency. " 6938 "SCB index == 0x%x, yet numscbs == 0x%x.", 6939 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 6940 ahd_dump_card_state(ahd); 6941 panic("for safety"); 6942 } 6943 scb = ahd_lookup_scb(ahd, scbid); 6944 if (scb == NULL) { 6945 printf("%s: SCB = 0x%x Not Active!\n", 6946 ahd_name(ahd), scbid); 6947 panic("Waiting TID List traversal\n"); 6948 break; 6949 } 6950 ahd_set_scbptr(ahd, scbid); 6951 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 6952 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 6953 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 6954 tid_prev = scbid; 6955 continue; 6956 } 6957 6958 /* 6959 * We found a list of scbs that needs to be searched. 6960 */ 6961 if (action == SEARCH_PRINT) 6962 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 6963 tid_head = scbid; 6964 found += ahd_search_scb_list(ahd, target, channel, 6965 lun, tag, role, status, 6966 action, &tid_head, 6967 SCB_GET_TARGET(ahd, scb)); 6968 if (tid_head != scbid) 6969 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 6970 if (!SCBID_IS_NULL(tid_head)) 6971 tid_prev = tid_head; 6972 if (action == SEARCH_PRINT) 6973 printf(")\n"); 6974 } 6975 ahd_set_scbptr(ahd, savedscbptr); 6976 ahd_restore_modes(ahd, saved_modes); 6977 return (found); 6978 } 6979 6980 static int 6981 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 6982 int lun, u_int tag, role_t role, uint32_t status, 6983 ahd_search_action action, u_int *list_head, u_int tid) 6984 { 6985 struct scb *scb; 6986 u_int scbid; 6987 u_int next; 6988 u_int prev; 6989 int found; 6990 6991 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6992 found = 0; 6993 prev = SCB_LIST_NULL; 6994 next = *list_head; 6995 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 6996 if (scbid >= ahd->scb_data.numscbs) { 6997 printf("%s:SCB List inconsistency. " 6998 "SCB == 0x%x, yet numscbs == 0x%x.", 6999 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7000 ahd_dump_card_state(ahd); 7001 panic("for safety"); 7002 } 7003 scb = ahd_lookup_scb(ahd, scbid); 7004 if (scb == NULL) { 7005 printf("%s: SCB = %d Not Active!\n", 7006 ahd_name(ahd), scbid); 7007 panic("Waiting List traversal\n"); 7008 } 7009 ahd_set_scbptr(ahd, scbid); 7010 next = ahd_inw_scbram(ahd, SCB_NEXT); 7011 if (ahd_match_scb(ahd, scb, target, channel, 7012 lun, SCB_LIST_NULL, role) == 0) { 7013 prev = scbid; 7014 continue; 7015 } 7016 found++; 7017 switch (action) { 7018 case SEARCH_COMPLETE: 7019 { 7020 cam_status ostat; 7021 cam_status cstat; 7022 7023 ostat = ahd_get_scsi_status(scb); 7024 if (ostat == CAM_REQ_INPROG) 7025 ahd_set_scsi_status(scb, status); 7026 cstat = ahd_get_transaction_status(scb); 7027 if (cstat != CAM_REQ_CMP) 7028 ahd_freeze_scb(scb); 7029 if ((scb->flags & SCB_ACTIVE) == 0) 7030 printf("Inactive SCB in Waiting List\n"); 7031 ahd_done(ahd, scb); 7032 /* FALLTHROUGH */ 7033 } 7034 case SEARCH_REMOVE: 7035 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7036 if (prev == SCB_LIST_NULL) 7037 *list_head = next; 7038 break; 7039 case SEARCH_PRINT: 7040 printf("0x%x ", scbid); 7041 case SEARCH_COUNT: 7042 prev = scbid; 7043 break; 7044 } 7045 if (found > AHD_SCB_MAX) 7046 panic("SCB LIST LOOP"); 7047 } 7048 if (action == SEARCH_COMPLETE 7049 || action == SEARCH_REMOVE) 7050 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7051 return (found); 7052 } 7053 7054 static void 7055 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7056 u_int tid_cur, u_int tid_next) 7057 { 7058 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7059 7060 if (SCBID_IS_NULL(tid_cur)) { 7061 7062 /* Bypass current TID list */ 7063 if (SCBID_IS_NULL(tid_prev)) { 7064 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7065 } else { 7066 ahd_set_scbptr(ahd, tid_prev); 7067 ahd_outw(ahd, SCB_NEXT2, tid_next); 7068 } 7069 if (SCBID_IS_NULL(tid_next)) 7070 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7071 } else { 7072 7073 /* Stitch through tid_cur */ 7074 if (SCBID_IS_NULL(tid_prev)) { 7075 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7076 } else { 7077 ahd_set_scbptr(ahd, tid_prev); 7078 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7079 } 7080 ahd_set_scbptr(ahd, tid_cur); 7081 ahd_outw(ahd, SCB_NEXT2, tid_next); 7082 7083 if (SCBID_IS_NULL(tid_next)) 7084 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7085 } 7086 } 7087 7088 /* 7089 * Manipulate the waiting for selection list and return the 7090 * scb that follows the one that we remove. 7091 */ 7092 static u_int 7093 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7094 u_int prev, u_int next, u_int tid) 7095 { 7096 u_int tail_offset; 7097 7098 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7099 if (!SCBID_IS_NULL(prev)) { 7100 ahd_set_scbptr(ahd, prev); 7101 ahd_outw(ahd, SCB_NEXT, next); 7102 } 7103 7104 /* 7105 * SCBs that had MK_MESSAGE set in them will not 7106 * be queued to the per-target lists, so don't 7107 * blindly clear the tail pointer. 7108 */ 7109 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7110 if (SCBID_IS_NULL(next) 7111 && ahd_inw(ahd, tail_offset) == scbid) 7112 ahd_outw(ahd, tail_offset, prev); 7113 ahd_add_scb_to_free_list(ahd, scbid); 7114 return (next); 7115 } 7116 7117 /* 7118 * Add the SCB as selected by SCBPTR onto the on chip list of 7119 * free hardware SCBs. This list is empty/unused if we are not 7120 * performing SCB paging. 7121 */ 7122 static void 7123 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7124 { 7125 /* XXX Need some other mechanism to designate "free". */ 7126 /* 7127 * Invalidate the tag so that our abort 7128 * routines don't think it's active. 7129 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7130 */ 7131 } 7132 7133 /******************************** Error Handling ******************************/ 7134 /* 7135 * Abort all SCBs that match the given description (target/channel/lun/tag), 7136 * setting their status to the passed in status if the status has not already 7137 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7138 * is paused before it is called. 7139 */ 7140 int 7141 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7142 int lun, u_int tag, role_t role, uint32_t status) 7143 { 7144 struct scb *scbp; 7145 struct scb *scbp_next; 7146 u_int active_scb; 7147 u_int i, j; 7148 u_int maxtarget; 7149 u_int minlun; 7150 u_int maxlun; 7151 int found; 7152 ahd_mode_state saved_modes; 7153 7154 /* restore these when we're done */ 7155 active_scb = ahd_get_scbptr(ahd); 7156 saved_modes = ahd_save_modes(ahd); 7157 7158 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7159 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7160 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7161 7162 /* 7163 * Clean out the busy target table for any untagged commands. 7164 */ 7165 i = 0; 7166 maxtarget = 16; 7167 if (target != CAM_TARGET_WILDCARD) { 7168 i = target; 7169 if (channel == 'B') 7170 i += 8; 7171 maxtarget = i + 1; 7172 } 7173 7174 if (lun == CAM_LUN_WILDCARD) { 7175 minlun = 0; 7176 maxlun = AHD_NUM_LUNS_NONPKT; 7177 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7178 minlun = maxlun = 0; 7179 } else { 7180 minlun = lun; 7181 maxlun = lun + 1; 7182 } 7183 7184 if (role != ROLE_TARGET) { 7185 for (;i < maxtarget; i++) { 7186 for (j = minlun;j < maxlun; j++) { 7187 u_int scbid; 7188 u_int tcl; 7189 7190 tcl = BUILD_TCL_RAW(i, 'A', j); 7191 scbid = ahd_find_busy_tcl(ahd, tcl); 7192 scbp = ahd_lookup_scb(ahd, scbid); 7193 if (scbp == NULL 7194 || ahd_match_scb(ahd, scbp, target, channel, 7195 lun, tag, role) == 0) 7196 continue; 7197 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7198 } 7199 } 7200 } 7201 7202 /* 7203 * Don't abort commands that have already completed, 7204 * but haven't quite made it up to the host yet. 7205 */ 7206 ahd_flush_qoutfifo(ahd); 7207 7208 /* 7209 * Go through the pending CCB list and look for 7210 * commands for this target that are still active. 7211 * These are other tagged commands that were 7212 * disconnected when the reset occurred. 7213 */ 7214 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7215 while (scbp_next != NULL) { 7216 scbp = scbp_next; 7217 scbp_next = LIST_NEXT(scbp, pending_links); 7218 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7219 cam_status ostat; 7220 7221 ostat = ahd_get_scsi_status(scbp); 7222 if (ostat == CAM_REQ_INPROG) 7223 ahd_set_scsi_status(scbp, status); 7224 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7225 ahd_freeze_scb(scbp); 7226 if ((scbp->flags & SCB_ACTIVE) == 0) 7227 printf("Inactive SCB on pending list\n"); 7228 ahd_done(ahd, scbp); 7229 found++; 7230 } 7231 } 7232 ahd_set_scbptr(ahd, active_scb); 7233 ahd_restore_modes(ahd, saved_modes); 7234 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7235 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7236 return found; 7237 } 7238 7239 static void 7240 ahd_reset_current_bus(struct ahd_softc *ahd) 7241 { 7242 uint8_t scsiseq; 7243 7244 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7245 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7246 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7247 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7248 ahd_delay(AHD_BUSRESET_DELAY); 7249 /* Turn off the bus reset */ 7250 ahd_outb(ahd, SCSISEQ0, scsiseq); 7251 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7252 /* 7253 * 2A Razor #474 7254 * Certain chip state is not cleared for 7255 * SCSI bus resets that we initiate, so 7256 * we must reset the chip. 7257 */ 7258 ahd_delay(AHD_BUSRESET_DELAY); 7259 ahd_reset(ahd); 7260 ahd_intr_enable(ahd, /*enable*/TRUE); 7261 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7262 } 7263 7264 ahd_clear_intstat(ahd); 7265 } 7266 7267 int 7268 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7269 { 7270 struct ahd_devinfo devinfo; 7271 u_int initiator; 7272 u_int target; 7273 u_int max_scsiid; 7274 int found; 7275 u_int fifo; 7276 u_int next_fifo; 7277 7278 7279 ahd->pending_device = NULL; 7280 7281 ahd_compile_devinfo(&devinfo, 7282 CAM_TARGET_WILDCARD, 7283 CAM_TARGET_WILDCARD, 7284 CAM_LUN_WILDCARD, 7285 channel, ROLE_UNKNOWN); 7286 ahd_pause(ahd); 7287 7288 /* Make sure the sequencer is in a safe location. */ 7289 ahd_clear_critical_section(ahd); 7290 7291 #if AHD_TARGET_MODE 7292 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7293 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7294 } 7295 #endif 7296 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7297 7298 /* 7299 * Disable selections so no automatic hardware 7300 * functions will modify chip state. 7301 */ 7302 ahd_outb(ahd, SCSISEQ0, 0); 7303 ahd_outb(ahd, SCSISEQ1, 0); 7304 7305 /* 7306 * Safely shut down our DMA engines. Always start with 7307 * the FIFO that is not currently active (if any are 7308 * actively connected). 7309 */ 7310 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7311 if (next_fifo > CURRFIFO_1) 7312 /* If disconneced, arbitrarily start with FIFO1. */ 7313 next_fifo = fifo = 0; 7314 do { 7315 next_fifo ^= CURRFIFO_1; 7316 ahd_set_modes(ahd, next_fifo, next_fifo); 7317 ahd_outb(ahd, DFCNTRL, 7318 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7319 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7320 ahd_delay(10); 7321 /* 7322 * Set CURRFIFO to the now inactive channel. 7323 */ 7324 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7325 ahd_outb(ahd, DFFSTAT, next_fifo); 7326 } while (next_fifo != fifo); 7327 /* 7328 * Reset the bus if we are initiating this reset 7329 */ 7330 ahd_clear_msg_state(ahd); 7331 ahd_outb(ahd, SIMODE1, 7332 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7333 if (initiate_reset) 7334 ahd_reset_current_bus(ahd); 7335 ahd_clear_intstat(ahd); 7336 7337 /* 7338 * Clean up all the state information for the 7339 * pending transactions on this bus. 7340 */ 7341 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7342 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7343 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7344 7345 /* 7346 * Cleanup anything left in the FIFOs. 7347 */ 7348 ahd_clear_fifo(ahd, 0); 7349 ahd_clear_fifo(ahd, 1); 7350 7351 /* 7352 * Revert to async/narrow transfers until we renegotiate. 7353 */ 7354 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7355 for (target = 0; target <= max_scsiid; target++) { 7356 7357 if (ahd->enabled_targets[target] == NULL) 7358 continue; 7359 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7360 struct ahd_devinfo devinfo; 7361 7362 ahd_compile_devinfo(&devinfo, target, initiator, 7363 CAM_LUN_WILDCARD, 7364 'A', ROLE_UNKNOWN); 7365 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7366 AHD_TRANS_CUR, /*paused*/TRUE); 7367 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7368 /*offset*/0, /*ppr_options*/0, 7369 AHD_TRANS_CUR, /*paused*/TRUE); 7370 } 7371 } 7372 7373 #ifdef AHD_TARGET_MODE 7374 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7375 7376 /* 7377 * Send an immediate notify ccb to all target more peripheral 7378 * drivers affected by this action. 7379 */ 7380 for (target = 0; target <= max_scsiid; target++) { 7381 struct ahd_tmode_tstate* tstate; 7382 u_int lun; 7383 7384 tstate = ahd->enabled_targets[target]; 7385 if (tstate == NULL) 7386 continue; 7387 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7388 struct ahd_tmode_lstate* lstate; 7389 7390 lstate = tstate->enabled_luns[lun]; 7391 if (lstate == NULL) 7392 continue; 7393 7394 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7395 EVENT_TYPE_BUS_RESET, /*arg*/0); 7396 ahd_send_lstate_events(ahd, lstate); 7397 } 7398 } 7399 #endif 7400 7401 /* Notify the XPT that a bus reset occurred */ 7402 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7403 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7404 ahd_restart(ahd); 7405 7406 /* 7407 * Freeze the SIMQ until our poller can determine that 7408 * the bus reset has really gone away. We set the initial 7409 * timer to 0 to have the check performed as soon as possible 7410 * from the timer context. 7411 */ 7412 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7413 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7414 ahd_freeze_simq(ahd); 7415 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7416 } 7417 return (found); 7418 } 7419 7420 7421 #define AHD_RESET_POLL_US 1000 7422 static void 7423 ahd_reset_poll(void *arg) 7424 { 7425 struct ahd_softc *ahd; 7426 u_int scsiseq1; 7427 u_long l; 7428 int s; 7429 7430 ahd_list_lock(&l); 7431 ahd = (void*)arg; 7432 if (ahd == NULL) { 7433 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7434 ahd_list_unlock(&l); 7435 return; 7436 } 7437 ahd_lock(ahd, &s); 7438 ahd_pause(ahd); 7439 ahd_update_modes(ahd); 7440 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7441 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7442 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7443 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7444 ahd_reset_poll, ahd); 7445 ahd_unpause(ahd); 7446 ahd_unlock(ahd, &s); 7447 ahd_list_unlock(&l); 7448 return; 7449 } 7450 7451 /* Reset is now low. Complete chip reinitialization. */ 7452 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7453 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7454 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7455 ahd_unpause(ahd); 7456 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7457 ahd_unlock(ahd, &s); 7458 ahd_release_simq(ahd); 7459 ahd_list_unlock(&l); 7460 } 7461 7462 /**************************** Statistics Processing ***************************/ 7463 static void 7464 ahd_stat_timer(void *arg) 7465 { 7466 struct ahd_softc *ahd; 7467 u_long l; 7468 int s; 7469 int enint_coal; 7470 7471 ahd_list_lock(&l); 7472 ahd = (void *)arg; 7473 if (ahd == NULL) { 7474 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7475 ahd_list_unlock(&l); 7476 return; 7477 } 7478 ahd_lock(ahd, &s); 7479 7480 enint_coal = ahd->hs_mailbox & ENINT_COALESS; 7481 if (ahd->cmdcmplt_total > ahd->int_coalessing_threshold) 7482 enint_coal |= ENINT_COALESS; 7483 else if (ahd->cmdcmplt_total < ahd->int_coalessing_stop_threshold) 7484 enint_coal &= ~ENINT_COALESS; 7485 7486 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESS)) { 7487 ahd_enable_coalessing(ahd, enint_coal); 7488 #ifdef AHD_DEBUG 7489 if ((ahd_debug & AHD_SHOW_INT_COALESSING) != 0) 7490 printf("%s: Interrupt coalessing " 7491 "now %sabled. Cmds %d\n", 7492 ahd_name(ahd), 7493 (enint_coal & ENINT_COALESS) ? "en" : "dis", 7494 ahd->cmdcmplt_total); 7495 #endif 7496 } 7497 7498 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7499 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7500 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7501 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7502 ahd_stat_timer, ahd); 7503 ahd_unlock(ahd, &s); 7504 ahd_list_unlock(&l); 7505 } 7506 7507 /****************************** Status Processing *****************************/ 7508 void 7509 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7510 { 7511 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7512 ahd_handle_scsi_status(ahd, scb); 7513 } else { 7514 ahd_calc_residual(ahd, scb); 7515 ahd_done(ahd, scb); 7516 } 7517 } 7518 7519 void 7520 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7521 { 7522 struct hardware_scb *hscb; 7523 u_int qfreeze_cnt; 7524 7525 /* 7526 * The sequencer freezes its select-out queue 7527 * anytime a SCSI status error occurs. We must 7528 * handle the error and decrement the QFREEZE count 7529 * to allow the sequencer to continue. 7530 */ 7531 hscb = scb->hscb; 7532 7533 /* Freeze the queue until the client sees the error. */ 7534 ahd_pause(ahd); 7535 ahd_clear_critical_section(ahd); 7536 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7537 ahd_freeze_devq(ahd, scb); 7538 ahd_freeze_scb(scb); 7539 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7540 if (qfreeze_cnt == 0) { 7541 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7542 } else { 7543 qfreeze_cnt--; 7544 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7545 } 7546 if (qfreeze_cnt == 0) 7547 ahd_outb(ahd, SEQ_FLAGS2, 7548 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7549 ahd_unpause(ahd); 7550 /* Don't want to clobber the original sense code */ 7551 if ((scb->flags & SCB_SENSE) != 0) { 7552 /* 7553 * Clear the SCB_SENSE Flag and perform 7554 * a normal command completion. 7555 */ 7556 scb->flags &= ~SCB_SENSE; 7557 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7558 ahd_done(ahd, scb); 7559 return; 7560 } 7561 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7562 ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7563 switch (hscb->shared_data.istatus.scsi_status) { 7564 case STATUS_PKT_SENSE: 7565 { 7566 struct scsi_status_iu_header *siu; 7567 7568 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7569 siu = (struct scsi_status_iu_header *)scb->sense_data; 7570 ahd_set_scsi_status(scb, siu->status); 7571 #ifdef AHD_DEBUG 7572 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7573 ahd_print_path(ahd, scb); 7574 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7575 SCB_GET_TAG(scb), siu->status); 7576 } 7577 #endif 7578 if ((siu->flags & SIU_RSPVALID) != 0) { 7579 scsipi_printaddr(scb->xs->xs_periph); 7580 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7581 printf("Unable to parse pkt_failures\n"); 7582 } else { 7583 7584 switch (SIU_PKTFAIL_CODE(siu)) { 7585 case SIU_PFC_NONE: 7586 printf("No packet failure found\n"); 7587 break; 7588 case SIU_PFC_CIU_FIELDS_INVALID: 7589 printf("Invalid Command IU Field\n"); 7590 break; 7591 case SIU_PFC_TMF_NOT_SUPPORTED: 7592 printf("TMF not supportd\n"); 7593 break; 7594 case SIU_PFC_TMF_FAILED: 7595 printf("TMF failed\n"); 7596 break; 7597 case SIU_PFC_INVALID_TYPE_CODE: 7598 printf("Invalid L_Q Type code\n"); 7599 break; 7600 case SIU_PFC_ILLEGAL_REQUEST: 7601 printf("Illegal request\n"); 7602 default: 7603 break; 7604 } 7605 } 7606 if (siu->status == SCSI_STATUS_OK) 7607 ahd_set_transaction_status(scb, CAM_REQ_CMP_ERR); 7608 } 7609 if ((siu->flags & SIU_SNSVALID) != 0) { 7610 scb->flags |= SCB_PKT_SENSE; 7611 #ifdef AHD_DEBUG 7612 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7613 printf("Sense data available (%d)\n", siu->sense_length[0]); 7614 printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7615 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7616 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+12]), 7617 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+13])); 7618 } 7619 #endif 7620 } 7621 ahd_done(ahd, scb); 7622 break; 7623 } 7624 case SCSI_STATUS_CMD_TERMINATED: 7625 case SCSI_STATUS_CHECK_COND: 7626 { 7627 struct ahd_devinfo devinfo; 7628 struct ahd_dma_seg *sg; 7629 struct scsipi_sense *sc; 7630 struct ahd_initiator_tinfo *targ_info; 7631 struct ahd_tmode_tstate *tstate; 7632 struct ahd_transinfo *tinfo; 7633 #ifdef AHD_DEBUG 7634 if (ahd_debug & AHD_SHOW_SENSE) { 7635 ahd_print_path(ahd, scb); 7636 printf("SCB %d: requests Check Status\n", 7637 SCB_GET_TAG(scb)); 7638 } 7639 #endif 7640 7641 if (ahd_perform_autosense(scb) == 0) 7642 break; 7643 7644 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7645 SCB_GET_TARGET(ahd, scb), 7646 SCB_GET_LUN(scb), 7647 SCB_GET_CHANNEL(ahd, scb), 7648 ROLE_INITIATOR); 7649 targ_info = ahd_fetch_transinfo(ahd, 7650 devinfo.channel, 7651 devinfo.our_scsiid, 7652 devinfo.target, 7653 &tstate); 7654 tinfo = &targ_info->curr; 7655 sg = scb->sg_list; 7656 sc = (struct scsipi_sense *)hscb->shared_data.idata.cdb; 7657 /* 7658 * Save off the residual if there is one. 7659 */ 7660 ahd_update_residual(ahd, scb); 7661 #ifdef AHD_DEBUG 7662 if (ahd_debug & AHD_SHOW_SENSE) { 7663 ahd_print_path(ahd, scb); 7664 printf("Sending Sense\n"); 7665 } 7666 #endif 7667 scb->sg_count = 0; 7668 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7669 ahd_get_sense_bufsize(ahd, scb), 7670 /*last*/TRUE); 7671 sc->opcode = REQUEST_SENSE; 7672 sc->byte2 = 0; 7673 sc->unused[0] = 0; 7674 sc->unused[1] = 0; 7675 sc->length = ahd_get_sense_bufsize(ahd, scb); 7676 sc->control = 0; 7677 7678 /* 7679 * We can't allow the target to disconnect. 7680 * This will be an untagged transaction and 7681 * having the target disconnect will make this 7682 * transaction indestinguishable from outstanding 7683 * tagged transactions. 7684 */ 7685 hscb->control = 0; 7686 7687 /* 7688 * This request sense could be because the 7689 * the device lost power or in some other 7690 * way has lost our transfer negotiations. 7691 * Renegotiate if appropriate. Unit attention 7692 * errors will be reported before any data 7693 * phases occur. 7694 */ 7695 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7696 ahd_update_neg_request(ahd, &devinfo, 7697 tstate, targ_info, 7698 AHD_NEG_IF_NON_ASYNC); 7699 } 7700 if (tstate->auto_negotiate & devinfo.target_mask) { 7701 hscb->control |= MK_MESSAGE; 7702 scb->flags &= 7703 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7704 scb->flags |= SCB_AUTO_NEGOTIATE; 7705 } 7706 hscb->cdb_len = sizeof(*sc); 7707 ahd_setup_data_scb(ahd, scb); 7708 scb->flags |= SCB_SENSE; 7709 ahd_queue_scb(ahd, scb); 7710 /* 7711 * Ensure we have enough time to actually 7712 * retrieve the sense. 7713 */ 7714 ahd_scb_timer_reset(scb, 5 * 1000000); 7715 break; 7716 } 7717 case SCSI_STATUS_OK: 7718 printf("%s: Interrupted for status of 0??? (SCB 0x%x)\n", 7719 ahd_name(ahd), SCB_GET_TAG(scb)); 7720 /* FALLTHROUGH */ 7721 default: 7722 ahd_done(ahd, scb); 7723 break; 7724 } 7725 } 7726 7727 /* 7728 * Calculate the residual for a just completed SCB. 7729 */ 7730 void 7731 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7732 { 7733 struct hardware_scb *hscb; 7734 struct initiator_status *spkt; 7735 uint32_t sgptr; 7736 uint32_t resid_sgptr; 7737 uint32_t resid; 7738 7739 /* 7740 * 5 cases. 7741 * 1) No residual. 7742 * SG_STATUS_VALID clear in sgptr. 7743 * 2) Transferless command 7744 * 3) Never performed any transfers. 7745 * sgptr has SG_FULL_RESID set. 7746 * 4) No residual but target did not 7747 * save data pointers after the 7748 * last transfer, so sgptr was 7749 * never updated. 7750 * 5) We have a partial residual. 7751 * Use residual_sgptr to determine 7752 * where we are. 7753 */ 7754 7755 hscb = scb->hscb; 7756 sgptr = ahd_le32toh(hscb->sgptr); 7757 if ((sgptr & SG_STATUS_VALID) == 0) 7758 /* Case 1 */ 7759 return; 7760 sgptr &= ~SG_STATUS_VALID; 7761 7762 if ((sgptr & SG_LIST_NULL) != 0) 7763 /* Case 2 */ 7764 return; 7765 7766 /* 7767 * Residual fields are the same in both 7768 * target and initiator status packets, 7769 * so we can always use the initiator fields 7770 * regardless of the role for this SCB. 7771 */ 7772 spkt = &hscb->shared_data.istatus; 7773 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7774 if ((sgptr & SG_FULL_RESID) != 0) { 7775 /* Case 3 */ 7776 resid = ahd_get_transfer_length(scb); 7777 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7778 /* Case 4 */ 7779 return; 7780 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7781 ahd_print_path(ahd, scb); 7782 printf("data overrun detected Tag == 0x%x.\n", 7783 SCB_GET_TAG(scb)); 7784 ahd_freeze_devq(ahd, scb); 7785 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7786 ahd_freeze_scb(scb); 7787 return; 7788 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7789 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7790 /* NOTREACHED */ 7791 } else { 7792 struct ahd_dma_seg *sg; 7793 7794 /* 7795 * Remainder of the SG where the transfer 7796 * stopped. 7797 */ 7798 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7799 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7800 7801 /* The residual sg_ptr always points to the next sg */ 7802 sg--; 7803 7804 /* 7805 * Add up the contents of all residual 7806 * SG segments that are after the SG where 7807 * the transfer stopped. 7808 */ 7809 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7810 sg++; 7811 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7812 } 7813 } 7814 7815 if ((scb->flags & SCB_SENSE) == 0) 7816 ahd_set_residual(scb, resid); 7817 /*else 7818 ahd_set_sense_residual(scb, resid);*/ 7819 7820 #ifdef AHD_DEBUG 7821 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7822 ahd_print_path(ahd, scb); 7823 printf("Handled %sResidual of %d bytes\n", 7824 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7825 } 7826 #endif 7827 } 7828 7829 /******************************* Target Mode **********************************/ 7830 #ifdef AHD_TARGET_MODE 7831 /* 7832 * Add a target mode event to this lun's queue 7833 */ 7834 static void 7835 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 7836 u_int initiator_id, u_int event_type, u_int event_arg) 7837 { 7838 struct ahd_tmode_event *event; 7839 int pending; 7840 7841 xpt_freeze_devq(lstate->path, /*count*/1); 7842 if (lstate->event_w_idx >= lstate->event_r_idx) 7843 pending = lstate->event_w_idx - lstate->event_r_idx; 7844 else 7845 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 7846 - (lstate->event_r_idx - lstate->event_w_idx); 7847 7848 if (event_type == EVENT_TYPE_BUS_RESET 7849 || event_type == MSG_BUS_DEV_RESET) { 7850 /* 7851 * Any earlier events are irrelevant, so reset our buffer. 7852 * This has the effect of allowing us to deal with reset 7853 * floods (an external device holding down the reset line) 7854 * without losing the event that is really interesting. 7855 */ 7856 lstate->event_r_idx = 0; 7857 lstate->event_w_idx = 0; 7858 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 7859 } 7860 7861 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 7862 xpt_print_path(lstate->path); 7863 printf("immediate event %x:%x lost\n", 7864 lstate->event_buffer[lstate->event_r_idx].event_type, 7865 lstate->event_buffer[lstate->event_r_idx].event_arg); 7866 lstate->event_r_idx++; 7867 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7868 lstate->event_r_idx = 0; 7869 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 7870 } 7871 7872 event = &lstate->event_buffer[lstate->event_w_idx]; 7873 event->initiator_id = initiator_id; 7874 event->event_type = event_type; 7875 event->event_arg = event_arg; 7876 lstate->event_w_idx++; 7877 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7878 lstate->event_w_idx = 0; 7879 } 7880 7881 /* 7882 * Send any target mode events queued up waiting 7883 * for immediate notify resources. 7884 */ 7885 void 7886 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 7887 { 7888 struct ccb_hdr *ccbh; 7889 struct ccb_immed_notify *inot; 7890 7891 while (lstate->event_r_idx != lstate->event_w_idx 7892 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 7893 struct ahd_tmode_event *event; 7894 7895 event = &lstate->event_buffer[lstate->event_r_idx]; 7896 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 7897 inot = (struct ccb_immed_notify *)ccbh; 7898 switch (event->event_type) { 7899 case EVENT_TYPE_BUS_RESET: 7900 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 7901 break; 7902 default: 7903 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 7904 inot->message_args[0] = event->event_type; 7905 inot->message_args[1] = event->event_arg; 7906 break; 7907 } 7908 inot->initiator_id = event->initiator_id; 7909 inot->sense_len = 0; 7910 xpt_done((union ccb *)inot); 7911 lstate->event_r_idx++; 7912 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7913 lstate->event_r_idx = 0; 7914 } 7915 } 7916 #endif 7917 7918 /******************** Sequencer Program Patching/Download *********************/ 7919 7920 #ifdef AHD_DUMP_SEQ 7921 void 7922 ahd_dumpseq(struct ahd_softc* ahd) 7923 { 7924 int i; 7925 int max_prog; 7926 7927 max_prog = 2048; 7928 7929 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 7930 ahd_outb(ahd, PRGMCNT, 0); 7931 ahd_outb(ahd, PRGMCNT+1, 0); 7932 for (i = 0; i < max_prog; i++) { 7933 uint8_t ins_bytes[4]; 7934 7935 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 7936 printf("0x%08x\n", ins_bytes[0] << 24 7937 | ins_bytes[1] << 16 7938 | ins_bytes[2] << 8 7939 | ins_bytes[3]); 7940 } 7941 } 7942 #endif 7943 7944 static void 7945 ahd_loadseq(struct ahd_softc *ahd) 7946 { 7947 struct cs cs_table[num_critical_sections]; 7948 u_int begin_set[num_critical_sections]; 7949 u_int end_set[num_critical_sections]; 7950 struct patch *cur_patch; 7951 u_int cs_count; 7952 u_int cur_cs; 7953 u_int i; 7954 int downloaded; 7955 u_int skip_addr; 7956 u_int sg_prefetch_cnt; 7957 u_int sg_prefetch_cnt_limit; 7958 u_int sg_prefetch_align; 7959 u_int sg_size; 7960 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 7961 7962 if (bootverbose) 7963 printf("%s: Downloading Sequencer Program...", 7964 ahd_name(ahd)); 7965 7966 #if DOWNLOAD_CONST_COUNT != 7 7967 #error "Download Const Mismatch" 7968 #endif 7969 /* 7970 * Start out with 0 critical sections 7971 * that apply to this firmware load. 7972 */ 7973 cs_count = 0; 7974 cur_cs = 0; 7975 memset(begin_set, 0, sizeof(begin_set)); 7976 memset(end_set, 0, sizeof(end_set)); 7977 7978 /* 7979 * Setup downloadable constant table. 7980 * 7981 * The computation for the S/G prefetch variables is 7982 * a bit complicated. We would like to always fetch 7983 * in terms of cachelined sized increments. However, 7984 * if the cacheline is not an even multiple of the 7985 * SG element size or is larger than our SG RAM, using 7986 * just the cache size might leave us with only a portion 7987 * of an SG element at the tail of a prefetch. If the 7988 * cacheline is larger than our S/G prefetch buffer less 7989 * the size of an SG element, we may round down to a cacheline 7990 * that doesn't contain any or all of the S/G of interest 7991 * within the bounds of our S/G ram. Provide variables to 7992 * the sequencer that will allow it to handle these edge 7993 * cases. 7994 */ 7995 /* Start by aligning to the nearest cacheline. */ 7996 sg_prefetch_align = ahd->pci_cachesize; 7997 if (sg_prefetch_align == 0) 7998 sg_prefetch_align = 8; 7999 /* Round down to the nearest power of 2. */ 8000 while (powerof2(sg_prefetch_align) == 0) 8001 sg_prefetch_align--; 8002 /* 8003 * If the cacheline boundary is greater than half our prefetch RAM 8004 * we risk not being able to fetch even a single complete S/G 8005 * segment if we align to that boundary. 8006 */ 8007 if (sg_prefetch_align > CCSGADDR_MAX/2) 8008 sg_prefetch_align = CCSGADDR_MAX/2; 8009 /* Start by fetching a single cacheline. */ 8010 sg_prefetch_cnt = sg_prefetch_align; 8011 /* 8012 * Increment the prefetch count by cachelines until 8013 * at least one S/G element will fit. 8014 */ 8015 sg_size = sizeof(struct ahd_dma_seg); 8016 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8017 sg_size = sizeof(struct ahd_dma64_seg); 8018 while (sg_prefetch_cnt < sg_size) 8019 sg_prefetch_cnt += sg_prefetch_align; 8020 /* 8021 * If the cacheline is not an even multiple of 8022 * the S/G size, we may only get a partial S/G when 8023 * we align. Add a cacheline if this is the case. 8024 */ 8025 if ((sg_prefetch_align % sg_size) != 0 8026 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8027 sg_prefetch_cnt += sg_prefetch_align; 8028 /* 8029 * Lastly, compute a value that the sequencer can use 8030 * to determine if the remainder of the CCSGRAM buffer 8031 * has a full S/G element in it. 8032 */ 8033 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8034 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8035 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8036 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8037 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8038 download_consts[SG_SIZEOF] = sg_size; 8039 download_consts[PKT_OVERRUN_BUFOFFSET] = 8040 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8041 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8042 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) 8043 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_FULL_LUN; 8044 cur_patch = patches; 8045 downloaded = 0; 8046 skip_addr = 0; 8047 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8048 ahd_outb(ahd, PRGMCNT, 0); 8049 ahd_outb(ahd, PRGMCNT+1, 0); 8050 8051 for (i = 0; i < sizeof(seqprog)/4; i++) { 8052 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8053 /* 8054 * Don't download this instruction as it 8055 * is in a patch that was removed. 8056 */ 8057 continue; 8058 } 8059 /* 8060 * Move through the CS table until we find a CS 8061 * that might apply to this instruction. 8062 */ 8063 for (; cur_cs < num_critical_sections; cur_cs++) { 8064 if (critical_sections[cur_cs].end <= i) { 8065 if (begin_set[cs_count] == TRUE 8066 && end_set[cs_count] == FALSE) { 8067 cs_table[cs_count].end = downloaded; 8068 end_set[cs_count] = TRUE; 8069 cs_count++; 8070 } 8071 continue; 8072 } 8073 if (critical_sections[cur_cs].begin <= i 8074 && begin_set[cs_count] == FALSE) { 8075 cs_table[cs_count].begin = downloaded; 8076 begin_set[cs_count] = TRUE; 8077 } 8078 break; 8079 } 8080 ahd_download_instr(ahd, i, download_consts); 8081 downloaded++; 8082 } 8083 8084 ahd->num_critical_sections = cs_count; 8085 if (cs_count != 0) { 8086 8087 cs_count *= sizeof(struct cs); 8088 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8089 if (ahd->critical_sections == NULL) 8090 panic("ahd_loadseq: Could not malloc"); 8091 memcpy(ahd->critical_sections, cs_table, cs_count); 8092 } 8093 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8094 8095 if (bootverbose) { 8096 printf(" %d instructions downloaded\n", downloaded); 8097 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8098 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8099 } 8100 } 8101 8102 static int 8103 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8104 u_int start_instr, u_int *skip_addr) 8105 { 8106 struct patch *cur_patch; 8107 struct patch *last_patch; 8108 u_int num_patches; 8109 8110 num_patches = sizeof(patches)/sizeof(struct patch); 8111 last_patch = &patches[num_patches]; 8112 cur_patch = *start_patch; 8113 8114 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8115 8116 if (cur_patch->patch_func(ahd) == 0) { 8117 8118 /* Start rejecting code */ 8119 *skip_addr = start_instr + cur_patch->skip_instr; 8120 cur_patch += cur_patch->skip_patch; 8121 } else { 8122 /* Accepted this patch. Advance to the next 8123 * one and wait for our intruction pointer to 8124 * hit this point. 8125 */ 8126 cur_patch++; 8127 } 8128 } 8129 8130 *start_patch = cur_patch; 8131 if (start_instr < *skip_addr) 8132 /* Still skipping */ 8133 return (0); 8134 8135 return (1); 8136 } 8137 8138 static u_int 8139 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8140 { 8141 struct patch *cur_patch; 8142 int address_offset; 8143 u_int skip_addr; 8144 u_int i; 8145 8146 address_offset = 0; 8147 cur_patch = patches; 8148 skip_addr = 0; 8149 8150 for (i = 0; i < address;) { 8151 8152 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8153 8154 if (skip_addr > i) { 8155 int end_addr; 8156 8157 end_addr = MIN(address, skip_addr); 8158 address_offset += end_addr - i; 8159 i = skip_addr; 8160 } else { 8161 i++; 8162 } 8163 } 8164 return (address - address_offset); 8165 } 8166 8167 static void 8168 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8169 { 8170 union ins_formats instr; 8171 struct ins_format1 *fmt1_ins; 8172 struct ins_format3 *fmt3_ins; 8173 u_int opcode; 8174 8175 /* 8176 * The firmware is always compiled into a little endian format. 8177 */ 8178 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8179 8180 fmt1_ins = &instr.format1; 8181 fmt3_ins = NULL; 8182 8183 /* Pull the opcode */ 8184 opcode = instr.format1.opcode; 8185 switch (opcode) { 8186 case AIC_OP_JMP: 8187 case AIC_OP_JC: 8188 case AIC_OP_JNC: 8189 case AIC_OP_CALL: 8190 case AIC_OP_JNE: 8191 case AIC_OP_JNZ: 8192 case AIC_OP_JE: 8193 case AIC_OP_JZ: 8194 { 8195 fmt3_ins = &instr.format3; 8196 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8197 /* FALLTHROUGH */ 8198 } 8199 case AIC_OP_OR: 8200 case AIC_OP_AND: 8201 case AIC_OP_XOR: 8202 case AIC_OP_ADD: 8203 case AIC_OP_ADC: 8204 case AIC_OP_BMOV: 8205 if (fmt1_ins->parity != 0) { 8206 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8207 } 8208 fmt1_ins->parity = 0; 8209 /* FALLTHROUGH */ 8210 case AIC_OP_ROL: 8211 { 8212 int i, count; 8213 8214 /* Calculate odd parity for the instruction */ 8215 for (i = 0, count = 0; i < 31; i++) { 8216 uint32_t mask; 8217 8218 mask = 0x01 << i; 8219 if ((instr.integer & mask) != 0) 8220 count++; 8221 } 8222 if ((count & 0x01) == 0) 8223 instr.format1.parity = 1; 8224 8225 /* The sequencer is a little endian cpu */ 8226 instr.integer = ahd_htole32(instr.integer); 8227 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8228 break; 8229 } 8230 default: 8231 panic("Unknown opcode encountered in seq program"); 8232 break; 8233 } 8234 } 8235 8236 static int 8237 ahd_probe_stack_size(struct ahd_softc *ahd) 8238 { 8239 int last_probe; 8240 8241 last_probe = 0; 8242 while (1) { 8243 int i; 8244 8245 /* 8246 * We avoid using 0 as a pattern to avoid 8247 * confusion if the stack implementation 8248 * "back-fills" with zeros when "poping' 8249 * entries. 8250 */ 8251 for (i = 1; i <= last_probe+1; i++) { 8252 ahd_outb(ahd, STACK, i & 0xFF); 8253 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8254 } 8255 8256 /* Verify */ 8257 for (i = last_probe+1; i > 0; i--) { 8258 u_int stack_entry; 8259 8260 stack_entry = ahd_inb(ahd, STACK) 8261 |(ahd_inb(ahd, STACK) << 8); 8262 if (stack_entry != i) 8263 goto sized; 8264 } 8265 last_probe++; 8266 } 8267 sized: 8268 return (last_probe); 8269 } 8270 8271 void 8272 ahd_dump_all_cards_state() 8273 { 8274 struct ahd_softc *list_ahd; 8275 8276 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8277 ahd_dump_card_state(list_ahd); 8278 } 8279 } 8280 8281 int 8282 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8283 const char *name, u_int address, u_int value, 8284 u_int *cur_column, u_int wrap_point) 8285 { 8286 int printed; 8287 u_int printed_mask; 8288 char line[1024]; 8289 8290 line[0] = 0; 8291 8292 if (cur_column != NULL && *cur_column >= wrap_point) { 8293 printf("\n"); 8294 *cur_column = 0; 8295 } 8296 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8297 if (table == NULL) { 8298 printed += snprintf(&line[printed], (sizeof line) - printed, 8299 " "); 8300 printf("%s", line); 8301 if (cur_column != NULL) 8302 *cur_column += printed; 8303 return (printed); 8304 } 8305 printed_mask = 0; 8306 while (printed_mask != 0xFF) { 8307 int entry; 8308 8309 for (entry = 0; entry < num_entries; entry++) { 8310 if (((value & table[entry].mask) 8311 != table[entry].value) 8312 || ((printed_mask & table[entry].mask) 8313 == table[entry].mask)) 8314 continue; 8315 printed += snprintf(&line[printed], 8316 (sizeof line) - printed, "%s%s", 8317 printed_mask == 0 ? ":(" : "|", 8318 table[entry].name); 8319 printed_mask |= table[entry].mask; 8320 8321 break; 8322 } 8323 if (entry >= num_entries) 8324 break; 8325 } 8326 if (printed_mask != 0) 8327 printed += snprintf(&line[printed], 8328 (sizeof line) - printed, ") "); 8329 else 8330 printed += snprintf(&line[printed], 8331 (sizeof line) - printed, " "); 8332 if (cur_column != NULL) 8333 *cur_column += printed; 8334 printf("%s", line); 8335 8336 return (printed); 8337 } 8338 8339 void 8340 ahd_dump_card_state(struct ahd_softc *ahd) 8341 { 8342 struct scb *scb; 8343 ahd_mode_state saved_modes; 8344 u_int dffstat; 8345 int paused; 8346 u_int scb_index; 8347 u_int saved_scb_index; 8348 u_int cur_col; 8349 int i; 8350 8351 if (ahd_is_paused(ahd)) { 8352 paused = 1; 8353 } else { 8354 paused = 0; 8355 ahd_pause(ahd); 8356 } 8357 saved_modes = ahd_save_modes(ahd); 8358 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8359 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8360 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8361 ahd_name(ahd), 8362 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8363 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8364 ahd->saved_dst_mode)); 8365 if (paused) 8366 printf("Card was paused\n"); 8367 /* 8368 * Mode independent registers. 8369 */ 8370 cur_col = 0; 8371 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8372 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8373 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8374 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8375 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8376 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8377 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8378 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8379 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8380 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8381 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8382 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8383 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8384 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8385 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8386 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8387 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8388 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8389 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8390 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8391 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8392 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8393 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8394 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8395 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8396 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8397 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8398 printf("\n"); 8399 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8400 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8401 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8402 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8403 ahd_inw(ahd, NEXTSCB)); 8404 cur_col = 0; 8405 /* QINFIFO */ 8406 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8407 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8408 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8409 saved_scb_index = ahd_get_scbptr(ahd); 8410 printf("Pending list:"); 8411 i = 0; 8412 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8413 if (i++ > AHD_SCB_MAX) 8414 break; 8415 /*cur_col = */ printf("\n%3d ", SCB_GET_TAG(scb)); 8416 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8417 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8418 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8419 ahd_scb_tag_print(ahd_inb(ahd, SCB_TAG), &cur_col, 60); 8420 } 8421 printf("\nTotal %d\n", i); 8422 8423 printf("Kernel Free SCB list: "); 8424 i = 0; 8425 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8426 struct scb *list_scb; 8427 8428 list_scb = scb; 8429 do { 8430 printf("%d ", SCB_GET_TAG(list_scb)); 8431 list_scb = LIST_NEXT(list_scb, collision_links); 8432 } while (list_scb && i++ < AHD_SCB_MAX); 8433 } 8434 8435 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8436 if (i++ > AHD_SCB_MAX) 8437 break; 8438 printf("%d ", SCB_GET_TAG(scb)); 8439 } 8440 printf("\n"); 8441 8442 printf("Sequencer Complete DMA-inprog list: "); 8443 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8444 i = 0; 8445 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8446 ahd_set_scbptr(ahd, scb_index); 8447 printf("%d ", scb_index); 8448 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8449 } 8450 printf("\n"); 8451 8452 printf("Sequencer Complete list: "); 8453 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8454 i = 0; 8455 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8456 ahd_set_scbptr(ahd, scb_index); 8457 printf("%d ", scb_index); 8458 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8459 } 8460 printf("\n"); 8461 8462 8463 printf("Sequencer DMA-Up and Complete list: "); 8464 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8465 i = 0; 8466 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8467 ahd_set_scbptr(ahd, scb_index); 8468 printf("%d ", scb_index); 8469 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8470 } 8471 printf("\n"); 8472 ahd_set_scbptr(ahd, saved_scb_index); 8473 dffstat = ahd_inb(ahd, DFFSTAT); 8474 for (i = 0; i < 2; i++) { 8475 #ifdef AHD_DEBUG 8476 struct scb *fifo_scb; 8477 #endif 8478 u_int fifo_scbptr; 8479 8480 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8481 fifo_scbptr = ahd_get_scbptr(ahd); 8482 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, " 8483 "SCB 0x%x, LJSCB 0x%x\n", 8484 ahd_name(ahd), i, 8485 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8486 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr, 8487 ahd_inw(ahd, LONGJMP_SCB)); 8488 cur_col = 0; 8489 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8490 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8491 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8492 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8493 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8494 &cur_col, 50); 8495 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8496 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8497 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8498 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8499 if (cur_col > 50) { 8500 printf("\n"); 8501 cur_col = 0; 8502 } 8503 printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8504 ahd_inl(ahd, SHADDR+4), 8505 ahd_inl(ahd, SHADDR), 8506 (ahd_inb(ahd, SHCNT) 8507 | (ahd_inb(ahd, SHCNT + 1) << 8) 8508 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8509 printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8510 ahd_inl(ahd, HADDR+4), 8511 ahd_inl(ahd, HADDR), 8512 (ahd_inb(ahd, HCNT) 8513 | (ahd_inb(ahd, HCNT + 1) << 8) 8514 | (ahd_inb(ahd, HCNT + 2) << 16))); 8515 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8516 #ifdef AHD_DEBUG 8517 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8518 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8519 if (fifo_scb != NULL) 8520 ahd_dump_sglist(fifo_scb); 8521 } 8522 #endif 8523 } 8524 printf("\nLQIN: "); 8525 for (i = 0; i < 20; i++) 8526 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8527 printf("\n"); 8528 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8529 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8530 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8531 ahd_inb(ahd, OPTIONMODE)); 8532 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8533 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8534 ahd_inb(ahd, MAXCMDCNT)); 8535 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8536 printf("\n"); 8537 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8538 cur_col = 0; 8539 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8540 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8541 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8542 ahd_inw(ahd, DINDEX)); 8543 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8544 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8545 ahd_inw(ahd, SCB_NEXT2)); 8546 printf("CDB %x %x %x %x %x %x\n", 8547 ahd_inb(ahd, SCB_CDB_STORE), 8548 ahd_inb(ahd, SCB_CDB_STORE+1), 8549 ahd_inb(ahd, SCB_CDB_STORE+2), 8550 ahd_inb(ahd, SCB_CDB_STORE+3), 8551 ahd_inb(ahd, SCB_CDB_STORE+4), 8552 ahd_inb(ahd, SCB_CDB_STORE+5)); 8553 printf("STACK:"); 8554 for (i = 0; i < ahd->stack_size; i++) { 8555 ahd->saved_stack[i] = 8556 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8557 printf(" 0x%x", ahd->saved_stack[i]); 8558 } 8559 for (i = ahd->stack_size-1; i >= 0; i--) { 8560 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8561 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8562 } 8563 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8564 ahd_platform_dump_card_state(ahd); 8565 ahd_restore_modes(ahd, saved_modes); 8566 if (paused == 0) 8567 ahd_unpause(ahd); 8568 } 8569 8570 void 8571 ahd_dump_scbs(struct ahd_softc *ahd) 8572 { 8573 ahd_mode_state saved_modes; 8574 u_int saved_scb_index; 8575 int i; 8576 8577 saved_modes = ahd_save_modes(ahd); 8578 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8579 saved_scb_index = ahd_get_scbptr(ahd); 8580 for (i = 0; i < AHD_SCB_MAX; i++) { 8581 ahd_set_scbptr(ahd, i); 8582 printf("%3d", i); 8583 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8584 ahd_inb(ahd, SCB_CONTROL), 8585 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8586 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8587 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8588 } 8589 printf("\n"); 8590 ahd_set_scbptr(ahd, saved_scb_index); 8591 ahd_restore_modes(ahd, saved_modes); 8592 } 8593 8594 /**************************** Flexport Logic **********************************/ 8595 /* 8596 * Read count 16bit words from 16bit word address start_addr from the 8597 * SEEPROM attached to the controller, into buf, using the controller's 8598 * SEEPROM reading state machine. 8599 */ 8600 int 8601 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8602 u_int start_addr, u_int count) 8603 { 8604 u_int cur_addr; 8605 u_int end_addr; 8606 int error; 8607 8608 /* 8609 * If we never make it through the loop even once, 8610 * we were passed invalid arguments. 8611 */ 8612 error = EINVAL; 8613 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8614 end_addr = start_addr + count; 8615 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8616 ahd_outb(ahd, SEEADR, cur_addr); 8617 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8618 8619 error = ahd_wait_seeprom(ahd); 8620 if (error) { 8621 printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd)); 8622 break; 8623 } 8624 *buf++ = ahd_inw(ahd, SEEDAT); 8625 } 8626 return (error); 8627 } 8628 8629 /* 8630 * Write count 16bit words from buf, into SEEPROM attache to the 8631 * controller starting at 16bit word address start_addr, using the 8632 * controller's SEEPROM writing state machine. 8633 */ 8634 int 8635 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8636 u_int start_addr, u_int count) 8637 { 8638 u_int cur_addr; 8639 u_int end_addr; 8640 int error; 8641 int retval; 8642 8643 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8644 error = ENOENT; 8645 8646 /* Place the chip into write-enable mode */ 8647 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8648 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8649 error = ahd_wait_seeprom(ahd); 8650 if (error) 8651 return (error); 8652 8653 /* 8654 * Write the data. If we don't get throught the loop at 8655 * least once, the arguments were invalid. 8656 */ 8657 retval = EINVAL; 8658 end_addr = start_addr + count; 8659 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8660 ahd_outw(ahd, SEEDAT, *buf++); 8661 ahd_outb(ahd, SEEADR, cur_addr); 8662 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8663 8664 retval = ahd_wait_seeprom(ahd); 8665 if (retval) 8666 break; 8667 } 8668 8669 /* 8670 * Disable writes. 8671 */ 8672 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8673 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8674 error = ahd_wait_seeprom(ahd); 8675 if (error) 8676 return (error); 8677 return (retval); 8678 } 8679 8680 /* 8681 * Wait ~100us for the serial eeprom to satisfy our request. 8682 */ 8683 int 8684 ahd_wait_seeprom(struct ahd_softc *ahd) 8685 { 8686 int cnt; 8687 8688 cnt = 2000; 8689 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8690 ahd_delay(5); 8691 8692 if (cnt == 0) 8693 return (ETIMEDOUT); 8694 return (0); 8695 } 8696 8697 int 8698 ahd_verify_cksum(struct seeprom_config *sc) 8699 { 8700 int i; 8701 int maxaddr; 8702 uint32_t checksum; 8703 uint16_t *scarray; 8704 8705 maxaddr = (sizeof(*sc)/2) - 1; 8706 checksum = 0; 8707 scarray = (uint16_t *)sc; 8708 8709 for (i = 0; i < maxaddr; i++) 8710 checksum = checksum + scarray[i]; 8711 if (checksum == 0 8712 || (checksum & 0xFFFF) != sc->checksum) { 8713 return (0); 8714 } else { 8715 return (1); 8716 } 8717 } 8718 8719 int 8720 ahd_acquire_seeprom(struct ahd_softc *ahd) 8721 { 8722 /* 8723 * We should be able to determine the SEEPROM type 8724 * from the flexport logic, but unfortunately not 8725 * all implementations have this logic and there is 8726 * no programatic method for determining if the logic 8727 * is present. 8728 */ 8729 8730 return (1); 8731 #if 0 8732 uint8_t seetype; 8733 int error; 8734 8735 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8736 if (error != 0 8737 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8738 return (0); 8739 return (1); 8740 #endif 8741 } 8742 8743 void 8744 ahd_release_seeprom(struct ahd_softc *ahd) 8745 { 8746 /* Currently a no-op */ 8747 } 8748 8749 int 8750 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8751 { 8752 int error; 8753 8754 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8755 if (addr > 7) 8756 panic("ahd_write_flexport: address out of range"); 8757 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8758 error = ahd_wait_flexport(ahd); 8759 if (error != 0) 8760 return (error); 8761 ahd_outb(ahd, BRDDAT, value); 8762 ahd_flush_device_writes(ahd); 8763 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8764 ahd_flush_device_writes(ahd); 8765 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8766 ahd_flush_device_writes(ahd); 8767 ahd_outb(ahd, BRDCTL, 0); 8768 ahd_flush_device_writes(ahd); 8769 return (0); 8770 } 8771 8772 int 8773 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8774 { 8775 int error; 8776 8777 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8778 if (addr > 7) 8779 panic("ahd_read_flexport: address out of range"); 8780 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8781 error = ahd_wait_flexport(ahd); 8782 if (error != 0) 8783 return (error); 8784 *value = ahd_inb(ahd, BRDDAT); 8785 ahd_outb(ahd, BRDCTL, 0); 8786 ahd_flush_device_writes(ahd); 8787 return (0); 8788 } 8789 8790 /* 8791 * Wait at most 2 seconds for flexport arbitration to succeed. 8792 */ 8793 int 8794 ahd_wait_flexport(struct ahd_softc *ahd) 8795 { 8796 int cnt; 8797 8798 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8799 cnt = 1000000 * 2 / 5; 8800 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8801 ahd_delay(5); 8802 8803 if (cnt == 0) 8804 return (ETIMEDOUT); 8805 return (0); 8806 } 8807 8808 /************************* Target Mode ****************************************/ 8809 #ifdef AHD_TARGET_MODE 8810 cam_status 8811 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8812 struct ahd_tmode_tstate **tstate, 8813 struct ahd_tmode_lstate **lstate, 8814 int notfound_failure) 8815 { 8816 8817 if ((ahd->features & AHD_TARGETMODE) == 0) 8818 return (CAM_REQ_INVALID); 8819 8820 /* 8821 * Handle the 'black hole' device that sucks up 8822 * requests to unattached luns on enabled targets. 8823 */ 8824 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8825 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8826 *tstate = NULL; 8827 *lstate = ahd->black_hole; 8828 } else { 8829 u_int max_id; 8830 8831 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8832 if (ccb->ccb_h.target_id > max_id) 8833 return (CAM_TID_INVALID); 8834 8835 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 8836 return (CAM_LUN_INVALID); 8837 8838 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 8839 *lstate = NULL; 8840 if (*tstate != NULL) 8841 *lstate = 8842 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 8843 } 8844 8845 if (notfound_failure != 0 && *lstate == NULL) 8846 return (CAM_PATH_INVALID); 8847 8848 return (CAM_REQ_CMP); 8849 } 8850 8851 void 8852 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 8853 { 8854 #if NOT_YET 8855 struct ahd_tmode_tstate *tstate; 8856 struct ahd_tmode_lstate *lstate; 8857 struct ccb_en_lun *cel; 8858 cam_status status; 8859 u_int target; 8860 u_int lun; 8861 u_int target_mask; 8862 u_long s; 8863 char channel; 8864 8865 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 8866 /*notfound_failure*/FALSE); 8867 8868 if (status != CAM_REQ_CMP) { 8869 ccb->ccb_h.status = status; 8870 return; 8871 } 8872 8873 if ((ahd->features & AHD_MULTIROLE) != 0) { 8874 u_int our_id; 8875 8876 our_id = ahd->our_id; 8877 if (ccb->ccb_h.target_id != our_id) { 8878 if ((ahd->features & AHD_MULTI_TID) != 0 8879 && (ahd->flags & AHD_INITIATORROLE) != 0) { 8880 /* 8881 * Only allow additional targets if 8882 * the initiator role is disabled. 8883 * The hardware cannot handle a re-select-in 8884 * on the initiator id during a re-select-out 8885 * on a different target id. 8886 */ 8887 status = CAM_TID_INVALID; 8888 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 8889 || ahd->enabled_luns > 0) { 8890 /* 8891 * Only allow our target id to change 8892 * if the initiator role is not configured 8893 * and there are no enabled luns which 8894 * are attached to the currently registered 8895 * scsi id. 8896 */ 8897 status = CAM_TID_INVALID; 8898 } 8899 } 8900 } 8901 8902 if (status != CAM_REQ_CMP) { 8903 ccb->ccb_h.status = status; 8904 return; 8905 } 8906 8907 /* 8908 * We now have an id that is valid. 8909 * If we aren't in target mode, switch modes. 8910 */ 8911 if ((ahd->flags & AHD_TARGETROLE) == 0 8912 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 8913 u_long s; 8914 8915 printf("Configuring Target Mode\n"); 8916 ahd_lock(ahd, &s); 8917 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 8918 ccb->ccb_h.status = CAM_BUSY; 8919 ahd_unlock(ahd, &s); 8920 return; 8921 } 8922 ahd->flags |= AHD_TARGETROLE; 8923 if ((ahd->features & AHD_MULTIROLE) == 0) 8924 ahd->flags &= ~AHD_INITIATORROLE; 8925 ahd_pause(ahd); 8926 ahd_loadseq(ahd); 8927 ahd_unlock(ahd, &s); 8928 } 8929 cel = &ccb->cel; 8930 target = ccb->ccb_h.target_id; 8931 lun = ccb->ccb_h.target_lun; 8932 channel = SIM_CHANNEL(ahd, sim); 8933 target_mask = 0x01 << target; 8934 if (channel == 'B') 8935 target_mask <<= 8; 8936 8937 if (cel->enable != 0) { 8938 u_int scsiseq1; 8939 8940 /* Are we already enabled?? */ 8941 if (lstate != NULL) { 8942 xpt_print_path(ccb->ccb_h.path); 8943 printf("Lun already enabled\n"); 8944 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 8945 return; 8946 } 8947 8948 if (cel->grp6_len != 0 8949 || cel->grp7_len != 0) { 8950 /* 8951 * Don't (yet?) support vendor 8952 * specific commands. 8953 */ 8954 ccb->ccb_h.status = CAM_REQ_INVALID; 8955 printf("Non-zero Group Codes\n"); 8956 return; 8957 } 8958 8959 /* 8960 * Seems to be okay. 8961 * Setup our data structures. 8962 */ 8963 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 8964 tstate = ahd_alloc_tstate(ahd, target, channel); 8965 if (tstate == NULL) { 8966 xpt_print_path(ccb->ccb_h.path); 8967 printf("Couldn't allocate tstate\n"); 8968 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8969 return; 8970 } 8971 } 8972 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 8973 if (lstate == NULL) { 8974 xpt_print_path(ccb->ccb_h.path); 8975 printf("Couldn't allocate lstate\n"); 8976 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8977 return; 8978 } 8979 memset(lstate, 0, sizeof(*lstate)); 8980 status = xpt_create_path(&lstate->path, /*periph*/NULL, 8981 xpt_path_path_id(ccb->ccb_h.path), 8982 xpt_path_target_id(ccb->ccb_h.path), 8983 xpt_path_lun_id(ccb->ccb_h.path)); 8984 if (status != CAM_REQ_CMP) { 8985 free(lstate, M_DEVBUF); 8986 xpt_print_path(ccb->ccb_h.path); 8987 printf("Couldn't allocate path\n"); 8988 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8989 return; 8990 } 8991 SLIST_INIT(&lstate->accept_tios); 8992 SLIST_INIT(&lstate->immed_notifies); 8993 ahd_lock(ahd, &s); 8994 ahd_pause(ahd); 8995 if (target != CAM_TARGET_WILDCARD) { 8996 tstate->enabled_luns[lun] = lstate; 8997 ahd->enabled_luns++; 8998 8999 if ((ahd->features & AHD_MULTI_TID) != 0) { 9000 u_int targid_mask; 9001 9002 targid_mask = ahd_inb(ahd, TARGID) 9003 | (ahd_inb(ahd, TARGID + 1) << 8); 9004 9005 targid_mask |= target_mask; 9006 ahd_outb(ahd, TARGID, targid_mask); 9007 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9008 9009 ahd_update_scsiid(ahd, targid_mask); 9010 } else { 9011 u_int our_id; 9012 char channel; 9013 9014 channel = SIM_CHANNEL(ahd, sim); 9015 our_id = SIM_SCSI_ID(ahd, sim); 9016 9017 /* 9018 * This can only happen if selections 9019 * are not enabled 9020 */ 9021 if (target != our_id) { 9022 u_int sblkctl; 9023 char cur_channel; 9024 int swap; 9025 9026 sblkctl = ahd_inb(ahd, SBLKCTL); 9027 cur_channel = (sblkctl & SELBUSB) 9028 ? 'B' : 'A'; 9029 if ((ahd->features & AHD_TWIN) == 0) 9030 cur_channel = 'A'; 9031 swap = cur_channel != channel; 9032 ahd->our_id = target; 9033 9034 if (swap) 9035 ahd_outb(ahd, SBLKCTL, 9036 sblkctl ^ SELBUSB); 9037 9038 ahd_outb(ahd, SCSIID, target); 9039 9040 if (swap) 9041 ahd_outb(ahd, SBLKCTL, sblkctl); 9042 } 9043 } 9044 } else 9045 ahd->black_hole = lstate; 9046 /* Allow select-in operations */ 9047 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9048 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9049 scsiseq1 |= ENSELI; 9050 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9051 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9052 scsiseq1 |= ENSELI; 9053 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9054 } 9055 ahd_unpause(ahd); 9056 ahd_unlock(ahd, &s); 9057 ccb->ccb_h.status = CAM_REQ_CMP; 9058 xpt_print_path(ccb->ccb_h.path); 9059 printf("Lun now enabled for target mode\n"); 9060 } else { 9061 struct scb *scb; 9062 int i, empty; 9063 9064 if (lstate == NULL) { 9065 ccb->ccb_h.status = CAM_LUN_INVALID; 9066 return; 9067 } 9068 9069 ahd_lock(ahd, &s); 9070 9071 ccb->ccb_h.status = CAM_REQ_CMP; 9072 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9073 struct ccb_hdr *ccbh; 9074 9075 ccbh = &scb->io_ctx->ccb_h; 9076 if (ccbh->func_code == XPT_CONT_TARGET_IO 9077 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9078 printf("CTIO pending\n"); 9079 ccb->ccb_h.status = CAM_REQ_INVALID; 9080 ahd_unlock(ahd, &s); 9081 return; 9082 } 9083 } 9084 9085 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9086 printf("ATIOs pending\n"); 9087 ccb->ccb_h.status = CAM_REQ_INVALID; 9088 } 9089 9090 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9091 printf("INOTs pending\n"); 9092 ccb->ccb_h.status = CAM_REQ_INVALID; 9093 } 9094 9095 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9096 ahd_unlock(ahd, &s); 9097 return; 9098 } 9099 9100 xpt_print_path(ccb->ccb_h.path); 9101 printf("Target mode disabled\n"); 9102 xpt_free_path(lstate->path); 9103 free(lstate, M_DEVBUF); 9104 9105 ahd_pause(ahd); 9106 /* Can we clean up the target too? */ 9107 if (target != CAM_TARGET_WILDCARD) { 9108 tstate->enabled_luns[lun] = NULL; 9109 ahd->enabled_luns--; 9110 for (empty = 1, i = 0; i < 8; i++) 9111 if (tstate->enabled_luns[i] != NULL) { 9112 empty = 0; 9113 break; 9114 } 9115 9116 if (empty) { 9117 ahd_free_tstate(ahd, target, channel, 9118 /*force*/FALSE); 9119 if (ahd->features & AHD_MULTI_TID) { 9120 u_int targid_mask; 9121 9122 targid_mask = ahd_inb(ahd, TARGID) 9123 | (ahd_inb(ahd, TARGID + 1) 9124 << 8); 9125 9126 targid_mask &= ~target_mask; 9127 ahd_outb(ahd, TARGID, targid_mask); 9128 ahd_outb(ahd, TARGID+1, 9129 (targid_mask >> 8)); 9130 ahd_update_scsiid(ahd, targid_mask); 9131 } 9132 } 9133 } else { 9134 9135 ahd->black_hole = NULL; 9136 9137 /* 9138 * We can't allow selections without 9139 * our black hole device. 9140 */ 9141 empty = TRUE; 9142 } 9143 if (ahd->enabled_luns == 0) { 9144 /* Disallow select-in */ 9145 u_int scsiseq1; 9146 9147 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9148 scsiseq1 &= ~ENSELI; 9149 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9150 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9151 scsiseq1 &= ~ENSELI; 9152 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9153 9154 if ((ahd->features & AHD_MULTIROLE) == 0) { 9155 printf("Configuring Initiator Mode\n"); 9156 ahd->flags &= ~AHD_TARGETROLE; 9157 ahd->flags |= AHD_INITIATORROLE; 9158 ahd_pause(ahd); 9159 ahd_loadseq(ahd); 9160 } 9161 } 9162 ahd_unpause(ahd); 9163 ahd_unlock(ahd, &s); 9164 } 9165 #endif 9166 } 9167 9168 static void 9169 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9170 { 9171 #if NOT_YET 9172 u_int scsiid_mask; 9173 u_int scsiid; 9174 9175 if ((ahd->features & AHD_MULTI_TID) == 0) 9176 panic("ahd_update_scsiid called on non-multitid unit\n"); 9177 9178 /* 9179 * Since we will rely on the TARGID mask 9180 * for selection enables, ensure that OID 9181 * in SCSIID is not set to some other ID 9182 * that we don't want to allow selections on. 9183 */ 9184 if ((ahd->features & AHD_ULTRA2) != 0) 9185 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9186 else 9187 scsiid = ahd_inb(ahd, SCSIID); 9188 scsiid_mask = 0x1 << (scsiid & OID); 9189 if ((targid_mask & scsiid_mask) == 0) { 9190 u_int our_id; 9191 9192 /* ffs counts from 1 */ 9193 our_id = ffs(targid_mask); 9194 if (our_id == 0) 9195 our_id = ahd->our_id; 9196 else 9197 our_id--; 9198 scsiid &= TID; 9199 scsiid |= our_id; 9200 } 9201 if ((ahd->features & AHD_ULTRA2) != 0) 9202 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9203 else 9204 ahd_outb(ahd, SCSIID, scsiid); 9205 #endif 9206 } 9207 9208 #ifdef AHD_TARGET_MODE 9209 void 9210 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9211 { 9212 struct target_cmd *cmd; 9213 9214 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9215 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9216 9217 /* 9218 * Only advance through the queue if we 9219 * have the resources to process the command. 9220 */ 9221 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9222 break; 9223 9224 cmd->cmd_valid = 0; 9225 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9226 ahd->shared_data_dmamap, 9227 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9228 sizeof(struct target_cmd), 9229 BUS_DMASYNC_PREREAD); 9230 ahd->tqinfifonext++; 9231 9232 /* 9233 * Lazily update our position in the target mode incoming 9234 * command queue as seen by the sequencer. 9235 */ 9236 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9237 u_int hs_mailbox; 9238 9239 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9240 hs_mailbox &= ~HOST_TQINPOS; 9241 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9242 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9243 } 9244 } 9245 } 9246 #endif 9247 9248 static int 9249 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9250 { 9251 struct ahd_tmode_tstate *tstate; 9252 struct ahd_tmode_lstate *lstate; 9253 struct ccb_accept_tio *atio; 9254 uint8_t *byte; 9255 int initiator; 9256 int target; 9257 int lun; 9258 9259 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9260 target = SCSIID_OUR_ID(cmd->scsiid); 9261 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9262 9263 byte = cmd->bytes; 9264 tstate = ahd->enabled_targets[target]; 9265 lstate = NULL; 9266 if (tstate != NULL) 9267 lstate = tstate->enabled_luns[lun]; 9268 9269 /* 9270 * Commands for disabled luns go to the black hole driver. 9271 */ 9272 if (lstate == NULL) 9273 lstate = ahd->black_hole; 9274 9275 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9276 if (atio == NULL) { 9277 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9278 /* 9279 * Wait for more ATIOs from the peripheral driver for this lun. 9280 */ 9281 return (1); 9282 } else 9283 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9284 #ifdef AHD_DEBUG 9285 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9286 printf("%s: incoming command from %d for %d:%d%s\n", 9287 ahd_name(ahd), 9288 initiator, target, lun, 9289 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9290 #endif 9291 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9292 9293 if (lstate == ahd->black_hole) { 9294 /* Fill in the wildcards */ 9295 atio->ccb_h.target_id = target; 9296 atio->ccb_h.target_lun = lun; 9297 } 9298 9299 /* 9300 * Package it up and send it off to 9301 * whomever has this lun enabled. 9302 */ 9303 atio->sense_len = 0; 9304 atio->init_id = initiator; 9305 if (byte[0] != 0xFF) { 9306 /* Tag was included */ 9307 atio->tag_action = *byte++; 9308 atio->tag_id = *byte++; 9309 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9310 } else { 9311 atio->ccb_h.flags = 0; 9312 } 9313 byte++; 9314 9315 /* Okay. Now determine the cdb size based on the command code */ 9316 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9317 case 0: 9318 atio->cdb_len = 6; 9319 break; 9320 case 1: 9321 case 2: 9322 atio->cdb_len = 10; 9323 break; 9324 case 4: 9325 atio->cdb_len = 16; 9326 break; 9327 case 5: 9328 atio->cdb_len = 12; 9329 break; 9330 case 3: 9331 default: 9332 /* Only copy the opcode. */ 9333 atio->cdb_len = 1; 9334 printf("Reserved or VU command code type encountered\n"); 9335 break; 9336 } 9337 9338 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9339 9340 atio->ccb_h.status |= CAM_CDB_RECVD; 9341 9342 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9343 /* 9344 * We weren't allowed to disconnect. 9345 * We're hanging on the bus until a 9346 * continue target I/O comes in response 9347 * to this accept tio. 9348 */ 9349 #ifdef AHD_DEBUG 9350 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9351 printf("Received Immediate Command %d:%d:%d - %p\n", 9352 initiator, target, lun, ahd->pending_device); 9353 #endif 9354 ahd->pending_device = lstate; 9355 ahd_freeze_ccb((union ccb *)atio); 9356 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9357 } 9358 xpt_done((union ccb*)atio); 9359 return (0); 9360 } 9361 9362 #endif 9363 9364 static int 9365 ahd_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 9366 bus_dma_tag_t tag; 9367 int size; 9368 int flags; 9369 bus_dmamap_t *mapp; 9370 caddr_t *vaddr; 9371 bus_addr_t *baddr; 9372 bus_dma_segment_t *seg; 9373 int *nseg; 9374 const char *myname, *what; 9375 { 9376 int error, level = 0; 9377 9378 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9379 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 9380 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9381 myname, what, error); 9382 goto out; 9383 } 9384 level++; 9385 9386 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9387 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 9388 printf("%s: failed to map DMA mem for %s, error = %d\n", 9389 myname, what, error); 9390 goto out; 9391 } 9392 level++; 9393 9394 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9395 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 9396 printf("%s: failed to create DMA map for %s, error = %d\n", 9397 myname, what, error); 9398 goto out; 9399 } 9400 level++; 9401 9402 9403 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9404 BUS_DMA_NOWAIT)) != 0) { 9405 printf("%s: failed to load DMA map for %s, error = %d\n", 9406 myname, what, error); 9407 goto out; 9408 } 9409 9410 *baddr = (*mapp)->dm_segs[0].ds_addr; 9411 9412 return 0; 9413 out: 9414 printf("ahd_createdmamem error (%d)\n", level); 9415 switch (level) { 9416 case 3: 9417 bus_dmamap_destroy(tag, *mapp); 9418 /* FALLTHROUGH */ 9419 case 2: 9420 bus_dmamem_unmap(tag, *vaddr, size); 9421 /* FALLTHROUGH */ 9422 case 1: 9423 bus_dmamem_free(tag, seg, *nseg); 9424 break; 9425 default: 9426 break; 9427 } 9428 9429 return error; 9430 } 9431 9432 static void 9433 ahd_freedmamem(tag, size, map, vaddr, seg, nseg) 9434 bus_dma_tag_t tag; 9435 int size; 9436 bus_dmamap_t map; 9437 caddr_t vaddr; 9438 bus_dma_segment_t *seg; 9439 int nseg; 9440 { 9441 9442 bus_dmamap_unload(tag, map); 9443 bus_dmamap_destroy(tag, map); 9444 bus_dmamem_unmap(tag, vaddr, size); 9445 bus_dmamem_free(tag, seg, nseg); 9446 } 9447 9448 static void 9449 ahd_update_xfer_mode(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 9450 { 9451 struct scsipi_xfer_mode xm; 9452 struct ahd_initiator_tinfo *tinfo; 9453 struct ahd_tmode_tstate *tstate; 9454 9455 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 9456 devinfo->target, &tstate); 9457 9458 xm.xm_target = devinfo->target; 9459 xm.xm_mode = 0; 9460 xm.xm_period = tinfo->curr.period; 9461 xm.xm_offset = tinfo->curr.offset; 9462 if (tinfo->curr.width == 1) 9463 xm.xm_mode |= PERIPH_CAP_WIDE16; 9464 if (tinfo->curr.period) 9465 xm.xm_mode |= PERIPH_CAP_SYNC; 9466 if (tstate->tagenable & devinfo->target_mask) 9467 xm.xm_mode |= PERIPH_CAP_TQING; 9468 9469 tinfo->goal.width = tinfo->curr.width; 9470 tinfo->goal.period = tinfo->curr.period; 9471 tinfo->goal.offset = tinfo->curr.offset; 9472 tinfo->goal.ppr_options = tinfo->curr.ppr_options; 9473 9474 ahd_update_neg_request(ahd, devinfo, tstate, 9475 tinfo, AHD_NEG_TO_GOAL); 9476 9477 scsipi_async_event(&ahd->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 9478 } 9479
Indexes created Sun Sep 28 16:09:52 GMT 2025