aic79xx.c revision 1.11
1 /* $NetBSD: aic79xx.c,v 1.11 2003/08/29 01:28:51 thorpej Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#193 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.15 2003/05/26 21:26:51 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 * - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.11 2003/08/29 01:28:51 thorpej Exp $"); 53 54 #include <dev/ic/aic79xx_osm.h> 55 #include <dev/ic/aic79xx_inline.h> 56 #include <dev/ic/aic7xxx_cam.h> 57 58 #include <dev/microcode/aic7xxx/aicasm.h> 59 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 60 61 62 /******************************** Globals *************************************/ 63 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 64 65 /***************************** Lookup Tables **********************************/ 66 char *ahd_chip_names[] = 67 { 68 "NONE", 69 "aic7901", 70 "aic7902", 71 "aic7901A" 72 }; 73 74 /* 75 * Hardware error codes. 76 */ 77 struct ahd_hard_error_entry { 78 uint8_t errno; 79 char *errmesg; 80 }; 81 82 static struct ahd_hard_error_entry ahd_hard_errors[] = { 83 { DSCTMOUT, "Discard Timer has timed out" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { CIOPARERR, "CIOBUS Parity Error" }, 89 }; 90 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 91 92 static struct ahd_phase_table_entry ahd_phase_table[] = 93 { 94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 96 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 97 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 98 { P_COMMAND, MSG_NOOP, "in Command phase" }, 99 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 100 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 101 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 102 { P_BUSFREE, MSG_NOOP, "while idle" }, 103 { 0, MSG_NOOP, "in unknown phase" } 104 }; 105 106 /* 107 * In most cases we only wish to itterate over real phases, so 108 * exclude the last element from the count. 109 */ 110 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 111 112 /* Our Sequencer Program */ 113 #include <dev/microcode/aic7xxx/aic79xx_seq.h> 114 115 /**************************** Function Declarations ***************************/ 116 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 117 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 118 u_int lqistat1); 119 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 120 u_int busfreetime); 121 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 122 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 123 static void ahd_force_renegotiation(struct ahd_softc *ahd, 124 struct ahd_devinfo *devinfo); 125 126 static struct ahd_tmode_tstate* 127 ahd_alloc_tstate(struct ahd_softc *ahd, 128 u_int scsi_id, char channel); 129 #ifdef AHD_TARGET_MODE 130 static void ahd_free_tstate(struct ahd_softc *ahd, 131 u_int scsi_id, char channel, int force); 132 #endif 133 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 134 struct ahd_initiator_tinfo *, 135 u_int *period, 136 u_int *ppr_options, 137 role_t role); 138 static void ahd_update_neg_table(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct ahd_transinfo *tinfo); 141 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 142 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo); 144 static void ahd_scb_devinfo(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo, 146 struct scb *scb); 147 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 struct scb *scb); 150 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo); 152 static void ahd_construct_sdtr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset); 155 static void ahd_construct_wdtr(struct ahd_softc *ahd, 156 struct ahd_devinfo *devinfo, 157 u_int bus_width); 158 static void ahd_construct_ppr(struct ahd_softc *ahd, 159 struct ahd_devinfo *devinfo, 160 u_int period, u_int offset, 161 u_int bus_width, u_int ppr_options); 162 static void ahd_clear_msg_state(struct ahd_softc *ahd); 163 static void ahd_handle_message_phase(struct ahd_softc *ahd); 164 typedef enum { 165 AHDMSG_1B, 166 AHDMSG_2B, 167 AHDMSG_EXT 168 } ahd_msgtype; 169 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 170 u_int msgval, int full); 171 static int ahd_parse_msg(struct ahd_softc *ahd, 172 struct ahd_devinfo *devinfo); 173 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo); 175 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 176 struct ahd_devinfo *devinfo); 177 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 178 static void ahd_handle_devreset(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 u_int lun, cam_status status, 181 char *message, int verbose_level); 182 #if AHD_TARGET_MODE 183 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 184 struct ahd_devinfo *devinfo, 185 struct scb *scb); 186 #endif 187 188 static u_int ahd_sglist_size(struct ahd_softc *ahd); 189 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 190 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 191 static int ahd_init_scbdata(struct ahd_softc *ahd); 192 static void ahd_fini_scbdata(struct ahd_softc *ahd); 193 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 194 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 195 static void ahd_add_col_list(struct ahd_softc *ahd, 196 struct scb *scb, u_int col_idx); 197 static void ahd_rem_col_list(struct ahd_softc *ahd, 198 struct scb *scb); 199 static void ahd_chip_init(struct ahd_softc *ahd); 200 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 201 struct scb *prev_scb, 202 struct scb *scb); 203 static int ahd_qinfifo_count(struct ahd_softc *ahd); 204 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 205 char channel, int lun, u_int tag, 206 role_t role, uint32_t status, 207 ahd_search_action action, 208 u_int *list_head, u_int tid); 209 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 210 u_int tid_prev, u_int tid_cur, 211 u_int tid_next); 212 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 213 u_int scbid); 214 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 215 u_int prev, u_int next, u_int tid); 216 static void ahd_reset_current_bus(struct ahd_softc *ahd); 217 static ahd_callback_t ahd_reset_poll; 218 static ahd_callback_t ahd_stat_timer; 219 #ifdef AHD_DUMP_SEQ 220 static void ahd_dumpseq(struct ahd_softc *ahd); 221 #endif 222 static void ahd_loadseq(struct ahd_softc *ahd); 223 static int ahd_check_patch(struct ahd_softc *ahd, 224 struct patch **start_patch, 225 u_int start_instr, u_int *skip_addr); 226 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 227 u_int address); 228 static void ahd_download_instr(struct ahd_softc *ahd, 229 u_int instrptr, uint8_t *dconsts); 230 static int ahd_probe_stack_size(struct ahd_softc *ahd); 231 #ifdef AHD_TARGET_MODE 232 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 233 struct ahd_tmode_lstate *lstate, 234 u_int initiator_id, 235 u_int event_type, 236 u_int event_arg); 237 static void ahd_update_scsiid(struct ahd_softc *ahd, 238 u_int targid_mask); 239 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 240 struct target_cmd *cmd); 241 #endif 242 243 /************************** Added for porting to NetBSD ***********************/ 244 static int ahd_createdmamem(bus_dma_tag_t tag, 245 int size, 246 int flags, 247 bus_dmamap_t *mapp, 248 caddr_t *vaddr, 249 bus_addr_t *baddr, 250 bus_dma_segment_t *seg, 251 int *nseg, 252 const char *myname, const char *what); 253 254 static void ahd_freedmamem(bus_dma_tag_t tag, 255 int size, 256 bus_dmamap_t map, 257 caddr_t vaddr, 258 bus_dma_segment_t *seg, 259 int nseg); 260 static void ahd_update_xfer_mode(struct ahd_softc *ahc, 261 struct ahd_devinfo *devinfo); 262 263 /******************************** Private Inlines *****************************/ 264 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 265 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 266 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 267 268 static __inline void 269 ahd_assert_atn(struct ahd_softc *ahd) 270 { 271 ahd_outb(ahd, SCSISIGO, ATNO); 272 } 273 274 /* 275 * Determine if the current connection has a packetized 276 * agreement. This does not necessarily mean that we 277 * are currently in a packetized transfer. We could 278 * just as easily be sending or receiving a message. 279 */ 280 static __inline int 281 ahd_currently_packetized(struct ahd_softc *ahd) 282 { 283 ahd_mode_state saved_modes; 284 int packetized; 285 286 saved_modes = ahd_save_modes(ahd); 287 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 288 /* 289 * The packetized bit refers to the last 290 * connection, not the current one. Check 291 * for non-zero LQISTATE instead. 292 */ 293 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 294 packetized = ahd_inb(ahd, LQISTATE) != 0; 295 } else { 296 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 297 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 298 } 299 ahd_restore_modes(ahd, saved_modes); 300 return (packetized); 301 } 302 303 static __inline int 304 ahd_set_active_fifo(struct ahd_softc *ahd) 305 { 306 u_int active_fifo; 307 308 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 309 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 310 switch (active_fifo) { 311 case 0: 312 case 1: 313 ahd_set_modes(ahd, active_fifo, active_fifo); 314 return (1); 315 default: 316 return (0); 317 } 318 } 319 320 /************************* Sequencer Execution Control ************************/ 321 /* 322 * Restart the sequencer program from address zero 323 */ 324 void 325 ahd_restart(struct ahd_softc *ahd) 326 { 327 328 ahd_pause(ahd); 329 330 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 331 332 /* No more pending messages */ 333 ahd_clear_msg_state(ahd); 334 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 335 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 336 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 337 ahd_outb(ahd, SEQINTCTL, 0); 338 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 339 ahd_outb(ahd, SEQ_FLAGS, 0); 340 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 341 ahd_outb(ahd, SAVED_LUN, 0xFF); 342 343 /* 344 * Ensure that the sequencer's idea of TQINPOS 345 * matches our own. The sequencer increments TQINPOS 346 * only after it sees a DMA complete and a reset could 347 * occur before the increment leaving the kernel to believe 348 * the command arrived but the sequencer to not. 349 */ 350 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 351 352 /* Always allow reselection */ 353 ahd_outb(ahd, SCSISEQ1, 354 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 355 /* Ensure that no DMA operations are in progress */ 356 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 357 ahd_outb(ahd, SCBHCNT, 0); 358 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 359 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 360 ahd_unpause(ahd); 361 } 362 363 void 364 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 365 { 366 ahd_mode_state saved_modes; 367 368 #ifdef AHD_DEBUG 369 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 370 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 371 #endif 372 saved_modes = ahd_save_modes(ahd); 373 ahd_set_modes(ahd, fifo, fifo); 374 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 375 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 376 ahd_outb(ahd, CCSGCTL, CCSGRESET); 377 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 378 ahd_outb(ahd, SG_STATE, 0); 379 ahd_restore_modes(ahd, saved_modes); 380 } 381 382 /************************* Input/Output Queues ********************************/ 383 /* 384 * Flush and completed commands that are sitting in the command 385 * complete queues down on the chip but have yet to be DMA'ed back up. 386 */ 387 void 388 ahd_flush_qoutfifo(struct ahd_softc *ahd) 389 { 390 struct scb *scb; 391 ahd_mode_state saved_modes; 392 u_int saved_scbptr; 393 u_int ccscbctl; 394 u_int scbid; 395 u_int next_scbid; 396 397 saved_modes = ahd_save_modes(ahd); 398 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 399 saved_scbptr = ahd_get_scbptr(ahd); 400 401 /* 402 * Wait for any inprogress DMA to complete and clear DMA state 403 * if this if for an SCB in the qinfifo. 404 */ 405 while ((ccscbctl = ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) { 406 407 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 408 if ((ccscbctl & ARRDONE) != 0) 409 break; 410 } else if ((ccscbctl & CCSCBDONE) != 0) 411 break; 412 ahd_delay(200); 413 } 414 if ((ccscbctl & CCSCBDIR) != 0) 415 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 416 417 /* 418 * Complete any SCBs that just finished being 419 * DMA'ed into the qoutfifo. 420 */ 421 ahd_run_qoutfifo(ahd); 422 423 /* 424 * Manually update/complete any completed SCBs that are waiting to be 425 * DMA'ed back up to the host. 426 */ 427 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 428 while (!SCBID_IS_NULL(scbid)) { 429 uint8_t *hscb_ptr; 430 u_int i; 431 432 ahd_set_scbptr(ahd, scbid); 433 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 434 scb = ahd_lookup_scb(ahd, scbid); 435 if (scb == NULL) { 436 printf("%s: Warning - DMA-up and complete " 437 "SCB %d invalid\n", ahd_name(ahd), scbid); 438 continue; 439 } 440 hscb_ptr = (uint8_t *)scb->hscb; 441 for (i = 0; i < sizeof(struct hardware_scb); i++) 442 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 443 444 ahd_complete_scb(ahd, scb); 445 scbid = next_scbid; 446 } 447 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 448 449 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 450 while (!SCBID_IS_NULL(scbid)) { 451 452 ahd_set_scbptr(ahd, scbid); 453 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 454 scb = ahd_lookup_scb(ahd, scbid); 455 if (scb == NULL) { 456 printf("%s: Warning - Complete SCB %d invalid\n", 457 ahd_name(ahd), scbid); 458 continue; 459 } 460 461 ahd_complete_scb(ahd, scb); 462 scbid = next_scbid; 463 } 464 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 465 ahd_set_scbptr(ahd, saved_scbptr); 466 467 /* 468 * Flush the good status FIFO for compelted packetized commands. 469 */ 470 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 471 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 472 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 473 | ahd_inb(ahd, GSFIFO); 474 scb = ahd_lookup_scb(ahd, scbid); 475 if (scb == NULL) { 476 printf("%s: Warning - GSFIFO SCB %d invalid\n", 477 ahd_name(ahd), scbid); 478 continue; 479 } 480 ahd_complete_scb(ahd, scb); 481 } 482 483 /* 484 * Restore state. 485 */ 486 ahd_restore_modes(ahd, saved_modes); 487 ahd->flags |= AHD_UPDATE_PEND_CMDS; 488 } 489 490 void 491 ahd_run_qoutfifo(struct ahd_softc *ahd) 492 { 493 struct scb *scb; 494 u_int scb_index; 495 496 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 497 panic("ahd_run_qoutfifo recursion"); 498 ahd->flags |= AHD_RUNNING_QOUTFIFO; 499 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 500 while ((ahd->qoutfifo[ahd->qoutfifonext] 501 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 502 503 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 504 & ~QOUTFIFO_ENTRY_VALID_LE); 505 scb = ahd_lookup_scb(ahd, scb_index); 506 if (scb == NULL) { 507 printf("%s: WARNING no command for scb %d " 508 "(cmdcmplt)\nQOUTPOS = %d\n", 509 ahd_name(ahd), scb_index, 510 ahd->qoutfifonext); 511 ahd_dump_card_state(ahd); 512 } else 513 ahd_complete_scb(ahd, scb); 514 515 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 516 if (ahd->qoutfifonext == 0) 517 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 518 } 519 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 520 } 521 522 /************************* Interrupt Handling *********************************/ 523 void 524 ahd_handle_hwerrint(struct ahd_softc *ahd) 525 { 526 /* 527 * Some catastrophic hardware error has occurred. 528 * Print it for the user and disable the controller. 529 */ 530 int i; 531 int error; 532 533 error = ahd_inb(ahd, ERROR); 534 for (i = 0; i < num_errors; i++) { 535 if ((error & ahd_hard_errors[i].errno) != 0) 536 printf("%s: hwerrint, %s\n", 537 ahd_name(ahd), ahd_hard_errors[i].errmesg); 538 } 539 540 ahd_dump_card_state(ahd); 541 panic("BRKADRINT"); 542 543 /* Tell everyone that this HBA is no longer available */ 544 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 545 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 546 CAM_NO_HBA); 547 548 /* Tell the system that this controller has gone away. */ 549 ahd_free(ahd); 550 } 551 552 void 553 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 554 { 555 u_int seqintcode; 556 557 /* 558 * Save the sequencer interrupt code and clear the SEQINT 559 * bit. We will unpause the sequencer, if appropriate, 560 * after servicing the request. 561 */ 562 seqintcode = ahd_inb(ahd, SEQINTCODE); 563 ahd_outb(ahd, CLRINT, CLRSEQINT); 564 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 565 /* 566 * Unpause the sequencer and let it clear 567 * SEQINT by writing NO_SEQINT to it. This 568 * will cause the sequencer to be paused again, 569 * which is the expected state of this routine. 570 */ 571 ahd_unpause(ahd); 572 while (!ahd_is_paused(ahd)) 573 ; 574 ahd_outb(ahd, CLRINT, CLRSEQINT); 575 } 576 ahd_update_modes(ahd); 577 #ifdef AHD_DEBUG 578 if ((ahd_debug & AHD_SHOW_MISC) != 0) 579 printf("%s: Handle Seqint Called for code %d\n", 580 ahd_name(ahd), seqintcode); 581 #endif 582 switch (seqintcode) { 583 case BAD_SCB_STATUS: 584 { 585 struct scb *scb; 586 u_int scbid; 587 int cmds_pending; 588 589 scbid = ahd_get_scbptr(ahd); 590 scb = ahd_lookup_scb(ahd, scbid); 591 if (scb != NULL) { 592 ahd_complete_scb(ahd, scb); 593 } else { 594 printf("%s: WARNING no command for scb %d " 595 "(bad status)\n", ahd_name(ahd), scbid); 596 ahd_dump_card_state(ahd); 597 } 598 cmds_pending = ahd_inw(ahd, CMDS_PENDING); 599 if (cmds_pending > 0) 600 ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); 601 break; 602 } 603 case ENTERING_NONPACK: 604 { 605 struct scb *scb; 606 u_int scbid; 607 608 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 609 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 610 scbid = ahd_get_scbptr(ahd); 611 scb = ahd_lookup_scb(ahd, scbid); 612 if (scb == NULL) { 613 /* 614 * Somehow need to know if this 615 * is from a selection or reselection. 616 * From that, we can termine target 617 * ID so we at least have an I_T nexus. 618 */ 619 } else { 620 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 621 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 622 ahd_outb(ahd, SEQ_FLAGS, 0x0); 623 } 624 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 625 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 626 /* 627 * Phase change after read stream with 628 * CRC error with P0 asserted on last 629 * packet. 630 */ 631 #ifdef AHD_DEBUG 632 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 633 printf("%s: Assuming LQIPHASE_NLQ with " 634 "P0 assertion\n", ahd_name(ahd)); 635 #endif 636 } 637 #ifdef AHD_DEBUG 638 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 639 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 640 #endif 641 break; 642 } 643 case INVALID_SEQINT: 644 printf("%s: Invalid Sequencer interrupt occurred.\n", 645 ahd_name(ahd)); 646 ahd_dump_card_state(ahd); 647 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 648 break; 649 case STATUS_OVERRUN: 650 { 651 struct scb *scb; 652 u_int scbid; 653 654 scbid = ahd_get_scbptr(ahd); 655 scb = ahd_lookup_scb(ahd, scbid); 656 if (scb != NULL) 657 ahd_print_path(ahd, scb); 658 else 659 printf("%s: ", ahd_name(ahd)); 660 printf("SCB %d Packetized Status Overrun", scbid); 661 ahd_dump_card_state(ahd); 662 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 663 break; 664 } 665 case CFG4ISTAT_INTR: 666 { 667 struct scb *scb; 668 u_int scbid; 669 670 scbid = ahd_get_scbptr(ahd); 671 scb = ahd_lookup_scb(ahd, scbid); 672 if (scb == NULL) { 673 ahd_dump_card_state(ahd); 674 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 675 panic("For safety"); 676 } 677 ahd_outq(ahd, HADDR, scb->sense_busaddr); 678 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 679 ahd_outb(ahd, HCNT + 2, 0); 680 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 681 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 682 break; 683 } 684 case ILLEGAL_PHASE: 685 { 686 u_int bus_phase; 687 688 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 689 printf("%s: ILLEGAL_PHASE 0x%x\n", 690 ahd_name(ahd), bus_phase); 691 692 switch (bus_phase) { 693 case P_DATAOUT: 694 case P_DATAIN: 695 case P_DATAOUT_DT: 696 case P_DATAIN_DT: 697 case P_MESGOUT: 698 case P_STATUS: 699 case P_MESGIN: 700 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 701 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 702 break; 703 case P_COMMAND: 704 { 705 struct ahd_devinfo devinfo; 706 struct scb *scb; 707 struct ahd_initiator_tinfo *targ_info; 708 struct ahd_tmode_tstate *tstate; 709 struct ahd_transinfo *tinfo; 710 u_int scbid; 711 712 /* 713 * If a target takes us into the command phase 714 * assume that it has been externally reset and 715 * has thus lost our previous packetized negotiation 716 * agreement. Since we have not sent an identify 717 * message and may not have fully qualified the 718 * connection, we change our command to TUR, assert 719 * ATN and ABORT the task when we go to message in 720 * phase. The OSM will see the REQUEUE_REQUEST 721 * status and retry the command. 722 */ 723 scbid = ahd_get_scbptr(ahd); 724 scb = ahd_lookup_scb(ahd, scbid); 725 if (scb == NULL) { 726 printf("Invalid phase with no valid SCB. " 727 "Resetting bus.\n"); 728 ahd_reset_channel(ahd, 'A', 729 /*Initiate Reset*/TRUE); 730 break; 731 } 732 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 733 SCB_GET_TARGET(ahd, scb), 734 SCB_GET_LUN(scb), 735 SCB_GET_CHANNEL(ahd, scb), 736 ROLE_INITIATOR); 737 targ_info = ahd_fetch_transinfo(ahd, 738 devinfo.channel, 739 devinfo.our_scsiid, 740 devinfo.target, 741 &tstate); 742 tinfo = &targ_info->curr; 743 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 744 AHD_TRANS_ACTIVE, /*paused*/TRUE); 745 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 746 /*offset*/0, /*ppr_options*/0, 747 AHD_TRANS_ACTIVE, /*paused*/TRUE); 748 ahd_outb(ahd, SCB_CDB_STORE, 0); 749 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 750 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 751 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 752 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 753 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 754 ahd_outb(ahd, SCB_CDB_LEN, 6); 755 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 756 scb->hscb->control |= MK_MESSAGE; 757 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 758 ahd_outb(ahd, MSG_OUT, HOST_MSG); 759 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 760 /* 761 * The lun is 0, regardless of the SCB's lun 762 * as we have not sent an identify message. 763 */ 764 ahd_outb(ahd, SAVED_LUN, 0); 765 ahd_outb(ahd, SEQ_FLAGS, 0); 766 ahd_assert_atn(ahd); 767 scb->flags &= ~(SCB_PACKETIZED); 768 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 769 ahd_freeze_devq(ahd, scb); 770 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 771 ahd_freeze_scb(scb); 772 773 /* 774 * Allow the sequencer to continue with 775 * non-pack processing. 776 */ 777 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 778 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 779 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 780 ahd_outb(ahd, CLRLQOINT1, 0); 781 } 782 #ifdef AHD_DEBUG 783 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 784 ahd_print_path(ahd, scb); 785 printf("Unexpected command phase from " 786 "packetized target\n"); 787 } 788 #endif 789 break; 790 } 791 } 792 break; 793 } 794 case CFG4OVERRUN: 795 { 796 struct scb *scb; 797 u_int scb_index; 798 799 #ifdef AHD_DEBUG 800 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 801 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 802 ahd_inb(ahd, MODE_PTR)); 803 } 804 #endif 805 scb_index = ahd_get_scbptr(ahd); 806 scb = ahd_lookup_scb(ahd, scb_index); 807 if (scb == NULL) { 808 /* 809 * Attempt to transfer to an SCB that is 810 * not outstanding. 811 */ 812 ahd_assert_atn(ahd); 813 ahd_outb(ahd, MSG_OUT, HOST_MSG); 814 ahd->msgout_buf[0] = MSG_ABORT_TASK; 815 ahd->msgout_len = 1; 816 ahd->msgout_index = 0; 817 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 818 /* 819 * Clear status received flag to prevent any 820 * attempt to complete this bogus SCB. 821 */ 822 ahd_outb(ahd, SCB_CONTROL, 823 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 824 } 825 break; 826 } 827 case DUMP_CARD_STATE: 828 { 829 ahd_dump_card_state(ahd); 830 break; 831 } 832 case PDATA_REINIT: 833 { 834 #ifdef AHD_DEBUG 835 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 836 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 837 "SG_CACHE_SHADOW = 0x%x\n", 838 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 839 ahd_inb(ahd, SG_CACHE_SHADOW)); 840 } 841 #endif 842 ahd_reinitialize_dataptrs(ahd); 843 break; 844 } 845 case HOST_MSG_LOOP: 846 { 847 struct ahd_devinfo devinfo; 848 849 /* 850 * The sequencer has encountered a message phase 851 * that requires host assistance for completion. 852 * While handling the message phase(s), we will be 853 * notified by the sequencer after each byte is 854 * transfered so we can track bus phase changes. 855 * 856 * If this is the first time we've seen a HOST_MSG_LOOP 857 * interrupt, initialize the state of the host message 858 * loop. 859 */ 860 ahd_fetch_devinfo(ahd, &devinfo); 861 if (ahd->msg_type == MSG_TYPE_NONE) { 862 struct scb *scb; 863 u_int scb_index; 864 u_int bus_phase; 865 866 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 867 if (bus_phase != P_MESGIN 868 && bus_phase != P_MESGOUT) { 869 printf("ahd_intr: HOST_MSG_LOOP bad " 870 "phase 0x%x\n", bus_phase); 871 /* 872 * Probably transitioned to bus free before 873 * we got here. Just punt the message. 874 */ 875 ahd_dump_card_state(ahd); 876 ahd_clear_intstat(ahd); 877 ahd_restart(ahd); 878 return; 879 } 880 881 scb_index = ahd_get_scbptr(ahd); 882 scb = ahd_lookup_scb(ahd, scb_index); 883 if (devinfo.role == ROLE_INITIATOR) { 884 if (bus_phase == P_MESGOUT) 885 ahd_setup_initiator_msgout(ahd, 886 &devinfo, 887 scb); 888 else { 889 ahd->msg_type = 890 MSG_TYPE_INITIATOR_MSGIN; 891 ahd->msgin_index = 0; 892 } 893 } 894 #if AHD_TARGET_MODE 895 else { 896 if (bus_phase == P_MESGOUT) { 897 ahd->msg_type = 898 MSG_TYPE_TARGET_MSGOUT; 899 ahd->msgin_index = 0; 900 } 901 else 902 ahd_setup_target_msgin(ahd, 903 &devinfo, 904 scb); 905 } 906 #endif 907 } 908 909 ahd_handle_message_phase(ahd); 910 break; 911 } 912 case NO_MATCH: 913 { 914 /* Ensure we don't leave the selection hardware on */ 915 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 916 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 917 918 printf("%s:%c:%d: no active SCB for reconnecting " 919 "target - issuing BUS DEVICE RESET\n", 920 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 921 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 922 "REG0 == 0x%x ACCUM = 0x%x\n", 923 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 924 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 925 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 926 "SINDEX == 0x%x\n", 927 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 928 ahd_find_busy_tcl(ahd, 929 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 930 ahd_inb(ahd, SAVED_LUN))), 931 ahd_inw(ahd, SINDEX)); 932 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 933 "SCB_CONTROL == 0x%x\n", 934 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 935 ahd_inb_scbram(ahd, SCB_LUN), 936 ahd_inb_scbram(ahd, SCB_CONTROL)); 937 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 938 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 939 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 940 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 941 ahd_dump_card_state(ahd); 942 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 943 ahd->msgout_len = 1; 944 ahd->msgout_index = 0; 945 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 946 ahd_outb(ahd, MSG_OUT, HOST_MSG); 947 ahd_assert_atn(ahd); 948 break; 949 } 950 case PROTO_VIOLATION: 951 { 952 ahd_handle_proto_violation(ahd); 953 break; 954 } 955 case IGN_WIDE_RES: 956 { 957 struct ahd_devinfo devinfo; 958 959 ahd_fetch_devinfo(ahd, &devinfo); 960 ahd_handle_ign_wide_residue(ahd, &devinfo); 961 break; 962 } 963 case BAD_PHASE: 964 { 965 u_int lastphase; 966 967 lastphase = ahd_inb(ahd, LASTPHASE); 968 printf("%s:%c:%d: unknown scsi bus phase %x, " 969 "lastphase = 0x%x. Attempting to continue\n", 970 ahd_name(ahd), 'A', 971 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 972 lastphase, ahd_inb(ahd, SCSISIGI)); 973 break; 974 } 975 case MISSED_BUSFREE: 976 { 977 u_int lastphase; 978 979 lastphase = ahd_inb(ahd, LASTPHASE); 980 printf("%s:%c:%d: Missed busfree. " 981 "Lastphase = 0x%x, Curphase = 0x%x\n", 982 ahd_name(ahd), 'A', 983 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 984 lastphase, ahd_inb(ahd, SCSISIGI)); 985 ahd_restart(ahd); 986 return; 987 } 988 case DATA_OVERRUN: 989 { 990 /* 991 * When the sequencer detects an overrun, it 992 * places the controller in "BITBUCKET" mode 993 * and allows the target to complete its transfer. 994 * Unfortunately, none of the counters get updated 995 * when the controller is in this mode, so we have 996 * no way of knowing how large the overrun was. 997 */ 998 struct scb *scb; 999 u_int scbindex; 1000 #ifdef AHD_DEBUG 1001 u_int lastphase; 1002 #endif 1003 1004 scbindex = ahd_get_scbptr(ahd); 1005 scb = ahd_lookup_scb(ahd, scbindex); 1006 #ifdef AHD_DEBUG 1007 lastphase = ahd_inb(ahd, LASTPHASE); 1008 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1009 ahd_print_path(ahd, scb); 1010 printf("data overrun detected %s. Tag == 0x%x.\n", 1011 ahd_lookup_phase_entry(lastphase)->phasemsg, 1012 SCB_GET_TAG(scb)); 1013 ahd_print_path(ahd, scb); 1014 printf("%s seen Data Phase. Length = %ld. " 1015 "NumSGs = %d.\n", 1016 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1017 ? "Have" : "Haven't", 1018 ahd_get_transfer_length(scb), scb->sg_count); 1019 ahd_dump_sglist(scb); 1020 } 1021 #endif 1022 1023 /* 1024 * Set this and it will take effect when the 1025 * target does a command complete. 1026 */ 1027 ahd_freeze_devq(ahd, scb); 1028 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1029 ahd_freeze_scb(scb); 1030 break; 1031 } 1032 case MKMSG_FAILED: 1033 { 1034 struct ahd_devinfo devinfo; 1035 struct scb *scb; 1036 u_int scbid; 1037 1038 ahd_fetch_devinfo(ahd, &devinfo); 1039 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1040 ahd_name(ahd), devinfo.channel, devinfo.target, 1041 devinfo.lun); 1042 scbid = ahd_get_scbptr(ahd); 1043 scb = ahd_lookup_scb(ahd, scbid); 1044 if (scb != NULL 1045 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1046 /* 1047 * Ensure that we didn't put a second instance of this 1048 * SCB into the QINFIFO. 1049 */ 1050 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1051 SCB_GET_CHANNEL(ahd, scb), 1052 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1053 ROLE_INITIATOR, /*status*/0, 1054 SEARCH_REMOVE); 1055 ahd_outb(ahd, SCB_CONTROL, 1056 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1057 break; 1058 } 1059 case TASKMGMT_FUNC_COMPLETE: 1060 { 1061 u_int scbid; 1062 struct scb *scb; 1063 1064 scbid = ahd_get_scbptr(ahd); 1065 scb = ahd_lookup_scb(ahd, scbid); 1066 if (scb != NULL) { 1067 u_int lun; 1068 u_int tag; 1069 cam_status error; 1070 1071 ahd_print_path(ahd, scb); 1072 printf("Task Management Func 0x%x Complete\n", 1073 scb->hscb->task_management); 1074 lun = CAM_LUN_WILDCARD; 1075 tag = SCB_LIST_NULL; 1076 1077 switch (scb->hscb->task_management) { 1078 case SIU_TASKMGMT_ABORT_TASK: 1079 tag = SCB_GET_TAG(scb); 1080 case SIU_TASKMGMT_ABORT_TASK_SET: 1081 case SIU_TASKMGMT_CLEAR_TASK_SET: 1082 lun = scb->hscb->lun; 1083 error = CAM_REQ_ABORTED; 1084 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1085 'A', lun, tag, ROLE_INITIATOR, 1086 error); 1087 break; 1088 case SIU_TASKMGMT_LUN_RESET: 1089 lun = scb->hscb->lun; 1090 case SIU_TASKMGMT_TARGET_RESET: 1091 { 1092 struct ahd_devinfo devinfo; 1093 1094 ahd_scb_devinfo(ahd, &devinfo, scb); 1095 error = CAM_BDR_SENT; 1096 ahd_handle_devreset(ahd, &devinfo, lun, 1097 CAM_BDR_SENT, 1098 lun != CAM_LUN_WILDCARD 1099 ? "Lun Reset" 1100 : "Target Reset", 1101 /*verbose_level*/0); 1102 break; 1103 } 1104 default: 1105 panic("Unexpected TaskMgmt Func\n"); 1106 break; 1107 } 1108 } 1109 break; 1110 } 1111 case TASKMGMT_CMD_CMPLT_OKAY: 1112 { 1113 u_int scbid; 1114 struct scb *scb; 1115 1116 /* 1117 * An ABORT TASK TMF failed to be delivered before 1118 * the targeted command completed normally. 1119 */ 1120 scbid = ahd_get_scbptr(ahd); 1121 scb = ahd_lookup_scb(ahd, scbid); 1122 if (scb != NULL) { 1123 /* 1124 * Remove the second instance of this SCB from 1125 * the QINFIFO if it is still there. 1126 */ 1127 ahd_print_path(ahd, scb); 1128 printf("SCB completes before TMF\n"); 1129 /* 1130 * Handle losing the race. Wait until any 1131 * current selection completes. We will then 1132 * set the TMF back to zero in this SCB so that 1133 * the sequencer doesn't bother to issue another 1134 * sequencer interrupt for its completion. 1135 */ 1136 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1137 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1138 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1139 ; 1140 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1141 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1142 SCB_GET_CHANNEL(ahd, scb), 1143 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1144 ROLE_INITIATOR, /*status*/0, 1145 SEARCH_REMOVE); 1146 } 1147 break; 1148 } 1149 case TRACEPOINT0: 1150 case TRACEPOINT1: 1151 case TRACEPOINT2: 1152 case TRACEPOINT3: 1153 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1154 seqintcode - TRACEPOINT0); 1155 break; 1156 case NO_SEQINT: 1157 break; 1158 case SAW_HWERR: 1159 ahd_handle_hwerrint(ahd); 1160 break; 1161 default: 1162 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1163 seqintcode); 1164 break; 1165 } 1166 /* 1167 * The sequencer is paused immediately on 1168 * a SEQINT, so we should restart it when 1169 * we're done. 1170 */ 1171 ahd_unpause(ahd); 1172 } 1173 1174 void 1175 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1176 { 1177 struct scb *scb; 1178 u_int status0; 1179 u_int status3; 1180 u_int status; 1181 u_int lqistat1; 1182 u_int lqostat0; 1183 u_int scbid; 1184 u_int busfreetime; 1185 1186 ahd_update_modes(ahd); 1187 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1188 1189 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1190 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1191 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1192 lqistat1 = ahd_inb(ahd, LQISTAT1); 1193 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1194 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1195 if ((status0 & (SELDI|SELDO)) != 0) { 1196 u_int simode0; 1197 1198 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1199 simode0 = ahd_inb(ahd, SIMODE0); 1200 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1201 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1202 } 1203 scbid = ahd_get_scbptr(ahd); 1204 scb = ahd_lookup_scb(ahd, scbid); 1205 if (scb != NULL 1206 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1207 scb = NULL; 1208 1209 /* Make sure the sequencer is in a safe location. */ 1210 ahd_clear_critical_section(ahd); 1211 1212 if ((status0 & IOERR) != 0) { 1213 u_int now_lvd; 1214 1215 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1216 printf("%s: Transceiver State Has Changed to %s mode\n", 1217 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1218 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1219 /* 1220 * A change in I/O mode is equivalent to a bus reset. 1221 */ 1222 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1223 ahd_pause(ahd); 1224 ahd_setup_iocell_workaround(ahd); 1225 ahd_unpause(ahd); 1226 } else if ((status0 & OVERRUN) != 0) { 1227 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1228 ahd_name(ahd)); 1229 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1230 } else if ((status & SCSIRSTI) != 0) { 1231 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1232 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1233 } else if ((status & SCSIPERR) != 0) { 1234 ahd_handle_transmission_error(ahd); 1235 } else if (lqostat0 != 0) { 1236 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1237 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1238 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1239 ahd_outb(ahd, CLRLQOINT1, 0); 1240 } 1241 } else if ((status & SELTO) != 0) { 1242 u_int scbid; 1243 1244 /* Stop the selection */ 1245 ahd_outb(ahd, SCSISEQ0, 0); 1246 1247 /* No more pending messages */ 1248 ahd_clear_msg_state(ahd); 1249 1250 /* Clear interrupt state */ 1251 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1252 1253 /* 1254 * Although the driver does not care about the 1255 * 'Selection in Progress' status bit, the busy 1256 * LED does. SELINGO is only cleared by a sucessfull 1257 * selection, so we must manually clear it to insure 1258 * the LED turns off just incase no future successful 1259 * selections occur (e.g. no devices on the bus). 1260 */ 1261 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1262 1263 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1264 scb = ahd_lookup_scb(ahd, scbid); 1265 if (scb == NULL) { 1266 printf("%s: ahd_intr - referenced scb not " 1267 "valid during SELTO scb(0x%x)\n", 1268 ahd_name(ahd), scbid); 1269 ahd_dump_card_state(ahd); 1270 } else { 1271 struct ahd_devinfo devinfo; 1272 #ifdef AHD_DEBUG 1273 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1274 ahd_print_path(ahd, scb); 1275 printf("Saw Selection Timeout for SCB 0x%x\n", 1276 scbid); 1277 } 1278 #endif 1279 /* 1280 * Force a renegotiation with this target just in 1281 * case the cable was pulled and will later be 1282 * re-attached. The target may forget its negotiation 1283 * settings with us should it attempt to reselect 1284 * during the interruption. The target will not issue 1285 * a unit attention in this case, so we must always 1286 * renegotiate. 1287 */ 1288 ahd_scb_devinfo(ahd, &devinfo, scb); 1289 ahd_force_renegotiation(ahd, &devinfo); 1290 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1291 ahd_freeze_devq(ahd, scb); 1292 } 1293 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1294 ahd_iocell_first_selection(ahd); 1295 ahd_unpause(ahd); 1296 } else if ((status0 & (SELDI|SELDO)) != 0) { 1297 ahd_iocell_first_selection(ahd); 1298 ahd_unpause(ahd); 1299 } else if (status3 != 0) { 1300 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1301 ahd_name(ahd), status3); 1302 ahd_outb(ahd, CLRSINT3, status3); 1303 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1304 ahd_handle_lqiphase_error(ahd, lqistat1); 1305 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1306 /* 1307 * This status can be delayed during some 1308 * streaming operations. The SCSIPHASE 1309 * handler has already dealt with this case 1310 * so just clear the error. 1311 */ 1312 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1313 } else if ((status & BUSFREE) != 0) { 1314 u_int lqostat1; 1315 int restart; 1316 int clear_fifo; 1317 int packetized; 1318 u_int mode; 1319 1320 /* 1321 * Clear our selection hardware as soon as possible. 1322 * We may have an entry in the waiting Q for this target, 1323 * that is affected by this busfree and we don't want to 1324 * go about selecting the target while we handle the event. 1325 */ 1326 ahd_outb(ahd, SCSISEQ0, 0); 1327 1328 /* 1329 * Determine what we were up to at the time of 1330 * the busfree. 1331 */ 1332 mode = AHD_MODE_SCSI; 1333 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1334 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1335 switch (busfreetime) { 1336 case BUSFREE_DFF0: 1337 case BUSFREE_DFF1: 1338 { 1339 u_int scbid; 1340 struct scb *scb; 1341 1342 mode = busfreetime == BUSFREE_DFF0 1343 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1344 ahd_set_modes(ahd, mode, mode); 1345 scbid = ahd_get_scbptr(ahd); 1346 scb = ahd_lookup_scb(ahd, scbid); 1347 if (scb == NULL) { 1348 printf("%s: Invalid SCB %d in DFF%d " 1349 "during unexpected busfree\n", 1350 ahd_name(ahd), scbid, mode); 1351 packetized = 0; 1352 } else 1353 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1354 clear_fifo = 1; 1355 break; 1356 } 1357 case BUSFREE_LQO: 1358 clear_fifo = 0; 1359 packetized = 1; 1360 break; 1361 default: 1362 clear_fifo = 0; 1363 packetized = (lqostat1 & LQOBUSFREE) != 0; 1364 if (!packetized 1365 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1366 packetized = 1; 1367 break; 1368 } 1369 1370 #ifdef AHD_DEBUG 1371 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1372 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1373 busfreetime); 1374 #endif 1375 /* 1376 * Busfrees that occur in non-packetized phases are 1377 * handled by the nonpkt_busfree handler. 1378 */ 1379 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1380 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1381 } else { 1382 packetized = 0; 1383 restart = ahd_handle_nonpkt_busfree(ahd); 1384 } 1385 /* 1386 * Clear the busfree interrupt status. The setting of 1387 * the interrupt is a pulse, so in a perfect world, we 1388 * would not need to muck with the ENBUSFREE logic. This 1389 * would ensure that if the bus moves on to another 1390 * connection, busfree protection is still in force. If 1391 * BUSFREEREV is broken, however, we must manually clear 1392 * the ENBUSFREE if the busfree occurred during a non-pack 1393 * connection so that we don't get false positives during 1394 * future, packetized, connections. 1395 */ 1396 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1397 if (packetized == 0 1398 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1399 ahd_outb(ahd, SIMODE1, 1400 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1401 1402 if (clear_fifo) 1403 ahd_clear_fifo(ahd, mode); 1404 1405 ahd_clear_msg_state(ahd); 1406 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1407 if (restart) { 1408 ahd_restart(ahd); 1409 } else { 1410 ahd_unpause(ahd); 1411 } 1412 } else { 1413 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1414 ahd_name(ahd), status); 1415 ahd_dump_card_state(ahd); 1416 ahd_clear_intstat(ahd); 1417 ahd_unpause(ahd); 1418 } 1419 } 1420 1421 static void 1422 ahd_handle_transmission_error(struct ahd_softc *ahd) 1423 { 1424 struct scb *scb; 1425 u_int scbid; 1426 u_int lqistat1; 1427 u_int lqistat2; 1428 u_int msg_out; 1429 u_int curphase; 1430 u_int lastphase; 1431 u_int perrdiag; 1432 u_int cur_col; 1433 int silent; 1434 1435 scb = NULL; 1436 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1437 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1438 lqistat2 = ahd_inb(ahd, LQISTAT2); 1439 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1440 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1441 u_int lqistate; 1442 1443 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1444 lqistate = ahd_inb(ahd, LQISTATE); 1445 if ((lqistate >= 0x1E && lqistate <= 0x24) 1446 || (lqistate == 0x29)) { 1447 #ifdef AHD_DEBUG 1448 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1449 printf("%s: NLQCRC found via LQISTATE\n", 1450 ahd_name(ahd)); 1451 } 1452 #endif 1453 lqistat1 |= LQICRCI_NLQ; 1454 } 1455 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1456 } 1457 1458 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1459 lastphase = ahd_inb(ahd, LASTPHASE); 1460 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1461 perrdiag = ahd_inb(ahd, PERRDIAG); 1462 msg_out = MSG_INITIATOR_DET_ERR; 1463 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1464 1465 /* 1466 * Try to find the SCB associated with this error. 1467 */ 1468 silent = FALSE; 1469 if (lqistat1 == 0 1470 || (lqistat1 & LQICRCI_NLQ) != 0) { 1471 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1472 ahd_set_active_fifo(ahd); 1473 scbid = ahd_get_scbptr(ahd); 1474 scb = ahd_lookup_scb(ahd, scbid); 1475 if (scb != NULL && SCB_IS_SILENT(scb)) 1476 silent = TRUE; 1477 } 1478 1479 cur_col = 0; 1480 if (silent == FALSE) { 1481 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1482 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1483 ahd_lastphase_print(lastphase, &cur_col, 50); 1484 ahd_scsisigi_print(curphase, &cur_col, 50); 1485 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1486 printf("\n"); 1487 ahd_dump_card_state(ahd); 1488 } 1489 1490 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1491 if (silent == FALSE) { 1492 printf("%s: Gross protocol error during incoming " 1493 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1494 ahd_name(ahd), lqistat1); 1495 } 1496 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1497 return; 1498 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1499 /* 1500 * A CRC error has been detected on an incoming LQ. 1501 * The bus is currently hung on the last ACK. 1502 * Hit LQIRETRY to release the last ack, and 1503 * wait for the sequencer to determine that ATNO 1504 * is asserted while in message out to take us 1505 * to our host message loop. No NONPACKREQ or 1506 * LQIPHASE type errors will occur in this 1507 * scenario. After this first LQIRETRY, the LQI 1508 * manager will be in ISELO where it will 1509 * happily sit until another packet phase begins. 1510 * Unexpected bus free detection is enabled 1511 * through any phases that occur after we release 1512 * this last ack until the LQI manager sees a 1513 * packet phase. This implies we may have to 1514 * ignore a perfectly valid "unexected busfree" 1515 * after our "initiator detected error" message is 1516 * sent. A busfree is the expected response after 1517 * we tell the target that it's L_Q was corrupted. 1518 * (SPI4R09 10.7.3.3.3) 1519 */ 1520 ahd_outb(ahd, LQCTL2, LQIRETRY); 1521 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1522 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1523 /* 1524 * We detected a CRC error in a NON-LQ packet. 1525 * The hardware has varying behavior in this situation 1526 * depending on whether this packet was part of a 1527 * stream or not. 1528 * 1529 * PKT by PKT mode: 1530 * The hardware has already acked the complete packet. 1531 * If the target honors our outstanding ATN condition, 1532 * we should be (or soon will be) in MSGOUT phase. 1533 * This will trigger the LQIPHASE_LQ status bit as the 1534 * hardware was expecting another LQ. Unexpected 1535 * busfree detection is enabled. Once LQIPHASE_LQ is 1536 * true (first entry into host message loop is much 1537 * the same), we must clear LQIPHASE_LQ and hit 1538 * LQIRETRY so the hardware is ready to handle 1539 * a future LQ. NONPACKREQ will not be asserted again 1540 * once we hit LQIRETRY until another packet is 1541 * processed. The target may either go busfree 1542 * or start another packet in response to our message. 1543 * 1544 * Read Streaming P0 asserted: 1545 * If we raise ATN and the target completes the entire 1546 * stream (P0 asserted during the last packet), the 1547 * hardware will ack all data and return to the ISTART 1548 * state. When the target reponds to our ATN condition, 1549 * LQIPHASE_LQ will be asserted. We should respond to 1550 * this with an LQIRETRY to prepare for any future 1551 * packets. NONPACKREQ will not be asserted again 1552 * once we hit LQIRETRY until another packet is 1553 * processed. The target may either go busfree or 1554 * start another packet in response to our message. 1555 * Busfree detection is enabled. 1556 * 1557 * Read Streaming P0 not asserted: 1558 * If we raise ATN and the target transitions to 1559 * MSGOUT in or after a packet where P0 is not 1560 * asserted, the hardware will assert LQIPHASE_NLQ. 1561 * We should respond to the LQIPHASE_NLQ with an 1562 * LQIRETRY. Should the target stay in a non-pkt 1563 * phase after we send our message, the hardware 1564 * will assert LQIPHASE_LQ. Recovery is then just as 1565 * listed above for the read streaming with P0 asserted. 1566 * Busfree detection is enabled. 1567 */ 1568 if (silent == FALSE) 1569 printf("LQICRC_NLQ\n"); 1570 if (scb == NULL) { 1571 printf("%s: No SCB valid for LQICRC_NLQ. " 1572 "Resetting bus\n", ahd_name(ahd)); 1573 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1574 return; 1575 } 1576 } else if ((lqistat1 & LQIBADLQI) != 0) { 1577 printf("Need to handle BADLQI!\n"); 1578 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1579 return; 1580 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1581 if ((curphase & ~P_DATAIN_DT) != 0) { 1582 /* Ack the byte. So we can continue. */ 1583 if (silent == FALSE) 1584 printf("Acking %s to clear perror\n", 1585 ahd_lookup_phase_entry(curphase)->phasemsg); 1586 ahd_inb(ahd, SCSIDAT); 1587 } 1588 1589 if (curphase == P_MESGIN) 1590 msg_out = MSG_PARITY_ERROR; 1591 } 1592 1593 /* 1594 * We've set the hardware to assert ATN if we 1595 * get a parity error on "in" phases, so all we 1596 * need to do is stuff the message buffer with 1597 * the appropriate message. "In" phases have set 1598 * mesg_out to something other than MSG_NOP. 1599 */ 1600 ahd->send_msg_perror = msg_out; 1601 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1602 scb->flags |= SCB_TRANSMISSION_ERROR; 1603 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1604 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1605 ahd_unpause(ahd); 1606 } 1607 1608 static void 1609 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1610 { 1611 /* 1612 * Clear the sources of the interrupts. 1613 */ 1614 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1615 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1616 1617 /* 1618 * If the "illegal" phase changes were in response 1619 * to our ATN to flag a CRC error, AND we ended up 1620 * on packet boundaries, clear the error, restart the 1621 * LQI manager as appropriate, and go on our merry 1622 * way toward sending the message. Otherwise, reset 1623 * the bus to clear the error. 1624 */ 1625 ahd_set_active_fifo(ahd); 1626 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1627 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1628 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1629 printf("LQIRETRY for LQIPHASE_LQ\n"); 1630 ahd_outb(ahd, LQCTL2, LQIRETRY); 1631 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1632 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1633 ahd_outb(ahd, LQCTL2, LQIRETRY); 1634 } else 1635 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1636 ahd_dump_card_state(ahd); 1637 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1638 ahd_unpause(ahd); 1639 } else { 1640 printf("Reseting Channel for LQI Phase error\n"); 1641 ahd_dump_card_state(ahd); 1642 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1643 } 1644 } 1645 1646 /* 1647 * Packetized unexpected or expected busfree. 1648 * Entered in mode based on busfreetime. 1649 */ 1650 static int 1651 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1652 { 1653 u_int lqostat1; 1654 1655 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1656 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1657 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1658 if ((lqostat1 & LQOBUSFREE) != 0) { 1659 struct scb *scb; 1660 u_int scbid; 1661 u_int saved_scbptr; 1662 u_int waiting_h; 1663 u_int waiting_t; 1664 u_int next; 1665 1666 if ((busfreetime & BUSFREE_LQO) == 0) 1667 printf("%s: Warning, BUSFREE time is 0x%x. " 1668 "Expected BUSFREE_LQO.\n", 1669 ahd_name(ahd), busfreetime); 1670 /* 1671 * The LQO manager detected an unexpected busfree 1672 * either: 1673 * 1674 * 1) During an outgoing LQ. 1675 * 2) After an outgoing LQ but before the first 1676 * REQ of the command packet. 1677 * 3) During an outgoing command packet. 1678 * 1679 * In all cases, CURRSCB is pointing to the 1680 * SCB that encountered the failure. Clean 1681 * up the queue, clear SELDO and LQOBUSFREE, 1682 * and allow the sequencer to restart the select 1683 * out at its lesure. 1684 */ 1685 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1686 scbid = ahd_inw(ahd, CURRSCB); 1687 scb = ahd_lookup_scb(ahd, scbid); 1688 if (scb == NULL) 1689 panic("SCB not valid during LQOBUSFREE"); 1690 /* 1691 * Clear the status. 1692 */ 1693 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1694 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1695 ahd_outb(ahd, CLRLQOINT1, 0); 1696 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1697 ahd_flush_device_writes(ahd); 1698 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1699 1700 /* 1701 * Return the LQO manager to its idle loop. It will 1702 * not do this automatically if the busfree occurs 1703 * after the first REQ of either the LQ or command 1704 * packet or between the LQ and command packet. 1705 */ 1706 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1707 1708 /* 1709 * Update the waiting for selection queue so 1710 * we restart on the correct SCB. 1711 */ 1712 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1713 saved_scbptr = ahd_get_scbptr(ahd); 1714 if (waiting_h != scbid) { 1715 1716 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1717 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1718 if (waiting_t == waiting_h) { 1719 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1720 next = SCB_LIST_NULL; 1721 } else { 1722 ahd_set_scbptr(ahd, waiting_h); 1723 next = ahd_inw_scbram(ahd, SCB_NEXT2); 1724 } 1725 ahd_set_scbptr(ahd, scbid); 1726 ahd_outw(ahd, SCB_NEXT2, next); 1727 } 1728 ahd_set_scbptr(ahd, saved_scbptr); 1729 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1730 if (SCB_IS_SILENT(scb) == FALSE) { 1731 ahd_print_path(ahd, scb); 1732 printf("Probable outgoing LQ CRC error. " 1733 "Retrying command\n"); 1734 } 1735 scb->crc_retry_count++; 1736 } else { 1737 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1738 ahd_freeze_scb(scb); 1739 ahd_freeze_devq(ahd, scb); 1740 } 1741 /* Return unpausing the sequencer. */ 1742 return (0); 1743 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1744 /* 1745 * Ignore what are really parity errors that 1746 * occur on the last REQ of a free running 1747 * clock prior to going busfree. Some drives 1748 * do not properly active negate just before 1749 * going busfree resulting in a parity glitch. 1750 */ 1751 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1752 #ifdef AHD_DEBUG 1753 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1754 printf("%s: Parity on last REQ detected " 1755 "during busfree phase.\n", 1756 ahd_name(ahd)); 1757 #endif 1758 /* Return unpausing the sequencer. */ 1759 return (0); 1760 } 1761 if (ahd->src_mode != AHD_MODE_SCSI) { 1762 u_int scbid; 1763 struct scb *scb; 1764 1765 scbid = ahd_get_scbptr(ahd); 1766 scb = ahd_lookup_scb(ahd, scbid); 1767 ahd_print_path(ahd, scb); 1768 printf("Unexpected PKT busfree condition\n"); 1769 ahd_dump_card_state(ahd); 1770 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1771 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1772 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1773 1774 /* Return restarting the sequencer. */ 1775 return (1); 1776 } 1777 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1778 ahd_dump_card_state(ahd); 1779 /* Restart the sequencer. */ 1780 return (1); 1781 } 1782 1783 /* 1784 * Non-packetized unexpected or expected busfree. 1785 */ 1786 static int 1787 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1788 { 1789 struct ahd_devinfo devinfo; 1790 struct scb *scb; 1791 u_int lastphase; 1792 u_int saved_scsiid; 1793 u_int saved_lun; 1794 u_int target; 1795 u_int initiator_role_id; 1796 u_int scbid; 1797 u_int ppr_busfree; 1798 int printerror; 1799 1800 /* 1801 * Look at what phase we were last in. If its message out, 1802 * chances are pretty good that the busfree was in response 1803 * to one of our abort requests. 1804 */ 1805 lastphase = ahd_inb(ahd, LASTPHASE); 1806 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1807 saved_lun = ahd_inb(ahd, SAVED_LUN); 1808 target = SCSIID_TARGET(ahd, saved_scsiid); 1809 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1810 ahd_compile_devinfo(&devinfo, initiator_role_id, 1811 target, saved_lun, 'A', ROLE_INITIATOR); 1812 printerror = 1; 1813 1814 scbid = ahd_get_scbptr(ahd); 1815 scb = ahd_lookup_scb(ahd, scbid); 1816 if (scb != NULL 1817 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1818 scb = NULL; 1819 1820 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1821 if (lastphase == P_MESGOUT) { 1822 u_int tag; 1823 1824 tag = SCB_LIST_NULL; 1825 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1826 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1827 int found; 1828 int sent_msg; 1829 1830 if (scb == NULL) { 1831 ahd_print_devinfo(ahd, &devinfo); 1832 printf("Abort for unidentified " 1833 "connection completed.\n"); 1834 /* restart the sequencer. */ 1835 return (1); 1836 } 1837 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1838 ahd_print_path(ahd, scb); 1839 printf("SCB %d - Abort%s Completed.\n", 1840 SCB_GET_TAG(scb), 1841 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1842 1843 if (sent_msg == MSG_ABORT_TAG) 1844 tag = SCB_GET_TAG(scb); 1845 1846 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1847 /* 1848 * This abort is in response to an 1849 * unexpected switch to command phase 1850 * for a packetized connection. Since 1851 * the identify message was never sent, 1852 * "saved lun" is 0. We really want to 1853 * abort only the SCB that encountered 1854 * this error, which could have a different 1855 * lun. The SCB will be retried so the OS 1856 * will see the UA after renegotiating to 1857 * packetized. 1858 */ 1859 tag = SCB_GET_TAG(scb); 1860 saved_lun = scb->hscb->lun; 1861 } 1862 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1863 tag, ROLE_INITIATOR, 1864 CAM_REQ_ABORTED); 1865 printf("found == 0x%x\n", found); 1866 printerror = 0; 1867 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1868 MSG_BUS_DEV_RESET, TRUE)) { 1869 #ifdef __FreeBSD__ 1870 /* 1871 * Don't mark the user's request for this BDR 1872 * as completing with CAM_BDR_SENT. CAM3 1873 * specifies CAM_REQ_CMP. 1874 */ 1875 if (scb != NULL 1876 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1877 && ahd_match_scb(ahd, scb, target, 'A', 1878 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1879 ROLE_INITIATOR)) 1880 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1881 #endif 1882 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1883 CAM_BDR_SENT, "Bus Device Reset", 1884 /*verbose_level*/0); 1885 printerror = 0; 1886 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1887 && ppr_busfree == 0) { 1888 struct ahd_initiator_tinfo *tinfo; 1889 struct ahd_tmode_tstate *tstate; 1890 1891 /* 1892 * PPR Rejected. Try non-ppr negotiation 1893 * and retry command. 1894 */ 1895 #ifdef AHD_DEBUG 1896 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1897 printf("PPR negotiation rejected busfree.\n"); 1898 #endif 1899 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1900 devinfo.our_scsiid, 1901 devinfo.target, &tstate); 1902 tinfo->curr.transport_version = 2; 1903 tinfo->goal.transport_version = 2; 1904 tinfo->goal.ppr_options = 0; 1905 ahd_qinfifo_requeue_tail(ahd, scb); 1906 printerror = 0; 1907 } else if ((ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1908 || ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)) 1909 && ppr_busfree == 0) { 1910 /* 1911 * Negotiation Rejected. Go-async and 1912 * retry command. 1913 */ 1914 #ifdef AHD_DEBUG 1915 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1916 printf("Negotiation rejected busfree.\n"); 1917 #endif 1918 ahd_set_width(ahd, &devinfo, 1919 MSG_EXT_WDTR_BUS_8_BIT, 1920 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1921 /*paused*/TRUE); 1922 ahd_set_syncrate(ahd, &devinfo, 1923 /*period*/0, /*offset*/0, 1924 /*ppr_options*/0, 1925 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1926 /*paused*/TRUE); 1927 ahd_qinfifo_requeue_tail(ahd, scb); 1928 printerror = 0; 1929 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1930 && ahd_sent_msg(ahd, AHDMSG_1B, 1931 MSG_INITIATOR_DET_ERR, TRUE)) { 1932 1933 #ifdef AHD_DEBUG 1934 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1935 printf("Expected IDE Busfree\n"); 1936 #endif 1937 printerror = 0; 1938 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1939 && ahd_sent_msg(ahd, AHDMSG_1B, 1940 MSG_MESSAGE_REJECT, TRUE)) { 1941 1942 #ifdef AHD_DEBUG 1943 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1944 printf("Expected QAS Reject Busfree\n"); 1945 #endif 1946 printerror = 0; 1947 } 1948 } 1949 1950 /* 1951 * The busfree required flag is honored at the end of 1952 * the message phases. We check it last in case we 1953 * had to send some other message that caused a busfree. 1954 */ 1955 if (printerror != 0 1956 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1957 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1958 1959 ahd_freeze_devq(ahd, scb); 1960 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1961 ahd_freeze_scb(scb); 1962 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1963 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1964 SCB_GET_CHANNEL(ahd, scb), 1965 SCB_GET_LUN(scb), SCB_LIST_NULL, 1966 ROLE_INITIATOR, CAM_REQ_ABORTED); 1967 } else { 1968 #ifdef AHD_DEBUG 1969 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1970 printf("PPR Negotiation Busfree.\n"); 1971 #endif 1972 ahd_done(ahd, scb); 1973 } 1974 printerror = 0; 1975 } 1976 if (printerror != 0) { 1977 int aborted; 1978 1979 aborted = 0; 1980 if (scb != NULL) { 1981 u_int tag; 1982 1983 if ((scb->hscb->control & TAG_ENB) != 0) 1984 tag = SCB_GET_TAG(scb); 1985 else 1986 tag = SCB_LIST_NULL; 1987 ahd_print_path(ahd, scb); 1988 aborted = ahd_abort_scbs(ahd, target, 'A', 1989 SCB_GET_LUN(scb), tag, 1990 ROLE_INITIATOR, 1991 CAM_UNEXP_BUSFREE); 1992 } else { 1993 /* 1994 * We had not fully identified this connection, 1995 * so we cannot abort anything. 1996 */ 1997 printf("%s: ", ahd_name(ahd)); 1998 } 1999 if (lastphase != P_BUSFREE) 2000 ahd_force_renegotiation(ahd, &devinfo); 2001 printf("Unexpected busfree %s, %d SCBs aborted, " 2002 "PRGMCNT == 0x%x\n", 2003 ahd_lookup_phase_entry(lastphase)->phasemsg, 2004 aborted, 2005 ahd_inb(ahd, PRGMCNT) 2006 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 2007 ahd_dump_card_state(ahd); 2008 } 2009 /* Always restart the sequencer. */ 2010 return (1); 2011 } 2012 2013 static void 2014 ahd_handle_proto_violation(struct ahd_softc *ahd) 2015 { 2016 struct ahd_devinfo devinfo; 2017 struct scb *scb; 2018 u_int scbid; 2019 u_int seq_flags; 2020 u_int curphase; 2021 u_int lastphase; 2022 int found; 2023 2024 ahd_fetch_devinfo(ahd, &devinfo); 2025 scbid = ahd_get_scbptr(ahd); 2026 scb = ahd_lookup_scb(ahd, scbid); 2027 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2028 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2029 lastphase = ahd_inb(ahd, LASTPHASE); 2030 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2031 2032 /* 2033 * The reconnecting target either did not send an 2034 * identify message, or did, but we didn't find an SCB 2035 * to match. 2036 */ 2037 ahd_print_devinfo(ahd, &devinfo); 2038 printf("Target did not send an IDENTIFY message. " 2039 "LASTPHASE = 0x%x.\n", lastphase); 2040 scb = NULL; 2041 } else if (scb == NULL) { 2042 /* 2043 * We don't seem to have an SCB active for this 2044 * transaction. Print an error and reset the bus. 2045 */ 2046 ahd_print_devinfo(ahd, &devinfo); 2047 printf("No SCB found during protocol violation\n"); 2048 goto proto_violation_reset; 2049 } else { 2050 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2051 if ((seq_flags & NO_CDB_SENT) != 0) { 2052 ahd_print_path(ahd, scb); 2053 printf("No or incomplete CDB sent to device.\n"); 2054 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2055 & STATUS_RCVD) == 0) { 2056 /* 2057 * The target never bothered to provide status to 2058 * us prior to completing the command. Since we don't 2059 * know the disposition of this command, we must attempt 2060 * to abort it. Assert ATN and prepare to send an abort 2061 * message. 2062 */ 2063 ahd_print_path(ahd, scb); 2064 printf("Completed command without status.\n"); 2065 } else { 2066 ahd_print_path(ahd, scb); 2067 printf("Unknown protocol violation.\n"); 2068 ahd_dump_card_state(ahd); 2069 } 2070 } 2071 if ((lastphase & ~P_DATAIN_DT) == 0 2072 || lastphase == P_COMMAND) { 2073 proto_violation_reset: 2074 /* 2075 * Target either went directly to data 2076 * phase or didn't respond to our ATN. 2077 * The only safe thing to do is to blow 2078 * it away with a bus reset. 2079 */ 2080 found = ahd_reset_channel(ahd, 'A', TRUE); 2081 printf("%s: Issued Channel %c Bus Reset. " 2082 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2083 } else { 2084 /* 2085 * Leave the selection hardware off in case 2086 * this abort attempt will affect yet to 2087 * be sent commands. 2088 */ 2089 ahd_outb(ahd, SCSISEQ0, 2090 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2091 ahd_assert_atn(ahd); 2092 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2093 if (scb == NULL) { 2094 ahd_print_devinfo(ahd, &devinfo); 2095 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2096 ahd->msgout_len = 1; 2097 ahd->msgout_index = 0; 2098 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2099 } else { 2100 ahd_print_path(ahd, scb); 2101 scb->flags |= SCB_ABORT; 2102 } 2103 printf("Protocol violation %s. Attempting to abort.\n", 2104 ahd_lookup_phase_entry(curphase)->phasemsg); 2105 } 2106 } 2107 2108 /* 2109 * Force renegotiation to occur the next time we initiate 2110 * a command to the current device. 2111 */ 2112 static void 2113 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2114 { 2115 struct ahd_initiator_tinfo *targ_info; 2116 struct ahd_tmode_tstate *tstate; 2117 2118 #ifdef AHD_DEBUG 2119 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2120 ahd_print_devinfo(ahd, devinfo); 2121 printf("Forcing renegotiation\n"); 2122 } 2123 #endif 2124 targ_info = ahd_fetch_transinfo(ahd, 2125 devinfo->channel, 2126 devinfo->our_scsiid, 2127 devinfo->target, 2128 &tstate); 2129 ahd_update_neg_request(ahd, devinfo, tstate, 2130 targ_info, AHD_NEG_IF_NON_ASYNC); 2131 } 2132 2133 #define AHD_MAX_STEPS 2000 2134 void 2135 ahd_clear_critical_section(struct ahd_softc *ahd) 2136 { 2137 ahd_mode_state saved_modes; 2138 int stepping; 2139 int steps; 2140 int first_instr; 2141 u_int simode0; 2142 u_int simode1; 2143 u_int simode3; 2144 u_int lqimode0; 2145 u_int lqimode1; 2146 u_int lqomode0; 2147 u_int lqomode1; 2148 2149 if (ahd->num_critical_sections == 0) 2150 return; 2151 2152 stepping = FALSE; 2153 steps = 0; 2154 first_instr = 0; 2155 simode0 = 0; 2156 simode1 = 0; 2157 simode3 = 0; 2158 lqimode0 = 0; 2159 lqimode1 = 0; 2160 lqomode0 = 0; 2161 lqomode1 = 0; 2162 saved_modes = ahd_save_modes(ahd); 2163 for (;;) { 2164 struct cs *cs; 2165 u_int seqaddr; 2166 u_int i; 2167 2168 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2169 seqaddr = ahd_inb(ahd, CURADDR) 2170 | (ahd_inb(ahd, CURADDR+1) << 8); 2171 2172 cs = ahd->critical_sections; 2173 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2174 2175 if (cs->begin < seqaddr && cs->end >= seqaddr) 2176 break; 2177 } 2178 2179 if (i == ahd->num_critical_sections) 2180 break; 2181 2182 if (steps > AHD_MAX_STEPS) { 2183 printf("%s: Infinite loop in critical section\n" 2184 "%s: First Instruction 0x%x now 0x%x\n", 2185 ahd_name(ahd), ahd_name(ahd), first_instr, 2186 seqaddr); 2187 ahd_dump_card_state(ahd); 2188 panic("critical section loop"); 2189 } 2190 2191 steps++; 2192 #ifdef AHD_DEBUG 2193 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2194 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2195 seqaddr); 2196 #endif 2197 if (stepping == FALSE) { 2198 2199 first_instr = seqaddr; 2200 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2201 simode0 = ahd_inb(ahd, SIMODE0); 2202 simode3 = ahd_inb(ahd, SIMODE3); 2203 lqimode0 = ahd_inb(ahd, LQIMODE0); 2204 lqimode1 = ahd_inb(ahd, LQIMODE1); 2205 lqomode0 = ahd_inb(ahd, LQOMODE0); 2206 lqomode1 = ahd_inb(ahd, LQOMODE1); 2207 ahd_outb(ahd, SIMODE0, 0); 2208 ahd_outb(ahd, SIMODE3, 0); 2209 ahd_outb(ahd, LQIMODE0, 0); 2210 ahd_outb(ahd, LQIMODE1, 0); 2211 ahd_outb(ahd, LQOMODE0, 0); 2212 ahd_outb(ahd, LQOMODE1, 0); 2213 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2214 simode1 = ahd_inb(ahd, SIMODE1); 2215 ahd_outb(ahd, SIMODE1, ENBUSFREE); 2216 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2217 stepping = TRUE; 2218 } 2219 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2220 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2221 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2222 ahd_outb(ahd, HCNTRL, ahd->unpause); 2223 do { 2224 ahd_delay(200); 2225 } while (!ahd_is_paused(ahd)); 2226 ahd_update_modes(ahd); 2227 } 2228 if (stepping) { 2229 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2230 ahd_outb(ahd, SIMODE0, simode0); 2231 ahd_outb(ahd, SIMODE3, simode3); 2232 ahd_outb(ahd, LQIMODE0, lqimode0); 2233 ahd_outb(ahd, LQIMODE1, lqimode1); 2234 ahd_outb(ahd, LQOMODE0, lqomode0); 2235 ahd_outb(ahd, LQOMODE1, lqomode1); 2236 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2237 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2238 ahd_outb(ahd, SIMODE1, simode1); 2239 /* 2240 * SCSIINT seems to glitch occassionally when 2241 * the interrupt masks are restored. Clear SCSIINT 2242 * one more time so that only persistent errors 2243 * are seen as a real interrupt. 2244 */ 2245 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2246 } 2247 ahd_restore_modes(ahd, saved_modes); 2248 } 2249 2250 /* 2251 * Clear any pending interrupt status. 2252 */ 2253 void 2254 ahd_clear_intstat(struct ahd_softc *ahd) 2255 { 2256 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2257 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2258 /* Clear any interrupt conditions this may have caused */ 2259 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2260 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2261 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2262 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2263 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2264 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2265 |CLRLQOATNPKT|CLRLQOTCRC); 2266 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2267 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2268 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2269 ahd_outb(ahd, CLRLQOINT0, 0); 2270 ahd_outb(ahd, CLRLQOINT1, 0); 2271 } 2272 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2273 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2274 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2275 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2276 |CLRIOERR|CLROVERRUN); 2277 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2278 } 2279 2280 /**************************** Debugging Routines ******************************/ 2281 #ifdef AHD_DEBUG 2282 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2283 #endif 2284 void 2285 ahd_print_scb(struct scb *scb) 2286 { 2287 struct hardware_scb *hscb; 2288 int i; 2289 2290 hscb = scb->hscb; 2291 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2292 (void *)scb, 2293 hscb->control, 2294 hscb->scsiid, 2295 hscb->lun, 2296 hscb->cdb_len); 2297 printf("Shared Data: "); 2298 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2299 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2300 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2301 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2302 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2303 ahd_le32toh(hscb->datacnt), 2304 ahd_le32toh(hscb->sgptr), 2305 SCB_GET_TAG(scb)); 2306 ahd_dump_sglist(scb); 2307 } 2308 2309 void 2310 ahd_dump_sglist(struct scb *scb) 2311 { 2312 int i; 2313 2314 if (scb->sg_count > 0) { 2315 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2316 struct ahd_dma64_seg *sg_list; 2317 2318 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2319 for (i = 0; i < scb->sg_count; i++) { 2320 uint64_t addr; 2321 uint32_t len; 2322 2323 addr = ahd_le64toh(sg_list[i].addr); 2324 len = ahd_le32toh(sg_list[i].len); 2325 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2326 i, 2327 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2328 (uint32_t)(addr & 0xFFFFFFFF), 2329 sg_list[i].len & AHD_SG_LEN_MASK, 2330 (sg_list[i].len & AHD_DMA_LAST_SEG) 2331 ? " Last" : ""); 2332 } 2333 } else { 2334 struct ahd_dma_seg *sg_list; 2335 2336 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2337 for (i = 0; i < scb->sg_count; i++) { 2338 uint32_t len; 2339 2340 len = ahd_le32toh(sg_list[i].len); 2341 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2342 i, 2343 (len >> 24) & SG_HIGH_ADDR_BITS, 2344 ahd_le32toh(sg_list[i].addr), 2345 len & AHD_SG_LEN_MASK, 2346 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2347 } 2348 } 2349 } 2350 } 2351 2352 /************************* Transfer Negotiation *******************************/ 2353 /* 2354 * Allocate per target mode instance (ID we respond to as a target) 2355 * transfer negotiation data structures. 2356 */ 2357 static struct ahd_tmode_tstate * 2358 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2359 { 2360 struct ahd_tmode_tstate *master_tstate; 2361 struct ahd_tmode_tstate *tstate; 2362 int i; 2363 2364 master_tstate = ahd->enabled_targets[ahd->our_id]; 2365 if (ahd->enabled_targets[scsi_id] != NULL 2366 && ahd->enabled_targets[scsi_id] != master_tstate) 2367 panic("%s: ahd_alloc_tstate - Target already allocated", 2368 ahd_name(ahd)); 2369 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 2370 if (tstate == NULL) 2371 return (NULL); 2372 2373 /* 2374 * If we have allocated a master tstate, copy user settings from 2375 * the master tstate (taken from SRAM or the EEPROM) for this 2376 * channel, but reset our current and goal settings to async/narrow 2377 * until an initiator talks to us. 2378 */ 2379 if (master_tstate != NULL) { 2380 memcpy(tstate, master_tstate, sizeof(*tstate)); 2381 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2382 for (i = 0; i < 16; i++) { 2383 memset(&tstate->transinfo[i].curr, 0, 2384 sizeof(tstate->transinfo[i].curr)); 2385 memset(&tstate->transinfo[i].goal, 0, 2386 sizeof(tstate->transinfo[i].goal)); 2387 } 2388 } else 2389 memset(tstate, 0, sizeof(*tstate)); 2390 ahd->enabled_targets[scsi_id] = tstate; 2391 return (tstate); 2392 } 2393 2394 #ifdef AHD_TARGET_MODE 2395 /* 2396 * Free per target mode instance (ID we respond to as a target) 2397 * transfer negotiation data structures. 2398 */ 2399 static void 2400 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2401 { 2402 struct ahd_tmode_tstate *tstate; 2403 2404 /* 2405 * Don't clean up our "master" tstate. 2406 * It has our default user settings. 2407 */ 2408 if (scsi_id == ahd->our_id 2409 && force == FALSE) 2410 return; 2411 2412 tstate = ahd->enabled_targets[scsi_id]; 2413 if (tstate != NULL) 2414 free(tstate, M_DEVBUF); 2415 ahd->enabled_targets[scsi_id] = NULL; 2416 } 2417 #endif 2418 2419 /* 2420 * Called when we have an active connection to a target on the bus, 2421 * this function finds the nearest period to the input period limited 2422 * by the capabilities of the bus connectivity of and sync settings for 2423 * the target. 2424 */ 2425 void 2426 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2427 struct ahd_initiator_tinfo *tinfo, 2428 u_int *period, u_int *ppr_options, role_t role) 2429 { 2430 struct ahd_transinfo *transinfo; 2431 u_int maxsync; 2432 2433 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2434 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2435 maxsync = AHD_SYNCRATE_PACED; 2436 } else { 2437 maxsync = AHD_SYNCRATE_ULTRA; 2438 /* Can't do DT related options on an SE bus */ 2439 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2440 } 2441 /* 2442 * Never allow a value higher than our current goal 2443 * period otherwise we may allow a target initiated 2444 * negotiation to go above the limit as set by the 2445 * user. In the case of an initiator initiated 2446 * sync negotiation, we limit based on the user 2447 * setting. This allows the system to still accept 2448 * incoming negotiations even if target initiated 2449 * negotiation is not performed. 2450 */ 2451 if (role == ROLE_TARGET) 2452 transinfo = &tinfo->user; 2453 else 2454 transinfo = &tinfo->goal; 2455 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2456 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2457 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2458 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2459 } 2460 if (transinfo->period == 0) { 2461 *period = 0; 2462 *ppr_options = 0; 2463 } else { 2464 *period = MAX(*period, transinfo->period); 2465 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2466 } 2467 } 2468 2469 /* 2470 * Look up the valid period to SCSIRATE conversion in our table. 2471 * Return the period and offset that should be sent to the target 2472 * if this was the beginning of an SDTR. 2473 */ 2474 void 2475 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2476 u_int *ppr_options, u_int maxsync) 2477 { 2478 if (*period < maxsync) 2479 *period = maxsync; 2480 2481 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2482 && *period > AHD_SYNCRATE_MIN_DT) 2483 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2484 2485 if (*period > AHD_SYNCRATE_MIN) 2486 *period = 0; 2487 2488 /* Honor PPR option conformance rules. */ 2489 if (*period > AHD_SYNCRATE_PACED) 2490 *ppr_options &= ~MSG_EXT_PPR_RTI; 2491 2492 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2493 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2494 2495 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2496 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2497 2498 /* Skip all PACED only entries if IU is not available */ 2499 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2500 && *period < AHD_SYNCRATE_DT) 2501 *period = AHD_SYNCRATE_DT; 2502 2503 /* Skip all DT only entries if DT is not available */ 2504 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2505 && *period < AHD_SYNCRATE_ULTRA2) 2506 *period = AHD_SYNCRATE_ULTRA2; 2507 } 2508 2509 /* 2510 * Truncate the given synchronous offset to a value the 2511 * current adapter type and syncrate are capable of. 2512 */ 2513 void 2514 ahd_validate_offset(struct ahd_softc *ahd, 2515 struct ahd_initiator_tinfo *tinfo, 2516 u_int period, u_int *offset, int wide, 2517 role_t role) 2518 { 2519 u_int maxoffset; 2520 2521 /* Limit offset to what we can do */ 2522 if (period == 0) 2523 maxoffset = 0; 2524 else if (period <= AHD_SYNCRATE_PACED) { 2525 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2526 maxoffset = MAX_OFFSET_PACED_BUG; 2527 else 2528 maxoffset = MAX_OFFSET_PACED; 2529 } else 2530 maxoffset = MAX_OFFSET_NON_PACED; 2531 *offset = MIN(*offset, maxoffset); 2532 if (tinfo != NULL) { 2533 if (role == ROLE_TARGET) 2534 *offset = MIN(*offset, tinfo->user.offset); 2535 else 2536 *offset = MIN(*offset, tinfo->goal.offset); 2537 } 2538 } 2539 2540 /* 2541 * Truncate the given transfer width parameter to a value the 2542 * current adapter type is capable of. 2543 */ 2544 void 2545 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2546 u_int *bus_width, role_t role) 2547 { 2548 switch (*bus_width) { 2549 default: 2550 if (ahd->features & AHD_WIDE) { 2551 /* Respond Wide */ 2552 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2553 break; 2554 } 2555 /* FALLTHROUGH */ 2556 case MSG_EXT_WDTR_BUS_8_BIT: 2557 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2558 break; 2559 } 2560 if (tinfo != NULL) { 2561 if (role == ROLE_TARGET) 2562 *bus_width = MIN(tinfo->user.width, *bus_width); 2563 else 2564 *bus_width = MIN(tinfo->goal.width, *bus_width); 2565 } 2566 } 2567 2568 /* 2569 * Update the bitmask of targets for which the controller should 2570 * negotiate with at the next convenient oportunity. This currently 2571 * means the next time we send the initial identify messages for 2572 * a new transaction. 2573 */ 2574 int 2575 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2576 struct ahd_tmode_tstate *tstate, 2577 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2578 { 2579 u_int auto_negotiate_orig; 2580 2581 auto_negotiate_orig = tstate->auto_negotiate; 2582 if (neg_type == AHD_NEG_ALWAYS) { 2583 /* 2584 * Force our "current" settings to be 2585 * unknown so that unless a bus reset 2586 * occurs the need to renegotiate is 2587 * recorded persistently. 2588 */ 2589 if ((ahd->features & AHD_WIDE) != 0) 2590 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2591 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2592 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2593 } 2594 if (tinfo->curr.period != tinfo->goal.period 2595 || tinfo->curr.width != tinfo->goal.width 2596 || tinfo->curr.offset != tinfo->goal.offset 2597 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2598 || (neg_type == AHD_NEG_IF_NON_ASYNC 2599 && (tinfo->goal.offset != 0 2600 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2601 || tinfo->goal.ppr_options != 0))) 2602 tstate->auto_negotiate |= devinfo->target_mask; 2603 else 2604 tstate->auto_negotiate &= ~devinfo->target_mask; 2605 2606 return (auto_negotiate_orig != tstate->auto_negotiate); 2607 } 2608 2609 /* 2610 * Update the user/goal/curr tables of synchronous negotiation 2611 * parameters as well as, in the case of a current or active update, 2612 * any data structures on the host controller. In the case of an 2613 * active update, the specified target is currently talking to us on 2614 * the bus, so the transfer parameter update must take effect 2615 * immediately. 2616 */ 2617 void 2618 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2619 u_int period, u_int offset, u_int ppr_options, 2620 u_int type, int paused) 2621 { 2622 struct ahd_initiator_tinfo *tinfo; 2623 struct ahd_tmode_tstate *tstate; 2624 u_int old_period; 2625 u_int old_offset; 2626 u_int old_ppr; 2627 int active; 2628 int update_needed; 2629 2630 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2631 update_needed = 0; 2632 2633 if (period == 0 || offset == 0) { 2634 period = 0; 2635 offset = 0; 2636 } 2637 2638 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2639 devinfo->target, &tstate); 2640 2641 if ((type & AHD_TRANS_USER) != 0) { 2642 tinfo->user.period = period; 2643 tinfo->user.offset = offset; 2644 tinfo->user.ppr_options = ppr_options; 2645 } 2646 2647 if ((type & AHD_TRANS_GOAL) != 0) { 2648 tinfo->goal.period = period; 2649 tinfo->goal.offset = offset; 2650 tinfo->goal.ppr_options = ppr_options; 2651 } 2652 2653 old_period = tinfo->curr.period; 2654 old_offset = tinfo->curr.offset; 2655 old_ppr = tinfo->curr.ppr_options; 2656 2657 if ((type & AHD_TRANS_CUR) != 0 2658 && (old_period != period 2659 || old_offset != offset 2660 || old_ppr != ppr_options)) { 2661 2662 update_needed++; 2663 2664 tinfo->curr.period = period; 2665 tinfo->curr.offset = offset; 2666 tinfo->curr.ppr_options = ppr_options; 2667 2668 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2669 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2670 2671 if (bootverbose) { 2672 if (offset != 0) { 2673 int options; 2674 2675 printf("%s: target %d synchronous with " 2676 "period = 0x%x, offset = 0x%x", 2677 ahd_name(ahd), devinfo->target, 2678 period, offset); 2679 options = 0; 2680 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 2681 printf("(RDSTRM"); 2682 options++; 2683 } 2684 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2685 printf("%s", options ? "|DT" : "(DT"); 2686 options++; 2687 } 2688 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2689 printf("%s", options ? "|IU" : "(IU"); 2690 options++; 2691 } 2692 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2693 printf("%s", options ? "|RTI" : "(RTI"); 2694 options++; 2695 } 2696 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2697 printf("%s", options ? "|QAS" : "(QAS"); 2698 options++; 2699 } 2700 if (options != 0) 2701 printf(")\n"); 2702 else 2703 printf("\n"); 2704 } else { 2705 printf("%s: target %d using " 2706 "asynchronous transfers%s\n", 2707 ahd_name(ahd), devinfo->target, 2708 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2709 ? "(QAS)" : ""); 2710 } 2711 } 2712 } 2713 /* 2714 * Always refresh the neg-table to handle the case of the 2715 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2716 * We will always renegotiate in that case if this is a 2717 * packetized request. Also manage the busfree expected flag 2718 * from this common routine so that we catch changes due to 2719 * WDTR or SDTR messages. 2720 */ 2721 if ((type & AHD_TRANS_CUR) != 0) { 2722 if (!paused) 2723 ahd_pause(ahd); 2724 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2725 if (!paused) 2726 ahd_unpause(ahd); 2727 if (ahd->msg_type != MSG_TYPE_NONE) { 2728 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2729 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2730 #ifdef AHD_DEBUG 2731 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2732 ahd_print_devinfo(ahd, devinfo); 2733 printf("Expecting IU Change busfree\n"); 2734 } 2735 #endif 2736 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2737 | MSG_FLAG_IU_REQ_CHANGED; 2738 } 2739 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2740 #ifdef AHD_DEBUG 2741 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2742 printf("PPR with IU_REQ outstanding\n"); 2743 #endif 2744 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2745 } 2746 } 2747 } 2748 2749 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2750 tinfo, AHD_NEG_TO_GOAL); 2751 2752 if (update_needed) 2753 ahd_update_xfer_mode(ahd, devinfo); 2754 ahd->sc_req = 0; 2755 2756 if (update_needed && active) 2757 ahd_update_pending_scbs(ahd); 2758 } 2759 2760 /* 2761 * Update the user/goal/curr tables of wide negotiation 2762 * parameters as well as, in the case of a current or active update, 2763 * any data structures on the host controller. In the case of an 2764 * active update, the specified target is currently talking to us on 2765 * the bus, so the transfer parameter update must take effect 2766 * immediately. 2767 */ 2768 void 2769 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2770 u_int width, u_int type, int paused) 2771 { 2772 struct ahd_initiator_tinfo *tinfo; 2773 struct ahd_tmode_tstate *tstate; 2774 u_int oldwidth; 2775 int active; 2776 int update_needed; 2777 2778 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2779 update_needed = 0; 2780 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2781 devinfo->target, &tstate); 2782 2783 if ((type & AHD_TRANS_USER) != 0) 2784 tinfo->user.width = width; 2785 2786 if ((type & AHD_TRANS_GOAL) != 0) 2787 tinfo->goal.width = width; 2788 2789 oldwidth = tinfo->curr.width; 2790 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2791 2792 update_needed++; 2793 2794 tinfo->curr.width = width; 2795 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2796 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2797 2798 if (bootverbose) { 2799 printf("%s: target %d using %dbit transfers\n", 2800 ahd_name(ahd), devinfo->target, 2801 8 * (0x01 << width)); 2802 } 2803 } 2804 2805 if ((type & AHD_TRANS_CUR) != 0) { 2806 if (!paused) 2807 ahd_pause(ahd); 2808 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2809 if (!paused) 2810 ahd_unpause(ahd); 2811 } 2812 2813 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2814 tinfo, AHD_NEG_TO_GOAL); 2815 if (update_needed && active) 2816 ahd_update_pending_scbs(ahd); 2817 2818 } 2819 2820 /* 2821 * Update the current state of tagged queuing for a given target. 2822 */ 2823 void 2824 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2825 ahd_queue_alg alg) 2826 { 2827 ahd_platform_set_tags(ahd, devinfo, alg); 2828 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2829 devinfo->lun, AC_TRANSFER_NEG, &alg); 2830 } 2831 2832 static void 2833 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2834 struct ahd_transinfo *tinfo) 2835 { 2836 ahd_mode_state saved_modes; 2837 u_int period; 2838 u_int ppr_opts; 2839 u_int con_opts; 2840 u_int offset; 2841 u_int saved_negoaddr; 2842 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2843 2844 saved_modes = ahd_save_modes(ahd); 2845 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2846 2847 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2848 ahd_outb(ahd, NEGOADDR, devinfo->target); 2849 period = tinfo->period; 2850 offset = tinfo->offset; 2851 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2852 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2853 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2854 con_opts = 0; 2855 if (period == 0) 2856 period = AHD_SYNCRATE_ASYNC; 2857 if (period == AHD_SYNCRATE_160) { 2858 2859 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2860 /* 2861 * When the SPI4 spec was finalized, PACE transfers 2862 * was not made a configurable option in the PPR 2863 * message. Instead it is assumed to be enabled for 2864 * any syncrate faster than 80MHz. Nevertheless, 2865 * Harpoon2A4 allows this to be configurable. 2866 * 2867 * Harpoon2A4 also assumes at most 2 data bytes per 2868 * negotiated REQ/ACK offset. Paced transfers take 2869 * 4, so we must adjust our offset. 2870 */ 2871 ppr_opts |= PPROPT_PACE; 2872 offset *= 2; 2873 2874 /* 2875 * Harpoon2A assumed that there would be a 2876 * fallback rate between 160MHz and 80Mhz, 2877 * so 7 is used as the period factor rather 2878 * than 8 for 160MHz. 2879 */ 2880 period = AHD_SYNCRATE_REVA_160; 2881 } 2882 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2883 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2884 ~AHD_PRECOMP_MASK; 2885 } else { 2886 /* 2887 * Precomp should be disabled for non-paced transfers. 2888 */ 2889 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2890 2891 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2892 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2893 /* 2894 * Slow down our CRC interval to be 2895 * compatible with devices that can't 2896 * handle a CRC at full speed. 2897 */ 2898 con_opts |= ENSLOWCRC; 2899 } 2900 } 2901 2902 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2903 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2904 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2905 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2906 2907 ahd_outb(ahd, NEGPERIOD, period); 2908 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2909 ahd_outb(ahd, NEGOFFSET, offset); 2910 2911 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2912 con_opts |= WIDEXFER; 2913 2914 /* 2915 * During packetized transfers, the target will 2916 * give us the oportunity to send command packets 2917 * without us asserting attention. 2918 */ 2919 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2920 con_opts |= ENAUTOATNO; 2921 ahd_outb(ahd, NEGCONOPTS, con_opts); 2922 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2923 ahd_restore_modes(ahd, saved_modes); 2924 } 2925 2926 /* 2927 * When the transfer settings for a connection change, setup for 2928 * negotiation in pending SCBs to effect the change as quickly as 2929 * possible. We also cancel any negotiations that are scheduled 2930 * for inflight SCBs that have not been started yet. 2931 */ 2932 static void 2933 ahd_update_pending_scbs(struct ahd_softc *ahd) 2934 { 2935 struct scb *pending_scb; 2936 int pending_scb_count; 2937 int i; 2938 int paused; 2939 u_int saved_scbptr; 2940 ahd_mode_state saved_modes; 2941 2942 /* 2943 * Traverse the pending SCB list and ensure that all of the 2944 * SCBs there have the proper settings. We can only safely 2945 * clear the negotiation required flag (setting requires the 2946 * execution queue to be modified) and this is only possible 2947 * if we are not already attempting to select out for this 2948 * SCB. For this reason, all callers only call this routine 2949 * if we are changing the negotiation settings for the currently 2950 * active transaction on the bus. 2951 */ 2952 pending_scb_count = 0; 2953 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2954 struct ahd_devinfo devinfo; 2955 struct hardware_scb *pending_hscb; 2956 struct ahd_initiator_tinfo *tinfo; 2957 struct ahd_tmode_tstate *tstate; 2958 2959 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2960 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2961 devinfo.our_scsiid, 2962 devinfo.target, &tstate); 2963 pending_hscb = pending_scb->hscb; 2964 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2965 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2966 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2967 pending_hscb->control &= ~MK_MESSAGE; 2968 } 2969 ahd_sync_scb(ahd, pending_scb, 2970 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2971 pending_scb_count++; 2972 } 2973 2974 if (pending_scb_count == 0) 2975 return; 2976 2977 if (ahd_is_paused(ahd)) { 2978 paused = 1; 2979 } else { 2980 paused = 0; 2981 ahd_pause(ahd); 2982 } 2983 2984 /* 2985 * Force the sequencer to reinitialize the selection for 2986 * the command at the head of the execution queue if it 2987 * has already been setup. The negotiation changes may 2988 * effect whether we select-out with ATN. 2989 */ 2990 saved_modes = ahd_save_modes(ahd); 2991 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2992 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2993 saved_scbptr = ahd_get_scbptr(ahd); 2994 /* Ensure that the hscbs down on the card match the new information */ 2995 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 2996 struct hardware_scb *pending_hscb; 2997 u_int control; 2998 u_int scb_tag; 2999 3000 ahd_set_scbptr(ahd, i); 3001 scb_tag = i; 3002 pending_scb = ahd_lookup_scb(ahd, scb_tag); 3003 if (pending_scb == NULL) 3004 continue; 3005 3006 pending_hscb = pending_scb->hscb; 3007 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3008 control &= ~MK_MESSAGE; 3009 control |= pending_hscb->control & MK_MESSAGE; 3010 ahd_outb(ahd, SCB_CONTROL, control); 3011 } 3012 ahd_set_scbptr(ahd, saved_scbptr); 3013 ahd_restore_modes(ahd, saved_modes); 3014 3015 if (paused == 0) 3016 ahd_unpause(ahd); 3017 } 3018 3019 /**************************** Pathing Information *****************************/ 3020 static void 3021 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3022 { 3023 ahd_mode_state saved_modes; 3024 u_int saved_scsiid; 3025 role_t role; 3026 int our_id; 3027 3028 saved_modes = ahd_save_modes(ahd); 3029 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3030 3031 if (ahd_inb(ahd, SSTAT0) & TARGET) 3032 role = ROLE_TARGET; 3033 else 3034 role = ROLE_INITIATOR; 3035 3036 if (role == ROLE_TARGET 3037 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3038 /* We were selected, so pull our id from TARGIDIN */ 3039 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3040 } else if (role == ROLE_TARGET) 3041 our_id = ahd_inb(ahd, TOWNID); 3042 else 3043 our_id = ahd_inb(ahd, IOWNID); 3044 3045 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3046 ahd_compile_devinfo(devinfo, 3047 our_id, 3048 SCSIID_TARGET(ahd, saved_scsiid), 3049 ahd_inb(ahd, SAVED_LUN), 3050 SCSIID_CHANNEL(ahd, saved_scsiid), 3051 role); 3052 ahd_restore_modes(ahd, saved_modes); 3053 } 3054 3055 void 3056 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3057 { 3058 printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3059 devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3060 } 3061 3062 struct ahd_phase_table_entry* 3063 ahd_lookup_phase_entry(int phase) 3064 { 3065 struct ahd_phase_table_entry *entry; 3066 struct ahd_phase_table_entry *last_entry; 3067 3068 /* 3069 * num_phases doesn't include the default entry which 3070 * will be returned if the phase doesn't match. 3071 */ 3072 last_entry = &ahd_phase_table[num_phases]; 3073 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3074 if (phase == entry->phase) 3075 break; 3076 } 3077 return (entry); 3078 } 3079 3080 void 3081 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3082 u_int lun, char channel, role_t role) 3083 { 3084 devinfo->our_scsiid = our_id; 3085 devinfo->target = target; 3086 devinfo->lun = lun; 3087 devinfo->target_offset = target; 3088 devinfo->channel = channel; 3089 devinfo->role = role; 3090 if (channel == 'B') 3091 devinfo->target_offset += 8; 3092 devinfo->target_mask = (0x01 << devinfo->target_offset); 3093 } 3094 3095 static void 3096 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3097 struct scb *scb) 3098 { 3099 role_t role; 3100 int our_id; 3101 3102 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3103 role = ROLE_INITIATOR; 3104 if ((scb->hscb->control & TARGET_SCB) != 0) 3105 role = ROLE_TARGET; 3106 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3107 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3108 } 3109 3110 3111 /************************ Message Phase Processing ****************************/ 3112 /* 3113 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3114 * or enters the initial message out phase, we are interrupted. Fill our 3115 * outgoing message buffer with the appropriate message and beging handing 3116 * the message phase(s) manually. 3117 */ 3118 static void 3119 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3120 struct scb *scb) 3121 { 3122 /* 3123 * To facilitate adding multiple messages together, 3124 * each routine should increment the index and len 3125 * variables instead of setting them explicitly. 3126 */ 3127 ahd->msgout_index = 0; 3128 ahd->msgout_len = 0; 3129 3130 if (ahd_currently_packetized(ahd)) 3131 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3132 3133 if (ahd->send_msg_perror 3134 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3135 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3136 ahd->msgout_len++; 3137 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3138 #ifdef AHD_DEBUG 3139 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3140 printf("Setting up for Parity Error delivery\n"); 3141 #endif 3142 return; 3143 } else if (scb == NULL) { 3144 printf("%s: WARNING. No pending message for " 3145 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3146 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3147 ahd->msgout_len++; 3148 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3149 return; 3150 } 3151 3152 if ((scb->flags & SCB_DEVICE_RESET) == 0 3153 && (scb->flags & SCB_PACKETIZED) == 0 3154 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3155 u_int identify_msg; 3156 3157 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3158 if ((scb->hscb->control & DISCENB) != 0) 3159 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3160 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3161 ahd->msgout_len++; 3162 3163 if ((scb->hscb->control & TAG_ENB) != 0) { 3164 ahd->msgout_buf[ahd->msgout_index++] = 3165 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3166 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3167 ahd->msgout_len += 2; 3168 } 3169 } 3170 3171 if (scb->flags & SCB_DEVICE_RESET) { 3172 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3173 ahd->msgout_len++; 3174 ahd_print_path(ahd, scb); 3175 printf("Bus Device Reset Message Sent\n"); 3176 /* 3177 * Clear our selection hardware in advance of 3178 * the busfree. We may have an entry in the waiting 3179 * Q for this target, and we don't want to go about 3180 * selecting while we handle the busfree and blow it 3181 * away. 3182 */ 3183 ahd_outb(ahd, SCSISEQ0, 0); 3184 } else if ((scb->flags & SCB_ABORT) != 0) { 3185 3186 if ((scb->hscb->control & TAG_ENB) != 0) { 3187 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3188 } else { 3189 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3190 } 3191 ahd->msgout_len++; 3192 ahd_print_path(ahd, scb); 3193 printf("Abort%s Message Sent\n", 3194 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3195 /* 3196 * Clear our selection hardware in advance of 3197 * the busfree. We may have an entry in the waiting 3198 * Q for this target, and we don't want to go about 3199 * selecting while we handle the busfree and blow it 3200 * away. 3201 */ 3202 ahd_outb(ahd, SCSISEQ0, 0); 3203 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3204 ahd_build_transfer_msg(ahd, devinfo); 3205 /* 3206 * Clear our selection hardware in advance of potential 3207 * PPR IU status change busfree. We may have an entry in 3208 * the waiting Q for this target, and we don't want to go 3209 * about selecting while we handle the busfree and blow 3210 * it away. 3211 */ 3212 ahd_outb(ahd, SCSISEQ0, 0); 3213 } else { 3214 printf("ahd_intr: AWAITING_MSG for an SCB that " 3215 "does not have a waiting message\n"); 3216 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3217 devinfo->target_mask); 3218 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3219 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3220 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3221 scb->flags); 3222 } 3223 3224 /* 3225 * Clear the MK_MESSAGE flag from the SCB so we aren't 3226 * asked to send this message again. 3227 */ 3228 ahd_outb(ahd, SCB_CONTROL, 3229 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3230 scb->hscb->control &= ~MK_MESSAGE; 3231 ahd->msgout_index = 0; 3232 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3233 } 3234 3235 /* 3236 * Build an appropriate transfer negotiation message for the 3237 * currently active target. 3238 */ 3239 static void 3240 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3241 { 3242 /* 3243 * We need to initiate transfer negotiations. 3244 * If our current and goal settings are identical, 3245 * we want to renegotiate due to a check condition. 3246 */ 3247 struct ahd_initiator_tinfo *tinfo; 3248 struct ahd_tmode_tstate *tstate; 3249 int dowide; 3250 int dosync; 3251 int doppr; 3252 u_int period; 3253 u_int ppr_options; 3254 u_int offset; 3255 3256 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3257 devinfo->target, &tstate); 3258 /* 3259 * Filter our period based on the current connection. 3260 * If we can't perform DT transfers on this segment (not in LVD 3261 * mode for instance), then our decision to issue a PPR message 3262 * may change. 3263 */ 3264 period = tinfo->goal.period; 3265 ppr_options = tinfo->goal.ppr_options; 3266 /* Target initiated PPR is not allowed in the SCSI spec */ 3267 if (devinfo->role == ROLE_TARGET) 3268 ppr_options = 0; 3269 ahd_devlimited_syncrate(ahd, tinfo, &period, 3270 &ppr_options, devinfo->role); 3271 dowide = tinfo->curr.width != tinfo->goal.width; 3272 dosync = tinfo->curr.period != period; 3273 /* 3274 * Only use PPR if we have options that need it, even if the device 3275 * claims to support it. There might be an expander in the way 3276 * that doesn't. 3277 */ 3278 doppr = ppr_options != 0; 3279 3280 if (!dowide && !dosync && !doppr) { 3281 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3282 dosync = tinfo->goal.period != 0; 3283 } 3284 3285 if (!dowide && !dosync && !doppr) { 3286 /* 3287 * Force async with a WDTR message if we have a wide bus, 3288 * or just issue an SDTR with a 0 offset. 3289 */ 3290 if ((ahd->features & AHD_WIDE) != 0) 3291 dowide = 1; 3292 else 3293 dosync = 1; 3294 3295 if (bootverbose) { 3296 ahd_print_devinfo(ahd, devinfo); 3297 printf("Ensuring async\n"); 3298 } 3299 } 3300 /* Target initiated PPR is not allowed in the SCSI spec */ 3301 if (devinfo->role == ROLE_TARGET) 3302 doppr = 0; 3303 3304 /* 3305 * Both the PPR message and SDTR message require the 3306 * goal syncrate to be limited to what the target device 3307 * is capable of handling (based on whether an LVD->SE 3308 * expander is on the bus), so combine these two cases. 3309 * Regardless, guarantee that if we are using WDTR and SDTR 3310 * messages that WDTR comes first. 3311 */ 3312 if (doppr || (dosync && !dowide)) { 3313 3314 offset = tinfo->goal.offset; 3315 ahd_validate_offset(ahd, tinfo, period, &offset, 3316 doppr ? tinfo->goal.width 3317 : tinfo->curr.width, 3318 devinfo->role); 3319 if (doppr) { 3320 ahd_construct_ppr(ahd, devinfo, period, offset, 3321 tinfo->goal.width, ppr_options); 3322 } else { 3323 ahd_construct_sdtr(ahd, devinfo, period, offset); 3324 } 3325 } else { 3326 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3327 } 3328 } 3329 3330 /* 3331 * Build a synchronous negotiation message in our message 3332 * buffer based on the input parameters. 3333 */ 3334 static void 3335 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3336 u_int period, u_int offset) 3337 { 3338 if (offset == 0) 3339 period = AHD_ASYNC_XFER_PERIOD; 3340 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3341 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3342 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3343 ahd->msgout_buf[ahd->msgout_index++] = period; 3344 ahd->msgout_buf[ahd->msgout_index++] = offset; 3345 ahd->msgout_len += 5; 3346 if (bootverbose) { 3347 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3348 ahd_name(ahd), devinfo->channel, devinfo->target, 3349 devinfo->lun, period, offset); 3350 } 3351 } 3352 3353 /* 3354 * Build a wide negotiateion message in our message 3355 * buffer based on the input parameters. 3356 */ 3357 static void 3358 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3359 u_int bus_width) 3360 { 3361 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3362 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3363 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3364 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3365 ahd->msgout_len += 4; 3366 if (bootverbose) { 3367 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3368 ahd_name(ahd), devinfo->channel, devinfo->target, 3369 devinfo->lun, bus_width); 3370 } 3371 } 3372 3373 /* 3374 * Build a parallel protocol request message in our message 3375 * buffer based on the input parameters. 3376 */ 3377 static void 3378 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3379 u_int period, u_int offset, u_int bus_width, 3380 u_int ppr_options) 3381 { 3382 /* 3383 * Always request precompensation from 3384 * the other target if we are running 3385 * at paced syncrates. 3386 */ 3387 if (period <= AHD_SYNCRATE_PACED) 3388 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3389 if (offset == 0) 3390 period = AHD_ASYNC_XFER_PERIOD; 3391 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3392 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3393 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3394 ahd->msgout_buf[ahd->msgout_index++] = period; 3395 ahd->msgout_buf[ahd->msgout_index++] = 0; 3396 ahd->msgout_buf[ahd->msgout_index++] = offset; 3397 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3398 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3399 ahd->msgout_len += 8; 3400 if (bootverbose) { 3401 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3402 "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3403 devinfo->channel, devinfo->target, devinfo->lun, 3404 bus_width, period, offset, ppr_options); 3405 } 3406 } 3407 3408 /* 3409 * Clear any active message state. 3410 */ 3411 static void 3412 ahd_clear_msg_state(struct ahd_softc *ahd) 3413 { 3414 ahd_mode_state saved_modes; 3415 3416 saved_modes = ahd_save_modes(ahd); 3417 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3418 ahd->send_msg_perror = 0; 3419 ahd->msg_flags = MSG_FLAG_NONE; 3420 ahd->msgout_len = 0; 3421 ahd->msgin_index = 0; 3422 ahd->msg_type = MSG_TYPE_NONE; 3423 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3424 /* 3425 * The target didn't care to respond to our 3426 * message request, so clear ATN. 3427 */ 3428 ahd_outb(ahd, CLRSINT1, CLRATNO); 3429 } 3430 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3431 ahd_outb(ahd, SEQ_FLAGS2, 3432 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3433 ahd_restore_modes(ahd, saved_modes); 3434 } 3435 3436 /* 3437 * Manual message loop handler. 3438 */ 3439 static void 3440 ahd_handle_message_phase(struct ahd_softc *ahd) 3441 { 3442 struct ahd_devinfo devinfo; 3443 u_int bus_phase; 3444 int end_session; 3445 3446 ahd_fetch_devinfo(ahd, &devinfo); 3447 end_session = FALSE; 3448 bus_phase = ahd_inb(ahd, LASTPHASE); 3449 3450 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3451 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3452 ahd_outb(ahd, LQCTL2, LQIRETRY); 3453 } 3454 reswitch: 3455 switch (ahd->msg_type) { 3456 case MSG_TYPE_INITIATOR_MSGOUT: 3457 { 3458 int lastbyte; 3459 int phasemis; 3460 int msgdone; 3461 3462 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3463 panic("HOST_MSG_LOOP interrupt with no active message"); 3464 3465 #ifdef AHD_DEBUG 3466 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3467 ahd_print_devinfo(ahd, &devinfo); 3468 printf("INITIATOR_MSG_OUT"); 3469 } 3470 #endif 3471 phasemis = bus_phase != P_MESGOUT; 3472 if (phasemis) { 3473 #ifdef AHD_DEBUG 3474 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3475 printf(" PHASEMIS %s\n", 3476 ahd_lookup_phase_entry(bus_phase) 3477 ->phasemsg); 3478 } 3479 #endif 3480 if (bus_phase == P_MESGIN) { 3481 /* 3482 * Change gears and see if 3483 * this messages is of interest to 3484 * us or should be passed back to 3485 * the sequencer. 3486 */ 3487 ahd_outb(ahd, CLRSINT1, CLRATNO); 3488 ahd->send_msg_perror = 0; 3489 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3490 ahd->msgin_index = 0; 3491 goto reswitch; 3492 } 3493 end_session = TRUE; 3494 break; 3495 } 3496 3497 if (ahd->send_msg_perror) { 3498 ahd_outb(ahd, CLRSINT1, CLRATNO); 3499 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3500 #ifdef AHD_DEBUG 3501 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3502 printf(" byte 0x%x\n", ahd->send_msg_perror); 3503 #endif 3504 /* 3505 * If we are notifying the target of a CRC error 3506 * during packetized operations, the target is 3507 * within its rights to acknowledge our message 3508 * with a busfree. 3509 */ 3510 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3511 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3512 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3513 3514 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3515 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3516 break; 3517 } 3518 3519 msgdone = ahd->msgout_index == ahd->msgout_len; 3520 if (msgdone) { 3521 /* 3522 * The target has requested a retry. 3523 * Re-assert ATN, reset our message index to 3524 * 0, and try again. 3525 */ 3526 ahd->msgout_index = 0; 3527 ahd_assert_atn(ahd); 3528 } 3529 3530 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3531 if (lastbyte) { 3532 /* Last byte is signified by dropping ATN */ 3533 ahd_outb(ahd, CLRSINT1, CLRATNO); 3534 } 3535 3536 /* 3537 * Clear our interrupt status and present 3538 * the next byte on the bus. 3539 */ 3540 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3541 #ifdef AHD_DEBUG 3542 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3543 printf(" byte 0x%x\n", 3544 ahd->msgout_buf[ahd->msgout_index]); 3545 #endif 3546 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3547 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3548 break; 3549 } 3550 case MSG_TYPE_INITIATOR_MSGIN: 3551 { 3552 int phasemis; 3553 int message_done; 3554 3555 #ifdef AHD_DEBUG 3556 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3557 ahd_print_devinfo(ahd, &devinfo); 3558 printf("INITIATOR_MSG_IN"); 3559 } 3560 #endif 3561 phasemis = bus_phase != P_MESGIN; 3562 if (phasemis) { 3563 #ifdef AHD_DEBUG 3564 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3565 printf(" PHASEMIS %s\n", 3566 ahd_lookup_phase_entry(bus_phase) 3567 ->phasemsg); 3568 } 3569 #endif 3570 ahd->msgin_index = 0; 3571 if (bus_phase == P_MESGOUT 3572 && (ahd->send_msg_perror != 0 3573 || (ahd->msgout_len != 0 3574 && ahd->msgout_index == 0))) { 3575 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3576 goto reswitch; 3577 } 3578 end_session = TRUE; 3579 break; 3580 } 3581 3582 /* Pull the byte in without acking it */ 3583 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3584 #ifdef AHD_DEBUG 3585 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3586 printf(" byte 0x%x\n", 3587 ahd->msgin_buf[ahd->msgin_index]); 3588 #endif 3589 3590 message_done = ahd_parse_msg(ahd, &devinfo); 3591 3592 if (message_done) { 3593 /* 3594 * Clear our incoming message buffer in case there 3595 * is another message following this one. 3596 */ 3597 ahd->msgin_index = 0; 3598 3599 /* 3600 * If this message illicited a response, 3601 * assert ATN so the target takes us to the 3602 * message out phase. 3603 */ 3604 if (ahd->msgout_len != 0) { 3605 #ifdef AHD_DEBUG 3606 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3607 ahd_print_devinfo(ahd, &devinfo); 3608 printf("Asserting ATN for response\n"); 3609 } 3610 #endif 3611 ahd_assert_atn(ahd); 3612 } 3613 } else 3614 ahd->msgin_index++; 3615 3616 if (message_done == MSGLOOP_TERMINATED) { 3617 end_session = TRUE; 3618 } else { 3619 /* Ack the byte */ 3620 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3621 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3622 } 3623 break; 3624 } 3625 case MSG_TYPE_TARGET_MSGIN: 3626 { 3627 int msgdone; 3628 int msgout_request; 3629 3630 /* 3631 * By default, the message loop will continue. 3632 */ 3633 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3634 3635 if (ahd->msgout_len == 0) 3636 panic("Target MSGIN with no active message"); 3637 3638 /* 3639 * If we interrupted a mesgout session, the initiator 3640 * will not know this until our first REQ. So, we 3641 * only honor mesgout requests after we've sent our 3642 * first byte. 3643 */ 3644 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3645 && ahd->msgout_index > 0) 3646 msgout_request = TRUE; 3647 else 3648 msgout_request = FALSE; 3649 3650 if (msgout_request) { 3651 3652 /* 3653 * Change gears and see if 3654 * this messages is of interest to 3655 * us or should be passed back to 3656 * the sequencer. 3657 */ 3658 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3659 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3660 ahd->msgin_index = 0; 3661 /* Dummy read to REQ for first byte */ 3662 ahd_inb(ahd, SCSIDAT); 3663 ahd_outb(ahd, SXFRCTL0, 3664 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3665 break; 3666 } 3667 3668 msgdone = ahd->msgout_index == ahd->msgout_len; 3669 if (msgdone) { 3670 ahd_outb(ahd, SXFRCTL0, 3671 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3672 end_session = TRUE; 3673 break; 3674 } 3675 3676 /* 3677 * Present the next byte on the bus. 3678 */ 3679 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3680 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3681 break; 3682 } 3683 case MSG_TYPE_TARGET_MSGOUT: 3684 { 3685 int lastbyte; 3686 int msgdone; 3687 3688 /* 3689 * By default, the message loop will continue. 3690 */ 3691 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3692 3693 /* 3694 * The initiator signals that this is 3695 * the last byte by dropping ATN. 3696 */ 3697 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3698 3699 /* 3700 * Read the latched byte, but turn off SPIOEN first 3701 * so that we don't inadvertently cause a REQ for the 3702 * next byte. 3703 */ 3704 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3705 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3706 msgdone = ahd_parse_msg(ahd, &devinfo); 3707 if (msgdone == MSGLOOP_TERMINATED) { 3708 /* 3709 * The message is *really* done in that it caused 3710 * us to go to bus free. The sequencer has already 3711 * been reset at this point, so pull the ejection 3712 * handle. 3713 */ 3714 return; 3715 } 3716 3717 ahd->msgin_index++; 3718 3719 /* 3720 * XXX Read spec about initiator dropping ATN too soon 3721 * and use msgdone to detect it. 3722 */ 3723 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3724 ahd->msgin_index = 0; 3725 3726 /* 3727 * If this message illicited a response, transition 3728 * to the Message in phase and send it. 3729 */ 3730 if (ahd->msgout_len != 0) { 3731 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3732 ahd_outb(ahd, SXFRCTL0, 3733 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3734 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3735 ahd->msgin_index = 0; 3736 break; 3737 } 3738 } 3739 3740 if (lastbyte) 3741 end_session = TRUE; 3742 else { 3743 /* Ask for the next byte. */ 3744 ahd_outb(ahd, SXFRCTL0, 3745 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3746 } 3747 3748 break; 3749 } 3750 default: 3751 panic("Unknown REQINIT message type"); 3752 } 3753 3754 if (end_session) { 3755 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3756 printf("%s: Returning to Idle Loop\n", 3757 ahd_name(ahd)); 3758 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3759 ahd_clear_msg_state(ahd); 3760 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3761 } else { 3762 ahd_clear_msg_state(ahd); 3763 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3764 } 3765 } 3766 } 3767 3768 /* 3769 * See if we sent a particular extended message to the target. 3770 * If "full" is true, return true only if the target saw the full 3771 * message. If "full" is false, return true if the target saw at 3772 * least the first byte of the message. 3773 */ 3774 static int 3775 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3776 { 3777 int found; 3778 u_int index; 3779 3780 found = FALSE; 3781 index = 0; 3782 3783 while (index < ahd->msgout_len) { 3784 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3785 u_int end_index; 3786 3787 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3788 if (ahd->msgout_buf[index+2] == msgval 3789 && type == AHDMSG_EXT) { 3790 3791 if (full) { 3792 if (ahd->msgout_index > end_index) 3793 found = TRUE; 3794 } else if (ahd->msgout_index > index) 3795 found = TRUE; 3796 } 3797 index = end_index; 3798 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3799 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3800 3801 /* Skip tag type and tag id or residue param*/ 3802 index += 2; 3803 } else { 3804 /* Single byte message */ 3805 if (type == AHDMSG_1B 3806 && ahd->msgout_index > index 3807 && (ahd->msgout_buf[index] == msgval 3808 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3809 && msgval == MSG_IDENTIFYFLAG))) 3810 found = TRUE; 3811 index++; 3812 } 3813 3814 if (found) 3815 break; 3816 } 3817 return (found); 3818 } 3819 3820 /* 3821 * Wait for a complete incoming message, parse it, and respond accordingly. 3822 */ 3823 static int 3824 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3825 { 3826 struct ahd_initiator_tinfo *tinfo; 3827 struct ahd_tmode_tstate *tstate; 3828 int reject; 3829 int done; 3830 int response; 3831 3832 done = MSGLOOP_IN_PROG; 3833 response = FALSE; 3834 reject = FALSE; 3835 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3836 devinfo->target, &tstate); 3837 3838 /* 3839 * Parse as much of the message as is available, 3840 * rejecting it if we don't support it. When 3841 * the entire message is available and has been 3842 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3843 * that we have parsed an entire message. 3844 * 3845 * In the case of extended messages, we accept the length 3846 * byte outright and perform more checking once we know the 3847 * extended message type. 3848 */ 3849 switch (ahd->msgin_buf[0]) { 3850 case MSG_DISCONNECT: 3851 case MSG_SAVEDATAPOINTER: 3852 case MSG_CMDCOMPLETE: 3853 case MSG_RESTOREPOINTERS: 3854 case MSG_IGN_WIDE_RESIDUE: 3855 /* 3856 * End our message loop as these are messages 3857 * the sequencer handles on its own. 3858 */ 3859 done = MSGLOOP_TERMINATED; 3860 break; 3861 case MSG_MESSAGE_REJECT: 3862 response = ahd_handle_msg_reject(ahd, devinfo); 3863 /* FALLTHROUGH */ 3864 case MSG_NOOP: 3865 done = MSGLOOP_MSGCOMPLETE; 3866 break; 3867 case MSG_EXTENDED: 3868 { 3869 /* Wait for enough of the message to begin validation */ 3870 if (ahd->msgin_index < 2) 3871 break; 3872 switch (ahd->msgin_buf[2]) { 3873 case MSG_EXT_SDTR: 3874 { 3875 u_int period; 3876 u_int ppr_options; 3877 u_int offset; 3878 u_int saved_offset; 3879 3880 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3881 reject = TRUE; 3882 break; 3883 } 3884 3885 /* 3886 * Wait until we have both args before validating 3887 * and acting on this message. 3888 * 3889 * Add one to MSG_EXT_SDTR_LEN to account for 3890 * the extended message preamble. 3891 */ 3892 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3893 break; 3894 3895 period = ahd->msgin_buf[3]; 3896 ppr_options = 0; 3897 saved_offset = offset = ahd->msgin_buf[4]; 3898 ahd_devlimited_syncrate(ahd, tinfo, &period, 3899 &ppr_options, devinfo->role); 3900 ahd_validate_offset(ahd, tinfo, period, &offset, 3901 tinfo->curr.width, devinfo->role); 3902 if (bootverbose) { 3903 printf("(%s:%c:%d:%d): Received " 3904 "SDTR period %x, offset %x\n\t" 3905 "Filtered to period %x, offset %x\n", 3906 ahd_name(ahd), devinfo->channel, 3907 devinfo->target, devinfo->lun, 3908 ahd->msgin_buf[3], saved_offset, 3909 period, offset); 3910 } 3911 ahd_set_syncrate(ahd, devinfo, period, 3912 offset, ppr_options, 3913 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3914 /*paused*/TRUE); 3915 3916 /* 3917 * See if we initiated Sync Negotiation 3918 * and didn't have to fall down to async 3919 * transfers. 3920 */ 3921 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3922 /* We started it */ 3923 if (saved_offset != offset) { 3924 /* Went too low - force async */ 3925 reject = TRUE; 3926 } 3927 } else { 3928 /* 3929 * Send our own SDTR in reply 3930 */ 3931 if (bootverbose 3932 && devinfo->role == ROLE_INITIATOR) { 3933 printf("(%s:%c:%d:%d): Target " 3934 "Initiated SDTR\n", 3935 ahd_name(ahd), devinfo->channel, 3936 devinfo->target, devinfo->lun); 3937 } 3938 ahd->msgout_index = 0; 3939 ahd->msgout_len = 0; 3940 ahd_construct_sdtr(ahd, devinfo, 3941 period, offset); 3942 ahd->msgout_index = 0; 3943 response = TRUE; 3944 } 3945 done = MSGLOOP_MSGCOMPLETE; 3946 break; 3947 } 3948 case MSG_EXT_WDTR: 3949 { 3950 u_int bus_width; 3951 u_int saved_width; 3952 u_int sending_reply; 3953 3954 sending_reply = FALSE; 3955 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3956 reject = TRUE; 3957 break; 3958 } 3959 3960 /* 3961 * Wait until we have our arg before validating 3962 * and acting on this message. 3963 * 3964 * Add one to MSG_EXT_WDTR_LEN to account for 3965 * the extended message preamble. 3966 */ 3967 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3968 break; 3969 3970 bus_width = ahd->msgin_buf[3]; 3971 saved_width = bus_width; 3972 ahd_validate_width(ahd, tinfo, &bus_width, 3973 devinfo->role); 3974 if (bootverbose) { 3975 printf("(%s:%c:%d:%d): Received WDTR " 3976 "%x filtered to %x\n", 3977 ahd_name(ahd), devinfo->channel, 3978 devinfo->target, devinfo->lun, 3979 saved_width, bus_width); 3980 } 3981 3982 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3983 /* 3984 * Don't send a WDTR back to the 3985 * target, since we asked first. 3986 * If the width went higher than our 3987 * request, reject it. 3988 */ 3989 if (saved_width > bus_width) { 3990 reject = TRUE; 3991 printf("(%s:%c:%d:%d): requested %dBit " 3992 "transfers. Rejecting...\n", 3993 ahd_name(ahd), devinfo->channel, 3994 devinfo->target, devinfo->lun, 3995 8 * (0x01 << bus_width)); 3996 bus_width = 0; 3997 } 3998 } else { 3999 /* 4000 * Send our own WDTR in reply 4001 */ 4002 if (bootverbose 4003 && devinfo->role == ROLE_INITIATOR) { 4004 printf("(%s:%c:%d:%d): Target " 4005 "Initiated WDTR\n", 4006 ahd_name(ahd), devinfo->channel, 4007 devinfo->target, devinfo->lun); 4008 } 4009 ahd->msgout_index = 0; 4010 ahd->msgout_len = 0; 4011 ahd_construct_wdtr(ahd, devinfo, bus_width); 4012 ahd->msgout_index = 0; 4013 response = TRUE; 4014 sending_reply = TRUE; 4015 } 4016 ahd_set_width(ahd, devinfo, bus_width, 4017 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4018 /*paused*/TRUE); 4019 /* After a wide message, we are async */ 4020 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4021 /*offset*/0, /*ppr_options*/0, 4022 AHD_TRANS_ACTIVE, /*paused*/TRUE); 4023 if (sending_reply == FALSE && reject == FALSE) { 4024 4025 if (tinfo->goal.offset) { 4026 ahd->msgout_index = 0; 4027 ahd->msgout_len = 0; 4028 ahd_build_transfer_msg(ahd, devinfo); 4029 ahd->msgout_index = 0; 4030 response = TRUE; 4031 } 4032 } 4033 done = MSGLOOP_MSGCOMPLETE; 4034 break; 4035 } 4036 case MSG_EXT_PPR: 4037 { 4038 u_int period; 4039 u_int offset; 4040 u_int bus_width; 4041 u_int ppr_options; 4042 u_int saved_width; 4043 u_int saved_offset; 4044 u_int saved_ppr_options; 4045 4046 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4047 reject = TRUE; 4048 break; 4049 } 4050 4051 /* 4052 * Wait until we have all args before validating 4053 * and acting on this message. 4054 * 4055 * Add one to MSG_EXT_PPR_LEN to account for 4056 * the extended message preamble. 4057 */ 4058 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4059 break; 4060 4061 period = ahd->msgin_buf[3]; 4062 offset = ahd->msgin_buf[5]; 4063 bus_width = ahd->msgin_buf[6]; 4064 saved_width = bus_width; 4065 ppr_options = ahd->msgin_buf[7]; 4066 /* 4067 * According to the spec, a DT only 4068 * period factor with no DT option 4069 * set implies async. 4070 */ 4071 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4072 && period <= 9) 4073 offset = 0; 4074 saved_ppr_options = ppr_options; 4075 saved_offset = offset; 4076 4077 /* 4078 * Transfer options are only available if we 4079 * are negotiating wide. 4080 */ 4081 if (bus_width == 0) 4082 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4083 4084 ahd_validate_width(ahd, tinfo, &bus_width, 4085 devinfo->role); 4086 ahd_devlimited_syncrate(ahd, tinfo, &period, 4087 &ppr_options, devinfo->role); 4088 ahd_validate_offset(ahd, tinfo, period, &offset, 4089 bus_width, devinfo->role); 4090 4091 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4092 /* 4093 * If we are unable to do any of the 4094 * requested options (we went too low), 4095 * then we'll have to reject the message. 4096 */ 4097 if (saved_width > bus_width 4098 || saved_offset != offset 4099 || saved_ppr_options != ppr_options) { 4100 reject = TRUE; 4101 period = 0; 4102 offset = 0; 4103 bus_width = 0; 4104 ppr_options = 0; 4105 } 4106 } else { 4107 if (devinfo->role != ROLE_TARGET) 4108 printf("(%s:%c:%d:%d): Target " 4109 "Initiated PPR\n", 4110 ahd_name(ahd), devinfo->channel, 4111 devinfo->target, devinfo->lun); 4112 else 4113 printf("(%s:%c:%d:%d): Initiator " 4114 "Initiated PPR\n", 4115 ahd_name(ahd), devinfo->channel, 4116 devinfo->target, devinfo->lun); 4117 ahd->msgout_index = 0; 4118 ahd->msgout_len = 0; 4119 ahd_construct_ppr(ahd, devinfo, period, offset, 4120 bus_width, ppr_options); 4121 ahd->msgout_index = 0; 4122 response = TRUE; 4123 } 4124 if (bootverbose) { 4125 printf("(%s:%c:%d:%d): Received PPR width %x, " 4126 "period %x, offset %x,options %x\n" 4127 "\tFiltered to width %x, period %x, " 4128 "offset %x, options %x\n", 4129 ahd_name(ahd), devinfo->channel, 4130 devinfo->target, devinfo->lun, 4131 saved_width, ahd->msgin_buf[3], 4132 saved_offset, saved_ppr_options, 4133 bus_width, period, offset, ppr_options); 4134 } 4135 ahd_set_width(ahd, devinfo, bus_width, 4136 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4137 /*paused*/TRUE); 4138 ahd_set_syncrate(ahd, devinfo, period, 4139 offset, ppr_options, 4140 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4141 /*paused*/TRUE); 4142 4143 done = MSGLOOP_MSGCOMPLETE; 4144 break; 4145 } 4146 default: 4147 /* Unknown extended message. Reject it. */ 4148 reject = TRUE; 4149 break; 4150 } 4151 break; 4152 } 4153 #ifdef AHD_TARGET_MODE 4154 case MSG_BUS_DEV_RESET: 4155 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4156 CAM_BDR_SENT, 4157 "Bus Device Reset Received", 4158 /*verbose_level*/0); 4159 ahd_restart(ahd); 4160 done = MSGLOOP_TERMINATED; 4161 break; 4162 case MSG_ABORT_TAG: 4163 case MSG_ABORT: 4164 case MSG_CLEAR_QUEUE: 4165 { 4166 int tag; 4167 4168 /* Target mode messages */ 4169 if (devinfo->role != ROLE_TARGET) { 4170 reject = TRUE; 4171 break; 4172 } 4173 tag = SCB_LIST_NULL; 4174 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4175 tag = ahd_inb(ahd, INITIATOR_TAG); 4176 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4177 devinfo->lun, tag, ROLE_TARGET, 4178 CAM_REQ_ABORTED); 4179 4180 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4181 if (tstate != NULL) { 4182 struct ahd_tmode_lstate* lstate; 4183 4184 lstate = tstate->enabled_luns[devinfo->lun]; 4185 if (lstate != NULL) { 4186 ahd_queue_lstate_event(ahd, lstate, 4187 devinfo->our_scsiid, 4188 ahd->msgin_buf[0], 4189 /*arg*/tag); 4190 ahd_send_lstate_events(ahd, lstate); 4191 } 4192 } 4193 ahd_restart(ahd); 4194 done = MSGLOOP_TERMINATED; 4195 break; 4196 } 4197 #endif 4198 case MSG_QAS_REQUEST: 4199 #ifdef AHD_DEBUG 4200 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4201 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4202 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4203 #endif 4204 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4205 /* FALLTHROUGH */ 4206 case MSG_TERM_IO_PROC: 4207 default: 4208 reject = TRUE; 4209 break; 4210 } 4211 4212 if (reject) { 4213 /* 4214 * Setup to reject the message. 4215 */ 4216 ahd->msgout_index = 0; 4217 ahd->msgout_len = 1; 4218 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4219 done = MSGLOOP_MSGCOMPLETE; 4220 response = TRUE; 4221 } 4222 4223 if (done != MSGLOOP_IN_PROG && !response) 4224 /* Clear the outgoing message buffer */ 4225 ahd->msgout_len = 0; 4226 4227 return (done); 4228 } 4229 4230 /* 4231 * Process a message reject message. 4232 */ 4233 static int 4234 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4235 { 4236 /* 4237 * What we care about here is if we had an 4238 * outstanding SDTR or WDTR message for this 4239 * target. If we did, this is a signal that 4240 * the target is refusing negotiation. 4241 */ 4242 struct scb *scb; 4243 struct ahd_initiator_tinfo *tinfo; 4244 struct ahd_tmode_tstate *tstate; 4245 u_int scb_index; 4246 u_int last_msg; 4247 int response = 0; 4248 4249 scb_index = ahd_get_scbptr(ahd); 4250 scb = ahd_lookup_scb(ahd, scb_index); 4251 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4252 devinfo->our_scsiid, 4253 devinfo->target, &tstate); 4254 /* Might be necessary */ 4255 last_msg = ahd_inb(ahd, LAST_MSG); 4256 4257 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4258 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4259 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4260 /* 4261 * Target may not like our SPI-4 PPR Options. 4262 * Attempt to negotiate 80MHz which will turn 4263 * off these options. 4264 */ 4265 if (bootverbose) { 4266 printf("(%s:%c:%d:%d): PPR Rejected. " 4267 "Trying simple U160 PPR\n", 4268 ahd_name(ahd), devinfo->channel, 4269 devinfo->target, devinfo->lun); 4270 } 4271 tinfo->goal.period = AHD_SYNCRATE_DT; 4272 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4273 | MSG_EXT_PPR_QAS_REQ 4274 | MSG_EXT_PPR_DT_REQ; 4275 } else { 4276 /* 4277 * Target does not support the PPR message. 4278 * Attempt to negotiate SPI-2 style. 4279 */ 4280 if (bootverbose) { 4281 printf("(%s:%c:%d:%d): PPR Rejected. " 4282 "Trying WDTR/SDTR\n", 4283 ahd_name(ahd), devinfo->channel, 4284 devinfo->target, devinfo->lun); 4285 } 4286 tinfo->goal.ppr_options = 0; 4287 tinfo->curr.transport_version = 2; 4288 tinfo->goal.transport_version = 2; 4289 } 4290 ahd->msgout_index = 0; 4291 ahd->msgout_len = 0; 4292 ahd_build_transfer_msg(ahd, devinfo); 4293 ahd->msgout_index = 0; 4294 response = 1; 4295 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4296 4297 /* note 8bit xfers */ 4298 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4299 "8bit transfers\n", ahd_name(ahd), 4300 devinfo->channel, devinfo->target, devinfo->lun); 4301 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4302 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4303 /*paused*/TRUE); 4304 /* 4305 * No need to clear the sync rate. If the target 4306 * did not accept the command, our syncrate is 4307 * unaffected. If the target started the negotiation, 4308 * but rejected our response, we already cleared the 4309 * sync rate before sending our WDTR. 4310 */ 4311 if (tinfo->goal.offset != tinfo->curr.offset) { 4312 4313 /* Start the sync negotiation */ 4314 ahd->msgout_index = 0; 4315 ahd->msgout_len = 0; 4316 ahd_build_transfer_msg(ahd, devinfo); 4317 ahd->msgout_index = 0; 4318 response = 1; 4319 } 4320 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4321 /* note asynch xfers and clear flag */ 4322 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4323 /*offset*/0, /*ppr_options*/0, 4324 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4325 /*paused*/TRUE); 4326 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4327 "Using asynchronous transfers\n", 4328 ahd_name(ahd), devinfo->channel, 4329 devinfo->target, devinfo->lun); 4330 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4331 int tag_type; 4332 int mask; 4333 4334 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4335 4336 if (tag_type == MSG_SIMPLE_TASK) { 4337 printf("(%s:%c:%d:%d): refuses tagged commands. " 4338 "Performing non-tagged I/O\n", ahd_name(ahd), 4339 devinfo->channel, devinfo->target, devinfo->lun); 4340 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4341 mask = ~0x23; 4342 } else { 4343 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4344 "Performing simple queue tagged I/O only\n", 4345 ahd_name(ahd), devinfo->channel, devinfo->target, 4346 devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4347 ? "ordered" : "head of queue"); 4348 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4349 mask = ~0x03; 4350 } 4351 4352 /* 4353 * Resend the identify for this CCB as the target 4354 * may believe that the selection is invalid otherwise. 4355 */ 4356 ahd_outb(ahd, SCB_CONTROL, 4357 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4358 scb->hscb->control &= mask; 4359 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4360 /*type*/MSG_SIMPLE_TASK); 4361 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4362 ahd_assert_atn(ahd); 4363 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4364 SCB_GET_TAG(scb)); 4365 4366 /* 4367 * Requeue all tagged commands for this target 4368 * currently in our posession so they can be 4369 * converted to untagged commands. 4370 */ 4371 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4372 SCB_GET_CHANNEL(ahd, scb), 4373 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4374 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4375 SEARCH_COMPLETE); 4376 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4377 /* 4378 * Most likely the device believes that we had 4379 * previously negotiated packetized. 4380 */ 4381 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4382 | MSG_FLAG_IU_REQ_CHANGED; 4383 4384 ahd_force_renegotiation(ahd, devinfo); 4385 ahd->msgout_index = 0; 4386 ahd->msgout_len = 0; 4387 ahd_build_transfer_msg(ahd, devinfo); 4388 ahd->msgout_index = 0; 4389 response = 1; 4390 } else { 4391 /* 4392 * Otherwise, we ignore it. 4393 */ 4394 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4395 ahd_name(ahd), devinfo->channel, devinfo->target, 4396 last_msg); 4397 } 4398 return (response); 4399 } 4400 4401 /* 4402 * Process an ignore wide residue message. 4403 */ 4404 static void 4405 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4406 { 4407 u_int scb_index; 4408 struct scb *scb; 4409 4410 printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4411 4412 scb_index = ahd_get_scbptr(ahd); 4413 scb = ahd_lookup_scb(ahd, scb_index); 4414 /* 4415 * XXX Actually check data direction in the sequencer? 4416 * Perhaps add datadir to some spare bits in the hscb? 4417 */ 4418 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4419 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4420 /* 4421 * Ignore the message if we haven't 4422 * seen an appropriate data phase yet. 4423 */ 4424 } else { 4425 /* 4426 * If the residual occurred on the last 4427 * transfer and the transfer request was 4428 * expected to end on an odd count, do 4429 * nothing. Otherwise, subtract a byte 4430 * and update the residual count accordingly. 4431 */ 4432 uint32_t sgptr; 4433 4434 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4435 if ((sgptr & SG_LIST_NULL) != 0 4436 && (ahd_inb(ahd, SCB_TASK_ATTRIBUTE) & SCB_XFERLEN_ODD) != 0) { 4437 /* 4438 * If the residual occurred on the last 4439 * transfer and the transfer request was 4440 * expected to end on an odd count, do 4441 * nothing. 4442 */ 4443 } else { 4444 uint32_t data_cnt; 4445 uint64_t data_addr; 4446 uint32_t sglen; 4447 4448 /* Pull in the rest of the sgptr */ 4449 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4450 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4451 if ((sgptr & SG_LIST_NULL) != 0) { 4452 /* 4453 * The residual data count is not updated 4454 * for the command run to completion case. 4455 * Explcitly zero the count. 4456 */ 4457 data_cnt &= ~AHD_SG_LEN_MASK; 4458 } 4459 data_addr = ahd_inq(ahd, SHADDR); 4460 data_cnt += 1; 4461 data_addr -= 1; 4462 sgptr &= SG_PTR_MASK; 4463 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4464 struct ahd_dma64_seg *sg; 4465 4466 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4467 4468 /* 4469 * The residual sg ptr points to the next S/G 4470 * to load so we must go back one. 4471 */ 4472 sg--; 4473 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4474 if (sg != scb->sg_list 4475 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4476 4477 sg--; 4478 sglen = ahd_le32toh(sg->len); 4479 /* 4480 * Preserve High Address and SG_LIST 4481 * bits while setting the count to 1. 4482 */ 4483 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4484 data_addr = ahd_le64toh(sg->addr) 4485 + (sglen & AHD_SG_LEN_MASK) 4486 - 1; 4487 4488 /* 4489 * Increment sg so it points to the 4490 * "next" sg. 4491 */ 4492 sg++; 4493 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4494 sg); 4495 } 4496 } else { 4497 struct ahd_dma_seg *sg; 4498 4499 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4500 4501 /* 4502 * The residual sg ptr points to the next S/G 4503 * to load so we must go back one. 4504 */ 4505 sg--; 4506 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4507 if (sg != scb->sg_list 4508 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4509 4510 sg--; 4511 sglen = ahd_le32toh(sg->len); 4512 /* 4513 * Preserve High Address and SG_LIST 4514 * bits while setting the count to 1. 4515 */ 4516 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4517 data_addr = ahd_le32toh(sg->addr) 4518 + (sglen & AHD_SG_LEN_MASK) 4519 - 1; 4520 4521 /* 4522 * Increment sg so it points to the 4523 * "next" sg. 4524 */ 4525 sg++; 4526 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4527 sg); 4528 } 4529 } 4530 /* 4531 * Toggle the "oddness" of the transfer length 4532 * to handle this mid-transfer ignore wide 4533 * residue. This ensures that the oddness is 4534 * correct for subsequent data transfers. 4535 */ 4536 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4537 ahd_inb(ahd, SCB_TASK_ATTRIBUTE) ^ SCB_XFERLEN_ODD); 4538 4539 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4540 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4541 /* 4542 * The FIFO's pointers will be updated if/when the 4543 * sequencer re-enters a data phase. 4544 */ 4545 } 4546 } 4547 } 4548 4549 4550 /* 4551 * Reinitialize the data pointers for the active transfer 4552 * based on its current residual. 4553 */ 4554 static void 4555 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4556 { 4557 struct scb *scb; 4558 ahd_mode_state saved_modes; 4559 u_int scb_index; 4560 u_int wait; 4561 uint32_t sgptr; 4562 uint32_t resid; 4563 uint64_t dataptr; 4564 4565 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4566 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4567 4568 scb_index = ahd_get_scbptr(ahd); 4569 scb = ahd_lookup_scb(ahd, scb_index); 4570 4571 /* 4572 * Release and reacquire the FIFO so we 4573 * have a clean slate. 4574 */ 4575 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4576 wait = 1000; 4577 do { 4578 ahd_delay(100); 4579 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)); 4580 if (wait == 0) { 4581 ahd_print_path(ahd, scb); 4582 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4583 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4584 } 4585 saved_modes = ahd_save_modes(ahd); 4586 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4587 ahd_outb(ahd, DFFSTAT, 4588 ahd_inb(ahd, DFFSTAT) 4589 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4590 4591 /* 4592 * Determine initial values for data_addr and data_cnt 4593 * for resuming the data phase. 4594 */ 4595 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4596 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4597 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4598 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4599 sgptr &= SG_PTR_MASK; 4600 4601 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4602 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4603 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4604 4605 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4606 struct ahd_dma64_seg *sg; 4607 4608 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4609 4610 /* The residual sg_ptr always points to the next sg */ 4611 sg--; 4612 4613 dataptr = ahd_le64toh(sg->addr) 4614 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4615 - resid; 4616 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4617 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4618 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4619 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4620 } else { 4621 struct ahd_dma_seg *sg; 4622 4623 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4624 4625 /* The residual sg_ptr always points to the next sg */ 4626 sg--; 4627 4628 dataptr = ahd_le32toh(sg->addr) 4629 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4630 - resid; 4631 ahd_outb(ahd, HADDR + 4, 4632 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4633 } 4634 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4635 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4636 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4637 ahd_outb(ahd, HADDR, dataptr); 4638 ahd_outb(ahd, HCNT + 2, resid >> 16); 4639 ahd_outb(ahd, HCNT + 1, resid >> 8); 4640 ahd_outb(ahd, HCNT, resid); 4641 } 4642 4643 /* 4644 * Handle the effects of issuing a bus device reset message. 4645 */ 4646 static void 4647 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4648 u_int lun, cam_status status, char *message, 4649 int verbose_level) 4650 { 4651 #ifdef AHD_TARGET_MODE 4652 struct ahd_tmode_tstate* tstate; 4653 #endif 4654 int found; 4655 4656 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4657 lun, SCB_LIST_NULL, devinfo->role, 4658 status); 4659 4660 #ifdef AHD_TARGET_MODE 4661 /* 4662 * Send an immediate notify ccb to all target mord peripheral 4663 * drivers affected by this action. 4664 */ 4665 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4666 if (tstate != NULL) { 4667 u_int cur_lun; 4668 u_int max_lun; 4669 4670 if (lun != CAM_LUN_WILDCARD) { 4671 cur_lun = 0; 4672 max_lun = AHD_NUM_LUNS - 1; 4673 } else { 4674 cur_lun = lun; 4675 max_lun = lun; 4676 } 4677 for (cur_lun <= max_lun; cur_lun++) { 4678 struct ahd_tmode_lstate* lstate; 4679 4680 lstate = tstate->enabled_luns[cur_lun]; 4681 if (lstate == NULL) 4682 continue; 4683 4684 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4685 MSG_BUS_DEV_RESET, /*arg*/0); 4686 ahd_send_lstate_events(ahd, lstate); 4687 } 4688 } 4689 #endif 4690 4691 /* 4692 * Go back to async/narrow transfers and renegotiate. 4693 */ 4694 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4695 AHD_TRANS_CUR, /*paused*/TRUE); 4696 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4697 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4698 4699 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4700 lun, AC_SENT_BDR, NULL); 4701 4702 if (message != NULL 4703 && (verbose_level <= bootverbose)) 4704 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4705 message, devinfo->channel, devinfo->target, found); 4706 } 4707 4708 #ifdef AHD_TARGET_MODE 4709 static void 4710 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4711 struct scb *scb) 4712 { 4713 4714 /* 4715 * To facilitate adding multiple messages together, 4716 * each routine should increment the index and len 4717 * variables instead of setting them explicitly. 4718 */ 4719 ahd->msgout_index = 0; 4720 ahd->msgout_len = 0; 4721 4722 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4723 ahd_build_transfer_msg(ahd, devinfo); 4724 else 4725 panic("ahd_intr: AWAITING target message with no message"); 4726 4727 ahd->msgout_index = 0; 4728 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4729 } 4730 #endif 4731 /**************************** Initialization **********************************/ 4732 static u_int 4733 ahd_sglist_size(struct ahd_softc *ahd) 4734 { 4735 bus_size_t list_size; 4736 4737 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4738 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4739 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4740 return (list_size); 4741 } 4742 4743 /* 4744 * Calculate the optimum S/G List allocation size. S/G elements used 4745 * for a given transaction must be physically contiguous. Assume the 4746 * OS will allocate full pages to us, so it doesn't make sense to request 4747 * less than a page. 4748 */ 4749 static u_int 4750 ahd_sglist_allocsize(struct ahd_softc *ahd) 4751 { 4752 bus_size_t sg_list_increment; 4753 bus_size_t sg_list_size; 4754 bus_size_t max_list_size; 4755 bus_size_t best_list_size; 4756 4757 /* Start out with the minimum required for AHD_NSEG. */ 4758 sg_list_increment = ahd_sglist_size(ahd); 4759 sg_list_size = sg_list_increment; 4760 4761 /* Get us as close as possible to a page in size. */ 4762 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4763 sg_list_size += sg_list_increment; 4764 4765 /* 4766 * Try to reduce the amount of wastage by allocating 4767 * multiple pages. 4768 */ 4769 best_list_size = sg_list_size; 4770 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4771 if (max_list_size < 4 * PAGE_SIZE) 4772 max_list_size = 4 * PAGE_SIZE; 4773 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4774 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4775 while ((sg_list_size + sg_list_increment) <= max_list_size 4776 && (sg_list_size % PAGE_SIZE) != 0) { 4777 bus_size_t new_mod; 4778 bus_size_t best_mod; 4779 4780 sg_list_size += sg_list_increment; 4781 new_mod = sg_list_size % PAGE_SIZE; 4782 best_mod = best_list_size % PAGE_SIZE; 4783 if (new_mod > best_mod || new_mod == 0) { 4784 best_list_size = sg_list_size; 4785 } 4786 } 4787 return (best_list_size); 4788 } 4789 4790 int 4791 ahd_softc_init(struct ahd_softc *ahd) 4792 { 4793 4794 ahd->unpause = 0; 4795 ahd->pause = PAUSE; 4796 return (0); 4797 } 4798 4799 void 4800 ahd_set_unit(struct ahd_softc *ahd, int unit) 4801 { 4802 ahd->unit = unit; 4803 } 4804 4805 void 4806 ahd_set_name(struct ahd_softc *ahd, char *name) 4807 { 4808 if (ahd->name != NULL) 4809 free(ahd->name, M_DEVBUF); 4810 ahd->name = name; 4811 } 4812 4813 void 4814 ahd_free(struct ahd_softc *ahd) 4815 { 4816 int i; 4817 4818 switch (ahd->init_level) { 4819 default: 4820 case 2: 4821 ahd_shutdown(ahd); 4822 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4823 /* FALLTHROUGH */ 4824 case 1: 4825 bus_dmamap_unload(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4826 bus_dmamap_destroy(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4827 bus_dmamem_unmap(ahd->parent_dmat, (caddr_t)ahd->qoutfifo, ahd->shared_data_size); 4828 bus_dmamem_free(ahd->parent_dmat, &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); 4829 break; 4830 case 0: 4831 break; 4832 } 4833 4834 ahd_platform_free(ahd); 4835 ahd_fini_scbdata(ahd); 4836 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4837 struct ahd_tmode_tstate *tstate; 4838 4839 tstate = ahd->enabled_targets[i]; 4840 if (tstate != NULL) { 4841 #if AHD_TARGET_MODE 4842 int j; 4843 4844 for (j = 0; j < AHD_NUM_LUNS; j++) { 4845 struct ahd_tmode_lstate *lstate; 4846 4847 lstate = tstate->enabled_luns[j]; 4848 if (lstate != NULL) { 4849 xpt_free_path(lstate->path); 4850 free(lstate, M_DEVBUF); 4851 } 4852 } 4853 #endif 4854 free(tstate, M_DEVBUF); 4855 } 4856 } 4857 #if AHD_TARGET_MODE 4858 if (ahd->black_hole != NULL) { 4859 xpt_free_path(ahd->black_hole->path); 4860 free(ahd->black_hole, M_DEVBUF); 4861 } 4862 #endif 4863 if (ahd->name != NULL) 4864 free(ahd->name, M_DEVBUF); 4865 if (ahd->seep_config != NULL) 4866 free(ahd->seep_config, M_DEVBUF); 4867 if (ahd->saved_stack != NULL) 4868 free(ahd->saved_stack, M_DEVBUF); 4869 #ifndef __FreeBSD__ 4870 free(ahd, M_DEVBUF); 4871 #endif 4872 return; 4873 } 4874 4875 void 4876 ahd_shutdown(void *arg) 4877 { 4878 struct ahd_softc *ahd; 4879 4880 ahd = (struct ahd_softc *)arg; 4881 4882 #ifdef AHD_DEBUG 4883 printf("%s: ahd_shutdown\n", ahd_name(ahd)); 4884 #endif 4885 /* 4886 * Stop periodic timer callbacks. 4887 */ 4888 ahd_timer_stop(&ahd->reset_timer); 4889 ahd_timer_stop(&ahd->stat_timer); 4890 4891 /* This will reset most registers to 0, but not all */ 4892 ahd_reset(ahd); 4893 } 4894 4895 /* 4896 * Reset the controller and record some information about it 4897 * that is only available just after a reset. 4898 */ 4899 int 4900 ahd_reset(struct ahd_softc *ahd) 4901 { 4902 u_int sxfrctl1; 4903 int wait; 4904 uint32_t cmd; 4905 struct ahd_pci_busdata *bd = ahd->bus_data; 4906 4907 /* 4908 * Preserve the value of the SXFRCTL1 register for all channels. 4909 * It contains settings that affect termination and we don't want 4910 * to disturb the integrity of the bus. 4911 */ 4912 ahd_pause(ahd); 4913 ahd_update_modes(ahd); 4914 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4915 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4916 4917 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 4918 4919 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4920 uint32_t mod_cmd; 4921 4922 /* 4923 * A4 Razor #632 4924 * During the assertion of CHIPRST, the chip 4925 * does not disable its parity logic prior to 4926 * the start of the reset. This may cause a 4927 * parity error to be detected and thus a 4928 * spurious SERR or PERR assertion. Disble 4929 * PERR and SERR responses during the CHIPRST. 4930 */ 4931 mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 4932 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, mod_cmd); 4933 } 4934 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 4935 4936 /* 4937 * Ensure that the reset has finished. We delay 1000us 4938 * prior to reading the register to make sure the chip 4939 * has sufficiently completed its reset to handle register 4940 * accesses. 4941 */ 4942 wait = 1000; 4943 do { 4944 ahd_delay(1000); 4945 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 4946 4947 if (wait == 0) { 4948 printf("%s: WARNING - Failed chip reset! " 4949 "Trying to initialize anyway.\n", ahd_name(ahd)); 4950 } 4951 ahd_outb(ahd, HCNTRL, ahd->pause); 4952 4953 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4954 /* 4955 * Clear any latched PCI error status and restore 4956 * previous SERR and PERR response enables. 4957 */ 4958 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 0x000000FF); 4959 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 4960 PCI_COMMAND_SERR_ENABLE|PCI_COMMAND_PARITY_ENABLE); 4961 } 4962 4963 /* 4964 * Mode should be SCSI after a chip reset, but lets 4965 * set it just to be safe. We touch the MODE_PTR 4966 * register directly so as to bypass the lazy update 4967 * ode in ahd_set_modes(). 4968 */ 4969 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4970 ahd_outb(ahd, MODE_PTR, 4971 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 4972 4973 /* 4974 * Restore SXFRCTL1. 4975 * 4976 * We must always initialize STPWEN to 1 before we 4977 * restore the saved values. STPWEN is initialized 4978 * to a tri-state condition which can only be cleared 4979 * by turning it on. 4980 */ 4981 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 4982 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 4983 4984 /* Determine chip configuration */ 4985 ahd->features &= ~AHD_WIDE; 4986 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 4987 ahd->features |= AHD_WIDE; 4988 4989 /* 4990 * If a recovery action has forced a chip reset, 4991 * re-initialize the chip to our liking. 4992 */ 4993 if (ahd->init_level > 0) 4994 ahd_chip_init(ahd); 4995 4996 return (0); 4997 } 4998 4999 /* 5000 * Determine the number of SCBs available on the controller 5001 */ 5002 int 5003 ahd_probe_scbs(struct ahd_softc *ahd) { 5004 int i; 5005 5006 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5007 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5008 for (i = 0; i < AHD_SCB_MAX; i++) { 5009 int j; 5010 int ret; 5011 5012 ahd_set_scbptr(ahd, i); 5013 ahd_outw(ahd, SCB_BASE, i); 5014 for (j = 2; j < 64; j++) 5015 ahd_outb(ahd, SCB_BASE+j, 0); 5016 /* Start out life as unallocated (needing an abort) */ 5017 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5018 ret = ahd_inw_scbram(ahd, SCB_BASE); 5019 if (ret != i) { 5020 printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", ahd_name(ahd), i, ret); 5021 break; 5022 } 5023 ahd_set_scbptr(ahd, 0); 5024 ret = ahd_inw_scbram(ahd, SCB_BASE); 5025 if (ret != 0) { 5026 printf("ahd_probe_scbs (non zero): returned 0x%x\n", ret); 5027 break; 5028 } 5029 } 5030 return (i); 5031 } 5032 5033 static void 5034 ahd_initialize_hscbs(struct ahd_softc *ahd) 5035 { 5036 int i; 5037 5038 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5039 ahd_set_scbptr(ahd, i); 5040 5041 /* Clear the control byte. */ 5042 ahd_outb(ahd, SCB_CONTROL, 0); 5043 5044 /* Set the next pointer */ 5045 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5046 } 5047 } 5048 5049 static int 5050 ahd_init_scbdata(struct ahd_softc *ahd) 5051 { 5052 struct scb_data *scb_data; 5053 int i; 5054 5055 scb_data = &ahd->scb_data; 5056 TAILQ_INIT(&scb_data->free_scbs); 5057 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5058 LIST_INIT(&scb_data->free_scb_lists[i]); 5059 LIST_INIT(&scb_data->any_dev_free_scb_list); 5060 SLIST_INIT(&scb_data->hscb_maps); 5061 SLIST_INIT(&scb_data->sg_maps); 5062 SLIST_INIT(&scb_data->sense_maps); 5063 5064 /* Determine the number of hardware SCBs and initialize them */ 5065 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5066 if (scb_data->maxhscbs == 0) { 5067 printf("%s: No SCB space found\n", ahd_name(ahd)); 5068 return (ENXIO); 5069 } 5070 ahd_initialize_hscbs(ahd); 5071 5072 /* 5073 * Create our DMA tags. These tags define the kinds of device 5074 * accessible memory allocations and memory mappings we will 5075 * need to perform during normal operation. 5076 * 5077 * Unless we need to further restrict the allocation, we rely 5078 * on the restrictions of the parent dmat, hence the common 5079 * use of MAXADDR and MAXSIZE. 5080 */ 5081 5082 /* Perform initial CCB allocation */ 5083 ahd_alloc_scbs(ahd); 5084 5085 if (scb_data->numscbs == 0) { 5086 printf("%s: ahd_init_scbdata - " 5087 "Unable to allocate initial scbs\n", 5088 ahd_name(ahd)); 5089 goto error_exit; 5090 } 5091 5092 /* 5093 * Note that we were successfull 5094 */ 5095 return (0); 5096 5097 error_exit: 5098 5099 return (ENOMEM); 5100 } 5101 5102 static struct scb * 5103 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5104 { 5105 struct scb *scb; 5106 5107 /* 5108 * Look on the pending list. 5109 */ 5110 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5111 if (SCB_GET_TAG(scb) == tag) 5112 return (scb); 5113 } 5114 5115 /* 5116 * Then on all of the collision free lists. 5117 */ 5118 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5119 struct scb *list_scb; 5120 5121 list_scb = scb; 5122 do { 5123 if (SCB_GET_TAG(list_scb) == tag) 5124 return (list_scb); 5125 list_scb = LIST_NEXT(list_scb, collision_links); 5126 } while (list_scb); 5127 } 5128 5129 /* 5130 * And finally on the generic free list. 5131 */ 5132 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5133 if (SCB_GET_TAG(scb) == tag) 5134 return (scb); 5135 } 5136 5137 return (NULL); 5138 } 5139 5140 static void 5141 ahd_fini_scbdata(struct ahd_softc *ahd) 5142 { 5143 struct scb_data *scb_data; 5144 5145 scb_data = &ahd->scb_data; 5146 if (scb_data == NULL) 5147 return; 5148 5149 switch (scb_data->init_level) { 5150 default: 5151 case 3: 5152 { 5153 struct map_node *sns_map; 5154 5155 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5156 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5157 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5158 sns_map->dmamap, (caddr_t)sns_map->vaddr, 5159 &sns_map->dmasegs, sns_map->nseg); 5160 free(sns_map, M_DEVBUF); 5161 } 5162 /* FALLTHROUGH */ 5163 } 5164 case 2: 5165 { 5166 struct map_node *sg_map; 5167 5168 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5169 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5170 ahd_freedmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), 5171 sg_map->dmamap, (caddr_t)sg_map->vaddr, 5172 &sg_map->dmasegs, sg_map->nseg); 5173 free(sg_map, M_DEVBUF); 5174 } 5175 /* FALLTHROUGH */ 5176 } 5177 case 1: 5178 { 5179 struct map_node *hscb_map; 5180 5181 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5182 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5183 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5184 hscb_map->dmamap, (caddr_t)hscb_map->vaddr, 5185 &hscb_map->dmasegs, hscb_map->nseg); 5186 free(hscb_map, M_DEVBUF); 5187 } 5188 /* FALLTHROUGH */ 5189 } 5190 case 0: 5191 break; 5192 } 5193 } 5194 5195 /* 5196 * DSP filter Bypass must be enabled until the first selection 5197 * after a change in bus mode (Razor #491 and #493). 5198 */ 5199 static void 5200 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5201 { 5202 ahd_mode_state saved_modes; 5203 5204 saved_modes = ahd_save_modes(ahd); 5205 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5206 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5207 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5208 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5209 #ifdef AHD_DEBUG 5210 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5211 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5212 #endif 5213 ahd_restore_modes(ahd, saved_modes); 5214 } 5215 5216 static void 5217 ahd_iocell_first_selection(struct ahd_softc *ahd) 5218 { 5219 ahd_mode_state saved_modes; 5220 u_int sblkctl; 5221 5222 saved_modes = ahd_save_modes(ahd); 5223 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5224 sblkctl = ahd_inb(ahd, SBLKCTL); 5225 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5226 #ifdef AHD_DEBUG 5227 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5228 printf("%s: iocell first selection\n", ahd_name(ahd)); 5229 #endif 5230 if ((sblkctl & ENAB40) != 0) { 5231 ahd_outb(ahd, DSPDATACTL, 5232 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5233 #ifdef AHD_DEBUG 5234 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5235 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5236 #endif 5237 } 5238 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5239 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5240 ahd_restore_modes(ahd, saved_modes); 5241 } 5242 5243 /*************************** SCB Management ***********************************/ 5244 static void 5245 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5246 { 5247 struct scb_list *free_list; 5248 struct scb_tailq *free_tailq; 5249 struct scb *first_scb; 5250 5251 scb->flags |= SCB_ON_COL_LIST; 5252 AHD_SET_SCB_COL_IDX(scb, col_idx); 5253 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5254 free_tailq = &ahd->scb_data.free_scbs; 5255 first_scb = LIST_FIRST(free_list); 5256 if (first_scb != NULL) { 5257 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5258 } else { 5259 LIST_INSERT_HEAD(free_list, scb, collision_links); 5260 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5261 } 5262 } 5263 5264 static void 5265 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5266 { 5267 struct scb_list *free_list; 5268 struct scb_tailq *free_tailq; 5269 struct scb *first_scb; 5270 u_int col_idx; 5271 5272 scb->flags &= ~SCB_ON_COL_LIST; 5273 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5274 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5275 free_tailq = &ahd->scb_data.free_scbs; 5276 first_scb = LIST_FIRST(free_list); 5277 if (first_scb == scb) { 5278 struct scb *next_scb; 5279 5280 /* 5281 * Maintain order in the collision free 5282 * lists for fairness if this device has 5283 * other colliding tags active. 5284 */ 5285 next_scb = LIST_NEXT(scb, collision_links); 5286 if (next_scb != NULL) { 5287 TAILQ_INSERT_AFTER(free_tailq, scb, 5288 next_scb, links.tqe); 5289 } 5290 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5291 } 5292 LIST_REMOVE(scb, collision_links); 5293 } 5294 5295 /* 5296 * Get a free scb. If there are none, see if we can allocate a new SCB. 5297 */ 5298 struct scb * 5299 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5300 { 5301 struct scb *scb; 5302 int tries; 5303 5304 tries = 0; 5305 look_again: 5306 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5307 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5308 ahd_rem_col_list(ahd, scb); 5309 goto found; 5310 } 5311 } 5312 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5313 5314 if (tries++ != 0) 5315 return (NULL); 5316 ahd_alloc_scbs(ahd); 5317 goto look_again; 5318 } 5319 LIST_REMOVE(scb, links.le); 5320 if (col_idx != AHD_NEVER_COL_IDX 5321 && (scb->col_scb != NULL) 5322 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5323 LIST_REMOVE(scb->col_scb, links.le); 5324 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5325 } 5326 found: 5327 scb->flags |= SCB_ACTIVE; 5328 return (scb); 5329 } 5330 5331 /* 5332 * Return an SCB resource to the free list. 5333 */ 5334 void 5335 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5336 { 5337 5338 /* Clean up for the next user */ 5339 scb->flags = SCB_FLAG_NONE; 5340 scb->hscb->control = 0; 5341 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5342 5343 if (scb->col_scb == NULL) { 5344 5345 /* 5346 * No collision possible. Just free normally. 5347 */ 5348 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5349 scb, links.le); 5350 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5351 5352 /* 5353 * The SCB we might have collided with is on 5354 * a free collision list. Put both SCBs on 5355 * the generic list. 5356 */ 5357 ahd_rem_col_list(ahd, scb->col_scb); 5358 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5359 scb, links.le); 5360 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5361 scb->col_scb, links.le); 5362 } else if ((scb->col_scb->flags 5363 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5364 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5365 5366 /* 5367 * The SCB we might collide with on the next allocation 5368 * is still active in a non-packetized, tagged, context. 5369 * Put us on the SCB collision list. 5370 */ 5371 ahd_add_col_list(ahd, scb, 5372 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5373 } else { 5374 /* 5375 * The SCB we might collide with on the next allocation 5376 * is either active in a packetized context, or free. 5377 * Since we can't collide, put this SCB on the generic 5378 * free list. 5379 */ 5380 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5381 scb, links.le); 5382 } 5383 5384 ahd_platform_scb_free(ahd, scb); 5385 } 5386 5387 void 5388 ahd_alloc_scbs(struct ahd_softc *ahd) 5389 { 5390 struct scb_data *scb_data; 5391 struct scb *next_scb; 5392 struct hardware_scb *hscb; 5393 struct map_node *hscb_map; 5394 struct map_node *sg_map; 5395 struct map_node *sense_map; 5396 uint8_t *segs; 5397 uint8_t *sense_data; 5398 bus_addr_t hscb_busaddr; 5399 bus_addr_t sg_busaddr; 5400 bus_addr_t sense_busaddr; 5401 int newcount; 5402 int i; 5403 5404 scb_data = &ahd->scb_data; 5405 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5406 /* Can't allocate any more */ 5407 return; 5408 5409 KASSERT(scb_data->scbs_left >= 0); 5410 if (scb_data->scbs_left != 0) { 5411 int offset; 5412 5413 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5414 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5415 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5416 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5417 } else { 5418 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5419 5420 if (hscb_map == NULL) 5421 return; 5422 5423 memset(hscb_map, 0, sizeof(*hscb_map)); 5424 5425 /* Allocate the next batch of hardware SCBs */ 5426 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5427 &hscb_map->dmamap, (caddr_t *)&hscb_map->vaddr, 5428 &hscb_map->physaddr, &hscb_map->dmasegs, 5429 &hscb_map->nseg, ahd_name(ahd), 5430 "hardware SCB structures") < 0) { 5431 free(hscb_map, M_DEVBUF); 5432 return; 5433 } 5434 5435 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5436 5437 hscb = (struct hardware_scb *)hscb_map->vaddr; 5438 hscb_busaddr = hscb_map->physaddr; 5439 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5440 } 5441 5442 scb_data->init_level++; 5443 5444 if (scb_data->sgs_left != 0) { 5445 int offset; 5446 5447 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5448 - scb_data->sgs_left) * ahd_sglist_size(ahd); 5449 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5450 segs = sg_map->vaddr + offset; 5451 sg_busaddr = sg_map->physaddr + offset; 5452 } else { 5453 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5454 5455 if (sg_map == NULL) 5456 return; 5457 5458 bzero(sg_map, sizeof(*sg_map)); 5459 5460 /* Allocate the next batch of S/G lists */ 5461 if (ahd_createdmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), ahd->sc_dmaflags, 5462 &sg_map->dmamap, (caddr_t *)&sg_map->vaddr, 5463 &sg_map->physaddr, &sg_map->dmasegs, 5464 &sg_map->nseg, ahd_name(ahd), 5465 "SG data structures") < 0) { 5466 free(sg_map, M_DEVBUF); 5467 return; 5468 } 5469 5470 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5471 5472 segs = sg_map->vaddr; 5473 sg_busaddr = sg_map->physaddr; 5474 scb_data->sgs_left = 5475 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5476 #ifdef AHD_DEBUG 5477 if (ahd_debug & AHD_SHOW_MEMORY) 5478 printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd)); 5479 #endif 5480 } 5481 5482 scb_data->init_level++; 5483 5484 5485 if (scb_data->sense_left != 0) { 5486 int offset; 5487 5488 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5489 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5490 sense_data = sense_map->vaddr + offset; 5491 sense_busaddr = sense_map->physaddr + offset; 5492 } else { 5493 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5494 5495 if (sense_map == NULL) 5496 return; 5497 5498 bzero(sense_map, sizeof(*sense_map)); 5499 5500 /* Allocate the next batch of sense buffers */ 5501 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5502 &sense_map->dmamap, (caddr_t *)&sense_map->vaddr, 5503 &sense_map->physaddr, &sense_map->dmasegs, 5504 &sense_map->nseg, ahd_name(ahd), 5505 "Sense Data structures") < 0) { 5506 free(sense_map, M_DEVBUF); 5507 return; 5508 } 5509 5510 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5511 5512 sense_data = sense_map->vaddr; 5513 sense_busaddr = sense_map->physaddr; 5514 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5515 #ifdef AHD_DEBUG 5516 if (ahd_debug & AHD_SHOW_MEMORY) 5517 printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd)); 5518 #endif 5519 } 5520 5521 scb_data->init_level++; 5522 5523 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5524 newcount = MIN(newcount, scb_data->sgs_left); 5525 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5526 scb_data->sense_left -= newcount; 5527 scb_data->scbs_left -= newcount; 5528 scb_data->sgs_left -= newcount; 5529 5530 for (i = 0; i < newcount; i++) { 5531 u_int col_tag; 5532 5533 struct scb_platform_data *pdata; 5534 #ifndef __linux__ 5535 int error; 5536 #endif 5537 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5538 M_DEVBUF, M_NOWAIT); 5539 if (next_scb == NULL) 5540 break; 5541 5542 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5543 M_DEVBUF, M_NOWAIT); 5544 if (pdata == NULL) { 5545 free(next_scb, M_DEVBUF); 5546 break; 5547 } 5548 next_scb->platform_data = pdata; 5549 next_scb->hscb_map = hscb_map; 5550 next_scb->sg_map = sg_map; 5551 next_scb->sense_map = sense_map; 5552 next_scb->sg_list = segs; 5553 next_scb->sense_data = sense_data; 5554 next_scb->sense_busaddr = sense_busaddr; 5555 memset(hscb, 0, sizeof(*hscb)); 5556 next_scb->hscb = hscb; 5557 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5558 KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && 5559 (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); 5560 5561 /* 5562 * The sequencer always starts with the second entry. 5563 * The first entry is embedded in the scb. 5564 */ 5565 next_scb->sg_list_busaddr = sg_busaddr; 5566 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5567 next_scb->sg_list_busaddr 5568 += sizeof(struct ahd_dma64_seg); 5569 else 5570 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5571 next_scb->ahd_softc = ahd; 5572 next_scb->flags = SCB_FLAG_NONE; 5573 5574 error = bus_dmamap_create(ahd->parent_dmat, 5575 AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0, 5576 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahd->sc_dmaflags, 5577 &next_scb->dmamap); 5578 if (error != 0) { 5579 free(next_scb, M_DEVBUF); 5580 free(pdata, M_DEVBUF); 5581 break; 5582 } 5583 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5584 col_tag = scb_data->numscbs ^ 0x100; 5585 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5586 if (next_scb->col_scb != NULL) 5587 next_scb->col_scb->col_scb = next_scb; 5588 ahd_free_scb(ahd, next_scb); 5589 hscb++; 5590 hscb_busaddr += sizeof(*hscb); 5591 segs += ahd_sglist_size(ahd); 5592 sg_busaddr += ahd_sglist_size(ahd); 5593 sense_data += AHD_SENSE_BUFSIZE; 5594 sense_busaddr += AHD_SENSE_BUFSIZE; 5595 scb_data->numscbs++; 5596 } 5597 } 5598 5599 void 5600 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5601 { 5602 const char *speed; 5603 const char *type; 5604 int len; 5605 5606 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5607 buf += len; 5608 5609 speed = "Ultra320 "; 5610 if ((ahd->features & AHD_WIDE) != 0) { 5611 type = "Wide "; 5612 } else { 5613 type = "Single "; 5614 } 5615 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5616 speed, type, ahd->channel, ahd->our_id); 5617 buf += len; 5618 5619 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5620 ahd->scb_data.maxhscbs); 5621 } 5622 5623 static const char *channel_strings[] = { 5624 "Primary Low", 5625 "Primary High", 5626 "Secondary Low", 5627 "Secondary High" 5628 }; 5629 5630 static const char *termstat_strings[] = { 5631 "Terminated Correctly", 5632 "Over Terminated", 5633 "Under Terminated", 5634 "Not Configured" 5635 }; 5636 5637 /* 5638 * Start the board, ready for normal operation 5639 */ 5640 int 5641 ahd_init(struct ahd_softc *ahd) 5642 { 5643 uint8_t *next_vaddr; 5644 bus_addr_t next_baddr; 5645 size_t driver_data_size; 5646 int i; 5647 int error; 5648 u_int warn_user; 5649 uint8_t current_sensing; 5650 uint8_t fstat; 5651 5652 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5653 5654 ahd->stack_size = ahd_probe_stack_size(ahd); 5655 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5656 M_DEVBUF, M_NOWAIT); 5657 if (ahd->saved_stack == NULL) 5658 return (ENOMEM); 5659 /* Zero the memory */ 5660 memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); 5661 5662 /* 5663 * Verify that the compiler hasn't over-agressively 5664 * padded important structures. 5665 */ 5666 if (sizeof(struct hardware_scb) != 64) 5667 panic("Hardware SCB size is incorrect"); 5668 5669 #ifdef AHD_DEBUG 5670 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5671 ahd->flags |= AHD_SEQUENCER_DEBUG; 5672 #endif 5673 5674 /* 5675 * Default to allowing initiator operations. 5676 */ 5677 ahd->flags |= AHD_INITIATORROLE; 5678 5679 /* 5680 * Only allow target mode features if this unit has them enabled. 5681 */ 5682 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5683 ahd->features &= ~AHD_TARGETMODE; 5684 5685 /* 5686 * DMA tag for our command fifos and other data in system memory 5687 * the card's sequencer must be able to access. For initiator 5688 * roles, we need to allocate space for the qoutfifo. When providing 5689 * for the target mode role, we must additionally provide space for 5690 * the incoming target command fifo. 5691 */ 5692 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5693 + sizeof(struct hardware_scb); 5694 if ((ahd->features & AHD_TARGETMODE) != 0) 5695 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5696 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5697 driver_data_size += PKT_OVERRUN_BUFSIZE; 5698 ahd->shared_data_size = driver_data_size; 5699 5700 memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); 5701 ahd->sc_dmaflags = BUS_DMA_NOWAIT; 5702 5703 if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 5704 ahd->sc_dmaflags, 5705 &ahd->shared_data_map.dmamap, (caddr_t *)&ahd->shared_data_map.vaddr, 5706 &ahd->shared_data_map.physaddr, &ahd->shared_data_map.dmasegs, 5707 &ahd->shared_data_map.nseg, ahd_name(ahd), "shared data") < 0) 5708 return (ENOMEM); 5709 ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; 5710 5711 ahd->init_level++; 5712 5713 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5714 next_baddr = ahd->shared_data_map.physaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5715 if ((ahd->features & AHD_TARGETMODE) != 0) { 5716 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5717 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5718 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5719 } 5720 5721 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5722 ahd->overrun_buf = next_vaddr; 5723 next_vaddr += PKT_OVERRUN_BUFSIZE; 5724 next_baddr += PKT_OVERRUN_BUFSIZE; 5725 } 5726 5727 /* 5728 * We need one SCB to serve as the "next SCB". Since the 5729 * tag identifier in this SCB will never be used, there is 5730 * no point in using a valid HSCB tag from an SCB pulled from 5731 * the standard free pool. So, we allocate this "sentinel" 5732 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5733 */ 5734 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5735 ahd->next_queued_hscb_map = &ahd->shared_data_map; 5736 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 5737 5738 memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 5739 5740 /* Allocate SCB data now that parent_dmat is initialized */ 5741 if (ahd_init_scbdata(ahd) != 0) 5742 return (ENOMEM); 5743 5744 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5745 ahd->flags &= ~AHD_RESET_BUS_A; 5746 5747 /* 5748 * Before committing these settings to the chip, give 5749 * the OSM one last chance to modify our configuration. 5750 */ 5751 ahd_platform_init(ahd); 5752 5753 /* Bring up the chip. */ 5754 ahd_chip_init(ahd); 5755 5756 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5757 5758 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5759 goto init_done; 5760 5761 /* 5762 * Verify termination based on current draw and 5763 * warn user if the bus is over/under terminated. 5764 */ 5765 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5766 CURSENSE_ENB); 5767 if (error != 0) { 5768 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5769 goto init_done; 5770 } 5771 for (i = 20, fstat = FLX_FSTAT_BUSY; 5772 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5773 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5774 if (error != 0) { 5775 printf("%s: current sensing timeout 2\n", 5776 ahd_name(ahd)); 5777 goto init_done; 5778 } 5779 } 5780 if (i == 0) { 5781 printf("%s: Timedout during current-sensing test\n", 5782 ahd_name(ahd)); 5783 goto init_done; 5784 } 5785 5786 /* Latch Current Sensing status. */ 5787 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5788 if (error != 0) { 5789 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5790 goto init_done; 5791 } 5792 5793 /* Diable current sensing. */ 5794 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5795 5796 #ifdef AHD_DEBUG 5797 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5798 printf("%s: current_sensing == 0x%x\n", 5799 ahd_name(ahd), current_sensing); 5800 } 5801 #endif 5802 warn_user = 0; 5803 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5804 u_int term_stat; 5805 5806 term_stat = (current_sensing & FLX_CSTAT_MASK); 5807 switch (term_stat) { 5808 case FLX_CSTAT_OVER: 5809 case FLX_CSTAT_UNDER: 5810 warn_user++; 5811 case FLX_CSTAT_INVALID: 5812 case FLX_CSTAT_OKAY: 5813 if (warn_user == 0 && bootverbose == 0) 5814 break; 5815 printf("%s: %s Channel %s\n", ahd_name(ahd), 5816 channel_strings[i], termstat_strings[term_stat]); 5817 break; 5818 } 5819 } 5820 if (warn_user) { 5821 printf("%s: WARNING. Termination is not configured correctly.\n" 5822 "%s: WARNING. SCSI bus operations may FAIL.\n", 5823 ahd_name(ahd), ahd_name(ahd)); 5824 } 5825 init_done: 5826 ahd_reset_current_bus(ahd); 5827 ahd_restart(ahd); 5828 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5829 ahd_stat_timer, ahd); 5830 5831 /* We have to wait until after any system dumps... */ 5832 ahd->shutdown_hook = shutdownhook_establish(ahd_shutdown, ahd); 5833 5834 return (0); 5835 } 5836 5837 /* 5838 * (Re)initialize chip state after a chip reset. 5839 */ 5840 static void 5841 ahd_chip_init(struct ahd_softc *ahd) 5842 { 5843 uint32_t busaddr; 5844 u_int sxfrctl1; 5845 u_int scsiseq_template; 5846 u_int wait; 5847 u_int i; 5848 u_int target; 5849 5850 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5851 /* 5852 * Take the LED out of diagnostic mode 5853 */ 5854 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 5855 5856 /* 5857 * Return HS_MAILBOX to its default value. 5858 */ 5859 ahd->hs_mailbox = 0; 5860 ahd_outb(ahd, HS_MAILBOX, 0); 5861 5862 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 5863 ahd_outb(ahd, IOWNID, ahd->our_id); 5864 ahd_outb(ahd, TOWNID, ahd->our_id); 5865 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 5866 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 5867 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 5868 && (ahd->seltime != STIMESEL_MIN)) { 5869 /* 5870 * The selection timer duration is twice as long 5871 * as it should be. Halve it by adding "1" to 5872 * the user specified setting. 5873 */ 5874 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 5875 } else { 5876 sxfrctl1 |= ahd->seltime; 5877 } 5878 5879 ahd_outb(ahd, SXFRCTL0, DFON); 5880 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 5881 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5882 5883 /* 5884 * Now that termination is set, wait for up 5885 * to 500ms for our transceivers to settle. If 5886 * the adapter does not have a cable attached, 5887 * the transceivers may never settle, so don't 5888 * complain if we fail here. 5889 */ 5890 for (wait = 10000; 5891 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 5892 wait--) 5893 ahd_delay(100); 5894 5895 /* Clear any false bus resets due to the transceivers settling */ 5896 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 5897 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5898 5899 /* Initialize mode specific S/G state. */ 5900 for (i = 0; i < 2; i++) { 5901 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 5902 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 5903 ahd_outb(ahd, SG_STATE, 0); 5904 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 5905 ahd_outb(ahd, SEQIMODE, 5906 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 5907 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 5908 } 5909 5910 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5911 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 5912 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 5913 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 5914 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 5915 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 5916 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 5917 } else { 5918 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 5919 } 5920 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 5921 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 5922 /* 5923 * Do not issue a target abort when a split completion 5924 * error occurs. Let our PCIX interrupt handler deal 5925 * with it instead. H2A4 Razor #625 5926 */ 5927 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 5928 5929 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 5930 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 5931 5932 /* 5933 * Tweak IOCELL settings. 5934 */ 5935 if ((ahd->flags & AHD_HP_BOARD) != 0) { 5936 for (i = 0; i < NUMDSPS; i++) { 5937 ahd_outb(ahd, DSPSELECT, i); 5938 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 5939 } 5940 #ifdef AHD_DEBUG 5941 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5942 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 5943 WRTBIASCTL_HP_DEFAULT); 5944 #endif 5945 } 5946 ahd_setup_iocell_workaround(ahd); 5947 5948 /* 5949 * Enable LQI Manager interrupts. 5950 */ 5951 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 5952 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 5953 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 5954 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 5955 /* 5956 * An interrupt from LQOBUSFREE is made redundant by the 5957 * BUSFREE interrupt. We choose to have the sequencer catch 5958 * LQOPHCHGINPKT errors manually for the command phase at the 5959 * start of a packetized selection case. 5960 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 5961 */ 5962 ahd_outb(ahd, LQOMODE1, 0); 5963 5964 /* 5965 * Setup sequencer interrupt handlers. 5966 */ 5967 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 5968 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 5969 5970 /* 5971 * Setup SCB Offset registers. 5972 */ 5973 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 5974 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 5975 pkt_long_lun)); 5976 } else { 5977 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 5978 } 5979 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 5980 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 5981 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 5982 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 5983 shared_data.idata.cdb)); 5984 ahd_outb(ahd, QNEXTPTR, 5985 offsetof(struct hardware_scb, next_hscb_busaddr)); 5986 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 5987 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 5988 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 5989 ahd_outb(ahd, LUNLEN, 5990 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 5991 } else { 5992 ahd_outb(ahd, LUNLEN, sizeof(ahd->next_queued_hscb->lun) - 1); 5993 } 5994 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 5995 ahd_outb(ahd, MAXCMD, 0xFF); 5996 ahd_outb(ahd, SCBAUTOPTR, 5997 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 5998 5999 /* We haven't been enabled for target mode yet. */ 6000 ahd_outb(ahd, MULTARGID, 0); 6001 ahd_outb(ahd, MULTARGID + 1, 0); 6002 6003 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6004 /* Initialize the negotiation table. */ 6005 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6006 /* 6007 * Clear the spare bytes in the neg table to avoid 6008 * spurious parity errors. 6009 */ 6010 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6011 ahd_outb(ahd, NEGOADDR, target); 6012 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6013 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6014 ahd_outb(ahd, ANNEXDAT, 0); 6015 } 6016 } 6017 6018 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6019 struct ahd_devinfo devinfo; 6020 struct ahd_initiator_tinfo *tinfo; 6021 struct ahd_tmode_tstate *tstate; 6022 6023 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6024 target, &tstate); 6025 ahd_compile_devinfo(&devinfo, ahd->our_id, 6026 target, CAM_LUN_WILDCARD, 6027 'A', ROLE_INITIATOR); 6028 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6029 } 6030 6031 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6032 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6033 6034 /* 6035 * Always enable abort on incoming L_Qs if this feature is 6036 * supported. We use this to catch invalid SCB references. 6037 */ 6038 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6039 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6040 else 6041 ahd_outb(ahd, LQCTL1, 0); 6042 6043 /* All of our queues are empty */ 6044 ahd->qoutfifonext = 0; 6045 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6046 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6047 for (i = 0; i < AHD_QOUT_SIZE; i++) 6048 ahd->qoutfifo[i] = 0; 6049 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6050 6051 ahd->qinfifonext = 0; 6052 for (i = 0; i < AHD_QIN_SIZE; i++) 6053 ahd->qinfifo[i] = SCB_LIST_NULL; 6054 6055 if ((ahd->features & AHD_TARGETMODE) != 0) { 6056 /* All target command blocks start out invalid. */ 6057 for (i = 0; i < AHD_TMODE_CMDS; i++) 6058 ahd->targetcmds[i].cmd_valid = 0; 6059 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6060 ahd->tqinfifonext = 1; 6061 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6062 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6063 } 6064 6065 /* Initialize Scratch Ram. */ 6066 ahd_outb(ahd, SEQ_FLAGS, 0); 6067 ahd_outb(ahd, SEQ_FLAGS2, 0); 6068 6069 /* We don't have any waiting selections */ 6070 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6071 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6072 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6073 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6074 } 6075 6076 /* 6077 * Nobody is waiting to be DMAed into the QOUTFIFO. 6078 */ 6079 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6080 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6081 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6082 6083 /* 6084 * The Freeze Count is 0. 6085 */ 6086 ahd_outw(ahd, QFREEZE_COUNT, 0); 6087 6088 /* 6089 * Tell the sequencer where it can find our arrays in memory. 6090 */ 6091 busaddr = ahd->shared_data_map.physaddr; 6092 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6093 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6094 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6095 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6096 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6097 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6098 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6099 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6100 /* 6101 * Setup the allowed SCSI Sequences based on operational mode. 6102 * If we are a target, we'll enable select in operations once 6103 * we've had a lun enabled. 6104 */ 6105 scsiseq_template = ENAUTOATNP; 6106 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6107 scsiseq_template |= ENRSELI; 6108 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6109 6110 /* There are no busy SCBs yet. */ 6111 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6112 int lun; 6113 6114 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6115 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6116 } 6117 6118 /* 6119 * Initialize the group code to command length table. 6120 * Vendor Unique codes are set to 0 so we only capture 6121 * the first byte of the cdb. These can be overridden 6122 * when target mode is enabled. 6123 */ 6124 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6125 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6126 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6127 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6128 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6129 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6130 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6131 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6132 6133 /* Tell the sequencer of our initial queue positions */ 6134 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6135 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6136 ahd->qinfifonext = 0; 6137 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6138 ahd_set_hescb_qoff(ahd, 0); 6139 ahd_set_snscb_qoff(ahd, 0); 6140 ahd_set_sescb_qoff(ahd, 0); 6141 ahd_set_sdscb_qoff(ahd, 0); 6142 6143 /* 6144 * Tell the sequencer which SCB will be the next one it receives. 6145 */ 6146 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6147 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6148 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6149 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6150 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6151 6152 /* 6153 * Default to coalescing disabled. 6154 */ 6155 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6156 ahd_outw(ahd, CMDS_PENDING, 0); 6157 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6158 ahd->int_coalescing_maxcmds, 6159 ahd->int_coalescing_mincmds); 6160 ahd_enable_coalescing(ahd, FALSE); 6161 6162 ahd_loadseq(ahd); 6163 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6164 } 6165 6166 /* 6167 * Setup default device and controller settings. 6168 * This should only be called if our probe has 6169 * determined that no configuration data is available. 6170 */ 6171 int 6172 ahd_default_config(struct ahd_softc *ahd) 6173 { 6174 int targ; 6175 6176 ahd->our_id = 7; 6177 6178 /* 6179 * Allocate a tstate to house information for our 6180 * initiator presence on the bus as well as the user 6181 * data for any target mode initiator. 6182 */ 6183 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6184 printf("%s: unable to allocate ahd_tmode_tstate. " 6185 "Failing attach\n", ahd_name(ahd)); 6186 return (ENOMEM); 6187 } 6188 6189 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6190 struct ahd_devinfo devinfo; 6191 struct ahd_initiator_tinfo *tinfo; 6192 struct ahd_tmode_tstate *tstate; 6193 uint16_t target_mask; 6194 6195 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6196 targ, &tstate); 6197 /* 6198 * We support SPC2 and SPI4. 6199 */ 6200 tinfo->user.protocol_version = 4; 6201 tinfo->user.transport_version = 4; 6202 6203 target_mask = 0x01 << targ; 6204 ahd->user_discenable |= target_mask; 6205 tstate->discenable |= target_mask; 6206 ahd->user_tagenable |= target_mask; 6207 #ifdef AHD_FORCE_160 6208 tinfo->user.period = AHD_SYNCRATE_DT; 6209 #else 6210 tinfo->user.period = AHD_SYNCRATE_160; 6211 #endif 6212 tinfo->user.offset= MAX_OFFSET; 6213 tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6214 | MSG_EXT_PPR_WRFLOW 6215 | MSG_EXT_PPR_HOLDMCS 6216 | MSG_EXT_PPR_IU_REQ 6217 | MSG_EXT_PPR_QAS_REQ 6218 | MSG_EXT_PPR_DT_REQ; 6219 if ((ahd->features & AHD_RTI) != 0) 6220 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6221 6222 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6223 6224 /* 6225 * Start out Async/Narrow/Untagged and with 6226 * conservative protocol support. 6227 */ 6228 tinfo->goal.protocol_version = 2; 6229 tinfo->goal.transport_version = 2; 6230 tinfo->curr.protocol_version = 2; 6231 tinfo->curr.transport_version = 2; 6232 ahd_compile_devinfo(&devinfo, ahd->our_id, 6233 targ, CAM_LUN_WILDCARD, 6234 'A', ROLE_INITIATOR); 6235 tstate->tagenable &= ~target_mask; 6236 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6237 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6238 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6239 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6240 /*paused*/TRUE); 6241 } 6242 return (0); 6243 } 6244 6245 /* 6246 * Parse device configuration information. 6247 */ 6248 int 6249 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6250 { 6251 int targ; 6252 int max_targ; 6253 6254 max_targ = sc->max_targets & CFMAXTARG; 6255 ahd->our_id = sc->brtime_id & CFSCSIID; 6256 6257 /* 6258 * Allocate a tstate to house information for our 6259 * initiator presence on the bus as well as the user 6260 * data for any target mode initiator. 6261 */ 6262 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6263 printf("%s: unable to allocate ahd_tmode_tstate. " 6264 "Failing attach\n", ahd_name(ahd)); 6265 return (ENOMEM); 6266 } 6267 6268 for (targ = 0; targ < max_targ; targ++) { 6269 struct ahd_devinfo devinfo; 6270 struct ahd_initiator_tinfo *tinfo; 6271 struct ahd_transinfo *user_tinfo; 6272 struct ahd_tmode_tstate *tstate; 6273 uint16_t target_mask; 6274 6275 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6276 targ, &tstate); 6277 user_tinfo = &tinfo->user; 6278 6279 /* 6280 * We support SPC2 and SPI4. 6281 */ 6282 tinfo->user.protocol_version = 4; 6283 tinfo->user.transport_version = 4; 6284 6285 target_mask = 0x01 << targ; 6286 ahd->user_discenable &= ~target_mask; 6287 tstate->discenable &= ~target_mask; 6288 ahd->user_tagenable &= ~target_mask; 6289 if (sc->device_flags[targ] & CFDISC) { 6290 tstate->discenable |= target_mask; 6291 ahd->user_discenable |= target_mask; 6292 ahd->user_tagenable |= target_mask; 6293 } else { 6294 /* 6295 * Cannot be packetized without disconnection. 6296 */ 6297 sc->device_flags[targ] &= ~CFPACKETIZED; 6298 } 6299 6300 user_tinfo->ppr_options = 0; 6301 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6302 if (user_tinfo->period < CFXFER_ASYNC) { 6303 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6304 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6305 user_tinfo->offset = MAX_OFFSET; 6306 } else { 6307 user_tinfo->offset = 0; 6308 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6309 } 6310 #ifdef AHD_FORCE_160 6311 if (user_tinfo->period <= AHD_SYNCRATE_160) 6312 user_tinfo->period = AHD_SYNCRATE_DT; 6313 #endif 6314 6315 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6316 user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6317 | MSG_EXT_PPR_WRFLOW 6318 | MSG_EXT_PPR_HOLDMCS 6319 | MSG_EXT_PPR_IU_REQ; 6320 if ((ahd->features & AHD_RTI) != 0) 6321 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6322 } 6323 6324 if ((sc->device_flags[targ] & CFQAS) != 0) 6325 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6326 6327 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6328 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6329 else 6330 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6331 #ifdef AHD_DEBUG 6332 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6333 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6334 user_tinfo->period, user_tinfo->offset, 6335 user_tinfo->ppr_options); 6336 #endif 6337 /* 6338 * Start out Async/Narrow/Untagged and with 6339 * conservative protocol support. 6340 */ 6341 tstate->tagenable &= ~target_mask; 6342 tinfo->goal.protocol_version = 2; 6343 tinfo->goal.transport_version = 2; 6344 tinfo->curr.protocol_version = 2; 6345 tinfo->curr.transport_version = 2; 6346 ahd_compile_devinfo(&devinfo, ahd->our_id, 6347 targ, CAM_LUN_WILDCARD, 6348 'A', ROLE_INITIATOR); 6349 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6350 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6351 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6352 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6353 /*paused*/TRUE); 6354 } 6355 6356 ahd->flags &= ~AHD_SPCHK_ENB_A; 6357 if (sc->bios_control & CFSPARITY) 6358 ahd->flags |= AHD_SPCHK_ENB_A; 6359 6360 ahd->flags &= ~AHD_RESET_BUS_A; 6361 if (sc->bios_control & CFRESETB) 6362 ahd->flags |= AHD_RESET_BUS_A; 6363 6364 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6365 if (sc->bios_control & CFEXTEND) 6366 ahd->flags |= AHD_EXTENDED_TRANS_A; 6367 6368 ahd->flags &= ~AHD_BIOS_ENABLED; 6369 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6370 ahd->flags |= AHD_BIOS_ENABLED; 6371 6372 ahd->flags &= ~AHD_STPWLEVEL_A; 6373 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6374 ahd->flags |= AHD_STPWLEVEL_A; 6375 6376 return (0); 6377 } 6378 6379 /* 6380 * Parse device configuration information. 6381 */ 6382 int 6383 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6384 { 6385 int error; 6386 6387 error = ahd_verify_vpd_cksum(vpd); 6388 if (error == 0) 6389 return (EINVAL); 6390 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6391 ahd->flags |= AHD_BOOT_CHANNEL; 6392 return (0); 6393 } 6394 6395 void 6396 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6397 { 6398 u_int hcntrl; 6399 6400 hcntrl = ahd_inb(ahd, HCNTRL); 6401 hcntrl &= ~INTEN; 6402 ahd->pause &= ~INTEN; 6403 ahd->unpause &= ~INTEN; 6404 if (enable) { 6405 hcntrl |= INTEN; 6406 ahd->pause |= INTEN; 6407 ahd->unpause |= INTEN; 6408 } 6409 ahd_outb(ahd, HCNTRL, hcntrl); 6410 } 6411 6412 void 6413 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6414 u_int mincmds) 6415 { 6416 if (timer > AHD_TIMER_MAX_US) 6417 timer = AHD_TIMER_MAX_US; 6418 ahd->int_coalescing_timer = timer; 6419 6420 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6421 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6422 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6423 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6424 ahd->int_coalescing_maxcmds = maxcmds; 6425 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6426 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6427 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6428 } 6429 6430 void 6431 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 6432 { 6433 6434 ahd->hs_mailbox &= ~ENINT_COALESCE; 6435 if (enable) 6436 ahd->hs_mailbox |= ENINT_COALESCE; 6437 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6438 ahd_flush_device_writes(ahd); 6439 ahd_run_qoutfifo(ahd); 6440 } 6441 6442 /* 6443 * Ensure that the card is paused in a location 6444 * outside of all critical sections and that all 6445 * pending work is completed prior to returning. 6446 * This routine should only be called from outside 6447 * an interrupt context. 6448 */ 6449 void 6450 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6451 { 6452 u_int intstat; 6453 u_int maxloops; 6454 u_int qfreeze_cnt; 6455 6456 maxloops = 1000; 6457 ahd->flags |= AHD_ALL_INTERRUPTS; 6458 ahd_pause(ahd); 6459 /* 6460 * Increment the QFreeze Count so that the sequencer 6461 * will not start new selections. We do this only 6462 * until we are safely paused without further selections 6463 * pending. 6464 */ 6465 ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); 6466 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 6467 do { 6468 struct scb *waiting_scb; 6469 6470 ahd_unpause(ahd); 6471 ahd_intr(ahd); 6472 ahd_pause(ahd); 6473 ahd_clear_critical_section(ahd); 6474 intstat = ahd_inb(ahd, INTSTAT); 6475 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6476 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6477 ahd_outb(ahd, SCSISEQ0, 6478 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6479 /* 6480 * In the non-packetized case, the sequencer (for Rev A), 6481 * relies on ENSELO remaining set after SELDO. The hardware 6482 * auto-clears ENSELO in the packetized case. 6483 */ 6484 waiting_scb = ahd_lookup_scb(ahd, 6485 ahd_inw(ahd, WAITING_TID_HEAD)); 6486 if (waiting_scb != NULL 6487 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6488 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6489 ahd_outb(ahd, SCSISEQ0, 6490 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6491 } while (--maxloops 6492 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6493 && ((intstat & INT_PEND) != 0 6494 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 6495 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 6496 if (maxloops == 0) { 6497 printf("Infinite interrupt loop, INTSTAT = %x", 6498 ahd_inb(ahd, INTSTAT)); 6499 } 6500 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 6501 if (qfreeze_cnt == 0) { 6502 printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n", 6503 ahd_name(ahd)); 6504 } else { 6505 qfreeze_cnt--; 6506 } 6507 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 6508 if (qfreeze_cnt == 0) 6509 ahd_outb(ahd, SEQ_FLAGS2, 6510 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 6511 6512 ahd_flush_qoutfifo(ahd); 6513 6514 ahd_platform_flushwork(ahd); 6515 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6516 } 6517 6518 int 6519 ahd_suspend(struct ahd_softc *ahd) 6520 { 6521 #if 0 6522 uint8_t *ptr; 6523 int i; 6524 6525 ahd_pause_and_flushwork(ahd); 6526 6527 if (LIST_FIRST(&ahd->pending_scbs) != NULL) 6528 return (EBUSY); 6529 6530 #if AHD_TARGET_MODE 6531 /* 6532 * XXX What about ATIOs that have not yet been serviced? 6533 * Perhaps we should just refuse to be suspended if we 6534 * are acting in a target role. 6535 */ 6536 if (ahd->pending_device != NULL) 6537 return (EBUSY); 6538 #endif 6539 6540 /* Save volatile registers */ 6541 ahd->suspend_state.channel[0].scsiseq = ahd_inb(ahd, SCSISEQ0); 6542 ahd->suspend_state.channel[0].sxfrctl0 = ahd_inb(ahd, SXFRCTL0); 6543 ahd->suspend_state.channel[0].sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 6544 ahd->suspend_state.channel[0].simode0 = ahd_inb(ahd, SIMODE0); 6545 ahd->suspend_state.channel[0].simode1 = ahd_inb(ahd, SIMODE1); 6546 ahd->suspend_state.channel[0].seltimer = ahd_inb(ahd, SELTIMER); 6547 ahd->suspend_state.channel[0].seqctl = ahd_inb(ahd, SEQCTL0); 6548 ahd->suspend_state.dscommand0 = ahd_inb(ahd, DSCOMMAND0); 6549 ahd->suspend_state.dspcistatus = ahd_inb(ahd, DSPCISTATUS); 6550 6551 if ((ahd->features & AHD_DT) != 0) { 6552 u_int sfunct; 6553 6554 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6555 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6556 ahd->suspend_state.optionmode = ahd_inb(ahd, OPTIONMODE); 6557 ahd_outb(ahd, SFUNCT, sfunct); 6558 ahd->suspend_state.crccontrol1 = ahd_inb(ahd, CRCCONTROL1); 6559 } 6560 6561 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6562 ahd->suspend_state.scbbaddr = ahd_inb(ahd, SCBBADDR); 6563 6564 if ((ahd->features & AHD_ULTRA2) != 0) 6565 ahd->suspend_state.dff_thrsh = ahd_inb(ahd, DFF_THRSH); 6566 6567 ptr = ahd->suspend_state.scratch_ram; 6568 for (i = 0; i < 64; i++) 6569 *ptr++ = ahd_inb(ahd, SRAM_BASE + i); 6570 6571 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6572 for (i = 0; i < 16; i++) 6573 *ptr++ = ahd_inb(ahd, TARG_OFFSET + i); 6574 } 6575 6576 ptr = ahd->suspend_state.btt; 6577 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6578 int j; 6579 6580 for (j = 0;j < AHD_NUM_LUNS_NONPKT; j++) { 6581 u_int tcl; 6582 6583 tcl = BUILD_TCL_RAW(i, 'A', j); 6584 *ptr = ahd_find_busy_tcl(ahd, tcl); 6585 } 6586 } 6587 ahd_shutdown(ahd); 6588 #endif 6589 return (0); 6590 } 6591 6592 int 6593 ahd_resume(struct ahd_softc *ahd) 6594 { 6595 #if 0 6596 uint8_t *ptr; 6597 int i; 6598 6599 ahd_reset(ahd); 6600 6601 ahd_build_free_scb_list(ahd); 6602 6603 /* Restore volatile registers */ 6604 ahd_outb(ahd, SCSISEQ0, ahd->suspend_state.channel[0].scsiseq); 6605 ahd_outb(ahd, SXFRCTL0, ahd->suspend_state.channel[0].sxfrctl0); 6606 ahd_outb(ahd, SXFRCTL1, ahd->suspend_state.channel[0].sxfrctl1); 6607 ahd_outb(ahd, SIMODE0, ahd->suspend_state.channel[0].simode0); 6608 ahd_outb(ahd, SIMODE1, ahd->suspend_state.channel[0].simode1); 6609 ahd_outb(ahd, SELTIMER, ahd->suspend_state.channel[0].seltimer); 6610 ahd_outb(ahd, SEQCTL0, ahd->suspend_state.channel[0].seqctl); 6611 if ((ahd->features & AHD_ULTRA2) != 0) 6612 ahd_outb(ahd, SCSIID_ULTRA2, ahd->our_id); 6613 else 6614 ahd_outb(ahd, SCSIID, ahd->our_id); 6615 6616 ahd_outb(ahd, DSCOMMAND0, ahd->suspend_state.dscommand0); 6617 ahd_outb(ahd, DSPCISTATUS, ahd->suspend_state.dspcistatus); 6618 6619 if ((ahd->features & AHD_DT) != 0) { 6620 u_int sfunct; 6621 6622 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6623 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6624 ahd_outb(ahd, OPTIONMODE, ahd->suspend_state.optionmode); 6625 ahd_outb(ahd, SFUNCT, sfunct); 6626 ahd_outb(ahd, CRCCONTROL1, ahd->suspend_state.crccontrol1); 6627 } 6628 6629 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6630 ahd_outb(ahd, SCBBADDR, ahd->suspend_state.scbbaddr); 6631 6632 if ((ahd->features & AHD_ULTRA2) != 0) 6633 ahd_outb(ahd, DFF_THRSH, ahd->suspend_state.dff_thrsh); 6634 6635 ptr = ahd->suspend_state.scratch_ram; 6636 for (i = 0; i < 64; i++) 6637 ahd_outb(ahd, SRAM_BASE + i, *ptr++); 6638 6639 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6640 for (i = 0; i < 16; i++) 6641 ahd_outb(ahd, TARG_OFFSET + i, *ptr++); 6642 } 6643 6644 ptr = ahd->suspend_state.btt; 6645 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6646 int j; 6647 6648 for (j = 0;j < AHD_NUM_LUNS; j++) { 6649 u_int tcl; 6650 6651 tcl = BUILD_TCL(i << 4, j); 6652 ahd_busy_tcl(ahd, tcl, *ptr); 6653 } 6654 } 6655 #endif 6656 return (0); 6657 } 6658 6659 /************************** Busy Target Table *********************************/ 6660 /* 6661 * Set SCBPTR to the SCB that contains the busy 6662 * table entry for TCL. Return the offset into 6663 * the SCB that contains the entry for TCL. 6664 * saved_scbid is dereferenced and set to the 6665 * scbid that should be restored once manipualtion 6666 * of the TCL entry is complete. 6667 */ 6668 static __inline u_int 6669 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6670 { 6671 /* 6672 * Index to the SCB that contains the busy entry. 6673 */ 6674 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6675 *saved_scbid = ahd_get_scbptr(ahd); 6676 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6677 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6678 6679 /* 6680 * And now calculate the SCB offset to the entry. 6681 * Each entry is 2 bytes wide, hence the 6682 * multiplication by 2. 6683 */ 6684 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6685 } 6686 6687 /* 6688 * Return the untagged transaction id for a given target/channel lun. 6689 */ 6690 u_int 6691 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6692 { 6693 u_int scbid; 6694 u_int scb_offset; 6695 u_int saved_scbptr; 6696 6697 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6698 scbid = ahd_inw_scbram(ahd, scb_offset); 6699 ahd_set_scbptr(ahd, saved_scbptr); 6700 return (scbid); 6701 } 6702 6703 void 6704 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6705 { 6706 u_int scb_offset; 6707 u_int saved_scbptr; 6708 6709 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6710 ahd_outw(ahd, scb_offset, scbid); 6711 ahd_set_scbptr(ahd, saved_scbptr); 6712 } 6713 6714 /************************** SCB and SCB queue management **********************/ 6715 int 6716 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6717 char channel, int lun, u_int tag, role_t role) 6718 { 6719 int targ = SCB_GET_TARGET(ahd, scb); 6720 char chan = SCB_GET_CHANNEL(ahd, scb); 6721 int slun = SCB_GET_LUN(scb); 6722 int match; 6723 6724 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6725 if (match != 0) 6726 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6727 if (match != 0) 6728 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6729 if (match != 0) { 6730 #if AHD_TARGET_MODE 6731 int group; 6732 6733 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6734 if (role == ROLE_INITIATOR) { 6735 match = (group != XPT_FC_GROUP_TMODE) 6736 && ((tag == SCB_GET_TAG(scb)) 6737 || (tag == SCB_LIST_NULL)); 6738 } else if (role == ROLE_TARGET) { 6739 match = (group == XPT_FC_GROUP_TMODE) 6740 && ((tag == scb->io_ctx->csio.tag_id) 6741 || (tag == SCB_LIST_NULL)); 6742 } 6743 #else /* !AHD_TARGET_MODE */ 6744 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6745 #endif /* AHD_TARGET_MODE */ 6746 } 6747 6748 return match; 6749 } 6750 6751 void 6752 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6753 { 6754 int target; 6755 char channel; 6756 int lun; 6757 6758 target = SCB_GET_TARGET(ahd, scb); 6759 lun = SCB_GET_LUN(scb); 6760 channel = SCB_GET_CHANNEL(ahd, scb); 6761 6762 ahd_search_qinfifo(ahd, target, channel, lun, 6763 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6764 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6765 6766 ahd_platform_freeze_devq(ahd, scb); 6767 } 6768 6769 void 6770 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6771 { 6772 struct scb *prev_scb; 6773 ahd_mode_state saved_modes; 6774 6775 saved_modes = ahd_save_modes(ahd); 6776 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6777 prev_scb = NULL; 6778 if (ahd_qinfifo_count(ahd) != 0) { 6779 u_int prev_tag; 6780 u_int prev_pos; 6781 6782 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6783 prev_tag = ahd->qinfifo[prev_pos]; 6784 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6785 } 6786 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6787 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6788 ahd_restore_modes(ahd, saved_modes); 6789 } 6790 6791 static void 6792 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6793 struct scb *scb) 6794 { 6795 if (prev_scb == NULL) { 6796 uint32_t busaddr; 6797 6798 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6799 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6800 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6801 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6802 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6803 } else { 6804 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6805 ahd_sync_scb(ahd, prev_scb, 6806 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6807 } 6808 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6809 ahd->qinfifonext++; 6810 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6811 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6812 } 6813 6814 static int 6815 ahd_qinfifo_count(struct ahd_softc *ahd) 6816 { 6817 u_int qinpos; 6818 u_int wrap_qinpos; 6819 u_int wrap_qinfifonext; 6820 6821 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6822 qinpos = ahd_get_snscb_qoff(ahd); 6823 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6824 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6825 if (wrap_qinfifonext >= wrap_qinpos) 6826 return (wrap_qinfifonext - wrap_qinpos); 6827 else 6828 return (wrap_qinfifonext 6829 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6830 } 6831 6832 void 6833 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6834 { 6835 struct scb *scb; 6836 ahd_mode_state saved_modes; 6837 u_int pending_cmds; 6838 6839 saved_modes = ahd_save_modes(ahd); 6840 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6841 6842 /* 6843 * Don't count any commands as outstanding that the 6844 * sequencer has already marked for completion. 6845 */ 6846 ahd_flush_qoutfifo(ahd); 6847 6848 pending_cmds = 0; 6849 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6850 pending_cmds++; 6851 } 6852 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6853 ahd_restore_modes(ahd, saved_modes); 6854 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6855 } 6856 6857 int 6858 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6859 int lun, u_int tag, role_t role, uint32_t status, 6860 ahd_search_action action) 6861 { 6862 struct scb *scb; 6863 struct scb *prev_scb; 6864 ahd_mode_state saved_modes; 6865 u_int qinstart; 6866 u_int qinpos; 6867 u_int qintail; 6868 u_int tid_next; 6869 u_int tid_prev; 6870 u_int scbid; 6871 u_int savedscbptr; 6872 uint32_t busaddr; 6873 int found; 6874 int targets; 6875 int pending_cmds; 6876 int qincount; 6877 6878 /* Must be in CCHAN mode */ 6879 saved_modes = ahd_save_modes(ahd); 6880 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6881 6882 /* 6883 * Halt any pending SCB DMA. The sequencer will reinitiate 6884 * this DMA if the qinfifo is not empty once we unpause. 6885 */ 6886 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 6887 == (CCARREN|CCSCBEN|CCSCBDIR)) { 6888 ahd_outb(ahd, CCSCBCTL, 6889 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 6890 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 6891 ; 6892 } 6893 /* Determine sequencer's position in the qinfifo. */ 6894 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 6895 qinstart = ahd_get_snscb_qoff(ahd); 6896 qinpos = AHD_QIN_WRAP(qinstart); 6897 found = 0; 6898 prev_scb = NULL; 6899 6900 pending_cmds = 0; 6901 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6902 pending_cmds++; 6903 } 6904 qincount = ahd_qinfifo_count(ahd); 6905 6906 if (action == SEARCH_PRINT) { 6907 printf("qinstart = 0x%x qinfifonext = 0x%x\n", 6908 qinstart, ahd->qinfifonext); 6909 } 6910 6911 /* 6912 * Start with an empty queue. Entries that are not chosen 6913 * for removal will be re-added to the queue as we go. 6914 */ 6915 ahd->qinfifonext = qinstart; 6916 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6917 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6918 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6919 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6920 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6921 6922 while (qinpos != qintail) { 6923 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 6924 if (scb == NULL) { 6925 panic("Loop 1\n"); 6926 } 6927 6928 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 6929 /* 6930 * We found an scb that needs to be acted on. 6931 */ 6932 found++; 6933 switch (action) { 6934 case SEARCH_COMPLETE: 6935 { 6936 cam_status ostat; 6937 cam_status cstat; 6938 6939 ostat = ahd_get_scsi_status(scb); 6940 if (ostat == CAM_REQ_INPROG) 6941 ahd_set_scsi_status(scb, status); 6942 cstat = ahd_get_transaction_status(scb); 6943 if (cstat != CAM_REQ_CMP) 6944 ahd_freeze_scb(scb); 6945 if ((scb->flags & SCB_ACTIVE) == 0) 6946 printf("Inactive SCB in qinfifo\n"); 6947 if (scb->xs->error != CAM_REQ_CMP) 6948 printf("SEARCH_COMPLETE(0x%x): ostat 0x%x, cstat 0x%x, xs_error 0x%x\n", 6949 SCB_GET_TAG(scb), ostat, cstat, scb->xs->error); 6950 ahd_done(ahd, scb); 6951 6952 /* FALLTHROUGH */ 6953 } 6954 case SEARCH_REMOVE: 6955 break; 6956 case SEARCH_PRINT: 6957 printf(" 0x%x", ahd->qinfifo[qinpos]); 6958 /* FALLTHROUGH */ 6959 case SEARCH_COUNT: 6960 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6961 prev_scb = scb; 6962 break; 6963 } 6964 } else { 6965 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6966 prev_scb = scb; 6967 } 6968 qinpos = AHD_QIN_WRAP(qinpos+1); 6969 } 6970 6971 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6972 6973 if (action == SEARCH_PRINT) 6974 printf("\nWAITING_TID_QUEUES:\n"); 6975 6976 /* 6977 * Search waiting for selection lists. We traverse the 6978 * list of "their ids" waiting for selection and, if 6979 * appropriate, traverse the SCBs of each "their id" 6980 * looking for matches. 6981 */ 6982 savedscbptr = ahd_get_scbptr(ahd); 6983 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 6984 tid_prev = SCB_LIST_NULL; 6985 targets = 0; 6986 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 6987 u_int tid_head; 6988 6989 /* 6990 * We limit based on the number of SCBs since 6991 * MK_MESSAGE SCBs are not in the per-tid lists. 6992 */ 6993 targets++; 6994 if (targets > AHD_SCB_MAX) { 6995 panic("TID LIST LOOP"); 6996 } 6997 if (scbid >= ahd->scb_data.numscbs) { 6998 printf("%s: Waiting TID List inconsistency. " 6999 "SCB index == 0x%x, yet numscbs == 0x%x.", 7000 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7001 ahd_dump_card_state(ahd); 7002 panic("for safety"); 7003 } 7004 scb = ahd_lookup_scb(ahd, scbid); 7005 if (scb == NULL) { 7006 printf("%s: SCB = 0x%x Not Active!\n", 7007 ahd_name(ahd), scbid); 7008 panic("Waiting TID List traversal\n"); 7009 break; 7010 } 7011 ahd_set_scbptr(ahd, scbid); 7012 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7013 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7014 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7015 tid_prev = scbid; 7016 continue; 7017 } 7018 7019 /* 7020 * We found a list of scbs that needs to be searched. 7021 */ 7022 if (action == SEARCH_PRINT) 7023 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7024 tid_head = scbid; 7025 found += ahd_search_scb_list(ahd, target, channel, 7026 lun, tag, role, status, 7027 action, &tid_head, 7028 SCB_GET_TARGET(ahd, scb)); 7029 if (tid_head != scbid) 7030 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7031 if (!SCBID_IS_NULL(tid_head)) 7032 tid_prev = tid_head; 7033 if (action == SEARCH_PRINT) 7034 printf(")\n"); 7035 } 7036 ahd_set_scbptr(ahd, savedscbptr); 7037 ahd_restore_modes(ahd, saved_modes); 7038 return (found); 7039 } 7040 7041 static int 7042 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7043 int lun, u_int tag, role_t role, uint32_t status, 7044 ahd_search_action action, u_int *list_head, u_int tid) 7045 { 7046 struct scb *scb; 7047 u_int scbid; 7048 u_int next; 7049 u_int prev; 7050 int found; 7051 7052 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7053 found = 0; 7054 prev = SCB_LIST_NULL; 7055 next = *list_head; 7056 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7057 if (scbid >= ahd->scb_data.numscbs) { 7058 printf("%s:SCB List inconsistency. " 7059 "SCB == 0x%x, yet numscbs == 0x%x.", 7060 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7061 ahd_dump_card_state(ahd); 7062 panic("for safety"); 7063 } 7064 scb = ahd_lookup_scb(ahd, scbid); 7065 if (scb == NULL) { 7066 printf("%s: SCB = %d Not Active!\n", 7067 ahd_name(ahd), scbid); 7068 panic("Waiting List traversal\n"); 7069 } 7070 ahd_set_scbptr(ahd, scbid); 7071 next = ahd_inw_scbram(ahd, SCB_NEXT); 7072 if (ahd_match_scb(ahd, scb, target, channel, 7073 lun, SCB_LIST_NULL, role) == 0) { 7074 prev = scbid; 7075 continue; 7076 } 7077 found++; 7078 switch (action) { 7079 case SEARCH_COMPLETE: 7080 { 7081 cam_status ostat; 7082 cam_status cstat; 7083 7084 ostat = ahd_get_scsi_status(scb); 7085 if (ostat == CAM_REQ_INPROG) 7086 ahd_set_scsi_status(scb, status); 7087 cstat = ahd_get_transaction_status(scb); 7088 if (cstat != CAM_REQ_CMP) 7089 ahd_freeze_scb(scb); 7090 if ((scb->flags & SCB_ACTIVE) == 0) 7091 printf("Inactive SCB in Waiting List\n"); 7092 ahd_done(ahd, scb); 7093 /* FALLTHROUGH */ 7094 } 7095 case SEARCH_REMOVE: 7096 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7097 if (prev == SCB_LIST_NULL) 7098 *list_head = next; 7099 break; 7100 case SEARCH_PRINT: 7101 printf("0x%x ", scbid); 7102 case SEARCH_COUNT: 7103 prev = scbid; 7104 break; 7105 } 7106 if (found > AHD_SCB_MAX) 7107 panic("SCB LIST LOOP"); 7108 } 7109 if (action == SEARCH_COMPLETE 7110 || action == SEARCH_REMOVE) 7111 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7112 return (found); 7113 } 7114 7115 static void 7116 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7117 u_int tid_cur, u_int tid_next) 7118 { 7119 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7120 7121 if (SCBID_IS_NULL(tid_cur)) { 7122 7123 /* Bypass current TID list */ 7124 if (SCBID_IS_NULL(tid_prev)) { 7125 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7126 } else { 7127 ahd_set_scbptr(ahd, tid_prev); 7128 ahd_outw(ahd, SCB_NEXT2, tid_next); 7129 } 7130 if (SCBID_IS_NULL(tid_next)) 7131 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7132 } else { 7133 7134 /* Stitch through tid_cur */ 7135 if (SCBID_IS_NULL(tid_prev)) { 7136 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7137 } else { 7138 ahd_set_scbptr(ahd, tid_prev); 7139 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7140 } 7141 ahd_set_scbptr(ahd, tid_cur); 7142 ahd_outw(ahd, SCB_NEXT2, tid_next); 7143 7144 if (SCBID_IS_NULL(tid_next)) 7145 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7146 } 7147 } 7148 7149 /* 7150 * Manipulate the waiting for selection list and return the 7151 * scb that follows the one that we remove. 7152 */ 7153 static u_int 7154 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7155 u_int prev, u_int next, u_int tid) 7156 { 7157 u_int tail_offset; 7158 7159 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7160 if (!SCBID_IS_NULL(prev)) { 7161 ahd_set_scbptr(ahd, prev); 7162 ahd_outw(ahd, SCB_NEXT, next); 7163 } 7164 7165 /* 7166 * SCBs that had MK_MESSAGE set in them will not 7167 * be queued to the per-target lists, so don't 7168 * blindly clear the tail pointer. 7169 */ 7170 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7171 if (SCBID_IS_NULL(next) 7172 && ahd_inw(ahd, tail_offset) == scbid) 7173 ahd_outw(ahd, tail_offset, prev); 7174 ahd_add_scb_to_free_list(ahd, scbid); 7175 return (next); 7176 } 7177 7178 /* 7179 * Add the SCB as selected by SCBPTR onto the on chip list of 7180 * free hardware SCBs. This list is empty/unused if we are not 7181 * performing SCB paging. 7182 */ 7183 static void 7184 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7185 { 7186 /* XXX Need some other mechanism to designate "free". */ 7187 /* 7188 * Invalidate the tag so that our abort 7189 * routines don't think it's active. 7190 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7191 */ 7192 } 7193 7194 /******************************** Error Handling ******************************/ 7195 /* 7196 * Abort all SCBs that match the given description (target/channel/lun/tag), 7197 * setting their status to the passed in status if the status has not already 7198 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7199 * is paused before it is called. 7200 */ 7201 int 7202 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7203 int lun, u_int tag, role_t role, uint32_t status) 7204 { 7205 struct scb *scbp; 7206 struct scb *scbp_next; 7207 u_int i, j; 7208 u_int maxtarget; 7209 u_int minlun; 7210 u_int maxlun; 7211 int found; 7212 ahd_mode_state saved_modes; 7213 7214 /* restore this when we're done */ 7215 saved_modes = ahd_save_modes(ahd); 7216 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7217 7218 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7219 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7220 7221 /* 7222 * Clean out the busy target table for any untagged commands. 7223 */ 7224 i = 0; 7225 maxtarget = 16; 7226 if (target != CAM_TARGET_WILDCARD) { 7227 i = target; 7228 if (channel == 'B') 7229 i += 8; 7230 maxtarget = i + 1; 7231 } 7232 7233 if (lun == CAM_LUN_WILDCARD) { 7234 minlun = 0; 7235 maxlun = AHD_NUM_LUNS_NONPKT; 7236 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7237 minlun = maxlun = 0; 7238 } else { 7239 minlun = lun; 7240 maxlun = lun + 1; 7241 } 7242 7243 if (role != ROLE_TARGET) { 7244 for (;i < maxtarget; i++) { 7245 for (j = minlun;j < maxlun; j++) { 7246 u_int scbid; 7247 u_int tcl; 7248 7249 tcl = BUILD_TCL_RAW(i, 'A', j); 7250 scbid = ahd_find_busy_tcl(ahd, tcl); 7251 scbp = ahd_lookup_scb(ahd, scbid); 7252 if (scbp == NULL 7253 || ahd_match_scb(ahd, scbp, target, channel, 7254 lun, tag, role) == 0) 7255 continue; 7256 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7257 } 7258 } 7259 } 7260 7261 /* 7262 * Don't abort commands that have already completed, 7263 * but haven't quite made it up to the host yet. 7264 */ 7265 ahd_flush_qoutfifo(ahd); 7266 7267 /* 7268 * Go through the pending CCB list and look for 7269 * commands for this target that are still active. 7270 * These are other tagged commands that were 7271 * disconnected when the reset occurred. 7272 */ 7273 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7274 while (scbp_next != NULL) { 7275 scbp = scbp_next; 7276 scbp_next = LIST_NEXT(scbp, pending_links); 7277 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7278 cam_status ostat; 7279 7280 ostat = ahd_get_scsi_status(scbp); 7281 if (ostat == CAM_REQ_INPROG) 7282 ahd_set_scsi_status(scbp, status); 7283 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7284 ahd_freeze_scb(scbp); 7285 if ((scbp->flags & SCB_ACTIVE) == 0) 7286 printf("Inactive SCB on pending list\n"); 7287 ahd_done(ahd, scbp); 7288 found++; 7289 } 7290 } 7291 ahd_restore_modes(ahd, saved_modes); 7292 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7293 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7294 return found; 7295 } 7296 7297 static void 7298 ahd_reset_current_bus(struct ahd_softc *ahd) 7299 { 7300 uint8_t scsiseq; 7301 7302 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7303 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7304 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7305 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7306 ahd_delay(AHD_BUSRESET_DELAY); 7307 /* Turn off the bus reset */ 7308 ahd_outb(ahd, SCSISEQ0, scsiseq); 7309 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7310 /* 7311 * 2A Razor #474 7312 * Certain chip state is not cleared for 7313 * SCSI bus resets that we initiate, so 7314 * we must reset the chip. 7315 */ 7316 ahd_delay(AHD_BUSRESET_DELAY); 7317 ahd_reset(ahd); 7318 ahd_intr_enable(ahd, /*enable*/TRUE); 7319 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7320 } 7321 7322 ahd_clear_intstat(ahd); 7323 } 7324 7325 int 7326 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7327 { 7328 struct ahd_devinfo devinfo; 7329 u_int initiator; 7330 u_int target; 7331 u_int max_scsiid; 7332 int found; 7333 u_int fifo; 7334 u_int next_fifo; 7335 7336 7337 ahd->pending_device = NULL; 7338 7339 ahd_compile_devinfo(&devinfo, 7340 CAM_TARGET_WILDCARD, 7341 CAM_TARGET_WILDCARD, 7342 CAM_LUN_WILDCARD, 7343 channel, ROLE_UNKNOWN); 7344 ahd_pause(ahd); 7345 7346 /* Make sure the sequencer is in a safe location. */ 7347 ahd_clear_critical_section(ahd); 7348 7349 #if AHD_TARGET_MODE 7350 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7351 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7352 } 7353 #endif 7354 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7355 7356 /* 7357 * Disable selections so no automatic hardware 7358 * functions will modify chip state. 7359 */ 7360 ahd_outb(ahd, SCSISEQ0, 0); 7361 ahd_outb(ahd, SCSISEQ1, 0); 7362 7363 /* 7364 * Safely shut down our DMA engines. Always start with 7365 * the FIFO that is not currently active (if any are 7366 * actively connected). 7367 */ 7368 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7369 if (next_fifo > CURRFIFO_1) 7370 /* If disconneced, arbitrarily start with FIFO1. */ 7371 next_fifo = fifo = 0; 7372 do { 7373 next_fifo ^= CURRFIFO_1; 7374 ahd_set_modes(ahd, next_fifo, next_fifo); 7375 ahd_outb(ahd, DFCNTRL, 7376 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7377 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7378 ahd_delay(10); 7379 /* 7380 * Set CURRFIFO to the now inactive channel. 7381 */ 7382 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7383 ahd_outb(ahd, DFFSTAT, next_fifo); 7384 } while (next_fifo != fifo); 7385 7386 /* 7387 * Reset the bus if we are initiating this reset 7388 */ 7389 ahd_clear_msg_state(ahd); 7390 ahd_outb(ahd, SIMODE1, 7391 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7392 7393 if (initiate_reset) 7394 ahd_reset_current_bus(ahd); 7395 7396 ahd_clear_intstat(ahd); 7397 7398 /* 7399 * Clean up all the state information for the 7400 * pending transactions on this bus. 7401 */ 7402 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7403 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7404 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7405 7406 /* 7407 * Cleanup anything left in the FIFOs. 7408 */ 7409 ahd_clear_fifo(ahd, 0); 7410 ahd_clear_fifo(ahd, 1); 7411 7412 /* 7413 * Revert to async/narrow transfers until we renegotiate. 7414 */ 7415 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7416 for (target = 0; target <= max_scsiid; target++) { 7417 7418 if (ahd->enabled_targets[target] == NULL) 7419 continue; 7420 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7421 struct ahd_devinfo devinfo; 7422 7423 ahd_compile_devinfo(&devinfo, target, initiator, 7424 CAM_LUN_WILDCARD, 7425 'A', ROLE_UNKNOWN); 7426 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7427 AHD_TRANS_CUR, /*paused*/TRUE); 7428 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7429 /*offset*/0, /*ppr_options*/0, 7430 AHD_TRANS_CUR, /*paused*/TRUE); 7431 } 7432 } 7433 7434 #ifdef AHD_TARGET_MODE 7435 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7436 7437 /* 7438 * Send an immediate notify ccb to all target more peripheral 7439 * drivers affected by this action. 7440 */ 7441 for (target = 0; target <= max_scsiid; target++) { 7442 struct ahd_tmode_tstate* tstate; 7443 u_int lun; 7444 7445 tstate = ahd->enabled_targets[target]; 7446 if (tstate == NULL) 7447 continue; 7448 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7449 struct ahd_tmode_lstate* lstate; 7450 7451 lstate = tstate->enabled_luns[lun]; 7452 if (lstate == NULL) 7453 continue; 7454 7455 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7456 EVENT_TYPE_BUS_RESET, /*arg*/0); 7457 ahd_send_lstate_events(ahd, lstate); 7458 } 7459 } 7460 #endif 7461 7462 /* Notify the XPT that a bus reset occurred */ 7463 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7464 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7465 ahd_restart(ahd); 7466 7467 /* 7468 * Freeze the SIMQ until our poller can determine that 7469 * the bus reset has really gone away. We set the initial 7470 * timer to 0 to have the check performed as soon as possible 7471 * from the timer context. 7472 */ 7473 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7474 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7475 ahd_freeze_simq(ahd); 7476 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7477 } 7478 return (found); 7479 } 7480 7481 7482 #define AHD_RESET_POLL_US 1000 7483 static void 7484 ahd_reset_poll(void *arg) 7485 { 7486 struct ahd_softc *ahd; 7487 u_int scsiseq1; 7488 u_long l; 7489 int s; 7490 7491 ahd_list_lock(&l); 7492 ahd = (void*)arg; 7493 if (ahd == NULL) { 7494 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7495 ahd_list_unlock(&l); 7496 return; 7497 } 7498 ahd_lock(ahd, &s); 7499 ahd_pause(ahd); 7500 ahd_update_modes(ahd); 7501 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7502 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7503 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7504 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7505 ahd_reset_poll, ahd); 7506 ahd_unpause(ahd); 7507 ahd_unlock(ahd, &s); 7508 ahd_list_unlock(&l); 7509 return; 7510 } 7511 7512 /* Reset is now low. Complete chip reinitialization. */ 7513 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7514 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7515 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7516 ahd_unpause(ahd); 7517 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7518 ahd_unlock(ahd, &s); 7519 ahd_release_simq(ahd); 7520 ahd_list_unlock(&l); 7521 } 7522 7523 /**************************** Statistics Processing ***************************/ 7524 static void 7525 ahd_stat_timer(void *arg) 7526 { 7527 struct ahd_softc *ahd; 7528 u_long l; 7529 int s; 7530 int enint_coal; 7531 7532 ahd_list_lock(&l); 7533 ahd = (void *)arg; 7534 if (ahd == NULL) { 7535 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7536 ahd_list_unlock(&l); 7537 return; 7538 } 7539 ahd_lock(ahd, &s); 7540 7541 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7542 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7543 enint_coal |= ENINT_COALESCE; 7544 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7545 enint_coal &= ~ENINT_COALESCE; 7546 7547 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 7548 ahd_enable_coalescing(ahd, enint_coal); 7549 #ifdef AHD_DEBUG 7550 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 7551 printf("%s: Interrupt coalescing " 7552 "now %sabled. Cmds %d\n", 7553 ahd_name(ahd), 7554 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 7555 ahd->cmdcmplt_total); 7556 #endif 7557 } 7558 7559 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7560 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7561 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7562 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7563 ahd_stat_timer, ahd); 7564 ahd_unlock(ahd, &s); 7565 ahd_list_unlock(&l); 7566 } 7567 7568 /****************************** Status Processing *****************************/ 7569 void 7570 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7571 { 7572 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7573 ahd_handle_scsi_status(ahd, scb); 7574 } else { 7575 ahd_calc_residual(ahd, scb); 7576 ahd_done(ahd, scb); 7577 } 7578 } 7579 7580 void 7581 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7582 { 7583 struct hardware_scb *hscb; 7584 u_int qfreeze_cnt; 7585 7586 /* 7587 * The sequencer freezes its select-out queue 7588 * anytime a SCSI status error occurs. We must 7589 * handle the error and decrement the QFREEZE count 7590 * to allow the sequencer to continue. 7591 */ 7592 hscb = scb->hscb; 7593 7594 /* Freeze the queue until the client sees the error. */ 7595 ahd_freeze_devq(ahd, scb); 7596 ahd_freeze_scb(scb); 7597 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7598 if (qfreeze_cnt == 0) { 7599 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7600 } else { 7601 qfreeze_cnt--; 7602 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7603 } 7604 if (qfreeze_cnt == 0) 7605 ahd_outb(ahd, SEQ_FLAGS2, 7606 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7607 7608 /* Don't want to clobber the original sense code */ 7609 if ((scb->flags & SCB_SENSE) != 0) { 7610 /* 7611 * Clear the SCB_SENSE Flag and perform 7612 * a normal command completion. 7613 */ 7614 scb->flags &= ~SCB_SENSE; 7615 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7616 ahd_done(ahd, scb); 7617 return; 7618 } 7619 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7620 ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7621 switch (hscb->shared_data.istatus.scsi_status) { 7622 case STATUS_PKT_SENSE: 7623 { 7624 struct scsi_status_iu_header *siu; 7625 7626 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7627 siu = (struct scsi_status_iu_header *)scb->sense_data; 7628 ahd_set_scsi_status(scb, siu->status); 7629 #ifdef AHD_DEBUG 7630 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7631 ahd_print_path(ahd, scb); 7632 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7633 SCB_GET_TAG(scb), siu->status); 7634 } 7635 #endif 7636 if ((siu->flags & SIU_RSPVALID) != 0) { 7637 scsipi_printaddr(scb->xs->xs_periph); 7638 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7639 printf("Unable to parse pkt_failures\n"); 7640 } else { 7641 7642 switch (SIU_PKTFAIL_CODE(siu)) { 7643 case SIU_PFC_NONE: 7644 printf("No packet failure found\n"); 7645 break; 7646 case SIU_PFC_CIU_FIELDS_INVALID: 7647 printf("Invalid Command IU Field\n"); 7648 break; 7649 case SIU_PFC_TMF_NOT_SUPPORTED: 7650 printf("TMF not supportd\n"); 7651 break; 7652 case SIU_PFC_TMF_FAILED: 7653 printf("TMF failed\n"); 7654 break; 7655 case SIU_PFC_INVALID_TYPE_CODE: 7656 printf("Invalid L_Q Type code\n"); 7657 break; 7658 case SIU_PFC_ILLEGAL_REQUEST: 7659 printf("Illegal request\n"); 7660 default: 7661 break; 7662 } 7663 } 7664 if (siu->status == SCSI_STATUS_OK) 7665 ahd_set_transaction_status(scb, CAM_REQ_CMP_ERR); 7666 } 7667 if ((siu->flags & SIU_SNSVALID) != 0) { 7668 scb->flags |= SCB_PKT_SENSE; 7669 #ifdef AHD_DEBUG 7670 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7671 printf("Sense data available (%d)\n", siu->sense_length[0]); 7672 printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7673 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7674 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+12]), 7675 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+13])); 7676 } 7677 #endif 7678 } 7679 ahd_done(ahd, scb); 7680 break; 7681 } 7682 case SCSI_STATUS_CMD_TERMINATED: 7683 case SCSI_STATUS_CHECK_COND: 7684 { 7685 struct ahd_devinfo devinfo; 7686 struct ahd_dma_seg *sg; 7687 struct scsipi_sense *sc; 7688 struct ahd_initiator_tinfo *targ_info; 7689 struct ahd_tmode_tstate *tstate; 7690 struct ahd_transinfo *tinfo; 7691 #ifdef AHD_DEBUG 7692 if (ahd_debug & AHD_SHOW_SENSE) { 7693 ahd_print_path(ahd, scb); 7694 printf("SCB %d: requests Check Status\n", 7695 SCB_GET_TAG(scb)); 7696 } 7697 #endif 7698 7699 if (ahd_perform_autosense(scb) == 0) 7700 break; 7701 7702 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7703 SCB_GET_TARGET(ahd, scb), 7704 SCB_GET_LUN(scb), 7705 SCB_GET_CHANNEL(ahd, scb), 7706 ROLE_INITIATOR); 7707 targ_info = ahd_fetch_transinfo(ahd, 7708 devinfo.channel, 7709 devinfo.our_scsiid, 7710 devinfo.target, 7711 &tstate); 7712 tinfo = &targ_info->curr; 7713 sg = scb->sg_list; 7714 sc = (struct scsipi_sense *)hscb->shared_data.idata.cdb; 7715 /* 7716 * Save off the residual if there is one. 7717 */ 7718 ahd_update_residual(ahd, scb); 7719 #ifdef AHD_DEBUG 7720 if (ahd_debug & AHD_SHOW_SENSE) { 7721 ahd_print_path(ahd, scb); 7722 printf("Sending Sense\n"); 7723 } 7724 #endif 7725 scb->sg_count = 0; 7726 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7727 ahd_get_sense_bufsize(ahd, scb), 7728 /*last*/TRUE); 7729 sc->opcode = REQUEST_SENSE; 7730 sc->byte2 = 0; 7731 sc->unused[0] = 0; 7732 sc->unused[1] = 0; 7733 sc->length = ahd_get_sense_bufsize(ahd, scb); 7734 sc->control = 0; 7735 7736 /* 7737 * We can't allow the target to disconnect. 7738 * This will be an untagged transaction and 7739 * having the target disconnect will make this 7740 * transaction indestinguishable from outstanding 7741 * tagged transactions. 7742 */ 7743 hscb->control = 0; 7744 7745 /* 7746 * This request sense could be because the 7747 * the device lost power or in some other 7748 * way has lost our transfer negotiations. 7749 * Renegotiate if appropriate. Unit attention 7750 * errors will be reported before any data 7751 * phases occur. 7752 */ 7753 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7754 ahd_update_neg_request(ahd, &devinfo, 7755 tstate, targ_info, 7756 AHD_NEG_IF_NON_ASYNC); 7757 } 7758 if (tstate->auto_negotiate & devinfo.target_mask) { 7759 hscb->control |= MK_MESSAGE; 7760 scb->flags &= 7761 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7762 scb->flags |= SCB_AUTO_NEGOTIATE; 7763 } 7764 hscb->cdb_len = sizeof(*sc); 7765 ahd_setup_data_scb(ahd, scb); 7766 scb->flags |= SCB_SENSE; 7767 ahd_queue_scb(ahd, scb); 7768 /* 7769 * Ensure we have enough time to actually 7770 * retrieve the sense. 7771 */ 7772 ahd_scb_timer_reset(scb, 5 * 1000000); 7773 break; 7774 } 7775 case SCSI_STATUS_OK: 7776 printf("%s: Interrupted for status of 0? (SCB 0x%x)\n", 7777 ahd_name(ahd), SCB_GET_TAG(scb)); 7778 /* FALLTHROUGH */ 7779 default: 7780 ahd_done(ahd, scb); 7781 break; 7782 } 7783 } 7784 7785 /* 7786 * Calculate the residual for a just completed SCB. 7787 */ 7788 void 7789 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7790 { 7791 struct hardware_scb *hscb; 7792 struct initiator_status *spkt; 7793 uint32_t sgptr; 7794 uint32_t resid_sgptr; 7795 uint32_t resid; 7796 7797 /* 7798 * 5 cases. 7799 * 1) No residual. 7800 * SG_STATUS_VALID clear in sgptr. 7801 * 2) Transferless command 7802 * 3) Never performed any transfers. 7803 * sgptr has SG_FULL_RESID set. 7804 * 4) No residual but target did not 7805 * save data pointers after the 7806 * last transfer, so sgptr was 7807 * never updated. 7808 * 5) We have a partial residual. 7809 * Use residual_sgptr to determine 7810 * where we are. 7811 */ 7812 7813 hscb = scb->hscb; 7814 sgptr = ahd_le32toh(hscb->sgptr); 7815 if ((sgptr & SG_STATUS_VALID) == 0) 7816 /* Case 1 */ 7817 return; 7818 sgptr &= ~SG_STATUS_VALID; 7819 7820 if ((sgptr & SG_LIST_NULL) != 0) 7821 /* Case 2 */ 7822 return; 7823 7824 /* 7825 * Residual fields are the same in both 7826 * target and initiator status packets, 7827 * so we can always use the initiator fields 7828 * regardless of the role for this SCB. 7829 */ 7830 spkt = &hscb->shared_data.istatus; 7831 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7832 if ((sgptr & SG_FULL_RESID) != 0) { 7833 /* Case 3 */ 7834 resid = ahd_get_transfer_length(scb); 7835 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7836 /* Case 4 */ 7837 return; 7838 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7839 ahd_print_path(ahd, scb); 7840 printf("data overrun detected Tag == 0x%x.\n", 7841 SCB_GET_TAG(scb)); 7842 ahd_freeze_devq(ahd, scb); 7843 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7844 ahd_freeze_scb(scb); 7845 return; 7846 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7847 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7848 /* NOTREACHED */ 7849 } else { 7850 struct ahd_dma_seg *sg; 7851 7852 /* 7853 * Remainder of the SG where the transfer 7854 * stopped. 7855 */ 7856 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7857 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7858 7859 /* The residual sg_ptr always points to the next sg */ 7860 sg--; 7861 7862 /* 7863 * Add up the contents of all residual 7864 * SG segments that are after the SG where 7865 * the transfer stopped. 7866 */ 7867 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7868 sg++; 7869 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7870 } 7871 } 7872 7873 if ((scb->flags & SCB_SENSE) == 0) 7874 ahd_set_residual(scb, resid); 7875 /*else 7876 ahd_set_sense_residual(scb, resid);*/ 7877 7878 #ifdef AHD_DEBUG 7879 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7880 ahd_print_path(ahd, scb); 7881 printf("Handled %sResidual of %d bytes\n", 7882 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7883 } 7884 #endif 7885 } 7886 7887 /******************************* Target Mode **********************************/ 7888 #ifdef AHD_TARGET_MODE 7889 /* 7890 * Add a target mode event to this lun's queue 7891 */ 7892 static void 7893 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 7894 u_int initiator_id, u_int event_type, u_int event_arg) 7895 { 7896 struct ahd_tmode_event *event; 7897 int pending; 7898 7899 xpt_freeze_devq(lstate->path, /*count*/1); 7900 if (lstate->event_w_idx >= lstate->event_r_idx) 7901 pending = lstate->event_w_idx - lstate->event_r_idx; 7902 else 7903 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 7904 - (lstate->event_r_idx - lstate->event_w_idx); 7905 7906 if (event_type == EVENT_TYPE_BUS_RESET 7907 || event_type == MSG_BUS_DEV_RESET) { 7908 /* 7909 * Any earlier events are irrelevant, so reset our buffer. 7910 * This has the effect of allowing us to deal with reset 7911 * floods (an external device holding down the reset line) 7912 * without losing the event that is really interesting. 7913 */ 7914 lstate->event_r_idx = 0; 7915 lstate->event_w_idx = 0; 7916 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 7917 } 7918 7919 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 7920 xpt_print_path(lstate->path); 7921 printf("immediate event %x:%x lost\n", 7922 lstate->event_buffer[lstate->event_r_idx].event_type, 7923 lstate->event_buffer[lstate->event_r_idx].event_arg); 7924 lstate->event_r_idx++; 7925 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7926 lstate->event_r_idx = 0; 7927 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 7928 } 7929 7930 event = &lstate->event_buffer[lstate->event_w_idx]; 7931 event->initiator_id = initiator_id; 7932 event->event_type = event_type; 7933 event->event_arg = event_arg; 7934 lstate->event_w_idx++; 7935 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7936 lstate->event_w_idx = 0; 7937 } 7938 7939 /* 7940 * Send any target mode events queued up waiting 7941 * for immediate notify resources. 7942 */ 7943 void 7944 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 7945 { 7946 struct ccb_hdr *ccbh; 7947 struct ccb_immed_notify *inot; 7948 7949 while (lstate->event_r_idx != lstate->event_w_idx 7950 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 7951 struct ahd_tmode_event *event; 7952 7953 event = &lstate->event_buffer[lstate->event_r_idx]; 7954 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 7955 inot = (struct ccb_immed_notify *)ccbh; 7956 switch (event->event_type) { 7957 case EVENT_TYPE_BUS_RESET: 7958 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 7959 break; 7960 default: 7961 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 7962 inot->message_args[0] = event->event_type; 7963 inot->message_args[1] = event->event_arg; 7964 break; 7965 } 7966 inot->initiator_id = event->initiator_id; 7967 inot->sense_len = 0; 7968 xpt_done((union ccb *)inot); 7969 lstate->event_r_idx++; 7970 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7971 lstate->event_r_idx = 0; 7972 } 7973 } 7974 #endif 7975 7976 /******************** Sequencer Program Patching/Download *********************/ 7977 7978 #ifdef AHD_DUMP_SEQ 7979 void 7980 ahd_dumpseq(struct ahd_softc* ahd) 7981 { 7982 int i; 7983 int max_prog; 7984 7985 max_prog = 2048; 7986 7987 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 7988 ahd_outb(ahd, PRGMCNT, 0); 7989 ahd_outb(ahd, PRGMCNT+1, 0); 7990 for (i = 0; i < max_prog; i++) { 7991 uint8_t ins_bytes[4]; 7992 7993 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 7994 printf("0x%08x\n", ins_bytes[0] << 24 7995 | ins_bytes[1] << 16 7996 | ins_bytes[2] << 8 7997 | ins_bytes[3]); 7998 } 7999 } 8000 #endif 8001 8002 static void 8003 ahd_loadseq(struct ahd_softc *ahd) 8004 { 8005 struct cs cs_table[num_critical_sections]; 8006 u_int begin_set[num_critical_sections]; 8007 u_int end_set[num_critical_sections]; 8008 struct patch *cur_patch; 8009 u_int cs_count; 8010 u_int cur_cs; 8011 u_int i; 8012 int downloaded; 8013 u_int skip_addr; 8014 u_int sg_prefetch_cnt; 8015 u_int sg_prefetch_cnt_limit; 8016 u_int sg_prefetch_align; 8017 u_int sg_size; 8018 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8019 8020 if (bootverbose) 8021 printf("%s: Downloading Sequencer Program...", 8022 ahd_name(ahd)); 8023 8024 #if DOWNLOAD_CONST_COUNT != 7 8025 #error "Download Const Mismatch" 8026 #endif 8027 /* 8028 * Start out with 0 critical sections 8029 * that apply to this firmware load. 8030 */ 8031 cs_count = 0; 8032 cur_cs = 0; 8033 memset(begin_set, 0, sizeof(begin_set)); 8034 memset(end_set, 0, sizeof(end_set)); 8035 8036 /* 8037 * Setup downloadable constant table. 8038 * 8039 * The computation for the S/G prefetch variables is 8040 * a bit complicated. We would like to always fetch 8041 * in terms of cachelined sized increments. However, 8042 * if the cacheline is not an even multiple of the 8043 * SG element size or is larger than our SG RAM, using 8044 * just the cache size might leave us with only a portion 8045 * of an SG element at the tail of a prefetch. If the 8046 * cacheline is larger than our S/G prefetch buffer less 8047 * the size of an SG element, we may round down to a cacheline 8048 * that doesn't contain any or all of the S/G of interest 8049 * within the bounds of our S/G ram. Provide variables to 8050 * the sequencer that will allow it to handle these edge 8051 * cases. 8052 */ 8053 /* Start by aligning to the nearest cacheline. */ 8054 sg_prefetch_align = ahd->pci_cachesize; 8055 if (sg_prefetch_align == 0) 8056 sg_prefetch_align = 8; 8057 /* Round down to the nearest power of 2. */ 8058 while (powerof2(sg_prefetch_align) == 0) 8059 sg_prefetch_align--; 8060 /* 8061 * If the cacheline boundary is greater than half our prefetch RAM 8062 * we risk not being able to fetch even a single complete S/G 8063 * segment if we align to that boundary. 8064 */ 8065 if (sg_prefetch_align > CCSGADDR_MAX/2) 8066 sg_prefetch_align = CCSGADDR_MAX/2; 8067 /* Start by fetching a single cacheline. */ 8068 sg_prefetch_cnt = sg_prefetch_align; 8069 /* 8070 * Increment the prefetch count by cachelines until 8071 * at least one S/G element will fit. 8072 */ 8073 sg_size = sizeof(struct ahd_dma_seg); 8074 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8075 sg_size = sizeof(struct ahd_dma64_seg); 8076 while (sg_prefetch_cnt < sg_size) 8077 sg_prefetch_cnt += sg_prefetch_align; 8078 /* 8079 * If the cacheline is not an even multiple of 8080 * the S/G size, we may only get a partial S/G when 8081 * we align. Add a cacheline if this is the case. 8082 */ 8083 if ((sg_prefetch_align % sg_size) != 0 8084 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8085 sg_prefetch_cnt += sg_prefetch_align; 8086 /* 8087 * Lastly, compute a value that the sequencer can use 8088 * to determine if the remainder of the CCSGRAM buffer 8089 * has a full S/G element in it. 8090 */ 8091 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8092 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8093 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8094 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8095 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8096 download_consts[SG_SIZEOF] = sg_size; 8097 download_consts[PKT_OVERRUN_BUFOFFSET] = 8098 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8099 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8100 cur_patch = patches; 8101 downloaded = 0; 8102 skip_addr = 0; 8103 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8104 ahd_outb(ahd, PRGMCNT, 0); 8105 ahd_outb(ahd, PRGMCNT+1, 0); 8106 8107 for (i = 0; i < sizeof(seqprog)/4; i++) { 8108 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8109 /* 8110 * Don't download this instruction as it 8111 * is in a patch that was removed. 8112 */ 8113 continue; 8114 } 8115 /* 8116 * Move through the CS table until we find a CS 8117 * that might apply to this instruction. 8118 */ 8119 for (; cur_cs < num_critical_sections; cur_cs++) { 8120 if (critical_sections[cur_cs].end <= i) { 8121 if (begin_set[cs_count] == TRUE 8122 && end_set[cs_count] == FALSE) { 8123 cs_table[cs_count].end = downloaded; 8124 end_set[cs_count] = TRUE; 8125 cs_count++; 8126 } 8127 continue; 8128 } 8129 if (critical_sections[cur_cs].begin <= i 8130 && begin_set[cs_count] == FALSE) { 8131 cs_table[cs_count].begin = downloaded; 8132 begin_set[cs_count] = TRUE; 8133 } 8134 break; 8135 } 8136 ahd_download_instr(ahd, i, download_consts); 8137 downloaded++; 8138 } 8139 8140 ahd->num_critical_sections = cs_count; 8141 if (cs_count != 0) { 8142 8143 cs_count *= sizeof(struct cs); 8144 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8145 if (ahd->critical_sections == NULL) 8146 panic("ahd_loadseq: Could not malloc"); 8147 memcpy(ahd->critical_sections, cs_table, cs_count); 8148 } 8149 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8150 8151 if (bootverbose) { 8152 printf(" %d instructions downloaded\n", downloaded); 8153 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8154 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8155 } 8156 } 8157 8158 static int 8159 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8160 u_int start_instr, u_int *skip_addr) 8161 { 8162 struct patch *cur_patch; 8163 struct patch *last_patch; 8164 u_int num_patches; 8165 8166 num_patches = sizeof(patches)/sizeof(struct patch); 8167 last_patch = &patches[num_patches]; 8168 cur_patch = *start_patch; 8169 8170 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8171 8172 if (cur_patch->patch_func(ahd) == 0) { 8173 8174 /* Start rejecting code */ 8175 *skip_addr = start_instr + cur_patch->skip_instr; 8176 cur_patch += cur_patch->skip_patch; 8177 } else { 8178 /* Accepted this patch. Advance to the next 8179 * one and wait for our intruction pointer to 8180 * hit this point. 8181 */ 8182 cur_patch++; 8183 } 8184 } 8185 8186 *start_patch = cur_patch; 8187 if (start_instr < *skip_addr) 8188 /* Still skipping */ 8189 return (0); 8190 8191 return (1); 8192 } 8193 8194 static u_int 8195 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8196 { 8197 struct patch *cur_patch; 8198 int address_offset; 8199 u_int skip_addr; 8200 u_int i; 8201 8202 address_offset = 0; 8203 cur_patch = patches; 8204 skip_addr = 0; 8205 8206 for (i = 0; i < address;) { 8207 8208 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8209 8210 if (skip_addr > i) { 8211 int end_addr; 8212 8213 end_addr = MIN(address, skip_addr); 8214 address_offset += end_addr - i; 8215 i = skip_addr; 8216 } else { 8217 i++; 8218 } 8219 } 8220 return (address - address_offset); 8221 } 8222 8223 static void 8224 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8225 { 8226 union ins_formats instr; 8227 struct ins_format1 *fmt1_ins; 8228 struct ins_format3 *fmt3_ins; 8229 u_int opcode; 8230 8231 /* 8232 * The firmware is always compiled into a little endian format. 8233 */ 8234 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8235 8236 fmt1_ins = &instr.format1; 8237 fmt3_ins = NULL; 8238 8239 /* Pull the opcode */ 8240 opcode = instr.format1.opcode; 8241 switch (opcode) { 8242 case AIC_OP_JMP: 8243 case AIC_OP_JC: 8244 case AIC_OP_JNC: 8245 case AIC_OP_CALL: 8246 case AIC_OP_JNE: 8247 case AIC_OP_JNZ: 8248 case AIC_OP_JE: 8249 case AIC_OP_JZ: 8250 { 8251 fmt3_ins = &instr.format3; 8252 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8253 /* FALLTHROUGH */ 8254 } 8255 case AIC_OP_OR: 8256 case AIC_OP_AND: 8257 case AIC_OP_XOR: 8258 case AIC_OP_ADD: 8259 case AIC_OP_ADC: 8260 case AIC_OP_BMOV: 8261 if (fmt1_ins->parity != 0) { 8262 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8263 } 8264 fmt1_ins->parity = 0; 8265 /* FALLTHROUGH */ 8266 case AIC_OP_ROL: 8267 { 8268 int i, count; 8269 8270 /* Calculate odd parity for the instruction */ 8271 for (i = 0, count = 0; i < 31; i++) { 8272 uint32_t mask; 8273 8274 mask = 0x01 << i; 8275 if ((instr.integer & mask) != 0) 8276 count++; 8277 } 8278 if ((count & 0x01) == 0) 8279 instr.format1.parity = 1; 8280 8281 /* The sequencer is a little endian cpu */ 8282 instr.integer = ahd_htole32(instr.integer); 8283 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8284 break; 8285 } 8286 default: 8287 panic("Unknown opcode encountered in seq program"); 8288 break; 8289 } 8290 } 8291 8292 static int 8293 ahd_probe_stack_size(struct ahd_softc *ahd) 8294 { 8295 int last_probe; 8296 8297 last_probe = 0; 8298 while (1) { 8299 int i; 8300 8301 /* 8302 * We avoid using 0 as a pattern to avoid 8303 * confusion if the stack implementation 8304 * "back-fills" with zeros when "poping' 8305 * entries. 8306 */ 8307 for (i = 1; i <= last_probe+1; i++) { 8308 ahd_outb(ahd, STACK, i & 0xFF); 8309 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8310 } 8311 8312 /* Verify */ 8313 for (i = last_probe+1; i > 0; i--) { 8314 u_int stack_entry; 8315 8316 stack_entry = ahd_inb(ahd, STACK) 8317 |(ahd_inb(ahd, STACK) << 8); 8318 if (stack_entry != i) 8319 goto sized; 8320 } 8321 last_probe++; 8322 } 8323 sized: 8324 return (last_probe); 8325 } 8326 8327 void 8328 ahd_dump_all_cards_state() 8329 { 8330 struct ahd_softc *list_ahd; 8331 8332 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8333 ahd_dump_card_state(list_ahd); 8334 } 8335 } 8336 8337 int 8338 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8339 const char *name, u_int address, u_int value, 8340 u_int *cur_column, u_int wrap_point) 8341 { 8342 int printed; 8343 u_int printed_mask; 8344 char line[1024]; 8345 8346 line[0] = 0; 8347 8348 if (cur_column != NULL && *cur_column >= wrap_point) { 8349 printf("\n"); 8350 *cur_column = 0; 8351 } 8352 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8353 if (table == NULL) { 8354 printed += snprintf(&line[printed], (sizeof line) - printed, 8355 " "); 8356 printf("%s", line); 8357 if (cur_column != NULL) 8358 *cur_column += printed; 8359 return (printed); 8360 } 8361 printed_mask = 0; 8362 while (printed_mask != 0xFF) { 8363 int entry; 8364 8365 for (entry = 0; entry < num_entries; entry++) { 8366 if (((value & table[entry].mask) 8367 != table[entry].value) 8368 || ((printed_mask & table[entry].mask) 8369 == table[entry].mask)) 8370 continue; 8371 printed += snprintf(&line[printed], 8372 (sizeof line) - printed, "%s%s", 8373 printed_mask == 0 ? ":(" : "|", 8374 table[entry].name); 8375 printed_mask |= table[entry].mask; 8376 8377 break; 8378 } 8379 if (entry >= num_entries) 8380 break; 8381 } 8382 if (printed_mask != 0) 8383 printed += snprintf(&line[printed], 8384 (sizeof line) - printed, ") "); 8385 else 8386 printed += snprintf(&line[printed], 8387 (sizeof line) - printed, " "); 8388 if (cur_column != NULL) 8389 *cur_column += printed; 8390 printf("%s", line); 8391 8392 return (printed); 8393 } 8394 8395 void 8396 ahd_dump_card_state(struct ahd_softc *ahd) 8397 { 8398 struct scb *scb; 8399 ahd_mode_state saved_modes; 8400 u_int dffstat; 8401 int paused; 8402 u_int scb_index; 8403 u_int saved_scb_index; 8404 u_int cur_col; 8405 int i; 8406 8407 if (ahd_is_paused(ahd)) { 8408 paused = 1; 8409 } else { 8410 paused = 0; 8411 ahd_pause(ahd); 8412 } 8413 saved_modes = ahd_save_modes(ahd); 8414 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8415 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8416 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8417 ahd_name(ahd), 8418 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8419 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8420 ahd->saved_dst_mode)); 8421 if (paused) 8422 printf("Card was paused\n"); 8423 /* 8424 * Mode independent registers. 8425 */ 8426 cur_col = 0; 8427 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8428 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8429 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8430 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8431 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8432 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8433 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8434 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8435 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8436 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8437 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8438 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8439 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8440 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8441 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8442 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8443 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8444 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8445 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8446 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8447 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8448 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8449 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8450 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8451 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8452 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8453 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8454 printf("\n"); 8455 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8456 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8457 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8458 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8459 ahd_inw(ahd, NEXTSCB)); 8460 cur_col = 0; 8461 /* QINFIFO */ 8462 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8463 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8464 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8465 saved_scb_index = ahd_get_scbptr(ahd); 8466 printf("Pending list:"); 8467 i = 0; 8468 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8469 if (i++ > AHD_SCB_MAX) 8470 break; 8471 /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8472 ahd_inb(ahd, SCB_FIFO_USE_COUNT)); 8473 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8474 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8475 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8476 } 8477 printf("\nTotal %d\n", i); 8478 8479 printf("Kernel Free SCB list: "); 8480 i = 0; 8481 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8482 struct scb *list_scb; 8483 8484 list_scb = scb; 8485 do { 8486 printf("%d ", SCB_GET_TAG(list_scb)); 8487 list_scb = LIST_NEXT(list_scb, collision_links); 8488 } while (list_scb && i++ < AHD_SCB_MAX); 8489 } 8490 8491 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8492 if (i++ > AHD_SCB_MAX) 8493 break; 8494 printf("%d ", SCB_GET_TAG(scb)); 8495 } 8496 printf("\n"); 8497 8498 printf("Sequencer Complete DMA-inprog list: "); 8499 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8500 i = 0; 8501 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8502 ahd_set_scbptr(ahd, scb_index); 8503 printf("%d ", scb_index); 8504 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8505 } 8506 printf("\n"); 8507 8508 printf("Sequencer Complete list: "); 8509 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8510 i = 0; 8511 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8512 ahd_set_scbptr(ahd, scb_index); 8513 printf("%d ", scb_index); 8514 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8515 } 8516 printf("\n"); 8517 8518 8519 printf("Sequencer DMA-Up and Complete list: "); 8520 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8521 i = 0; 8522 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8523 ahd_set_scbptr(ahd, scb_index); 8524 printf("%d ", scb_index); 8525 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8526 } 8527 printf("\n"); 8528 ahd_set_scbptr(ahd, saved_scb_index); 8529 dffstat = ahd_inb(ahd, DFFSTAT); 8530 for (i = 0; i < 2; i++) { 8531 #ifdef AHD_DEBUG 8532 struct scb *fifo_scb; 8533 #endif 8534 u_int fifo_scbptr; 8535 8536 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8537 fifo_scbptr = ahd_get_scbptr(ahd); 8538 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8539 ahd_name(ahd), i, 8540 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8541 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 8542 cur_col = 0; 8543 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8544 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8545 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8546 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8547 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8548 &cur_col, 50); 8549 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8550 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8551 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8552 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8553 if (cur_col > 50) { 8554 printf("\n"); 8555 cur_col = 0; 8556 } 8557 printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8558 ahd_inl(ahd, SHADDR+4), 8559 ahd_inl(ahd, SHADDR), 8560 (ahd_inb(ahd, SHCNT) 8561 | (ahd_inb(ahd, SHCNT + 1) << 8) 8562 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8563 printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8564 ahd_inl(ahd, HADDR+4), 8565 ahd_inl(ahd, HADDR), 8566 (ahd_inb(ahd, HCNT) 8567 | (ahd_inb(ahd, HCNT + 1) << 8) 8568 | (ahd_inb(ahd, HCNT + 2) << 16))); 8569 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8570 #ifdef AHD_DEBUG 8571 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8572 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8573 if (fifo_scb != NULL) 8574 ahd_dump_sglist(fifo_scb); 8575 } 8576 #endif 8577 } 8578 printf("\nLQIN: "); 8579 for (i = 0; i < 20; i++) 8580 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8581 printf("\n"); 8582 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8583 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8584 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8585 ahd_inb(ahd, OPTIONMODE)); 8586 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8587 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8588 ahd_inb(ahd, MAXCMDCNT)); 8589 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8590 printf("\n"); 8591 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8592 cur_col = 0; 8593 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8594 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8595 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8596 ahd_inw(ahd, DINDEX)); 8597 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8598 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8599 ahd_inw(ahd, SCB_NEXT2)); 8600 printf("CDB %x %x %x %x %x %x\n", 8601 ahd_inb(ahd, SCB_CDB_STORE), 8602 ahd_inb(ahd, SCB_CDB_STORE+1), 8603 ahd_inb(ahd, SCB_CDB_STORE+2), 8604 ahd_inb(ahd, SCB_CDB_STORE+3), 8605 ahd_inb(ahd, SCB_CDB_STORE+4), 8606 ahd_inb(ahd, SCB_CDB_STORE+5)); 8607 printf("STACK:"); 8608 for (i = 0; i < ahd->stack_size; i++) { 8609 ahd->saved_stack[i] = 8610 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8611 printf(" 0x%x", ahd->saved_stack[i]); 8612 } 8613 for (i = ahd->stack_size-1; i >= 0; i--) { 8614 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8615 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8616 } 8617 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8618 ahd_platform_dump_card_state(ahd); 8619 ahd_restore_modes(ahd, saved_modes); 8620 if (paused == 0) 8621 ahd_unpause(ahd); 8622 } 8623 8624 void 8625 ahd_dump_scbs(struct ahd_softc *ahd) 8626 { 8627 ahd_mode_state saved_modes; 8628 u_int saved_scb_index; 8629 int i; 8630 8631 saved_modes = ahd_save_modes(ahd); 8632 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8633 saved_scb_index = ahd_get_scbptr(ahd); 8634 for (i = 0; i < AHD_SCB_MAX; i++) { 8635 ahd_set_scbptr(ahd, i); 8636 printf("%3d", i); 8637 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8638 ahd_inb(ahd, SCB_CONTROL), 8639 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8640 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8641 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8642 } 8643 printf("\n"); 8644 ahd_set_scbptr(ahd, saved_scb_index); 8645 ahd_restore_modes(ahd, saved_modes); 8646 } 8647 8648 /**************************** Flexport Logic **********************************/ 8649 /* 8650 * Read count 16bit words from 16bit word address start_addr from the 8651 * SEEPROM attached to the controller, into buf, using the controller's 8652 * SEEPROM reading state machine. Optionally treat the data as a byte 8653 * stream in terms of byte order. 8654 */ 8655 int 8656 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8657 u_int start_addr, u_int count, int bytestream) 8658 { 8659 u_int cur_addr; 8660 u_int end_addr; 8661 int error; 8662 8663 /* 8664 * If we never make it through the loop even once, 8665 * we were passed invalid arguments. 8666 */ 8667 error = EINVAL; 8668 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8669 end_addr = start_addr + count; 8670 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8671 8672 ahd_outb(ahd, SEEADR, cur_addr); 8673 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8674 8675 error = ahd_wait_seeprom(ahd); 8676 if (error) { 8677 printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd)); 8678 break; 8679 } 8680 if (bytestream != 0) { 8681 uint8_t *bytestream_ptr; 8682 8683 bytestream_ptr = (uint8_t *)buf; 8684 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 8685 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 8686 } else { 8687 /* 8688 * ahd_inw() already handles machine byte order. 8689 */ 8690 *buf = ahd_inw(ahd, SEEDAT); 8691 } 8692 buf++; 8693 } 8694 return (error); 8695 } 8696 8697 /* 8698 * Write count 16bit words from buf, into SEEPROM attache to the 8699 * controller starting at 16bit word address start_addr, using the 8700 * controller's SEEPROM writing state machine. 8701 */ 8702 int 8703 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8704 u_int start_addr, u_int count) 8705 { 8706 u_int cur_addr; 8707 u_int end_addr; 8708 int error; 8709 int retval; 8710 8711 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8712 error = ENOENT; 8713 8714 /* Place the chip into write-enable mode */ 8715 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8716 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8717 error = ahd_wait_seeprom(ahd); 8718 if (error) 8719 return (error); 8720 8721 /* 8722 * Write the data. If we don't get throught the loop at 8723 * least once, the arguments were invalid. 8724 */ 8725 retval = EINVAL; 8726 end_addr = start_addr + count; 8727 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8728 ahd_outw(ahd, SEEDAT, *buf++); 8729 ahd_outb(ahd, SEEADR, cur_addr); 8730 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8731 8732 retval = ahd_wait_seeprom(ahd); 8733 if (retval) 8734 break; 8735 } 8736 8737 /* 8738 * Disable writes. 8739 */ 8740 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8741 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8742 error = ahd_wait_seeprom(ahd); 8743 if (error) 8744 return (error); 8745 return (retval); 8746 } 8747 8748 /* 8749 * Wait ~100us for the serial eeprom to satisfy our request. 8750 */ 8751 int 8752 ahd_wait_seeprom(struct ahd_softc *ahd) 8753 { 8754 int cnt; 8755 8756 cnt = 2000; 8757 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8758 ahd_delay(5); 8759 8760 if (cnt == 0) 8761 return (ETIMEDOUT); 8762 return (0); 8763 } 8764 8765 /* 8766 * Validate the two checksums in the per_channel 8767 * vital product data struct. 8768 */ 8769 int 8770 ahd_verify_vpd_cksum(struct vpd_config *vpd) 8771 { 8772 int i; 8773 int maxaddr; 8774 uint32_t checksum; 8775 uint8_t *vpdarray; 8776 8777 vpdarray = (uint8_t *)vpd; 8778 maxaddr = offsetof(struct vpd_config, vpd_checksum); 8779 checksum = 0; 8780 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 8781 checksum = checksum + vpdarray[i]; 8782 if (checksum == 0 8783 || (-checksum & 0xFF) != vpd->vpd_checksum) 8784 return (0); 8785 8786 checksum = 0; 8787 maxaddr = offsetof(struct vpd_config, checksum); 8788 for (i = offsetof(struct vpd_config, default_target_flags); 8789 i < maxaddr; i++) 8790 checksum = checksum + vpdarray[i]; 8791 if (checksum == 0 8792 || (-checksum & 0xFF) != vpd->checksum) 8793 return (0); 8794 return (1); 8795 } 8796 8797 int 8798 ahd_verify_cksum(struct seeprom_config *sc) 8799 { 8800 int i; 8801 int maxaddr; 8802 uint32_t checksum; 8803 uint16_t *scarray; 8804 8805 maxaddr = (sizeof(*sc)/2) - 1; 8806 checksum = 0; 8807 scarray = (uint16_t *)sc; 8808 8809 for (i = 0; i < maxaddr; i++) 8810 checksum = checksum + scarray[i]; 8811 if (checksum == 0 8812 || (checksum & 0xFFFF) != sc->checksum) { 8813 return (0); 8814 } else { 8815 return (1); 8816 } 8817 } 8818 8819 int 8820 ahd_acquire_seeprom(struct ahd_softc *ahd) 8821 { 8822 /* 8823 * We should be able to determine the SEEPROM type 8824 * from the flexport logic, but unfortunately not 8825 * all implementations have this logic and there is 8826 * no programatic method for determining if the logic 8827 * is present. 8828 */ 8829 8830 return (1); 8831 #if 0 8832 uint8_t seetype; 8833 int error; 8834 8835 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8836 if (error != 0 8837 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8838 return (0); 8839 return (1); 8840 #endif 8841 } 8842 8843 void 8844 ahd_release_seeprom(struct ahd_softc *ahd) 8845 { 8846 /* Currently a no-op */ 8847 } 8848 8849 int 8850 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8851 { 8852 int error; 8853 8854 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8855 if (addr > 7) 8856 panic("ahd_write_flexport: address out of range"); 8857 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8858 error = ahd_wait_flexport(ahd); 8859 if (error != 0) 8860 return (error); 8861 ahd_outb(ahd, BRDDAT, value); 8862 ahd_flush_device_writes(ahd); 8863 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8864 ahd_flush_device_writes(ahd); 8865 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8866 ahd_flush_device_writes(ahd); 8867 ahd_outb(ahd, BRDCTL, 0); 8868 ahd_flush_device_writes(ahd); 8869 return (0); 8870 } 8871 8872 int 8873 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8874 { 8875 int error; 8876 8877 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8878 if (addr > 7) 8879 panic("ahd_read_flexport: address out of range"); 8880 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8881 error = ahd_wait_flexport(ahd); 8882 if (error != 0) 8883 return (error); 8884 *value = ahd_inb(ahd, BRDDAT); 8885 ahd_outb(ahd, BRDCTL, 0); 8886 ahd_flush_device_writes(ahd); 8887 return (0); 8888 } 8889 8890 /* 8891 * Wait at most 2 seconds for flexport arbitration to succeed. 8892 */ 8893 int 8894 ahd_wait_flexport(struct ahd_softc *ahd) 8895 { 8896 int cnt; 8897 8898 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8899 cnt = 1000000 * 2 / 5; 8900 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8901 ahd_delay(5); 8902 8903 if (cnt == 0) 8904 return (ETIMEDOUT); 8905 return (0); 8906 } 8907 8908 /************************* Target Mode ****************************************/ 8909 #ifdef AHD_TARGET_MODE 8910 cam_status 8911 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8912 struct ahd_tmode_tstate **tstate, 8913 struct ahd_tmode_lstate **lstate, 8914 int notfound_failure) 8915 { 8916 8917 if ((ahd->features & AHD_TARGETMODE) == 0) 8918 return (CAM_REQ_INVALID); 8919 8920 /* 8921 * Handle the 'black hole' device that sucks up 8922 * requests to unattached luns on enabled targets. 8923 */ 8924 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8925 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8926 *tstate = NULL; 8927 *lstate = ahd->black_hole; 8928 } else { 8929 u_int max_id; 8930 8931 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8932 if (ccb->ccb_h.target_id > max_id) 8933 return (CAM_TID_INVALID); 8934 8935 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 8936 return (CAM_LUN_INVALID); 8937 8938 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 8939 *lstate = NULL; 8940 if (*tstate != NULL) 8941 *lstate = 8942 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 8943 } 8944 8945 if (notfound_failure != 0 && *lstate == NULL) 8946 return (CAM_PATH_INVALID); 8947 8948 return (CAM_REQ_CMP); 8949 } 8950 8951 void 8952 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 8953 { 8954 #if NOT_YET 8955 struct ahd_tmode_tstate *tstate; 8956 struct ahd_tmode_lstate *lstate; 8957 struct ccb_en_lun *cel; 8958 cam_status status; 8959 u_int target; 8960 u_int lun; 8961 u_int target_mask; 8962 u_long s; 8963 char channel; 8964 8965 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 8966 /*notfound_failure*/FALSE); 8967 8968 if (status != CAM_REQ_CMP) { 8969 ccb->ccb_h.status = status; 8970 return; 8971 } 8972 8973 if ((ahd->features & AHD_MULTIROLE) != 0) { 8974 u_int our_id; 8975 8976 our_id = ahd->our_id; 8977 if (ccb->ccb_h.target_id != our_id) { 8978 if ((ahd->features & AHD_MULTI_TID) != 0 8979 && (ahd->flags & AHD_INITIATORROLE) != 0) { 8980 /* 8981 * Only allow additional targets if 8982 * the initiator role is disabled. 8983 * The hardware cannot handle a re-select-in 8984 * on the initiator id during a re-select-out 8985 * on a different target id. 8986 */ 8987 status = CAM_TID_INVALID; 8988 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 8989 || ahd->enabled_luns > 0) { 8990 /* 8991 * Only allow our target id to change 8992 * if the initiator role is not configured 8993 * and there are no enabled luns which 8994 * are attached to the currently registered 8995 * scsi id. 8996 */ 8997 status = CAM_TID_INVALID; 8998 } 8999 } 9000 } 9001 9002 if (status != CAM_REQ_CMP) { 9003 ccb->ccb_h.status = status; 9004 return; 9005 } 9006 9007 /* 9008 * We now have an id that is valid. 9009 * If we aren't in target mode, switch modes. 9010 */ 9011 if ((ahd->flags & AHD_TARGETROLE) == 0 9012 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9013 u_long s; 9014 9015 printf("Configuring Target Mode\n"); 9016 ahd_lock(ahd, &s); 9017 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9018 ccb->ccb_h.status = CAM_BUSY; 9019 ahd_unlock(ahd, &s); 9020 return; 9021 } 9022 ahd->flags |= AHD_TARGETROLE; 9023 if ((ahd->features & AHD_MULTIROLE) == 0) 9024 ahd->flags &= ~AHD_INITIATORROLE; 9025 ahd_pause(ahd); 9026 ahd_loadseq(ahd); 9027 ahd_unlock(ahd, &s); 9028 } 9029 cel = &ccb->cel; 9030 target = ccb->ccb_h.target_id; 9031 lun = ccb->ccb_h.target_lun; 9032 channel = SIM_CHANNEL(ahd, sim); 9033 target_mask = 0x01 << target; 9034 if (channel == 'B') 9035 target_mask <<= 8; 9036 9037 if (cel->enable != 0) { 9038 u_int scsiseq1; 9039 9040 /* Are we already enabled?? */ 9041 if (lstate != NULL) { 9042 xpt_print_path(ccb->ccb_h.path); 9043 printf("Lun already enabled\n"); 9044 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9045 return; 9046 } 9047 9048 if (cel->grp6_len != 0 9049 || cel->grp7_len != 0) { 9050 /* 9051 * Don't (yet?) support vendor 9052 * specific commands. 9053 */ 9054 ccb->ccb_h.status = CAM_REQ_INVALID; 9055 printf("Non-zero Group Codes\n"); 9056 return; 9057 } 9058 9059 /* 9060 * Seems to be okay. 9061 * Setup our data structures. 9062 */ 9063 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9064 tstate = ahd_alloc_tstate(ahd, target, channel); 9065 if (tstate == NULL) { 9066 xpt_print_path(ccb->ccb_h.path); 9067 printf("Couldn't allocate tstate\n"); 9068 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9069 return; 9070 } 9071 } 9072 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9073 if (lstate == NULL) { 9074 xpt_print_path(ccb->ccb_h.path); 9075 printf("Couldn't allocate lstate\n"); 9076 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9077 return; 9078 } 9079 memset(lstate, 0, sizeof(*lstate)); 9080 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9081 xpt_path_path_id(ccb->ccb_h.path), 9082 xpt_path_target_id(ccb->ccb_h.path), 9083 xpt_path_lun_id(ccb->ccb_h.path)); 9084 if (status != CAM_REQ_CMP) { 9085 free(lstate, M_DEVBUF); 9086 xpt_print_path(ccb->ccb_h.path); 9087 printf("Couldn't allocate path\n"); 9088 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9089 return; 9090 } 9091 SLIST_INIT(&lstate->accept_tios); 9092 SLIST_INIT(&lstate->immed_notifies); 9093 ahd_lock(ahd, &s); 9094 ahd_pause(ahd); 9095 if (target != CAM_TARGET_WILDCARD) { 9096 tstate->enabled_luns[lun] = lstate; 9097 ahd->enabled_luns++; 9098 9099 if ((ahd->features & AHD_MULTI_TID) != 0) { 9100 u_int targid_mask; 9101 9102 targid_mask = ahd_inb(ahd, TARGID) 9103 | (ahd_inb(ahd, TARGID + 1) << 8); 9104 9105 targid_mask |= target_mask; 9106 ahd_outb(ahd, TARGID, targid_mask); 9107 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9108 9109 ahd_update_scsiid(ahd, targid_mask); 9110 } else { 9111 u_int our_id; 9112 char channel; 9113 9114 channel = SIM_CHANNEL(ahd, sim); 9115 our_id = SIM_SCSI_ID(ahd, sim); 9116 9117 /* 9118 * This can only happen if selections 9119 * are not enabled 9120 */ 9121 if (target != our_id) { 9122 u_int sblkctl; 9123 char cur_channel; 9124 int swap; 9125 9126 sblkctl = ahd_inb(ahd, SBLKCTL); 9127 cur_channel = (sblkctl & SELBUSB) 9128 ? 'B' : 'A'; 9129 if ((ahd->features & AHD_TWIN) == 0) 9130 cur_channel = 'A'; 9131 swap = cur_channel != channel; 9132 ahd->our_id = target; 9133 9134 if (swap) 9135 ahd_outb(ahd, SBLKCTL, 9136 sblkctl ^ SELBUSB); 9137 9138 ahd_outb(ahd, SCSIID, target); 9139 9140 if (swap) 9141 ahd_outb(ahd, SBLKCTL, sblkctl); 9142 } 9143 } 9144 } else 9145 ahd->black_hole = lstate; 9146 /* Allow select-in operations */ 9147 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9148 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9149 scsiseq1 |= ENSELI; 9150 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9151 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9152 scsiseq1 |= ENSELI; 9153 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9154 } 9155 ahd_unpause(ahd); 9156 ahd_unlock(ahd, &s); 9157 ccb->ccb_h.status = CAM_REQ_CMP; 9158 xpt_print_path(ccb->ccb_h.path); 9159 printf("Lun now enabled for target mode\n"); 9160 } else { 9161 struct scb *scb; 9162 int i, empty; 9163 9164 if (lstate == NULL) { 9165 ccb->ccb_h.status = CAM_LUN_INVALID; 9166 return; 9167 } 9168 9169 ahd_lock(ahd, &s); 9170 9171 ccb->ccb_h.status = CAM_REQ_CMP; 9172 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9173 struct ccb_hdr *ccbh; 9174 9175 ccbh = &scb->io_ctx->ccb_h; 9176 if (ccbh->func_code == XPT_CONT_TARGET_IO 9177 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9178 printf("CTIO pending\n"); 9179 ccb->ccb_h.status = CAM_REQ_INVALID; 9180 ahd_unlock(ahd, &s); 9181 return; 9182 } 9183 } 9184 9185 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9186 printf("ATIOs pending\n"); 9187 ccb->ccb_h.status = CAM_REQ_INVALID; 9188 } 9189 9190 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9191 printf("INOTs pending\n"); 9192 ccb->ccb_h.status = CAM_REQ_INVALID; 9193 } 9194 9195 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9196 ahd_unlock(ahd, &s); 9197 return; 9198 } 9199 9200 xpt_print_path(ccb->ccb_h.path); 9201 printf("Target mode disabled\n"); 9202 xpt_free_path(lstate->path); 9203 free(lstate, M_DEVBUF); 9204 9205 ahd_pause(ahd); 9206 /* Can we clean up the target too? */ 9207 if (target != CAM_TARGET_WILDCARD) { 9208 tstate->enabled_luns[lun] = NULL; 9209 ahd->enabled_luns--; 9210 for (empty = 1, i = 0; i < 8; i++) 9211 if (tstate->enabled_luns[i] != NULL) { 9212 empty = 0; 9213 break; 9214 } 9215 9216 if (empty) { 9217 ahd_free_tstate(ahd, target, channel, 9218 /*force*/FALSE); 9219 if (ahd->features & AHD_MULTI_TID) { 9220 u_int targid_mask; 9221 9222 targid_mask = ahd_inb(ahd, TARGID) 9223 | (ahd_inb(ahd, TARGID + 1) 9224 << 8); 9225 9226 targid_mask &= ~target_mask; 9227 ahd_outb(ahd, TARGID, targid_mask); 9228 ahd_outb(ahd, TARGID+1, 9229 (targid_mask >> 8)); 9230 ahd_update_scsiid(ahd, targid_mask); 9231 } 9232 } 9233 } else { 9234 9235 ahd->black_hole = NULL; 9236 9237 /* 9238 * We can't allow selections without 9239 * our black hole device. 9240 */ 9241 empty = TRUE; 9242 } 9243 if (ahd->enabled_luns == 0) { 9244 /* Disallow select-in */ 9245 u_int scsiseq1; 9246 9247 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9248 scsiseq1 &= ~ENSELI; 9249 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9250 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9251 scsiseq1 &= ~ENSELI; 9252 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9253 9254 if ((ahd->features & AHD_MULTIROLE) == 0) { 9255 printf("Configuring Initiator Mode\n"); 9256 ahd->flags &= ~AHD_TARGETROLE; 9257 ahd->flags |= AHD_INITIATORROLE; 9258 ahd_pause(ahd); 9259 ahd_loadseq(ahd); 9260 } 9261 } 9262 ahd_unpause(ahd); 9263 ahd_unlock(ahd, &s); 9264 } 9265 #endif 9266 } 9267 9268 static void 9269 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9270 { 9271 #if NOT_YET 9272 u_int scsiid_mask; 9273 u_int scsiid; 9274 9275 if ((ahd->features & AHD_MULTI_TID) == 0) 9276 panic("ahd_update_scsiid called on non-multitid unit\n"); 9277 9278 /* 9279 * Since we will rely on the TARGID mask 9280 * for selection enables, ensure that OID 9281 * in SCSIID is not set to some other ID 9282 * that we don't want to allow selections on. 9283 */ 9284 if ((ahd->features & AHD_ULTRA2) != 0) 9285 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9286 else 9287 scsiid = ahd_inb(ahd, SCSIID); 9288 scsiid_mask = 0x1 << (scsiid & OID); 9289 if ((targid_mask & scsiid_mask) == 0) { 9290 u_int our_id; 9291 9292 /* ffs counts from 1 */ 9293 our_id = ffs(targid_mask); 9294 if (our_id == 0) 9295 our_id = ahd->our_id; 9296 else 9297 our_id--; 9298 scsiid &= TID; 9299 scsiid |= our_id; 9300 } 9301 if ((ahd->features & AHD_ULTRA2) != 0) 9302 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9303 else 9304 ahd_outb(ahd, SCSIID, scsiid); 9305 #endif 9306 } 9307 9308 #ifdef AHD_TARGET_MODE 9309 void 9310 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9311 { 9312 struct target_cmd *cmd; 9313 9314 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9315 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9316 9317 /* 9318 * Only advance through the queue if we 9319 * have the resources to process the command. 9320 */ 9321 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9322 break; 9323 9324 cmd->cmd_valid = 0; 9325 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9326 ahd->shared_data_map.dmamap, 9327 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9328 sizeof(struct target_cmd), 9329 BUS_DMASYNC_PREREAD); 9330 ahd->tqinfifonext++; 9331 9332 /* 9333 * Lazily update our position in the target mode incoming 9334 * command queue as seen by the sequencer. 9335 */ 9336 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9337 u_int hs_mailbox; 9338 9339 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9340 hs_mailbox &= ~HOST_TQINPOS; 9341 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9342 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9343 } 9344 } 9345 } 9346 #endif 9347 9348 static int 9349 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9350 { 9351 struct ahd_tmode_tstate *tstate; 9352 struct ahd_tmode_lstate *lstate; 9353 struct ccb_accept_tio *atio; 9354 uint8_t *byte; 9355 int initiator; 9356 int target; 9357 int lun; 9358 9359 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9360 target = SCSIID_OUR_ID(cmd->scsiid); 9361 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9362 9363 byte = cmd->bytes; 9364 tstate = ahd->enabled_targets[target]; 9365 lstate = NULL; 9366 if (tstate != NULL) 9367 lstate = tstate->enabled_luns[lun]; 9368 9369 /* 9370 * Commands for disabled luns go to the black hole driver. 9371 */ 9372 if (lstate == NULL) 9373 lstate = ahd->black_hole; 9374 9375 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9376 if (atio == NULL) { 9377 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9378 /* 9379 * Wait for more ATIOs from the peripheral driver for this lun. 9380 */ 9381 return (1); 9382 } else 9383 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9384 #ifdef AHD_DEBUG 9385 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9386 printf("%s: incoming command from %d for %d:%d%s\n", 9387 ahd_name(ahd), 9388 initiator, target, lun, 9389 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9390 #endif 9391 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9392 9393 if (lstate == ahd->black_hole) { 9394 /* Fill in the wildcards */ 9395 atio->ccb_h.target_id = target; 9396 atio->ccb_h.target_lun = lun; 9397 } 9398 9399 /* 9400 * Package it up and send it off to 9401 * whomever has this lun enabled. 9402 */ 9403 atio->sense_len = 0; 9404 atio->init_id = initiator; 9405 if (byte[0] != 0xFF) { 9406 /* Tag was included */ 9407 atio->tag_action = *byte++; 9408 atio->tag_id = *byte++; 9409 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9410 } else { 9411 atio->ccb_h.flags = 0; 9412 } 9413 byte++; 9414 9415 /* Okay. Now determine the cdb size based on the command code */ 9416 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9417 case 0: 9418 atio->cdb_len = 6; 9419 break; 9420 case 1: 9421 case 2: 9422 atio->cdb_len = 10; 9423 break; 9424 case 4: 9425 atio->cdb_len = 16; 9426 break; 9427 case 5: 9428 atio->cdb_len = 12; 9429 break; 9430 case 3: 9431 default: 9432 /* Only copy the opcode. */ 9433 atio->cdb_len = 1; 9434 printf("Reserved or VU command code type encountered\n"); 9435 break; 9436 } 9437 9438 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9439 9440 atio->ccb_h.status |= CAM_CDB_RECVD; 9441 9442 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9443 /* 9444 * We weren't allowed to disconnect. 9445 * We're hanging on the bus until a 9446 * continue target I/O comes in response 9447 * to this accept tio. 9448 */ 9449 #ifdef AHD_DEBUG 9450 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9451 printf("Received Immediate Command %d:%d:%d - %p\n", 9452 initiator, target, lun, ahd->pending_device); 9453 #endif 9454 ahd->pending_device = lstate; 9455 ahd_freeze_ccb((union ccb *)atio); 9456 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9457 } 9458 xpt_done((union ccb*)atio); 9459 return (0); 9460 } 9461 9462 #endif 9463 9464 static int 9465 ahd_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 9466 bus_dma_tag_t tag; 9467 int size; 9468 int flags; 9469 bus_dmamap_t *mapp; 9470 caddr_t *vaddr; 9471 bus_addr_t *baddr; 9472 bus_dma_segment_t *seg; 9473 int *nseg; 9474 const char *myname, *what; 9475 { 9476 int error, level = 0; 9477 9478 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9479 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 9480 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9481 myname, what, error); 9482 goto out; 9483 } 9484 level++; 9485 9486 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9487 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 9488 printf("%s: failed to map DMA mem for %s, error = %d\n", 9489 myname, what, error); 9490 goto out; 9491 } 9492 level++; 9493 9494 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9495 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 9496 printf("%s: failed to create DMA map for %s, error = %d\n", 9497 myname, what, error); 9498 goto out; 9499 } 9500 level++; 9501 9502 9503 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9504 BUS_DMA_NOWAIT)) != 0) { 9505 printf("%s: failed to load DMA map for %s, error = %d\n", 9506 myname, what, error); 9507 goto out; 9508 } 9509 9510 *baddr = (*mapp)->dm_segs[0].ds_addr; 9511 9512 return 0; 9513 out: 9514 printf("ahd_createdmamem error (%d)\n", level); 9515 switch (level) { 9516 case 3: 9517 bus_dmamap_destroy(tag, *mapp); 9518 /* FALLTHROUGH */ 9519 case 2: 9520 bus_dmamem_unmap(tag, *vaddr, size); 9521 /* FALLTHROUGH */ 9522 case 1: 9523 bus_dmamem_free(tag, seg, *nseg); 9524 break; 9525 default: 9526 break; 9527 } 9528 9529 return error; 9530 } 9531 9532 static void 9533 ahd_freedmamem(tag, size, map, vaddr, seg, nseg) 9534 bus_dma_tag_t tag; 9535 int size; 9536 bus_dmamap_t map; 9537 caddr_t vaddr; 9538 bus_dma_segment_t *seg; 9539 int nseg; 9540 { 9541 9542 bus_dmamap_unload(tag, map); 9543 bus_dmamap_destroy(tag, map); 9544 bus_dmamem_unmap(tag, vaddr, size); 9545 bus_dmamem_free(tag, seg, nseg); 9546 } 9547 9548 static void 9549 ahd_update_xfer_mode(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 9550 { 9551 struct scsipi_xfer_mode xm; 9552 struct ahd_initiator_tinfo *tinfo; 9553 struct ahd_tmode_tstate *tstate; 9554 9555 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 9556 devinfo->target, &tstate); 9557 9558 xm.xm_target = devinfo->target; 9559 xm.xm_mode = 0; 9560 xm.xm_period = tinfo->curr.period; 9561 xm.xm_offset = tinfo->curr.offset; 9562 if (tinfo->curr.width == 1) 9563 xm.xm_mode |= PERIPH_CAP_WIDE16; 9564 if (tinfo->curr.period) 9565 xm.xm_mode |= PERIPH_CAP_SYNC; 9566 if (tinfo->curr.ppr_options & MSG_EXT_PPR_DT_REQ) 9567 xm.xm_mode |= PERIPH_CAP_DT; 9568 if (tstate->tagenable & devinfo->target_mask) 9569 xm.xm_mode |= PERIPH_CAP_TQING; 9570 9571 tinfo->goal.width = tinfo->curr.width; 9572 tinfo->goal.period = tinfo->curr.period; 9573 tinfo->goal.offset = tinfo->curr.offset; 9574 tinfo->goal.ppr_options = tinfo->curr.ppr_options; 9575 9576 ahd_update_neg_request(ahd, devinfo, tstate, 9577 tinfo, AHD_NEG_TO_GOAL); 9578 9579 scsipi_async_event(&ahd->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 9580 } 9581
Indexes created Mon Sep 29 21:09:56 GMT 2025