aic79xx.c revision 1.18
1 /* $NetBSD: aic79xx.c,v 1.18 2003/08/29 04:03:09 thorpej Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#199 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.21 2003/06/23 22:06:34 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 * - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.18 2003/08/29 04:03:09 thorpej Exp $"); 53 54 #include <dev/ic/aic79xx_osm.h> 55 #include <dev/ic/aic79xx_inline.h> 56 #include <dev/ic/aic7xxx_cam.h> 57 58 #include <dev/microcode/aic7xxx/aicasm.h> 59 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 60 61 62 /******************************** Globals *************************************/ 63 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 64 65 /***************************** Lookup Tables **********************************/ 66 char *ahd_chip_names[] = 67 { 68 "NONE", 69 "aic7901", 70 "aic7902", 71 "aic7901A" 72 }; 73 74 /* 75 * Hardware error codes. 76 */ 77 struct ahd_hard_error_entry { 78 uint8_t errno; 79 char *errmesg; 80 }; 81 82 static struct ahd_hard_error_entry ahd_hard_errors[] = { 83 { DSCTMOUT, "Discard Timer has timed out" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { CIOPARERR, "CIOBUS Parity Error" }, 89 }; 90 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 91 92 static struct ahd_phase_table_entry ahd_phase_table[] = 93 { 94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 96 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 97 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 98 { P_COMMAND, MSG_NOOP, "in Command phase" }, 99 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 100 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 101 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 102 { P_BUSFREE, MSG_NOOP, "while idle" }, 103 { 0, MSG_NOOP, "in unknown phase" } 104 }; 105 106 /* 107 * In most cases we only wish to itterate over real phases, so 108 * exclude the last element from the count. 109 */ 110 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 111 112 /* Our Sequencer Program */ 113 #include <dev/microcode/aic7xxx/aic79xx_seq.h> 114 115 /**************************** Function Declarations ***************************/ 116 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 117 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 118 u_int lqistat1); 119 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 120 u_int busfreetime); 121 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 122 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 123 static void ahd_force_renegotiation(struct ahd_softc *ahd, 124 struct ahd_devinfo *devinfo); 125 126 static struct ahd_tmode_tstate* 127 ahd_alloc_tstate(struct ahd_softc *ahd, 128 u_int scsi_id, char channel); 129 #ifdef AHD_TARGET_MODE 130 static void ahd_free_tstate(struct ahd_softc *ahd, 131 u_int scsi_id, char channel, int force); 132 #endif 133 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 134 struct ahd_initiator_tinfo *, 135 u_int *period, 136 u_int *ppr_options, 137 role_t role); 138 static void ahd_update_neg_table(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct ahd_transinfo *tinfo); 141 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 142 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo); 144 static void ahd_scb_devinfo(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo, 146 struct scb *scb); 147 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 struct scb *scb); 150 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo); 152 static void ahd_construct_sdtr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset); 155 static void ahd_construct_wdtr(struct ahd_softc *ahd, 156 struct ahd_devinfo *devinfo, 157 u_int bus_width); 158 static void ahd_construct_ppr(struct ahd_softc *ahd, 159 struct ahd_devinfo *devinfo, 160 u_int period, u_int offset, 161 u_int bus_width, u_int ppr_options); 162 static void ahd_clear_msg_state(struct ahd_softc *ahd); 163 static void ahd_handle_message_phase(struct ahd_softc *ahd); 164 typedef enum { 165 AHDMSG_1B, 166 AHDMSG_2B, 167 AHDMSG_EXT 168 } ahd_msgtype; 169 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 170 u_int msgval, int full); 171 static int ahd_parse_msg(struct ahd_softc *ahd, 172 struct ahd_devinfo *devinfo); 173 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo); 175 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 176 struct ahd_devinfo *devinfo); 177 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 178 static void ahd_handle_devreset(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 u_int lun, cam_status status, 181 char *message, int verbose_level); 182 #if AHD_TARGET_MODE 183 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 184 struct ahd_devinfo *devinfo, 185 struct scb *scb); 186 #endif 187 188 static u_int ahd_sglist_size(struct ahd_softc *ahd); 189 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 190 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 191 static int ahd_init_scbdata(struct ahd_softc *ahd); 192 static void ahd_fini_scbdata(struct ahd_softc *ahd); 193 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 194 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 195 static void ahd_add_col_list(struct ahd_softc *ahd, 196 struct scb *scb, u_int col_idx); 197 static void ahd_rem_col_list(struct ahd_softc *ahd, 198 struct scb *scb); 199 static void ahd_chip_init(struct ahd_softc *ahd); 200 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 201 struct scb *prev_scb, 202 struct scb *scb); 203 static int ahd_qinfifo_count(struct ahd_softc *ahd); 204 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 205 char channel, int lun, u_int tag, 206 role_t role, uint32_t status, 207 ahd_search_action action, 208 u_int *list_head, u_int tid); 209 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 210 u_int tid_prev, u_int tid_cur, 211 u_int tid_next); 212 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 213 u_int scbid); 214 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 215 u_int prev, u_int next, u_int tid); 216 static void ahd_reset_current_bus(struct ahd_softc *ahd); 217 static ahd_callback_t ahd_reset_poll; 218 static ahd_callback_t ahd_stat_timer; 219 #ifdef AHD_DUMP_SEQ 220 static void ahd_dumpseq(struct ahd_softc *ahd); 221 #endif 222 static void ahd_loadseq(struct ahd_softc *ahd); 223 static int ahd_check_patch(struct ahd_softc *ahd, 224 struct patch **start_patch, 225 u_int start_instr, u_int *skip_addr); 226 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 227 u_int address); 228 static void ahd_download_instr(struct ahd_softc *ahd, 229 u_int instrptr, uint8_t *dconsts); 230 static int ahd_probe_stack_size(struct ahd_softc *ahd); 231 #ifdef AHD_TARGET_MODE 232 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 233 struct ahd_tmode_lstate *lstate, 234 u_int initiator_id, 235 u_int event_type, 236 u_int event_arg); 237 static void ahd_update_scsiid(struct ahd_softc *ahd, 238 u_int targid_mask); 239 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 240 struct target_cmd *cmd); 241 #endif 242 243 /************************** Added for porting to NetBSD ***********************/ 244 static int ahd_createdmamem(bus_dma_tag_t tag, 245 int size, 246 int flags, 247 bus_dmamap_t *mapp, 248 caddr_t *vaddr, 249 bus_addr_t *baddr, 250 bus_dma_segment_t *seg, 251 int *nseg, 252 const char *myname, const char *what); 253 254 static void ahd_freedmamem(bus_dma_tag_t tag, 255 int size, 256 bus_dmamap_t map, 257 caddr_t vaddr, 258 bus_dma_segment_t *seg, 259 int nseg); 260 static void ahd_update_xfer_mode(struct ahd_softc *ahc, 261 struct ahd_devinfo *devinfo); 262 263 /******************************** Private Inlines *****************************/ 264 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 265 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 266 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 267 268 static __inline void 269 ahd_assert_atn(struct ahd_softc *ahd) 270 { 271 ahd_outb(ahd, SCSISIGO, ATNO); 272 } 273 274 /* 275 * Determine if the current connection has a packetized 276 * agreement. This does not necessarily mean that we 277 * are currently in a packetized transfer. We could 278 * just as easily be sending or receiving a message. 279 */ 280 static __inline int 281 ahd_currently_packetized(struct ahd_softc *ahd) 282 { 283 ahd_mode_state saved_modes; 284 int packetized; 285 286 saved_modes = ahd_save_modes(ahd); 287 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 288 /* 289 * The packetized bit refers to the last 290 * connection, not the current one. Check 291 * for non-zero LQISTATE instead. 292 */ 293 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 294 packetized = ahd_inb(ahd, LQISTATE) != 0; 295 } else { 296 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 297 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 298 } 299 ahd_restore_modes(ahd, saved_modes); 300 return (packetized); 301 } 302 303 static __inline int 304 ahd_set_active_fifo(struct ahd_softc *ahd) 305 { 306 u_int active_fifo; 307 308 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 309 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 310 switch (active_fifo) { 311 case 0: 312 case 1: 313 ahd_set_modes(ahd, active_fifo, active_fifo); 314 return (1); 315 default: 316 return (0); 317 } 318 } 319 320 /************************* Sequencer Execution Control ************************/ 321 /* 322 * Restart the sequencer program from address zero 323 */ 324 void 325 ahd_restart(struct ahd_softc *ahd) 326 { 327 328 ahd_pause(ahd); 329 330 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 331 332 /* No more pending messages */ 333 ahd_clear_msg_state(ahd); 334 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 335 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 336 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 337 ahd_outb(ahd, SEQINTCTL, 0); 338 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 339 ahd_outb(ahd, SEQ_FLAGS, 0); 340 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 341 ahd_outb(ahd, SAVED_LUN, 0xFF); 342 343 /* 344 * Ensure that the sequencer's idea of TQINPOS 345 * matches our own. The sequencer increments TQINPOS 346 * only after it sees a DMA complete and a reset could 347 * occur before the increment leaving the kernel to believe 348 * the command arrived but the sequencer to not. 349 */ 350 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 351 352 /* Always allow reselection */ 353 ahd_outb(ahd, SCSISEQ1, 354 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 355 /* Ensure that no DMA operations are in progress */ 356 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 357 ahd_outb(ahd, SCBHCNT, 0); 358 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 359 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 360 ahd_unpause(ahd); 361 } 362 363 void 364 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 365 { 366 ahd_mode_state saved_modes; 367 368 #ifdef AHD_DEBUG 369 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 370 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 371 #endif 372 saved_modes = ahd_save_modes(ahd); 373 ahd_set_modes(ahd, fifo, fifo); 374 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 375 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 376 ahd_outb(ahd, CCSGCTL, CCSGRESET); 377 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 378 ahd_outb(ahd, SG_STATE, 0); 379 ahd_restore_modes(ahd, saved_modes); 380 } 381 382 /************************* Input/Output Queues ********************************/ 383 /* 384 * Flush and completed commands that are sitting in the command 385 * complete queues down on the chip but have yet to be DMA'ed back up. 386 */ 387 void 388 ahd_flush_qoutfifo(struct ahd_softc *ahd) 389 { 390 struct scb *scb; 391 ahd_mode_state saved_modes; 392 u_int saved_scbptr; 393 u_int ccscbctl; 394 u_int scbid; 395 u_int next_scbid; 396 397 saved_modes = ahd_save_modes(ahd); 398 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 399 saved_scbptr = ahd_get_scbptr(ahd); 400 401 /* 402 * Wait for any inprogress DMA to complete and clear DMA state 403 * if this if for an SCB in the qinfifo. 404 */ 405 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 406 407 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 408 if ((ccscbctl & ARRDONE) != 0) 409 break; 410 } else if ((ccscbctl & CCSCBDONE) != 0) 411 break; 412 ahd_delay(200); 413 } 414 if ((ccscbctl & CCSCBDIR) != 0) 415 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 416 417 /* 418 * Complete any SCBs that just finished being 419 * DMA'ed into the qoutfifo. 420 */ 421 ahd_run_qoutfifo(ahd); 422 423 /* 424 * Manually update/complete any completed SCBs that are waiting to be 425 * DMA'ed back up to the host. 426 */ 427 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 428 while (!SCBID_IS_NULL(scbid)) { 429 uint8_t *hscb_ptr; 430 u_int i; 431 432 ahd_set_scbptr(ahd, scbid); 433 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 434 scb = ahd_lookup_scb(ahd, scbid); 435 if (scb == NULL) { 436 printf("%s: Warning - DMA-up and complete " 437 "SCB %d invalid\n", ahd_name(ahd), scbid); 438 continue; 439 } 440 hscb_ptr = (uint8_t *)scb->hscb; 441 for (i = 0; i < sizeof(struct hardware_scb); i++) 442 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 443 444 ahd_complete_scb(ahd, scb); 445 scbid = next_scbid; 446 } 447 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 448 449 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 450 while (!SCBID_IS_NULL(scbid)) { 451 452 ahd_set_scbptr(ahd, scbid); 453 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 454 scb = ahd_lookup_scb(ahd, scbid); 455 if (scb == NULL) { 456 printf("%s: Warning - Complete SCB %d invalid\n", 457 ahd_name(ahd), scbid); 458 continue; 459 } 460 461 ahd_complete_scb(ahd, scb); 462 scbid = next_scbid; 463 } 464 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 465 ahd_set_scbptr(ahd, saved_scbptr); 466 467 /* 468 * Flush the good status FIFO for compelted packetized commands. 469 */ 470 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 471 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 472 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 473 | ahd_inb(ahd, GSFIFO); 474 scb = ahd_lookup_scb(ahd, scbid); 475 if (scb == NULL) { 476 printf("%s: Warning - GSFIFO SCB %d invalid\n", 477 ahd_name(ahd), scbid); 478 continue; 479 } 480 ahd_complete_scb(ahd, scb); 481 } 482 483 /* 484 * Restore state. 485 */ 486 ahd_restore_modes(ahd, saved_modes); 487 ahd->flags |= AHD_UPDATE_PEND_CMDS; 488 } 489 490 void 491 ahd_run_qoutfifo(struct ahd_softc *ahd) 492 { 493 struct scb *scb; 494 u_int scb_index; 495 496 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 497 panic("ahd_run_qoutfifo recursion"); 498 ahd->flags |= AHD_RUNNING_QOUTFIFO; 499 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 500 while ((ahd->qoutfifo[ahd->qoutfifonext] 501 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 502 503 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 504 & ~QOUTFIFO_ENTRY_VALID_LE); 505 scb = ahd_lookup_scb(ahd, scb_index); 506 if (scb == NULL) { 507 printf("%s: WARNING no command for scb %d " 508 "(cmdcmplt)\nQOUTPOS = %d\n", 509 ahd_name(ahd), scb_index, 510 ahd->qoutfifonext); 511 ahd_dump_card_state(ahd); 512 } else 513 ahd_complete_scb(ahd, scb); 514 515 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 516 if (ahd->qoutfifonext == 0) 517 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 518 } 519 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 520 } 521 522 /************************* Interrupt Handling *********************************/ 523 void 524 ahd_handle_hwerrint(struct ahd_softc *ahd) 525 { 526 /* 527 * Some catastrophic hardware error has occurred. 528 * Print it for the user and disable the controller. 529 */ 530 int i; 531 int error; 532 533 error = ahd_inb(ahd, ERROR); 534 for (i = 0; i < num_errors; i++) { 535 if ((error & ahd_hard_errors[i].errno) != 0) 536 printf("%s: hwerrint, %s\n", 537 ahd_name(ahd), ahd_hard_errors[i].errmesg); 538 } 539 540 ahd_dump_card_state(ahd); 541 panic("BRKADRINT"); 542 543 /* Tell everyone that this HBA is no longer available */ 544 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 545 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 546 CAM_NO_HBA); 547 548 /* Tell the system that this controller has gone away. */ 549 ahd_free(ahd); 550 } 551 552 void 553 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 554 { 555 u_int seqintcode; 556 557 /* 558 * Save the sequencer interrupt code and clear the SEQINT 559 * bit. We will unpause the sequencer, if appropriate, 560 * after servicing the request. 561 */ 562 seqintcode = ahd_inb(ahd, SEQINTCODE); 563 ahd_outb(ahd, CLRINT, CLRSEQINT); 564 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 565 /* 566 * Unpause the sequencer and let it clear 567 * SEQINT by writing NO_SEQINT to it. This 568 * will cause the sequencer to be paused again, 569 * which is the expected state of this routine. 570 */ 571 ahd_unpause(ahd); 572 while (!ahd_is_paused(ahd)) 573 ; 574 ahd_outb(ahd, CLRINT, CLRSEQINT); 575 } 576 ahd_update_modes(ahd); 577 #ifdef AHD_DEBUG 578 if ((ahd_debug & AHD_SHOW_MISC) != 0) 579 printf("%s: Handle Seqint Called for code %d\n", 580 ahd_name(ahd), seqintcode); 581 #endif 582 switch (seqintcode) { 583 case BAD_SCB_STATUS: 584 { 585 struct scb *scb; 586 u_int scbid; 587 int cmds_pending; 588 589 scbid = ahd_get_scbptr(ahd); 590 scb = ahd_lookup_scb(ahd, scbid); 591 if (scb != NULL) { 592 ahd_complete_scb(ahd, scb); 593 } else { 594 printf("%s: WARNING no command for scb %d " 595 "(bad status)\n", ahd_name(ahd), scbid); 596 ahd_dump_card_state(ahd); 597 } 598 cmds_pending = ahd_inw(ahd, CMDS_PENDING); 599 if (cmds_pending > 0) 600 ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); 601 break; 602 } 603 case ENTERING_NONPACK: 604 { 605 struct scb *scb; 606 u_int scbid; 607 608 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 609 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 610 scbid = ahd_get_scbptr(ahd); 611 scb = ahd_lookup_scb(ahd, scbid); 612 if (scb == NULL) { 613 /* 614 * Somehow need to know if this 615 * is from a selection or reselection. 616 * From that, we can termine target 617 * ID so we at least have an I_T nexus. 618 */ 619 } else { 620 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 621 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 622 ahd_outb(ahd, SEQ_FLAGS, 0x0); 623 } 624 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 625 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 626 /* 627 * Phase change after read stream with 628 * CRC error with P0 asserted on last 629 * packet. 630 */ 631 #ifdef AHD_DEBUG 632 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 633 printf("%s: Assuming LQIPHASE_NLQ with " 634 "P0 assertion\n", ahd_name(ahd)); 635 #endif 636 } 637 #ifdef AHD_DEBUG 638 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 639 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 640 #endif 641 break; 642 } 643 case INVALID_SEQINT: 644 printf("%s: Invalid Sequencer interrupt occurred.\n", 645 ahd_name(ahd)); 646 ahd_dump_card_state(ahd); 647 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 648 break; 649 case STATUS_OVERRUN: 650 { 651 struct scb *scb; 652 u_int scbid; 653 654 scbid = ahd_get_scbptr(ahd); 655 scb = ahd_lookup_scb(ahd, scbid); 656 if (scb != NULL) 657 ahd_print_path(ahd, scb); 658 else 659 printf("%s: ", ahd_name(ahd)); 660 printf("SCB %d Packetized Status Overrun", scbid); 661 ahd_dump_card_state(ahd); 662 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 663 break; 664 } 665 case CFG4ISTAT_INTR: 666 { 667 struct scb *scb; 668 u_int scbid; 669 670 scbid = ahd_get_scbptr(ahd); 671 scb = ahd_lookup_scb(ahd, scbid); 672 if (scb == NULL) { 673 ahd_dump_card_state(ahd); 674 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 675 panic("For safety"); 676 } 677 ahd_outq(ahd, HADDR, scb->sense_busaddr); 678 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 679 ahd_outb(ahd, HCNT + 2, 0); 680 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 681 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 682 break; 683 } 684 case ILLEGAL_PHASE: 685 { 686 u_int bus_phase; 687 688 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 689 printf("%s: ILLEGAL_PHASE 0x%x\n", 690 ahd_name(ahd), bus_phase); 691 692 switch (bus_phase) { 693 case P_DATAOUT: 694 case P_DATAIN: 695 case P_DATAOUT_DT: 696 case P_DATAIN_DT: 697 case P_MESGOUT: 698 case P_STATUS: 699 case P_MESGIN: 700 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 701 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 702 break; 703 case P_COMMAND: 704 { 705 struct ahd_devinfo devinfo; 706 struct scb *scb; 707 struct ahd_initiator_tinfo *targ_info; 708 struct ahd_tmode_tstate *tstate; 709 struct ahd_transinfo *tinfo; 710 u_int scbid; 711 712 /* 713 * If a target takes us into the command phase 714 * assume that it has been externally reset and 715 * has thus lost our previous packetized negotiation 716 * agreement. Since we have not sent an identify 717 * message and may not have fully qualified the 718 * connection, we change our command to TUR, assert 719 * ATN and ABORT the task when we go to message in 720 * phase. The OSM will see the REQUEUE_REQUEST 721 * status and retry the command. 722 */ 723 scbid = ahd_get_scbptr(ahd); 724 scb = ahd_lookup_scb(ahd, scbid); 725 if (scb == NULL) { 726 printf("Invalid phase with no valid SCB. " 727 "Resetting bus.\n"); 728 ahd_reset_channel(ahd, 'A', 729 /*Initiate Reset*/TRUE); 730 break; 731 } 732 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 733 SCB_GET_TARGET(ahd, scb), 734 SCB_GET_LUN(scb), 735 SCB_GET_CHANNEL(ahd, scb), 736 ROLE_INITIATOR); 737 targ_info = ahd_fetch_transinfo(ahd, 738 devinfo.channel, 739 devinfo.our_scsiid, 740 devinfo.target, 741 &tstate); 742 tinfo = &targ_info->curr; 743 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 744 AHD_TRANS_ACTIVE, /*paused*/TRUE); 745 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 746 /*offset*/0, /*ppr_options*/0, 747 AHD_TRANS_ACTIVE, /*paused*/TRUE); 748 ahd_outb(ahd, SCB_CDB_STORE, 0); 749 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 750 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 751 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 752 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 753 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 754 ahd_outb(ahd, SCB_CDB_LEN, 6); 755 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 756 scb->hscb->control |= MK_MESSAGE; 757 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 758 ahd_outb(ahd, MSG_OUT, HOST_MSG); 759 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 760 /* 761 * The lun is 0, regardless of the SCB's lun 762 * as we have not sent an identify message. 763 */ 764 ahd_outb(ahd, SAVED_LUN, 0); 765 ahd_outb(ahd, SEQ_FLAGS, 0); 766 ahd_assert_atn(ahd); 767 scb->flags &= ~(SCB_PACKETIZED); 768 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 769 ahd_freeze_devq(ahd, scb); 770 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 771 ahd_freeze_scb(scb); 772 773 /* 774 * Allow the sequencer to continue with 775 * non-pack processing. 776 */ 777 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 778 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 779 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 780 ahd_outb(ahd, CLRLQOINT1, 0); 781 } 782 #ifdef AHD_DEBUG 783 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 784 ahd_print_path(ahd, scb); 785 printf("Unexpected command phase from " 786 "packetized target\n"); 787 } 788 #endif 789 break; 790 } 791 } 792 break; 793 } 794 case CFG4OVERRUN: 795 { 796 struct scb *scb; 797 u_int scb_index; 798 799 #ifdef AHD_DEBUG 800 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 801 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 802 ahd_inb(ahd, MODE_PTR)); 803 } 804 #endif 805 scb_index = ahd_get_scbptr(ahd); 806 scb = ahd_lookup_scb(ahd, scb_index); 807 if (scb == NULL) { 808 /* 809 * Attempt to transfer to an SCB that is 810 * not outstanding. 811 */ 812 ahd_assert_atn(ahd); 813 ahd_outb(ahd, MSG_OUT, HOST_MSG); 814 ahd->msgout_buf[0] = MSG_ABORT_TASK; 815 ahd->msgout_len = 1; 816 ahd->msgout_index = 0; 817 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 818 /* 819 * Clear status received flag to prevent any 820 * attempt to complete this bogus SCB. 821 */ 822 ahd_outb(ahd, SCB_CONTROL, 823 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 824 } 825 break; 826 } 827 case DUMP_CARD_STATE: 828 { 829 ahd_dump_card_state(ahd); 830 break; 831 } 832 case PDATA_REINIT: 833 { 834 #ifdef AHD_DEBUG 835 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 836 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 837 "SG_CACHE_SHADOW = 0x%x\n", 838 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 839 ahd_inb(ahd, SG_CACHE_SHADOW)); 840 } 841 #endif 842 ahd_reinitialize_dataptrs(ahd); 843 break; 844 } 845 case HOST_MSG_LOOP: 846 { 847 struct ahd_devinfo devinfo; 848 849 /* 850 * The sequencer has encountered a message phase 851 * that requires host assistance for completion. 852 * While handling the message phase(s), we will be 853 * notified by the sequencer after each byte is 854 * transfered so we can track bus phase changes. 855 * 856 * If this is the first time we've seen a HOST_MSG_LOOP 857 * interrupt, initialize the state of the host message 858 * loop. 859 */ 860 ahd_fetch_devinfo(ahd, &devinfo); 861 if (ahd->msg_type == MSG_TYPE_NONE) { 862 struct scb *scb; 863 u_int scb_index; 864 u_int bus_phase; 865 866 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 867 if (bus_phase != P_MESGIN 868 && bus_phase != P_MESGOUT) { 869 printf("ahd_intr: HOST_MSG_LOOP bad " 870 "phase 0x%x\n", bus_phase); 871 /* 872 * Probably transitioned to bus free before 873 * we got here. Just punt the message. 874 */ 875 ahd_dump_card_state(ahd); 876 ahd_clear_intstat(ahd); 877 ahd_restart(ahd); 878 return; 879 } 880 881 scb_index = ahd_get_scbptr(ahd); 882 scb = ahd_lookup_scb(ahd, scb_index); 883 if (devinfo.role == ROLE_INITIATOR) { 884 if (bus_phase == P_MESGOUT) 885 ahd_setup_initiator_msgout(ahd, 886 &devinfo, 887 scb); 888 else { 889 ahd->msg_type = 890 MSG_TYPE_INITIATOR_MSGIN; 891 ahd->msgin_index = 0; 892 } 893 } 894 #if AHD_TARGET_MODE 895 else { 896 if (bus_phase == P_MESGOUT) { 897 ahd->msg_type = 898 MSG_TYPE_TARGET_MSGOUT; 899 ahd->msgin_index = 0; 900 } 901 else 902 ahd_setup_target_msgin(ahd, 903 &devinfo, 904 scb); 905 } 906 #endif 907 } 908 909 ahd_handle_message_phase(ahd); 910 break; 911 } 912 case NO_MATCH: 913 { 914 /* Ensure we don't leave the selection hardware on */ 915 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 916 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 917 918 printf("%s:%c:%d: no active SCB for reconnecting " 919 "target - issuing BUS DEVICE RESET\n", 920 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 921 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 922 "REG0 == 0x%x ACCUM = 0x%x\n", 923 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 924 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 925 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 926 "SINDEX == 0x%x\n", 927 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 928 ahd_find_busy_tcl(ahd, 929 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 930 ahd_inb(ahd, SAVED_LUN))), 931 ahd_inw(ahd, SINDEX)); 932 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 933 "SCB_CONTROL == 0x%x\n", 934 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 935 ahd_inb_scbram(ahd, SCB_LUN), 936 ahd_inb_scbram(ahd, SCB_CONTROL)); 937 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 938 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 939 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 940 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 941 ahd_dump_card_state(ahd); 942 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 943 ahd->msgout_len = 1; 944 ahd->msgout_index = 0; 945 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 946 ahd_outb(ahd, MSG_OUT, HOST_MSG); 947 ahd_assert_atn(ahd); 948 break; 949 } 950 case PROTO_VIOLATION: 951 { 952 ahd_handle_proto_violation(ahd); 953 break; 954 } 955 case IGN_WIDE_RES: 956 { 957 struct ahd_devinfo devinfo; 958 959 ahd_fetch_devinfo(ahd, &devinfo); 960 ahd_handle_ign_wide_residue(ahd, &devinfo); 961 break; 962 } 963 case BAD_PHASE: 964 { 965 u_int lastphase; 966 967 lastphase = ahd_inb(ahd, LASTPHASE); 968 printf("%s:%c:%d: unknown scsi bus phase %x, " 969 "lastphase = 0x%x. Attempting to continue\n", 970 ahd_name(ahd), 'A', 971 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 972 lastphase, ahd_inb(ahd, SCSISIGI)); 973 break; 974 } 975 case MISSED_BUSFREE: 976 { 977 u_int lastphase; 978 979 lastphase = ahd_inb(ahd, LASTPHASE); 980 printf("%s:%c:%d: Missed busfree. " 981 "Lastphase = 0x%x, Curphase = 0x%x\n", 982 ahd_name(ahd), 'A', 983 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 984 lastphase, ahd_inb(ahd, SCSISIGI)); 985 ahd_restart(ahd); 986 return; 987 } 988 case DATA_OVERRUN: 989 { 990 /* 991 * When the sequencer detects an overrun, it 992 * places the controller in "BITBUCKET" mode 993 * and allows the target to complete its transfer. 994 * Unfortunately, none of the counters get updated 995 * when the controller is in this mode, so we have 996 * no way of knowing how large the overrun was. 997 */ 998 struct scb *scb; 999 u_int scbindex; 1000 #ifdef AHD_DEBUG 1001 u_int lastphase; 1002 #endif 1003 1004 scbindex = ahd_get_scbptr(ahd); 1005 scb = ahd_lookup_scb(ahd, scbindex); 1006 #ifdef AHD_DEBUG 1007 lastphase = ahd_inb(ahd, LASTPHASE); 1008 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1009 ahd_print_path(ahd, scb); 1010 printf("data overrun detected %s. Tag == 0x%x.\n", 1011 ahd_lookup_phase_entry(lastphase)->phasemsg, 1012 SCB_GET_TAG(scb)); 1013 ahd_print_path(ahd, scb); 1014 printf("%s seen Data Phase. Length = %ld. " 1015 "NumSGs = %d.\n", 1016 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1017 ? "Have" : "Haven't", 1018 ahd_get_transfer_length(scb), scb->sg_count); 1019 ahd_dump_sglist(scb); 1020 } 1021 #endif 1022 1023 /* 1024 * Set this and it will take effect when the 1025 * target does a command complete. 1026 */ 1027 ahd_freeze_devq(ahd, scb); 1028 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1029 ahd_freeze_scb(scb); 1030 break; 1031 } 1032 case MKMSG_FAILED: 1033 { 1034 struct ahd_devinfo devinfo; 1035 struct scb *scb; 1036 u_int scbid; 1037 1038 ahd_fetch_devinfo(ahd, &devinfo); 1039 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1040 ahd_name(ahd), devinfo.channel, devinfo.target, 1041 devinfo.lun); 1042 scbid = ahd_get_scbptr(ahd); 1043 scb = ahd_lookup_scb(ahd, scbid); 1044 if (scb != NULL 1045 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1046 /* 1047 * Ensure that we didn't put a second instance of this 1048 * SCB into the QINFIFO. 1049 */ 1050 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1051 SCB_GET_CHANNEL(ahd, scb), 1052 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1053 ROLE_INITIATOR, /*status*/0, 1054 SEARCH_REMOVE); 1055 ahd_outb(ahd, SCB_CONTROL, 1056 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1057 break; 1058 } 1059 case TASKMGMT_FUNC_COMPLETE: 1060 { 1061 u_int scbid; 1062 struct scb *scb; 1063 1064 scbid = ahd_get_scbptr(ahd); 1065 scb = ahd_lookup_scb(ahd, scbid); 1066 if (scb != NULL) { 1067 u_int lun; 1068 u_int tag; 1069 cam_status error; 1070 1071 ahd_print_path(ahd, scb); 1072 printf("Task Management Func 0x%x Complete\n", 1073 scb->hscb->task_management); 1074 lun = CAM_LUN_WILDCARD; 1075 tag = SCB_LIST_NULL; 1076 1077 switch (scb->hscb->task_management) { 1078 case SIU_TASKMGMT_ABORT_TASK: 1079 tag = SCB_GET_TAG(scb); 1080 case SIU_TASKMGMT_ABORT_TASK_SET: 1081 case SIU_TASKMGMT_CLEAR_TASK_SET: 1082 lun = scb->hscb->lun; 1083 error = CAM_REQ_ABORTED; 1084 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1085 'A', lun, tag, ROLE_INITIATOR, 1086 error); 1087 break; 1088 case SIU_TASKMGMT_LUN_RESET: 1089 lun = scb->hscb->lun; 1090 case SIU_TASKMGMT_TARGET_RESET: 1091 { 1092 struct ahd_devinfo devinfo; 1093 1094 ahd_scb_devinfo(ahd, &devinfo, scb); 1095 error = CAM_BDR_SENT; 1096 ahd_handle_devreset(ahd, &devinfo, lun, 1097 CAM_BDR_SENT, 1098 lun != CAM_LUN_WILDCARD 1099 ? "Lun Reset" 1100 : "Target Reset", 1101 /*verbose_level*/0); 1102 break; 1103 } 1104 default: 1105 panic("Unexpected TaskMgmt Func\n"); 1106 break; 1107 } 1108 } 1109 break; 1110 } 1111 case TASKMGMT_CMD_CMPLT_OKAY: 1112 { 1113 u_int scbid; 1114 struct scb *scb; 1115 1116 /* 1117 * An ABORT TASK TMF failed to be delivered before 1118 * the targeted command completed normally. 1119 */ 1120 scbid = ahd_get_scbptr(ahd); 1121 scb = ahd_lookup_scb(ahd, scbid); 1122 if (scb != NULL) { 1123 /* 1124 * Remove the second instance of this SCB from 1125 * the QINFIFO if it is still there. 1126 */ 1127 ahd_print_path(ahd, scb); 1128 printf("SCB completes before TMF\n"); 1129 /* 1130 * Handle losing the race. Wait until any 1131 * current selection completes. We will then 1132 * set the TMF back to zero in this SCB so that 1133 * the sequencer doesn't bother to issue another 1134 * sequencer interrupt for its completion. 1135 */ 1136 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1137 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1138 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1139 ; 1140 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1141 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1142 SCB_GET_CHANNEL(ahd, scb), 1143 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1144 ROLE_INITIATOR, /*status*/0, 1145 SEARCH_REMOVE); 1146 } 1147 break; 1148 } 1149 case TRACEPOINT0: 1150 case TRACEPOINT1: 1151 case TRACEPOINT2: 1152 case TRACEPOINT3: 1153 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1154 seqintcode - TRACEPOINT0); 1155 break; 1156 case NO_SEQINT: 1157 break; 1158 case SAW_HWERR: 1159 ahd_handle_hwerrint(ahd); 1160 break; 1161 default: 1162 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1163 seqintcode); 1164 break; 1165 } 1166 /* 1167 * The sequencer is paused immediately on 1168 * a SEQINT, so we should restart it when 1169 * we're done. 1170 */ 1171 ahd_unpause(ahd); 1172 } 1173 1174 void 1175 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1176 { 1177 struct scb *scb; 1178 u_int status0; 1179 u_int status3; 1180 u_int status; 1181 u_int lqistat1; 1182 u_int lqostat0; 1183 u_int scbid; 1184 u_int busfreetime; 1185 1186 ahd_update_modes(ahd); 1187 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1188 1189 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1190 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1191 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1192 lqistat1 = ahd_inb(ahd, LQISTAT1); 1193 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1194 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1195 if ((status0 & (SELDI|SELDO)) != 0) { 1196 u_int simode0; 1197 1198 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1199 simode0 = ahd_inb(ahd, SIMODE0); 1200 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1201 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1202 } 1203 scbid = ahd_get_scbptr(ahd); 1204 scb = ahd_lookup_scb(ahd, scbid); 1205 if (scb != NULL 1206 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1207 scb = NULL; 1208 1209 /* Make sure the sequencer is in a safe location. */ 1210 ahd_clear_critical_section(ahd); 1211 1212 if ((status0 & IOERR) != 0) { 1213 u_int now_lvd; 1214 1215 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1216 printf("%s: Transceiver State Has Changed to %s mode\n", 1217 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1218 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1219 /* 1220 * A change in I/O mode is equivalent to a bus reset. 1221 */ 1222 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1223 ahd_pause(ahd); 1224 ahd_setup_iocell_workaround(ahd); 1225 ahd_unpause(ahd); 1226 } else if ((status0 & OVERRUN) != 0) { 1227 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1228 ahd_name(ahd)); 1229 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1230 } else if ((status & SCSIRSTI) != 0) { 1231 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1232 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1233 } else if ((status & SCSIPERR) != 0) { 1234 ahd_handle_transmission_error(ahd); 1235 } else if (lqostat0 != 0) { 1236 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1237 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1238 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1239 ahd_outb(ahd, CLRLQOINT1, 0); 1240 } 1241 } else if ((status & SELTO) != 0) { 1242 u_int scbid; 1243 1244 /* Stop the selection */ 1245 ahd_outb(ahd, SCSISEQ0, 0); 1246 1247 /* No more pending messages */ 1248 ahd_clear_msg_state(ahd); 1249 1250 /* Clear interrupt state */ 1251 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1252 1253 /* 1254 * Although the driver does not care about the 1255 * 'Selection in Progress' status bit, the busy 1256 * LED does. SELINGO is only cleared by a sucessfull 1257 * selection, so we must manually clear it to insure 1258 * the LED turns off just incase no future successful 1259 * selections occur (e.g. no devices on the bus). 1260 */ 1261 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1262 1263 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1264 scb = ahd_lookup_scb(ahd, scbid); 1265 if (scb == NULL) { 1266 printf("%s: ahd_intr - referenced scb not " 1267 "valid during SELTO scb(0x%x)\n", 1268 ahd_name(ahd), scbid); 1269 ahd_dump_card_state(ahd); 1270 } else { 1271 struct ahd_devinfo devinfo; 1272 #ifdef AHD_DEBUG 1273 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1274 ahd_print_path(ahd, scb); 1275 printf("Saw Selection Timeout for SCB 0x%x\n", 1276 scbid); 1277 } 1278 #endif 1279 /* 1280 * Force a renegotiation with this target just in 1281 * case the cable was pulled and will later be 1282 * re-attached. The target may forget its negotiation 1283 * settings with us should it attempt to reselect 1284 * during the interruption. The target will not issue 1285 * a unit attention in this case, so we must always 1286 * renegotiate. 1287 */ 1288 ahd_scb_devinfo(ahd, &devinfo, scb); 1289 ahd_force_renegotiation(ahd, &devinfo); 1290 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1291 ahd_freeze_devq(ahd, scb); 1292 } 1293 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1294 ahd_iocell_first_selection(ahd); 1295 ahd_unpause(ahd); 1296 } else if ((status0 & (SELDI|SELDO)) != 0) { 1297 ahd_iocell_first_selection(ahd); 1298 ahd_unpause(ahd); 1299 } else if (status3 != 0) { 1300 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1301 ahd_name(ahd), status3); 1302 ahd_outb(ahd, CLRSINT3, status3); 1303 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1304 ahd_handle_lqiphase_error(ahd, lqistat1); 1305 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1306 /* 1307 * This status can be delayed during some 1308 * streaming operations. The SCSIPHASE 1309 * handler has already dealt with this case 1310 * so just clear the error. 1311 */ 1312 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1313 } else if ((status & BUSFREE) != 0) { 1314 u_int lqostat1; 1315 int restart; 1316 int clear_fifo; 1317 int packetized; 1318 u_int mode; 1319 1320 /* 1321 * Clear our selection hardware as soon as possible. 1322 * We may have an entry in the waiting Q for this target, 1323 * that is affected by this busfree and we don't want to 1324 * go about selecting the target while we handle the event. 1325 */ 1326 ahd_outb(ahd, SCSISEQ0, 0); 1327 1328 /* 1329 * Determine what we were up to at the time of 1330 * the busfree. 1331 */ 1332 mode = AHD_MODE_SCSI; 1333 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1334 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1335 switch (busfreetime) { 1336 case BUSFREE_DFF0: 1337 case BUSFREE_DFF1: 1338 { 1339 u_int scbid; 1340 struct scb *scb; 1341 1342 mode = busfreetime == BUSFREE_DFF0 1343 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1344 ahd_set_modes(ahd, mode, mode); 1345 scbid = ahd_get_scbptr(ahd); 1346 scb = ahd_lookup_scb(ahd, scbid); 1347 if (scb == NULL) { 1348 printf("%s: Invalid SCB %d in DFF%d " 1349 "during unexpected busfree\n", 1350 ahd_name(ahd), scbid, mode); 1351 packetized = 0; 1352 } else 1353 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1354 clear_fifo = 1; 1355 break; 1356 } 1357 case BUSFREE_LQO: 1358 clear_fifo = 0; 1359 packetized = 1; 1360 break; 1361 default: 1362 clear_fifo = 0; 1363 packetized = (lqostat1 & LQOBUSFREE) != 0; 1364 if (!packetized 1365 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1366 packetized = 1; 1367 break; 1368 } 1369 1370 #ifdef AHD_DEBUG 1371 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1372 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1373 busfreetime); 1374 #endif 1375 /* 1376 * Busfrees that occur in non-packetized phases are 1377 * handled by the nonpkt_busfree handler. 1378 */ 1379 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1380 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1381 } else { 1382 packetized = 0; 1383 restart = ahd_handle_nonpkt_busfree(ahd); 1384 } 1385 /* 1386 * Clear the busfree interrupt status. The setting of 1387 * the interrupt is a pulse, so in a perfect world, we 1388 * would not need to muck with the ENBUSFREE logic. This 1389 * would ensure that if the bus moves on to another 1390 * connection, busfree protection is still in force. If 1391 * BUSFREEREV is broken, however, we must manually clear 1392 * the ENBUSFREE if the busfree occurred during a non-pack 1393 * connection so that we don't get false positives during 1394 * future, packetized, connections. 1395 */ 1396 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1397 if (packetized == 0 1398 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1399 ahd_outb(ahd, SIMODE1, 1400 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1401 1402 if (clear_fifo) 1403 ahd_clear_fifo(ahd, mode); 1404 1405 ahd_clear_msg_state(ahd); 1406 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1407 if (restart) { 1408 ahd_restart(ahd); 1409 } else { 1410 ahd_unpause(ahd); 1411 } 1412 } else { 1413 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1414 ahd_name(ahd), status); 1415 ahd_dump_card_state(ahd); 1416 ahd_clear_intstat(ahd); 1417 ahd_unpause(ahd); 1418 } 1419 } 1420 1421 static void 1422 ahd_handle_transmission_error(struct ahd_softc *ahd) 1423 { 1424 struct scb *scb; 1425 u_int scbid; 1426 u_int lqistat1; 1427 u_int lqistat2; 1428 u_int msg_out; 1429 u_int curphase; 1430 u_int lastphase; 1431 u_int perrdiag; 1432 u_int cur_col; 1433 int silent; 1434 1435 scb = NULL; 1436 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1437 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1438 lqistat2 = ahd_inb(ahd, LQISTAT2); 1439 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1440 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1441 u_int lqistate; 1442 1443 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1444 lqistate = ahd_inb(ahd, LQISTATE); 1445 if ((lqistate >= 0x1E && lqistate <= 0x24) 1446 || (lqistate == 0x29)) { 1447 #ifdef AHD_DEBUG 1448 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1449 printf("%s: NLQCRC found via LQISTATE\n", 1450 ahd_name(ahd)); 1451 } 1452 #endif 1453 lqistat1 |= LQICRCI_NLQ; 1454 } 1455 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1456 } 1457 1458 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1459 lastphase = ahd_inb(ahd, LASTPHASE); 1460 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1461 perrdiag = ahd_inb(ahd, PERRDIAG); 1462 msg_out = MSG_INITIATOR_DET_ERR; 1463 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1464 1465 /* 1466 * Try to find the SCB associated with this error. 1467 */ 1468 silent = FALSE; 1469 if (lqistat1 == 0 1470 || (lqistat1 & LQICRCI_NLQ) != 0) { 1471 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1472 ahd_set_active_fifo(ahd); 1473 scbid = ahd_get_scbptr(ahd); 1474 scb = ahd_lookup_scb(ahd, scbid); 1475 if (scb != NULL && SCB_IS_SILENT(scb)) 1476 silent = TRUE; 1477 } 1478 1479 cur_col = 0; 1480 if (silent == FALSE) { 1481 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1482 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1483 ahd_lastphase_print(lastphase, &cur_col, 50); 1484 ahd_scsisigi_print(curphase, &cur_col, 50); 1485 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1486 printf("\n"); 1487 ahd_dump_card_state(ahd); 1488 } 1489 1490 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1491 if (silent == FALSE) { 1492 printf("%s: Gross protocol error during incoming " 1493 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1494 ahd_name(ahd), lqistat1); 1495 } 1496 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1497 return; 1498 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1499 /* 1500 * A CRC error has been detected on an incoming LQ. 1501 * The bus is currently hung on the last ACK. 1502 * Hit LQIRETRY to release the last ack, and 1503 * wait for the sequencer to determine that ATNO 1504 * is asserted while in message out to take us 1505 * to our host message loop. No NONPACKREQ or 1506 * LQIPHASE type errors will occur in this 1507 * scenario. After this first LQIRETRY, the LQI 1508 * manager will be in ISELO where it will 1509 * happily sit until another packet phase begins. 1510 * Unexpected bus free detection is enabled 1511 * through any phases that occur after we release 1512 * this last ack until the LQI manager sees a 1513 * packet phase. This implies we may have to 1514 * ignore a perfectly valid "unexected busfree" 1515 * after our "initiator detected error" message is 1516 * sent. A busfree is the expected response after 1517 * we tell the target that it's L_Q was corrupted. 1518 * (SPI4R09 10.7.3.3.3) 1519 */ 1520 ahd_outb(ahd, LQCTL2, LQIRETRY); 1521 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1522 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1523 /* 1524 * We detected a CRC error in a NON-LQ packet. 1525 * The hardware has varying behavior in this situation 1526 * depending on whether this packet was part of a 1527 * stream or not. 1528 * 1529 * PKT by PKT mode: 1530 * The hardware has already acked the complete packet. 1531 * If the target honors our outstanding ATN condition, 1532 * we should be (or soon will be) in MSGOUT phase. 1533 * This will trigger the LQIPHASE_LQ status bit as the 1534 * hardware was expecting another LQ. Unexpected 1535 * busfree detection is enabled. Once LQIPHASE_LQ is 1536 * true (first entry into host message loop is much 1537 * the same), we must clear LQIPHASE_LQ and hit 1538 * LQIRETRY so the hardware is ready to handle 1539 * a future LQ. NONPACKREQ will not be asserted again 1540 * once we hit LQIRETRY until another packet is 1541 * processed. The target may either go busfree 1542 * or start another packet in response to our message. 1543 * 1544 * Read Streaming P0 asserted: 1545 * If we raise ATN and the target completes the entire 1546 * stream (P0 asserted during the last packet), the 1547 * hardware will ack all data and return to the ISTART 1548 * state. When the target reponds to our ATN condition, 1549 * LQIPHASE_LQ will be asserted. We should respond to 1550 * this with an LQIRETRY to prepare for any future 1551 * packets. NONPACKREQ will not be asserted again 1552 * once we hit LQIRETRY until another packet is 1553 * processed. The target may either go busfree or 1554 * start another packet in response to our message. 1555 * Busfree detection is enabled. 1556 * 1557 * Read Streaming P0 not asserted: 1558 * If we raise ATN and the target transitions to 1559 * MSGOUT in or after a packet where P0 is not 1560 * asserted, the hardware will assert LQIPHASE_NLQ. 1561 * We should respond to the LQIPHASE_NLQ with an 1562 * LQIRETRY. Should the target stay in a non-pkt 1563 * phase after we send our message, the hardware 1564 * will assert LQIPHASE_LQ. Recovery is then just as 1565 * listed above for the read streaming with P0 asserted. 1566 * Busfree detection is enabled. 1567 */ 1568 if (silent == FALSE) 1569 printf("LQICRC_NLQ\n"); 1570 if (scb == NULL) { 1571 printf("%s: No SCB valid for LQICRC_NLQ. " 1572 "Resetting bus\n", ahd_name(ahd)); 1573 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1574 return; 1575 } 1576 } else if ((lqistat1 & LQIBADLQI) != 0) { 1577 printf("Need to handle BADLQI!\n"); 1578 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1579 return; 1580 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1581 if ((curphase & ~P_DATAIN_DT) != 0) { 1582 /* Ack the byte. So we can continue. */ 1583 if (silent == FALSE) 1584 printf("Acking %s to clear perror\n", 1585 ahd_lookup_phase_entry(curphase)->phasemsg); 1586 ahd_inb(ahd, SCSIDAT); 1587 } 1588 1589 if (curphase == P_MESGIN) 1590 msg_out = MSG_PARITY_ERROR; 1591 } 1592 1593 /* 1594 * We've set the hardware to assert ATN if we 1595 * get a parity error on "in" phases, so all we 1596 * need to do is stuff the message buffer with 1597 * the appropriate message. "In" phases have set 1598 * mesg_out to something other than MSG_NOP. 1599 */ 1600 ahd->send_msg_perror = msg_out; 1601 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1602 scb->flags |= SCB_TRANSMISSION_ERROR; 1603 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1604 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1605 ahd_unpause(ahd); 1606 } 1607 1608 static void 1609 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1610 { 1611 /* 1612 * Clear the sources of the interrupts. 1613 */ 1614 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1615 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1616 1617 /* 1618 * If the "illegal" phase changes were in response 1619 * to our ATN to flag a CRC error, AND we ended up 1620 * on packet boundaries, clear the error, restart the 1621 * LQI manager as appropriate, and go on our merry 1622 * way toward sending the message. Otherwise, reset 1623 * the bus to clear the error. 1624 */ 1625 ahd_set_active_fifo(ahd); 1626 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1627 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1628 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1629 printf("LQIRETRY for LQIPHASE_LQ\n"); 1630 ahd_outb(ahd, LQCTL2, LQIRETRY); 1631 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1632 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1633 ahd_outb(ahd, LQCTL2, LQIRETRY); 1634 } else 1635 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1636 ahd_dump_card_state(ahd); 1637 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1638 ahd_unpause(ahd); 1639 } else { 1640 printf("Reseting Channel for LQI Phase error\n"); 1641 ahd_dump_card_state(ahd); 1642 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1643 } 1644 } 1645 1646 /* 1647 * Packetized unexpected or expected busfree. 1648 * Entered in mode based on busfreetime. 1649 */ 1650 static int 1651 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1652 { 1653 u_int lqostat1; 1654 1655 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1656 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1657 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1658 if ((lqostat1 & LQOBUSFREE) != 0) { 1659 struct scb *scb; 1660 u_int scbid; 1661 u_int saved_scbptr; 1662 u_int waiting_h; 1663 u_int waiting_t; 1664 u_int next; 1665 1666 if ((busfreetime & BUSFREE_LQO) == 0) 1667 printf("%s: Warning, BUSFREE time is 0x%x. " 1668 "Expected BUSFREE_LQO.\n", 1669 ahd_name(ahd), busfreetime); 1670 /* 1671 * The LQO manager detected an unexpected busfree 1672 * either: 1673 * 1674 * 1) During an outgoing LQ. 1675 * 2) After an outgoing LQ but before the first 1676 * REQ of the command packet. 1677 * 3) During an outgoing command packet. 1678 * 1679 * In all cases, CURRSCB is pointing to the 1680 * SCB that encountered the failure. Clean 1681 * up the queue, clear SELDO and LQOBUSFREE, 1682 * and allow the sequencer to restart the select 1683 * out at its lesure. 1684 */ 1685 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1686 scbid = ahd_inw(ahd, CURRSCB); 1687 scb = ahd_lookup_scb(ahd, scbid); 1688 if (scb == NULL) 1689 panic("SCB not valid during LQOBUSFREE"); 1690 /* 1691 * Clear the status. 1692 */ 1693 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1694 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1695 ahd_outb(ahd, CLRLQOINT1, 0); 1696 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1697 ahd_flush_device_writes(ahd); 1698 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1699 1700 /* 1701 * Return the LQO manager to its idle loop. It will 1702 * not do this automatically if the busfree occurs 1703 * after the first REQ of either the LQ or command 1704 * packet or between the LQ and command packet. 1705 */ 1706 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1707 1708 /* 1709 * Update the waiting for selection queue so 1710 * we restart on the correct SCB. 1711 */ 1712 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1713 saved_scbptr = ahd_get_scbptr(ahd); 1714 if (waiting_h != scbid) { 1715 1716 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1717 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1718 if (waiting_t == waiting_h) { 1719 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1720 next = SCB_LIST_NULL; 1721 } else { 1722 ahd_set_scbptr(ahd, waiting_h); 1723 next = ahd_inw_scbram(ahd, SCB_NEXT2); 1724 } 1725 ahd_set_scbptr(ahd, scbid); 1726 ahd_outw(ahd, SCB_NEXT2, next); 1727 } 1728 ahd_set_scbptr(ahd, saved_scbptr); 1729 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1730 if (SCB_IS_SILENT(scb) == FALSE) { 1731 ahd_print_path(ahd, scb); 1732 printf("Probable outgoing LQ CRC error. " 1733 "Retrying command\n"); 1734 } 1735 scb->crc_retry_count++; 1736 } else { 1737 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1738 ahd_freeze_scb(scb); 1739 ahd_freeze_devq(ahd, scb); 1740 } 1741 /* Return unpausing the sequencer. */ 1742 return (0); 1743 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1744 /* 1745 * Ignore what are really parity errors that 1746 * occur on the last REQ of a free running 1747 * clock prior to going busfree. Some drives 1748 * do not properly active negate just before 1749 * going busfree resulting in a parity glitch. 1750 */ 1751 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1752 #ifdef AHD_DEBUG 1753 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1754 printf("%s: Parity on last REQ detected " 1755 "during busfree phase.\n", 1756 ahd_name(ahd)); 1757 #endif 1758 /* Return unpausing the sequencer. */ 1759 return (0); 1760 } 1761 if (ahd->src_mode != AHD_MODE_SCSI) { 1762 u_int scbid; 1763 struct scb *scb; 1764 1765 scbid = ahd_get_scbptr(ahd); 1766 scb = ahd_lookup_scb(ahd, scbid); 1767 ahd_print_path(ahd, scb); 1768 printf("Unexpected PKT busfree condition\n"); 1769 ahd_dump_card_state(ahd); 1770 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1771 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1772 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1773 1774 /* Return restarting the sequencer. */ 1775 return (1); 1776 } 1777 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1778 ahd_dump_card_state(ahd); 1779 /* Restart the sequencer. */ 1780 return (1); 1781 } 1782 1783 /* 1784 * Non-packetized unexpected or expected busfree. 1785 */ 1786 static int 1787 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1788 { 1789 struct ahd_devinfo devinfo; 1790 struct scb *scb; 1791 u_int lastphase; 1792 u_int saved_scsiid; 1793 u_int saved_lun; 1794 u_int target; 1795 u_int initiator_role_id; 1796 u_int scbid; 1797 u_int ppr_busfree; 1798 int printerror; 1799 1800 /* 1801 * Look at what phase we were last in. If its message out, 1802 * chances are pretty good that the busfree was in response 1803 * to one of our abort requests. 1804 */ 1805 lastphase = ahd_inb(ahd, LASTPHASE); 1806 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1807 saved_lun = ahd_inb(ahd, SAVED_LUN); 1808 target = SCSIID_TARGET(ahd, saved_scsiid); 1809 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1810 ahd_compile_devinfo(&devinfo, initiator_role_id, 1811 target, saved_lun, 'A', ROLE_INITIATOR); 1812 printerror = 1; 1813 1814 scbid = ahd_get_scbptr(ahd); 1815 scb = ahd_lookup_scb(ahd, scbid); 1816 if (scb != NULL 1817 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1818 scb = NULL; 1819 1820 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1821 if (lastphase == P_MESGOUT) { 1822 u_int tag; 1823 1824 tag = SCB_LIST_NULL; 1825 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1826 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1827 int found; 1828 int sent_msg; 1829 1830 if (scb == NULL) { 1831 ahd_print_devinfo(ahd, &devinfo); 1832 printf("Abort for unidentified " 1833 "connection completed.\n"); 1834 /* restart the sequencer. */ 1835 return (1); 1836 } 1837 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1838 ahd_print_path(ahd, scb); 1839 printf("SCB %d - Abort%s Completed.\n", 1840 SCB_GET_TAG(scb), 1841 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1842 1843 if (sent_msg == MSG_ABORT_TAG) 1844 tag = SCB_GET_TAG(scb); 1845 1846 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1847 /* 1848 * This abort is in response to an 1849 * unexpected switch to command phase 1850 * for a packetized connection. Since 1851 * the identify message was never sent, 1852 * "saved lun" is 0. We really want to 1853 * abort only the SCB that encountered 1854 * this error, which could have a different 1855 * lun. The SCB will be retried so the OS 1856 * will see the UA after renegotiating to 1857 * packetized. 1858 */ 1859 tag = SCB_GET_TAG(scb); 1860 saved_lun = scb->hscb->lun; 1861 } 1862 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1863 tag, ROLE_INITIATOR, 1864 CAM_REQ_ABORTED); 1865 printf("found == 0x%x\n", found); 1866 printerror = 0; 1867 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1868 MSG_BUS_DEV_RESET, TRUE)) { 1869 #ifdef __FreeBSD__ 1870 /* 1871 * Don't mark the user's request for this BDR 1872 * as completing with CAM_BDR_SENT. CAM3 1873 * specifies CAM_REQ_CMP. 1874 */ 1875 if (scb != NULL 1876 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1877 && ahd_match_scb(ahd, scb, target, 'A', 1878 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1879 ROLE_INITIATOR)) 1880 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1881 #endif 1882 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1883 CAM_BDR_SENT, "Bus Device Reset", 1884 /*verbose_level*/0); 1885 printerror = 0; 1886 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1887 && ppr_busfree == 0) { 1888 struct ahd_initiator_tinfo *tinfo; 1889 struct ahd_tmode_tstate *tstate; 1890 1891 /* 1892 * PPR Rejected. Try non-ppr negotiation 1893 * and retry command. 1894 */ 1895 #ifdef AHD_DEBUG 1896 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1897 printf("PPR negotiation rejected busfree.\n"); 1898 #endif 1899 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1900 devinfo.our_scsiid, 1901 devinfo.target, &tstate); 1902 tinfo->curr.transport_version = 2; 1903 tinfo->goal.transport_version = 2; 1904 tinfo->goal.ppr_options = 0; 1905 ahd_qinfifo_requeue_tail(ahd, scb); 1906 printerror = 0; 1907 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1908 && ppr_busfree == 0) { 1909 /* 1910 * Negotiation Rejected. Go-narrow and 1911 * retry command. 1912 */ 1913 #ifdef AHD_DEBUG 1914 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1915 printf("WDTR Negotiation rejected busfree.\n"); 1916 #endif 1917 ahd_set_width(ahd, &devinfo, 1918 MSG_EXT_WDTR_BUS_8_BIT, 1919 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1920 /*paused*/TRUE); 1921 ahd_qinfifo_requeue_tail(ahd, scb); 1922 printerror = 0; 1923 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 1924 && ppr_busfree == 0) { 1925 /* 1926 * Negotiation Rejected. Go-async and 1927 * retry command. 1928 */ 1929 #ifdef AHD_DEBUG 1930 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1931 printf("SDTR negotiation rejected busfree.\n"); 1932 #endif 1933 ahd_set_syncrate(ahd, &devinfo, 1934 /*period*/0, /*offset*/0, 1935 /*ppr_options*/0, 1936 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1937 /*paused*/TRUE); 1938 ahd_qinfifo_requeue_tail(ahd, scb); 1939 printerror = 0; 1940 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1941 && ahd_sent_msg(ahd, AHDMSG_1B, 1942 MSG_INITIATOR_DET_ERR, TRUE)) { 1943 1944 #ifdef AHD_DEBUG 1945 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1946 printf("Expected IDE Busfree\n"); 1947 #endif 1948 printerror = 0; 1949 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1950 && ahd_sent_msg(ahd, AHDMSG_1B, 1951 MSG_MESSAGE_REJECT, TRUE)) { 1952 1953 #ifdef AHD_DEBUG 1954 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1955 printf("Expected QAS Reject Busfree\n"); 1956 #endif 1957 printerror = 0; 1958 } 1959 } 1960 1961 /* 1962 * The busfree required flag is honored at the end of 1963 * the message phases. We check it last in case we 1964 * had to send some other message that caused a busfree. 1965 */ 1966 if (printerror != 0 1967 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1968 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1969 1970 ahd_freeze_devq(ahd, scb); 1971 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1972 ahd_freeze_scb(scb); 1973 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1974 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1975 SCB_GET_CHANNEL(ahd, scb), 1976 SCB_GET_LUN(scb), SCB_LIST_NULL, 1977 ROLE_INITIATOR, CAM_REQ_ABORTED); 1978 } else { 1979 #ifdef AHD_DEBUG 1980 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1981 printf("PPR Negotiation Busfree.\n"); 1982 #endif 1983 ahd_done(ahd, scb); 1984 } 1985 printerror = 0; 1986 } 1987 if (printerror != 0) { 1988 int aborted; 1989 1990 aborted = 0; 1991 if (scb != NULL) { 1992 u_int tag; 1993 1994 if ((scb->hscb->control & TAG_ENB) != 0) 1995 tag = SCB_GET_TAG(scb); 1996 else 1997 tag = SCB_LIST_NULL; 1998 ahd_print_path(ahd, scb); 1999 aborted = ahd_abort_scbs(ahd, target, 'A', 2000 SCB_GET_LUN(scb), tag, 2001 ROLE_INITIATOR, 2002 CAM_UNEXP_BUSFREE); 2003 } else { 2004 /* 2005 * We had not fully identified this connection, 2006 * so we cannot abort anything. 2007 */ 2008 printf("%s: ", ahd_name(ahd)); 2009 } 2010 if (lastphase != P_BUSFREE) 2011 ahd_force_renegotiation(ahd, &devinfo); 2012 printf("Unexpected busfree %s, %d SCBs aborted, " 2013 "PRGMCNT == 0x%x\n", 2014 ahd_lookup_phase_entry(lastphase)->phasemsg, 2015 aborted, 2016 ahd_inb(ahd, PRGMCNT) 2017 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 2018 ahd_dump_card_state(ahd); 2019 } 2020 /* Always restart the sequencer. */ 2021 return (1); 2022 } 2023 2024 static void 2025 ahd_handle_proto_violation(struct ahd_softc *ahd) 2026 { 2027 struct ahd_devinfo devinfo; 2028 struct scb *scb; 2029 u_int scbid; 2030 u_int seq_flags; 2031 u_int curphase; 2032 u_int lastphase; 2033 int found; 2034 2035 ahd_fetch_devinfo(ahd, &devinfo); 2036 scbid = ahd_get_scbptr(ahd); 2037 scb = ahd_lookup_scb(ahd, scbid); 2038 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2039 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2040 lastphase = ahd_inb(ahd, LASTPHASE); 2041 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2042 2043 /* 2044 * The reconnecting target either did not send an 2045 * identify message, or did, but we didn't find an SCB 2046 * to match. 2047 */ 2048 ahd_print_devinfo(ahd, &devinfo); 2049 printf("Target did not send an IDENTIFY message. " 2050 "LASTPHASE = 0x%x.\n", lastphase); 2051 scb = NULL; 2052 } else if (scb == NULL) { 2053 /* 2054 * We don't seem to have an SCB active for this 2055 * transaction. Print an error and reset the bus. 2056 */ 2057 ahd_print_devinfo(ahd, &devinfo); 2058 printf("No SCB found during protocol violation\n"); 2059 goto proto_violation_reset; 2060 } else { 2061 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2062 if ((seq_flags & NO_CDB_SENT) != 0) { 2063 ahd_print_path(ahd, scb); 2064 printf("No or incomplete CDB sent to device.\n"); 2065 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2066 & STATUS_RCVD) == 0) { 2067 /* 2068 * The target never bothered to provide status to 2069 * us prior to completing the command. Since we don't 2070 * know the disposition of this command, we must attempt 2071 * to abort it. Assert ATN and prepare to send an abort 2072 * message. 2073 */ 2074 ahd_print_path(ahd, scb); 2075 printf("Completed command without status.\n"); 2076 } else { 2077 ahd_print_path(ahd, scb); 2078 printf("Unknown protocol violation.\n"); 2079 ahd_dump_card_state(ahd); 2080 } 2081 } 2082 if ((lastphase & ~P_DATAIN_DT) == 0 2083 || lastphase == P_COMMAND) { 2084 proto_violation_reset: 2085 /* 2086 * Target either went directly to data 2087 * phase or didn't respond to our ATN. 2088 * The only safe thing to do is to blow 2089 * it away with a bus reset. 2090 */ 2091 found = ahd_reset_channel(ahd, 'A', TRUE); 2092 printf("%s: Issued Channel %c Bus Reset. " 2093 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2094 } else { 2095 /* 2096 * Leave the selection hardware off in case 2097 * this abort attempt will affect yet to 2098 * be sent commands. 2099 */ 2100 ahd_outb(ahd, SCSISEQ0, 2101 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2102 ahd_assert_atn(ahd); 2103 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2104 if (scb == NULL) { 2105 ahd_print_devinfo(ahd, &devinfo); 2106 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2107 ahd->msgout_len = 1; 2108 ahd->msgout_index = 0; 2109 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2110 } else { 2111 ahd_print_path(ahd, scb); 2112 scb->flags |= SCB_ABORT; 2113 } 2114 printf("Protocol violation %s. Attempting to abort.\n", 2115 ahd_lookup_phase_entry(curphase)->phasemsg); 2116 } 2117 } 2118 2119 /* 2120 * Force renegotiation to occur the next time we initiate 2121 * a command to the current device. 2122 */ 2123 static void 2124 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2125 { 2126 struct ahd_initiator_tinfo *targ_info; 2127 struct ahd_tmode_tstate *tstate; 2128 2129 #ifdef AHD_DEBUG 2130 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2131 ahd_print_devinfo(ahd, devinfo); 2132 printf("Forcing renegotiation\n"); 2133 } 2134 #endif 2135 targ_info = ahd_fetch_transinfo(ahd, 2136 devinfo->channel, 2137 devinfo->our_scsiid, 2138 devinfo->target, 2139 &tstate); 2140 ahd_update_neg_request(ahd, devinfo, tstate, 2141 targ_info, AHD_NEG_IF_NON_ASYNC); 2142 } 2143 2144 #define AHD_MAX_STEPS 2000 2145 void 2146 ahd_clear_critical_section(struct ahd_softc *ahd) 2147 { 2148 ahd_mode_state saved_modes; 2149 int stepping; 2150 int steps; 2151 int first_instr; 2152 u_int simode0; 2153 u_int simode1; 2154 u_int simode3; 2155 u_int lqimode0; 2156 u_int lqimode1; 2157 u_int lqomode0; 2158 u_int lqomode1; 2159 2160 if (ahd->num_critical_sections == 0) 2161 return; 2162 2163 stepping = FALSE; 2164 steps = 0; 2165 first_instr = 0; 2166 simode0 = 0; 2167 simode1 = 0; 2168 simode3 = 0; 2169 lqimode0 = 0; 2170 lqimode1 = 0; 2171 lqomode0 = 0; 2172 lqomode1 = 0; 2173 saved_modes = ahd_save_modes(ahd); 2174 for (;;) { 2175 struct cs *cs; 2176 u_int seqaddr; 2177 u_int i; 2178 2179 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2180 seqaddr = ahd_inb(ahd, CURADDR) 2181 | (ahd_inb(ahd, CURADDR+1) << 8); 2182 2183 cs = ahd->critical_sections; 2184 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2185 2186 if (cs->begin < seqaddr && cs->end >= seqaddr) 2187 break; 2188 } 2189 2190 if (i == ahd->num_critical_sections) 2191 break; 2192 2193 if (steps > AHD_MAX_STEPS) { 2194 printf("%s: Infinite loop in critical section\n" 2195 "%s: First Instruction 0x%x now 0x%x\n", 2196 ahd_name(ahd), ahd_name(ahd), first_instr, 2197 seqaddr); 2198 ahd_dump_card_state(ahd); 2199 panic("critical section loop"); 2200 } 2201 2202 steps++; 2203 #ifdef AHD_DEBUG 2204 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2205 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2206 seqaddr); 2207 #endif 2208 if (stepping == FALSE) { 2209 2210 first_instr = seqaddr; 2211 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2212 simode0 = ahd_inb(ahd, SIMODE0); 2213 simode3 = ahd_inb(ahd, SIMODE3); 2214 lqimode0 = ahd_inb(ahd, LQIMODE0); 2215 lqimode1 = ahd_inb(ahd, LQIMODE1); 2216 lqomode0 = ahd_inb(ahd, LQOMODE0); 2217 lqomode1 = ahd_inb(ahd, LQOMODE1); 2218 ahd_outb(ahd, SIMODE0, 0); 2219 ahd_outb(ahd, SIMODE3, 0); 2220 ahd_outb(ahd, LQIMODE0, 0); 2221 ahd_outb(ahd, LQIMODE1, 0); 2222 ahd_outb(ahd, LQOMODE0, 0); 2223 ahd_outb(ahd, LQOMODE1, 0); 2224 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2225 simode1 = ahd_inb(ahd, SIMODE1); 2226 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2227 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2228 stepping = TRUE; 2229 } 2230 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2231 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2232 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2233 ahd_outb(ahd, HCNTRL, ahd->unpause); 2234 do { 2235 ahd_delay(200); 2236 } while (!ahd_is_paused(ahd)); 2237 ahd_update_modes(ahd); 2238 } 2239 if (stepping) { 2240 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2241 ahd_outb(ahd, SIMODE0, simode0); 2242 ahd_outb(ahd, SIMODE3, simode3); 2243 ahd_outb(ahd, LQIMODE0, lqimode0); 2244 ahd_outb(ahd, LQIMODE1, lqimode1); 2245 ahd_outb(ahd, LQOMODE0, lqomode0); 2246 ahd_outb(ahd, LQOMODE1, lqomode1); 2247 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2248 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2249 ahd_outb(ahd, SIMODE1, simode1); 2250 /* 2251 * SCSIINT seems to glitch occassionally when 2252 * the interrupt masks are restored. Clear SCSIINT 2253 * one more time so that only persistent errors 2254 * are seen as a real interrupt. 2255 */ 2256 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2257 } 2258 ahd_restore_modes(ahd, saved_modes); 2259 } 2260 2261 /* 2262 * Clear any pending interrupt status. 2263 */ 2264 void 2265 ahd_clear_intstat(struct ahd_softc *ahd) 2266 { 2267 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2268 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2269 /* Clear any interrupt conditions this may have caused */ 2270 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2271 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2272 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2273 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2274 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2275 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2276 |CLRLQOATNPKT|CLRLQOTCRC); 2277 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2278 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2279 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2280 ahd_outb(ahd, CLRLQOINT0, 0); 2281 ahd_outb(ahd, CLRLQOINT1, 0); 2282 } 2283 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2284 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2285 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2286 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2287 |CLRIOERR|CLROVERRUN); 2288 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2289 } 2290 2291 /**************************** Debugging Routines ******************************/ 2292 #ifdef AHD_DEBUG 2293 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2294 #endif 2295 void 2296 ahd_print_scb(struct scb *scb) 2297 { 2298 struct hardware_scb *hscb; 2299 int i; 2300 2301 hscb = scb->hscb; 2302 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2303 (void *)scb, 2304 hscb->control, 2305 hscb->scsiid, 2306 hscb->lun, 2307 hscb->cdb_len); 2308 printf("Shared Data: "); 2309 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2310 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2311 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2312 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2313 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2314 ahd_le32toh(hscb->datacnt), 2315 ahd_le32toh(hscb->sgptr), 2316 SCB_GET_TAG(scb)); 2317 ahd_dump_sglist(scb); 2318 } 2319 2320 void 2321 ahd_dump_sglist(struct scb *scb) 2322 { 2323 int i; 2324 2325 if (scb->sg_count > 0) { 2326 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2327 struct ahd_dma64_seg *sg_list; 2328 2329 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2330 for (i = 0; i < scb->sg_count; i++) { 2331 uint64_t addr; 2332 uint32_t len; 2333 2334 addr = ahd_le64toh(sg_list[i].addr); 2335 len = ahd_le32toh(sg_list[i].len); 2336 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2337 i, 2338 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2339 (uint32_t)(addr & 0xFFFFFFFF), 2340 sg_list[i].len & AHD_SG_LEN_MASK, 2341 (sg_list[i].len & AHD_DMA_LAST_SEG) 2342 ? " Last" : ""); 2343 } 2344 } else { 2345 struct ahd_dma_seg *sg_list; 2346 2347 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2348 for (i = 0; i < scb->sg_count; i++) { 2349 uint32_t len; 2350 2351 len = ahd_le32toh(sg_list[i].len); 2352 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2353 i, 2354 (len >> 24) & SG_HIGH_ADDR_BITS, 2355 ahd_le32toh(sg_list[i].addr), 2356 len & AHD_SG_LEN_MASK, 2357 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2358 } 2359 } 2360 } 2361 } 2362 2363 /************************* Transfer Negotiation *******************************/ 2364 /* 2365 * Allocate per target mode instance (ID we respond to as a target) 2366 * transfer negotiation data structures. 2367 */ 2368 static struct ahd_tmode_tstate * 2369 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2370 { 2371 struct ahd_tmode_tstate *master_tstate; 2372 struct ahd_tmode_tstate *tstate; 2373 int i; 2374 2375 master_tstate = ahd->enabled_targets[ahd->our_id]; 2376 if (ahd->enabled_targets[scsi_id] != NULL 2377 && ahd->enabled_targets[scsi_id] != master_tstate) 2378 panic("%s: ahd_alloc_tstate - Target already allocated", 2379 ahd_name(ahd)); 2380 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 2381 if (tstate == NULL) 2382 return (NULL); 2383 2384 /* 2385 * If we have allocated a master tstate, copy user settings from 2386 * the master tstate (taken from SRAM or the EEPROM) for this 2387 * channel, but reset our current and goal settings to async/narrow 2388 * until an initiator talks to us. 2389 */ 2390 if (master_tstate != NULL) { 2391 memcpy(tstate, master_tstate, sizeof(*tstate)); 2392 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2393 for (i = 0; i < 16; i++) { 2394 memset(&tstate->transinfo[i].curr, 0, 2395 sizeof(tstate->transinfo[i].curr)); 2396 memset(&tstate->transinfo[i].goal, 0, 2397 sizeof(tstate->transinfo[i].goal)); 2398 } 2399 } else 2400 memset(tstate, 0, sizeof(*tstate)); 2401 ahd->enabled_targets[scsi_id] = tstate; 2402 return (tstate); 2403 } 2404 2405 #ifdef AHD_TARGET_MODE 2406 /* 2407 * Free per target mode instance (ID we respond to as a target) 2408 * transfer negotiation data structures. 2409 */ 2410 static void 2411 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2412 { 2413 struct ahd_tmode_tstate *tstate; 2414 2415 /* 2416 * Don't clean up our "master" tstate. 2417 * It has our default user settings. 2418 */ 2419 if (scsi_id == ahd->our_id 2420 && force == FALSE) 2421 return; 2422 2423 tstate = ahd->enabled_targets[scsi_id]; 2424 if (tstate != NULL) 2425 free(tstate, M_DEVBUF); 2426 ahd->enabled_targets[scsi_id] = NULL; 2427 } 2428 #endif 2429 2430 /* 2431 * Called when we have an active connection to a target on the bus, 2432 * this function finds the nearest period to the input period limited 2433 * by the capabilities of the bus connectivity of and sync settings for 2434 * the target. 2435 */ 2436 void 2437 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2438 struct ahd_initiator_tinfo *tinfo, 2439 u_int *period, u_int *ppr_options, role_t role) 2440 { 2441 struct ahd_transinfo *transinfo; 2442 u_int maxsync; 2443 2444 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2445 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2446 maxsync = AHD_SYNCRATE_PACED; 2447 } else { 2448 maxsync = AHD_SYNCRATE_ULTRA; 2449 /* Can't do DT related options on an SE bus */ 2450 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2451 } 2452 /* 2453 * Never allow a value higher than our current goal 2454 * period otherwise we may allow a target initiated 2455 * negotiation to go above the limit as set by the 2456 * user. In the case of an initiator initiated 2457 * sync negotiation, we limit based on the user 2458 * setting. This allows the system to still accept 2459 * incoming negotiations even if target initiated 2460 * negotiation is not performed. 2461 */ 2462 if (role == ROLE_TARGET) 2463 transinfo = &tinfo->user; 2464 else 2465 transinfo = &tinfo->goal; 2466 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2467 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2468 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2469 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2470 } 2471 if (transinfo->period == 0) { 2472 *period = 0; 2473 *ppr_options = 0; 2474 } else { 2475 *period = MAX(*period, transinfo->period); 2476 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2477 } 2478 } 2479 2480 /* 2481 * Look up the valid period to SCSIRATE conversion in our table. 2482 * Return the period and offset that should be sent to the target 2483 * if this was the beginning of an SDTR. 2484 */ 2485 void 2486 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2487 u_int *ppr_options, u_int maxsync) 2488 { 2489 if (*period < maxsync) 2490 *period = maxsync; 2491 2492 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2493 && *period > AHD_SYNCRATE_MIN_DT) 2494 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2495 2496 if (*period > AHD_SYNCRATE_MIN) 2497 *period = 0; 2498 2499 /* Honor PPR option conformance rules. */ 2500 if (*period > AHD_SYNCRATE_PACED) 2501 *ppr_options &= ~MSG_EXT_PPR_RTI; 2502 2503 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2504 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2505 2506 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2507 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2508 2509 /* Skip all PACED only entries if IU is not available */ 2510 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2511 && *period < AHD_SYNCRATE_DT) 2512 *period = AHD_SYNCRATE_DT; 2513 2514 /* Skip all DT only entries if DT is not available */ 2515 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2516 && *period < AHD_SYNCRATE_ULTRA2) 2517 *period = AHD_SYNCRATE_ULTRA2; 2518 } 2519 2520 /* 2521 * Truncate the given synchronous offset to a value the 2522 * current adapter type and syncrate are capable of. 2523 */ 2524 void 2525 ahd_validate_offset(struct ahd_softc *ahd, 2526 struct ahd_initiator_tinfo *tinfo, 2527 u_int period, u_int *offset, int wide, 2528 role_t role) 2529 { 2530 u_int maxoffset; 2531 2532 /* Limit offset to what we can do */ 2533 if (period == 0) 2534 maxoffset = 0; 2535 else if (period <= AHD_SYNCRATE_PACED) { 2536 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2537 maxoffset = MAX_OFFSET_PACED_BUG; 2538 else 2539 maxoffset = MAX_OFFSET_PACED; 2540 } else 2541 maxoffset = MAX_OFFSET_NON_PACED; 2542 *offset = MIN(*offset, maxoffset); 2543 if (tinfo != NULL) { 2544 if (role == ROLE_TARGET) 2545 *offset = MIN(*offset, tinfo->user.offset); 2546 else 2547 *offset = MIN(*offset, tinfo->goal.offset); 2548 } 2549 } 2550 2551 /* 2552 * Truncate the given transfer width parameter to a value the 2553 * current adapter type is capable of. 2554 */ 2555 void 2556 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2557 u_int *bus_width, role_t role) 2558 { 2559 switch (*bus_width) { 2560 default: 2561 if (ahd->features & AHD_WIDE) { 2562 /* Respond Wide */ 2563 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2564 break; 2565 } 2566 /* FALLTHROUGH */ 2567 case MSG_EXT_WDTR_BUS_8_BIT: 2568 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2569 break; 2570 } 2571 if (tinfo != NULL) { 2572 if (role == ROLE_TARGET) 2573 *bus_width = MIN(tinfo->user.width, *bus_width); 2574 else 2575 *bus_width = MIN(tinfo->goal.width, *bus_width); 2576 } 2577 } 2578 2579 /* 2580 * Update the bitmask of targets for which the controller should 2581 * negotiate with at the next convenient oportunity. This currently 2582 * means the next time we send the initial identify messages for 2583 * a new transaction. 2584 */ 2585 int 2586 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2587 struct ahd_tmode_tstate *tstate, 2588 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2589 { 2590 u_int auto_negotiate_orig; 2591 2592 auto_negotiate_orig = tstate->auto_negotiate; 2593 if (neg_type == AHD_NEG_ALWAYS) { 2594 /* 2595 * Force our "current" settings to be 2596 * unknown so that unless a bus reset 2597 * occurs the need to renegotiate is 2598 * recorded persistently. 2599 */ 2600 if ((ahd->features & AHD_WIDE) != 0) 2601 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2602 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2603 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2604 } 2605 if (tinfo->curr.period != tinfo->goal.period 2606 || tinfo->curr.width != tinfo->goal.width 2607 || tinfo->curr.offset != tinfo->goal.offset 2608 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2609 || (neg_type == AHD_NEG_IF_NON_ASYNC 2610 && (tinfo->goal.offset != 0 2611 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2612 || tinfo->goal.ppr_options != 0))) 2613 tstate->auto_negotiate |= devinfo->target_mask; 2614 else 2615 tstate->auto_negotiate &= ~devinfo->target_mask; 2616 2617 return (auto_negotiate_orig != tstate->auto_negotiate); 2618 } 2619 2620 /* 2621 * Update the user/goal/curr tables of synchronous negotiation 2622 * parameters as well as, in the case of a current or active update, 2623 * any data structures on the host controller. In the case of an 2624 * active update, the specified target is currently talking to us on 2625 * the bus, so the transfer parameter update must take effect 2626 * immediately. 2627 */ 2628 void 2629 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2630 u_int period, u_int offset, u_int ppr_options, 2631 u_int type, int paused) 2632 { 2633 struct ahd_initiator_tinfo *tinfo; 2634 struct ahd_tmode_tstate *tstate; 2635 u_int old_period; 2636 u_int old_offset; 2637 u_int old_ppr; 2638 int active; 2639 int update_needed; 2640 2641 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2642 update_needed = 0; 2643 2644 if (period == 0 || offset == 0) { 2645 period = 0; 2646 offset = 0; 2647 } 2648 2649 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2650 devinfo->target, &tstate); 2651 2652 if ((type & AHD_TRANS_USER) != 0) { 2653 tinfo->user.period = period; 2654 tinfo->user.offset = offset; 2655 tinfo->user.ppr_options = ppr_options; 2656 } 2657 2658 if ((type & AHD_TRANS_GOAL) != 0) { 2659 tinfo->goal.period = period; 2660 tinfo->goal.offset = offset; 2661 tinfo->goal.ppr_options = ppr_options; 2662 } 2663 2664 old_period = tinfo->curr.period; 2665 old_offset = tinfo->curr.offset; 2666 old_ppr = tinfo->curr.ppr_options; 2667 2668 if ((type & AHD_TRANS_CUR) != 0 2669 && (old_period != period 2670 || old_offset != offset 2671 || old_ppr != ppr_options)) { 2672 2673 update_needed++; 2674 2675 tinfo->curr.period = period; 2676 tinfo->curr.offset = offset; 2677 tinfo->curr.ppr_options = ppr_options; 2678 2679 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2680 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2681 2682 if (bootverbose) { 2683 if (offset != 0) { 2684 int options; 2685 2686 printf("%s: target %d synchronous with " 2687 "period = 0x%x, offset = 0x%x", 2688 ahd_name(ahd), devinfo->target, 2689 period, offset); 2690 options = 0; 2691 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 2692 printf("(RDSTRM"); 2693 options++; 2694 } 2695 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2696 printf("%s", options ? "|DT" : "(DT"); 2697 options++; 2698 } 2699 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2700 printf("%s", options ? "|IU" : "(IU"); 2701 options++; 2702 } 2703 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2704 printf("%s", options ? "|RTI" : "(RTI"); 2705 options++; 2706 } 2707 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2708 printf("%s", options ? "|QAS" : "(QAS"); 2709 options++; 2710 } 2711 if (options != 0) 2712 printf(")\n"); 2713 else 2714 printf("\n"); 2715 } else { 2716 printf("%s: target %d using " 2717 "asynchronous transfers%s\n", 2718 ahd_name(ahd), devinfo->target, 2719 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2720 ? "(QAS)" : ""); 2721 } 2722 } 2723 } 2724 /* 2725 * Always refresh the neg-table to handle the case of the 2726 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2727 * We will always renegotiate in that case if this is a 2728 * packetized request. Also manage the busfree expected flag 2729 * from this common routine so that we catch changes due to 2730 * WDTR or SDTR messages. 2731 */ 2732 if ((type & AHD_TRANS_CUR) != 0) { 2733 if (!paused) 2734 ahd_pause(ahd); 2735 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2736 if (!paused) 2737 ahd_unpause(ahd); 2738 if (ahd->msg_type != MSG_TYPE_NONE) { 2739 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2740 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2741 #ifdef AHD_DEBUG 2742 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2743 ahd_print_devinfo(ahd, devinfo); 2744 printf("Expecting IU Change busfree\n"); 2745 } 2746 #endif 2747 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2748 | MSG_FLAG_IU_REQ_CHANGED; 2749 } 2750 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2751 #ifdef AHD_DEBUG 2752 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2753 printf("PPR with IU_REQ outstanding\n"); 2754 #endif 2755 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2756 } 2757 } 2758 } 2759 2760 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2761 tinfo, AHD_NEG_TO_GOAL); 2762 2763 if (update_needed) 2764 ahd_update_xfer_mode(ahd, devinfo); 2765 ahd->sc_req = 0; 2766 2767 if (update_needed && active) 2768 ahd_update_pending_scbs(ahd); 2769 } 2770 2771 /* 2772 * Update the user/goal/curr tables of wide negotiation 2773 * parameters as well as, in the case of a current or active update, 2774 * any data structures on the host controller. In the case of an 2775 * active update, the specified target is currently talking to us on 2776 * the bus, so the transfer parameter update must take effect 2777 * immediately. 2778 */ 2779 void 2780 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2781 u_int width, u_int type, int paused) 2782 { 2783 struct ahd_initiator_tinfo *tinfo; 2784 struct ahd_tmode_tstate *tstate; 2785 u_int oldwidth; 2786 int active; 2787 int update_needed; 2788 2789 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2790 update_needed = 0; 2791 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2792 devinfo->target, &tstate); 2793 2794 if ((type & AHD_TRANS_USER) != 0) 2795 tinfo->user.width = width; 2796 2797 if ((type & AHD_TRANS_GOAL) != 0) 2798 tinfo->goal.width = width; 2799 2800 oldwidth = tinfo->curr.width; 2801 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2802 2803 update_needed++; 2804 2805 tinfo->curr.width = width; 2806 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2807 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2808 2809 if (bootverbose) { 2810 printf("%s: target %d using %dbit transfers\n", 2811 ahd_name(ahd), devinfo->target, 2812 8 * (0x01 << width)); 2813 } 2814 } 2815 2816 if ((type & AHD_TRANS_CUR) != 0) { 2817 if (!paused) 2818 ahd_pause(ahd); 2819 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2820 if (!paused) 2821 ahd_unpause(ahd); 2822 } 2823 2824 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2825 tinfo, AHD_NEG_TO_GOAL); 2826 if (update_needed && active) 2827 ahd_update_pending_scbs(ahd); 2828 2829 } 2830 2831 /* 2832 * Update the current state of tagged queuing for a given target. 2833 */ 2834 void 2835 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2836 ahd_queue_alg alg) 2837 { 2838 ahd_platform_set_tags(ahd, devinfo, alg); 2839 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2840 devinfo->lun, AC_TRANSFER_NEG, &alg); 2841 } 2842 2843 static void 2844 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2845 struct ahd_transinfo *tinfo) 2846 { 2847 ahd_mode_state saved_modes; 2848 u_int period; 2849 u_int ppr_opts; 2850 u_int con_opts; 2851 u_int offset; 2852 u_int saved_negoaddr; 2853 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2854 2855 saved_modes = ahd_save_modes(ahd); 2856 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2857 2858 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2859 ahd_outb(ahd, NEGOADDR, devinfo->target); 2860 period = tinfo->period; 2861 offset = tinfo->offset; 2862 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2863 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2864 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2865 con_opts = 0; 2866 if (period == 0) 2867 period = AHD_SYNCRATE_ASYNC; 2868 if (period == AHD_SYNCRATE_160) { 2869 2870 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2871 /* 2872 * When the SPI4 spec was finalized, PACE transfers 2873 * was not made a configurable option in the PPR 2874 * message. Instead it is assumed to be enabled for 2875 * any syncrate faster than 80MHz. Nevertheless, 2876 * Harpoon2A4 allows this to be configurable. 2877 * 2878 * Harpoon2A4 also assumes at most 2 data bytes per 2879 * negotiated REQ/ACK offset. Paced transfers take 2880 * 4, so we must adjust our offset. 2881 */ 2882 ppr_opts |= PPROPT_PACE; 2883 offset *= 2; 2884 2885 /* 2886 * Harpoon2A assumed that there would be a 2887 * fallback rate between 160MHz and 80Mhz, 2888 * so 7 is used as the period factor rather 2889 * than 8 for 160MHz. 2890 */ 2891 period = AHD_SYNCRATE_REVA_160; 2892 } 2893 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2894 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2895 ~AHD_PRECOMP_MASK; 2896 } else { 2897 /* 2898 * Precomp should be disabled for non-paced transfers. 2899 */ 2900 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2901 2902 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2903 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2904 /* 2905 * Slow down our CRC interval to be 2906 * compatible with devices that can't 2907 * handle a CRC at full speed. 2908 */ 2909 con_opts |= ENSLOWCRC; 2910 } 2911 } 2912 2913 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2914 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2915 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2916 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2917 2918 ahd_outb(ahd, NEGPERIOD, period); 2919 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2920 ahd_outb(ahd, NEGOFFSET, offset); 2921 2922 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2923 con_opts |= WIDEXFER; 2924 2925 /* 2926 * During packetized transfers, the target will 2927 * give us the oportunity to send command packets 2928 * without us asserting attention. 2929 */ 2930 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2931 con_opts |= ENAUTOATNO; 2932 ahd_outb(ahd, NEGCONOPTS, con_opts); 2933 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2934 ahd_restore_modes(ahd, saved_modes); 2935 } 2936 2937 /* 2938 * When the transfer settings for a connection change, setup for 2939 * negotiation in pending SCBs to effect the change as quickly as 2940 * possible. We also cancel any negotiations that are scheduled 2941 * for inflight SCBs that have not been started yet. 2942 */ 2943 static void 2944 ahd_update_pending_scbs(struct ahd_softc *ahd) 2945 { 2946 struct scb *pending_scb; 2947 int pending_scb_count; 2948 int i; 2949 int paused; 2950 u_int saved_scbptr; 2951 ahd_mode_state saved_modes; 2952 2953 /* 2954 * Traverse the pending SCB list and ensure that all of the 2955 * SCBs there have the proper settings. We can only safely 2956 * clear the negotiation required flag (setting requires the 2957 * execution queue to be modified) and this is only possible 2958 * if we are not already attempting to select out for this 2959 * SCB. For this reason, all callers only call this routine 2960 * if we are changing the negotiation settings for the currently 2961 * active transaction on the bus. 2962 */ 2963 pending_scb_count = 0; 2964 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2965 struct ahd_devinfo devinfo; 2966 struct hardware_scb *pending_hscb; 2967 struct ahd_initiator_tinfo *tinfo; 2968 struct ahd_tmode_tstate *tstate; 2969 2970 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2971 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2972 devinfo.our_scsiid, 2973 devinfo.target, &tstate); 2974 pending_hscb = pending_scb->hscb; 2975 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2976 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2977 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2978 pending_hscb->control &= ~MK_MESSAGE; 2979 } 2980 ahd_sync_scb(ahd, pending_scb, 2981 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2982 pending_scb_count++; 2983 } 2984 2985 if (pending_scb_count == 0) 2986 return; 2987 2988 if (ahd_is_paused(ahd)) { 2989 paused = 1; 2990 } else { 2991 paused = 0; 2992 ahd_pause(ahd); 2993 } 2994 2995 /* 2996 * Force the sequencer to reinitialize the selection for 2997 * the command at the head of the execution queue if it 2998 * has already been setup. The negotiation changes may 2999 * effect whether we select-out with ATN. 3000 */ 3001 saved_modes = ahd_save_modes(ahd); 3002 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3003 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3004 saved_scbptr = ahd_get_scbptr(ahd); 3005 /* Ensure that the hscbs down on the card match the new information */ 3006 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 3007 struct hardware_scb *pending_hscb; 3008 u_int control; 3009 u_int scb_tag; 3010 3011 ahd_set_scbptr(ahd, i); 3012 scb_tag = i; 3013 pending_scb = ahd_lookup_scb(ahd, scb_tag); 3014 if (pending_scb == NULL) 3015 continue; 3016 3017 pending_hscb = pending_scb->hscb; 3018 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3019 control &= ~MK_MESSAGE; 3020 control |= pending_hscb->control & MK_MESSAGE; 3021 ahd_outb(ahd, SCB_CONTROL, control); 3022 } 3023 ahd_set_scbptr(ahd, saved_scbptr); 3024 ahd_restore_modes(ahd, saved_modes); 3025 3026 if (paused == 0) 3027 ahd_unpause(ahd); 3028 } 3029 3030 /**************************** Pathing Information *****************************/ 3031 static void 3032 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3033 { 3034 ahd_mode_state saved_modes; 3035 u_int saved_scsiid; 3036 role_t role; 3037 int our_id; 3038 3039 saved_modes = ahd_save_modes(ahd); 3040 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3041 3042 if (ahd_inb(ahd, SSTAT0) & TARGET) 3043 role = ROLE_TARGET; 3044 else 3045 role = ROLE_INITIATOR; 3046 3047 if (role == ROLE_TARGET 3048 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3049 /* We were selected, so pull our id from TARGIDIN */ 3050 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3051 } else if (role == ROLE_TARGET) 3052 our_id = ahd_inb(ahd, TOWNID); 3053 else 3054 our_id = ahd_inb(ahd, IOWNID); 3055 3056 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3057 ahd_compile_devinfo(devinfo, 3058 our_id, 3059 SCSIID_TARGET(ahd, saved_scsiid), 3060 ahd_inb(ahd, SAVED_LUN), 3061 SCSIID_CHANNEL(ahd, saved_scsiid), 3062 role); 3063 ahd_restore_modes(ahd, saved_modes); 3064 } 3065 3066 void 3067 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3068 { 3069 printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3070 devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3071 } 3072 3073 struct ahd_phase_table_entry* 3074 ahd_lookup_phase_entry(int phase) 3075 { 3076 struct ahd_phase_table_entry *entry; 3077 struct ahd_phase_table_entry *last_entry; 3078 3079 /* 3080 * num_phases doesn't include the default entry which 3081 * will be returned if the phase doesn't match. 3082 */ 3083 last_entry = &ahd_phase_table[num_phases]; 3084 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3085 if (phase == entry->phase) 3086 break; 3087 } 3088 return (entry); 3089 } 3090 3091 void 3092 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3093 u_int lun, char channel, role_t role) 3094 { 3095 devinfo->our_scsiid = our_id; 3096 devinfo->target = target; 3097 devinfo->lun = lun; 3098 devinfo->target_offset = target; 3099 devinfo->channel = channel; 3100 devinfo->role = role; 3101 if (channel == 'B') 3102 devinfo->target_offset += 8; 3103 devinfo->target_mask = (0x01 << devinfo->target_offset); 3104 } 3105 3106 static void 3107 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3108 struct scb *scb) 3109 { 3110 role_t role; 3111 int our_id; 3112 3113 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3114 role = ROLE_INITIATOR; 3115 if ((scb->hscb->control & TARGET_SCB) != 0) 3116 role = ROLE_TARGET; 3117 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3118 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3119 } 3120 3121 3122 /************************ Message Phase Processing ****************************/ 3123 /* 3124 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3125 * or enters the initial message out phase, we are interrupted. Fill our 3126 * outgoing message buffer with the appropriate message and beging handing 3127 * the message phase(s) manually. 3128 */ 3129 static void 3130 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3131 struct scb *scb) 3132 { 3133 /* 3134 * To facilitate adding multiple messages together, 3135 * each routine should increment the index and len 3136 * variables instead of setting them explicitly. 3137 */ 3138 ahd->msgout_index = 0; 3139 ahd->msgout_len = 0; 3140 3141 if (ahd_currently_packetized(ahd)) 3142 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3143 3144 if (ahd->send_msg_perror 3145 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3146 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3147 ahd->msgout_len++; 3148 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3149 #ifdef AHD_DEBUG 3150 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3151 printf("Setting up for Parity Error delivery\n"); 3152 #endif 3153 return; 3154 } else if (scb == NULL) { 3155 printf("%s: WARNING. No pending message for " 3156 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3157 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3158 ahd->msgout_len++; 3159 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3160 return; 3161 } 3162 3163 if ((scb->flags & SCB_DEVICE_RESET) == 0 3164 && (scb->flags & SCB_PACKETIZED) == 0 3165 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3166 u_int identify_msg; 3167 3168 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3169 if ((scb->hscb->control & DISCENB) != 0) 3170 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3171 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3172 ahd->msgout_len++; 3173 3174 if ((scb->hscb->control & TAG_ENB) != 0) { 3175 ahd->msgout_buf[ahd->msgout_index++] = 3176 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3177 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3178 ahd->msgout_len += 2; 3179 } 3180 } 3181 3182 if (scb->flags & SCB_DEVICE_RESET) { 3183 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3184 ahd->msgout_len++; 3185 ahd_print_path(ahd, scb); 3186 printf("Bus Device Reset Message Sent\n"); 3187 /* 3188 * Clear our selection hardware in advance of 3189 * the busfree. We may have an entry in the waiting 3190 * Q for this target, and we don't want to go about 3191 * selecting while we handle the busfree and blow it 3192 * away. 3193 */ 3194 ahd_outb(ahd, SCSISEQ0, 0); 3195 } else if ((scb->flags & SCB_ABORT) != 0) { 3196 3197 if ((scb->hscb->control & TAG_ENB) != 0) { 3198 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3199 } else { 3200 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3201 } 3202 ahd->msgout_len++; 3203 ahd_print_path(ahd, scb); 3204 printf("Abort%s Message Sent\n", 3205 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3206 /* 3207 * Clear our selection hardware in advance of 3208 * the busfree. We may have an entry in the waiting 3209 * Q for this target, and we don't want to go about 3210 * selecting while we handle the busfree and blow it 3211 * away. 3212 */ 3213 ahd_outb(ahd, SCSISEQ0, 0); 3214 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3215 ahd_build_transfer_msg(ahd, devinfo); 3216 /* 3217 * Clear our selection hardware in advance of potential 3218 * PPR IU status change busfree. We may have an entry in 3219 * the waiting Q for this target, and we don't want to go 3220 * about selecting while we handle the busfree and blow 3221 * it away. 3222 */ 3223 ahd_outb(ahd, SCSISEQ0, 0); 3224 } else { 3225 printf("ahd_intr: AWAITING_MSG for an SCB that " 3226 "does not have a waiting message\n"); 3227 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3228 devinfo->target_mask); 3229 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3230 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3231 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3232 scb->flags); 3233 } 3234 3235 /* 3236 * Clear the MK_MESSAGE flag from the SCB so we aren't 3237 * asked to send this message again. 3238 */ 3239 ahd_outb(ahd, SCB_CONTROL, 3240 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3241 scb->hscb->control &= ~MK_MESSAGE; 3242 ahd->msgout_index = 0; 3243 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3244 } 3245 3246 /* 3247 * Build an appropriate transfer negotiation message for the 3248 * currently active target. 3249 */ 3250 static void 3251 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3252 { 3253 /* 3254 * We need to initiate transfer negotiations. 3255 * If our current and goal settings are identical, 3256 * we want to renegotiate due to a check condition. 3257 */ 3258 struct ahd_initiator_tinfo *tinfo; 3259 struct ahd_tmode_tstate *tstate; 3260 int dowide; 3261 int dosync; 3262 int doppr; 3263 u_int period; 3264 u_int ppr_options; 3265 u_int offset; 3266 3267 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3268 devinfo->target, &tstate); 3269 /* 3270 * Filter our period based on the current connection. 3271 * If we can't perform DT transfers on this segment (not in LVD 3272 * mode for instance), then our decision to issue a PPR message 3273 * may change. 3274 */ 3275 period = tinfo->goal.period; 3276 offset = tinfo->goal.offset; 3277 ppr_options = tinfo->goal.ppr_options; 3278 /* Target initiated PPR is not allowed in the SCSI spec */ 3279 if (devinfo->role == ROLE_TARGET) 3280 ppr_options = 0; 3281 ahd_devlimited_syncrate(ahd, tinfo, &period, 3282 &ppr_options, devinfo->role); 3283 dowide = tinfo->curr.width != tinfo->goal.width; 3284 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3285 /* 3286 * Only use PPR if we have options that need it, even if the device 3287 * claims to support it. There might be an expander in the way 3288 * that doesn't. 3289 */ 3290 doppr = ppr_options != 0; 3291 3292 if (!dowide && !dosync && !doppr) { 3293 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3294 dosync = tinfo->goal.offset != 0; 3295 } 3296 3297 if (!dowide && !dosync && !doppr) { 3298 /* 3299 * Force async with a WDTR message if we have a wide bus, 3300 * or just issue an SDTR with a 0 offset. 3301 */ 3302 if ((ahd->features & AHD_WIDE) != 0) 3303 dowide = 1; 3304 else 3305 dosync = 1; 3306 3307 if (bootverbose) { 3308 ahd_print_devinfo(ahd, devinfo); 3309 printf("Ensuring async\n"); 3310 } 3311 } 3312 /* Target initiated PPR is not allowed in the SCSI spec */ 3313 if (devinfo->role == ROLE_TARGET) 3314 doppr = 0; 3315 3316 /* 3317 * Both the PPR message and SDTR message require the 3318 * goal syncrate to be limited to what the target device 3319 * is capable of handling (based on whether an LVD->SE 3320 * expander is on the bus), so combine these two cases. 3321 * Regardless, guarantee that if we are using WDTR and SDTR 3322 * messages that WDTR comes first. 3323 */ 3324 if (doppr || (dosync && !dowide)) { 3325 3326 offset = tinfo->goal.offset; 3327 ahd_validate_offset(ahd, tinfo, period, &offset, 3328 doppr ? tinfo->goal.width 3329 : tinfo->curr.width, 3330 devinfo->role); 3331 if (doppr) { 3332 ahd_construct_ppr(ahd, devinfo, period, offset, 3333 tinfo->goal.width, ppr_options); 3334 } else { 3335 ahd_construct_sdtr(ahd, devinfo, period, offset); 3336 } 3337 } else { 3338 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3339 } 3340 } 3341 3342 /* 3343 * Build a synchronous negotiation message in our message 3344 * buffer based on the input parameters. 3345 */ 3346 static void 3347 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3348 u_int period, u_int offset) 3349 { 3350 if (offset == 0) 3351 period = AHD_ASYNC_XFER_PERIOD; 3352 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3353 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3354 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3355 ahd->msgout_buf[ahd->msgout_index++] = period; 3356 ahd->msgout_buf[ahd->msgout_index++] = offset; 3357 ahd->msgout_len += 5; 3358 if (bootverbose) { 3359 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3360 ahd_name(ahd), devinfo->channel, devinfo->target, 3361 devinfo->lun, period, offset); 3362 } 3363 } 3364 3365 /* 3366 * Build a wide negotiateion message in our message 3367 * buffer based on the input parameters. 3368 */ 3369 static void 3370 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3371 u_int bus_width) 3372 { 3373 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3374 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3375 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3376 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3377 ahd->msgout_len += 4; 3378 if (bootverbose) { 3379 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3380 ahd_name(ahd), devinfo->channel, devinfo->target, 3381 devinfo->lun, bus_width); 3382 } 3383 } 3384 3385 /* 3386 * Build a parallel protocol request message in our message 3387 * buffer based on the input parameters. 3388 */ 3389 static void 3390 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3391 u_int period, u_int offset, u_int bus_width, 3392 u_int ppr_options) 3393 { 3394 /* 3395 * Always request precompensation from 3396 * the other target if we are running 3397 * at paced syncrates. 3398 */ 3399 if (period <= AHD_SYNCRATE_PACED) 3400 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3401 if (offset == 0) 3402 period = AHD_ASYNC_XFER_PERIOD; 3403 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3404 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3405 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3406 ahd->msgout_buf[ahd->msgout_index++] = period; 3407 ahd->msgout_buf[ahd->msgout_index++] = 0; 3408 ahd->msgout_buf[ahd->msgout_index++] = offset; 3409 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3410 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3411 ahd->msgout_len += 8; 3412 if (bootverbose) { 3413 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3414 "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3415 devinfo->channel, devinfo->target, devinfo->lun, 3416 bus_width, period, offset, ppr_options); 3417 } 3418 } 3419 3420 /* 3421 * Clear any active message state. 3422 */ 3423 static void 3424 ahd_clear_msg_state(struct ahd_softc *ahd) 3425 { 3426 ahd_mode_state saved_modes; 3427 3428 saved_modes = ahd_save_modes(ahd); 3429 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3430 ahd->send_msg_perror = 0; 3431 ahd->msg_flags = MSG_FLAG_NONE; 3432 ahd->msgout_len = 0; 3433 ahd->msgin_index = 0; 3434 ahd->msg_type = MSG_TYPE_NONE; 3435 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3436 /* 3437 * The target didn't care to respond to our 3438 * message request, so clear ATN. 3439 */ 3440 ahd_outb(ahd, CLRSINT1, CLRATNO); 3441 } 3442 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3443 ahd_outb(ahd, SEQ_FLAGS2, 3444 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3445 ahd_restore_modes(ahd, saved_modes); 3446 } 3447 3448 /* 3449 * Manual message loop handler. 3450 */ 3451 static void 3452 ahd_handle_message_phase(struct ahd_softc *ahd) 3453 { 3454 struct ahd_devinfo devinfo; 3455 u_int bus_phase; 3456 int end_session; 3457 3458 ahd_fetch_devinfo(ahd, &devinfo); 3459 end_session = FALSE; 3460 bus_phase = ahd_inb(ahd, LASTPHASE); 3461 3462 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3463 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3464 ahd_outb(ahd, LQCTL2, LQIRETRY); 3465 } 3466 reswitch: 3467 switch (ahd->msg_type) { 3468 case MSG_TYPE_INITIATOR_MSGOUT: 3469 { 3470 int lastbyte; 3471 int phasemis; 3472 int msgdone; 3473 3474 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3475 panic("HOST_MSG_LOOP interrupt with no active message"); 3476 3477 #ifdef AHD_DEBUG 3478 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3479 ahd_print_devinfo(ahd, &devinfo); 3480 printf("INITIATOR_MSG_OUT"); 3481 } 3482 #endif 3483 phasemis = bus_phase != P_MESGOUT; 3484 if (phasemis) { 3485 #ifdef AHD_DEBUG 3486 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3487 printf(" PHASEMIS %s\n", 3488 ahd_lookup_phase_entry(bus_phase) 3489 ->phasemsg); 3490 } 3491 #endif 3492 if (bus_phase == P_MESGIN) { 3493 /* 3494 * Change gears and see if 3495 * this messages is of interest to 3496 * us or should be passed back to 3497 * the sequencer. 3498 */ 3499 ahd_outb(ahd, CLRSINT1, CLRATNO); 3500 ahd->send_msg_perror = 0; 3501 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3502 ahd->msgin_index = 0; 3503 goto reswitch; 3504 } 3505 end_session = TRUE; 3506 break; 3507 } 3508 3509 if (ahd->send_msg_perror) { 3510 ahd_outb(ahd, CLRSINT1, CLRATNO); 3511 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3512 #ifdef AHD_DEBUG 3513 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3514 printf(" byte 0x%x\n", ahd->send_msg_perror); 3515 #endif 3516 /* 3517 * If we are notifying the target of a CRC error 3518 * during packetized operations, the target is 3519 * within its rights to acknowledge our message 3520 * with a busfree. 3521 */ 3522 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3523 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3524 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3525 3526 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3527 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3528 break; 3529 } 3530 3531 msgdone = ahd->msgout_index == ahd->msgout_len; 3532 if (msgdone) { 3533 /* 3534 * The target has requested a retry. 3535 * Re-assert ATN, reset our message index to 3536 * 0, and try again. 3537 */ 3538 ahd->msgout_index = 0; 3539 ahd_assert_atn(ahd); 3540 } 3541 3542 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3543 if (lastbyte) { 3544 /* Last byte is signified by dropping ATN */ 3545 ahd_outb(ahd, CLRSINT1, CLRATNO); 3546 } 3547 3548 /* 3549 * Clear our interrupt status and present 3550 * the next byte on the bus. 3551 */ 3552 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3553 #ifdef AHD_DEBUG 3554 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3555 printf(" byte 0x%x\n", 3556 ahd->msgout_buf[ahd->msgout_index]); 3557 #endif 3558 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3559 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3560 break; 3561 } 3562 case MSG_TYPE_INITIATOR_MSGIN: 3563 { 3564 int phasemis; 3565 int message_done; 3566 3567 #ifdef AHD_DEBUG 3568 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3569 ahd_print_devinfo(ahd, &devinfo); 3570 printf("INITIATOR_MSG_IN"); 3571 } 3572 #endif 3573 phasemis = bus_phase != P_MESGIN; 3574 if (phasemis) { 3575 #ifdef AHD_DEBUG 3576 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3577 printf(" PHASEMIS %s\n", 3578 ahd_lookup_phase_entry(bus_phase) 3579 ->phasemsg); 3580 } 3581 #endif 3582 ahd->msgin_index = 0; 3583 if (bus_phase == P_MESGOUT 3584 && (ahd->send_msg_perror != 0 3585 || (ahd->msgout_len != 0 3586 && ahd->msgout_index == 0))) { 3587 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3588 goto reswitch; 3589 } 3590 end_session = TRUE; 3591 break; 3592 } 3593 3594 /* Pull the byte in without acking it */ 3595 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3596 #ifdef AHD_DEBUG 3597 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3598 printf(" byte 0x%x\n", 3599 ahd->msgin_buf[ahd->msgin_index]); 3600 #endif 3601 3602 message_done = ahd_parse_msg(ahd, &devinfo); 3603 3604 if (message_done) { 3605 /* 3606 * Clear our incoming message buffer in case there 3607 * is another message following this one. 3608 */ 3609 ahd->msgin_index = 0; 3610 3611 /* 3612 * If this message illicited a response, 3613 * assert ATN so the target takes us to the 3614 * message out phase. 3615 */ 3616 if (ahd->msgout_len != 0) { 3617 #ifdef AHD_DEBUG 3618 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3619 ahd_print_devinfo(ahd, &devinfo); 3620 printf("Asserting ATN for response\n"); 3621 } 3622 #endif 3623 ahd_assert_atn(ahd); 3624 } 3625 } else 3626 ahd->msgin_index++; 3627 3628 if (message_done == MSGLOOP_TERMINATED) { 3629 end_session = TRUE; 3630 } else { 3631 /* Ack the byte */ 3632 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3633 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3634 } 3635 break; 3636 } 3637 case MSG_TYPE_TARGET_MSGIN: 3638 { 3639 int msgdone; 3640 int msgout_request; 3641 3642 /* 3643 * By default, the message loop will continue. 3644 */ 3645 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3646 3647 if (ahd->msgout_len == 0) 3648 panic("Target MSGIN with no active message"); 3649 3650 /* 3651 * If we interrupted a mesgout session, the initiator 3652 * will not know this until our first REQ. So, we 3653 * only honor mesgout requests after we've sent our 3654 * first byte. 3655 */ 3656 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3657 && ahd->msgout_index > 0) 3658 msgout_request = TRUE; 3659 else 3660 msgout_request = FALSE; 3661 3662 if (msgout_request) { 3663 3664 /* 3665 * Change gears and see if 3666 * this messages is of interest to 3667 * us or should be passed back to 3668 * the sequencer. 3669 */ 3670 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3671 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3672 ahd->msgin_index = 0; 3673 /* Dummy read to REQ for first byte */ 3674 ahd_inb(ahd, SCSIDAT); 3675 ahd_outb(ahd, SXFRCTL0, 3676 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3677 break; 3678 } 3679 3680 msgdone = ahd->msgout_index == ahd->msgout_len; 3681 if (msgdone) { 3682 ahd_outb(ahd, SXFRCTL0, 3683 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3684 end_session = TRUE; 3685 break; 3686 } 3687 3688 /* 3689 * Present the next byte on the bus. 3690 */ 3691 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3692 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3693 break; 3694 } 3695 case MSG_TYPE_TARGET_MSGOUT: 3696 { 3697 int lastbyte; 3698 int msgdone; 3699 3700 /* 3701 * By default, the message loop will continue. 3702 */ 3703 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3704 3705 /* 3706 * The initiator signals that this is 3707 * the last byte by dropping ATN. 3708 */ 3709 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3710 3711 /* 3712 * Read the latched byte, but turn off SPIOEN first 3713 * so that we don't inadvertently cause a REQ for the 3714 * next byte. 3715 */ 3716 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3717 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3718 msgdone = ahd_parse_msg(ahd, &devinfo); 3719 if (msgdone == MSGLOOP_TERMINATED) { 3720 /* 3721 * The message is *really* done in that it caused 3722 * us to go to bus free. The sequencer has already 3723 * been reset at this point, so pull the ejection 3724 * handle. 3725 */ 3726 return; 3727 } 3728 3729 ahd->msgin_index++; 3730 3731 /* 3732 * XXX Read spec about initiator dropping ATN too soon 3733 * and use msgdone to detect it. 3734 */ 3735 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3736 ahd->msgin_index = 0; 3737 3738 /* 3739 * If this message illicited a response, transition 3740 * to the Message in phase and send it. 3741 */ 3742 if (ahd->msgout_len != 0) { 3743 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3744 ahd_outb(ahd, SXFRCTL0, 3745 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3746 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3747 ahd->msgin_index = 0; 3748 break; 3749 } 3750 } 3751 3752 if (lastbyte) 3753 end_session = TRUE; 3754 else { 3755 /* Ask for the next byte. */ 3756 ahd_outb(ahd, SXFRCTL0, 3757 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3758 } 3759 3760 break; 3761 } 3762 default: 3763 panic("Unknown REQINIT message type"); 3764 } 3765 3766 if (end_session) { 3767 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3768 printf("%s: Returning to Idle Loop\n", 3769 ahd_name(ahd)); 3770 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3771 ahd_clear_msg_state(ahd); 3772 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3773 } else { 3774 ahd_clear_msg_state(ahd); 3775 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3776 } 3777 } 3778 } 3779 3780 /* 3781 * See if we sent a particular extended message to the target. 3782 * If "full" is true, return true only if the target saw the full 3783 * message. If "full" is false, return true if the target saw at 3784 * least the first byte of the message. 3785 */ 3786 static int 3787 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3788 { 3789 int found; 3790 u_int index; 3791 3792 found = FALSE; 3793 index = 0; 3794 3795 while (index < ahd->msgout_len) { 3796 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3797 u_int end_index; 3798 3799 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3800 if (ahd->msgout_buf[index+2] == msgval 3801 && type == AHDMSG_EXT) { 3802 3803 if (full) { 3804 if (ahd->msgout_index > end_index) 3805 found = TRUE; 3806 } else if (ahd->msgout_index > index) 3807 found = TRUE; 3808 } 3809 index = end_index; 3810 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3811 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3812 3813 /* Skip tag type and tag id or residue param*/ 3814 index += 2; 3815 } else { 3816 /* Single byte message */ 3817 if (type == AHDMSG_1B 3818 && ahd->msgout_index > index 3819 && (ahd->msgout_buf[index] == msgval 3820 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3821 && msgval == MSG_IDENTIFYFLAG))) 3822 found = TRUE; 3823 index++; 3824 } 3825 3826 if (found) 3827 break; 3828 } 3829 return (found); 3830 } 3831 3832 /* 3833 * Wait for a complete incoming message, parse it, and respond accordingly. 3834 */ 3835 static int 3836 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3837 { 3838 struct ahd_initiator_tinfo *tinfo; 3839 struct ahd_tmode_tstate *tstate; 3840 int reject; 3841 int done; 3842 int response; 3843 3844 done = MSGLOOP_IN_PROG; 3845 response = FALSE; 3846 reject = FALSE; 3847 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3848 devinfo->target, &tstate); 3849 3850 /* 3851 * Parse as much of the message as is available, 3852 * rejecting it if we don't support it. When 3853 * the entire message is available and has been 3854 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3855 * that we have parsed an entire message. 3856 * 3857 * In the case of extended messages, we accept the length 3858 * byte outright and perform more checking once we know the 3859 * extended message type. 3860 */ 3861 switch (ahd->msgin_buf[0]) { 3862 case MSG_DISCONNECT: 3863 case MSG_SAVEDATAPOINTER: 3864 case MSG_CMDCOMPLETE: 3865 case MSG_RESTOREPOINTERS: 3866 case MSG_IGN_WIDE_RESIDUE: 3867 /* 3868 * End our message loop as these are messages 3869 * the sequencer handles on its own. 3870 */ 3871 done = MSGLOOP_TERMINATED; 3872 break; 3873 case MSG_MESSAGE_REJECT: 3874 response = ahd_handle_msg_reject(ahd, devinfo); 3875 /* FALLTHROUGH */ 3876 case MSG_NOOP: 3877 done = MSGLOOP_MSGCOMPLETE; 3878 break; 3879 case MSG_EXTENDED: 3880 { 3881 /* Wait for enough of the message to begin validation */ 3882 if (ahd->msgin_index < 2) 3883 break; 3884 switch (ahd->msgin_buf[2]) { 3885 case MSG_EXT_SDTR: 3886 { 3887 u_int period; 3888 u_int ppr_options; 3889 u_int offset; 3890 u_int saved_offset; 3891 3892 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3893 reject = TRUE; 3894 break; 3895 } 3896 3897 /* 3898 * Wait until we have both args before validating 3899 * and acting on this message. 3900 * 3901 * Add one to MSG_EXT_SDTR_LEN to account for 3902 * the extended message preamble. 3903 */ 3904 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3905 break; 3906 3907 period = ahd->msgin_buf[3]; 3908 ppr_options = 0; 3909 saved_offset = offset = ahd->msgin_buf[4]; 3910 ahd_devlimited_syncrate(ahd, tinfo, &period, 3911 &ppr_options, devinfo->role); 3912 ahd_validate_offset(ahd, tinfo, period, &offset, 3913 tinfo->curr.width, devinfo->role); 3914 if (bootverbose) { 3915 printf("(%s:%c:%d:%d): Received " 3916 "SDTR period %x, offset %x\n\t" 3917 "Filtered to period %x, offset %x\n", 3918 ahd_name(ahd), devinfo->channel, 3919 devinfo->target, devinfo->lun, 3920 ahd->msgin_buf[3], saved_offset, 3921 period, offset); 3922 } 3923 ahd_set_syncrate(ahd, devinfo, period, 3924 offset, ppr_options, 3925 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3926 /*paused*/TRUE); 3927 3928 /* 3929 * See if we initiated Sync Negotiation 3930 * and didn't have to fall down to async 3931 * transfers. 3932 */ 3933 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3934 /* We started it */ 3935 if (saved_offset != offset) { 3936 /* Went too low - force async */ 3937 reject = TRUE; 3938 } 3939 } else { 3940 /* 3941 * Send our own SDTR in reply 3942 */ 3943 if (bootverbose 3944 && devinfo->role == ROLE_INITIATOR) { 3945 printf("(%s:%c:%d:%d): Target " 3946 "Initiated SDTR\n", 3947 ahd_name(ahd), devinfo->channel, 3948 devinfo->target, devinfo->lun); 3949 } 3950 ahd->msgout_index = 0; 3951 ahd->msgout_len = 0; 3952 ahd_construct_sdtr(ahd, devinfo, 3953 period, offset); 3954 ahd->msgout_index = 0; 3955 response = TRUE; 3956 } 3957 done = MSGLOOP_MSGCOMPLETE; 3958 break; 3959 } 3960 case MSG_EXT_WDTR: 3961 { 3962 u_int bus_width; 3963 u_int saved_width; 3964 u_int sending_reply; 3965 3966 sending_reply = FALSE; 3967 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3968 reject = TRUE; 3969 break; 3970 } 3971 3972 /* 3973 * Wait until we have our arg before validating 3974 * and acting on this message. 3975 * 3976 * Add one to MSG_EXT_WDTR_LEN to account for 3977 * the extended message preamble. 3978 */ 3979 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3980 break; 3981 3982 bus_width = ahd->msgin_buf[3]; 3983 saved_width = bus_width; 3984 ahd_validate_width(ahd, tinfo, &bus_width, 3985 devinfo->role); 3986 if (bootverbose) { 3987 printf("(%s:%c:%d:%d): Received WDTR " 3988 "%x filtered to %x\n", 3989 ahd_name(ahd), devinfo->channel, 3990 devinfo->target, devinfo->lun, 3991 saved_width, bus_width); 3992 } 3993 3994 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3995 /* 3996 * Don't send a WDTR back to the 3997 * target, since we asked first. 3998 * If the width went higher than our 3999 * request, reject it. 4000 */ 4001 if (saved_width > bus_width) { 4002 reject = TRUE; 4003 printf("(%s:%c:%d:%d): requested %dBit " 4004 "transfers. Rejecting...\n", 4005 ahd_name(ahd), devinfo->channel, 4006 devinfo->target, devinfo->lun, 4007 8 * (0x01 << bus_width)); 4008 bus_width = 0; 4009 } 4010 } else { 4011 /* 4012 * Send our own WDTR in reply 4013 */ 4014 if (bootverbose 4015 && devinfo->role == ROLE_INITIATOR) { 4016 printf("(%s:%c:%d:%d): Target " 4017 "Initiated WDTR\n", 4018 ahd_name(ahd), devinfo->channel, 4019 devinfo->target, devinfo->lun); 4020 } 4021 ahd->msgout_index = 0; 4022 ahd->msgout_len = 0; 4023 ahd_construct_wdtr(ahd, devinfo, bus_width); 4024 ahd->msgout_index = 0; 4025 response = TRUE; 4026 sending_reply = TRUE; 4027 } 4028 /* 4029 * After a wide message, we are async, but 4030 * some devices don't seem to honor this portion 4031 * of the spec. Force a renegotiation of the 4032 * sync component of our transfer agreement even 4033 * if our goal is async. By updating our width 4034 * after forcing the negotiation, we avoid 4035 * renegotiating for width. 4036 */ 4037 ahd_update_neg_request(ahd, devinfo, tstate, 4038 tinfo, AHD_NEG_ALWAYS); 4039 ahd_set_width(ahd, devinfo, bus_width, 4040 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4041 /*paused*/TRUE); 4042 if (sending_reply == FALSE && reject == FALSE) { 4043 4044 /* 4045 * We will always have an SDTR to send. 4046 */ 4047 ahd->msgout_index = 0; 4048 ahd->msgout_len = 0; 4049 ahd_build_transfer_msg(ahd, devinfo); 4050 ahd->msgout_index = 0; 4051 response = TRUE; 4052 } 4053 done = MSGLOOP_MSGCOMPLETE; 4054 break; 4055 } 4056 case MSG_EXT_PPR: 4057 { 4058 u_int period; 4059 u_int offset; 4060 u_int bus_width; 4061 u_int ppr_options; 4062 u_int saved_width; 4063 u_int saved_offset; 4064 u_int saved_ppr_options; 4065 4066 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4067 reject = TRUE; 4068 break; 4069 } 4070 4071 /* 4072 * Wait until we have all args before validating 4073 * and acting on this message. 4074 * 4075 * Add one to MSG_EXT_PPR_LEN to account for 4076 * the extended message preamble. 4077 */ 4078 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4079 break; 4080 4081 period = ahd->msgin_buf[3]; 4082 offset = ahd->msgin_buf[5]; 4083 bus_width = ahd->msgin_buf[6]; 4084 saved_width = bus_width; 4085 ppr_options = ahd->msgin_buf[7]; 4086 /* 4087 * According to the spec, a DT only 4088 * period factor with no DT option 4089 * set implies async. 4090 */ 4091 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4092 && period <= 9) 4093 offset = 0; 4094 saved_ppr_options = ppr_options; 4095 saved_offset = offset; 4096 4097 /* 4098 * Transfer options are only available if we 4099 * are negotiating wide. 4100 */ 4101 if (bus_width == 0) 4102 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4103 4104 ahd_validate_width(ahd, tinfo, &bus_width, 4105 devinfo->role); 4106 ahd_devlimited_syncrate(ahd, tinfo, &period, 4107 &ppr_options, devinfo->role); 4108 ahd_validate_offset(ahd, tinfo, period, &offset, 4109 bus_width, devinfo->role); 4110 4111 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4112 /* 4113 * If we are unable to do any of the 4114 * requested options (we went too low), 4115 * then we'll have to reject the message. 4116 */ 4117 if (saved_width > bus_width 4118 || saved_offset != offset 4119 || saved_ppr_options != ppr_options) { 4120 reject = TRUE; 4121 period = 0; 4122 offset = 0; 4123 bus_width = 0; 4124 ppr_options = 0; 4125 } 4126 } else { 4127 if (devinfo->role != ROLE_TARGET) 4128 printf("(%s:%c:%d:%d): Target " 4129 "Initiated PPR\n", 4130 ahd_name(ahd), devinfo->channel, 4131 devinfo->target, devinfo->lun); 4132 else 4133 printf("(%s:%c:%d:%d): Initiator " 4134 "Initiated PPR\n", 4135 ahd_name(ahd), devinfo->channel, 4136 devinfo->target, devinfo->lun); 4137 ahd->msgout_index = 0; 4138 ahd->msgout_len = 0; 4139 ahd_construct_ppr(ahd, devinfo, period, offset, 4140 bus_width, ppr_options); 4141 ahd->msgout_index = 0; 4142 response = TRUE; 4143 } 4144 if (bootverbose) { 4145 printf("(%s:%c:%d:%d): Received PPR width %x, " 4146 "period %x, offset %x,options %x\n" 4147 "\tFiltered to width %x, period %x, " 4148 "offset %x, options %x\n", 4149 ahd_name(ahd), devinfo->channel, 4150 devinfo->target, devinfo->lun, 4151 saved_width, ahd->msgin_buf[3], 4152 saved_offset, saved_ppr_options, 4153 bus_width, period, offset, ppr_options); 4154 } 4155 ahd_set_width(ahd, devinfo, bus_width, 4156 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4157 /*paused*/TRUE); 4158 ahd_set_syncrate(ahd, devinfo, period, 4159 offset, ppr_options, 4160 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4161 /*paused*/TRUE); 4162 4163 done = MSGLOOP_MSGCOMPLETE; 4164 break; 4165 } 4166 default: 4167 /* Unknown extended message. Reject it. */ 4168 reject = TRUE; 4169 break; 4170 } 4171 break; 4172 } 4173 #ifdef AHD_TARGET_MODE 4174 case MSG_BUS_DEV_RESET: 4175 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4176 CAM_BDR_SENT, 4177 "Bus Device Reset Received", 4178 /*verbose_level*/0); 4179 ahd_restart(ahd); 4180 done = MSGLOOP_TERMINATED; 4181 break; 4182 case MSG_ABORT_TAG: 4183 case MSG_ABORT: 4184 case MSG_CLEAR_QUEUE: 4185 { 4186 int tag; 4187 4188 /* Target mode messages */ 4189 if (devinfo->role != ROLE_TARGET) { 4190 reject = TRUE; 4191 break; 4192 } 4193 tag = SCB_LIST_NULL; 4194 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4195 tag = ahd_inb(ahd, INITIATOR_TAG); 4196 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4197 devinfo->lun, tag, ROLE_TARGET, 4198 CAM_REQ_ABORTED); 4199 4200 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4201 if (tstate != NULL) { 4202 struct ahd_tmode_lstate* lstate; 4203 4204 lstate = tstate->enabled_luns[devinfo->lun]; 4205 if (lstate != NULL) { 4206 ahd_queue_lstate_event(ahd, lstate, 4207 devinfo->our_scsiid, 4208 ahd->msgin_buf[0], 4209 /*arg*/tag); 4210 ahd_send_lstate_events(ahd, lstate); 4211 } 4212 } 4213 ahd_restart(ahd); 4214 done = MSGLOOP_TERMINATED; 4215 break; 4216 } 4217 #endif 4218 case MSG_QAS_REQUEST: 4219 #ifdef AHD_DEBUG 4220 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4221 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4222 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4223 #endif 4224 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4225 /* FALLTHROUGH */ 4226 case MSG_TERM_IO_PROC: 4227 default: 4228 reject = TRUE; 4229 break; 4230 } 4231 4232 if (reject) { 4233 /* 4234 * Setup to reject the message. 4235 */ 4236 ahd->msgout_index = 0; 4237 ahd->msgout_len = 1; 4238 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4239 done = MSGLOOP_MSGCOMPLETE; 4240 response = TRUE; 4241 } 4242 4243 if (done != MSGLOOP_IN_PROG && !response) 4244 /* Clear the outgoing message buffer */ 4245 ahd->msgout_len = 0; 4246 4247 return (done); 4248 } 4249 4250 /* 4251 * Process a message reject message. 4252 */ 4253 static int 4254 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4255 { 4256 /* 4257 * What we care about here is if we had an 4258 * outstanding SDTR or WDTR message for this 4259 * target. If we did, this is a signal that 4260 * the target is refusing negotiation. 4261 */ 4262 struct scb *scb; 4263 struct ahd_initiator_tinfo *tinfo; 4264 struct ahd_tmode_tstate *tstate; 4265 u_int scb_index; 4266 u_int last_msg; 4267 int response = 0; 4268 4269 scb_index = ahd_get_scbptr(ahd); 4270 scb = ahd_lookup_scb(ahd, scb_index); 4271 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4272 devinfo->our_scsiid, 4273 devinfo->target, &tstate); 4274 /* Might be necessary */ 4275 last_msg = ahd_inb(ahd, LAST_MSG); 4276 4277 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4278 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4279 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4280 /* 4281 * Target may not like our SPI-4 PPR Options. 4282 * Attempt to negotiate 80MHz which will turn 4283 * off these options. 4284 */ 4285 if (bootverbose) { 4286 printf("(%s:%c:%d:%d): PPR Rejected. " 4287 "Trying simple U160 PPR\n", 4288 ahd_name(ahd), devinfo->channel, 4289 devinfo->target, devinfo->lun); 4290 } 4291 tinfo->goal.period = AHD_SYNCRATE_DT; 4292 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4293 | MSG_EXT_PPR_QAS_REQ 4294 | MSG_EXT_PPR_DT_REQ; 4295 } else { 4296 /* 4297 * Target does not support the PPR message. 4298 * Attempt to negotiate SPI-2 style. 4299 */ 4300 if (bootverbose) { 4301 printf("(%s:%c:%d:%d): PPR Rejected. " 4302 "Trying WDTR/SDTR\n", 4303 ahd_name(ahd), devinfo->channel, 4304 devinfo->target, devinfo->lun); 4305 } 4306 tinfo->goal.ppr_options = 0; 4307 tinfo->curr.transport_version = 2; 4308 tinfo->goal.transport_version = 2; 4309 } 4310 ahd->msgout_index = 0; 4311 ahd->msgout_len = 0; 4312 ahd_build_transfer_msg(ahd, devinfo); 4313 ahd->msgout_index = 0; 4314 response = 1; 4315 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4316 4317 /* note 8bit xfers */ 4318 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4319 "8bit transfers\n", ahd_name(ahd), 4320 devinfo->channel, devinfo->target, devinfo->lun); 4321 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4322 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4323 /*paused*/TRUE); 4324 /* 4325 * No need to clear the sync rate. If the target 4326 * did not accept the command, our syncrate is 4327 * unaffected. If the target started the negotiation, 4328 * but rejected our response, we already cleared the 4329 * sync rate before sending our WDTR. 4330 */ 4331 if (tinfo->goal.offset != tinfo->curr.offset) { 4332 4333 /* Start the sync negotiation */ 4334 ahd->msgout_index = 0; 4335 ahd->msgout_len = 0; 4336 ahd_build_transfer_msg(ahd, devinfo); 4337 ahd->msgout_index = 0; 4338 response = 1; 4339 } 4340 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4341 /* note asynch xfers and clear flag */ 4342 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4343 /*offset*/0, /*ppr_options*/0, 4344 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4345 /*paused*/TRUE); 4346 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4347 "Using asynchronous transfers\n", 4348 ahd_name(ahd), devinfo->channel, 4349 devinfo->target, devinfo->lun); 4350 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4351 int tag_type; 4352 int mask; 4353 4354 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4355 4356 if (tag_type == MSG_SIMPLE_TASK) { 4357 printf("(%s:%c:%d:%d): refuses tagged commands. " 4358 "Performing non-tagged I/O\n", ahd_name(ahd), 4359 devinfo->channel, devinfo->target, devinfo->lun); 4360 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4361 mask = ~0x23; 4362 } else { 4363 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4364 "Performing simple queue tagged I/O only\n", 4365 ahd_name(ahd), devinfo->channel, devinfo->target, 4366 devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4367 ? "ordered" : "head of queue"); 4368 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4369 mask = ~0x03; 4370 } 4371 4372 /* 4373 * Resend the identify for this CCB as the target 4374 * may believe that the selection is invalid otherwise. 4375 */ 4376 ahd_outb(ahd, SCB_CONTROL, 4377 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4378 scb->hscb->control &= mask; 4379 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4380 /*type*/MSG_SIMPLE_TASK); 4381 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4382 ahd_assert_atn(ahd); 4383 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4384 SCB_GET_TAG(scb)); 4385 4386 /* 4387 * Requeue all tagged commands for this target 4388 * currently in our posession so they can be 4389 * converted to untagged commands. 4390 */ 4391 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4392 SCB_GET_CHANNEL(ahd, scb), 4393 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4394 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4395 SEARCH_COMPLETE); 4396 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4397 /* 4398 * Most likely the device believes that we had 4399 * previously negotiated packetized. 4400 */ 4401 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4402 | MSG_FLAG_IU_REQ_CHANGED; 4403 4404 ahd_force_renegotiation(ahd, devinfo); 4405 ahd->msgout_index = 0; 4406 ahd->msgout_len = 0; 4407 ahd_build_transfer_msg(ahd, devinfo); 4408 ahd->msgout_index = 0; 4409 response = 1; 4410 } else { 4411 /* 4412 * Otherwise, we ignore it. 4413 */ 4414 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4415 ahd_name(ahd), devinfo->channel, devinfo->target, 4416 last_msg); 4417 } 4418 return (response); 4419 } 4420 4421 /* 4422 * Process an ignore wide residue message. 4423 */ 4424 static void 4425 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4426 { 4427 u_int scb_index; 4428 struct scb *scb; 4429 4430 printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4431 4432 scb_index = ahd_get_scbptr(ahd); 4433 scb = ahd_lookup_scb(ahd, scb_index); 4434 /* 4435 * XXX Actually check data direction in the sequencer? 4436 * Perhaps add datadir to some spare bits in the hscb? 4437 */ 4438 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4439 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4440 /* 4441 * Ignore the message if we haven't 4442 * seen an appropriate data phase yet. 4443 */ 4444 } else { 4445 /* 4446 * If the residual occurred on the last 4447 * transfer and the transfer request was 4448 * expected to end on an odd count, do 4449 * nothing. Otherwise, subtract a byte 4450 * and update the residual count accordingly. 4451 */ 4452 uint32_t sgptr; 4453 4454 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4455 if ((sgptr & SG_LIST_NULL) != 0 4456 && (ahd_inb(ahd, SCB_TASK_ATTRIBUTE) & SCB_XFERLEN_ODD) != 0) { 4457 /* 4458 * If the residual occurred on the last 4459 * transfer and the transfer request was 4460 * expected to end on an odd count, do 4461 * nothing. 4462 */ 4463 } else { 4464 uint32_t data_cnt; 4465 uint64_t data_addr; 4466 uint32_t sglen; 4467 4468 /* Pull in the rest of the sgptr */ 4469 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4470 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4471 if ((sgptr & SG_LIST_NULL) != 0) { 4472 /* 4473 * The residual data count is not updated 4474 * for the command run to completion case. 4475 * Explcitly zero the count. 4476 */ 4477 data_cnt &= ~AHD_SG_LEN_MASK; 4478 } 4479 data_addr = ahd_inq(ahd, SHADDR); 4480 data_cnt += 1; 4481 data_addr -= 1; 4482 sgptr &= SG_PTR_MASK; 4483 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4484 struct ahd_dma64_seg *sg; 4485 4486 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4487 4488 /* 4489 * The residual sg ptr points to the next S/G 4490 * to load so we must go back one. 4491 */ 4492 sg--; 4493 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4494 if (sg != scb->sg_list 4495 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4496 4497 sg--; 4498 sglen = ahd_le32toh(sg->len); 4499 /* 4500 * Preserve High Address and SG_LIST 4501 * bits while setting the count to 1. 4502 */ 4503 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4504 data_addr = ahd_le64toh(sg->addr) 4505 + (sglen & AHD_SG_LEN_MASK) 4506 - 1; 4507 4508 /* 4509 * Increment sg so it points to the 4510 * "next" sg. 4511 */ 4512 sg++; 4513 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4514 sg); 4515 } 4516 } else { 4517 struct ahd_dma_seg *sg; 4518 4519 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4520 4521 /* 4522 * The residual sg ptr points to the next S/G 4523 * to load so we must go back one. 4524 */ 4525 sg--; 4526 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4527 if (sg != scb->sg_list 4528 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4529 4530 sg--; 4531 sglen = ahd_le32toh(sg->len); 4532 /* 4533 * Preserve High Address and SG_LIST 4534 * bits while setting the count to 1. 4535 */ 4536 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4537 data_addr = ahd_le32toh(sg->addr) 4538 + (sglen & AHD_SG_LEN_MASK) 4539 - 1; 4540 4541 /* 4542 * Increment sg so it points to the 4543 * "next" sg. 4544 */ 4545 sg++; 4546 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4547 sg); 4548 } 4549 } 4550 /* 4551 * Toggle the "oddness" of the transfer length 4552 * to handle this mid-transfer ignore wide 4553 * residue. This ensures that the oddness is 4554 * correct for subsequent data transfers. 4555 */ 4556 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4557 ahd_inb(ahd, SCB_TASK_ATTRIBUTE) ^ SCB_XFERLEN_ODD); 4558 4559 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4560 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4561 /* 4562 * The FIFO's pointers will be updated if/when the 4563 * sequencer re-enters a data phase. 4564 */ 4565 } 4566 } 4567 } 4568 4569 4570 /* 4571 * Reinitialize the data pointers for the active transfer 4572 * based on its current residual. 4573 */ 4574 static void 4575 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4576 { 4577 struct scb *scb; 4578 ahd_mode_state saved_modes; 4579 u_int scb_index; 4580 u_int wait; 4581 uint32_t sgptr; 4582 uint32_t resid; 4583 uint64_t dataptr; 4584 4585 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4586 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4587 4588 scb_index = ahd_get_scbptr(ahd); 4589 scb = ahd_lookup_scb(ahd, scb_index); 4590 4591 /* 4592 * Release and reacquire the FIFO so we 4593 * have a clean slate. 4594 */ 4595 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4596 wait = 1000; 4597 do { 4598 ahd_delay(100); 4599 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)); 4600 if (wait == 0) { 4601 ahd_print_path(ahd, scb); 4602 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4603 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4604 } 4605 saved_modes = ahd_save_modes(ahd); 4606 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4607 ahd_outb(ahd, DFFSTAT, 4608 ahd_inb(ahd, DFFSTAT) 4609 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4610 4611 /* 4612 * Determine initial values for data_addr and data_cnt 4613 * for resuming the data phase. 4614 */ 4615 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4616 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4617 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4618 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4619 sgptr &= SG_PTR_MASK; 4620 4621 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4622 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4623 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4624 4625 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4626 struct ahd_dma64_seg *sg; 4627 4628 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4629 4630 /* The residual sg_ptr always points to the next sg */ 4631 sg--; 4632 4633 dataptr = ahd_le64toh(sg->addr) 4634 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4635 - resid; 4636 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4637 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4638 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4639 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4640 } else { 4641 struct ahd_dma_seg *sg; 4642 4643 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4644 4645 /* The residual sg_ptr always points to the next sg */ 4646 sg--; 4647 4648 dataptr = ahd_le32toh(sg->addr) 4649 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4650 - resid; 4651 ahd_outb(ahd, HADDR + 4, 4652 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4653 } 4654 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4655 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4656 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4657 ahd_outb(ahd, HADDR, dataptr); 4658 ahd_outb(ahd, HCNT + 2, resid >> 16); 4659 ahd_outb(ahd, HCNT + 1, resid >> 8); 4660 ahd_outb(ahd, HCNT, resid); 4661 } 4662 4663 /* 4664 * Handle the effects of issuing a bus device reset message. 4665 */ 4666 static void 4667 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4668 u_int lun, cam_status status, char *message, 4669 int verbose_level) 4670 { 4671 #ifdef AHD_TARGET_MODE 4672 struct ahd_tmode_tstate* tstate; 4673 #endif 4674 int found; 4675 4676 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4677 lun, SCB_LIST_NULL, devinfo->role, 4678 status); 4679 4680 #ifdef AHD_TARGET_MODE 4681 /* 4682 * Send an immediate notify ccb to all target mord peripheral 4683 * drivers affected by this action. 4684 */ 4685 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4686 if (tstate != NULL) { 4687 u_int cur_lun; 4688 u_int max_lun; 4689 4690 if (lun != CAM_LUN_WILDCARD) { 4691 cur_lun = 0; 4692 max_lun = AHD_NUM_LUNS - 1; 4693 } else { 4694 cur_lun = lun; 4695 max_lun = lun; 4696 } 4697 for (cur_lun <= max_lun; cur_lun++) { 4698 struct ahd_tmode_lstate* lstate; 4699 4700 lstate = tstate->enabled_luns[cur_lun]; 4701 if (lstate == NULL) 4702 continue; 4703 4704 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4705 MSG_BUS_DEV_RESET, /*arg*/0); 4706 ahd_send_lstate_events(ahd, lstate); 4707 } 4708 } 4709 #endif 4710 4711 /* 4712 * Go back to async/narrow transfers and renegotiate. 4713 */ 4714 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4715 AHD_TRANS_CUR, /*paused*/TRUE); 4716 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4717 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4718 4719 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4720 lun, AC_SENT_BDR, NULL); 4721 4722 if (message != NULL 4723 && (verbose_level <= bootverbose)) 4724 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4725 message, devinfo->channel, devinfo->target, found); 4726 } 4727 4728 #ifdef AHD_TARGET_MODE 4729 static void 4730 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4731 struct scb *scb) 4732 { 4733 4734 /* 4735 * To facilitate adding multiple messages together, 4736 * each routine should increment the index and len 4737 * variables instead of setting them explicitly. 4738 */ 4739 ahd->msgout_index = 0; 4740 ahd->msgout_len = 0; 4741 4742 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4743 ahd_build_transfer_msg(ahd, devinfo); 4744 else 4745 panic("ahd_intr: AWAITING target message with no message"); 4746 4747 ahd->msgout_index = 0; 4748 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4749 } 4750 #endif 4751 /**************************** Initialization **********************************/ 4752 static u_int 4753 ahd_sglist_size(struct ahd_softc *ahd) 4754 { 4755 bus_size_t list_size; 4756 4757 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4758 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4759 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4760 return (list_size); 4761 } 4762 4763 /* 4764 * Calculate the optimum S/G List allocation size. S/G elements used 4765 * for a given transaction must be physically contiguous. Assume the 4766 * OS will allocate full pages to us, so it doesn't make sense to request 4767 * less than a page. 4768 */ 4769 static u_int 4770 ahd_sglist_allocsize(struct ahd_softc *ahd) 4771 { 4772 bus_size_t sg_list_increment; 4773 bus_size_t sg_list_size; 4774 bus_size_t max_list_size; 4775 bus_size_t best_list_size; 4776 4777 /* Start out with the minimum required for AHD_NSEG. */ 4778 sg_list_increment = ahd_sglist_size(ahd); 4779 sg_list_size = sg_list_increment; 4780 4781 /* Get us as close as possible to a page in size. */ 4782 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4783 sg_list_size += sg_list_increment; 4784 4785 /* 4786 * Try to reduce the amount of wastage by allocating 4787 * multiple pages. 4788 */ 4789 best_list_size = sg_list_size; 4790 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4791 if (max_list_size < 4 * PAGE_SIZE) 4792 max_list_size = 4 * PAGE_SIZE; 4793 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4794 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4795 while ((sg_list_size + sg_list_increment) <= max_list_size 4796 && (sg_list_size % PAGE_SIZE) != 0) { 4797 bus_size_t new_mod; 4798 bus_size_t best_mod; 4799 4800 sg_list_size += sg_list_increment; 4801 new_mod = sg_list_size % PAGE_SIZE; 4802 best_mod = best_list_size % PAGE_SIZE; 4803 if (new_mod > best_mod || new_mod == 0) { 4804 best_list_size = sg_list_size; 4805 } 4806 } 4807 return (best_list_size); 4808 } 4809 4810 int 4811 ahd_softc_init(struct ahd_softc *ahd) 4812 { 4813 4814 ahd->unpause = 0; 4815 ahd->pause = PAUSE; 4816 return (0); 4817 } 4818 4819 void 4820 ahd_set_unit(struct ahd_softc *ahd, int unit) 4821 { 4822 ahd->unit = unit; 4823 } 4824 4825 void 4826 ahd_set_name(struct ahd_softc *ahd, char *name) 4827 { 4828 if (ahd->name != NULL) 4829 free(ahd->name, M_DEVBUF); 4830 ahd->name = name; 4831 } 4832 4833 void 4834 ahd_free(struct ahd_softc *ahd) 4835 { 4836 int i; 4837 4838 switch (ahd->init_level) { 4839 default: 4840 case 2: 4841 ahd_shutdown(ahd); 4842 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4843 /* FALLTHROUGH */ 4844 case 1: 4845 bus_dmamap_unload(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4846 bus_dmamap_destroy(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4847 bus_dmamem_unmap(ahd->parent_dmat, (caddr_t)ahd->qoutfifo, ahd->shared_data_size); 4848 bus_dmamem_free(ahd->parent_dmat, &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); 4849 break; 4850 case 0: 4851 break; 4852 } 4853 4854 ahd_platform_free(ahd); 4855 ahd_fini_scbdata(ahd); 4856 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4857 struct ahd_tmode_tstate *tstate; 4858 4859 tstate = ahd->enabled_targets[i]; 4860 if (tstate != NULL) { 4861 #if AHD_TARGET_MODE 4862 int j; 4863 4864 for (j = 0; j < AHD_NUM_LUNS; j++) { 4865 struct ahd_tmode_lstate *lstate; 4866 4867 lstate = tstate->enabled_luns[j]; 4868 if (lstate != NULL) { 4869 xpt_free_path(lstate->path); 4870 free(lstate, M_DEVBUF); 4871 } 4872 } 4873 #endif 4874 free(tstate, M_DEVBUF); 4875 } 4876 } 4877 #if AHD_TARGET_MODE 4878 if (ahd->black_hole != NULL) { 4879 xpt_free_path(ahd->black_hole->path); 4880 free(ahd->black_hole, M_DEVBUF); 4881 } 4882 #endif 4883 if (ahd->name != NULL) 4884 free(ahd->name, M_DEVBUF); 4885 if (ahd->seep_config != NULL) 4886 free(ahd->seep_config, M_DEVBUF); 4887 if (ahd->saved_stack != NULL) 4888 free(ahd->saved_stack, M_DEVBUF); 4889 #ifndef __FreeBSD__ 4890 free(ahd, M_DEVBUF); 4891 #endif 4892 return; 4893 } 4894 4895 void 4896 ahd_shutdown(void *arg) 4897 { 4898 struct ahd_softc *ahd; 4899 4900 ahd = (struct ahd_softc *)arg; 4901 4902 #ifdef AHD_DEBUG 4903 printf("%s: ahd_shutdown\n", ahd_name(ahd)); 4904 #endif 4905 /* 4906 * Stop periodic timer callbacks. 4907 */ 4908 ahd_timer_stop(&ahd->reset_timer); 4909 ahd_timer_stop(&ahd->stat_timer); 4910 4911 /* This will reset most registers to 0, but not all */ 4912 ahd_reset(ahd, /*reinit*/FALSE); 4913 } 4914 4915 /* 4916 * Reset the controller and record some information about it 4917 * that is only available just after a reset. If "reinit" is 4918 * non-zero, this reset occured after initial configuration 4919 * and the caller requests that the chip be fully reinitialized 4920 * to a runable state. Chip interrupts are *not* enabled after 4921 * a reinitialization. The caller must enable interrupts via 4922 * ahd_intr_enable(). 4923 */ 4924 int 4925 ahd_reset(struct ahd_softc *ahd, int reinit) 4926 { 4927 u_int sxfrctl1; 4928 int wait; 4929 uint32_t cmd; 4930 struct ahd_pci_busdata *bd = ahd->bus_data; 4931 4932 /* 4933 * Preserve the value of the SXFRCTL1 register for all channels. 4934 * It contains settings that affect termination and we don't want 4935 * to disturb the integrity of the bus. 4936 */ 4937 ahd_pause(ahd); 4938 ahd_update_modes(ahd); 4939 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4940 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4941 4942 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 4943 4944 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4945 uint32_t mod_cmd; 4946 4947 /* 4948 * A4 Razor #632 4949 * During the assertion of CHIPRST, the chip 4950 * does not disable its parity logic prior to 4951 * the start of the reset. This may cause a 4952 * parity error to be detected and thus a 4953 * spurious SERR or PERR assertion. Disble 4954 * PERR and SERR responses during the CHIPRST. 4955 */ 4956 mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 4957 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, mod_cmd); 4958 } 4959 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 4960 4961 /* 4962 * Ensure that the reset has finished. We delay 1000us 4963 * prior to reading the register to make sure the chip 4964 * has sufficiently completed its reset to handle register 4965 * accesses. 4966 */ 4967 wait = 1000; 4968 do { 4969 ahd_delay(1000); 4970 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 4971 4972 if (wait == 0) { 4973 printf("%s: WARNING - Failed chip reset! " 4974 "Trying to initialize anyway.\n", ahd_name(ahd)); 4975 } 4976 ahd_outb(ahd, HCNTRL, ahd->pause); 4977 4978 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4979 /* 4980 * Clear any latched PCI error status and restore 4981 * previous SERR and PERR response enables. 4982 */ 4983 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 0x000000FF); 4984 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 4985 PCI_COMMAND_SERR_ENABLE|PCI_COMMAND_PARITY_ENABLE); 4986 } 4987 4988 /* 4989 * Mode should be SCSI after a chip reset, but lets 4990 * set it just to be safe. We touch the MODE_PTR 4991 * register directly so as to bypass the lazy update 4992 * ode in ahd_set_modes(). 4993 */ 4994 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4995 ahd_outb(ahd, MODE_PTR, 4996 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 4997 4998 /* 4999 * Restore SXFRCTL1. 5000 * 5001 * We must always initialize STPWEN to 1 before we 5002 * restore the saved values. STPWEN is initialized 5003 * to a tri-state condition which can only be cleared 5004 * by turning it on. 5005 */ 5006 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5007 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5008 5009 /* Determine chip configuration */ 5010 ahd->features &= ~AHD_WIDE; 5011 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5012 ahd->features |= AHD_WIDE; 5013 5014 /* 5015 * If a recovery action has forced a chip reset, 5016 * re-initialize the chip to our liking. 5017 */ 5018 if (reinit != 0) 5019 ahd_chip_init(ahd); 5020 5021 return (0); 5022 } 5023 5024 /* 5025 * Determine the number of SCBs available on the controller 5026 */ 5027 int 5028 ahd_probe_scbs(struct ahd_softc *ahd) { 5029 int i; 5030 5031 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5032 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5033 for (i = 0; i < AHD_SCB_MAX; i++) { 5034 int j; 5035 int ret; 5036 5037 ahd_set_scbptr(ahd, i); 5038 ahd_outw(ahd, SCB_BASE, i); 5039 for (j = 2; j < 64; j++) 5040 ahd_outb(ahd, SCB_BASE+j, 0); 5041 /* Start out life as unallocated (needing an abort) */ 5042 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5043 ret = ahd_inw_scbram(ahd, SCB_BASE); 5044 if (ret != i) { 5045 printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", ahd_name(ahd), i, ret); 5046 break; 5047 } 5048 ahd_set_scbptr(ahd, 0); 5049 ret = ahd_inw_scbram(ahd, SCB_BASE); 5050 if (ret != 0) { 5051 printf("ahd_probe_scbs (non zero): returned 0x%x\n", ret); 5052 break; 5053 } 5054 } 5055 return (i); 5056 } 5057 5058 static void 5059 ahd_initialize_hscbs(struct ahd_softc *ahd) 5060 { 5061 int i; 5062 5063 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5064 ahd_set_scbptr(ahd, i); 5065 5066 /* Clear the control byte. */ 5067 ahd_outb(ahd, SCB_CONTROL, 0); 5068 5069 /* Set the next pointer */ 5070 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5071 } 5072 } 5073 5074 static int 5075 ahd_init_scbdata(struct ahd_softc *ahd) 5076 { 5077 struct scb_data *scb_data; 5078 int i; 5079 5080 scb_data = &ahd->scb_data; 5081 TAILQ_INIT(&scb_data->free_scbs); 5082 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5083 LIST_INIT(&scb_data->free_scb_lists[i]); 5084 LIST_INIT(&scb_data->any_dev_free_scb_list); 5085 SLIST_INIT(&scb_data->hscb_maps); 5086 SLIST_INIT(&scb_data->sg_maps); 5087 SLIST_INIT(&scb_data->sense_maps); 5088 5089 /* Determine the number of hardware SCBs and initialize them */ 5090 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5091 if (scb_data->maxhscbs == 0) { 5092 printf("%s: No SCB space found\n", ahd_name(ahd)); 5093 return (ENXIO); 5094 } 5095 ahd_initialize_hscbs(ahd); 5096 5097 /* 5098 * Create our DMA tags. These tags define the kinds of device 5099 * accessible memory allocations and memory mappings we will 5100 * need to perform during normal operation. 5101 * 5102 * Unless we need to further restrict the allocation, we rely 5103 * on the restrictions of the parent dmat, hence the common 5104 * use of MAXADDR and MAXSIZE. 5105 */ 5106 5107 /* Perform initial CCB allocation */ 5108 ahd_alloc_scbs(ahd); 5109 5110 if (scb_data->numscbs == 0) { 5111 printf("%s: ahd_init_scbdata - " 5112 "Unable to allocate initial scbs\n", 5113 ahd_name(ahd)); 5114 goto error_exit; 5115 } 5116 5117 /* 5118 * Note that we were successfull 5119 */ 5120 return (0); 5121 5122 error_exit: 5123 5124 return (ENOMEM); 5125 } 5126 5127 static struct scb * 5128 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5129 { 5130 struct scb *scb; 5131 5132 /* 5133 * Look on the pending list. 5134 */ 5135 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5136 if (SCB_GET_TAG(scb) == tag) 5137 return (scb); 5138 } 5139 5140 /* 5141 * Then on all of the collision free lists. 5142 */ 5143 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5144 struct scb *list_scb; 5145 5146 list_scb = scb; 5147 do { 5148 if (SCB_GET_TAG(list_scb) == tag) 5149 return (list_scb); 5150 list_scb = LIST_NEXT(list_scb, collision_links); 5151 } while (list_scb); 5152 } 5153 5154 /* 5155 * And finally on the generic free list. 5156 */ 5157 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5158 if (SCB_GET_TAG(scb) == tag) 5159 return (scb); 5160 } 5161 5162 return (NULL); 5163 } 5164 5165 static void 5166 ahd_fini_scbdata(struct ahd_softc *ahd) 5167 { 5168 struct scb_data *scb_data; 5169 5170 scb_data = &ahd->scb_data; 5171 if (scb_data == NULL) 5172 return; 5173 5174 switch (scb_data->init_level) { 5175 default: 5176 case 3: 5177 { 5178 struct map_node *sns_map; 5179 5180 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5181 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5182 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5183 sns_map->dmamap, (caddr_t)sns_map->vaddr, 5184 &sns_map->dmasegs, sns_map->nseg); 5185 free(sns_map, M_DEVBUF); 5186 } 5187 /* FALLTHROUGH */ 5188 } 5189 case 2: 5190 { 5191 struct map_node *sg_map; 5192 5193 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5194 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5195 ahd_freedmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), 5196 sg_map->dmamap, (caddr_t)sg_map->vaddr, 5197 &sg_map->dmasegs, sg_map->nseg); 5198 free(sg_map, M_DEVBUF); 5199 } 5200 /* FALLTHROUGH */ 5201 } 5202 case 1: 5203 { 5204 struct map_node *hscb_map; 5205 5206 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5207 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5208 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5209 hscb_map->dmamap, (caddr_t)hscb_map->vaddr, 5210 &hscb_map->dmasegs, hscb_map->nseg); 5211 free(hscb_map, M_DEVBUF); 5212 } 5213 /* FALLTHROUGH */ 5214 } 5215 case 0: 5216 break; 5217 } 5218 } 5219 5220 /* 5221 * DSP filter Bypass must be enabled until the first selection 5222 * after a change in bus mode (Razor #491 and #493). 5223 */ 5224 static void 5225 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5226 { 5227 ahd_mode_state saved_modes; 5228 5229 saved_modes = ahd_save_modes(ahd); 5230 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5231 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5232 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5233 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5234 #ifdef AHD_DEBUG 5235 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5236 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5237 #endif 5238 ahd_restore_modes(ahd, saved_modes); 5239 } 5240 5241 static void 5242 ahd_iocell_first_selection(struct ahd_softc *ahd) 5243 { 5244 ahd_mode_state saved_modes; 5245 u_int sblkctl; 5246 5247 saved_modes = ahd_save_modes(ahd); 5248 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5249 sblkctl = ahd_inb(ahd, SBLKCTL); 5250 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5251 #ifdef AHD_DEBUG 5252 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5253 printf("%s: iocell first selection\n", ahd_name(ahd)); 5254 #endif 5255 if ((sblkctl & ENAB40) != 0) { 5256 ahd_outb(ahd, DSPDATACTL, 5257 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5258 #ifdef AHD_DEBUG 5259 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5260 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5261 #endif 5262 } 5263 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5264 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5265 ahd_restore_modes(ahd, saved_modes); 5266 } 5267 5268 /*************************** SCB Management ***********************************/ 5269 static void 5270 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5271 { 5272 struct scb_list *free_list; 5273 struct scb_tailq *free_tailq; 5274 struct scb *first_scb; 5275 5276 scb->flags |= SCB_ON_COL_LIST; 5277 AHD_SET_SCB_COL_IDX(scb, col_idx); 5278 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5279 free_tailq = &ahd->scb_data.free_scbs; 5280 first_scb = LIST_FIRST(free_list); 5281 if (first_scb != NULL) { 5282 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5283 } else { 5284 LIST_INSERT_HEAD(free_list, scb, collision_links); 5285 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5286 } 5287 } 5288 5289 static void 5290 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5291 { 5292 struct scb_list *free_list; 5293 struct scb_tailq *free_tailq; 5294 struct scb *first_scb; 5295 u_int col_idx; 5296 5297 scb->flags &= ~SCB_ON_COL_LIST; 5298 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5299 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5300 free_tailq = &ahd->scb_data.free_scbs; 5301 first_scb = LIST_FIRST(free_list); 5302 if (first_scb == scb) { 5303 struct scb *next_scb; 5304 5305 /* 5306 * Maintain order in the collision free 5307 * lists for fairness if this device has 5308 * other colliding tags active. 5309 */ 5310 next_scb = LIST_NEXT(scb, collision_links); 5311 if (next_scb != NULL) { 5312 TAILQ_INSERT_AFTER(free_tailq, scb, 5313 next_scb, links.tqe); 5314 } 5315 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5316 } 5317 LIST_REMOVE(scb, collision_links); 5318 } 5319 5320 /* 5321 * Get a free scb. If there are none, see if we can allocate a new SCB. 5322 */ 5323 struct scb * 5324 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5325 { 5326 struct scb *scb; 5327 int tries; 5328 5329 tries = 0; 5330 look_again: 5331 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5332 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5333 ahd_rem_col_list(ahd, scb); 5334 goto found; 5335 } 5336 } 5337 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5338 5339 if (tries++ != 0) 5340 return (NULL); 5341 ahd_alloc_scbs(ahd); 5342 goto look_again; 5343 } 5344 LIST_REMOVE(scb, links.le); 5345 if (col_idx != AHD_NEVER_COL_IDX 5346 && (scb->col_scb != NULL) 5347 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5348 LIST_REMOVE(scb->col_scb, links.le); 5349 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5350 } 5351 found: 5352 scb->flags |= SCB_ACTIVE; 5353 return (scb); 5354 } 5355 5356 /* 5357 * Return an SCB resource to the free list. 5358 */ 5359 void 5360 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5361 { 5362 5363 /* Clean up for the next user */ 5364 scb->flags = SCB_FLAG_NONE; 5365 scb->hscb->control = 0; 5366 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5367 5368 if (scb->col_scb == NULL) { 5369 5370 /* 5371 * No collision possible. Just free normally. 5372 */ 5373 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5374 scb, links.le); 5375 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5376 5377 /* 5378 * The SCB we might have collided with is on 5379 * a free collision list. Put both SCBs on 5380 * the generic list. 5381 */ 5382 ahd_rem_col_list(ahd, scb->col_scb); 5383 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5384 scb, links.le); 5385 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5386 scb->col_scb, links.le); 5387 } else if ((scb->col_scb->flags 5388 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5389 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5390 5391 /* 5392 * The SCB we might collide with on the next allocation 5393 * is still active in a non-packetized, tagged, context. 5394 * Put us on the SCB collision list. 5395 */ 5396 ahd_add_col_list(ahd, scb, 5397 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5398 } else { 5399 /* 5400 * The SCB we might collide with on the next allocation 5401 * is either active in a packetized context, or free. 5402 * Since we can't collide, put this SCB on the generic 5403 * free list. 5404 */ 5405 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5406 scb, links.le); 5407 } 5408 5409 ahd_platform_scb_free(ahd, scb); 5410 } 5411 5412 void 5413 ahd_alloc_scbs(struct ahd_softc *ahd) 5414 { 5415 struct scb_data *scb_data; 5416 struct scb *next_scb; 5417 struct hardware_scb *hscb; 5418 struct map_node *hscb_map; 5419 struct map_node *sg_map; 5420 struct map_node *sense_map; 5421 uint8_t *segs; 5422 uint8_t *sense_data; 5423 bus_addr_t hscb_busaddr; 5424 bus_addr_t sg_busaddr; 5425 bus_addr_t sense_busaddr; 5426 int newcount; 5427 int i; 5428 5429 scb_data = &ahd->scb_data; 5430 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5431 /* Can't allocate any more */ 5432 return; 5433 5434 KASSERT(scb_data->scbs_left >= 0); 5435 if (scb_data->scbs_left != 0) { 5436 int offset; 5437 5438 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5439 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5440 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5441 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5442 } else { 5443 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5444 5445 if (hscb_map == NULL) 5446 return; 5447 5448 memset(hscb_map, 0, sizeof(*hscb_map)); 5449 5450 /* Allocate the next batch of hardware SCBs */ 5451 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5452 &hscb_map->dmamap, (caddr_t *)&hscb_map->vaddr, 5453 &hscb_map->physaddr, &hscb_map->dmasegs, 5454 &hscb_map->nseg, ahd_name(ahd), 5455 "hardware SCB structures") < 0) { 5456 free(hscb_map, M_DEVBUF); 5457 return; 5458 } 5459 5460 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5461 5462 hscb = (struct hardware_scb *)hscb_map->vaddr; 5463 hscb_busaddr = hscb_map->physaddr; 5464 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5465 } 5466 5467 scb_data->init_level++; 5468 5469 if (scb_data->sgs_left != 0) { 5470 int offset; 5471 5472 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5473 - scb_data->sgs_left) * ahd_sglist_size(ahd); 5474 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5475 segs = sg_map->vaddr + offset; 5476 sg_busaddr = sg_map->physaddr + offset; 5477 } else { 5478 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5479 5480 if (sg_map == NULL) 5481 return; 5482 5483 bzero(sg_map, sizeof(*sg_map)); 5484 5485 /* Allocate the next batch of S/G lists */ 5486 if (ahd_createdmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), ahd->sc_dmaflags, 5487 &sg_map->dmamap, (caddr_t *)&sg_map->vaddr, 5488 &sg_map->physaddr, &sg_map->dmasegs, 5489 &sg_map->nseg, ahd_name(ahd), 5490 "SG data structures") < 0) { 5491 free(sg_map, M_DEVBUF); 5492 return; 5493 } 5494 5495 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5496 5497 segs = sg_map->vaddr; 5498 sg_busaddr = sg_map->physaddr; 5499 scb_data->sgs_left = 5500 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5501 #ifdef AHD_DEBUG 5502 if (ahd_debug & AHD_SHOW_MEMORY) 5503 printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd)); 5504 #endif 5505 } 5506 5507 scb_data->init_level++; 5508 5509 5510 if (scb_data->sense_left != 0) { 5511 int offset; 5512 5513 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5514 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5515 sense_data = sense_map->vaddr + offset; 5516 sense_busaddr = sense_map->physaddr + offset; 5517 } else { 5518 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5519 5520 if (sense_map == NULL) 5521 return; 5522 5523 bzero(sense_map, sizeof(*sense_map)); 5524 5525 /* Allocate the next batch of sense buffers */ 5526 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5527 &sense_map->dmamap, (caddr_t *)&sense_map->vaddr, 5528 &sense_map->physaddr, &sense_map->dmasegs, 5529 &sense_map->nseg, ahd_name(ahd), 5530 "Sense Data structures") < 0) { 5531 free(sense_map, M_DEVBUF); 5532 return; 5533 } 5534 5535 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5536 5537 sense_data = sense_map->vaddr; 5538 sense_busaddr = sense_map->physaddr; 5539 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5540 #ifdef AHD_DEBUG 5541 if (ahd_debug & AHD_SHOW_MEMORY) 5542 printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd)); 5543 #endif 5544 } 5545 5546 scb_data->init_level++; 5547 5548 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5549 newcount = MIN(newcount, scb_data->sgs_left); 5550 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5551 scb_data->sense_left -= newcount; 5552 scb_data->scbs_left -= newcount; 5553 scb_data->sgs_left -= newcount; 5554 5555 for (i = 0; i < newcount; i++) { 5556 u_int col_tag; 5557 5558 struct scb_platform_data *pdata; 5559 #ifndef __linux__ 5560 int error; 5561 #endif 5562 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5563 M_DEVBUF, M_NOWAIT); 5564 if (next_scb == NULL) 5565 break; 5566 5567 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5568 M_DEVBUF, M_NOWAIT); 5569 if (pdata == NULL) { 5570 free(next_scb, M_DEVBUF); 5571 break; 5572 } 5573 next_scb->platform_data = pdata; 5574 next_scb->hscb_map = hscb_map; 5575 next_scb->sg_map = sg_map; 5576 next_scb->sense_map = sense_map; 5577 next_scb->sg_list = segs; 5578 next_scb->sense_data = sense_data; 5579 next_scb->sense_busaddr = sense_busaddr; 5580 memset(hscb, 0, sizeof(*hscb)); 5581 next_scb->hscb = hscb; 5582 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5583 KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && 5584 (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); 5585 5586 /* 5587 * The sequencer always starts with the second entry. 5588 * The first entry is embedded in the scb. 5589 */ 5590 next_scb->sg_list_busaddr = sg_busaddr; 5591 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5592 next_scb->sg_list_busaddr 5593 += sizeof(struct ahd_dma64_seg); 5594 else 5595 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5596 next_scb->ahd_softc = ahd; 5597 next_scb->flags = SCB_FLAG_NONE; 5598 5599 error = bus_dmamap_create(ahd->parent_dmat, 5600 AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0, 5601 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahd->sc_dmaflags, 5602 &next_scb->dmamap); 5603 if (error != 0) { 5604 free(next_scb, M_DEVBUF); 5605 free(pdata, M_DEVBUF); 5606 break; 5607 } 5608 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5609 col_tag = scb_data->numscbs ^ 0x100; 5610 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5611 if (next_scb->col_scb != NULL) 5612 next_scb->col_scb->col_scb = next_scb; 5613 ahd_free_scb(ahd, next_scb); 5614 hscb++; 5615 hscb_busaddr += sizeof(*hscb); 5616 segs += ahd_sglist_size(ahd); 5617 sg_busaddr += ahd_sglist_size(ahd); 5618 sense_data += AHD_SENSE_BUFSIZE; 5619 sense_busaddr += AHD_SENSE_BUFSIZE; 5620 scb_data->numscbs++; 5621 } 5622 } 5623 5624 void 5625 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5626 { 5627 const char *speed; 5628 const char *type; 5629 int len; 5630 5631 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5632 buf += len; 5633 5634 speed = "Ultra320 "; 5635 if ((ahd->features & AHD_WIDE) != 0) { 5636 type = "Wide "; 5637 } else { 5638 type = "Single "; 5639 } 5640 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5641 speed, type, ahd->channel, ahd->our_id); 5642 buf += len; 5643 5644 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5645 ahd->scb_data.maxhscbs); 5646 } 5647 5648 static const char *channel_strings[] = { 5649 "Primary Low", 5650 "Primary High", 5651 "Secondary Low", 5652 "Secondary High" 5653 }; 5654 5655 static const char *termstat_strings[] = { 5656 "Terminated Correctly", 5657 "Over Terminated", 5658 "Under Terminated", 5659 "Not Configured" 5660 }; 5661 5662 /* 5663 * Start the board, ready for normal operation 5664 */ 5665 int 5666 ahd_init(struct ahd_softc *ahd) 5667 { 5668 uint8_t *next_vaddr; 5669 bus_addr_t next_baddr; 5670 size_t driver_data_size; 5671 int i; 5672 int error; 5673 u_int warn_user; 5674 uint8_t current_sensing; 5675 uint8_t fstat; 5676 5677 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5678 5679 ahd->stack_size = ahd_probe_stack_size(ahd); 5680 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5681 M_DEVBUF, M_NOWAIT); 5682 if (ahd->saved_stack == NULL) 5683 return (ENOMEM); 5684 /* Zero the memory */ 5685 memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); 5686 5687 /* 5688 * Verify that the compiler hasn't over-agressively 5689 * padded important structures. 5690 */ 5691 if (sizeof(struct hardware_scb) != 64) 5692 panic("Hardware SCB size is incorrect"); 5693 5694 #ifdef AHD_DEBUG 5695 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5696 ahd->flags |= AHD_SEQUENCER_DEBUG; 5697 #endif 5698 5699 /* 5700 * Default to allowing initiator operations. 5701 */ 5702 ahd->flags |= AHD_INITIATORROLE; 5703 5704 /* 5705 * Only allow target mode features if this unit has them enabled. 5706 */ 5707 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5708 ahd->features &= ~AHD_TARGETMODE; 5709 5710 /* 5711 * DMA tag for our command fifos and other data in system memory 5712 * the card's sequencer must be able to access. For initiator 5713 * roles, we need to allocate space for the qoutfifo. When providing 5714 * for the target mode role, we must additionally provide space for 5715 * the incoming target command fifo. 5716 */ 5717 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5718 + sizeof(struct hardware_scb); 5719 if ((ahd->features & AHD_TARGETMODE) != 0) 5720 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5721 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5722 driver_data_size += PKT_OVERRUN_BUFSIZE; 5723 ahd->shared_data_size = driver_data_size; 5724 5725 memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); 5726 ahd->sc_dmaflags = BUS_DMA_NOWAIT; 5727 5728 if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 5729 ahd->sc_dmaflags, 5730 &ahd->shared_data_map.dmamap, (caddr_t *)&ahd->shared_data_map.vaddr, 5731 &ahd->shared_data_map.physaddr, &ahd->shared_data_map.dmasegs, 5732 &ahd->shared_data_map.nseg, ahd_name(ahd), "shared data") < 0) 5733 return (ENOMEM); 5734 ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; 5735 5736 ahd->init_level++; 5737 5738 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5739 next_baddr = ahd->shared_data_map.physaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5740 if ((ahd->features & AHD_TARGETMODE) != 0) { 5741 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5742 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5743 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5744 } 5745 5746 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5747 ahd->overrun_buf = next_vaddr; 5748 next_vaddr += PKT_OVERRUN_BUFSIZE; 5749 next_baddr += PKT_OVERRUN_BUFSIZE; 5750 } 5751 5752 /* 5753 * We need one SCB to serve as the "next SCB". Since the 5754 * tag identifier in this SCB will never be used, there is 5755 * no point in using a valid HSCB tag from an SCB pulled from 5756 * the standard free pool. So, we allocate this "sentinel" 5757 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5758 */ 5759 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5760 ahd->next_queued_hscb_map = &ahd->shared_data_map; 5761 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 5762 5763 memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 5764 5765 /* Allocate SCB data now that parent_dmat is initialized */ 5766 if (ahd_init_scbdata(ahd) != 0) 5767 return (ENOMEM); 5768 5769 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5770 ahd->flags &= ~AHD_RESET_BUS_A; 5771 5772 /* 5773 * Before committing these settings to the chip, give 5774 * the OSM one last chance to modify our configuration. 5775 */ 5776 ahd_platform_init(ahd); 5777 5778 /* Bring up the chip. */ 5779 ahd_chip_init(ahd); 5780 5781 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5782 5783 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5784 goto init_done; 5785 5786 /* 5787 * Verify termination based on current draw and 5788 * warn user if the bus is over/under terminated. 5789 */ 5790 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5791 CURSENSE_ENB); 5792 if (error != 0) { 5793 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5794 goto init_done; 5795 } 5796 for (i = 20, fstat = FLX_FSTAT_BUSY; 5797 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5798 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5799 if (error != 0) { 5800 printf("%s: current sensing timeout 2\n", 5801 ahd_name(ahd)); 5802 goto init_done; 5803 } 5804 } 5805 if (i == 0) { 5806 printf("%s: Timedout during current-sensing test\n", 5807 ahd_name(ahd)); 5808 goto init_done; 5809 } 5810 5811 /* Latch Current Sensing status. */ 5812 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5813 if (error != 0) { 5814 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5815 goto init_done; 5816 } 5817 5818 /* Diable current sensing. */ 5819 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5820 5821 #ifdef AHD_DEBUG 5822 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5823 printf("%s: current_sensing == 0x%x\n", 5824 ahd_name(ahd), current_sensing); 5825 } 5826 #endif 5827 warn_user = 0; 5828 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5829 u_int term_stat; 5830 5831 term_stat = (current_sensing & FLX_CSTAT_MASK); 5832 switch (term_stat) { 5833 case FLX_CSTAT_OVER: 5834 case FLX_CSTAT_UNDER: 5835 warn_user++; 5836 case FLX_CSTAT_INVALID: 5837 case FLX_CSTAT_OKAY: 5838 if (warn_user == 0 && bootverbose == 0) 5839 break; 5840 printf("%s: %s Channel %s\n", ahd_name(ahd), 5841 channel_strings[i], termstat_strings[term_stat]); 5842 break; 5843 } 5844 } 5845 if (warn_user) { 5846 printf("%s: WARNING. Termination is not configured correctly.\n" 5847 "%s: WARNING. SCSI bus operations may FAIL.\n", 5848 ahd_name(ahd), ahd_name(ahd)); 5849 } 5850 init_done: 5851 ahd_reset_current_bus(ahd); 5852 ahd_restart(ahd); 5853 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5854 ahd_stat_timer, ahd); 5855 5856 /* We have to wait until after any system dumps... */ 5857 ahd->shutdown_hook = shutdownhook_establish(ahd_shutdown, ahd); 5858 5859 return (0); 5860 } 5861 5862 /* 5863 * (Re)initialize chip state after a chip reset. 5864 */ 5865 static void 5866 ahd_chip_init(struct ahd_softc *ahd) 5867 { 5868 uint32_t busaddr; 5869 u_int sxfrctl1; 5870 u_int scsiseq_template; 5871 u_int wait; 5872 u_int i; 5873 u_int target; 5874 5875 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5876 /* 5877 * Take the LED out of diagnostic mode 5878 */ 5879 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 5880 5881 /* 5882 * Return HS_MAILBOX to its default value. 5883 */ 5884 ahd->hs_mailbox = 0; 5885 ahd_outb(ahd, HS_MAILBOX, 0); 5886 5887 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 5888 ahd_outb(ahd, IOWNID, ahd->our_id); 5889 ahd_outb(ahd, TOWNID, ahd->our_id); 5890 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 5891 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 5892 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 5893 && (ahd->seltime != STIMESEL_MIN)) { 5894 /* 5895 * The selection timer duration is twice as long 5896 * as it should be. Halve it by adding "1" to 5897 * the user specified setting. 5898 */ 5899 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 5900 } else { 5901 sxfrctl1 |= ahd->seltime; 5902 } 5903 5904 ahd_outb(ahd, SXFRCTL0, DFON); 5905 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 5906 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5907 5908 /* 5909 * Now that termination is set, wait for up 5910 * to 500ms for our transceivers to settle. If 5911 * the adapter does not have a cable attached, 5912 * the transceivers may never settle, so don't 5913 * complain if we fail here. 5914 */ 5915 for (wait = 10000; 5916 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 5917 wait--) 5918 ahd_delay(100); 5919 5920 /* Clear any false bus resets due to the transceivers settling */ 5921 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 5922 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5923 5924 /* Initialize mode specific S/G state. */ 5925 for (i = 0; i < 2; i++) { 5926 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 5927 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 5928 ahd_outb(ahd, SG_STATE, 0); 5929 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 5930 ahd_outb(ahd, SEQIMODE, 5931 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 5932 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 5933 } 5934 5935 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5936 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 5937 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 5938 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 5939 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 5940 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 5941 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 5942 } else { 5943 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 5944 } 5945 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 5946 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 5947 /* 5948 * Do not issue a target abort when a split completion 5949 * error occurs. Let our PCIX interrupt handler deal 5950 * with it instead. H2A4 Razor #625 5951 */ 5952 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 5953 5954 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 5955 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 5956 5957 /* 5958 * Tweak IOCELL settings. 5959 */ 5960 if ((ahd->flags & AHD_HP_BOARD) != 0) { 5961 for (i = 0; i < NUMDSPS; i++) { 5962 ahd_outb(ahd, DSPSELECT, i); 5963 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 5964 } 5965 #ifdef AHD_DEBUG 5966 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5967 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 5968 WRTBIASCTL_HP_DEFAULT); 5969 #endif 5970 } 5971 ahd_setup_iocell_workaround(ahd); 5972 5973 /* 5974 * Enable LQI Manager interrupts. 5975 */ 5976 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 5977 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 5978 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 5979 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 5980 /* 5981 * An interrupt from LQOBUSFREE is made redundant by the 5982 * BUSFREE interrupt. We choose to have the sequencer catch 5983 * LQOPHCHGINPKT errors manually for the command phase at the 5984 * start of a packetized selection case. 5985 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 5986 */ 5987 ahd_outb(ahd, LQOMODE1, 0); 5988 5989 /* 5990 * Setup sequencer interrupt handlers. 5991 */ 5992 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 5993 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 5994 5995 /* 5996 * Setup SCB Offset registers. 5997 */ 5998 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 5999 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6000 pkt_long_lun)); 6001 } else { 6002 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6003 } 6004 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6005 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6006 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6007 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6008 shared_data.idata.cdb)); 6009 ahd_outb(ahd, QNEXTPTR, 6010 offsetof(struct hardware_scb, next_hscb_busaddr)); 6011 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6012 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6013 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6014 ahd_outb(ahd, LUNLEN, 6015 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6016 } else { 6017 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6018 } 6019 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6020 ahd_outb(ahd, MAXCMD, 0xFF); 6021 ahd_outb(ahd, SCBAUTOPTR, 6022 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6023 6024 /* We haven't been enabled for target mode yet. */ 6025 ahd_outb(ahd, MULTARGID, 0); 6026 ahd_outb(ahd, MULTARGID + 1, 0); 6027 6028 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6029 /* Initialize the negotiation table. */ 6030 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6031 /* 6032 * Clear the spare bytes in the neg table to avoid 6033 * spurious parity errors. 6034 */ 6035 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6036 ahd_outb(ahd, NEGOADDR, target); 6037 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6038 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6039 ahd_outb(ahd, ANNEXDAT, 0); 6040 } 6041 } 6042 6043 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6044 struct ahd_devinfo devinfo; 6045 struct ahd_initiator_tinfo *tinfo; 6046 struct ahd_tmode_tstate *tstate; 6047 6048 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6049 target, &tstate); 6050 ahd_compile_devinfo(&devinfo, ahd->our_id, 6051 target, CAM_LUN_WILDCARD, 6052 'A', ROLE_INITIATOR); 6053 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6054 } 6055 6056 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6057 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6058 6059 /* 6060 * Always enable abort on incoming L_Qs if this feature is 6061 * supported. We use this to catch invalid SCB references. 6062 */ 6063 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6064 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6065 else 6066 ahd_outb(ahd, LQCTL1, 0); 6067 6068 /* All of our queues are empty */ 6069 ahd->qoutfifonext = 0; 6070 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6071 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6072 for (i = 0; i < AHD_QOUT_SIZE; i++) 6073 ahd->qoutfifo[i] = 0; 6074 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6075 6076 ahd->qinfifonext = 0; 6077 for (i = 0; i < AHD_QIN_SIZE; i++) 6078 ahd->qinfifo[i] = SCB_LIST_NULL; 6079 6080 if ((ahd->features & AHD_TARGETMODE) != 0) { 6081 /* All target command blocks start out invalid. */ 6082 for (i = 0; i < AHD_TMODE_CMDS; i++) 6083 ahd->targetcmds[i].cmd_valid = 0; 6084 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6085 ahd->tqinfifonext = 1; 6086 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6087 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6088 } 6089 6090 /* Initialize Scratch Ram. */ 6091 ahd_outb(ahd, SEQ_FLAGS, 0); 6092 ahd_outb(ahd, SEQ_FLAGS2, 0); 6093 6094 /* We don't have any waiting selections */ 6095 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6096 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6097 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6098 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6099 } 6100 6101 /* 6102 * Nobody is waiting to be DMAed into the QOUTFIFO. 6103 */ 6104 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6105 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6106 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6107 6108 /* 6109 * The Freeze Count is 0. 6110 */ 6111 ahd_outw(ahd, QFREEZE_COUNT, 0); 6112 6113 /* 6114 * Tell the sequencer where it can find our arrays in memory. 6115 */ 6116 busaddr = ahd->shared_data_map.physaddr; 6117 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6118 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6119 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6120 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6121 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6122 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6123 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6124 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6125 /* 6126 * Setup the allowed SCSI Sequences based on operational mode. 6127 * If we are a target, we'll enable select in operations once 6128 * we've had a lun enabled. 6129 */ 6130 scsiseq_template = ENAUTOATNP; 6131 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6132 scsiseq_template |= ENRSELI; 6133 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6134 6135 /* There are no busy SCBs yet. */ 6136 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6137 int lun; 6138 6139 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6140 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6141 } 6142 6143 /* 6144 * Initialize the group code to command length table. 6145 * Vendor Unique codes are set to 0 so we only capture 6146 * the first byte of the cdb. These can be overridden 6147 * when target mode is enabled. 6148 */ 6149 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6150 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6151 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6152 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6153 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6154 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6155 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6156 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6157 6158 /* Tell the sequencer of our initial queue positions */ 6159 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6160 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6161 ahd->qinfifonext = 0; 6162 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6163 ahd_set_hescb_qoff(ahd, 0); 6164 ahd_set_snscb_qoff(ahd, 0); 6165 ahd_set_sescb_qoff(ahd, 0); 6166 ahd_set_sdscb_qoff(ahd, 0); 6167 6168 /* 6169 * Tell the sequencer which SCB will be the next one it receives. 6170 */ 6171 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6172 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6173 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6174 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6175 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6176 6177 /* 6178 * Default to coalescing disabled. 6179 */ 6180 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6181 ahd_outw(ahd, CMDS_PENDING, 0); 6182 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6183 ahd->int_coalescing_maxcmds, 6184 ahd->int_coalescing_mincmds); 6185 ahd_enable_coalescing(ahd, FALSE); 6186 6187 ahd_loadseq(ahd); 6188 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6189 } 6190 6191 /* 6192 * Setup default device and controller settings. 6193 * This should only be called if our probe has 6194 * determined that no configuration data is available. 6195 */ 6196 int 6197 ahd_default_config(struct ahd_softc *ahd) 6198 { 6199 int targ; 6200 6201 ahd->our_id = 7; 6202 6203 /* 6204 * Allocate a tstate to house information for our 6205 * initiator presence on the bus as well as the user 6206 * data for any target mode initiator. 6207 */ 6208 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6209 printf("%s: unable to allocate ahd_tmode_tstate. " 6210 "Failing attach\n", ahd_name(ahd)); 6211 return (ENOMEM); 6212 } 6213 6214 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6215 struct ahd_devinfo devinfo; 6216 struct ahd_initiator_tinfo *tinfo; 6217 struct ahd_tmode_tstate *tstate; 6218 uint16_t target_mask; 6219 6220 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6221 targ, &tstate); 6222 /* 6223 * We support SPC2 and SPI4. 6224 */ 6225 tinfo->user.protocol_version = 4; 6226 tinfo->user.transport_version = 4; 6227 6228 target_mask = 0x01 << targ; 6229 ahd->user_discenable |= target_mask; 6230 tstate->discenable |= target_mask; 6231 ahd->user_tagenable |= target_mask; 6232 #ifdef AHD_FORCE_160 6233 tinfo->user.period = AHD_SYNCRATE_DT; 6234 #else 6235 tinfo->user.period = AHD_SYNCRATE_160; 6236 #endif 6237 tinfo->user.offset= MAX_OFFSET; 6238 tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6239 | MSG_EXT_PPR_WRFLOW 6240 | MSG_EXT_PPR_HOLDMCS 6241 | MSG_EXT_PPR_IU_REQ 6242 | MSG_EXT_PPR_QAS_REQ 6243 | MSG_EXT_PPR_DT_REQ; 6244 if ((ahd->features & AHD_RTI) != 0) 6245 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6246 6247 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6248 6249 /* 6250 * Start out Async/Narrow/Untagged and with 6251 * conservative protocol support. 6252 */ 6253 tinfo->goal.protocol_version = 2; 6254 tinfo->goal.transport_version = 2; 6255 tinfo->curr.protocol_version = 2; 6256 tinfo->curr.transport_version = 2; 6257 ahd_compile_devinfo(&devinfo, ahd->our_id, 6258 targ, CAM_LUN_WILDCARD, 6259 'A', ROLE_INITIATOR); 6260 tstate->tagenable &= ~target_mask; 6261 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6262 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6263 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6264 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6265 /*paused*/TRUE); 6266 } 6267 return (0); 6268 } 6269 6270 /* 6271 * Parse device configuration information. 6272 */ 6273 int 6274 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6275 { 6276 int targ; 6277 int max_targ; 6278 6279 max_targ = sc->max_targets & CFMAXTARG; 6280 ahd->our_id = sc->brtime_id & CFSCSIID; 6281 6282 /* 6283 * Allocate a tstate to house information for our 6284 * initiator presence on the bus as well as the user 6285 * data for any target mode initiator. 6286 */ 6287 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6288 printf("%s: unable to allocate ahd_tmode_tstate. " 6289 "Failing attach\n", ahd_name(ahd)); 6290 return (ENOMEM); 6291 } 6292 6293 for (targ = 0; targ < max_targ; targ++) { 6294 struct ahd_devinfo devinfo; 6295 struct ahd_initiator_tinfo *tinfo; 6296 struct ahd_transinfo *user_tinfo; 6297 struct ahd_tmode_tstate *tstate; 6298 uint16_t target_mask; 6299 6300 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6301 targ, &tstate); 6302 user_tinfo = &tinfo->user; 6303 6304 /* 6305 * We support SPC2 and SPI4. 6306 */ 6307 tinfo->user.protocol_version = 4; 6308 tinfo->user.transport_version = 4; 6309 6310 target_mask = 0x01 << targ; 6311 ahd->user_discenable &= ~target_mask; 6312 tstate->discenable &= ~target_mask; 6313 ahd->user_tagenable &= ~target_mask; 6314 if (sc->device_flags[targ] & CFDISC) { 6315 tstate->discenable |= target_mask; 6316 ahd->user_discenable |= target_mask; 6317 ahd->user_tagenable |= target_mask; 6318 } else { 6319 /* 6320 * Cannot be packetized without disconnection. 6321 */ 6322 sc->device_flags[targ] &= ~CFPACKETIZED; 6323 } 6324 6325 user_tinfo->ppr_options = 0; 6326 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6327 if (user_tinfo->period < CFXFER_ASYNC) { 6328 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6329 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6330 user_tinfo->offset = MAX_OFFSET; 6331 } else { 6332 user_tinfo->offset = 0; 6333 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6334 } 6335 #ifdef AHD_FORCE_160 6336 if (user_tinfo->period <= AHD_SYNCRATE_160) 6337 user_tinfo->period = AHD_SYNCRATE_DT; 6338 #endif 6339 6340 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6341 user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6342 | MSG_EXT_PPR_WRFLOW 6343 | MSG_EXT_PPR_HOLDMCS 6344 | MSG_EXT_PPR_IU_REQ; 6345 if ((ahd->features & AHD_RTI) != 0) 6346 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6347 } 6348 6349 if ((sc->device_flags[targ] & CFQAS) != 0) 6350 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6351 6352 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6353 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6354 else 6355 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6356 #ifdef AHD_DEBUG 6357 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6358 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6359 user_tinfo->period, user_tinfo->offset, 6360 user_tinfo->ppr_options); 6361 #endif 6362 /* 6363 * Start out Async/Narrow/Untagged and with 6364 * conservative protocol support. 6365 */ 6366 tstate->tagenable &= ~target_mask; 6367 tinfo->goal.protocol_version = 2; 6368 tinfo->goal.transport_version = 2; 6369 tinfo->curr.protocol_version = 2; 6370 tinfo->curr.transport_version = 2; 6371 ahd_compile_devinfo(&devinfo, ahd->our_id, 6372 targ, CAM_LUN_WILDCARD, 6373 'A', ROLE_INITIATOR); 6374 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6375 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6376 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6377 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6378 /*paused*/TRUE); 6379 } 6380 6381 ahd->flags &= ~AHD_SPCHK_ENB_A; 6382 if (sc->bios_control & CFSPARITY) 6383 ahd->flags |= AHD_SPCHK_ENB_A; 6384 6385 ahd->flags &= ~AHD_RESET_BUS_A; 6386 if (sc->bios_control & CFRESETB) 6387 ahd->flags |= AHD_RESET_BUS_A; 6388 6389 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6390 if (sc->bios_control & CFEXTEND) 6391 ahd->flags |= AHD_EXTENDED_TRANS_A; 6392 6393 ahd->flags &= ~AHD_BIOS_ENABLED; 6394 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6395 ahd->flags |= AHD_BIOS_ENABLED; 6396 6397 ahd->flags &= ~AHD_STPWLEVEL_A; 6398 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6399 ahd->flags |= AHD_STPWLEVEL_A; 6400 6401 return (0); 6402 } 6403 6404 /* 6405 * Parse device configuration information. 6406 */ 6407 int 6408 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6409 { 6410 int error; 6411 6412 error = ahd_verify_vpd_cksum(vpd); 6413 if (error == 0) 6414 return (EINVAL); 6415 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6416 ahd->flags |= AHD_BOOT_CHANNEL; 6417 return (0); 6418 } 6419 6420 void 6421 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6422 { 6423 u_int hcntrl; 6424 6425 hcntrl = ahd_inb(ahd, HCNTRL); 6426 hcntrl &= ~INTEN; 6427 ahd->pause &= ~INTEN; 6428 ahd->unpause &= ~INTEN; 6429 if (enable) { 6430 hcntrl |= INTEN; 6431 ahd->pause |= INTEN; 6432 ahd->unpause |= INTEN; 6433 } 6434 ahd_outb(ahd, HCNTRL, hcntrl); 6435 } 6436 6437 void 6438 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6439 u_int mincmds) 6440 { 6441 if (timer > AHD_TIMER_MAX_US) 6442 timer = AHD_TIMER_MAX_US; 6443 ahd->int_coalescing_timer = timer; 6444 6445 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6446 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6447 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6448 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6449 ahd->int_coalescing_maxcmds = maxcmds; 6450 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6451 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6452 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6453 } 6454 6455 void 6456 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 6457 { 6458 6459 ahd->hs_mailbox &= ~ENINT_COALESCE; 6460 if (enable) 6461 ahd->hs_mailbox |= ENINT_COALESCE; 6462 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6463 ahd_flush_device_writes(ahd); 6464 ahd_run_qoutfifo(ahd); 6465 } 6466 6467 /* 6468 * Ensure that the card is paused in a location 6469 * outside of all critical sections and that all 6470 * pending work is completed prior to returning. 6471 * This routine should only be called from outside 6472 * an interrupt context. 6473 */ 6474 void 6475 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6476 { 6477 u_int intstat; 6478 u_int maxloops; 6479 u_int qfreeze_cnt; 6480 6481 maxloops = 1000; 6482 ahd->flags |= AHD_ALL_INTERRUPTS; 6483 ahd_pause(ahd); 6484 /* 6485 * Increment the QFreeze Count so that the sequencer 6486 * will not start new selections. We do this only 6487 * until we are safely paused without further selections 6488 * pending. 6489 */ 6490 ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); 6491 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 6492 do { 6493 struct scb *waiting_scb; 6494 6495 ahd_unpause(ahd); 6496 ahd_intr(ahd); 6497 ahd_pause(ahd); 6498 ahd_clear_critical_section(ahd); 6499 intstat = ahd_inb(ahd, INTSTAT); 6500 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6501 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6502 ahd_outb(ahd, SCSISEQ0, 6503 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6504 /* 6505 * In the non-packetized case, the sequencer (for Rev A), 6506 * relies on ENSELO remaining set after SELDO. The hardware 6507 * auto-clears ENSELO in the packetized case. 6508 */ 6509 waiting_scb = ahd_lookup_scb(ahd, 6510 ahd_inw(ahd, WAITING_TID_HEAD)); 6511 if (waiting_scb != NULL 6512 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6513 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6514 ahd_outb(ahd, SCSISEQ0, 6515 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6516 } while (--maxloops 6517 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6518 && ((intstat & INT_PEND) != 0 6519 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 6520 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 6521 if (maxloops == 0) { 6522 printf("Infinite interrupt loop, INTSTAT = %x", 6523 ahd_inb(ahd, INTSTAT)); 6524 } 6525 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 6526 if (qfreeze_cnt == 0) { 6527 printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n", 6528 ahd_name(ahd)); 6529 } else { 6530 qfreeze_cnt--; 6531 } 6532 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 6533 if (qfreeze_cnt == 0) 6534 ahd_outb(ahd, SEQ_FLAGS2, 6535 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 6536 6537 ahd_flush_qoutfifo(ahd); 6538 6539 ahd_platform_flushwork(ahd); 6540 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6541 } 6542 6543 int 6544 ahd_suspend(struct ahd_softc *ahd) 6545 { 6546 6547 ahd_pause_and_flushwork(ahd); 6548 6549 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 6550 ahd_unpause(ahd); 6551 return (EBUSY); 6552 } 6553 ahd_shutdown(ahd); 6554 return (0); 6555 } 6556 6557 int 6558 ahd_resume(struct ahd_softc *ahd) 6559 { 6560 6561 ahd_reset(ahd, /*reinit*/TRUE); 6562 ahd_intr_enable(ahd, TRUE); 6563 ahd_restart(ahd); 6564 return (0); 6565 } 6566 6567 /************************** Busy Target Table *********************************/ 6568 /* 6569 * Set SCBPTR to the SCB that contains the busy 6570 * table entry for TCL. Return the offset into 6571 * the SCB that contains the entry for TCL. 6572 * saved_scbid is dereferenced and set to the 6573 * scbid that should be restored once manipualtion 6574 * of the TCL entry is complete. 6575 */ 6576 static __inline u_int 6577 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6578 { 6579 /* 6580 * Index to the SCB that contains the busy entry. 6581 */ 6582 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6583 *saved_scbid = ahd_get_scbptr(ahd); 6584 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6585 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6586 6587 /* 6588 * And now calculate the SCB offset to the entry. 6589 * Each entry is 2 bytes wide, hence the 6590 * multiplication by 2. 6591 */ 6592 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6593 } 6594 6595 /* 6596 * Return the untagged transaction id for a given target/channel lun. 6597 */ 6598 u_int 6599 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6600 { 6601 u_int scbid; 6602 u_int scb_offset; 6603 u_int saved_scbptr; 6604 6605 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6606 scbid = ahd_inw_scbram(ahd, scb_offset); 6607 ahd_set_scbptr(ahd, saved_scbptr); 6608 return (scbid); 6609 } 6610 6611 void 6612 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6613 { 6614 u_int scb_offset; 6615 u_int saved_scbptr; 6616 6617 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6618 ahd_outw(ahd, scb_offset, scbid); 6619 ahd_set_scbptr(ahd, saved_scbptr); 6620 } 6621 6622 /************************** SCB and SCB queue management **********************/ 6623 int 6624 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6625 char channel, int lun, u_int tag, role_t role) 6626 { 6627 int targ = SCB_GET_TARGET(ahd, scb); 6628 char chan = SCB_GET_CHANNEL(ahd, scb); 6629 int slun = SCB_GET_LUN(scb); 6630 int match; 6631 6632 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6633 if (match != 0) 6634 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6635 if (match != 0) 6636 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6637 if (match != 0) { 6638 #if AHD_TARGET_MODE 6639 int group; 6640 6641 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6642 if (role == ROLE_INITIATOR) { 6643 match = (group != XPT_FC_GROUP_TMODE) 6644 && ((tag == SCB_GET_TAG(scb)) 6645 || (tag == SCB_LIST_NULL)); 6646 } else if (role == ROLE_TARGET) { 6647 match = (group == XPT_FC_GROUP_TMODE) 6648 && ((tag == scb->io_ctx->csio.tag_id) 6649 || (tag == SCB_LIST_NULL)); 6650 } 6651 #else /* !AHD_TARGET_MODE */ 6652 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6653 #endif /* AHD_TARGET_MODE */ 6654 } 6655 6656 return match; 6657 } 6658 6659 void 6660 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6661 { 6662 int target; 6663 char channel; 6664 int lun; 6665 6666 target = SCB_GET_TARGET(ahd, scb); 6667 lun = SCB_GET_LUN(scb); 6668 channel = SCB_GET_CHANNEL(ahd, scb); 6669 6670 ahd_search_qinfifo(ahd, target, channel, lun, 6671 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6672 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6673 6674 ahd_platform_freeze_devq(ahd, scb); 6675 } 6676 6677 void 6678 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6679 { 6680 struct scb *prev_scb; 6681 ahd_mode_state saved_modes; 6682 6683 saved_modes = ahd_save_modes(ahd); 6684 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6685 prev_scb = NULL; 6686 if (ahd_qinfifo_count(ahd) != 0) { 6687 u_int prev_tag; 6688 u_int prev_pos; 6689 6690 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6691 prev_tag = ahd->qinfifo[prev_pos]; 6692 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6693 } 6694 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6695 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6696 ahd_restore_modes(ahd, saved_modes); 6697 } 6698 6699 static void 6700 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6701 struct scb *scb) 6702 { 6703 if (prev_scb == NULL) { 6704 uint32_t busaddr; 6705 6706 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6707 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6708 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6709 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6710 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6711 } else { 6712 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6713 ahd_sync_scb(ahd, prev_scb, 6714 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6715 } 6716 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6717 ahd->qinfifonext++; 6718 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6719 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6720 } 6721 6722 static int 6723 ahd_qinfifo_count(struct ahd_softc *ahd) 6724 { 6725 u_int qinpos; 6726 u_int wrap_qinpos; 6727 u_int wrap_qinfifonext; 6728 6729 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6730 qinpos = ahd_get_snscb_qoff(ahd); 6731 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6732 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6733 if (wrap_qinfifonext >= wrap_qinpos) 6734 return (wrap_qinfifonext - wrap_qinpos); 6735 else 6736 return (wrap_qinfifonext 6737 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6738 } 6739 6740 void 6741 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6742 { 6743 struct scb *scb; 6744 ahd_mode_state saved_modes; 6745 u_int pending_cmds; 6746 6747 saved_modes = ahd_save_modes(ahd); 6748 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6749 6750 /* 6751 * Don't count any commands as outstanding that the 6752 * sequencer has already marked for completion. 6753 */ 6754 ahd_flush_qoutfifo(ahd); 6755 6756 pending_cmds = 0; 6757 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6758 pending_cmds++; 6759 } 6760 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6761 ahd_restore_modes(ahd, saved_modes); 6762 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6763 } 6764 6765 int 6766 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6767 int lun, u_int tag, role_t role, uint32_t status, 6768 ahd_search_action action) 6769 { 6770 struct scb *scb; 6771 struct scb *prev_scb; 6772 ahd_mode_state saved_modes; 6773 u_int qinstart; 6774 u_int qinpos; 6775 u_int qintail; 6776 u_int tid_next; 6777 u_int tid_prev; 6778 u_int scbid; 6779 u_int savedscbptr; 6780 uint32_t busaddr; 6781 int found; 6782 int targets; 6783 int pending_cmds; 6784 int qincount; 6785 6786 /* Must be in CCHAN mode */ 6787 saved_modes = ahd_save_modes(ahd); 6788 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6789 6790 /* 6791 * Halt any pending SCB DMA. The sequencer will reinitiate 6792 * this DMA if the qinfifo is not empty once we unpause. 6793 */ 6794 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 6795 == (CCARREN|CCSCBEN|CCSCBDIR)) { 6796 ahd_outb(ahd, CCSCBCTL, 6797 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 6798 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 6799 ; 6800 } 6801 /* Determine sequencer's position in the qinfifo. */ 6802 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 6803 qinstart = ahd_get_snscb_qoff(ahd); 6804 qinpos = AHD_QIN_WRAP(qinstart); 6805 found = 0; 6806 prev_scb = NULL; 6807 6808 pending_cmds = 0; 6809 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6810 pending_cmds++; 6811 } 6812 qincount = ahd_qinfifo_count(ahd); 6813 6814 if (action == SEARCH_PRINT) { 6815 printf("qinstart = 0x%x qinfifonext = 0x%x\n", 6816 qinstart, ahd->qinfifonext); 6817 } 6818 6819 /* 6820 * Start with an empty queue. Entries that are not chosen 6821 * for removal will be re-added to the queue as we go. 6822 */ 6823 ahd->qinfifonext = qinstart; 6824 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6825 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6826 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6827 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6828 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6829 6830 while (qinpos != qintail) { 6831 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 6832 if (scb == NULL) { 6833 panic("Loop 1\n"); 6834 } 6835 6836 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 6837 /* 6838 * We found an scb that needs to be acted on. 6839 */ 6840 found++; 6841 switch (action) { 6842 case SEARCH_COMPLETE: 6843 { 6844 cam_status ostat; 6845 cam_status cstat; 6846 6847 ostat = ahd_get_scsi_status(scb); 6848 if (ostat == CAM_REQ_INPROG) 6849 ahd_set_scsi_status(scb, status); 6850 cstat = ahd_get_transaction_status(scb); 6851 if (cstat != CAM_REQ_CMP) 6852 ahd_freeze_scb(scb); 6853 if ((scb->flags & SCB_ACTIVE) == 0) 6854 printf("Inactive SCB in qinfifo\n"); 6855 if (scb->xs->error != CAM_REQ_CMP) 6856 printf("SEARCH_COMPLETE(0x%x): ostat 0x%x, cstat 0x%x, xs_error 0x%x\n", 6857 SCB_GET_TAG(scb), ostat, cstat, scb->xs->error); 6858 ahd_done(ahd, scb); 6859 6860 /* FALLTHROUGH */ 6861 } 6862 case SEARCH_REMOVE: 6863 break; 6864 case SEARCH_PRINT: 6865 printf(" 0x%x", ahd->qinfifo[qinpos]); 6866 /* FALLTHROUGH */ 6867 case SEARCH_COUNT: 6868 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6869 prev_scb = scb; 6870 break; 6871 } 6872 } else { 6873 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6874 prev_scb = scb; 6875 } 6876 qinpos = AHD_QIN_WRAP(qinpos+1); 6877 } 6878 6879 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6880 6881 if (action == SEARCH_PRINT) 6882 printf("\nWAITING_TID_QUEUES:\n"); 6883 6884 /* 6885 * Search waiting for selection lists. We traverse the 6886 * list of "their ids" waiting for selection and, if 6887 * appropriate, traverse the SCBs of each "their id" 6888 * looking for matches. 6889 */ 6890 savedscbptr = ahd_get_scbptr(ahd); 6891 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 6892 tid_prev = SCB_LIST_NULL; 6893 targets = 0; 6894 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 6895 u_int tid_head; 6896 6897 /* 6898 * We limit based on the number of SCBs since 6899 * MK_MESSAGE SCBs are not in the per-tid lists. 6900 */ 6901 targets++; 6902 if (targets > AHD_SCB_MAX) { 6903 panic("TID LIST LOOP"); 6904 } 6905 if (scbid >= ahd->scb_data.numscbs) { 6906 printf("%s: Waiting TID List inconsistency. " 6907 "SCB index == 0x%x, yet numscbs == 0x%x.", 6908 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 6909 ahd_dump_card_state(ahd); 6910 panic("for safety"); 6911 } 6912 scb = ahd_lookup_scb(ahd, scbid); 6913 if (scb == NULL) { 6914 printf("%s: SCB = 0x%x Not Active!\n", 6915 ahd_name(ahd), scbid); 6916 panic("Waiting TID List traversal\n"); 6917 break; 6918 } 6919 ahd_set_scbptr(ahd, scbid); 6920 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 6921 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 6922 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 6923 tid_prev = scbid; 6924 continue; 6925 } 6926 6927 /* 6928 * We found a list of scbs that needs to be searched. 6929 */ 6930 if (action == SEARCH_PRINT) 6931 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 6932 tid_head = scbid; 6933 found += ahd_search_scb_list(ahd, target, channel, 6934 lun, tag, role, status, 6935 action, &tid_head, 6936 SCB_GET_TARGET(ahd, scb)); 6937 if (tid_head != scbid) 6938 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 6939 if (!SCBID_IS_NULL(tid_head)) 6940 tid_prev = tid_head; 6941 if (action == SEARCH_PRINT) 6942 printf(")\n"); 6943 } 6944 ahd_set_scbptr(ahd, savedscbptr); 6945 ahd_restore_modes(ahd, saved_modes); 6946 return (found); 6947 } 6948 6949 static int 6950 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 6951 int lun, u_int tag, role_t role, uint32_t status, 6952 ahd_search_action action, u_int *list_head, u_int tid) 6953 { 6954 struct scb *scb; 6955 u_int scbid; 6956 u_int next; 6957 u_int prev; 6958 int found; 6959 6960 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6961 found = 0; 6962 prev = SCB_LIST_NULL; 6963 next = *list_head; 6964 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 6965 if (scbid >= ahd->scb_data.numscbs) { 6966 printf("%s:SCB List inconsistency. " 6967 "SCB == 0x%x, yet numscbs == 0x%x.", 6968 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 6969 ahd_dump_card_state(ahd); 6970 panic("for safety"); 6971 } 6972 scb = ahd_lookup_scb(ahd, scbid); 6973 if (scb == NULL) { 6974 printf("%s: SCB = %d Not Active!\n", 6975 ahd_name(ahd), scbid); 6976 panic("Waiting List traversal\n"); 6977 } 6978 ahd_set_scbptr(ahd, scbid); 6979 next = ahd_inw_scbram(ahd, SCB_NEXT); 6980 if (ahd_match_scb(ahd, scb, target, channel, 6981 lun, SCB_LIST_NULL, role) == 0) { 6982 prev = scbid; 6983 continue; 6984 } 6985 found++; 6986 switch (action) { 6987 case SEARCH_COMPLETE: 6988 { 6989 cam_status ostat; 6990 cam_status cstat; 6991 6992 ostat = ahd_get_scsi_status(scb); 6993 if (ostat == CAM_REQ_INPROG) 6994 ahd_set_scsi_status(scb, status); 6995 cstat = ahd_get_transaction_status(scb); 6996 if (cstat != CAM_REQ_CMP) 6997 ahd_freeze_scb(scb); 6998 if ((scb->flags & SCB_ACTIVE) == 0) 6999 printf("Inactive SCB in Waiting List\n"); 7000 ahd_done(ahd, scb); 7001 /* FALLTHROUGH */ 7002 } 7003 case SEARCH_REMOVE: 7004 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7005 if (prev == SCB_LIST_NULL) 7006 *list_head = next; 7007 break; 7008 case SEARCH_PRINT: 7009 printf("0x%x ", scbid); 7010 case SEARCH_COUNT: 7011 prev = scbid; 7012 break; 7013 } 7014 if (found > AHD_SCB_MAX) 7015 panic("SCB LIST LOOP"); 7016 } 7017 if (action == SEARCH_COMPLETE 7018 || action == SEARCH_REMOVE) 7019 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7020 return (found); 7021 } 7022 7023 static void 7024 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7025 u_int tid_cur, u_int tid_next) 7026 { 7027 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7028 7029 if (SCBID_IS_NULL(tid_cur)) { 7030 7031 /* Bypass current TID list */ 7032 if (SCBID_IS_NULL(tid_prev)) { 7033 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7034 } else { 7035 ahd_set_scbptr(ahd, tid_prev); 7036 ahd_outw(ahd, SCB_NEXT2, tid_next); 7037 } 7038 if (SCBID_IS_NULL(tid_next)) 7039 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7040 } else { 7041 7042 /* Stitch through tid_cur */ 7043 if (SCBID_IS_NULL(tid_prev)) { 7044 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7045 } else { 7046 ahd_set_scbptr(ahd, tid_prev); 7047 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7048 } 7049 ahd_set_scbptr(ahd, tid_cur); 7050 ahd_outw(ahd, SCB_NEXT2, tid_next); 7051 7052 if (SCBID_IS_NULL(tid_next)) 7053 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7054 } 7055 } 7056 7057 /* 7058 * Manipulate the waiting for selection list and return the 7059 * scb that follows the one that we remove. 7060 */ 7061 static u_int 7062 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7063 u_int prev, u_int next, u_int tid) 7064 { 7065 u_int tail_offset; 7066 7067 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7068 if (!SCBID_IS_NULL(prev)) { 7069 ahd_set_scbptr(ahd, prev); 7070 ahd_outw(ahd, SCB_NEXT, next); 7071 } 7072 7073 /* 7074 * SCBs that had MK_MESSAGE set in them will not 7075 * be queued to the per-target lists, so don't 7076 * blindly clear the tail pointer. 7077 */ 7078 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7079 if (SCBID_IS_NULL(next) 7080 && ahd_inw(ahd, tail_offset) == scbid) 7081 ahd_outw(ahd, tail_offset, prev); 7082 ahd_add_scb_to_free_list(ahd, scbid); 7083 return (next); 7084 } 7085 7086 /* 7087 * Add the SCB as selected by SCBPTR onto the on chip list of 7088 * free hardware SCBs. This list is empty/unused if we are not 7089 * performing SCB paging. 7090 */ 7091 static void 7092 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7093 { 7094 /* XXX Need some other mechanism to designate "free". */ 7095 /* 7096 * Invalidate the tag so that our abort 7097 * routines don't think it's active. 7098 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7099 */ 7100 } 7101 7102 /******************************** Error Handling ******************************/ 7103 /* 7104 * Abort all SCBs that match the given description (target/channel/lun/tag), 7105 * setting their status to the passed in status if the status has not already 7106 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7107 * is paused before it is called. 7108 */ 7109 int 7110 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7111 int lun, u_int tag, role_t role, uint32_t status) 7112 { 7113 struct scb *scbp; 7114 struct scb *scbp_next; 7115 u_int i, j; 7116 u_int maxtarget; 7117 u_int minlun; 7118 u_int maxlun; 7119 int found; 7120 ahd_mode_state saved_modes; 7121 7122 /* restore this when we're done */ 7123 saved_modes = ahd_save_modes(ahd); 7124 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7125 7126 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7127 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7128 7129 /* 7130 * Clean out the busy target table for any untagged commands. 7131 */ 7132 i = 0; 7133 maxtarget = 16; 7134 if (target != CAM_TARGET_WILDCARD) { 7135 i = target; 7136 if (channel == 'B') 7137 i += 8; 7138 maxtarget = i + 1; 7139 } 7140 7141 if (lun == CAM_LUN_WILDCARD) { 7142 minlun = 0; 7143 maxlun = AHD_NUM_LUNS_NONPKT; 7144 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7145 minlun = maxlun = 0; 7146 } else { 7147 minlun = lun; 7148 maxlun = lun + 1; 7149 } 7150 7151 if (role != ROLE_TARGET) { 7152 for (;i < maxtarget; i++) { 7153 for (j = minlun;j < maxlun; j++) { 7154 u_int scbid; 7155 u_int tcl; 7156 7157 tcl = BUILD_TCL_RAW(i, 'A', j); 7158 scbid = ahd_find_busy_tcl(ahd, tcl); 7159 scbp = ahd_lookup_scb(ahd, scbid); 7160 if (scbp == NULL 7161 || ahd_match_scb(ahd, scbp, target, channel, 7162 lun, tag, role) == 0) 7163 continue; 7164 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7165 } 7166 } 7167 } 7168 7169 /* 7170 * Don't abort commands that have already completed, 7171 * but haven't quite made it up to the host yet. 7172 */ 7173 ahd_flush_qoutfifo(ahd); 7174 7175 /* 7176 * Go through the pending CCB list and look for 7177 * commands for this target that are still active. 7178 * These are other tagged commands that were 7179 * disconnected when the reset occurred. 7180 */ 7181 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7182 while (scbp_next != NULL) { 7183 scbp = scbp_next; 7184 scbp_next = LIST_NEXT(scbp, pending_links); 7185 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7186 cam_status ostat; 7187 7188 ostat = ahd_get_scsi_status(scbp); 7189 if (ostat == CAM_REQ_INPROG) 7190 ahd_set_scsi_status(scbp, status); 7191 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7192 ahd_freeze_scb(scbp); 7193 if ((scbp->flags & SCB_ACTIVE) == 0) 7194 printf("Inactive SCB on pending list\n"); 7195 ahd_done(ahd, scbp); 7196 found++; 7197 } 7198 } 7199 ahd_restore_modes(ahd, saved_modes); 7200 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7201 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7202 return found; 7203 } 7204 7205 static void 7206 ahd_reset_current_bus(struct ahd_softc *ahd) 7207 { 7208 uint8_t scsiseq; 7209 7210 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7211 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7212 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7213 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7214 ahd_delay(AHD_BUSRESET_DELAY); 7215 /* Turn off the bus reset */ 7216 ahd_outb(ahd, SCSISEQ0, scsiseq); 7217 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7218 /* 7219 * 2A Razor #474 7220 * Certain chip state is not cleared for 7221 * SCSI bus resets that we initiate, so 7222 * we must reset the chip. 7223 */ 7224 ahd_delay(AHD_BUSRESET_DELAY); 7225 ahd_reset(ahd, /*reinit*/TRUE); 7226 ahd_intr_enable(ahd, /*enable*/TRUE); 7227 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7228 } 7229 7230 ahd_clear_intstat(ahd); 7231 } 7232 7233 int 7234 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7235 { 7236 struct ahd_devinfo devinfo; 7237 u_int initiator; 7238 u_int target; 7239 u_int max_scsiid; 7240 int found; 7241 u_int fifo; 7242 u_int next_fifo; 7243 7244 7245 ahd->pending_device = NULL; 7246 7247 ahd_compile_devinfo(&devinfo, 7248 CAM_TARGET_WILDCARD, 7249 CAM_TARGET_WILDCARD, 7250 CAM_LUN_WILDCARD, 7251 channel, ROLE_UNKNOWN); 7252 ahd_pause(ahd); 7253 7254 /* Make sure the sequencer is in a safe location. */ 7255 ahd_clear_critical_section(ahd); 7256 7257 #if AHD_TARGET_MODE 7258 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7259 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7260 } 7261 #endif 7262 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7263 7264 /* 7265 * Disable selections so no automatic hardware 7266 * functions will modify chip state. 7267 */ 7268 ahd_outb(ahd, SCSISEQ0, 0); 7269 ahd_outb(ahd, SCSISEQ1, 0); 7270 7271 /* 7272 * Safely shut down our DMA engines. Always start with 7273 * the FIFO that is not currently active (if any are 7274 * actively connected). 7275 */ 7276 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7277 if (next_fifo > CURRFIFO_1) 7278 /* If disconneced, arbitrarily start with FIFO1. */ 7279 next_fifo = fifo = 0; 7280 do { 7281 next_fifo ^= CURRFIFO_1; 7282 ahd_set_modes(ahd, next_fifo, next_fifo); 7283 ahd_outb(ahd, DFCNTRL, 7284 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7285 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7286 ahd_delay(10); 7287 /* 7288 * Set CURRFIFO to the now inactive channel. 7289 */ 7290 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7291 ahd_outb(ahd, DFFSTAT, next_fifo); 7292 } while (next_fifo != fifo); 7293 7294 /* 7295 * Reset the bus if we are initiating this reset 7296 */ 7297 ahd_clear_msg_state(ahd); 7298 ahd_outb(ahd, SIMODE1, 7299 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7300 7301 if (initiate_reset) 7302 ahd_reset_current_bus(ahd); 7303 7304 ahd_clear_intstat(ahd); 7305 7306 /* 7307 * Clean up all the state information for the 7308 * pending transactions on this bus. 7309 */ 7310 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7311 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7312 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7313 7314 /* 7315 * Cleanup anything left in the FIFOs. 7316 */ 7317 ahd_clear_fifo(ahd, 0); 7318 ahd_clear_fifo(ahd, 1); 7319 7320 /* 7321 * Revert to async/narrow transfers until we renegotiate. 7322 */ 7323 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7324 for (target = 0; target <= max_scsiid; target++) { 7325 7326 if (ahd->enabled_targets[target] == NULL) 7327 continue; 7328 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7329 struct ahd_devinfo devinfo; 7330 7331 ahd_compile_devinfo(&devinfo, target, initiator, 7332 CAM_LUN_WILDCARD, 7333 'A', ROLE_UNKNOWN); 7334 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7335 AHD_TRANS_CUR, /*paused*/TRUE); 7336 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7337 /*offset*/0, /*ppr_options*/0, 7338 AHD_TRANS_CUR, /*paused*/TRUE); 7339 } 7340 } 7341 7342 #ifdef AHD_TARGET_MODE 7343 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7344 7345 /* 7346 * Send an immediate notify ccb to all target more peripheral 7347 * drivers affected by this action. 7348 */ 7349 for (target = 0; target <= max_scsiid; target++) { 7350 struct ahd_tmode_tstate* tstate; 7351 u_int lun; 7352 7353 tstate = ahd->enabled_targets[target]; 7354 if (tstate == NULL) 7355 continue; 7356 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7357 struct ahd_tmode_lstate* lstate; 7358 7359 lstate = tstate->enabled_luns[lun]; 7360 if (lstate == NULL) 7361 continue; 7362 7363 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7364 EVENT_TYPE_BUS_RESET, /*arg*/0); 7365 ahd_send_lstate_events(ahd, lstate); 7366 } 7367 } 7368 #endif 7369 7370 /* Notify the XPT that a bus reset occurred */ 7371 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7372 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7373 ahd_restart(ahd); 7374 7375 /* 7376 * Freeze the SIMQ until our poller can determine that 7377 * the bus reset has really gone away. We set the initial 7378 * timer to 0 to have the check performed as soon as possible 7379 * from the timer context. 7380 */ 7381 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7382 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7383 ahd_freeze_simq(ahd); 7384 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7385 } 7386 return (found); 7387 } 7388 7389 7390 #define AHD_RESET_POLL_US 1000 7391 static void 7392 ahd_reset_poll(void *arg) 7393 { 7394 struct ahd_softc *ahd; 7395 u_int scsiseq1; 7396 u_long l; 7397 int s; 7398 7399 ahd_list_lock(&l); 7400 ahd = (void*)arg; 7401 if (ahd == NULL) { 7402 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7403 ahd_list_unlock(&l); 7404 return; 7405 } 7406 ahd_lock(ahd, &s); 7407 ahd_pause(ahd); 7408 ahd_update_modes(ahd); 7409 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7410 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7411 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7412 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7413 ahd_reset_poll, ahd); 7414 ahd_unpause(ahd); 7415 ahd_unlock(ahd, &s); 7416 ahd_list_unlock(&l); 7417 return; 7418 } 7419 7420 /* Reset is now low. Complete chip reinitialization. */ 7421 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7422 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7423 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7424 ahd_unpause(ahd); 7425 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7426 ahd_unlock(ahd, &s); 7427 ahd_release_simq(ahd); 7428 ahd_list_unlock(&l); 7429 } 7430 7431 /**************************** Statistics Processing ***************************/ 7432 static void 7433 ahd_stat_timer(void *arg) 7434 { 7435 struct ahd_softc *ahd; 7436 u_long l; 7437 int s; 7438 int enint_coal; 7439 7440 ahd_list_lock(&l); 7441 ahd = (void *)arg; 7442 if (ahd == NULL) { 7443 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7444 ahd_list_unlock(&l); 7445 return; 7446 } 7447 ahd_lock(ahd, &s); 7448 7449 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7450 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7451 enint_coal |= ENINT_COALESCE; 7452 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7453 enint_coal &= ~ENINT_COALESCE; 7454 7455 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 7456 ahd_enable_coalescing(ahd, enint_coal); 7457 #ifdef AHD_DEBUG 7458 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 7459 printf("%s: Interrupt coalescing " 7460 "now %sabled. Cmds %d\n", 7461 ahd_name(ahd), 7462 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 7463 ahd->cmdcmplt_total); 7464 #endif 7465 } 7466 7467 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7468 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7469 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7470 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7471 ahd_stat_timer, ahd); 7472 ahd_unlock(ahd, &s); 7473 ahd_list_unlock(&l); 7474 } 7475 7476 /****************************** Status Processing *****************************/ 7477 void 7478 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7479 { 7480 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7481 ahd_handle_scsi_status(ahd, scb); 7482 } else { 7483 ahd_calc_residual(ahd, scb); 7484 ahd_done(ahd, scb); 7485 } 7486 } 7487 7488 void 7489 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7490 { 7491 struct hardware_scb *hscb; 7492 u_int qfreeze_cnt; 7493 7494 /* 7495 * The sequencer freezes its select-out queue 7496 * anytime a SCSI status error occurs. We must 7497 * handle the error and decrement the QFREEZE count 7498 * to allow the sequencer to continue. 7499 */ 7500 hscb = scb->hscb; 7501 7502 /* Freeze the queue until the client sees the error. */ 7503 ahd_freeze_devq(ahd, scb); 7504 ahd_freeze_scb(scb); 7505 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7506 if (qfreeze_cnt == 0) { 7507 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7508 } else { 7509 qfreeze_cnt--; 7510 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7511 } 7512 if (qfreeze_cnt == 0) 7513 ahd_outb(ahd, SEQ_FLAGS2, 7514 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7515 7516 /* Don't want to clobber the original sense code */ 7517 if ((scb->flags & SCB_SENSE) != 0) { 7518 /* 7519 * Clear the SCB_SENSE Flag and perform 7520 * a normal command completion. 7521 */ 7522 scb->flags &= ~SCB_SENSE; 7523 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7524 ahd_done(ahd, scb); 7525 return; 7526 } 7527 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7528 ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7529 switch (hscb->shared_data.istatus.scsi_status) { 7530 case STATUS_PKT_SENSE: 7531 { 7532 struct scsi_status_iu_header *siu; 7533 7534 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7535 siu = (struct scsi_status_iu_header *)scb->sense_data; 7536 ahd_set_scsi_status(scb, siu->status); 7537 #ifdef AHD_DEBUG 7538 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7539 ahd_print_path(ahd, scb); 7540 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7541 SCB_GET_TAG(scb), siu->status); 7542 } 7543 #endif 7544 if ((siu->flags & SIU_RSPVALID) != 0) { 7545 scsipi_printaddr(scb->xs->xs_periph); 7546 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7547 printf("Unable to parse pkt_failures\n"); 7548 } else { 7549 7550 switch (SIU_PKTFAIL_CODE(siu)) { 7551 case SIU_PFC_NONE: 7552 printf("No packet failure found\n"); 7553 break; 7554 case SIU_PFC_CIU_FIELDS_INVALID: 7555 printf("Invalid Command IU Field\n"); 7556 break; 7557 case SIU_PFC_TMF_NOT_SUPPORTED: 7558 printf("TMF not supportd\n"); 7559 break; 7560 case SIU_PFC_TMF_FAILED: 7561 printf("TMF failed\n"); 7562 break; 7563 case SIU_PFC_INVALID_TYPE_CODE: 7564 printf("Invalid L_Q Type code\n"); 7565 break; 7566 case SIU_PFC_ILLEGAL_REQUEST: 7567 printf("Illegal request\n"); 7568 default: 7569 break; 7570 } 7571 } 7572 if (siu->status == SCSI_STATUS_OK) 7573 ahd_set_transaction_status(scb, CAM_REQ_CMP_ERR); 7574 } 7575 if ((siu->flags & SIU_SNSVALID) != 0) { 7576 scb->flags |= SCB_PKT_SENSE; 7577 #ifdef AHD_DEBUG 7578 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7579 printf("Sense data available (%d)\n", siu->sense_length[0]); 7580 printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7581 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7582 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+12]), 7583 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+13])); 7584 } 7585 #endif 7586 } 7587 ahd_done(ahd, scb); 7588 break; 7589 } 7590 case SCSI_STATUS_CMD_TERMINATED: 7591 case SCSI_STATUS_CHECK_COND: 7592 { 7593 struct ahd_devinfo devinfo; 7594 struct ahd_dma_seg *sg; 7595 struct scsipi_sense *sc; 7596 struct ahd_initiator_tinfo *targ_info; 7597 struct ahd_tmode_tstate *tstate; 7598 struct ahd_transinfo *tinfo; 7599 #ifdef AHD_DEBUG 7600 if (ahd_debug & AHD_SHOW_SENSE) { 7601 ahd_print_path(ahd, scb); 7602 printf("SCB %d: requests Check Status\n", 7603 SCB_GET_TAG(scb)); 7604 } 7605 #endif 7606 7607 if (ahd_perform_autosense(scb) == 0) 7608 break; 7609 7610 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7611 SCB_GET_TARGET(ahd, scb), 7612 SCB_GET_LUN(scb), 7613 SCB_GET_CHANNEL(ahd, scb), 7614 ROLE_INITIATOR); 7615 targ_info = ahd_fetch_transinfo(ahd, 7616 devinfo.channel, 7617 devinfo.our_scsiid, 7618 devinfo.target, 7619 &tstate); 7620 tinfo = &targ_info->curr; 7621 sg = scb->sg_list; 7622 sc = (struct scsipi_sense *)hscb->shared_data.idata.cdb; 7623 /* 7624 * Save off the residual if there is one. 7625 */ 7626 ahd_update_residual(ahd, scb); 7627 #ifdef AHD_DEBUG 7628 if (ahd_debug & AHD_SHOW_SENSE) { 7629 ahd_print_path(ahd, scb); 7630 printf("Sending Sense\n"); 7631 } 7632 #endif 7633 scb->sg_count = 0; 7634 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7635 ahd_get_sense_bufsize(ahd, scb), 7636 /*last*/TRUE); 7637 sc->opcode = REQUEST_SENSE; 7638 sc->byte2 = 0; 7639 sc->unused[0] = 0; 7640 sc->unused[1] = 0; 7641 sc->length = ahd_get_sense_bufsize(ahd, scb); 7642 sc->control = 0; 7643 7644 /* 7645 * We can't allow the target to disconnect. 7646 * This will be an untagged transaction and 7647 * having the target disconnect will make this 7648 * transaction indestinguishable from outstanding 7649 * tagged transactions. 7650 */ 7651 hscb->control = 0; 7652 7653 /* 7654 * This request sense could be because the 7655 * the device lost power or in some other 7656 * way has lost our transfer negotiations. 7657 * Renegotiate if appropriate. Unit attention 7658 * errors will be reported before any data 7659 * phases occur. 7660 */ 7661 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7662 ahd_update_neg_request(ahd, &devinfo, 7663 tstate, targ_info, 7664 AHD_NEG_IF_NON_ASYNC); 7665 } 7666 if (tstate->auto_negotiate & devinfo.target_mask) { 7667 hscb->control |= MK_MESSAGE; 7668 scb->flags &= 7669 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7670 scb->flags |= SCB_AUTO_NEGOTIATE; 7671 } 7672 hscb->cdb_len = sizeof(*sc); 7673 ahd_setup_data_scb(ahd, scb); 7674 scb->flags |= SCB_SENSE; 7675 ahd_queue_scb(ahd, scb); 7676 /* 7677 * Ensure we have enough time to actually 7678 * retrieve the sense. 7679 */ 7680 ahd_scb_timer_reset(scb, 5 * 1000000); 7681 break; 7682 } 7683 case SCSI_STATUS_OK: 7684 printf("%s: Interrupted for status of 0? (SCB 0x%x)\n", 7685 ahd_name(ahd), SCB_GET_TAG(scb)); 7686 /* FALLTHROUGH */ 7687 default: 7688 ahd_done(ahd, scb); 7689 break; 7690 } 7691 } 7692 7693 /* 7694 * Calculate the residual for a just completed SCB. 7695 */ 7696 void 7697 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7698 { 7699 struct hardware_scb *hscb; 7700 struct initiator_status *spkt; 7701 uint32_t sgptr; 7702 uint32_t resid_sgptr; 7703 uint32_t resid; 7704 7705 /* 7706 * 5 cases. 7707 * 1) No residual. 7708 * SG_STATUS_VALID clear in sgptr. 7709 * 2) Transferless command 7710 * 3) Never performed any transfers. 7711 * sgptr has SG_FULL_RESID set. 7712 * 4) No residual but target did not 7713 * save data pointers after the 7714 * last transfer, so sgptr was 7715 * never updated. 7716 * 5) We have a partial residual. 7717 * Use residual_sgptr to determine 7718 * where we are. 7719 */ 7720 7721 hscb = scb->hscb; 7722 sgptr = ahd_le32toh(hscb->sgptr); 7723 if ((sgptr & SG_STATUS_VALID) == 0) 7724 /* Case 1 */ 7725 return; 7726 sgptr &= ~SG_STATUS_VALID; 7727 7728 if ((sgptr & SG_LIST_NULL) != 0) 7729 /* Case 2 */ 7730 return; 7731 7732 /* 7733 * Residual fields are the same in both 7734 * target and initiator status packets, 7735 * so we can always use the initiator fields 7736 * regardless of the role for this SCB. 7737 */ 7738 spkt = &hscb->shared_data.istatus; 7739 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7740 if ((sgptr & SG_FULL_RESID) != 0) { 7741 /* Case 3 */ 7742 resid = ahd_get_transfer_length(scb); 7743 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7744 /* Case 4 */ 7745 return; 7746 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7747 ahd_print_path(ahd, scb); 7748 printf("data overrun detected Tag == 0x%x.\n", 7749 SCB_GET_TAG(scb)); 7750 ahd_freeze_devq(ahd, scb); 7751 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7752 ahd_freeze_scb(scb); 7753 return; 7754 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7755 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7756 /* NOTREACHED */ 7757 } else { 7758 struct ahd_dma_seg *sg; 7759 7760 /* 7761 * Remainder of the SG where the transfer 7762 * stopped. 7763 */ 7764 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7765 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7766 7767 /* The residual sg_ptr always points to the next sg */ 7768 sg--; 7769 7770 /* 7771 * Add up the contents of all residual 7772 * SG segments that are after the SG where 7773 * the transfer stopped. 7774 */ 7775 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7776 sg++; 7777 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7778 } 7779 } 7780 7781 if ((scb->flags & SCB_SENSE) == 0) 7782 ahd_set_residual(scb, resid); 7783 /*else 7784 ahd_set_sense_residual(scb, resid);*/ 7785 7786 #ifdef AHD_DEBUG 7787 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7788 ahd_print_path(ahd, scb); 7789 printf("Handled %sResidual of %d bytes\n", 7790 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7791 } 7792 #endif 7793 } 7794 7795 /******************************* Target Mode **********************************/ 7796 #ifdef AHD_TARGET_MODE 7797 /* 7798 * Add a target mode event to this lun's queue 7799 */ 7800 static void 7801 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 7802 u_int initiator_id, u_int event_type, u_int event_arg) 7803 { 7804 struct ahd_tmode_event *event; 7805 int pending; 7806 7807 xpt_freeze_devq(lstate->path, /*count*/1); 7808 if (lstate->event_w_idx >= lstate->event_r_idx) 7809 pending = lstate->event_w_idx - lstate->event_r_idx; 7810 else 7811 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 7812 - (lstate->event_r_idx - lstate->event_w_idx); 7813 7814 if (event_type == EVENT_TYPE_BUS_RESET 7815 || event_type == MSG_BUS_DEV_RESET) { 7816 /* 7817 * Any earlier events are irrelevant, so reset our buffer. 7818 * This has the effect of allowing us to deal with reset 7819 * floods (an external device holding down the reset line) 7820 * without losing the event that is really interesting. 7821 */ 7822 lstate->event_r_idx = 0; 7823 lstate->event_w_idx = 0; 7824 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 7825 } 7826 7827 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 7828 xpt_print_path(lstate->path); 7829 printf("immediate event %x:%x lost\n", 7830 lstate->event_buffer[lstate->event_r_idx].event_type, 7831 lstate->event_buffer[lstate->event_r_idx].event_arg); 7832 lstate->event_r_idx++; 7833 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7834 lstate->event_r_idx = 0; 7835 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 7836 } 7837 7838 event = &lstate->event_buffer[lstate->event_w_idx]; 7839 event->initiator_id = initiator_id; 7840 event->event_type = event_type; 7841 event->event_arg = event_arg; 7842 lstate->event_w_idx++; 7843 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7844 lstate->event_w_idx = 0; 7845 } 7846 7847 /* 7848 * Send any target mode events queued up waiting 7849 * for immediate notify resources. 7850 */ 7851 void 7852 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 7853 { 7854 struct ccb_hdr *ccbh; 7855 struct ccb_immed_notify *inot; 7856 7857 while (lstate->event_r_idx != lstate->event_w_idx 7858 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 7859 struct ahd_tmode_event *event; 7860 7861 event = &lstate->event_buffer[lstate->event_r_idx]; 7862 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 7863 inot = (struct ccb_immed_notify *)ccbh; 7864 switch (event->event_type) { 7865 case EVENT_TYPE_BUS_RESET: 7866 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 7867 break; 7868 default: 7869 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 7870 inot->message_args[0] = event->event_type; 7871 inot->message_args[1] = event->event_arg; 7872 break; 7873 } 7874 inot->initiator_id = event->initiator_id; 7875 inot->sense_len = 0; 7876 xpt_done((union ccb *)inot); 7877 lstate->event_r_idx++; 7878 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7879 lstate->event_r_idx = 0; 7880 } 7881 } 7882 #endif 7883 7884 /******************** Sequencer Program Patching/Download *********************/ 7885 7886 #ifdef AHD_DUMP_SEQ 7887 void 7888 ahd_dumpseq(struct ahd_softc* ahd) 7889 { 7890 int i; 7891 int max_prog; 7892 7893 max_prog = 2048; 7894 7895 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 7896 ahd_outb(ahd, PRGMCNT, 0); 7897 ahd_outb(ahd, PRGMCNT+1, 0); 7898 for (i = 0; i < max_prog; i++) { 7899 uint8_t ins_bytes[4]; 7900 7901 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 7902 printf("0x%08x\n", ins_bytes[0] << 24 7903 | ins_bytes[1] << 16 7904 | ins_bytes[2] << 8 7905 | ins_bytes[3]); 7906 } 7907 } 7908 #endif 7909 7910 static void 7911 ahd_loadseq(struct ahd_softc *ahd) 7912 { 7913 struct cs cs_table[num_critical_sections]; 7914 u_int begin_set[num_critical_sections]; 7915 u_int end_set[num_critical_sections]; 7916 struct patch *cur_patch; 7917 u_int cs_count; 7918 u_int cur_cs; 7919 u_int i; 7920 int downloaded; 7921 u_int skip_addr; 7922 u_int sg_prefetch_cnt; 7923 u_int sg_prefetch_cnt_limit; 7924 u_int sg_prefetch_align; 7925 u_int sg_size; 7926 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 7927 7928 if (bootverbose) 7929 printf("%s: Downloading Sequencer Program...", 7930 ahd_name(ahd)); 7931 7932 #if DOWNLOAD_CONST_COUNT != 7 7933 #error "Download Const Mismatch" 7934 #endif 7935 /* 7936 * Start out with 0 critical sections 7937 * that apply to this firmware load. 7938 */ 7939 cs_count = 0; 7940 cur_cs = 0; 7941 memset(begin_set, 0, sizeof(begin_set)); 7942 memset(end_set, 0, sizeof(end_set)); 7943 7944 /* 7945 * Setup downloadable constant table. 7946 * 7947 * The computation for the S/G prefetch variables is 7948 * a bit complicated. We would like to always fetch 7949 * in terms of cachelined sized increments. However, 7950 * if the cacheline is not an even multiple of the 7951 * SG element size or is larger than our SG RAM, using 7952 * just the cache size might leave us with only a portion 7953 * of an SG element at the tail of a prefetch. If the 7954 * cacheline is larger than our S/G prefetch buffer less 7955 * the size of an SG element, we may round down to a cacheline 7956 * that doesn't contain any or all of the S/G of interest 7957 * within the bounds of our S/G ram. Provide variables to 7958 * the sequencer that will allow it to handle these edge 7959 * cases. 7960 */ 7961 /* Start by aligning to the nearest cacheline. */ 7962 sg_prefetch_align = ahd->pci_cachesize; 7963 if (sg_prefetch_align == 0) 7964 sg_prefetch_align = 8; 7965 /* Round down to the nearest power of 2. */ 7966 while (powerof2(sg_prefetch_align) == 0) 7967 sg_prefetch_align--; 7968 /* 7969 * If the cacheline boundary is greater than half our prefetch RAM 7970 * we risk not being able to fetch even a single complete S/G 7971 * segment if we align to that boundary. 7972 */ 7973 if (sg_prefetch_align > CCSGADDR_MAX/2) 7974 sg_prefetch_align = CCSGADDR_MAX/2; 7975 /* Start by fetching a single cacheline. */ 7976 sg_prefetch_cnt = sg_prefetch_align; 7977 /* 7978 * Increment the prefetch count by cachelines until 7979 * at least one S/G element will fit. 7980 */ 7981 sg_size = sizeof(struct ahd_dma_seg); 7982 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 7983 sg_size = sizeof(struct ahd_dma64_seg); 7984 while (sg_prefetch_cnt < sg_size) 7985 sg_prefetch_cnt += sg_prefetch_align; 7986 /* 7987 * If the cacheline is not an even multiple of 7988 * the S/G size, we may only get a partial S/G when 7989 * we align. Add a cacheline if this is the case. 7990 */ 7991 if ((sg_prefetch_align % sg_size) != 0 7992 && (sg_prefetch_cnt < CCSGADDR_MAX)) 7993 sg_prefetch_cnt += sg_prefetch_align; 7994 /* 7995 * Lastly, compute a value that the sequencer can use 7996 * to determine if the remainder of the CCSGRAM buffer 7997 * has a full S/G element in it. 7998 */ 7999 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8000 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8001 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8002 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8003 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8004 download_consts[SG_SIZEOF] = sg_size; 8005 download_consts[PKT_OVERRUN_BUFOFFSET] = 8006 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8007 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8008 cur_patch = patches; 8009 downloaded = 0; 8010 skip_addr = 0; 8011 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8012 ahd_outb(ahd, PRGMCNT, 0); 8013 ahd_outb(ahd, PRGMCNT+1, 0); 8014 8015 for (i = 0; i < sizeof(seqprog)/4; i++) { 8016 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8017 /* 8018 * Don't download this instruction as it 8019 * is in a patch that was removed. 8020 */ 8021 continue; 8022 } 8023 /* 8024 * Move through the CS table until we find a CS 8025 * that might apply to this instruction. 8026 */ 8027 for (; cur_cs < num_critical_sections; cur_cs++) { 8028 if (critical_sections[cur_cs].end <= i) { 8029 if (begin_set[cs_count] == TRUE 8030 && end_set[cs_count] == FALSE) { 8031 cs_table[cs_count].end = downloaded; 8032 end_set[cs_count] = TRUE; 8033 cs_count++; 8034 } 8035 continue; 8036 } 8037 if (critical_sections[cur_cs].begin <= i 8038 && begin_set[cs_count] == FALSE) { 8039 cs_table[cs_count].begin = downloaded; 8040 begin_set[cs_count] = TRUE; 8041 } 8042 break; 8043 } 8044 ahd_download_instr(ahd, i, download_consts); 8045 downloaded++; 8046 } 8047 8048 ahd->num_critical_sections = cs_count; 8049 if (cs_count != 0) { 8050 8051 cs_count *= sizeof(struct cs); 8052 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8053 if (ahd->critical_sections == NULL) 8054 panic("ahd_loadseq: Could not malloc"); 8055 memcpy(ahd->critical_sections, cs_table, cs_count); 8056 } 8057 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8058 8059 if (bootverbose) { 8060 printf(" %d instructions downloaded\n", downloaded); 8061 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8062 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8063 } 8064 } 8065 8066 static int 8067 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8068 u_int start_instr, u_int *skip_addr) 8069 { 8070 struct patch *cur_patch; 8071 struct patch *last_patch; 8072 u_int num_patches; 8073 8074 num_patches = sizeof(patches)/sizeof(struct patch); 8075 last_patch = &patches[num_patches]; 8076 cur_patch = *start_patch; 8077 8078 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8079 8080 if (cur_patch->patch_func(ahd) == 0) { 8081 8082 /* Start rejecting code */ 8083 *skip_addr = start_instr + cur_patch->skip_instr; 8084 cur_patch += cur_patch->skip_patch; 8085 } else { 8086 /* Accepted this patch. Advance to the next 8087 * one and wait for our intruction pointer to 8088 * hit this point. 8089 */ 8090 cur_patch++; 8091 } 8092 } 8093 8094 *start_patch = cur_patch; 8095 if (start_instr < *skip_addr) 8096 /* Still skipping */ 8097 return (0); 8098 8099 return (1); 8100 } 8101 8102 static u_int 8103 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8104 { 8105 struct patch *cur_patch; 8106 int address_offset; 8107 u_int skip_addr; 8108 u_int i; 8109 8110 address_offset = 0; 8111 cur_patch = patches; 8112 skip_addr = 0; 8113 8114 for (i = 0; i < address;) { 8115 8116 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8117 8118 if (skip_addr > i) { 8119 int end_addr; 8120 8121 end_addr = MIN(address, skip_addr); 8122 address_offset += end_addr - i; 8123 i = skip_addr; 8124 } else { 8125 i++; 8126 } 8127 } 8128 return (address - address_offset); 8129 } 8130 8131 static void 8132 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8133 { 8134 union ins_formats instr; 8135 struct ins_format1 *fmt1_ins; 8136 struct ins_format3 *fmt3_ins; 8137 u_int opcode; 8138 8139 /* 8140 * The firmware is always compiled into a little endian format. 8141 */ 8142 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8143 8144 fmt1_ins = &instr.format1; 8145 fmt3_ins = NULL; 8146 8147 /* Pull the opcode */ 8148 opcode = instr.format1.opcode; 8149 switch (opcode) { 8150 case AIC_OP_JMP: 8151 case AIC_OP_JC: 8152 case AIC_OP_JNC: 8153 case AIC_OP_CALL: 8154 case AIC_OP_JNE: 8155 case AIC_OP_JNZ: 8156 case AIC_OP_JE: 8157 case AIC_OP_JZ: 8158 { 8159 fmt3_ins = &instr.format3; 8160 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8161 /* FALLTHROUGH */ 8162 } 8163 case AIC_OP_OR: 8164 case AIC_OP_AND: 8165 case AIC_OP_XOR: 8166 case AIC_OP_ADD: 8167 case AIC_OP_ADC: 8168 case AIC_OP_BMOV: 8169 if (fmt1_ins->parity != 0) { 8170 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8171 } 8172 fmt1_ins->parity = 0; 8173 /* FALLTHROUGH */ 8174 case AIC_OP_ROL: 8175 { 8176 int i, count; 8177 8178 /* Calculate odd parity for the instruction */ 8179 for (i = 0, count = 0; i < 31; i++) { 8180 uint32_t mask; 8181 8182 mask = 0x01 << i; 8183 if ((instr.integer & mask) != 0) 8184 count++; 8185 } 8186 if ((count & 0x01) == 0) 8187 instr.format1.parity = 1; 8188 8189 /* The sequencer is a little endian cpu */ 8190 instr.integer = ahd_htole32(instr.integer); 8191 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8192 break; 8193 } 8194 default: 8195 panic("Unknown opcode encountered in seq program"); 8196 break; 8197 } 8198 } 8199 8200 static int 8201 ahd_probe_stack_size(struct ahd_softc *ahd) 8202 { 8203 int last_probe; 8204 8205 last_probe = 0; 8206 while (1) { 8207 int i; 8208 8209 /* 8210 * We avoid using 0 as a pattern to avoid 8211 * confusion if the stack implementation 8212 * "back-fills" with zeros when "poping' 8213 * entries. 8214 */ 8215 for (i = 1; i <= last_probe+1; i++) { 8216 ahd_outb(ahd, STACK, i & 0xFF); 8217 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8218 } 8219 8220 /* Verify */ 8221 for (i = last_probe+1; i > 0; i--) { 8222 u_int stack_entry; 8223 8224 stack_entry = ahd_inb(ahd, STACK) 8225 |(ahd_inb(ahd, STACK) << 8); 8226 if (stack_entry != i) 8227 goto sized; 8228 } 8229 last_probe++; 8230 } 8231 sized: 8232 return (last_probe); 8233 } 8234 8235 void 8236 ahd_dump_all_cards_state(void) 8237 { 8238 struct ahd_softc *list_ahd; 8239 8240 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8241 ahd_dump_card_state(list_ahd); 8242 } 8243 } 8244 8245 int 8246 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8247 const char *name, u_int address, u_int value, 8248 u_int *cur_column, u_int wrap_point) 8249 { 8250 int printed; 8251 u_int printed_mask; 8252 char line[1024]; 8253 8254 line[0] = 0; 8255 8256 if (cur_column != NULL && *cur_column >= wrap_point) { 8257 printf("\n"); 8258 *cur_column = 0; 8259 } 8260 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8261 if (table == NULL) { 8262 printed += snprintf(&line[printed], (sizeof line) - printed, 8263 " "); 8264 printf("%s", line); 8265 if (cur_column != NULL) 8266 *cur_column += printed; 8267 return (printed); 8268 } 8269 printed_mask = 0; 8270 while (printed_mask != 0xFF) { 8271 int entry; 8272 8273 for (entry = 0; entry < num_entries; entry++) { 8274 if (((value & table[entry].mask) 8275 != table[entry].value) 8276 || ((printed_mask & table[entry].mask) 8277 == table[entry].mask)) 8278 continue; 8279 printed += snprintf(&line[printed], 8280 (sizeof line) - printed, "%s%s", 8281 printed_mask == 0 ? ":(" : "|", 8282 table[entry].name); 8283 printed_mask |= table[entry].mask; 8284 8285 break; 8286 } 8287 if (entry >= num_entries) 8288 break; 8289 } 8290 if (printed_mask != 0) 8291 printed += snprintf(&line[printed], 8292 (sizeof line) - printed, ") "); 8293 else 8294 printed += snprintf(&line[printed], 8295 (sizeof line) - printed, " "); 8296 if (cur_column != NULL) 8297 *cur_column += printed; 8298 printf("%s", line); 8299 8300 return (printed); 8301 } 8302 8303 void 8304 ahd_dump_card_state(struct ahd_softc *ahd) 8305 { 8306 struct scb *scb; 8307 ahd_mode_state saved_modes; 8308 u_int dffstat; 8309 int paused; 8310 u_int scb_index; 8311 u_int saved_scb_index; 8312 u_int cur_col; 8313 int i; 8314 8315 if (ahd_is_paused(ahd)) { 8316 paused = 1; 8317 } else { 8318 paused = 0; 8319 ahd_pause(ahd); 8320 } 8321 saved_modes = ahd_save_modes(ahd); 8322 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8323 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8324 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8325 ahd_name(ahd), 8326 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8327 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8328 ahd->saved_dst_mode)); 8329 if (paused) 8330 printf("Card was paused\n"); 8331 /* 8332 * Mode independent registers. 8333 */ 8334 cur_col = 0; 8335 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8336 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8337 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8338 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8339 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8340 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8341 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8342 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8343 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8344 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8345 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8346 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8347 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8348 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8349 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8350 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8351 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8352 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8353 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8354 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8355 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8356 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8357 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8358 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8359 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8360 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8361 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8362 printf("\n"); 8363 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8364 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8365 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8366 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8367 ahd_inw(ahd, NEXTSCB)); 8368 cur_col = 0; 8369 /* QINFIFO */ 8370 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8371 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8372 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8373 saved_scb_index = ahd_get_scbptr(ahd); 8374 printf("Pending list:"); 8375 i = 0; 8376 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8377 if (i++ > AHD_SCB_MAX) 8378 break; 8379 /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8380 ahd_inb(ahd, SCB_FIFO_USE_COUNT)); 8381 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8382 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8383 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8384 } 8385 printf("\nTotal %d\n", i); 8386 8387 printf("Kernel Free SCB list: "); 8388 i = 0; 8389 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8390 struct scb *list_scb; 8391 8392 list_scb = scb; 8393 do { 8394 printf("%d ", SCB_GET_TAG(list_scb)); 8395 list_scb = LIST_NEXT(list_scb, collision_links); 8396 } while (list_scb && i++ < AHD_SCB_MAX); 8397 } 8398 8399 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8400 if (i++ > AHD_SCB_MAX) 8401 break; 8402 printf("%d ", SCB_GET_TAG(scb)); 8403 } 8404 printf("\n"); 8405 8406 printf("Sequencer Complete DMA-inprog list: "); 8407 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8408 i = 0; 8409 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8410 ahd_set_scbptr(ahd, scb_index); 8411 printf("%d ", scb_index); 8412 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8413 } 8414 printf("\n"); 8415 8416 printf("Sequencer Complete list: "); 8417 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8418 i = 0; 8419 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8420 ahd_set_scbptr(ahd, scb_index); 8421 printf("%d ", scb_index); 8422 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8423 } 8424 printf("\n"); 8425 8426 8427 printf("Sequencer DMA-Up and Complete list: "); 8428 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8429 i = 0; 8430 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8431 ahd_set_scbptr(ahd, scb_index); 8432 printf("%d ", scb_index); 8433 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8434 } 8435 printf("\n"); 8436 ahd_set_scbptr(ahd, saved_scb_index); 8437 dffstat = ahd_inb(ahd, DFFSTAT); 8438 for (i = 0; i < 2; i++) { 8439 #ifdef AHD_DEBUG 8440 struct scb *fifo_scb; 8441 #endif 8442 u_int fifo_scbptr; 8443 8444 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8445 fifo_scbptr = ahd_get_scbptr(ahd); 8446 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8447 ahd_name(ahd), i, 8448 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8449 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 8450 cur_col = 0; 8451 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8452 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8453 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8454 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8455 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8456 &cur_col, 50); 8457 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8458 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8459 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8460 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8461 if (cur_col > 50) { 8462 printf("\n"); 8463 cur_col = 0; 8464 } 8465 printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8466 ahd_inl(ahd, SHADDR+4), 8467 ahd_inl(ahd, SHADDR), 8468 (ahd_inb(ahd, SHCNT) 8469 | (ahd_inb(ahd, SHCNT + 1) << 8) 8470 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8471 printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8472 ahd_inl(ahd, HADDR+4), 8473 ahd_inl(ahd, HADDR), 8474 (ahd_inb(ahd, HCNT) 8475 | (ahd_inb(ahd, HCNT + 1) << 8) 8476 | (ahd_inb(ahd, HCNT + 2) << 16))); 8477 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8478 #ifdef AHD_DEBUG 8479 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8480 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8481 if (fifo_scb != NULL) 8482 ahd_dump_sglist(fifo_scb); 8483 } 8484 #endif 8485 } 8486 printf("\nLQIN: "); 8487 for (i = 0; i < 20; i++) 8488 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8489 printf("\n"); 8490 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8491 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8492 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8493 ahd_inb(ahd, OPTIONMODE)); 8494 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8495 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8496 ahd_inb(ahd, MAXCMDCNT)); 8497 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8498 printf("\n"); 8499 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8500 cur_col = 0; 8501 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8502 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8503 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8504 ahd_inw(ahd, DINDEX)); 8505 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8506 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8507 ahd_inw(ahd, SCB_NEXT2)); 8508 printf("CDB %x %x %x %x %x %x\n", 8509 ahd_inb(ahd, SCB_CDB_STORE), 8510 ahd_inb(ahd, SCB_CDB_STORE+1), 8511 ahd_inb(ahd, SCB_CDB_STORE+2), 8512 ahd_inb(ahd, SCB_CDB_STORE+3), 8513 ahd_inb(ahd, SCB_CDB_STORE+4), 8514 ahd_inb(ahd, SCB_CDB_STORE+5)); 8515 printf("STACK:"); 8516 for (i = 0; i < ahd->stack_size; i++) { 8517 ahd->saved_stack[i] = 8518 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8519 printf(" 0x%x", ahd->saved_stack[i]); 8520 } 8521 for (i = ahd->stack_size-1; i >= 0; i--) { 8522 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8523 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8524 } 8525 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8526 ahd_platform_dump_card_state(ahd); 8527 ahd_restore_modes(ahd, saved_modes); 8528 if (paused == 0) 8529 ahd_unpause(ahd); 8530 } 8531 8532 void 8533 ahd_dump_scbs(struct ahd_softc *ahd) 8534 { 8535 ahd_mode_state saved_modes; 8536 u_int saved_scb_index; 8537 int i; 8538 8539 saved_modes = ahd_save_modes(ahd); 8540 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8541 saved_scb_index = ahd_get_scbptr(ahd); 8542 for (i = 0; i < AHD_SCB_MAX; i++) { 8543 ahd_set_scbptr(ahd, i); 8544 printf("%3d", i); 8545 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8546 ahd_inb(ahd, SCB_CONTROL), 8547 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8548 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8549 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8550 } 8551 printf("\n"); 8552 ahd_set_scbptr(ahd, saved_scb_index); 8553 ahd_restore_modes(ahd, saved_modes); 8554 } 8555 8556 /**************************** Flexport Logic **********************************/ 8557 /* 8558 * Read count 16bit words from 16bit word address start_addr from the 8559 * SEEPROM attached to the controller, into buf, using the controller's 8560 * SEEPROM reading state machine. Optionally treat the data as a byte 8561 * stream in terms of byte order. 8562 */ 8563 int 8564 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8565 u_int start_addr, u_int count, int bytestream) 8566 { 8567 u_int cur_addr; 8568 u_int end_addr; 8569 int error; 8570 8571 /* 8572 * If we never make it through the loop even once, 8573 * we were passed invalid arguments. 8574 */ 8575 error = EINVAL; 8576 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8577 end_addr = start_addr + count; 8578 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8579 8580 ahd_outb(ahd, SEEADR, cur_addr); 8581 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8582 8583 error = ahd_wait_seeprom(ahd); 8584 if (error) { 8585 printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd)); 8586 break; 8587 } 8588 if (bytestream != 0) { 8589 uint8_t *bytestream_ptr; 8590 8591 bytestream_ptr = (uint8_t *)buf; 8592 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 8593 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 8594 } else { 8595 /* 8596 * ahd_inw() already handles machine byte order. 8597 */ 8598 *buf = ahd_inw(ahd, SEEDAT); 8599 } 8600 buf++; 8601 } 8602 return (error); 8603 } 8604 8605 /* 8606 * Write count 16bit words from buf, into SEEPROM attache to the 8607 * controller starting at 16bit word address start_addr, using the 8608 * controller's SEEPROM writing state machine. 8609 */ 8610 int 8611 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8612 u_int start_addr, u_int count) 8613 { 8614 u_int cur_addr; 8615 u_int end_addr; 8616 int error; 8617 int retval; 8618 8619 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8620 error = ENOENT; 8621 8622 /* Place the chip into write-enable mode */ 8623 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8624 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8625 error = ahd_wait_seeprom(ahd); 8626 if (error) 8627 return (error); 8628 8629 /* 8630 * Write the data. If we don't get throught the loop at 8631 * least once, the arguments were invalid. 8632 */ 8633 retval = EINVAL; 8634 end_addr = start_addr + count; 8635 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8636 ahd_outw(ahd, SEEDAT, *buf++); 8637 ahd_outb(ahd, SEEADR, cur_addr); 8638 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8639 8640 retval = ahd_wait_seeprom(ahd); 8641 if (retval) 8642 break; 8643 } 8644 8645 /* 8646 * Disable writes. 8647 */ 8648 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8649 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8650 error = ahd_wait_seeprom(ahd); 8651 if (error) 8652 return (error); 8653 return (retval); 8654 } 8655 8656 /* 8657 * Wait ~100us for the serial eeprom to satisfy our request. 8658 */ 8659 int 8660 ahd_wait_seeprom(struct ahd_softc *ahd) 8661 { 8662 int cnt; 8663 8664 cnt = 2000; 8665 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8666 ahd_delay(5); 8667 8668 if (cnt == 0) 8669 return (ETIMEDOUT); 8670 return (0); 8671 } 8672 8673 /* 8674 * Validate the two checksums in the per_channel 8675 * vital product data struct. 8676 */ 8677 int 8678 ahd_verify_vpd_cksum(struct vpd_config *vpd) 8679 { 8680 int i; 8681 int maxaddr; 8682 uint32_t checksum; 8683 uint8_t *vpdarray; 8684 8685 vpdarray = (uint8_t *)vpd; 8686 maxaddr = offsetof(struct vpd_config, vpd_checksum); 8687 checksum = 0; 8688 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 8689 checksum = checksum + vpdarray[i]; 8690 if (checksum == 0 8691 || (-checksum & 0xFF) != vpd->vpd_checksum) 8692 return (0); 8693 8694 checksum = 0; 8695 maxaddr = offsetof(struct vpd_config, checksum); 8696 for (i = offsetof(struct vpd_config, default_target_flags); 8697 i < maxaddr; i++) 8698 checksum = checksum + vpdarray[i]; 8699 if (checksum == 0 8700 || (-checksum & 0xFF) != vpd->checksum) 8701 return (0); 8702 return (1); 8703 } 8704 8705 int 8706 ahd_verify_cksum(struct seeprom_config *sc) 8707 { 8708 int i; 8709 int maxaddr; 8710 uint32_t checksum; 8711 uint16_t *scarray; 8712 8713 maxaddr = (sizeof(*sc)/2) - 1; 8714 checksum = 0; 8715 scarray = (uint16_t *)sc; 8716 8717 for (i = 0; i < maxaddr; i++) 8718 checksum = checksum + scarray[i]; 8719 if (checksum == 0 8720 || (checksum & 0xFFFF) != sc->checksum) { 8721 return (0); 8722 } else { 8723 return (1); 8724 } 8725 } 8726 8727 int 8728 ahd_acquire_seeprom(struct ahd_softc *ahd) 8729 { 8730 /* 8731 * We should be able to determine the SEEPROM type 8732 * from the flexport logic, but unfortunately not 8733 * all implementations have this logic and there is 8734 * no programatic method for determining if the logic 8735 * is present. 8736 */ 8737 8738 return (1); 8739 #if 0 8740 uint8_t seetype; 8741 int error; 8742 8743 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8744 if (error != 0 8745 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8746 return (0); 8747 return (1); 8748 #endif 8749 } 8750 8751 void 8752 ahd_release_seeprom(struct ahd_softc *ahd) 8753 { 8754 /* Currently a no-op */ 8755 } 8756 8757 int 8758 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8759 { 8760 int error; 8761 8762 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8763 if (addr > 7) 8764 panic("ahd_write_flexport: address out of range"); 8765 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8766 error = ahd_wait_flexport(ahd); 8767 if (error != 0) 8768 return (error); 8769 ahd_outb(ahd, BRDDAT, value); 8770 ahd_flush_device_writes(ahd); 8771 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8772 ahd_flush_device_writes(ahd); 8773 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8774 ahd_flush_device_writes(ahd); 8775 ahd_outb(ahd, BRDCTL, 0); 8776 ahd_flush_device_writes(ahd); 8777 return (0); 8778 } 8779 8780 int 8781 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8782 { 8783 int error; 8784 8785 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8786 if (addr > 7) 8787 panic("ahd_read_flexport: address out of range"); 8788 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8789 error = ahd_wait_flexport(ahd); 8790 if (error != 0) 8791 return (error); 8792 *value = ahd_inb(ahd, BRDDAT); 8793 ahd_outb(ahd, BRDCTL, 0); 8794 ahd_flush_device_writes(ahd); 8795 return (0); 8796 } 8797 8798 /* 8799 * Wait at most 2 seconds for flexport arbitration to succeed. 8800 */ 8801 int 8802 ahd_wait_flexport(struct ahd_softc *ahd) 8803 { 8804 int cnt; 8805 8806 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8807 cnt = 1000000 * 2 / 5; 8808 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8809 ahd_delay(5); 8810 8811 if (cnt == 0) 8812 return (ETIMEDOUT); 8813 return (0); 8814 } 8815 8816 /************************* Target Mode ****************************************/ 8817 #ifdef AHD_TARGET_MODE 8818 cam_status 8819 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8820 struct ahd_tmode_tstate **tstate, 8821 struct ahd_tmode_lstate **lstate, 8822 int notfound_failure) 8823 { 8824 8825 if ((ahd->features & AHD_TARGETMODE) == 0) 8826 return (CAM_REQ_INVALID); 8827 8828 /* 8829 * Handle the 'black hole' device that sucks up 8830 * requests to unattached luns on enabled targets. 8831 */ 8832 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8833 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8834 *tstate = NULL; 8835 *lstate = ahd->black_hole; 8836 } else { 8837 u_int max_id; 8838 8839 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8840 if (ccb->ccb_h.target_id > max_id) 8841 return (CAM_TID_INVALID); 8842 8843 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 8844 return (CAM_LUN_INVALID); 8845 8846 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 8847 *lstate = NULL; 8848 if (*tstate != NULL) 8849 *lstate = 8850 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 8851 } 8852 8853 if (notfound_failure != 0 && *lstate == NULL) 8854 return (CAM_PATH_INVALID); 8855 8856 return (CAM_REQ_CMP); 8857 } 8858 8859 void 8860 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 8861 { 8862 #if NOT_YET 8863 struct ahd_tmode_tstate *tstate; 8864 struct ahd_tmode_lstate *lstate; 8865 struct ccb_en_lun *cel; 8866 cam_status status; 8867 u_int target; 8868 u_int lun; 8869 u_int target_mask; 8870 u_long s; 8871 char channel; 8872 8873 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 8874 /*notfound_failure*/FALSE); 8875 8876 if (status != CAM_REQ_CMP) { 8877 ccb->ccb_h.status = status; 8878 return; 8879 } 8880 8881 if ((ahd->features & AHD_MULTIROLE) != 0) { 8882 u_int our_id; 8883 8884 our_id = ahd->our_id; 8885 if (ccb->ccb_h.target_id != our_id) { 8886 if ((ahd->features & AHD_MULTI_TID) != 0 8887 && (ahd->flags & AHD_INITIATORROLE) != 0) { 8888 /* 8889 * Only allow additional targets if 8890 * the initiator role is disabled. 8891 * The hardware cannot handle a re-select-in 8892 * on the initiator id during a re-select-out 8893 * on a different target id. 8894 */ 8895 status = CAM_TID_INVALID; 8896 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 8897 || ahd->enabled_luns > 0) { 8898 /* 8899 * Only allow our target id to change 8900 * if the initiator role is not configured 8901 * and there are no enabled luns which 8902 * are attached to the currently registered 8903 * scsi id. 8904 */ 8905 status = CAM_TID_INVALID; 8906 } 8907 } 8908 } 8909 8910 if (status != CAM_REQ_CMP) { 8911 ccb->ccb_h.status = status; 8912 return; 8913 } 8914 8915 /* 8916 * We now have an id that is valid. 8917 * If we aren't in target mode, switch modes. 8918 */ 8919 if ((ahd->flags & AHD_TARGETROLE) == 0 8920 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 8921 u_long s; 8922 8923 printf("Configuring Target Mode\n"); 8924 ahd_lock(ahd, &s); 8925 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 8926 ccb->ccb_h.status = CAM_BUSY; 8927 ahd_unlock(ahd, &s); 8928 return; 8929 } 8930 ahd->flags |= AHD_TARGETROLE; 8931 if ((ahd->features & AHD_MULTIROLE) == 0) 8932 ahd->flags &= ~AHD_INITIATORROLE; 8933 ahd_pause(ahd); 8934 ahd_loadseq(ahd); 8935 ahd_restart(ahd); 8936 ahd_unlock(ahd, &s); 8937 } 8938 cel = &ccb->cel; 8939 target = ccb->ccb_h.target_id; 8940 lun = ccb->ccb_h.target_lun; 8941 channel = SIM_CHANNEL(ahd, sim); 8942 target_mask = 0x01 << target; 8943 if (channel == 'B') 8944 target_mask <<= 8; 8945 8946 if (cel->enable != 0) { 8947 u_int scsiseq1; 8948 8949 /* Are we already enabled?? */ 8950 if (lstate != NULL) { 8951 xpt_print_path(ccb->ccb_h.path); 8952 printf("Lun already enabled\n"); 8953 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 8954 return; 8955 } 8956 8957 if (cel->grp6_len != 0 8958 || cel->grp7_len != 0) { 8959 /* 8960 * Don't (yet?) support vendor 8961 * specific commands. 8962 */ 8963 ccb->ccb_h.status = CAM_REQ_INVALID; 8964 printf("Non-zero Group Codes\n"); 8965 return; 8966 } 8967 8968 /* 8969 * Seems to be okay. 8970 * Setup our data structures. 8971 */ 8972 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 8973 tstate = ahd_alloc_tstate(ahd, target, channel); 8974 if (tstate == NULL) { 8975 xpt_print_path(ccb->ccb_h.path); 8976 printf("Couldn't allocate tstate\n"); 8977 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8978 return; 8979 } 8980 } 8981 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 8982 if (lstate == NULL) { 8983 xpt_print_path(ccb->ccb_h.path); 8984 printf("Couldn't allocate lstate\n"); 8985 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8986 return; 8987 } 8988 memset(lstate, 0, sizeof(*lstate)); 8989 status = xpt_create_path(&lstate->path, /*periph*/NULL, 8990 xpt_path_path_id(ccb->ccb_h.path), 8991 xpt_path_target_id(ccb->ccb_h.path), 8992 xpt_path_lun_id(ccb->ccb_h.path)); 8993 if (status != CAM_REQ_CMP) { 8994 free(lstate, M_DEVBUF); 8995 xpt_print_path(ccb->ccb_h.path); 8996 printf("Couldn't allocate path\n"); 8997 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8998 return; 8999 } 9000 SLIST_INIT(&lstate->accept_tios); 9001 SLIST_INIT(&lstate->immed_notifies); 9002 ahd_lock(ahd, &s); 9003 ahd_pause(ahd); 9004 if (target != CAM_TARGET_WILDCARD) { 9005 tstate->enabled_luns[lun] = lstate; 9006 ahd->enabled_luns++; 9007 9008 if ((ahd->features & AHD_MULTI_TID) != 0) { 9009 u_int targid_mask; 9010 9011 targid_mask = ahd_inb(ahd, TARGID) 9012 | (ahd_inb(ahd, TARGID + 1) << 8); 9013 9014 targid_mask |= target_mask; 9015 ahd_outb(ahd, TARGID, targid_mask); 9016 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9017 9018 ahd_update_scsiid(ahd, targid_mask); 9019 } else { 9020 u_int our_id; 9021 char channel; 9022 9023 channel = SIM_CHANNEL(ahd, sim); 9024 our_id = SIM_SCSI_ID(ahd, sim); 9025 9026 /* 9027 * This can only happen if selections 9028 * are not enabled 9029 */ 9030 if (target != our_id) { 9031 u_int sblkctl; 9032 char cur_channel; 9033 int swap; 9034 9035 sblkctl = ahd_inb(ahd, SBLKCTL); 9036 cur_channel = (sblkctl & SELBUSB) 9037 ? 'B' : 'A'; 9038 if ((ahd->features & AHD_TWIN) == 0) 9039 cur_channel = 'A'; 9040 swap = cur_channel != channel; 9041 ahd->our_id = target; 9042 9043 if (swap) 9044 ahd_outb(ahd, SBLKCTL, 9045 sblkctl ^ SELBUSB); 9046 9047 ahd_outb(ahd, SCSIID, target); 9048 9049 if (swap) 9050 ahd_outb(ahd, SBLKCTL, sblkctl); 9051 } 9052 } 9053 } else 9054 ahd->black_hole = lstate; 9055 /* Allow select-in operations */ 9056 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9057 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9058 scsiseq1 |= ENSELI; 9059 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9060 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9061 scsiseq1 |= ENSELI; 9062 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9063 } 9064 ahd_unpause(ahd); 9065 ahd_unlock(ahd, &s); 9066 ccb->ccb_h.status = CAM_REQ_CMP; 9067 xpt_print_path(ccb->ccb_h.path); 9068 printf("Lun now enabled for target mode\n"); 9069 } else { 9070 struct scb *scb; 9071 int i, empty; 9072 9073 if (lstate == NULL) { 9074 ccb->ccb_h.status = CAM_LUN_INVALID; 9075 return; 9076 } 9077 9078 ahd_lock(ahd, &s); 9079 9080 ccb->ccb_h.status = CAM_REQ_CMP; 9081 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9082 struct ccb_hdr *ccbh; 9083 9084 ccbh = &scb->io_ctx->ccb_h; 9085 if (ccbh->func_code == XPT_CONT_TARGET_IO 9086 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9087 printf("CTIO pending\n"); 9088 ccb->ccb_h.status = CAM_REQ_INVALID; 9089 ahd_unlock(ahd, &s); 9090 return; 9091 } 9092 } 9093 9094 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9095 printf("ATIOs pending\n"); 9096 ccb->ccb_h.status = CAM_REQ_INVALID; 9097 } 9098 9099 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9100 printf("INOTs pending\n"); 9101 ccb->ccb_h.status = CAM_REQ_INVALID; 9102 } 9103 9104 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9105 ahd_unlock(ahd, &s); 9106 return; 9107 } 9108 9109 xpt_print_path(ccb->ccb_h.path); 9110 printf("Target mode disabled\n"); 9111 xpt_free_path(lstate->path); 9112 free(lstate, M_DEVBUF); 9113 9114 ahd_pause(ahd); 9115 /* Can we clean up the target too? */ 9116 if (target != CAM_TARGET_WILDCARD) { 9117 tstate->enabled_luns[lun] = NULL; 9118 ahd->enabled_luns--; 9119 for (empty = 1, i = 0; i < 8; i++) 9120 if (tstate->enabled_luns[i] != NULL) { 9121 empty = 0; 9122 break; 9123 } 9124 9125 if (empty) { 9126 ahd_free_tstate(ahd, target, channel, 9127 /*force*/FALSE); 9128 if (ahd->features & AHD_MULTI_TID) { 9129 u_int targid_mask; 9130 9131 targid_mask = ahd_inb(ahd, TARGID) 9132 | (ahd_inb(ahd, TARGID + 1) 9133 << 8); 9134 9135 targid_mask &= ~target_mask; 9136 ahd_outb(ahd, TARGID, targid_mask); 9137 ahd_outb(ahd, TARGID+1, 9138 (targid_mask >> 8)); 9139 ahd_update_scsiid(ahd, targid_mask); 9140 } 9141 } 9142 } else { 9143 9144 ahd->black_hole = NULL; 9145 9146 /* 9147 * We can't allow selections without 9148 * our black hole device. 9149 */ 9150 empty = TRUE; 9151 } 9152 if (ahd->enabled_luns == 0) { 9153 /* Disallow select-in */ 9154 u_int scsiseq1; 9155 9156 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9157 scsiseq1 &= ~ENSELI; 9158 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9159 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9160 scsiseq1 &= ~ENSELI; 9161 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9162 9163 if ((ahd->features & AHD_MULTIROLE) == 0) { 9164 printf("Configuring Initiator Mode\n"); 9165 ahd->flags &= ~AHD_TARGETROLE; 9166 ahd->flags |= AHD_INITIATORROLE; 9167 ahd_pause(ahd); 9168 ahd_loadseq(ahd); 9169 ahd_restart(ahd); 9170 /* 9171 * Unpaused. The extra unpause 9172 * that follows is harmless. 9173 */ 9174 } 9175 } 9176 ahd_unpause(ahd); 9177 ahd_unlock(ahd, &s); 9178 } 9179 #endif 9180 } 9181 9182 static void 9183 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9184 { 9185 #if NOT_YET 9186 u_int scsiid_mask; 9187 u_int scsiid; 9188 9189 if ((ahd->features & AHD_MULTI_TID) == 0) 9190 panic("ahd_update_scsiid called on non-multitid unit\n"); 9191 9192 /* 9193 * Since we will rely on the TARGID mask 9194 * for selection enables, ensure that OID 9195 * in SCSIID is not set to some other ID 9196 * that we don't want to allow selections on. 9197 */ 9198 if ((ahd->features & AHD_ULTRA2) != 0) 9199 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9200 else 9201 scsiid = ahd_inb(ahd, SCSIID); 9202 scsiid_mask = 0x1 << (scsiid & OID); 9203 if ((targid_mask & scsiid_mask) == 0) { 9204 u_int our_id; 9205 9206 /* ffs counts from 1 */ 9207 our_id = ffs(targid_mask); 9208 if (our_id == 0) 9209 our_id = ahd->our_id; 9210 else 9211 our_id--; 9212 scsiid &= TID; 9213 scsiid |= our_id; 9214 } 9215 if ((ahd->features & AHD_ULTRA2) != 0) 9216 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9217 else 9218 ahd_outb(ahd, SCSIID, scsiid); 9219 #endif 9220 } 9221 9222 #ifdef AHD_TARGET_MODE 9223 void 9224 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9225 { 9226 struct target_cmd *cmd; 9227 9228 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9229 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9230 9231 /* 9232 * Only advance through the queue if we 9233 * have the resources to process the command. 9234 */ 9235 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9236 break; 9237 9238 cmd->cmd_valid = 0; 9239 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9240 ahd->shared_data_map.dmamap, 9241 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9242 sizeof(struct target_cmd), 9243 BUS_DMASYNC_PREREAD); 9244 ahd->tqinfifonext++; 9245 9246 /* 9247 * Lazily update our position in the target mode incoming 9248 * command queue as seen by the sequencer. 9249 */ 9250 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9251 u_int hs_mailbox; 9252 9253 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9254 hs_mailbox &= ~HOST_TQINPOS; 9255 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9256 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9257 } 9258 } 9259 } 9260 #endif 9261 9262 static int 9263 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9264 { 9265 struct ahd_tmode_tstate *tstate; 9266 struct ahd_tmode_lstate *lstate; 9267 struct ccb_accept_tio *atio; 9268 uint8_t *byte; 9269 int initiator; 9270 int target; 9271 int lun; 9272 9273 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9274 target = SCSIID_OUR_ID(cmd->scsiid); 9275 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9276 9277 byte = cmd->bytes; 9278 tstate = ahd->enabled_targets[target]; 9279 lstate = NULL; 9280 if (tstate != NULL) 9281 lstate = tstate->enabled_luns[lun]; 9282 9283 /* 9284 * Commands for disabled luns go to the black hole driver. 9285 */ 9286 if (lstate == NULL) 9287 lstate = ahd->black_hole; 9288 9289 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9290 if (atio == NULL) { 9291 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9292 /* 9293 * Wait for more ATIOs from the peripheral driver for this lun. 9294 */ 9295 return (1); 9296 } else 9297 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9298 #ifdef AHD_DEBUG 9299 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9300 printf("%s: incoming command from %d for %d:%d%s\n", 9301 ahd_name(ahd), 9302 initiator, target, lun, 9303 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9304 #endif 9305 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9306 9307 if (lstate == ahd->black_hole) { 9308 /* Fill in the wildcards */ 9309 atio->ccb_h.target_id = target; 9310 atio->ccb_h.target_lun = lun; 9311 } 9312 9313 /* 9314 * Package it up and send it off to 9315 * whomever has this lun enabled. 9316 */ 9317 atio->sense_len = 0; 9318 atio->init_id = initiator; 9319 if (byte[0] != 0xFF) { 9320 /* Tag was included */ 9321 atio->tag_action = *byte++; 9322 atio->tag_id = *byte++; 9323 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9324 } else { 9325 atio->ccb_h.flags = 0; 9326 } 9327 byte++; 9328 9329 /* Okay. Now determine the cdb size based on the command code */ 9330 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9331 case 0: 9332 atio->cdb_len = 6; 9333 break; 9334 case 1: 9335 case 2: 9336 atio->cdb_len = 10; 9337 break; 9338 case 4: 9339 atio->cdb_len = 16; 9340 break; 9341 case 5: 9342 atio->cdb_len = 12; 9343 break; 9344 case 3: 9345 default: 9346 /* Only copy the opcode. */ 9347 atio->cdb_len = 1; 9348 printf("Reserved or VU command code type encountered\n"); 9349 break; 9350 } 9351 9352 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9353 9354 atio->ccb_h.status |= CAM_CDB_RECVD; 9355 9356 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9357 /* 9358 * We weren't allowed to disconnect. 9359 * We're hanging on the bus until a 9360 * continue target I/O comes in response 9361 * to this accept tio. 9362 */ 9363 #ifdef AHD_DEBUG 9364 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9365 printf("Received Immediate Command %d:%d:%d - %p\n", 9366 initiator, target, lun, ahd->pending_device); 9367 #endif 9368 ahd->pending_device = lstate; 9369 ahd_freeze_ccb((union ccb *)atio); 9370 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9371 } 9372 xpt_done((union ccb*)atio); 9373 return (0); 9374 } 9375 9376 #endif 9377 9378 static int 9379 ahd_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 9380 bus_dma_tag_t tag; 9381 int size; 9382 int flags; 9383 bus_dmamap_t *mapp; 9384 caddr_t *vaddr; 9385 bus_addr_t *baddr; 9386 bus_dma_segment_t *seg; 9387 int *nseg; 9388 const char *myname, *what; 9389 { 9390 int error, level = 0; 9391 9392 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9393 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 9394 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9395 myname, what, error); 9396 goto out; 9397 } 9398 level++; 9399 9400 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9401 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 9402 printf("%s: failed to map DMA mem for %s, error = %d\n", 9403 myname, what, error); 9404 goto out; 9405 } 9406 level++; 9407 9408 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9409 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 9410 printf("%s: failed to create DMA map for %s, error = %d\n", 9411 myname, what, error); 9412 goto out; 9413 } 9414 level++; 9415 9416 9417 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9418 BUS_DMA_NOWAIT)) != 0) { 9419 printf("%s: failed to load DMA map for %s, error = %d\n", 9420 myname, what, error); 9421 goto out; 9422 } 9423 9424 *baddr = (*mapp)->dm_segs[0].ds_addr; 9425 9426 return 0; 9427 out: 9428 printf("ahd_createdmamem error (%d)\n", level); 9429 switch (level) { 9430 case 3: 9431 bus_dmamap_destroy(tag, *mapp); 9432 /* FALLTHROUGH */ 9433 case 2: 9434 bus_dmamem_unmap(tag, *vaddr, size); 9435 /* FALLTHROUGH */ 9436 case 1: 9437 bus_dmamem_free(tag, seg, *nseg); 9438 break; 9439 default: 9440 break; 9441 } 9442 9443 return error; 9444 } 9445 9446 static void 9447 ahd_freedmamem(tag, size, map, vaddr, seg, nseg) 9448 bus_dma_tag_t tag; 9449 int size; 9450 bus_dmamap_t map; 9451 caddr_t vaddr; 9452 bus_dma_segment_t *seg; 9453 int nseg; 9454 { 9455 9456 bus_dmamap_unload(tag, map); 9457 bus_dmamap_destroy(tag, map); 9458 bus_dmamem_unmap(tag, vaddr, size); 9459 bus_dmamem_free(tag, seg, nseg); 9460 } 9461 9462 static void 9463 ahd_update_xfer_mode(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 9464 { 9465 struct scsipi_xfer_mode xm; 9466 struct ahd_initiator_tinfo *tinfo; 9467 struct ahd_tmode_tstate *tstate; 9468 9469 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 9470 devinfo->target, &tstate); 9471 9472 xm.xm_target = devinfo->target; 9473 xm.xm_mode = 0; 9474 xm.xm_period = tinfo->curr.period; 9475 xm.xm_offset = tinfo->curr.offset; 9476 if (tinfo->curr.width == 1) 9477 xm.xm_mode |= PERIPH_CAP_WIDE16; 9478 if (tinfo->curr.period) 9479 xm.xm_mode |= PERIPH_CAP_SYNC; 9480 if (tinfo->curr.ppr_options & MSG_EXT_PPR_DT_REQ) 9481 xm.xm_mode |= PERIPH_CAP_DT; 9482 if (tstate->tagenable & devinfo->target_mask) 9483 xm.xm_mode |= PERIPH_CAP_TQING; 9484 9485 tinfo->goal.width = tinfo->curr.width; 9486 tinfo->goal.period = tinfo->curr.period; 9487 tinfo->goal.offset = tinfo->curr.offset; 9488 tinfo->goal.ppr_options = tinfo->curr.ppr_options; 9489 9490 ahd_update_neg_request(ahd, devinfo, tstate, 9491 tinfo, AHD_NEG_TO_GOAL); 9492 9493 scsipi_async_event(&ahd->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 9494 } 9495
Indexes created Mon Sep 29 21:09:56 GMT 2025