aic79xx.c revision 1.19
1 /* $NetBSD: aic79xx.c,v 1.19 2003/08/29 04:38:07 thorpej Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#200 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.22 2003/06/28 04:42:11 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 * - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.19 2003/08/29 04:38:07 thorpej Exp $"); 53 54 #include <dev/ic/aic79xx_osm.h> 55 #include <dev/ic/aic79xx_inline.h> 56 #include <dev/ic/aic7xxx_cam.h> 57 58 #include <dev/microcode/aic7xxx/aicasm.h> 59 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 60 61 62 /******************************** Globals *************************************/ 63 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 64 65 /***************************** Lookup Tables **********************************/ 66 char *ahd_chip_names[] = 67 { 68 "NONE", 69 "aic7901", 70 "aic7902", 71 "aic7901A" 72 }; 73 74 /* 75 * Hardware error codes. 76 */ 77 struct ahd_hard_error_entry { 78 uint8_t errno; 79 char *errmesg; 80 }; 81 82 static struct ahd_hard_error_entry ahd_hard_errors[] = { 83 { DSCTMOUT, "Discard Timer has timed out" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { CIOPARERR, "CIOBUS Parity Error" }, 89 }; 90 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 91 92 static struct ahd_phase_table_entry ahd_phase_table[] = 93 { 94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 96 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 97 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 98 { P_COMMAND, MSG_NOOP, "in Command phase" }, 99 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 100 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 101 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 102 { P_BUSFREE, MSG_NOOP, "while idle" }, 103 { 0, MSG_NOOP, "in unknown phase" } 104 }; 105 106 /* 107 * In most cases we only wish to itterate over real phases, so 108 * exclude the last element from the count. 109 */ 110 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 111 112 /* Our Sequencer Program */ 113 #include <dev/microcode/aic7xxx/aic79xx_seq.h> 114 115 /**************************** Function Declarations ***************************/ 116 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 117 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 118 u_int lqistat1); 119 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 120 u_int busfreetime); 121 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 122 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 123 static void ahd_force_renegotiation(struct ahd_softc *ahd, 124 struct ahd_devinfo *devinfo); 125 126 static struct ahd_tmode_tstate* 127 ahd_alloc_tstate(struct ahd_softc *ahd, 128 u_int scsi_id, char channel); 129 #ifdef AHD_TARGET_MODE 130 static void ahd_free_tstate(struct ahd_softc *ahd, 131 u_int scsi_id, char channel, int force); 132 #endif 133 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 134 struct ahd_initiator_tinfo *, 135 u_int *period, 136 u_int *ppr_options, 137 role_t role); 138 static void ahd_update_neg_table(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct ahd_transinfo *tinfo); 141 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 142 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo); 144 static void ahd_scb_devinfo(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo, 146 struct scb *scb); 147 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 struct scb *scb); 150 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo); 152 static void ahd_construct_sdtr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset); 155 static void ahd_construct_wdtr(struct ahd_softc *ahd, 156 struct ahd_devinfo *devinfo, 157 u_int bus_width); 158 static void ahd_construct_ppr(struct ahd_softc *ahd, 159 struct ahd_devinfo *devinfo, 160 u_int period, u_int offset, 161 u_int bus_width, u_int ppr_options); 162 static void ahd_clear_msg_state(struct ahd_softc *ahd); 163 static void ahd_handle_message_phase(struct ahd_softc *ahd); 164 typedef enum { 165 AHDMSG_1B, 166 AHDMSG_2B, 167 AHDMSG_EXT 168 } ahd_msgtype; 169 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 170 u_int msgval, int full); 171 static int ahd_parse_msg(struct ahd_softc *ahd, 172 struct ahd_devinfo *devinfo); 173 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo); 175 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 176 struct ahd_devinfo *devinfo); 177 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 178 static void ahd_handle_devreset(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 u_int lun, cam_status status, 181 char *message, int verbose_level); 182 #if AHD_TARGET_MODE 183 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 184 struct ahd_devinfo *devinfo, 185 struct scb *scb); 186 #endif 187 188 static u_int ahd_sglist_size(struct ahd_softc *ahd); 189 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 190 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 191 static int ahd_init_scbdata(struct ahd_softc *ahd); 192 static void ahd_fini_scbdata(struct ahd_softc *ahd); 193 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 194 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 195 static void ahd_add_col_list(struct ahd_softc *ahd, 196 struct scb *scb, u_int col_idx); 197 static void ahd_rem_col_list(struct ahd_softc *ahd, 198 struct scb *scb); 199 static void ahd_chip_init(struct ahd_softc *ahd); 200 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 201 struct scb *prev_scb, 202 struct scb *scb); 203 static int ahd_qinfifo_count(struct ahd_softc *ahd); 204 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 205 char channel, int lun, u_int tag, 206 role_t role, uint32_t status, 207 ahd_search_action action, 208 u_int *list_head, u_int tid); 209 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 210 u_int tid_prev, u_int tid_cur, 211 u_int tid_next); 212 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 213 u_int scbid); 214 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 215 u_int prev, u_int next, u_int tid); 216 static void ahd_reset_current_bus(struct ahd_softc *ahd); 217 static ahd_callback_t ahd_reset_poll; 218 static ahd_callback_t ahd_stat_timer; 219 #ifdef AHD_DUMP_SEQ 220 static void ahd_dumpseq(struct ahd_softc *ahd); 221 #endif 222 static void ahd_loadseq(struct ahd_softc *ahd); 223 static int ahd_check_patch(struct ahd_softc *ahd, 224 struct patch **start_patch, 225 u_int start_instr, u_int *skip_addr); 226 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 227 u_int address); 228 static void ahd_download_instr(struct ahd_softc *ahd, 229 u_int instrptr, uint8_t *dconsts); 230 static int ahd_probe_stack_size(struct ahd_softc *ahd); 231 #ifdef AHD_TARGET_MODE 232 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 233 struct ahd_tmode_lstate *lstate, 234 u_int initiator_id, 235 u_int event_type, 236 u_int event_arg); 237 static void ahd_update_scsiid(struct ahd_softc *ahd, 238 u_int targid_mask); 239 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 240 struct target_cmd *cmd); 241 #endif 242 243 /************************** Added for porting to NetBSD ***********************/ 244 static int ahd_createdmamem(bus_dma_tag_t tag, 245 int size, 246 int flags, 247 bus_dmamap_t *mapp, 248 caddr_t *vaddr, 249 bus_addr_t *baddr, 250 bus_dma_segment_t *seg, 251 int *nseg, 252 const char *myname, const char *what); 253 254 static void ahd_freedmamem(bus_dma_tag_t tag, 255 int size, 256 bus_dmamap_t map, 257 caddr_t vaddr, 258 bus_dma_segment_t *seg, 259 int nseg); 260 static void ahd_update_xfer_mode(struct ahd_softc *ahc, 261 struct ahd_devinfo *devinfo); 262 263 /******************************** Private Inlines *****************************/ 264 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 265 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 266 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 267 268 static __inline void 269 ahd_assert_atn(struct ahd_softc *ahd) 270 { 271 ahd_outb(ahd, SCSISIGO, ATNO); 272 } 273 274 /* 275 * Determine if the current connection has a packetized 276 * agreement. This does not necessarily mean that we 277 * are currently in a packetized transfer. We could 278 * just as easily be sending or receiving a message. 279 */ 280 static __inline int 281 ahd_currently_packetized(struct ahd_softc *ahd) 282 { 283 ahd_mode_state saved_modes; 284 int packetized; 285 286 saved_modes = ahd_save_modes(ahd); 287 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 288 /* 289 * The packetized bit refers to the last 290 * connection, not the current one. Check 291 * for non-zero LQISTATE instead. 292 */ 293 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 294 packetized = ahd_inb(ahd, LQISTATE) != 0; 295 } else { 296 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 297 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 298 } 299 ahd_restore_modes(ahd, saved_modes); 300 return (packetized); 301 } 302 303 static __inline int 304 ahd_set_active_fifo(struct ahd_softc *ahd) 305 { 306 u_int active_fifo; 307 308 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 309 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 310 switch (active_fifo) { 311 case 0: 312 case 1: 313 ahd_set_modes(ahd, active_fifo, active_fifo); 314 return (1); 315 default: 316 return (0); 317 } 318 } 319 320 /************************* Sequencer Execution Control ************************/ 321 /* 322 * Restart the sequencer program from address zero 323 */ 324 void 325 ahd_restart(struct ahd_softc *ahd) 326 { 327 328 ahd_pause(ahd); 329 330 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 331 332 /* No more pending messages */ 333 ahd_clear_msg_state(ahd); 334 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 335 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 336 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 337 ahd_outb(ahd, SEQINTCTL, 0); 338 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 339 ahd_outb(ahd, SEQ_FLAGS, 0); 340 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 341 ahd_outb(ahd, SAVED_LUN, 0xFF); 342 343 /* 344 * Ensure that the sequencer's idea of TQINPOS 345 * matches our own. The sequencer increments TQINPOS 346 * only after it sees a DMA complete and a reset could 347 * occur before the increment leaving the kernel to believe 348 * the command arrived but the sequencer to not. 349 */ 350 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 351 352 /* Always allow reselection */ 353 ahd_outb(ahd, SCSISEQ1, 354 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 355 /* Ensure that no DMA operations are in progress */ 356 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 357 ahd_outb(ahd, SCBHCNT, 0); 358 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 359 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 360 ahd_unpause(ahd); 361 } 362 363 void 364 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 365 { 366 ahd_mode_state saved_modes; 367 368 #ifdef AHD_DEBUG 369 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 370 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 371 #endif 372 saved_modes = ahd_save_modes(ahd); 373 ahd_set_modes(ahd, fifo, fifo); 374 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 375 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 376 ahd_outb(ahd, CCSGCTL, CCSGRESET); 377 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 378 ahd_outb(ahd, SG_STATE, 0); 379 ahd_restore_modes(ahd, saved_modes); 380 } 381 382 /************************* Input/Output Queues ********************************/ 383 /* 384 * Flush and completed commands that are sitting in the command 385 * complete queues down on the chip but have yet to be DMA'ed back up. 386 */ 387 void 388 ahd_flush_qoutfifo(struct ahd_softc *ahd) 389 { 390 struct scb *scb; 391 ahd_mode_state saved_modes; 392 u_int saved_scbptr; 393 u_int ccscbctl; 394 u_int scbid; 395 u_int next_scbid; 396 397 saved_modes = ahd_save_modes(ahd); 398 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 399 saved_scbptr = ahd_get_scbptr(ahd); 400 401 /* 402 * Wait for any inprogress DMA to complete and clear DMA state 403 * if this if for an SCB in the qinfifo. 404 */ 405 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 406 407 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 408 if ((ccscbctl & ARRDONE) != 0) 409 break; 410 } else if ((ccscbctl & CCSCBDONE) != 0) 411 break; 412 ahd_delay(200); 413 } 414 if ((ccscbctl & CCSCBDIR) != 0) 415 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 416 417 /* 418 * Complete any SCBs that just finished being 419 * DMA'ed into the qoutfifo. 420 */ 421 ahd_run_qoutfifo(ahd); 422 423 /* 424 * Manually update/complete any completed SCBs that are waiting to be 425 * DMA'ed back up to the host. 426 */ 427 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 428 while (!SCBID_IS_NULL(scbid)) { 429 uint8_t *hscb_ptr; 430 u_int i; 431 432 ahd_set_scbptr(ahd, scbid); 433 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 434 scb = ahd_lookup_scb(ahd, scbid); 435 if (scb == NULL) { 436 printf("%s: Warning - DMA-up and complete " 437 "SCB %d invalid\n", ahd_name(ahd), scbid); 438 continue; 439 } 440 hscb_ptr = (uint8_t *)scb->hscb; 441 for (i = 0; i < sizeof(struct hardware_scb); i++) 442 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 443 444 ahd_complete_scb(ahd, scb); 445 scbid = next_scbid; 446 } 447 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 448 449 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 450 while (!SCBID_IS_NULL(scbid)) { 451 452 ahd_set_scbptr(ahd, scbid); 453 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 454 scb = ahd_lookup_scb(ahd, scbid); 455 if (scb == NULL) { 456 printf("%s: Warning - Complete SCB %d invalid\n", 457 ahd_name(ahd), scbid); 458 continue; 459 } 460 461 ahd_complete_scb(ahd, scb); 462 scbid = next_scbid; 463 } 464 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 465 ahd_set_scbptr(ahd, saved_scbptr); 466 467 /* 468 * Flush the good status FIFO for compelted packetized commands. 469 */ 470 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 471 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 472 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 473 | ahd_inb(ahd, GSFIFO); 474 scb = ahd_lookup_scb(ahd, scbid); 475 if (scb == NULL) { 476 printf("%s: Warning - GSFIFO SCB %d invalid\n", 477 ahd_name(ahd), scbid); 478 continue; 479 } 480 ahd_complete_scb(ahd, scb); 481 } 482 483 /* 484 * Restore state. 485 */ 486 ahd_restore_modes(ahd, saved_modes); 487 ahd->flags |= AHD_UPDATE_PEND_CMDS; 488 } 489 490 void 491 ahd_run_qoutfifo(struct ahd_softc *ahd) 492 { 493 struct scb *scb; 494 u_int scb_index; 495 496 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 497 panic("ahd_run_qoutfifo recursion"); 498 ahd->flags |= AHD_RUNNING_QOUTFIFO; 499 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 500 while ((ahd->qoutfifo[ahd->qoutfifonext] 501 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 502 503 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 504 & ~QOUTFIFO_ENTRY_VALID_LE); 505 scb = ahd_lookup_scb(ahd, scb_index); 506 if (scb == NULL) { 507 printf("%s: WARNING no command for scb %d " 508 "(cmdcmplt)\nQOUTPOS = %d\n", 509 ahd_name(ahd), scb_index, 510 ahd->qoutfifonext); 511 ahd_dump_card_state(ahd); 512 } else 513 ahd_complete_scb(ahd, scb); 514 515 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 516 if (ahd->qoutfifonext == 0) 517 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 518 } 519 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 520 } 521 522 /************************* Interrupt Handling *********************************/ 523 void 524 ahd_handle_hwerrint(struct ahd_softc *ahd) 525 { 526 /* 527 * Some catastrophic hardware error has occurred. 528 * Print it for the user and disable the controller. 529 */ 530 int i; 531 int error; 532 533 error = ahd_inb(ahd, ERROR); 534 for (i = 0; i < num_errors; i++) { 535 if ((error & ahd_hard_errors[i].errno) != 0) 536 printf("%s: hwerrint, %s\n", 537 ahd_name(ahd), ahd_hard_errors[i].errmesg); 538 } 539 540 ahd_dump_card_state(ahd); 541 panic("BRKADRINT"); 542 543 /* Tell everyone that this HBA is no longer available */ 544 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 545 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 546 CAM_NO_HBA); 547 548 /* Tell the system that this controller has gone away. */ 549 ahd_free(ahd); 550 } 551 552 void 553 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 554 { 555 u_int seqintcode; 556 557 /* 558 * Save the sequencer interrupt code and clear the SEQINT 559 * bit. We will unpause the sequencer, if appropriate, 560 * after servicing the request. 561 */ 562 seqintcode = ahd_inb(ahd, SEQINTCODE); 563 ahd_outb(ahd, CLRINT, CLRSEQINT); 564 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 565 /* 566 * Unpause the sequencer and let it clear 567 * SEQINT by writing NO_SEQINT to it. This 568 * will cause the sequencer to be paused again, 569 * which is the expected state of this routine. 570 */ 571 ahd_unpause(ahd); 572 while (!ahd_is_paused(ahd)) 573 ; 574 ahd_outb(ahd, CLRINT, CLRSEQINT); 575 } 576 ahd_update_modes(ahd); 577 #ifdef AHD_DEBUG 578 if ((ahd_debug & AHD_SHOW_MISC) != 0) 579 printf("%s: Handle Seqint Called for code %d\n", 580 ahd_name(ahd), seqintcode); 581 #endif 582 switch (seqintcode) { 583 case BAD_SCB_STATUS: 584 { 585 struct scb *scb; 586 u_int scbid; 587 int cmds_pending; 588 589 scbid = ahd_get_scbptr(ahd); 590 scb = ahd_lookup_scb(ahd, scbid); 591 if (scb != NULL) { 592 ahd_complete_scb(ahd, scb); 593 } else { 594 printf("%s: WARNING no command for scb %d " 595 "(bad status)\n", ahd_name(ahd), scbid); 596 ahd_dump_card_state(ahd); 597 } 598 cmds_pending = ahd_inw(ahd, CMDS_PENDING); 599 if (cmds_pending > 0) 600 ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); 601 break; 602 } 603 case ENTERING_NONPACK: 604 { 605 struct scb *scb; 606 u_int scbid; 607 608 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 609 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 610 scbid = ahd_get_scbptr(ahd); 611 scb = ahd_lookup_scb(ahd, scbid); 612 if (scb == NULL) { 613 /* 614 * Somehow need to know if this 615 * is from a selection or reselection. 616 * From that, we can determine target 617 * ID so we at least have an I_T nexus. 618 */ 619 } else { 620 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 621 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 622 ahd_outb(ahd, SEQ_FLAGS, 0x0); 623 } 624 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 625 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 626 /* 627 * Phase change after read stream with 628 * CRC error with P0 asserted on last 629 * packet. 630 */ 631 #ifdef AHD_DEBUG 632 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 633 printf("%s: Assuming LQIPHASE_NLQ with " 634 "P0 assertion\n", ahd_name(ahd)); 635 #endif 636 } 637 #ifdef AHD_DEBUG 638 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 639 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 640 #endif 641 break; 642 } 643 case INVALID_SEQINT: 644 printf("%s: Invalid Sequencer interrupt occurred.\n", 645 ahd_name(ahd)); 646 ahd_dump_card_state(ahd); 647 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 648 break; 649 case STATUS_OVERRUN: 650 { 651 struct scb *scb; 652 u_int scbid; 653 654 scbid = ahd_get_scbptr(ahd); 655 scb = ahd_lookup_scb(ahd, scbid); 656 if (scb != NULL) 657 ahd_print_path(ahd, scb); 658 else 659 printf("%s: ", ahd_name(ahd)); 660 printf("SCB %d Packetized Status Overrun", scbid); 661 ahd_dump_card_state(ahd); 662 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 663 break; 664 } 665 case CFG4ISTAT_INTR: 666 { 667 struct scb *scb; 668 u_int scbid; 669 670 scbid = ahd_get_scbptr(ahd); 671 scb = ahd_lookup_scb(ahd, scbid); 672 if (scb == NULL) { 673 ahd_dump_card_state(ahd); 674 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 675 panic("For safety"); 676 } 677 ahd_outq(ahd, HADDR, scb->sense_busaddr); 678 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 679 ahd_outb(ahd, HCNT + 2, 0); 680 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 681 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 682 break; 683 } 684 case ILLEGAL_PHASE: 685 { 686 u_int bus_phase; 687 688 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 689 printf("%s: ILLEGAL_PHASE 0x%x\n", 690 ahd_name(ahd), bus_phase); 691 692 switch (bus_phase) { 693 case P_DATAOUT: 694 case P_DATAIN: 695 case P_DATAOUT_DT: 696 case P_DATAIN_DT: 697 case P_MESGOUT: 698 case P_STATUS: 699 case P_MESGIN: 700 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 701 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 702 break; 703 case P_COMMAND: 704 { 705 struct ahd_devinfo devinfo; 706 struct scb *scb; 707 struct ahd_initiator_tinfo *targ_info; 708 struct ahd_tmode_tstate *tstate; 709 struct ahd_transinfo *tinfo; 710 u_int scbid; 711 712 /* 713 * If a target takes us into the command phase 714 * assume that it has been externally reset and 715 * has thus lost our previous packetized negotiation 716 * agreement. Since we have not sent an identify 717 * message and may not have fully qualified the 718 * connection, we change our command to TUR, assert 719 * ATN and ABORT the task when we go to message in 720 * phase. The OSM will see the REQUEUE_REQUEST 721 * status and retry the command. 722 */ 723 scbid = ahd_get_scbptr(ahd); 724 scb = ahd_lookup_scb(ahd, scbid); 725 if (scb == NULL) { 726 printf("Invalid phase with no valid SCB. " 727 "Resetting bus.\n"); 728 ahd_reset_channel(ahd, 'A', 729 /*Initiate Reset*/TRUE); 730 break; 731 } 732 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 733 SCB_GET_TARGET(ahd, scb), 734 SCB_GET_LUN(scb), 735 SCB_GET_CHANNEL(ahd, scb), 736 ROLE_INITIATOR); 737 targ_info = ahd_fetch_transinfo(ahd, 738 devinfo.channel, 739 devinfo.our_scsiid, 740 devinfo.target, 741 &tstate); 742 tinfo = &targ_info->curr; 743 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 744 AHD_TRANS_ACTIVE, /*paused*/TRUE); 745 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 746 /*offset*/0, /*ppr_options*/0, 747 AHD_TRANS_ACTIVE, /*paused*/TRUE); 748 ahd_outb(ahd, SCB_CDB_STORE, 0); 749 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 750 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 751 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 752 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 753 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 754 ahd_outb(ahd, SCB_CDB_LEN, 6); 755 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 756 scb->hscb->control |= MK_MESSAGE; 757 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 758 ahd_outb(ahd, MSG_OUT, HOST_MSG); 759 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 760 /* 761 * The lun is 0, regardless of the SCB's lun 762 * as we have not sent an identify message. 763 */ 764 ahd_outb(ahd, SAVED_LUN, 0); 765 ahd_outb(ahd, SEQ_FLAGS, 0); 766 ahd_assert_atn(ahd); 767 scb->flags &= ~(SCB_PACKETIZED); 768 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 769 ahd_freeze_devq(ahd, scb); 770 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 771 ahd_freeze_scb(scb); 772 773 /* 774 * Allow the sequencer to continue with 775 * non-pack processing. 776 */ 777 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 778 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 779 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 780 ahd_outb(ahd, CLRLQOINT1, 0); 781 } 782 #ifdef AHD_DEBUG 783 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 784 ahd_print_path(ahd, scb); 785 printf("Unexpected command phase from " 786 "packetized target\n"); 787 } 788 #endif 789 break; 790 } 791 } 792 break; 793 } 794 case CFG4OVERRUN: 795 { 796 struct scb *scb; 797 u_int scb_index; 798 799 #ifdef AHD_DEBUG 800 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 801 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 802 ahd_inb(ahd, MODE_PTR)); 803 } 804 #endif 805 scb_index = ahd_get_scbptr(ahd); 806 scb = ahd_lookup_scb(ahd, scb_index); 807 if (scb == NULL) { 808 /* 809 * Attempt to transfer to an SCB that is 810 * not outstanding. 811 */ 812 ahd_assert_atn(ahd); 813 ahd_outb(ahd, MSG_OUT, HOST_MSG); 814 ahd->msgout_buf[0] = MSG_ABORT_TASK; 815 ahd->msgout_len = 1; 816 ahd->msgout_index = 0; 817 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 818 /* 819 * Clear status received flag to prevent any 820 * attempt to complete this bogus SCB. 821 */ 822 ahd_outb(ahd, SCB_CONTROL, 823 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 824 } 825 break; 826 } 827 case DUMP_CARD_STATE: 828 { 829 ahd_dump_card_state(ahd); 830 break; 831 } 832 case PDATA_REINIT: 833 { 834 #ifdef AHD_DEBUG 835 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 836 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 837 "SG_CACHE_SHADOW = 0x%x\n", 838 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 839 ahd_inb(ahd, SG_CACHE_SHADOW)); 840 } 841 #endif 842 ahd_reinitialize_dataptrs(ahd); 843 break; 844 } 845 case HOST_MSG_LOOP: 846 { 847 struct ahd_devinfo devinfo; 848 849 /* 850 * The sequencer has encountered a message phase 851 * that requires host assistance for completion. 852 * While handling the message phase(s), we will be 853 * notified by the sequencer after each byte is 854 * transfered so we can track bus phase changes. 855 * 856 * If this is the first time we've seen a HOST_MSG_LOOP 857 * interrupt, initialize the state of the host message 858 * loop. 859 */ 860 ahd_fetch_devinfo(ahd, &devinfo); 861 if (ahd->msg_type == MSG_TYPE_NONE) { 862 struct scb *scb; 863 u_int scb_index; 864 u_int bus_phase; 865 866 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 867 if (bus_phase != P_MESGIN 868 && bus_phase != P_MESGOUT) { 869 printf("ahd_intr: HOST_MSG_LOOP bad " 870 "phase 0x%x\n", bus_phase); 871 /* 872 * Probably transitioned to bus free before 873 * we got here. Just punt the message. 874 */ 875 ahd_dump_card_state(ahd); 876 ahd_clear_intstat(ahd); 877 ahd_restart(ahd); 878 return; 879 } 880 881 scb_index = ahd_get_scbptr(ahd); 882 scb = ahd_lookup_scb(ahd, scb_index); 883 if (devinfo.role == ROLE_INITIATOR) { 884 if (bus_phase == P_MESGOUT) 885 ahd_setup_initiator_msgout(ahd, 886 &devinfo, 887 scb); 888 else { 889 ahd->msg_type = 890 MSG_TYPE_INITIATOR_MSGIN; 891 ahd->msgin_index = 0; 892 } 893 } 894 #if AHD_TARGET_MODE 895 else { 896 if (bus_phase == P_MESGOUT) { 897 ahd->msg_type = 898 MSG_TYPE_TARGET_MSGOUT; 899 ahd->msgin_index = 0; 900 } 901 else 902 ahd_setup_target_msgin(ahd, 903 &devinfo, 904 scb); 905 } 906 #endif 907 } 908 909 ahd_handle_message_phase(ahd); 910 break; 911 } 912 case NO_MATCH: 913 { 914 /* Ensure we don't leave the selection hardware on */ 915 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 916 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 917 918 printf("%s:%c:%d: no active SCB for reconnecting " 919 "target - issuing BUS DEVICE RESET\n", 920 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 921 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 922 "REG0 == 0x%x ACCUM = 0x%x\n", 923 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 924 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 925 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 926 "SINDEX == 0x%x\n", 927 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 928 ahd_find_busy_tcl(ahd, 929 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 930 ahd_inb(ahd, SAVED_LUN))), 931 ahd_inw(ahd, SINDEX)); 932 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 933 "SCB_CONTROL == 0x%x\n", 934 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 935 ahd_inb_scbram(ahd, SCB_LUN), 936 ahd_inb_scbram(ahd, SCB_CONTROL)); 937 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 938 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 939 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 940 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 941 ahd_dump_card_state(ahd); 942 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 943 ahd->msgout_len = 1; 944 ahd->msgout_index = 0; 945 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 946 ahd_outb(ahd, MSG_OUT, HOST_MSG); 947 ahd_assert_atn(ahd); 948 break; 949 } 950 case PROTO_VIOLATION: 951 { 952 ahd_handle_proto_violation(ahd); 953 break; 954 } 955 case IGN_WIDE_RES: 956 { 957 struct ahd_devinfo devinfo; 958 959 ahd_fetch_devinfo(ahd, &devinfo); 960 ahd_handle_ign_wide_residue(ahd, &devinfo); 961 break; 962 } 963 case BAD_PHASE: 964 { 965 u_int lastphase; 966 967 lastphase = ahd_inb(ahd, LASTPHASE); 968 printf("%s:%c:%d: unknown scsi bus phase %x, " 969 "lastphase = 0x%x. Attempting to continue\n", 970 ahd_name(ahd), 'A', 971 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 972 lastphase, ahd_inb(ahd, SCSISIGI)); 973 break; 974 } 975 case MISSED_BUSFREE: 976 { 977 u_int lastphase; 978 979 lastphase = ahd_inb(ahd, LASTPHASE); 980 printf("%s:%c:%d: Missed busfree. " 981 "Lastphase = 0x%x, Curphase = 0x%x\n", 982 ahd_name(ahd), 'A', 983 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 984 lastphase, ahd_inb(ahd, SCSISIGI)); 985 ahd_restart(ahd); 986 return; 987 } 988 case DATA_OVERRUN: 989 { 990 /* 991 * When the sequencer detects an overrun, it 992 * places the controller in "BITBUCKET" mode 993 * and allows the target to complete its transfer. 994 * Unfortunately, none of the counters get updated 995 * when the controller is in this mode, so we have 996 * no way of knowing how large the overrun was. 997 */ 998 struct scb *scb; 999 u_int scbindex; 1000 #ifdef AHD_DEBUG 1001 u_int lastphase; 1002 #endif 1003 1004 scbindex = ahd_get_scbptr(ahd); 1005 scb = ahd_lookup_scb(ahd, scbindex); 1006 #ifdef AHD_DEBUG 1007 lastphase = ahd_inb(ahd, LASTPHASE); 1008 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1009 ahd_print_path(ahd, scb); 1010 printf("data overrun detected %s. Tag == 0x%x.\n", 1011 ahd_lookup_phase_entry(lastphase)->phasemsg, 1012 SCB_GET_TAG(scb)); 1013 ahd_print_path(ahd, scb); 1014 printf("%s seen Data Phase. Length = %ld. " 1015 "NumSGs = %d.\n", 1016 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1017 ? "Have" : "Haven't", 1018 ahd_get_transfer_length(scb), scb->sg_count); 1019 ahd_dump_sglist(scb); 1020 } 1021 #endif 1022 1023 /* 1024 * Set this and it will take effect when the 1025 * target does a command complete. 1026 */ 1027 ahd_freeze_devq(ahd, scb); 1028 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1029 ahd_freeze_scb(scb); 1030 break; 1031 } 1032 case MKMSG_FAILED: 1033 { 1034 struct ahd_devinfo devinfo; 1035 struct scb *scb; 1036 u_int scbid; 1037 1038 ahd_fetch_devinfo(ahd, &devinfo); 1039 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1040 ahd_name(ahd), devinfo.channel, devinfo.target, 1041 devinfo.lun); 1042 scbid = ahd_get_scbptr(ahd); 1043 scb = ahd_lookup_scb(ahd, scbid); 1044 if (scb != NULL 1045 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1046 /* 1047 * Ensure that we didn't put a second instance of this 1048 * SCB into the QINFIFO. 1049 */ 1050 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1051 SCB_GET_CHANNEL(ahd, scb), 1052 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1053 ROLE_INITIATOR, /*status*/0, 1054 SEARCH_REMOVE); 1055 ahd_outb(ahd, SCB_CONTROL, 1056 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1057 break; 1058 } 1059 case TASKMGMT_FUNC_COMPLETE: 1060 { 1061 u_int scbid; 1062 struct scb *scb; 1063 1064 scbid = ahd_get_scbptr(ahd); 1065 scb = ahd_lookup_scb(ahd, scbid); 1066 if (scb != NULL) { 1067 u_int lun; 1068 u_int tag; 1069 cam_status error; 1070 1071 ahd_print_path(ahd, scb); 1072 printf("Task Management Func 0x%x Complete\n", 1073 scb->hscb->task_management); 1074 lun = CAM_LUN_WILDCARD; 1075 tag = SCB_LIST_NULL; 1076 1077 switch (scb->hscb->task_management) { 1078 case SIU_TASKMGMT_ABORT_TASK: 1079 tag = SCB_GET_TAG(scb); 1080 case SIU_TASKMGMT_ABORT_TASK_SET: 1081 case SIU_TASKMGMT_CLEAR_TASK_SET: 1082 lun = scb->hscb->lun; 1083 error = CAM_REQ_ABORTED; 1084 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1085 'A', lun, tag, ROLE_INITIATOR, 1086 error); 1087 break; 1088 case SIU_TASKMGMT_LUN_RESET: 1089 lun = scb->hscb->lun; 1090 case SIU_TASKMGMT_TARGET_RESET: 1091 { 1092 struct ahd_devinfo devinfo; 1093 1094 ahd_scb_devinfo(ahd, &devinfo, scb); 1095 error = CAM_BDR_SENT; 1096 ahd_handle_devreset(ahd, &devinfo, lun, 1097 CAM_BDR_SENT, 1098 lun != CAM_LUN_WILDCARD 1099 ? "Lun Reset" 1100 : "Target Reset", 1101 /*verbose_level*/0); 1102 break; 1103 } 1104 default: 1105 panic("Unexpected TaskMgmt Func\n"); 1106 break; 1107 } 1108 } 1109 break; 1110 } 1111 case TASKMGMT_CMD_CMPLT_OKAY: 1112 { 1113 u_int scbid; 1114 struct scb *scb; 1115 1116 /* 1117 * An ABORT TASK TMF failed to be delivered before 1118 * the targeted command completed normally. 1119 */ 1120 scbid = ahd_get_scbptr(ahd); 1121 scb = ahd_lookup_scb(ahd, scbid); 1122 if (scb != NULL) { 1123 /* 1124 * Remove the second instance of this SCB from 1125 * the QINFIFO if it is still there. 1126 */ 1127 ahd_print_path(ahd, scb); 1128 printf("SCB completes before TMF\n"); 1129 /* 1130 * Handle losing the race. Wait until any 1131 * current selection completes. We will then 1132 * set the TMF back to zero in this SCB so that 1133 * the sequencer doesn't bother to issue another 1134 * sequencer interrupt for its completion. 1135 */ 1136 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1137 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1138 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1139 ; 1140 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1141 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1142 SCB_GET_CHANNEL(ahd, scb), 1143 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1144 ROLE_INITIATOR, /*status*/0, 1145 SEARCH_REMOVE); 1146 } 1147 break; 1148 } 1149 case TRACEPOINT0: 1150 case TRACEPOINT1: 1151 case TRACEPOINT2: 1152 case TRACEPOINT3: 1153 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1154 seqintcode - TRACEPOINT0); 1155 break; 1156 case NO_SEQINT: 1157 break; 1158 case SAW_HWERR: 1159 ahd_handle_hwerrint(ahd); 1160 break; 1161 default: 1162 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1163 seqintcode); 1164 break; 1165 } 1166 /* 1167 * The sequencer is paused immediately on 1168 * a SEQINT, so we should restart it when 1169 * we're done. 1170 */ 1171 ahd_unpause(ahd); 1172 } 1173 1174 void 1175 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1176 { 1177 struct scb *scb; 1178 u_int status0; 1179 u_int status3; 1180 u_int status; 1181 u_int lqistat1; 1182 u_int lqostat0; 1183 u_int scbid; 1184 u_int busfreetime; 1185 1186 ahd_update_modes(ahd); 1187 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1188 1189 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1190 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1191 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1192 lqistat1 = ahd_inb(ahd, LQISTAT1); 1193 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1194 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1195 if ((status0 & (SELDI|SELDO)) != 0) { 1196 u_int simode0; 1197 1198 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1199 simode0 = ahd_inb(ahd, SIMODE0); 1200 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1201 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1202 } 1203 scbid = ahd_get_scbptr(ahd); 1204 scb = ahd_lookup_scb(ahd, scbid); 1205 if (scb != NULL 1206 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1207 scb = NULL; 1208 1209 /* Make sure the sequencer is in a safe location. */ 1210 ahd_clear_critical_section(ahd); 1211 1212 if ((status0 & IOERR) != 0) { 1213 u_int now_lvd; 1214 1215 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1216 printf("%s: Transceiver State Has Changed to %s mode\n", 1217 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1218 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1219 /* 1220 * A change in I/O mode is equivalent to a bus reset. 1221 */ 1222 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1223 ahd_pause(ahd); 1224 ahd_setup_iocell_workaround(ahd); 1225 ahd_unpause(ahd); 1226 } else if ((status0 & OVERRUN) != 0) { 1227 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1228 ahd_name(ahd)); 1229 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1230 } else if ((status & SCSIRSTI) != 0) { 1231 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1232 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1233 } else if ((status & SCSIPERR) != 0) { 1234 ahd_handle_transmission_error(ahd); 1235 } else if (lqostat0 != 0) { 1236 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1237 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1238 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1239 ahd_outb(ahd, CLRLQOINT1, 0); 1240 } 1241 } else if ((status & SELTO) != 0) { 1242 u_int scbid; 1243 1244 /* Stop the selection */ 1245 ahd_outb(ahd, SCSISEQ0, 0); 1246 1247 /* No more pending messages */ 1248 ahd_clear_msg_state(ahd); 1249 1250 /* Clear interrupt state */ 1251 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1252 1253 /* 1254 * Although the driver does not care about the 1255 * 'Selection in Progress' status bit, the busy 1256 * LED does. SELINGO is only cleared by a sucessfull 1257 * selection, so we must manually clear it to insure 1258 * the LED turns off just incase no future successful 1259 * selections occur (e.g. no devices on the bus). 1260 */ 1261 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1262 1263 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1264 scb = ahd_lookup_scb(ahd, scbid); 1265 if (scb == NULL) { 1266 printf("%s: ahd_intr - referenced scb not " 1267 "valid during SELTO scb(0x%x)\n", 1268 ahd_name(ahd), scbid); 1269 ahd_dump_card_state(ahd); 1270 } else { 1271 struct ahd_devinfo devinfo; 1272 #ifdef AHD_DEBUG 1273 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1274 ahd_print_path(ahd, scb); 1275 printf("Saw Selection Timeout for SCB 0x%x\n", 1276 scbid); 1277 } 1278 #endif 1279 /* 1280 * Force a renegotiation with this target just in 1281 * case the cable was pulled and will later be 1282 * re-attached. The target may forget its negotiation 1283 * settings with us should it attempt to reselect 1284 * during the interruption. The target will not issue 1285 * a unit attention in this case, so we must always 1286 * renegotiate. 1287 */ 1288 ahd_scb_devinfo(ahd, &devinfo, scb); 1289 ahd_force_renegotiation(ahd, &devinfo); 1290 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1291 ahd_freeze_devq(ahd, scb); 1292 } 1293 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1294 ahd_iocell_first_selection(ahd); 1295 ahd_unpause(ahd); 1296 } else if ((status0 & (SELDI|SELDO)) != 0) { 1297 ahd_iocell_first_selection(ahd); 1298 ahd_unpause(ahd); 1299 } else if (status3 != 0) { 1300 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1301 ahd_name(ahd), status3); 1302 ahd_outb(ahd, CLRSINT3, status3); 1303 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1304 ahd_handle_lqiphase_error(ahd, lqistat1); 1305 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1306 /* 1307 * This status can be delayed during some 1308 * streaming operations. The SCSIPHASE 1309 * handler has already dealt with this case 1310 * so just clear the error. 1311 */ 1312 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1313 } else if ((status & BUSFREE) != 0) { 1314 u_int lqostat1; 1315 int restart; 1316 int clear_fifo; 1317 int packetized; 1318 u_int mode; 1319 1320 /* 1321 * Clear our selection hardware as soon as possible. 1322 * We may have an entry in the waiting Q for this target, 1323 * that is affected by this busfree and we don't want to 1324 * go about selecting the target while we handle the event. 1325 */ 1326 ahd_outb(ahd, SCSISEQ0, 0); 1327 1328 /* 1329 * Determine what we were up to at the time of 1330 * the busfree. 1331 */ 1332 mode = AHD_MODE_SCSI; 1333 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1334 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1335 switch (busfreetime) { 1336 case BUSFREE_DFF0: 1337 case BUSFREE_DFF1: 1338 { 1339 u_int scbid; 1340 struct scb *scb; 1341 1342 mode = busfreetime == BUSFREE_DFF0 1343 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1344 ahd_set_modes(ahd, mode, mode); 1345 scbid = ahd_get_scbptr(ahd); 1346 scb = ahd_lookup_scb(ahd, scbid); 1347 if (scb == NULL) { 1348 printf("%s: Invalid SCB %d in DFF%d " 1349 "during unexpected busfree\n", 1350 ahd_name(ahd), scbid, mode); 1351 packetized = 0; 1352 } else 1353 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1354 clear_fifo = 1; 1355 break; 1356 } 1357 case BUSFREE_LQO: 1358 clear_fifo = 0; 1359 packetized = 1; 1360 break; 1361 default: 1362 clear_fifo = 0; 1363 packetized = (lqostat1 & LQOBUSFREE) != 0; 1364 if (!packetized 1365 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1366 packetized = 1; 1367 break; 1368 } 1369 1370 #ifdef AHD_DEBUG 1371 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1372 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1373 busfreetime); 1374 #endif 1375 /* 1376 * Busfrees that occur in non-packetized phases are 1377 * handled by the nonpkt_busfree handler. 1378 */ 1379 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1380 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1381 } else { 1382 packetized = 0; 1383 restart = ahd_handle_nonpkt_busfree(ahd); 1384 } 1385 /* 1386 * Clear the busfree interrupt status. The setting of 1387 * the interrupt is a pulse, so in a perfect world, we 1388 * would not need to muck with the ENBUSFREE logic. This 1389 * would ensure that if the bus moves on to another 1390 * connection, busfree protection is still in force. If 1391 * BUSFREEREV is broken, however, we must manually clear 1392 * the ENBUSFREE if the busfree occurred during a non-pack 1393 * connection so that we don't get false positives during 1394 * future, packetized, connections. 1395 */ 1396 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1397 if (packetized == 0 1398 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1399 ahd_outb(ahd, SIMODE1, 1400 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1401 1402 if (clear_fifo) 1403 ahd_clear_fifo(ahd, mode); 1404 1405 ahd_clear_msg_state(ahd); 1406 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1407 if (restart) { 1408 ahd_restart(ahd); 1409 } else { 1410 ahd_unpause(ahd); 1411 } 1412 } else { 1413 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1414 ahd_name(ahd), status); 1415 ahd_dump_card_state(ahd); 1416 ahd_clear_intstat(ahd); 1417 ahd_unpause(ahd); 1418 } 1419 } 1420 1421 static void 1422 ahd_handle_transmission_error(struct ahd_softc *ahd) 1423 { 1424 struct scb *scb; 1425 u_int scbid; 1426 u_int lqistat1; 1427 u_int lqistat2; 1428 u_int msg_out; 1429 u_int curphase; 1430 u_int lastphase; 1431 u_int perrdiag; 1432 u_int cur_col; 1433 int silent; 1434 1435 scb = NULL; 1436 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1437 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1438 lqistat2 = ahd_inb(ahd, LQISTAT2); 1439 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1440 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1441 u_int lqistate; 1442 1443 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1444 lqistate = ahd_inb(ahd, LQISTATE); 1445 if ((lqistate >= 0x1E && lqistate <= 0x24) 1446 || (lqistate == 0x29)) { 1447 #ifdef AHD_DEBUG 1448 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1449 printf("%s: NLQCRC found via LQISTATE\n", 1450 ahd_name(ahd)); 1451 } 1452 #endif 1453 lqistat1 |= LQICRCI_NLQ; 1454 } 1455 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1456 } 1457 1458 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1459 lastphase = ahd_inb(ahd, LASTPHASE); 1460 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1461 perrdiag = ahd_inb(ahd, PERRDIAG); 1462 msg_out = MSG_INITIATOR_DET_ERR; 1463 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1464 1465 /* 1466 * Try to find the SCB associated with this error. 1467 */ 1468 silent = FALSE; 1469 if (lqistat1 == 0 1470 || (lqistat1 & LQICRCI_NLQ) != 0) { 1471 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1472 ahd_set_active_fifo(ahd); 1473 scbid = ahd_get_scbptr(ahd); 1474 scb = ahd_lookup_scb(ahd, scbid); 1475 if (scb != NULL && SCB_IS_SILENT(scb)) 1476 silent = TRUE; 1477 } 1478 1479 cur_col = 0; 1480 if (silent == FALSE) { 1481 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1482 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1483 ahd_lastphase_print(lastphase, &cur_col, 50); 1484 ahd_scsisigi_print(curphase, &cur_col, 50); 1485 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1486 printf("\n"); 1487 ahd_dump_card_state(ahd); 1488 } 1489 1490 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1491 if (silent == FALSE) { 1492 printf("%s: Gross protocol error during incoming " 1493 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1494 ahd_name(ahd), lqistat1); 1495 } 1496 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1497 return; 1498 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1499 /* 1500 * A CRC error has been detected on an incoming LQ. 1501 * The bus is currently hung on the last ACK. 1502 * Hit LQIRETRY to release the last ack, and 1503 * wait for the sequencer to determine that ATNO 1504 * is asserted while in message out to take us 1505 * to our host message loop. No NONPACKREQ or 1506 * LQIPHASE type errors will occur in this 1507 * scenario. After this first LQIRETRY, the LQI 1508 * manager will be in ISELO where it will 1509 * happily sit until another packet phase begins. 1510 * Unexpected bus free detection is enabled 1511 * through any phases that occur after we release 1512 * this last ack until the LQI manager sees a 1513 * packet phase. This implies we may have to 1514 * ignore a perfectly valid "unexected busfree" 1515 * after our "initiator detected error" message is 1516 * sent. A busfree is the expected response after 1517 * we tell the target that it's L_Q was corrupted. 1518 * (SPI4R09 10.7.3.3.3) 1519 */ 1520 ahd_outb(ahd, LQCTL2, LQIRETRY); 1521 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1522 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1523 /* 1524 * We detected a CRC error in a NON-LQ packet. 1525 * The hardware has varying behavior in this situation 1526 * depending on whether this packet was part of a 1527 * stream or not. 1528 * 1529 * PKT by PKT mode: 1530 * The hardware has already acked the complete packet. 1531 * If the target honors our outstanding ATN condition, 1532 * we should be (or soon will be) in MSGOUT phase. 1533 * This will trigger the LQIPHASE_LQ status bit as the 1534 * hardware was expecting another LQ. Unexpected 1535 * busfree detection is enabled. Once LQIPHASE_LQ is 1536 * true (first entry into host message loop is much 1537 * the same), we must clear LQIPHASE_LQ and hit 1538 * LQIRETRY so the hardware is ready to handle 1539 * a future LQ. NONPACKREQ will not be asserted again 1540 * once we hit LQIRETRY until another packet is 1541 * processed. The target may either go busfree 1542 * or start another packet in response to our message. 1543 * 1544 * Read Streaming P0 asserted: 1545 * If we raise ATN and the target completes the entire 1546 * stream (P0 asserted during the last packet), the 1547 * hardware will ack all data and return to the ISTART 1548 * state. When the target reponds to our ATN condition, 1549 * LQIPHASE_LQ will be asserted. We should respond to 1550 * this with an LQIRETRY to prepare for any future 1551 * packets. NONPACKREQ will not be asserted again 1552 * once we hit LQIRETRY until another packet is 1553 * processed. The target may either go busfree or 1554 * start another packet in response to our message. 1555 * Busfree detection is enabled. 1556 * 1557 * Read Streaming P0 not asserted: 1558 * If we raise ATN and the target transitions to 1559 * MSGOUT in or after a packet where P0 is not 1560 * asserted, the hardware will assert LQIPHASE_NLQ. 1561 * We should respond to the LQIPHASE_NLQ with an 1562 * LQIRETRY. Should the target stay in a non-pkt 1563 * phase after we send our message, the hardware 1564 * will assert LQIPHASE_LQ. Recovery is then just as 1565 * listed above for the read streaming with P0 asserted. 1566 * Busfree detection is enabled. 1567 */ 1568 if (silent == FALSE) 1569 printf("LQICRC_NLQ\n"); 1570 if (scb == NULL) { 1571 printf("%s: No SCB valid for LQICRC_NLQ. " 1572 "Resetting bus\n", ahd_name(ahd)); 1573 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1574 return; 1575 } 1576 } else if ((lqistat1 & LQIBADLQI) != 0) { 1577 printf("Need to handle BADLQI!\n"); 1578 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1579 return; 1580 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1581 if ((curphase & ~P_DATAIN_DT) != 0) { 1582 /* Ack the byte. So we can continue. */ 1583 if (silent == FALSE) 1584 printf("Acking %s to clear perror\n", 1585 ahd_lookup_phase_entry(curphase)->phasemsg); 1586 ahd_inb(ahd, SCSIDAT); 1587 } 1588 1589 if (curphase == P_MESGIN) 1590 msg_out = MSG_PARITY_ERROR; 1591 } 1592 1593 /* 1594 * We've set the hardware to assert ATN if we 1595 * get a parity error on "in" phases, so all we 1596 * need to do is stuff the message buffer with 1597 * the appropriate message. "In" phases have set 1598 * mesg_out to something other than MSG_NOP. 1599 */ 1600 ahd->send_msg_perror = msg_out; 1601 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1602 scb->flags |= SCB_TRANSMISSION_ERROR; 1603 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1604 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1605 ahd_unpause(ahd); 1606 } 1607 1608 static void 1609 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1610 { 1611 /* 1612 * Clear the sources of the interrupts. 1613 */ 1614 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1615 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1616 1617 /* 1618 * If the "illegal" phase changes were in response 1619 * to our ATN to flag a CRC error, AND we ended up 1620 * on packet boundaries, clear the error, restart the 1621 * LQI manager as appropriate, and go on our merry 1622 * way toward sending the message. Otherwise, reset 1623 * the bus to clear the error. 1624 */ 1625 ahd_set_active_fifo(ahd); 1626 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1627 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1628 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1629 printf("LQIRETRY for LQIPHASE_LQ\n"); 1630 ahd_outb(ahd, LQCTL2, LQIRETRY); 1631 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1632 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1633 ahd_outb(ahd, LQCTL2, LQIRETRY); 1634 } else 1635 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1636 ahd_dump_card_state(ahd); 1637 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1638 ahd_unpause(ahd); 1639 } else { 1640 printf("Reseting Channel for LQI Phase error\n"); 1641 ahd_dump_card_state(ahd); 1642 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1643 } 1644 } 1645 1646 /* 1647 * Packetized unexpected or expected busfree. 1648 * Entered in mode based on busfreetime. 1649 */ 1650 static int 1651 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1652 { 1653 u_int lqostat1; 1654 1655 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1656 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1657 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1658 if ((lqostat1 & LQOBUSFREE) != 0) { 1659 struct scb *scb; 1660 u_int scbid; 1661 u_int saved_scbptr; 1662 u_int waiting_h; 1663 u_int waiting_t; 1664 u_int next; 1665 1666 if ((busfreetime & BUSFREE_LQO) == 0) 1667 printf("%s: Warning, BUSFREE time is 0x%x. " 1668 "Expected BUSFREE_LQO.\n", 1669 ahd_name(ahd), busfreetime); 1670 /* 1671 * The LQO manager detected an unexpected busfree 1672 * either: 1673 * 1674 * 1) During an outgoing LQ. 1675 * 2) After an outgoing LQ but before the first 1676 * REQ of the command packet. 1677 * 3) During an outgoing command packet. 1678 * 1679 * In all cases, CURRSCB is pointing to the 1680 * SCB that encountered the failure. Clean 1681 * up the queue, clear SELDO and LQOBUSFREE, 1682 * and allow the sequencer to restart the select 1683 * out at its lesure. 1684 */ 1685 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1686 scbid = ahd_inw(ahd, CURRSCB); 1687 scb = ahd_lookup_scb(ahd, scbid); 1688 if (scb == NULL) 1689 panic("SCB not valid during LQOBUSFREE"); 1690 /* 1691 * Clear the status. 1692 */ 1693 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1694 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1695 ahd_outb(ahd, CLRLQOINT1, 0); 1696 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1697 ahd_flush_device_writes(ahd); 1698 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1699 1700 /* 1701 * Return the LQO manager to its idle loop. It will 1702 * not do this automatically if the busfree occurs 1703 * after the first REQ of either the LQ or command 1704 * packet or between the LQ and command packet. 1705 */ 1706 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1707 1708 /* 1709 * Update the waiting for selection queue so 1710 * we restart on the correct SCB. 1711 */ 1712 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1713 saved_scbptr = ahd_get_scbptr(ahd); 1714 if (waiting_h != scbid) { 1715 1716 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1717 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1718 if (waiting_t == waiting_h) { 1719 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1720 next = SCB_LIST_NULL; 1721 } else { 1722 ahd_set_scbptr(ahd, waiting_h); 1723 next = ahd_inw_scbram(ahd, SCB_NEXT2); 1724 } 1725 ahd_set_scbptr(ahd, scbid); 1726 ahd_outw(ahd, SCB_NEXT2, next); 1727 } 1728 ahd_set_scbptr(ahd, saved_scbptr); 1729 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1730 if (SCB_IS_SILENT(scb) == FALSE) { 1731 ahd_print_path(ahd, scb); 1732 printf("Probable outgoing LQ CRC error. " 1733 "Retrying command\n"); 1734 } 1735 scb->crc_retry_count++; 1736 } else { 1737 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1738 ahd_freeze_scb(scb); 1739 ahd_freeze_devq(ahd, scb); 1740 } 1741 /* Return unpausing the sequencer. */ 1742 return (0); 1743 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1744 /* 1745 * Ignore what are really parity errors that 1746 * occur on the last REQ of a free running 1747 * clock prior to going busfree. Some drives 1748 * do not properly active negate just before 1749 * going busfree resulting in a parity glitch. 1750 */ 1751 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1752 #ifdef AHD_DEBUG 1753 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1754 printf("%s: Parity on last REQ detected " 1755 "during busfree phase.\n", 1756 ahd_name(ahd)); 1757 #endif 1758 /* Return unpausing the sequencer. */ 1759 return (0); 1760 } 1761 if (ahd->src_mode != AHD_MODE_SCSI) { 1762 u_int scbid; 1763 struct scb *scb; 1764 1765 scbid = ahd_get_scbptr(ahd); 1766 scb = ahd_lookup_scb(ahd, scbid); 1767 ahd_print_path(ahd, scb); 1768 printf("Unexpected PKT busfree condition\n"); 1769 ahd_dump_card_state(ahd); 1770 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1771 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1772 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1773 1774 /* Return restarting the sequencer. */ 1775 return (1); 1776 } 1777 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1778 ahd_dump_card_state(ahd); 1779 /* Restart the sequencer. */ 1780 return (1); 1781 } 1782 1783 /* 1784 * Non-packetized unexpected or expected busfree. 1785 */ 1786 static int 1787 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1788 { 1789 struct ahd_devinfo devinfo; 1790 struct scb *scb; 1791 u_int lastphase; 1792 u_int saved_scsiid; 1793 u_int saved_lun; 1794 u_int target; 1795 u_int initiator_role_id; 1796 u_int scbid; 1797 u_int ppr_busfree; 1798 int printerror; 1799 1800 /* 1801 * Look at what phase we were last in. If its message out, 1802 * chances are pretty good that the busfree was in response 1803 * to one of our abort requests. 1804 */ 1805 lastphase = ahd_inb(ahd, LASTPHASE); 1806 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1807 saved_lun = ahd_inb(ahd, SAVED_LUN); 1808 target = SCSIID_TARGET(ahd, saved_scsiid); 1809 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1810 ahd_compile_devinfo(&devinfo, initiator_role_id, 1811 target, saved_lun, 'A', ROLE_INITIATOR); 1812 printerror = 1; 1813 1814 scbid = ahd_get_scbptr(ahd); 1815 scb = ahd_lookup_scb(ahd, scbid); 1816 if (scb != NULL 1817 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1818 scb = NULL; 1819 1820 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1821 if (lastphase == P_MESGOUT) { 1822 u_int tag; 1823 1824 tag = SCB_LIST_NULL; 1825 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1826 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1827 int found; 1828 int sent_msg; 1829 1830 if (scb == NULL) { 1831 ahd_print_devinfo(ahd, &devinfo); 1832 printf("Abort for unidentified " 1833 "connection completed.\n"); 1834 /* restart the sequencer. */ 1835 return (1); 1836 } 1837 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1838 ahd_print_path(ahd, scb); 1839 printf("SCB %d - Abort%s Completed.\n", 1840 SCB_GET_TAG(scb), 1841 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1842 1843 if (sent_msg == MSG_ABORT_TAG) 1844 tag = SCB_GET_TAG(scb); 1845 1846 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1847 /* 1848 * This abort is in response to an 1849 * unexpected switch to command phase 1850 * for a packetized connection. Since 1851 * the identify message was never sent, 1852 * "saved lun" is 0. We really want to 1853 * abort only the SCB that encountered 1854 * this error, which could have a different 1855 * lun. The SCB will be retried so the OS 1856 * will see the UA after renegotiating to 1857 * packetized. 1858 */ 1859 tag = SCB_GET_TAG(scb); 1860 saved_lun = scb->hscb->lun; 1861 } 1862 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1863 tag, ROLE_INITIATOR, 1864 CAM_REQ_ABORTED); 1865 printf("found == 0x%x\n", found); 1866 printerror = 0; 1867 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1868 MSG_BUS_DEV_RESET, TRUE)) { 1869 #ifdef __FreeBSD__ 1870 /* 1871 * Don't mark the user's request for this BDR 1872 * as completing with CAM_BDR_SENT. CAM3 1873 * specifies CAM_REQ_CMP. 1874 */ 1875 if (scb != NULL 1876 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1877 && ahd_match_scb(ahd, scb, target, 'A', 1878 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1879 ROLE_INITIATOR)) 1880 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1881 #endif 1882 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1883 CAM_BDR_SENT, "Bus Device Reset", 1884 /*verbose_level*/0); 1885 printerror = 0; 1886 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1887 && ppr_busfree == 0) { 1888 struct ahd_initiator_tinfo *tinfo; 1889 struct ahd_tmode_tstate *tstate; 1890 1891 /* 1892 * PPR Rejected. Try non-ppr negotiation 1893 * and retry command. 1894 */ 1895 #ifdef AHD_DEBUG 1896 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1897 printf("PPR negotiation rejected busfree.\n"); 1898 #endif 1899 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1900 devinfo.our_scsiid, 1901 devinfo.target, &tstate); 1902 tinfo->curr.transport_version = 2; 1903 tinfo->goal.transport_version = 2; 1904 tinfo->goal.ppr_options = 0; 1905 ahd_qinfifo_requeue_tail(ahd, scb); 1906 printerror = 0; 1907 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1908 && ppr_busfree == 0) { 1909 /* 1910 * Negotiation Rejected. Go-narrow and 1911 * retry command. 1912 */ 1913 #ifdef AHD_DEBUG 1914 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1915 printf("WDTR Negotiation rejected busfree.\n"); 1916 #endif 1917 ahd_set_width(ahd, &devinfo, 1918 MSG_EXT_WDTR_BUS_8_BIT, 1919 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1920 /*paused*/TRUE); 1921 ahd_qinfifo_requeue_tail(ahd, scb); 1922 printerror = 0; 1923 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 1924 && ppr_busfree == 0) { 1925 /* 1926 * Negotiation Rejected. Go-async and 1927 * retry command. 1928 */ 1929 #ifdef AHD_DEBUG 1930 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1931 printf("SDTR negotiation rejected busfree.\n"); 1932 #endif 1933 ahd_set_syncrate(ahd, &devinfo, 1934 /*period*/0, /*offset*/0, 1935 /*ppr_options*/0, 1936 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1937 /*paused*/TRUE); 1938 ahd_qinfifo_requeue_tail(ahd, scb); 1939 printerror = 0; 1940 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1941 && ahd_sent_msg(ahd, AHDMSG_1B, 1942 MSG_INITIATOR_DET_ERR, TRUE)) { 1943 1944 #ifdef AHD_DEBUG 1945 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1946 printf("Expected IDE Busfree\n"); 1947 #endif 1948 printerror = 0; 1949 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1950 && ahd_sent_msg(ahd, AHDMSG_1B, 1951 MSG_MESSAGE_REJECT, TRUE)) { 1952 1953 #ifdef AHD_DEBUG 1954 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1955 printf("Expected QAS Reject Busfree\n"); 1956 #endif 1957 printerror = 0; 1958 } 1959 } 1960 1961 /* 1962 * The busfree required flag is honored at the end of 1963 * the message phases. We check it last in case we 1964 * had to send some other message that caused a busfree. 1965 */ 1966 if (printerror != 0 1967 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1968 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1969 1970 ahd_freeze_devq(ahd, scb); 1971 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1972 ahd_freeze_scb(scb); 1973 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1974 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1975 SCB_GET_CHANNEL(ahd, scb), 1976 SCB_GET_LUN(scb), SCB_LIST_NULL, 1977 ROLE_INITIATOR, CAM_REQ_ABORTED); 1978 } else { 1979 #ifdef AHD_DEBUG 1980 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1981 printf("PPR Negotiation Busfree.\n"); 1982 #endif 1983 ahd_done(ahd, scb); 1984 } 1985 printerror = 0; 1986 } 1987 if (printerror != 0) { 1988 int aborted; 1989 1990 aborted = 0; 1991 if (scb != NULL) { 1992 u_int tag; 1993 1994 if ((scb->hscb->control & TAG_ENB) != 0) 1995 tag = SCB_GET_TAG(scb); 1996 else 1997 tag = SCB_LIST_NULL; 1998 ahd_print_path(ahd, scb); 1999 aborted = ahd_abort_scbs(ahd, target, 'A', 2000 SCB_GET_LUN(scb), tag, 2001 ROLE_INITIATOR, 2002 CAM_UNEXP_BUSFREE); 2003 } else { 2004 /* 2005 * We had not fully identified this connection, 2006 * so we cannot abort anything. 2007 */ 2008 printf("%s: ", ahd_name(ahd)); 2009 } 2010 if (lastphase != P_BUSFREE) 2011 ahd_force_renegotiation(ahd, &devinfo); 2012 printf("Unexpected busfree %s, %d SCBs aborted, " 2013 "PRGMCNT == 0x%x\n", 2014 ahd_lookup_phase_entry(lastphase)->phasemsg, 2015 aborted, 2016 ahd_inb(ahd, PRGMCNT) 2017 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 2018 ahd_dump_card_state(ahd); 2019 } 2020 /* Always restart the sequencer. */ 2021 return (1); 2022 } 2023 2024 static void 2025 ahd_handle_proto_violation(struct ahd_softc *ahd) 2026 { 2027 struct ahd_devinfo devinfo; 2028 struct scb *scb; 2029 u_int scbid; 2030 u_int seq_flags; 2031 u_int curphase; 2032 u_int lastphase; 2033 int found; 2034 2035 ahd_fetch_devinfo(ahd, &devinfo); 2036 scbid = ahd_get_scbptr(ahd); 2037 scb = ahd_lookup_scb(ahd, scbid); 2038 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2039 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2040 lastphase = ahd_inb(ahd, LASTPHASE); 2041 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2042 2043 /* 2044 * The reconnecting target either did not send an 2045 * identify message, or did, but we didn't find an SCB 2046 * to match. 2047 */ 2048 ahd_print_devinfo(ahd, &devinfo); 2049 printf("Target did not send an IDENTIFY message. " 2050 "LASTPHASE = 0x%x.\n", lastphase); 2051 scb = NULL; 2052 } else if (scb == NULL) { 2053 /* 2054 * We don't seem to have an SCB active for this 2055 * transaction. Print an error and reset the bus. 2056 */ 2057 ahd_print_devinfo(ahd, &devinfo); 2058 printf("No SCB found during protocol violation\n"); 2059 goto proto_violation_reset; 2060 } else { 2061 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2062 if ((seq_flags & NO_CDB_SENT) != 0) { 2063 ahd_print_path(ahd, scb); 2064 printf("No or incomplete CDB sent to device.\n"); 2065 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2066 & STATUS_RCVD) == 0) { 2067 /* 2068 * The target never bothered to provide status to 2069 * us prior to completing the command. Since we don't 2070 * know the disposition of this command, we must attempt 2071 * to abort it. Assert ATN and prepare to send an abort 2072 * message. 2073 */ 2074 ahd_print_path(ahd, scb); 2075 printf("Completed command without status.\n"); 2076 } else { 2077 ahd_print_path(ahd, scb); 2078 printf("Unknown protocol violation.\n"); 2079 ahd_dump_card_state(ahd); 2080 } 2081 } 2082 if ((lastphase & ~P_DATAIN_DT) == 0 2083 || lastphase == P_COMMAND) { 2084 proto_violation_reset: 2085 /* 2086 * Target either went directly to data 2087 * phase or didn't respond to our ATN. 2088 * The only safe thing to do is to blow 2089 * it away with a bus reset. 2090 */ 2091 found = ahd_reset_channel(ahd, 'A', TRUE); 2092 printf("%s: Issued Channel %c Bus Reset. " 2093 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2094 } else { 2095 /* 2096 * Leave the selection hardware off in case 2097 * this abort attempt will affect yet to 2098 * be sent commands. 2099 */ 2100 ahd_outb(ahd, SCSISEQ0, 2101 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2102 ahd_assert_atn(ahd); 2103 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2104 if (scb == NULL) { 2105 ahd_print_devinfo(ahd, &devinfo); 2106 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2107 ahd->msgout_len = 1; 2108 ahd->msgout_index = 0; 2109 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2110 } else { 2111 ahd_print_path(ahd, scb); 2112 scb->flags |= SCB_ABORT; 2113 } 2114 printf("Protocol violation %s. Attempting to abort.\n", 2115 ahd_lookup_phase_entry(curphase)->phasemsg); 2116 } 2117 } 2118 2119 /* 2120 * Force renegotiation to occur the next time we initiate 2121 * a command to the current device. 2122 */ 2123 static void 2124 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2125 { 2126 struct ahd_initiator_tinfo *targ_info; 2127 struct ahd_tmode_tstate *tstate; 2128 2129 #ifdef AHD_DEBUG 2130 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2131 ahd_print_devinfo(ahd, devinfo); 2132 printf("Forcing renegotiation\n"); 2133 } 2134 #endif 2135 targ_info = ahd_fetch_transinfo(ahd, 2136 devinfo->channel, 2137 devinfo->our_scsiid, 2138 devinfo->target, 2139 &tstate); 2140 ahd_update_neg_request(ahd, devinfo, tstate, 2141 targ_info, AHD_NEG_IF_NON_ASYNC); 2142 } 2143 2144 #define AHD_MAX_STEPS 2000 2145 void 2146 ahd_clear_critical_section(struct ahd_softc *ahd) 2147 { 2148 ahd_mode_state saved_modes; 2149 int stepping; 2150 int steps; 2151 int first_instr; 2152 u_int simode0; 2153 u_int simode1; 2154 u_int simode3; 2155 u_int lqimode0; 2156 u_int lqimode1; 2157 u_int lqomode0; 2158 u_int lqomode1; 2159 2160 if (ahd->num_critical_sections == 0) 2161 return; 2162 2163 stepping = FALSE; 2164 steps = 0; 2165 first_instr = 0; 2166 simode0 = 0; 2167 simode1 = 0; 2168 simode3 = 0; 2169 lqimode0 = 0; 2170 lqimode1 = 0; 2171 lqomode0 = 0; 2172 lqomode1 = 0; 2173 saved_modes = ahd_save_modes(ahd); 2174 for (;;) { 2175 struct cs *cs; 2176 u_int seqaddr; 2177 u_int i; 2178 2179 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2180 seqaddr = ahd_inb(ahd, CURADDR) 2181 | (ahd_inb(ahd, CURADDR+1) << 8); 2182 2183 cs = ahd->critical_sections; 2184 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2185 2186 if (cs->begin < seqaddr && cs->end >= seqaddr) 2187 break; 2188 } 2189 2190 if (i == ahd->num_critical_sections) 2191 break; 2192 2193 if (steps > AHD_MAX_STEPS) { 2194 printf("%s: Infinite loop in critical section\n" 2195 "%s: First Instruction 0x%x now 0x%x\n", 2196 ahd_name(ahd), ahd_name(ahd), first_instr, 2197 seqaddr); 2198 ahd_dump_card_state(ahd); 2199 panic("critical section loop"); 2200 } 2201 2202 steps++; 2203 #ifdef AHD_DEBUG 2204 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2205 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2206 seqaddr); 2207 #endif 2208 if (stepping == FALSE) { 2209 2210 first_instr = seqaddr; 2211 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2212 simode0 = ahd_inb(ahd, SIMODE0); 2213 simode3 = ahd_inb(ahd, SIMODE3); 2214 lqimode0 = ahd_inb(ahd, LQIMODE0); 2215 lqimode1 = ahd_inb(ahd, LQIMODE1); 2216 lqomode0 = ahd_inb(ahd, LQOMODE0); 2217 lqomode1 = ahd_inb(ahd, LQOMODE1); 2218 ahd_outb(ahd, SIMODE0, 0); 2219 ahd_outb(ahd, SIMODE3, 0); 2220 ahd_outb(ahd, LQIMODE0, 0); 2221 ahd_outb(ahd, LQIMODE1, 0); 2222 ahd_outb(ahd, LQOMODE0, 0); 2223 ahd_outb(ahd, LQOMODE1, 0); 2224 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2225 simode1 = ahd_inb(ahd, SIMODE1); 2226 /* 2227 * We don't clear ENBUSFREE. Unfortunately 2228 * we cannot re-enable busfree detection within 2229 * the current connection, so we must leave it 2230 * on while single stepping. 2231 */ 2232 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2233 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2234 stepping = TRUE; 2235 } 2236 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2237 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2238 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2239 ahd_outb(ahd, HCNTRL, ahd->unpause); 2240 while (!ahd_is_paused(ahd)) 2241 ahd_delay(200); 2242 ahd_update_modes(ahd); 2243 } 2244 if (stepping) { 2245 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2246 ahd_outb(ahd, SIMODE0, simode0); 2247 ahd_outb(ahd, SIMODE3, simode3); 2248 ahd_outb(ahd, LQIMODE0, lqimode0); 2249 ahd_outb(ahd, LQIMODE1, lqimode1); 2250 ahd_outb(ahd, LQOMODE0, lqomode0); 2251 ahd_outb(ahd, LQOMODE1, lqomode1); 2252 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2253 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2254 ahd_outb(ahd, SIMODE1, simode1); 2255 /* 2256 * SCSIINT seems to glitch occassionally when 2257 * the interrupt masks are restored. Clear SCSIINT 2258 * one more time so that only persistent errors 2259 * are seen as a real interrupt. 2260 */ 2261 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2262 } 2263 ahd_restore_modes(ahd, saved_modes); 2264 } 2265 2266 /* 2267 * Clear any pending interrupt status. 2268 */ 2269 void 2270 ahd_clear_intstat(struct ahd_softc *ahd) 2271 { 2272 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2273 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2274 /* Clear any interrupt conditions this may have caused */ 2275 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2276 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2277 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2278 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2279 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2280 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2281 |CLRLQOATNPKT|CLRLQOTCRC); 2282 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2283 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2284 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2285 ahd_outb(ahd, CLRLQOINT0, 0); 2286 ahd_outb(ahd, CLRLQOINT1, 0); 2287 } 2288 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2289 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2290 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2291 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2292 |CLRIOERR|CLROVERRUN); 2293 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2294 } 2295 2296 /**************************** Debugging Routines ******************************/ 2297 #ifdef AHD_DEBUG 2298 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2299 #endif 2300 void 2301 ahd_print_scb(struct scb *scb) 2302 { 2303 struct hardware_scb *hscb; 2304 int i; 2305 2306 hscb = scb->hscb; 2307 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2308 (void *)scb, 2309 hscb->control, 2310 hscb->scsiid, 2311 hscb->lun, 2312 hscb->cdb_len); 2313 printf("Shared Data: "); 2314 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2315 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2316 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2317 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2318 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2319 ahd_le32toh(hscb->datacnt), 2320 ahd_le32toh(hscb->sgptr), 2321 SCB_GET_TAG(scb)); 2322 ahd_dump_sglist(scb); 2323 } 2324 2325 void 2326 ahd_dump_sglist(struct scb *scb) 2327 { 2328 int i; 2329 2330 if (scb->sg_count > 0) { 2331 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2332 struct ahd_dma64_seg *sg_list; 2333 2334 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2335 for (i = 0; i < scb->sg_count; i++) { 2336 uint64_t addr; 2337 uint32_t len; 2338 2339 addr = ahd_le64toh(sg_list[i].addr); 2340 len = ahd_le32toh(sg_list[i].len); 2341 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2342 i, 2343 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2344 (uint32_t)(addr & 0xFFFFFFFF), 2345 sg_list[i].len & AHD_SG_LEN_MASK, 2346 (sg_list[i].len & AHD_DMA_LAST_SEG) 2347 ? " Last" : ""); 2348 } 2349 } else { 2350 struct ahd_dma_seg *sg_list; 2351 2352 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2353 for (i = 0; i < scb->sg_count; i++) { 2354 uint32_t len; 2355 2356 len = ahd_le32toh(sg_list[i].len); 2357 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2358 i, 2359 (len >> 24) & SG_HIGH_ADDR_BITS, 2360 ahd_le32toh(sg_list[i].addr), 2361 len & AHD_SG_LEN_MASK, 2362 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2363 } 2364 } 2365 } 2366 } 2367 2368 /************************* Transfer Negotiation *******************************/ 2369 /* 2370 * Allocate per target mode instance (ID we respond to as a target) 2371 * transfer negotiation data structures. 2372 */ 2373 static struct ahd_tmode_tstate * 2374 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2375 { 2376 struct ahd_tmode_tstate *master_tstate; 2377 struct ahd_tmode_tstate *tstate; 2378 int i; 2379 2380 master_tstate = ahd->enabled_targets[ahd->our_id]; 2381 if (ahd->enabled_targets[scsi_id] != NULL 2382 && ahd->enabled_targets[scsi_id] != master_tstate) 2383 panic("%s: ahd_alloc_tstate - Target already allocated", 2384 ahd_name(ahd)); 2385 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 2386 if (tstate == NULL) 2387 return (NULL); 2388 2389 /* 2390 * If we have allocated a master tstate, copy user settings from 2391 * the master tstate (taken from SRAM or the EEPROM) for this 2392 * channel, but reset our current and goal settings to async/narrow 2393 * until an initiator talks to us. 2394 */ 2395 if (master_tstate != NULL) { 2396 memcpy(tstate, master_tstate, sizeof(*tstate)); 2397 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2398 for (i = 0; i < 16; i++) { 2399 memset(&tstate->transinfo[i].curr, 0, 2400 sizeof(tstate->transinfo[i].curr)); 2401 memset(&tstate->transinfo[i].goal, 0, 2402 sizeof(tstate->transinfo[i].goal)); 2403 } 2404 } else 2405 memset(tstate, 0, sizeof(*tstate)); 2406 ahd->enabled_targets[scsi_id] = tstate; 2407 return (tstate); 2408 } 2409 2410 #ifdef AHD_TARGET_MODE 2411 /* 2412 * Free per target mode instance (ID we respond to as a target) 2413 * transfer negotiation data structures. 2414 */ 2415 static void 2416 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2417 { 2418 struct ahd_tmode_tstate *tstate; 2419 2420 /* 2421 * Don't clean up our "master" tstate. 2422 * It has our default user settings. 2423 */ 2424 if (scsi_id == ahd->our_id 2425 && force == FALSE) 2426 return; 2427 2428 tstate = ahd->enabled_targets[scsi_id]; 2429 if (tstate != NULL) 2430 free(tstate, M_DEVBUF); 2431 ahd->enabled_targets[scsi_id] = NULL; 2432 } 2433 #endif 2434 2435 /* 2436 * Called when we have an active connection to a target on the bus, 2437 * this function finds the nearest period to the input period limited 2438 * by the capabilities of the bus connectivity of and sync settings for 2439 * the target. 2440 */ 2441 void 2442 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2443 struct ahd_initiator_tinfo *tinfo, 2444 u_int *period, u_int *ppr_options, role_t role) 2445 { 2446 struct ahd_transinfo *transinfo; 2447 u_int maxsync; 2448 2449 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2450 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2451 maxsync = AHD_SYNCRATE_PACED; 2452 } else { 2453 maxsync = AHD_SYNCRATE_ULTRA; 2454 /* Can't do DT related options on an SE bus */ 2455 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2456 } 2457 /* 2458 * Never allow a value higher than our current goal 2459 * period otherwise we may allow a target initiated 2460 * negotiation to go above the limit as set by the 2461 * user. In the case of an initiator initiated 2462 * sync negotiation, we limit based on the user 2463 * setting. This allows the system to still accept 2464 * incoming negotiations even if target initiated 2465 * negotiation is not performed. 2466 */ 2467 if (role == ROLE_TARGET) 2468 transinfo = &tinfo->user; 2469 else 2470 transinfo = &tinfo->goal; 2471 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2472 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2473 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2474 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2475 } 2476 if (transinfo->period == 0) { 2477 *period = 0; 2478 *ppr_options = 0; 2479 } else { 2480 *period = MAX(*period, transinfo->period); 2481 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2482 } 2483 } 2484 2485 /* 2486 * Look up the valid period to SCSIRATE conversion in our table. 2487 * Return the period and offset that should be sent to the target 2488 * if this was the beginning of an SDTR. 2489 */ 2490 void 2491 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2492 u_int *ppr_options, u_int maxsync) 2493 { 2494 if (*period < maxsync) 2495 *period = maxsync; 2496 2497 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2498 && *period > AHD_SYNCRATE_MIN_DT) 2499 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2500 2501 if (*period > AHD_SYNCRATE_MIN) 2502 *period = 0; 2503 2504 /* Honor PPR option conformance rules. */ 2505 if (*period > AHD_SYNCRATE_PACED) 2506 *ppr_options &= ~MSG_EXT_PPR_RTI; 2507 2508 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2509 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2510 2511 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2512 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2513 2514 /* Skip all PACED only entries if IU is not available */ 2515 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2516 && *period < AHD_SYNCRATE_DT) 2517 *period = AHD_SYNCRATE_DT; 2518 2519 /* Skip all DT only entries if DT is not available */ 2520 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2521 && *period < AHD_SYNCRATE_ULTRA2) 2522 *period = AHD_SYNCRATE_ULTRA2; 2523 } 2524 2525 /* 2526 * Truncate the given synchronous offset to a value the 2527 * current adapter type and syncrate are capable of. 2528 */ 2529 void 2530 ahd_validate_offset(struct ahd_softc *ahd, 2531 struct ahd_initiator_tinfo *tinfo, 2532 u_int period, u_int *offset, int wide, 2533 role_t role) 2534 { 2535 u_int maxoffset; 2536 2537 /* Limit offset to what we can do */ 2538 if (period == 0) 2539 maxoffset = 0; 2540 else if (period <= AHD_SYNCRATE_PACED) { 2541 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2542 maxoffset = MAX_OFFSET_PACED_BUG; 2543 else 2544 maxoffset = MAX_OFFSET_PACED; 2545 } else 2546 maxoffset = MAX_OFFSET_NON_PACED; 2547 *offset = MIN(*offset, maxoffset); 2548 if (tinfo != NULL) { 2549 if (role == ROLE_TARGET) 2550 *offset = MIN(*offset, tinfo->user.offset); 2551 else 2552 *offset = MIN(*offset, tinfo->goal.offset); 2553 } 2554 } 2555 2556 /* 2557 * Truncate the given transfer width parameter to a value the 2558 * current adapter type is capable of. 2559 */ 2560 void 2561 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2562 u_int *bus_width, role_t role) 2563 { 2564 switch (*bus_width) { 2565 default: 2566 if (ahd->features & AHD_WIDE) { 2567 /* Respond Wide */ 2568 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2569 break; 2570 } 2571 /* FALLTHROUGH */ 2572 case MSG_EXT_WDTR_BUS_8_BIT: 2573 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2574 break; 2575 } 2576 if (tinfo != NULL) { 2577 if (role == ROLE_TARGET) 2578 *bus_width = MIN(tinfo->user.width, *bus_width); 2579 else 2580 *bus_width = MIN(tinfo->goal.width, *bus_width); 2581 } 2582 } 2583 2584 /* 2585 * Update the bitmask of targets for which the controller should 2586 * negotiate with at the next convenient oportunity. This currently 2587 * means the next time we send the initial identify messages for 2588 * a new transaction. 2589 */ 2590 int 2591 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2592 struct ahd_tmode_tstate *tstate, 2593 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2594 { 2595 u_int auto_negotiate_orig; 2596 2597 auto_negotiate_orig = tstate->auto_negotiate; 2598 if (neg_type == AHD_NEG_ALWAYS) { 2599 /* 2600 * Force our "current" settings to be 2601 * unknown so that unless a bus reset 2602 * occurs the need to renegotiate is 2603 * recorded persistently. 2604 */ 2605 if ((ahd->features & AHD_WIDE) != 0) 2606 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2607 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2608 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2609 } 2610 if (tinfo->curr.period != tinfo->goal.period 2611 || tinfo->curr.width != tinfo->goal.width 2612 || tinfo->curr.offset != tinfo->goal.offset 2613 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2614 || (neg_type == AHD_NEG_IF_NON_ASYNC 2615 && (tinfo->goal.offset != 0 2616 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2617 || tinfo->goal.ppr_options != 0))) 2618 tstate->auto_negotiate |= devinfo->target_mask; 2619 else 2620 tstate->auto_negotiate &= ~devinfo->target_mask; 2621 2622 return (auto_negotiate_orig != tstate->auto_negotiate); 2623 } 2624 2625 /* 2626 * Update the user/goal/curr tables of synchronous negotiation 2627 * parameters as well as, in the case of a current or active update, 2628 * any data structures on the host controller. In the case of an 2629 * active update, the specified target is currently talking to us on 2630 * the bus, so the transfer parameter update must take effect 2631 * immediately. 2632 */ 2633 void 2634 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2635 u_int period, u_int offset, u_int ppr_options, 2636 u_int type, int paused) 2637 { 2638 struct ahd_initiator_tinfo *tinfo; 2639 struct ahd_tmode_tstate *tstate; 2640 u_int old_period; 2641 u_int old_offset; 2642 u_int old_ppr; 2643 int active; 2644 int update_needed; 2645 2646 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2647 update_needed = 0; 2648 2649 if (period == 0 || offset == 0) { 2650 period = 0; 2651 offset = 0; 2652 } 2653 2654 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2655 devinfo->target, &tstate); 2656 2657 if ((type & AHD_TRANS_USER) != 0) { 2658 tinfo->user.period = period; 2659 tinfo->user.offset = offset; 2660 tinfo->user.ppr_options = ppr_options; 2661 } 2662 2663 if ((type & AHD_TRANS_GOAL) != 0) { 2664 tinfo->goal.period = period; 2665 tinfo->goal.offset = offset; 2666 tinfo->goal.ppr_options = ppr_options; 2667 } 2668 2669 old_period = tinfo->curr.period; 2670 old_offset = tinfo->curr.offset; 2671 old_ppr = tinfo->curr.ppr_options; 2672 2673 if ((type & AHD_TRANS_CUR) != 0 2674 && (old_period != period 2675 || old_offset != offset 2676 || old_ppr != ppr_options)) { 2677 2678 update_needed++; 2679 2680 tinfo->curr.period = period; 2681 tinfo->curr.offset = offset; 2682 tinfo->curr.ppr_options = ppr_options; 2683 2684 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2685 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2686 2687 if (bootverbose) { 2688 if (offset != 0) { 2689 int options; 2690 2691 printf("%s: target %d synchronous with " 2692 "period = 0x%x, offset = 0x%x", 2693 ahd_name(ahd), devinfo->target, 2694 period, offset); 2695 options = 0; 2696 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 2697 printf("(RDSTRM"); 2698 options++; 2699 } 2700 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2701 printf("%s", options ? "|DT" : "(DT"); 2702 options++; 2703 } 2704 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2705 printf("%s", options ? "|IU" : "(IU"); 2706 options++; 2707 } 2708 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2709 printf("%s", options ? "|RTI" : "(RTI"); 2710 options++; 2711 } 2712 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2713 printf("%s", options ? "|QAS" : "(QAS"); 2714 options++; 2715 } 2716 if (options != 0) 2717 printf(")\n"); 2718 else 2719 printf("\n"); 2720 } else { 2721 printf("%s: target %d using " 2722 "asynchronous transfers%s\n", 2723 ahd_name(ahd), devinfo->target, 2724 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2725 ? "(QAS)" : ""); 2726 } 2727 } 2728 } 2729 /* 2730 * Always refresh the neg-table to handle the case of the 2731 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2732 * We will always renegotiate in that case if this is a 2733 * packetized request. Also manage the busfree expected flag 2734 * from this common routine so that we catch changes due to 2735 * WDTR or SDTR messages. 2736 */ 2737 if ((type & AHD_TRANS_CUR) != 0) { 2738 if (!paused) 2739 ahd_pause(ahd); 2740 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2741 if (!paused) 2742 ahd_unpause(ahd); 2743 if (ahd->msg_type != MSG_TYPE_NONE) { 2744 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2745 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2746 #ifdef AHD_DEBUG 2747 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2748 ahd_print_devinfo(ahd, devinfo); 2749 printf("Expecting IU Change busfree\n"); 2750 } 2751 #endif 2752 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2753 | MSG_FLAG_IU_REQ_CHANGED; 2754 } 2755 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2756 #ifdef AHD_DEBUG 2757 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2758 printf("PPR with IU_REQ outstanding\n"); 2759 #endif 2760 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2761 } 2762 } 2763 } 2764 2765 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2766 tinfo, AHD_NEG_TO_GOAL); 2767 2768 if (update_needed) 2769 ahd_update_xfer_mode(ahd, devinfo); 2770 ahd->sc_req = 0; 2771 2772 if (update_needed && active) 2773 ahd_update_pending_scbs(ahd); 2774 } 2775 2776 /* 2777 * Update the user/goal/curr tables of wide negotiation 2778 * parameters as well as, in the case of a current or active update, 2779 * any data structures on the host controller. In the case of an 2780 * active update, the specified target is currently talking to us on 2781 * the bus, so the transfer parameter update must take effect 2782 * immediately. 2783 */ 2784 void 2785 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2786 u_int width, u_int type, int paused) 2787 { 2788 struct ahd_initiator_tinfo *tinfo; 2789 struct ahd_tmode_tstate *tstate; 2790 u_int oldwidth; 2791 int active; 2792 int update_needed; 2793 2794 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2795 update_needed = 0; 2796 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2797 devinfo->target, &tstate); 2798 2799 if ((type & AHD_TRANS_USER) != 0) 2800 tinfo->user.width = width; 2801 2802 if ((type & AHD_TRANS_GOAL) != 0) 2803 tinfo->goal.width = width; 2804 2805 oldwidth = tinfo->curr.width; 2806 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2807 2808 update_needed++; 2809 2810 tinfo->curr.width = width; 2811 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2812 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2813 2814 if (bootverbose) { 2815 printf("%s: target %d using %dbit transfers\n", 2816 ahd_name(ahd), devinfo->target, 2817 8 * (0x01 << width)); 2818 } 2819 } 2820 2821 if ((type & AHD_TRANS_CUR) != 0) { 2822 if (!paused) 2823 ahd_pause(ahd); 2824 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2825 if (!paused) 2826 ahd_unpause(ahd); 2827 } 2828 2829 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2830 tinfo, AHD_NEG_TO_GOAL); 2831 if (update_needed && active) 2832 ahd_update_pending_scbs(ahd); 2833 2834 } 2835 2836 /* 2837 * Update the current state of tagged queuing for a given target. 2838 */ 2839 void 2840 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2841 ahd_queue_alg alg) 2842 { 2843 ahd_platform_set_tags(ahd, devinfo, alg); 2844 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2845 devinfo->lun, AC_TRANSFER_NEG, &alg); 2846 } 2847 2848 static void 2849 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2850 struct ahd_transinfo *tinfo) 2851 { 2852 ahd_mode_state saved_modes; 2853 u_int period; 2854 u_int ppr_opts; 2855 u_int con_opts; 2856 u_int offset; 2857 u_int saved_negoaddr; 2858 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2859 2860 saved_modes = ahd_save_modes(ahd); 2861 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2862 2863 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2864 ahd_outb(ahd, NEGOADDR, devinfo->target); 2865 period = tinfo->period; 2866 offset = tinfo->offset; 2867 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2868 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2869 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2870 con_opts = 0; 2871 if (period == 0) 2872 period = AHD_SYNCRATE_ASYNC; 2873 if (period == AHD_SYNCRATE_160) { 2874 2875 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2876 /* 2877 * When the SPI4 spec was finalized, PACE transfers 2878 * was not made a configurable option in the PPR 2879 * message. Instead it is assumed to be enabled for 2880 * any syncrate faster than 80MHz. Nevertheless, 2881 * Harpoon2A4 allows this to be configurable. 2882 * 2883 * Harpoon2A4 also assumes at most 2 data bytes per 2884 * negotiated REQ/ACK offset. Paced transfers take 2885 * 4, so we must adjust our offset. 2886 */ 2887 ppr_opts |= PPROPT_PACE; 2888 offset *= 2; 2889 2890 /* 2891 * Harpoon2A assumed that there would be a 2892 * fallback rate between 160MHz and 80Mhz, 2893 * so 7 is used as the period factor rather 2894 * than 8 for 160MHz. 2895 */ 2896 period = AHD_SYNCRATE_REVA_160; 2897 } 2898 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2899 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2900 ~AHD_PRECOMP_MASK; 2901 } else { 2902 /* 2903 * Precomp should be disabled for non-paced transfers. 2904 */ 2905 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2906 2907 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2908 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2909 /* 2910 * Slow down our CRC interval to be 2911 * compatible with devices that can't 2912 * handle a CRC at full speed. 2913 */ 2914 con_opts |= ENSLOWCRC; 2915 } 2916 } 2917 2918 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2919 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2920 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2921 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2922 2923 ahd_outb(ahd, NEGPERIOD, period); 2924 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2925 ahd_outb(ahd, NEGOFFSET, offset); 2926 2927 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2928 con_opts |= WIDEXFER; 2929 2930 /* 2931 * During packetized transfers, the target will 2932 * give us the oportunity to send command packets 2933 * without us asserting attention. 2934 */ 2935 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2936 con_opts |= ENAUTOATNO; 2937 ahd_outb(ahd, NEGCONOPTS, con_opts); 2938 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2939 ahd_restore_modes(ahd, saved_modes); 2940 } 2941 2942 /* 2943 * When the transfer settings for a connection change, setup for 2944 * negotiation in pending SCBs to effect the change as quickly as 2945 * possible. We also cancel any negotiations that are scheduled 2946 * for inflight SCBs that have not been started yet. 2947 */ 2948 static void 2949 ahd_update_pending_scbs(struct ahd_softc *ahd) 2950 { 2951 struct scb *pending_scb; 2952 int pending_scb_count; 2953 int i; 2954 int paused; 2955 u_int saved_scbptr; 2956 ahd_mode_state saved_modes; 2957 2958 /* 2959 * Traverse the pending SCB list and ensure that all of the 2960 * SCBs there have the proper settings. We can only safely 2961 * clear the negotiation required flag (setting requires the 2962 * execution queue to be modified) and this is only possible 2963 * if we are not already attempting to select out for this 2964 * SCB. For this reason, all callers only call this routine 2965 * if we are changing the negotiation settings for the currently 2966 * active transaction on the bus. 2967 */ 2968 pending_scb_count = 0; 2969 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2970 struct ahd_devinfo devinfo; 2971 struct hardware_scb *pending_hscb; 2972 struct ahd_initiator_tinfo *tinfo; 2973 struct ahd_tmode_tstate *tstate; 2974 2975 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2976 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2977 devinfo.our_scsiid, 2978 devinfo.target, &tstate); 2979 pending_hscb = pending_scb->hscb; 2980 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2981 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2982 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2983 pending_hscb->control &= ~MK_MESSAGE; 2984 } 2985 ahd_sync_scb(ahd, pending_scb, 2986 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2987 pending_scb_count++; 2988 } 2989 2990 if (pending_scb_count == 0) 2991 return; 2992 2993 if (ahd_is_paused(ahd)) { 2994 paused = 1; 2995 } else { 2996 paused = 0; 2997 ahd_pause(ahd); 2998 } 2999 3000 /* 3001 * Force the sequencer to reinitialize the selection for 3002 * the command at the head of the execution queue if it 3003 * has already been setup. The negotiation changes may 3004 * effect whether we select-out with ATN. 3005 */ 3006 saved_modes = ahd_save_modes(ahd); 3007 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3008 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3009 saved_scbptr = ahd_get_scbptr(ahd); 3010 /* Ensure that the hscbs down on the card match the new information */ 3011 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 3012 struct hardware_scb *pending_hscb; 3013 u_int control; 3014 u_int scb_tag; 3015 3016 ahd_set_scbptr(ahd, i); 3017 scb_tag = i; 3018 pending_scb = ahd_lookup_scb(ahd, scb_tag); 3019 if (pending_scb == NULL) 3020 continue; 3021 3022 pending_hscb = pending_scb->hscb; 3023 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3024 control &= ~MK_MESSAGE; 3025 control |= pending_hscb->control & MK_MESSAGE; 3026 ahd_outb(ahd, SCB_CONTROL, control); 3027 } 3028 ahd_set_scbptr(ahd, saved_scbptr); 3029 ahd_restore_modes(ahd, saved_modes); 3030 3031 if (paused == 0) 3032 ahd_unpause(ahd); 3033 } 3034 3035 /**************************** Pathing Information *****************************/ 3036 static void 3037 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3038 { 3039 ahd_mode_state saved_modes; 3040 u_int saved_scsiid; 3041 role_t role; 3042 int our_id; 3043 3044 saved_modes = ahd_save_modes(ahd); 3045 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3046 3047 if (ahd_inb(ahd, SSTAT0) & TARGET) 3048 role = ROLE_TARGET; 3049 else 3050 role = ROLE_INITIATOR; 3051 3052 if (role == ROLE_TARGET 3053 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3054 /* We were selected, so pull our id from TARGIDIN */ 3055 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3056 } else if (role == ROLE_TARGET) 3057 our_id = ahd_inb(ahd, TOWNID); 3058 else 3059 our_id = ahd_inb(ahd, IOWNID); 3060 3061 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3062 ahd_compile_devinfo(devinfo, 3063 our_id, 3064 SCSIID_TARGET(ahd, saved_scsiid), 3065 ahd_inb(ahd, SAVED_LUN), 3066 SCSIID_CHANNEL(ahd, saved_scsiid), 3067 role); 3068 ahd_restore_modes(ahd, saved_modes); 3069 } 3070 3071 void 3072 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3073 { 3074 printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3075 devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3076 } 3077 3078 struct ahd_phase_table_entry* 3079 ahd_lookup_phase_entry(int phase) 3080 { 3081 struct ahd_phase_table_entry *entry; 3082 struct ahd_phase_table_entry *last_entry; 3083 3084 /* 3085 * num_phases doesn't include the default entry which 3086 * will be returned if the phase doesn't match. 3087 */ 3088 last_entry = &ahd_phase_table[num_phases]; 3089 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3090 if (phase == entry->phase) 3091 break; 3092 } 3093 return (entry); 3094 } 3095 3096 void 3097 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3098 u_int lun, char channel, role_t role) 3099 { 3100 devinfo->our_scsiid = our_id; 3101 devinfo->target = target; 3102 devinfo->lun = lun; 3103 devinfo->target_offset = target; 3104 devinfo->channel = channel; 3105 devinfo->role = role; 3106 if (channel == 'B') 3107 devinfo->target_offset += 8; 3108 devinfo->target_mask = (0x01 << devinfo->target_offset); 3109 } 3110 3111 static void 3112 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3113 struct scb *scb) 3114 { 3115 role_t role; 3116 int our_id; 3117 3118 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3119 role = ROLE_INITIATOR; 3120 if ((scb->hscb->control & TARGET_SCB) != 0) 3121 role = ROLE_TARGET; 3122 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3123 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3124 } 3125 3126 3127 /************************ Message Phase Processing ****************************/ 3128 /* 3129 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3130 * or enters the initial message out phase, we are interrupted. Fill our 3131 * outgoing message buffer with the appropriate message and beging handing 3132 * the message phase(s) manually. 3133 */ 3134 static void 3135 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3136 struct scb *scb) 3137 { 3138 /* 3139 * To facilitate adding multiple messages together, 3140 * each routine should increment the index and len 3141 * variables instead of setting them explicitly. 3142 */ 3143 ahd->msgout_index = 0; 3144 ahd->msgout_len = 0; 3145 3146 if (ahd_currently_packetized(ahd)) 3147 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3148 3149 if (ahd->send_msg_perror 3150 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3151 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3152 ahd->msgout_len++; 3153 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3154 #ifdef AHD_DEBUG 3155 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3156 printf("Setting up for Parity Error delivery\n"); 3157 #endif 3158 return; 3159 } else if (scb == NULL) { 3160 printf("%s: WARNING. No pending message for " 3161 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3162 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3163 ahd->msgout_len++; 3164 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3165 return; 3166 } 3167 3168 if ((scb->flags & SCB_DEVICE_RESET) == 0 3169 && (scb->flags & SCB_PACKETIZED) == 0 3170 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3171 u_int identify_msg; 3172 3173 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3174 if ((scb->hscb->control & DISCENB) != 0) 3175 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3176 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3177 ahd->msgout_len++; 3178 3179 if ((scb->hscb->control & TAG_ENB) != 0) { 3180 ahd->msgout_buf[ahd->msgout_index++] = 3181 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3182 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3183 ahd->msgout_len += 2; 3184 } 3185 } 3186 3187 if (scb->flags & SCB_DEVICE_RESET) { 3188 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3189 ahd->msgout_len++; 3190 ahd_print_path(ahd, scb); 3191 printf("Bus Device Reset Message Sent\n"); 3192 /* 3193 * Clear our selection hardware in advance of 3194 * the busfree. We may have an entry in the waiting 3195 * Q for this target, and we don't want to go about 3196 * selecting while we handle the busfree and blow it 3197 * away. 3198 */ 3199 ahd_outb(ahd, SCSISEQ0, 0); 3200 } else if ((scb->flags & SCB_ABORT) != 0) { 3201 3202 if ((scb->hscb->control & TAG_ENB) != 0) { 3203 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3204 } else { 3205 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3206 } 3207 ahd->msgout_len++; 3208 ahd_print_path(ahd, scb); 3209 printf("Abort%s Message Sent\n", 3210 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3211 /* 3212 * Clear our selection hardware in advance of 3213 * the busfree. We may have an entry in the waiting 3214 * Q for this target, and we don't want to go about 3215 * selecting while we handle the busfree and blow it 3216 * away. 3217 */ 3218 ahd_outb(ahd, SCSISEQ0, 0); 3219 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3220 ahd_build_transfer_msg(ahd, devinfo); 3221 /* 3222 * Clear our selection hardware in advance of potential 3223 * PPR IU status change busfree. We may have an entry in 3224 * the waiting Q for this target, and we don't want to go 3225 * about selecting while we handle the busfree and blow 3226 * it away. 3227 */ 3228 ahd_outb(ahd, SCSISEQ0, 0); 3229 } else { 3230 printf("ahd_intr: AWAITING_MSG for an SCB that " 3231 "does not have a waiting message\n"); 3232 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3233 devinfo->target_mask); 3234 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3235 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3236 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3237 scb->flags); 3238 } 3239 3240 /* 3241 * Clear the MK_MESSAGE flag from the SCB so we aren't 3242 * asked to send this message again. 3243 */ 3244 ahd_outb(ahd, SCB_CONTROL, 3245 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3246 scb->hscb->control &= ~MK_MESSAGE; 3247 ahd->msgout_index = 0; 3248 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3249 } 3250 3251 /* 3252 * Build an appropriate transfer negotiation message for the 3253 * currently active target. 3254 */ 3255 static void 3256 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3257 { 3258 /* 3259 * We need to initiate transfer negotiations. 3260 * If our current and goal settings are identical, 3261 * we want to renegotiate due to a check condition. 3262 */ 3263 struct ahd_initiator_tinfo *tinfo; 3264 struct ahd_tmode_tstate *tstate; 3265 int dowide; 3266 int dosync; 3267 int doppr; 3268 u_int period; 3269 u_int ppr_options; 3270 u_int offset; 3271 3272 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3273 devinfo->target, &tstate); 3274 /* 3275 * Filter our period based on the current connection. 3276 * If we can't perform DT transfers on this segment (not in LVD 3277 * mode for instance), then our decision to issue a PPR message 3278 * may change. 3279 */ 3280 period = tinfo->goal.period; 3281 offset = tinfo->goal.offset; 3282 ppr_options = tinfo->goal.ppr_options; 3283 /* Target initiated PPR is not allowed in the SCSI spec */ 3284 if (devinfo->role == ROLE_TARGET) 3285 ppr_options = 0; 3286 ahd_devlimited_syncrate(ahd, tinfo, &period, 3287 &ppr_options, devinfo->role); 3288 dowide = tinfo->curr.width != tinfo->goal.width; 3289 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3290 /* 3291 * Only use PPR if we have options that need it, even if the device 3292 * claims to support it. There might be an expander in the way 3293 * that doesn't. 3294 */ 3295 doppr = ppr_options != 0; 3296 3297 if (!dowide && !dosync && !doppr) { 3298 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3299 dosync = tinfo->goal.offset != 0; 3300 } 3301 3302 if (!dowide && !dosync && !doppr) { 3303 /* 3304 * Force async with a WDTR message if we have a wide bus, 3305 * or just issue an SDTR with a 0 offset. 3306 */ 3307 if ((ahd->features & AHD_WIDE) != 0) 3308 dowide = 1; 3309 else 3310 dosync = 1; 3311 3312 if (bootverbose) { 3313 ahd_print_devinfo(ahd, devinfo); 3314 printf("Ensuring async\n"); 3315 } 3316 } 3317 /* Target initiated PPR is not allowed in the SCSI spec */ 3318 if (devinfo->role == ROLE_TARGET) 3319 doppr = 0; 3320 3321 /* 3322 * Both the PPR message and SDTR message require the 3323 * goal syncrate to be limited to what the target device 3324 * is capable of handling (based on whether an LVD->SE 3325 * expander is on the bus), so combine these two cases. 3326 * Regardless, guarantee that if we are using WDTR and SDTR 3327 * messages that WDTR comes first. 3328 */ 3329 if (doppr || (dosync && !dowide)) { 3330 3331 offset = tinfo->goal.offset; 3332 ahd_validate_offset(ahd, tinfo, period, &offset, 3333 doppr ? tinfo->goal.width 3334 : tinfo->curr.width, 3335 devinfo->role); 3336 if (doppr) { 3337 ahd_construct_ppr(ahd, devinfo, period, offset, 3338 tinfo->goal.width, ppr_options); 3339 } else { 3340 ahd_construct_sdtr(ahd, devinfo, period, offset); 3341 } 3342 } else { 3343 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3344 } 3345 } 3346 3347 /* 3348 * Build a synchronous negotiation message in our message 3349 * buffer based on the input parameters. 3350 */ 3351 static void 3352 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3353 u_int period, u_int offset) 3354 { 3355 if (offset == 0) 3356 period = AHD_ASYNC_XFER_PERIOD; 3357 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3358 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3359 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3360 ahd->msgout_buf[ahd->msgout_index++] = period; 3361 ahd->msgout_buf[ahd->msgout_index++] = offset; 3362 ahd->msgout_len += 5; 3363 if (bootverbose) { 3364 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3365 ahd_name(ahd), devinfo->channel, devinfo->target, 3366 devinfo->lun, period, offset); 3367 } 3368 } 3369 3370 /* 3371 * Build a wide negotiateion message in our message 3372 * buffer based on the input parameters. 3373 */ 3374 static void 3375 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3376 u_int bus_width) 3377 { 3378 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3379 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3380 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3381 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3382 ahd->msgout_len += 4; 3383 if (bootverbose) { 3384 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3385 ahd_name(ahd), devinfo->channel, devinfo->target, 3386 devinfo->lun, bus_width); 3387 } 3388 } 3389 3390 /* 3391 * Build a parallel protocol request message in our message 3392 * buffer based on the input parameters. 3393 */ 3394 static void 3395 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3396 u_int period, u_int offset, u_int bus_width, 3397 u_int ppr_options) 3398 { 3399 /* 3400 * Always request precompensation from 3401 * the other target if we are running 3402 * at paced syncrates. 3403 */ 3404 if (period <= AHD_SYNCRATE_PACED) 3405 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3406 if (offset == 0) 3407 period = AHD_ASYNC_XFER_PERIOD; 3408 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3409 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3410 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3411 ahd->msgout_buf[ahd->msgout_index++] = period; 3412 ahd->msgout_buf[ahd->msgout_index++] = 0; 3413 ahd->msgout_buf[ahd->msgout_index++] = offset; 3414 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3415 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3416 ahd->msgout_len += 8; 3417 if (bootverbose) { 3418 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3419 "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3420 devinfo->channel, devinfo->target, devinfo->lun, 3421 bus_width, period, offset, ppr_options); 3422 } 3423 } 3424 3425 /* 3426 * Clear any active message state. 3427 */ 3428 static void 3429 ahd_clear_msg_state(struct ahd_softc *ahd) 3430 { 3431 ahd_mode_state saved_modes; 3432 3433 saved_modes = ahd_save_modes(ahd); 3434 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3435 ahd->send_msg_perror = 0; 3436 ahd->msg_flags = MSG_FLAG_NONE; 3437 ahd->msgout_len = 0; 3438 ahd->msgin_index = 0; 3439 ahd->msg_type = MSG_TYPE_NONE; 3440 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3441 /* 3442 * The target didn't care to respond to our 3443 * message request, so clear ATN. 3444 */ 3445 ahd_outb(ahd, CLRSINT1, CLRATNO); 3446 } 3447 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3448 ahd_outb(ahd, SEQ_FLAGS2, 3449 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3450 ahd_restore_modes(ahd, saved_modes); 3451 } 3452 3453 /* 3454 * Manual message loop handler. 3455 */ 3456 static void 3457 ahd_handle_message_phase(struct ahd_softc *ahd) 3458 { 3459 struct ahd_devinfo devinfo; 3460 u_int bus_phase; 3461 int end_session; 3462 3463 ahd_fetch_devinfo(ahd, &devinfo); 3464 end_session = FALSE; 3465 bus_phase = ahd_inb(ahd, LASTPHASE); 3466 3467 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3468 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3469 ahd_outb(ahd, LQCTL2, LQIRETRY); 3470 } 3471 reswitch: 3472 switch (ahd->msg_type) { 3473 case MSG_TYPE_INITIATOR_MSGOUT: 3474 { 3475 int lastbyte; 3476 int phasemis; 3477 int msgdone; 3478 3479 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3480 panic("HOST_MSG_LOOP interrupt with no active message"); 3481 3482 #ifdef AHD_DEBUG 3483 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3484 ahd_print_devinfo(ahd, &devinfo); 3485 printf("INITIATOR_MSG_OUT"); 3486 } 3487 #endif 3488 phasemis = bus_phase != P_MESGOUT; 3489 if (phasemis) { 3490 #ifdef AHD_DEBUG 3491 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3492 printf(" PHASEMIS %s\n", 3493 ahd_lookup_phase_entry(bus_phase) 3494 ->phasemsg); 3495 } 3496 #endif 3497 if (bus_phase == P_MESGIN) { 3498 /* 3499 * Change gears and see if 3500 * this messages is of interest to 3501 * us or should be passed back to 3502 * the sequencer. 3503 */ 3504 ahd_outb(ahd, CLRSINT1, CLRATNO); 3505 ahd->send_msg_perror = 0; 3506 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3507 ahd->msgin_index = 0; 3508 goto reswitch; 3509 } 3510 end_session = TRUE; 3511 break; 3512 } 3513 3514 if (ahd->send_msg_perror) { 3515 ahd_outb(ahd, CLRSINT1, CLRATNO); 3516 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3517 #ifdef AHD_DEBUG 3518 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3519 printf(" byte 0x%x\n", ahd->send_msg_perror); 3520 #endif 3521 /* 3522 * If we are notifying the target of a CRC error 3523 * during packetized operations, the target is 3524 * within its rights to acknowledge our message 3525 * with a busfree. 3526 */ 3527 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3528 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3529 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3530 3531 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3532 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3533 break; 3534 } 3535 3536 msgdone = ahd->msgout_index == ahd->msgout_len; 3537 if (msgdone) { 3538 /* 3539 * The target has requested a retry. 3540 * Re-assert ATN, reset our message index to 3541 * 0, and try again. 3542 */ 3543 ahd->msgout_index = 0; 3544 ahd_assert_atn(ahd); 3545 } 3546 3547 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3548 if (lastbyte) { 3549 /* Last byte is signified by dropping ATN */ 3550 ahd_outb(ahd, CLRSINT1, CLRATNO); 3551 } 3552 3553 /* 3554 * Clear our interrupt status and present 3555 * the next byte on the bus. 3556 */ 3557 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3558 #ifdef AHD_DEBUG 3559 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3560 printf(" byte 0x%x\n", 3561 ahd->msgout_buf[ahd->msgout_index]); 3562 #endif 3563 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3564 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3565 break; 3566 } 3567 case MSG_TYPE_INITIATOR_MSGIN: 3568 { 3569 int phasemis; 3570 int message_done; 3571 3572 #ifdef AHD_DEBUG 3573 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3574 ahd_print_devinfo(ahd, &devinfo); 3575 printf("INITIATOR_MSG_IN"); 3576 } 3577 #endif 3578 phasemis = bus_phase != P_MESGIN; 3579 if (phasemis) { 3580 #ifdef AHD_DEBUG 3581 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3582 printf(" PHASEMIS %s\n", 3583 ahd_lookup_phase_entry(bus_phase) 3584 ->phasemsg); 3585 } 3586 #endif 3587 ahd->msgin_index = 0; 3588 if (bus_phase == P_MESGOUT 3589 && (ahd->send_msg_perror != 0 3590 || (ahd->msgout_len != 0 3591 && ahd->msgout_index == 0))) { 3592 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3593 goto reswitch; 3594 } 3595 end_session = TRUE; 3596 break; 3597 } 3598 3599 /* Pull the byte in without acking it */ 3600 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3601 #ifdef AHD_DEBUG 3602 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3603 printf(" byte 0x%x\n", 3604 ahd->msgin_buf[ahd->msgin_index]); 3605 #endif 3606 3607 message_done = ahd_parse_msg(ahd, &devinfo); 3608 3609 if (message_done) { 3610 /* 3611 * Clear our incoming message buffer in case there 3612 * is another message following this one. 3613 */ 3614 ahd->msgin_index = 0; 3615 3616 /* 3617 * If this message illicited a response, 3618 * assert ATN so the target takes us to the 3619 * message out phase. 3620 */ 3621 if (ahd->msgout_len != 0) { 3622 #ifdef AHD_DEBUG 3623 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3624 ahd_print_devinfo(ahd, &devinfo); 3625 printf("Asserting ATN for response\n"); 3626 } 3627 #endif 3628 ahd_assert_atn(ahd); 3629 } 3630 } else 3631 ahd->msgin_index++; 3632 3633 if (message_done == MSGLOOP_TERMINATED) { 3634 end_session = TRUE; 3635 } else { 3636 /* Ack the byte */ 3637 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3638 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3639 } 3640 break; 3641 } 3642 case MSG_TYPE_TARGET_MSGIN: 3643 { 3644 int msgdone; 3645 int msgout_request; 3646 3647 /* 3648 * By default, the message loop will continue. 3649 */ 3650 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3651 3652 if (ahd->msgout_len == 0) 3653 panic("Target MSGIN with no active message"); 3654 3655 /* 3656 * If we interrupted a mesgout session, the initiator 3657 * will not know this until our first REQ. So, we 3658 * only honor mesgout requests after we've sent our 3659 * first byte. 3660 */ 3661 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3662 && ahd->msgout_index > 0) 3663 msgout_request = TRUE; 3664 else 3665 msgout_request = FALSE; 3666 3667 if (msgout_request) { 3668 3669 /* 3670 * Change gears and see if 3671 * this messages is of interest to 3672 * us or should be passed back to 3673 * the sequencer. 3674 */ 3675 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3676 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3677 ahd->msgin_index = 0; 3678 /* Dummy read to REQ for first byte */ 3679 ahd_inb(ahd, SCSIDAT); 3680 ahd_outb(ahd, SXFRCTL0, 3681 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3682 break; 3683 } 3684 3685 msgdone = ahd->msgout_index == ahd->msgout_len; 3686 if (msgdone) { 3687 ahd_outb(ahd, SXFRCTL0, 3688 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3689 end_session = TRUE; 3690 break; 3691 } 3692 3693 /* 3694 * Present the next byte on the bus. 3695 */ 3696 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3697 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3698 break; 3699 } 3700 case MSG_TYPE_TARGET_MSGOUT: 3701 { 3702 int lastbyte; 3703 int msgdone; 3704 3705 /* 3706 * By default, the message loop will continue. 3707 */ 3708 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3709 3710 /* 3711 * The initiator signals that this is 3712 * the last byte by dropping ATN. 3713 */ 3714 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3715 3716 /* 3717 * Read the latched byte, but turn off SPIOEN first 3718 * so that we don't inadvertently cause a REQ for the 3719 * next byte. 3720 */ 3721 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3722 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3723 msgdone = ahd_parse_msg(ahd, &devinfo); 3724 if (msgdone == MSGLOOP_TERMINATED) { 3725 /* 3726 * The message is *really* done in that it caused 3727 * us to go to bus free. The sequencer has already 3728 * been reset at this point, so pull the ejection 3729 * handle. 3730 */ 3731 return; 3732 } 3733 3734 ahd->msgin_index++; 3735 3736 /* 3737 * XXX Read spec about initiator dropping ATN too soon 3738 * and use msgdone to detect it. 3739 */ 3740 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3741 ahd->msgin_index = 0; 3742 3743 /* 3744 * If this message illicited a response, transition 3745 * to the Message in phase and send it. 3746 */ 3747 if (ahd->msgout_len != 0) { 3748 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3749 ahd_outb(ahd, SXFRCTL0, 3750 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3751 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3752 ahd->msgin_index = 0; 3753 break; 3754 } 3755 } 3756 3757 if (lastbyte) 3758 end_session = TRUE; 3759 else { 3760 /* Ask for the next byte. */ 3761 ahd_outb(ahd, SXFRCTL0, 3762 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3763 } 3764 3765 break; 3766 } 3767 default: 3768 panic("Unknown REQINIT message type"); 3769 } 3770 3771 if (end_session) { 3772 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3773 printf("%s: Returning to Idle Loop\n", 3774 ahd_name(ahd)); 3775 ahd_clear_msg_state(ahd); 3776 3777 /* 3778 * Perform the equivalent of a clear_target_state. 3779 */ 3780 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3781 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 3782 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3783 } else { 3784 ahd_clear_msg_state(ahd); 3785 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3786 } 3787 } 3788 } 3789 3790 /* 3791 * See if we sent a particular extended message to the target. 3792 * If "full" is true, return true only if the target saw the full 3793 * message. If "full" is false, return true if the target saw at 3794 * least the first byte of the message. 3795 */ 3796 static int 3797 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3798 { 3799 int found; 3800 u_int index; 3801 3802 found = FALSE; 3803 index = 0; 3804 3805 while (index < ahd->msgout_len) { 3806 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3807 u_int end_index; 3808 3809 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3810 if (ahd->msgout_buf[index+2] == msgval 3811 && type == AHDMSG_EXT) { 3812 3813 if (full) { 3814 if (ahd->msgout_index > end_index) 3815 found = TRUE; 3816 } else if (ahd->msgout_index > index) 3817 found = TRUE; 3818 } 3819 index = end_index; 3820 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3821 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3822 3823 /* Skip tag type and tag id or residue param*/ 3824 index += 2; 3825 } else { 3826 /* Single byte message */ 3827 if (type == AHDMSG_1B 3828 && ahd->msgout_index > index 3829 && (ahd->msgout_buf[index] == msgval 3830 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3831 && msgval == MSG_IDENTIFYFLAG))) 3832 found = TRUE; 3833 index++; 3834 } 3835 3836 if (found) 3837 break; 3838 } 3839 return (found); 3840 } 3841 3842 /* 3843 * Wait for a complete incoming message, parse it, and respond accordingly. 3844 */ 3845 static int 3846 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3847 { 3848 struct ahd_initiator_tinfo *tinfo; 3849 struct ahd_tmode_tstate *tstate; 3850 int reject; 3851 int done; 3852 int response; 3853 3854 done = MSGLOOP_IN_PROG; 3855 response = FALSE; 3856 reject = FALSE; 3857 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3858 devinfo->target, &tstate); 3859 3860 /* 3861 * Parse as much of the message as is available, 3862 * rejecting it if we don't support it. When 3863 * the entire message is available and has been 3864 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3865 * that we have parsed an entire message. 3866 * 3867 * In the case of extended messages, we accept the length 3868 * byte outright and perform more checking once we know the 3869 * extended message type. 3870 */ 3871 switch (ahd->msgin_buf[0]) { 3872 case MSG_DISCONNECT: 3873 case MSG_SAVEDATAPOINTER: 3874 case MSG_CMDCOMPLETE: 3875 case MSG_RESTOREPOINTERS: 3876 case MSG_IGN_WIDE_RESIDUE: 3877 /* 3878 * End our message loop as these are messages 3879 * the sequencer handles on its own. 3880 */ 3881 done = MSGLOOP_TERMINATED; 3882 break; 3883 case MSG_MESSAGE_REJECT: 3884 response = ahd_handle_msg_reject(ahd, devinfo); 3885 /* FALLTHROUGH */ 3886 case MSG_NOOP: 3887 done = MSGLOOP_MSGCOMPLETE; 3888 break; 3889 case MSG_EXTENDED: 3890 { 3891 /* Wait for enough of the message to begin validation */ 3892 if (ahd->msgin_index < 2) 3893 break; 3894 switch (ahd->msgin_buf[2]) { 3895 case MSG_EXT_SDTR: 3896 { 3897 u_int period; 3898 u_int ppr_options; 3899 u_int offset; 3900 u_int saved_offset; 3901 3902 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3903 reject = TRUE; 3904 break; 3905 } 3906 3907 /* 3908 * Wait until we have both args before validating 3909 * and acting on this message. 3910 * 3911 * Add one to MSG_EXT_SDTR_LEN to account for 3912 * the extended message preamble. 3913 */ 3914 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3915 break; 3916 3917 period = ahd->msgin_buf[3]; 3918 ppr_options = 0; 3919 saved_offset = offset = ahd->msgin_buf[4]; 3920 ahd_devlimited_syncrate(ahd, tinfo, &period, 3921 &ppr_options, devinfo->role); 3922 ahd_validate_offset(ahd, tinfo, period, &offset, 3923 tinfo->curr.width, devinfo->role); 3924 if (bootverbose) { 3925 printf("(%s:%c:%d:%d): Received " 3926 "SDTR period %x, offset %x\n\t" 3927 "Filtered to period %x, offset %x\n", 3928 ahd_name(ahd), devinfo->channel, 3929 devinfo->target, devinfo->lun, 3930 ahd->msgin_buf[3], saved_offset, 3931 period, offset); 3932 } 3933 ahd_set_syncrate(ahd, devinfo, period, 3934 offset, ppr_options, 3935 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3936 /*paused*/TRUE); 3937 3938 /* 3939 * See if we initiated Sync Negotiation 3940 * and didn't have to fall down to async 3941 * transfers. 3942 */ 3943 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3944 /* We started it */ 3945 if (saved_offset != offset) { 3946 /* Went too low - force async */ 3947 reject = TRUE; 3948 } 3949 } else { 3950 /* 3951 * Send our own SDTR in reply 3952 */ 3953 if (bootverbose 3954 && devinfo->role == ROLE_INITIATOR) { 3955 printf("(%s:%c:%d:%d): Target " 3956 "Initiated SDTR\n", 3957 ahd_name(ahd), devinfo->channel, 3958 devinfo->target, devinfo->lun); 3959 } 3960 ahd->msgout_index = 0; 3961 ahd->msgout_len = 0; 3962 ahd_construct_sdtr(ahd, devinfo, 3963 period, offset); 3964 ahd->msgout_index = 0; 3965 response = TRUE; 3966 } 3967 done = MSGLOOP_MSGCOMPLETE; 3968 break; 3969 } 3970 case MSG_EXT_WDTR: 3971 { 3972 u_int bus_width; 3973 u_int saved_width; 3974 u_int sending_reply; 3975 3976 sending_reply = FALSE; 3977 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3978 reject = TRUE; 3979 break; 3980 } 3981 3982 /* 3983 * Wait until we have our arg before validating 3984 * and acting on this message. 3985 * 3986 * Add one to MSG_EXT_WDTR_LEN to account for 3987 * the extended message preamble. 3988 */ 3989 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3990 break; 3991 3992 bus_width = ahd->msgin_buf[3]; 3993 saved_width = bus_width; 3994 ahd_validate_width(ahd, tinfo, &bus_width, 3995 devinfo->role); 3996 if (bootverbose) { 3997 printf("(%s:%c:%d:%d): Received WDTR " 3998 "%x filtered to %x\n", 3999 ahd_name(ahd), devinfo->channel, 4000 devinfo->target, devinfo->lun, 4001 saved_width, bus_width); 4002 } 4003 4004 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4005 /* 4006 * Don't send a WDTR back to the 4007 * target, since we asked first. 4008 * If the width went higher than our 4009 * request, reject it. 4010 */ 4011 if (saved_width > bus_width) { 4012 reject = TRUE; 4013 printf("(%s:%c:%d:%d): requested %dBit " 4014 "transfers. Rejecting...\n", 4015 ahd_name(ahd), devinfo->channel, 4016 devinfo->target, devinfo->lun, 4017 8 * (0x01 << bus_width)); 4018 bus_width = 0; 4019 } 4020 } else { 4021 /* 4022 * Send our own WDTR in reply 4023 */ 4024 if (bootverbose 4025 && devinfo->role == ROLE_INITIATOR) { 4026 printf("(%s:%c:%d:%d): Target " 4027 "Initiated WDTR\n", 4028 ahd_name(ahd), devinfo->channel, 4029 devinfo->target, devinfo->lun); 4030 } 4031 ahd->msgout_index = 0; 4032 ahd->msgout_len = 0; 4033 ahd_construct_wdtr(ahd, devinfo, bus_width); 4034 ahd->msgout_index = 0; 4035 response = TRUE; 4036 sending_reply = TRUE; 4037 } 4038 /* 4039 * After a wide message, we are async, but 4040 * some devices don't seem to honor this portion 4041 * of the spec. Force a renegotiation of the 4042 * sync component of our transfer agreement even 4043 * if our goal is async. By updating our width 4044 * after forcing the negotiation, we avoid 4045 * renegotiating for width. 4046 */ 4047 ahd_update_neg_request(ahd, devinfo, tstate, 4048 tinfo, AHD_NEG_ALWAYS); 4049 ahd_set_width(ahd, devinfo, bus_width, 4050 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4051 /*paused*/TRUE); 4052 if (sending_reply == FALSE && reject == FALSE) { 4053 4054 /* 4055 * We will always have an SDTR to send. 4056 */ 4057 ahd->msgout_index = 0; 4058 ahd->msgout_len = 0; 4059 ahd_build_transfer_msg(ahd, devinfo); 4060 ahd->msgout_index = 0; 4061 response = TRUE; 4062 } 4063 done = MSGLOOP_MSGCOMPLETE; 4064 break; 4065 } 4066 case MSG_EXT_PPR: 4067 { 4068 u_int period; 4069 u_int offset; 4070 u_int bus_width; 4071 u_int ppr_options; 4072 u_int saved_width; 4073 u_int saved_offset; 4074 u_int saved_ppr_options; 4075 4076 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4077 reject = TRUE; 4078 break; 4079 } 4080 4081 /* 4082 * Wait until we have all args before validating 4083 * and acting on this message. 4084 * 4085 * Add one to MSG_EXT_PPR_LEN to account for 4086 * the extended message preamble. 4087 */ 4088 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4089 break; 4090 4091 period = ahd->msgin_buf[3]; 4092 offset = ahd->msgin_buf[5]; 4093 bus_width = ahd->msgin_buf[6]; 4094 saved_width = bus_width; 4095 ppr_options = ahd->msgin_buf[7]; 4096 /* 4097 * According to the spec, a DT only 4098 * period factor with no DT option 4099 * set implies async. 4100 */ 4101 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4102 && period <= 9) 4103 offset = 0; 4104 saved_ppr_options = ppr_options; 4105 saved_offset = offset; 4106 4107 /* 4108 * Transfer options are only available if we 4109 * are negotiating wide. 4110 */ 4111 if (bus_width == 0) 4112 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4113 4114 ahd_validate_width(ahd, tinfo, &bus_width, 4115 devinfo->role); 4116 ahd_devlimited_syncrate(ahd, tinfo, &period, 4117 &ppr_options, devinfo->role); 4118 ahd_validate_offset(ahd, tinfo, period, &offset, 4119 bus_width, devinfo->role); 4120 4121 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4122 /* 4123 * If we are unable to do any of the 4124 * requested options (we went too low), 4125 * then we'll have to reject the message. 4126 */ 4127 if (saved_width > bus_width 4128 || saved_offset != offset 4129 || saved_ppr_options != ppr_options) { 4130 reject = TRUE; 4131 period = 0; 4132 offset = 0; 4133 bus_width = 0; 4134 ppr_options = 0; 4135 } 4136 } else { 4137 if (devinfo->role != ROLE_TARGET) 4138 printf("(%s:%c:%d:%d): Target " 4139 "Initiated PPR\n", 4140 ahd_name(ahd), devinfo->channel, 4141 devinfo->target, devinfo->lun); 4142 else 4143 printf("(%s:%c:%d:%d): Initiator " 4144 "Initiated PPR\n", 4145 ahd_name(ahd), devinfo->channel, 4146 devinfo->target, devinfo->lun); 4147 ahd->msgout_index = 0; 4148 ahd->msgout_len = 0; 4149 ahd_construct_ppr(ahd, devinfo, period, offset, 4150 bus_width, ppr_options); 4151 ahd->msgout_index = 0; 4152 response = TRUE; 4153 } 4154 if (bootverbose) { 4155 printf("(%s:%c:%d:%d): Received PPR width %x, " 4156 "period %x, offset %x,options %x\n" 4157 "\tFiltered to width %x, period %x, " 4158 "offset %x, options %x\n", 4159 ahd_name(ahd), devinfo->channel, 4160 devinfo->target, devinfo->lun, 4161 saved_width, ahd->msgin_buf[3], 4162 saved_offset, saved_ppr_options, 4163 bus_width, period, offset, ppr_options); 4164 } 4165 ahd_set_width(ahd, devinfo, bus_width, 4166 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4167 /*paused*/TRUE); 4168 ahd_set_syncrate(ahd, devinfo, period, 4169 offset, ppr_options, 4170 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4171 /*paused*/TRUE); 4172 4173 done = MSGLOOP_MSGCOMPLETE; 4174 break; 4175 } 4176 default: 4177 /* Unknown extended message. Reject it. */ 4178 reject = TRUE; 4179 break; 4180 } 4181 break; 4182 } 4183 #ifdef AHD_TARGET_MODE 4184 case MSG_BUS_DEV_RESET: 4185 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4186 CAM_BDR_SENT, 4187 "Bus Device Reset Received", 4188 /*verbose_level*/0); 4189 ahd_restart(ahd); 4190 done = MSGLOOP_TERMINATED; 4191 break; 4192 case MSG_ABORT_TAG: 4193 case MSG_ABORT: 4194 case MSG_CLEAR_QUEUE: 4195 { 4196 int tag; 4197 4198 /* Target mode messages */ 4199 if (devinfo->role != ROLE_TARGET) { 4200 reject = TRUE; 4201 break; 4202 } 4203 tag = SCB_LIST_NULL; 4204 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4205 tag = ahd_inb(ahd, INITIATOR_TAG); 4206 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4207 devinfo->lun, tag, ROLE_TARGET, 4208 CAM_REQ_ABORTED); 4209 4210 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4211 if (tstate != NULL) { 4212 struct ahd_tmode_lstate* lstate; 4213 4214 lstate = tstate->enabled_luns[devinfo->lun]; 4215 if (lstate != NULL) { 4216 ahd_queue_lstate_event(ahd, lstate, 4217 devinfo->our_scsiid, 4218 ahd->msgin_buf[0], 4219 /*arg*/tag); 4220 ahd_send_lstate_events(ahd, lstate); 4221 } 4222 } 4223 ahd_restart(ahd); 4224 done = MSGLOOP_TERMINATED; 4225 break; 4226 } 4227 #endif 4228 case MSG_QAS_REQUEST: 4229 #ifdef AHD_DEBUG 4230 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4231 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4232 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4233 #endif 4234 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4235 /* FALLTHROUGH */ 4236 case MSG_TERM_IO_PROC: 4237 default: 4238 reject = TRUE; 4239 break; 4240 } 4241 4242 if (reject) { 4243 /* 4244 * Setup to reject the message. 4245 */ 4246 ahd->msgout_index = 0; 4247 ahd->msgout_len = 1; 4248 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4249 done = MSGLOOP_MSGCOMPLETE; 4250 response = TRUE; 4251 } 4252 4253 if (done != MSGLOOP_IN_PROG && !response) 4254 /* Clear the outgoing message buffer */ 4255 ahd->msgout_len = 0; 4256 4257 return (done); 4258 } 4259 4260 /* 4261 * Process a message reject message. 4262 */ 4263 static int 4264 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4265 { 4266 /* 4267 * What we care about here is if we had an 4268 * outstanding SDTR or WDTR message for this 4269 * target. If we did, this is a signal that 4270 * the target is refusing negotiation. 4271 */ 4272 struct scb *scb; 4273 struct ahd_initiator_tinfo *tinfo; 4274 struct ahd_tmode_tstate *tstate; 4275 u_int scb_index; 4276 u_int last_msg; 4277 int response = 0; 4278 4279 scb_index = ahd_get_scbptr(ahd); 4280 scb = ahd_lookup_scb(ahd, scb_index); 4281 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4282 devinfo->our_scsiid, 4283 devinfo->target, &tstate); 4284 /* Might be necessary */ 4285 last_msg = ahd_inb(ahd, LAST_MSG); 4286 4287 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4288 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4289 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4290 /* 4291 * Target may not like our SPI-4 PPR Options. 4292 * Attempt to negotiate 80MHz which will turn 4293 * off these options. 4294 */ 4295 if (bootverbose) { 4296 printf("(%s:%c:%d:%d): PPR Rejected. " 4297 "Trying simple U160 PPR\n", 4298 ahd_name(ahd), devinfo->channel, 4299 devinfo->target, devinfo->lun); 4300 } 4301 tinfo->goal.period = AHD_SYNCRATE_DT; 4302 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4303 | MSG_EXT_PPR_QAS_REQ 4304 | MSG_EXT_PPR_DT_REQ; 4305 } else { 4306 /* 4307 * Target does not support the PPR message. 4308 * Attempt to negotiate SPI-2 style. 4309 */ 4310 if (bootverbose) { 4311 printf("(%s:%c:%d:%d): PPR Rejected. " 4312 "Trying WDTR/SDTR\n", 4313 ahd_name(ahd), devinfo->channel, 4314 devinfo->target, devinfo->lun); 4315 } 4316 tinfo->goal.ppr_options = 0; 4317 tinfo->curr.transport_version = 2; 4318 tinfo->goal.transport_version = 2; 4319 } 4320 ahd->msgout_index = 0; 4321 ahd->msgout_len = 0; 4322 ahd_build_transfer_msg(ahd, devinfo); 4323 ahd->msgout_index = 0; 4324 response = 1; 4325 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4326 4327 /* note 8bit xfers */ 4328 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4329 "8bit transfers\n", ahd_name(ahd), 4330 devinfo->channel, devinfo->target, devinfo->lun); 4331 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4332 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4333 /*paused*/TRUE); 4334 /* 4335 * No need to clear the sync rate. If the target 4336 * did not accept the command, our syncrate is 4337 * unaffected. If the target started the negotiation, 4338 * but rejected our response, we already cleared the 4339 * sync rate before sending our WDTR. 4340 */ 4341 if (tinfo->goal.offset != tinfo->curr.offset) { 4342 4343 /* Start the sync negotiation */ 4344 ahd->msgout_index = 0; 4345 ahd->msgout_len = 0; 4346 ahd_build_transfer_msg(ahd, devinfo); 4347 ahd->msgout_index = 0; 4348 response = 1; 4349 } 4350 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4351 /* note asynch xfers and clear flag */ 4352 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4353 /*offset*/0, /*ppr_options*/0, 4354 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4355 /*paused*/TRUE); 4356 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4357 "Using asynchronous transfers\n", 4358 ahd_name(ahd), devinfo->channel, 4359 devinfo->target, devinfo->lun); 4360 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4361 int tag_type; 4362 int mask; 4363 4364 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4365 4366 if (tag_type == MSG_SIMPLE_TASK) { 4367 printf("(%s:%c:%d:%d): refuses tagged commands. " 4368 "Performing non-tagged I/O\n", ahd_name(ahd), 4369 devinfo->channel, devinfo->target, devinfo->lun); 4370 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4371 mask = ~0x23; 4372 } else { 4373 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4374 "Performing simple queue tagged I/O only\n", 4375 ahd_name(ahd), devinfo->channel, devinfo->target, 4376 devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4377 ? "ordered" : "head of queue"); 4378 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4379 mask = ~0x03; 4380 } 4381 4382 /* 4383 * Resend the identify for this CCB as the target 4384 * may believe that the selection is invalid otherwise. 4385 */ 4386 ahd_outb(ahd, SCB_CONTROL, 4387 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4388 scb->hscb->control &= mask; 4389 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4390 /*type*/MSG_SIMPLE_TASK); 4391 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4392 ahd_assert_atn(ahd); 4393 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4394 SCB_GET_TAG(scb)); 4395 4396 /* 4397 * Requeue all tagged commands for this target 4398 * currently in our posession so they can be 4399 * converted to untagged commands. 4400 */ 4401 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4402 SCB_GET_CHANNEL(ahd, scb), 4403 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4404 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4405 SEARCH_COMPLETE); 4406 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4407 /* 4408 * Most likely the device believes that we had 4409 * previously negotiated packetized. 4410 */ 4411 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4412 | MSG_FLAG_IU_REQ_CHANGED; 4413 4414 ahd_force_renegotiation(ahd, devinfo); 4415 ahd->msgout_index = 0; 4416 ahd->msgout_len = 0; 4417 ahd_build_transfer_msg(ahd, devinfo); 4418 ahd->msgout_index = 0; 4419 response = 1; 4420 } else { 4421 /* 4422 * Otherwise, we ignore it. 4423 */ 4424 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4425 ahd_name(ahd), devinfo->channel, devinfo->target, 4426 last_msg); 4427 } 4428 return (response); 4429 } 4430 4431 /* 4432 * Process an ignore wide residue message. 4433 */ 4434 static void 4435 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4436 { 4437 u_int scb_index; 4438 struct scb *scb; 4439 4440 printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4441 4442 scb_index = ahd_get_scbptr(ahd); 4443 scb = ahd_lookup_scb(ahd, scb_index); 4444 /* 4445 * XXX Actually check data direction in the sequencer? 4446 * Perhaps add datadir to some spare bits in the hscb? 4447 */ 4448 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4449 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4450 /* 4451 * Ignore the message if we haven't 4452 * seen an appropriate data phase yet. 4453 */ 4454 } else { 4455 /* 4456 * If the residual occurred on the last 4457 * transfer and the transfer request was 4458 * expected to end on an odd count, do 4459 * nothing. Otherwise, subtract a byte 4460 * and update the residual count accordingly. 4461 */ 4462 uint32_t sgptr; 4463 4464 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4465 if ((sgptr & SG_LIST_NULL) != 0 4466 && (ahd_inb(ahd, SCB_TASK_ATTRIBUTE) & SCB_XFERLEN_ODD) != 0) { 4467 /* 4468 * If the residual occurred on the last 4469 * transfer and the transfer request was 4470 * expected to end on an odd count, do 4471 * nothing. 4472 */ 4473 } else { 4474 uint32_t data_cnt; 4475 uint64_t data_addr; 4476 uint32_t sglen; 4477 4478 /* Pull in the rest of the sgptr */ 4479 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4480 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4481 if ((sgptr & SG_LIST_NULL) != 0) { 4482 /* 4483 * The residual data count is not updated 4484 * for the command run to completion case. 4485 * Explcitly zero the count. 4486 */ 4487 data_cnt &= ~AHD_SG_LEN_MASK; 4488 } 4489 data_addr = ahd_inq(ahd, SHADDR); 4490 data_cnt += 1; 4491 data_addr -= 1; 4492 sgptr &= SG_PTR_MASK; 4493 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4494 struct ahd_dma64_seg *sg; 4495 4496 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4497 4498 /* 4499 * The residual sg ptr points to the next S/G 4500 * to load so we must go back one. 4501 */ 4502 sg--; 4503 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4504 if (sg != scb->sg_list 4505 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4506 4507 sg--; 4508 sglen = ahd_le32toh(sg->len); 4509 /* 4510 * Preserve High Address and SG_LIST 4511 * bits while setting the count to 1. 4512 */ 4513 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4514 data_addr = ahd_le64toh(sg->addr) 4515 + (sglen & AHD_SG_LEN_MASK) 4516 - 1; 4517 4518 /* 4519 * Increment sg so it points to the 4520 * "next" sg. 4521 */ 4522 sg++; 4523 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4524 sg); 4525 } 4526 } else { 4527 struct ahd_dma_seg *sg; 4528 4529 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4530 4531 /* 4532 * The residual sg ptr points to the next S/G 4533 * to load so we must go back one. 4534 */ 4535 sg--; 4536 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4537 if (sg != scb->sg_list 4538 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4539 4540 sg--; 4541 sglen = ahd_le32toh(sg->len); 4542 /* 4543 * Preserve High Address and SG_LIST 4544 * bits while setting the count to 1. 4545 */ 4546 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4547 data_addr = ahd_le32toh(sg->addr) 4548 + (sglen & AHD_SG_LEN_MASK) 4549 - 1; 4550 4551 /* 4552 * Increment sg so it points to the 4553 * "next" sg. 4554 */ 4555 sg++; 4556 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4557 sg); 4558 } 4559 } 4560 /* 4561 * Toggle the "oddness" of the transfer length 4562 * to handle this mid-transfer ignore wide 4563 * residue. This ensures that the oddness is 4564 * correct for subsequent data transfers. 4565 */ 4566 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4567 ahd_inb(ahd, SCB_TASK_ATTRIBUTE) ^ SCB_XFERLEN_ODD); 4568 4569 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4570 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4571 /* 4572 * The FIFO's pointers will be updated if/when the 4573 * sequencer re-enters a data phase. 4574 */ 4575 } 4576 } 4577 } 4578 4579 4580 /* 4581 * Reinitialize the data pointers for the active transfer 4582 * based on its current residual. 4583 */ 4584 static void 4585 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4586 { 4587 struct scb *scb; 4588 ahd_mode_state saved_modes; 4589 u_int scb_index; 4590 u_int wait; 4591 uint32_t sgptr; 4592 uint32_t resid; 4593 uint64_t dataptr; 4594 4595 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4596 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4597 4598 scb_index = ahd_get_scbptr(ahd); 4599 scb = ahd_lookup_scb(ahd, scb_index); 4600 4601 /* 4602 * Release and reacquire the FIFO so we 4603 * have a clean slate. 4604 */ 4605 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4606 wait = 1000; 4607 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 4608 ahd_delay(100); 4609 if (wait == 0) { 4610 ahd_print_path(ahd, scb); 4611 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4612 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4613 } 4614 saved_modes = ahd_save_modes(ahd); 4615 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4616 ahd_outb(ahd, DFFSTAT, 4617 ahd_inb(ahd, DFFSTAT) 4618 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4619 4620 /* 4621 * Determine initial values for data_addr and data_cnt 4622 * for resuming the data phase. 4623 */ 4624 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4625 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4626 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4627 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4628 sgptr &= SG_PTR_MASK; 4629 4630 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4631 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4632 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4633 4634 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4635 struct ahd_dma64_seg *sg; 4636 4637 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4638 4639 /* The residual sg_ptr always points to the next sg */ 4640 sg--; 4641 4642 dataptr = ahd_le64toh(sg->addr) 4643 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4644 - resid; 4645 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4646 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4647 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4648 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4649 } else { 4650 struct ahd_dma_seg *sg; 4651 4652 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4653 4654 /* The residual sg_ptr always points to the next sg */ 4655 sg--; 4656 4657 dataptr = ahd_le32toh(sg->addr) 4658 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4659 - resid; 4660 ahd_outb(ahd, HADDR + 4, 4661 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4662 } 4663 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4664 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4665 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4666 ahd_outb(ahd, HADDR, dataptr); 4667 ahd_outb(ahd, HCNT + 2, resid >> 16); 4668 ahd_outb(ahd, HCNT + 1, resid >> 8); 4669 ahd_outb(ahd, HCNT, resid); 4670 } 4671 4672 /* 4673 * Handle the effects of issuing a bus device reset message. 4674 */ 4675 static void 4676 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4677 u_int lun, cam_status status, char *message, 4678 int verbose_level) 4679 { 4680 #ifdef AHD_TARGET_MODE 4681 struct ahd_tmode_tstate* tstate; 4682 #endif 4683 int found; 4684 4685 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4686 lun, SCB_LIST_NULL, devinfo->role, 4687 status); 4688 4689 #ifdef AHD_TARGET_MODE 4690 /* 4691 * Send an immediate notify ccb to all target mord peripheral 4692 * drivers affected by this action. 4693 */ 4694 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4695 if (tstate != NULL) { 4696 u_int cur_lun; 4697 u_int max_lun; 4698 4699 if (lun != CAM_LUN_WILDCARD) { 4700 cur_lun = 0; 4701 max_lun = AHD_NUM_LUNS - 1; 4702 } else { 4703 cur_lun = lun; 4704 max_lun = lun; 4705 } 4706 for (cur_lun <= max_lun; cur_lun++) { 4707 struct ahd_tmode_lstate* lstate; 4708 4709 lstate = tstate->enabled_luns[cur_lun]; 4710 if (lstate == NULL) 4711 continue; 4712 4713 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4714 MSG_BUS_DEV_RESET, /*arg*/0); 4715 ahd_send_lstate_events(ahd, lstate); 4716 } 4717 } 4718 #endif 4719 4720 /* 4721 * Go back to async/narrow transfers and renegotiate. 4722 */ 4723 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4724 AHD_TRANS_CUR, /*paused*/TRUE); 4725 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4726 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4727 4728 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4729 lun, AC_SENT_BDR, NULL); 4730 4731 if (message != NULL 4732 && (verbose_level <= bootverbose)) 4733 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4734 message, devinfo->channel, devinfo->target, found); 4735 } 4736 4737 #ifdef AHD_TARGET_MODE 4738 static void 4739 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4740 struct scb *scb) 4741 { 4742 4743 /* 4744 * To facilitate adding multiple messages together, 4745 * each routine should increment the index and len 4746 * variables instead of setting them explicitly. 4747 */ 4748 ahd->msgout_index = 0; 4749 ahd->msgout_len = 0; 4750 4751 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4752 ahd_build_transfer_msg(ahd, devinfo); 4753 else 4754 panic("ahd_intr: AWAITING target message with no message"); 4755 4756 ahd->msgout_index = 0; 4757 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4758 } 4759 #endif 4760 /**************************** Initialization **********************************/ 4761 static u_int 4762 ahd_sglist_size(struct ahd_softc *ahd) 4763 { 4764 bus_size_t list_size; 4765 4766 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4767 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4768 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4769 return (list_size); 4770 } 4771 4772 /* 4773 * Calculate the optimum S/G List allocation size. S/G elements used 4774 * for a given transaction must be physically contiguous. Assume the 4775 * OS will allocate full pages to us, so it doesn't make sense to request 4776 * less than a page. 4777 */ 4778 static u_int 4779 ahd_sglist_allocsize(struct ahd_softc *ahd) 4780 { 4781 bus_size_t sg_list_increment; 4782 bus_size_t sg_list_size; 4783 bus_size_t max_list_size; 4784 bus_size_t best_list_size; 4785 4786 /* Start out with the minimum required for AHD_NSEG. */ 4787 sg_list_increment = ahd_sglist_size(ahd); 4788 sg_list_size = sg_list_increment; 4789 4790 /* Get us as close as possible to a page in size. */ 4791 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4792 sg_list_size += sg_list_increment; 4793 4794 /* 4795 * Try to reduce the amount of wastage by allocating 4796 * multiple pages. 4797 */ 4798 best_list_size = sg_list_size; 4799 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4800 if (max_list_size < 4 * PAGE_SIZE) 4801 max_list_size = 4 * PAGE_SIZE; 4802 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4803 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4804 while ((sg_list_size + sg_list_increment) <= max_list_size 4805 && (sg_list_size % PAGE_SIZE) != 0) { 4806 bus_size_t new_mod; 4807 bus_size_t best_mod; 4808 4809 sg_list_size += sg_list_increment; 4810 new_mod = sg_list_size % PAGE_SIZE; 4811 best_mod = best_list_size % PAGE_SIZE; 4812 if (new_mod > best_mod || new_mod == 0) { 4813 best_list_size = sg_list_size; 4814 } 4815 } 4816 return (best_list_size); 4817 } 4818 4819 int 4820 ahd_softc_init(struct ahd_softc *ahd) 4821 { 4822 4823 ahd->unpause = 0; 4824 ahd->pause = PAUSE; 4825 return (0); 4826 } 4827 4828 void 4829 ahd_set_unit(struct ahd_softc *ahd, int unit) 4830 { 4831 ahd->unit = unit; 4832 } 4833 4834 void 4835 ahd_set_name(struct ahd_softc *ahd, char *name) 4836 { 4837 if (ahd->name != NULL) 4838 free(ahd->name, M_DEVBUF); 4839 ahd->name = name; 4840 } 4841 4842 void 4843 ahd_free(struct ahd_softc *ahd) 4844 { 4845 int i; 4846 4847 switch (ahd->init_level) { 4848 default: 4849 case 2: 4850 ahd_shutdown(ahd); 4851 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4852 /* FALLTHROUGH */ 4853 case 1: 4854 bus_dmamap_unload(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4855 bus_dmamap_destroy(ahd->parent_dmat, ahd->shared_data_map.dmamap); 4856 bus_dmamem_unmap(ahd->parent_dmat, (caddr_t)ahd->qoutfifo, ahd->shared_data_size); 4857 bus_dmamem_free(ahd->parent_dmat, &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); 4858 break; 4859 case 0: 4860 break; 4861 } 4862 4863 ahd_platform_free(ahd); 4864 ahd_fini_scbdata(ahd); 4865 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4866 struct ahd_tmode_tstate *tstate; 4867 4868 tstate = ahd->enabled_targets[i]; 4869 if (tstate != NULL) { 4870 #if AHD_TARGET_MODE 4871 int j; 4872 4873 for (j = 0; j < AHD_NUM_LUNS; j++) { 4874 struct ahd_tmode_lstate *lstate; 4875 4876 lstate = tstate->enabled_luns[j]; 4877 if (lstate != NULL) { 4878 xpt_free_path(lstate->path); 4879 free(lstate, M_DEVBUF); 4880 } 4881 } 4882 #endif 4883 free(tstate, M_DEVBUF); 4884 } 4885 } 4886 #if AHD_TARGET_MODE 4887 if (ahd->black_hole != NULL) { 4888 xpt_free_path(ahd->black_hole->path); 4889 free(ahd->black_hole, M_DEVBUF); 4890 } 4891 #endif 4892 if (ahd->name != NULL) 4893 free(ahd->name, M_DEVBUF); 4894 if (ahd->seep_config != NULL) 4895 free(ahd->seep_config, M_DEVBUF); 4896 if (ahd->saved_stack != NULL) 4897 free(ahd->saved_stack, M_DEVBUF); 4898 #ifndef __FreeBSD__ 4899 free(ahd, M_DEVBUF); 4900 #endif 4901 return; 4902 } 4903 4904 void 4905 ahd_shutdown(void *arg) 4906 { 4907 struct ahd_softc *ahd; 4908 4909 ahd = (struct ahd_softc *)arg; 4910 4911 #ifdef AHD_DEBUG 4912 printf("%s: ahd_shutdown\n", ahd_name(ahd)); 4913 #endif 4914 /* 4915 * Stop periodic timer callbacks. 4916 */ 4917 ahd_timer_stop(&ahd->reset_timer); 4918 ahd_timer_stop(&ahd->stat_timer); 4919 4920 /* This will reset most registers to 0, but not all */ 4921 ahd_reset(ahd, /*reinit*/FALSE); 4922 } 4923 4924 /* 4925 * Reset the controller and record some information about it 4926 * that is only available just after a reset. If "reinit" is 4927 * non-zero, this reset occured after initial configuration 4928 * and the caller requests that the chip be fully reinitialized 4929 * to a runable state. Chip interrupts are *not* enabled after 4930 * a reinitialization. The caller must enable interrupts via 4931 * ahd_intr_enable(). 4932 */ 4933 int 4934 ahd_reset(struct ahd_softc *ahd, int reinit) 4935 { 4936 u_int sxfrctl1; 4937 int wait; 4938 uint32_t cmd; 4939 struct ahd_pci_busdata *bd = ahd->bus_data; 4940 4941 /* 4942 * Preserve the value of the SXFRCTL1 register for all channels. 4943 * It contains settings that affect termination and we don't want 4944 * to disturb the integrity of the bus. 4945 */ 4946 ahd_pause(ahd); 4947 ahd_update_modes(ahd); 4948 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4949 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4950 4951 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 4952 4953 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4954 uint32_t mod_cmd; 4955 4956 /* 4957 * A4 Razor #632 4958 * During the assertion of CHIPRST, the chip 4959 * does not disable its parity logic prior to 4960 * the start of the reset. This may cause a 4961 * parity error to be detected and thus a 4962 * spurious SERR or PERR assertion. Disble 4963 * PERR and SERR responses during the CHIPRST. 4964 */ 4965 mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 4966 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, mod_cmd); 4967 } 4968 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 4969 4970 /* 4971 * Ensure that the reset has finished. We delay 1000us 4972 * prior to reading the register to make sure the chip 4973 * has sufficiently completed its reset to handle register 4974 * accesses. 4975 */ 4976 wait = 1000; 4977 do { 4978 ahd_delay(1000); 4979 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 4980 4981 if (wait == 0) { 4982 printf("%s: WARNING - Failed chip reset! " 4983 "Trying to initialize anyway.\n", ahd_name(ahd)); 4984 } 4985 ahd_outb(ahd, HCNTRL, ahd->pause); 4986 4987 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4988 /* 4989 * Clear any latched PCI error status and restore 4990 * previous SERR and PERR response enables. 4991 */ 4992 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 0x000000FF); 4993 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 4994 PCI_COMMAND_SERR_ENABLE|PCI_COMMAND_PARITY_ENABLE); 4995 } 4996 4997 /* 4998 * Mode should be SCSI after a chip reset, but lets 4999 * set it just to be safe. We touch the MODE_PTR 5000 * register directly so as to bypass the lazy update 5001 * ode in ahd_set_modes(). 5002 */ 5003 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5004 ahd_outb(ahd, MODE_PTR, 5005 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5006 5007 /* 5008 * Restore SXFRCTL1. 5009 * 5010 * We must always initialize STPWEN to 1 before we 5011 * restore the saved values. STPWEN is initialized 5012 * to a tri-state condition which can only be cleared 5013 * by turning it on. 5014 */ 5015 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5016 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5017 5018 /* Determine chip configuration */ 5019 ahd->features &= ~AHD_WIDE; 5020 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5021 ahd->features |= AHD_WIDE; 5022 5023 /* 5024 * If a recovery action has forced a chip reset, 5025 * re-initialize the chip to our liking. 5026 */ 5027 if (reinit != 0) 5028 ahd_chip_init(ahd); 5029 5030 return (0); 5031 } 5032 5033 /* 5034 * Determine the number of SCBs available on the controller 5035 */ 5036 int 5037 ahd_probe_scbs(struct ahd_softc *ahd) { 5038 int i; 5039 5040 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5041 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5042 for (i = 0; i < AHD_SCB_MAX; i++) { 5043 int j; 5044 int ret; 5045 5046 ahd_set_scbptr(ahd, i); 5047 ahd_outw(ahd, SCB_BASE, i); 5048 for (j = 2; j < 64; j++) 5049 ahd_outb(ahd, SCB_BASE+j, 0); 5050 /* Start out life as unallocated (needing an abort) */ 5051 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5052 ret = ahd_inw_scbram(ahd, SCB_BASE); 5053 if (ret != i) { 5054 printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", ahd_name(ahd), i, ret); 5055 break; 5056 } 5057 ahd_set_scbptr(ahd, 0); 5058 ret = ahd_inw_scbram(ahd, SCB_BASE); 5059 if (ret != 0) { 5060 printf("ahd_probe_scbs (non zero): returned 0x%x\n", ret); 5061 break; 5062 } 5063 } 5064 return (i); 5065 } 5066 5067 static void 5068 ahd_initialize_hscbs(struct ahd_softc *ahd) 5069 { 5070 int i; 5071 5072 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5073 ahd_set_scbptr(ahd, i); 5074 5075 /* Clear the control byte. */ 5076 ahd_outb(ahd, SCB_CONTROL, 0); 5077 5078 /* Set the next pointer */ 5079 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5080 } 5081 } 5082 5083 static int 5084 ahd_init_scbdata(struct ahd_softc *ahd) 5085 { 5086 struct scb_data *scb_data; 5087 int i; 5088 5089 scb_data = &ahd->scb_data; 5090 TAILQ_INIT(&scb_data->free_scbs); 5091 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5092 LIST_INIT(&scb_data->free_scb_lists[i]); 5093 LIST_INIT(&scb_data->any_dev_free_scb_list); 5094 SLIST_INIT(&scb_data->hscb_maps); 5095 SLIST_INIT(&scb_data->sg_maps); 5096 SLIST_INIT(&scb_data->sense_maps); 5097 5098 /* Determine the number of hardware SCBs and initialize them */ 5099 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5100 if (scb_data->maxhscbs == 0) { 5101 printf("%s: No SCB space found\n", ahd_name(ahd)); 5102 return (ENXIO); 5103 } 5104 ahd_initialize_hscbs(ahd); 5105 5106 /* 5107 * Create our DMA tags. These tags define the kinds of device 5108 * accessible memory allocations and memory mappings we will 5109 * need to perform during normal operation. 5110 * 5111 * Unless we need to further restrict the allocation, we rely 5112 * on the restrictions of the parent dmat, hence the common 5113 * use of MAXADDR and MAXSIZE. 5114 */ 5115 5116 /* Perform initial CCB allocation */ 5117 ahd_alloc_scbs(ahd); 5118 5119 if (scb_data->numscbs == 0) { 5120 printf("%s: ahd_init_scbdata - " 5121 "Unable to allocate initial scbs\n", 5122 ahd_name(ahd)); 5123 goto error_exit; 5124 } 5125 5126 /* 5127 * Note that we were successfull 5128 */ 5129 return (0); 5130 5131 error_exit: 5132 5133 return (ENOMEM); 5134 } 5135 5136 static struct scb * 5137 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5138 { 5139 struct scb *scb; 5140 5141 /* 5142 * Look on the pending list. 5143 */ 5144 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5145 if (SCB_GET_TAG(scb) == tag) 5146 return (scb); 5147 } 5148 5149 /* 5150 * Then on all of the collision free lists. 5151 */ 5152 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5153 struct scb *list_scb; 5154 5155 list_scb = scb; 5156 do { 5157 if (SCB_GET_TAG(list_scb) == tag) 5158 return (list_scb); 5159 list_scb = LIST_NEXT(list_scb, collision_links); 5160 } while (list_scb); 5161 } 5162 5163 /* 5164 * And finally on the generic free list. 5165 */ 5166 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5167 if (SCB_GET_TAG(scb) == tag) 5168 return (scb); 5169 } 5170 5171 return (NULL); 5172 } 5173 5174 static void 5175 ahd_fini_scbdata(struct ahd_softc *ahd) 5176 { 5177 struct scb_data *scb_data; 5178 5179 scb_data = &ahd->scb_data; 5180 if (scb_data == NULL) 5181 return; 5182 5183 switch (scb_data->init_level) { 5184 default: 5185 case 3: 5186 { 5187 struct map_node *sns_map; 5188 5189 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5190 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5191 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5192 sns_map->dmamap, (caddr_t)sns_map->vaddr, 5193 &sns_map->dmasegs, sns_map->nseg); 5194 free(sns_map, M_DEVBUF); 5195 } 5196 /* FALLTHROUGH */ 5197 } 5198 case 2: 5199 { 5200 struct map_node *sg_map; 5201 5202 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5203 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5204 ahd_freedmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), 5205 sg_map->dmamap, (caddr_t)sg_map->vaddr, 5206 &sg_map->dmasegs, sg_map->nseg); 5207 free(sg_map, M_DEVBUF); 5208 } 5209 /* FALLTHROUGH */ 5210 } 5211 case 1: 5212 { 5213 struct map_node *hscb_map; 5214 5215 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5216 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5217 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5218 hscb_map->dmamap, (caddr_t)hscb_map->vaddr, 5219 &hscb_map->dmasegs, hscb_map->nseg); 5220 free(hscb_map, M_DEVBUF); 5221 } 5222 /* FALLTHROUGH */ 5223 } 5224 case 0: 5225 break; 5226 } 5227 } 5228 5229 /* 5230 * DSP filter Bypass must be enabled until the first selection 5231 * after a change in bus mode (Razor #491 and #493). 5232 */ 5233 static void 5234 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5235 { 5236 ahd_mode_state saved_modes; 5237 5238 saved_modes = ahd_save_modes(ahd); 5239 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5240 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5241 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5242 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5243 #ifdef AHD_DEBUG 5244 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5245 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5246 #endif 5247 ahd_restore_modes(ahd, saved_modes); 5248 } 5249 5250 static void 5251 ahd_iocell_first_selection(struct ahd_softc *ahd) 5252 { 5253 ahd_mode_state saved_modes; 5254 u_int sblkctl; 5255 5256 saved_modes = ahd_save_modes(ahd); 5257 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5258 sblkctl = ahd_inb(ahd, SBLKCTL); 5259 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5260 #ifdef AHD_DEBUG 5261 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5262 printf("%s: iocell first selection\n", ahd_name(ahd)); 5263 #endif 5264 if ((sblkctl & ENAB40) != 0) { 5265 ahd_outb(ahd, DSPDATACTL, 5266 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5267 #ifdef AHD_DEBUG 5268 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5269 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5270 #endif 5271 } 5272 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5273 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5274 ahd_restore_modes(ahd, saved_modes); 5275 } 5276 5277 /*************************** SCB Management ***********************************/ 5278 static void 5279 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5280 { 5281 struct scb_list *free_list; 5282 struct scb_tailq *free_tailq; 5283 struct scb *first_scb; 5284 5285 scb->flags |= SCB_ON_COL_LIST; 5286 AHD_SET_SCB_COL_IDX(scb, col_idx); 5287 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5288 free_tailq = &ahd->scb_data.free_scbs; 5289 first_scb = LIST_FIRST(free_list); 5290 if (first_scb != NULL) { 5291 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5292 } else { 5293 LIST_INSERT_HEAD(free_list, scb, collision_links); 5294 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5295 } 5296 } 5297 5298 static void 5299 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5300 { 5301 struct scb_list *free_list; 5302 struct scb_tailq *free_tailq; 5303 struct scb *first_scb; 5304 u_int col_idx; 5305 5306 scb->flags &= ~SCB_ON_COL_LIST; 5307 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5308 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5309 free_tailq = &ahd->scb_data.free_scbs; 5310 first_scb = LIST_FIRST(free_list); 5311 if (first_scb == scb) { 5312 struct scb *next_scb; 5313 5314 /* 5315 * Maintain order in the collision free 5316 * lists for fairness if this device has 5317 * other colliding tags active. 5318 */ 5319 next_scb = LIST_NEXT(scb, collision_links); 5320 if (next_scb != NULL) { 5321 TAILQ_INSERT_AFTER(free_tailq, scb, 5322 next_scb, links.tqe); 5323 } 5324 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5325 } 5326 LIST_REMOVE(scb, collision_links); 5327 } 5328 5329 /* 5330 * Get a free scb. If there are none, see if we can allocate a new SCB. 5331 */ 5332 struct scb * 5333 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5334 { 5335 struct scb *scb; 5336 int tries; 5337 5338 tries = 0; 5339 look_again: 5340 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5341 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5342 ahd_rem_col_list(ahd, scb); 5343 goto found; 5344 } 5345 } 5346 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5347 5348 if (tries++ != 0) 5349 return (NULL); 5350 ahd_alloc_scbs(ahd); 5351 goto look_again; 5352 } 5353 LIST_REMOVE(scb, links.le); 5354 if (col_idx != AHD_NEVER_COL_IDX 5355 && (scb->col_scb != NULL) 5356 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5357 LIST_REMOVE(scb->col_scb, links.le); 5358 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5359 } 5360 found: 5361 scb->flags |= SCB_ACTIVE; 5362 return (scb); 5363 } 5364 5365 /* 5366 * Return an SCB resource to the free list. 5367 */ 5368 void 5369 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5370 { 5371 5372 /* Clean up for the next user */ 5373 scb->flags = SCB_FLAG_NONE; 5374 scb->hscb->control = 0; 5375 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5376 5377 if (scb->col_scb == NULL) { 5378 5379 /* 5380 * No collision possible. Just free normally. 5381 */ 5382 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5383 scb, links.le); 5384 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5385 5386 /* 5387 * The SCB we might have collided with is on 5388 * a free collision list. Put both SCBs on 5389 * the generic list. 5390 */ 5391 ahd_rem_col_list(ahd, scb->col_scb); 5392 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5393 scb, links.le); 5394 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5395 scb->col_scb, links.le); 5396 } else if ((scb->col_scb->flags 5397 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5398 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5399 5400 /* 5401 * The SCB we might collide with on the next allocation 5402 * is still active in a non-packetized, tagged, context. 5403 * Put us on the SCB collision list. 5404 */ 5405 ahd_add_col_list(ahd, scb, 5406 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5407 } else { 5408 /* 5409 * The SCB we might collide with on the next allocation 5410 * is either active in a packetized context, or free. 5411 * Since we can't collide, put this SCB on the generic 5412 * free list. 5413 */ 5414 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5415 scb, links.le); 5416 } 5417 5418 ahd_platform_scb_free(ahd, scb); 5419 } 5420 5421 void 5422 ahd_alloc_scbs(struct ahd_softc *ahd) 5423 { 5424 struct scb_data *scb_data; 5425 struct scb *next_scb; 5426 struct hardware_scb *hscb; 5427 struct map_node *hscb_map; 5428 struct map_node *sg_map; 5429 struct map_node *sense_map; 5430 uint8_t *segs; 5431 uint8_t *sense_data; 5432 bus_addr_t hscb_busaddr; 5433 bus_addr_t sg_busaddr; 5434 bus_addr_t sense_busaddr; 5435 int newcount; 5436 int i; 5437 5438 scb_data = &ahd->scb_data; 5439 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5440 /* Can't allocate any more */ 5441 return; 5442 5443 KASSERT(scb_data->scbs_left >= 0); 5444 if (scb_data->scbs_left != 0) { 5445 int offset; 5446 5447 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5448 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5449 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5450 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5451 } else { 5452 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5453 5454 if (hscb_map == NULL) 5455 return; 5456 5457 memset(hscb_map, 0, sizeof(*hscb_map)); 5458 5459 /* Allocate the next batch of hardware SCBs */ 5460 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5461 &hscb_map->dmamap, (caddr_t *)&hscb_map->vaddr, 5462 &hscb_map->physaddr, &hscb_map->dmasegs, 5463 &hscb_map->nseg, ahd_name(ahd), 5464 "hardware SCB structures") < 0) { 5465 free(hscb_map, M_DEVBUF); 5466 return; 5467 } 5468 5469 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5470 5471 hscb = (struct hardware_scb *)hscb_map->vaddr; 5472 hscb_busaddr = hscb_map->physaddr; 5473 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5474 } 5475 5476 scb_data->init_level++; 5477 5478 if (scb_data->sgs_left != 0) { 5479 int offset; 5480 5481 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5482 - scb_data->sgs_left) * ahd_sglist_size(ahd); 5483 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5484 segs = sg_map->vaddr + offset; 5485 sg_busaddr = sg_map->physaddr + offset; 5486 } else { 5487 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5488 5489 if (sg_map == NULL) 5490 return; 5491 5492 bzero(sg_map, sizeof(*sg_map)); 5493 5494 /* Allocate the next batch of S/G lists */ 5495 if (ahd_createdmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), ahd->sc_dmaflags, 5496 &sg_map->dmamap, (caddr_t *)&sg_map->vaddr, 5497 &sg_map->physaddr, &sg_map->dmasegs, 5498 &sg_map->nseg, ahd_name(ahd), 5499 "SG data structures") < 0) { 5500 free(sg_map, M_DEVBUF); 5501 return; 5502 } 5503 5504 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5505 5506 segs = sg_map->vaddr; 5507 sg_busaddr = sg_map->physaddr; 5508 scb_data->sgs_left = 5509 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5510 #ifdef AHD_DEBUG 5511 if (ahd_debug & AHD_SHOW_MEMORY) 5512 printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd)); 5513 #endif 5514 } 5515 5516 scb_data->init_level++; 5517 5518 5519 if (scb_data->sense_left != 0) { 5520 int offset; 5521 5522 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5523 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5524 sense_data = sense_map->vaddr + offset; 5525 sense_busaddr = sense_map->physaddr + offset; 5526 } else { 5527 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5528 5529 if (sense_map == NULL) 5530 return; 5531 5532 bzero(sense_map, sizeof(*sense_map)); 5533 5534 /* Allocate the next batch of sense buffers */ 5535 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5536 &sense_map->dmamap, (caddr_t *)&sense_map->vaddr, 5537 &sense_map->physaddr, &sense_map->dmasegs, 5538 &sense_map->nseg, ahd_name(ahd), 5539 "Sense Data structures") < 0) { 5540 free(sense_map, M_DEVBUF); 5541 return; 5542 } 5543 5544 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5545 5546 sense_data = sense_map->vaddr; 5547 sense_busaddr = sense_map->physaddr; 5548 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5549 #ifdef AHD_DEBUG 5550 if (ahd_debug & AHD_SHOW_MEMORY) 5551 printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd)); 5552 #endif 5553 } 5554 5555 scb_data->init_level++; 5556 5557 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5558 newcount = MIN(newcount, scb_data->sgs_left); 5559 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5560 scb_data->sense_left -= newcount; 5561 scb_data->scbs_left -= newcount; 5562 scb_data->sgs_left -= newcount; 5563 5564 for (i = 0; i < newcount; i++) { 5565 u_int col_tag; 5566 5567 struct scb_platform_data *pdata; 5568 #ifndef __linux__ 5569 int error; 5570 #endif 5571 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5572 M_DEVBUF, M_NOWAIT); 5573 if (next_scb == NULL) 5574 break; 5575 5576 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5577 M_DEVBUF, M_NOWAIT); 5578 if (pdata == NULL) { 5579 free(next_scb, M_DEVBUF); 5580 break; 5581 } 5582 next_scb->platform_data = pdata; 5583 next_scb->hscb_map = hscb_map; 5584 next_scb->sg_map = sg_map; 5585 next_scb->sense_map = sense_map; 5586 next_scb->sg_list = segs; 5587 next_scb->sense_data = sense_data; 5588 next_scb->sense_busaddr = sense_busaddr; 5589 memset(hscb, 0, sizeof(*hscb)); 5590 next_scb->hscb = hscb; 5591 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5592 KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && 5593 (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); 5594 5595 /* 5596 * The sequencer always starts with the second entry. 5597 * The first entry is embedded in the scb. 5598 */ 5599 next_scb->sg_list_busaddr = sg_busaddr; 5600 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5601 next_scb->sg_list_busaddr 5602 += sizeof(struct ahd_dma64_seg); 5603 else 5604 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5605 next_scb->ahd_softc = ahd; 5606 next_scb->flags = SCB_FLAG_NONE; 5607 5608 error = bus_dmamap_create(ahd->parent_dmat, 5609 AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0, 5610 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahd->sc_dmaflags, 5611 &next_scb->dmamap); 5612 if (error != 0) { 5613 free(next_scb, M_DEVBUF); 5614 free(pdata, M_DEVBUF); 5615 break; 5616 } 5617 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5618 col_tag = scb_data->numscbs ^ 0x100; 5619 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5620 if (next_scb->col_scb != NULL) 5621 next_scb->col_scb->col_scb = next_scb; 5622 ahd_free_scb(ahd, next_scb); 5623 hscb++; 5624 hscb_busaddr += sizeof(*hscb); 5625 segs += ahd_sglist_size(ahd); 5626 sg_busaddr += ahd_sglist_size(ahd); 5627 sense_data += AHD_SENSE_BUFSIZE; 5628 sense_busaddr += AHD_SENSE_BUFSIZE; 5629 scb_data->numscbs++; 5630 } 5631 } 5632 5633 void 5634 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5635 { 5636 const char *speed; 5637 const char *type; 5638 int len; 5639 5640 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5641 buf += len; 5642 5643 speed = "Ultra320 "; 5644 if ((ahd->features & AHD_WIDE) != 0) { 5645 type = "Wide "; 5646 } else { 5647 type = "Single "; 5648 } 5649 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5650 speed, type, ahd->channel, ahd->our_id); 5651 buf += len; 5652 5653 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5654 ahd->scb_data.maxhscbs); 5655 } 5656 5657 static const char *channel_strings[] = { 5658 "Primary Low", 5659 "Primary High", 5660 "Secondary Low", 5661 "Secondary High" 5662 }; 5663 5664 static const char *termstat_strings[] = { 5665 "Terminated Correctly", 5666 "Over Terminated", 5667 "Under Terminated", 5668 "Not Configured" 5669 }; 5670 5671 /* 5672 * Start the board, ready for normal operation 5673 */ 5674 int 5675 ahd_init(struct ahd_softc *ahd) 5676 { 5677 uint8_t *next_vaddr; 5678 bus_addr_t next_baddr; 5679 size_t driver_data_size; 5680 int i; 5681 int error; 5682 u_int warn_user; 5683 uint8_t current_sensing; 5684 uint8_t fstat; 5685 5686 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5687 5688 ahd->stack_size = ahd_probe_stack_size(ahd); 5689 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5690 M_DEVBUF, M_NOWAIT); 5691 if (ahd->saved_stack == NULL) 5692 return (ENOMEM); 5693 /* Zero the memory */ 5694 memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); 5695 5696 /* 5697 * Verify that the compiler hasn't over-agressively 5698 * padded important structures. 5699 */ 5700 if (sizeof(struct hardware_scb) != 64) 5701 panic("Hardware SCB size is incorrect"); 5702 5703 #ifdef AHD_DEBUG 5704 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5705 ahd->flags |= AHD_SEQUENCER_DEBUG; 5706 #endif 5707 5708 /* 5709 * Default to allowing initiator operations. 5710 */ 5711 ahd->flags |= AHD_INITIATORROLE; 5712 5713 /* 5714 * Only allow target mode features if this unit has them enabled. 5715 */ 5716 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5717 ahd->features &= ~AHD_TARGETMODE; 5718 5719 /* 5720 * DMA tag for our command fifos and other data in system memory 5721 * the card's sequencer must be able to access. For initiator 5722 * roles, we need to allocate space for the qoutfifo. When providing 5723 * for the target mode role, we must additionally provide space for 5724 * the incoming target command fifo. 5725 */ 5726 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5727 + sizeof(struct hardware_scb); 5728 if ((ahd->features & AHD_TARGETMODE) != 0) 5729 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5730 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5731 driver_data_size += PKT_OVERRUN_BUFSIZE; 5732 ahd->shared_data_size = driver_data_size; 5733 5734 memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); 5735 ahd->sc_dmaflags = BUS_DMA_NOWAIT; 5736 5737 if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 5738 ahd->sc_dmaflags, 5739 &ahd->shared_data_map.dmamap, (caddr_t *)&ahd->shared_data_map.vaddr, 5740 &ahd->shared_data_map.physaddr, &ahd->shared_data_map.dmasegs, 5741 &ahd->shared_data_map.nseg, ahd_name(ahd), "shared data") < 0) 5742 return (ENOMEM); 5743 ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; 5744 5745 ahd->init_level++; 5746 5747 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5748 next_baddr = ahd->shared_data_map.physaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5749 if ((ahd->features & AHD_TARGETMODE) != 0) { 5750 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5751 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5752 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5753 } 5754 5755 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5756 ahd->overrun_buf = next_vaddr; 5757 next_vaddr += PKT_OVERRUN_BUFSIZE; 5758 next_baddr += PKT_OVERRUN_BUFSIZE; 5759 } 5760 5761 /* 5762 * We need one SCB to serve as the "next SCB". Since the 5763 * tag identifier in this SCB will never be used, there is 5764 * no point in using a valid HSCB tag from an SCB pulled from 5765 * the standard free pool. So, we allocate this "sentinel" 5766 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5767 */ 5768 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5769 ahd->next_queued_hscb_map = &ahd->shared_data_map; 5770 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 5771 5772 memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 5773 5774 /* Allocate SCB data now that parent_dmat is initialized */ 5775 if (ahd_init_scbdata(ahd) != 0) 5776 return (ENOMEM); 5777 5778 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5779 ahd->flags &= ~AHD_RESET_BUS_A; 5780 5781 /* 5782 * Before committing these settings to the chip, give 5783 * the OSM one last chance to modify our configuration. 5784 */ 5785 ahd_platform_init(ahd); 5786 5787 /* Bring up the chip. */ 5788 ahd_chip_init(ahd); 5789 5790 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5791 5792 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5793 goto init_done; 5794 5795 /* 5796 * Verify termination based on current draw and 5797 * warn user if the bus is over/under terminated. 5798 */ 5799 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5800 CURSENSE_ENB); 5801 if (error != 0) { 5802 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5803 goto init_done; 5804 } 5805 for (i = 20, fstat = FLX_FSTAT_BUSY; 5806 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5807 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5808 if (error != 0) { 5809 printf("%s: current sensing timeout 2\n", 5810 ahd_name(ahd)); 5811 goto init_done; 5812 } 5813 } 5814 if (i == 0) { 5815 printf("%s: Timedout during current-sensing test\n", 5816 ahd_name(ahd)); 5817 goto init_done; 5818 } 5819 5820 /* Latch Current Sensing status. */ 5821 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5822 if (error != 0) { 5823 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5824 goto init_done; 5825 } 5826 5827 /* Diable current sensing. */ 5828 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5829 5830 #ifdef AHD_DEBUG 5831 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5832 printf("%s: current_sensing == 0x%x\n", 5833 ahd_name(ahd), current_sensing); 5834 } 5835 #endif 5836 warn_user = 0; 5837 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5838 u_int term_stat; 5839 5840 term_stat = (current_sensing & FLX_CSTAT_MASK); 5841 switch (term_stat) { 5842 case FLX_CSTAT_OVER: 5843 case FLX_CSTAT_UNDER: 5844 warn_user++; 5845 case FLX_CSTAT_INVALID: 5846 case FLX_CSTAT_OKAY: 5847 if (warn_user == 0 && bootverbose == 0) 5848 break; 5849 printf("%s: %s Channel %s\n", ahd_name(ahd), 5850 channel_strings[i], termstat_strings[term_stat]); 5851 break; 5852 } 5853 } 5854 if (warn_user) { 5855 printf("%s: WARNING. Termination is not configured correctly.\n" 5856 "%s: WARNING. SCSI bus operations may FAIL.\n", 5857 ahd_name(ahd), ahd_name(ahd)); 5858 } 5859 init_done: 5860 ahd_reset_current_bus(ahd); 5861 ahd_restart(ahd); 5862 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5863 ahd_stat_timer, ahd); 5864 5865 /* We have to wait until after any system dumps... */ 5866 ahd->shutdown_hook = shutdownhook_establish(ahd_shutdown, ahd); 5867 5868 return (0); 5869 } 5870 5871 /* 5872 * (Re)initialize chip state after a chip reset. 5873 */ 5874 static void 5875 ahd_chip_init(struct ahd_softc *ahd) 5876 { 5877 uint32_t busaddr; 5878 u_int sxfrctl1; 5879 u_int scsiseq_template; 5880 u_int wait; 5881 u_int i; 5882 u_int target; 5883 5884 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5885 /* 5886 * Take the LED out of diagnostic mode 5887 */ 5888 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 5889 5890 /* 5891 * Return HS_MAILBOX to its default value. 5892 */ 5893 ahd->hs_mailbox = 0; 5894 ahd_outb(ahd, HS_MAILBOX, 0); 5895 5896 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 5897 ahd_outb(ahd, IOWNID, ahd->our_id); 5898 ahd_outb(ahd, TOWNID, ahd->our_id); 5899 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 5900 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 5901 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 5902 && (ahd->seltime != STIMESEL_MIN)) { 5903 /* 5904 * The selection timer duration is twice as long 5905 * as it should be. Halve it by adding "1" to 5906 * the user specified setting. 5907 */ 5908 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 5909 } else { 5910 sxfrctl1 |= ahd->seltime; 5911 } 5912 5913 ahd_outb(ahd, SXFRCTL0, DFON); 5914 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 5915 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5916 5917 /* 5918 * Now that termination is set, wait for up 5919 * to 500ms for our transceivers to settle. If 5920 * the adapter does not have a cable attached, 5921 * the transceivers may never settle, so don't 5922 * complain if we fail here. 5923 */ 5924 for (wait = 10000; 5925 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 5926 wait--) 5927 ahd_delay(100); 5928 5929 /* Clear any false bus resets due to the transceivers settling */ 5930 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 5931 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5932 5933 /* Initialize mode specific S/G state. */ 5934 for (i = 0; i < 2; i++) { 5935 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 5936 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 5937 ahd_outb(ahd, SG_STATE, 0); 5938 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 5939 ahd_outb(ahd, SEQIMODE, 5940 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 5941 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 5942 } 5943 5944 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5945 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 5946 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 5947 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 5948 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 5949 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 5950 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 5951 } else { 5952 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 5953 } 5954 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 5955 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 5956 /* 5957 * Do not issue a target abort when a split completion 5958 * error occurs. Let our PCIX interrupt handler deal 5959 * with it instead. H2A4 Razor #625 5960 */ 5961 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 5962 5963 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 5964 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 5965 5966 /* 5967 * Tweak IOCELL settings. 5968 */ 5969 if ((ahd->flags & AHD_HP_BOARD) != 0) { 5970 for (i = 0; i < NUMDSPS; i++) { 5971 ahd_outb(ahd, DSPSELECT, i); 5972 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 5973 } 5974 #ifdef AHD_DEBUG 5975 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5976 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 5977 WRTBIASCTL_HP_DEFAULT); 5978 #endif 5979 } 5980 ahd_setup_iocell_workaround(ahd); 5981 5982 /* 5983 * Enable LQI Manager interrupts. 5984 */ 5985 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 5986 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 5987 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 5988 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 5989 /* 5990 * An interrupt from LQOBUSFREE is made redundant by the 5991 * BUSFREE interrupt. We choose to have the sequencer catch 5992 * LQOPHCHGINPKT errors manually for the command phase at the 5993 * start of a packetized selection case. 5994 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 5995 */ 5996 ahd_outb(ahd, LQOMODE1, 0); 5997 5998 /* 5999 * Setup sequencer interrupt handlers. 6000 */ 6001 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6002 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6003 6004 /* 6005 * Setup SCB Offset registers. 6006 */ 6007 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6008 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6009 pkt_long_lun)); 6010 } else { 6011 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6012 } 6013 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6014 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6015 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6016 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6017 shared_data.idata.cdb)); 6018 ahd_outb(ahd, QNEXTPTR, 6019 offsetof(struct hardware_scb, next_hscb_busaddr)); 6020 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6021 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6022 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6023 ahd_outb(ahd, LUNLEN, 6024 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6025 } else { 6026 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6027 } 6028 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6029 ahd_outb(ahd, MAXCMD, 0xFF); 6030 ahd_outb(ahd, SCBAUTOPTR, 6031 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6032 6033 /* We haven't been enabled for target mode yet. */ 6034 ahd_outb(ahd, MULTARGID, 0); 6035 ahd_outb(ahd, MULTARGID + 1, 0); 6036 6037 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6038 /* Initialize the negotiation table. */ 6039 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6040 /* 6041 * Clear the spare bytes in the neg table to avoid 6042 * spurious parity errors. 6043 */ 6044 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6045 ahd_outb(ahd, NEGOADDR, target); 6046 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6047 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6048 ahd_outb(ahd, ANNEXDAT, 0); 6049 } 6050 } 6051 6052 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6053 struct ahd_devinfo devinfo; 6054 struct ahd_initiator_tinfo *tinfo; 6055 struct ahd_tmode_tstate *tstate; 6056 6057 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6058 target, &tstate); 6059 ahd_compile_devinfo(&devinfo, ahd->our_id, 6060 target, CAM_LUN_WILDCARD, 6061 'A', ROLE_INITIATOR); 6062 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6063 } 6064 6065 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6066 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6067 6068 #if NEEDS_MORE_TESTING 6069 /* 6070 * Always enable abort on incoming L_Qs if this feature is 6071 * supported. We use this to catch invalid SCB references. 6072 */ 6073 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6074 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6075 else 6076 #endif 6077 ahd_outb(ahd, LQCTL1, 0); 6078 6079 /* All of our queues are empty */ 6080 ahd->qoutfifonext = 0; 6081 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6082 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6083 for (i = 0; i < AHD_QOUT_SIZE; i++) 6084 ahd->qoutfifo[i] = 0; 6085 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6086 6087 ahd->qinfifonext = 0; 6088 for (i = 0; i < AHD_QIN_SIZE; i++) 6089 ahd->qinfifo[i] = SCB_LIST_NULL; 6090 6091 if ((ahd->features & AHD_TARGETMODE) != 0) { 6092 /* All target command blocks start out invalid. */ 6093 for (i = 0; i < AHD_TMODE_CMDS; i++) 6094 ahd->targetcmds[i].cmd_valid = 0; 6095 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6096 ahd->tqinfifonext = 1; 6097 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6098 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6099 } 6100 6101 /* Initialize Scratch Ram. */ 6102 ahd_outb(ahd, SEQ_FLAGS, 0); 6103 ahd_outb(ahd, SEQ_FLAGS2, 0); 6104 6105 /* We don't have any waiting selections */ 6106 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6107 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6108 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6109 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6110 } 6111 6112 /* 6113 * Nobody is waiting to be DMAed into the QOUTFIFO. 6114 */ 6115 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6116 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6117 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6118 6119 /* 6120 * The Freeze Count is 0. 6121 */ 6122 ahd_outw(ahd, QFREEZE_COUNT, 0); 6123 6124 /* 6125 * Tell the sequencer where it can find our arrays in memory. 6126 */ 6127 busaddr = ahd->shared_data_map.physaddr; 6128 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6129 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6130 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6131 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6132 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6133 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6134 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6135 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6136 /* 6137 * Setup the allowed SCSI Sequences based on operational mode. 6138 * If we are a target, we'll enable select in operations once 6139 * we've had a lun enabled. 6140 */ 6141 scsiseq_template = ENAUTOATNP; 6142 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6143 scsiseq_template |= ENRSELI; 6144 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6145 6146 /* There are no busy SCBs yet. */ 6147 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6148 int lun; 6149 6150 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6151 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6152 } 6153 6154 /* 6155 * Initialize the group code to command length table. 6156 * Vendor Unique codes are set to 0 so we only capture 6157 * the first byte of the cdb. These can be overridden 6158 * when target mode is enabled. 6159 */ 6160 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6161 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6162 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6163 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6164 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6165 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6166 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6167 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6168 6169 /* Tell the sequencer of our initial queue positions */ 6170 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6171 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6172 ahd->qinfifonext = 0; 6173 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6174 ahd_set_hescb_qoff(ahd, 0); 6175 ahd_set_snscb_qoff(ahd, 0); 6176 ahd_set_sescb_qoff(ahd, 0); 6177 ahd_set_sdscb_qoff(ahd, 0); 6178 6179 /* 6180 * Tell the sequencer which SCB will be the next one it receives. 6181 */ 6182 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6183 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6184 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6185 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6186 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6187 6188 /* 6189 * Default to coalescing disabled. 6190 */ 6191 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6192 ahd_outw(ahd, CMDS_PENDING, 0); 6193 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6194 ahd->int_coalescing_maxcmds, 6195 ahd->int_coalescing_mincmds); 6196 ahd_enable_coalescing(ahd, FALSE); 6197 6198 ahd_loadseq(ahd); 6199 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6200 } 6201 6202 /* 6203 * Setup default device and controller settings. 6204 * This should only be called if our probe has 6205 * determined that no configuration data is available. 6206 */ 6207 int 6208 ahd_default_config(struct ahd_softc *ahd) 6209 { 6210 int targ; 6211 6212 ahd->our_id = 7; 6213 6214 /* 6215 * Allocate a tstate to house information for our 6216 * initiator presence on the bus as well as the user 6217 * data for any target mode initiator. 6218 */ 6219 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6220 printf("%s: unable to allocate ahd_tmode_tstate. " 6221 "Failing attach\n", ahd_name(ahd)); 6222 return (ENOMEM); 6223 } 6224 6225 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6226 struct ahd_devinfo devinfo; 6227 struct ahd_initiator_tinfo *tinfo; 6228 struct ahd_tmode_tstate *tstate; 6229 uint16_t target_mask; 6230 6231 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6232 targ, &tstate); 6233 /* 6234 * We support SPC2 and SPI4. 6235 */ 6236 tinfo->user.protocol_version = 4; 6237 tinfo->user.transport_version = 4; 6238 6239 target_mask = 0x01 << targ; 6240 ahd->user_discenable |= target_mask; 6241 tstate->discenable |= target_mask; 6242 ahd->user_tagenable |= target_mask; 6243 #ifdef AHD_FORCE_160 6244 tinfo->user.period = AHD_SYNCRATE_DT; 6245 #else 6246 tinfo->user.period = AHD_SYNCRATE_160; 6247 #endif 6248 tinfo->user.offset= MAX_OFFSET; 6249 tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6250 | MSG_EXT_PPR_WRFLOW 6251 | MSG_EXT_PPR_HOLDMCS 6252 | MSG_EXT_PPR_IU_REQ 6253 | MSG_EXT_PPR_QAS_REQ 6254 | MSG_EXT_PPR_DT_REQ; 6255 if ((ahd->features & AHD_RTI) != 0) 6256 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6257 6258 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6259 6260 /* 6261 * Start out Async/Narrow/Untagged and with 6262 * conservative protocol support. 6263 */ 6264 tinfo->goal.protocol_version = 2; 6265 tinfo->goal.transport_version = 2; 6266 tinfo->curr.protocol_version = 2; 6267 tinfo->curr.transport_version = 2; 6268 ahd_compile_devinfo(&devinfo, ahd->our_id, 6269 targ, CAM_LUN_WILDCARD, 6270 'A', ROLE_INITIATOR); 6271 tstate->tagenable &= ~target_mask; 6272 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6273 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6274 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6275 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6276 /*paused*/TRUE); 6277 } 6278 return (0); 6279 } 6280 6281 /* 6282 * Parse device configuration information. 6283 */ 6284 int 6285 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6286 { 6287 int targ; 6288 int max_targ; 6289 6290 max_targ = sc->max_targets & CFMAXTARG; 6291 ahd->our_id = sc->brtime_id & CFSCSIID; 6292 6293 /* 6294 * Allocate a tstate to house information for our 6295 * initiator presence on the bus as well as the user 6296 * data for any target mode initiator. 6297 */ 6298 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6299 printf("%s: unable to allocate ahd_tmode_tstate. " 6300 "Failing attach\n", ahd_name(ahd)); 6301 return (ENOMEM); 6302 } 6303 6304 for (targ = 0; targ < max_targ; targ++) { 6305 struct ahd_devinfo devinfo; 6306 struct ahd_initiator_tinfo *tinfo; 6307 struct ahd_transinfo *user_tinfo; 6308 struct ahd_tmode_tstate *tstate; 6309 uint16_t target_mask; 6310 6311 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6312 targ, &tstate); 6313 user_tinfo = &tinfo->user; 6314 6315 /* 6316 * We support SPC2 and SPI4. 6317 */ 6318 tinfo->user.protocol_version = 4; 6319 tinfo->user.transport_version = 4; 6320 6321 target_mask = 0x01 << targ; 6322 ahd->user_discenable &= ~target_mask; 6323 tstate->discenable &= ~target_mask; 6324 ahd->user_tagenable &= ~target_mask; 6325 if (sc->device_flags[targ] & CFDISC) { 6326 tstate->discenable |= target_mask; 6327 ahd->user_discenable |= target_mask; 6328 ahd->user_tagenable |= target_mask; 6329 } else { 6330 /* 6331 * Cannot be packetized without disconnection. 6332 */ 6333 sc->device_flags[targ] &= ~CFPACKETIZED; 6334 } 6335 6336 user_tinfo->ppr_options = 0; 6337 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6338 if (user_tinfo->period < CFXFER_ASYNC) { 6339 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6340 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6341 user_tinfo->offset = MAX_OFFSET; 6342 } else { 6343 user_tinfo->offset = 0; 6344 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6345 } 6346 #ifdef AHD_FORCE_160 6347 if (user_tinfo->period <= AHD_SYNCRATE_160) 6348 user_tinfo->period = AHD_SYNCRATE_DT; 6349 #endif 6350 6351 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6352 user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6353 | MSG_EXT_PPR_WRFLOW 6354 | MSG_EXT_PPR_HOLDMCS 6355 | MSG_EXT_PPR_IU_REQ; 6356 if ((ahd->features & AHD_RTI) != 0) 6357 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6358 } 6359 6360 if ((sc->device_flags[targ] & CFQAS) != 0) 6361 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6362 6363 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6364 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6365 else 6366 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6367 #ifdef AHD_DEBUG 6368 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6369 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6370 user_tinfo->period, user_tinfo->offset, 6371 user_tinfo->ppr_options); 6372 #endif 6373 /* 6374 * Start out Async/Narrow/Untagged and with 6375 * conservative protocol support. 6376 */ 6377 tstate->tagenable &= ~target_mask; 6378 tinfo->goal.protocol_version = 2; 6379 tinfo->goal.transport_version = 2; 6380 tinfo->curr.protocol_version = 2; 6381 tinfo->curr.transport_version = 2; 6382 ahd_compile_devinfo(&devinfo, ahd->our_id, 6383 targ, CAM_LUN_WILDCARD, 6384 'A', ROLE_INITIATOR); 6385 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6386 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6387 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6388 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6389 /*paused*/TRUE); 6390 } 6391 6392 ahd->flags &= ~AHD_SPCHK_ENB_A; 6393 if (sc->bios_control & CFSPARITY) 6394 ahd->flags |= AHD_SPCHK_ENB_A; 6395 6396 ahd->flags &= ~AHD_RESET_BUS_A; 6397 if (sc->bios_control & CFRESETB) 6398 ahd->flags |= AHD_RESET_BUS_A; 6399 6400 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6401 if (sc->bios_control & CFEXTEND) 6402 ahd->flags |= AHD_EXTENDED_TRANS_A; 6403 6404 ahd->flags &= ~AHD_BIOS_ENABLED; 6405 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6406 ahd->flags |= AHD_BIOS_ENABLED; 6407 6408 ahd->flags &= ~AHD_STPWLEVEL_A; 6409 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6410 ahd->flags |= AHD_STPWLEVEL_A; 6411 6412 return (0); 6413 } 6414 6415 /* 6416 * Parse device configuration information. 6417 */ 6418 int 6419 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6420 { 6421 int error; 6422 6423 error = ahd_verify_vpd_cksum(vpd); 6424 if (error == 0) 6425 return (EINVAL); 6426 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6427 ahd->flags |= AHD_BOOT_CHANNEL; 6428 return (0); 6429 } 6430 6431 void 6432 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6433 { 6434 u_int hcntrl; 6435 6436 hcntrl = ahd_inb(ahd, HCNTRL); 6437 hcntrl &= ~INTEN; 6438 ahd->pause &= ~INTEN; 6439 ahd->unpause &= ~INTEN; 6440 if (enable) { 6441 hcntrl |= INTEN; 6442 ahd->pause |= INTEN; 6443 ahd->unpause |= INTEN; 6444 } 6445 ahd_outb(ahd, HCNTRL, hcntrl); 6446 } 6447 6448 void 6449 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6450 u_int mincmds) 6451 { 6452 if (timer > AHD_TIMER_MAX_US) 6453 timer = AHD_TIMER_MAX_US; 6454 ahd->int_coalescing_timer = timer; 6455 6456 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6457 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6458 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6459 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6460 ahd->int_coalescing_maxcmds = maxcmds; 6461 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6462 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6463 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6464 } 6465 6466 void 6467 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 6468 { 6469 6470 ahd->hs_mailbox &= ~ENINT_COALESCE; 6471 if (enable) 6472 ahd->hs_mailbox |= ENINT_COALESCE; 6473 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6474 ahd_flush_device_writes(ahd); 6475 ahd_run_qoutfifo(ahd); 6476 } 6477 6478 /* 6479 * Ensure that the card is paused in a location 6480 * outside of all critical sections and that all 6481 * pending work is completed prior to returning. 6482 * This routine should only be called from outside 6483 * an interrupt context. 6484 */ 6485 void 6486 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6487 { 6488 u_int intstat; 6489 u_int maxloops; 6490 u_int qfreeze_cnt; 6491 6492 maxloops = 1000; 6493 ahd->flags |= AHD_ALL_INTERRUPTS; 6494 ahd_pause(ahd); 6495 /* 6496 * Increment the QFreeze Count so that the sequencer 6497 * will not start new selections. We do this only 6498 * until we are safely paused without further selections 6499 * pending. 6500 */ 6501 ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); 6502 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 6503 do { 6504 struct scb *waiting_scb; 6505 6506 ahd_unpause(ahd); 6507 ahd_intr(ahd); 6508 ahd_pause(ahd); 6509 ahd_clear_critical_section(ahd); 6510 intstat = ahd_inb(ahd, INTSTAT); 6511 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6512 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6513 ahd_outb(ahd, SCSISEQ0, 6514 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6515 /* 6516 * In the non-packetized case, the sequencer (for Rev A), 6517 * relies on ENSELO remaining set after SELDO. The hardware 6518 * auto-clears ENSELO in the packetized case. 6519 */ 6520 waiting_scb = ahd_lookup_scb(ahd, 6521 ahd_inw(ahd, WAITING_TID_HEAD)); 6522 if (waiting_scb != NULL 6523 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6524 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6525 ahd_outb(ahd, SCSISEQ0, 6526 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6527 } while (--maxloops 6528 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6529 && ((intstat & INT_PEND) != 0 6530 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 6531 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 6532 if (maxloops == 0) { 6533 printf("Infinite interrupt loop, INTSTAT = %x", 6534 ahd_inb(ahd, INTSTAT)); 6535 } 6536 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 6537 if (qfreeze_cnt == 0) { 6538 printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n", 6539 ahd_name(ahd)); 6540 } else { 6541 qfreeze_cnt--; 6542 } 6543 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 6544 if (qfreeze_cnt == 0) 6545 ahd_outb(ahd, SEQ_FLAGS2, 6546 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 6547 6548 ahd_flush_qoutfifo(ahd); 6549 6550 ahd_platform_flushwork(ahd); 6551 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6552 } 6553 6554 int 6555 ahd_suspend(struct ahd_softc *ahd) 6556 { 6557 6558 ahd_pause_and_flushwork(ahd); 6559 6560 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 6561 ahd_unpause(ahd); 6562 return (EBUSY); 6563 } 6564 ahd_shutdown(ahd); 6565 return (0); 6566 } 6567 6568 int 6569 ahd_resume(struct ahd_softc *ahd) 6570 { 6571 6572 ahd_reset(ahd, /*reinit*/TRUE); 6573 ahd_intr_enable(ahd, TRUE); 6574 ahd_restart(ahd); 6575 return (0); 6576 } 6577 6578 /************************** Busy Target Table *********************************/ 6579 /* 6580 * Set SCBPTR to the SCB that contains the busy 6581 * table entry for TCL. Return the offset into 6582 * the SCB that contains the entry for TCL. 6583 * saved_scbid is dereferenced and set to the 6584 * scbid that should be restored once manipualtion 6585 * of the TCL entry is complete. 6586 */ 6587 static __inline u_int 6588 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6589 { 6590 /* 6591 * Index to the SCB that contains the busy entry. 6592 */ 6593 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6594 *saved_scbid = ahd_get_scbptr(ahd); 6595 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6596 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6597 6598 /* 6599 * And now calculate the SCB offset to the entry. 6600 * Each entry is 2 bytes wide, hence the 6601 * multiplication by 2. 6602 */ 6603 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6604 } 6605 6606 /* 6607 * Return the untagged transaction id for a given target/channel lun. 6608 */ 6609 u_int 6610 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6611 { 6612 u_int scbid; 6613 u_int scb_offset; 6614 u_int saved_scbptr; 6615 6616 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6617 scbid = ahd_inw_scbram(ahd, scb_offset); 6618 ahd_set_scbptr(ahd, saved_scbptr); 6619 return (scbid); 6620 } 6621 6622 void 6623 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6624 { 6625 u_int scb_offset; 6626 u_int saved_scbptr; 6627 6628 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6629 ahd_outw(ahd, scb_offset, scbid); 6630 ahd_set_scbptr(ahd, saved_scbptr); 6631 } 6632 6633 /************************** SCB and SCB queue management **********************/ 6634 int 6635 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6636 char channel, int lun, u_int tag, role_t role) 6637 { 6638 int targ = SCB_GET_TARGET(ahd, scb); 6639 char chan = SCB_GET_CHANNEL(ahd, scb); 6640 int slun = SCB_GET_LUN(scb); 6641 int match; 6642 6643 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6644 if (match != 0) 6645 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6646 if (match != 0) 6647 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6648 if (match != 0) { 6649 #if AHD_TARGET_MODE 6650 int group; 6651 6652 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6653 if (role == ROLE_INITIATOR) { 6654 match = (group != XPT_FC_GROUP_TMODE) 6655 && ((tag == SCB_GET_TAG(scb)) 6656 || (tag == SCB_LIST_NULL)); 6657 } else if (role == ROLE_TARGET) { 6658 match = (group == XPT_FC_GROUP_TMODE) 6659 && ((tag == scb->io_ctx->csio.tag_id) 6660 || (tag == SCB_LIST_NULL)); 6661 } 6662 #else /* !AHD_TARGET_MODE */ 6663 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6664 #endif /* AHD_TARGET_MODE */ 6665 } 6666 6667 return match; 6668 } 6669 6670 void 6671 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6672 { 6673 int target; 6674 char channel; 6675 int lun; 6676 6677 target = SCB_GET_TARGET(ahd, scb); 6678 lun = SCB_GET_LUN(scb); 6679 channel = SCB_GET_CHANNEL(ahd, scb); 6680 6681 ahd_search_qinfifo(ahd, target, channel, lun, 6682 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6683 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6684 6685 ahd_platform_freeze_devq(ahd, scb); 6686 } 6687 6688 void 6689 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6690 { 6691 struct scb *prev_scb; 6692 ahd_mode_state saved_modes; 6693 6694 saved_modes = ahd_save_modes(ahd); 6695 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6696 prev_scb = NULL; 6697 if (ahd_qinfifo_count(ahd) != 0) { 6698 u_int prev_tag; 6699 u_int prev_pos; 6700 6701 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6702 prev_tag = ahd->qinfifo[prev_pos]; 6703 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6704 } 6705 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6706 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6707 ahd_restore_modes(ahd, saved_modes); 6708 } 6709 6710 static void 6711 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6712 struct scb *scb) 6713 { 6714 if (prev_scb == NULL) { 6715 uint32_t busaddr; 6716 6717 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6718 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6719 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6720 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6721 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6722 } else { 6723 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6724 ahd_sync_scb(ahd, prev_scb, 6725 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6726 } 6727 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6728 ahd->qinfifonext++; 6729 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6730 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6731 } 6732 6733 static int 6734 ahd_qinfifo_count(struct ahd_softc *ahd) 6735 { 6736 u_int qinpos; 6737 u_int wrap_qinpos; 6738 u_int wrap_qinfifonext; 6739 6740 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6741 qinpos = ahd_get_snscb_qoff(ahd); 6742 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6743 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6744 if (wrap_qinfifonext >= wrap_qinpos) 6745 return (wrap_qinfifonext - wrap_qinpos); 6746 else 6747 return (wrap_qinfifonext 6748 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6749 } 6750 6751 void 6752 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6753 { 6754 struct scb *scb; 6755 ahd_mode_state saved_modes; 6756 u_int pending_cmds; 6757 6758 saved_modes = ahd_save_modes(ahd); 6759 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6760 6761 /* 6762 * Don't count any commands as outstanding that the 6763 * sequencer has already marked for completion. 6764 */ 6765 ahd_flush_qoutfifo(ahd); 6766 6767 pending_cmds = 0; 6768 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6769 pending_cmds++; 6770 } 6771 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6772 ahd_restore_modes(ahd, saved_modes); 6773 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6774 } 6775 6776 int 6777 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6778 int lun, u_int tag, role_t role, uint32_t status, 6779 ahd_search_action action) 6780 { 6781 struct scb *scb; 6782 struct scb *prev_scb; 6783 ahd_mode_state saved_modes; 6784 u_int qinstart; 6785 u_int qinpos; 6786 u_int qintail; 6787 u_int tid_next; 6788 u_int tid_prev; 6789 u_int scbid; 6790 u_int savedscbptr; 6791 uint32_t busaddr; 6792 int found; 6793 int targets; 6794 int pending_cmds; 6795 int qincount; 6796 6797 /* Must be in CCHAN mode */ 6798 saved_modes = ahd_save_modes(ahd); 6799 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6800 6801 /* 6802 * Halt any pending SCB DMA. The sequencer will reinitiate 6803 * this DMA if the qinfifo is not empty once we unpause. 6804 */ 6805 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 6806 == (CCARREN|CCSCBEN|CCSCBDIR)) { 6807 ahd_outb(ahd, CCSCBCTL, 6808 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 6809 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 6810 ; 6811 } 6812 /* Determine sequencer's position in the qinfifo. */ 6813 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 6814 qinstart = ahd_get_snscb_qoff(ahd); 6815 qinpos = AHD_QIN_WRAP(qinstart); 6816 found = 0; 6817 prev_scb = NULL; 6818 6819 pending_cmds = 0; 6820 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6821 pending_cmds++; 6822 } 6823 qincount = ahd_qinfifo_count(ahd); 6824 6825 if (action == SEARCH_PRINT) { 6826 printf("qinstart = 0x%x qinfifonext = 0x%x\n", 6827 qinstart, ahd->qinfifonext); 6828 } 6829 6830 /* 6831 * Start with an empty queue. Entries that are not chosen 6832 * for removal will be re-added to the queue as we go. 6833 */ 6834 ahd->qinfifonext = qinstart; 6835 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6836 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6837 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6838 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6839 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6840 6841 while (qinpos != qintail) { 6842 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 6843 if (scb == NULL) { 6844 panic("Loop 1\n"); 6845 } 6846 6847 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 6848 /* 6849 * We found an scb that needs to be acted on. 6850 */ 6851 found++; 6852 switch (action) { 6853 case SEARCH_COMPLETE: 6854 { 6855 cam_status ostat; 6856 cam_status cstat; 6857 6858 ostat = ahd_get_scsi_status(scb); 6859 if (ostat == CAM_REQ_INPROG) 6860 ahd_set_scsi_status(scb, status); 6861 cstat = ahd_get_transaction_status(scb); 6862 if (cstat != CAM_REQ_CMP) 6863 ahd_freeze_scb(scb); 6864 if ((scb->flags & SCB_ACTIVE) == 0) 6865 printf("Inactive SCB in qinfifo\n"); 6866 if (scb->xs->error != CAM_REQ_CMP) 6867 printf("SEARCH_COMPLETE(0x%x): ostat 0x%x, cstat 0x%x, xs_error 0x%x\n", 6868 SCB_GET_TAG(scb), ostat, cstat, scb->xs->error); 6869 ahd_done(ahd, scb); 6870 6871 /* FALLTHROUGH */ 6872 } 6873 case SEARCH_REMOVE: 6874 break; 6875 case SEARCH_PRINT: 6876 printf(" 0x%x", ahd->qinfifo[qinpos]); 6877 /* FALLTHROUGH */ 6878 case SEARCH_COUNT: 6879 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6880 prev_scb = scb; 6881 break; 6882 } 6883 } else { 6884 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6885 prev_scb = scb; 6886 } 6887 qinpos = AHD_QIN_WRAP(qinpos+1); 6888 } 6889 6890 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6891 6892 if (action == SEARCH_PRINT) 6893 printf("\nWAITING_TID_QUEUES:\n"); 6894 6895 /* 6896 * Search waiting for selection lists. We traverse the 6897 * list of "their ids" waiting for selection and, if 6898 * appropriate, traverse the SCBs of each "their id" 6899 * looking for matches. 6900 */ 6901 savedscbptr = ahd_get_scbptr(ahd); 6902 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 6903 tid_prev = SCB_LIST_NULL; 6904 targets = 0; 6905 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 6906 u_int tid_head; 6907 6908 /* 6909 * We limit based on the number of SCBs since 6910 * MK_MESSAGE SCBs are not in the per-tid lists. 6911 */ 6912 targets++; 6913 if (targets > AHD_SCB_MAX) { 6914 panic("TID LIST LOOP"); 6915 } 6916 if (scbid >= ahd->scb_data.numscbs) { 6917 printf("%s: Waiting TID List inconsistency. " 6918 "SCB index == 0x%x, yet numscbs == 0x%x.", 6919 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 6920 ahd_dump_card_state(ahd); 6921 panic("for safety"); 6922 } 6923 scb = ahd_lookup_scb(ahd, scbid); 6924 if (scb == NULL) { 6925 printf("%s: SCB = 0x%x Not Active!\n", 6926 ahd_name(ahd), scbid); 6927 panic("Waiting TID List traversal\n"); 6928 break; 6929 } 6930 ahd_set_scbptr(ahd, scbid); 6931 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 6932 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 6933 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 6934 tid_prev = scbid; 6935 continue; 6936 } 6937 6938 /* 6939 * We found a list of scbs that needs to be searched. 6940 */ 6941 if (action == SEARCH_PRINT) 6942 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 6943 tid_head = scbid; 6944 found += ahd_search_scb_list(ahd, target, channel, 6945 lun, tag, role, status, 6946 action, &tid_head, 6947 SCB_GET_TARGET(ahd, scb)); 6948 if (tid_head != scbid) 6949 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 6950 if (!SCBID_IS_NULL(tid_head)) 6951 tid_prev = tid_head; 6952 if (action == SEARCH_PRINT) 6953 printf(")\n"); 6954 } 6955 ahd_set_scbptr(ahd, savedscbptr); 6956 ahd_restore_modes(ahd, saved_modes); 6957 return (found); 6958 } 6959 6960 static int 6961 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 6962 int lun, u_int tag, role_t role, uint32_t status, 6963 ahd_search_action action, u_int *list_head, u_int tid) 6964 { 6965 struct scb *scb; 6966 u_int scbid; 6967 u_int next; 6968 u_int prev; 6969 int found; 6970 6971 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6972 found = 0; 6973 prev = SCB_LIST_NULL; 6974 next = *list_head; 6975 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 6976 if (scbid >= ahd->scb_data.numscbs) { 6977 printf("%s:SCB List inconsistency. " 6978 "SCB == 0x%x, yet numscbs == 0x%x.", 6979 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 6980 ahd_dump_card_state(ahd); 6981 panic("for safety"); 6982 } 6983 scb = ahd_lookup_scb(ahd, scbid); 6984 if (scb == NULL) { 6985 printf("%s: SCB = %d Not Active!\n", 6986 ahd_name(ahd), scbid); 6987 panic("Waiting List traversal\n"); 6988 } 6989 ahd_set_scbptr(ahd, scbid); 6990 next = ahd_inw_scbram(ahd, SCB_NEXT); 6991 if (ahd_match_scb(ahd, scb, target, channel, 6992 lun, SCB_LIST_NULL, role) == 0) { 6993 prev = scbid; 6994 continue; 6995 } 6996 found++; 6997 switch (action) { 6998 case SEARCH_COMPLETE: 6999 { 7000 cam_status ostat; 7001 cam_status cstat; 7002 7003 ostat = ahd_get_scsi_status(scb); 7004 if (ostat == CAM_REQ_INPROG) 7005 ahd_set_scsi_status(scb, status); 7006 cstat = ahd_get_transaction_status(scb); 7007 if (cstat != CAM_REQ_CMP) 7008 ahd_freeze_scb(scb); 7009 if ((scb->flags & SCB_ACTIVE) == 0) 7010 printf("Inactive SCB in Waiting List\n"); 7011 ahd_done(ahd, scb); 7012 /* FALLTHROUGH */ 7013 } 7014 case SEARCH_REMOVE: 7015 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7016 if (prev == SCB_LIST_NULL) 7017 *list_head = next; 7018 break; 7019 case SEARCH_PRINT: 7020 printf("0x%x ", scbid); 7021 case SEARCH_COUNT: 7022 prev = scbid; 7023 break; 7024 } 7025 if (found > AHD_SCB_MAX) 7026 panic("SCB LIST LOOP"); 7027 } 7028 if (action == SEARCH_COMPLETE 7029 || action == SEARCH_REMOVE) 7030 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7031 return (found); 7032 } 7033 7034 static void 7035 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7036 u_int tid_cur, u_int tid_next) 7037 { 7038 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7039 7040 if (SCBID_IS_NULL(tid_cur)) { 7041 7042 /* Bypass current TID list */ 7043 if (SCBID_IS_NULL(tid_prev)) { 7044 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7045 } else { 7046 ahd_set_scbptr(ahd, tid_prev); 7047 ahd_outw(ahd, SCB_NEXT2, tid_next); 7048 } 7049 if (SCBID_IS_NULL(tid_next)) 7050 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7051 } else { 7052 7053 /* Stitch through tid_cur */ 7054 if (SCBID_IS_NULL(tid_prev)) { 7055 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7056 } else { 7057 ahd_set_scbptr(ahd, tid_prev); 7058 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7059 } 7060 ahd_set_scbptr(ahd, tid_cur); 7061 ahd_outw(ahd, SCB_NEXT2, tid_next); 7062 7063 if (SCBID_IS_NULL(tid_next)) 7064 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7065 } 7066 } 7067 7068 /* 7069 * Manipulate the waiting for selection list and return the 7070 * scb that follows the one that we remove. 7071 */ 7072 static u_int 7073 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7074 u_int prev, u_int next, u_int tid) 7075 { 7076 u_int tail_offset; 7077 7078 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7079 if (!SCBID_IS_NULL(prev)) { 7080 ahd_set_scbptr(ahd, prev); 7081 ahd_outw(ahd, SCB_NEXT, next); 7082 } 7083 7084 /* 7085 * SCBs that had MK_MESSAGE set in them will not 7086 * be queued to the per-target lists, so don't 7087 * blindly clear the tail pointer. 7088 */ 7089 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7090 if (SCBID_IS_NULL(next) 7091 && ahd_inw(ahd, tail_offset) == scbid) 7092 ahd_outw(ahd, tail_offset, prev); 7093 ahd_add_scb_to_free_list(ahd, scbid); 7094 return (next); 7095 } 7096 7097 /* 7098 * Add the SCB as selected by SCBPTR onto the on chip list of 7099 * free hardware SCBs. This list is empty/unused if we are not 7100 * performing SCB paging. 7101 */ 7102 static void 7103 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7104 { 7105 /* XXX Need some other mechanism to designate "free". */ 7106 /* 7107 * Invalidate the tag so that our abort 7108 * routines don't think it's active. 7109 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7110 */ 7111 } 7112 7113 /******************************** Error Handling ******************************/ 7114 /* 7115 * Abort all SCBs that match the given description (target/channel/lun/tag), 7116 * setting their status to the passed in status if the status has not already 7117 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7118 * is paused before it is called. 7119 */ 7120 int 7121 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7122 int lun, u_int tag, role_t role, uint32_t status) 7123 { 7124 struct scb *scbp; 7125 struct scb *scbp_next; 7126 u_int i, j; 7127 u_int maxtarget; 7128 u_int minlun; 7129 u_int maxlun; 7130 int found; 7131 ahd_mode_state saved_modes; 7132 7133 /* restore this when we're done */ 7134 saved_modes = ahd_save_modes(ahd); 7135 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7136 7137 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7138 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7139 7140 /* 7141 * Clean out the busy target table for any untagged commands. 7142 */ 7143 i = 0; 7144 maxtarget = 16; 7145 if (target != CAM_TARGET_WILDCARD) { 7146 i = target; 7147 if (channel == 'B') 7148 i += 8; 7149 maxtarget = i + 1; 7150 } 7151 7152 if (lun == CAM_LUN_WILDCARD) { 7153 minlun = 0; 7154 maxlun = AHD_NUM_LUNS_NONPKT; 7155 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7156 minlun = maxlun = 0; 7157 } else { 7158 minlun = lun; 7159 maxlun = lun + 1; 7160 } 7161 7162 if (role != ROLE_TARGET) { 7163 for (;i < maxtarget; i++) { 7164 for (j = minlun;j < maxlun; j++) { 7165 u_int scbid; 7166 u_int tcl; 7167 7168 tcl = BUILD_TCL_RAW(i, 'A', j); 7169 scbid = ahd_find_busy_tcl(ahd, tcl); 7170 scbp = ahd_lookup_scb(ahd, scbid); 7171 if (scbp == NULL 7172 || ahd_match_scb(ahd, scbp, target, channel, 7173 lun, tag, role) == 0) 7174 continue; 7175 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7176 } 7177 } 7178 } 7179 7180 /* 7181 * Don't abort commands that have already completed, 7182 * but haven't quite made it up to the host yet. 7183 */ 7184 ahd_flush_qoutfifo(ahd); 7185 7186 /* 7187 * Go through the pending CCB list and look for 7188 * commands for this target that are still active. 7189 * These are other tagged commands that were 7190 * disconnected when the reset occurred. 7191 */ 7192 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7193 while (scbp_next != NULL) { 7194 scbp = scbp_next; 7195 scbp_next = LIST_NEXT(scbp, pending_links); 7196 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7197 cam_status ostat; 7198 7199 ostat = ahd_get_scsi_status(scbp); 7200 if (ostat == CAM_REQ_INPROG) 7201 ahd_set_scsi_status(scbp, status); 7202 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7203 ahd_freeze_scb(scbp); 7204 if ((scbp->flags & SCB_ACTIVE) == 0) 7205 printf("Inactive SCB on pending list\n"); 7206 ahd_done(ahd, scbp); 7207 found++; 7208 } 7209 } 7210 ahd_restore_modes(ahd, saved_modes); 7211 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7212 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7213 return found; 7214 } 7215 7216 static void 7217 ahd_reset_current_bus(struct ahd_softc *ahd) 7218 { 7219 uint8_t scsiseq; 7220 7221 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7222 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7223 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7224 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7225 ahd_flush_device_writes(ahd); 7226 ahd_delay(AHD_BUSRESET_DELAY); 7227 /* Turn off the bus reset */ 7228 ahd_outb(ahd, SCSISEQ0, scsiseq); 7229 ahd_flush_device_writes(ahd); 7230 ahd_delay(AHD_BUSRESET_DELAY); 7231 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7232 /* 7233 * 2A Razor #474 7234 * Certain chip state is not cleared for 7235 * SCSI bus resets that we initiate, so 7236 * we must reset the chip. 7237 */ 7238 ahd_reset(ahd, /*reinit*/TRUE); 7239 ahd_intr_enable(ahd, /*enable*/TRUE); 7240 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7241 } 7242 7243 ahd_clear_intstat(ahd); 7244 } 7245 7246 int 7247 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7248 { 7249 struct ahd_devinfo devinfo; 7250 u_int initiator; 7251 u_int target; 7252 u_int max_scsiid; 7253 int found; 7254 u_int fifo; 7255 u_int next_fifo; 7256 7257 7258 ahd->pending_device = NULL; 7259 7260 ahd_compile_devinfo(&devinfo, 7261 CAM_TARGET_WILDCARD, 7262 CAM_TARGET_WILDCARD, 7263 CAM_LUN_WILDCARD, 7264 channel, ROLE_UNKNOWN); 7265 ahd_pause(ahd); 7266 7267 /* Make sure the sequencer is in a safe location. */ 7268 ahd_clear_critical_section(ahd); 7269 7270 #if AHD_TARGET_MODE 7271 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7272 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7273 } 7274 #endif 7275 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7276 7277 /* 7278 * Disable selections so no automatic hardware 7279 * functions will modify chip state. 7280 */ 7281 ahd_outb(ahd, SCSISEQ0, 0); 7282 ahd_outb(ahd, SCSISEQ1, 0); 7283 7284 /* 7285 * Safely shut down our DMA engines. Always start with 7286 * the FIFO that is not currently active (if any are 7287 * actively connected). 7288 */ 7289 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7290 if (next_fifo > CURRFIFO_1) 7291 /* If disconneced, arbitrarily start with FIFO1. */ 7292 next_fifo = fifo = 0; 7293 do { 7294 next_fifo ^= CURRFIFO_1; 7295 ahd_set_modes(ahd, next_fifo, next_fifo); 7296 ahd_outb(ahd, DFCNTRL, 7297 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7298 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7299 ahd_delay(10); 7300 /* 7301 * Set CURRFIFO to the now inactive channel. 7302 */ 7303 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7304 ahd_outb(ahd, DFFSTAT, next_fifo); 7305 } while (next_fifo != fifo); 7306 7307 /* 7308 * Reset the bus if we are initiating this reset 7309 */ 7310 ahd_clear_msg_state(ahd); 7311 ahd_outb(ahd, SIMODE1, 7312 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7313 7314 if (initiate_reset) 7315 ahd_reset_current_bus(ahd); 7316 7317 ahd_clear_intstat(ahd); 7318 7319 /* 7320 * Clean up all the state information for the 7321 * pending transactions on this bus. 7322 */ 7323 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7324 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7325 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7326 7327 /* 7328 * Cleanup anything left in the FIFOs. 7329 */ 7330 ahd_clear_fifo(ahd, 0); 7331 ahd_clear_fifo(ahd, 1); 7332 7333 /* 7334 * Revert to async/narrow transfers until we renegotiate. 7335 */ 7336 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7337 for (target = 0; target <= max_scsiid; target++) { 7338 7339 if (ahd->enabled_targets[target] == NULL) 7340 continue; 7341 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7342 struct ahd_devinfo devinfo; 7343 7344 ahd_compile_devinfo(&devinfo, target, initiator, 7345 CAM_LUN_WILDCARD, 7346 'A', ROLE_UNKNOWN); 7347 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7348 AHD_TRANS_CUR, /*paused*/TRUE); 7349 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7350 /*offset*/0, /*ppr_options*/0, 7351 AHD_TRANS_CUR, /*paused*/TRUE); 7352 } 7353 } 7354 7355 #ifdef AHD_TARGET_MODE 7356 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7357 7358 /* 7359 * Send an immediate notify ccb to all target more peripheral 7360 * drivers affected by this action. 7361 */ 7362 for (target = 0; target <= max_scsiid; target++) { 7363 struct ahd_tmode_tstate* tstate; 7364 u_int lun; 7365 7366 tstate = ahd->enabled_targets[target]; 7367 if (tstate == NULL) 7368 continue; 7369 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7370 struct ahd_tmode_lstate* lstate; 7371 7372 lstate = tstate->enabled_luns[lun]; 7373 if (lstate == NULL) 7374 continue; 7375 7376 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7377 EVENT_TYPE_BUS_RESET, /*arg*/0); 7378 ahd_send_lstate_events(ahd, lstate); 7379 } 7380 } 7381 #endif 7382 7383 /* Notify the XPT that a bus reset occurred */ 7384 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7385 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7386 ahd_restart(ahd); 7387 7388 /* 7389 * Freeze the SIMQ until our poller can determine that 7390 * the bus reset has really gone away. We set the initial 7391 * timer to 0 to have the check performed as soon as possible 7392 * from the timer context. 7393 */ 7394 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7395 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7396 ahd_freeze_simq(ahd); 7397 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7398 } 7399 return (found); 7400 } 7401 7402 7403 #define AHD_RESET_POLL_US 1000 7404 static void 7405 ahd_reset_poll(void *arg) 7406 { 7407 struct ahd_softc *ahd; 7408 u_int scsiseq1; 7409 u_long l; 7410 int s; 7411 7412 ahd_list_lock(&l); 7413 ahd = (void*)arg; 7414 if (ahd == NULL) { 7415 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7416 ahd_list_unlock(&l); 7417 return; 7418 } 7419 ahd_lock(ahd, &s); 7420 ahd_pause(ahd); 7421 ahd_update_modes(ahd); 7422 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7423 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7424 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7425 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7426 ahd_reset_poll, ahd); 7427 ahd_unpause(ahd); 7428 ahd_unlock(ahd, &s); 7429 ahd_list_unlock(&l); 7430 return; 7431 } 7432 7433 /* Reset is now low. Complete chip reinitialization. */ 7434 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7435 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7436 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7437 ahd_unpause(ahd); 7438 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7439 ahd_unlock(ahd, &s); 7440 ahd_release_simq(ahd); 7441 ahd_list_unlock(&l); 7442 } 7443 7444 /**************************** Statistics Processing ***************************/ 7445 static void 7446 ahd_stat_timer(void *arg) 7447 { 7448 struct ahd_softc *ahd; 7449 u_long l; 7450 int s; 7451 int enint_coal; 7452 7453 ahd_list_lock(&l); 7454 ahd = (void *)arg; 7455 if (ahd == NULL) { 7456 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7457 ahd_list_unlock(&l); 7458 return; 7459 } 7460 ahd_lock(ahd, &s); 7461 7462 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7463 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7464 enint_coal |= ENINT_COALESCE; 7465 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7466 enint_coal &= ~ENINT_COALESCE; 7467 7468 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 7469 ahd_enable_coalescing(ahd, enint_coal); 7470 #ifdef AHD_DEBUG 7471 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 7472 printf("%s: Interrupt coalescing " 7473 "now %sabled. Cmds %d\n", 7474 ahd_name(ahd), 7475 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 7476 ahd->cmdcmplt_total); 7477 #endif 7478 } 7479 7480 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7481 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7482 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7483 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7484 ahd_stat_timer, ahd); 7485 ahd_unlock(ahd, &s); 7486 ahd_list_unlock(&l); 7487 } 7488 7489 /****************************** Status Processing *****************************/ 7490 void 7491 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7492 { 7493 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7494 ahd_handle_scsi_status(ahd, scb); 7495 } else { 7496 ahd_calc_residual(ahd, scb); 7497 ahd_done(ahd, scb); 7498 } 7499 } 7500 7501 void 7502 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7503 { 7504 struct hardware_scb *hscb; 7505 u_int qfreeze_cnt; 7506 7507 /* 7508 * The sequencer freezes its select-out queue 7509 * anytime a SCSI status error occurs. We must 7510 * handle the error and decrement the QFREEZE count 7511 * to allow the sequencer to continue. 7512 */ 7513 hscb = scb->hscb; 7514 7515 /* Freeze the queue until the client sees the error. */ 7516 ahd_freeze_devq(ahd, scb); 7517 ahd_freeze_scb(scb); 7518 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7519 if (qfreeze_cnt == 0) { 7520 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7521 } else { 7522 qfreeze_cnt--; 7523 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7524 } 7525 if (qfreeze_cnt == 0) 7526 ahd_outb(ahd, SEQ_FLAGS2, 7527 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7528 7529 /* Don't want to clobber the original sense code */ 7530 if ((scb->flags & SCB_SENSE) != 0) { 7531 /* 7532 * Clear the SCB_SENSE Flag and perform 7533 * a normal command completion. 7534 */ 7535 scb->flags &= ~SCB_SENSE; 7536 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7537 ahd_done(ahd, scb); 7538 return; 7539 } 7540 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7541 ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7542 switch (hscb->shared_data.istatus.scsi_status) { 7543 case STATUS_PKT_SENSE: 7544 { 7545 struct scsi_status_iu_header *siu; 7546 7547 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7548 siu = (struct scsi_status_iu_header *)scb->sense_data; 7549 ahd_set_scsi_status(scb, siu->status); 7550 #ifdef AHD_DEBUG 7551 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7552 ahd_print_path(ahd, scb); 7553 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7554 SCB_GET_TAG(scb), siu->status); 7555 } 7556 #endif 7557 if ((siu->flags & SIU_RSPVALID) != 0) { 7558 scsipi_printaddr(scb->xs->xs_periph); 7559 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7560 printf("Unable to parse pkt_failures\n"); 7561 } else { 7562 7563 switch (SIU_PKTFAIL_CODE(siu)) { 7564 case SIU_PFC_NONE: 7565 printf("No packet failure found\n"); 7566 break; 7567 case SIU_PFC_CIU_FIELDS_INVALID: 7568 printf("Invalid Command IU Field\n"); 7569 break; 7570 case SIU_PFC_TMF_NOT_SUPPORTED: 7571 printf("TMF not supportd\n"); 7572 break; 7573 case SIU_PFC_TMF_FAILED: 7574 printf("TMF failed\n"); 7575 break; 7576 case SIU_PFC_INVALID_TYPE_CODE: 7577 printf("Invalid L_Q Type code\n"); 7578 break; 7579 case SIU_PFC_ILLEGAL_REQUEST: 7580 printf("Illegal request\n"); 7581 default: 7582 break; 7583 } 7584 } 7585 if (siu->status == SCSI_STATUS_OK) 7586 ahd_set_transaction_status(scb, CAM_REQ_CMP_ERR); 7587 } 7588 if ((siu->flags & SIU_SNSVALID) != 0) { 7589 scb->flags |= SCB_PKT_SENSE; 7590 #ifdef AHD_DEBUG 7591 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7592 printf("Sense data available (%d)\n", siu->sense_length[0]); 7593 printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7594 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7595 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+12]), 7596 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+13])); 7597 } 7598 #endif 7599 } 7600 ahd_done(ahd, scb); 7601 break; 7602 } 7603 case SCSI_STATUS_CMD_TERMINATED: 7604 case SCSI_STATUS_CHECK_COND: 7605 { 7606 struct ahd_devinfo devinfo; 7607 struct ahd_dma_seg *sg; 7608 struct scsipi_sense *sc; 7609 struct ahd_initiator_tinfo *targ_info; 7610 struct ahd_tmode_tstate *tstate; 7611 struct ahd_transinfo *tinfo; 7612 #ifdef AHD_DEBUG 7613 if (ahd_debug & AHD_SHOW_SENSE) { 7614 ahd_print_path(ahd, scb); 7615 printf("SCB %d: requests Check Status\n", 7616 SCB_GET_TAG(scb)); 7617 } 7618 #endif 7619 7620 if (ahd_perform_autosense(scb) == 0) 7621 break; 7622 7623 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7624 SCB_GET_TARGET(ahd, scb), 7625 SCB_GET_LUN(scb), 7626 SCB_GET_CHANNEL(ahd, scb), 7627 ROLE_INITIATOR); 7628 targ_info = ahd_fetch_transinfo(ahd, 7629 devinfo.channel, 7630 devinfo.our_scsiid, 7631 devinfo.target, 7632 &tstate); 7633 tinfo = &targ_info->curr; 7634 sg = scb->sg_list; 7635 sc = (struct scsipi_sense *)hscb->shared_data.idata.cdb; 7636 /* 7637 * Save off the residual if there is one. 7638 */ 7639 ahd_update_residual(ahd, scb); 7640 #ifdef AHD_DEBUG 7641 if (ahd_debug & AHD_SHOW_SENSE) { 7642 ahd_print_path(ahd, scb); 7643 printf("Sending Sense\n"); 7644 } 7645 #endif 7646 scb->sg_count = 0; 7647 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7648 ahd_get_sense_bufsize(ahd, scb), 7649 /*last*/TRUE); 7650 sc->opcode = REQUEST_SENSE; 7651 sc->byte2 = 0; 7652 sc->unused[0] = 0; 7653 sc->unused[1] = 0; 7654 sc->length = ahd_get_sense_bufsize(ahd, scb); 7655 sc->control = 0; 7656 7657 /* 7658 * We can't allow the target to disconnect. 7659 * This will be an untagged transaction and 7660 * having the target disconnect will make this 7661 * transaction indestinguishable from outstanding 7662 * tagged transactions. 7663 */ 7664 hscb->control = 0; 7665 7666 /* 7667 * This request sense could be because the 7668 * the device lost power or in some other 7669 * way has lost our transfer negotiations. 7670 * Renegotiate if appropriate. Unit attention 7671 * errors will be reported before any data 7672 * phases occur. 7673 */ 7674 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7675 ahd_update_neg_request(ahd, &devinfo, 7676 tstate, targ_info, 7677 AHD_NEG_IF_NON_ASYNC); 7678 } 7679 if (tstate->auto_negotiate & devinfo.target_mask) { 7680 hscb->control |= MK_MESSAGE; 7681 scb->flags &= 7682 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7683 scb->flags |= SCB_AUTO_NEGOTIATE; 7684 } 7685 hscb->cdb_len = sizeof(*sc); 7686 ahd_setup_data_scb(ahd, scb); 7687 scb->flags |= SCB_SENSE; 7688 ahd_queue_scb(ahd, scb); 7689 /* 7690 * Ensure we have enough time to actually 7691 * retrieve the sense. 7692 */ 7693 ahd_scb_timer_reset(scb, 5 * 1000000); 7694 break; 7695 } 7696 case SCSI_STATUS_OK: 7697 printf("%s: Interrupted for status of 0? (SCB 0x%x)\n", 7698 ahd_name(ahd), SCB_GET_TAG(scb)); 7699 /* FALLTHROUGH */ 7700 default: 7701 ahd_done(ahd, scb); 7702 break; 7703 } 7704 } 7705 7706 /* 7707 * Calculate the residual for a just completed SCB. 7708 */ 7709 void 7710 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7711 { 7712 struct hardware_scb *hscb; 7713 struct initiator_status *spkt; 7714 uint32_t sgptr; 7715 uint32_t resid_sgptr; 7716 uint32_t resid; 7717 7718 /* 7719 * 5 cases. 7720 * 1) No residual. 7721 * SG_STATUS_VALID clear in sgptr. 7722 * 2) Transferless command 7723 * 3) Never performed any transfers. 7724 * sgptr has SG_FULL_RESID set. 7725 * 4) No residual but target did not 7726 * save data pointers after the 7727 * last transfer, so sgptr was 7728 * never updated. 7729 * 5) We have a partial residual. 7730 * Use residual_sgptr to determine 7731 * where we are. 7732 */ 7733 7734 hscb = scb->hscb; 7735 sgptr = ahd_le32toh(hscb->sgptr); 7736 if ((sgptr & SG_STATUS_VALID) == 0) 7737 /* Case 1 */ 7738 return; 7739 sgptr &= ~SG_STATUS_VALID; 7740 7741 if ((sgptr & SG_LIST_NULL) != 0) 7742 /* Case 2 */ 7743 return; 7744 7745 /* 7746 * Residual fields are the same in both 7747 * target and initiator status packets, 7748 * so we can always use the initiator fields 7749 * regardless of the role for this SCB. 7750 */ 7751 spkt = &hscb->shared_data.istatus; 7752 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7753 if ((sgptr & SG_FULL_RESID) != 0) { 7754 /* Case 3 */ 7755 resid = ahd_get_transfer_length(scb); 7756 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7757 /* Case 4 */ 7758 return; 7759 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7760 ahd_print_path(ahd, scb); 7761 printf("data overrun detected Tag == 0x%x.\n", 7762 SCB_GET_TAG(scb)); 7763 ahd_freeze_devq(ahd, scb); 7764 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7765 ahd_freeze_scb(scb); 7766 return; 7767 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7768 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7769 /* NOTREACHED */ 7770 } else { 7771 struct ahd_dma_seg *sg; 7772 7773 /* 7774 * Remainder of the SG where the transfer 7775 * stopped. 7776 */ 7777 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7778 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7779 7780 /* The residual sg_ptr always points to the next sg */ 7781 sg--; 7782 7783 /* 7784 * Add up the contents of all residual 7785 * SG segments that are after the SG where 7786 * the transfer stopped. 7787 */ 7788 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7789 sg++; 7790 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7791 } 7792 } 7793 7794 if ((scb->flags & SCB_SENSE) == 0) 7795 ahd_set_residual(scb, resid); 7796 /*else 7797 ahd_set_sense_residual(scb, resid);*/ 7798 7799 #ifdef AHD_DEBUG 7800 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7801 ahd_print_path(ahd, scb); 7802 printf("Handled %sResidual of %d bytes\n", 7803 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7804 } 7805 #endif 7806 } 7807 7808 /******************************* Target Mode **********************************/ 7809 #ifdef AHD_TARGET_MODE 7810 /* 7811 * Add a target mode event to this lun's queue 7812 */ 7813 static void 7814 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 7815 u_int initiator_id, u_int event_type, u_int event_arg) 7816 { 7817 struct ahd_tmode_event *event; 7818 int pending; 7819 7820 xpt_freeze_devq(lstate->path, /*count*/1); 7821 if (lstate->event_w_idx >= lstate->event_r_idx) 7822 pending = lstate->event_w_idx - lstate->event_r_idx; 7823 else 7824 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 7825 - (lstate->event_r_idx - lstate->event_w_idx); 7826 7827 if (event_type == EVENT_TYPE_BUS_RESET 7828 || event_type == MSG_BUS_DEV_RESET) { 7829 /* 7830 * Any earlier events are irrelevant, so reset our buffer. 7831 * This has the effect of allowing us to deal with reset 7832 * floods (an external device holding down the reset line) 7833 * without losing the event that is really interesting. 7834 */ 7835 lstate->event_r_idx = 0; 7836 lstate->event_w_idx = 0; 7837 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 7838 } 7839 7840 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 7841 xpt_print_path(lstate->path); 7842 printf("immediate event %x:%x lost\n", 7843 lstate->event_buffer[lstate->event_r_idx].event_type, 7844 lstate->event_buffer[lstate->event_r_idx].event_arg); 7845 lstate->event_r_idx++; 7846 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7847 lstate->event_r_idx = 0; 7848 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 7849 } 7850 7851 event = &lstate->event_buffer[lstate->event_w_idx]; 7852 event->initiator_id = initiator_id; 7853 event->event_type = event_type; 7854 event->event_arg = event_arg; 7855 lstate->event_w_idx++; 7856 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7857 lstate->event_w_idx = 0; 7858 } 7859 7860 /* 7861 * Send any target mode events queued up waiting 7862 * for immediate notify resources. 7863 */ 7864 void 7865 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 7866 { 7867 struct ccb_hdr *ccbh; 7868 struct ccb_immed_notify *inot; 7869 7870 while (lstate->event_r_idx != lstate->event_w_idx 7871 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 7872 struct ahd_tmode_event *event; 7873 7874 event = &lstate->event_buffer[lstate->event_r_idx]; 7875 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 7876 inot = (struct ccb_immed_notify *)ccbh; 7877 switch (event->event_type) { 7878 case EVENT_TYPE_BUS_RESET: 7879 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 7880 break; 7881 default: 7882 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 7883 inot->message_args[0] = event->event_type; 7884 inot->message_args[1] = event->event_arg; 7885 break; 7886 } 7887 inot->initiator_id = event->initiator_id; 7888 inot->sense_len = 0; 7889 xpt_done((union ccb *)inot); 7890 lstate->event_r_idx++; 7891 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 7892 lstate->event_r_idx = 0; 7893 } 7894 } 7895 #endif 7896 7897 /******************** Sequencer Program Patching/Download *********************/ 7898 7899 #ifdef AHD_DUMP_SEQ 7900 void 7901 ahd_dumpseq(struct ahd_softc* ahd) 7902 { 7903 int i; 7904 int max_prog; 7905 7906 max_prog = 2048; 7907 7908 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 7909 ahd_outb(ahd, PRGMCNT, 0); 7910 ahd_outb(ahd, PRGMCNT+1, 0); 7911 for (i = 0; i < max_prog; i++) { 7912 uint8_t ins_bytes[4]; 7913 7914 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 7915 printf("0x%08x\n", ins_bytes[0] << 24 7916 | ins_bytes[1] << 16 7917 | ins_bytes[2] << 8 7918 | ins_bytes[3]); 7919 } 7920 } 7921 #endif 7922 7923 static void 7924 ahd_loadseq(struct ahd_softc *ahd) 7925 { 7926 struct cs cs_table[num_critical_sections]; 7927 u_int begin_set[num_critical_sections]; 7928 u_int end_set[num_critical_sections]; 7929 struct patch *cur_patch; 7930 u_int cs_count; 7931 u_int cur_cs; 7932 u_int i; 7933 int downloaded; 7934 u_int skip_addr; 7935 u_int sg_prefetch_cnt; 7936 u_int sg_prefetch_cnt_limit; 7937 u_int sg_prefetch_align; 7938 u_int sg_size; 7939 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 7940 7941 if (bootverbose) 7942 printf("%s: Downloading Sequencer Program...", 7943 ahd_name(ahd)); 7944 7945 #if DOWNLOAD_CONST_COUNT != 7 7946 #error "Download Const Mismatch" 7947 #endif 7948 /* 7949 * Start out with 0 critical sections 7950 * that apply to this firmware load. 7951 */ 7952 cs_count = 0; 7953 cur_cs = 0; 7954 memset(begin_set, 0, sizeof(begin_set)); 7955 memset(end_set, 0, sizeof(end_set)); 7956 7957 /* 7958 * Setup downloadable constant table. 7959 * 7960 * The computation for the S/G prefetch variables is 7961 * a bit complicated. We would like to always fetch 7962 * in terms of cachelined sized increments. However, 7963 * if the cacheline is not an even multiple of the 7964 * SG element size or is larger than our SG RAM, using 7965 * just the cache size might leave us with only a portion 7966 * of an SG element at the tail of a prefetch. If the 7967 * cacheline is larger than our S/G prefetch buffer less 7968 * the size of an SG element, we may round down to a cacheline 7969 * that doesn't contain any or all of the S/G of interest 7970 * within the bounds of our S/G ram. Provide variables to 7971 * the sequencer that will allow it to handle these edge 7972 * cases. 7973 */ 7974 /* Start by aligning to the nearest cacheline. */ 7975 sg_prefetch_align = ahd->pci_cachesize; 7976 if (sg_prefetch_align == 0) 7977 sg_prefetch_align = 8; 7978 /* Round down to the nearest power of 2. */ 7979 while (powerof2(sg_prefetch_align) == 0) 7980 sg_prefetch_align--; 7981 /* 7982 * If the cacheline boundary is greater than half our prefetch RAM 7983 * we risk not being able to fetch even a single complete S/G 7984 * segment if we align to that boundary. 7985 */ 7986 if (sg_prefetch_align > CCSGADDR_MAX/2) 7987 sg_prefetch_align = CCSGADDR_MAX/2; 7988 /* Start by fetching a single cacheline. */ 7989 sg_prefetch_cnt = sg_prefetch_align; 7990 /* 7991 * Increment the prefetch count by cachelines until 7992 * at least one S/G element will fit. 7993 */ 7994 sg_size = sizeof(struct ahd_dma_seg); 7995 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 7996 sg_size = sizeof(struct ahd_dma64_seg); 7997 while (sg_prefetch_cnt < sg_size) 7998 sg_prefetch_cnt += sg_prefetch_align; 7999 /* 8000 * If the cacheline is not an even multiple of 8001 * the S/G size, we may only get a partial S/G when 8002 * we align. Add a cacheline if this is the case. 8003 */ 8004 if ((sg_prefetch_align % sg_size) != 0 8005 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8006 sg_prefetch_cnt += sg_prefetch_align; 8007 /* 8008 * Lastly, compute a value that the sequencer can use 8009 * to determine if the remainder of the CCSGRAM buffer 8010 * has a full S/G element in it. 8011 */ 8012 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8013 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8014 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8015 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8016 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8017 download_consts[SG_SIZEOF] = sg_size; 8018 download_consts[PKT_OVERRUN_BUFOFFSET] = 8019 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8020 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8021 cur_patch = patches; 8022 downloaded = 0; 8023 skip_addr = 0; 8024 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8025 ahd_outb(ahd, PRGMCNT, 0); 8026 ahd_outb(ahd, PRGMCNT+1, 0); 8027 8028 for (i = 0; i < sizeof(seqprog)/4; i++) { 8029 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8030 /* 8031 * Don't download this instruction as it 8032 * is in a patch that was removed. 8033 */ 8034 continue; 8035 } 8036 /* 8037 * Move through the CS table until we find a CS 8038 * that might apply to this instruction. 8039 */ 8040 for (; cur_cs < num_critical_sections; cur_cs++) { 8041 if (critical_sections[cur_cs].end <= i) { 8042 if (begin_set[cs_count] == TRUE 8043 && end_set[cs_count] == FALSE) { 8044 cs_table[cs_count].end = downloaded; 8045 end_set[cs_count] = TRUE; 8046 cs_count++; 8047 } 8048 continue; 8049 } 8050 if (critical_sections[cur_cs].begin <= i 8051 && begin_set[cs_count] == FALSE) { 8052 cs_table[cs_count].begin = downloaded; 8053 begin_set[cs_count] = TRUE; 8054 } 8055 break; 8056 } 8057 ahd_download_instr(ahd, i, download_consts); 8058 downloaded++; 8059 } 8060 8061 ahd->num_critical_sections = cs_count; 8062 if (cs_count != 0) { 8063 8064 cs_count *= sizeof(struct cs); 8065 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8066 if (ahd->critical_sections == NULL) 8067 panic("ahd_loadseq: Could not malloc"); 8068 memcpy(ahd->critical_sections, cs_table, cs_count); 8069 } 8070 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8071 8072 if (bootverbose) { 8073 printf(" %d instructions downloaded\n", downloaded); 8074 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8075 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8076 } 8077 } 8078 8079 static int 8080 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8081 u_int start_instr, u_int *skip_addr) 8082 { 8083 struct patch *cur_patch; 8084 struct patch *last_patch; 8085 u_int num_patches; 8086 8087 num_patches = sizeof(patches)/sizeof(struct patch); 8088 last_patch = &patches[num_patches]; 8089 cur_patch = *start_patch; 8090 8091 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8092 8093 if (cur_patch->patch_func(ahd) == 0) { 8094 8095 /* Start rejecting code */ 8096 *skip_addr = start_instr + cur_patch->skip_instr; 8097 cur_patch += cur_patch->skip_patch; 8098 } else { 8099 /* Accepted this patch. Advance to the next 8100 * one and wait for our intruction pointer to 8101 * hit this point. 8102 */ 8103 cur_patch++; 8104 } 8105 } 8106 8107 *start_patch = cur_patch; 8108 if (start_instr < *skip_addr) 8109 /* Still skipping */ 8110 return (0); 8111 8112 return (1); 8113 } 8114 8115 static u_int 8116 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8117 { 8118 struct patch *cur_patch; 8119 int address_offset; 8120 u_int skip_addr; 8121 u_int i; 8122 8123 address_offset = 0; 8124 cur_patch = patches; 8125 skip_addr = 0; 8126 8127 for (i = 0; i < address;) { 8128 8129 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8130 8131 if (skip_addr > i) { 8132 int end_addr; 8133 8134 end_addr = MIN(address, skip_addr); 8135 address_offset += end_addr - i; 8136 i = skip_addr; 8137 } else { 8138 i++; 8139 } 8140 } 8141 return (address - address_offset); 8142 } 8143 8144 static void 8145 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8146 { 8147 union ins_formats instr; 8148 struct ins_format1 *fmt1_ins; 8149 struct ins_format3 *fmt3_ins; 8150 u_int opcode; 8151 8152 /* 8153 * The firmware is always compiled into a little endian format. 8154 */ 8155 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8156 8157 fmt1_ins = &instr.format1; 8158 fmt3_ins = NULL; 8159 8160 /* Pull the opcode */ 8161 opcode = instr.format1.opcode; 8162 switch (opcode) { 8163 case AIC_OP_JMP: 8164 case AIC_OP_JC: 8165 case AIC_OP_JNC: 8166 case AIC_OP_CALL: 8167 case AIC_OP_JNE: 8168 case AIC_OP_JNZ: 8169 case AIC_OP_JE: 8170 case AIC_OP_JZ: 8171 { 8172 fmt3_ins = &instr.format3; 8173 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8174 /* FALLTHROUGH */ 8175 } 8176 case AIC_OP_OR: 8177 case AIC_OP_AND: 8178 case AIC_OP_XOR: 8179 case AIC_OP_ADD: 8180 case AIC_OP_ADC: 8181 case AIC_OP_BMOV: 8182 if (fmt1_ins->parity != 0) { 8183 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8184 } 8185 fmt1_ins->parity = 0; 8186 /* FALLTHROUGH */ 8187 case AIC_OP_ROL: 8188 { 8189 int i, count; 8190 8191 /* Calculate odd parity for the instruction */ 8192 for (i = 0, count = 0; i < 31; i++) { 8193 uint32_t mask; 8194 8195 mask = 0x01 << i; 8196 if ((instr.integer & mask) != 0) 8197 count++; 8198 } 8199 if ((count & 0x01) == 0) 8200 instr.format1.parity = 1; 8201 8202 /* The sequencer is a little endian cpu */ 8203 instr.integer = ahd_htole32(instr.integer); 8204 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8205 break; 8206 } 8207 default: 8208 panic("Unknown opcode encountered in seq program"); 8209 break; 8210 } 8211 } 8212 8213 static int 8214 ahd_probe_stack_size(struct ahd_softc *ahd) 8215 { 8216 int last_probe; 8217 8218 last_probe = 0; 8219 while (1) { 8220 int i; 8221 8222 /* 8223 * We avoid using 0 as a pattern to avoid 8224 * confusion if the stack implementation 8225 * "back-fills" with zeros when "poping' 8226 * entries. 8227 */ 8228 for (i = 1; i <= last_probe+1; i++) { 8229 ahd_outb(ahd, STACK, i & 0xFF); 8230 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8231 } 8232 8233 /* Verify */ 8234 for (i = last_probe+1; i > 0; i--) { 8235 u_int stack_entry; 8236 8237 stack_entry = ahd_inb(ahd, STACK) 8238 |(ahd_inb(ahd, STACK) << 8); 8239 if (stack_entry != i) 8240 goto sized; 8241 } 8242 last_probe++; 8243 } 8244 sized: 8245 return (last_probe); 8246 } 8247 8248 void 8249 ahd_dump_all_cards_state(void) 8250 { 8251 struct ahd_softc *list_ahd; 8252 8253 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8254 ahd_dump_card_state(list_ahd); 8255 } 8256 } 8257 8258 int 8259 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8260 const char *name, u_int address, u_int value, 8261 u_int *cur_column, u_int wrap_point) 8262 { 8263 int printed; 8264 u_int printed_mask; 8265 char line[1024]; 8266 8267 line[0] = 0; 8268 8269 if (cur_column != NULL && *cur_column >= wrap_point) { 8270 printf("\n"); 8271 *cur_column = 0; 8272 } 8273 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8274 if (table == NULL) { 8275 printed += snprintf(&line[printed], (sizeof line) - printed, 8276 " "); 8277 printf("%s", line); 8278 if (cur_column != NULL) 8279 *cur_column += printed; 8280 return (printed); 8281 } 8282 printed_mask = 0; 8283 while (printed_mask != 0xFF) { 8284 int entry; 8285 8286 for (entry = 0; entry < num_entries; entry++) { 8287 if (((value & table[entry].mask) 8288 != table[entry].value) 8289 || ((printed_mask & table[entry].mask) 8290 == table[entry].mask)) 8291 continue; 8292 printed += snprintf(&line[printed], 8293 (sizeof line) - printed, "%s%s", 8294 printed_mask == 0 ? ":(" : "|", 8295 table[entry].name); 8296 printed_mask |= table[entry].mask; 8297 8298 break; 8299 } 8300 if (entry >= num_entries) 8301 break; 8302 } 8303 if (printed_mask != 0) 8304 printed += snprintf(&line[printed], 8305 (sizeof line) - printed, ") "); 8306 else 8307 printed += snprintf(&line[printed], 8308 (sizeof line) - printed, " "); 8309 if (cur_column != NULL) 8310 *cur_column += printed; 8311 printf("%s", line); 8312 8313 return (printed); 8314 } 8315 8316 void 8317 ahd_dump_card_state(struct ahd_softc *ahd) 8318 { 8319 struct scb *scb; 8320 ahd_mode_state saved_modes; 8321 u_int dffstat; 8322 int paused; 8323 u_int scb_index; 8324 u_int saved_scb_index; 8325 u_int cur_col; 8326 int i; 8327 8328 if (ahd_is_paused(ahd)) { 8329 paused = 1; 8330 } else { 8331 paused = 0; 8332 ahd_pause(ahd); 8333 } 8334 saved_modes = ahd_save_modes(ahd); 8335 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8336 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8337 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8338 ahd_name(ahd), 8339 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8340 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8341 ahd->saved_dst_mode)); 8342 if (paused) 8343 printf("Card was paused\n"); 8344 /* 8345 * Mode independent registers. 8346 */ 8347 cur_col = 0; 8348 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8349 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8350 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8351 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8352 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8353 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8354 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8355 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8356 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8357 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8358 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8359 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8360 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8361 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8362 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8363 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8364 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8365 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8366 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8367 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8368 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8369 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8370 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8371 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8372 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8373 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8374 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8375 printf("\n"); 8376 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8377 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8378 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8379 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8380 ahd_inw(ahd, NEXTSCB)); 8381 cur_col = 0; 8382 /* QINFIFO */ 8383 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8384 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8385 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8386 saved_scb_index = ahd_get_scbptr(ahd); 8387 printf("Pending list:"); 8388 i = 0; 8389 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8390 if (i++ > AHD_SCB_MAX) 8391 break; 8392 /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8393 ahd_inb(ahd, SCB_FIFO_USE_COUNT)); 8394 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8395 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8396 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8397 } 8398 printf("\nTotal %d\n", i); 8399 8400 printf("Kernel Free SCB list: "); 8401 i = 0; 8402 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8403 struct scb *list_scb; 8404 8405 list_scb = scb; 8406 do { 8407 printf("%d ", SCB_GET_TAG(list_scb)); 8408 list_scb = LIST_NEXT(list_scb, collision_links); 8409 } while (list_scb && i++ < AHD_SCB_MAX); 8410 } 8411 8412 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8413 if (i++ > AHD_SCB_MAX) 8414 break; 8415 printf("%d ", SCB_GET_TAG(scb)); 8416 } 8417 printf("\n"); 8418 8419 printf("Sequencer Complete DMA-inprog list: "); 8420 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8421 i = 0; 8422 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8423 ahd_set_scbptr(ahd, scb_index); 8424 printf("%d ", scb_index); 8425 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8426 } 8427 printf("\n"); 8428 8429 printf("Sequencer Complete list: "); 8430 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8431 i = 0; 8432 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8433 ahd_set_scbptr(ahd, scb_index); 8434 printf("%d ", scb_index); 8435 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8436 } 8437 printf("\n"); 8438 8439 8440 printf("Sequencer DMA-Up and Complete list: "); 8441 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8442 i = 0; 8443 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8444 ahd_set_scbptr(ahd, scb_index); 8445 printf("%d ", scb_index); 8446 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8447 } 8448 printf("\n"); 8449 ahd_set_scbptr(ahd, saved_scb_index); 8450 dffstat = ahd_inb(ahd, DFFSTAT); 8451 for (i = 0; i < 2; i++) { 8452 #ifdef AHD_DEBUG 8453 struct scb *fifo_scb; 8454 #endif 8455 u_int fifo_scbptr; 8456 8457 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8458 fifo_scbptr = ahd_get_scbptr(ahd); 8459 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8460 ahd_name(ahd), i, 8461 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8462 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 8463 cur_col = 0; 8464 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8465 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8466 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8467 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8468 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8469 &cur_col, 50); 8470 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8471 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8472 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8473 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8474 if (cur_col > 50) { 8475 printf("\n"); 8476 cur_col = 0; 8477 } 8478 printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8479 ahd_inl(ahd, SHADDR+4), 8480 ahd_inl(ahd, SHADDR), 8481 (ahd_inb(ahd, SHCNT) 8482 | (ahd_inb(ahd, SHCNT + 1) << 8) 8483 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8484 printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8485 ahd_inl(ahd, HADDR+4), 8486 ahd_inl(ahd, HADDR), 8487 (ahd_inb(ahd, HCNT) 8488 | (ahd_inb(ahd, HCNT + 1) << 8) 8489 | (ahd_inb(ahd, HCNT + 2) << 16))); 8490 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8491 #ifdef AHD_DEBUG 8492 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8493 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8494 if (fifo_scb != NULL) 8495 ahd_dump_sglist(fifo_scb); 8496 } 8497 #endif 8498 } 8499 printf("\nLQIN: "); 8500 for (i = 0; i < 20; i++) 8501 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8502 printf("\n"); 8503 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8504 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8505 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8506 ahd_inb(ahd, OPTIONMODE)); 8507 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8508 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8509 ahd_inb(ahd, MAXCMDCNT)); 8510 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8511 printf("\n"); 8512 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8513 cur_col = 0; 8514 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8515 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8516 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8517 ahd_inw(ahd, DINDEX)); 8518 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8519 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8520 ahd_inw(ahd, SCB_NEXT2)); 8521 printf("CDB %x %x %x %x %x %x\n", 8522 ahd_inb(ahd, SCB_CDB_STORE), 8523 ahd_inb(ahd, SCB_CDB_STORE+1), 8524 ahd_inb(ahd, SCB_CDB_STORE+2), 8525 ahd_inb(ahd, SCB_CDB_STORE+3), 8526 ahd_inb(ahd, SCB_CDB_STORE+4), 8527 ahd_inb(ahd, SCB_CDB_STORE+5)); 8528 printf("STACK:"); 8529 for (i = 0; i < ahd->stack_size; i++) { 8530 ahd->saved_stack[i] = 8531 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8532 printf(" 0x%x", ahd->saved_stack[i]); 8533 } 8534 for (i = ahd->stack_size-1; i >= 0; i--) { 8535 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8536 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8537 } 8538 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8539 ahd_platform_dump_card_state(ahd); 8540 ahd_restore_modes(ahd, saved_modes); 8541 if (paused == 0) 8542 ahd_unpause(ahd); 8543 } 8544 8545 void 8546 ahd_dump_scbs(struct ahd_softc *ahd) 8547 { 8548 ahd_mode_state saved_modes; 8549 u_int saved_scb_index; 8550 int i; 8551 8552 saved_modes = ahd_save_modes(ahd); 8553 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8554 saved_scb_index = ahd_get_scbptr(ahd); 8555 for (i = 0; i < AHD_SCB_MAX; i++) { 8556 ahd_set_scbptr(ahd, i); 8557 printf("%3d", i); 8558 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8559 ahd_inb(ahd, SCB_CONTROL), 8560 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8561 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8562 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8563 } 8564 printf("\n"); 8565 ahd_set_scbptr(ahd, saved_scb_index); 8566 ahd_restore_modes(ahd, saved_modes); 8567 } 8568 8569 /**************************** Flexport Logic **********************************/ 8570 /* 8571 * Read count 16bit words from 16bit word address start_addr from the 8572 * SEEPROM attached to the controller, into buf, using the controller's 8573 * SEEPROM reading state machine. Optionally treat the data as a byte 8574 * stream in terms of byte order. 8575 */ 8576 int 8577 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8578 u_int start_addr, u_int count, int bytestream) 8579 { 8580 u_int cur_addr; 8581 u_int end_addr; 8582 int error; 8583 8584 /* 8585 * If we never make it through the loop even once, 8586 * we were passed invalid arguments. 8587 */ 8588 error = EINVAL; 8589 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8590 end_addr = start_addr + count; 8591 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8592 8593 ahd_outb(ahd, SEEADR, cur_addr); 8594 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8595 8596 error = ahd_wait_seeprom(ahd); 8597 if (error) { 8598 printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd)); 8599 break; 8600 } 8601 if (bytestream != 0) { 8602 uint8_t *bytestream_ptr; 8603 8604 bytestream_ptr = (uint8_t *)buf; 8605 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 8606 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 8607 } else { 8608 /* 8609 * ahd_inw() already handles machine byte order. 8610 */ 8611 *buf = ahd_inw(ahd, SEEDAT); 8612 } 8613 buf++; 8614 } 8615 return (error); 8616 } 8617 8618 /* 8619 * Write count 16bit words from buf, into SEEPROM attache to the 8620 * controller starting at 16bit word address start_addr, using the 8621 * controller's SEEPROM writing state machine. 8622 */ 8623 int 8624 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8625 u_int start_addr, u_int count) 8626 { 8627 u_int cur_addr; 8628 u_int end_addr; 8629 int error; 8630 int retval; 8631 8632 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8633 error = ENOENT; 8634 8635 /* Place the chip into write-enable mode */ 8636 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8637 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8638 error = ahd_wait_seeprom(ahd); 8639 if (error) 8640 return (error); 8641 8642 /* 8643 * Write the data. If we don't get throught the loop at 8644 * least once, the arguments were invalid. 8645 */ 8646 retval = EINVAL; 8647 end_addr = start_addr + count; 8648 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8649 ahd_outw(ahd, SEEDAT, *buf++); 8650 ahd_outb(ahd, SEEADR, cur_addr); 8651 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8652 8653 retval = ahd_wait_seeprom(ahd); 8654 if (retval) 8655 break; 8656 } 8657 8658 /* 8659 * Disable writes. 8660 */ 8661 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8662 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8663 error = ahd_wait_seeprom(ahd); 8664 if (error) 8665 return (error); 8666 return (retval); 8667 } 8668 8669 /* 8670 * Wait ~100us for the serial eeprom to satisfy our request. 8671 */ 8672 int 8673 ahd_wait_seeprom(struct ahd_softc *ahd) 8674 { 8675 int cnt; 8676 8677 cnt = 2000; 8678 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8679 ahd_delay(5); 8680 8681 if (cnt == 0) 8682 return (ETIMEDOUT); 8683 return (0); 8684 } 8685 8686 /* 8687 * Validate the two checksums in the per_channel 8688 * vital product data struct. 8689 */ 8690 int 8691 ahd_verify_vpd_cksum(struct vpd_config *vpd) 8692 { 8693 int i; 8694 int maxaddr; 8695 uint32_t checksum; 8696 uint8_t *vpdarray; 8697 8698 vpdarray = (uint8_t *)vpd; 8699 maxaddr = offsetof(struct vpd_config, vpd_checksum); 8700 checksum = 0; 8701 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 8702 checksum = checksum + vpdarray[i]; 8703 if (checksum == 0 8704 || (-checksum & 0xFF) != vpd->vpd_checksum) 8705 return (0); 8706 8707 checksum = 0; 8708 maxaddr = offsetof(struct vpd_config, checksum); 8709 for (i = offsetof(struct vpd_config, default_target_flags); 8710 i < maxaddr; i++) 8711 checksum = checksum + vpdarray[i]; 8712 if (checksum == 0 8713 || (-checksum & 0xFF) != vpd->checksum) 8714 return (0); 8715 return (1); 8716 } 8717 8718 int 8719 ahd_verify_cksum(struct seeprom_config *sc) 8720 { 8721 int i; 8722 int maxaddr; 8723 uint32_t checksum; 8724 uint16_t *scarray; 8725 8726 maxaddr = (sizeof(*sc)/2) - 1; 8727 checksum = 0; 8728 scarray = (uint16_t *)sc; 8729 8730 for (i = 0; i < maxaddr; i++) 8731 checksum = checksum + scarray[i]; 8732 if (checksum == 0 8733 || (checksum & 0xFFFF) != sc->checksum) { 8734 return (0); 8735 } else { 8736 return (1); 8737 } 8738 } 8739 8740 int 8741 ahd_acquire_seeprom(struct ahd_softc *ahd) 8742 { 8743 /* 8744 * We should be able to determine the SEEPROM type 8745 * from the flexport logic, but unfortunately not 8746 * all implementations have this logic and there is 8747 * no programatic method for determining if the logic 8748 * is present. 8749 */ 8750 8751 return (1); 8752 #if 0 8753 uint8_t seetype; 8754 int error; 8755 8756 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8757 if (error != 0 8758 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8759 return (0); 8760 return (1); 8761 #endif 8762 } 8763 8764 void 8765 ahd_release_seeprom(struct ahd_softc *ahd) 8766 { 8767 /* Currently a no-op */ 8768 } 8769 8770 int 8771 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8772 { 8773 int error; 8774 8775 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8776 if (addr > 7) 8777 panic("ahd_write_flexport: address out of range"); 8778 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8779 error = ahd_wait_flexport(ahd); 8780 if (error != 0) 8781 return (error); 8782 ahd_outb(ahd, BRDDAT, value); 8783 ahd_flush_device_writes(ahd); 8784 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8785 ahd_flush_device_writes(ahd); 8786 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8787 ahd_flush_device_writes(ahd); 8788 ahd_outb(ahd, BRDCTL, 0); 8789 ahd_flush_device_writes(ahd); 8790 return (0); 8791 } 8792 8793 int 8794 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8795 { 8796 int error; 8797 8798 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8799 if (addr > 7) 8800 panic("ahd_read_flexport: address out of range"); 8801 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8802 error = ahd_wait_flexport(ahd); 8803 if (error != 0) 8804 return (error); 8805 *value = ahd_inb(ahd, BRDDAT); 8806 ahd_outb(ahd, BRDCTL, 0); 8807 ahd_flush_device_writes(ahd); 8808 return (0); 8809 } 8810 8811 /* 8812 * Wait at most 2 seconds for flexport arbitration to succeed. 8813 */ 8814 int 8815 ahd_wait_flexport(struct ahd_softc *ahd) 8816 { 8817 int cnt; 8818 8819 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8820 cnt = 1000000 * 2 / 5; 8821 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8822 ahd_delay(5); 8823 8824 if (cnt == 0) 8825 return (ETIMEDOUT); 8826 return (0); 8827 } 8828 8829 /************************* Target Mode ****************************************/ 8830 #ifdef AHD_TARGET_MODE 8831 cam_status 8832 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8833 struct ahd_tmode_tstate **tstate, 8834 struct ahd_tmode_lstate **lstate, 8835 int notfound_failure) 8836 { 8837 8838 if ((ahd->features & AHD_TARGETMODE) == 0) 8839 return (CAM_REQ_INVALID); 8840 8841 /* 8842 * Handle the 'black hole' device that sucks up 8843 * requests to unattached luns on enabled targets. 8844 */ 8845 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8846 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8847 *tstate = NULL; 8848 *lstate = ahd->black_hole; 8849 } else { 8850 u_int max_id; 8851 8852 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8853 if (ccb->ccb_h.target_id > max_id) 8854 return (CAM_TID_INVALID); 8855 8856 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 8857 return (CAM_LUN_INVALID); 8858 8859 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 8860 *lstate = NULL; 8861 if (*tstate != NULL) 8862 *lstate = 8863 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 8864 } 8865 8866 if (notfound_failure != 0 && *lstate == NULL) 8867 return (CAM_PATH_INVALID); 8868 8869 return (CAM_REQ_CMP); 8870 } 8871 8872 void 8873 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 8874 { 8875 #if NOT_YET 8876 struct ahd_tmode_tstate *tstate; 8877 struct ahd_tmode_lstate *lstate; 8878 struct ccb_en_lun *cel; 8879 cam_status status; 8880 u_int target; 8881 u_int lun; 8882 u_int target_mask; 8883 u_long s; 8884 char channel; 8885 8886 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 8887 /*notfound_failure*/FALSE); 8888 8889 if (status != CAM_REQ_CMP) { 8890 ccb->ccb_h.status = status; 8891 return; 8892 } 8893 8894 if ((ahd->features & AHD_MULTIROLE) != 0) { 8895 u_int our_id; 8896 8897 our_id = ahd->our_id; 8898 if (ccb->ccb_h.target_id != our_id) { 8899 if ((ahd->features & AHD_MULTI_TID) != 0 8900 && (ahd->flags & AHD_INITIATORROLE) != 0) { 8901 /* 8902 * Only allow additional targets if 8903 * the initiator role is disabled. 8904 * The hardware cannot handle a re-select-in 8905 * on the initiator id during a re-select-out 8906 * on a different target id. 8907 */ 8908 status = CAM_TID_INVALID; 8909 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 8910 || ahd->enabled_luns > 0) { 8911 /* 8912 * Only allow our target id to change 8913 * if the initiator role is not configured 8914 * and there are no enabled luns which 8915 * are attached to the currently registered 8916 * scsi id. 8917 */ 8918 status = CAM_TID_INVALID; 8919 } 8920 } 8921 } 8922 8923 if (status != CAM_REQ_CMP) { 8924 ccb->ccb_h.status = status; 8925 return; 8926 } 8927 8928 /* 8929 * We now have an id that is valid. 8930 * If we aren't in target mode, switch modes. 8931 */ 8932 if ((ahd->flags & AHD_TARGETROLE) == 0 8933 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 8934 u_long s; 8935 8936 printf("Configuring Target Mode\n"); 8937 ahd_lock(ahd, &s); 8938 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 8939 ccb->ccb_h.status = CAM_BUSY; 8940 ahd_unlock(ahd, &s); 8941 return; 8942 } 8943 ahd->flags |= AHD_TARGETROLE; 8944 if ((ahd->features & AHD_MULTIROLE) == 0) 8945 ahd->flags &= ~AHD_INITIATORROLE; 8946 ahd_pause(ahd); 8947 ahd_loadseq(ahd); 8948 ahd_restart(ahd); 8949 ahd_unlock(ahd, &s); 8950 } 8951 cel = &ccb->cel; 8952 target = ccb->ccb_h.target_id; 8953 lun = ccb->ccb_h.target_lun; 8954 channel = SIM_CHANNEL(ahd, sim); 8955 target_mask = 0x01 << target; 8956 if (channel == 'B') 8957 target_mask <<= 8; 8958 8959 if (cel->enable != 0) { 8960 u_int scsiseq1; 8961 8962 /* Are we already enabled?? */ 8963 if (lstate != NULL) { 8964 xpt_print_path(ccb->ccb_h.path); 8965 printf("Lun already enabled\n"); 8966 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 8967 return; 8968 } 8969 8970 if (cel->grp6_len != 0 8971 || cel->grp7_len != 0) { 8972 /* 8973 * Don't (yet?) support vendor 8974 * specific commands. 8975 */ 8976 ccb->ccb_h.status = CAM_REQ_INVALID; 8977 printf("Non-zero Group Codes\n"); 8978 return; 8979 } 8980 8981 /* 8982 * Seems to be okay. 8983 * Setup our data structures. 8984 */ 8985 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 8986 tstate = ahd_alloc_tstate(ahd, target, channel); 8987 if (tstate == NULL) { 8988 xpt_print_path(ccb->ccb_h.path); 8989 printf("Couldn't allocate tstate\n"); 8990 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8991 return; 8992 } 8993 } 8994 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 8995 if (lstate == NULL) { 8996 xpt_print_path(ccb->ccb_h.path); 8997 printf("Couldn't allocate lstate\n"); 8998 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 8999 return; 9000 } 9001 memset(lstate, 0, sizeof(*lstate)); 9002 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9003 xpt_path_path_id(ccb->ccb_h.path), 9004 xpt_path_target_id(ccb->ccb_h.path), 9005 xpt_path_lun_id(ccb->ccb_h.path)); 9006 if (status != CAM_REQ_CMP) { 9007 free(lstate, M_DEVBUF); 9008 xpt_print_path(ccb->ccb_h.path); 9009 printf("Couldn't allocate path\n"); 9010 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9011 return; 9012 } 9013 SLIST_INIT(&lstate->accept_tios); 9014 SLIST_INIT(&lstate->immed_notifies); 9015 ahd_lock(ahd, &s); 9016 ahd_pause(ahd); 9017 if (target != CAM_TARGET_WILDCARD) { 9018 tstate->enabled_luns[lun] = lstate; 9019 ahd->enabled_luns++; 9020 9021 if ((ahd->features & AHD_MULTI_TID) != 0) { 9022 u_int targid_mask; 9023 9024 targid_mask = ahd_inb(ahd, TARGID) 9025 | (ahd_inb(ahd, TARGID + 1) << 8); 9026 9027 targid_mask |= target_mask; 9028 ahd_outb(ahd, TARGID, targid_mask); 9029 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9030 9031 ahd_update_scsiid(ahd, targid_mask); 9032 } else { 9033 u_int our_id; 9034 char channel; 9035 9036 channel = SIM_CHANNEL(ahd, sim); 9037 our_id = SIM_SCSI_ID(ahd, sim); 9038 9039 /* 9040 * This can only happen if selections 9041 * are not enabled 9042 */ 9043 if (target != our_id) { 9044 u_int sblkctl; 9045 char cur_channel; 9046 int swap; 9047 9048 sblkctl = ahd_inb(ahd, SBLKCTL); 9049 cur_channel = (sblkctl & SELBUSB) 9050 ? 'B' : 'A'; 9051 if ((ahd->features & AHD_TWIN) == 0) 9052 cur_channel = 'A'; 9053 swap = cur_channel != channel; 9054 ahd->our_id = target; 9055 9056 if (swap) 9057 ahd_outb(ahd, SBLKCTL, 9058 sblkctl ^ SELBUSB); 9059 9060 ahd_outb(ahd, SCSIID, target); 9061 9062 if (swap) 9063 ahd_outb(ahd, SBLKCTL, sblkctl); 9064 } 9065 } 9066 } else 9067 ahd->black_hole = lstate; 9068 /* Allow select-in operations */ 9069 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9070 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9071 scsiseq1 |= ENSELI; 9072 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9073 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9074 scsiseq1 |= ENSELI; 9075 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9076 } 9077 ahd_unpause(ahd); 9078 ahd_unlock(ahd, &s); 9079 ccb->ccb_h.status = CAM_REQ_CMP; 9080 xpt_print_path(ccb->ccb_h.path); 9081 printf("Lun now enabled for target mode\n"); 9082 } else { 9083 struct scb *scb; 9084 int i, empty; 9085 9086 if (lstate == NULL) { 9087 ccb->ccb_h.status = CAM_LUN_INVALID; 9088 return; 9089 } 9090 9091 ahd_lock(ahd, &s); 9092 9093 ccb->ccb_h.status = CAM_REQ_CMP; 9094 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9095 struct ccb_hdr *ccbh; 9096 9097 ccbh = &scb->io_ctx->ccb_h; 9098 if (ccbh->func_code == XPT_CONT_TARGET_IO 9099 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9100 printf("CTIO pending\n"); 9101 ccb->ccb_h.status = CAM_REQ_INVALID; 9102 ahd_unlock(ahd, &s); 9103 return; 9104 } 9105 } 9106 9107 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9108 printf("ATIOs pending\n"); 9109 ccb->ccb_h.status = CAM_REQ_INVALID; 9110 } 9111 9112 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9113 printf("INOTs pending\n"); 9114 ccb->ccb_h.status = CAM_REQ_INVALID; 9115 } 9116 9117 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9118 ahd_unlock(ahd, &s); 9119 return; 9120 } 9121 9122 xpt_print_path(ccb->ccb_h.path); 9123 printf("Target mode disabled\n"); 9124 xpt_free_path(lstate->path); 9125 free(lstate, M_DEVBUF); 9126 9127 ahd_pause(ahd); 9128 /* Can we clean up the target too? */ 9129 if (target != CAM_TARGET_WILDCARD) { 9130 tstate->enabled_luns[lun] = NULL; 9131 ahd->enabled_luns--; 9132 for (empty = 1, i = 0; i < 8; i++) 9133 if (tstate->enabled_luns[i] != NULL) { 9134 empty = 0; 9135 break; 9136 } 9137 9138 if (empty) { 9139 ahd_free_tstate(ahd, target, channel, 9140 /*force*/FALSE); 9141 if (ahd->features & AHD_MULTI_TID) { 9142 u_int targid_mask; 9143 9144 targid_mask = ahd_inb(ahd, TARGID) 9145 | (ahd_inb(ahd, TARGID + 1) 9146 << 8); 9147 9148 targid_mask &= ~target_mask; 9149 ahd_outb(ahd, TARGID, targid_mask); 9150 ahd_outb(ahd, TARGID+1, 9151 (targid_mask >> 8)); 9152 ahd_update_scsiid(ahd, targid_mask); 9153 } 9154 } 9155 } else { 9156 9157 ahd->black_hole = NULL; 9158 9159 /* 9160 * We can't allow selections without 9161 * our black hole device. 9162 */ 9163 empty = TRUE; 9164 } 9165 if (ahd->enabled_luns == 0) { 9166 /* Disallow select-in */ 9167 u_int scsiseq1; 9168 9169 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9170 scsiseq1 &= ~ENSELI; 9171 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9172 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9173 scsiseq1 &= ~ENSELI; 9174 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9175 9176 if ((ahd->features & AHD_MULTIROLE) == 0) { 9177 printf("Configuring Initiator Mode\n"); 9178 ahd->flags &= ~AHD_TARGETROLE; 9179 ahd->flags |= AHD_INITIATORROLE; 9180 ahd_pause(ahd); 9181 ahd_loadseq(ahd); 9182 ahd_restart(ahd); 9183 /* 9184 * Unpaused. The extra unpause 9185 * that follows is harmless. 9186 */ 9187 } 9188 } 9189 ahd_unpause(ahd); 9190 ahd_unlock(ahd, &s); 9191 } 9192 #endif 9193 } 9194 9195 static void 9196 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9197 { 9198 #if NOT_YET 9199 u_int scsiid_mask; 9200 u_int scsiid; 9201 9202 if ((ahd->features & AHD_MULTI_TID) == 0) 9203 panic("ahd_update_scsiid called on non-multitid unit\n"); 9204 9205 /* 9206 * Since we will rely on the TARGID mask 9207 * for selection enables, ensure that OID 9208 * in SCSIID is not set to some other ID 9209 * that we don't want to allow selections on. 9210 */ 9211 if ((ahd->features & AHD_ULTRA2) != 0) 9212 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9213 else 9214 scsiid = ahd_inb(ahd, SCSIID); 9215 scsiid_mask = 0x1 << (scsiid & OID); 9216 if ((targid_mask & scsiid_mask) == 0) { 9217 u_int our_id; 9218 9219 /* ffs counts from 1 */ 9220 our_id = ffs(targid_mask); 9221 if (our_id == 0) 9222 our_id = ahd->our_id; 9223 else 9224 our_id--; 9225 scsiid &= TID; 9226 scsiid |= our_id; 9227 } 9228 if ((ahd->features & AHD_ULTRA2) != 0) 9229 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9230 else 9231 ahd_outb(ahd, SCSIID, scsiid); 9232 #endif 9233 } 9234 9235 #ifdef AHD_TARGET_MODE 9236 void 9237 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9238 { 9239 struct target_cmd *cmd; 9240 9241 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9242 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9243 9244 /* 9245 * Only advance through the queue if we 9246 * have the resources to process the command. 9247 */ 9248 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9249 break; 9250 9251 cmd->cmd_valid = 0; 9252 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9253 ahd->shared_data_map.dmamap, 9254 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9255 sizeof(struct target_cmd), 9256 BUS_DMASYNC_PREREAD); 9257 ahd->tqinfifonext++; 9258 9259 /* 9260 * Lazily update our position in the target mode incoming 9261 * command queue as seen by the sequencer. 9262 */ 9263 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9264 u_int hs_mailbox; 9265 9266 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9267 hs_mailbox &= ~HOST_TQINPOS; 9268 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9269 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9270 } 9271 } 9272 } 9273 #endif 9274 9275 static int 9276 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9277 { 9278 struct ahd_tmode_tstate *tstate; 9279 struct ahd_tmode_lstate *lstate; 9280 struct ccb_accept_tio *atio; 9281 uint8_t *byte; 9282 int initiator; 9283 int target; 9284 int lun; 9285 9286 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9287 target = SCSIID_OUR_ID(cmd->scsiid); 9288 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9289 9290 byte = cmd->bytes; 9291 tstate = ahd->enabled_targets[target]; 9292 lstate = NULL; 9293 if (tstate != NULL) 9294 lstate = tstate->enabled_luns[lun]; 9295 9296 /* 9297 * Commands for disabled luns go to the black hole driver. 9298 */ 9299 if (lstate == NULL) 9300 lstate = ahd->black_hole; 9301 9302 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9303 if (atio == NULL) { 9304 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9305 /* 9306 * Wait for more ATIOs from the peripheral driver for this lun. 9307 */ 9308 return (1); 9309 } else 9310 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9311 #ifdef AHD_DEBUG 9312 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9313 printf("%s: incoming command from %d for %d:%d%s\n", 9314 ahd_name(ahd), 9315 initiator, target, lun, 9316 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9317 #endif 9318 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9319 9320 if (lstate == ahd->black_hole) { 9321 /* Fill in the wildcards */ 9322 atio->ccb_h.target_id = target; 9323 atio->ccb_h.target_lun = lun; 9324 } 9325 9326 /* 9327 * Package it up and send it off to 9328 * whomever has this lun enabled. 9329 */ 9330 atio->sense_len = 0; 9331 atio->init_id = initiator; 9332 if (byte[0] != 0xFF) { 9333 /* Tag was included */ 9334 atio->tag_action = *byte++; 9335 atio->tag_id = *byte++; 9336 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9337 } else { 9338 atio->ccb_h.flags = 0; 9339 } 9340 byte++; 9341 9342 /* Okay. Now determine the cdb size based on the command code */ 9343 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9344 case 0: 9345 atio->cdb_len = 6; 9346 break; 9347 case 1: 9348 case 2: 9349 atio->cdb_len = 10; 9350 break; 9351 case 4: 9352 atio->cdb_len = 16; 9353 break; 9354 case 5: 9355 atio->cdb_len = 12; 9356 break; 9357 case 3: 9358 default: 9359 /* Only copy the opcode. */ 9360 atio->cdb_len = 1; 9361 printf("Reserved or VU command code type encountered\n"); 9362 break; 9363 } 9364 9365 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9366 9367 atio->ccb_h.status |= CAM_CDB_RECVD; 9368 9369 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9370 /* 9371 * We weren't allowed to disconnect. 9372 * We're hanging on the bus until a 9373 * continue target I/O comes in response 9374 * to this accept tio. 9375 */ 9376 #ifdef AHD_DEBUG 9377 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9378 printf("Received Immediate Command %d:%d:%d - %p\n", 9379 initiator, target, lun, ahd->pending_device); 9380 #endif 9381 ahd->pending_device = lstate; 9382 ahd_freeze_ccb((union ccb *)atio); 9383 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9384 } 9385 xpt_done((union ccb*)atio); 9386 return (0); 9387 } 9388 9389 #endif 9390 9391 static int 9392 ahd_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 9393 bus_dma_tag_t tag; 9394 int size; 9395 int flags; 9396 bus_dmamap_t *mapp; 9397 caddr_t *vaddr; 9398 bus_addr_t *baddr; 9399 bus_dma_segment_t *seg; 9400 int *nseg; 9401 const char *myname, *what; 9402 { 9403 int error, level = 0; 9404 9405 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9406 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 9407 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9408 myname, what, error); 9409 goto out; 9410 } 9411 level++; 9412 9413 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9414 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 9415 printf("%s: failed to map DMA mem for %s, error = %d\n", 9416 myname, what, error); 9417 goto out; 9418 } 9419 level++; 9420 9421 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9422 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 9423 printf("%s: failed to create DMA map for %s, error = %d\n", 9424 myname, what, error); 9425 goto out; 9426 } 9427 level++; 9428 9429 9430 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9431 BUS_DMA_NOWAIT)) != 0) { 9432 printf("%s: failed to load DMA map for %s, error = %d\n", 9433 myname, what, error); 9434 goto out; 9435 } 9436 9437 *baddr = (*mapp)->dm_segs[0].ds_addr; 9438 9439 return 0; 9440 out: 9441 printf("ahd_createdmamem error (%d)\n", level); 9442 switch (level) { 9443 case 3: 9444 bus_dmamap_destroy(tag, *mapp); 9445 /* FALLTHROUGH */ 9446 case 2: 9447 bus_dmamem_unmap(tag, *vaddr, size); 9448 /* FALLTHROUGH */ 9449 case 1: 9450 bus_dmamem_free(tag, seg, *nseg); 9451 break; 9452 default: 9453 break; 9454 } 9455 9456 return error; 9457 } 9458 9459 static void 9460 ahd_freedmamem(tag, size, map, vaddr, seg, nseg) 9461 bus_dma_tag_t tag; 9462 int size; 9463 bus_dmamap_t map; 9464 caddr_t vaddr; 9465 bus_dma_segment_t *seg; 9466 int nseg; 9467 { 9468 9469 bus_dmamap_unload(tag, map); 9470 bus_dmamap_destroy(tag, map); 9471 bus_dmamem_unmap(tag, vaddr, size); 9472 bus_dmamem_free(tag, seg, nseg); 9473 } 9474 9475 static void 9476 ahd_update_xfer_mode(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 9477 { 9478 struct scsipi_xfer_mode xm; 9479 struct ahd_initiator_tinfo *tinfo; 9480 struct ahd_tmode_tstate *tstate; 9481 9482 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 9483 devinfo->target, &tstate); 9484 9485 xm.xm_target = devinfo->target; 9486 xm.xm_mode = 0; 9487 xm.xm_period = tinfo->curr.period; 9488 xm.xm_offset = tinfo->curr.offset; 9489 if (tinfo->curr.width == 1) 9490 xm.xm_mode |= PERIPH_CAP_WIDE16; 9491 if (tinfo->curr.period) 9492 xm.xm_mode |= PERIPH_CAP_SYNC; 9493 if (tinfo->curr.ppr_options & MSG_EXT_PPR_DT_REQ) 9494 xm.xm_mode |= PERIPH_CAP_DT; 9495 if (tstate->tagenable & devinfo->target_mask) 9496 xm.xm_mode |= PERIPH_CAP_TQING; 9497 9498 tinfo->goal.width = tinfo->curr.width; 9499 tinfo->goal.period = tinfo->curr.period; 9500 tinfo->goal.offset = tinfo->curr.offset; 9501 tinfo->goal.ppr_options = tinfo->curr.ppr_options; 9502 9503 ahd_update_neg_request(ahd, devinfo, tstate, 9504 tinfo, AHD_NEG_TO_GOAL); 9505 9506 scsipi_async_event(&ahd->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 9507 } 9508
Indexes created Mon Sep 29 21:09:56 GMT 2025