aic79xx.c revision 1.31
1 /* $NetBSD: aic79xx.c,v 1.31 2005/05/30 04:43:46 christos Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#202 $ 43 * 44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.24 2003/06/28 04:46:54 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 48 * - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: aic79xx.c,v 1.31 2005/05/30 04:43:46 christos Exp $"); 53 54 #include <dev/ic/aic79xx_osm.h> 55 #include <dev/ic/aic79xx_inline.h> 56 #include <dev/ic/aic7xxx_cam.h> 57 58 #include <dev/microcode/aic7xxx/aicasm.h> 59 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 60 61 62 /******************************** Globals *************************************/ 63 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 64 65 /***************************** Lookup Tables **********************************/ 66 const char *ahd_chip_names[] = 67 { 68 "NONE", 69 "aic7901", 70 "aic7902", 71 "aic7901A" 72 }; 73 74 /* 75 * Hardware error codes. 76 */ 77 struct ahd_hard_error_entry { 78 uint8_t errno; 79 const char *errmesg; 80 }; 81 82 static struct ahd_hard_error_entry ahd_hard_errors[] = { 83 { DSCTMOUT, "Discard Timer has timed out" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { CIOPARERR, "CIOBUS Parity Error" }, 89 }; 90 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 91 92 static struct ahd_phase_table_entry ahd_phase_table[] = 93 { 94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 96 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 97 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 98 { P_COMMAND, MSG_NOOP, "in Command phase" }, 99 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 100 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 101 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 102 { P_BUSFREE, MSG_NOOP, "while idle" }, 103 { 0, MSG_NOOP, "in unknown phase" } 104 }; 105 106 /* 107 * In most cases we only wish to itterate over real phases, so 108 * exclude the last element from the count. 109 */ 110 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 111 112 /* Our Sequencer Program */ 113 #include <dev/microcode/aic7xxx/aic79xx_seq.h> 114 115 /**************************** Function Declarations ***************************/ 116 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 117 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 118 u_int lqistat1); 119 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 120 u_int busfreetime); 121 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 122 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 123 static void ahd_force_renegotiation(struct ahd_softc *ahd, 124 struct ahd_devinfo *devinfo); 125 126 static struct ahd_tmode_tstate* 127 ahd_alloc_tstate(struct ahd_softc *ahd, 128 u_int scsi_id, char channel); 129 #ifdef AHD_TARGET_MODE 130 static void ahd_free_tstate(struct ahd_softc *ahd, 131 u_int scsi_id, char channel, int force); 132 #endif 133 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 134 struct ahd_initiator_tinfo *, 135 u_int *period, 136 u_int *ppr_options, 137 role_t role); 138 static void ahd_update_neg_table(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct ahd_transinfo *tinfo); 141 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 142 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo); 144 static void ahd_scb_devinfo(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo, 146 struct scb *scb); 147 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 struct scb *scb); 150 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo); 152 static void ahd_construct_sdtr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset); 155 static void ahd_construct_wdtr(struct ahd_softc *ahd, 156 struct ahd_devinfo *devinfo, 157 u_int bus_width); 158 static void ahd_construct_ppr(struct ahd_softc *ahd, 159 struct ahd_devinfo *devinfo, 160 u_int period, u_int offset, 161 u_int bus_width, u_int ppr_options); 162 static void ahd_clear_msg_state(struct ahd_softc *ahd); 163 static void ahd_handle_message_phase(struct ahd_softc *ahd); 164 typedef enum { 165 AHDMSG_1B, 166 AHDMSG_2B, 167 AHDMSG_EXT 168 } ahd_msgtype; 169 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 170 u_int msgval, int full); 171 static int ahd_parse_msg(struct ahd_softc *ahd, 172 struct ahd_devinfo *devinfo); 173 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo); 175 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 176 struct ahd_devinfo *devinfo); 177 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 178 static void ahd_handle_devreset(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 u_int lun, cam_status status, 181 const char *message, 182 int verbose_level); 183 #if AHD_TARGET_MODE 184 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 185 struct ahd_devinfo *devinfo, 186 struct scb *scb); 187 #endif 188 189 static u_int ahd_sglist_size(struct ahd_softc *ahd); 190 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 191 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 192 static int ahd_init_scbdata(struct ahd_softc *ahd); 193 static void ahd_fini_scbdata(struct ahd_softc *ahd); 194 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 195 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 196 static void ahd_add_col_list(struct ahd_softc *ahd, 197 struct scb *scb, u_int col_idx); 198 static void ahd_rem_col_list(struct ahd_softc *ahd, 199 struct scb *scb); 200 static void ahd_chip_init(struct ahd_softc *ahd); 201 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 202 struct scb *prev_scb, 203 struct scb *scb); 204 static int ahd_qinfifo_count(struct ahd_softc *ahd); 205 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 206 char channel, int lun, u_int tag, 207 role_t role, uint32_t status, 208 ahd_search_action action, 209 u_int *list_head, u_int tid); 210 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 211 u_int tid_prev, u_int tid_cur, 212 u_int tid_next); 213 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 214 u_int scbid); 215 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 216 u_int prev, u_int next, u_int tid); 217 static void ahd_reset_current_bus(struct ahd_softc *ahd); 218 static ahd_callback_t ahd_reset_poll; 219 static ahd_callback_t ahd_stat_timer; 220 #ifdef AHD_DUMP_SEQ 221 static void ahd_dumpseq(struct ahd_softc *ahd); 222 #endif 223 static void ahd_loadseq(struct ahd_softc *ahd); 224 static int ahd_check_patch(struct ahd_softc *ahd, 225 struct patch **start_patch, 226 u_int start_instr, u_int *skip_addr); 227 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 228 u_int address); 229 static void ahd_download_instr(struct ahd_softc *ahd, 230 u_int instrptr, uint8_t *dconsts); 231 static int ahd_probe_stack_size(struct ahd_softc *ahd); 232 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 233 struct scb *scb); 234 static void ahd_run_data_fifo(struct ahd_softc *ahd, 235 struct scb *scb); 236 237 #ifdef AHD_TARGET_MODE 238 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 239 struct ahd_tmode_lstate *lstate, 240 u_int initiator_id, 241 u_int event_type, 242 u_int event_arg); 243 static void ahd_update_scsiid(struct ahd_softc *ahd, 244 u_int targid_mask); 245 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 246 struct target_cmd *cmd); 247 #endif 248 249 /************************** Added for porting to NetBSD ***********************/ 250 static int ahd_createdmamem(bus_dma_tag_t tag, 251 int size, 252 int flags, 253 bus_dmamap_t *mapp, 254 caddr_t *vaddr, 255 bus_addr_t *baddr, 256 bus_dma_segment_t *seg, 257 int *nseg, 258 const char *myname, const char *what); 259 260 static void ahd_freedmamem(bus_dma_tag_t tag, 261 int size, 262 bus_dmamap_t map, 263 caddr_t vaddr, 264 bus_dma_segment_t *seg, 265 int nseg); 266 267 /******************************** Private Inlines *****************************/ 268 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 269 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 270 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 271 272 static __inline void 273 ahd_assert_atn(struct ahd_softc *ahd) 274 { 275 ahd_outb(ahd, SCSISIGO, ATNO); 276 } 277 278 /* 279 * Determine if the current connection has a packetized 280 * agreement. This does not necessarily mean that we 281 * are currently in a packetized transfer. We could 282 * just as easily be sending or receiving a message. 283 */ 284 static __inline int 285 ahd_currently_packetized(struct ahd_softc *ahd) 286 { 287 ahd_mode_state saved_modes; 288 int packetized; 289 290 saved_modes = ahd_save_modes(ahd); 291 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 292 /* 293 * The packetized bit refers to the last 294 * connection, not the current one. Check 295 * for non-zero LQISTATE instead. 296 */ 297 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 298 packetized = ahd_inb(ahd, LQISTATE) != 0; 299 } else { 300 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 301 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 302 } 303 ahd_restore_modes(ahd, saved_modes); 304 return (packetized); 305 } 306 307 static __inline int 308 ahd_set_active_fifo(struct ahd_softc *ahd) 309 { 310 u_int active_fifo; 311 312 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 313 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 314 switch (active_fifo) { 315 case 0: 316 case 1: 317 ahd_set_modes(ahd, active_fifo, active_fifo); 318 return (1); 319 default: 320 return (0); 321 } 322 } 323 324 /************************* Sequencer Execution Control ************************/ 325 /* 326 * Restart the sequencer program from address zero 327 */ 328 void 329 ahd_restart(struct ahd_softc *ahd) 330 { 331 332 ahd_pause(ahd); 333 334 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 335 336 /* No more pending messages */ 337 ahd_clear_msg_state(ahd); 338 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 339 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 340 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 341 ahd_outb(ahd, SEQINTCTL, 0); 342 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 343 ahd_outb(ahd, SEQ_FLAGS, 0); 344 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 345 ahd_outb(ahd, SAVED_LUN, 0xFF); 346 347 /* 348 * Ensure that the sequencer's idea of TQINPOS 349 * matches our own. The sequencer increments TQINPOS 350 * only after it sees a DMA complete and a reset could 351 * occur before the increment leaving the kernel to believe 352 * the command arrived but the sequencer to not. 353 */ 354 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 355 356 /* Always allow reselection */ 357 ahd_outb(ahd, SCSISEQ1, 358 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 359 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 360 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 361 ahd_unpause(ahd); 362 } 363 364 void 365 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 366 { 367 ahd_mode_state saved_modes; 368 369 #ifdef AHD_DEBUG 370 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 371 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 372 #endif 373 saved_modes = ahd_save_modes(ahd); 374 ahd_set_modes(ahd, fifo, fifo); 375 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 376 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 377 ahd_outb(ahd, CCSGCTL, CCSGRESET); 378 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 379 ahd_outb(ahd, SG_STATE, 0); 380 ahd_restore_modes(ahd, saved_modes); 381 } 382 383 /************************* Input/Output Queues ********************************/ 384 /* 385 * Flush and completed commands that are sitting in the command 386 * complete queues down on the chip but have yet to be DMA'ed back up. 387 */ 388 void 389 ahd_flush_qoutfifo(struct ahd_softc *ahd) 390 { 391 struct scb *scb; 392 ahd_mode_state saved_modes; 393 u_int saved_scbptr; 394 u_int ccscbctl; 395 u_int scbid; 396 u_int next_scbid; 397 398 saved_modes = ahd_save_modes(ahd); 399 400 /* 401 * Complete any SCBs that just finished being 402 * DMA'ed into the qoutfifo. 403 */ 404 ahd_run_qoutfifo(ahd); 405 406 /* 407 * Flush the good status FIFO for compelted packetized commands. 408 */ 409 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 410 saved_scbptr = ahd_get_scbptr(ahd); 411 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 412 u_int fifo_mode; 413 u_int i; 414 415 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 416 | ahd_inb(ahd, GSFIFO); 417 scb = ahd_lookup_scb(ahd, scbid); 418 if (scb == NULL) { 419 printf("%s: Warning - GSFIFO SCB %d invalid\n", 420 ahd_name(ahd), scbid); 421 continue; 422 } 423 /* 424 * Determine if this transaction is still active in 425 * any FIFO. If it is, we must flush that FIFO to 426 * the host before completing the command. 427 */ 428 fifo_mode = 0; 429 for (i = 0; i < 2; i++) { 430 /* Toggle to the other mode. */ 431 fifo_mode ^= 1; 432 ahd_set_modes(ahd, fifo_mode, fifo_mode); 433 if (ahd_scb_active_in_fifo(ahd, scb) == 0) 434 continue; 435 436 ahd_run_data_fifo(ahd, scb); 437 438 /* 439 * Clearing this transaction in this FIFO may 440 * cause a CFG4DATA for this same transaction 441 * to assert in the other FIFO. Make sure we 442 * loop one more time and check the other FIFO. 443 */ 444 i = 0; 445 } 446 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 447 ahd_set_scbptr(ahd, scbid); 448 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 449 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 450 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 451 & SG_LIST_NULL) != 0)) { 452 u_int comp_head; 453 454 /* 455 * The transfer completed with a residual. 456 * Place this SCB on the complete DMA list 457 * so that we Update our in-core copy of the 458 * SCB before completing the command. 459 */ 460 ahd_outb(ahd, SCB_SCSI_STATUS, 0); 461 ahd_outb(ahd, SCB_SGPTR, 462 ahd_inb_scbram(ahd, SCB_SGPTR) 463 | SG_STATUS_VALID); 464 ahd_outw(ahd, SCB_TAG, SCB_GET_TAG(scb)); 465 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 466 ahd_outw(ahd, SCB_NEXT_COMPLETE, comp_head); 467 if (SCBID_IS_NULL(comp_head)) 468 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, 469 SCB_GET_TAG(scb)); 470 } else 471 ahd_complete_scb(ahd, scb); 472 } 473 ahd_set_scbptr(ahd, saved_scbptr); 474 475 /* 476 * Setup for command channel portion of flush. 477 */ 478 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 479 480 /* 481 * Wait for any inprogress DMA to complete and clear DMA state 482 * if this if for an SCB in the qinfifo. 483 */ 484 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 485 486 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 487 if ((ccscbctl & ARRDONE) != 0) 488 break; 489 } else if ((ccscbctl & CCSCBDONE) != 0) 490 break; 491 ahd_delay(200); 492 } 493 if ((ccscbctl & CCSCBDIR) != 0) 494 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 495 496 saved_scbptr = ahd_get_scbptr(ahd); 497 /* 498 * Manually update/complete any completed SCBs that are waiting to be 499 * DMA'ed back up to the host. 500 */ 501 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 502 while (!SCBID_IS_NULL(scbid)) { 503 uint8_t *hscb_ptr; 504 u_int i; 505 506 ahd_set_scbptr(ahd, scbid); 507 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 508 scb = ahd_lookup_scb(ahd, scbid); 509 if (scb == NULL) { 510 printf("%s: Warning - DMA-up and complete " 511 "SCB %d invalid\n", ahd_name(ahd), scbid); 512 continue; 513 } 514 hscb_ptr = (uint8_t *)scb->hscb; 515 for (i = 0; i < sizeof(struct hardware_scb); i++) 516 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 517 518 ahd_complete_scb(ahd, scb); 519 scbid = next_scbid; 520 } 521 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 522 523 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 524 while (!SCBID_IS_NULL(scbid)) { 525 526 ahd_set_scbptr(ahd, scbid); 527 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 528 scb = ahd_lookup_scb(ahd, scbid); 529 if (scb == NULL) { 530 printf("%s: Warning - Complete SCB %d invalid\n", 531 ahd_name(ahd), scbid); 532 continue; 533 } 534 535 ahd_complete_scb(ahd, scb); 536 scbid = next_scbid; 537 } 538 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 539 540 /* 541 * Restore state. 542 */ 543 ahd_set_scbptr(ahd, saved_scbptr); 544 ahd_restore_modes(ahd, saved_modes); 545 ahd->flags |= AHD_UPDATE_PEND_CMDS; 546 } 547 548 /* 549 * Determine if an SCB for a packetized transaction 550 * is active in a FIFO. 551 */ 552 static int 553 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 554 { 555 556 /* 557 * The FIFO is only active for our transaction if 558 * the SCBPTR matches the SCB's ID and the firmware 559 * has installed a handler for the FIFO or we have 560 * a pending SAVEPTRS or CFG4DATA interrupt. 561 */ 562 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 563 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 564 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 565 return (0); 566 567 return (1); 568 } 569 570 /* 571 * Run a data fifo to completion for a transaction we know 572 * has completed across the SCSI bus (good status has been 573 * received). We are already set to the correct FIFO mode 574 * on entry to this routine. 575 * 576 * This function attempts to operate exactly as the firmware 577 * would when running this FIFO. Care must be taken to update 578 * this routine any time the firmware's FIFO algorithm is 579 * changed. 580 */ 581 static void 582 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 583 { 584 u_int seqintsrc; 585 586 while (1) { 587 seqintsrc = ahd_inb(ahd, SEQINTSRC); 588 if ((seqintsrc & CFG4DATA) != 0) { 589 uint32_t datacnt; 590 uint32_t sgptr; 591 592 /* 593 * Clear full residual flag. 594 */ 595 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 596 ahd_outb(ahd, SCB_SGPTR, sgptr); 597 598 /* 599 * Load datacnt and address. 600 */ 601 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 602 if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 603 sgptr |= LAST_SEG; 604 ahd_outb(ahd, SG_STATE, 0); 605 } else 606 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 607 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 608 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 609 ahd_outb(ahd, SG_CACHE_PRE, sgptr); 610 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 611 612 /* 613 * Initialize Residual Fields. 614 */ 615 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 616 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 617 618 /* 619 * Mark the SCB as having a FIFO in use. 620 */ 621 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 622 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 623 624 /* 625 * Install a "fake" handler for this FIFO. 626 */ 627 ahd_outw(ahd, LONGJMP_ADDR, 0); 628 629 /* 630 * Notify the hardware that we have satisfied 631 * this sequencer interrupt. 632 */ 633 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 634 } else if ((seqintsrc & SAVEPTRS) != 0) { 635 uint32_t sgptr; 636 uint32_t resid; 637 638 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 639 /* 640 * Snapshot Save Pointers. Clear 641 * the snapshot and continue. 642 */ 643 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 644 continue; 645 } 646 647 /* 648 * Disable S/G fetch so the DMA engine 649 * is available to future users. 650 */ 651 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 652 ahd_outb(ahd, CCSGCTL, 0); 653 ahd_outb(ahd, SG_STATE, 0); 654 655 /* 656 * Flush the data FIFO. Strickly only 657 * necessary for Rev A parts. 658 */ 659 ahd_outb(ahd, DFCNTRL, 660 ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 661 662 /* 663 * Calculate residual. 664 */ 665 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 666 resid = ahd_inl(ahd, SHCNT); 667 resid |= 668 ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 669 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 670 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 671 /* 672 * Must back up to the correct S/G element. 673 * Typically this just means resetting our 674 * low byte to the offset in the SG_CACHE, 675 * but if we wrapped, we have to correct 676 * the other bytes of the sgptr too. 677 */ 678 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 679 && (sgptr & 0x80) == 0) 680 sgptr -= 0x100; 681 sgptr &= ~0xFF; 682 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 683 & SG_ADDR_MASK; 684 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 685 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 686 } else if ((resid & AHD_SG_LEN_MASK) == 0) { 687 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 688 sgptr | SG_LIST_NULL); 689 } 690 /* 691 * Save Pointers. 692 */ 693 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 694 ahd_outl(ahd, SCB_DATACNT, resid); 695 ahd_outl(ahd, SCB_SGPTR, sgptr); 696 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 697 ahd_outb(ahd, SEQIMODE, 698 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 699 /* 700 * If the data is to the SCSI bus, we are 701 * done, otherwise wait for FIFOEMP. 702 */ 703 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 704 break; 705 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 706 uint32_t sgptr; 707 uint64_t data_addr; 708 uint32_t data_len; 709 u_int dfcntrl; 710 711 /* 712 * Disable S/G fetch so the DMA engine 713 * is available to future users. 714 */ 715 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 716 ahd_outb(ahd, CCSGCTL, 0); 717 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 718 } 719 720 /* 721 * Wait for the DMA engine to notice that the 722 * host transfer is enabled and that there is 723 * space in the S/G FIFO for new segments before 724 * loading more segments. 725 */ 726 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) == 0) 727 continue; 728 if ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) == 0) 729 continue; 730 731 /* 732 * Determine the offset of the next S/G 733 * element to load. 734 */ 735 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 736 sgptr &= SG_PTR_MASK; 737 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 738 struct ahd_dma64_seg *sg; 739 740 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 741 data_addr = sg->addr; 742 data_len = sg->len; 743 sgptr += sizeof(*sg); 744 } else { 745 struct ahd_dma_seg *sg; 746 747 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 748 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 749 data_addr <<= 8; 750 data_addr |= sg->addr; 751 data_len = sg->len; 752 sgptr += sizeof(*sg); 753 } 754 755 /* 756 * Update residual information. 757 */ 758 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 759 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 760 761 /* 762 * Load the S/G. 763 */ 764 if (data_len & AHD_DMA_LAST_SEG) { 765 sgptr |= LAST_SEG; 766 ahd_outb(ahd, SG_STATE, 0); 767 } 768 ahd_outq(ahd, HADDR, data_addr); 769 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 770 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 771 772 /* 773 * Advertise the segment to the hardware. 774 */ 775 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 776 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS)!=0) { 777 /* 778 * Use SCSIENWRDIS so that SCSIEN 779 * is never modified by this 780 * operation. 781 */ 782 dfcntrl |= SCSIENWRDIS; 783 } 784 ahd_outb(ahd, DFCNTRL, dfcntrl); 785 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) 786 & LAST_SEG_DONE) != 0) { 787 788 /* 789 * Transfer completed to the end of SG list 790 * and has flushed to the host. 791 */ 792 ahd_outb(ahd, SCB_SGPTR, 793 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 794 break; 795 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 796 break; 797 } 798 ahd_delay(200); 799 } 800 /* 801 * Clear any handler for this FIFO, decrement 802 * the FIFO use count for the SCB, and release 803 * the FIFO. 804 */ 805 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 806 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 807 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 808 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 809 } 810 811 void 812 ahd_run_qoutfifo(struct ahd_softc *ahd) 813 { 814 struct scb *scb; 815 u_int scb_index; 816 817 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 818 panic("ahd_run_qoutfifo recursion"); 819 ahd->flags |= AHD_RUNNING_QOUTFIFO; 820 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 821 while ((ahd->qoutfifo[ahd->qoutfifonext] 822 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 823 824 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 825 & ~QOUTFIFO_ENTRY_VALID_LE); 826 scb = ahd_lookup_scb(ahd, scb_index); 827 if (scb == NULL) { 828 printf("%s: WARNING no command for scb %d " 829 "(cmdcmplt)\nQOUTPOS = %d\n", 830 ahd_name(ahd), scb_index, 831 ahd->qoutfifonext); 832 ahd_dump_card_state(ahd); 833 } else 834 ahd_complete_scb(ahd, scb); 835 836 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 837 if (ahd->qoutfifonext == 0) 838 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 839 } 840 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 841 } 842 843 /************************* Interrupt Handling *********************************/ 844 void 845 ahd_handle_hwerrint(struct ahd_softc *ahd) 846 { 847 /* 848 * Some catastrophic hardware error has occurred. 849 * Print it for the user and disable the controller. 850 */ 851 int i; 852 int error; 853 854 error = ahd_inb(ahd, ERROR); 855 for (i = 0; i < num_errors; i++) { 856 if ((error & ahd_hard_errors[i].errno) != 0) 857 printf("%s: hwerrint, %s\n", 858 ahd_name(ahd), ahd_hard_errors[i].errmesg); 859 } 860 861 ahd_dump_card_state(ahd); 862 panic("BRKADRINT"); 863 864 /* Tell everyone that this HBA is no longer available */ 865 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 866 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 867 CAM_NO_HBA); 868 869 /* Tell the system that this controller has gone away. */ 870 ahd_free(ahd); 871 } 872 873 void 874 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 875 { 876 u_int seqintcode; 877 878 /* 879 * Save the sequencer interrupt code and clear the SEQINT 880 * bit. We will unpause the sequencer, if appropriate, 881 * after servicing the request. 882 */ 883 seqintcode = ahd_inb(ahd, SEQINTCODE); 884 ahd_outb(ahd, CLRINT, CLRSEQINT); 885 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 886 /* 887 * Unpause the sequencer and let it clear 888 * SEQINT by writing NO_SEQINT to it. This 889 * will cause the sequencer to be paused again, 890 * which is the expected state of this routine. 891 */ 892 ahd_unpause(ahd); 893 while (!ahd_is_paused(ahd)) 894 ; 895 ahd_outb(ahd, CLRINT, CLRSEQINT); 896 } 897 ahd_update_modes(ahd); 898 #ifdef AHD_DEBUG 899 if ((ahd_debug & AHD_SHOW_MISC) != 0) 900 printf("%s: Handle Seqint Called for code %d\n", 901 ahd_name(ahd), seqintcode); 902 #endif 903 switch (seqintcode) { 904 case BAD_SCB_STATUS: 905 { 906 struct scb *scb; 907 u_int scbid; 908 int cmds_pending; 909 910 scbid = ahd_get_scbptr(ahd); 911 scb = ahd_lookup_scb(ahd, scbid); 912 if (scb != NULL) { 913 ahd_complete_scb(ahd, scb); 914 } else { 915 printf("%s: WARNING no command for scb %d " 916 "(bad status)\n", ahd_name(ahd), scbid); 917 ahd_dump_card_state(ahd); 918 } 919 cmds_pending = ahd_inw(ahd, CMDS_PENDING); 920 if (cmds_pending > 0) 921 ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1); 922 break; 923 } 924 case ENTERING_NONPACK: 925 { 926 struct scb *scb; 927 u_int scbid; 928 929 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 930 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 931 scbid = ahd_get_scbptr(ahd); 932 scb = ahd_lookup_scb(ahd, scbid); 933 if (scb == NULL) { 934 /* 935 * Somehow need to know if this 936 * is from a selection or reselection. 937 * From that, we can determine target 938 * ID so we at least have an I_T nexus. 939 */ 940 } else { 941 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 942 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 943 ahd_outb(ahd, SEQ_FLAGS, 0x0); 944 } 945 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 946 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 947 /* 948 * Phase change after read stream with 949 * CRC error with P0 asserted on last 950 * packet. 951 */ 952 #ifdef AHD_DEBUG 953 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 954 printf("%s: Assuming LQIPHASE_NLQ with " 955 "P0 assertion\n", ahd_name(ahd)); 956 #endif 957 } 958 #ifdef AHD_DEBUG 959 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 960 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 961 #endif 962 break; 963 } 964 case INVALID_SEQINT: 965 printf("%s: Invalid Sequencer interrupt occurred.\n", 966 ahd_name(ahd)); 967 ahd_dump_card_state(ahd); 968 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 969 break; 970 case STATUS_OVERRUN: 971 { 972 struct scb *scb; 973 u_int scbid; 974 975 scbid = ahd_get_scbptr(ahd); 976 scb = ahd_lookup_scb(ahd, scbid); 977 if (scb != NULL) 978 ahd_print_path(ahd, scb); 979 else 980 printf("%s: ", ahd_name(ahd)); 981 printf("SCB %d Packetized Status Overrun", scbid); 982 ahd_dump_card_state(ahd); 983 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 984 break; 985 } 986 case CFG4ISTAT_INTR: 987 { 988 struct scb *scb; 989 u_int scbid; 990 991 scbid = ahd_get_scbptr(ahd); 992 scb = ahd_lookup_scb(ahd, scbid); 993 if (scb == NULL) { 994 ahd_dump_card_state(ahd); 995 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 996 panic("For safety"); 997 } 998 ahd_outq(ahd, HADDR, scb->sense_busaddr); 999 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1000 ahd_outb(ahd, HCNT + 2, 0); 1001 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1002 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1003 break; 1004 } 1005 case ILLEGAL_PHASE: 1006 { 1007 u_int bus_phase; 1008 1009 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1010 printf("%s: ILLEGAL_PHASE 0x%x\n", 1011 ahd_name(ahd), bus_phase); 1012 1013 switch (bus_phase) { 1014 case P_DATAOUT: 1015 case P_DATAIN: 1016 case P_DATAOUT_DT: 1017 case P_DATAIN_DT: 1018 case P_MESGOUT: 1019 case P_STATUS: 1020 case P_MESGIN: 1021 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1022 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1023 break; 1024 case P_COMMAND: 1025 { 1026 struct ahd_devinfo devinfo; 1027 struct scb *scb; 1028 struct ahd_initiator_tinfo *targ_info; 1029 struct ahd_tmode_tstate *tstate; 1030 struct ahd_transinfo *tinfo; 1031 u_int scbid; 1032 1033 /* 1034 * If a target takes us into the command phase 1035 * assume that it has been externally reset and 1036 * has thus lost our previous packetized negotiation 1037 * agreement. Since we have not sent an identify 1038 * message and may not have fully qualified the 1039 * connection, we change our command to TUR, assert 1040 * ATN and ABORT the task when we go to message in 1041 * phase. The OSM will see the REQUEUE_REQUEST 1042 * status and retry the command. 1043 */ 1044 scbid = ahd_get_scbptr(ahd); 1045 scb = ahd_lookup_scb(ahd, scbid); 1046 if (scb == NULL) { 1047 printf("Invalid phase with no valid SCB. " 1048 "Resetting bus.\n"); 1049 ahd_reset_channel(ahd, 'A', 1050 /*Initiate Reset*/TRUE); 1051 break; 1052 } 1053 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1054 SCB_GET_TARGET(ahd, scb), 1055 SCB_GET_LUN(scb), 1056 SCB_GET_CHANNEL(ahd, scb), 1057 ROLE_INITIATOR); 1058 targ_info = ahd_fetch_transinfo(ahd, 1059 devinfo.channel, 1060 devinfo.our_scsiid, 1061 devinfo.target, 1062 &tstate); 1063 tinfo = &targ_info->curr; 1064 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1065 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1066 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1067 /*offset*/0, /*ppr_options*/0, 1068 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1069 ahd_outb(ahd, SCB_CDB_STORE, 0); 1070 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 1071 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 1072 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 1073 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 1074 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 1075 ahd_outb(ahd, SCB_CDB_LEN, 6); 1076 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 1077 scb->hscb->control |= MK_MESSAGE; 1078 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 1079 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1080 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1081 /* 1082 * The lun is 0, regardless of the SCB's lun 1083 * as we have not sent an identify message. 1084 */ 1085 ahd_outb(ahd, SAVED_LUN, 0); 1086 ahd_outb(ahd, SEQ_FLAGS, 0); 1087 ahd_assert_atn(ahd); 1088 scb->flags &= ~(SCB_PACKETIZED); 1089 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 1090 ahd_freeze_devq(ahd, scb); 1091 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1092 ahd_freeze_scb(scb); 1093 1094 /* 1095 * Allow the sequencer to continue with 1096 * non-pack processing. 1097 */ 1098 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1099 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1100 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1101 ahd_outb(ahd, CLRLQOINT1, 0); 1102 } 1103 #ifdef AHD_DEBUG 1104 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1105 ahd_print_path(ahd, scb); 1106 printf("Unexpected command phase from " 1107 "packetized target\n"); 1108 } 1109 #endif 1110 break; 1111 } 1112 } 1113 break; 1114 } 1115 case CFG4OVERRUN: 1116 { 1117 struct scb *scb; 1118 u_int scb_index; 1119 1120 #ifdef AHD_DEBUG 1121 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1122 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 1123 ahd_inb(ahd, MODE_PTR)); 1124 } 1125 #endif 1126 scb_index = ahd_get_scbptr(ahd); 1127 scb = ahd_lookup_scb(ahd, scb_index); 1128 if (scb == NULL) { 1129 /* 1130 * Attempt to transfer to an SCB that is 1131 * not outstanding. 1132 */ 1133 ahd_assert_atn(ahd); 1134 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1135 ahd->msgout_buf[0] = MSG_ABORT_TASK; 1136 ahd->msgout_len = 1; 1137 ahd->msgout_index = 0; 1138 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1139 /* 1140 * Clear status received flag to prevent any 1141 * attempt to complete this bogus SCB. 1142 */ 1143 ahd_outb(ahd, SCB_CONTROL, 1144 ahd_inb_scbram(ahd, SCB_CONTROL) 1145 & ~STATUS_RCVD); 1146 } 1147 break; 1148 } 1149 case DUMP_CARD_STATE: 1150 { 1151 ahd_dump_card_state(ahd); 1152 break; 1153 } 1154 case PDATA_REINIT: 1155 { 1156 #ifdef AHD_DEBUG 1157 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1158 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 1159 "SG_CACHE_SHADOW = 0x%x\n", 1160 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 1161 ahd_inb(ahd, SG_CACHE_SHADOW)); 1162 } 1163 #endif 1164 ahd_reinitialize_dataptrs(ahd); 1165 break; 1166 } 1167 case HOST_MSG_LOOP: 1168 { 1169 struct ahd_devinfo devinfo; 1170 1171 /* 1172 * The sequencer has encountered a message phase 1173 * that requires host assistance for completion. 1174 * While handling the message phase(s), we will be 1175 * notified by the sequencer after each byte is 1176 * transferred so we can track bus phase changes. 1177 * 1178 * If this is the first time we've seen a HOST_MSG_LOOP 1179 * interrupt, initialize the state of the host message 1180 * loop. 1181 */ 1182 ahd_fetch_devinfo(ahd, &devinfo); 1183 if (ahd->msg_type == MSG_TYPE_NONE) { 1184 struct scb *scb; 1185 u_int scb_index; 1186 u_int bus_phase; 1187 1188 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1189 if (bus_phase != P_MESGIN 1190 && bus_phase != P_MESGOUT) { 1191 printf("ahd_intr: HOST_MSG_LOOP bad " 1192 "phase 0x%x\n", bus_phase); 1193 /* 1194 * Probably transitioned to bus free before 1195 * we got here. Just punt the message. 1196 */ 1197 ahd_dump_card_state(ahd); 1198 ahd_clear_intstat(ahd); 1199 ahd_restart(ahd); 1200 return; 1201 } 1202 1203 scb_index = ahd_get_scbptr(ahd); 1204 scb = ahd_lookup_scb(ahd, scb_index); 1205 if (devinfo.role == ROLE_INITIATOR) { 1206 if (bus_phase == P_MESGOUT) 1207 ahd_setup_initiator_msgout(ahd, 1208 &devinfo, 1209 scb); 1210 else { 1211 ahd->msg_type = 1212 MSG_TYPE_INITIATOR_MSGIN; 1213 ahd->msgin_index = 0; 1214 } 1215 } 1216 #if AHD_TARGET_MODE 1217 else { 1218 if (bus_phase == P_MESGOUT) { 1219 ahd->msg_type = 1220 MSG_TYPE_TARGET_MSGOUT; 1221 ahd->msgin_index = 0; 1222 } 1223 else 1224 ahd_setup_target_msgin(ahd, 1225 &devinfo, 1226 scb); 1227 } 1228 #endif 1229 } 1230 1231 ahd_handle_message_phase(ahd); 1232 break; 1233 } 1234 case NO_MATCH: 1235 { 1236 /* Ensure we don't leave the selection hardware on */ 1237 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1238 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1239 1240 printf("%s:%c:%d: no active SCB for reconnecting " 1241 "target - issuing BUS DEVICE RESET\n", 1242 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 1243 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1244 "REG0 == 0x%x ACCUM = 0x%x\n", 1245 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 1246 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 1247 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1248 "SINDEX == 0x%x\n", 1249 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 1250 ahd_find_busy_tcl(ahd, 1251 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 1252 ahd_inb(ahd, SAVED_LUN))), 1253 ahd_inw(ahd, SINDEX)); 1254 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1255 "SCB_CONTROL == 0x%x\n", 1256 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 1257 ahd_inb_scbram(ahd, SCB_LUN), 1258 ahd_inb_scbram(ahd, SCB_CONTROL)); 1259 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 1260 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 1261 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 1262 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 1263 ahd_dump_card_state(ahd); 1264 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 1265 ahd->msgout_len = 1; 1266 ahd->msgout_index = 0; 1267 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1268 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1269 ahd_assert_atn(ahd); 1270 break; 1271 } 1272 case PROTO_VIOLATION: 1273 { 1274 ahd_handle_proto_violation(ahd); 1275 break; 1276 } 1277 case IGN_WIDE_RES: 1278 { 1279 struct ahd_devinfo devinfo; 1280 1281 ahd_fetch_devinfo(ahd, &devinfo); 1282 ahd_handle_ign_wide_residue(ahd, &devinfo); 1283 break; 1284 } 1285 case BAD_PHASE: 1286 { 1287 u_int lastphase; 1288 1289 lastphase = ahd_inb(ahd, LASTPHASE); 1290 printf("%s:%c:%d: unknown scsi bus phase %x, " 1291 "lastphase = 0x%x. Attempting to continue\n", 1292 ahd_name(ahd), 'A', 1293 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1294 lastphase, ahd_inb(ahd, SCSISIGI)); 1295 break; 1296 } 1297 case MISSED_BUSFREE: 1298 { 1299 u_int lastphase; 1300 1301 lastphase = ahd_inb(ahd, LASTPHASE); 1302 printf("%s:%c:%d: Missed busfree. " 1303 "Lastphase = 0x%x, Curphase = 0x%x\n", 1304 ahd_name(ahd), 'A', 1305 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1306 lastphase, ahd_inb(ahd, SCSISIGI)); 1307 ahd_restart(ahd); 1308 return; 1309 } 1310 case DATA_OVERRUN: 1311 { 1312 /* 1313 * When the sequencer detects an overrun, it 1314 * places the controller in "BITBUCKET" mode 1315 * and allows the target to complete its transfer. 1316 * Unfortunately, none of the counters get updated 1317 * when the controller is in this mode, so we have 1318 * no way of knowing how large the overrun was. 1319 */ 1320 struct scb *scb; 1321 u_int scbindex; 1322 #ifdef AHD_DEBUG 1323 u_int lastphase; 1324 #endif 1325 1326 scbindex = ahd_get_scbptr(ahd); 1327 scb = ahd_lookup_scb(ahd, scbindex); 1328 #ifdef AHD_DEBUG 1329 lastphase = ahd_inb(ahd, LASTPHASE); 1330 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1331 ahd_print_path(ahd, scb); 1332 printf("data overrun detected %s. Tag == 0x%x.\n", 1333 ahd_lookup_phase_entry(lastphase)->phasemsg, 1334 SCB_GET_TAG(scb)); 1335 ahd_print_path(ahd, scb); 1336 printf("%s seen Data Phase. Length = %ld. " 1337 "NumSGs = %d.\n", 1338 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1339 ? "Have" : "Haven't", 1340 ahd_get_transfer_length(scb), scb->sg_count); 1341 ahd_dump_sglist(scb); 1342 } 1343 #endif 1344 1345 /* 1346 * Set this and it will take effect when the 1347 * target does a command complete. 1348 */ 1349 ahd_freeze_devq(ahd, scb); 1350 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1351 ahd_freeze_scb(scb); 1352 break; 1353 } 1354 case MKMSG_FAILED: 1355 { 1356 struct ahd_devinfo devinfo; 1357 struct scb *scb; 1358 u_int scbid; 1359 1360 ahd_fetch_devinfo(ahd, &devinfo); 1361 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1362 ahd_name(ahd), devinfo.channel, devinfo.target, 1363 devinfo.lun); 1364 scbid = ahd_get_scbptr(ahd); 1365 scb = ahd_lookup_scb(ahd, scbid); 1366 if (scb != NULL 1367 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1368 /* 1369 * Ensure that we didn't put a second instance of this 1370 * SCB into the QINFIFO. 1371 */ 1372 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1373 SCB_GET_CHANNEL(ahd, scb), 1374 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1375 ROLE_INITIATOR, /*status*/0, 1376 SEARCH_REMOVE); 1377 ahd_outb(ahd, SCB_CONTROL, 1378 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1379 break; 1380 } 1381 case TASKMGMT_FUNC_COMPLETE: 1382 { 1383 u_int scbid; 1384 struct scb *scb; 1385 1386 scbid = ahd_get_scbptr(ahd); 1387 scb = ahd_lookup_scb(ahd, scbid); 1388 if (scb != NULL) { 1389 u_int lun; 1390 u_int tag; 1391 cam_status error; 1392 1393 ahd_print_path(ahd, scb); 1394 printf("Task Management Func 0x%x Complete\n", 1395 scb->hscb->task_management); 1396 lun = CAM_LUN_WILDCARD; 1397 tag = SCB_LIST_NULL; 1398 1399 switch (scb->hscb->task_management) { 1400 case SIU_TASKMGMT_ABORT_TASK: 1401 tag = SCB_GET_TAG(scb); 1402 case SIU_TASKMGMT_ABORT_TASK_SET: 1403 case SIU_TASKMGMT_CLEAR_TASK_SET: 1404 lun = scb->hscb->lun; 1405 error = CAM_REQ_ABORTED; 1406 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1407 'A', lun, tag, ROLE_INITIATOR, 1408 error); 1409 break; 1410 case SIU_TASKMGMT_LUN_RESET: 1411 lun = scb->hscb->lun; 1412 case SIU_TASKMGMT_TARGET_RESET: 1413 { 1414 struct ahd_devinfo devinfo; 1415 1416 ahd_scb_devinfo(ahd, &devinfo, scb); 1417 error = CAM_BDR_SENT; 1418 ahd_handle_devreset(ahd, &devinfo, lun, 1419 CAM_BDR_SENT, 1420 lun != CAM_LUN_WILDCARD 1421 ? "Lun Reset" 1422 : "Target Reset", 1423 /*verbose_level*/0); 1424 break; 1425 } 1426 default: 1427 panic("Unexpected TaskMgmt Func\n"); 1428 break; 1429 } 1430 } 1431 break; 1432 } 1433 case TASKMGMT_CMD_CMPLT_OKAY: 1434 { 1435 u_int scbid; 1436 struct scb *scb; 1437 1438 /* 1439 * An ABORT TASK TMF failed to be delivered before 1440 * the targeted command completed normally. 1441 */ 1442 scbid = ahd_get_scbptr(ahd); 1443 scb = ahd_lookup_scb(ahd, scbid); 1444 if (scb != NULL) { 1445 /* 1446 * Remove the second instance of this SCB from 1447 * the QINFIFO if it is still there. 1448 */ 1449 ahd_print_path(ahd, scb); 1450 printf("SCB completes before TMF\n"); 1451 /* 1452 * Handle losing the race. Wait until any 1453 * current selection completes. We will then 1454 * set the TMF back to zero in this SCB so that 1455 * the sequencer doesn't bother to issue another 1456 * sequencer interrupt for its completion. 1457 */ 1458 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1459 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1460 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1461 ; 1462 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1463 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1464 SCB_GET_CHANNEL(ahd, scb), 1465 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1466 ROLE_INITIATOR, /*status*/0, 1467 SEARCH_REMOVE); 1468 } 1469 break; 1470 } 1471 case TRACEPOINT0: 1472 case TRACEPOINT1: 1473 case TRACEPOINT2: 1474 case TRACEPOINT3: 1475 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1476 seqintcode - TRACEPOINT0); 1477 break; 1478 case NO_SEQINT: 1479 break; 1480 case SAW_HWERR: 1481 ahd_handle_hwerrint(ahd); 1482 break; 1483 default: 1484 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1485 seqintcode); 1486 break; 1487 } 1488 /* 1489 * The sequencer is paused immediately on 1490 * a SEQINT, so we should restart it when 1491 * we're done. 1492 */ 1493 ahd_unpause(ahd); 1494 } 1495 1496 void 1497 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1498 { 1499 struct scb *scb; 1500 u_int status0; 1501 u_int status3; 1502 u_int status; 1503 u_int lqistat1; 1504 u_int lqostat0; 1505 u_int scbid; 1506 u_int busfreetime; 1507 1508 ahd_update_modes(ahd); 1509 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1510 1511 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1512 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1513 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1514 lqistat1 = ahd_inb(ahd, LQISTAT1); 1515 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1516 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1517 if ((status0 & (SELDI|SELDO)) != 0) { 1518 u_int simode0; 1519 1520 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1521 simode0 = ahd_inb(ahd, SIMODE0); 1522 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1523 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1524 } 1525 scbid = ahd_get_scbptr(ahd); 1526 scb = ahd_lookup_scb(ahd, scbid); 1527 if (scb != NULL 1528 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1529 scb = NULL; 1530 1531 /* Make sure the sequencer is in a safe location. */ 1532 ahd_clear_critical_section(ahd); 1533 1534 if ((status0 & IOERR) != 0) { 1535 u_int now_lvd; 1536 1537 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1538 printf("%s: Transceiver State Has Changed to %s mode\n", 1539 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1540 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1541 /* 1542 * A change in I/O mode is equivalent to a bus reset. 1543 */ 1544 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1545 ahd_pause(ahd); 1546 ahd_setup_iocell_workaround(ahd); 1547 ahd_unpause(ahd); 1548 } else if ((status0 & OVERRUN) != 0) { 1549 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1550 ahd_name(ahd)); 1551 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1552 } else if ((status & SCSIRSTI) != 0) { 1553 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1554 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1555 } else if ((status & SCSIPERR) != 0) { 1556 ahd_handle_transmission_error(ahd); 1557 } else if (lqostat0 != 0) { 1558 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1559 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1560 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1561 ahd_outb(ahd, CLRLQOINT1, 0); 1562 } 1563 } else if ((status & SELTO) != 0) { 1564 u_int scbid1; 1565 1566 /* Stop the selection */ 1567 ahd_outb(ahd, SCSISEQ0, 0); 1568 1569 /* No more pending messages */ 1570 ahd_clear_msg_state(ahd); 1571 1572 /* Clear interrupt state */ 1573 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1574 1575 /* 1576 * Although the driver does not care about the 1577 * 'Selection in Progress' status bit, the busy 1578 * LED does. SELINGO is only cleared by a sucessfull 1579 * selection, so we must manually clear it to insure 1580 * the LED turns off just incase no future successful 1581 * selections occur (e.g. no devices on the bus). 1582 */ 1583 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1584 1585 scbid1 = ahd_inw(ahd, WAITING_TID_HEAD); 1586 scb = ahd_lookup_scb(ahd, scbid1); 1587 if (scb == NULL) { 1588 printf("%s: ahd_intr - referenced scb not " 1589 "valid during SELTO scb(0x%x)\n", 1590 ahd_name(ahd), scbid1); 1591 ahd_dump_card_state(ahd); 1592 } else { 1593 struct ahd_devinfo devinfo; 1594 #ifdef AHD_DEBUG 1595 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1596 ahd_print_path(ahd, scb); 1597 printf("Saw Selection Timeout for SCB 0x%x\n", 1598 scbid1); 1599 } 1600 #endif 1601 /* 1602 * Force a renegotiation with this target just in 1603 * case the cable was pulled and will later be 1604 * re-attached. The target may forget its negotiation 1605 * settings with us should it attempt to reselect 1606 * during the interruption. The target will not issue 1607 * a unit attention in this case, so we must always 1608 * renegotiate. 1609 */ 1610 ahd_scb_devinfo(ahd, &devinfo, scb); 1611 ahd_force_renegotiation(ahd, &devinfo); 1612 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1613 ahd_freeze_devq(ahd, scb); 1614 } 1615 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1616 ahd_iocell_first_selection(ahd); 1617 ahd_unpause(ahd); 1618 } else if ((status0 & (SELDI|SELDO)) != 0) { 1619 ahd_iocell_first_selection(ahd); 1620 ahd_unpause(ahd); 1621 } else if (status3 != 0) { 1622 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1623 ahd_name(ahd), status3); 1624 ahd_outb(ahd, CLRSINT3, status3); 1625 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1626 ahd_handle_lqiphase_error(ahd, lqistat1); 1627 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1628 /* 1629 * This status can be delayed during some 1630 * streaming operations. The SCSIPHASE 1631 * handler has already dealt with this case 1632 * so just clear the error. 1633 */ 1634 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1635 } else if ((status & BUSFREE) != 0) { 1636 u_int lqostat1; 1637 int restart; 1638 int clear_fifo; 1639 int packetized; 1640 u_int mode; 1641 1642 /* 1643 * Clear our selection hardware as soon as possible. 1644 * We may have an entry in the waiting Q for this target, 1645 * that is affected by this busfree and we don't want to 1646 * go about selecting the target while we handle the event. 1647 */ 1648 ahd_outb(ahd, SCSISEQ0, 0); 1649 1650 /* 1651 * Determine what we were up to at the time of 1652 * the busfree. 1653 */ 1654 mode = AHD_MODE_SCSI; 1655 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1656 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1657 switch (busfreetime) { 1658 case BUSFREE_DFF0: 1659 case BUSFREE_DFF1: 1660 { 1661 u_int scbid1; 1662 struct scb *scb1; 1663 1664 mode = busfreetime == BUSFREE_DFF0 1665 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1666 ahd_set_modes(ahd, mode, mode); 1667 scbid1 = ahd_get_scbptr(ahd); 1668 scb1 = ahd_lookup_scb(ahd, scbid1); 1669 if (scb1 == NULL) { 1670 printf("%s: Invalid SCB %d in DFF%d " 1671 "during unexpected busfree\n", 1672 ahd_name(ahd), scbid1, mode); 1673 packetized = 0; 1674 } else 1675 packetized = (scb1->flags & SCB_PACKETIZED) != 0; 1676 clear_fifo = 1; 1677 break; 1678 } 1679 case BUSFREE_LQO: 1680 clear_fifo = 0; 1681 packetized = 1; 1682 break; 1683 default: 1684 clear_fifo = 0; 1685 packetized = (lqostat1 & LQOBUSFREE) != 0; 1686 if (!packetized 1687 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1688 packetized = 1; 1689 break; 1690 } 1691 1692 #ifdef AHD_DEBUG 1693 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1694 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1695 busfreetime); 1696 #endif 1697 /* 1698 * Busfrees that occur in non-packetized phases are 1699 * handled by the nonpkt_busfree handler. 1700 */ 1701 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1702 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1703 } else { 1704 packetized = 0; 1705 restart = ahd_handle_nonpkt_busfree(ahd); 1706 } 1707 /* 1708 * Clear the busfree interrupt status. The setting of 1709 * the interrupt is a pulse, so in a perfect world, we 1710 * would not need to muck with the ENBUSFREE logic. This 1711 * would ensure that if the bus moves on to another 1712 * connection, busfree protection is still in force. If 1713 * BUSFREEREV is broken, however, we must manually clear 1714 * the ENBUSFREE if the busfree occurred during a non-pack 1715 * connection so that we don't get false positives during 1716 * future, packetized, connections. 1717 */ 1718 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1719 if (packetized == 0 1720 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1721 ahd_outb(ahd, SIMODE1, 1722 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1723 1724 if (clear_fifo) 1725 ahd_clear_fifo(ahd, mode); 1726 1727 ahd_clear_msg_state(ahd); 1728 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1729 if (restart) { 1730 ahd_restart(ahd); 1731 } else { 1732 ahd_unpause(ahd); 1733 } 1734 } else { 1735 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1736 ahd_name(ahd), status); 1737 ahd_dump_card_state(ahd); 1738 ahd_clear_intstat(ahd); 1739 ahd_unpause(ahd); 1740 } 1741 } 1742 1743 static void 1744 ahd_handle_transmission_error(struct ahd_softc *ahd) 1745 { 1746 struct scb *scb; 1747 u_int scbid; 1748 u_int lqistat1; 1749 u_int lqistat2; 1750 u_int msg_out; 1751 u_int curphase; 1752 u_int lastphase; 1753 u_int perrdiag; 1754 u_int cur_col; 1755 int silent; 1756 1757 scb = NULL; 1758 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1759 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1760 lqistat2 = ahd_inb(ahd, LQISTAT2); 1761 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1762 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1763 u_int lqistate; 1764 1765 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1766 lqistate = ahd_inb(ahd, LQISTATE); 1767 if ((lqistate >= 0x1E && lqistate <= 0x24) 1768 || (lqistate == 0x29)) { 1769 #ifdef AHD_DEBUG 1770 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1771 printf("%s: NLQCRC found via LQISTATE\n", 1772 ahd_name(ahd)); 1773 } 1774 #endif 1775 lqistat1 |= LQICRCI_NLQ; 1776 } 1777 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1778 } 1779 1780 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1781 lastphase = ahd_inb(ahd, LASTPHASE); 1782 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1783 perrdiag = ahd_inb(ahd, PERRDIAG); 1784 msg_out = MSG_INITIATOR_DET_ERR; 1785 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1786 1787 /* 1788 * Try to find the SCB associated with this error. 1789 */ 1790 silent = FALSE; 1791 if (lqistat1 == 0 1792 || (lqistat1 & LQICRCI_NLQ) != 0) { 1793 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1794 ahd_set_active_fifo(ahd); 1795 scbid = ahd_get_scbptr(ahd); 1796 scb = ahd_lookup_scb(ahd, scbid); 1797 if (scb != NULL && SCB_IS_SILENT(scb)) 1798 silent = TRUE; 1799 } 1800 1801 cur_col = 0; 1802 if (silent == FALSE) { 1803 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1804 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1805 ahd_lastphase_print(lastphase, &cur_col, 50); 1806 ahd_scsisigi_print(curphase, &cur_col, 50); 1807 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1808 printf("\n"); 1809 ahd_dump_card_state(ahd); 1810 } 1811 1812 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1813 if (silent == FALSE) { 1814 printf("%s: Gross protocol error during incoming " 1815 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1816 ahd_name(ahd), lqistat1); 1817 } 1818 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1819 return; 1820 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1821 /* 1822 * A CRC error has been detected on an incoming LQ. 1823 * The bus is currently hung on the last ACK. 1824 * Hit LQIRETRY to release the last ack, and 1825 * wait for the sequencer to determine that ATNO 1826 * is asserted while in message out to take us 1827 * to our host message loop. No NONPACKREQ or 1828 * LQIPHASE type errors will occur in this 1829 * scenario. After this first LQIRETRY, the LQI 1830 * manager will be in ISELO where it will 1831 * happily sit until another packet phase begins. 1832 * Unexpected bus free detection is enabled 1833 * through any phases that occur after we release 1834 * this last ack until the LQI manager sees a 1835 * packet phase. This implies we may have to 1836 * ignore a perfectly valid "unexected busfree" 1837 * after our "initiator detected error" message is 1838 * sent. A busfree is the expected response after 1839 * we tell the target that it's L_Q was corrupted. 1840 * (SPI4R09 10.7.3.3.3) 1841 */ 1842 ahd_outb(ahd, LQCTL2, LQIRETRY); 1843 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1844 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1845 /* 1846 * We detected a CRC error in a NON-LQ packet. 1847 * The hardware has varying behavior in this situation 1848 * depending on whether this packet was part of a 1849 * stream or not. 1850 * 1851 * PKT by PKT mode: 1852 * The hardware has already acked the complete packet. 1853 * If the target honors our outstanding ATN condition, 1854 * we should be (or soon will be) in MSGOUT phase. 1855 * This will trigger the LQIPHASE_LQ status bit as the 1856 * hardware was expecting another LQ. Unexpected 1857 * busfree detection is enabled. Once LQIPHASE_LQ is 1858 * true (first entry into host message loop is much 1859 * the same), we must clear LQIPHASE_LQ and hit 1860 * LQIRETRY so the hardware is ready to handle 1861 * a future LQ. NONPACKREQ will not be asserted again 1862 * once we hit LQIRETRY until another packet is 1863 * processed. The target may either go busfree 1864 * or start another packet in response to our message. 1865 * 1866 * Read Streaming P0 asserted: 1867 * If we raise ATN and the target completes the entire 1868 * stream (P0 asserted during the last packet), the 1869 * hardware will ack all data and return to the ISTART 1870 * state. When the target reponds to our ATN condition, 1871 * LQIPHASE_LQ will be asserted. We should respond to 1872 * this with an LQIRETRY to prepare for any future 1873 * packets. NONPACKREQ will not be asserted again 1874 * once we hit LQIRETRY until another packet is 1875 * processed. The target may either go busfree or 1876 * start another packet in response to our message. 1877 * Busfree detection is enabled. 1878 * 1879 * Read Streaming P0 not asserted: 1880 * If we raise ATN and the target transitions to 1881 * MSGOUT in or after a packet where P0 is not 1882 * asserted, the hardware will assert LQIPHASE_NLQ. 1883 * We should respond to the LQIPHASE_NLQ with an 1884 * LQIRETRY. Should the target stay in a non-pkt 1885 * phase after we send our message, the hardware 1886 * will assert LQIPHASE_LQ. Recovery is then just as 1887 * listed above for the read streaming with P0 asserted. 1888 * Busfree detection is enabled. 1889 */ 1890 if (silent == FALSE) 1891 printf("LQICRC_NLQ\n"); 1892 if (scb == NULL) { 1893 printf("%s: No SCB valid for LQICRC_NLQ. " 1894 "Resetting bus\n", ahd_name(ahd)); 1895 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1896 return; 1897 } 1898 } else if ((lqistat1 & LQIBADLQI) != 0) { 1899 printf("Need to handle BADLQI!\n"); 1900 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1901 return; 1902 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1903 if ((curphase & ~P_DATAIN_DT) != 0) { 1904 /* Ack the byte. So we can continue. */ 1905 if (silent == FALSE) 1906 printf("Acking %s to clear perror\n", 1907 ahd_lookup_phase_entry(curphase)->phasemsg); 1908 ahd_inb(ahd, SCSIDAT); 1909 } 1910 1911 if (curphase == P_MESGIN) 1912 msg_out = MSG_PARITY_ERROR; 1913 } 1914 1915 /* 1916 * We've set the hardware to assert ATN if we 1917 * get a parity error on "in" phases, so all we 1918 * need to do is stuff the message buffer with 1919 * the appropriate message. "In" phases have set 1920 * mesg_out to something other than MSG_NOP. 1921 */ 1922 ahd->send_msg_perror = msg_out; 1923 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1924 scb->flags |= SCB_TRANSMISSION_ERROR; 1925 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1926 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1927 ahd_unpause(ahd); 1928 } 1929 1930 static void 1931 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1932 { 1933 /* 1934 * Clear the sources of the interrupts. 1935 */ 1936 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1937 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1938 1939 /* 1940 * If the "illegal" phase changes were in response 1941 * to our ATN to flag a CRC error, AND we ended up 1942 * on packet boundaries, clear the error, restart the 1943 * LQI manager as appropriate, and go on our merry 1944 * way toward sending the message. Otherwise, reset 1945 * the bus to clear the error. 1946 */ 1947 ahd_set_active_fifo(ahd); 1948 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1949 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1950 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1951 printf("LQIRETRY for LQIPHASE_LQ\n"); 1952 ahd_outb(ahd, LQCTL2, LQIRETRY); 1953 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1954 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1955 ahd_outb(ahd, LQCTL2, LQIRETRY); 1956 } else 1957 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1958 ahd_dump_card_state(ahd); 1959 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1960 ahd_unpause(ahd); 1961 } else { 1962 printf("Reseting Channel for LQI Phase error\n"); 1963 ahd_dump_card_state(ahd); 1964 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1965 } 1966 } 1967 1968 /* 1969 * Packetized unexpected or expected busfree. 1970 * Entered in mode based on busfreetime. 1971 */ 1972 static int 1973 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1974 { 1975 u_int lqostat1; 1976 1977 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1978 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1979 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1980 if ((lqostat1 & LQOBUSFREE) != 0) { 1981 struct scb *scb; 1982 u_int scbid; 1983 u_int saved_scbptr; 1984 u_int waiting_h; 1985 u_int waiting_t; 1986 u_int next; 1987 1988 if ((busfreetime & BUSFREE_LQO) == 0) 1989 printf("%s: Warning, BUSFREE time is 0x%x. " 1990 "Expected BUSFREE_LQO.\n", 1991 ahd_name(ahd), busfreetime); 1992 /* 1993 * The LQO manager detected an unexpected busfree 1994 * either: 1995 * 1996 * 1) During an outgoing LQ. 1997 * 2) After an outgoing LQ but before the first 1998 * REQ of the command packet. 1999 * 3) During an outgoing command packet. 2000 * 2001 * In all cases, CURRSCB is pointing to the 2002 * SCB that encountered the failure. Clean 2003 * up the queue, clear SELDO and LQOBUSFREE, 2004 * and allow the sequencer to restart the select 2005 * out at its lesure. 2006 */ 2007 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2008 scbid = ahd_inw(ahd, CURRSCB); 2009 scb = ahd_lookup_scb(ahd, scbid); 2010 if (scb == NULL) 2011 panic("SCB not valid during LQOBUSFREE"); 2012 /* 2013 * Clear the status. 2014 */ 2015 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2016 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2017 ahd_outb(ahd, CLRLQOINT1, 0); 2018 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2019 ahd_flush_device_writes(ahd); 2020 ahd_outb(ahd, CLRSINT0, CLRSELDO); 2021 2022 /* 2023 * Return the LQO manager to its idle loop. It will 2024 * not do this automatically if the busfree occurs 2025 * after the first REQ of either the LQ or command 2026 * packet or between the LQ and command packet. 2027 */ 2028 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2029 2030 /* 2031 * Update the waiting for selection queue so 2032 * we restart on the correct SCB. 2033 */ 2034 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2035 saved_scbptr = ahd_get_scbptr(ahd); 2036 if (waiting_h != scbid) { 2037 2038 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2039 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2040 if (waiting_t == waiting_h) { 2041 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2042 next = SCB_LIST_NULL; 2043 } else { 2044 ahd_set_scbptr(ahd, waiting_h); 2045 next = ahd_inw_scbram(ahd, SCB_NEXT2); 2046 } 2047 ahd_set_scbptr(ahd, scbid); 2048 ahd_outw(ahd, SCB_NEXT2, next); 2049 } 2050 ahd_set_scbptr(ahd, saved_scbptr); 2051 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2052 if (SCB_IS_SILENT(scb) == FALSE) { 2053 ahd_print_path(ahd, scb); 2054 printf("Probable outgoing LQ CRC error. " 2055 "Retrying command\n"); 2056 } 2057 scb->crc_retry_count++; 2058 } else { 2059 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 2060 ahd_freeze_scb(scb); 2061 ahd_freeze_devq(ahd, scb); 2062 } 2063 /* Return unpausing the sequencer. */ 2064 return (0); 2065 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2066 /* 2067 * Ignore what are really parity errors that 2068 * occur on the last REQ of a free running 2069 * clock prior to going busfree. Some drives 2070 * do not properly active negate just before 2071 * going busfree resulting in a parity glitch. 2072 */ 2073 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2074 #ifdef AHD_DEBUG 2075 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2076 printf("%s: Parity on last REQ detected " 2077 "during busfree phase.\n", 2078 ahd_name(ahd)); 2079 #endif 2080 /* Return unpausing the sequencer. */ 2081 return (0); 2082 } 2083 if (ahd->src_mode != AHD_MODE_SCSI) { 2084 u_int scbid; 2085 struct scb *scb; 2086 2087 scbid = ahd_get_scbptr(ahd); 2088 scb = ahd_lookup_scb(ahd, scbid); 2089 ahd_print_path(ahd, scb); 2090 printf("Unexpected PKT busfree condition\n"); 2091 ahd_dump_card_state(ahd); 2092 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 2093 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2094 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 2095 2096 /* Return restarting the sequencer. */ 2097 return (1); 2098 } 2099 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 2100 ahd_dump_card_state(ahd); 2101 /* Restart the sequencer. */ 2102 return (1); 2103 } 2104 2105 /* 2106 * Non-packetized unexpected or expected busfree. 2107 */ 2108 static int 2109 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 2110 { 2111 struct ahd_devinfo devinfo; 2112 struct scb *scb; 2113 u_int lastphase; 2114 u_int saved_scsiid; 2115 u_int saved_lun; 2116 u_int target; 2117 u_int initiator_role_id; 2118 u_int scbid; 2119 u_int ppr_busfree; 2120 int printerror; 2121 2122 /* 2123 * Look at what phase we were last in. If its message out, 2124 * chances are pretty good that the busfree was in response 2125 * to one of our abort requests. 2126 */ 2127 lastphase = ahd_inb(ahd, LASTPHASE); 2128 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2129 saved_lun = ahd_inb(ahd, SAVED_LUN); 2130 target = SCSIID_TARGET(ahd, saved_scsiid); 2131 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 2132 ahd_compile_devinfo(&devinfo, initiator_role_id, 2133 target, saved_lun, 'A', ROLE_INITIATOR); 2134 printerror = 1; 2135 2136 scbid = ahd_get_scbptr(ahd); 2137 scb = ahd_lookup_scb(ahd, scbid); 2138 if (scb != NULL 2139 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2140 scb = NULL; 2141 2142 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 2143 if (lastphase == P_MESGOUT) { 2144 u_int tag; 2145 2146 tag = SCB_LIST_NULL; 2147 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 2148 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 2149 int found; 2150 int sent_msg; 2151 2152 if (scb == NULL) { 2153 ahd_print_devinfo(ahd, &devinfo); 2154 printf("Abort for unidentified " 2155 "connection completed.\n"); 2156 /* restart the sequencer. */ 2157 return (1); 2158 } 2159 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 2160 ahd_print_path(ahd, scb); 2161 printf("SCB %d - Abort%s Completed.\n", 2162 SCB_GET_TAG(scb), 2163 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 2164 2165 if (sent_msg == MSG_ABORT_TAG) 2166 tag = SCB_GET_TAG(scb); 2167 2168 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 2169 /* 2170 * This abort is in response to an 2171 * unexpected switch to command phase 2172 * for a packetized connection. Since 2173 * the identify message was never sent, 2174 * "saved lun" is 0. We really want to 2175 * abort only the SCB that encountered 2176 * this error, which could have a different 2177 * lun. The SCB will be retried so the OS 2178 * will see the UA after renegotiating to 2179 * packetized. 2180 */ 2181 tag = SCB_GET_TAG(scb); 2182 saved_lun = scb->hscb->lun; 2183 } 2184 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 2185 tag, ROLE_INITIATOR, 2186 CAM_REQ_ABORTED); 2187 printf("found == 0x%x\n", found); 2188 printerror = 0; 2189 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 2190 MSG_BUS_DEV_RESET, TRUE)) { 2191 #ifdef __FreeBSD__ 2192 /* 2193 * Don't mark the user's request for this BDR 2194 * as completing with CAM_BDR_SENT. CAM3 2195 * specifies CAM_REQ_CMP. 2196 */ 2197 if (scb != NULL 2198 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 2199 && ahd_match_scb(ahd, scb, target, 'A', 2200 CAM_LUN_WILDCARD, SCB_LIST_NULL, 2201 ROLE_INITIATOR)) 2202 ahd_set_transaction_status(scb, CAM_REQ_CMP); 2203 #endif 2204 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 2205 CAM_BDR_SENT, "Bus Device Reset", 2206 /*verbose_level*/0); 2207 printerror = 0; 2208 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 2209 && ppr_busfree == 0) { 2210 struct ahd_initiator_tinfo *tinfo; 2211 struct ahd_tmode_tstate *tstate; 2212 2213 /* 2214 * PPR Rejected. Try non-ppr negotiation 2215 * and retry command. 2216 */ 2217 #ifdef AHD_DEBUG 2218 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2219 printf("PPR negotiation rejected busfree.\n"); 2220 #endif 2221 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2222 devinfo.our_scsiid, 2223 devinfo.target, &tstate); 2224 tinfo->curr.transport_version = 2; 2225 tinfo->goal.transport_version = 2; 2226 tinfo->goal.ppr_options = 0; 2227 ahd_qinfifo_requeue_tail(ahd, scb); 2228 printerror = 0; 2229 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 2230 && ppr_busfree == 0) { 2231 /* 2232 * Negotiation Rejected. Go-narrow and 2233 * retry command. 2234 */ 2235 #ifdef AHD_DEBUG 2236 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2237 printf("WDTR Negotiation rejected busfree.\n"); 2238 #endif 2239 ahd_set_width(ahd, &devinfo, 2240 MSG_EXT_WDTR_BUS_8_BIT, 2241 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2242 /*paused*/TRUE); 2243 ahd_qinfifo_requeue_tail(ahd, scb); 2244 printerror = 0; 2245 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 2246 && ppr_busfree == 0) { 2247 /* 2248 * Negotiation Rejected. Go-async and 2249 * retry command. 2250 */ 2251 #ifdef AHD_DEBUG 2252 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2253 printf("SDTR negotiation rejected busfree.\n"); 2254 #endif 2255 ahd_set_syncrate(ahd, &devinfo, 2256 /*period*/0, /*offset*/0, 2257 /*ppr_options*/0, 2258 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2259 /*paused*/TRUE); 2260 ahd_qinfifo_requeue_tail(ahd, scb); 2261 printerror = 0; 2262 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 2263 && ahd_sent_msg(ahd, AHDMSG_1B, 2264 MSG_INITIATOR_DET_ERR, TRUE)) { 2265 2266 #ifdef AHD_DEBUG 2267 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2268 printf("Expected IDE Busfree\n"); 2269 #endif 2270 printerror = 0; 2271 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 2272 && ahd_sent_msg(ahd, AHDMSG_1B, 2273 MSG_MESSAGE_REJECT, TRUE)) { 2274 2275 #ifdef AHD_DEBUG 2276 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2277 printf("Expected QAS Reject Busfree\n"); 2278 #endif 2279 printerror = 0; 2280 } 2281 } 2282 2283 /* 2284 * The busfree required flag is honored at the end of 2285 * the message phases. We check it last in case we 2286 * had to send some other message that caused a busfree. 2287 */ 2288 if (printerror != 0 2289 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 2290 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 2291 2292 ahd_freeze_devq(ahd, scb); 2293 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 2294 ahd_freeze_scb(scb); 2295 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 2296 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2297 SCB_GET_CHANNEL(ahd, scb), 2298 SCB_GET_LUN(scb), SCB_LIST_NULL, 2299 ROLE_INITIATOR, CAM_REQ_ABORTED); 2300 } else { 2301 #ifdef AHD_DEBUG 2302 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2303 printf("PPR Negotiation Busfree.\n"); 2304 #endif 2305 ahd_done(ahd, scb); 2306 } 2307 printerror = 0; 2308 } 2309 if (printerror != 0) { 2310 int aborted; 2311 2312 aborted = 0; 2313 if (scb != NULL) { 2314 u_int tag; 2315 2316 if ((scb->hscb->control & TAG_ENB) != 0) 2317 tag = SCB_GET_TAG(scb); 2318 else 2319 tag = SCB_LIST_NULL; 2320 ahd_print_path(ahd, scb); 2321 aborted = ahd_abort_scbs(ahd, target, 'A', 2322 SCB_GET_LUN(scb), tag, 2323 ROLE_INITIATOR, 2324 CAM_UNEXP_BUSFREE); 2325 } else { 2326 /* 2327 * We had not fully identified this connection, 2328 * so we cannot abort anything. 2329 */ 2330 printf("%s: ", ahd_name(ahd)); 2331 } 2332 if (lastphase != P_BUSFREE) 2333 ahd_force_renegotiation(ahd, &devinfo); 2334 printf("Unexpected busfree %s, %d SCBs aborted, " 2335 "PRGMCNT == 0x%x\n", 2336 ahd_lookup_phase_entry(lastphase)->phasemsg, 2337 aborted, 2338 ahd_inb(ahd, PRGMCNT) 2339 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 2340 ahd_dump_card_state(ahd); 2341 } 2342 /* Always restart the sequencer. */ 2343 return (1); 2344 } 2345 2346 static void 2347 ahd_handle_proto_violation(struct ahd_softc *ahd) 2348 { 2349 struct ahd_devinfo devinfo; 2350 struct scb *scb; 2351 u_int scbid; 2352 u_int seq_flags; 2353 u_int curphase; 2354 u_int lastphase; 2355 int found; 2356 2357 ahd_fetch_devinfo(ahd, &devinfo); 2358 scbid = ahd_get_scbptr(ahd); 2359 scb = ahd_lookup_scb(ahd, scbid); 2360 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2361 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2362 lastphase = ahd_inb(ahd, LASTPHASE); 2363 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2364 2365 /* 2366 * The reconnecting target either did not send an 2367 * identify message, or did, but we didn't find an SCB 2368 * to match. 2369 */ 2370 ahd_print_devinfo(ahd, &devinfo); 2371 printf("Target did not send an IDENTIFY message. " 2372 "LASTPHASE = 0x%x.\n", lastphase); 2373 scb = NULL; 2374 } else if (scb == NULL) { 2375 /* 2376 * We don't seem to have an SCB active for this 2377 * transaction. Print an error and reset the bus. 2378 */ 2379 ahd_print_devinfo(ahd, &devinfo); 2380 printf("No SCB found during protocol violation\n"); 2381 goto proto_violation_reset; 2382 } else { 2383 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2384 if ((seq_flags & NO_CDB_SENT) != 0) { 2385 ahd_print_path(ahd, scb); 2386 printf("No or incomplete CDB sent to device.\n"); 2387 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2388 & STATUS_RCVD) == 0) { 2389 /* 2390 * The target never bothered to provide status to 2391 * us prior to completing the command. Since we don't 2392 * know the disposition of this command, we must attempt 2393 * to abort it. Assert ATN and prepare to send an abort 2394 * message. 2395 */ 2396 ahd_print_path(ahd, scb); 2397 printf("Completed command without status.\n"); 2398 } else { 2399 ahd_print_path(ahd, scb); 2400 printf("Unknown protocol violation.\n"); 2401 ahd_dump_card_state(ahd); 2402 } 2403 } 2404 if ((lastphase & ~P_DATAIN_DT) == 0 2405 || lastphase == P_COMMAND) { 2406 proto_violation_reset: 2407 /* 2408 * Target either went directly to data 2409 * phase or didn't respond to our ATN. 2410 * The only safe thing to do is to blow 2411 * it away with a bus reset. 2412 */ 2413 found = ahd_reset_channel(ahd, 'A', TRUE); 2414 printf("%s: Issued Channel %c Bus Reset. " 2415 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2416 } else { 2417 /* 2418 * Leave the selection hardware off in case 2419 * this abort attempt will affect yet to 2420 * be sent commands. 2421 */ 2422 ahd_outb(ahd, SCSISEQ0, 2423 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2424 ahd_assert_atn(ahd); 2425 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2426 if (scb == NULL) { 2427 ahd_print_devinfo(ahd, &devinfo); 2428 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2429 ahd->msgout_len = 1; 2430 ahd->msgout_index = 0; 2431 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2432 } else { 2433 ahd_print_path(ahd, scb); 2434 scb->flags |= SCB_ABORT; 2435 } 2436 printf("Protocol violation %s. Attempting to abort.\n", 2437 ahd_lookup_phase_entry(curphase)->phasemsg); 2438 } 2439 } 2440 2441 /* 2442 * Force renegotiation to occur the next time we initiate 2443 * a command to the current device. 2444 */ 2445 static void 2446 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2447 { 2448 struct ahd_initiator_tinfo *targ_info; 2449 struct ahd_tmode_tstate *tstate; 2450 2451 #ifdef AHD_DEBUG 2452 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2453 ahd_print_devinfo(ahd, devinfo); 2454 printf("Forcing renegotiation\n"); 2455 } 2456 #endif 2457 targ_info = ahd_fetch_transinfo(ahd, 2458 devinfo->channel, 2459 devinfo->our_scsiid, 2460 devinfo->target, 2461 &tstate); 2462 ahd_update_neg_request(ahd, devinfo, tstate, 2463 targ_info, AHD_NEG_IF_NON_ASYNC); 2464 } 2465 2466 #define AHD_MAX_STEPS 2000 2467 void 2468 ahd_clear_critical_section(struct ahd_softc *ahd) 2469 { 2470 ahd_mode_state saved_modes; 2471 int stepping; 2472 int steps; 2473 int first_instr; 2474 u_int simode0; 2475 u_int simode1; 2476 u_int simode3; 2477 u_int lqimode0; 2478 u_int lqimode1; 2479 u_int lqomode0; 2480 u_int lqomode1; 2481 2482 if (ahd->num_critical_sections == 0) 2483 return; 2484 2485 stepping = FALSE; 2486 steps = 0; 2487 first_instr = 0; 2488 simode0 = 0; 2489 simode1 = 0; 2490 simode3 = 0; 2491 lqimode0 = 0; 2492 lqimode1 = 0; 2493 lqomode0 = 0; 2494 lqomode1 = 0; 2495 saved_modes = ahd_save_modes(ahd); 2496 for (;;) { 2497 struct cs *cs; 2498 u_int seqaddr; 2499 u_int i; 2500 2501 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2502 seqaddr = ahd_inb(ahd, CURADDR) 2503 | (ahd_inb(ahd, CURADDR+1) << 8); 2504 2505 cs = ahd->critical_sections; 2506 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2507 2508 if (cs->begin < seqaddr && cs->end >= seqaddr) 2509 break; 2510 } 2511 2512 if (i == ahd->num_critical_sections) 2513 break; 2514 2515 if (steps > AHD_MAX_STEPS) { 2516 printf("%s: Infinite loop in critical section\n" 2517 "%s: First Instruction 0x%x now 0x%x\n", 2518 ahd_name(ahd), ahd_name(ahd), first_instr, 2519 seqaddr); 2520 ahd_dump_card_state(ahd); 2521 panic("critical section loop"); 2522 } 2523 2524 steps++; 2525 #ifdef AHD_DEBUG 2526 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2527 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2528 seqaddr); 2529 #endif 2530 if (stepping == FALSE) { 2531 2532 first_instr = seqaddr; 2533 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2534 simode0 = ahd_inb(ahd, SIMODE0); 2535 simode3 = ahd_inb(ahd, SIMODE3); 2536 lqimode0 = ahd_inb(ahd, LQIMODE0); 2537 lqimode1 = ahd_inb(ahd, LQIMODE1); 2538 lqomode0 = ahd_inb(ahd, LQOMODE0); 2539 lqomode1 = ahd_inb(ahd, LQOMODE1); 2540 ahd_outb(ahd, SIMODE0, 0); 2541 ahd_outb(ahd, SIMODE3, 0); 2542 ahd_outb(ahd, LQIMODE0, 0); 2543 ahd_outb(ahd, LQIMODE1, 0); 2544 ahd_outb(ahd, LQOMODE0, 0); 2545 ahd_outb(ahd, LQOMODE1, 0); 2546 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2547 simode1 = ahd_inb(ahd, SIMODE1); 2548 /* 2549 * We don't clear ENBUSFREE. Unfortunately 2550 * we cannot re-enable busfree detection within 2551 * the current connection, so we must leave it 2552 * on while single stepping. 2553 */ 2554 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2555 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2556 stepping = TRUE; 2557 } 2558 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2559 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2560 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2561 ahd_outb(ahd, HCNTRL, ahd->unpause); 2562 while (!ahd_is_paused(ahd)) 2563 ahd_delay(200); 2564 ahd_update_modes(ahd); 2565 } 2566 if (stepping) { 2567 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2568 ahd_outb(ahd, SIMODE0, simode0); 2569 ahd_outb(ahd, SIMODE3, simode3); 2570 ahd_outb(ahd, LQIMODE0, lqimode0); 2571 ahd_outb(ahd, LQIMODE1, lqimode1); 2572 ahd_outb(ahd, LQOMODE0, lqomode0); 2573 ahd_outb(ahd, LQOMODE1, lqomode1); 2574 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2575 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2576 ahd_outb(ahd, SIMODE1, simode1); 2577 /* 2578 * SCSIINT seems to glitch occassionally when 2579 * the interrupt masks are restored. Clear SCSIINT 2580 * one more time so that only persistent errors 2581 * are seen as a real interrupt. 2582 */ 2583 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2584 } 2585 ahd_restore_modes(ahd, saved_modes); 2586 } 2587 2588 /* 2589 * Clear any pending interrupt status. 2590 */ 2591 void 2592 ahd_clear_intstat(struct ahd_softc *ahd) 2593 { 2594 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2595 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2596 /* Clear any interrupt conditions this may have caused */ 2597 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2598 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2599 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2600 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2601 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2602 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2603 |CLRLQOATNPKT|CLRLQOTCRC); 2604 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2605 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2606 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2607 ahd_outb(ahd, CLRLQOINT0, 0); 2608 ahd_outb(ahd, CLRLQOINT1, 0); 2609 } 2610 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2611 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2612 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2613 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2614 |CLRIOERR|CLROVERRUN); 2615 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2616 } 2617 2618 /**************************** Debugging Routines ******************************/ 2619 #ifdef AHD_DEBUG 2620 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2621 #endif 2622 void 2623 ahd_print_scb(struct scb *scb) 2624 { 2625 struct hardware_scb *hscb; 2626 int i; 2627 2628 hscb = scb->hscb; 2629 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2630 (void *)scb, 2631 hscb->control, 2632 hscb->scsiid, 2633 hscb->lun, 2634 hscb->cdb_len); 2635 printf("Shared Data: "); 2636 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2637 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2638 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2639 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2640 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2641 ahd_le32toh(hscb->datacnt), 2642 ahd_le32toh(hscb->sgptr), 2643 SCB_GET_TAG(scb)); 2644 ahd_dump_sglist(scb); 2645 } 2646 2647 void 2648 ahd_dump_sglist(struct scb *scb) 2649 { 2650 int i; 2651 2652 if (scb->sg_count > 0) { 2653 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2654 struct ahd_dma64_seg *sg_list; 2655 2656 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2657 for (i = 0; i < scb->sg_count; i++) { 2658 uint64_t addr; 2659 uint32_t len; 2660 2661 addr = ahd_le64toh(sg_list[i].addr); 2662 len = ahd_le32toh(sg_list[i].len); 2663 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2664 i, 2665 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2666 (uint32_t)(addr & 0xFFFFFFFF), 2667 sg_list[i].len & AHD_SG_LEN_MASK, 2668 (sg_list[i].len & AHD_DMA_LAST_SEG) 2669 ? " Last" : ""); 2670 } 2671 } else { 2672 struct ahd_dma_seg *sg_list; 2673 2674 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2675 for (i = 0; i < scb->sg_count; i++) { 2676 uint32_t len; 2677 2678 len = ahd_le32toh(sg_list[i].len); 2679 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2680 i, 2681 (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 2682 ahd_le32toh(sg_list[i].addr), 2683 len & AHD_SG_LEN_MASK, 2684 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2685 } 2686 } 2687 } 2688 } 2689 2690 /************************* Transfer Negotiation *******************************/ 2691 /* 2692 * Allocate per target mode instance (ID we respond to as a target) 2693 * transfer negotiation data structures. 2694 */ 2695 static struct ahd_tmode_tstate * 2696 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2697 { 2698 struct ahd_tmode_tstate *master_tstate; 2699 struct ahd_tmode_tstate *tstate; 2700 int i; 2701 2702 master_tstate = ahd->enabled_targets[ahd->our_id]; 2703 if (ahd->enabled_targets[scsi_id] != NULL 2704 && ahd->enabled_targets[scsi_id] != master_tstate) 2705 panic("%s: ahd_alloc_tstate - Target already allocated", 2706 ahd_name(ahd)); 2707 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 2708 if (tstate == NULL) 2709 return (NULL); 2710 2711 /* 2712 * If we have allocated a master tstate, copy user settings from 2713 * the master tstate (taken from SRAM or the EEPROM) for this 2714 * channel, but reset our current and goal settings to async/narrow 2715 * until an initiator talks to us. 2716 */ 2717 if (master_tstate != NULL) { 2718 memcpy(tstate, master_tstate, sizeof(*tstate)); 2719 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2720 for (i = 0; i < 16; i++) { 2721 memset(&tstate->transinfo[i].curr, 0, 2722 sizeof(tstate->transinfo[i].curr)); 2723 memset(&tstate->transinfo[i].goal, 0, 2724 sizeof(tstate->transinfo[i].goal)); 2725 } 2726 } else 2727 memset(tstate, 0, sizeof(*tstate)); 2728 ahd->enabled_targets[scsi_id] = tstate; 2729 return (tstate); 2730 } 2731 2732 #ifdef AHD_TARGET_MODE 2733 /* 2734 * Free per target mode instance (ID we respond to as a target) 2735 * transfer negotiation data structures. 2736 */ 2737 static void 2738 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2739 { 2740 struct ahd_tmode_tstate *tstate; 2741 2742 /* 2743 * Don't clean up our "master" tstate. 2744 * It has our default user settings. 2745 */ 2746 if (scsi_id == ahd->our_id 2747 && force == FALSE) 2748 return; 2749 2750 tstate = ahd->enabled_targets[scsi_id]; 2751 if (tstate != NULL) 2752 free(tstate, M_DEVBUF); 2753 ahd->enabled_targets[scsi_id] = NULL; 2754 } 2755 #endif 2756 2757 /* 2758 * Called when we have an active connection to a target on the bus, 2759 * this function finds the nearest period to the input period limited 2760 * by the capabilities of the bus connectivity of and sync settings for 2761 * the target. 2762 */ 2763 void 2764 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2765 struct ahd_initiator_tinfo *tinfo, 2766 u_int *period, u_int *ppr_options, role_t role) 2767 { 2768 struct ahd_transinfo *transinfo; 2769 u_int maxsync; 2770 2771 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2772 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2773 maxsync = AHD_SYNCRATE_PACED; 2774 } else { 2775 maxsync = AHD_SYNCRATE_ULTRA; 2776 /* Can't do DT related options on an SE bus */ 2777 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2778 } 2779 /* 2780 * Never allow a value higher than our current goal 2781 * period otherwise we may allow a target initiated 2782 * negotiation to go above the limit as set by the 2783 * user. In the case of an initiator initiated 2784 * sync negotiation, we limit based on the user 2785 * setting. This allows the system to still accept 2786 * incoming negotiations even if target initiated 2787 * negotiation is not performed. 2788 */ 2789 if (role == ROLE_TARGET) 2790 transinfo = &tinfo->user; 2791 else 2792 transinfo = &tinfo->goal; 2793 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2794 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2795 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2796 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2797 } 2798 if (transinfo->period == 0) { 2799 *period = 0; 2800 *ppr_options = 0; 2801 } else { 2802 *period = MAX(*period, transinfo->period); 2803 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2804 } 2805 } 2806 2807 /* 2808 * Look up the valid period to SCSIRATE conversion in our table. 2809 * Return the period and offset that should be sent to the target 2810 * if this was the beginning of an SDTR. 2811 */ 2812 void 2813 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2814 u_int *ppr_options, u_int maxsync) 2815 { 2816 if (*period < maxsync) 2817 *period = maxsync; 2818 2819 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2820 && *period > AHD_SYNCRATE_MIN_DT) 2821 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2822 2823 if (*period > AHD_SYNCRATE_MIN) 2824 *period = 0; 2825 2826 /* Honor PPR option conformance rules. */ 2827 if (*period > AHD_SYNCRATE_PACED) 2828 *ppr_options &= ~MSG_EXT_PPR_RTI; 2829 2830 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2831 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2832 2833 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2834 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2835 2836 /* Skip all PACED only entries if IU is not available */ 2837 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2838 && *period < AHD_SYNCRATE_DT) 2839 *period = AHD_SYNCRATE_DT; 2840 2841 /* Skip all DT only entries if DT is not available */ 2842 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2843 && *period < AHD_SYNCRATE_ULTRA2) 2844 *period = AHD_SYNCRATE_ULTRA2; 2845 } 2846 2847 /* 2848 * Truncate the given synchronous offset to a value the 2849 * current adapter type and syncrate are capable of. 2850 */ 2851 void 2852 ahd_validate_offset(struct ahd_softc *ahd, 2853 struct ahd_initiator_tinfo *tinfo, 2854 u_int period, u_int *offset, int wide, 2855 role_t role) 2856 { 2857 u_int maxoffset; 2858 2859 /* Limit offset to what we can do */ 2860 if (period == 0) 2861 maxoffset = 0; 2862 else if (period <= AHD_SYNCRATE_PACED) { 2863 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2864 maxoffset = MAX_OFFSET_PACED_BUG; 2865 else 2866 maxoffset = MAX_OFFSET_PACED; 2867 } else 2868 maxoffset = MAX_OFFSET_NON_PACED; 2869 *offset = MIN(*offset, maxoffset); 2870 if (tinfo != NULL) { 2871 if (role == ROLE_TARGET) 2872 *offset = MIN(*offset, tinfo->user.offset); 2873 else 2874 *offset = MIN(*offset, tinfo->goal.offset); 2875 } 2876 } 2877 2878 /* 2879 * Truncate the given transfer width parameter to a value the 2880 * current adapter type is capable of. 2881 */ 2882 void 2883 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2884 u_int *bus_width, role_t role) 2885 { 2886 switch (*bus_width) { 2887 default: 2888 if (ahd->features & AHD_WIDE) { 2889 /* Respond Wide */ 2890 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2891 break; 2892 } 2893 /* FALLTHROUGH */ 2894 case MSG_EXT_WDTR_BUS_8_BIT: 2895 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2896 break; 2897 } 2898 if (tinfo != NULL) { 2899 if (role == ROLE_TARGET) 2900 *bus_width = MIN(tinfo->user.width, *bus_width); 2901 else 2902 *bus_width = MIN(tinfo->goal.width, *bus_width); 2903 } 2904 } 2905 2906 /* 2907 * Update the bitmask of targets for which the controller should 2908 * negotiate with at the next convenient opportunity. This currently 2909 * means the next time we send the initial identify messages for 2910 * a new transaction. 2911 */ 2912 int 2913 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2914 struct ahd_tmode_tstate *tstate, 2915 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2916 { 2917 u_int auto_negotiate_orig; 2918 2919 auto_negotiate_orig = tstate->auto_negotiate; 2920 if (neg_type == AHD_NEG_ALWAYS) { 2921 /* 2922 * Force our "current" settings to be 2923 * unknown so that unless a bus reset 2924 * occurs the need to renegotiate is 2925 * recorded persistently. 2926 */ 2927 if ((ahd->features & AHD_WIDE) != 0) 2928 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2929 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2930 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2931 } 2932 if (tinfo->curr.period != tinfo->goal.period 2933 || tinfo->curr.width != tinfo->goal.width 2934 || tinfo->curr.offset != tinfo->goal.offset 2935 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2936 || (neg_type == AHD_NEG_IF_NON_ASYNC 2937 && (tinfo->goal.offset != 0 2938 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2939 || tinfo->goal.ppr_options != 0))) 2940 tstate->auto_negotiate |= devinfo->target_mask; 2941 else 2942 tstate->auto_negotiate &= ~devinfo->target_mask; 2943 2944 return (auto_negotiate_orig != tstate->auto_negotiate); 2945 } 2946 2947 /* 2948 * Update the user/goal/curr tables of synchronous negotiation 2949 * parameters as well as, in the case of a current or active update, 2950 * any data structures on the host controller. In the case of an 2951 * active update, the specified target is currently talking to us on 2952 * the bus, so the transfer parameter update must take effect 2953 * immediately. 2954 */ 2955 void 2956 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2957 u_int period, u_int offset, u_int ppr_options, 2958 u_int type, int paused) 2959 { 2960 struct ahd_initiator_tinfo *tinfo; 2961 struct ahd_tmode_tstate *tstate; 2962 u_int old_period; 2963 u_int old_offset; 2964 u_int old_ppr; 2965 int active; 2966 int update_needed; 2967 2968 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2969 update_needed = 0; 2970 2971 if (period == 0 || offset == 0) { 2972 period = 0; 2973 offset = 0; 2974 } 2975 2976 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2977 devinfo->target, &tstate); 2978 2979 if ((type & AHD_TRANS_USER) != 0) { 2980 tinfo->user.period = period; 2981 tinfo->user.offset = offset; 2982 tinfo->user.ppr_options = ppr_options; 2983 } 2984 2985 if ((type & AHD_TRANS_GOAL) != 0) { 2986 tinfo->goal.period = period; 2987 tinfo->goal.offset = offset; 2988 tinfo->goal.ppr_options = ppr_options; 2989 } 2990 2991 old_period = tinfo->curr.period; 2992 old_offset = tinfo->curr.offset; 2993 old_ppr = tinfo->curr.ppr_options; 2994 2995 if ((type & AHD_TRANS_CUR) != 0 2996 && (old_period != period 2997 || old_offset != offset 2998 || old_ppr != ppr_options)) { 2999 3000 update_needed++; 3001 3002 tinfo->curr.period = period; 3003 tinfo->curr.offset = offset; 3004 tinfo->curr.ppr_options = ppr_options; 3005 3006 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3007 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3008 3009 if (bootverbose) { 3010 if (offset != 0) { 3011 int options; 3012 3013 printf("%s: target %d synchronous with " 3014 "period = 0x%x, offset = 0x%x", 3015 ahd_name(ahd), devinfo->target, 3016 period, offset); 3017 options = 0; 3018 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3019 printf("(RDSTRM"); 3020 options++; 3021 } 3022 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3023 printf("%s", options ? "|DT" : "(DT"); 3024 options++; 3025 } 3026 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3027 printf("%s", options ? "|IU" : "(IU"); 3028 options++; 3029 } 3030 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3031 printf("%s", options ? "|RTI" : "(RTI"); 3032 options++; 3033 } 3034 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3035 printf("%s", options ? "|QAS" : "(QAS"); 3036 options++; 3037 } 3038 if (options != 0) 3039 printf(")\n"); 3040 else 3041 printf("\n"); 3042 } else { 3043 printf("%s: target %d using " 3044 "asynchronous transfers%s\n", 3045 ahd_name(ahd), devinfo->target, 3046 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3047 ? "(QAS)" : ""); 3048 } 3049 } 3050 } 3051 /* 3052 * Always refresh the neg-table to handle the case of the 3053 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3054 * We will always renegotiate in that case if this is a 3055 * packetized request. Also manage the busfree expected flag 3056 * from this common routine so that we catch changes due to 3057 * WDTR or SDTR messages. 3058 */ 3059 if ((type & AHD_TRANS_CUR) != 0) { 3060 if (!paused) 3061 ahd_pause(ahd); 3062 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3063 if (!paused) 3064 ahd_unpause(ahd); 3065 if (ahd->msg_type != MSG_TYPE_NONE) { 3066 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3067 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3068 #ifdef AHD_DEBUG 3069 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3070 ahd_print_devinfo(ahd, devinfo); 3071 printf("Expecting IU Change busfree\n"); 3072 } 3073 #endif 3074 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3075 | MSG_FLAG_IU_REQ_CHANGED; 3076 } 3077 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3078 #ifdef AHD_DEBUG 3079 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3080 printf("PPR with IU_REQ outstanding\n"); 3081 #endif 3082 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3083 } 3084 } 3085 } 3086 3087 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3088 tinfo, AHD_NEG_TO_GOAL); 3089 3090 if (update_needed && active) 3091 ahd_update_pending_scbs(ahd); 3092 } 3093 3094 /* 3095 * Update the user/goal/curr tables of wide negotiation 3096 * parameters as well as, in the case of a current or active update, 3097 * any data structures on the host controller. In the case of an 3098 * active update, the specified target is currently talking to us on 3099 * the bus, so the transfer parameter update must take effect 3100 * immediately. 3101 */ 3102 void 3103 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3104 u_int width, u_int type, int paused) 3105 { 3106 struct ahd_initiator_tinfo *tinfo; 3107 struct ahd_tmode_tstate *tstate; 3108 u_int oldwidth; 3109 int active; 3110 int update_needed; 3111 3112 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3113 update_needed = 0; 3114 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3115 devinfo->target, &tstate); 3116 3117 if ((type & AHD_TRANS_USER) != 0) 3118 tinfo->user.width = width; 3119 3120 if ((type & AHD_TRANS_GOAL) != 0) 3121 tinfo->goal.width = width; 3122 3123 oldwidth = tinfo->curr.width; 3124 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 3125 3126 update_needed++; 3127 3128 tinfo->curr.width = width; 3129 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3130 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3131 3132 if (bootverbose) { 3133 printf("%s: target %d using %dbit transfers\n", 3134 ahd_name(ahd), devinfo->target, 3135 8 * (0x01 << width)); 3136 } 3137 } 3138 3139 if ((type & AHD_TRANS_CUR) != 0) { 3140 if (!paused) 3141 ahd_pause(ahd); 3142 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3143 if (!paused) 3144 ahd_unpause(ahd); 3145 } 3146 3147 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3148 tinfo, AHD_NEG_TO_GOAL); 3149 if (update_needed && active) 3150 ahd_update_pending_scbs(ahd); 3151 3152 } 3153 3154 /* 3155 * Update the current state of tagged queuing for a given target. 3156 */ 3157 void 3158 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3159 ahd_queue_alg alg) 3160 { 3161 ahd_platform_set_tags(ahd, devinfo, alg); 3162 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3163 devinfo->lun, AC_TRANSFER_NEG, &alg); 3164 } 3165 3166 static void 3167 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3168 struct ahd_transinfo *tinfo) 3169 { 3170 ahd_mode_state saved_modes; 3171 u_int period; 3172 u_int ppr_opts; 3173 u_int con_opts; 3174 u_int offset; 3175 u_int saved_negoaddr; 3176 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 3177 3178 saved_modes = ahd_save_modes(ahd); 3179 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3180 3181 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 3182 ahd_outb(ahd, NEGOADDR, devinfo->target); 3183 period = tinfo->period; 3184 offset = tinfo->offset; 3185 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 3186 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 3187 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 3188 con_opts = 0; 3189 if (period == 0) 3190 period = AHD_SYNCRATE_ASYNC; 3191 if (period == AHD_SYNCRATE_160) { 3192 3193 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3194 /* 3195 * When the SPI4 spec was finalized, PACE transfers 3196 * was not made a configurable option in the PPR 3197 * message. Instead it is assumed to be enabled for 3198 * any syncrate faster than 80MHz. Nevertheless, 3199 * Harpoon2A4 allows this to be configurable. 3200 * 3201 * Harpoon2A4 also assumes at most 2 data bytes per 3202 * negotiated REQ/ACK offset. Paced transfers take 3203 * 4, so we must adjust our offset. 3204 */ 3205 ppr_opts |= PPROPT_PACE; 3206 offset *= 2; 3207 3208 /* 3209 * Harpoon2A assumed that there would be a 3210 * fallback rate between 160MHz and 80Mhz, 3211 * so 7 is used as the period factor rather 3212 * than 8 for 160MHz. 3213 */ 3214 period = AHD_SYNCRATE_REVA_160; 3215 } 3216 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 3217 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3218 ~AHD_PRECOMP_MASK; 3219 } else { 3220 /* 3221 * Precomp should be disabled for non-paced transfers. 3222 */ 3223 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 3224 3225 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 3226 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 3227 /* 3228 * Slow down our CRC interval to be 3229 * compatible with devices that can't 3230 * handle a CRC at full speed. 3231 */ 3232 con_opts |= ENSLOWCRC; 3233 } 3234 } 3235 3236 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 3237 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 3238 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 3239 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 3240 3241 ahd_outb(ahd, NEGPERIOD, period); 3242 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 3243 ahd_outb(ahd, NEGOFFSET, offset); 3244 3245 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 3246 con_opts |= WIDEXFER; 3247 3248 /* 3249 * During packetized transfers, the target will 3250 * give us the opportunity to send command packets 3251 * without us asserting attention. 3252 */ 3253 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3254 con_opts |= ENAUTOATNO; 3255 ahd_outb(ahd, NEGCONOPTS, con_opts); 3256 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 3257 ahd_restore_modes(ahd, saved_modes); 3258 } 3259 3260 /* 3261 * When the transfer settings for a connection change, setup for 3262 * negotiation in pending SCBs to effect the change as quickly as 3263 * possible. We also cancel any negotiations that are scheduled 3264 * for inflight SCBs that have not been started yet. 3265 */ 3266 static void 3267 ahd_update_pending_scbs(struct ahd_softc *ahd) 3268 { 3269 struct scb *pending_scb; 3270 int pending_scb_count; 3271 u_int scb_tag; 3272 int paused; 3273 u_int saved_scbptr; 3274 ahd_mode_state saved_modes; 3275 3276 /* 3277 * Traverse the pending SCB list and ensure that all of the 3278 * SCBs there have the proper settings. We can only safely 3279 * clear the negotiation required flag (setting requires the 3280 * execution queue to be modified) and this is only possible 3281 * if we are not already attempting to select out for this 3282 * SCB. For this reason, all callers only call this routine 3283 * if we are changing the negotiation settings for the currently 3284 * active transaction on the bus. 3285 */ 3286 pending_scb_count = 0; 3287 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3288 struct ahd_devinfo devinfo; 3289 struct hardware_scb *pending_hscb; 3290 struct ahd_initiator_tinfo *tinfo; 3291 struct ahd_tmode_tstate *tstate; 3292 3293 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 3294 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 3295 devinfo.our_scsiid, 3296 devinfo.target, &tstate); 3297 pending_hscb = pending_scb->hscb; 3298 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 3299 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 3300 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 3301 pending_hscb->control &= ~MK_MESSAGE; 3302 } 3303 ahd_sync_scb(ahd, pending_scb, 3304 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3305 pending_scb_count++; 3306 } 3307 3308 if (pending_scb_count == 0) 3309 return; 3310 3311 if (ahd_is_paused(ahd)) { 3312 paused = 1; 3313 } else { 3314 paused = 0; 3315 ahd_pause(ahd); 3316 } 3317 3318 /* 3319 * Force the sequencer to reinitialize the selection for 3320 * the command at the head of the execution queue if it 3321 * has already been setup. The negotiation changes may 3322 * effect whether we select-out with ATN. 3323 */ 3324 saved_modes = ahd_save_modes(ahd); 3325 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3326 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3327 saved_scbptr = ahd_get_scbptr(ahd); 3328 /* Ensure that the hscbs down on the card match the new information */ 3329 for (scb_tag = 0; scb_tag < ahd->scb_data.maxhscbs; scb_tag++) { 3330 struct hardware_scb *pending_hscb; 3331 u_int control; 3332 3333 pending_scb = ahd_lookup_scb(ahd, scb_tag); 3334 if (pending_scb == NULL) 3335 continue; 3336 ahd_set_scbptr(ahd, scb_tag); 3337 pending_hscb = pending_scb->hscb; 3338 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3339 control &= ~MK_MESSAGE; 3340 control |= pending_hscb->control & MK_MESSAGE; 3341 ahd_outb(ahd, SCB_CONTROL, control); 3342 } 3343 ahd_set_scbptr(ahd, saved_scbptr); 3344 ahd_restore_modes(ahd, saved_modes); 3345 3346 if (paused == 0) 3347 ahd_unpause(ahd); 3348 } 3349 3350 /**************************** Pathing Information *****************************/ 3351 static void 3352 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3353 { 3354 ahd_mode_state saved_modes; 3355 u_int saved_scsiid; 3356 role_t role; 3357 int our_id; 3358 3359 saved_modes = ahd_save_modes(ahd); 3360 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3361 3362 if (ahd_inb(ahd, SSTAT0) & TARGET) 3363 role = ROLE_TARGET; 3364 else 3365 role = ROLE_INITIATOR; 3366 3367 if (role == ROLE_TARGET 3368 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3369 /* We were selected, so pull our id from TARGIDIN */ 3370 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3371 } else if (role == ROLE_TARGET) 3372 our_id = ahd_inb(ahd, TOWNID); 3373 else 3374 our_id = ahd_inb(ahd, IOWNID); 3375 3376 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3377 ahd_compile_devinfo(devinfo, 3378 our_id, 3379 SCSIID_TARGET(ahd, saved_scsiid), 3380 ahd_inb(ahd, SAVED_LUN), 3381 SCSIID_CHANNEL(ahd, saved_scsiid), 3382 role); 3383 ahd_restore_modes(ahd, saved_modes); 3384 } 3385 3386 void 3387 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3388 { 3389 printf("%s:%c:%d:%d: (0x%x) ", ahd_name(ahd), 'A', 3390 devinfo->target, devinfo->lun, ahd_get_scbptr(ahd)); 3391 } 3392 3393 struct ahd_phase_table_entry* 3394 ahd_lookup_phase_entry(int phase) 3395 { 3396 struct ahd_phase_table_entry *entry; 3397 struct ahd_phase_table_entry *last_entry; 3398 3399 /* 3400 * num_phases doesn't include the default entry which 3401 * will be returned if the phase doesn't match. 3402 */ 3403 last_entry = &ahd_phase_table[num_phases]; 3404 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3405 if (phase == entry->phase) 3406 break; 3407 } 3408 return (entry); 3409 } 3410 3411 void 3412 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3413 u_int lun, char channel, role_t role) 3414 { 3415 devinfo->our_scsiid = our_id; 3416 devinfo->target = target; 3417 devinfo->lun = lun; 3418 devinfo->target_offset = target; 3419 devinfo->channel = channel; 3420 devinfo->role = role; 3421 if (channel == 'B') 3422 devinfo->target_offset += 8; 3423 devinfo->target_mask = (0x01 << devinfo->target_offset); 3424 } 3425 3426 static void 3427 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3428 struct scb *scb) 3429 { 3430 role_t role; 3431 int our_id; 3432 3433 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3434 role = ROLE_INITIATOR; 3435 if ((scb->hscb->control & TARGET_SCB) != 0) 3436 role = ROLE_TARGET; 3437 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3438 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3439 } 3440 3441 3442 /************************ Message Phase Processing ****************************/ 3443 /* 3444 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3445 * or enters the initial message out phase, we are interrupted. Fill our 3446 * outgoing message buffer with the appropriate message and begin handing 3447 * the message phase(s) manually. 3448 */ 3449 static void 3450 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3451 struct scb *scb) 3452 { 3453 /* 3454 * To facilitate adding multiple messages together, 3455 * each routine should increment the index and len 3456 * variables instead of setting them explicitly. 3457 */ 3458 ahd->msgout_index = 0; 3459 ahd->msgout_len = 0; 3460 3461 if (ahd_currently_packetized(ahd)) 3462 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3463 3464 if (ahd->send_msg_perror 3465 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3466 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3467 ahd->msgout_len++; 3468 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3469 #ifdef AHD_DEBUG 3470 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3471 printf("Setting up for Parity Error delivery\n"); 3472 #endif 3473 return; 3474 } else if (scb == NULL) { 3475 printf("%s: WARNING. No pending message for " 3476 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3477 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3478 ahd->msgout_len++; 3479 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3480 return; 3481 } 3482 3483 if ((scb->flags & SCB_DEVICE_RESET) == 0 3484 && (scb->flags & SCB_PACKETIZED) == 0 3485 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3486 u_int identify_msg; 3487 3488 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3489 if ((scb->hscb->control & DISCENB) != 0) 3490 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3491 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3492 ahd->msgout_len++; 3493 3494 if ((scb->hscb->control & TAG_ENB) != 0) { 3495 ahd->msgout_buf[ahd->msgout_index++] = 3496 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3497 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3498 ahd->msgout_len += 2; 3499 } 3500 } 3501 3502 if (scb->flags & SCB_DEVICE_RESET) { 3503 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3504 ahd->msgout_len++; 3505 ahd_print_path(ahd, scb); 3506 printf("Bus Device Reset Message Sent\n"); 3507 /* 3508 * Clear our selection hardware in advance of 3509 * the busfree. We may have an entry in the waiting 3510 * Q for this target, and we don't want to go about 3511 * selecting while we handle the busfree and blow it 3512 * away. 3513 */ 3514 ahd_outb(ahd, SCSISEQ0, 0); 3515 } else if ((scb->flags & SCB_ABORT) != 0) { 3516 3517 if ((scb->hscb->control & TAG_ENB) != 0) { 3518 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3519 } else { 3520 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3521 } 3522 ahd->msgout_len++; 3523 ahd_print_path(ahd, scb); 3524 printf("Abort%s Message Sent\n", 3525 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3526 /* 3527 * Clear our selection hardware in advance of 3528 * the busfree. We may have an entry in the waiting 3529 * Q for this target, and we don't want to go about 3530 * selecting while we handle the busfree and blow it 3531 * away. 3532 */ 3533 ahd_outb(ahd, SCSISEQ0, 0); 3534 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3535 ahd_build_transfer_msg(ahd, devinfo); 3536 /* 3537 * Clear our selection hardware in advance of potential 3538 * PPR IU status change busfree. We may have an entry in 3539 * the waiting Q for this target, and we don't want to go 3540 * about selecting while we handle the busfree and blow 3541 * it away. 3542 */ 3543 ahd_outb(ahd, SCSISEQ0, 0); 3544 } else { 3545 printf("ahd_intr: AWAITING_MSG for an SCB that " 3546 "does not have a waiting message\n"); 3547 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3548 devinfo->target_mask); 3549 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3550 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3551 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3552 scb->flags); 3553 } 3554 3555 /* 3556 * Clear the MK_MESSAGE flag from the SCB so we aren't 3557 * asked to send this message again. 3558 */ 3559 ahd_outb(ahd, SCB_CONTROL, 3560 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3561 scb->hscb->control &= ~MK_MESSAGE; 3562 ahd->msgout_index = 0; 3563 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3564 } 3565 3566 /* 3567 * Build an appropriate transfer negotiation message for the 3568 * currently active target. 3569 */ 3570 static void 3571 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3572 { 3573 /* 3574 * We need to initiate transfer negotiations. 3575 * If our current and goal settings are identical, 3576 * we want to renegotiate due to a check condition. 3577 */ 3578 struct ahd_initiator_tinfo *tinfo; 3579 struct ahd_tmode_tstate *tstate; 3580 int dowide; 3581 int dosync; 3582 int doppr; 3583 u_int period; 3584 u_int ppr_options; 3585 u_int offset; 3586 3587 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3588 devinfo->target, &tstate); 3589 /* 3590 * Filter our period based on the current connection. 3591 * If we can't perform DT transfers on this segment (not in LVD 3592 * mode for instance), then our decision to issue a PPR message 3593 * may change. 3594 */ 3595 period = tinfo->goal.period; 3596 offset = tinfo->goal.offset; 3597 ppr_options = tinfo->goal.ppr_options; 3598 /* Target initiated PPR is not allowed in the SCSI spec */ 3599 if (devinfo->role == ROLE_TARGET) 3600 ppr_options = 0; 3601 ahd_devlimited_syncrate(ahd, tinfo, &period, 3602 &ppr_options, devinfo->role); 3603 dowide = tinfo->curr.width != tinfo->goal.width; 3604 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3605 /* 3606 * Only use PPR if we have options that need it, even if the device 3607 * claims to support it. There might be an expander in the way 3608 * that doesn't. 3609 */ 3610 doppr = ppr_options != 0; 3611 3612 if (!dowide && !dosync && !doppr) { 3613 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3614 dosync = tinfo->goal.offset != 0; 3615 } 3616 3617 if (!dowide && !dosync && !doppr) { 3618 /* 3619 * Force async with a WDTR message if we have a wide bus, 3620 * or just issue an SDTR with a 0 offset. 3621 */ 3622 if ((ahd->features & AHD_WIDE) != 0) 3623 dowide = 1; 3624 else 3625 dosync = 1; 3626 3627 if (bootverbose) { 3628 ahd_print_devinfo(ahd, devinfo); 3629 printf("Ensuring async\n"); 3630 } 3631 } 3632 /* Target initiated PPR is not allowed in the SCSI spec */ 3633 if (devinfo->role == ROLE_TARGET) 3634 doppr = 0; 3635 3636 /* 3637 * Both the PPR message and SDTR message require the 3638 * goal syncrate to be limited to what the target device 3639 * is capable of handling (based on whether an LVD->SE 3640 * expander is on the bus), so combine these two cases. 3641 * Regardless, guarantee that if we are using WDTR and SDTR 3642 * messages that WDTR comes first. 3643 */ 3644 if (doppr || (dosync && !dowide)) { 3645 3646 offset = tinfo->goal.offset; 3647 ahd_validate_offset(ahd, tinfo, period, &offset, 3648 doppr ? tinfo->goal.width 3649 : tinfo->curr.width, 3650 devinfo->role); 3651 if (doppr) { 3652 ahd_construct_ppr(ahd, devinfo, period, offset, 3653 tinfo->goal.width, ppr_options); 3654 } else { 3655 ahd_construct_sdtr(ahd, devinfo, period, offset); 3656 } 3657 } else { 3658 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3659 } 3660 } 3661 3662 /* 3663 * Build a synchronous negotiation message in our message 3664 * buffer based on the input parameters. 3665 */ 3666 static void 3667 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3668 u_int period, u_int offset) 3669 { 3670 if (offset == 0) 3671 period = AHD_ASYNC_XFER_PERIOD; 3672 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3673 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3674 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3675 ahd->msgout_buf[ahd->msgout_index++] = period; 3676 ahd->msgout_buf[ahd->msgout_index++] = offset; 3677 ahd->msgout_len += 5; 3678 if (bootverbose) { 3679 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3680 ahd_name(ahd), devinfo->channel, devinfo->target, 3681 devinfo->lun, period, offset); 3682 } 3683 } 3684 3685 /* 3686 * Build a wide negotiation message in our message 3687 * buffer based on the input parameters. 3688 */ 3689 static void 3690 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3691 u_int bus_width) 3692 { 3693 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3694 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3695 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3696 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3697 ahd->msgout_len += 4; 3698 if (bootverbose) { 3699 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3700 ahd_name(ahd), devinfo->channel, devinfo->target, 3701 devinfo->lun, bus_width); 3702 } 3703 } 3704 3705 /* 3706 * Build a parallel protocol request message in our message 3707 * buffer based on the input parameters. 3708 */ 3709 static void 3710 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3711 u_int period, u_int offset, u_int bus_width, 3712 u_int ppr_options) 3713 { 3714 /* 3715 * Always request precompensation from 3716 * the other target if we are running 3717 * at paced syncrates. 3718 */ 3719 if (period <= AHD_SYNCRATE_PACED) 3720 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3721 if (offset == 0) 3722 period = AHD_ASYNC_XFER_PERIOD; 3723 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3724 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3725 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3726 ahd->msgout_buf[ahd->msgout_index++] = period; 3727 ahd->msgout_buf[ahd->msgout_index++] = 0; 3728 ahd->msgout_buf[ahd->msgout_index++] = offset; 3729 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3730 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3731 ahd->msgout_len += 8; 3732 if (bootverbose) { 3733 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period 0x%x, " 3734 "offset 0x%x, ppr_options 0x%x\n", ahd_name(ahd), 3735 devinfo->channel, devinfo->target, devinfo->lun, 3736 bus_width, period, offset, ppr_options); 3737 } 3738 } 3739 3740 /* 3741 * Clear any active message state. 3742 */ 3743 static void 3744 ahd_clear_msg_state(struct ahd_softc *ahd) 3745 { 3746 ahd_mode_state saved_modes; 3747 3748 saved_modes = ahd_save_modes(ahd); 3749 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3750 ahd->send_msg_perror = 0; 3751 ahd->msg_flags = MSG_FLAG_NONE; 3752 ahd->msgout_len = 0; 3753 ahd->msgin_index = 0; 3754 ahd->msg_type = MSG_TYPE_NONE; 3755 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3756 /* 3757 * The target didn't care to respond to our 3758 * message request, so clear ATN. 3759 */ 3760 ahd_outb(ahd, CLRSINT1, CLRATNO); 3761 } 3762 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3763 ahd_outb(ahd, SEQ_FLAGS2, 3764 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3765 ahd_restore_modes(ahd, saved_modes); 3766 } 3767 3768 /* 3769 * Manual message loop handler. 3770 */ 3771 static void 3772 ahd_handle_message_phase(struct ahd_softc *ahd) 3773 { 3774 struct ahd_devinfo devinfo; 3775 u_int bus_phase; 3776 int end_session; 3777 3778 ahd_fetch_devinfo(ahd, &devinfo); 3779 end_session = FALSE; 3780 bus_phase = ahd_inb(ahd, LASTPHASE); 3781 3782 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3783 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3784 ahd_outb(ahd, LQCTL2, LQIRETRY); 3785 } 3786 reswitch: 3787 switch (ahd->msg_type) { 3788 case MSG_TYPE_INITIATOR_MSGOUT: 3789 { 3790 int lastbyte; 3791 int phasemis; 3792 int msgdone; 3793 3794 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3795 panic("HOST_MSG_LOOP interrupt with no active message"); 3796 3797 #ifdef AHD_DEBUG 3798 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3799 ahd_print_devinfo(ahd, &devinfo); 3800 printf("INITIATOR_MSG_OUT"); 3801 } 3802 #endif 3803 phasemis = bus_phase != P_MESGOUT; 3804 if (phasemis) { 3805 #ifdef AHD_DEBUG 3806 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3807 printf(" PHASEMIS %s\n", 3808 ahd_lookup_phase_entry(bus_phase) 3809 ->phasemsg); 3810 } 3811 #endif 3812 if (bus_phase == P_MESGIN) { 3813 /* 3814 * Change gears and see if 3815 * this messages is of interest to 3816 * us or should be passed back to 3817 * the sequencer. 3818 */ 3819 ahd_outb(ahd, CLRSINT1, CLRATNO); 3820 ahd->send_msg_perror = 0; 3821 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3822 ahd->msgin_index = 0; 3823 goto reswitch; 3824 } 3825 end_session = TRUE; 3826 break; 3827 } 3828 3829 if (ahd->send_msg_perror) { 3830 ahd_outb(ahd, CLRSINT1, CLRATNO); 3831 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3832 #ifdef AHD_DEBUG 3833 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3834 printf(" byte 0x%x\n", ahd->send_msg_perror); 3835 #endif 3836 /* 3837 * If we are notifying the target of a CRC error 3838 * during packetized operations, the target is 3839 * within its rights to acknowledge our message 3840 * with a busfree. 3841 */ 3842 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3843 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3844 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3845 3846 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3847 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3848 break; 3849 } 3850 3851 msgdone = ahd->msgout_index == ahd->msgout_len; 3852 if (msgdone) { 3853 /* 3854 * The target has requested a retry. 3855 * Re-assert ATN, reset our message index to 3856 * 0, and try again. 3857 */ 3858 ahd->msgout_index = 0; 3859 ahd_assert_atn(ahd); 3860 } 3861 3862 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3863 if (lastbyte) { 3864 /* Last byte is signified by dropping ATN */ 3865 ahd_outb(ahd, CLRSINT1, CLRATNO); 3866 } 3867 3868 /* 3869 * Clear our interrupt status and present 3870 * the next byte on the bus. 3871 */ 3872 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3873 #ifdef AHD_DEBUG 3874 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3875 printf(" byte 0x%x\n", 3876 ahd->msgout_buf[ahd->msgout_index]); 3877 #endif 3878 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3879 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3880 break; 3881 } 3882 case MSG_TYPE_INITIATOR_MSGIN: 3883 { 3884 int phasemis; 3885 int message_done; 3886 3887 #ifdef AHD_DEBUG 3888 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3889 ahd_print_devinfo(ahd, &devinfo); 3890 printf("INITIATOR_MSG_IN"); 3891 } 3892 #endif 3893 phasemis = bus_phase != P_MESGIN; 3894 if (phasemis) { 3895 #ifdef AHD_DEBUG 3896 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3897 printf(" PHASEMIS %s\n", 3898 ahd_lookup_phase_entry(bus_phase) 3899 ->phasemsg); 3900 } 3901 #endif 3902 ahd->msgin_index = 0; 3903 if (bus_phase == P_MESGOUT 3904 && (ahd->send_msg_perror != 0 3905 || (ahd->msgout_len != 0 3906 && ahd->msgout_index == 0))) { 3907 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3908 goto reswitch; 3909 } 3910 end_session = TRUE; 3911 break; 3912 } 3913 3914 /* Pull the byte in without acking it */ 3915 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3916 #ifdef AHD_DEBUG 3917 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3918 printf(" byte 0x%x\n", 3919 ahd->msgin_buf[ahd->msgin_index]); 3920 #endif 3921 3922 message_done = ahd_parse_msg(ahd, &devinfo); 3923 3924 if (message_done) { 3925 /* 3926 * Clear our incoming message buffer in case there 3927 * is another message following this one. 3928 */ 3929 ahd->msgin_index = 0; 3930 3931 /* 3932 * If this message illicited a response, 3933 * assert ATN so the target takes us to the 3934 * message out phase. 3935 */ 3936 if (ahd->msgout_len != 0) { 3937 #ifdef AHD_DEBUG 3938 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3939 ahd_print_devinfo(ahd, &devinfo); 3940 printf("Asserting ATN for response\n"); 3941 } 3942 #endif 3943 ahd_assert_atn(ahd); 3944 } 3945 } else 3946 ahd->msgin_index++; 3947 3948 if (message_done == MSGLOOP_TERMINATED) { 3949 end_session = TRUE; 3950 } else { 3951 /* Ack the byte */ 3952 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3953 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3954 } 3955 break; 3956 } 3957 case MSG_TYPE_TARGET_MSGIN: 3958 { 3959 int msgdone; 3960 int msgout_request; 3961 3962 /* 3963 * By default, the message loop will continue. 3964 */ 3965 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3966 3967 if (ahd->msgout_len == 0) 3968 panic("Target MSGIN with no active message"); 3969 3970 /* 3971 * If we interrupted a mesgout session, the initiator 3972 * will not know this until our first REQ. So, we 3973 * only honor mesgout requests after we've sent our 3974 * first byte. 3975 */ 3976 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3977 && ahd->msgout_index > 0) 3978 msgout_request = TRUE; 3979 else 3980 msgout_request = FALSE; 3981 3982 if (msgout_request) { 3983 3984 /* 3985 * Change gears and see if 3986 * this messages is of interest to 3987 * us or should be passed back to 3988 * the sequencer. 3989 */ 3990 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3991 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3992 ahd->msgin_index = 0; 3993 /* Dummy read to REQ for first byte */ 3994 ahd_inb(ahd, SCSIDAT); 3995 ahd_outb(ahd, SXFRCTL0, 3996 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3997 break; 3998 } 3999 4000 msgdone = ahd->msgout_index == ahd->msgout_len; 4001 if (msgdone) { 4002 ahd_outb(ahd, SXFRCTL0, 4003 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4004 end_session = TRUE; 4005 break; 4006 } 4007 4008 /* 4009 * Present the next byte on the bus. 4010 */ 4011 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4012 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4013 break; 4014 } 4015 case MSG_TYPE_TARGET_MSGOUT: 4016 { 4017 int lastbyte; 4018 int msgdone; 4019 4020 /* 4021 * By default, the message loop will continue. 4022 */ 4023 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4024 4025 /* 4026 * The initiator signals that this is 4027 * the last byte by dropping ATN. 4028 */ 4029 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4030 4031 /* 4032 * Read the latched byte, but turn off SPIOEN first 4033 * so that we don't inadvertently cause a REQ for the 4034 * next byte. 4035 */ 4036 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4037 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4038 msgdone = ahd_parse_msg(ahd, &devinfo); 4039 if (msgdone == MSGLOOP_TERMINATED) { 4040 /* 4041 * The message is *really* done in that it caused 4042 * us to go to bus free. The sequencer has already 4043 * been reset at this point, so pull the ejection 4044 * handle. 4045 */ 4046 return; 4047 } 4048 4049 ahd->msgin_index++; 4050 4051 /* 4052 * XXX Read spec about initiator dropping ATN too soon 4053 * and use msgdone to detect it. 4054 */ 4055 if (msgdone == MSGLOOP_MSGCOMPLETE) { 4056 ahd->msgin_index = 0; 4057 4058 /* 4059 * If this message illicited a response, transition 4060 * to the Message in phase and send it. 4061 */ 4062 if (ahd->msgout_len != 0) { 4063 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4064 ahd_outb(ahd, SXFRCTL0, 4065 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4066 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4067 ahd->msgin_index = 0; 4068 break; 4069 } 4070 } 4071 4072 if (lastbyte) 4073 end_session = TRUE; 4074 else { 4075 /* Ask for the next byte. */ 4076 ahd_outb(ahd, SXFRCTL0, 4077 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4078 } 4079 4080 break; 4081 } 4082 default: 4083 panic("Unknown REQINIT message type"); 4084 } 4085 4086 if (end_session) { 4087 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 4088 printf("%s: Returning to Idle Loop\n", 4089 ahd_name(ahd)); 4090 ahd_clear_msg_state(ahd); 4091 4092 /* 4093 * Perform the equivalent of a clear_target_state. 4094 */ 4095 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 4096 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 4097 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 4098 } else { 4099 ahd_clear_msg_state(ahd); 4100 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 4101 } 4102 } 4103 } 4104 4105 /* 4106 * See if we sent a particular extended message to the target. 4107 * If "full" is true, return true only if the target saw the full 4108 * message. If "full" is false, return true if the target saw at 4109 * least the first byte of the message. 4110 */ 4111 static int 4112 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 4113 { 4114 int found; 4115 u_int index; 4116 4117 found = FALSE; 4118 index = 0; 4119 4120 while (index < ahd->msgout_len) { 4121 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 4122 u_int end_index; 4123 4124 end_index = index + 1 + ahd->msgout_buf[index + 1]; 4125 if (ahd->msgout_buf[index+2] == msgval 4126 && type == AHDMSG_EXT) { 4127 4128 if (full) { 4129 if (ahd->msgout_index > end_index) 4130 found = TRUE; 4131 } else if (ahd->msgout_index > index) 4132 found = TRUE; 4133 } 4134 index = end_index; 4135 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 4136 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 4137 4138 /* Skip tag type and tag id or residue param*/ 4139 index += 2; 4140 } else { 4141 /* Single byte message */ 4142 if (type == AHDMSG_1B 4143 && ahd->msgout_index > index 4144 && (ahd->msgout_buf[index] == msgval 4145 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 4146 && msgval == MSG_IDENTIFYFLAG))) 4147 found = TRUE; 4148 index++; 4149 } 4150 4151 if (found) 4152 break; 4153 } 4154 return (found); 4155 } 4156 4157 /* 4158 * Wait for a complete incoming message, parse it, and respond accordingly. 4159 */ 4160 static int 4161 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4162 { 4163 struct ahd_initiator_tinfo *tinfo; 4164 struct ahd_tmode_tstate *tstate; 4165 int reject; 4166 int done; 4167 int response; 4168 4169 done = MSGLOOP_IN_PROG; 4170 response = FALSE; 4171 reject = FALSE; 4172 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4173 devinfo->target, &tstate); 4174 4175 /* 4176 * Parse as much of the message as is available, 4177 * rejecting it if we don't support it. When 4178 * the entire message is available and has been 4179 * handled, return MSGLOOP_MSGCOMPLETE, indicating 4180 * that we have parsed an entire message. 4181 * 4182 * In the case of extended messages, we accept the length 4183 * byte outright and perform more checking once we know the 4184 * extended message type. 4185 */ 4186 switch (ahd->msgin_buf[0]) { 4187 case MSG_DISCONNECT: 4188 case MSG_SAVEDATAPOINTER: 4189 case MSG_CMDCOMPLETE: 4190 case MSG_RESTOREPOINTERS: 4191 case MSG_IGN_WIDE_RESIDUE: 4192 /* 4193 * End our message loop as these are messages 4194 * the sequencer handles on its own. 4195 */ 4196 done = MSGLOOP_TERMINATED; 4197 break; 4198 case MSG_MESSAGE_REJECT: 4199 response = ahd_handle_msg_reject(ahd, devinfo); 4200 /* FALLTHROUGH */ 4201 case MSG_NOOP: 4202 done = MSGLOOP_MSGCOMPLETE; 4203 break; 4204 case MSG_EXTENDED: 4205 { 4206 /* Wait for enough of the message to begin validation */ 4207 if (ahd->msgin_index < 2) 4208 break; 4209 switch (ahd->msgin_buf[2]) { 4210 case MSG_EXT_SDTR: 4211 { 4212 u_int period; 4213 u_int ppr_options; 4214 u_int offset; 4215 u_int saved_offset; 4216 4217 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 4218 reject = TRUE; 4219 break; 4220 } 4221 4222 /* 4223 * Wait until we have both args before validating 4224 * and acting on this message. 4225 * 4226 * Add one to MSG_EXT_SDTR_LEN to account for 4227 * the extended message preamble. 4228 */ 4229 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 4230 break; 4231 4232 period = ahd->msgin_buf[3]; 4233 ppr_options = 0; 4234 saved_offset = offset = ahd->msgin_buf[4]; 4235 ahd_devlimited_syncrate(ahd, tinfo, &period, 4236 &ppr_options, devinfo->role); 4237 ahd_validate_offset(ahd, tinfo, period, &offset, 4238 tinfo->curr.width, devinfo->role); 4239 if (bootverbose) { 4240 printf("(%s:%c:%d:%d): Received " 4241 "SDTR period %x, offset %x\n\t" 4242 "Filtered to period %x, offset %x\n", 4243 ahd_name(ahd), devinfo->channel, 4244 devinfo->target, devinfo->lun, 4245 ahd->msgin_buf[3], saved_offset, 4246 period, offset); 4247 } 4248 ahd_set_syncrate(ahd, devinfo, period, 4249 offset, ppr_options, 4250 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4251 /*paused*/TRUE); 4252 4253 /* 4254 * See if we initiated Sync Negotiation 4255 * and didn't have to fall down to async 4256 * transfers. 4257 */ 4258 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 4259 /* We started it */ 4260 if (saved_offset != offset) { 4261 /* Went too low - force async */ 4262 reject = TRUE; 4263 } 4264 } else { 4265 /* 4266 * Send our own SDTR in reply 4267 */ 4268 if (bootverbose 4269 && devinfo->role == ROLE_INITIATOR) { 4270 printf("(%s:%c:%d:%d): Target " 4271 "Initiated SDTR\n", 4272 ahd_name(ahd), devinfo->channel, 4273 devinfo->target, devinfo->lun); 4274 } 4275 ahd->msgout_index = 0; 4276 ahd->msgout_len = 0; 4277 ahd_construct_sdtr(ahd, devinfo, 4278 period, offset); 4279 ahd->msgout_index = 0; 4280 response = TRUE; 4281 } 4282 done = MSGLOOP_MSGCOMPLETE; 4283 break; 4284 } 4285 case MSG_EXT_WDTR: 4286 { 4287 u_int bus_width; 4288 u_int saved_width; 4289 u_int sending_reply; 4290 4291 sending_reply = FALSE; 4292 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 4293 reject = TRUE; 4294 break; 4295 } 4296 4297 /* 4298 * Wait until we have our arg before validating 4299 * and acting on this message. 4300 * 4301 * Add one to MSG_EXT_WDTR_LEN to account for 4302 * the extended message preamble. 4303 */ 4304 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 4305 break; 4306 4307 bus_width = ahd->msgin_buf[3]; 4308 saved_width = bus_width; 4309 ahd_validate_width(ahd, tinfo, &bus_width, 4310 devinfo->role); 4311 if (bootverbose) { 4312 printf("(%s:%c:%d:%d): Received WDTR " 4313 "%x filtered to %x\n", 4314 ahd_name(ahd), devinfo->channel, 4315 devinfo->target, devinfo->lun, 4316 saved_width, bus_width); 4317 } 4318 4319 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4320 /* 4321 * Don't send a WDTR back to the 4322 * target, since we asked first. 4323 * If the width went higher than our 4324 * request, reject it. 4325 */ 4326 if (saved_width > bus_width) { 4327 reject = TRUE; 4328 printf("(%s:%c:%d:%d): requested %dBit " 4329 "transfers. Rejecting...\n", 4330 ahd_name(ahd), devinfo->channel, 4331 devinfo->target, devinfo->lun, 4332 8 * (0x01 << bus_width)); 4333 bus_width = 0; 4334 } 4335 } else { 4336 /* 4337 * Send our own WDTR in reply 4338 */ 4339 if (bootverbose 4340 && devinfo->role == ROLE_INITIATOR) { 4341 printf("(%s:%c:%d:%d): Target " 4342 "Initiated WDTR\n", 4343 ahd_name(ahd), devinfo->channel, 4344 devinfo->target, devinfo->lun); 4345 } 4346 ahd->msgout_index = 0; 4347 ahd->msgout_len = 0; 4348 ahd_construct_wdtr(ahd, devinfo, bus_width); 4349 ahd->msgout_index = 0; 4350 response = TRUE; 4351 sending_reply = TRUE; 4352 } 4353 /* 4354 * After a wide message, we are async, but 4355 * some devices don't seem to honor this portion 4356 * of the spec. Force a renegotiation of the 4357 * sync component of our transfer agreement even 4358 * if our goal is async. By updating our width 4359 * after forcing the negotiation, we avoid 4360 * renegotiating for width. 4361 */ 4362 ahd_update_neg_request(ahd, devinfo, tstate, 4363 tinfo, AHD_NEG_ALWAYS); 4364 ahd_set_width(ahd, devinfo, bus_width, 4365 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4366 /*paused*/TRUE); 4367 if (sending_reply == FALSE && reject == FALSE) { 4368 4369 /* 4370 * We will always have an SDTR to send. 4371 */ 4372 ahd->msgout_index = 0; 4373 ahd->msgout_len = 0; 4374 ahd_build_transfer_msg(ahd, devinfo); 4375 ahd->msgout_index = 0; 4376 response = TRUE; 4377 } 4378 done = MSGLOOP_MSGCOMPLETE; 4379 break; 4380 } 4381 case MSG_EXT_PPR: 4382 { 4383 u_int period; 4384 u_int offset; 4385 u_int bus_width; 4386 u_int ppr_options; 4387 u_int saved_width; 4388 u_int saved_offset; 4389 u_int saved_ppr_options; 4390 4391 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4392 reject = TRUE; 4393 break; 4394 } 4395 4396 /* 4397 * Wait until we have all args before validating 4398 * and acting on this message. 4399 * 4400 * Add one to MSG_EXT_PPR_LEN to account for 4401 * the extended message preamble. 4402 */ 4403 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4404 break; 4405 4406 period = ahd->msgin_buf[3]; 4407 offset = ahd->msgin_buf[5]; 4408 bus_width = ahd->msgin_buf[6]; 4409 saved_width = bus_width; 4410 ppr_options = ahd->msgin_buf[7]; 4411 /* 4412 * According to the spec, a DT only 4413 * period factor with no DT option 4414 * set implies async. 4415 */ 4416 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4417 && period <= 9) 4418 offset = 0; 4419 saved_ppr_options = ppr_options; 4420 saved_offset = offset; 4421 4422 /* 4423 * Transfer options are only available if we 4424 * are negotiating wide. 4425 */ 4426 if (bus_width == 0) 4427 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4428 4429 ahd_validate_width(ahd, tinfo, &bus_width, 4430 devinfo->role); 4431 ahd_devlimited_syncrate(ahd, tinfo, &period, 4432 &ppr_options, devinfo->role); 4433 ahd_validate_offset(ahd, tinfo, period, &offset, 4434 bus_width, devinfo->role); 4435 4436 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4437 /* 4438 * If we are unable to do any of the 4439 * requested options (we went too low), 4440 * then we'll have to reject the message. 4441 */ 4442 if (saved_width > bus_width 4443 || saved_offset != offset 4444 || saved_ppr_options != ppr_options) { 4445 reject = TRUE; 4446 period = 0; 4447 offset = 0; 4448 bus_width = 0; 4449 ppr_options = 0; 4450 } 4451 } else { 4452 if (devinfo->role != ROLE_TARGET) 4453 printf("(%s:%c:%d:%d): Target " 4454 "Initiated PPR\n", 4455 ahd_name(ahd), devinfo->channel, 4456 devinfo->target, devinfo->lun); 4457 else 4458 printf("(%s:%c:%d:%d): Initiator " 4459 "Initiated PPR\n", 4460 ahd_name(ahd), devinfo->channel, 4461 devinfo->target, devinfo->lun); 4462 ahd->msgout_index = 0; 4463 ahd->msgout_len = 0; 4464 ahd_construct_ppr(ahd, devinfo, period, offset, 4465 bus_width, ppr_options); 4466 ahd->msgout_index = 0; 4467 response = TRUE; 4468 } 4469 if (bootverbose) { 4470 printf("(%s:%c:%d:%d): Received PPR width %x, " 4471 "period %x, offset %x,options %x\n" 4472 "\tFiltered to width %x, period %x, " 4473 "offset %x, options %x\n", 4474 ahd_name(ahd), devinfo->channel, 4475 devinfo->target, devinfo->lun, 4476 saved_width, ahd->msgin_buf[3], 4477 saved_offset, saved_ppr_options, 4478 bus_width, period, offset, ppr_options); 4479 } 4480 ahd_set_width(ahd, devinfo, bus_width, 4481 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4482 /*paused*/TRUE); 4483 ahd_set_syncrate(ahd, devinfo, period, 4484 offset, ppr_options, 4485 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4486 /*paused*/TRUE); 4487 4488 done = MSGLOOP_MSGCOMPLETE; 4489 break; 4490 } 4491 default: 4492 /* Unknown extended message. Reject it. */ 4493 reject = TRUE; 4494 break; 4495 } 4496 break; 4497 } 4498 #ifdef AHD_TARGET_MODE 4499 case MSG_BUS_DEV_RESET: 4500 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4501 CAM_BDR_SENT, 4502 "Bus Device Reset Received", 4503 /*verbose_level*/0); 4504 ahd_restart(ahd); 4505 done = MSGLOOP_TERMINATED; 4506 break; 4507 case MSG_ABORT_TAG: 4508 case MSG_ABORT: 4509 case MSG_CLEAR_QUEUE: 4510 { 4511 int tag; 4512 4513 /* Target mode messages */ 4514 if (devinfo->role != ROLE_TARGET) { 4515 reject = TRUE; 4516 break; 4517 } 4518 tag = SCB_LIST_NULL; 4519 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4520 tag = ahd_inb(ahd, INITIATOR_TAG); 4521 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4522 devinfo->lun, tag, ROLE_TARGET, 4523 CAM_REQ_ABORTED); 4524 4525 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4526 if (tstate != NULL) { 4527 struct ahd_tmode_lstate* lstate; 4528 4529 lstate = tstate->enabled_luns[devinfo->lun]; 4530 if (lstate != NULL) { 4531 ahd_queue_lstate_event(ahd, lstate, 4532 devinfo->our_scsiid, 4533 ahd->msgin_buf[0], 4534 /*arg*/tag); 4535 ahd_send_lstate_events(ahd, lstate); 4536 } 4537 } 4538 ahd_restart(ahd); 4539 done = MSGLOOP_TERMINATED; 4540 break; 4541 } 4542 #endif 4543 case MSG_QAS_REQUEST: 4544 #ifdef AHD_DEBUG 4545 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4546 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4547 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4548 #endif 4549 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4550 /* FALLTHROUGH */ 4551 case MSG_TERM_IO_PROC: 4552 default: 4553 reject = TRUE; 4554 break; 4555 } 4556 4557 if (reject) { 4558 /* 4559 * Setup to reject the message. 4560 */ 4561 ahd->msgout_index = 0; 4562 ahd->msgout_len = 1; 4563 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4564 done = MSGLOOP_MSGCOMPLETE; 4565 response = TRUE; 4566 } 4567 4568 if (done != MSGLOOP_IN_PROG && !response) 4569 /* Clear the outgoing message buffer */ 4570 ahd->msgout_len = 0; 4571 4572 return (done); 4573 } 4574 4575 /* 4576 * Process a message reject message. 4577 */ 4578 static int 4579 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4580 { 4581 /* 4582 * What we care about here is if we had an 4583 * outstanding SDTR or WDTR message for this 4584 * target. If we did, this is a signal that 4585 * the target is refusing negotiation. 4586 */ 4587 struct scb *scb; 4588 struct ahd_initiator_tinfo *tinfo; 4589 struct ahd_tmode_tstate *tstate; 4590 u_int scb_index; 4591 u_int last_msg; 4592 int response = 0; 4593 4594 scb_index = ahd_get_scbptr(ahd); 4595 scb = ahd_lookup_scb(ahd, scb_index); 4596 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4597 devinfo->our_scsiid, 4598 devinfo->target, &tstate); 4599 /* Might be necessary */ 4600 last_msg = ahd_inb(ahd, LAST_MSG); 4601 4602 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4603 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4604 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4605 /* 4606 * Target may not like our SPI-4 PPR Options. 4607 * Attempt to negotiate 80MHz which will turn 4608 * off these options. 4609 */ 4610 if (bootverbose) { 4611 printf("(%s:%c:%d:%d): PPR Rejected. " 4612 "Trying simple U160 PPR\n", 4613 ahd_name(ahd), devinfo->channel, 4614 devinfo->target, devinfo->lun); 4615 } 4616 tinfo->goal.period = AHD_SYNCRATE_DT; 4617 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4618 | MSG_EXT_PPR_QAS_REQ 4619 | MSG_EXT_PPR_DT_REQ; 4620 } else { 4621 /* 4622 * Target does not support the PPR message. 4623 * Attempt to negotiate SPI-2 style. 4624 */ 4625 if (bootverbose) { 4626 printf("(%s:%c:%d:%d): PPR Rejected. " 4627 "Trying WDTR/SDTR\n", 4628 ahd_name(ahd), devinfo->channel, 4629 devinfo->target, devinfo->lun); 4630 } 4631 tinfo->goal.ppr_options = 0; 4632 tinfo->curr.transport_version = 2; 4633 tinfo->goal.transport_version = 2; 4634 } 4635 ahd->msgout_index = 0; 4636 ahd->msgout_len = 0; 4637 ahd_build_transfer_msg(ahd, devinfo); 4638 ahd->msgout_index = 0; 4639 response = 1; 4640 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4641 4642 /* note 8bit xfers */ 4643 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4644 "8bit transfers\n", ahd_name(ahd), 4645 devinfo->channel, devinfo->target, devinfo->lun); 4646 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4647 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4648 /*paused*/TRUE); 4649 /* 4650 * No need to clear the sync rate. If the target 4651 * did not accept the command, our syncrate is 4652 * unaffected. If the target started the negotiation, 4653 * but rejected our response, we already cleared the 4654 * sync rate before sending our WDTR. 4655 */ 4656 if (tinfo->goal.offset != tinfo->curr.offset) { 4657 4658 /* Start the sync negotiation */ 4659 ahd->msgout_index = 0; 4660 ahd->msgout_len = 0; 4661 ahd_build_transfer_msg(ahd, devinfo); 4662 ahd->msgout_index = 0; 4663 response = 1; 4664 } 4665 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4666 /* note asynch xfers and clear flag */ 4667 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4668 /*offset*/0, /*ppr_options*/0, 4669 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4670 /*paused*/TRUE); 4671 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4672 "Using asynchronous transfers\n", 4673 ahd_name(ahd), devinfo->channel, 4674 devinfo->target, devinfo->lun); 4675 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4676 int tag_type; 4677 int mask; 4678 4679 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4680 4681 if (tag_type == MSG_SIMPLE_TASK) { 4682 printf("(%s:%c:%d:%d): refuses tagged commands. " 4683 "Performing non-tagged I/O\n", ahd_name(ahd), 4684 devinfo->channel, devinfo->target, devinfo->lun); 4685 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4686 mask = ~0x23; 4687 } else { 4688 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4689 "Performing simple queue tagged I/O only\n", 4690 ahd_name(ahd), devinfo->channel, devinfo->target, 4691 devinfo->lun, tag_type == MSG_ORDERED_Q_TAG 4692 ? "ordered" : "head of queue"); 4693 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4694 mask = ~0x03; 4695 } 4696 4697 /* 4698 * Resend the identify for this CCB as the target 4699 * may believe that the selection is invalid otherwise. 4700 */ 4701 ahd_outb(ahd, SCB_CONTROL, 4702 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4703 scb->hscb->control &= mask; 4704 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4705 /*type*/MSG_SIMPLE_TASK); 4706 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4707 ahd_assert_atn(ahd); 4708 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4709 SCB_GET_TAG(scb)); 4710 4711 /* 4712 * Requeue all tagged commands for this target 4713 * currently in our possession so they can be 4714 * converted to untagged commands. 4715 */ 4716 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4717 SCB_GET_CHANNEL(ahd, scb), 4718 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4719 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4720 SEARCH_COMPLETE); 4721 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4722 /* 4723 * Most likely the device believes that we had 4724 * previously negotiated packetized. 4725 */ 4726 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4727 | MSG_FLAG_IU_REQ_CHANGED; 4728 4729 ahd_force_renegotiation(ahd, devinfo); 4730 ahd->msgout_index = 0; 4731 ahd->msgout_len = 0; 4732 ahd_build_transfer_msg(ahd, devinfo); 4733 ahd->msgout_index = 0; 4734 response = 1; 4735 } else { 4736 /* 4737 * Otherwise, we ignore it. 4738 */ 4739 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4740 ahd_name(ahd), devinfo->channel, devinfo->target, 4741 last_msg); 4742 } 4743 return (response); 4744 } 4745 4746 /* 4747 * Process an ignore wide residue message. 4748 */ 4749 static void 4750 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4751 { 4752 u_int scb_index; 4753 struct scb *scb; 4754 4755 printf("%s: ahd_handle_ign_wide_residue\n", ahd_name(ahd)); 4756 4757 scb_index = ahd_get_scbptr(ahd); 4758 scb = ahd_lookup_scb(ahd, scb_index); 4759 /* 4760 * XXX Actually check data direction in the sequencer? 4761 * Perhaps add datadir to some spare bits in the hscb? 4762 */ 4763 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4764 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4765 /* 4766 * Ignore the message if we haven't 4767 * seen an appropriate data phase yet. 4768 */ 4769 } else { 4770 /* 4771 * If the residual occurred on the last 4772 * transfer and the transfer request was 4773 * expected to end on an odd count, do 4774 * nothing. Otherwise, subtract a byte 4775 * and update the residual count accordingly. 4776 */ 4777 uint32_t sgptr; 4778 4779 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4780 if ((sgptr & SG_LIST_NULL) != 0 4781 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4782 & SCB_XFERLEN_ODD) != 0) { 4783 /* 4784 * If the residual occurred on the last 4785 * transfer and the transfer request was 4786 * expected to end on an odd count, do 4787 * nothing. 4788 */ 4789 } else { 4790 uint32_t data_cnt; 4791 uint64_t data_addr; 4792 uint32_t sglen; 4793 4794 /* Pull in the rest of the sgptr */ 4795 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4796 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4797 if ((sgptr & SG_LIST_NULL) != 0) { 4798 /* 4799 * The residual data count is not updated 4800 * for the command run to completion case. 4801 * Explcitly zero the count. 4802 */ 4803 data_cnt &= ~AHD_SG_LEN_MASK; 4804 } 4805 data_addr = ahd_inq(ahd, SHADDR); 4806 data_cnt += 1; 4807 data_addr -= 1; 4808 sgptr &= SG_PTR_MASK; 4809 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4810 struct ahd_dma64_seg *sg; 4811 4812 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4813 4814 /* 4815 * The residual sg ptr points to the next S/G 4816 * to load so we must go back one. 4817 */ 4818 sg--; 4819 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4820 if (sg != scb->sg_list 4821 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4822 4823 sg--; 4824 sglen = ahd_le32toh(sg->len); 4825 /* 4826 * Preserve High Address and SG_LIST 4827 * bits while setting the count to 1. 4828 */ 4829 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4830 data_addr = ahd_le64toh(sg->addr) 4831 + (sglen & AHD_SG_LEN_MASK) 4832 - 1; 4833 4834 /* 4835 * Increment sg so it points to the 4836 * "next" sg. 4837 */ 4838 sg++; 4839 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4840 sg); 4841 } 4842 } else { 4843 struct ahd_dma_seg *sg; 4844 4845 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4846 4847 /* 4848 * The residual sg ptr points to the next S/G 4849 * to load so we must go back one. 4850 */ 4851 sg--; 4852 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4853 if (sg != scb->sg_list 4854 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4855 4856 sg--; 4857 sglen = ahd_le32toh(sg->len); 4858 /* 4859 * Preserve High Address and SG_LIST 4860 * bits while setting the count to 1. 4861 */ 4862 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4863 data_addr = ahd_le32toh(sg->addr) 4864 + (sglen & AHD_SG_LEN_MASK) 4865 - 1; 4866 4867 /* 4868 * Increment sg so it points to the 4869 * "next" sg. 4870 */ 4871 sg++; 4872 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4873 sg); 4874 } 4875 } 4876 /* 4877 * Toggle the "oddness" of the transfer length 4878 * to handle this mid-transfer ignore wide 4879 * residue. This ensures that the oddness is 4880 * correct for subsequent data transfers. 4881 */ 4882 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4883 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4884 ^ SCB_XFERLEN_ODD); 4885 4886 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4887 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4888 /* 4889 * The FIFO's pointers will be updated if/when the 4890 * sequencer re-enters a data phase. 4891 */ 4892 } 4893 } 4894 } 4895 4896 4897 /* 4898 * Reinitialize the data pointers for the active transfer 4899 * based on its current residual. 4900 */ 4901 static void 4902 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4903 { 4904 struct scb *scb; 4905 ahd_mode_state saved_modes; 4906 u_int scb_index; 4907 u_int wait; 4908 uint32_t sgptr; 4909 uint32_t resid; 4910 uint64_t dataptr; 4911 4912 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4913 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4914 4915 scb_index = ahd_get_scbptr(ahd); 4916 scb = ahd_lookup_scb(ahd, scb_index); 4917 4918 /* 4919 * Release and reacquire the FIFO so we 4920 * have a clean slate. 4921 */ 4922 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4923 wait = 1000; 4924 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 4925 ahd_delay(100); 4926 if (wait == 0) { 4927 ahd_print_path(ahd, scb); 4928 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4929 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4930 } 4931 saved_modes = ahd_save_modes(ahd); 4932 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4933 ahd_outb(ahd, DFFSTAT, 4934 ahd_inb(ahd, DFFSTAT) 4935 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4936 4937 /* 4938 * Determine initial values for data_addr and data_cnt 4939 * for resuming the data phase. 4940 */ 4941 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4942 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4943 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4944 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4945 sgptr &= SG_PTR_MASK; 4946 4947 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4948 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4949 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4950 4951 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4952 struct ahd_dma64_seg *sg; 4953 4954 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4955 4956 /* The residual sg_ptr always points to the next sg */ 4957 sg--; 4958 4959 dataptr = ahd_le64toh(sg->addr) 4960 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4961 - resid; 4962 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4963 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4964 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4965 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4966 } else { 4967 struct ahd_dma_seg *sg; 4968 4969 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4970 4971 /* The residual sg_ptr always points to the next sg */ 4972 sg--; 4973 4974 dataptr = ahd_le32toh(sg->addr) 4975 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4976 - resid; 4977 ahd_outb(ahd, HADDR + 4, 4978 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4979 } 4980 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4981 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4982 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4983 ahd_outb(ahd, HADDR, dataptr); 4984 ahd_outb(ahd, HCNT + 2, resid >> 16); 4985 ahd_outb(ahd, HCNT + 1, resid >> 8); 4986 ahd_outb(ahd, HCNT, resid); 4987 } 4988 4989 /* 4990 * Handle the effects of issuing a bus device reset message. 4991 */ 4992 static void 4993 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4994 u_int lun, cam_status status, const char *message, 4995 int verbose_level) 4996 { 4997 #ifdef AHD_TARGET_MODE 4998 struct ahd_tmode_tstate* tstate; 4999 #endif 5000 int found; 5001 5002 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5003 lun, SCB_LIST_NULL, devinfo->role, 5004 status); 5005 5006 #ifdef AHD_TARGET_MODE 5007 /* 5008 * Send an immediate notify ccb to all target mord peripheral 5009 * drivers affected by this action. 5010 */ 5011 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5012 if (tstate != NULL) { 5013 u_int cur_lun; 5014 u_int max_lun; 5015 5016 if (lun != CAM_LUN_WILDCARD) { 5017 cur_lun = 0; 5018 max_lun = AHD_NUM_LUNS - 1; 5019 } else { 5020 cur_lun = lun; 5021 max_lun = lun; 5022 } 5023 for (cur_lun <= max_lun; cur_lun++) { 5024 struct ahd_tmode_lstate* lstate; 5025 5026 lstate = tstate->enabled_luns[cur_lun]; 5027 if (lstate == NULL) 5028 continue; 5029 5030 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5031 MSG_BUS_DEV_RESET, /*arg*/0); 5032 ahd_send_lstate_events(ahd, lstate); 5033 } 5034 } 5035 #endif 5036 5037 /* 5038 * Go back to async/narrow transfers and renegotiate. 5039 */ 5040 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5041 AHD_TRANS_CUR, /*paused*/TRUE); 5042 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5043 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 5044 5045 ahd_send_async(ahd, devinfo->channel, devinfo->target, 5046 lun, AC_SENT_BDR, NULL); 5047 5048 if (message != NULL 5049 && (verbose_level <= bootverbose)) 5050 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5051 message, devinfo->channel, devinfo->target, found); 5052 } 5053 5054 #ifdef AHD_TARGET_MODE 5055 static void 5056 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5057 struct scb *scb) 5058 { 5059 5060 /* 5061 * To facilitate adding multiple messages together, 5062 * each routine should increment the index and len 5063 * variables instead of setting them explicitly. 5064 */ 5065 ahd->msgout_index = 0; 5066 ahd->msgout_len = 0; 5067 5068 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5069 ahd_build_transfer_msg(ahd, devinfo); 5070 else 5071 panic("ahd_intr: AWAITING target message with no message"); 5072 5073 ahd->msgout_index = 0; 5074 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5075 } 5076 #endif 5077 /**************************** Initialization **********************************/ 5078 static u_int 5079 ahd_sglist_size(struct ahd_softc *ahd) 5080 { 5081 bus_size_t list_size; 5082 5083 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5084 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5085 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5086 return (list_size); 5087 } 5088 5089 /* 5090 * Calculate the optimum S/G List allocation size. S/G elements used 5091 * for a given transaction must be physically contiguous. Assume the 5092 * OS will allocate full pages to us, so it doesn't make sense to request 5093 * less than a page. 5094 */ 5095 static u_int 5096 ahd_sglist_allocsize(struct ahd_softc *ahd) 5097 { 5098 bus_size_t sg_list_increment; 5099 bus_size_t sg_list_size; 5100 bus_size_t max_list_size; 5101 bus_size_t best_list_size; 5102 5103 /* Start out with the minimum required for AHD_NSEG. */ 5104 sg_list_increment = ahd_sglist_size(ahd); 5105 sg_list_size = sg_list_increment; 5106 5107 /* Get us as close as possible to a page in size. */ 5108 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 5109 sg_list_size += sg_list_increment; 5110 5111 /* 5112 * Try to reduce the amount of wastage by allocating 5113 * multiple pages. 5114 */ 5115 best_list_size = sg_list_size; 5116 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 5117 if (max_list_size < 4 * PAGE_SIZE) 5118 max_list_size = 4 * PAGE_SIZE; 5119 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 5120 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 5121 while ((sg_list_size + sg_list_increment) <= max_list_size 5122 && (sg_list_size % PAGE_SIZE) != 0) { 5123 bus_size_t new_mod; 5124 bus_size_t best_mod; 5125 5126 sg_list_size += sg_list_increment; 5127 new_mod = sg_list_size % PAGE_SIZE; 5128 best_mod = best_list_size % PAGE_SIZE; 5129 if (new_mod > best_mod || new_mod == 0) { 5130 best_list_size = sg_list_size; 5131 } 5132 } 5133 return (best_list_size); 5134 } 5135 5136 int 5137 ahd_softc_init(struct ahd_softc *ahd) 5138 { 5139 5140 ahd->unpause = 0; 5141 ahd->pause = PAUSE; 5142 return (0); 5143 } 5144 5145 void 5146 ahd_set_unit(struct ahd_softc *ahd, int unit) 5147 { 5148 ahd->unit = unit; 5149 } 5150 5151 void 5152 ahd_set_name(struct ahd_softc *ahd, char *name) 5153 { 5154 if (ahd->name != NULL) 5155 free(ahd->name, M_DEVBUF); 5156 ahd->name = name; 5157 } 5158 5159 void 5160 ahd_free(struct ahd_softc *ahd) 5161 { 5162 int i; 5163 5164 switch (ahd->init_level) { 5165 default: 5166 case 2: 5167 ahd_shutdown(ahd); 5168 TAILQ_REMOVE(&ahd_tailq, ahd, links); 5169 /* FALLTHROUGH */ 5170 case 1: 5171 bus_dmamap_unload(ahd->parent_dmat, ahd->shared_data_map.dmamap); 5172 bus_dmamap_destroy(ahd->parent_dmat, ahd->shared_data_map.dmamap); 5173 bus_dmamem_unmap(ahd->parent_dmat, (caddr_t)ahd->qoutfifo, ahd->shared_data_size); 5174 bus_dmamem_free(ahd->parent_dmat, &ahd->shared_data_map.dmasegs, ahd->shared_data_map.nseg); 5175 break; 5176 case 0: 5177 break; 5178 } 5179 5180 ahd_platform_free(ahd); 5181 ahd_fini_scbdata(ahd); 5182 for (i = 0; i < AHD_NUM_TARGETS; i++) { 5183 struct ahd_tmode_tstate *tstate; 5184 5185 tstate = ahd->enabled_targets[i]; 5186 if (tstate != NULL) { 5187 #if AHD_TARGET_MODE 5188 int j; 5189 5190 for (j = 0; j < AHD_NUM_LUNS; j++) { 5191 struct ahd_tmode_lstate *lstate; 5192 5193 lstate = tstate->enabled_luns[j]; 5194 if (lstate != NULL) { 5195 xpt_free_path(lstate->path); 5196 free(lstate, M_DEVBUF); 5197 } 5198 } 5199 #endif 5200 free(tstate, M_DEVBUF); 5201 } 5202 } 5203 #if AHD_TARGET_MODE 5204 if (ahd->black_hole != NULL) { 5205 xpt_free_path(ahd->black_hole->path); 5206 free(ahd->black_hole, M_DEVBUF); 5207 } 5208 #endif 5209 if (ahd->name != NULL) 5210 free(ahd->name, M_DEVBUF); 5211 if (ahd->seep_config != NULL) 5212 free(ahd->seep_config, M_DEVBUF); 5213 if (ahd->saved_stack != NULL) 5214 free(ahd->saved_stack, M_DEVBUF); 5215 #ifndef __FreeBSD__ 5216 free(ahd, M_DEVBUF); 5217 #endif 5218 return; 5219 } 5220 5221 void 5222 ahd_shutdown(void *arg) 5223 { 5224 struct ahd_softc *ahd; 5225 5226 ahd = (struct ahd_softc *)arg; 5227 5228 #ifdef AHD_DEBUG 5229 printf("%s: ahd_shutdown\n", ahd_name(ahd)); 5230 #endif 5231 /* 5232 * Stop periodic timer callbacks. 5233 */ 5234 ahd_timer_stop(&ahd->reset_timer); 5235 ahd_timer_stop(&ahd->stat_timer); 5236 5237 /* This will reset most registers to 0, but not all */ 5238 ahd_reset(ahd, /*reinit*/FALSE); 5239 } 5240 5241 /* 5242 * Reset the controller and record some information about it 5243 * that is only available just after a reset. If "reinit" is 5244 * non-zero, this reset occurred after initial configuration 5245 * and the caller requests that the chip be fully reinitialized 5246 * to a runable state. Chip interrupts are *not* enabled after 5247 * a reinitialization. The caller must enable interrupts via 5248 * ahd_intr_enable(). 5249 */ 5250 int 5251 ahd_reset(struct ahd_softc *ahd, int reinit) 5252 { 5253 u_int sxfrctl1; 5254 int wait; 5255 uint32_t cmd; 5256 struct ahd_pci_busdata *bd = ahd->bus_data; 5257 5258 /* 5259 * Preserve the value of the SXFRCTL1 register for all channels. 5260 * It contains settings that affect termination and we don't want 5261 * to disturb the integrity of the bus. 5262 */ 5263 ahd_pause(ahd); 5264 ahd_update_modes(ahd); 5265 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5266 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 5267 5268 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 5269 5270 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5271 uint32_t mod_cmd; 5272 5273 /* 5274 * A4 Razor #632 5275 * During the assertion of CHIPRST, the chip 5276 * does not disable its parity logic prior to 5277 * the start of the reset. This may cause a 5278 * parity error to be detected and thus a 5279 * spurious SERR or PERR assertion. Disble 5280 * PERR and SERR responses during the CHIPRST. 5281 */ 5282 mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 5283 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, mod_cmd); 5284 } 5285 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5286 5287 /* 5288 * Ensure that the reset has finished. We delay 1000us 5289 * prior to reading the register to make sure the chip 5290 * has sufficiently completed its reset to handle register 5291 * accesses. 5292 */ 5293 wait = 1000; 5294 do { 5295 ahd_delay(1000); 5296 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5297 5298 if (wait == 0) { 5299 printf("%s: WARNING - Failed chip reset! " 5300 "Trying to initialize anyway.\n", ahd_name(ahd)); 5301 } 5302 ahd_outb(ahd, HCNTRL, ahd->pause); 5303 5304 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5305 /* 5306 * Clear any latched PCI error status and restore 5307 * previous SERR and PERR response enables. 5308 */ 5309 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd | 5310 (PCI_STATUS_PARITY_ERROR | PCI_STATUS_TARGET_TARGET_ABORT | 5311 PCI_STATUS_MASTER_TARGET_ABORT | PCI_STATUS_MASTER_ABORT | 5312 PCI_STATUS_SPECIAL_ERROR)); 5313 } 5314 5315 /* 5316 * Mode should be SCSI after a chip reset, but lets 5317 * set it just to be safe. We touch the MODE_PTR 5318 * register directly so as to bypass the lazy update 5319 * ode in ahd_set_modes(). 5320 */ 5321 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5322 ahd_outb(ahd, MODE_PTR, 5323 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5324 5325 /* 5326 * Restore SXFRCTL1. 5327 * 5328 * We must always initialize STPWEN to 1 before we 5329 * restore the saved values. STPWEN is initialized 5330 * to a tri-state condition which can only be cleared 5331 * by turning it on. 5332 */ 5333 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5334 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5335 5336 /* Determine chip configuration */ 5337 ahd->features &= ~AHD_WIDE; 5338 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5339 ahd->features |= AHD_WIDE; 5340 5341 /* 5342 * If a recovery action has forced a chip reset, 5343 * re-initialize the chip to our liking. 5344 */ 5345 if (reinit != 0) 5346 ahd_chip_init(ahd); 5347 5348 return (0); 5349 } 5350 5351 /* 5352 * Determine the number of SCBs available on the controller 5353 */ 5354 int 5355 ahd_probe_scbs(struct ahd_softc *ahd) { 5356 int i; 5357 5358 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5359 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5360 for (i = 0; i < AHD_SCB_MAX; i++) { 5361 int j; 5362 int ret; 5363 5364 ahd_set_scbptr(ahd, i); 5365 ahd_outw(ahd, SCB_BASE, i); 5366 for (j = 2; j < 64; j++) 5367 ahd_outb(ahd, SCB_BASE+j, 0); 5368 /* Start out life as unallocated (needing an abort) */ 5369 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5370 ret = ahd_inw_scbram(ahd, SCB_BASE); 5371 if (ret != i) { 5372 printf("%s: ahd_probe_scbs (!=%d): returned 0x%x\n", ahd_name(ahd), i, ret); 5373 break; 5374 } 5375 ahd_set_scbptr(ahd, 0); 5376 ret = ahd_inw_scbram(ahd, SCB_BASE); 5377 if (ret != 0) { 5378 printf("ahd_probe_scbs (non zero): returned 0x%x\n", ret); 5379 break; 5380 } 5381 } 5382 return (i); 5383 } 5384 5385 static void 5386 ahd_initialize_hscbs(struct ahd_softc *ahd) 5387 { 5388 int i; 5389 5390 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5391 ahd_set_scbptr(ahd, i); 5392 5393 /* Clear the control byte. */ 5394 ahd_outb(ahd, SCB_CONTROL, 0); 5395 5396 /* Set the next pointer */ 5397 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5398 } 5399 } 5400 5401 static int 5402 ahd_init_scbdata(struct ahd_softc *ahd) 5403 { 5404 struct scb_data *scb_data; 5405 int i; 5406 5407 scb_data = &ahd->scb_data; 5408 TAILQ_INIT(&scb_data->free_scbs); 5409 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5410 LIST_INIT(&scb_data->free_scb_lists[i]); 5411 LIST_INIT(&scb_data->any_dev_free_scb_list); 5412 SLIST_INIT(&scb_data->hscb_maps); 5413 SLIST_INIT(&scb_data->sg_maps); 5414 SLIST_INIT(&scb_data->sense_maps); 5415 5416 /* Determine the number of hardware SCBs and initialize them */ 5417 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5418 if (scb_data->maxhscbs == 0) { 5419 printf("%s: No SCB space found\n", ahd_name(ahd)); 5420 return (ENXIO); 5421 } 5422 ahd_initialize_hscbs(ahd); 5423 5424 /* 5425 * Create our DMA tags. These tags define the kinds of device 5426 * accessible memory allocations and memory mappings we will 5427 * need to perform during normal operation. 5428 * 5429 * Unless we need to further restrict the allocation, we rely 5430 * on the restrictions of the parent dmat, hence the common 5431 * use of MAXADDR and MAXSIZE. 5432 */ 5433 5434 /* Perform initial CCB allocation */ 5435 ahd_alloc_scbs(ahd); 5436 5437 if (scb_data->numscbs == 0) { 5438 printf("%s: ahd_init_scbdata - " 5439 "Unable to allocate initial scbs\n", 5440 ahd_name(ahd)); 5441 goto error_exit; 5442 } 5443 5444 /* 5445 * Note that we were successfull 5446 */ 5447 return (0); 5448 5449 error_exit: 5450 5451 return (ENOMEM); 5452 } 5453 5454 static struct scb * 5455 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5456 { 5457 struct scb *scb; 5458 5459 /* 5460 * Look on the pending list. 5461 */ 5462 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5463 if (SCB_GET_TAG(scb) == tag) 5464 return (scb); 5465 } 5466 5467 /* 5468 * Then on all of the collision free lists. 5469 */ 5470 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5471 struct scb *list_scb; 5472 5473 list_scb = scb; 5474 do { 5475 if (SCB_GET_TAG(list_scb) == tag) 5476 return (list_scb); 5477 list_scb = LIST_NEXT(list_scb, collision_links); 5478 } while (list_scb); 5479 } 5480 5481 /* 5482 * And finally on the generic free list. 5483 */ 5484 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5485 if (SCB_GET_TAG(scb) == tag) 5486 return (scb); 5487 } 5488 5489 return (NULL); 5490 } 5491 5492 static void 5493 ahd_fini_scbdata(struct ahd_softc *ahd) 5494 { 5495 struct scb_data *scb_data; 5496 5497 scb_data = &ahd->scb_data; 5498 if (scb_data == NULL) 5499 return; 5500 5501 switch (scb_data->init_level) { 5502 default: 5503 case 3: 5504 { 5505 struct map_node *sns_map; 5506 5507 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5508 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5509 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5510 sns_map->dmamap, (caddr_t)sns_map->vaddr, 5511 &sns_map->dmasegs, sns_map->nseg); 5512 free(sns_map, M_DEVBUF); 5513 } 5514 /* FALLTHROUGH */ 5515 } 5516 case 2: 5517 { 5518 struct map_node *sg_map; 5519 5520 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5521 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5522 ahd_freedmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), 5523 sg_map->dmamap, (caddr_t)sg_map->vaddr, 5524 &sg_map->dmasegs, sg_map->nseg); 5525 free(sg_map, M_DEVBUF); 5526 } 5527 /* FALLTHROUGH */ 5528 } 5529 case 1: 5530 { 5531 struct map_node *hscb_map; 5532 5533 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5534 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5535 ahd_freedmamem(ahd->parent_dmat, PAGE_SIZE, 5536 hscb_map->dmamap, (caddr_t)hscb_map->vaddr, 5537 &hscb_map->dmasegs, hscb_map->nseg); 5538 free(hscb_map, M_DEVBUF); 5539 } 5540 /* FALLTHROUGH */ 5541 } 5542 case 0: 5543 break; 5544 } 5545 } 5546 5547 /* 5548 * DSP filter Bypass must be enabled until the first selection 5549 * after a change in bus mode (Razor #491 and #493). 5550 */ 5551 static void 5552 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5553 { 5554 ahd_mode_state saved_modes; 5555 5556 saved_modes = ahd_save_modes(ahd); 5557 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5558 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5559 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5560 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5561 #ifdef AHD_DEBUG 5562 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5563 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5564 #endif 5565 ahd_restore_modes(ahd, saved_modes); 5566 ahd->flags &= ~AHD_HAD_FIRST_SEL; 5567 } 5568 5569 static void 5570 ahd_iocell_first_selection(struct ahd_softc *ahd) 5571 { 5572 ahd_mode_state saved_modes; 5573 u_int sblkctl; 5574 5575 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 5576 return; 5577 saved_modes = ahd_save_modes(ahd); 5578 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5579 sblkctl = ahd_inb(ahd, SBLKCTL); 5580 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5581 #ifdef AHD_DEBUG 5582 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5583 printf("%s: iocell first selection\n", ahd_name(ahd)); 5584 #endif 5585 if ((sblkctl & ENAB40) != 0) { 5586 ahd_outb(ahd, DSPDATACTL, 5587 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5588 #ifdef AHD_DEBUG 5589 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5590 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5591 #endif 5592 } 5593 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5594 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5595 ahd_restore_modes(ahd, saved_modes); 5596 ahd->flags |= AHD_HAD_FIRST_SEL; 5597 } 5598 5599 /*************************** SCB Management ***********************************/ 5600 static void 5601 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5602 { 5603 struct scb_list *free_list; 5604 struct scb_tailq *free_tailq; 5605 struct scb *first_scb; 5606 5607 scb->flags |= SCB_ON_COL_LIST; 5608 AHD_SET_SCB_COL_IDX(scb, col_idx); 5609 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5610 free_tailq = &ahd->scb_data.free_scbs; 5611 first_scb = LIST_FIRST(free_list); 5612 if (first_scb != NULL) { 5613 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5614 } else { 5615 LIST_INSERT_HEAD(free_list, scb, collision_links); 5616 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5617 } 5618 } 5619 5620 static void 5621 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5622 { 5623 struct scb_list *free_list; 5624 struct scb_tailq *free_tailq; 5625 struct scb *first_scb; 5626 u_int col_idx; 5627 5628 scb->flags &= ~SCB_ON_COL_LIST; 5629 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5630 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5631 free_tailq = &ahd->scb_data.free_scbs; 5632 first_scb = LIST_FIRST(free_list); 5633 if (first_scb == scb) { 5634 struct scb *next_scb; 5635 5636 /* 5637 * Maintain order in the collision free 5638 * lists for fairness if this device has 5639 * other colliding tags active. 5640 */ 5641 next_scb = LIST_NEXT(scb, collision_links); 5642 if (next_scb != NULL) { 5643 TAILQ_INSERT_AFTER(free_tailq, scb, 5644 next_scb, links.tqe); 5645 } 5646 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5647 } 5648 LIST_REMOVE(scb, collision_links); 5649 } 5650 5651 /* 5652 * Get a free scb. If there are none, see if we can allocate a new SCB. 5653 */ 5654 struct scb * 5655 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5656 { 5657 struct scb *scb; 5658 int tries; 5659 5660 tries = 0; 5661 look_again: 5662 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5663 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5664 ahd_rem_col_list(ahd, scb); 5665 goto found; 5666 } 5667 } 5668 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5669 5670 if (tries++ != 0) 5671 return (NULL); 5672 ahd_alloc_scbs(ahd); 5673 goto look_again; 5674 } 5675 LIST_REMOVE(scb, links.le); 5676 if (col_idx != AHD_NEVER_COL_IDX 5677 && (scb->col_scb != NULL) 5678 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5679 LIST_REMOVE(scb->col_scb, links.le); 5680 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5681 } 5682 found: 5683 scb->flags |= SCB_ACTIVE; 5684 return (scb); 5685 } 5686 5687 /* 5688 * Return an SCB resource to the free list. 5689 */ 5690 void 5691 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5692 { 5693 5694 /* Clean up for the next user */ 5695 scb->flags = SCB_FLAG_NONE; 5696 scb->hscb->control = 0; 5697 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5698 5699 if (scb->col_scb == NULL) { 5700 5701 /* 5702 * No collision possible. Just free normally. 5703 */ 5704 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5705 scb, links.le); 5706 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5707 5708 /* 5709 * The SCB we might have collided with is on 5710 * a free collision list. Put both SCBs on 5711 * the generic list. 5712 */ 5713 ahd_rem_col_list(ahd, scb->col_scb); 5714 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5715 scb, links.le); 5716 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5717 scb->col_scb, links.le); 5718 } else if ((scb->col_scb->flags 5719 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5720 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5721 5722 /* 5723 * The SCB we might collide with on the next allocation 5724 * is still active in a non-packetized, tagged, context. 5725 * Put us on the SCB collision list. 5726 */ 5727 ahd_add_col_list(ahd, scb, 5728 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5729 } else { 5730 /* 5731 * The SCB we might collide with on the next allocation 5732 * is either active in a packetized context, or free. 5733 * Since we can't collide, put this SCB on the generic 5734 * free list. 5735 */ 5736 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5737 scb, links.le); 5738 } 5739 5740 ahd_platform_scb_free(ahd, scb); 5741 } 5742 5743 void 5744 ahd_alloc_scbs(struct ahd_softc *ahd) 5745 { 5746 struct scb_data *scb_data; 5747 struct scb *next_scb; 5748 struct hardware_scb *hscb; 5749 struct map_node *hscb_map; 5750 struct map_node *sg_map; 5751 struct map_node *sense_map; 5752 uint8_t *segs; 5753 uint8_t *sense_data; 5754 bus_addr_t hscb_busaddr; 5755 bus_addr_t sg_busaddr; 5756 bus_addr_t sense_busaddr; 5757 int newcount; 5758 int i; 5759 5760 scb_data = &ahd->scb_data; 5761 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5762 /* Can't allocate any more */ 5763 return; 5764 5765 KASSERT(scb_data->scbs_left >= 0); 5766 if (scb_data->scbs_left != 0) { 5767 int offset; 5768 5769 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5770 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5771 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5772 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5773 } else { 5774 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5775 5776 if (hscb_map == NULL) 5777 return; 5778 5779 memset(hscb_map, 0, sizeof(*hscb_map)); 5780 5781 /* Allocate the next batch of hardware SCBs */ 5782 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5783 &hscb_map->dmamap, (caddr_t *)&hscb_map->vaddr, 5784 &hscb_map->physaddr, &hscb_map->dmasegs, 5785 &hscb_map->nseg, ahd_name(ahd), 5786 "hardware SCB structures") < 0) { 5787 free(hscb_map, M_DEVBUF); 5788 return; 5789 } 5790 5791 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5792 5793 hscb = (struct hardware_scb *)hscb_map->vaddr; 5794 hscb_busaddr = hscb_map->physaddr; 5795 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5796 } 5797 5798 scb_data->init_level++; 5799 5800 if (scb_data->sgs_left != 0) { 5801 int offset; 5802 5803 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 5804 - scb_data->sgs_left) * ahd_sglist_size(ahd); 5805 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5806 segs = sg_map->vaddr + offset; 5807 sg_busaddr = sg_map->physaddr + offset; 5808 } else { 5809 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5810 5811 if (sg_map == NULL) 5812 return; 5813 5814 bzero(sg_map, sizeof(*sg_map)); 5815 5816 /* Allocate the next batch of S/G lists */ 5817 if (ahd_createdmamem(ahd->parent_dmat, ahd_sglist_allocsize(ahd), ahd->sc_dmaflags, 5818 &sg_map->dmamap, (caddr_t *)&sg_map->vaddr, 5819 &sg_map->physaddr, &sg_map->dmasegs, 5820 &sg_map->nseg, ahd_name(ahd), 5821 "SG data structures") < 0) { 5822 free(sg_map, M_DEVBUF); 5823 return; 5824 } 5825 5826 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5827 5828 segs = sg_map->vaddr; 5829 sg_busaddr = sg_map->physaddr; 5830 scb_data->sgs_left = 5831 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5832 #ifdef AHD_DEBUG 5833 if (ahd_debug & AHD_SHOW_MEMORY) 5834 printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd)); 5835 #endif 5836 } 5837 5838 scb_data->init_level++; 5839 5840 5841 if (scb_data->sense_left != 0) { 5842 int offset; 5843 5844 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5845 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5846 sense_data = sense_map->vaddr + offset; 5847 sense_busaddr = sense_map->physaddr + offset; 5848 } else { 5849 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5850 5851 if (sense_map == NULL) 5852 return; 5853 5854 bzero(sense_map, sizeof(*sense_map)); 5855 5856 /* Allocate the next batch of sense buffers */ 5857 if (ahd_createdmamem(ahd->parent_dmat, PAGE_SIZE, ahd->sc_dmaflags, 5858 &sense_map->dmamap, (caddr_t *)&sense_map->vaddr, 5859 &sense_map->physaddr, &sense_map->dmasegs, 5860 &sense_map->nseg, ahd_name(ahd), 5861 "Sense Data structures") < 0) { 5862 free(sense_map, M_DEVBUF); 5863 return; 5864 } 5865 5866 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5867 5868 sense_data = sense_map->vaddr; 5869 sense_busaddr = sense_map->physaddr; 5870 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5871 #ifdef AHD_DEBUG 5872 if (ahd_debug & AHD_SHOW_MEMORY) 5873 printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd)); 5874 #endif 5875 } 5876 5877 scb_data->init_level++; 5878 5879 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5880 newcount = MIN(newcount, scb_data->sgs_left); 5881 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5882 scb_data->sense_left -= newcount; 5883 scb_data->scbs_left -= newcount; 5884 scb_data->sgs_left -= newcount; 5885 5886 for (i = 0; i < newcount; i++) { 5887 u_int col_tag; 5888 5889 struct scb_platform_data *pdata; 5890 #ifndef __linux__ 5891 int error; 5892 #endif 5893 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5894 M_DEVBUF, M_NOWAIT); 5895 if (next_scb == NULL) 5896 break; 5897 5898 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5899 M_DEVBUF, M_NOWAIT); 5900 if (pdata == NULL) { 5901 free(next_scb, M_DEVBUF); 5902 break; 5903 } 5904 next_scb->platform_data = pdata; 5905 next_scb->hscb_map = hscb_map; 5906 next_scb->sg_map = sg_map; 5907 next_scb->sense_map = sense_map; 5908 next_scb->sg_list = segs; 5909 next_scb->sense_data = sense_data; 5910 next_scb->sense_busaddr = sense_busaddr; 5911 memset(hscb, 0, sizeof(*hscb)); 5912 next_scb->hscb = hscb; 5913 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5914 KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr && 5915 (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE); 5916 5917 /* 5918 * The sequencer always starts with the second entry. 5919 * The first entry is embedded in the scb. 5920 */ 5921 next_scb->sg_list_busaddr = sg_busaddr; 5922 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5923 next_scb->sg_list_busaddr 5924 += sizeof(struct ahd_dma64_seg); 5925 else 5926 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5927 next_scb->ahd_softc = ahd; 5928 next_scb->flags = SCB_FLAG_NONE; 5929 5930 error = bus_dmamap_create(ahd->parent_dmat, 5931 AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0, 5932 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahd->sc_dmaflags, 5933 &next_scb->dmamap); 5934 if (error != 0) { 5935 free(next_scb, M_DEVBUF); 5936 free(pdata, M_DEVBUF); 5937 break; 5938 } 5939 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5940 col_tag = scb_data->numscbs ^ 0x100; 5941 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5942 if (next_scb->col_scb != NULL) 5943 next_scb->col_scb->col_scb = next_scb; 5944 ahd_free_scb(ahd, next_scb); 5945 hscb++; 5946 hscb_busaddr += sizeof(*hscb); 5947 segs += ahd_sglist_size(ahd); 5948 sg_busaddr += ahd_sglist_size(ahd); 5949 sense_data += AHD_SENSE_BUFSIZE; 5950 sense_busaddr += AHD_SENSE_BUFSIZE; 5951 scb_data->numscbs++; 5952 } 5953 } 5954 5955 void 5956 ahd_controller_info(struct ahd_softc *ahd, char *tbuf, size_t l) 5957 { 5958 const char *speed; 5959 const char *type; 5960 int len; 5961 char *ep; 5962 5963 ep = tbuf + l; 5964 5965 len = snprintf(tbuf, ep - tbuf, "%s: ", 5966 ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5967 tbuf += len; 5968 5969 speed = "Ultra320 "; 5970 if ((ahd->features & AHD_WIDE) != 0) { 5971 type = "Wide "; 5972 } else { 5973 type = "Single "; 5974 } 5975 len = snprintf(tbuf, ep - tbuf, "%s%sChannel %c, SCSI Id=%d, ", 5976 speed, type, ahd->channel, ahd->our_id); 5977 tbuf += len; 5978 5979 snprintf(tbuf, ep - tbuf, "%s, %d SCBs", ahd->bus_description, 5980 ahd->scb_data.maxhscbs); 5981 } 5982 5983 static const char *channel_strings[] = { 5984 "Primary Low", 5985 "Primary High", 5986 "Secondary Low", 5987 "Secondary High" 5988 }; 5989 5990 static const char *termstat_strings[] = { 5991 "Terminated Correctly", 5992 "Over Terminated", 5993 "Under Terminated", 5994 "Not Configured" 5995 }; 5996 5997 /* 5998 * Start the board, ready for normal operation 5999 */ 6000 int 6001 ahd_init(struct ahd_softc *ahd) 6002 { 6003 uint8_t *next_vaddr; 6004 bus_addr_t next_baddr; 6005 size_t driver_data_size; 6006 int i; 6007 int error; 6008 u_int warn_user; 6009 uint8_t current_sensing; 6010 uint8_t fstat; 6011 6012 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6013 6014 ahd->stack_size = ahd_probe_stack_size(ahd); 6015 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 6016 M_DEVBUF, M_NOWAIT); 6017 if (ahd->saved_stack == NULL) 6018 return (ENOMEM); 6019 /* Zero the memory */ 6020 memset(ahd->saved_stack, 0, ahd->stack_size * sizeof(uint16_t)); 6021 6022 /* 6023 * Verify that the compiler hasn't over-agressively 6024 * padded important structures. 6025 */ 6026 if (sizeof(struct hardware_scb) != 64) 6027 panic("Hardware SCB size is incorrect"); 6028 6029 #ifdef AHD_DEBUG 6030 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 6031 ahd->flags |= AHD_SEQUENCER_DEBUG; 6032 #endif 6033 6034 /* 6035 * Default to allowing initiator operations. 6036 */ 6037 ahd->flags |= AHD_INITIATORROLE; 6038 6039 /* 6040 * Only allow target mode features if this unit has them enabled. 6041 */ 6042 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 6043 ahd->features &= ~AHD_TARGETMODE; 6044 6045 /* 6046 * DMA tag for our command fifos and other data in system memory 6047 * the card's sequencer must be able to access. For initiator 6048 * roles, we need to allocate space for the qoutfifo. When providing 6049 * for the target mode role, we must additionally provide space for 6050 * the incoming target command fifo. 6051 */ 6052 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 6053 + sizeof(struct hardware_scb); 6054 if ((ahd->features & AHD_TARGETMODE) != 0) 6055 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6056 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 6057 driver_data_size += PKT_OVERRUN_BUFSIZE; 6058 ahd->shared_data_size = driver_data_size; 6059 6060 memset(&ahd->shared_data_map, 0, sizeof(ahd->shared_data_map)); 6061 ahd->sc_dmaflags = BUS_DMA_NOWAIT; 6062 6063 if (ahd_createdmamem(ahd->parent_dmat, ahd->shared_data_size, 6064 ahd->sc_dmaflags, 6065 &ahd->shared_data_map.dmamap, (caddr_t *)&ahd->shared_data_map.vaddr, 6066 &ahd->shared_data_map.physaddr, &ahd->shared_data_map.dmasegs, 6067 &ahd->shared_data_map.nseg, ahd_name(ahd), "shared data") < 0) 6068 return (ENOMEM); 6069 ahd->qoutfifo = (void *) ahd->shared_data_map.vaddr; 6070 6071 ahd->init_level++; 6072 6073 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 6074 next_baddr = ahd->shared_data_map.physaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 6075 if ((ahd->features & AHD_TARGETMODE) != 0) { 6076 ahd->targetcmds = (struct target_cmd *)next_vaddr; 6077 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6078 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6079 } 6080 6081 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 6082 ahd->overrun_buf = next_vaddr; 6083 next_vaddr += PKT_OVERRUN_BUFSIZE; 6084 next_baddr += PKT_OVERRUN_BUFSIZE; 6085 } 6086 6087 /* 6088 * We need one SCB to serve as the "next SCB". Since the 6089 * tag identifier in this SCB will never be used, there is 6090 * no point in using a valid HSCB tag from an SCB pulled from 6091 * the standard free pool. So, we allocate this "sentinel" 6092 * specially from the DMA safe memory chunk used for the QOUTFIFO. 6093 */ 6094 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 6095 ahd->next_queued_hscb_map = &ahd->shared_data_map; 6096 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 6097 6098 memset(&ahd->scb_data, 0, sizeof(struct scb_data)); 6099 6100 /* Allocate SCB data now that parent_dmat is initialized */ 6101 if (ahd_init_scbdata(ahd) != 0) 6102 return (ENOMEM); 6103 6104 if ((ahd->flags & AHD_INITIATORROLE) == 0) 6105 ahd->flags &= ~AHD_RESET_BUS_A; 6106 6107 /* 6108 * Before committing these settings to the chip, give 6109 * the OSM one last chance to modify our configuration. 6110 */ 6111 ahd_platform_init(ahd); 6112 6113 /* Bring up the chip. */ 6114 ahd_chip_init(ahd); 6115 6116 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6117 6118 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 6119 goto init_done; 6120 6121 /* 6122 * Verify termination based on current draw and 6123 * warn user if the bus is over/under terminated. 6124 */ 6125 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 6126 CURSENSE_ENB); 6127 if (error != 0) { 6128 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 6129 goto init_done; 6130 } 6131 for (i = 20, fstat = FLX_FSTAT_BUSY; 6132 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 6133 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 6134 if (error != 0) { 6135 printf("%s: current sensing timeout 2\n", 6136 ahd_name(ahd)); 6137 goto init_done; 6138 } 6139 } 6140 if (i == 0) { 6141 printf("%s: Timedout during current-sensing test\n", 6142 ahd_name(ahd)); 6143 goto init_done; 6144 } 6145 6146 /* Latch Current Sensing status. */ 6147 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 6148 if (error != 0) { 6149 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 6150 goto init_done; 6151 } 6152 6153 /* Diable current sensing. */ 6154 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 6155 6156 #ifdef AHD_DEBUG 6157 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 6158 printf("%s: current_sensing == 0x%x\n", 6159 ahd_name(ahd), current_sensing); 6160 } 6161 #endif 6162 warn_user = 0; 6163 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 6164 u_int term_stat; 6165 6166 term_stat = (current_sensing & FLX_CSTAT_MASK); 6167 switch (term_stat) { 6168 case FLX_CSTAT_OVER: 6169 case FLX_CSTAT_UNDER: 6170 warn_user++; 6171 case FLX_CSTAT_INVALID: 6172 case FLX_CSTAT_OKAY: 6173 if (warn_user == 0 && bootverbose == 0) 6174 break; 6175 printf("%s: %s Channel %s\n", ahd_name(ahd), 6176 channel_strings[i], termstat_strings[term_stat]); 6177 break; 6178 } 6179 } 6180 if (warn_user) { 6181 printf("%s: WARNING. Termination is not configured correctly.\n" 6182 "%s: WARNING. SCSI bus operations may FAIL.\n", 6183 ahd_name(ahd), ahd_name(ahd)); 6184 } 6185 init_done: 6186 ahd_reset_current_bus(ahd); 6187 ahd_restart(ahd); 6188 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 6189 ahd_stat_timer, ahd); 6190 6191 /* We have to wait until after any system dumps... */ 6192 ahd->shutdown_hook = shutdownhook_establish(ahd_shutdown, ahd); 6193 6194 return (0); 6195 } 6196 6197 /* 6198 * (Re)initialize chip state after a chip reset. 6199 */ 6200 static void 6201 ahd_chip_init(struct ahd_softc *ahd) 6202 { 6203 uint32_t busaddr; 6204 u_int sxfrctl1; 6205 u_int scsiseq_template; 6206 u_int wait; 6207 u_int i; 6208 u_int target; 6209 6210 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6211 /* 6212 * Take the LED out of diagnostic mode 6213 */ 6214 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6215 6216 /* 6217 * Return HS_MAILBOX to its default value. 6218 */ 6219 ahd->hs_mailbox = 0; 6220 ahd_outb(ahd, HS_MAILBOX, 0); 6221 6222 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6223 ahd_outb(ahd, IOWNID, ahd->our_id); 6224 ahd_outb(ahd, TOWNID, ahd->our_id); 6225 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6226 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6227 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6228 && (ahd->seltime != STIMESEL_MIN)) { 6229 /* 6230 * The selection timer duration is twice as long 6231 * as it should be. Halve it by adding "1" to 6232 * the user specified setting. 6233 */ 6234 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6235 } else { 6236 sxfrctl1 |= ahd->seltime; 6237 } 6238 6239 ahd_outb(ahd, SXFRCTL0, DFON); 6240 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6241 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6242 6243 /* 6244 * Now that termination is set, wait for up 6245 * to 500ms for our transceivers to settle. If 6246 * the adapter does not have a cable attached, 6247 * the transceivers may never settle, so don't 6248 * complain if we fail here. 6249 */ 6250 for (wait = 10000; 6251 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6252 wait--) 6253 ahd_delay(100); 6254 6255 /* Clear any false bus resets due to the transceivers settling */ 6256 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6257 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6258 6259 /* Initialize mode specific S/G state. */ 6260 for (i = 0; i < 2; i++) { 6261 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6262 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6263 ahd_outb(ahd, SG_STATE, 0); 6264 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6265 ahd_outb(ahd, SEQIMODE, 6266 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6267 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6268 } 6269 6270 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6271 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6272 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6273 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6274 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6275 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6276 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6277 } else { 6278 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6279 } 6280 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6281 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6282 /* 6283 * Do not issue a target abort when a split completion 6284 * error occurs. Let our PCIX interrupt handler deal 6285 * with it instead. H2A4 Razor #625 6286 */ 6287 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6288 6289 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6290 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6291 6292 /* 6293 * Tweak IOCELL settings. 6294 */ 6295 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6296 for (i = 0; i < NUMDSPS; i++) { 6297 ahd_outb(ahd, DSPSELECT, i); 6298 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6299 } 6300 #ifdef AHD_DEBUG 6301 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6302 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6303 WRTBIASCTL_HP_DEFAULT); 6304 #endif 6305 } 6306 ahd_setup_iocell_workaround(ahd); 6307 6308 /* 6309 * Enable LQI Manager interrupts. 6310 */ 6311 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6312 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6313 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6314 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6315 /* 6316 * An interrupt from LQOBUSFREE is made redundant by the 6317 * BUSFREE interrupt. We choose to have the sequencer catch 6318 * LQOPHCHGINPKT errors manually for the command phase at the 6319 * start of a packetized selection case. 6320 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 6321 */ 6322 ahd_outb(ahd, LQOMODE1, 0); 6323 6324 /* 6325 * Setup sequencer interrupt handlers. 6326 */ 6327 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6328 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6329 6330 /* 6331 * Setup SCB Offset registers. 6332 */ 6333 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6334 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6335 pkt_long_lun)); 6336 } else { 6337 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6338 } 6339 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6340 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6341 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6342 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6343 shared_data.idata.cdb)); 6344 ahd_outb(ahd, QNEXTPTR, 6345 offsetof(struct hardware_scb, next_hscb_busaddr)); 6346 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6347 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6348 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6349 ahd_outb(ahd, LUNLEN, 6350 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6351 } else { 6352 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6353 } 6354 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6355 ahd_outb(ahd, MAXCMD, 0xFF); 6356 ahd_outb(ahd, SCBAUTOPTR, 6357 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6358 6359 /* We haven't been enabled for target mode yet. */ 6360 ahd_outb(ahd, MULTARGID, 0); 6361 ahd_outb(ahd, MULTARGID + 1, 0); 6362 6363 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6364 /* Initialize the negotiation table. */ 6365 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6366 /* 6367 * Clear the spare bytes in the neg table to avoid 6368 * spurious parity errors. 6369 */ 6370 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6371 ahd_outb(ahd, NEGOADDR, target); 6372 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6373 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6374 ahd_outb(ahd, ANNEXDAT, 0); 6375 } 6376 } 6377 6378 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6379 struct ahd_devinfo devinfo; 6380 struct ahd_initiator_tinfo *tinfo; 6381 struct ahd_tmode_tstate *tstate; 6382 6383 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6384 target, &tstate); 6385 ahd_compile_devinfo(&devinfo, ahd->our_id, 6386 target, CAM_LUN_WILDCARD, 6387 'A', ROLE_INITIATOR); 6388 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6389 } 6390 6391 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6392 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6393 6394 #if NEEDS_MORE_TESTING 6395 /* 6396 * Always enable abort on incoming L_Qs if this feature is 6397 * supported. We use this to catch invalid SCB references. 6398 */ 6399 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6400 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6401 else 6402 #endif 6403 ahd_outb(ahd, LQCTL1, 0); 6404 6405 /* All of our queues are empty */ 6406 ahd->qoutfifonext = 0; 6407 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6408 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6409 for (i = 0; i < AHD_QOUT_SIZE; i++) 6410 ahd->qoutfifo[i] = 0; 6411 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6412 6413 ahd->qinfifonext = 0; 6414 for (i = 0; i < AHD_QIN_SIZE; i++) 6415 ahd->qinfifo[i] = SCB_LIST_NULL; 6416 6417 if ((ahd->features & AHD_TARGETMODE) != 0) { 6418 /* All target command blocks start out invalid. */ 6419 for (i = 0; i < AHD_TMODE_CMDS; i++) 6420 ahd->targetcmds[i].cmd_valid = 0; 6421 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6422 ahd->tqinfifonext = 1; 6423 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6424 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6425 } 6426 6427 /* Initialize Scratch Ram. */ 6428 ahd_outb(ahd, SEQ_FLAGS, 0); 6429 ahd_outb(ahd, SEQ_FLAGS2, 0); 6430 6431 /* We don't have any waiting selections */ 6432 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6433 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6434 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6435 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6436 } 6437 6438 /* 6439 * Nobody is waiting to be DMAed into the QOUTFIFO. 6440 */ 6441 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6442 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6443 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6444 6445 /* 6446 * The Freeze Count is 0. 6447 */ 6448 ahd_outw(ahd, QFREEZE_COUNT, 0); 6449 6450 /* 6451 * Tell the sequencer where it can find our arrays in memory. 6452 */ 6453 busaddr = ahd->shared_data_map.physaddr; 6454 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6455 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6456 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6457 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6458 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6459 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6460 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6461 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6462 /* 6463 * Setup the allowed SCSI Sequences based on operational mode. 6464 * If we are a target, we'll enable select in operations once 6465 * we've had a lun enabled. 6466 */ 6467 scsiseq_template = ENAUTOATNP; 6468 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6469 scsiseq_template |= ENRSELI; 6470 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6471 6472 /* There are no busy SCBs yet. */ 6473 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6474 int lun; 6475 6476 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6477 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6478 } 6479 6480 /* 6481 * Initialize the group code to command length table. 6482 * Vendor Unique codes are set to 0 so we only capture 6483 * the first byte of the cdb. These can be overridden 6484 * when target mode is enabled. 6485 */ 6486 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6487 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6488 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6489 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6490 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6491 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6492 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6493 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6494 6495 /* Tell the sequencer of our initial queue positions */ 6496 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6497 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6498 ahd->qinfifonext = 0; 6499 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6500 ahd_set_hescb_qoff(ahd, 0); 6501 ahd_set_snscb_qoff(ahd, 0); 6502 ahd_set_sescb_qoff(ahd, 0); 6503 ahd_set_sdscb_qoff(ahd, 0); 6504 6505 /* 6506 * Tell the sequencer which SCB will be the next one it receives. 6507 */ 6508 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6509 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6510 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6511 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6512 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6513 6514 /* 6515 * Default to coalescing disabled. 6516 */ 6517 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6518 ahd_outw(ahd, CMDS_PENDING, 0); 6519 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6520 ahd->int_coalescing_maxcmds, 6521 ahd->int_coalescing_mincmds); 6522 ahd_enable_coalescing(ahd, FALSE); 6523 6524 ahd_loadseq(ahd); 6525 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6526 } 6527 6528 /* 6529 * Setup default device and controller settings. 6530 * This should only be called if our probe has 6531 * determined that no configuration data is available. 6532 */ 6533 int 6534 ahd_default_config(struct ahd_softc *ahd) 6535 { 6536 int targ; 6537 6538 ahd->our_id = 7; 6539 6540 /* 6541 * Allocate a tstate to house information for our 6542 * initiator presence on the bus as well as the user 6543 * data for any target mode initiator. 6544 */ 6545 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6546 printf("%s: unable to allocate ahd_tmode_tstate. " 6547 "Failing attach\n", ahd_name(ahd)); 6548 return (ENOMEM); 6549 } 6550 6551 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6552 struct ahd_devinfo devinfo; 6553 struct ahd_initiator_tinfo *tinfo; 6554 struct ahd_tmode_tstate *tstate; 6555 uint16_t target_mask; 6556 6557 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6558 targ, &tstate); 6559 /* 6560 * We support SPC2 and SPI4. 6561 */ 6562 tinfo->user.protocol_version = 4; 6563 tinfo->user.transport_version = 4; 6564 6565 target_mask = 0x01 << targ; 6566 ahd->user_discenable |= target_mask; 6567 tstate->discenable |= target_mask; 6568 ahd->user_tagenable |= target_mask; 6569 #ifdef AHD_FORCE_160 6570 tinfo->user.period = AHD_SYNCRATE_DT; 6571 #else 6572 tinfo->user.period = AHD_SYNCRATE_160; 6573 #endif 6574 tinfo->user.offset= MAX_OFFSET; 6575 tinfo->user.ppr_options = MSG_EXT_PPR_RDSTRM 6576 | MSG_EXT_PPR_WRFLOW 6577 | MSG_EXT_PPR_HOLDMCS 6578 | MSG_EXT_PPR_IU_REQ 6579 | MSG_EXT_PPR_QAS_REQ 6580 | MSG_EXT_PPR_DT_REQ; 6581 if ((ahd->features & AHD_RTI) != 0) 6582 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6583 6584 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6585 6586 /* 6587 * Start out Async/Narrow/Untagged and with 6588 * conservative protocol support. 6589 */ 6590 tinfo->goal.protocol_version = 2; 6591 tinfo->goal.transport_version = 2; 6592 tinfo->curr.protocol_version = 2; 6593 tinfo->curr.transport_version = 2; 6594 ahd_compile_devinfo(&devinfo, ahd->our_id, 6595 targ, CAM_LUN_WILDCARD, 6596 'A', ROLE_INITIATOR); 6597 tstate->tagenable &= ~target_mask; 6598 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6599 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6600 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6601 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6602 /*paused*/TRUE); 6603 } 6604 return (0); 6605 } 6606 6607 /* 6608 * Parse device configuration information. 6609 */ 6610 int 6611 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6612 { 6613 int targ; 6614 int max_targ; 6615 6616 max_targ = sc->max_targets & CFMAXTARG; 6617 ahd->our_id = sc->brtime_id & CFSCSIID; 6618 6619 /* 6620 * Allocate a tstate to house information for our 6621 * initiator presence on the bus as well as the user 6622 * data for any target mode initiator. 6623 */ 6624 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6625 printf("%s: unable to allocate ahd_tmode_tstate. " 6626 "Failing attach\n", ahd_name(ahd)); 6627 return (ENOMEM); 6628 } 6629 6630 for (targ = 0; targ < max_targ; targ++) { 6631 struct ahd_devinfo devinfo; 6632 struct ahd_initiator_tinfo *tinfo; 6633 struct ahd_transinfo *user_tinfo; 6634 struct ahd_tmode_tstate *tstate; 6635 uint16_t target_mask; 6636 6637 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6638 targ, &tstate); 6639 user_tinfo = &tinfo->user; 6640 6641 /* 6642 * We support SPC2 and SPI4. 6643 */ 6644 tinfo->user.protocol_version = 4; 6645 tinfo->user.transport_version = 4; 6646 6647 target_mask = 0x01 << targ; 6648 ahd->user_discenable &= ~target_mask; 6649 tstate->discenable &= ~target_mask; 6650 ahd->user_tagenable &= ~target_mask; 6651 if (sc->device_flags[targ] & CFDISC) { 6652 tstate->discenable |= target_mask; 6653 ahd->user_discenable |= target_mask; 6654 ahd->user_tagenable |= target_mask; 6655 } else { 6656 /* 6657 * Cannot be packetized without disconnection. 6658 */ 6659 sc->device_flags[targ] &= ~CFPACKETIZED; 6660 } 6661 6662 user_tinfo->ppr_options = 0; 6663 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6664 if (user_tinfo->period < CFXFER_ASYNC) { 6665 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6666 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6667 user_tinfo->offset = MAX_OFFSET; 6668 } else { 6669 user_tinfo->offset = 0; 6670 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6671 } 6672 #ifdef AHD_FORCE_160 6673 if (user_tinfo->period <= AHD_SYNCRATE_160) 6674 user_tinfo->period = AHD_SYNCRATE_DT; 6675 #endif 6676 6677 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6678 user_tinfo->ppr_options |= MSG_EXT_PPR_RDSTRM 6679 | MSG_EXT_PPR_WRFLOW 6680 | MSG_EXT_PPR_HOLDMCS 6681 | MSG_EXT_PPR_IU_REQ; 6682 if ((ahd->features & AHD_RTI) != 0) 6683 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6684 } 6685 6686 if ((sc->device_flags[targ] & CFQAS) != 0) 6687 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6688 6689 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6690 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6691 else 6692 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6693 #ifdef AHD_DEBUG 6694 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6695 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6696 user_tinfo->period, user_tinfo->offset, 6697 user_tinfo->ppr_options); 6698 #endif 6699 /* 6700 * Start out Async/Narrow/Untagged and with 6701 * conservative protocol support. 6702 */ 6703 tstate->tagenable &= ~target_mask; 6704 tinfo->goal.protocol_version = 2; 6705 tinfo->goal.transport_version = 2; 6706 tinfo->curr.protocol_version = 2; 6707 tinfo->curr.transport_version = 2; 6708 ahd_compile_devinfo(&devinfo, ahd->our_id, 6709 targ, CAM_LUN_WILDCARD, 6710 'A', ROLE_INITIATOR); 6711 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6712 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6713 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6714 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6715 /*paused*/TRUE); 6716 } 6717 6718 ahd->flags &= ~AHD_SPCHK_ENB_A; 6719 if (sc->bios_control & CFSPARITY) 6720 ahd->flags |= AHD_SPCHK_ENB_A; 6721 6722 ahd->flags &= ~AHD_RESET_BUS_A; 6723 if (sc->bios_control & CFRESETB) 6724 ahd->flags |= AHD_RESET_BUS_A; 6725 6726 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6727 if (sc->bios_control & CFEXTEND) 6728 ahd->flags |= AHD_EXTENDED_TRANS_A; 6729 6730 ahd->flags &= ~AHD_BIOS_ENABLED; 6731 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6732 ahd->flags |= AHD_BIOS_ENABLED; 6733 6734 ahd->flags &= ~AHD_STPWLEVEL_A; 6735 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6736 ahd->flags |= AHD_STPWLEVEL_A; 6737 6738 return (0); 6739 } 6740 6741 /* 6742 * Parse device configuration information. 6743 */ 6744 int 6745 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 6746 { 6747 int error; 6748 6749 error = ahd_verify_vpd_cksum(vpd); 6750 if (error == 0) 6751 return (EINVAL); 6752 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 6753 ahd->flags |= AHD_BOOT_CHANNEL; 6754 return (0); 6755 } 6756 6757 void 6758 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6759 { 6760 u_int hcntrl; 6761 6762 hcntrl = ahd_inb(ahd, HCNTRL); 6763 hcntrl &= ~INTEN; 6764 ahd->pause &= ~INTEN; 6765 ahd->unpause &= ~INTEN; 6766 if (enable) { 6767 hcntrl |= INTEN; 6768 ahd->pause |= INTEN; 6769 ahd->unpause |= INTEN; 6770 } 6771 ahd_outb(ahd, HCNTRL, hcntrl); 6772 } 6773 6774 void 6775 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6776 u_int mincmds) 6777 { 6778 if (timer > AHD_TIMER_MAX_US) 6779 timer = AHD_TIMER_MAX_US; 6780 ahd->int_coalescing_timer = timer; 6781 6782 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 6783 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 6784 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 6785 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 6786 ahd->int_coalescing_maxcmds = maxcmds; 6787 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6788 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 6789 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 6790 } 6791 6792 void 6793 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 6794 { 6795 6796 ahd->hs_mailbox &= ~ENINT_COALESCE; 6797 if (enable) 6798 ahd->hs_mailbox |= ENINT_COALESCE; 6799 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6800 ahd_flush_device_writes(ahd); 6801 ahd_run_qoutfifo(ahd); 6802 } 6803 6804 /* 6805 * Ensure that the card is paused in a location 6806 * outside of all critical sections and that all 6807 * pending work is completed prior to returning. 6808 * This routine should only be called from outside 6809 * an interrupt context. 6810 */ 6811 void 6812 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6813 { 6814 u_int intstat; 6815 u_int maxloops; 6816 u_int qfreeze_cnt; 6817 6818 maxloops = 1000; 6819 ahd->flags |= AHD_ALL_INTERRUPTS; 6820 ahd_pause(ahd); 6821 /* 6822 * Increment the QFreeze Count so that the sequencer 6823 * will not start new selections. We do this only 6824 * until we are safely paused without further selections 6825 * pending. 6826 */ 6827 ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1); 6828 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 6829 do { 6830 struct scb *waiting_scb; 6831 6832 ahd_unpause(ahd); 6833 ahd_intr(ahd); 6834 ahd_pause(ahd); 6835 ahd_clear_critical_section(ahd); 6836 intstat = ahd_inb(ahd, INTSTAT); 6837 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6838 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6839 ahd_outb(ahd, SCSISEQ0, 6840 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6841 /* 6842 * In the non-packetized case, the sequencer (for Rev A), 6843 * relies on ENSELO remaining set after SELDO. The hardware 6844 * auto-clears ENSELO in the packetized case. 6845 */ 6846 waiting_scb = ahd_lookup_scb(ahd, 6847 ahd_inw(ahd, WAITING_TID_HEAD)); 6848 if (waiting_scb != NULL 6849 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6850 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6851 ahd_outb(ahd, SCSISEQ0, 6852 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6853 } while (--maxloops 6854 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6855 && ((intstat & INT_PEND) != 0 6856 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 6857 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 6858 if (maxloops == 0) { 6859 printf("Infinite interrupt loop, INTSTAT = %x", 6860 ahd_inb(ahd, INTSTAT)); 6861 } 6862 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 6863 if (qfreeze_cnt == 0) { 6864 printf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n", 6865 ahd_name(ahd)); 6866 } else { 6867 qfreeze_cnt--; 6868 } 6869 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 6870 if (qfreeze_cnt == 0) 6871 ahd_outb(ahd, SEQ_FLAGS2, 6872 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 6873 6874 ahd_flush_qoutfifo(ahd); 6875 6876 ahd_platform_flushwork(ahd); 6877 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6878 } 6879 6880 int 6881 ahd_suspend(struct ahd_softc *ahd) 6882 { 6883 6884 ahd_pause_and_flushwork(ahd); 6885 6886 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 6887 ahd_unpause(ahd); 6888 return (EBUSY); 6889 } 6890 ahd_shutdown(ahd); 6891 return (0); 6892 } 6893 6894 int 6895 ahd_resume(struct ahd_softc *ahd) 6896 { 6897 6898 ahd_reset(ahd, /*reinit*/TRUE); 6899 ahd_intr_enable(ahd, TRUE); 6900 ahd_restart(ahd); 6901 return (0); 6902 } 6903 6904 /************************** Busy Target Table *********************************/ 6905 /* 6906 * Set SCBPTR to the SCB that contains the busy 6907 * table entry for TCL. Return the offset into 6908 * the SCB that contains the entry for TCL. 6909 * saved_scbid is dereferenced and set to the 6910 * scbid that should be restored once manipualtion 6911 * of the TCL entry is complete. 6912 */ 6913 static __inline u_int 6914 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6915 { 6916 /* 6917 * Index to the SCB that contains the busy entry. 6918 */ 6919 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6920 *saved_scbid = ahd_get_scbptr(ahd); 6921 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6922 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6923 6924 /* 6925 * And now calculate the SCB offset to the entry. 6926 * Each entry is 2 bytes wide, hence the 6927 * multiplication by 2. 6928 */ 6929 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6930 } 6931 6932 /* 6933 * Return the untagged transaction id for a given target/channel lun. 6934 */ 6935 u_int 6936 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6937 { 6938 u_int scbid; 6939 u_int scb_offset; 6940 u_int saved_scbptr; 6941 6942 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6943 scbid = ahd_inw_scbram(ahd, scb_offset); 6944 ahd_set_scbptr(ahd, saved_scbptr); 6945 return (scbid); 6946 } 6947 6948 void 6949 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6950 { 6951 u_int scb_offset; 6952 u_int saved_scbptr; 6953 6954 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6955 ahd_outw(ahd, scb_offset, scbid); 6956 ahd_set_scbptr(ahd, saved_scbptr); 6957 } 6958 6959 /************************** SCB and SCB queue management **********************/ 6960 int 6961 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6962 char channel, int lun, u_int tag, role_t role) 6963 { 6964 int targ = SCB_GET_TARGET(ahd, scb); 6965 char chan = SCB_GET_CHANNEL(ahd, scb); 6966 int slun = SCB_GET_LUN(scb); 6967 int match; 6968 6969 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6970 if (match != 0) 6971 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6972 if (match != 0) 6973 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6974 if (match != 0) { 6975 #if AHD_TARGET_MODE 6976 int group; 6977 6978 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6979 if (role == ROLE_INITIATOR) { 6980 match = (group != XPT_FC_GROUP_TMODE) 6981 && ((tag == SCB_GET_TAG(scb)) 6982 || (tag == SCB_LIST_NULL)); 6983 } else if (role == ROLE_TARGET) { 6984 match = (group == XPT_FC_GROUP_TMODE) 6985 && ((tag == scb->io_ctx->csio.tag_id) 6986 || (tag == SCB_LIST_NULL)); 6987 } 6988 #else /* !AHD_TARGET_MODE */ 6989 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6990 #endif /* AHD_TARGET_MODE */ 6991 } 6992 6993 return match; 6994 } 6995 6996 void 6997 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6998 { 6999 int target; 7000 char channel; 7001 int lun; 7002 7003 target = SCB_GET_TARGET(ahd, scb); 7004 lun = SCB_GET_LUN(scb); 7005 channel = SCB_GET_CHANNEL(ahd, scb); 7006 7007 ahd_search_qinfifo(ahd, target, channel, lun, 7008 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 7009 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7010 7011 ahd_platform_freeze_devq(ahd, scb); 7012 } 7013 7014 void 7015 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 7016 { 7017 struct scb *prev_scb; 7018 ahd_mode_state saved_modes; 7019 7020 saved_modes = ahd_save_modes(ahd); 7021 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7022 prev_scb = NULL; 7023 if (ahd_qinfifo_count(ahd) != 0) { 7024 u_int prev_tag; 7025 u_int prev_pos; 7026 7027 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 7028 prev_tag = ahd->qinfifo[prev_pos]; 7029 prev_scb = ahd_lookup_scb(ahd, prev_tag); 7030 } 7031 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7032 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7033 ahd_restore_modes(ahd, saved_modes); 7034 } 7035 7036 static void 7037 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 7038 struct scb *scb) 7039 { 7040 if (prev_scb == NULL) { 7041 uint32_t busaddr; 7042 7043 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 7044 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7045 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7046 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7047 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7048 } else { 7049 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 7050 ahd_sync_scb(ahd, prev_scb, 7051 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7052 } 7053 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 7054 ahd->qinfifonext++; 7055 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 7056 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7057 } 7058 7059 static int 7060 ahd_qinfifo_count(struct ahd_softc *ahd) 7061 { 7062 u_int qinpos; 7063 u_int wrap_qinpos; 7064 u_int wrap_qinfifonext; 7065 7066 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7067 qinpos = ahd_get_snscb_qoff(ahd); 7068 wrap_qinpos = AHD_QIN_WRAP(qinpos); 7069 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 7070 if (wrap_qinfifonext >= wrap_qinpos) 7071 return (wrap_qinfifonext - wrap_qinpos); 7072 else 7073 return (wrap_qinfifonext 7074 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 7075 } 7076 7077 void 7078 ahd_reset_cmds_pending(struct ahd_softc *ahd) 7079 { 7080 struct scb *scb; 7081 ahd_mode_state saved_modes; 7082 u_int pending_cmds; 7083 7084 saved_modes = ahd_save_modes(ahd); 7085 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7086 7087 /* 7088 * Don't count any commands as outstanding that the 7089 * sequencer has already marked for completion. 7090 */ 7091 ahd_flush_qoutfifo(ahd); 7092 7093 pending_cmds = 0; 7094 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7095 pending_cmds++; 7096 } 7097 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 7098 ahd_restore_modes(ahd, saved_modes); 7099 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 7100 } 7101 7102 int 7103 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 7104 int lun, u_int tag, role_t role, uint32_t status, 7105 ahd_search_action action) 7106 { 7107 struct scb *scb; 7108 struct scb *prev_scb; 7109 ahd_mode_state saved_modes; 7110 u_int qinstart; 7111 u_int qinpos; 7112 u_int qintail; 7113 u_int tid_next; 7114 u_int tid_prev; 7115 u_int scbid; 7116 u_int savedscbptr; 7117 uint32_t busaddr; 7118 int found; 7119 int targets; 7120 int pending_cmds; 7121 int qincount; 7122 7123 /* Must be in CCHAN mode */ 7124 saved_modes = ahd_save_modes(ahd); 7125 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7126 7127 /* 7128 * Halt any pending SCB DMA. The sequencer will reinitiate 7129 * this DMA if the qinfifo is not empty once we unpause. 7130 */ 7131 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7132 == (CCARREN|CCSCBEN|CCSCBDIR)) { 7133 ahd_outb(ahd, CCSCBCTL, 7134 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7135 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7136 ; 7137 } 7138 /* Determine sequencer's position in the qinfifo. */ 7139 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7140 qinstart = ahd_get_snscb_qoff(ahd); 7141 qinpos = AHD_QIN_WRAP(qinstart); 7142 found = 0; 7143 prev_scb = NULL; 7144 7145 pending_cmds = 0; 7146 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7147 pending_cmds++; 7148 } 7149 qincount = ahd_qinfifo_count(ahd); 7150 7151 if (action == SEARCH_PRINT) { 7152 printf("qinstart = 0x%x qinfifonext = 0x%x\n", 7153 qinstart, ahd->qinfifonext); 7154 } 7155 7156 /* 7157 * Start with an empty queue. Entries that are not chosen 7158 * for removal will be re-added to the queue as we go. 7159 */ 7160 ahd->qinfifonext = qinstart; 7161 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7162 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7163 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7164 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7165 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7166 7167 while (qinpos != qintail) { 7168 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7169 if (scb == NULL) { 7170 panic("Loop 1\n"); 7171 } 7172 7173 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7174 /* 7175 * We found an scb that needs to be acted on. 7176 */ 7177 found++; 7178 switch (action) { 7179 case SEARCH_COMPLETE: 7180 { 7181 cam_status ostat; 7182 cam_status cstat; 7183 7184 ostat = ahd_get_scsi_status(scb); 7185 if (ostat == CAM_REQ_INPROG) 7186 ahd_set_scsi_status(scb, status); 7187 cstat = ahd_get_transaction_status(scb); 7188 if (cstat != CAM_REQ_CMP) 7189 ahd_freeze_scb(scb); 7190 if ((scb->flags & SCB_ACTIVE) == 0) 7191 printf("Inactive SCB in qinfifo\n"); 7192 if (scb->xs->error != CAM_REQ_CMP) 7193 printf("SEARCH_COMPLETE(0x%x): ostat 0x%x, cstat 0x%x, xs_error 0x%x\n", 7194 SCB_GET_TAG(scb), ostat, cstat, scb->xs->error); 7195 ahd_done(ahd, scb); 7196 7197 /* FALLTHROUGH */ 7198 } 7199 case SEARCH_REMOVE: 7200 break; 7201 case SEARCH_PRINT: 7202 printf(" 0x%x", ahd->qinfifo[qinpos]); 7203 /* FALLTHROUGH */ 7204 case SEARCH_COUNT: 7205 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7206 prev_scb = scb; 7207 break; 7208 } 7209 } else { 7210 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7211 prev_scb = scb; 7212 } 7213 qinpos = AHD_QIN_WRAP(qinpos+1); 7214 } 7215 7216 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7217 7218 if (action == SEARCH_PRINT) 7219 printf("\nWAITING_TID_QUEUES:\n"); 7220 7221 /* 7222 * Search waiting for selection lists. We traverse the 7223 * list of "their ids" waiting for selection and, if 7224 * appropriate, traverse the SCBs of each "their id" 7225 * looking for matches. 7226 */ 7227 savedscbptr = ahd_get_scbptr(ahd); 7228 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7229 tid_prev = SCB_LIST_NULL; 7230 targets = 0; 7231 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7232 u_int tid_head; 7233 7234 /* 7235 * We limit based on the number of SCBs since 7236 * MK_MESSAGE SCBs are not in the per-tid lists. 7237 */ 7238 targets++; 7239 if (targets > AHD_SCB_MAX) { 7240 panic("TID LIST LOOP"); 7241 } 7242 if (scbid >= ahd->scb_data.numscbs) { 7243 printf("%s: Waiting TID List inconsistency. " 7244 "SCB index == 0x%x, yet numscbs == 0x%x.", 7245 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7246 ahd_dump_card_state(ahd); 7247 panic("for safety"); 7248 } 7249 scb = ahd_lookup_scb(ahd, scbid); 7250 if (scb == NULL) { 7251 printf("%s: SCB = 0x%x Not Active!\n", 7252 ahd_name(ahd), scbid); 7253 panic("Waiting TID List traversal\n"); 7254 break; 7255 } 7256 ahd_set_scbptr(ahd, scbid); 7257 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7258 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7259 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7260 tid_prev = scbid; 7261 continue; 7262 } 7263 7264 /* 7265 * We found a list of scbs that needs to be searched. 7266 */ 7267 if (action == SEARCH_PRINT) 7268 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7269 tid_head = scbid; 7270 found += ahd_search_scb_list(ahd, target, channel, 7271 lun, tag, role, status, 7272 action, &tid_head, 7273 SCB_GET_TARGET(ahd, scb)); 7274 if (tid_head != scbid) 7275 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7276 if (!SCBID_IS_NULL(tid_head)) 7277 tid_prev = tid_head; 7278 if (action == SEARCH_PRINT) 7279 printf(")\n"); 7280 } 7281 ahd_set_scbptr(ahd, savedscbptr); 7282 ahd_restore_modes(ahd, saved_modes); 7283 return (found); 7284 } 7285 7286 static int 7287 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7288 int lun, u_int tag, role_t role, uint32_t status, 7289 ahd_search_action action, u_int *list_head, u_int tid) 7290 { 7291 struct scb *scb; 7292 u_int scbid; 7293 u_int next; 7294 u_int prev; 7295 int found; 7296 7297 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7298 found = 0; 7299 prev = SCB_LIST_NULL; 7300 next = *list_head; 7301 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7302 if (scbid >= ahd->scb_data.numscbs) { 7303 printf("%s:SCB List inconsistency. " 7304 "SCB == 0x%x, yet numscbs == 0x%x.", 7305 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7306 ahd_dump_card_state(ahd); 7307 panic("for safety"); 7308 } 7309 scb = ahd_lookup_scb(ahd, scbid); 7310 if (scb == NULL) { 7311 printf("%s: SCB = %d Not Active!\n", 7312 ahd_name(ahd), scbid); 7313 panic("Waiting List traversal\n"); 7314 } 7315 ahd_set_scbptr(ahd, scbid); 7316 next = ahd_inw_scbram(ahd, SCB_NEXT); 7317 if (ahd_match_scb(ahd, scb, target, channel, 7318 lun, SCB_LIST_NULL, role) == 0) { 7319 prev = scbid; 7320 continue; 7321 } 7322 found++; 7323 switch (action) { 7324 case SEARCH_COMPLETE: 7325 { 7326 cam_status ostat; 7327 cam_status cstat; 7328 7329 ostat = ahd_get_scsi_status(scb); 7330 if (ostat == CAM_REQ_INPROG) 7331 ahd_set_scsi_status(scb, status); 7332 cstat = ahd_get_transaction_status(scb); 7333 if (cstat != CAM_REQ_CMP) 7334 ahd_freeze_scb(scb); 7335 if ((scb->flags & SCB_ACTIVE) == 0) 7336 printf("Inactive SCB in Waiting List\n"); 7337 ahd_done(ahd, scb); 7338 /* FALLTHROUGH */ 7339 } 7340 case SEARCH_REMOVE: 7341 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7342 if (prev == SCB_LIST_NULL) 7343 *list_head = next; 7344 break; 7345 case SEARCH_PRINT: 7346 printf("0x%x ", scbid); 7347 case SEARCH_COUNT: 7348 prev = scbid; 7349 break; 7350 } 7351 if (found > AHD_SCB_MAX) 7352 panic("SCB LIST LOOP"); 7353 } 7354 if (action == SEARCH_COMPLETE 7355 || action == SEARCH_REMOVE) 7356 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7357 return (found); 7358 } 7359 7360 static void 7361 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7362 u_int tid_cur, u_int tid_next) 7363 { 7364 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7365 7366 if (SCBID_IS_NULL(tid_cur)) { 7367 7368 /* Bypass current TID list */ 7369 if (SCBID_IS_NULL(tid_prev)) { 7370 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7371 } else { 7372 ahd_set_scbptr(ahd, tid_prev); 7373 ahd_outw(ahd, SCB_NEXT2, tid_next); 7374 } 7375 if (SCBID_IS_NULL(tid_next)) 7376 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7377 } else { 7378 7379 /* Stitch through tid_cur */ 7380 if (SCBID_IS_NULL(tid_prev)) { 7381 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7382 } else { 7383 ahd_set_scbptr(ahd, tid_prev); 7384 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7385 } 7386 ahd_set_scbptr(ahd, tid_cur); 7387 ahd_outw(ahd, SCB_NEXT2, tid_next); 7388 7389 if (SCBID_IS_NULL(tid_next)) 7390 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7391 } 7392 } 7393 7394 /* 7395 * Manipulate the waiting for selection list and return the 7396 * scb that follows the one that we remove. 7397 */ 7398 static u_int 7399 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7400 u_int prev, u_int next, u_int tid) 7401 { 7402 u_int tail_offset; 7403 7404 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7405 if (!SCBID_IS_NULL(prev)) { 7406 ahd_set_scbptr(ahd, prev); 7407 ahd_outw(ahd, SCB_NEXT, next); 7408 } 7409 7410 /* 7411 * SCBs that had MK_MESSAGE set in them will not 7412 * be queued to the per-target lists, so don't 7413 * blindly clear the tail pointer. 7414 */ 7415 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7416 if (SCBID_IS_NULL(next) 7417 && ahd_inw(ahd, tail_offset) == scbid) 7418 ahd_outw(ahd, tail_offset, prev); 7419 ahd_add_scb_to_free_list(ahd, scbid); 7420 return (next); 7421 } 7422 7423 /* 7424 * Add the SCB as selected by SCBPTR onto the on chip list of 7425 * free hardware SCBs. This list is empty/unused if we are not 7426 * performing SCB paging. 7427 */ 7428 static void 7429 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7430 { 7431 /* XXX Need some other mechanism to designate "free". */ 7432 /* 7433 * Invalidate the tag so that our abort 7434 * routines don't think it's active. 7435 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7436 */ 7437 } 7438 7439 /******************************** Error Handling ******************************/ 7440 /* 7441 * Abort all SCBs that match the given description (target/channel/lun/tag), 7442 * setting their status to the passed in status if the status has not already 7443 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7444 * is paused before it is called. 7445 */ 7446 int 7447 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7448 int lun, u_int tag, role_t role, uint32_t status) 7449 { 7450 struct scb *scbp; 7451 struct scb *scbp_next; 7452 u_int i, j; 7453 u_int maxtarget; 7454 u_int minlun; 7455 u_int maxlun; 7456 int found; 7457 ahd_mode_state saved_modes; 7458 7459 /* restore this when we're done */ 7460 saved_modes = ahd_save_modes(ahd); 7461 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7462 7463 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7464 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7465 7466 /* 7467 * Clean out the busy target table for any untagged commands. 7468 */ 7469 i = 0; 7470 maxtarget = 16; 7471 if (target != CAM_TARGET_WILDCARD) { 7472 i = target; 7473 if (channel == 'B') 7474 i += 8; 7475 maxtarget = i + 1; 7476 } 7477 7478 if (lun == CAM_LUN_WILDCARD) { 7479 minlun = 0; 7480 maxlun = AHD_NUM_LUNS_NONPKT; 7481 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7482 minlun = maxlun = 0; 7483 } else { 7484 minlun = lun; 7485 maxlun = lun + 1; 7486 } 7487 7488 if (role != ROLE_TARGET) { 7489 for (;i < maxtarget; i++) { 7490 for (j = minlun;j < maxlun; j++) { 7491 u_int scbid; 7492 u_int tcl; 7493 7494 tcl = BUILD_TCL_RAW(i, 'A', j); 7495 scbid = ahd_find_busy_tcl(ahd, tcl); 7496 scbp = ahd_lookup_scb(ahd, scbid); 7497 if (scbp == NULL 7498 || ahd_match_scb(ahd, scbp, target, channel, 7499 lun, tag, role) == 0) 7500 continue; 7501 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7502 } 7503 } 7504 } 7505 7506 /* 7507 * Don't abort commands that have already completed, 7508 * but haven't quite made it up to the host yet. 7509 */ 7510 ahd_flush_qoutfifo(ahd); 7511 7512 /* 7513 * Go through the pending CCB list and look for 7514 * commands for this target that are still active. 7515 * These are other tagged commands that were 7516 * disconnected when the reset occurred. 7517 */ 7518 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7519 while (scbp_next != NULL) { 7520 scbp = scbp_next; 7521 scbp_next = LIST_NEXT(scbp, pending_links); 7522 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7523 cam_status ostat; 7524 7525 ostat = ahd_get_scsi_status(scbp); 7526 if (ostat == CAM_REQ_INPROG) 7527 ahd_set_scsi_status(scbp, status); 7528 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7529 ahd_freeze_scb(scbp); 7530 if ((scbp->flags & SCB_ACTIVE) == 0) 7531 printf("Inactive SCB on pending list\n"); 7532 ahd_done(ahd, scbp); 7533 found++; 7534 } 7535 } 7536 ahd_restore_modes(ahd, saved_modes); 7537 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7538 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7539 return found; 7540 } 7541 7542 static void 7543 ahd_reset_current_bus(struct ahd_softc *ahd) 7544 { 7545 uint8_t scsiseq; 7546 7547 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7548 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7549 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7550 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7551 ahd_flush_device_writes(ahd); 7552 ahd_delay(AHD_BUSRESET_DELAY); 7553 /* Turn off the bus reset */ 7554 ahd_outb(ahd, SCSISEQ0, scsiseq); 7555 ahd_flush_device_writes(ahd); 7556 ahd_delay(AHD_BUSRESET_DELAY); 7557 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7558 /* 7559 * 2A Razor #474 7560 * Certain chip state is not cleared for 7561 * SCSI bus resets that we initiate, so 7562 * we must reset the chip. 7563 */ 7564 ahd_reset(ahd, /*reinit*/TRUE); 7565 ahd_intr_enable(ahd, /*enable*/TRUE); 7566 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7567 } 7568 7569 ahd_clear_intstat(ahd); 7570 } 7571 7572 int 7573 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7574 { 7575 struct ahd_devinfo devinfo; 7576 u_int initiator; 7577 u_int target; 7578 u_int max_scsiid; 7579 int found; 7580 u_int fifo; 7581 u_int next_fifo; 7582 7583 7584 ahd->pending_device = NULL; 7585 7586 ahd_compile_devinfo(&devinfo, 7587 CAM_TARGET_WILDCARD, 7588 CAM_TARGET_WILDCARD, 7589 CAM_LUN_WILDCARD, 7590 channel, ROLE_UNKNOWN); 7591 ahd_pause(ahd); 7592 7593 /* Make sure the sequencer is in a safe location. */ 7594 ahd_clear_critical_section(ahd); 7595 7596 #if AHD_TARGET_MODE 7597 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7598 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7599 } 7600 #endif 7601 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7602 7603 /* 7604 * Disable selections so no automatic hardware 7605 * functions will modify chip state. 7606 */ 7607 ahd_outb(ahd, SCSISEQ0, 0); 7608 ahd_outb(ahd, SCSISEQ1, 0); 7609 7610 /* 7611 * Safely shut down our DMA engines. Always start with 7612 * the FIFO that is not currently active (if any are 7613 * actively connected). 7614 */ 7615 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7616 if (next_fifo > CURRFIFO_1) 7617 /* If disconneced, arbitrarily start with FIFO1. */ 7618 next_fifo = fifo = 0; 7619 do { 7620 next_fifo ^= CURRFIFO_1; 7621 ahd_set_modes(ahd, next_fifo, next_fifo); 7622 ahd_outb(ahd, DFCNTRL, 7623 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7624 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7625 ahd_delay(10); 7626 /* 7627 * Set CURRFIFO to the now inactive channel. 7628 */ 7629 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7630 ahd_outb(ahd, DFFSTAT, next_fifo); 7631 } while (next_fifo != fifo); 7632 7633 /* 7634 * Reset the bus if we are initiating this reset 7635 */ 7636 ahd_clear_msg_state(ahd); 7637 ahd_outb(ahd, SIMODE1, 7638 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7639 7640 if (initiate_reset) 7641 ahd_reset_current_bus(ahd); 7642 7643 ahd_clear_intstat(ahd); 7644 7645 /* 7646 * Clean up all the state information for the 7647 * pending transactions on this bus. 7648 */ 7649 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7650 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7651 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7652 7653 /* 7654 * Cleanup anything left in the FIFOs. 7655 */ 7656 ahd_clear_fifo(ahd, 0); 7657 ahd_clear_fifo(ahd, 1); 7658 7659 /* 7660 * Revert to async/narrow transfers until we renegotiate. 7661 */ 7662 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7663 for (target = 0; target <= max_scsiid; target++) { 7664 7665 if (ahd->enabled_targets[target] == NULL) 7666 continue; 7667 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7668 struct ahd_devinfo dinfo; 7669 7670 ahd_compile_devinfo(&dinfo, target, initiator, 7671 CAM_LUN_WILDCARD, 7672 'A', ROLE_UNKNOWN); 7673 ahd_set_width(ahd, &dinfo, MSG_EXT_WDTR_BUS_8_BIT, 7674 AHD_TRANS_CUR, /*paused*/TRUE); 7675 ahd_set_syncrate(ahd, &dinfo, /*period*/0, 7676 /*offset*/0, /*ppr_options*/0, 7677 AHD_TRANS_CUR, /*paused*/TRUE); 7678 } 7679 } 7680 7681 #ifdef AHD_TARGET_MODE 7682 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7683 7684 /* 7685 * Send an immediate notify ccb to all target more peripheral 7686 * drivers affected by this action. 7687 */ 7688 for (target = 0; target <= max_scsiid; target++) { 7689 struct ahd_tmode_tstate* tstate; 7690 u_int lun; 7691 7692 tstate = ahd->enabled_targets[target]; 7693 if (tstate == NULL) 7694 continue; 7695 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7696 struct ahd_tmode_lstate* lstate; 7697 7698 lstate = tstate->enabled_luns[lun]; 7699 if (lstate == NULL) 7700 continue; 7701 7702 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7703 EVENT_TYPE_BUS_RESET, /*arg*/0); 7704 ahd_send_lstate_events(ahd, lstate); 7705 } 7706 } 7707 #endif 7708 7709 /* Notify the XPT that a bus reset occurred */ 7710 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7711 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7712 ahd_restart(ahd); 7713 7714 /* 7715 * Freeze the SIMQ until our poller can determine that 7716 * the bus reset has really gone away. We set the initial 7717 * timer to 0 to have the check performed as soon as possible 7718 * from the timer context. 7719 */ 7720 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7721 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7722 ahd_freeze_simq(ahd); 7723 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7724 } 7725 return (found); 7726 } 7727 7728 7729 #define AHD_RESET_POLL_US 1000 7730 static void 7731 ahd_reset_poll(void *arg) 7732 { 7733 struct ahd_softc *ahd; 7734 u_int scsiseq1; 7735 u_long l; 7736 int s; 7737 7738 ahd_list_lock(&l); 7739 ahd = (void*)arg; 7740 if (ahd == NULL) { 7741 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7742 ahd_list_unlock(&l); 7743 return; 7744 } 7745 ahd_lock(ahd, &s); 7746 ahd_pause(ahd); 7747 ahd_update_modes(ahd); 7748 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7749 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7750 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7751 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7752 ahd_reset_poll, ahd); 7753 ahd_unpause(ahd); 7754 ahd_unlock(ahd, &s); 7755 ahd_list_unlock(&l); 7756 return; 7757 } 7758 7759 /* Reset is now low. Complete chip reinitialization. */ 7760 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7761 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7762 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7763 ahd_unpause(ahd); 7764 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7765 ahd_unlock(ahd, &s); 7766 ahd_release_simq(ahd); 7767 ahd_list_unlock(&l); 7768 } 7769 7770 /**************************** Statistics Processing ***************************/ 7771 static void 7772 ahd_stat_timer(void *arg) 7773 { 7774 struct ahd_softc *ahd; 7775 u_long l; 7776 int s; 7777 int enint_coal; 7778 7779 ahd_list_lock(&l); 7780 ahd = (void *)arg; 7781 if (ahd == NULL) { 7782 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7783 ahd_list_unlock(&l); 7784 return; 7785 } 7786 ahd_lock(ahd, &s); 7787 7788 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 7789 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 7790 enint_coal |= ENINT_COALESCE; 7791 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 7792 enint_coal &= ~ENINT_COALESCE; 7793 7794 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 7795 ahd_enable_coalescing(ahd, enint_coal); 7796 #ifdef AHD_DEBUG 7797 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 7798 printf("%s: Interrupt coalescing " 7799 "now %sabled. Cmds %d\n", 7800 ahd_name(ahd), 7801 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 7802 ahd->cmdcmplt_total); 7803 #endif 7804 } 7805 7806 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7807 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7808 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7809 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7810 ahd_stat_timer, ahd); 7811 ahd_unlock(ahd, &s); 7812 ahd_list_unlock(&l); 7813 } 7814 7815 /****************************** Status Processing *****************************/ 7816 void 7817 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7818 { 7819 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7820 ahd_handle_scsi_status(ahd, scb); 7821 } else { 7822 ahd_calc_residual(ahd, scb); 7823 ahd_done(ahd, scb); 7824 } 7825 } 7826 7827 void 7828 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7829 { 7830 struct hardware_scb *hscb; 7831 u_int qfreeze_cnt; 7832 7833 /* 7834 * The sequencer freezes its select-out queue 7835 * anytime a SCSI status error occurs. We must 7836 * handle the error and decrement the QFREEZE count 7837 * to allow the sequencer to continue. 7838 */ 7839 hscb = scb->hscb; 7840 7841 /* Freeze the queue until the client sees the error. */ 7842 ahd_freeze_devq(ahd, scb); 7843 ahd_freeze_scb(scb); 7844 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7845 if (qfreeze_cnt == 0) { 7846 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7847 } else { 7848 qfreeze_cnt--; 7849 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7850 } 7851 if (qfreeze_cnt == 0) 7852 ahd_outb(ahd, SEQ_FLAGS2, 7853 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7854 7855 /* Don't want to clobber the original sense code */ 7856 if ((scb->flags & SCB_SENSE) != 0) { 7857 /* 7858 * Clear the SCB_SENSE Flag and perform 7859 * a normal command completion. 7860 */ 7861 scb->flags &= ~SCB_SENSE; 7862 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7863 ahd_done(ahd, scb); 7864 return; 7865 } 7866 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7867 ahd_set_xfer_status(scb, hscb->shared_data.istatus.scsi_status); 7868 switch (hscb->shared_data.istatus.scsi_status) { 7869 case STATUS_PKT_SENSE: 7870 { 7871 struct scsi_status_iu_header *siu; 7872 7873 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7874 siu = (struct scsi_status_iu_header *)scb->sense_data; 7875 ahd_set_scsi_status(scb, siu->status); 7876 #ifdef AHD_DEBUG 7877 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7878 ahd_print_path(ahd, scb); 7879 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7880 SCB_GET_TAG(scb), siu->status); 7881 } 7882 #endif 7883 if ((siu->flags & SIU_RSPVALID) != 0) { 7884 scsipi_printaddr(scb->xs->xs_periph); 7885 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7886 printf("Unable to parse pkt_failures\n"); 7887 } else { 7888 7889 switch (SIU_PKTFAIL_CODE(siu)) { 7890 case SIU_PFC_NONE: 7891 printf("No packet failure found\n"); 7892 break; 7893 case SIU_PFC_CIU_FIELDS_INVALID: 7894 printf("Invalid Command IU Field\n"); 7895 break; 7896 case SIU_PFC_TMF_NOT_SUPPORTED: 7897 printf("TMF not supportd\n"); 7898 break; 7899 case SIU_PFC_TMF_FAILED: 7900 printf("TMF failed\n"); 7901 break; 7902 case SIU_PFC_INVALID_TYPE_CODE: 7903 printf("Invalid L_Q Type code\n"); 7904 break; 7905 case SIU_PFC_ILLEGAL_REQUEST: 7906 printf("Illegal request\n"); 7907 default: 7908 break; 7909 } 7910 } 7911 if (siu->status == SCSI_STATUS_OK) 7912 ahd_set_transaction_status(scb, CAM_REQ_CMP_ERR); 7913 } 7914 if ((siu->flags & SIU_SNSVALID) != 0) { 7915 scb->flags |= SCB_PKT_SENSE; 7916 #ifdef AHD_DEBUG 7917 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7918 printf("Sense data available (%d)\n", siu->sense_length[0]); 7919 printf("SK 0x%x ASC 0x%x ASCQ 0x%x\n", 7920 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+2]) & 0x0F, 7921 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+12]), 7922 ((uint8_t)scb->sense_data[SIU_SENSE_OFFSET(siu)+13])); 7923 } 7924 #endif 7925 } 7926 ahd_done(ahd, scb); 7927 break; 7928 } 7929 case SCSI_STATUS_CMD_TERMINATED: 7930 case SCSI_STATUS_CHECK_COND: 7931 { 7932 struct ahd_devinfo devinfo; 7933 struct ahd_dma_seg *sg; 7934 struct scsi_request_sense *sc; 7935 struct ahd_initiator_tinfo *targ_info; 7936 struct ahd_tmode_tstate *tstate; 7937 struct ahd_transinfo *tinfo; 7938 #ifdef AHD_DEBUG 7939 if (ahd_debug & AHD_SHOW_SENSE) { 7940 ahd_print_path(ahd, scb); 7941 printf("SCB %d: requests Check Status\n", 7942 SCB_GET_TAG(scb)); 7943 } 7944 #endif 7945 7946 if (ahd_perform_autosense(scb) == 0) 7947 break; 7948 7949 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7950 SCB_GET_TARGET(ahd, scb), 7951 SCB_GET_LUN(scb), 7952 SCB_GET_CHANNEL(ahd, scb), 7953 ROLE_INITIATOR); 7954 targ_info = ahd_fetch_transinfo(ahd, 7955 devinfo.channel, 7956 devinfo.our_scsiid, 7957 devinfo.target, 7958 &tstate); 7959 tinfo = &targ_info->curr; 7960 sg = scb->sg_list; 7961 sc = (struct scsi_request_sense *)hscb->shared_data.idata.cdb; 7962 /* 7963 * Save off the residual if there is one. 7964 */ 7965 ahd_update_residual(ahd, scb); 7966 #ifdef AHD_DEBUG 7967 if (ahd_debug & AHD_SHOW_SENSE) { 7968 ahd_print_path(ahd, scb); 7969 printf("Sending Sense\n"); 7970 } 7971 #endif 7972 scb->sg_count = 0; 7973 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7974 ahd_get_sense_bufsize(ahd, scb), 7975 /*last*/TRUE); 7976 memset(sc, 0, sizeof(*sc)); 7977 sc->opcode = SCSI_REQUEST_SENSE; 7978 sc->length = ahd_get_sense_bufsize(ahd, scb); 7979 7980 /* 7981 * We can't allow the target to disconnect. 7982 * This will be an untagged transaction and 7983 * having the target disconnect will make this 7984 * transaction indistinguishable from outstanding 7985 * tagged transactions. 7986 */ 7987 hscb->control = 0; 7988 7989 /* 7990 * This request sense could be because the 7991 * the device lost power or in some other 7992 * way has lost our transfer negotiations. 7993 * Renegotiate if appropriate. Unit attention 7994 * errors will be reported before any data 7995 * phases occur. 7996 */ 7997 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7998 ahd_update_neg_request(ahd, &devinfo, 7999 tstate, targ_info, 8000 AHD_NEG_IF_NON_ASYNC); 8001 } 8002 if (tstate->auto_negotiate & devinfo.target_mask) { 8003 hscb->control |= MK_MESSAGE; 8004 scb->flags &= 8005 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 8006 scb->flags |= SCB_AUTO_NEGOTIATE; 8007 } 8008 hscb->cdb_len = sizeof(*sc); 8009 ahd_setup_data_scb(ahd, scb); 8010 scb->flags |= SCB_SENSE; 8011 ahd_queue_scb(ahd, scb); 8012 /* 8013 * Ensure we have enough time to actually 8014 * retrieve the sense. 8015 */ 8016 ahd_scb_timer_reset(scb, 5 * 1000000); 8017 break; 8018 } 8019 case SCSI_STATUS_OK: 8020 printf("%s: Interrupted for status of 0? (SCB 0x%x)\n", 8021 ahd_name(ahd), SCB_GET_TAG(scb)); 8022 /* FALLTHROUGH */ 8023 default: 8024 ahd_done(ahd, scb); 8025 break; 8026 } 8027 } 8028 8029 /* 8030 * Calculate the residual for a just completed SCB. 8031 */ 8032 void 8033 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 8034 { 8035 struct hardware_scb *hscb; 8036 struct initiator_status *spkt; 8037 uint32_t sgptr; 8038 uint32_t resid_sgptr; 8039 uint32_t resid; 8040 8041 /* 8042 * 5 cases. 8043 * 1) No residual. 8044 * SG_STATUS_VALID clear in sgptr. 8045 * 2) Transferless command 8046 * 3) Never performed any transfers. 8047 * sgptr has SG_FULL_RESID set. 8048 * 4) No residual but target did not 8049 * save data pointers after the 8050 * last transfer, so sgptr was 8051 * never updated. 8052 * 5) We have a partial residual. 8053 * Use residual_sgptr to determine 8054 * where we are. 8055 */ 8056 8057 hscb = scb->hscb; 8058 sgptr = ahd_le32toh(hscb->sgptr); 8059 if ((sgptr & SG_STATUS_VALID) == 0) 8060 /* Case 1 */ 8061 return; 8062 sgptr &= ~SG_STATUS_VALID; 8063 8064 if ((sgptr & SG_LIST_NULL) != 0) 8065 /* Case 2 */ 8066 return; 8067 8068 /* 8069 * Residual fields are the same in both 8070 * target and initiator status packets, 8071 * so we can always use the initiator fields 8072 * regardless of the role for this SCB. 8073 */ 8074 spkt = &hscb->shared_data.istatus; 8075 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 8076 if ((sgptr & SG_FULL_RESID) != 0) { 8077 /* Case 3 */ 8078 resid = ahd_get_transfer_length(scb); 8079 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 8080 /* Case 4 */ 8081 return; 8082 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 8083 ahd_print_path(ahd, scb); 8084 printf("data overrun detected Tag == 0x%x.\n", 8085 SCB_GET_TAG(scb)); 8086 ahd_freeze_devq(ahd, scb); 8087 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 8088 ahd_freeze_scb(scb); 8089 return; 8090 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 8091 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 8092 /* NOTREACHED */ 8093 } else { 8094 struct ahd_dma_seg *sg; 8095 8096 /* 8097 * Remainder of the SG where the transfer 8098 * stopped. 8099 */ 8100 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 8101 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 8102 8103 /* The residual sg_ptr always points to the next sg */ 8104 sg--; 8105 8106 /* 8107 * Add up the contents of all residual 8108 * SG segments that are after the SG where 8109 * the transfer stopped. 8110 */ 8111 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 8112 sg++; 8113 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 8114 } 8115 } 8116 8117 if ((scb->flags & SCB_SENSE) == 0) 8118 ahd_set_residual(scb, resid); 8119 /*else 8120 ahd_set_sense_residual(scb, resid);*/ 8121 8122 #ifdef AHD_DEBUG 8123 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 8124 ahd_print_path(ahd, scb); 8125 printf("Handled %sResidual of %d bytes\n", 8126 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 8127 } 8128 #endif 8129 } 8130 8131 /******************************* Target Mode **********************************/ 8132 #ifdef AHD_TARGET_MODE 8133 /* 8134 * Add a target mode event to this lun's queue 8135 */ 8136 static void 8137 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8138 u_int initiator_id, u_int event_type, u_int event_arg) 8139 { 8140 struct ahd_tmode_event *event; 8141 int pending; 8142 8143 xpt_freeze_devq(lstate->path, /*count*/1); 8144 if (lstate->event_w_idx >= lstate->event_r_idx) 8145 pending = lstate->event_w_idx - lstate->event_r_idx; 8146 else 8147 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8148 - (lstate->event_r_idx - lstate->event_w_idx); 8149 8150 if (event_type == EVENT_TYPE_BUS_RESET 8151 || event_type == MSG_BUS_DEV_RESET) { 8152 /* 8153 * Any earlier events are irrelevant, so reset our buffer. 8154 * This has the effect of allowing us to deal with reset 8155 * floods (an external device holding down the reset line) 8156 * without losing the event that is really interesting. 8157 */ 8158 lstate->event_r_idx = 0; 8159 lstate->event_w_idx = 0; 8160 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8161 } 8162 8163 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8164 xpt_print_path(lstate->path); 8165 printf("immediate event %x:%x lost\n", 8166 lstate->event_buffer[lstate->event_r_idx].event_type, 8167 lstate->event_buffer[lstate->event_r_idx].event_arg); 8168 lstate->event_r_idx++; 8169 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8170 lstate->event_r_idx = 0; 8171 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8172 } 8173 8174 event = &lstate->event_buffer[lstate->event_w_idx]; 8175 event->initiator_id = initiator_id; 8176 event->event_type = event_type; 8177 event->event_arg = event_arg; 8178 lstate->event_w_idx++; 8179 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8180 lstate->event_w_idx = 0; 8181 } 8182 8183 /* 8184 * Send any target mode events queued up waiting 8185 * for immediate notify resources. 8186 */ 8187 void 8188 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8189 { 8190 struct ccb_hdr *ccbh; 8191 struct ccb_immed_notify *inot; 8192 8193 while (lstate->event_r_idx != lstate->event_w_idx 8194 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8195 struct ahd_tmode_event *event; 8196 8197 event = &lstate->event_buffer[lstate->event_r_idx]; 8198 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8199 inot = (struct ccb_immed_notify *)ccbh; 8200 switch (event->event_type) { 8201 case EVENT_TYPE_BUS_RESET: 8202 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8203 break; 8204 default: 8205 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8206 inot->message_args[0] = event->event_type; 8207 inot->message_args[1] = event->event_arg; 8208 break; 8209 } 8210 inot->initiator_id = event->initiator_id; 8211 inot->sense_len = 0; 8212 xpt_done((union ccb *)inot); 8213 lstate->event_r_idx++; 8214 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8215 lstate->event_r_idx = 0; 8216 } 8217 } 8218 #endif 8219 8220 /******************** Sequencer Program Patching/Download *********************/ 8221 8222 #ifdef AHD_DUMP_SEQ 8223 void 8224 ahd_dumpseq(struct ahd_softc* ahd) 8225 { 8226 int i; 8227 int max_prog; 8228 8229 max_prog = 2048; 8230 8231 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8232 ahd_outb(ahd, PRGMCNT, 0); 8233 ahd_outb(ahd, PRGMCNT+1, 0); 8234 for (i = 0; i < max_prog; i++) { 8235 uint8_t ins_bytes[4]; 8236 8237 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8238 printf("0x%08x\n", ins_bytes[0] << 24 8239 | ins_bytes[1] << 16 8240 | ins_bytes[2] << 8 8241 | ins_bytes[3]); 8242 } 8243 } 8244 #endif 8245 8246 static void 8247 ahd_loadseq(struct ahd_softc *ahd) 8248 { 8249 struct cs cs_table[num_critical_sections]; 8250 u_int begin_set[num_critical_sections]; 8251 u_int end_set[num_critical_sections]; 8252 struct patch *cur_patch; 8253 u_int cs_count; 8254 u_int cur_cs; 8255 u_int i; 8256 int downloaded; 8257 u_int skip_addr; 8258 u_int sg_prefetch_cnt; 8259 u_int sg_prefetch_cnt_limit; 8260 u_int sg_prefetch_align; 8261 u_int sg_size; 8262 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8263 8264 if (bootverbose) 8265 printf("%s: Downloading Sequencer Program...", 8266 ahd_name(ahd)); 8267 8268 #if DOWNLOAD_CONST_COUNT != 7 8269 #error "Download Const Mismatch" 8270 #endif 8271 /* 8272 * Start out with 0 critical sections 8273 * that apply to this firmware load. 8274 */ 8275 cs_count = 0; 8276 cur_cs = 0; 8277 memset(begin_set, 0, sizeof(begin_set)); 8278 memset(end_set, 0, sizeof(end_set)); 8279 8280 /* 8281 * Setup downloadable constant table. 8282 * 8283 * The computation for the S/G prefetch variables is 8284 * a bit complicated. We would like to always fetch 8285 * in terms of cachelined sized increments. However, 8286 * if the cacheline is not an even multiple of the 8287 * SG element size or is larger than our SG RAM, using 8288 * just the cache size might leave us with only a portion 8289 * of an SG element at the tail of a prefetch. If the 8290 * cacheline is larger than our S/G prefetch buffer less 8291 * the size of an SG element, we may round down to a cacheline 8292 * that doesn't contain any or all of the S/G of interest 8293 * within the bounds of our S/G ram. Provide variables to 8294 * the sequencer that will allow it to handle these edge 8295 * cases. 8296 */ 8297 /* Start by aligning to the nearest cacheline. */ 8298 sg_prefetch_align = ahd->pci_cachesize; 8299 if (sg_prefetch_align == 0) 8300 sg_prefetch_align = 8; 8301 /* Round down to the nearest power of 2. */ 8302 while (powerof2(sg_prefetch_align) == 0) 8303 sg_prefetch_align--; 8304 /* 8305 * If the cacheline boundary is greater than half our prefetch RAM 8306 * we risk not being able to fetch even a single complete S/G 8307 * segment if we align to that boundary. 8308 */ 8309 if (sg_prefetch_align > CCSGADDR_MAX/2) 8310 sg_prefetch_align = CCSGADDR_MAX/2; 8311 /* Start by fetching a single cacheline. */ 8312 sg_prefetch_cnt = sg_prefetch_align; 8313 /* 8314 * Increment the prefetch count by cachelines until 8315 * at least one S/G element will fit. 8316 */ 8317 sg_size = sizeof(struct ahd_dma_seg); 8318 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8319 sg_size = sizeof(struct ahd_dma64_seg); 8320 while (sg_prefetch_cnt < sg_size) 8321 sg_prefetch_cnt += sg_prefetch_align; 8322 /* 8323 * If the cacheline is not an even multiple of 8324 * the S/G size, we may only get a partial S/G when 8325 * we align. Add a cacheline if this is the case. 8326 */ 8327 if ((sg_prefetch_align % sg_size) != 0 8328 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8329 sg_prefetch_cnt += sg_prefetch_align; 8330 /* 8331 * Lastly, compute a value that the sequencer can use 8332 * to determine if the remainder of the CCSGRAM buffer 8333 * has a full S/G element in it. 8334 */ 8335 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8336 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8337 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8338 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8339 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8340 download_consts[SG_SIZEOF] = sg_size; 8341 download_consts[PKT_OVERRUN_BUFOFFSET] = 8342 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8343 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8344 cur_patch = patches; 8345 downloaded = 0; 8346 skip_addr = 0; 8347 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8348 ahd_outb(ahd, PRGMCNT, 0); 8349 ahd_outb(ahd, PRGMCNT+1, 0); 8350 8351 for (i = 0; i < sizeof(seqprog)/4; i++) { 8352 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8353 /* 8354 * Don't download this instruction as it 8355 * is in a patch that was removed. 8356 */ 8357 continue; 8358 } 8359 /* 8360 * Move through the CS table until we find a CS 8361 * that might apply to this instruction. 8362 */ 8363 for (; cur_cs < num_critical_sections; cur_cs++) { 8364 if (critical_sections[cur_cs].end <= i) { 8365 if (begin_set[cs_count] == TRUE 8366 && end_set[cs_count] == FALSE) { 8367 cs_table[cs_count].end = downloaded; 8368 end_set[cs_count] = TRUE; 8369 cs_count++; 8370 } 8371 continue; 8372 } 8373 if (critical_sections[cur_cs].begin <= i 8374 && begin_set[cs_count] == FALSE) { 8375 cs_table[cs_count].begin = downloaded; 8376 begin_set[cs_count] = TRUE; 8377 } 8378 break; 8379 } 8380 ahd_download_instr(ahd, i, download_consts); 8381 downloaded++; 8382 } 8383 8384 ahd->num_critical_sections = cs_count; 8385 if (cs_count != 0) { 8386 8387 cs_count *= sizeof(struct cs); 8388 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8389 if (ahd->critical_sections == NULL) 8390 panic("ahd_loadseq: Could not malloc"); 8391 memcpy(ahd->critical_sections, cs_table, cs_count); 8392 } 8393 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8394 8395 if (bootverbose) { 8396 printf(" %d instructions downloaded\n", downloaded); 8397 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8398 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8399 } 8400 } 8401 8402 static int 8403 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8404 u_int start_instr, u_int *skip_addr) 8405 { 8406 struct patch *cur_patch; 8407 struct patch *last_patch; 8408 u_int num_patches; 8409 8410 num_patches = sizeof(patches)/sizeof(struct patch); 8411 last_patch = &patches[num_patches]; 8412 cur_patch = *start_patch; 8413 8414 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8415 8416 if (cur_patch->patch_func(ahd) == 0) { 8417 8418 /* Start rejecting code */ 8419 *skip_addr = start_instr + cur_patch->skip_instr; 8420 cur_patch += cur_patch->skip_patch; 8421 } else { 8422 /* Accepted this patch. Advance to the next 8423 * one and wait for our intruction pointer to 8424 * hit this point. 8425 */ 8426 cur_patch++; 8427 } 8428 } 8429 8430 *start_patch = cur_patch; 8431 if (start_instr < *skip_addr) 8432 /* Still skipping */ 8433 return (0); 8434 8435 return (1); 8436 } 8437 8438 static u_int 8439 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8440 { 8441 struct patch *cur_patch; 8442 int address_offset; 8443 u_int skip_addr; 8444 u_int i; 8445 8446 address_offset = 0; 8447 cur_patch = patches; 8448 skip_addr = 0; 8449 8450 for (i = 0; i < address;) { 8451 8452 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8453 8454 if (skip_addr > i) { 8455 int end_addr; 8456 8457 end_addr = MIN(address, skip_addr); 8458 address_offset += end_addr - i; 8459 i = skip_addr; 8460 } else { 8461 i++; 8462 } 8463 } 8464 return (address - address_offset); 8465 } 8466 8467 static void 8468 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8469 { 8470 union ins_formats instr; 8471 struct ins_format1 *fmt1_ins; 8472 struct ins_format3 *fmt3_ins; 8473 u_int opcode; 8474 8475 /* 8476 * The firmware is always compiled into a little endian format. 8477 */ 8478 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8479 8480 fmt1_ins = &instr.format1; 8481 fmt3_ins = NULL; 8482 8483 /* Pull the opcode */ 8484 opcode = instr.format1.opcode; 8485 switch (opcode) { 8486 case AIC_OP_JMP: 8487 case AIC_OP_JC: 8488 case AIC_OP_JNC: 8489 case AIC_OP_CALL: 8490 case AIC_OP_JNE: 8491 case AIC_OP_JNZ: 8492 case AIC_OP_JE: 8493 case AIC_OP_JZ: 8494 { 8495 fmt3_ins = &instr.format3; 8496 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8497 /* FALLTHROUGH */ 8498 } 8499 case AIC_OP_OR: 8500 case AIC_OP_AND: 8501 case AIC_OP_XOR: 8502 case AIC_OP_ADD: 8503 case AIC_OP_ADC: 8504 case AIC_OP_BMOV: 8505 if (fmt1_ins->parity != 0) { 8506 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8507 } 8508 fmt1_ins->parity = 0; 8509 /* FALLTHROUGH */ 8510 case AIC_OP_ROL: 8511 { 8512 int i, count; 8513 8514 /* Calculate odd parity for the instruction */ 8515 for (i = 0, count = 0; i < 31; i++) { 8516 uint32_t mask; 8517 8518 mask = 0x01 << i; 8519 if ((instr.integer & mask) != 0) 8520 count++; 8521 } 8522 if ((count & 0x01) == 0) 8523 instr.format1.parity = 1; 8524 8525 /* The sequencer is a little endian CPU */ 8526 instr.integer = ahd_htole32(instr.integer); 8527 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8528 break; 8529 } 8530 default: 8531 panic("Unknown opcode encountered in seq program"); 8532 break; 8533 } 8534 } 8535 8536 static int 8537 ahd_probe_stack_size(struct ahd_softc *ahd) 8538 { 8539 int last_probe; 8540 8541 last_probe = 0; 8542 while (1) { 8543 int i; 8544 8545 /* 8546 * We avoid using 0 as a pattern to avoid 8547 * confusion if the stack implementation 8548 * "back-fills" with zeros when "poping' 8549 * entries. 8550 */ 8551 for (i = 1; i <= last_probe+1; i++) { 8552 ahd_outb(ahd, STACK, i & 0xFF); 8553 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8554 } 8555 8556 /* Verify */ 8557 for (i = last_probe+1; i > 0; i--) { 8558 u_int stack_entry; 8559 8560 stack_entry = ahd_inb(ahd, STACK) 8561 |(ahd_inb(ahd, STACK) << 8); 8562 if (stack_entry != i) 8563 goto sized; 8564 } 8565 last_probe++; 8566 } 8567 sized: 8568 return (last_probe); 8569 } 8570 8571 void 8572 ahd_dump_all_cards_state(void) 8573 { 8574 struct ahd_softc *list_ahd; 8575 8576 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8577 ahd_dump_card_state(list_ahd); 8578 } 8579 } 8580 8581 int 8582 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8583 const char *name, u_int address, u_int value, 8584 u_int *cur_column, u_int wrap_point) 8585 { 8586 int printed; 8587 u_int printed_mask; 8588 char line[1024]; 8589 8590 line[0] = 0; 8591 8592 if (cur_column != NULL && *cur_column >= wrap_point) { 8593 printf("\n"); 8594 *cur_column = 0; 8595 } 8596 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 8597 if (table == NULL) { 8598 printed += snprintf(&line[printed], (sizeof line) - printed, 8599 " "); 8600 printf("%s", line); 8601 if (cur_column != NULL) 8602 *cur_column += printed; 8603 return (printed); 8604 } 8605 printed_mask = 0; 8606 while (printed_mask != 0xFF) { 8607 int entry; 8608 8609 for (entry = 0; entry < num_entries; entry++) { 8610 if (((value & table[entry].mask) 8611 != table[entry].value) 8612 || ((printed_mask & table[entry].mask) 8613 == table[entry].mask)) 8614 continue; 8615 printed += snprintf(&line[printed], 8616 (sizeof line) - printed, "%s%s", 8617 printed_mask == 0 ? ":(" : "|", 8618 table[entry].name); 8619 printed_mask |= table[entry].mask; 8620 8621 break; 8622 } 8623 if (entry >= num_entries) 8624 break; 8625 } 8626 if (printed_mask != 0) 8627 printed += snprintf(&line[printed], 8628 (sizeof line) - printed, ") "); 8629 else 8630 printed += snprintf(&line[printed], 8631 (sizeof line) - printed, " "); 8632 if (cur_column != NULL) 8633 *cur_column += printed; 8634 printf("%s", line); 8635 8636 return (printed); 8637 } 8638 8639 void 8640 ahd_dump_card_state(struct ahd_softc *ahd) 8641 { 8642 struct scb *scb; 8643 ahd_mode_state saved_modes; 8644 u_int dffstat; 8645 int paused; 8646 u_int scb_index; 8647 u_int saved_scb_index; 8648 u_int cur_col; 8649 int i; 8650 8651 if (ahd_is_paused(ahd)) { 8652 paused = 1; 8653 } else { 8654 paused = 0; 8655 ahd_pause(ahd); 8656 } 8657 saved_modes = ahd_save_modes(ahd); 8658 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8659 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8660 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8661 ahd_name(ahd), 8662 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8663 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8664 ahd->saved_dst_mode)); 8665 if (paused) 8666 printf("Card was paused\n"); 8667 8668 if (ahd_check_cmdcmpltqueues(ahd)) 8669 printf("Completions are pending\n"); 8670 /* 8671 * Mode independent registers. 8672 */ 8673 cur_col = 0; 8674 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8675 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8676 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8677 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8678 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8679 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8680 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8681 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8682 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8683 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8684 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8685 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8686 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8687 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8688 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8689 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8690 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8691 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8692 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8693 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8694 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8695 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8696 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8697 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8698 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8699 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8700 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8701 printf("\n"); 8702 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8703 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8704 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8705 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8706 ahd_inw(ahd, NEXTSCB)); 8707 cur_col = 0; 8708 /* QINFIFO */ 8709 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8710 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8711 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8712 saved_scb_index = ahd_get_scbptr(ahd); 8713 printf("Pending list:"); 8714 i = 0; 8715 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8716 if (i++ > AHD_SCB_MAX) 8717 break; 8718 /*cur_col =*/ printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8719 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 8720 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8721 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 8722 &cur_col, 60); 8723 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 8724 &cur_col, 60); 8725 } 8726 printf("\nTotal %d\n", i); 8727 8728 printf("Kernel Free SCB list: "); 8729 i = 0; 8730 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8731 struct scb *list_scb; 8732 8733 list_scb = scb; 8734 do { 8735 printf("%d ", SCB_GET_TAG(list_scb)); 8736 list_scb = LIST_NEXT(list_scb, collision_links); 8737 } while (list_scb && i++ < AHD_SCB_MAX); 8738 } 8739 8740 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8741 if (i++ > AHD_SCB_MAX) 8742 break; 8743 printf("%d ", SCB_GET_TAG(scb)); 8744 } 8745 printf("\n"); 8746 8747 printf("Sequencer Complete DMA-inprog list: "); 8748 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8749 i = 0; 8750 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8751 ahd_set_scbptr(ahd, scb_index); 8752 printf("%d ", scb_index); 8753 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8754 } 8755 printf("\n"); 8756 8757 printf("Sequencer Complete list: "); 8758 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8759 i = 0; 8760 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8761 ahd_set_scbptr(ahd, scb_index); 8762 printf("%d ", scb_index); 8763 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8764 } 8765 printf("\n"); 8766 8767 8768 printf("Sequencer DMA-Up and Complete list: "); 8769 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8770 i = 0; 8771 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8772 ahd_set_scbptr(ahd, scb_index); 8773 printf("%d ", scb_index); 8774 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8775 } 8776 printf("\n"); 8777 ahd_set_scbptr(ahd, saved_scb_index); 8778 dffstat = ahd_inb(ahd, DFFSTAT); 8779 for (i = 0; i < 2; i++) { 8780 #ifdef AHD_DEBUG 8781 struct scb *fifo_scb; 8782 #endif 8783 u_int fifo_scbptr; 8784 8785 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8786 fifo_scbptr = ahd_get_scbptr(ahd); 8787 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 8788 ahd_name(ahd), i, 8789 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8790 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 8791 cur_col = 0; 8792 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8793 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8794 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8795 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8796 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8797 &cur_col, 50); 8798 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8799 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8800 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8801 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8802 if (cur_col > 50) { 8803 printf("\n"); 8804 cur_col = 0; 8805 } 8806 printf("\nSHADDR = 0x%x%x, SHCNT = 0x%x ", 8807 ahd_inl(ahd, SHADDR+4), 8808 ahd_inl(ahd, SHADDR), 8809 (ahd_inb(ahd, SHCNT) 8810 | (ahd_inb(ahd, SHCNT + 1) << 8) 8811 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8812 printf("HADDR = 0x%x%x, HCNT = 0x%x \n", 8813 ahd_inl(ahd, HADDR+4), 8814 ahd_inl(ahd, HADDR), 8815 (ahd_inb(ahd, HCNT) 8816 | (ahd_inb(ahd, HCNT + 1) << 8) 8817 | (ahd_inb(ahd, HCNT + 2) << 16))); 8818 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8819 #ifdef AHD_DEBUG 8820 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8821 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8822 if (fifo_scb != NULL) 8823 ahd_dump_sglist(fifo_scb); 8824 } 8825 #endif 8826 } 8827 printf("\nLQIN: "); 8828 for (i = 0; i < 20; i++) 8829 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8830 printf("\n"); 8831 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8832 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8833 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8834 ahd_inb(ahd, OPTIONMODE)); 8835 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8836 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8837 ahd_inb(ahd, MAXCMDCNT)); 8838 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8839 printf("\n"); 8840 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8841 cur_col = 0; 8842 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8843 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8844 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8845 ahd_inw(ahd, DINDEX)); 8846 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8847 ahd_name(ahd), ahd_get_scbptr(ahd), 8848 ahd_inw_scbram(ahd, SCB_NEXT), 8849 ahd_inw_scbram(ahd, SCB_NEXT2)); 8850 printf("CDB %x %x %x %x %x %x\n", 8851 ahd_inb_scbram(ahd, SCB_CDB_STORE), 8852 ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 8853 ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 8854 ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 8855 ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 8856 ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 8857 printf("STACK:"); 8858 for (i = 0; i < ahd->stack_size; i++) { 8859 ahd->saved_stack[i] = 8860 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8861 printf(" 0x%x", ahd->saved_stack[i]); 8862 } 8863 for (i = ahd->stack_size-1; i >= 0; i--) { 8864 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8865 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8866 } 8867 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8868 ahd_platform_dump_card_state(ahd); 8869 ahd_restore_modes(ahd, saved_modes); 8870 if (paused == 0) 8871 ahd_unpause(ahd); 8872 } 8873 8874 void 8875 ahd_dump_scbs(struct ahd_softc *ahd) 8876 { 8877 ahd_mode_state saved_modes; 8878 u_int saved_scb_index; 8879 int i; 8880 8881 saved_modes = ahd_save_modes(ahd); 8882 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8883 saved_scb_index = ahd_get_scbptr(ahd); 8884 for (i = 0; i < AHD_SCB_MAX; i++) { 8885 ahd_set_scbptr(ahd, i); 8886 printf("%3d", i); 8887 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8888 ahd_inb_scbram(ahd, SCB_CONTROL), 8889 ahd_inb_scbram(ahd, SCB_SCSIID), 8890 ahd_inw_scbram(ahd, SCB_NEXT), 8891 ahd_inw_scbram(ahd, SCB_NEXT2), 8892 ahd_inl_scbram(ahd, SCB_SGPTR), 8893 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 8894 } 8895 printf("\n"); 8896 ahd_set_scbptr(ahd, saved_scb_index); 8897 ahd_restore_modes(ahd, saved_modes); 8898 } 8899 8900 /**************************** Flexport Logic **********************************/ 8901 /* 8902 * Read count 16bit words from 16bit word address start_addr from the 8903 * SEEPROM attached to the controller, into tbuf, using the controller's 8904 * SEEPROM reading state machine. Optionally treat the data as a byte 8905 * stream in terms of byte order. 8906 */ 8907 int 8908 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, 8909 u_int start_addr, u_int count, int bytestream) 8910 { 8911 u_int cur_addr; 8912 u_int end_addr; 8913 int error; 8914 8915 /* 8916 * If we never make it through the loop even once, 8917 * we were passed invalid arguments. 8918 */ 8919 error = EINVAL; 8920 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8921 end_addr = start_addr + count; 8922 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8923 8924 ahd_outb(ahd, SEEADR, cur_addr); 8925 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8926 8927 error = ahd_wait_seeprom(ahd); 8928 if (error) { 8929 printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd)); 8930 break; 8931 } 8932 if (bytestream != 0) { 8933 uint8_t *bytestream_ptr; 8934 8935 bytestream_ptr = (uint8_t *)tbuf; 8936 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 8937 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 8938 } else { 8939 /* 8940 * ahd_inw() already handles machine byte order. 8941 */ 8942 *tbuf = ahd_inw(ahd, SEEDAT); 8943 } 8944 tbuf++; 8945 } 8946 return (error); 8947 } 8948 8949 /* 8950 * Write count 16bit words from tbuf, into SEEPROM attache to the 8951 * controller starting at 16bit word address start_addr, using the 8952 * controller's SEEPROM writing state machine. 8953 */ 8954 int 8955 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *tbuf, 8956 u_int start_addr, u_int count) 8957 { 8958 u_int cur_addr; 8959 u_int end_addr; 8960 int error; 8961 int retval; 8962 8963 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8964 error = ENOENT; 8965 8966 /* Place the chip into write-enable mode */ 8967 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8968 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8969 error = ahd_wait_seeprom(ahd); 8970 if (error) 8971 return (error); 8972 8973 /* 8974 * Write the data. If we don't get throught the loop at 8975 * least once, the arguments were invalid. 8976 */ 8977 retval = EINVAL; 8978 end_addr = start_addr + count; 8979 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8980 ahd_outw(ahd, SEEDAT, *tbuf++); 8981 ahd_outb(ahd, SEEADR, cur_addr); 8982 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8983 8984 retval = ahd_wait_seeprom(ahd); 8985 if (retval) 8986 break; 8987 } 8988 8989 /* 8990 * Disable writes. 8991 */ 8992 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8993 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8994 error = ahd_wait_seeprom(ahd); 8995 if (error) 8996 return (error); 8997 return (retval); 8998 } 8999 9000 /* 9001 * Wait ~100us for the serial eeprom to satisfy our request. 9002 */ 9003 int 9004 ahd_wait_seeprom(struct ahd_softc *ahd) 9005 { 9006 int cnt; 9007 9008 cnt = 2000; 9009 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 9010 ahd_delay(5); 9011 9012 if (cnt == 0) 9013 return (ETIMEDOUT); 9014 return (0); 9015 } 9016 9017 /* 9018 * Validate the two checksums in the per_channel 9019 * vital product data struct. 9020 */ 9021 int 9022 ahd_verify_vpd_cksum(struct vpd_config *vpd) 9023 { 9024 int i; 9025 int maxaddr; 9026 uint32_t checksum; 9027 uint8_t *vpdarray; 9028 9029 vpdarray = (uint8_t *)vpd; 9030 maxaddr = offsetof(struct vpd_config, vpd_checksum); 9031 checksum = 0; 9032 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 9033 checksum = checksum + vpdarray[i]; 9034 if (checksum == 0 9035 || (-checksum & 0xFF) != vpd->vpd_checksum) 9036 return (0); 9037 9038 checksum = 0; 9039 maxaddr = offsetof(struct vpd_config, checksum); 9040 for (i = offsetof(struct vpd_config, default_target_flags); 9041 i < maxaddr; i++) 9042 checksum = checksum + vpdarray[i]; 9043 if (checksum == 0 9044 || (-checksum & 0xFF) != vpd->checksum) 9045 return (0); 9046 return (1); 9047 } 9048 9049 int 9050 ahd_verify_cksum(struct seeprom_config *sc) 9051 { 9052 int i; 9053 int maxaddr; 9054 uint32_t checksum; 9055 uint16_t *scarray; 9056 9057 maxaddr = (sizeof(*sc)/2) - 1; 9058 checksum = 0; 9059 scarray = (uint16_t *)sc; 9060 9061 for (i = 0; i < maxaddr; i++) 9062 checksum = checksum + scarray[i]; 9063 if (checksum == 0 9064 || (checksum & 0xFFFF) != sc->checksum) { 9065 return (0); 9066 } else { 9067 return (1); 9068 } 9069 } 9070 9071 int 9072 ahd_acquire_seeprom(struct ahd_softc *ahd) 9073 { 9074 /* 9075 * We should be able to determine the SEEPROM type 9076 * from the flexport logic, but unfortunately not 9077 * all implementations have this logic and there is 9078 * no programatic method for determining if the logic 9079 * is present. 9080 */ 9081 9082 return (1); 9083 #if 0 9084 uint8_t seetype; 9085 int error; 9086 9087 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 9088 if (error != 0 9089 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 9090 return (0); 9091 return (1); 9092 #endif 9093 } 9094 9095 void 9096 ahd_release_seeprom(struct ahd_softc *ahd) 9097 { 9098 /* Currently a no-op */ 9099 } 9100 9101 int 9102 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 9103 { 9104 int error; 9105 9106 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9107 if (addr > 7) 9108 panic("ahd_write_flexport: address out of range"); 9109 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9110 error = ahd_wait_flexport(ahd); 9111 if (error != 0) 9112 return (error); 9113 ahd_outb(ahd, BRDDAT, value); 9114 ahd_flush_device_writes(ahd); 9115 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 9116 ahd_flush_device_writes(ahd); 9117 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9118 ahd_flush_device_writes(ahd); 9119 ahd_outb(ahd, BRDCTL, 0); 9120 ahd_flush_device_writes(ahd); 9121 return (0); 9122 } 9123 9124 int 9125 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 9126 { 9127 int error; 9128 9129 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9130 if (addr > 7) 9131 panic("ahd_read_flexport: address out of range"); 9132 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 9133 error = ahd_wait_flexport(ahd); 9134 if (error != 0) 9135 return (error); 9136 *value = ahd_inb(ahd, BRDDAT); 9137 ahd_outb(ahd, BRDCTL, 0); 9138 ahd_flush_device_writes(ahd); 9139 return (0); 9140 } 9141 9142 /* 9143 * Wait at most 2 seconds for flexport arbitration to succeed. 9144 */ 9145 int 9146 ahd_wait_flexport(struct ahd_softc *ahd) 9147 { 9148 int cnt; 9149 9150 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9151 cnt = 1000000 * 2 / 5; 9152 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 9153 ahd_delay(5); 9154 9155 if (cnt == 0) 9156 return (ETIMEDOUT); 9157 return (0); 9158 } 9159 9160 /************************* Target Mode ****************************************/ 9161 #ifdef AHD_TARGET_MODE 9162 cam_status 9163 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 9164 struct ahd_tmode_tstate **tstate, 9165 struct ahd_tmode_lstate **lstate, 9166 int notfound_failure) 9167 { 9168 9169 if ((ahd->features & AHD_TARGETMODE) == 0) 9170 return (CAM_REQ_INVALID); 9171 9172 /* 9173 * Handle the 'black hole' device that sucks up 9174 * requests to unattached luns on enabled targets. 9175 */ 9176 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 9177 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 9178 *tstate = NULL; 9179 *lstate = ahd->black_hole; 9180 } else { 9181 u_int max_id; 9182 9183 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 9184 if (ccb->ccb_h.target_id > max_id) 9185 return (CAM_TID_INVALID); 9186 9187 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9188 return (CAM_LUN_INVALID); 9189 9190 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9191 *lstate = NULL; 9192 if (*tstate != NULL) 9193 *lstate = 9194 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9195 } 9196 9197 if (notfound_failure != 0 && *lstate == NULL) 9198 return (CAM_PATH_INVALID); 9199 9200 return (CAM_REQ_CMP); 9201 } 9202 9203 void 9204 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9205 { 9206 #if NOT_YET 9207 struct ahd_tmode_tstate *tstate; 9208 struct ahd_tmode_lstate *lstate; 9209 struct ccb_en_lun *cel; 9210 cam_status status; 9211 u_int target; 9212 u_int lun; 9213 u_int target_mask; 9214 u_long s; 9215 char channel; 9216 9217 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9218 /*notfound_failure*/FALSE); 9219 9220 if (status != CAM_REQ_CMP) { 9221 ccb->ccb_h.status = status; 9222 return; 9223 } 9224 9225 if ((ahd->features & AHD_MULTIROLE) != 0) { 9226 u_int our_id; 9227 9228 our_id = ahd->our_id; 9229 if (ccb->ccb_h.target_id != our_id) { 9230 if ((ahd->features & AHD_MULTI_TID) != 0 9231 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9232 /* 9233 * Only allow additional targets if 9234 * the initiator role is disabled. 9235 * The hardware cannot handle a re-select-in 9236 * on the initiator id during a re-select-out 9237 * on a different target id. 9238 */ 9239 status = CAM_TID_INVALID; 9240 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9241 || ahd->enabled_luns > 0) { 9242 /* 9243 * Only allow our target id to change 9244 * if the initiator role is not configured 9245 * and there are no enabled luns which 9246 * are attached to the currently registered 9247 * scsi id. 9248 */ 9249 status = CAM_TID_INVALID; 9250 } 9251 } 9252 } 9253 9254 if (status != CAM_REQ_CMP) { 9255 ccb->ccb_h.status = status; 9256 return; 9257 } 9258 9259 /* 9260 * We now have an id that is valid. 9261 * If we aren't in target mode, switch modes. 9262 */ 9263 if ((ahd->flags & AHD_TARGETROLE) == 0 9264 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9265 u_long s; 9266 9267 printf("Configuring Target Mode\n"); 9268 ahd_lock(ahd, &s); 9269 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9270 ccb->ccb_h.status = CAM_BUSY; 9271 ahd_unlock(ahd, &s); 9272 return; 9273 } 9274 ahd->flags |= AHD_TARGETROLE; 9275 if ((ahd->features & AHD_MULTIROLE) == 0) 9276 ahd->flags &= ~AHD_INITIATORROLE; 9277 ahd_pause(ahd); 9278 ahd_loadseq(ahd); 9279 ahd_restart(ahd); 9280 ahd_unlock(ahd, &s); 9281 } 9282 cel = &ccb->cel; 9283 target = ccb->ccb_h.target_id; 9284 lun = ccb->ccb_h.target_lun; 9285 channel = SIM_CHANNEL(ahd, sim); 9286 target_mask = 0x01 << target; 9287 if (channel == 'B') 9288 target_mask <<= 8; 9289 9290 if (cel->enable != 0) { 9291 u_int scsiseq1; 9292 9293 /* Are we already enabled?? */ 9294 if (lstate != NULL) { 9295 xpt_print_path(ccb->ccb_h.path); 9296 printf("Lun already enabled\n"); 9297 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9298 return; 9299 } 9300 9301 if (cel->grp6_len != 0 9302 || cel->grp7_len != 0) { 9303 /* 9304 * Don't (yet?) support vendor 9305 * specific commands. 9306 */ 9307 ccb->ccb_h.status = CAM_REQ_INVALID; 9308 printf("Non-zero Group Codes\n"); 9309 return; 9310 } 9311 9312 /* 9313 * Seems to be okay. 9314 * Setup our data structures. 9315 */ 9316 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9317 tstate = ahd_alloc_tstate(ahd, target, channel); 9318 if (tstate == NULL) { 9319 xpt_print_path(ccb->ccb_h.path); 9320 printf("Couldn't allocate tstate\n"); 9321 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9322 return; 9323 } 9324 } 9325 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9326 if (lstate == NULL) { 9327 xpt_print_path(ccb->ccb_h.path); 9328 printf("Couldn't allocate lstate\n"); 9329 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9330 return; 9331 } 9332 memset(lstate, 0, sizeof(*lstate)); 9333 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9334 xpt_path_path_id(ccb->ccb_h.path), 9335 xpt_path_target_id(ccb->ccb_h.path), 9336 xpt_path_lun_id(ccb->ccb_h.path)); 9337 if (status != CAM_REQ_CMP) { 9338 free(lstate, M_DEVBUF); 9339 xpt_print_path(ccb->ccb_h.path); 9340 printf("Couldn't allocate path\n"); 9341 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9342 return; 9343 } 9344 SLIST_INIT(&lstate->accept_tios); 9345 SLIST_INIT(&lstate->immed_notifies); 9346 ahd_lock(ahd, &s); 9347 ahd_pause(ahd); 9348 if (target != CAM_TARGET_WILDCARD) { 9349 tstate->enabled_luns[lun] = lstate; 9350 ahd->enabled_luns++; 9351 9352 if ((ahd->features & AHD_MULTI_TID) != 0) { 9353 u_int targid_mask; 9354 9355 targid_mask = ahd_inb(ahd, TARGID) 9356 | (ahd_inb(ahd, TARGID + 1) << 8); 9357 9358 targid_mask |= target_mask; 9359 ahd_outb(ahd, TARGID, targid_mask); 9360 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9361 9362 ahd_update_scsiid(ahd, targid_mask); 9363 } else { 9364 u_int our_id; 9365 char channel; 9366 9367 channel = SIM_CHANNEL(ahd, sim); 9368 our_id = SIM_SCSI_ID(ahd, sim); 9369 9370 /* 9371 * This can only happen if selections 9372 * are not enabled 9373 */ 9374 if (target != our_id) { 9375 u_int sblkctl; 9376 char cur_channel; 9377 int swap; 9378 9379 sblkctl = ahd_inb(ahd, SBLKCTL); 9380 cur_channel = (sblkctl & SELBUSB) 9381 ? 'B' : 'A'; 9382 if ((ahd->features & AHD_TWIN) == 0) 9383 cur_channel = 'A'; 9384 swap = cur_channel != channel; 9385 ahd->our_id = target; 9386 9387 if (swap) 9388 ahd_outb(ahd, SBLKCTL, 9389 sblkctl ^ SELBUSB); 9390 9391 ahd_outb(ahd, SCSIID, target); 9392 9393 if (swap) 9394 ahd_outb(ahd, SBLKCTL, sblkctl); 9395 } 9396 } 9397 } else 9398 ahd->black_hole = lstate; 9399 /* Allow select-in operations */ 9400 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9401 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9402 scsiseq1 |= ENSELI; 9403 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9404 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9405 scsiseq1 |= ENSELI; 9406 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9407 } 9408 ahd_unpause(ahd); 9409 ahd_unlock(ahd, &s); 9410 ccb->ccb_h.status = CAM_REQ_CMP; 9411 xpt_print_path(ccb->ccb_h.path); 9412 printf("Lun now enabled for target mode\n"); 9413 } else { 9414 struct scb *scb; 9415 int i, empty; 9416 9417 if (lstate == NULL) { 9418 ccb->ccb_h.status = CAM_LUN_INVALID; 9419 return; 9420 } 9421 9422 ahd_lock(ahd, &s); 9423 9424 ccb->ccb_h.status = CAM_REQ_CMP; 9425 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9426 struct ccb_hdr *ccbh; 9427 9428 ccbh = &scb->io_ctx->ccb_h; 9429 if (ccbh->func_code == XPT_CONT_TARGET_IO 9430 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9431 printf("CTIO pending\n"); 9432 ccb->ccb_h.status = CAM_REQ_INVALID; 9433 ahd_unlock(ahd, &s); 9434 return; 9435 } 9436 } 9437 9438 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9439 printf("ATIOs pending\n"); 9440 ccb->ccb_h.status = CAM_REQ_INVALID; 9441 } 9442 9443 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9444 printf("INOTs pending\n"); 9445 ccb->ccb_h.status = CAM_REQ_INVALID; 9446 } 9447 9448 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9449 ahd_unlock(ahd, &s); 9450 return; 9451 } 9452 9453 xpt_print_path(ccb->ccb_h.path); 9454 printf("Target mode disabled\n"); 9455 xpt_free_path(lstate->path); 9456 free(lstate, M_DEVBUF); 9457 9458 ahd_pause(ahd); 9459 /* Can we clean up the target too? */ 9460 if (target != CAM_TARGET_WILDCARD) { 9461 tstate->enabled_luns[lun] = NULL; 9462 ahd->enabled_luns--; 9463 for (empty = 1, i = 0; i < 8; i++) 9464 if (tstate->enabled_luns[i] != NULL) { 9465 empty = 0; 9466 break; 9467 } 9468 9469 if (empty) { 9470 ahd_free_tstate(ahd, target, channel, 9471 /*force*/FALSE); 9472 if (ahd->features & AHD_MULTI_TID) { 9473 u_int targid_mask; 9474 9475 targid_mask = ahd_inb(ahd, TARGID) 9476 | (ahd_inb(ahd, TARGID + 1) 9477 << 8); 9478 9479 targid_mask &= ~target_mask; 9480 ahd_outb(ahd, TARGID, targid_mask); 9481 ahd_outb(ahd, TARGID+1, 9482 (targid_mask >> 8)); 9483 ahd_update_scsiid(ahd, targid_mask); 9484 } 9485 } 9486 } else { 9487 9488 ahd->black_hole = NULL; 9489 9490 /* 9491 * We can't allow selections without 9492 * our black hole device. 9493 */ 9494 empty = TRUE; 9495 } 9496 if (ahd->enabled_luns == 0) { 9497 /* Disallow select-in */ 9498 u_int scsiseq1; 9499 9500 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9501 scsiseq1 &= ~ENSELI; 9502 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9503 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9504 scsiseq1 &= ~ENSELI; 9505 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9506 9507 if ((ahd->features & AHD_MULTIROLE) == 0) { 9508 printf("Configuring Initiator Mode\n"); 9509 ahd->flags &= ~AHD_TARGETROLE; 9510 ahd->flags |= AHD_INITIATORROLE; 9511 ahd_pause(ahd); 9512 ahd_loadseq(ahd); 9513 ahd_restart(ahd); 9514 /* 9515 * Unpaused. The extra unpause 9516 * that follows is harmless. 9517 */ 9518 } 9519 } 9520 ahd_unpause(ahd); 9521 ahd_unlock(ahd, &s); 9522 } 9523 #endif 9524 } 9525 9526 static void 9527 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9528 { 9529 #if NOT_YET 9530 u_int scsiid_mask; 9531 u_int scsiid; 9532 9533 if ((ahd->features & AHD_MULTI_TID) == 0) 9534 panic("ahd_update_scsiid called on non-multitid unit\n"); 9535 9536 /* 9537 * Since we will rely on the TARGID mask 9538 * for selection enables, ensure that OID 9539 * in SCSIID is not set to some other ID 9540 * that we don't want to allow selections on. 9541 */ 9542 if ((ahd->features & AHD_ULTRA2) != 0) 9543 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9544 else 9545 scsiid = ahd_inb(ahd, SCSIID); 9546 scsiid_mask = 0x1 << (scsiid & OID); 9547 if ((targid_mask & scsiid_mask) == 0) { 9548 u_int our_id; 9549 9550 /* ffs counts from 1 */ 9551 our_id = ffs(targid_mask); 9552 if (our_id == 0) 9553 our_id = ahd->our_id; 9554 else 9555 our_id--; 9556 scsiid &= TID; 9557 scsiid |= our_id; 9558 } 9559 if ((ahd->features & AHD_ULTRA2) != 0) 9560 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9561 else 9562 ahd_outb(ahd, SCSIID, scsiid); 9563 #endif 9564 } 9565 9566 #ifdef AHD_TARGET_MODE 9567 void 9568 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9569 { 9570 struct target_cmd *cmd; 9571 9572 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9573 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9574 9575 /* 9576 * Only advance through the queue if we 9577 * have the resources to process the command. 9578 */ 9579 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9580 break; 9581 9582 cmd->cmd_valid = 0; 9583 ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/, 9584 ahd->shared_data_map.dmamap, 9585 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9586 sizeof(struct target_cmd), 9587 BUS_DMASYNC_PREREAD); 9588 ahd->tqinfifonext++; 9589 9590 /* 9591 * Lazily update our position in the target mode incoming 9592 * command queue as seen by the sequencer. 9593 */ 9594 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9595 u_int hs_mailbox; 9596 9597 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9598 hs_mailbox &= ~HOST_TQINPOS; 9599 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9600 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9601 } 9602 } 9603 } 9604 #endif 9605 9606 static int 9607 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9608 { 9609 struct ahd_tmode_tstate *tstate; 9610 struct ahd_tmode_lstate *lstate; 9611 struct ccb_accept_tio *atio; 9612 uint8_t *byte; 9613 int initiator; 9614 int target; 9615 int lun; 9616 9617 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9618 target = SCSIID_OUR_ID(cmd->scsiid); 9619 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9620 9621 byte = cmd->bytes; 9622 tstate = ahd->enabled_targets[target]; 9623 lstate = NULL; 9624 if (tstate != NULL) 9625 lstate = tstate->enabled_luns[lun]; 9626 9627 /* 9628 * Commands for disabled luns go to the black hole driver. 9629 */ 9630 if (lstate == NULL) 9631 lstate = ahd->black_hole; 9632 9633 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9634 if (atio == NULL) { 9635 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9636 /* 9637 * Wait for more ATIOs from the peripheral driver for this lun. 9638 */ 9639 return (1); 9640 } else 9641 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9642 #ifdef AHD_DEBUG 9643 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9644 printf("%s: incoming command from %d for %d:%d%s\n", 9645 ahd_name(ahd), 9646 initiator, target, lun, 9647 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9648 #endif 9649 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9650 9651 if (lstate == ahd->black_hole) { 9652 /* Fill in the wildcards */ 9653 atio->ccb_h.target_id = target; 9654 atio->ccb_h.target_lun = lun; 9655 } 9656 9657 /* 9658 * Package it up and send it off to 9659 * whomever has this lun enabled. 9660 */ 9661 atio->sense_len = 0; 9662 atio->init_id = initiator; 9663 if (byte[0] != 0xFF) { 9664 /* Tag was included */ 9665 atio->tag_action = *byte++; 9666 atio->tag_id = *byte++; 9667 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9668 } else { 9669 atio->ccb_h.flags = 0; 9670 } 9671 byte++; 9672 9673 /* Okay. Now determine the cdb size based on the command code */ 9674 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9675 case 0: 9676 atio->cdb_len = 6; 9677 break; 9678 case 1: 9679 case 2: 9680 atio->cdb_len = 10; 9681 break; 9682 case 4: 9683 atio->cdb_len = 16; 9684 break; 9685 case 5: 9686 atio->cdb_len = 12; 9687 break; 9688 case 3: 9689 default: 9690 /* Only copy the opcode. */ 9691 atio->cdb_len = 1; 9692 printf("Reserved or VU command code type encountered\n"); 9693 break; 9694 } 9695 9696 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9697 9698 atio->ccb_h.status |= CAM_CDB_RECVD; 9699 9700 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9701 /* 9702 * We weren't allowed to disconnect. 9703 * We're hanging on the bus until a 9704 * continue target I/O comes in response 9705 * to this accept tio. 9706 */ 9707 #ifdef AHD_DEBUG 9708 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9709 printf("Received Immediate Command %d:%d:%d - %p\n", 9710 initiator, target, lun, ahd->pending_device); 9711 #endif 9712 ahd->pending_device = lstate; 9713 ahd_freeze_ccb((union ccb *)atio); 9714 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9715 } 9716 xpt_done((union ccb*)atio); 9717 return (0); 9718 } 9719 9720 #endif 9721 9722 static int 9723 ahd_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 9724 bus_dma_tag_t tag; 9725 int size; 9726 int flags; 9727 bus_dmamap_t *mapp; 9728 caddr_t *vaddr; 9729 bus_addr_t *baddr; 9730 bus_dma_segment_t *seg; 9731 int *nseg; 9732 const char *myname, *what; 9733 { 9734 int error, level = 0; 9735 9736 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 9737 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 9738 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 9739 myname, what, error); 9740 goto out; 9741 } 9742 level++; 9743 9744 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 9745 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 9746 printf("%s: failed to map DMA mem for %s, error = %d\n", 9747 myname, what, error); 9748 goto out; 9749 } 9750 level++; 9751 9752 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 9753 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 9754 printf("%s: failed to create DMA map for %s, error = %d\n", 9755 myname, what, error); 9756 goto out; 9757 } 9758 level++; 9759 9760 9761 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 9762 BUS_DMA_NOWAIT)) != 0) { 9763 printf("%s: failed to load DMA map for %s, error = %d\n", 9764 myname, what, error); 9765 goto out; 9766 } 9767 9768 *baddr = (*mapp)->dm_segs[0].ds_addr; 9769 9770 return 0; 9771 out: 9772 printf("ahd_createdmamem error (%d)\n", level); 9773 switch (level) { 9774 case 3: 9775 bus_dmamap_destroy(tag, *mapp); 9776 /* FALLTHROUGH */ 9777 case 2: 9778 bus_dmamem_unmap(tag, *vaddr, size); 9779 /* FALLTHROUGH */ 9780 case 1: 9781 bus_dmamem_free(tag, seg, *nseg); 9782 break; 9783 default: 9784 break; 9785 } 9786 9787 return error; 9788 } 9789 9790 static void 9791 ahd_freedmamem(tag, size, map, vaddr, seg, nseg) 9792 bus_dma_tag_t tag; 9793 int size; 9794 bus_dmamap_t map; 9795 caddr_t vaddr; 9796 bus_dma_segment_t *seg; 9797 int nseg; 9798 { 9799 9800 bus_dmamap_unload(tag, map); 9801 bus_dmamap_destroy(tag, map); 9802 bus_dmamem_unmap(tag, vaddr, size); 9803 bus_dmamem_free(tag, seg, nseg); 9804 } 9805
Indexes created Tue Sep 30 17:09:57 GMT 2025