aic7xxx.c revision 1.1
1 /* $NetBSD: aic7xxx.c,v 1.1 1995/10/09 09:49:30 mycroft Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Copyright (c) 1994, 1995 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Product specific probe and attach routines can be found in: 9 * i386/isa/aic7770.c 27/284X and aic7770 motherboard controllers 10 * /pci/aic7870.c 294x and aic7870 motherboard controllers 11 * 12 * Portions of this driver are based on the FreeBSD 1742 Driver: 13 * 14 * Written by Julian Elischer (julian (at) tfs.com) 15 * for TRW Financial Systems for use under the MACH(2.5) operating system. 16 * 17 * TRW Financial Systems, in accordance with their agreement with Carnegie 18 * Mellon University, makes this software available to CMU to distribute 19 * or use in any manner that they see fit as long as this message is kept with 20 * the software. For this reason TFS also grants any other persons or 21 * organisations permission to use or modify this software. 22 * 23 * TFS supplies this software to be publicly redistributed 24 * on the understanding that TFS is not responsible for the correct 25 * functioning of this software in any circumstances. 26 * 27 * commenced: Sun Sep 27 18:14:01 PDT 1992 28 */ 29 /* 30 * TODO: 31 * Add target reset capabilities 32 * Implement Target Mode 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/proc.h> 43 #include <sys/user.h> 44 45 #include <machine/pio.h> 46 47 #include <dev/isa/isareg.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 51 #include <scsi/scsi_all.h> 52 #include <scsi/scsi_debug.h> 53 #include <scsi/scsiconf.h> 54 55 #include <dev/ic/aic7xxxvar.h> 56 57 int ahc_init __P((struct ahc_softc *)); 58 void ahc_loadseq __P((int)); 59 int ahc_scsi_cmd __P((struct scsi_xfer *)); 60 void ahc_timeout __P((void *)); 61 void ahc_done __P((struct ahc_softc *, struct ahc_scb *)); 62 struct ahc_scb *ahc_get_scb __P((struct ahc_softc *, int)); 63 void ahc_free_scb __P((struct ahc_softc *, struct ahc_scb *, int)); 64 void ahc_abort_scb __P((struct ahc_softc *, struct ahc_scb *)); 65 void ahcminphys __P((struct buf *)); 66 int ahc_poll __P((struct ahc_softc *, struct scsi_xfer *, int)); 67 68 /* Different debugging levels */ 69 #define AHC_SHOWMISC 0x0001 70 #define AHC_SHOWCMDS 0x0002 71 #define AHC_SHOWSCBS 0x0004 72 /*#define AHC_DEBUG /**/ 73 int ahc_debug = AHC_SHOWMISC; 74 75 /*#define AHC_MORE_DEBUG /**/ 76 77 #ifdef AHC_MORE_DEBUG 78 #define DEBUGLEVEL -1 79 #define DEBUGTARGET 0x0 80 #endif 81 82 /**** bit definitions for SCSIDEF ****/ 83 #define HSCSIID 0x07 /* our SCSI ID */ 84 #define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 85 86 struct scsi_adapter ahc_switch = { 87 ahc_scsi_cmd, 88 ahcminphys, 89 0, 90 0, 91 }; 92 93 94 /* the below structure is so we have a default dev struct for our link struct */ 95 struct scsi_device ahc_dev = { 96 NULL, /* Use default error handler */ 97 NULL, /* have a queue, served by this */ 98 NULL, /* have no async handler */ 99 NULL, /* Use default 'done' routine */ 100 }; 101 102 103 /* 104 * All of these should be in a separate header file shared by the sequencer 105 * code and the kernel level driver. The only catch is that we would need to 106 * add an additional 0xc00 offset when using them in the kernel driver. The 107 * aic7770 assembler must be modified to allow include files as well. All 108 * page numbers refer to the Adaptec AIC-7770 Data Book available from 109 * Adaptec's Technical Documents Department 1-800-934-2766 110 */ 111 112 /* -------------------- AIC-7770 offset definitions ----------------------- */ 113 114 /* 115 * SCSI Sequence Control (p. 3-11). 116 * Each bit, when set starts a specific SCSI sequence on the bus 117 */ 118 #define SCSISEQ 0xc00ul 119 #define TEMODEO 0x80 120 #define ENSELO 0x40 121 #define ENSELI 0x20 122 #define ENRSELI 0x10 123 #define ENAUTOATNO 0x08 124 #define ENAUTOATNI 0x04 125 #define ENAUTOATNP 0x02 126 #define SCSIRSTO 0x01 127 128 /* 129 * SCSI Transfer Control 1 Register (pp. 3-14,15). 130 * Controls the SCSI module data path. 131 */ 132 #define SXFRCTL1 0xc02ul 133 #define BITBUCKET 0x80 134 #define SWRAPEN 0x40 135 #define ENSPCHK 0x20 136 #define STIMESEL 0x18 137 #define ENSTIMER 0x04 138 #define ACTNEGEN 0x02 139 #define STPWEN 0x01 /* Powered Termination */ 140 141 /* 142 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 143 * Set bits in this register enable the corresponding 144 * interrupt source. 145 */ 146 #define SIMODE1 0xc11ul 147 #define ENSELTIMO 0x80 148 #define ENATNTARG 0x40 149 #define ENSCSIRST 0x20 150 #define ENPHASEMIS 0x10 151 #define ENBUSFREE 0x08 152 #define ENSCSIPERR 0x04 153 #define ENPHASECHG 0x02 154 #define ENREQINIT 0x01 155 156 /* 157 * SCSI Control Signal Read Register (p. 3-15). 158 * Reads the actual state of the SCSI bus pins 159 */ 160 #define SCSISIGI 0xc03ul 161 #define CDI 0x80 162 #define IOI 0x40 163 #define MSGI 0x20 164 #define ATNI 0x10 165 #define SELI 0x08 166 #define BSYI 0x04 167 #define REQI 0x02 168 #define ACKI 0x01 169 170 /* 171 * SCSI Contol Signal Write Register (p. 3-16). 172 * Writing to this register modifies the control signals on the bus. Only 173 * those signals that are allowed in the current mode (Initiator/Target) are 174 * asserted. 175 */ 176 #define SCSISIGO 0xc03ul 177 #define CDO 0x80 178 #define IOO 0x40 179 #define MSGO 0x20 180 #define ATNO 0x10 181 #define SELO 0x08 182 #define BSYO 0x04 183 #define REQO 0x02 184 #define ACKO 0x01 185 186 /* XXX document this thing */ 187 #define SCSIRATE 0xc04ul 188 189 /* 190 * SCSI ID (p. 3-18). 191 * Contains the ID of the board and the current target on the 192 * selected channel 193 */ 194 #define SCSIID 0xc05ul 195 #define TID 0xf0 /* Target ID mask */ 196 #define OID 0x0f /* Our ID mask */ 197 198 /* 199 * SCSI Status 0 (p. 3-21) 200 * Contains one set of SCSI Interrupt codes 201 * These are most likely of interest to the sequencer 202 */ 203 #define SSTAT0 0xc0bul 204 #define TARGET 0x80 /* Board is a target */ 205 #define SELDO 0x40 /* Selection Done */ 206 #define SELDI 0x20 /* Board has been selected */ 207 #define SELINGO 0x10 /* Selection In Progress */ 208 #define SWRAP 0x08 /* 24bit counter wrap */ 209 #define SDONE 0x04 /* STCNT = 0x000000 */ 210 #define SPIORDY 0x02 /* SCSI PIO Ready */ 211 #define DMADONE 0x01 /* DMA transfer completed */ 212 213 /* 214 * Clear SCSI Interrupt 1 (p. 3-23) 215 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 216 */ 217 #define CLRSINT1 0xc0cul 218 #define CLRSELTIMEO 0x80 219 #define CLRATNO 0x40 220 #define CLRSCSIRSTI 0x20 221 /* UNUSED 0x10 */ 222 #define CLRBUSFREE 0x08 223 #define CLRSCSIPERR 0x04 224 #define CLRPHASECHG 0x02 225 #define CLRREQINIT 0x01 226 227 /* 228 * SCSI Status 1 (p. 3-24) 229 * These interrupt bits are of interest to the kernel driver 230 */ 231 #define SSTAT1 0xc0cul 232 #define SELTO 0x80 233 #define ATNTARG 0x40 234 #define SCSIRSTI 0x20 235 #define PHASEMIS 0x10 236 #define BUSFREE 0x08 237 #define SCSIPERR 0x04 238 #define PHASECHG 0x02 239 #define REQINIT 0x01 240 241 /* 242 * Selection/Reselection ID (p. 3-31) 243 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 244 * device did not set its own ID. 245 */ 246 #define SELID 0xc19ul 247 #define SELID_MASK 0xf0 248 #define ONEBIT 0x08 249 /* UNUSED 0x07 */ 250 251 /* 252 * SCSI Block Control (p. 3-32) 253 * Controls Bus type and channel selection. In a twin channel configuration 254 * addresses 0x00-0x1e are gated to the appropriate channel based on this 255 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 256 * on a wide bus. 257 */ 258 #define SBLKCTL 0xc1ful 259 /* UNUSED 0xc0 */ 260 #define AUTOFLUSHDIS 0x20 261 /* UNUSED 0x10 */ 262 #define SELBUSB 0x08 263 /* UNUSED 0x04 */ 264 #define SELWIDE 0x02 265 /* UNUSED 0x01 */ 266 267 /* 268 * Sequencer Control (p. 3-33) 269 * Error detection mode and speed configuration 270 */ 271 #define SEQCTL 0xc60ul 272 #define PERRORDIS 0x80 273 #define PAUSEDIS 0x40 274 #define FAILDIS 0x20 275 #define FASTMODE 0x10 276 #define BRKADRINTEN 0x08 277 #define STEP 0x04 278 #define SEQRESET 0x02 279 #define LOADRAM 0x01 280 281 /* 282 * Sequencer RAM Data (p. 3-34) 283 * Single byte window into the Scratch Ram area starting at the address 284 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 285 * four bytes in sucessesion. The SEQADDRs will increment after the most 286 * significant byte is written 287 */ 288 #define SEQRAM 0xc61ul 289 290 /* 291 * Sequencer Address Registers (p. 3-35) 292 * Only the first bit of SEQADDR1 holds addressing information 293 */ 294 #define SEQADDR0 0xc62ul 295 #define SEQADDR1 0xc63ul 296 #define SEQADDR1_MASK 0x01 297 298 /* 299 * Accumulator 300 * We cheat by passing arguments in the Accumulator up to the kernel driver 301 */ 302 #define ACCUM 0xc64ul 303 304 #define SINDEX 0xc65ul 305 306 /* 307 * Board Control (p. 3-43) 308 */ 309 #define BCTL 0xc84ul 310 /* RSVD 0xf0 */ 311 #define ACE 0x08 /* Support for external processors */ 312 /* RSVD 0x06 */ 313 #define ENABLE 0x01 314 315 /* 316 * Host Control (p. 3-47) R/W 317 * Overal host control of the device. 318 */ 319 #define HCNTRL 0xc87ul 320 /* UNUSED 0x80 */ 321 #define POWRDN 0x40 322 /* UNUSED 0x20 */ 323 #define SWINT 0x10 324 #define IRQMS 0x08 325 #define PAUSE 0x04 326 #define INTEN 0x02 327 #define CHIPRST 0x01 328 329 /* 330 * SCB Pointer (p. 3-49) 331 * Gate one of the four SCBs into the SCBARRAY window. 332 */ 333 #define SCBPTR 0xc90ul 334 335 /* 336 * Interrupt Status (p. 3-50) 337 * Status for system interrupts 338 */ 339 #define INTSTAT 0xc91ul 340 #define SEQINT_MASK 0xf0 /* SEQINT Status Codes */ 341 #define BAD_PHASE 0x00 342 #define SEND_REJECT 0x10 343 #define NO_IDENT 0x20 344 #define NO_MATCH 0x30 345 #define MSG_SDTR 0x40 346 #define MSG_WDTR 0x50 347 #define MSG_REJECT 0x60 348 #define BAD_STATUS 0x70 349 #define RESIDUAL 0x80 350 #define ABORT_TAG 0x90 351 #define BRKADRINT 0x08 352 #define SCSIINT 0x04 353 #define CMDCMPLT 0x02 354 #define SEQINT 0x01 355 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 356 357 /* 358 * Hard Error (p. 3-53) 359 * Reporting of catastrophic errors. You usually cannot recover from 360 * these without a full board reset. 361 */ 362 #define ERROR 0xc92ul 363 /* UNUSED 0xf0 */ 364 #define PARERR 0x08 365 #define ILLOPCODE 0x04 366 #define ILLSADDR 0x02 367 #define ILLHADDR 0x01 368 369 /* 370 * Clear Interrupt Status (p. 3-52) 371 */ 372 #define CLRINT 0xc92ul 373 #define CLRBRKADRINT 0x08 374 #define CLRSCSIINT 0x04 375 #define CLRCMDINT 0x02 376 #define CLRSEQINT 0x01 377 378 /* 379 * SCB Auto Increment (p. 3-59) 380 * Byte offset into the SCB Array and an optional bit to allow auto 381 * incrementing of the address during download and upload operations 382 */ 383 #define SCBCNT 0xc9aul 384 #define SCBAUTO 0x80 385 #define SCBCNT_MASK 0x1f 386 387 /* 388 * Queue In FIFO (p. 3-60) 389 * Input queue for queued SCBs (commands that the seqencer has yet to start) 390 */ 391 #define QINFIFO 0xc9bul 392 393 /* 394 * Queue In Count (p. 3-60) 395 * Number of queued SCBs 396 */ 397 #define QINCNT 0xc9cul 398 399 /* 400 * Queue Out FIFO (p. 3-61) 401 * Queue of SCBs that have completed and await the host 402 */ 403 #define QOUTFIFO 0xc9dul 404 405 /* 406 * Queue Out Count (p. 3-61) 407 * Number of queued SCBs in the Out FIFO 408 */ 409 #define QOUTCNT 0xc9eul 410 411 #define SCBARRAY 0xca0ul 412 413 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 414 415 /* --------------------- AIC-7870-only definitions -------------------- */ 416 417 #define DSPCISTATUS 0xc86ul 418 419 /* ---------------------- Scratch RAM Offsets ------------------------- */ 420 /* These offsets are either to values that are initialized by the board's 421 * BIOS or are specified by the Linux sequencer code. If I can figure out 422 * how to read the EISA configuration info at probe time, the cards could 423 * be run without BIOS support installed 424 */ 425 426 /* 427 * 1 byte per target starting at this address for configuration values 428 */ 429 #define HA_TARG_SCRATCH 0xc20ul 430 431 /* 432 * The sequencer will stick the frist byte of any rejected message here so 433 * we can see what is getting thrown away. 434 */ 435 #define HA_REJBYTE 0xc31ul 436 437 /* 438 * Length of pending message 439 */ 440 #define HA_MSG_LEN 0xc34ul 441 442 /* 443 * message body 444 */ 445 #define HA_MSG_START 0xc35ul /* outgoing message body */ 446 447 /* 448 * These are offsets into the card's scratch ram. Some of the values are 449 * specified in the AHA2742 technical reference manual and are initialized 450 * by the BIOS at boot time. 451 */ 452 #define HA_ARG_1 0xc4aul 453 #define HA_RETURN_1 0xc4aul 454 #define SEND_SENSE 0x80 455 #define SEND_WDTR 0x80 456 #define SEND_SDTR 0x80 457 #define SEND_REJ 0x40 458 459 #define HA_SIGSTATE 0xc4bul 460 461 #define HA_SCBCOUNT 0xc52ul 462 #define HA_FLAGS 0xc53ul 463 #define SINGLE_BUS 0x00 464 #define TWIN_BUS 0x01 465 #define WIDE_BUS 0x02 466 #define ACTIVE_MSG 0x20 467 #define IDENTIFY_SEEN 0x40 468 #define RESELECTING 0x80 469 470 #define HA_ACTIVE0 0xc54ul 471 #define HA_ACTIVE1 0xc55ul 472 #define SAVED_TCL 0xc56ul 473 #define WAITING_SCBH 0xc57ul 474 #define WAITING_SCBT 0xc58ul 475 476 #define HA_SCSICONF 0xc5aul 477 #define INTDEF 0xc5cul 478 #define HA_HOSTCONF 0xc5dul 479 480 #define MSG_ABORT 0x06 481 #define BUS_8_BIT 0x00 482 #define BUS_16_BIT 0x01 483 #define BUS_32_BIT 0x02 484 485 /* 486 * Since the sequencer can disable pausing in a critical section, we 487 * must loop until it actually stops. 488 * XXX Should add a timeout in here?? 489 */ 490 #define PAUSE_SEQUENCER(ahc) \ 491 do { \ 492 outb(HCNTRL + ahc->sc_iobase, ahc->pause); \ 493 while ((inb(HCNTRL + ahc->sc_iobase) & PAUSE) == 0) \ 494 ; \ 495 } while (0) 496 497 #define UNPAUSE_SEQUENCER(ahc) \ 498 do { \ 499 outb(HCNTRL + ahc->sc_iobase, ahc->unpause); \ 500 } while (0) 501 502 /* 503 * Restart the sequencer program from address zero 504 * XXX Should add a timeout in here?? 505 */ 506 #define RESET_SEQUENCER(ahc) \ 507 do { \ 508 do { \ 509 outb(SEQCTL + ahc->sc_iobase, SEQRESET|FASTMODE); \ 510 } while (inb(SEQADDR0 + ahc->sc_iobase) != 0 && \ 511 inb(SEQADDR1 + ahc->sc_iobase) != 0); \ 512 } while (0) 513 514 #define RESTART_SEQUENCER(ahc) \ 515 do { \ 516 RESET_SEQUENCER(ahc); \ 517 UNPAUSE_SEQUENCER(ahc); \ 518 } while (0) 519 520 #ifdef AHC_DEBUG 521 void 522 ahc_print_scb(scb) 523 struct ahc_scb *scb; 524 { 525 526 printf("scb:0x%x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n", 527 scb, 528 scb->control, 529 scb->target_channel_lun, 530 scb->cmdlen, 531 scb->cmdpointer); 532 printf("\tdatlen:%d data:0x%x res:0x%x segs:0x%x segp:0x%x\n", 533 scb->datalen[2] << 16 | scb->datalen[1] << 8 | scb->datalen[0], 534 scb->data, 535 scb->RESERVED[1] << 8 | scb->RESERVED[0], 536 scb->SG_segment_count, 537 scb->SG_list_pointer); 538 printf("\tsg_addr:%x sg_len:%d\n", 539 scb->ahc_dma[0].addr, 540 scb->ahc_dma[0].len); 541 printf(" size:%d\n", 542 (int)&scb->next - (int)scb); 543 } 544 545 void 546 ahc_print_active_scb(ahc) 547 struct ahc_softc *ahc; 548 { 549 int iobase = ahc->sc_iobase; 550 int scb_index; 551 552 PAUSE_SEQUENCER(ahc); 553 scb_index = inb(SCBPTR + iobase); 554 UNPAUSE_SEQUENCER(ahc); 555 556 ahc_print_scb(ahc->scbarray[scb_index]); 557 } 558 #endif 559 560 #define PARERR 0x08 561 #define ILLOPCODE 0x04 562 #define ILLSADDR 0x02 563 #define ILLHADDR 0x01 564 565 static struct { 566 u_char errno; 567 char *errmesg; 568 } hard_error[] = { 569 { ILLHADDR, "Illegal Host Access" }, 570 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 571 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 572 { PARERR, "Sequencer Ram Parity Error" } 573 }; 574 575 576 /* 577 * Valid SCSIRATE values. (p. 3-17) 578 * Provides a mapping of tranfer periods in ns to the proper value to 579 * stick in the scsiscfr reg to use that transfer rate. 580 */ 581 static struct { 582 u_char sxfr; 583 int period; /* in ns */ 584 char *rate; 585 } ahc_syncrates[] = { 586 { 0x00, 100, "10.0" }, 587 { 0x10, 125, "8.0" }, 588 { 0x20, 150, "6.67" }, 589 { 0x30, 175, "5.7" }, 590 { 0x40, 200, "5.0" }, 591 { 0x50, 225, "4.4" }, 592 { 0x60, 250, "4.0" }, 593 { 0x70, 275, "3.6" } 594 }; 595 596 static int ahc_num_syncrates = 597 sizeof(ahc_syncrates) / sizeof(ahc_syncrates[0]); 598 599 /* 600 * Check if the device can be found at the port given 601 * and if so, determine configuration and set it up for further work. 602 */ 603 604 int 605 ahcprobe(ahc, iobase) 606 struct ahc_softc *ahc; 607 int iobase; 608 { 609 610 ahc->sc_iobase = iobase; 611 612 /* 613 * Try to initialize a unit at this location 614 * reset the AIC-7770, read its registers, 615 * and fill in the dev structure accordingly 616 */ 617 618 if (ahc_init(ahc) != 0) 619 return (0); 620 621 return (1); 622 } 623 624 625 /* 626 * Look up the valid period to SCSIRATE conversion in our table. 627 */ 628 static u_char 629 ahc_scsirate(offset, period, ahc, target) 630 u_char offset; 631 int period; 632 struct ahc_softc *ahc; 633 int target; 634 { 635 u_char scsirate; 636 int i; 637 638 for (i = 0; i < ahc_num_syncrates; i++) { 639 if ((ahc_syncrates[i].period - period) >= 0) { 640 printf("%s: target %d synchronous at %sMB/s, " 641 "offset = %d\n", 642 ahc->sc_dev.dv_xname, target, 643 ahc_syncrates[i].rate, offset); 644 #ifdef AHC_DEBUG 645 #endif /* AHC_DEBUG */ 646 return ((ahc_syncrates[i].sxfr) | (offset & 0x0f)); 647 } 648 } 649 650 /* Default to asyncronous transfers. Also reject this SDTR request. */ 651 printf("%s: target %d using asyncronous transfers\n", 652 ahc->sc_dev.dv_xname, target); 653 return (0); 654 #ifdef AHC_DEBUG 655 #endif /* AHC_DEBUG */ 656 } 657 658 ahcprint() 659 { 660 661 } 662 663 /* 664 * Attach all the sub-devices we can find 665 */ 666 int 667 ahcattach(ahc) 668 struct ahc_softc *ahc; 669 { 670 671 TAILQ_INIT(&ahc->free_scb); 672 673 /* 674 * fill in the prototype scsi_link. 675 */ 676 ahc->sc_link.adapter_softc = ahc; 677 ahc->sc_link.adapter_target = ahc->ahc_scsi_dev; 678 ahc->sc_link.adapter = &ahc_switch; 679 ahc->sc_link.device = &ahc_dev; 680 ahc->sc_link.openings = 1; 681 ahc->sc_link.flags = DEBUGLEVEL; 682 ahc->sc_link.quirks = 0; 683 684 /* 685 * ask the adapter what subunits are present 686 */ 687 printf("%s: Probing channel A\n", ahc->sc_dev.dv_xname); 688 config_found((void *)ahc, &ahc->sc_link, ahcprint); 689 if (ahc->type & AHC_TWIN) { 690 /* Configure the second scsi bus */ 691 ahc->sc_link_b = ahc->sc_link; 692 /* XXXX Didn't do this before. */ 693 ahc->sc_link_b.adapter_target = ahc->ahc_scsi_dev_b; 694 ahc->sc_link_b.quirks = 0x0008; /**/ 695 printf("%s: Probing channel B\n", ahc->sc_dev.dv_xname); 696 config_found((void *)ahc, &ahc->sc_link_b, ahcprint); 697 } 698 699 return 1; 700 } 701 702 void 703 ahc_send_scb(ahc, scb) 704 struct ahc_softc *ahc; 705 struct ahc_scb *scb; 706 { 707 int iobase = ahc->sc_iobase; 708 709 PAUSE_SEQUENCER(ahc); 710 outb(QINFIFO + iobase, scb->position); 711 UNPAUSE_SEQUENCER(ahc); 712 } 713 714 static void 715 ahc_getscb(iobase, scb) 716 int iobase; 717 struct ahc_scb *scb; 718 { 719 720 outb(SCBCNT + iobase, SCBAUTO); 721 insb(SCBARRAY + iobase, scb, SCB_UP_SIZE); 722 outb(SCBCNT + iobase, 0); 723 } 724 725 /* 726 * Catch an interrupt from the adaptor 727 */ 728 int 729 ahcintr(ahc) 730 struct ahc_softc *ahc; 731 { 732 int iobase = ahc->sc_iobase; 733 u_char intstat = inb(INTSTAT + iobase); 734 u_char status; 735 struct ahc_scb *scb = NULL; 736 struct scsi_xfer *xs = NULL; 737 738 /* 739 * Is this interrupt for me? or for 740 * someone who is sharing my interrupt 741 */ 742 if ((intstat & INT_PEND) == 0) 743 return 0; 744 745 if (intstat & BRKADRINT) { 746 /* We upset the sequencer :-( */ 747 748 /* Lookup the error message */ 749 int i, error = inb(ERROR + iobase); 750 int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 751 for (i = 0; error != 1 && i < num_errors; i++) 752 error >>= 1; 753 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 754 ahc->sc_dev.dv_xname, hard_error[i].errmesg, 755 (inb(SEQADDR1 + iobase) << 8) | 756 (inb(SEQADDR0 + iobase) << 0)); 757 } 758 759 if (intstat & SEQINT) { 760 switch (intstat & SEQINT_MASK) { 761 case BAD_PHASE: 762 panic("%s: unknown scsi bus phase. " 763 "Attempting to continue\n", 764 ahc->sc_dev.dv_xname); 765 break; 766 case SEND_REJECT: 767 printf("%s: Warning - " 768 "message reject, message type: 0x%x\n", 769 ahc->sc_dev.dv_xname, 770 inb(HA_REJBYTE + iobase)); 771 break; 772 case NO_IDENT: 773 panic("%s: No IDENTIFY message from reconnecting " 774 "target %d at seqaddr = 0x%lx " 775 "SAVED_TCL == 0x%x\n", 776 ahc->sc_dev.dv_xname, 777 (inb(SELID + iobase) >> 4) & 0xf, 778 (inb(SEQADDR1 + iobase) << 8) | 779 (inb(SEQADDR0 + iobase) << 0), 780 inb(SAVED_TCL + iobase)); 781 break; 782 case NO_MATCH: { 783 u_char active; 784 int active_port = HA_ACTIVE0 + iobase; 785 int tcl = inb(SCBARRAY+1 + iobase); 786 int target = (tcl >> 4) & 0x0f; 787 printf("%s: no active SCB for reconnecting " 788 "target %d, channel %c - issuing ABORT\n", 789 ahc->sc_dev.dv_xname, 790 target, tcl & 0x08 ? 'B' : 'A'); 791 printf("SAVED_TCL == 0x%x\n", inb(SAVED_TCL + iobase)); 792 if (tcl & 0x88) { 793 /* Second channel stores its info 794 * in byte two of HA_ACTIVE 795 */ 796 active_port++; 797 } 798 active = inb(active_port); 799 active &= ~(0x01 << (target & 0x07)); 800 outb(SCBARRAY + iobase, SCB_NEEDDMA); 801 outb(active_port, active); 802 outb(CLRSINT1 + iobase, CLRSELTIMEO); 803 RESTART_SEQUENCER(ahc); 804 break; 805 } 806 case MSG_SDTR: { 807 u_char scsi_id = 808 (inb(SCSIID + iobase) >> 0x4) | 809 (inb(SBLKCTL + iobase) & 0x08); 810 u_char scratch, offset; 811 int period; 812 813 /* 814 * Help the sequencer to translate the 815 * negotiated transfer rate. Transfer is 816 * 1/4 the period in ns as is returned by 817 * the sync negotiation message. So, we must 818 * multiply by four 819 */ 820 period = inb(HA_ARG_1 + iobase) << 2; 821 /* The bottom half of SCSIXFER */ 822 offset = inb(ACCUM + iobase); 823 824 printf("%s: SDTR, target %d period %d offset %d\n", 825 ahc->sc_dev.dv_xname, scsi_id, period, offset); 826 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 827 scratch &= 0x80; 828 scratch |= ahc_scsirate(offset, period, ahc, scsi_id); 829 830 if ((scratch & 0x7f) == 0) { 831 /* 832 * The requested rate was so low 833 * that asyncronous transfers are 834 * faster (not to mention the 835 * controller won't support them), 836 * so we issue a message reject to 837 * ensure we go to asyncronous 838 * transfers. 839 */ 840 outb(HA_RETURN_1 + iobase, SEND_REJ); 841 } else if (ahc->sdtrpending & (0x01 << scsi_id)) { 842 /* 843 * Don't send an SDTR back to the 844 * target, since we asked first. 845 */ 846 outb(HA_RETURN_1 + iobase, 0); 847 } else { 848 /* 849 * Send our own SDTR in reply 850 */ 851 #ifdef AHC_DEBUG 852 if (ahc_debug & AHC_SHOWMISC) 853 printf("Sending SDTR!!\n"); 854 #endif 855 outb(HA_RETURN_1 + iobase, SEND_SDTR); 856 } 857 /* 858 * Negate the flags 859 */ 860 ahc->needsdtr &= ~(0x01 << scsi_id); 861 ahc->sdtrpending &= ~(0x01 << scsi_id); 862 863 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 864 outb(SCSIRATE + iobase, scratch); 865 break; 866 } 867 case MSG_WDTR: { 868 u_char scsi_id = 869 (inb(SCSIID + iobase) >> 0x4) | 870 (inb(SBLKCTL + iobase) & 0x08); 871 u_char scratch, width; 872 873 width = inb(ACCUM + iobase); 874 875 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 876 877 if (ahc->wdtrpending & (0x01 << scsi_id)) { 878 /* 879 * Don't send a WDTR back to the 880 * target, since we asked first. 881 */ 882 outb(HA_RETURN_1 + iobase, 0); 883 switch (width) { 884 case BUS_8_BIT: 885 scratch &= 0x7f; 886 break; 887 case BUS_16_BIT: 888 printf("%s: target %d using 16Bit " 889 "transfers\n", 890 ahc->sc_dev.dv_xname, scsi_id); 891 scratch &= 0xf8; 892 scratch |= 0x88; 893 break; 894 case BUS_32_BIT: 895 /* XXXX */ 896 } 897 } else { 898 /* 899 * Send our own WDTR in reply 900 */ 901 switch (width) { 902 case BUS_8_BIT: 903 scratch &= 0x7f; 904 break; 905 case BUS_32_BIT: 906 /* Negotiate 16_BITS */ 907 width = BUS_16_BIT; 908 case BUS_16_BIT: 909 printf("%s: target %d using 16Bit " 910 "transfers\n", 911 ahc->sc_dev.dv_xname, scsi_id); 912 scratch &= 0xf8; 913 scratch |= 0x88; 914 break; 915 } 916 outb(HA_RETURN_1 + iobase, 917 width | SEND_WDTR); 918 } 919 ahc->needwdtr &= ~(0x01 << scsi_id); 920 ahc->wdtrpending &= ~(0x01 << scsi_id); 921 922 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 923 outb(SCSIRATE + iobase, scratch); 924 break; 925 } 926 case MSG_REJECT: { 927 /* 928 * What we care about here is if we had an 929 * outstanding SDTR or WDTR message for this 930 * target. If we did, this is a signal that 931 * the target is refusing negotiation. 932 */ 933 934 u_char scsi_id = 935 (inb(SCSIID + iobase) >> 0x4) | 936 (inb(SBLKCTL + iobase) & 0x08); 937 u_char scratch; 938 u_short mask; 939 940 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 941 942 mask = (0x01 << scsi_id); 943 if (ahc->wdtrpending & mask) { 944 /* note 8bit xfers and clear flag */ 945 scratch &= 0x7f; 946 ahc->needwdtr &= ~mask; 947 ahc->wdtrpending &= ~mask; 948 printf("%s: target %d refusing " 949 "WIDE negotiation. Using " 950 "8bit transfers\n", 951 ahc->sc_dev.dv_xname, scsi_id); 952 } else if (ahc->sdtrpending & mask) { 953 /* note asynch xfers and clear flag */ 954 scratch &= 0xf0; 955 ahc->needsdtr &= ~mask; 956 ahc->sdtrpending &= ~mask; 957 printf("%s: target %d refusing " 958 "syncronous negotiation; using " 959 "asyncronous transfers\n", 960 ahc->sc_dev.dv_xname, scsi_id); 961 } else { 962 /* 963 * Otherwise, we ignore it. 964 */ 965 #ifdef AHC_DEBUG 966 if (ahc_debug & AHC_SHOWMISC) 967 printf("Message reject -- ignored\n"); 968 #endif 969 break; 970 } 971 972 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 973 outb(SCSIRATE + iobase, scratch); 974 break; 975 } 976 case BAD_STATUS: { 977 int scb_index = inb(SCBPTR + iobase); 978 scb = ahc->scbarray[scb_index]; 979 980 /* 981 * The sequencer will notify us when a command 982 * has an error that would be of interest to 983 * the kernel. This allows us to leave the sequencer 984 * running in the common case of command completes 985 * without error. 986 */ 987 988 /* 989 * Set the default return value to 0 (don't 990 * send sense). The sense code with change 991 * this if needed and this reduces code 992 * duplication. 993 */ 994 outb(HA_RETURN_1 + iobase, 0); 995 if (!scb || scb->flags == SCB_FREE) { 996 printf("%s: ahcintr: referenced scb not " 997 "valid during seqint 0x%x scb(%d)\n", 998 ahc->sc_dev.dv_xname, intstat, scb_index); 999 goto clear; 1000 } 1001 1002 xs = scb->xs; 1003 1004 ahc_getscb(iobase, scb); 1005 1006 #ifdef AHC_DEBUG 1007 if (xs->sc_link->target == DEBUGTARGET) 1008 ahc_print_scb(scb); 1009 #endif 1010 xs->status = scb->target_status; 1011 switch (scb->target_status) { 1012 case SCSI_OK: 1013 printf("%s: Interrupted for status of 0???\n", 1014 ahc->sc_dev.dv_xname); 1015 break; 1016 case SCSI_CHECK: 1017 #ifdef AHC_DEBUG 1018 sc_print_addr(xs->sc_link); 1019 printf("requests Check Status\n"); 1020 #endif 1021 1022 if (xs->error == XS_NOERROR && 1023 scb->flags != SCB_CHKSENSE) { 1024 u_char flags; 1025 u_char head; 1026 u_char tail; 1027 struct ahc_dma_seg *sg = scb->ahc_dma; 1028 struct scsi_sense *sc = &(scb->sense_cmd); 1029 u_char control = scb->control; 1030 u_char tcl = scb->target_channel_lun; 1031 #ifdef AHC_DEBUG 1032 sc_print_addr(xs->sc_link); 1033 printf("Sending Sense\n"); 1034 #endif 1035 bzero(scb, SCB_DOWN_SIZE); 1036 scb->flags = SCB_CHKSENSE; 1037 scb->control = (control & SCB_TE); 1038 sc->opcode = REQUEST_SENSE; 1039 sc->byte2 = xs->sc_link->lun << 5; 1040 sc->length = sizeof(struct scsi_sense_data); 1041 sc->control = 0; 1042 1043 sg->seg_addr = vtophys(&xs->sense); 1044 sg->seg_len = sizeof(struct scsi_sense_data); 1045 1046 scb->target_channel_lun = tcl; 1047 scb->SG_segment_count = 1; 1048 scb->SG_list_pointer = vtophys(sg); 1049 scb->cmdpointer = vtophys(sc); 1050 scb->cmdlen = sizeof(*sc); 1051 1052 outb(SCBCNT + iobase, SCBAUTO); 1053 outsb(SCBARRAY + iobase, scb, 1054 SCB_DOWN_SIZE); 1055 outb(SCBCNT + iobase, 0); 1056 outb(SCBARRAY + iobase + 30, 1057 SCB_LIST_NULL); 1058 1059 /* 1060 * Add this SCB to the "waiting for 1061 * selection" list. 1062 */ 1063 head = inb(WAITING_SCBH + iobase); 1064 tail = inb(WAITING_SCBT + iobase); 1065 if (head & SCB_LIST_NULL) { 1066 /* List was empty */ 1067 head = scb->position; 1068 tail = SCB_LIST_NULL; 1069 } else if (tail & SCB_LIST_NULL) { 1070 /* List had one element */ 1071 tail = scb->position; 1072 outb(SCBPTR + iobase, head); 1073 outb(SCBARRAY + iobase + 30, 1074 tail); 1075 } else { 1076 outb(SCBPTR + iobase, tail); 1077 tail = scb->position; 1078 outb(SCBARRAY + iobase + 30, 1079 tail); 1080 } 1081 outb(WAITING_SCBH + iobase, head); 1082 outb(WAITING_SCBT + iobase, tail); 1083 outb(HA_RETURN_1 + iobase, SEND_SENSE); 1084 break; 1085 } 1086 /* 1087 * Have the sequencer do a normal command 1088 * complete with either a "DRIVER_STUFFUP" 1089 * error or whatever other error condition 1090 * we already had. 1091 */ 1092 if (xs->error == XS_NOERROR) 1093 xs->error = XS_DRIVER_STUFFUP; 1094 break; 1095 case SCSI_BUSY: 1096 sc_print_addr(xs->sc_link); 1097 printf("Target Busy\n"); 1098 xs->error = XS_BUSY; 1099 break; 1100 #if 0 1101 case SCSI_QUEUE_FULL: 1102 /* 1103 * The upper level SCSI code will eventually 1104 * handle this properly. 1105 */ 1106 sc_print_addr(xs->sc_link); 1107 printf("Queue Full\n"); 1108 xs->error = XS_BUSY; 1109 break; 1110 #endif 1111 default: 1112 sc_print_addr(xs->sc_link); 1113 printf("unexpected targ_status: %x\n", 1114 scb->target_status); 1115 xs->error = XS_DRIVER_STUFFUP; 1116 break; 1117 } 1118 break; 1119 } 1120 case RESIDUAL: { 1121 int scb_index = inb(SCBPTR + iobase); 1122 scb = ahc->scbarray[scb_index]; 1123 1124 /* 1125 * Don't clobber valid resid info with 1126 * a resid coming from a check sense 1127 * operation. 1128 */ 1129 if (scb->flags != SCB_CHKSENSE) 1130 scb->xs->resid = 1131 (inb(iobase + SCBARRAY + 17) << 16) | 1132 (inb(iobase + SCBARRAY + 16) << 8) | 1133 (inb(iobase + SCBARRAY + 15) << 0); 1134 #ifdef AHC_MORE_DEBUG 1135 printf("ahc: Handled Residual\n"); 1136 #endif 1137 break; 1138 } 1139 case ABORT_TAG: { 1140 int scb_index = inb(SCBPTR + iobase); 1141 scb = ahc->scbarray[scb_index]; 1142 1143 /* 1144 * We didn't recieve a valid tag back from 1145 * the target on a reconnect. 1146 */ 1147 sc_print_addr(xs->sc_link); 1148 printf("invalid tag recieved on channel %c " 1149 "-- sending ABORT_TAG\n", 1150 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1151 scb->xs->error = XS_DRIVER_STUFFUP; 1152 untimeout(ahc_timeout, scb); 1153 ahc_done(ahc, scb); 1154 break; 1155 } 1156 default: 1157 printf("%s: seqint, intstat == 0x%x, scsisigi = 0x%x\n", 1158 ahc->sc_dev.dv_xname, 1159 intstat, inb(SCSISIGI + iobase)); 1160 break; 1161 } 1162 1163 clear: 1164 /* 1165 * Clear the upper byte that holds SEQINT status 1166 * codes and clear the SEQINT bit. 1167 */ 1168 outb(CLRINT + iobase, CLRSEQINT); 1169 1170 /* 1171 * The sequencer is paused immediately on 1172 * a SEQINT, so we should restart it when 1173 * we leave this section. 1174 */ 1175 UNPAUSE_SEQUENCER(ahc); 1176 } 1177 1178 if (intstat & SCSIINT) { 1179 int scb_index = inb(SCBPTR + iobase); 1180 scb = ahc->scbarray[scb_index]; 1181 1182 status = inb(SSTAT1 + iobase); 1183 1184 if (!scb || scb->flags == SCB_FREE) { 1185 printf("%s: ahcintr - referenced scb not " 1186 "valid during scsiint 0x%x scb(%d)\n", 1187 ahc->sc_dev.dv_xname, status, scb_index); 1188 outb(CLRSINT1 + iobase, status); 1189 UNPAUSE_SEQUENCER(ahc); 1190 outb(CLRINT + iobase, CLRSCSIINT); 1191 scb = NULL; 1192 goto cmdcomplete; 1193 } 1194 xs = scb->xs; 1195 1196 #ifdef AHC_MORE_DEBUG 1197 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) 1198 printf("Intr status %x\n", status); 1199 #endif 1200 1201 if (status & SELTO) { 1202 u_char active; 1203 u_char waiting; 1204 u_char flags; 1205 int active_port = HA_ACTIVE0 + iobase; 1206 1207 outb(SCSISEQ + iobase, ENRSELI); 1208 xs->error = XS_SELTIMEOUT; 1209 /* 1210 * Clear any pending messages for the timed out 1211 * target, and mark the target as free 1212 */ 1213 flags = inb(HA_FLAGS + iobase); 1214 outb(HA_FLAGS + iobase, flags & ~ACTIVE_MSG); 1215 1216 if (scb->target_channel_lun & 0x88) 1217 active_port++; 1218 1219 active = inb(active_port) & 1220 ~(0x01 << (xs->sc_link->target & 0x07)); 1221 outb(active_port, active); 1222 1223 outb(SCBARRAY + iobase, SCB_NEEDDMA); 1224 1225 outb(CLRSINT1 + iobase, CLRSELTIMEO); 1226 1227 outb(CLRINT + iobase, CLRSCSIINT); 1228 1229 /* Shift the waiting for selection queue forward */ 1230 waiting = inb(WAITING_SCBH + iobase); 1231 outb(SCBPTR + iobase, waiting); 1232 waiting = inb(SCBARRAY + iobase + 30); 1233 outb(WAITING_SCBH + iobase, waiting); 1234 1235 RESTART_SEQUENCER(ahc); 1236 } 1237 1238 if (status & SCSIPERR) { 1239 sc_print_addr(xs->sc_link); 1240 printf("parity error on channel %c\n", 1241 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1242 xs->error = XS_DRIVER_STUFFUP; 1243 1244 outb(CLRSINT1 + iobase, CLRSCSIPERR); 1245 UNPAUSE_SEQUENCER(ahc); 1246 1247 outb(CLRINT + iobase, CLRSCSIINT); 1248 scb = NULL; 1249 } 1250 if (status & BUSFREE) { 1251 #if 0 1252 /* 1253 * Has seen busfree since selection, i.e. 1254 * a "spurious" selection. Shouldn't happen. 1255 */ 1256 printf("ahc: unexpected busfree\n"); 1257 #if 0 1258 xs->error = XS_DRIVER_STUFFUP; 1259 outb(CLRSINT1 + iobase, BUSFREE); /* CLRBUSFREE */ 1260 #endif 1261 #endif 1262 } else { 1263 printf("%s: Unknown SCSIINT. Status = 0x%x\n", 1264 ahc->sc_dev.dv_xname, status); 1265 outb(CLRSINT1 + iobase, status); 1266 UNPAUSE_SEQUENCER(ahc); 1267 outb(CLRINT + iobase, CLRSCSIINT); 1268 scb = NULL; 1269 } 1270 if (scb != NULL) { 1271 /* We want to process the command */ 1272 untimeout(ahc_timeout, scb); 1273 ahc_done(ahc, scb); 1274 } 1275 } 1276 1277 cmdcomplete: 1278 if (intstat & CMDCMPLT) { 1279 int scb_index; 1280 1281 do { 1282 scb_index = inb(QOUTFIFO + iobase); 1283 scb = ahc->scbarray[scb_index]; 1284 1285 if (!scb || scb->flags == SCB_FREE) { 1286 printf("%s: WARNING " 1287 "no command for scb %d (cmdcmplt)\n" 1288 "QOUTCNT == %d\n", 1289 ahc->sc_dev.dv_xname, 1290 scb_index, inb(QOUTCNT + iobase)); 1291 outb(CLRINT + iobase, CLRCMDINT); 1292 continue; 1293 } 1294 1295 /* XXXX Should do this before reading FIFO? */ 1296 outb(CLRINT + iobase, CLRCMDINT); 1297 untimeout(ahc_timeout, scb); 1298 ahc_done(ahc, scb); 1299 } while (inb(QOUTCNT + iobase)); 1300 } 1301 1302 return 1; 1303 } 1304 1305 /* 1306 * We have a scb which has been processed by the 1307 * adaptor, now we look to see how the operation 1308 * went. 1309 */ 1310 void 1311 ahc_done(ahc, scb) 1312 struct ahc_softc *ahc; 1313 struct ahc_scb *scb; 1314 { 1315 struct scsi_xfer *xs = scb->xs; 1316 1317 #ifdef AHC_MORE_DEBUG 1318 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) { 1319 xs->sc_link->flags |= 0xf0; 1320 SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); 1321 printf("%x %x %x %x\n", 1322 scb->flags, 1323 scb->target_status, 1324 xs->flags, 1325 xs->error); 1326 } 1327 #endif 1328 1329 /* 1330 * Put the results of the operation 1331 * into the xfer and call whoever started it 1332 */ 1333 if (xs->error == XS_NOERROR) { 1334 if (scb->flags == SCB_ABORTED) 1335 xs->error = XS_DRIVER_STUFFUP; 1336 else if (scb->flags == SCB_CHKSENSE) 1337 xs->error = XS_SENSE; 1338 } 1339 1340 xs->flags |= ITSDONE; 1341 1342 #ifdef AHC_TAGENABLE 1343 if (xs->cmd->opcode == 0x12 && xs->error == XS_NOERROR) { 1344 struct scsi_inquiry_data *inq_data; 1345 u_short mask = 0x01 << (xs->sc_link->target | 1346 (scb->target_channel_lun & 0x08)); 1347 /* 1348 * Sneak a look at the results of the SCSI Inquiry 1349 * command and see if we can do Tagged queing. XXX This 1350 * should really be done by the higher level drivers. 1351 */ 1352 inq_data = (struct scsi_inquiry_data *)xs->data; 1353 if (((inq_data->device & SID_TYPE) == 0) 1354 && (inq_data->flags & SID_CmdQue) 1355 && !(ahc->tagenable & mask)) { 1356 /* 1357 * Disk type device and can tag 1358 */ 1359 sc_print_addr(xs->sc_link); 1360 printf("Tagged Queuing Device\n"); 1361 ahc->tagenable |= mask; 1362 #ifdef QUEUE_FULL_SUPPORTED 1363 xs->sc_link->openings += 2; */ 1364 #endif 1365 } 1366 } 1367 #endif 1368 1369 ahc_free_scb(ahc, scb, xs->flags); 1370 scsi_done(xs); 1371 } 1372 1373 /* 1374 * Start the board, ready for normal operation 1375 */ 1376 /* XXXX clean */ 1377 int 1378 ahc_init(ahc) 1379 struct ahc_softc *ahc; 1380 { 1381 int iobase = ahc->sc_iobase; 1382 u_char scsi_conf, sblkctl, i; 1383 int intdef, max_targ = 16, wait; 1384 1385 /* 1386 * Assume we have a board at this stage 1387 * Find out the configured interupt and the card type. 1388 */ 1389 1390 #ifdef AHC_DEBUG 1391 printf("%s: scb %d bytes; SCB_SIZE %d bytes, ahc_dma %d bytes\n", 1392 ahc->sc_dev.dv_xname, sizeof(struct ahc_scb), SCB_DOWN_SIZE, 1393 sizeof(struct ahc_dma_seg)); 1394 #endif /* AHC_DEBUG */ 1395 /*printf("%s: reading board settings\n", ahc->sc_dev.dv_xname);/**/ 1396 1397 /* Save the IRQ type before we do a chip reset */ 1398 1399 ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN; 1400 ahc->pause = ahc->unpause | PAUSE; 1401 outb(HCNTRL + iobase, CHIPRST | ahc->pause); 1402 1403 /* 1404 * Ensure that the reset has finished 1405 */ 1406 wait = 1000; 1407 while (wait--) { 1408 delay(1000); 1409 if (!(inb(HCNTRL + iobase) & CHIPRST)) 1410 break; 1411 } 1412 if (wait == 0) { 1413 printf("\n%s: WARNING - Failed chip reset! " 1414 "Trying to initialize anyway.\n", ahc->sc_dev.dv_xname); 1415 /* Forcibly clear CHIPRST */ 1416 outb(HCNTRL + iobase, ahc->pause); 1417 } 1418 1419 switch (ahc->type) { 1420 case AHC_274: 1421 printf(": 274x ", ahc->sc_dev.dv_xname); 1422 ahc->maxscbs = 0x4; 1423 break; 1424 case AHC_284: 1425 printf(": 284x ", ahc->sc_dev.dv_xname); 1426 ahc->maxscbs = 0x4; 1427 break; 1428 case AHC_AIC7870: 1429 case AHC_294: 1430 if (ahc->type == AHC_AIC7870) 1431 printf(": aic7870 ", ahc->sc_dev.dv_xname); 1432 else 1433 printf(": 294x ", ahc->sc_dev.dv_xname); 1434 ahc->maxscbs = 0x10; 1435 #define DFTHRESH 3 1436 outb(DSPCISTATUS + iobase, DFTHRESH << 6); 1437 /* 1438 * XXX Hard coded SCSI ID until we can read it from the 1439 * SEEPROM or NVRAM. 1440 */ 1441 outb(HA_SCSICONF + iobase, 0x07 | (DFTHRESH << 6)); 1442 /* In case we are a wide card */ 1443 outb(HA_SCSICONF + 1 + iobase, 0x07); 1444 break; 1445 } 1446 1447 /* Determine channel configuration and who we are on the scsi bus. */ 1448 switch ((sblkctl = inb(SBLKCTL + iobase) & 0x0f)) { 1449 case 0: 1450 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1451 printf("Single Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1452 outb(HA_FLAGS + iobase, SINGLE_BUS); 1453 break; 1454 case 2: 1455 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + 1 + iobase) & HWSCSIID); 1456 printf("Wide Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1457 ahc->type |= AHC_WIDE; 1458 outb(HA_FLAGS + iobase, WIDE_BUS); 1459 break; 1460 case 8: 1461 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1462 ahc->ahc_scsi_dev_b = (inb(HA_SCSICONF + 1 + iobase) & HSCSIID); 1463 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ", 1464 ahc->ahc_scsi_dev, ahc->ahc_scsi_dev_b); 1465 ahc->type |= AHC_TWIN; 1466 outb(HA_FLAGS + iobase, TWIN_BUS); 1467 break; 1468 default: 1469 printf(" Unsupported adapter type. %x Ignoring\n",sblkctl); 1470 return(-1); 1471 } 1472 1473 /* 1474 * Take the bus led out of diagnostic mode 1475 */ 1476 outb(SBLKCTL + iobase, sblkctl); 1477 1478 /* 1479 * Number of SCBs that will be used. Rev E aic7770s and 1480 * aic7870s have 16. The rest have 4. 1481 */ 1482 if (!(ahc->type & AHC_AIC7870)) { 1483 /* 1484 * See if we have a Rev E or higher 1485 * aic7770. Anything below a Rev E will 1486 * have a R/O autoflush disable configuration 1487 * bit. 1488 */ 1489 u_char sblkctl_orig; 1490 sblkctl_orig = inb(SBLKCTL + iobase); 1491 sblkctl = sblkctl_orig ^ AUTOFLUSHDIS; 1492 outb(SBLKCTL + iobase, sblkctl); 1493 sblkctl = inb(SBLKCTL + iobase); 1494 if (sblkctl != sblkctl_orig) { 1495 printf("aic7770 >= Rev E, "); 1496 /* 1497 * Ensure autoflush is enabled 1498 */ 1499 sblkctl &= ~AUTOFLUSHDIS; 1500 outb(SBLKCTL + iobase, sblkctl); 1501 } else 1502 printf("aic7770 <= Rev C, "); 1503 } else 1504 printf("aic7870, "); 1505 printf("%d SCBs\n", ahc->maxscbs); 1506 1507 if (ahc->pause & IRQMS) 1508 printf("%s: Using Level Sensitive Interrupts\n", 1509 ahc->sc_dev.dv_xname); 1510 else 1511 printf("%s: Using Edge Triggered Interrupts\n", 1512 ahc->sc_dev.dv_xname); 1513 1514 if (!(ahc->type & AHC_AIC7870)) { 1515 /* 1516 * The 294x cards are PCI, so we get their interrupt from the 1517 * PCI BIOS. 1518 */ 1519 1520 intdef = inb(INTDEF + iobase); 1521 switch (intdef & 0xf) { 1522 case 9: 1523 ahc->sc_irq = 9; 1524 break; 1525 case 10: 1526 ahc->sc_irq = 10; 1527 break; 1528 case 11: 1529 ahc->sc_irq = 11; 1530 break; 1531 case 12: 1532 ahc->sc_irq = 12; 1533 break; 1534 case 14: 1535 ahc->sc_irq = 14; 1536 break; 1537 case 15: 1538 ahc->sc_irq = 15; 1539 break; 1540 default: 1541 printf("illegal irq setting\n"); 1542 return (EIO); 1543 } 1544 } 1545 1546 /* Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels */ 1547 if (ahc->type & AHC_TWIN) { 1548 /* 1549 * The device is gated to channel B after a chip reset, 1550 * so set those values first 1551 */ 1552 outb(SCSIID + iobase, ahc->ahc_scsi_dev_b); 1553 scsi_conf = inb(HA_SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL); 1554 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1555 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1556 /* Select Channel A */ 1557 outb(SBLKCTL + iobase, 0); 1558 } 1559 outb(SCSIID + iobase, ahc->ahc_scsi_dev); 1560 scsi_conf = inb(HA_SCSICONF + iobase) & (ENSPCHK|STIMESEL); 1561 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1562 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1563 1564 /* 1565 * Look at the information that board initialization or 1566 * the board bios has left us. In the lower four bits of each 1567 * target's scratch space any value other than 0 indicates 1568 * that we should initiate syncronous transfers. If it's zero, 1569 * the user or the BIOS has decided to disable syncronous 1570 * negotiation to that target so we don't activate the needsdr 1571 * flag. 1572 */ 1573 ahc->needsdtr_orig = 0; 1574 ahc->needwdtr_orig = 0; 1575 if (!(ahc->type & AHC_WIDE)) 1576 max_targ = 8; 1577 1578 for (i = 0; i < max_targ; i++) { 1579 u_char target_settings = inb(HA_TARG_SCRATCH + i + iobase); 1580 #if 0 /* XXXX */ 1581 target_settings |= 0x8f; 1582 #endif 1583 if (target_settings & 0x0f) { 1584 ahc->needsdtr_orig |= (0x01 << i); 1585 /* Default to a asyncronous transfers (0 offset) */ 1586 target_settings &= 0xf0; 1587 } 1588 if (target_settings & 0x80) { 1589 ahc->needwdtr_orig |= (0x01 << i); 1590 /* 1591 * We'll set the Wide flag when we 1592 * are successful with Wide negotiation, 1593 * so turn it off for now so we aren't 1594 * confused. 1595 */ 1596 target_settings &= 0x7f; 1597 } 1598 outb(HA_TARG_SCRATCH + i + iobase, target_settings); 1599 } 1600 /* 1601 * If we are not a WIDE device, forget WDTR. This 1602 * makes the driver work on some cards that don't 1603 * leave these fields cleared when the BIOS is not 1604 * installed. 1605 */ 1606 if (!(ahc->type & AHC_WIDE)) 1607 ahc->needwdtr_orig = 0; 1608 ahc->needsdtr = ahc->needsdtr_orig; 1609 ahc->needwdtr = ahc->needwdtr_orig; 1610 ahc->sdtrpending = 0; 1611 ahc->wdtrpending = 0; 1612 ahc->tagenable = 0; 1613 1614 /* 1615 * Clear the control byte for every SCB so that the sequencer 1616 * doesn't get confused and think that one of them is valid 1617 */ 1618 for (i = 0; i < ahc->maxscbs; i++) { 1619 outb(SCBPTR + iobase, i); 1620 outb(SCBARRAY + iobase, 0); 1621 } 1622 1623 #ifdef AHC_DEBUG 1624 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n", ahc->needsdtr, 1625 ahc->needwdtr); 1626 #endif 1627 1628 /* 1629 * Set the number of availible SCBs 1630 */ 1631 outb(HA_SCBCOUNT + iobase, ahc->maxscbs); 1632 1633 /* We don't have any busy targets right now */ 1634 outb(HA_ACTIVE0 + iobase, 0); 1635 outb(HA_ACTIVE1 + iobase, 0); 1636 1637 /* We don't have any waiting selections */ 1638 outb(WAITING_SCBH + iobase, SCB_LIST_NULL); 1639 outb(WAITING_SCBT + iobase, SCB_LIST_NULL); 1640 /* 1641 * Load the Sequencer program and Enable the adapter. 1642 * Place the aic7770 in fastmode which makes a big 1643 * difference when doing many small block transfers. 1644 */ 1645 1646 printf("%s: Downloading Sequencer Program...", ahc->sc_dev.dv_xname); 1647 ahc_loadseq(iobase); 1648 printf("Done\n"); 1649 1650 if (!(ahc->type & AHC_AIC7870)) 1651 outb(BCTL + iobase, ENABLE); 1652 1653 /* Reset the bus */ 1654 outb(SCSISEQ + iobase, SCSIRSTO); 1655 delay(1000); 1656 outb(SCSISEQ + iobase, 0); 1657 1658 RESTART_SEQUENCER(ahc); 1659 1660 return (0); 1661 } 1662 1663 void 1664 ahcminphys(bp) 1665 struct buf *bp; 1666 { 1667 1668 if (bp->b_bcount > ((AHC_NSEG - 1) << PGSHIFT)) 1669 bp->b_bcount = ((AHC_NSEG - 1) << PGSHIFT); 1670 minphys(bp); 1671 } 1672 1673 /* 1674 * start a scsi operation given the command and 1675 * the data address, target, and lun all of which 1676 * are stored in the scsi_xfer struct 1677 */ 1678 int 1679 ahc_scsi_cmd(xs) 1680 struct scsi_xfer *xs; 1681 { 1682 struct scsi_link *sc_link = xs->sc_link; 1683 struct ahc_softc *ahc = sc_link->adapter_softc; 1684 struct ahc_scb *scb; 1685 struct ahc_dma_seg *sg; 1686 int seg; /* scatter gather seg being worked on */ 1687 u_long thiskv, thisphys, nextphys; 1688 int bytes_this_seg, bytes_this_page, datalen, flags; 1689 int s; 1690 u_short mask = (0x01 << (sc_link->target | (sc_link->quirks & 0x08))); 1691 1692 #ifdef AHC_MORE_DEBUG 1693 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1694 printf("ahc ahc_scsi_cmd for %x\n", sc_link->target); 1695 sc_link->flags = 0xf0; 1696 SC_DEBUG(sc_link, SDEV_DB2, ("ahc_scsi_cmd\n")); 1697 } 1698 #endif 1699 1700 /* 1701 * get a scb to use. If the transfer 1702 * is from a buf (possibly from interrupt time) 1703 * then we can't allow it to sleep 1704 */ 1705 flags = xs->flags; 1706 if ((flags & (ITSDONE|INUSE)) != INUSE) { 1707 printf("%s: done or not in use?\n", ahc->sc_dev.dv_xname); 1708 xs->flags &= ~ITSDONE; 1709 xs->flags |= INUSE; 1710 } 1711 if ((scb = ahc_get_scb(ahc, flags)) == NULL) { 1712 xs->error = XS_DRIVER_STUFFUP; 1713 return (TRY_AGAIN_LATER); 1714 } 1715 scb->xs = xs; 1716 1717 #ifdef AHC_MORE_DEBUG 1718 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1719 sc_link->flags = 0xf0; 1720 SC_DEBUG(sc_link, SDEV_DB3, ("start scb(%x)\n", scb)); 1721 } 1722 #endif 1723 1724 if (flags & SCSI_RESET) { 1725 /* XXX: Needs Implementation */ 1726 printf("ahc: SCSI_RESET called.\n"); 1727 } 1728 1729 /* 1730 * Put all the arguments for the xfer in the scb 1731 */ 1732 scb->control = 0; 1733 if (ahc->tagenable & mask) 1734 scb->control |= SCB_TE; 1735 if ((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask)) { 1736 scb->control |= SCB_NEEDWDTR; 1737 ahc->wdtrpending |= mask; 1738 } 1739 if ((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask)) { 1740 scb->control |= SCB_NEEDSDTR; 1741 ahc->sdtrpending |= mask; 1742 } 1743 scb->target_channel_lun = ((sc_link->target << 4) & 0xF0) | 1744 (sc_link->quirks & 0x08) | (sc_link->lun & 0x07); 1745 scb->cmdlen = xs->cmdlen; 1746 scb->cmdpointer = vtophys(xs->cmd); 1747 1748 xs->resid = 0; 1749 if (xs->datalen) { 1750 scb->SG_list_pointer = vtophys(scb->ahc_dma); 1751 sg = scb->ahc_dma; 1752 seg = 0; 1753 { 1754 /* 1755 * Set up the scatter gather block 1756 */ 1757 #ifdef AHC_MORE_DEBUG 1758 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1759 sc_link->flags = 0xf0; 1760 SC_DEBUG(sc_link, SDEV_DB4, 1761 ("%ld @%x:- ", xs->datalen, xs->data)); 1762 } 1763 #endif 1764 datalen = xs->datalen; 1765 thiskv = (long) xs->data; 1766 thisphys = vtophys(thiskv); 1767 1768 while (datalen && seg < AHC_NSEG) { 1769 bytes_this_seg = 0; 1770 1771 /* put in the base address */ 1772 sg->seg_addr = thisphys; 1773 1774 #ifdef AHC_MORE_DEBUG 1775 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1776 sc_link->flags = 0xf0; 1777 SC_DEBUGN(sc_link, SDEV_DB4, ("0x%lx", 1778 thisphys)); 1779 } 1780 #endif 1781 1782 /* do it at least once */ 1783 nextphys = thisphys; 1784 while (datalen && thisphys == nextphys) { 1785 /* 1786 * This page is contiguous (physically) 1787 * with the the last, just extend the 1788 * length 1789 */ 1790 /* how far to the end of the page */ 1791 nextphys = (thisphys & ~PGOFSET) + NBPG; 1792 bytes_this_page = nextphys - thisphys; 1793 /**** or the data ****/ 1794 bytes_this_page = min(bytes_this_page, 1795 datalen); 1796 bytes_this_seg += bytes_this_page; 1797 datalen -= bytes_this_page; 1798 1799 /* get more ready for the next page */ 1800 thiskv = (thiskv & ~PGOFSET) + NBPG; 1801 if (datalen) 1802 thisphys = vtophys(thiskv); 1803 } 1804 /* 1805 * next page isn't contiguous, finish the seg 1806 */ 1807 #ifdef AHC_MORE_DEBUG 1808 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1809 sc_link->flags = 0xf0; 1810 SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x)", 1811 bytes_this_seg)); 1812 } 1813 #endif 1814 sg->seg_len = bytes_this_seg; 1815 sg++; 1816 seg++; 1817 } 1818 } 1819 /*end of iov/kv decision */ 1820 scb->SG_segment_count = seg; 1821 #ifdef AHC_MORE_DEBUG 1822 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1823 sc_link->flags = 0xf0; 1824 SC_DEBUGN(sc_link, SDEV_DB4, ("\n")); 1825 } 1826 #endif 1827 if (datalen) { 1828 /* 1829 * there's still data, must have run out of segs! 1830 */ 1831 printf("%s: ahc_scsi_cmd: more than %d dma segs\n", 1832 ahc->sc_dev.dv_xname, AHC_NSEG); 1833 xs->error = XS_DRIVER_STUFFUP; 1834 ahc_free_scb(ahc, scb, flags); 1835 return (COMPLETE); 1836 } 1837 } else { 1838 scb->SG_list_pointer = (physaddr)0; 1839 scb->SG_segment_count = 0; 1840 } 1841 1842 #ifdef AHC_DEBUG 1843 if (sc_link->target == DEBUGTARGET) 1844 ahc_print_scb(scb); 1845 #endif 1846 1847 s = splbio(); 1848 1849 ahc_send_scb(ahc, scb); 1850 1851 /* 1852 * Usually return SUCCESSFULLY QUEUED 1853 */ 1854 if ((flags & SCSI_POLL) == 0) { 1855 timeout(ahc_timeout, scb, (xs->timeout * hz) / 1000); 1856 splx(s); 1857 #ifdef AHC_MORE_DEBUG 1858 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1859 sc_link->flags = 0xf0; 1860 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n")); 1861 } 1862 #endif 1863 return (SUCCESSFULLY_QUEUED); 1864 } 1865 1866 splx(s); 1867 1868 /* 1869 * If we can't use interrupts, poll on completion 1870 */ 1871 #ifdef AHC_MORE_DEBUG 1872 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1873 sc_link->flags = 0xf0; 1874 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_wait\n")); 1875 } 1876 #endif 1877 if (ahc_poll(ahc, xs, xs->timeout)) { 1878 ahc_timeout(scb); 1879 if (ahc_poll(ahc, xs, 2000)) 1880 ahc_timeout(scb); 1881 } 1882 return (COMPLETE); 1883 } 1884 1885 1886 /* 1887 * A scb (and hence an scb entry on the board is put onto the 1888 * free list. 1889 */ 1890 void 1891 ahc_free_scb(ahc, scb, flags) 1892 struct ahc_softc *ahc; 1893 struct ahc_scb *scb; 1894 int flags; 1895 { 1896 int s; 1897 1898 s = splbio(); 1899 1900 scb->flags = SCB_FREE; 1901 TAILQ_INSERT_TAIL(&ahc->free_scb, scb, chain); 1902 #ifdef AHC_DEBUG 1903 ahc->activescbs--; 1904 #endif 1905 1906 /* 1907 * If there were none, wake anybody waiting for one to come free, 1908 * starting with queued entries. 1909 */ 1910 if (scb->chain.tqe_next == 0) 1911 wakeup(&ahc->free_scb); 1912 1913 splx(s); 1914 } 1915 1916 /* XXXX check */ 1917 static inline void 1918 ahc_init_scb(ahc, scb) 1919 struct ahc_softc *ahc; 1920 struct ahc_scb *scb; 1921 { 1922 int iobase = ahc->sc_iobase; 1923 u_char scb_index; 1924 1925 bzero(scb, sizeof(struct ahc_scb)); 1926 scb->position = ahc->numscbs; 1927 /* 1928 * Place in the scbarray 1929 * Never is removed. Position 1930 * in ahc->scbarray is the scbarray 1931 * position on the board we will 1932 * load it into. 1933 */ 1934 ahc->scbarray[scb->position] = scb; 1935 1936 /* 1937 * Initialize the host memory location 1938 * of this SCB down on the board and 1939 * flag that it should be DMA's before 1940 * reference. Also set its psuedo 1941 * next pointer (for use in the psuedo 1942 * list of SCBs waiting for selection) 1943 * to SCB_LIST_NULL. 1944 */ 1945 scb->control = SCB_NEEDDMA; 1946 scb->host_scb = vtophys(scb); 1947 scb->next_waiting = SCB_LIST_NULL; 1948 PAUSE_SEQUENCER(ahc); 1949 scb_index = inb(SCBPTR + iobase); 1950 outb(SCBPTR + iobase, scb->position); 1951 outb(SCBCNT + iobase, SCBAUTO); 1952 outsb(SCBARRAY + iobase, scb, 31); 1953 outb(SCBCNT + iobase, 0); 1954 outb(SCBPTR + iobase, scb_index); 1955 UNPAUSE_SEQUENCER(ahc); 1956 scb->control = 0; 1957 } 1958 1959 static inline void 1960 ahc_reset_scb(ahc, scb) 1961 struct ahc_softc *ahc; 1962 struct ahc_scb *scb; 1963 { 1964 1965 bzero(scb, SCB_BZERO_SIZE); 1966 } 1967 1968 /* 1969 * Get a free scb 1970 * 1971 * If there are none, see if we can allocate a new one. 1972 */ 1973 struct ahc_scb * 1974 ahc_get_scb(ahc, flags) 1975 struct ahc_softc *ahc; 1976 int flags; 1977 { 1978 struct ahc_scb *scb; 1979 int s; 1980 1981 s = splbio(); 1982 1983 /* 1984 * If we can and have to, sleep waiting for one to come free 1985 * but only if we can't allocate a new one. 1986 */ 1987 for (;;) { 1988 scb = ahc->free_scb.tqh_first; 1989 if (scb) { 1990 TAILQ_REMOVE(&ahc->free_scb, scb, chain); 1991 break; 1992 } 1993 if (ahc->numscbs < ahc->maxscbs) { 1994 if (scb = (struct ahc_scb *) malloc(sizeof(struct ahc_scb), 1995 M_TEMP, M_NOWAIT)) { 1996 ahc_init_scb(ahc, scb); 1997 ahc->numscbs++; 1998 } else { 1999 printf("%s: can't malloc scb\n", 2000 ahc->sc_dev.dv_xname); 2001 goto out; 2002 } 2003 break; 2004 } 2005 if ((flags & SCSI_NOSLEEP) != 0) 2006 goto out; 2007 tsleep(&ahc->free_scb, PRIBIO, "ahcscb", 0); 2008 } 2009 2010 ahc_reset_scb(ahc, scb); 2011 scb->flags = SCB_ACTIVE; 2012 #ifdef AHC_DEBUG 2013 ahc->activescbs++; 2014 if (ahc->activescbs == ahc->maxscbs) 2015 printf("%s: Max SCBs active\n", ahc->sc_dev.dv_xname); 2016 #endif 2017 2018 out: 2019 splx(s); 2020 return (scb); 2021 } 2022 2023 /* XXXX check */ 2024 void 2025 ahc_loadseq(iobase) 2026 int iobase; 2027 { 2028 static u_char seqprog[] = { 2029 # include "aic7xxx_seq.h" 2030 }; 2031 2032 outb(SEQCTL + iobase, PERRORDIS|SEQRESET|LOADRAM); 2033 outsb(SEQRAM + iobase, seqprog, sizeof(seqprog)); 2034 outb(SEQCTL + iobase, FASTMODE|SEQRESET); 2035 } 2036 2037 /* 2038 * Function to poll for command completion when in poll mode 2039 */ 2040 int 2041 ahc_poll(ahc, xs, count) 2042 struct ahc_softc *ahc; 2043 struct scsi_xfer *xs; 2044 int count; 2045 { /* in msec */ 2046 int iobase = ahc->sc_iobase; 2047 int stport = INTSTAT + iobase; 2048 2049 while (count) { 2050 /* 2051 * If we had interrupts enabled, would we 2052 * have got an interrupt? 2053 */ 2054 if (inb(stport) & INT_PEND) 2055 ahcintr(ahc); 2056 if (xs->flags & ITSDONE) 2057 return 0; 2058 delay(1000); 2059 count--; 2060 } 2061 return 1; 2062 } 2063 2064 /* XXXX check */ 2065 void 2066 ahc_abort_scb(ahc, scb) 2067 struct ahc_softc *ahc; 2068 struct ahc_scb *scb; 2069 { 2070 int iobase = ahc->sc_iobase; 2071 int found = 0; 2072 int scb_index; 2073 u_char flags; 2074 u_char scb_control; 2075 2076 PAUSE_SEQUENCER(ahc); 2077 /* 2078 * Case 1: In the QINFIFO 2079 */ 2080 { 2081 int saved_queue[AHC_SCB_MAX]; 2082 int i; 2083 int queued = inb(QINCNT + iobase); 2084 2085 for (i = 0; i < (queued - found); i++) { 2086 saved_queue[i] = inb(QINFIFO + iobase); 2087 if (saved_queue[i] == scb->position) { 2088 i--; 2089 found = 1; 2090 } 2091 } 2092 /* Re-insert entries back into the queue */ 2093 for (queued = 0; queued < i; queued++) 2094 outb(QINFIFO + iobase, saved_queue[queued]); 2095 2096 if (found) 2097 goto done; 2098 } 2099 2100 scb_index = inb(SCBPTR + iobase); 2101 /* 2102 * Case 2: Not the active command 2103 */ 2104 if (scb_index != scb->position) { 2105 /* 2106 * Select the SCB we want to abort 2107 * and turn off the disconnected bit. 2108 * the driver will then abort the command 2109 * and notify us of the abort. 2110 */ 2111 outb(SCBPTR + iobase, scb->position); 2112 scb_control = inb(SCBARRAY + iobase); 2113 scb_control &= ~SCB_DIS; 2114 outb(SCBARRAY + iobase, scb_control); 2115 outb(SCBPTR + iobase, scb_index); 2116 goto done; 2117 } 2118 scb_control = inb(SCBARRAY + iobase); 2119 if (scb_control & SCB_DIS) { 2120 scb_control &= ~SCB_DIS; 2121 outb(SCBARRAY + iobase, scb_control); 2122 goto done; 2123 } 2124 /* 2125 * Case 3: Currently active command 2126 */ 2127 if ((flags = inb(HA_FLAGS + iobase)) & ACTIVE_MSG) { 2128 /* 2129 * If there's a message in progress, 2130 * reset the bus and have all devices renegotiate. 2131 */ 2132 if (scb->target_channel_lun & 0x08) { 2133 ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00); 2134 ahc->sdtrpending &= 0x00ff; 2135 outb(HA_ACTIVE1, 0); 2136 } else if (ahc->type & AHC_WIDE) { 2137 ahc->needsdtr = ahc->needsdtr_orig; 2138 ahc->needwdtr = ahc->needwdtr_orig; 2139 ahc->sdtrpending = 0; 2140 ahc->wdtrpending = 0; 2141 outb(HA_ACTIVE0, 0); 2142 outb(HA_ACTIVE1, 0); 2143 } else { 2144 ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff); 2145 ahc->sdtrpending &= 0xff00; 2146 outb(HA_ACTIVE0, 0); 2147 } 2148 2149 /* Reset the bus */ 2150 outb(SCSISEQ + iobase, SCSIRSTO); 2151 delay(1000); 2152 outb(SCSISEQ + iobase, 0); 2153 goto done; 2154 } 2155 2156 /* 2157 * Otherwise, set up an abort message and have the sequencer 2158 * clean up 2159 */ 2160 outb(HA_FLAGS + iobase, flags | ACTIVE_MSG); 2161 outb(HA_MSG_LEN + iobase, 1); 2162 outb(HA_MSG_START + iobase, MSG_ABORT); 2163 2164 outb(SCSISIGO + iobase, inb(HA_SIGSTATE + iobase) | 0x10); 2165 2166 done: 2167 scb->flags = SCB_ABORTED; 2168 UNPAUSE_SEQUENCER(ahc); 2169 ahc_done(ahc, scb); 2170 return; 2171 } 2172 2173 void 2174 ahc_timeout(arg) 2175 void *arg; 2176 { 2177 struct ahc_scb *scb = arg; 2178 struct scsi_xfer *xs = scb->xs; 2179 struct scsi_link *sc_link = xs->sc_link; 2180 struct ahc_softc *ahc = sc_link->adapter_softc; 2181 int s; 2182 2183 sc_print_addr(sc_link); 2184 printf("timed out"); 2185 2186 s = splbio(); 2187 2188 #ifdef SCSIDEBUG 2189 show_scsi_cmd(scb->xs); 2190 #endif 2191 #ifdef AHC_DEBUG 2192 if (ahc_debug & AHC_SHOWSCBS) 2193 ahc_print_active_scb(ahc); 2194 #endif /*AHC_DEBUG */ 2195 2196 if (scb->flags & SCB_IMMED) { 2197 printf("\n"); 2198 scb->xs->retries = 0; /* I MEAN IT ! */ 2199 scb->flags |= SCB_IMMED_FAIL; 2200 ahc_done(ahc, scb); 2201 splx(s); 2202 return; 2203 } 2204 2205 /* 2206 * If it has been through before, then 2207 * a previous abort has failed, don't 2208 * try abort again 2209 */ 2210 if (scb->flags == SCB_ABORTED) { 2211 /* abort timed out */ 2212 printf(" AGAIN\n"); 2213 scb->xs->retries = 0; /* I MEAN IT ! */ 2214 ahc_done(ahc, scb); 2215 } else { 2216 /* abort the operation that has timed out */ 2217 printf("\n"); 2218 scb->xs->error = XS_TIMEOUT; 2219 scb->flags = SCB_ABORTED; 2220 ahc_abort_scb(ahc, scb); 2221 /* 2 secs for the abort */ 2222 if ((xs->flags & SCSI_POLL) == 0) 2223 timeout(ahc_timeout, scb, 2 * hz); 2224 } 2225 2226 splx(s); 2227 } 2228
Indexes created Tue Sep 30 11:09:46 GMT 2025