aic7xxx.c revision 1.100
1 /* $NetBSD: aic7xxx.c,v 1.100 2003/04/21 18:12:22 fvdl Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: aic7xxx.c,v 1.100 2003/04/21 18:12:22 fvdl Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <dev/ic/aic7xxx_osm.h> 53 #include <dev/ic/aic7xxx_inline.h> 54 #include <dev/ic/aic7xxx_cam.h> 55 56 /****************************** Softc Data ************************************/ 57 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 58 59 /***************************** Lookup Tables **********************************/ 60 char *ahc_chip_names[] = 61 { 62 "NONE", 63 "aic7770", 64 "aic7850", 65 "aic7855", 66 "aic7859", 67 "aic7860", 68 "aic7870", 69 "aic7880", 70 "aic7895", 71 "aic7895C", 72 "aic7890/91", 73 "aic7896/97", 74 "aic7892", 75 "aic7899" 76 }; 77 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 78 79 /* 80 * Hardware error codes. 81 */ 82 struct ahc_hard_error_entry { 83 uint8_t errno; 84 char *errmesg; 85 }; 86 87 static struct ahc_hard_error_entry ahc_hard_errors[] = { 88 { ILLHADDR, "Illegal Host Access" }, 89 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 90 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 91 { SQPARERR, "Sequencer Parity Error" }, 92 { DPARERR, "Data-path Parity Error" }, 93 { MPARERR, "Scratch or SCB Memory Parity Error" }, 94 { PCIERRSTAT, "PCI Error detected" }, 95 { CIOPARERR, "CIOBUS Parity Error" }, 96 }; 97 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 98 99 static struct ahc_phase_table_entry ahc_phase_table[] = 100 { 101 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 102 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 103 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 104 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 105 { P_COMMAND, MSG_NOOP, "in Command phase" }, 106 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 107 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 108 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 109 { P_BUSFREE, MSG_NOOP, "while idle" }, 110 { 0, MSG_NOOP, "in unknown phase" } 111 }; 112 113 /* 114 * In most cases we only wish to itterate over real phases, so 115 * exclude the last element from the count. 116 */ 117 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 118 119 /* 120 * Valid SCSIRATE values. (p. 3-17) 121 * Provides a mapping of tranfer periods in ns to the proper value to 122 * stick in the scsixfer reg. 123 */ 124 static struct ahc_syncrate ahc_syncrates[] = 125 { 126 /* ultra2 fast/ultra period rate */ 127 { 0x42, 0x000, 9, "80.0" }, 128 { 0x03, 0x000, 10, "40.0" }, 129 { 0x04, 0x000, 11, "33.0" }, 130 { 0x05, 0x100, 12, "20.0" }, 131 { 0x06, 0x110, 15, "16.0" }, 132 { 0x07, 0x120, 18, "13.4" }, 133 { 0x08, 0x000, 25, "10.0" }, 134 { 0x19, 0x010, 31, "8.0" }, 135 { 0x1a, 0x020, 37, "6.67" }, 136 { 0x1b, 0x030, 43, "5.7" }, 137 { 0x1c, 0x040, 50, "5.0" }, 138 { 0x00, 0x050, 56, "4.4" }, 139 { 0x00, 0x060, 62, "4.0" }, 140 { 0x00, 0x070, 68, "3.6" }, 141 { 0x00, 0x000, 0, NULL } 142 }; 143 144 /* Our Sequencer Program */ 145 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 146 147 /**************************** Function Declarations ***************************/ 148 static void ahc_force_renegotiation(struct ahc_softc *ahc); 149 static struct ahc_tmode_tstate* 150 ahc_alloc_tstate(struct ahc_softc *ahc, 151 u_int scsi_id, char channel); 152 #ifdef AHC_TARGET_MODE 153 static void ahc_free_tstate(struct ahc_softc *ahc, 154 u_int scsi_id, char channel, int force); 155 #endif 156 static struct ahc_syncrate* 157 ahc_devlimited_syncrate(struct ahc_softc *ahc, 158 struct ahc_initiator_tinfo *, 159 u_int *period, 160 u_int *ppr_options, 161 role_t role); 162 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 163 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo); 165 static void ahc_scb_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo, 167 struct scb *scb); 168 static void ahc_assert_atn(struct ahc_softc *ahc); 169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 struct scb *scb); 172 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo); 174 static void ahc_construct_sdtr(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo, 176 u_int period, u_int offset); 177 static void ahc_construct_wdtr(struct ahc_softc *ahc, 178 struct ahc_devinfo *devinfo, 179 u_int bus_width); 180 static void ahc_construct_ppr(struct ahc_softc *ahc, 181 struct ahc_devinfo *devinfo, 182 u_int period, u_int offset, 183 u_int bus_width, u_int ppr_options); 184 static void ahc_clear_msg_state(struct ahc_softc *ahc); 185 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 186 static void ahc_handle_message_phase(struct ahc_softc *ahc); 187 typedef enum { 188 AHCMSG_1B, 189 AHCMSG_2B, 190 AHCMSG_EXT 191 } ahc_msgtype; 192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 193 u_int msgval, int full); 194 static int ahc_parse_msg(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 201 static void ahc_handle_devreset(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 cam_status status, char *message, 204 int verbose_level); 205 #if AHC_TARGET_MODE 206 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 207 struct ahc_devinfo *devinfo, 208 struct scb *scb); 209 #endif 210 211 //static bus_dmamap_callback_t ahc_dmamap_cb; 212 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 213 static int ahc_init_scbdata(struct ahc_softc *ahc); 214 static void ahc_fini_scbdata(struct ahc_softc *ahc); 215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 216 struct scb *prev_scb, 217 struct scb *scb); 218 static int ahc_qinfifo_count(struct ahc_softc *ahc); 219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 220 u_int prev, u_int scbptr); 221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 222 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 223 u_int scbpos, u_int prev); 224 static void ahc_reset_current_bus(struct ahc_softc *ahc); 225 #ifdef AHC_DUMP_SEQ 226 static void ahc_dumpseq(struct ahc_softc *ahc); 227 #endif 228 static void ahc_loadseq(struct ahc_softc *ahc); 229 static int ahc_check_patch(struct ahc_softc *ahc, 230 struct patch **start_patch, 231 u_int start_instr, u_int *skip_addr); 232 static void ahc_download_instr(struct ahc_softc *ahc, 233 u_int instrptr, uint8_t *dconsts); 234 #ifdef AHC_TARGET_MODE 235 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 236 struct ahc_tmode_lstate *lstate, 237 u_int initiator_id, 238 u_int event_type, 239 u_int event_arg); 240 static void ahc_update_scsiid(struct ahc_softc *ahc, 241 u_int targid_mask); 242 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 243 struct target_cmd *cmd); 244 #endif 245 246 /************************** Added for porting to NetBSD ***********************/ 247 static int ahc_createdmamem(bus_dma_tag_t tag, 248 int size, 249 int flags, 250 bus_dmamap_t *mapp, 251 caddr_t *vaddr, 252 bus_addr_t *baddr, 253 bus_dma_segment_t *seg, 254 int *nseg, 255 const char *myname, const char *what); 256 static void ahc_freedmamem(bus_dma_tag_t tag, 257 int size, 258 bus_dmamap_t map, 259 caddr_t vaddr, 260 bus_dma_segment_t *seg, 261 int nseg); 262 263 /************************* Sequencer Execution Control ************************/ 264 /* 265 * Restart the sequencer program from address zero 266 */ 267 void 268 ahc_restart(struct ahc_softc *ahc) 269 { 270 271 ahc_pause(ahc); 272 273 /* No more pending messages. */ 274 ahc_clear_msg_state(ahc); 275 276 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 277 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 278 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 279 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 280 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 281 ahc_outb(ahc, SAVED_LUN, 0xFF); 282 283 /* 284 * Ensure that the sequencer's idea of TQINPOS 285 * matches our own. The sequencer increments TQINPOS 286 * only after it sees a DMA complete and a reset could 287 * occur before the increment leaving the kernel to believe 288 * the command arrived but the sequencer to not. 289 */ 290 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 291 292 /* Always allow reselection */ 293 ahc_outb(ahc, SCSISEQ, 294 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 295 if ((ahc->features & AHC_CMD_CHAN) != 0) { 296 /* Ensure that no DMA operations are in progress */ 297 ahc_outb(ahc, CCSCBCNT, 0); 298 ahc_outb(ahc, CCSGCTL, 0); 299 ahc_outb(ahc, CCSCBCTL, 0); 300 } 301 /* 302 * If we were in the process of DMA'ing SCB data into 303 * an SCB, replace that SCB on the free list. This prevents 304 * an SCB leak. 305 */ 306 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 307 ahc_add_curscb_to_free_list(ahc); 308 ahc_outb(ahc, SEQ_FLAGS2, 309 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 310 } 311 ahc_outb(ahc, MWI_RESIDUAL, 0); 312 ahc_outb(ahc, SEQCTL, FASTMODE); 313 ahc_outb(ahc, SEQADDR0, 0); 314 ahc_outb(ahc, SEQADDR1, 0); 315 ahc_unpause(ahc); 316 } 317 318 /************************* Input/Output Queues ********************************/ 319 void 320 ahc_run_qoutfifo(struct ahc_softc *ahc) 321 { 322 struct scb *scb; 323 u_int scb_index; 324 325 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 326 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 327 328 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 329 if ((ahc->qoutfifonext & 0x03) == 0x03) { 330 u_int modnext; 331 332 /* 333 * Clear 32bits of QOUTFIFO at a time 334 * so that we don't clobber an incoming 335 * byte DMA to the array on architectures 336 * that only support 32bit load and store 337 * operations. 338 */ 339 modnext = ahc->qoutfifonext & ~0x3; 340 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 341 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 342 ahc->shared_data_dmamap, 343 /*offset*/modnext, /*len*/4, 344 BUS_DMASYNC_PREREAD); 345 } 346 ahc->qoutfifonext++; 347 348 scb = ahc_lookup_scb(ahc, scb_index); 349 if (scb == NULL) { 350 printf("%s: WARNING no command for scb %d " 351 "(cmdcmplt)\nQOUTPOS = %d\n", 352 ahc_name(ahc), scb_index, 353 (ahc->qoutfifonext - 1) & 0xFF); 354 continue; 355 } 356 357 /* 358 * Save off the residual 359 * if there is one. 360 */ 361 ahc_update_residual(ahc, scb); 362 ahc_done(ahc, scb); 363 } 364 } 365 366 void 367 ahc_run_untagged_queues(struct ahc_softc *ahc) 368 { 369 int i; 370 371 for (i = 0; i < 16; i++) 372 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 373 } 374 375 void 376 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 377 { 378 struct scb *scb; 379 380 if (ahc->untagged_queue_lock != 0) 381 return; 382 383 if ((scb = TAILQ_FIRST(queue)) != NULL 384 && (scb->flags & SCB_ACTIVE) == 0) { 385 scb->flags |= SCB_ACTIVE; 386 ahc_queue_scb(ahc, scb); 387 } 388 } 389 390 /************************* Interrupt Handling *********************************/ 391 void 392 ahc_handle_brkadrint(struct ahc_softc *ahc) 393 { 394 /* 395 * We upset the sequencer :-( 396 * Lookup the error message 397 */ 398 int i; 399 int error; 400 401 error = ahc_inb(ahc, ERROR); 402 for (i = 0; error != 1 && i < num_errors; i++) 403 error >>= 1; 404 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 405 ahc_name(ahc), ahc_hard_errors[i].errmesg, 406 ahc_inb(ahc, SEQADDR0) | 407 (ahc_inb(ahc, SEQADDR1) << 8)); 408 409 ahc_dump_card_state(ahc); 410 411 /* Tell everyone that this HBA is no longer availible */ 412 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 413 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 414 CAM_NO_HBA); 415 416 /* Disable all interrupt sources by resetting the controller */ 417 ahc_shutdown(ahc); 418 } 419 420 void 421 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 422 { 423 struct scb *scb; 424 struct ahc_devinfo devinfo; 425 426 ahc_fetch_devinfo(ahc, &devinfo); 427 428 /* 429 * Clear the upper byte that holds SEQINT status 430 * codes and clear the SEQINT bit. We will unpause 431 * the sequencer, if appropriate, after servicing 432 * the request. 433 */ 434 ahc_outb(ahc, CLRINT, CLRSEQINT); 435 switch (intstat & SEQINT_MASK) { 436 case BAD_STATUS: 437 { 438 u_int scb_index; 439 struct hardware_scb *hscb; 440 441 /* 442 * Set the default return value to 0 (don't 443 * send sense). The sense code will change 444 * this if needed. 445 */ 446 ahc_outb(ahc, RETURN_1, 0); 447 448 /* 449 * The sequencer will notify us when a command 450 * has an error that would be of interest to 451 * the kernel. This allows us to leave the sequencer 452 * running in the common case of command completes 453 * without error. The sequencer will already have 454 * dma'd the SCB back up to us, so we can reference 455 * the in kernel copy directly. 456 */ 457 scb_index = ahc_inb(ahc, SCB_TAG); 458 scb = ahc_lookup_scb(ahc, scb_index); 459 if (scb == NULL) { 460 ahc_print_devinfo(ahc, &devinfo); 461 printf("ahc_intr - referenced scb " 462 "not valid during seqint 0x%x scb(%d)\n", 463 intstat, scb_index); 464 ahc_dump_card_state(ahc); 465 panic("for safety"); 466 goto unpause; 467 } 468 469 hscb = scb->hscb; 470 471 /* Don't want to clobber the original sense code */ 472 if ((scb->flags & SCB_SENSE) != 0) { 473 /* 474 * Clear the SCB_SENSE Flag and have 475 * the sequencer do a normal command 476 * complete. 477 */ 478 scb->flags &= ~SCB_SENSE; 479 break; 480 } 481 /* Freeze the queue until the client sees the error. */ 482 ahc_freeze_devq(ahc, scb); 483 ahc_freeze_scb(scb); 484 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 485 switch (hscb->shared_data.status.scsi_status) { 486 case SCSI_STATUS_OK: 487 printf("%s: Interrupted for status of 0 (???)\n", 488 ahc_name(ahc)); 489 break; 490 case SCSI_STATUS_CMD_TERMINATED: 491 case SCSI_STATUS_CHECK_COND: 492 { 493 struct ahc_dma_seg *sg; 494 struct scsipi_sense *sc; 495 struct ahc_initiator_tinfo *targ_info; 496 struct ahc_tmode_tstate *tstate; 497 struct ahc_transinfo *tinfo; 498 #ifdef AHC_DEBUG 499 if (ahc_debug & AHC_SHOW_SENSE) { 500 ahc_print_path(ahc, scb); 501 printf("SCB %d: requests Check Status\n", 502 scb->hscb->tag); 503 } 504 #endif 505 506 if (ahc_perform_autosense(scb) == 0) 507 break; 508 509 targ_info = ahc_fetch_transinfo(ahc, 510 devinfo.channel, 511 devinfo.our_scsiid, 512 devinfo.target, 513 &tstate); 514 tinfo = &targ_info->curr; 515 sg = scb->sg_list; 516 sc = (struct scsipi_sense *)(&hscb->shared_data.cdb); 517 /* 518 * Save off the residual if there is one. 519 */ 520 ahc_update_residual(ahc, scb); 521 #ifdef AHC_DEBUG 522 if (ahc_debug & AHC_SHOW_SENSE) { 523 ahc_print_path(ahc, scb); 524 printf("Sending Sense\n"); 525 } 526 #endif 527 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 528 sg->len = ahc_get_sense_bufsize(ahc, scb); 529 sg->len |= AHC_DMA_LAST_SEG; 530 531 /* Fixup byte order */ 532 sg->addr = ahc_htole32(sg->addr); 533 sg->len = ahc_htole32(sg->len); 534 535 sc->opcode = REQUEST_SENSE; 536 sc->byte2 = 0; 537 if (tinfo->protocol_version <= SCSI_REV_2 538 && SCB_GET_LUN(scb) < 8) 539 sc->byte2 = SCB_GET_LUN(scb) << 5; 540 sc->unused[0] = 0; 541 sc->unused[1] = 0; 542 sc->length = sg->len; 543 sc->control = 0; 544 545 /* 546 * We can't allow the target to disconnect. 547 * This will be an untagged transaction and 548 * having the target disconnect will make this 549 * transaction indestinguishable from outstanding 550 * tagged transactions. 551 */ 552 hscb->control = 0; 553 554 /* 555 * This request sense could be because the 556 * the device lost power or in some other 557 * way has lost our transfer negotiations. 558 * Renegotiate if appropriate. Unit attention 559 * errors will be reported before any data 560 * phases occur. 561 */ 562 if (ahc_get_residual(scb) 563 == ahc_get_transfer_length(scb)) { 564 ahc_update_neg_request(ahc, &devinfo, 565 tstate, targ_info, 566 AHC_NEG_IF_NON_ASYNC); 567 } 568 if (tstate->auto_negotiate & devinfo.target_mask) { 569 hscb->control |= MK_MESSAGE; 570 scb->flags &= ~SCB_NEGOTIATE; 571 scb->flags |= SCB_AUTO_NEGOTIATE; 572 } 573 hscb->cdb_len = sizeof(*sc); 574 hscb->dataptr = sg->addr; 575 hscb->datacnt = sg->len; 576 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 577 hscb->sgptr = ahc_htole32(hscb->sgptr); 578 scb->sg_count = 1; 579 scb->flags |= SCB_SENSE; 580 ahc_qinfifo_requeue_tail(ahc, scb); 581 ahc_outb(ahc, RETURN_1, SEND_SENSE); 582 /* 583 * Ensure we have enough time to actually 584 * retrieve the sense. 585 */ 586 ahc_scb_timer_reset(scb, 5 * 1000000); 587 break; 588 } 589 default: 590 break; 591 } 592 break; 593 } 594 case NO_MATCH: 595 { 596 /* Ensure we don't leave the selection hardware on */ 597 ahc_outb(ahc, SCSISEQ, 598 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 599 600 printf("%s:%c:%d: no active SCB for reconnecting " 601 "target - issuing BUS DEVICE RESET\n", 602 ahc_name(ahc), devinfo.channel, devinfo.target); 603 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 604 "ARG_1 == 0x%x ACCUM = 0x%x\n", 605 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 606 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 607 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 608 "SINDEX == 0x%x\n", 609 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 610 ahc_index_busy_tcl(ahc, 611 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 612 ahc_inb(ahc, SAVED_LUN))), 613 ahc_inb(ahc, SINDEX)); 614 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 615 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 616 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 617 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 618 ahc_inb(ahc, SCB_CONTROL)); 619 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 620 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 621 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 622 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 623 ahc_dump_card_state(ahc); 624 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 625 ahc->msgout_len = 1; 626 ahc->msgout_index = 0; 627 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 628 ahc_outb(ahc, MSG_OUT, HOST_MSG); 629 ahc_assert_atn(ahc); 630 break; 631 } 632 case SEND_REJECT: 633 { 634 u_int rejbyte = ahc_inb(ahc, ACCUM); 635 printf("%s:%c:%d: Warning - unknown message received from " 636 "target (0x%x). Rejecting\n", 637 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 638 break; 639 } 640 case PROTO_VIOLATION: 641 { 642 ahc_handle_proto_violation(ahc); 643 break; 644 } 645 case IGN_WIDE_RES: 646 ahc_handle_ign_wide_residue(ahc, &devinfo); 647 break; 648 case PDATA_REINIT: 649 ahc_reinitialize_dataptrs(ahc); 650 break; 651 case BAD_PHASE: 652 { 653 u_int lastphase; 654 655 lastphase = ahc_inb(ahc, LASTPHASE); 656 printf("%s:%c:%d: unknown scsi bus phase %x, " 657 "lastphase = 0x%x. Attempting to continue\n", 658 ahc_name(ahc), devinfo.channel, devinfo.target, 659 lastphase, ahc_inb(ahc, SCSISIGI)); 660 break; 661 } 662 case MISSED_BUSFREE: 663 { 664 u_int lastphase; 665 666 lastphase = ahc_inb(ahc, LASTPHASE); 667 printf("%s:%c:%d: Missed busfree. " 668 "Lastphase = 0x%x, Curphase = 0x%x\n", 669 ahc_name(ahc), devinfo.channel, devinfo.target, 670 lastphase, ahc_inb(ahc, SCSISIGI)); 671 ahc_restart(ahc); 672 return; 673 } 674 case HOST_MSG_LOOP: 675 { 676 /* 677 * The sequencer has encountered a message phase 678 * that requires host assistance for completion. 679 * While handling the message phase(s), we will be 680 * notified by the sequencer after each byte is 681 * transfered so we can track bus phase changes. 682 * 683 * If this is the first time we've seen a HOST_MSG_LOOP 684 * interrupt, initialize the state of the host message 685 * loop. 686 */ 687 if (ahc->msg_type == MSG_TYPE_NONE) { 688 struct scb *scb; 689 u_int scb_index; 690 u_int bus_phase; 691 692 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 693 if (bus_phase != P_MESGIN 694 && bus_phase != P_MESGOUT) { 695 printf("ahc_intr: HOST_MSG_LOOP bad " 696 "phase 0x%x\n", 697 bus_phase); 698 /* 699 * Probably transitioned to bus free before 700 * we got here. Just punt the message. 701 */ 702 ahc_clear_intstat(ahc); 703 ahc_restart(ahc); 704 return; 705 } 706 707 scb_index = ahc_inb(ahc, SCB_TAG); 708 scb = ahc_lookup_scb(ahc, scb_index); 709 if (devinfo.role == ROLE_INITIATOR) { 710 if (scb == NULL) 711 panic("HOST_MSG_LOOP with " 712 "invalid SCB %x\n", scb_index); 713 714 if (bus_phase == P_MESGOUT) 715 ahc_setup_initiator_msgout(ahc, 716 &devinfo, 717 scb); 718 else { 719 ahc->msg_type = 720 MSG_TYPE_INITIATOR_MSGIN; 721 ahc->msgin_index = 0; 722 } 723 } 724 #if AHC_TARGET_MODE 725 else { 726 if (bus_phase == P_MESGOUT) { 727 ahc->msg_type = 728 MSG_TYPE_TARGET_MSGOUT; 729 ahc->msgin_index = 0; 730 } 731 else 732 ahc_setup_target_msgin(ahc, 733 &devinfo, 734 scb); 735 } 736 #endif 737 } 738 739 ahc_handle_message_phase(ahc); 740 break; 741 } 742 case PERR_DETECTED: 743 { 744 /* 745 * If we've cleared the parity error interrupt 746 * but the sequencer still believes that SCSIPERR 747 * is true, it must be that the parity error is 748 * for the currently presented byte on the bus, 749 * and we are not in a phase (data-in) where we will 750 * eventually ack this byte. Ack the byte and 751 * throw it away in the hope that the target will 752 * take us to message out to deliver the appropriate 753 * error message. 754 */ 755 if ((intstat & SCSIINT) == 0 756 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 757 758 if ((ahc->features & AHC_DT) == 0) { 759 u_int curphase; 760 761 /* 762 * The hardware will only let you ack bytes 763 * if the expected phase in SCSISIGO matches 764 * the current phase. Make sure this is 765 * currently the case. 766 */ 767 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 768 ahc_outb(ahc, LASTPHASE, curphase); 769 ahc_outb(ahc, SCSISIGO, curphase); 770 } 771 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 772 int wait; 773 774 /* 775 * In a data phase. Faster to bitbucket 776 * the data than to individually ack each 777 * byte. This is also the only strategy 778 * that will work with AUTOACK enabled. 779 */ 780 ahc_outb(ahc, SXFRCTL1, 781 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 782 wait = 5000; 783 while (--wait != 0) { 784 if ((ahc_inb(ahc, SCSISIGI) 785 & (CDI|MSGI)) != 0) 786 break; 787 ahc_delay(100); 788 } 789 ahc_outb(ahc, SXFRCTL1, 790 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 791 if (wait == 0) { 792 struct scb *scb; 793 u_int scb_index; 794 795 ahc_print_devinfo(ahc, &devinfo); 796 printf("Unable to clear parity error. " 797 "Resetting bus.\n"); 798 scb_index = ahc_inb(ahc, SCB_TAG); 799 scb = ahc_lookup_scb(ahc, scb_index); 800 if (scb != NULL) 801 ahc_set_transaction_status(scb, 802 CAM_UNCOR_PARITY); 803 ahc_reset_channel(ahc, devinfo.channel, 804 /*init reset*/TRUE); 805 } 806 } else { 807 ahc_inb(ahc, SCSIDATL); 808 } 809 } 810 break; 811 } 812 case DATA_OVERRUN: 813 { 814 /* 815 * When the sequencer detects an overrun, it 816 * places the controller in "BITBUCKET" mode 817 * and allows the target to complete its transfer. 818 * Unfortunately, none of the counters get updated 819 * when the controller is in this mode, so we have 820 * no way of knowing how large the overrun was. 821 */ 822 u_int scbindex = ahc_inb(ahc, SCB_TAG); 823 u_int lastphase = ahc_inb(ahc, LASTPHASE); 824 u_int i; 825 826 scb = ahc_lookup_scb(ahc, scbindex); 827 for (i = 0; i < num_phases; i++) { 828 if (lastphase == ahc_phase_table[i].phase) 829 break; 830 } 831 ahc_print_path(ahc, scb); 832 printf("data overrun detected %s." 833 " Tag == 0x%x.\n", 834 ahc_phase_table[i].phasemsg, 835 scb->hscb->tag); 836 ahc_print_path(ahc, scb); 837 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 838 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 839 ahc_get_transfer_length(scb), scb->sg_count); 840 if (scb->sg_count > 0) { 841 for (i = 0; i < scb->sg_count; i++) { 842 843 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 844 i, 845 (ahc_le32toh(scb->sg_list[i].len) >> 24 846 & SG_HIGH_ADDR_BITS), 847 ahc_le32toh(scb->sg_list[i].addr), 848 ahc_le32toh(scb->sg_list[i].len) 849 & AHC_SG_LEN_MASK); 850 } 851 } 852 /* 853 * Set this and it will take effect when the 854 * target does a command complete. 855 */ 856 ahc_freeze_devq(ahc, scb); 857 if ((scb->flags & SCB_SENSE) == 0) { 858 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 859 } else { 860 scb->flags &= ~SCB_SENSE; 861 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 862 } 863 ahc_freeze_scb(scb); 864 865 if ((ahc->features & AHC_ULTRA2) != 0) { 866 /* 867 * Clear the channel in case we return 868 * to data phase later. 869 */ 870 ahc_outb(ahc, SXFRCTL0, 871 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 872 ahc_outb(ahc, SXFRCTL0, 873 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 874 } 875 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 876 u_int dscommand1; 877 878 /* Ensure HHADDR is 0 for future DMA operations. */ 879 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 880 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 881 ahc_outb(ahc, HADDR, 0); 882 ahc_outb(ahc, DSCOMMAND1, dscommand1); 883 } 884 break; 885 } 886 case MKMSG_FAILED: 887 { 888 u_int scbindex; 889 890 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 891 ahc_name(ahc), devinfo.channel, devinfo.target, 892 devinfo.lun); 893 scbindex = ahc_inb(ahc, SCB_TAG); 894 scb = ahc_lookup_scb(ahc, scbindex); 895 if (scb != NULL 896 && (scb->flags & SCB_RECOVERY_SCB) != 0) 897 /* 898 * Ensure that we didn't put a second instance of this 899 * SCB into the QINFIFO. 900 */ 901 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 902 SCB_GET_CHANNEL(ahc, scb), 903 SCB_GET_LUN(scb), scb->hscb->tag, 904 ROLE_INITIATOR, /*status*/0, 905 SEARCH_REMOVE); 906 break; 907 } 908 case NO_FREE_SCB: 909 { 910 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 911 ahc_dump_card_state(ahc); 912 panic("for safety"); 913 break; 914 } 915 case SCB_MISMATCH: 916 { 917 u_int scbptr; 918 919 scbptr = ahc_inb(ahc, SCBPTR); 920 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 921 scbptr, ahc_inb(ahc, ARG_1), 922 ahc->scb_data->hscbs[scbptr].tag); 923 ahc_dump_card_state(ahc); 924 panic("for saftey"); 925 break; 926 } 927 case OUT_OF_RANGE: 928 { 929 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 930 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 931 "ARG_1 == 0x%x ACCUM = 0x%x\n", 932 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 933 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 934 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 935 "SINDEX == 0x%x\n, A == 0x%x\n", 936 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 937 ahc_index_busy_tcl(ahc, 938 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 939 ahc_inb(ahc, SAVED_LUN))), 940 ahc_inb(ahc, SINDEX), 941 ahc_inb(ahc, ACCUM)); 942 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 943 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 944 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 945 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 946 ahc_inb(ahc, SCB_CONTROL)); 947 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 948 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 949 ahc_dump_card_state(ahc); 950 panic("for safety"); 951 break; 952 } 953 default: 954 printf("ahc_intr: seqint, " 955 "intstat == 0x%x, scsisigi = 0x%x\n", 956 intstat, ahc_inb(ahc, SCSISIGI)); 957 break; 958 } 959 unpause: 960 /* 961 * The sequencer is paused immediately on 962 * a SEQINT, so we should restart it when 963 * we're done. 964 */ 965 ahc_unpause(ahc); 966 } 967 968 void 969 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 970 { 971 u_int scb_index; 972 u_int status0; 973 u_int status; 974 struct scb *scb; 975 char cur_channel; 976 char intr_channel; 977 978 if ((ahc->features & AHC_TWIN) != 0 979 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 980 cur_channel = 'B'; 981 else 982 cur_channel = 'A'; 983 intr_channel = cur_channel; 984 985 if ((ahc->features & AHC_ULTRA2) != 0) 986 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 987 else 988 status0 = 0; 989 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 990 if (status == 0 && status0 == 0) { 991 if ((ahc->features & AHC_TWIN) != 0) { 992 /* Try the other channel */ 993 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 994 status = ahc_inb(ahc, SSTAT1) 995 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 996 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 997 } 998 if (status == 0) { 999 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1000 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1001 ahc_unpause(ahc); 1002 return; 1003 } 1004 } 1005 1006 /* Make sure the sequencer is in a safe location. */ 1007 ahc_clear_critical_section(ahc); 1008 1009 scb_index = ahc_inb(ahc, SCB_TAG); 1010 scb = ahc_lookup_scb(ahc, scb_index); 1011 if (scb != NULL 1012 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1013 scb = NULL; 1014 1015 if ((ahc->features & AHC_ULTRA2) != 0 1016 && (status0 & IOERR) != 0) { 1017 int now_lvd; 1018 1019 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1020 printf("%s: Transceiver State Has Changed to %s mode\n", 1021 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1022 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1023 /* 1024 * When transitioning to SE mode, the reset line 1025 * glitches, triggering an arbitration bug in some 1026 * Ultra2 controllers. This bug is cleared when we 1027 * assert the reset line. Since a reset glitch has 1028 * already occurred with this transition and a 1029 * transceiver state change is handled just like 1030 * a bus reset anyway, asserting the reset line 1031 * ourselves is safe. 1032 */ 1033 ahc_reset_channel(ahc, intr_channel, 1034 /*Initiate Reset*/now_lvd == 0); 1035 } else if ((status & SCSIRSTI) != 0) { 1036 printf("%s: Someone reset channel %c\n", 1037 ahc_name(ahc), intr_channel); 1038 if (intr_channel != cur_channel) 1039 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1040 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1041 } else if ((status & SCSIPERR) != 0) { 1042 /* 1043 * Determine the bus phase and queue an appropriate message. 1044 * SCSIPERR is latched true as soon as a parity error 1045 * occurs. If the sequencer acked the transfer that 1046 * caused the parity error and the currently presented 1047 * transfer on the bus has correct parity, SCSIPERR will 1048 * be cleared by CLRSCSIPERR. Use this to determine if 1049 * we should look at the last phase the sequencer recorded, 1050 * or the current phase presented on the bus. 1051 */ 1052 u_int mesg_out; 1053 u_int curphase; 1054 u_int errorphase; 1055 u_int lastphase; 1056 u_int scsirate; 1057 u_int i; 1058 u_int sstat2; 1059 int silent; 1060 1061 lastphase = ahc_inb(ahc, LASTPHASE); 1062 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1063 sstat2 = ahc_inb(ahc, SSTAT2); 1064 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1065 /* 1066 * For all phases save DATA, the sequencer won't 1067 * automatically ack a byte that has a parity error 1068 * in it. So the only way that the current phase 1069 * could be 'data-in' is if the parity error is for 1070 * an already acked byte in the data phase. During 1071 * synchronous data-in transfers, we may actually 1072 * ack bytes before latching the current phase in 1073 * LASTPHASE, leading to the discrepancy between 1074 * curphase and lastphase. 1075 */ 1076 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1077 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1078 errorphase = curphase; 1079 else 1080 errorphase = lastphase; 1081 1082 for (i = 0; i < num_phases; i++) { 1083 if (errorphase == ahc_phase_table[i].phase) 1084 break; 1085 } 1086 mesg_out = ahc_phase_table[i].mesg_out; 1087 silent = FALSE; 1088 if (scb != NULL) { 1089 if (SCB_IS_SILENT(scb)) 1090 silent = TRUE; 1091 else 1092 ahc_print_path(ahc, scb); 1093 scb->flags |= SCB_TRANSMISSION_ERROR; 1094 } else 1095 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1096 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1097 scsirate = ahc_inb(ahc, SCSIRATE); 1098 if (silent == FALSE) { 1099 printf("parity error detected %s. " 1100 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1101 ahc_phase_table[i].phasemsg, 1102 ahc_inw(ahc, SEQADDR0), 1103 scsirate); 1104 if ((ahc->features & AHC_DT) != 0) { 1105 if ((sstat2 & CRCVALERR) != 0) 1106 printf("\tCRC Value Mismatch\n"); 1107 if ((sstat2 & CRCENDERR) != 0) 1108 printf("\tNo terminal CRC packet " 1109 "recevied\n"); 1110 if ((sstat2 & CRCREQERR) != 0) 1111 printf("\tIllegal CRC packet " 1112 "request\n"); 1113 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1114 printf("\tUnexpected %sDT Data Phase\n", 1115 (scsirate & SINGLE_EDGE) 1116 ? "" : "non-"); 1117 } 1118 } 1119 1120 if ((ahc->features & AHC_DT) != 0 1121 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1122 /* 1123 * This error applies regardless of 1124 * data direction, so ignore the value 1125 * in the phase table. 1126 */ 1127 mesg_out = MSG_INITIATOR_DET_ERR; 1128 } 1129 1130 /* 1131 * We've set the hardware to assert ATN if we 1132 * get a parity error on "in" phases, so all we 1133 * need to do is stuff the message buffer with 1134 * the appropriate message. "In" phases have set 1135 * mesg_out to something other than MSG_NOP. 1136 */ 1137 if (mesg_out != MSG_NOOP) { 1138 if (ahc->msg_type != MSG_TYPE_NONE) 1139 ahc->send_msg_perror = TRUE; 1140 else 1141 ahc_outb(ahc, MSG_OUT, mesg_out); 1142 } 1143 /* 1144 * Force a renegotiation with this target just in 1145 * case we are out of sync for some external reason 1146 * unknown (or unreported) by the target. 1147 */ 1148 ahc_force_renegotiation(ahc); 1149 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1150 ahc_unpause(ahc); 1151 } else if ((status & SELTO) != 0) { 1152 u_int scbptr; 1153 1154 /* Stop the selection */ 1155 ahc_outb(ahc, SCSISEQ, 0); 1156 1157 /* No more pending messages */ 1158 ahc_clear_msg_state(ahc); 1159 1160 /* Clear interrupt state */ 1161 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1162 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1163 1164 /* 1165 * Although the driver does not care about the 1166 * 'Selection in Progress' status bit, the busy 1167 * LED does. SELINGO is only cleared by a sucessfull 1168 * selection, so we must manually clear it to insure 1169 * the LED turns off just incase no future successful 1170 * selections occur (e.g. no devices on the bus). 1171 */ 1172 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1173 1174 scbptr = ahc_inb(ahc, WAITING_SCBH); 1175 ahc_outb(ahc, SCBPTR, scbptr); 1176 scb_index = ahc_inb(ahc, SCB_TAG); 1177 1178 scb = ahc_lookup_scb(ahc, scb_index); 1179 if (scb == NULL) { 1180 printf("%s: ahc_intr - referenced scb not " 1181 "valid during SELTO scb(%d, %d)\n", 1182 ahc_name(ahc), scbptr, scb_index); 1183 ahc_dump_card_state(ahc); 1184 } else { 1185 #ifdef AHC_DEBUG 1186 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1187 ahc_print_path(ahc, scb); 1188 printf("Saw Selection Timeout for SCB 0x%x\n", 1189 scb_index); 1190 } 1191 #endif 1192 /* 1193 * Force a renegotiation with this target just in 1194 * case the cable was pulled and will later be 1195 * re-attached. The target may forget its negotiation 1196 * settings with us should it attempt to reselect 1197 * during the interruption. The target will not issue 1198 * a unit attention in this case, so we must always 1199 * renegotiate. 1200 */ 1201 ahc_force_renegotiation(ahc); 1202 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1203 ahc_freeze_devq(ahc, scb); 1204 } 1205 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1206 ahc_restart(ahc); 1207 } else if ((status & BUSFREE) != 0 1208 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1209 u_int lastphase; 1210 u_int saved_scsiid; 1211 u_int saved_lun; 1212 u_int target; 1213 u_int initiator_role_id; 1214 char channel; 1215 int printerror; 1216 1217 /* 1218 * Clear our selection hardware as soon as possible. 1219 * We may have an entry in the waiting Q for this target, 1220 * that is affected by this busfree and we don't want to 1221 * go about selecting the target while we handle the event. 1222 */ 1223 ahc_outb(ahc, SCSISEQ, 1224 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1225 1226 /* 1227 * Disable busfree interrupts and clear the busfree 1228 * interrupt status. We do this here so that several 1229 * bus transactions occur prior to clearing the SCSIINT 1230 * latch. It can take a bit for the clearing to take effect. 1231 */ 1232 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1233 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1234 1235 /* 1236 * Look at what phase we were last in. 1237 * If its message out, chances are pretty good 1238 * that the busfree was in response to one of 1239 * our abort requests. 1240 */ 1241 lastphase = ahc_inb(ahc, LASTPHASE); 1242 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1243 saved_lun = ahc_inb(ahc, SAVED_LUN); 1244 target = SCSIID_TARGET(ahc, saved_scsiid); 1245 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1246 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1247 printerror = 1; 1248 1249 if (lastphase == P_MESGOUT) { 1250 struct ahc_devinfo devinfo; 1251 u_int tag; 1252 1253 ahc_fetch_devinfo(ahc, &devinfo); 1254 tag = SCB_LIST_NULL; 1255 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1256 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1257 if (ahc->msgout_buf[ahc->msgout_index - 1] 1258 == MSG_ABORT_TAG) 1259 tag = scb->hscb->tag; 1260 ahc_print_path(ahc, scb); 1261 printf("SCB %d - Abort%s Completed.\n", 1262 scb->hscb->tag, tag == SCB_LIST_NULL ? 1263 "" : " Tag"); 1264 ahc_abort_scbs(ahc, target, channel, 1265 saved_lun, tag, 1266 ROLE_INITIATOR, 1267 CAM_REQ_ABORTED); 1268 printerror = 0; 1269 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1270 MSG_BUS_DEV_RESET, TRUE)) { 1271 #ifdef __FreeBSD__ 1272 /* 1273 * Don't mark the user's request for this BDR 1274 * as completing with CAM_BDR_SENT. CAM3 1275 * specifies CAM_REQ_CMP. 1276 */ 1277 if (scb != NULL 1278 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1279 && ahc_match_scb(ahc, scb, target, channel, 1280 CAM_LUN_WILDCARD, 1281 SCB_LIST_NULL, 1282 ROLE_INITIATOR)) { 1283 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1284 } 1285 #endif 1286 ahc_compile_devinfo(&devinfo, 1287 initiator_role_id, 1288 target, 1289 CAM_LUN_WILDCARD, 1290 channel, 1291 ROLE_INITIATOR); 1292 ahc_handle_devreset(ahc, &devinfo, 1293 CAM_BDR_SENT, 1294 "Bus Device Reset", 1295 /*verbose_level*/0); 1296 printerror = 0; 1297 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1298 MSG_EXT_PPR, FALSE)) { 1299 struct ahc_initiator_tinfo *tinfo; 1300 struct ahc_tmode_tstate *tstate; 1301 1302 /* 1303 * PPR Rejected. Try non-ppr negotiation 1304 * and retry command. 1305 */ 1306 tinfo = ahc_fetch_transinfo(ahc, 1307 devinfo.channel, 1308 devinfo.our_scsiid, 1309 devinfo.target, 1310 &tstate); 1311 tinfo->curr.transport_version = 2; 1312 tinfo->goal.transport_version = 2; 1313 tinfo->goal.ppr_options = 0; 1314 ahc_qinfifo_requeue_tail(ahc, scb); 1315 printerror = 0; 1316 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1317 MSG_EXT_WDTR, FALSE) 1318 || ahc_sent_msg(ahc, AHCMSG_EXT, 1319 MSG_EXT_SDTR, FALSE)) { 1320 /* 1321 * Negotiation Rejected. Go-async and 1322 * retry command. 1323 */ 1324 ahc_set_width(ahc, &devinfo, 1325 MSG_EXT_WDTR_BUS_8_BIT, 1326 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1327 /*paused*/TRUE); 1328 ahc_set_syncrate(ahc, &devinfo, 1329 /*syncrate*/NULL, 1330 /*period*/0, /*offset*/0, 1331 /*ppr_options*/0, 1332 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1333 /*paused*/TRUE); 1334 ahc_qinfifo_requeue_tail(ahc, scb); 1335 printerror = 0; 1336 } 1337 } 1338 if (printerror != 0) { 1339 u_int i; 1340 1341 if (scb != NULL) { 1342 u_int tag; 1343 1344 if ((scb->hscb->control & TAG_ENB) != 0) 1345 tag = scb->hscb->tag; 1346 else 1347 tag = SCB_LIST_NULL; 1348 ahc_print_path(ahc, scb); 1349 ahc_abort_scbs(ahc, target, channel, 1350 SCB_GET_LUN(scb), tag, 1351 ROLE_INITIATOR, 1352 CAM_UNEXP_BUSFREE); 1353 } else { 1354 /* 1355 * We had not fully identified this connection, 1356 * so we cannot abort anything. 1357 */ 1358 printf("%s: ", ahc_name(ahc)); 1359 } 1360 for (i = 0; i < num_phases; i++) { 1361 if (lastphase == ahc_phase_table[i].phase) 1362 break; 1363 } 1364 /* 1365 * Renegotiate with this device at the 1366 * next oportunity just in case this busfree 1367 * is due to a negotiation mismatch with the 1368 * device. 1369 */ 1370 ahc_force_renegotiation(ahc); 1371 printf("Unexpected busfree %s\n" 1372 "SEQADDR == 0x%x\n", 1373 ahc_phase_table[i].phasemsg, 1374 ahc_inb(ahc, SEQADDR0) 1375 | (ahc_inb(ahc, SEQADDR1) << 8)); 1376 } 1377 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1378 ahc_restart(ahc); 1379 } else { 1380 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1381 ahc_name(ahc), status); 1382 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1383 } 1384 } 1385 1386 /* 1387 * Force renegotiation to occur the next time we initiate 1388 * a command to the current device. 1389 */ 1390 static void 1391 ahc_force_renegotiation(struct ahc_softc *ahc) 1392 { 1393 struct ahc_devinfo devinfo; 1394 struct ahc_initiator_tinfo *targ_info; 1395 struct ahc_tmode_tstate *tstate; 1396 1397 ahc_fetch_devinfo(ahc, &devinfo); 1398 targ_info = ahc_fetch_transinfo(ahc, 1399 devinfo.channel, 1400 devinfo.our_scsiid, 1401 devinfo.target, 1402 &tstate); 1403 ahc_update_neg_request(ahc, &devinfo, tstate, 1404 targ_info, AHC_NEG_IF_NON_ASYNC); 1405 } 1406 1407 #define AHC_MAX_STEPS 2000 1408 void 1409 ahc_clear_critical_section(struct ahc_softc *ahc) 1410 { 1411 int stepping; 1412 int steps; 1413 u_int simode0; 1414 u_int simode1; 1415 1416 if (ahc->num_critical_sections == 0) 1417 return; 1418 1419 stepping = FALSE; 1420 steps = 0; 1421 simode0 = 0; 1422 simode1 = 0; 1423 for (;;) { 1424 struct cs *cs; 1425 u_int seqaddr; 1426 u_int i; 1427 1428 seqaddr = ahc_inb(ahc, SEQADDR0) 1429 | (ahc_inb(ahc, SEQADDR1) << 8); 1430 1431 /* 1432 * Seqaddr represents the next instruction to execute, 1433 * so we are really executing the instruction just 1434 * before it. 1435 */ 1436 if (seqaddr != 0) 1437 seqaddr -= 1; 1438 cs = ahc->critical_sections; 1439 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1440 1441 if (cs->begin < seqaddr && cs->end >= seqaddr) 1442 break; 1443 } 1444 1445 if (i == ahc->num_critical_sections) 1446 break; 1447 1448 if (steps > AHC_MAX_STEPS) { 1449 printf("%s: Infinite loop in critical section\n", 1450 ahc_name(ahc)); 1451 ahc_dump_card_state(ahc); 1452 panic("critical section loop"); 1453 } 1454 1455 steps++; 1456 if (stepping == FALSE) { 1457 1458 /* 1459 * Disable all interrupt sources so that the 1460 * sequencer will not be stuck by a pausing 1461 * interrupt condition while we attempt to 1462 * leave a critical section. 1463 */ 1464 simode0 = ahc_inb(ahc, SIMODE0); 1465 ahc_outb(ahc, SIMODE0, 0); 1466 simode1 = ahc_inb(ahc, SIMODE1); 1467 if ((ahc->features & AHC_DT) != 0) 1468 /* 1469 * On DT class controllers, we 1470 * use the enhanced busfree logic. 1471 * Unfortunately we cannot re-enable 1472 * busfree detection within the 1473 * current connection, so we must 1474 * leave it on while single stepping. 1475 */ 1476 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1477 else 1478 ahc_outb(ahc, SIMODE1, 0); 1479 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1480 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1481 stepping = TRUE; 1482 } 1483 if ((ahc->features & AHC_DT) != 0) { 1484 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1485 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1486 } 1487 ahc_outb(ahc, HCNTRL, ahc->unpause); 1488 while (!ahc_is_paused(ahc)) 1489 ahc_delay(200); 1490 } 1491 if (stepping) { 1492 ahc_outb(ahc, SIMODE0, simode0); 1493 ahc_outb(ahc, SIMODE1, simode1); 1494 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1495 } 1496 } 1497 1498 /* 1499 * Clear any pending interrupt status. 1500 */ 1501 void 1502 ahc_clear_intstat(struct ahc_softc *ahc) 1503 { 1504 /* Clear any interrupt conditions this may have caused */ 1505 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1506 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1507 CLRREQINIT); 1508 ahc_flush_device_writes(ahc); 1509 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1510 ahc_flush_device_writes(ahc); 1511 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1512 ahc_flush_device_writes(ahc); 1513 } 1514 1515 /**************************** Debugging Routines ******************************/ 1516 #ifdef AHC_DEBUG 1517 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1518 #endif 1519 1520 void 1521 ahc_print_scb(struct scb *scb) 1522 { 1523 int i; 1524 1525 struct hardware_scb *hscb = scb->hscb; 1526 1527 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1528 (void *)scb, 1529 hscb->control, 1530 hscb->scsiid, 1531 hscb->lun, 1532 hscb->cdb_len); 1533 printf("Shared Data: "); 1534 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1535 printf("%#02x", hscb->shared_data.cdb[i]); 1536 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1537 ahc_le32toh(hscb->dataptr), 1538 ahc_le32toh(hscb->datacnt), 1539 ahc_le32toh(hscb->sgptr), 1540 hscb->tag); 1541 if (scb->sg_count > 0) { 1542 for (i = 0; i < scb->sg_count; i++) { 1543 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1544 i, 1545 (ahc_le32toh(scb->sg_list[i].len) >> 24 1546 & SG_HIGH_ADDR_BITS), 1547 ahc_le32toh(scb->sg_list[i].addr), 1548 ahc_le32toh(scb->sg_list[i].len)); 1549 } 1550 } 1551 } 1552 1553 /************************* Transfer Negotiation *******************************/ 1554 /* 1555 * Allocate per target mode instance (ID we respond to as a target) 1556 * transfer negotiation data structures. 1557 */ 1558 static struct ahc_tmode_tstate * 1559 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1560 { 1561 struct ahc_tmode_tstate *master_tstate; 1562 struct ahc_tmode_tstate *tstate; 1563 int i; 1564 1565 master_tstate = ahc->enabled_targets[ahc->our_id]; 1566 if (channel == 'B') { 1567 scsi_id += 8; 1568 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1569 } 1570 if (ahc->enabled_targets[scsi_id] != NULL 1571 && ahc->enabled_targets[scsi_id] != master_tstate) 1572 panic("%s: ahc_alloc_tstate - Target already allocated", 1573 ahc_name(ahc)); 1574 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1575 M_DEVBUF, M_NOWAIT); 1576 if (tstate == NULL) 1577 return (NULL); 1578 1579 /* 1580 * If we have allocated a master tstate, copy user settings from 1581 * the master tstate (taken from SRAM or the EEPROM) for this 1582 * channel, but reset our current and goal settings to async/narrow 1583 * until an initiator talks to us. 1584 */ 1585 if (master_tstate != NULL) { 1586 memcpy(tstate, master_tstate, sizeof(*tstate)); 1587 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1588 tstate->ultraenb = 0; 1589 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1590 memset(&tstate->transinfo[i].curr, 0, 1591 sizeof(tstate->transinfo[i].curr)); 1592 memset(&tstate->transinfo[i].goal, 0, 1593 sizeof(tstate->transinfo[i].goal)); 1594 } 1595 } else 1596 memset(tstate, 0, sizeof(*tstate)); 1597 ahc->enabled_targets[scsi_id] = tstate; 1598 return (tstate); 1599 } 1600 1601 #ifdef AHC_TARGET_MODE 1602 /* 1603 * Free per target mode instance (ID we respond to as a target) 1604 * transfer negotiation data structures. 1605 */ 1606 static void 1607 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1608 { 1609 struct ahc_tmode_tstate *tstate; 1610 1611 /* 1612 * Don't clean up our "master" tstate. 1613 * It has our default user settings. 1614 */ 1615 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1616 || (channel == 'A' && scsi_id == ahc->our_id)) 1617 && force == FALSE) 1618 return; 1619 1620 if (channel == 'B') 1621 scsi_id += 8; 1622 tstate = ahc->enabled_targets[scsi_id]; 1623 if (tstate != NULL) 1624 free(tstate, M_DEVBUF); 1625 ahc->enabled_targets[scsi_id] = NULL; 1626 } 1627 #endif 1628 1629 /* 1630 * Called when we have an active connection to a target on the bus, 1631 * this function finds the nearest syncrate to the input period limited 1632 * by the capabilities of the bus connectivity of and sync settings for 1633 * the target. 1634 */ 1635 struct ahc_syncrate * 1636 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1637 struct ahc_initiator_tinfo *tinfo, 1638 u_int *period, u_int *ppr_options, role_t role) 1639 { 1640 struct ahc_transinfo *transinfo; 1641 u_int maxsync; 1642 1643 if ((ahc->features & AHC_ULTRA2) != 0) { 1644 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1645 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1646 maxsync = AHC_SYNCRATE_DT; 1647 } else { 1648 maxsync = AHC_SYNCRATE_ULTRA; 1649 /* Can't do DT on an SE bus */ 1650 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1651 } 1652 } else if ((ahc->features & AHC_ULTRA) != 0) { 1653 maxsync = AHC_SYNCRATE_ULTRA; 1654 } else { 1655 maxsync = AHC_SYNCRATE_FAST; 1656 } 1657 /* 1658 * Never allow a value higher than our current goal 1659 * period otherwise we may allow a target initiated 1660 * negotiation to go above the limit as set by the 1661 * user. In the case of an initiator initiated 1662 * sync negotiation, we limit based on the user 1663 * setting. This allows the system to still accept 1664 * incoming negotiations even if target initiated 1665 * negotiation is not performed. 1666 */ 1667 if (role == ROLE_TARGET) 1668 transinfo = &tinfo->user; 1669 else 1670 transinfo = &tinfo->goal; 1671 *ppr_options &= transinfo->ppr_options; 1672 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1673 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1674 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1675 } 1676 if (transinfo->period == 0) { 1677 *period = 0; 1678 *ppr_options = 0; 1679 return (NULL); 1680 } 1681 *period = MAX(*period, transinfo->period); 1682 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1683 } 1684 1685 /* 1686 * Look up the valid period to SCSIRATE conversion in our table. 1687 * Return the period and offset that should be sent to the target 1688 * if this was the beginning of an SDTR. 1689 */ 1690 struct ahc_syncrate * 1691 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1692 u_int *ppr_options, u_int maxsync) 1693 { 1694 struct ahc_syncrate *syncrate; 1695 1696 if ((ahc->features & AHC_DT) == 0) 1697 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1698 1699 /* Skip all DT only entries if DT is not available */ 1700 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1701 && maxsync < AHC_SYNCRATE_ULTRA2) 1702 maxsync = AHC_SYNCRATE_ULTRA2; 1703 1704 for (syncrate = &ahc_syncrates[maxsync]; 1705 syncrate->rate != NULL; 1706 syncrate++) { 1707 1708 /* 1709 * The Ultra2 table doesn't go as low 1710 * as for the Fast/Ultra cards. 1711 */ 1712 if ((ahc->features & AHC_ULTRA2) != 0 1713 && (syncrate->sxfr_u2 == 0)) 1714 break; 1715 1716 if (*period <= syncrate->period) { 1717 /* 1718 * When responding to a target that requests 1719 * sync, the requested rate may fall between 1720 * two rates that we can output, but still be 1721 * a rate that we can receive. Because of this, 1722 * we want to respond to the target with 1723 * the same rate that it sent to us even 1724 * if the period we use to send data to it 1725 * is lower. Only lower the response period 1726 * if we must. 1727 */ 1728 if (syncrate == &ahc_syncrates[maxsync]) 1729 *period = syncrate->period; 1730 1731 /* 1732 * At some speeds, we only support 1733 * ST transfers. 1734 */ 1735 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1736 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1737 break; 1738 } 1739 } 1740 1741 if ((*period == 0) 1742 || (syncrate->rate == NULL) 1743 || ((ahc->features & AHC_ULTRA2) != 0 1744 && (syncrate->sxfr_u2 == 0))) { 1745 /* Use asynchronous transfers. */ 1746 *period = 0; 1747 syncrate = NULL; 1748 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1749 } 1750 return (syncrate); 1751 } 1752 1753 /* 1754 * Convert from an entry in our syncrate table to the SCSI equivalent 1755 * sync "period" factor. 1756 */ 1757 u_int 1758 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1759 { 1760 struct ahc_syncrate *syncrate; 1761 1762 if ((ahc->features & AHC_ULTRA2) != 0) 1763 scsirate &= SXFR_ULTRA2; 1764 else 1765 scsirate &= SXFR; 1766 1767 syncrate = &ahc_syncrates[maxsync]; 1768 while (syncrate->rate != NULL) { 1769 1770 if ((ahc->features & AHC_ULTRA2) != 0) { 1771 if (syncrate->sxfr_u2 == 0) 1772 break; 1773 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1774 return (syncrate->period); 1775 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1776 return (syncrate->period); 1777 } 1778 syncrate++; 1779 } 1780 return (0); /* async */ 1781 } 1782 1783 /* 1784 * Truncate the given synchronous offset to a value the 1785 * current adapter type and syncrate are capable of. 1786 */ 1787 void 1788 ahc_validate_offset(struct ahc_softc *ahc, 1789 struct ahc_initiator_tinfo *tinfo, 1790 struct ahc_syncrate *syncrate, 1791 u_int *offset, int wide, role_t role) 1792 { 1793 u_int maxoffset; 1794 1795 /* Limit offset to what we can do */ 1796 if (syncrate == NULL) { 1797 maxoffset = 0; 1798 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1799 maxoffset = MAX_OFFSET_ULTRA2; 1800 } else { 1801 if (wide) 1802 maxoffset = MAX_OFFSET_16BIT; 1803 else 1804 maxoffset = MAX_OFFSET_8BIT; 1805 } 1806 *offset = MIN(*offset, maxoffset); 1807 if (tinfo != NULL) { 1808 if (role == ROLE_TARGET) 1809 *offset = MIN(*offset, tinfo->user.offset); 1810 else 1811 *offset = MIN(*offset, tinfo->goal.offset); 1812 } 1813 } 1814 1815 /* 1816 * Truncate the given transfer width parameter to a value the 1817 * current adapter type is capable of. 1818 */ 1819 void 1820 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1821 u_int *bus_width, role_t role) 1822 { 1823 switch (*bus_width) { 1824 default: 1825 if (ahc->features & AHC_WIDE) { 1826 /* Respond Wide */ 1827 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1828 break; 1829 } 1830 /* FALLTHROUGH */ 1831 case MSG_EXT_WDTR_BUS_8_BIT: 1832 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1833 break; 1834 } 1835 if (tinfo != NULL) { 1836 if (role == ROLE_TARGET) 1837 *bus_width = MIN(tinfo->user.width, *bus_width); 1838 else 1839 *bus_width = MIN(tinfo->goal.width, *bus_width); 1840 } 1841 } 1842 1843 /* 1844 * Update the bitmask of targets for which the controller should 1845 * negotiate with at the next convenient oportunity. This currently 1846 * means the next time we send the initial identify messages for 1847 * a new transaction. 1848 */ 1849 int 1850 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1851 struct ahc_tmode_tstate *tstate, 1852 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1853 { 1854 u_int auto_negotiate_orig; 1855 1856 auto_negotiate_orig = tstate->auto_negotiate; 1857 if (neg_type == AHC_NEG_ALWAYS) { 1858 /* 1859 * Force our "current" settings to be 1860 * unknown so that unless a bus reset 1861 * occurs the need to renegotiate is 1862 * recorded persistently. 1863 */ 1864 if ((ahc->features & AHC_WIDE) != 0) 1865 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1866 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1867 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1868 } 1869 if (tinfo->curr.period != tinfo->goal.period 1870 || tinfo->curr.width != tinfo->goal.width 1871 || tinfo->curr.offset != tinfo->goal.offset 1872 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1873 || (neg_type == AHC_NEG_IF_NON_ASYNC 1874 && (tinfo->goal.offset != 0 1875 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1876 || tinfo->goal.ppr_options != 0))) 1877 tstate->auto_negotiate |= devinfo->target_mask; 1878 else 1879 tstate->auto_negotiate &= ~devinfo->target_mask; 1880 1881 return (auto_negotiate_orig != tstate->auto_negotiate); 1882 } 1883 1884 /* 1885 * Update the user/goal/curr tables of synchronous negotiation 1886 * parameters as well as, in the case of a current or active update, 1887 * any data structures on the host controller. In the case of an 1888 * active update, the specified target is currently talking to us on 1889 * the bus, so the transfer parameter update must take effect 1890 * immediately. 1891 */ 1892 void 1893 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1894 struct ahc_syncrate *syncrate, u_int period, 1895 u_int offset, u_int ppr_options, u_int type, int paused) 1896 { 1897 struct ahc_initiator_tinfo *tinfo; 1898 struct ahc_tmode_tstate *tstate; 1899 u_int old_period; 1900 u_int old_offset; 1901 u_int old_ppr; 1902 int active; 1903 int update_needed; 1904 1905 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1906 update_needed = 0; 1907 1908 if (syncrate == NULL) { 1909 period = 0; 1910 offset = 0; 1911 } 1912 1913 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1914 devinfo->target, &tstate); 1915 1916 if ((type & AHC_TRANS_USER) != 0) { 1917 tinfo->user.period = period; 1918 tinfo->user.offset = offset; 1919 tinfo->user.ppr_options = ppr_options; 1920 } 1921 1922 if ((type & AHC_TRANS_GOAL) != 0) { 1923 tinfo->goal.period = period; 1924 tinfo->goal.offset = offset; 1925 tinfo->goal.ppr_options = ppr_options; 1926 } 1927 1928 old_period = tinfo->curr.period; 1929 old_offset = tinfo->curr.offset; 1930 old_ppr = tinfo->curr.ppr_options; 1931 1932 if ((type & AHC_TRANS_CUR) != 0 1933 && (old_period != period 1934 || old_offset != offset 1935 || old_ppr != ppr_options)) { 1936 u_int scsirate; 1937 1938 update_needed++; 1939 scsirate = tinfo->scsirate; 1940 if ((ahc->features & AHC_ULTRA2) != 0) { 1941 1942 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1943 if (syncrate != NULL) { 1944 scsirate |= syncrate->sxfr_u2; 1945 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1946 scsirate |= ENABLE_CRC; 1947 else 1948 scsirate |= SINGLE_EDGE; 1949 } 1950 } else { 1951 1952 scsirate &= ~(SXFR|SOFS); 1953 /* 1954 * Ensure Ultra mode is set properly for 1955 * this target. 1956 */ 1957 tstate->ultraenb &= ~devinfo->target_mask; 1958 if (syncrate != NULL) { 1959 if (syncrate->sxfr & ULTRA_SXFR) { 1960 tstate->ultraenb |= 1961 devinfo->target_mask; 1962 } 1963 scsirate |= syncrate->sxfr & SXFR; 1964 scsirate |= offset & SOFS; 1965 } 1966 if (active) { 1967 u_int sxfrctl0; 1968 1969 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1970 sxfrctl0 &= ~FAST20; 1971 if (tstate->ultraenb & devinfo->target_mask) 1972 sxfrctl0 |= FAST20; 1973 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1974 } 1975 } 1976 if (active) { 1977 ahc_outb(ahc, SCSIRATE, scsirate); 1978 if ((ahc->features & AHC_ULTRA2) != 0) 1979 ahc_outb(ahc, SCSIOFFSET, offset); 1980 } 1981 1982 tinfo->scsirate = scsirate; 1983 tinfo->curr.period = period; 1984 tinfo->curr.offset = offset; 1985 tinfo->curr.ppr_options = ppr_options; 1986 1987 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1988 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1989 if (bootverbose) { 1990 if (offset != 0) { 1991 printf("%s: target %d synchronous at %sMHz%s, " 1992 "offset = 0x%x\n", ahc_name(ahc), 1993 devinfo->target, syncrate->rate, 1994 (ppr_options & MSG_EXT_PPR_DT_REQ) 1995 ? " DT" : "", offset); 1996 } else { 1997 printf("%s: target %d using " 1998 "asynchronous transfers\n", 1999 ahc_name(ahc), devinfo->target); 2000 } 2001 } 2002 } 2003 2004 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2005 tinfo, AHC_NEG_TO_GOAL); 2006 2007 if (update_needed) 2008 ahc_update_pending_scbs(ahc); 2009 } 2010 2011 /* 2012 * Update the user/goal/curr tables of wide negotiation 2013 * parameters as well as, in the case of a current or active update, 2014 * any data structures on the host controller. In the case of an 2015 * active update, the specified target is currently talking to us on 2016 * the bus, so the transfer parameter update must take effect 2017 * immediately. 2018 */ 2019 void 2020 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2021 u_int width, u_int type, int paused) 2022 { 2023 struct ahc_initiator_tinfo *tinfo; 2024 struct ahc_tmode_tstate *tstate; 2025 u_int oldwidth; 2026 int active; 2027 int update_needed; 2028 2029 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2030 update_needed = 0; 2031 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2032 devinfo->target, &tstate); 2033 2034 if ((type & AHC_TRANS_USER) != 0) 2035 tinfo->user.width = width; 2036 2037 if ((type & AHC_TRANS_GOAL) != 0) 2038 tinfo->goal.width = width; 2039 2040 oldwidth = tinfo->curr.width; 2041 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2042 u_int scsirate; 2043 2044 update_needed++; 2045 scsirate = tinfo->scsirate; 2046 scsirate &= ~WIDEXFER; 2047 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2048 scsirate |= WIDEXFER; 2049 2050 tinfo->scsirate = scsirate; 2051 2052 if (active) 2053 ahc_outb(ahc, SCSIRATE, scsirate); 2054 2055 tinfo->curr.width = width; 2056 2057 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2058 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2059 if (bootverbose) { 2060 printf("%s: target %d using %dbit transfers\n", 2061 ahc_name(ahc), devinfo->target, 2062 8 * (0x01 << width)); 2063 } 2064 } 2065 2066 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2067 tinfo, AHC_NEG_TO_GOAL); 2068 if (update_needed) 2069 ahc_update_pending_scbs(ahc); 2070 } 2071 2072 /* 2073 * Update the current state of tagged queuing for a given target. 2074 */ 2075 void 2076 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2077 ahc_queue_alg alg) 2078 { 2079 ahc_platform_set_tags(ahc, devinfo, alg); 2080 } 2081 2082 /* 2083 * When the transfer settings for a connection change, update any 2084 * in-transit SCBs to contain the new data so the hardware will 2085 * be set correctly during future (re)selections. 2086 */ 2087 static void 2088 ahc_update_pending_scbs(struct ahc_softc *ahc) 2089 { 2090 struct scb *pending_scb; 2091 int pending_scb_count; 2092 int i; 2093 int paused; 2094 u_int saved_scbptr; 2095 2096 /* 2097 * Traverse the pending SCB list and ensure that all of the 2098 * SCBs there have the proper settings. 2099 */ 2100 pending_scb_count = 0; 2101 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2102 struct ahc_devinfo devinfo; 2103 struct hardware_scb *pending_hscb; 2104 struct ahc_initiator_tinfo *tinfo; 2105 struct ahc_tmode_tstate *tstate; 2106 2107 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2108 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2109 devinfo.our_scsiid, 2110 devinfo.target, &tstate); 2111 pending_hscb = pending_scb->hscb; 2112 pending_hscb->control &= ~ULTRAENB; 2113 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2114 pending_hscb->control |= ULTRAENB; 2115 pending_hscb->scsirate = tinfo->scsirate; 2116 pending_hscb->scsioffset = tinfo->curr.offset; 2117 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2118 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2119 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2120 pending_hscb->control &= ~MK_MESSAGE; 2121 } 2122 ahc_sync_scb(ahc, pending_scb, 2123 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2124 pending_scb_count++; 2125 } 2126 2127 if (pending_scb_count == 0) 2128 return; 2129 2130 if (ahc_is_paused(ahc)) { 2131 paused = 1; 2132 } else { 2133 paused = 0; 2134 ahc_pause(ahc); 2135 } 2136 2137 saved_scbptr = ahc_inb(ahc, SCBPTR); 2138 /* Ensure that the hscbs down on the card match the new information */ 2139 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2140 struct hardware_scb *pending_hscb; 2141 u_int control; 2142 u_int scb_tag; 2143 2144 ahc_outb(ahc, SCBPTR, i); 2145 scb_tag = ahc_inb(ahc, SCB_TAG); 2146 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2147 if (pending_scb == NULL) 2148 continue; 2149 2150 pending_hscb = pending_scb->hscb; 2151 control = ahc_inb(ahc, SCB_CONTROL); 2152 control &= ~(ULTRAENB|MK_MESSAGE); 2153 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2154 ahc_outb(ahc, SCB_CONTROL, control); 2155 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2156 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2157 } 2158 ahc_outb(ahc, SCBPTR, saved_scbptr); 2159 2160 if (paused == 0) 2161 ahc_unpause(ahc); 2162 } 2163 2164 /**************************** Pathing Information *****************************/ 2165 static void 2166 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2167 { 2168 u_int saved_scsiid; 2169 role_t role; 2170 int our_id; 2171 2172 if (ahc_inb(ahc, SSTAT0) & TARGET) 2173 role = ROLE_TARGET; 2174 else 2175 role = ROLE_INITIATOR; 2176 2177 if (role == ROLE_TARGET 2178 && (ahc->features & AHC_MULTI_TID) != 0 2179 && (ahc_inb(ahc, SEQ_FLAGS) 2180 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2181 /* We were selected, so pull our id from TARGIDIN */ 2182 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2183 } else if ((ahc->features & AHC_ULTRA2) != 0) 2184 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2185 else 2186 our_id = ahc_inb(ahc, SCSIID) & OID; 2187 2188 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2189 ahc_compile_devinfo(devinfo, 2190 our_id, 2191 SCSIID_TARGET(ahc, saved_scsiid), 2192 ahc_inb(ahc, SAVED_LUN), 2193 SCSIID_CHANNEL(ahc, saved_scsiid), 2194 role); 2195 } 2196 2197 struct ahc_phase_table_entry* 2198 ahc_lookup_phase_entry(int phase) 2199 { 2200 struct ahc_phase_table_entry *entry; 2201 struct ahc_phase_table_entry *last_entry; 2202 2203 /* 2204 * num_phases doesn't include the default entry which 2205 * will be returned if the phase doesn't match. 2206 */ 2207 last_entry = &ahc_phase_table[num_phases]; 2208 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2209 if (phase == entry->phase) 2210 break; 2211 } 2212 return (entry); 2213 } 2214 2215 void 2216 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2217 u_int lun, char channel, role_t role) 2218 { 2219 devinfo->our_scsiid = our_id; 2220 devinfo->target = target; 2221 devinfo->lun = lun; 2222 devinfo->target_offset = target; 2223 devinfo->channel = channel; 2224 devinfo->role = role; 2225 if (channel == 'B') 2226 devinfo->target_offset += 8; 2227 devinfo->target_mask = (0x01 << devinfo->target_offset); 2228 } 2229 2230 void 2231 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2232 { 2233 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2234 devinfo->target, devinfo->lun); 2235 } 2236 2237 static void 2238 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2239 struct scb *scb) 2240 { 2241 role_t role; 2242 int our_id; 2243 2244 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2245 role = ROLE_INITIATOR; 2246 if ((scb->flags & SCB_TARGET_SCB) != 0) 2247 role = ROLE_TARGET; 2248 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2249 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2250 } 2251 2252 2253 /************************ Message Phase Processing ****************************/ 2254 static void 2255 ahc_assert_atn(struct ahc_softc *ahc) 2256 { 2257 u_int scsisigo; 2258 2259 scsisigo = ATNO; 2260 if ((ahc->features & AHC_DT) == 0) 2261 scsisigo |= ahc_inb(ahc, SCSISIGI); 2262 ahc_outb(ahc, SCSISIGO, scsisigo); 2263 } 2264 2265 /* 2266 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2267 * or enters the initial message out phase, we are interrupted. Fill our 2268 * outgoing message buffer with the appropriate message and beging handing 2269 * the message phase(s) manually. 2270 */ 2271 static void 2272 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2273 struct scb *scb) 2274 { 2275 /* 2276 * To facilitate adding multiple messages together, 2277 * each routine should increment the index and len 2278 * variables instead of setting them explicitly. 2279 */ 2280 ahc->msgout_index = 0; 2281 ahc->msgout_len = 0; 2282 2283 if ((scb->flags & SCB_DEVICE_RESET) == 0 2284 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2285 u_int identify_msg; 2286 2287 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2288 if ((scb->hscb->control & DISCENB) != 0) 2289 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2290 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2291 ahc->msgout_len++; 2292 2293 if ((scb->hscb->control & TAG_ENB) != 0) { 2294 ahc->msgout_buf[ahc->msgout_index++] = 2295 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2296 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2297 ahc->msgout_len += 2; 2298 } 2299 } 2300 2301 if (scb->flags & SCB_DEVICE_RESET) { 2302 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2303 ahc->msgout_len++; 2304 ahc_print_path(ahc, scb); 2305 printf("Bus Device Reset Message Sent\n"); 2306 /* 2307 * Clear our selection hardware in advance of 2308 * the busfree. We may have an entry in the waiting 2309 * Q for this target, and we don't want to go about 2310 * selecting while we handle the busfree and blow it 2311 * away. 2312 */ 2313 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2314 } else if ((scb->flags & SCB_ABORT) != 0) { 2315 if ((scb->hscb->control & TAG_ENB) != 0) 2316 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2317 else 2318 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2319 ahc->msgout_len++; 2320 ahc_print_path(ahc, scb); 2321 printf("Abort%s Message Sent\n", 2322 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2323 /* 2324 * Clear our selection hardware in advance of 2325 * the busfree. We may have an entry in the waiting 2326 * Q for this target, and we don't want to go about 2327 * selecting while we handle the busfree and blow it 2328 * away. 2329 */ 2330 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2331 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2332 ahc_build_transfer_msg(ahc, devinfo); 2333 } else { 2334 printf("ahc_intr: AWAITING_MSG for an SCB that " 2335 "does not have a waiting message\n"); 2336 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2337 devinfo->target_mask); 2338 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2339 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2340 ahc_inb(ahc, MSG_OUT), scb->flags); 2341 } 2342 2343 /* 2344 * Clear the MK_MESSAGE flag from the SCB so we aren't 2345 * asked to send this message again. 2346 */ 2347 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2348 scb->hscb->control &= ~MK_MESSAGE; 2349 ahc->msgout_index = 0; 2350 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2351 } 2352 2353 /* 2354 * Build an appropriate transfer negotiation message for the 2355 * currently active target. 2356 */ 2357 static void 2358 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2359 { 2360 /* 2361 * We need to initiate transfer negotiations. 2362 * If our current and goal settings are identical, 2363 * we want to renegotiate due to a check condition. 2364 */ 2365 struct ahc_initiator_tinfo *tinfo; 2366 struct ahc_tmode_tstate *tstate; 2367 struct ahc_syncrate *rate; 2368 int dowide; 2369 int dosync; 2370 int doppr; 2371 u_int period; 2372 u_int ppr_options; 2373 u_int offset; 2374 2375 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2376 devinfo->target, &tstate); 2377 /* 2378 * Filter our period based on the current connection. 2379 * If we can't perform DT transfers on this segment (not in LVD 2380 * mode for instance), then our decision to issue a PPR message 2381 * may change. 2382 */ 2383 period = tinfo->goal.period; 2384 ppr_options = tinfo->goal.ppr_options; 2385 /* Target initiated PPR is not allowed in the SCSI spec */ 2386 if (devinfo->role == ROLE_TARGET) 2387 ppr_options = 0; 2388 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2389 &ppr_options, devinfo->role); 2390 dowide = tinfo->curr.width != tinfo->goal.width; 2391 dosync = tinfo->curr.period != period; 2392 /* 2393 * Only use PPR if we have options that need it, even if the device 2394 * claims to support it. There might be an expander in the way 2395 * that doesn't. 2396 */ 2397 doppr = ppr_options != 0; 2398 2399 if (!dowide && !dosync && !doppr) { 2400 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2401 dosync = tinfo->goal.offset != 0; 2402 } 2403 2404 if (!dowide && !dosync && !doppr) { 2405 /* 2406 * Force async with a WDTR message if we have a wide bus, 2407 * or just issue an SDTR with a 0 offset. 2408 */ 2409 if ((ahc->features & AHC_WIDE) != 0) 2410 dowide = 1; 2411 else 2412 dosync = 1; 2413 2414 if (bootverbose) { 2415 ahc_print_devinfo(ahc, devinfo); 2416 printf("Ensuring async\n"); 2417 } 2418 } 2419 2420 /* Target initiated PPR is not allowed in the SCSI spec */ 2421 if (devinfo->role == ROLE_TARGET) 2422 doppr = 0; 2423 2424 /* 2425 * Both the PPR message and SDTR message require the 2426 * goal syncrate to be limited to what the target device 2427 * is capable of handling (based on whether an LVD->SE 2428 * expander is on the bus), so combine these two cases. 2429 * Regardless, guarantee that if we are using WDTR and SDTR 2430 * messages that WDTR comes first. 2431 */ 2432 if (doppr || (dosync && !dowide)) { 2433 2434 offset = tinfo->goal.offset; 2435 ahc_validate_offset(ahc, tinfo, rate, &offset, 2436 doppr ? tinfo->goal.width 2437 : tinfo->curr.width, 2438 devinfo->role); 2439 if (doppr) { 2440 ahc_construct_ppr(ahc, devinfo, period, offset, 2441 tinfo->goal.width, ppr_options); 2442 } else { 2443 ahc_construct_sdtr(ahc, devinfo, period, offset); 2444 } 2445 } else { 2446 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2447 } 2448 } 2449 2450 /* 2451 * Build a synchronous negotiation message in our message 2452 * buffer based on the input parameters. 2453 */ 2454 static void 2455 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2456 u_int period, u_int offset) 2457 { 2458 if (offset == 0) 2459 period = AHC_ASYNC_XFER_PERIOD; 2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2462 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2463 ahc->msgout_buf[ahc->msgout_index++] = period; 2464 ahc->msgout_buf[ahc->msgout_index++] = offset; 2465 ahc->msgout_len += 5; 2466 if (bootverbose) { 2467 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2468 ahc_name(ahc), devinfo->channel, devinfo->target, 2469 devinfo->lun, period, offset); 2470 } 2471 } 2472 2473 /* 2474 * Build a wide negotiation message in our message 2475 * buffer based on the input parameters. 2476 */ 2477 static void 2478 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2479 u_int bus_width) 2480 { 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2483 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2484 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2485 ahc->msgout_len += 4; 2486 if (bootverbose) { 2487 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2488 ahc_name(ahc), devinfo->channel, devinfo->target, 2489 devinfo->lun, bus_width); 2490 } 2491 } 2492 2493 /* 2494 * Build a parallel protocol request message in our message 2495 * buffer based on the input parameters. 2496 */ 2497 static void 2498 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2499 u_int period, u_int offset, u_int bus_width, 2500 u_int ppr_options) 2501 { 2502 if (offset == 0) 2503 period = AHC_ASYNC_XFER_PERIOD; 2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2506 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2507 ahc->msgout_buf[ahc->msgout_index++] = period; 2508 ahc->msgout_buf[ahc->msgout_index++] = 0; 2509 ahc->msgout_buf[ahc->msgout_index++] = offset; 2510 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2511 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2512 ahc->msgout_len += 8; 2513 if (bootverbose) { 2514 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2515 "offset %x, ppr_options %x\n", ahc_name(ahc), 2516 devinfo->channel, devinfo->target, devinfo->lun, 2517 bus_width, period, offset, ppr_options); 2518 } 2519 } 2520 2521 /* 2522 * Clear any active message state. 2523 */ 2524 static void 2525 ahc_clear_msg_state(struct ahc_softc *ahc) 2526 { 2527 ahc->msgout_len = 0; 2528 ahc->msgin_index = 0; 2529 ahc->msg_type = MSG_TYPE_NONE; 2530 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2531 /* 2532 * The target didn't care to respond to our 2533 * message request, so clear ATN. 2534 */ 2535 ahc_outb(ahc, CLRSINT1, CLRATNO); 2536 } 2537 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2538 ahc_outb(ahc, SEQ_FLAGS2, 2539 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2540 } 2541 2542 static void 2543 ahc_handle_proto_violation(struct ahc_softc *ahc) 2544 { 2545 struct ahc_devinfo devinfo; 2546 struct scb *scb; 2547 u_int scbid; 2548 u_int seq_flags; 2549 u_int curphase; 2550 u_int lastphase; 2551 int found; 2552 2553 ahc_fetch_devinfo(ahc, &devinfo); 2554 scbid = ahc_inb(ahc, SCB_TAG); 2555 scb = ahc_lookup_scb(ahc, scbid); 2556 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2557 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2558 lastphase = ahc_inb(ahc, LASTPHASE); 2559 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2560 2561 /* 2562 * The reconnecting target either did not send an 2563 * identify message, or did, but we didn't find an SCB 2564 * to match. 2565 */ 2566 ahc_print_devinfo(ahc, &devinfo); 2567 printf("Target did not send an IDENTIFY message. " 2568 "LASTPHASE = 0x%x.\n", lastphase); 2569 scb = NULL; 2570 } else if (scb == NULL) { 2571 /* 2572 * We don't seem to have an SCB active for this 2573 * transaction. Print an error and reset the bus. 2574 */ 2575 ahc_print_devinfo(ahc, &devinfo); 2576 printf("No SCB found during protocol violation\n"); 2577 goto proto_violation_reset; 2578 } else { 2579 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2580 if ((seq_flags & NO_CDB_SENT) != 0) { 2581 ahc_print_path(ahc, scb); 2582 printf("No or incomplete CDB sent to device.\n"); 2583 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2584 /* 2585 * The target never bothered to provide status to 2586 * us prior to completing the command. Since we don't 2587 * know the disposition of this command, we must attempt 2588 * to abort it. Assert ATN and prepare to send an abort 2589 * message. 2590 */ 2591 ahc_print_path(ahc, scb); 2592 printf("Completed command without status.\n"); 2593 } else { 2594 ahc_print_path(ahc, scb); 2595 printf("Unknown protocol violation.\n"); 2596 ahc_dump_card_state(ahc); 2597 } 2598 } 2599 if ((lastphase & ~P_DATAIN_DT) == 0 2600 || lastphase == P_COMMAND) { 2601 proto_violation_reset: 2602 /* 2603 * Target either went directly to data/command 2604 * phase or didn't respond to our ATN. 2605 * The only safe thing to do is to blow 2606 * it away with a bus reset. 2607 */ 2608 found = ahc_reset_channel(ahc, 'A', TRUE); 2609 printf("%s: Issued Channel %c Bus Reset. " 2610 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2611 } else { 2612 /* 2613 * Leave the selection hardware off in case 2614 * this abort attempt will affect yet to 2615 * be sent commands. 2616 */ 2617 ahc_outb(ahc, SCSISEQ, 2618 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2619 ahc_assert_atn(ahc); 2620 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2621 if (scb == NULL) { 2622 ahc_print_devinfo(ahc, &devinfo); 2623 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2624 ahc->msgout_len = 1; 2625 ahc->msgout_index = 0; 2626 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2627 } else { 2628 ahc_print_path(ahc, scb); 2629 scb->flags |= SCB_ABORT; 2630 } 2631 printf("Protocol violation %s. Attempting to abort.\n", 2632 ahc_lookup_phase_entry(curphase)->phasemsg); 2633 } 2634 } 2635 2636 /* 2637 * Manual message loop handler. 2638 */ 2639 static void 2640 ahc_handle_message_phase(struct ahc_softc *ahc) 2641 { 2642 struct ahc_devinfo devinfo; 2643 u_int bus_phase; 2644 int end_session; 2645 2646 ahc_fetch_devinfo(ahc, &devinfo); 2647 end_session = FALSE; 2648 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2649 2650 reswitch: 2651 switch (ahc->msg_type) { 2652 case MSG_TYPE_INITIATOR_MSGOUT: 2653 { 2654 int lastbyte; 2655 int phasemis; 2656 int msgdone; 2657 2658 if (ahc->msgout_len == 0) 2659 panic("HOST_MSG_LOOP interrupt with no active message"); 2660 2661 #ifdef AHC_DEBUG 2662 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2663 ahc_print_devinfo(ahc, &devinfo); 2664 printf("INITIATOR_MSG_OUT"); 2665 } 2666 #endif 2667 phasemis = bus_phase != P_MESGOUT; 2668 if (phasemis) { 2669 #ifdef AHC_DEBUG 2670 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2671 printf(" PHASEMIS %s\n", 2672 ahc_lookup_phase_entry(bus_phase) 2673 ->phasemsg); 2674 } 2675 #endif 2676 if (bus_phase == P_MESGIN) { 2677 /* 2678 * Change gears and see if 2679 * this messages is of interest to 2680 * us or should be passed back to 2681 * the sequencer. 2682 */ 2683 ahc_outb(ahc, CLRSINT1, CLRATNO); 2684 ahc->send_msg_perror = FALSE; 2685 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2686 ahc->msgin_index = 0; 2687 goto reswitch; 2688 } 2689 end_session = TRUE; 2690 break; 2691 } 2692 2693 if (ahc->send_msg_perror) { 2694 ahc_outb(ahc, CLRSINT1, CLRATNO); 2695 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2696 #ifdef AHC_DEBUG 2697 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2698 printf(" byte 0x%x\n", ahc->send_msg_perror); 2699 #endif 2700 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2701 break; 2702 } 2703 2704 msgdone = ahc->msgout_index == ahc->msgout_len; 2705 if (msgdone) { 2706 /* 2707 * The target has requested a retry. 2708 * Re-assert ATN, reset our message index to 2709 * 0, and try again. 2710 */ 2711 ahc->msgout_index = 0; 2712 ahc_assert_atn(ahc); 2713 } 2714 2715 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2716 if (lastbyte) { 2717 /* Last byte is signified by dropping ATN */ 2718 ahc_outb(ahc, CLRSINT1, CLRATNO); 2719 } 2720 2721 /* 2722 * Clear our interrupt status and present 2723 * the next byte on the bus. 2724 */ 2725 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2726 #ifdef AHC_DEBUG 2727 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2728 printf(" byte 0x%x\n", 2729 ahc->msgout_buf[ahc->msgout_index]); 2730 #endif 2731 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2732 break; 2733 } 2734 case MSG_TYPE_INITIATOR_MSGIN: 2735 { 2736 int phasemis; 2737 int message_done; 2738 2739 #ifdef AHC_DEBUG 2740 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2741 ahc_print_devinfo(ahc, &devinfo); 2742 printf("INITIATOR_MSG_IN"); 2743 } 2744 #endif 2745 phasemis = bus_phase != P_MESGIN; 2746 if (phasemis) { 2747 #ifdef AHC_DEBUG 2748 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2749 printf(" PHASEMIS %s\n", 2750 ahc_lookup_phase_entry(bus_phase) 2751 ->phasemsg); 2752 } 2753 #endif 2754 ahc->msgin_index = 0; 2755 if (bus_phase == P_MESGOUT 2756 && (ahc->send_msg_perror == TRUE 2757 || (ahc->msgout_len != 0 2758 && ahc->msgout_index == 0))) { 2759 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2760 goto reswitch; 2761 } 2762 end_session = TRUE; 2763 break; 2764 } 2765 2766 /* Pull the byte in without acking it */ 2767 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2768 #ifdef AHC_DEBUG 2769 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2770 printf(" byte 0x%x\n", 2771 ahc->msgin_buf[ahc->msgin_index]); 2772 #endif 2773 2774 message_done = ahc_parse_msg(ahc, &devinfo); 2775 2776 if (message_done) { 2777 /* 2778 * Clear our incoming message buffer in case there 2779 * is another message following this one. 2780 */ 2781 ahc->msgin_index = 0; 2782 2783 /* 2784 * If this message illicited a response, 2785 * assert ATN so the target takes us to the 2786 * message out phase. 2787 */ 2788 if (ahc->msgout_len != 0) { 2789 #ifdef AHC_DEBUG 2790 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2791 ahc_print_devinfo(ahc, &devinfo); 2792 printf("Asserting ATN for response\n"); 2793 } 2794 #endif 2795 ahc_assert_atn(ahc); 2796 } 2797 } else 2798 ahc->msgin_index++; 2799 2800 if (message_done == MSGLOOP_TERMINATED) { 2801 end_session = TRUE; 2802 } else { 2803 /* Ack the byte */ 2804 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2805 ahc_inb(ahc, SCSIDATL); 2806 } 2807 break; 2808 } 2809 case MSG_TYPE_TARGET_MSGIN: 2810 { 2811 int msgdone; 2812 int msgout_request; 2813 2814 if (ahc->msgout_len == 0) 2815 panic("Target MSGIN with no active message"); 2816 2817 /* 2818 * If we interrupted a mesgout session, the initiator 2819 * will not know this until our first REQ. So, we 2820 * only honor mesgout requests after we've sent our 2821 * first byte. 2822 */ 2823 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2824 && ahc->msgout_index > 0) 2825 msgout_request = TRUE; 2826 else 2827 msgout_request = FALSE; 2828 2829 if (msgout_request) { 2830 2831 /* 2832 * Change gears and see if 2833 * this messages is of interest to 2834 * us or should be passed back to 2835 * the sequencer. 2836 */ 2837 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2838 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2839 ahc->msgin_index = 0; 2840 /* Dummy read to REQ for first byte */ 2841 ahc_inb(ahc, SCSIDATL); 2842 ahc_outb(ahc, SXFRCTL0, 2843 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2844 break; 2845 } 2846 2847 msgdone = ahc->msgout_index == ahc->msgout_len; 2848 if (msgdone) { 2849 ahc_outb(ahc, SXFRCTL0, 2850 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2851 end_session = TRUE; 2852 break; 2853 } 2854 2855 /* 2856 * Present the next byte on the bus. 2857 */ 2858 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2859 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2860 break; 2861 } 2862 case MSG_TYPE_TARGET_MSGOUT: 2863 { 2864 int lastbyte; 2865 int msgdone; 2866 2867 /* 2868 * The initiator signals that this is 2869 * the last byte by dropping ATN. 2870 */ 2871 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2872 2873 /* 2874 * Read the latched byte, but turn off SPIOEN first 2875 * so that we don't inadvertently cause a REQ for the 2876 * next byte. 2877 */ 2878 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2879 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2880 msgdone = ahc_parse_msg(ahc, &devinfo); 2881 if (msgdone == MSGLOOP_TERMINATED) { 2882 /* 2883 * The message is *really* done in that it caused 2884 * us to go to bus free. The sequencer has already 2885 * been reset at this point, so pull the ejection 2886 * handle. 2887 */ 2888 return; 2889 } 2890 2891 ahc->msgin_index++; 2892 2893 /* 2894 * XXX Read spec about initiator dropping ATN too soon 2895 * and use msgdone to detect it. 2896 */ 2897 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2898 ahc->msgin_index = 0; 2899 2900 /* 2901 * If this message illicited a response, transition 2902 * to the Message in phase and send it. 2903 */ 2904 if (ahc->msgout_len != 0) { 2905 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2906 ahc_outb(ahc, SXFRCTL0, 2907 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2908 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2909 ahc->msgin_index = 0; 2910 break; 2911 } 2912 } 2913 2914 if (lastbyte) 2915 end_session = TRUE; 2916 else { 2917 /* Ask for the next byte. */ 2918 ahc_outb(ahc, SXFRCTL0, 2919 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2920 } 2921 2922 break; 2923 } 2924 default: 2925 panic("Unknown REQINIT message type"); 2926 } 2927 2928 if (end_session) { 2929 ahc_clear_msg_state(ahc); 2930 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2931 } else 2932 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2933 } 2934 2935 /* 2936 * See if we sent a particular extended message to the target. 2937 * If "full" is true, return true only if the target saw the full 2938 * message. If "full" is false, return true if the target saw at 2939 * least the first byte of the message. 2940 */ 2941 static int 2942 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2943 { 2944 int found; 2945 u_int index; 2946 2947 found = FALSE; 2948 index = 0; 2949 2950 while (index < ahc->msgout_len) { 2951 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2952 u_int end_index; 2953 2954 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2955 if (ahc->msgout_buf[index+2] == msgval 2956 && type == AHCMSG_EXT) { 2957 2958 if (full) { 2959 if (ahc->msgout_index > end_index) 2960 found = TRUE; 2961 } else if (ahc->msgout_index > index) 2962 found = TRUE; 2963 } 2964 index = end_index; 2965 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2966 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2967 2968 /* Skip tag type and tag id or residue param*/ 2969 index += 2; 2970 } else { 2971 /* Single byte message */ 2972 if (type == AHCMSG_1B 2973 && ahc->msgout_buf[index] == msgval 2974 && ahc->msgout_index > index) 2975 found = TRUE; 2976 index++; 2977 } 2978 2979 if (found) 2980 break; 2981 } 2982 return (found); 2983 } 2984 2985 /* 2986 * Wait for a complete incoming message, parse it, and respond accordingly. 2987 */ 2988 static int 2989 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2990 { 2991 struct ahc_initiator_tinfo *tinfo; 2992 struct ahc_tmode_tstate *tstate; 2993 int reject; 2994 int done; 2995 int response; 2996 u_int targ_scsirate; 2997 2998 done = MSGLOOP_IN_PROG; 2999 response = FALSE; 3000 reject = FALSE; 3001 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3002 devinfo->target, &tstate); 3003 targ_scsirate = tinfo->scsirate; 3004 3005 /* 3006 * Parse as much of the message as is availible, 3007 * rejecting it if we don't support it. When 3008 * the entire message is availible and has been 3009 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3010 * that we have parsed an entire message. 3011 * 3012 * In the case of extended messages, we accept the length 3013 * byte outright and perform more checking once we know the 3014 * extended message type. 3015 */ 3016 switch (ahc->msgin_buf[0]) { 3017 case MSG_DISCONNECT: 3018 case MSG_SAVEDATAPOINTER: 3019 case MSG_CMDCOMPLETE: 3020 case MSG_RESTOREPOINTERS: 3021 case MSG_IGN_WIDE_RESIDUE: 3022 /* 3023 * End our message loop as these are messages 3024 * the sequencer handles on its own. 3025 */ 3026 done = MSGLOOP_TERMINATED; 3027 break; 3028 case MSG_MESSAGE_REJECT: 3029 response = ahc_handle_msg_reject(ahc, devinfo); 3030 /* FALLTHROUGH */ 3031 case MSG_NOOP: 3032 done = MSGLOOP_MSGCOMPLETE; 3033 break; 3034 case MSG_EXTENDED: 3035 { 3036 /* Wait for enough of the message to begin validation */ 3037 if (ahc->msgin_index < 2) 3038 break; 3039 switch (ahc->msgin_buf[2]) { 3040 case MSG_EXT_SDTR: 3041 { 3042 struct ahc_syncrate *syncrate; 3043 u_int period; 3044 u_int ppr_options; 3045 u_int offset; 3046 u_int saved_offset; 3047 3048 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3049 reject = TRUE; 3050 break; 3051 } 3052 3053 /* 3054 * Wait until we have both args before validating 3055 * and acting on this message. 3056 * 3057 * Add one to MSG_EXT_SDTR_LEN to account for 3058 * the extended message preamble. 3059 */ 3060 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3061 break; 3062 3063 period = ahc->msgin_buf[3]; 3064 ppr_options = 0; 3065 saved_offset = offset = ahc->msgin_buf[4]; 3066 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3067 &ppr_options, 3068 devinfo->role); 3069 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3070 targ_scsirate & WIDEXFER, 3071 devinfo->role); 3072 if (bootverbose) { 3073 printf("(%s:%c:%d:%d): Received " 3074 "SDTR period %x, offset %x\n\t" 3075 "Filtered to period %x, offset %x\n", 3076 ahc_name(ahc), devinfo->channel, 3077 devinfo->target, devinfo->lun, 3078 ahc->msgin_buf[3], saved_offset, 3079 period, offset); 3080 } 3081 ahc_set_syncrate(ahc, devinfo, 3082 syncrate, period, 3083 offset, ppr_options, 3084 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3085 /*paused*/TRUE); 3086 3087 /* 3088 * See if we initiated Sync Negotiation 3089 * and didn't have to fall down to async 3090 * transfers. 3091 */ 3092 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3093 /* We started it */ 3094 if (saved_offset != offset) { 3095 /* Went too low - force async */ 3096 reject = TRUE; 3097 } 3098 } else { 3099 /* 3100 * Send our own SDTR in reply 3101 */ 3102 if (bootverbose 3103 && devinfo->role == ROLE_INITIATOR) { 3104 printf("(%s:%c:%d:%d): Target " 3105 "Initiated SDTR\n", 3106 ahc_name(ahc), devinfo->channel, 3107 devinfo->target, devinfo->lun); 3108 } 3109 ahc->msgout_index = 0; 3110 ahc->msgout_len = 0; 3111 ahc_construct_sdtr(ahc, devinfo, 3112 period, offset); 3113 ahc->msgout_index = 0; 3114 response = TRUE; 3115 } 3116 done = MSGLOOP_MSGCOMPLETE; 3117 break; 3118 } 3119 case MSG_EXT_WDTR: 3120 { 3121 u_int bus_width; 3122 u_int saved_width; 3123 u_int sending_reply; 3124 3125 sending_reply = FALSE; 3126 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3127 reject = TRUE; 3128 break; 3129 } 3130 3131 /* 3132 * Wait until we have our arg before validating 3133 * and acting on this message. 3134 * 3135 * Add one to MSG_EXT_WDTR_LEN to account for 3136 * the extended message preamble. 3137 */ 3138 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3139 break; 3140 3141 bus_width = ahc->msgin_buf[3]; 3142 saved_width = bus_width; 3143 ahc_validate_width(ahc, tinfo, &bus_width, 3144 devinfo->role); 3145 if (bootverbose) { 3146 printf("(%s:%c:%d:%d): Received WDTR " 3147 "%x filtered to %x\n", 3148 ahc_name(ahc), devinfo->channel, 3149 devinfo->target, devinfo->lun, 3150 saved_width, bus_width); 3151 } 3152 3153 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3154 /* 3155 * Don't send a WDTR back to the 3156 * target, since we asked first. 3157 * If the width went higher than our 3158 * request, reject it. 3159 */ 3160 if (saved_width > bus_width) { 3161 reject = TRUE; 3162 printf("(%s:%c:%d:%d): requested %dBit " 3163 "transfers. Rejecting...\n", 3164 ahc_name(ahc), devinfo->channel, 3165 devinfo->target, devinfo->lun, 3166 8 * (0x01 << bus_width)); 3167 bus_width = 0; 3168 } 3169 } else { 3170 /* 3171 * Send our own WDTR in reply 3172 */ 3173 if (bootverbose 3174 && devinfo->role == ROLE_INITIATOR) { 3175 printf("(%s:%c:%d:%d): Target " 3176 "Initiated WDTR\n", 3177 ahc_name(ahc), devinfo->channel, 3178 devinfo->target, devinfo->lun); 3179 } 3180 ahc->msgout_index = 0; 3181 ahc->msgout_len = 0; 3182 ahc_construct_wdtr(ahc, devinfo, bus_width); 3183 ahc->msgout_index = 0; 3184 response = TRUE; 3185 sending_reply = TRUE; 3186 } 3187 ahc_set_width(ahc, devinfo, bus_width, 3188 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3189 /*paused*/TRUE); 3190 /* After a wide message, we are async */ 3191 ahc_set_syncrate(ahc, devinfo, 3192 /*syncrate*/NULL, /*period*/0, 3193 /*offset*/0, /*ppr_options*/0, 3194 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3195 if (sending_reply == FALSE && reject == FALSE) { 3196 3197 if (tinfo->goal.offset) { 3198 ahc->msgout_index = 0; 3199 ahc->msgout_len = 0; 3200 ahc_build_transfer_msg(ahc, devinfo); 3201 ahc->msgout_index = 0; 3202 response = TRUE; 3203 } 3204 } 3205 done = MSGLOOP_MSGCOMPLETE; 3206 break; 3207 } 3208 case MSG_EXT_PPR: 3209 { 3210 struct ahc_syncrate *syncrate; 3211 u_int period; 3212 u_int offset; 3213 u_int bus_width; 3214 u_int ppr_options; 3215 u_int saved_width; 3216 u_int saved_offset; 3217 u_int saved_ppr_options; 3218 3219 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3220 reject = TRUE; 3221 break; 3222 } 3223 3224 /* 3225 * Wait until we have all args before validating 3226 * and acting on this message. 3227 * 3228 * Add one to MSG_EXT_PPR_LEN to account for 3229 * the extended message preamble. 3230 */ 3231 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3232 break; 3233 3234 period = ahc->msgin_buf[3]; 3235 offset = ahc->msgin_buf[5]; 3236 bus_width = ahc->msgin_buf[6]; 3237 saved_width = bus_width; 3238 ppr_options = ahc->msgin_buf[7]; 3239 /* 3240 * According to the spec, a DT only 3241 * period factor with no DT option 3242 * set implies async. 3243 */ 3244 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3245 && period == 9) 3246 offset = 0; 3247 saved_ppr_options = ppr_options; 3248 saved_offset = offset; 3249 3250 /* 3251 * Mask out any options we don't support 3252 * on any controller. Transfer options are 3253 * only available if we are negotiating wide. 3254 */ 3255 ppr_options &= MSG_EXT_PPR_DT_REQ; 3256 if (bus_width == 0) 3257 ppr_options = 0; 3258 3259 ahc_validate_width(ahc, tinfo, &bus_width, 3260 devinfo->role); 3261 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3262 &ppr_options, 3263 devinfo->role); 3264 ahc_validate_offset(ahc, tinfo, syncrate, 3265 &offset, bus_width, 3266 devinfo->role); 3267 3268 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3269 /* 3270 * If we are unable to do any of the 3271 * requested options (we went too low), 3272 * then we'll have to reject the message. 3273 */ 3274 if (saved_width > bus_width 3275 || saved_offset != offset 3276 || saved_ppr_options != ppr_options) { 3277 reject = TRUE; 3278 period = 0; 3279 offset = 0; 3280 bus_width = 0; 3281 ppr_options = 0; 3282 syncrate = NULL; 3283 } 3284 } else { 3285 if (devinfo->role != ROLE_TARGET) 3286 printf("(%s:%c:%d:%d): Target " 3287 "Initiated PPR\n", 3288 ahc_name(ahc), devinfo->channel, 3289 devinfo->target, devinfo->lun); 3290 else 3291 printf("(%s:%c:%d:%d): Initiator " 3292 "Initiated PPR\n", 3293 ahc_name(ahc), devinfo->channel, 3294 devinfo->target, devinfo->lun); 3295 ahc->msgout_index = 0; 3296 ahc->msgout_len = 0; 3297 ahc_construct_ppr(ahc, devinfo, period, offset, 3298 bus_width, ppr_options); 3299 ahc->msgout_index = 0; 3300 response = TRUE; 3301 } 3302 if (bootverbose) { 3303 printf("(%s:%c:%d:%d): Received PPR width %x, " 3304 "period %x, offset %x,options %x\n" 3305 "\tFiltered to width %x, period %x, " 3306 "offset %x, options %x\n", 3307 ahc_name(ahc), devinfo->channel, 3308 devinfo->target, devinfo->lun, 3309 saved_width, ahc->msgin_buf[3], 3310 saved_offset, saved_ppr_options, 3311 bus_width, period, offset, ppr_options); 3312 } 3313 ahc_set_width(ahc, devinfo, bus_width, 3314 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3315 /*paused*/TRUE); 3316 ahc_set_syncrate(ahc, devinfo, 3317 syncrate, period, 3318 offset, ppr_options, 3319 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3320 /*paused*/TRUE); 3321 done = MSGLOOP_MSGCOMPLETE; 3322 break; 3323 } 3324 default: 3325 /* Unknown extended message. Reject it. */ 3326 reject = TRUE; 3327 break; 3328 } 3329 break; 3330 } 3331 #ifdef AHC_TARGET_MODE 3332 case MSG_BUS_DEV_RESET: 3333 ahc_handle_devreset(ahc, devinfo, 3334 CAM_BDR_SENT, 3335 "Bus Device Reset Received", 3336 /*verbose_level*/0); 3337 ahc_restart(ahc); 3338 done = MSGLOOP_TERMINATED; 3339 break; 3340 case MSG_ABORT_TAG: 3341 case MSG_ABORT: 3342 case MSG_CLEAR_QUEUE: 3343 { 3344 int tag; 3345 3346 /* Target mode messages */ 3347 if (devinfo->role != ROLE_TARGET) { 3348 reject = TRUE; 3349 break; 3350 } 3351 tag = SCB_LIST_NULL; 3352 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3353 tag = ahc_inb(ahc, INITIATOR_TAG); 3354 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3355 devinfo->lun, tag, ROLE_TARGET, 3356 CAM_REQ_ABORTED); 3357 3358 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3359 if (tstate != NULL) { 3360 struct ahc_tmode_lstate* lstate; 3361 3362 lstate = tstate->enabled_luns[devinfo->lun]; 3363 if (lstate != NULL) { 3364 ahc_queue_lstate_event(ahc, lstate, 3365 devinfo->our_scsiid, 3366 ahc->msgin_buf[0], 3367 /*arg*/tag); 3368 ahc_send_lstate_events(ahc, lstate); 3369 } 3370 } 3371 ahc_restart(ahc); 3372 done = MSGLOOP_TERMINATED; 3373 break; 3374 } 3375 #endif 3376 case MSG_TERM_IO_PROC: 3377 default: 3378 reject = TRUE; 3379 break; 3380 } 3381 3382 if (reject) { 3383 /* 3384 * Setup to reject the message. 3385 */ 3386 ahc->msgout_index = 0; 3387 ahc->msgout_len = 1; 3388 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3389 done = MSGLOOP_MSGCOMPLETE; 3390 response = TRUE; 3391 } 3392 3393 if (done != MSGLOOP_IN_PROG && !response) 3394 /* Clear the outgoing message buffer */ 3395 ahc->msgout_len = 0; 3396 3397 return (done); 3398 } 3399 3400 /* 3401 * Process a message reject message. 3402 */ 3403 static int 3404 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3405 { 3406 /* 3407 * What we care about here is if we had an 3408 * outstanding SDTR or WDTR message for this 3409 * target. If we did, this is a signal that 3410 * the target is refusing negotiation. 3411 */ 3412 struct scb *scb; 3413 struct ahc_initiator_tinfo *tinfo; 3414 struct ahc_tmode_tstate *tstate; 3415 u_int scb_index; 3416 u_int last_msg; 3417 int response = 0; 3418 3419 scb_index = ahc_inb(ahc, SCB_TAG); 3420 scb = ahc_lookup_scb(ahc, scb_index); 3421 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3422 devinfo->our_scsiid, 3423 devinfo->target, &tstate); 3424 /* Might be necessary */ 3425 last_msg = ahc_inb(ahc, LAST_MSG); 3426 3427 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3428 /* 3429 * Target does not support the PPR message. 3430 * Attempt to negotiate SPI-2 style. 3431 */ 3432 if (bootverbose) { 3433 printf("(%s:%c:%d:%d): PPR Rejected. " 3434 "Trying WDTR/SDTR\n", 3435 ahc_name(ahc), devinfo->channel, 3436 devinfo->target, devinfo->lun); 3437 } 3438 tinfo->goal.ppr_options = 0; 3439 tinfo->curr.transport_version = 2; 3440 tinfo->goal.transport_version = 2; 3441 ahc->msgout_index = 0; 3442 ahc->msgout_len = 0; 3443 ahc_build_transfer_msg(ahc, devinfo); 3444 ahc->msgout_index = 0; 3445 response = 1; 3446 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3447 3448 /* note 8bit xfers */ 3449 if (bootverbose) 3450 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3451 "8bit transfers\n", ahc_name(ahc), 3452 devinfo->channel, devinfo->target, devinfo->lun); 3453 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3454 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3455 /*paused*/TRUE); 3456 /* 3457 * No need to clear the sync rate. If the target 3458 * did not accept the command, our syncrate is 3459 * unaffected. If the target started the negotiation, 3460 * but rejected our response, we already cleared the 3461 * sync rate before sending our WDTR. 3462 */ 3463 if (tinfo->goal.offset != tinfo->curr.offset) { 3464 3465 /* Start the sync negotiation */ 3466 ahc->msgout_index = 0; 3467 ahc->msgout_len = 0; 3468 ahc_build_transfer_msg(ahc, devinfo); 3469 ahc->msgout_index = 0; 3470 response = 1; 3471 } 3472 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3473 /* note asynch xfers and clear flag */ 3474 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3475 /*offset*/0, /*ppr_options*/0, 3476 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3477 /*paused*/TRUE); 3478 if (bootverbose) 3479 printf("(%s:%c:%d:%d): refuses synchronous negotiation." 3480 " Using asynchronous transfers\n", 3481 ahc_name(ahc), devinfo->channel, 3482 devinfo->target, devinfo->lun); 3483 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3484 int tag_type; 3485 int mask; 3486 3487 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3488 3489 if (tag_type == MSG_SIMPLE_TASK) { 3490 if (bootverbose) 3491 printf("(%s:%c:%d:%d): refuses tagged commands." 3492 " Performing non-tagged I/O\n", 3493 ahc_name(ahc), devinfo->channel, 3494 devinfo->target, devinfo->lun); 3495 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3496 mask = ~0x23; 3497 } else { 3498 if (bootverbose) 3499 printf("(%s:%c:%d:%d): refuses %s tagged " 3500 "commands. Performing simple queue " 3501 "tagged I/O only\n", 3502 ahc_name(ahc), devinfo->channel, 3503 devinfo->target, devinfo->lun, 3504 tag_type == MSG_ORDERED_TASK 3505 ? "ordered" : "head of queue"); 3506 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3507 mask = ~0x03; 3508 } 3509 3510 /* 3511 * Resend the identify for this CCB as the target 3512 * may believe that the selection is invalid otherwise. 3513 */ 3514 ahc_outb(ahc, SCB_CONTROL, 3515 ahc_inb(ahc, SCB_CONTROL) & mask); 3516 scb->hscb->control &= mask; 3517 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3518 /*type*/MSG_SIMPLE_TASK); 3519 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3520 ahc_assert_atn(ahc); 3521 3522 /* 3523 * This transaction is now at the head of 3524 * the untagged queue for this target. 3525 */ 3526 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3527 struct scb_tailq *untagged_q; 3528 3529 untagged_q = 3530 &(ahc->untagged_queues[devinfo->target_offset]); 3531 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3532 scb->flags |= SCB_UNTAGGEDQ; 3533 } 3534 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3535 scb->hscb->tag); 3536 3537 /* 3538 * Requeue all tagged commands for this target 3539 * currently in our posession so they can be 3540 * converted to untagged commands. 3541 */ 3542 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3543 SCB_GET_CHANNEL(ahc, scb), 3544 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3545 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3546 SEARCH_COMPLETE); 3547 } else { 3548 /* 3549 * Otherwise, we ignore it. 3550 */ 3551 if (bootverbose) 3552 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3553 ahc_name(ahc), devinfo->channel, devinfo->target, 3554 last_msg); 3555 } 3556 return (response); 3557 } 3558 3559 /* 3560 * Process an ingnore wide residue message. 3561 */ 3562 static void 3563 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3564 { 3565 u_int scb_index; 3566 struct scb *scb; 3567 3568 scb_index = ahc_inb(ahc, SCB_TAG); 3569 scb = ahc_lookup_scb(ahc, scb_index); 3570 /* 3571 * XXX Actually check data direction in the sequencer? 3572 * Perhaps add datadir to some spare bits in the hscb? 3573 */ 3574 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3575 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3576 /* 3577 * Ignore the message if we haven't 3578 * seen an appropriate data phase yet. 3579 */ 3580 } else { 3581 /* 3582 * If the residual occurred on the last 3583 * transfer and the transfer request was 3584 * expected to end on an odd count, do 3585 * nothing. Otherwise, subtract a byte 3586 * and update the residual count accordingly. 3587 */ 3588 uint32_t sgptr; 3589 3590 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3591 if ((sgptr & SG_LIST_NULL) != 0 3592 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3593 /* 3594 * If the residual occurred on the last 3595 * transfer and the transfer request was 3596 * expected to end on an odd count, do 3597 * nothing. 3598 */ 3599 } else { 3600 struct ahc_dma_seg *sg; 3601 uint32_t data_cnt; 3602 uint32_t data_addr; 3603 uint32_t sglen; 3604 3605 /* Pull in the rest of the sgptr */ 3606 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3607 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3608 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3609 sgptr &= SG_PTR_MASK; 3610 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3611 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3612 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3613 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3614 3615 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3616 | (ahc_inb(ahc, SHADDR + 2) << 16) 3617 | (ahc_inb(ahc, SHADDR + 1) << 8) 3618 | (ahc_inb(ahc, SHADDR)); 3619 3620 data_cnt += 1; 3621 data_addr -= 1; 3622 3623 sg = ahc_sg_bus_to_virt(scb, sgptr); 3624 /* 3625 * The residual sg ptr points to the next S/G 3626 * to load so we must go back one. 3627 */ 3628 sg--; 3629 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3630 if (sg != scb->sg_list 3631 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3632 3633 sg--; 3634 sglen = ahc_le32toh(sg->len); 3635 /* 3636 * Preserve High Address and SG_LIST bits 3637 * while setting the count to 1. 3638 */ 3639 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3640 data_addr = ahc_le32toh(sg->addr) 3641 + (sglen & AHC_SG_LEN_MASK) - 1; 3642 3643 /* 3644 * Increment sg so it points to the 3645 * "next" sg. 3646 */ 3647 sg++; 3648 sgptr = ahc_sg_virt_to_bus(scb, sg); 3649 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3650 sgptr >> 24); 3651 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3652 sgptr >> 16); 3653 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3654 sgptr >> 8); 3655 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3656 } 3657 3658 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3659 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3660 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3661 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3662 } 3663 } 3664 } 3665 3666 3667 /* 3668 * Reinitialize the data pointers for the active transfer 3669 * based on its current residual. 3670 */ 3671 static void 3672 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3673 { 3674 struct scb *scb; 3675 struct ahc_dma_seg *sg; 3676 u_int scb_index; 3677 uint32_t sgptr; 3678 uint32_t resid; 3679 uint32_t dataptr; 3680 3681 scb_index = ahc_inb(ahc, SCB_TAG); 3682 scb = ahc_lookup_scb(ahc, scb_index); 3683 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3684 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3685 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3686 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3687 3688 sgptr &= SG_PTR_MASK; 3689 sg = ahc_sg_bus_to_virt(scb, sgptr); 3690 3691 /* The residual sg_ptr always points to the next sg */ 3692 sg--; 3693 3694 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3695 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3696 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3697 3698 dataptr = ahc_le32toh(sg->addr) 3699 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3700 - resid; 3701 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3702 u_int dscommand1; 3703 3704 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3705 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3706 ahc_outb(ahc, HADDR, 3707 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3708 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3709 } 3710 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3711 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3712 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3713 ahc_outb(ahc, HADDR, dataptr); 3714 ahc_outb(ahc, HCNT + 2, resid >> 16); 3715 ahc_outb(ahc, HCNT + 1, resid >> 8); 3716 ahc_outb(ahc, HCNT, resid); 3717 if ((ahc->features & AHC_ULTRA2) == 0) { 3718 ahc_outb(ahc, STCNT + 2, resid >> 16); 3719 ahc_outb(ahc, STCNT + 1, resid >> 8); 3720 ahc_outb(ahc, STCNT, resid); 3721 } 3722 } 3723 3724 /* 3725 * Handle the effects of issuing a bus device reset message. 3726 */ 3727 static void 3728 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3729 cam_status status, char *message, int verbose_level) 3730 { 3731 #ifdef AHC_TARGET_MODE 3732 struct ahc_tmode_tstate* tstate; 3733 u_int lun; 3734 #endif 3735 int found; 3736 3737 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3738 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3739 status); 3740 3741 #ifdef AHC_TARGET_MODE 3742 /* 3743 * Send an immediate notify ccb to all target mord peripheral 3744 * drivers affected by this action. 3745 */ 3746 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3747 if (tstate != NULL) { 3748 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3749 struct ahc_tmode_lstate* lstate; 3750 3751 lstate = tstate->enabled_luns[lun]; 3752 if (lstate == NULL) 3753 continue; 3754 3755 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3756 MSG_BUS_DEV_RESET, /*arg*/0); 3757 ahc_send_lstate_events(ahc, lstate); 3758 } 3759 } 3760 #endif 3761 3762 /* 3763 * Go back to async/narrow transfers and renegotiate. 3764 */ 3765 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3766 AHC_TRANS_CUR, /*paused*/TRUE); 3767 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3768 /*period*/0, /*offset*/0, /*ppr_options*/0, 3769 AHC_TRANS_CUR, /*paused*/TRUE); 3770 3771 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3772 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3773 3774 if (message != NULL 3775 && (verbose_level <= bootverbose)) 3776 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3777 message, devinfo->channel, devinfo->target, found); 3778 } 3779 3780 #ifdef AHC_TARGET_MODE 3781 static void 3782 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3783 struct scb *scb) 3784 { 3785 3786 /* 3787 * To facilitate adding multiple messages together, 3788 * each routine should increment the index and len 3789 * variables instead of setting them explicitly. 3790 */ 3791 ahc->msgout_index = 0; 3792 ahc->msgout_len = 0; 3793 3794 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3795 ahc_build_transfer_msg(ahc, devinfo); 3796 else 3797 panic("ahc_intr: AWAITING target message with no message"); 3798 3799 ahc->msgout_index = 0; 3800 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3801 } 3802 #endif 3803 3804 int 3805 ahc_softc_init(struct ahc_softc *ahc) 3806 { 3807 3808 /* The IRQMS bit is only valid on VL and EISA chips */ 3809 if ((ahc->chip & AHC_PCI) == 0) 3810 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3811 else 3812 ahc->unpause = 0; 3813 ahc->pause = ahc->unpause | PAUSE; 3814 /* XXX The shared scb data stuff should be deprecated */ 3815 if (ahc->scb_data == NULL) { 3816 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3817 M_DEVBUF, M_NOWAIT); 3818 if (ahc->scb_data == NULL) 3819 return (ENOMEM); 3820 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3821 } 3822 3823 return (0); 3824 } 3825 3826 void 3827 ahc_softc_insert(struct ahc_softc *ahc) 3828 { 3829 struct ahc_softc *list_ahc; 3830 3831 #if AHC_PCI_CONFIG > 0 3832 /* 3833 * Second Function PCI devices need to inherit some 3834 * settings from function 0. 3835 */ 3836 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3837 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3838 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3839 ahc_dev_softc_t list_pci; 3840 ahc_dev_softc_t pci; 3841 3842 list_pci = list_ahc->dev_softc; 3843 pci = ahc->dev_softc; 3844 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3845 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3846 struct ahc_softc *master; 3847 struct ahc_softc *slave; 3848 3849 if (ahc_get_pci_function(list_pci) == 0) { 3850 master = list_ahc; 3851 slave = ahc; 3852 } else { 3853 master = ahc; 3854 slave = list_ahc; 3855 } 3856 slave->flags &= ~AHC_BIOS_ENABLED; 3857 slave->flags |= 3858 master->flags & AHC_BIOS_ENABLED; 3859 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3860 slave->flags |= 3861 master->flags & AHC_PRIMARY_CHANNEL; 3862 break; 3863 } 3864 } 3865 } 3866 #endif 3867 3868 /* 3869 * Insertion sort into our list of softcs. 3870 */ 3871 list_ahc = TAILQ_FIRST(&ahc_tailq); 3872 while (list_ahc != NULL 3873 && ahc_softc_comp(list_ahc, ahc) <= 0) 3874 list_ahc = TAILQ_NEXT(list_ahc, links); 3875 if (list_ahc != NULL) 3876 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3877 else 3878 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3879 ahc->init_level++; 3880 } 3881 3882 /* 3883 * Verify that the passed in softc pointer is for a 3884 * controller that is still configured. 3885 */ 3886 struct ahc_softc * 3887 ahc_find_softc(struct ahc_softc *ahc) 3888 { 3889 struct ahc_softc *list_ahc; 3890 3891 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3892 if (list_ahc == ahc) 3893 return (ahc); 3894 } 3895 return (NULL); 3896 } 3897 3898 void 3899 ahc_set_unit(struct ahc_softc *ahc, int unit) 3900 { 3901 ahc->unit = unit; 3902 } 3903 3904 void 3905 ahc_set_name(struct ahc_softc *ahc, char *name) 3906 { 3907 if (ahc->name != NULL) 3908 free(ahc->name, M_DEVBUF); 3909 ahc->name = name; 3910 } 3911 3912 void 3913 ahc_free(struct ahc_softc *ahc) 3914 { 3915 int i; 3916 3917 ahc_fini_scbdata(ahc); 3918 switch (ahc->init_level) { 3919 default: 3920 case 2: 3921 ahc_shutdown(ahc); 3922 TAILQ_REMOVE(&ahc_tailq, ahc, links); 3923 /* FALLTHROUGH */ 3924 case 1: 3925 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3926 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3927 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3928 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3929 break; 3930 case 0: 3931 break; 3932 } 3933 3934 ahc_platform_free(ahc); 3935 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3936 struct ahc_tmode_tstate *tstate; 3937 3938 tstate = ahc->enabled_targets[i]; 3939 if (tstate != NULL) { 3940 #if AHC_TARGET_MODE 3941 int j; 3942 3943 for (j = 0; j < AHC_NUM_LUNS; j++) { 3944 struct ahc_tmode_lstate *lstate; 3945 3946 lstate = tstate->enabled_luns[j]; 3947 if (lstate != NULL) { 3948 /*xpt_free_path(lstate->path);*/ 3949 free(lstate, M_DEVBUF); 3950 } 3951 } 3952 #endif 3953 free(tstate, M_DEVBUF); 3954 } 3955 } 3956 #if AHC_TARGET_MODE 3957 if (ahc->black_hole != NULL) { 3958 /*xpt_free_path(ahc->black_hole->path);*/ 3959 free(ahc->black_hole, M_DEVBUF); 3960 } 3961 #endif 3962 if (ahc->name != NULL) 3963 free(ahc->name, M_DEVBUF); 3964 if (ahc->seep_config != NULL) 3965 free(ahc->seep_config, M_DEVBUF); 3966 #ifndef __FreeBSD__ 3967 free(ahc, M_DEVBUF); 3968 #endif 3969 return; 3970 } 3971 3972 void 3973 ahc_shutdown(void *arg) 3974 { 3975 struct ahc_softc *ahc; 3976 int i; 3977 3978 ahc = (struct ahc_softc *)arg; 3979 3980 /* This will reset most registers to 0, but not all */ 3981 ahc_reset(ahc); 3982 ahc_outb(ahc, SCSISEQ, 0); 3983 ahc_outb(ahc, SXFRCTL0, 0); 3984 ahc_outb(ahc, DSPCISTATUS, 0); 3985 3986 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3987 ahc_outb(ahc, i, 0); 3988 } 3989 3990 /* 3991 * Reset the controller and record some information about it 3992 * that is only available just after a reset. 3993 */ 3994 int 3995 ahc_reset(struct ahc_softc *ahc) 3996 { 3997 u_int sblkctl; 3998 u_int sxfrctl1_a, sxfrctl1_b; 3999 int wait; 4000 4001 /* 4002 * Preserve the value of the SXFRCTL1 register for all channels. 4003 * It contains settings that affect termination and we don't want 4004 * to disturb the integrity of the bus. 4005 */ 4006 ahc_pause(ahc); 4007 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4008 /* 4009 * The chip has not been initialized since 4010 * PCI/EISA/VLB bus reset. Don't trust 4011 * "left over BIOS data". 4012 */ 4013 ahc->flags |= AHC_NO_BIOS_INIT; 4014 } 4015 sxfrctl1_b = 0; 4016 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4017 u_int sblkctl; 4018 4019 /* 4020 * Save channel B's settings in case this chip 4021 * is setup for TWIN channel operation. 4022 */ 4023 sblkctl = ahc_inb(ahc, SBLKCTL); 4024 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4025 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4026 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4027 } 4028 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4029 4030 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4031 4032 /* 4033 * Ensure that the reset has finished. We delay 1000us 4034 * prior to reading the register to make sure the chip 4035 * has sufficiently completed its reset to handle register 4036 * accesses. 4037 */ 4038 wait = 1000; 4039 do { 4040 ahc_delay(1000); 4041 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4042 4043 if (wait == 0) { 4044 printf("%s: WARNING - Failed chip reset! " 4045 "Trying to initialize anyway.\n", ahc_name(ahc)); 4046 } 4047 ahc_outb(ahc, HCNTRL, ahc->pause); 4048 4049 /* Determine channel configuration */ 4050 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4051 /* No Twin Channel PCI cards */ 4052 if ((ahc->chip & AHC_PCI) != 0) 4053 sblkctl &= ~SELBUSB; 4054 switch (sblkctl) { 4055 case 0: 4056 /* Single Narrow Channel */ 4057 break; 4058 case 2: 4059 /* Wide Channel */ 4060 ahc->features |= AHC_WIDE; 4061 break; 4062 case 8: 4063 /* Twin Channel */ 4064 ahc->features |= AHC_TWIN; 4065 break; 4066 default: 4067 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4068 return(-1); 4069 } 4070 4071 /* 4072 * Reload sxfrctl1. 4073 * 4074 * We must always initialize STPWEN to 1 before we 4075 * restore the saved values. STPWEN is initialized 4076 * to a tri-state condition which can only be cleared 4077 * by turning it on. 4078 */ 4079 if ((ahc->features & AHC_TWIN) != 0) { 4080 u_int sblkctl; 4081 4082 sblkctl = ahc_inb(ahc, SBLKCTL); 4083 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4084 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4085 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4086 } 4087 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4088 4089 #ifdef AHC_DUMP_SEQ 4090 if (ahc->init_level == 0) 4091 ahc_dumpseq(ahc); 4092 #endif 4093 4094 return (0); 4095 } 4096 4097 /* 4098 * Determine the number of SCBs available on the controller 4099 */ 4100 int 4101 ahc_probe_scbs(struct ahc_softc *ahc) { 4102 int i; 4103 4104 for (i = 0; i < AHC_SCB_MAX; i++) { 4105 4106 ahc_outb(ahc, SCBPTR, i); 4107 ahc_outb(ahc, SCB_BASE, i); 4108 if (ahc_inb(ahc, SCB_BASE) != i) 4109 break; 4110 ahc_outb(ahc, SCBPTR, 0); 4111 if (ahc_inb(ahc, SCB_BASE) != 0) 4112 break; 4113 } 4114 return (i); 4115 } 4116 4117 #if 0 4118 static void 4119 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4120 { 4121 bus_addr_t *baddr; 4122 4123 baddr = (bus_addr_t *)arg; 4124 *baddr = segs->ds_addr; 4125 } 4126 #endif 4127 4128 static void 4129 ahc_build_free_scb_list(struct ahc_softc *ahc) 4130 { 4131 int scbsize; 4132 int i; 4133 4134 scbsize = 32; 4135 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4136 scbsize = 64; 4137 4138 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4139 int j; 4140 4141 ahc_outb(ahc, SCBPTR, i); 4142 4143 /* 4144 * Touch all SCB bytes to avoid parity errors 4145 * should one of our debugging routines read 4146 * an otherwise uninitiatlized byte. 4147 */ 4148 for (j = 0; j < scbsize; j++) 4149 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4150 4151 /* Clear the control byte. */ 4152 ahc_outb(ahc, SCB_CONTROL, 0); 4153 4154 /* Set the next pointer */ 4155 if ((ahc->flags & AHC_PAGESCBS) != 0) 4156 ahc_outb(ahc, SCB_NEXT, i+1); 4157 else 4158 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4159 4160 /* Make the tag number, SCSIID, and lun invalid */ 4161 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4162 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4163 ahc_outb(ahc, SCB_LUN, 0xFF); 4164 } 4165 4166 /* Make sure that the last SCB terminates the free list */ 4167 ahc_outb(ahc, SCBPTR, i-1); 4168 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4169 } 4170 4171 static int 4172 ahc_init_scbdata(struct ahc_softc *ahc) 4173 { 4174 struct scb_data *scb_data; 4175 4176 scb_data = ahc->scb_data; 4177 SLIST_INIT(&scb_data->free_scbs); 4178 SLIST_INIT(&scb_data->sg_maps); 4179 4180 /* Allocate SCB resources */ 4181 scb_data->scbarray = 4182 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4183 M_DEVBUF, M_NOWAIT); 4184 if (scb_data->scbarray == NULL) 4185 return (ENOMEM); 4186 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4187 4188 /* Determine the number of hardware SCBs and initialize them */ 4189 4190 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4191 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4192 /* SCB 0 heads the free list */ 4193 ahc_outb(ahc, FREE_SCBH, 0); 4194 } else { 4195 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4196 } 4197 4198 if (ahc->scb_data->maxhscbs == 0) { 4199 printf("%s: No SCB space found\n", ahc_name(ahc)); 4200 return (ENXIO); 4201 } 4202 4203 ahc_build_free_scb_list(ahc); 4204 4205 /* 4206 * Create our DMA tags. These tags define the kinds of device 4207 * accessible memory allocations and memory mappings we will 4208 * need to perform during normal operation. 4209 * 4210 * Unless we need to further restrict the allocation, we rely 4211 * on the restrictions of the parent dmat, hence the common 4212 * use of MAXADDR and MAXSIZE. 4213 */ 4214 4215 if (ahc_createdmamem(ahc->parent_dmat, 4216 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4217 &scb_data->hscb_dmamap, 4218 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4219 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4220 "hardware SCB structures") < 0) 4221 goto error_exit; 4222 4223 scb_data->init_level++; 4224 4225 if (ahc_createdmamem(ahc->parent_dmat, 4226 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 4227 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4228 &scb_data->sense_busaddr, &scb_data->sense_seg, 4229 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4230 goto error_exit; 4231 4232 scb_data->init_level++; 4233 4234 /* Perform initial CCB allocation */ 4235 memset(scb_data->hscbs, 0, 4236 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4237 ahc_alloc_scbs(ahc); 4238 4239 if (scb_data->numscbs == 0) { 4240 printf("%s: ahc_init_scbdata - " 4241 "Unable to allocate initial scbs\n", 4242 ahc_name(ahc)); 4243 goto error_exit; 4244 } 4245 4246 /* 4247 * Tell the sequencer which SCB will be the next one it receives. 4248 */ 4249 ahc->next_queued_scb = ahc_get_scb(ahc); 4250 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4251 4252 /* 4253 * Note that we were successfull 4254 */ 4255 return (0); 4256 4257 error_exit: 4258 4259 return (ENOMEM); 4260 } 4261 4262 static void 4263 ahc_fini_scbdata(struct ahc_softc *ahc) 4264 { 4265 struct scb_data *scb_data; 4266 4267 scb_data = ahc->scb_data; 4268 if (scb_data == NULL) 4269 return; 4270 4271 switch (scb_data->init_level) { 4272 default: 4273 case 3: 4274 { 4275 struct sg_map_node *sg_map; 4276 4277 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4278 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4279 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4280 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4281 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4282 free(sg_map, M_DEVBUF); 4283 } 4284 } 4285 /*FALLTHROUGH*/ 4286 case 2: 4287 ahc_freedmamem(ahc->parent_dmat, 4288 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 4289 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4290 &scb_data->sense_seg, scb_data->sense_nseg); 4291 /*FALLTHROUGH*/ 4292 case 1: 4293 ahc_freedmamem(ahc->parent_dmat, 4294 AHC_SCB_MAX * sizeof(struct hardware_scb), 4295 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4296 &scb_data->hscb_seg, scb_data->hscb_nseg); 4297 /*FALLTHROUGH*/ 4298 } 4299 if (scb_data->scbarray != NULL) 4300 free(scb_data->scbarray, M_DEVBUF); 4301 } 4302 4303 void 4304 ahc_alloc_scbs(struct ahc_softc *ahc) 4305 { 4306 struct scb_data *scb_data; 4307 struct scb *next_scb; 4308 struct sg_map_node *sg_map; 4309 bus_addr_t physaddr; 4310 struct ahc_dma_seg *segs; 4311 int newcount; 4312 int i; 4313 4314 scb_data = ahc->scb_data; 4315 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4316 /* Can't allocate any more */ 4317 return; 4318 4319 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4320 4321 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4322 4323 if (sg_map == NULL) 4324 return; 4325 4326 /* Allocate S/G space for the next batch of SCBS */ 4327 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4328 &sg_map->sg_dmamap, 4329 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4330 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4331 "SG space") < 0) { 4332 free(sg_map, M_DEVBUF); 4333 return; 4334 } 4335 4336 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4337 4338 segs = sg_map->sg_vaddr; 4339 physaddr = sg_map->sg_physaddr; 4340 4341 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4342 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4343 for (i = 0; i < newcount; i++) { 4344 struct scb_platform_data *pdata; 4345 int error; 4346 4347 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4348 M_DEVBUF, M_NOWAIT); 4349 if (pdata == NULL) 4350 break; 4351 next_scb->platform_data = pdata; 4352 next_scb->sg_map = sg_map; 4353 next_scb->sg_list = segs; 4354 /* 4355 * The sequencer always starts with the second entry. 4356 * The first entry is embedded in the scb. 4357 */ 4358 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4359 next_scb->ahc_softc = ahc; 4360 next_scb->flags = SCB_FREE; 4361 4362 error = bus_dmamap_create(ahc->parent_dmat, 4363 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4364 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 4365 &next_scb->dmamap); 4366 if (error != 0) 4367 break; 4368 4369 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4370 next_scb->hscb->tag = ahc->scb_data->numscbs; 4371 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4372 next_scb, links.sle); 4373 segs += AHC_NSEG; 4374 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4375 next_scb++; 4376 ahc->scb_data->numscbs++; 4377 } 4378 } 4379 4380 void 4381 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4382 { 4383 int len; 4384 4385 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4386 buf += len; 4387 if ((ahc->features & AHC_TWIN) != 0) 4388 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4389 "B SCSI Id=%d, primary %c, ", 4390 ahc->our_id, ahc->our_id_b, 4391 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4392 else { 4393 const char *speed; 4394 const char *type; 4395 4396 speed = ""; 4397 if ((ahc->features & AHC_ULTRA) != 0) { 4398 speed = "Ultra "; 4399 } else if ((ahc->features & AHC_DT) != 0) { 4400 speed = "Ultra160 "; 4401 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4402 speed = "Ultra2 "; 4403 } 4404 if ((ahc->features & AHC_WIDE) != 0) { 4405 type = "Wide"; 4406 } else { 4407 type = "Single"; 4408 } 4409 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4410 speed, type, ahc->channel, ahc->our_id); 4411 } 4412 buf += len; 4413 4414 if ((ahc->flags & AHC_PAGESCBS) != 0) 4415 sprintf(buf, "%d/%d SCBs", 4416 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4417 else 4418 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4419 } 4420 4421 /* 4422 * Start the board, ready for normal operation 4423 */ 4424 int 4425 ahc_init(struct ahc_softc *ahc) 4426 { 4427 int max_targ; 4428 int i; 4429 int term; 4430 u_int scsi_conf; 4431 u_int scsiseq_template; 4432 u_int ultraenb; 4433 u_int discenable; 4434 u_int tagenable; 4435 size_t driver_data_size; 4436 uint32_t physaddr; 4437 4438 #ifdef AHC_DEBUG 4439 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4440 ahc->flags |= AHC_SEQUENCER_DEBUG; 4441 #endif 4442 4443 #ifdef AHC_PRINT_SRAM 4444 printf("Scratch Ram:"); 4445 for (i = 0x20; i < 0x5f; i++) { 4446 if (((i % 8) == 0) && (i != 0)) { 4447 printf ("\n "); 4448 } 4449 printf (" 0x%x", ahc_inb(ahc, i)); 4450 } 4451 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4452 for (i = 0x70; i < 0x7f; i++) { 4453 if (((i % 8) == 0) && (i != 0)) { 4454 printf ("\n "); 4455 } 4456 printf (" 0x%x", ahc_inb(ahc, i)); 4457 } 4458 } 4459 printf ("\n"); 4460 /* 4461 * Reading uninitialized scratch ram may 4462 * generate parity errors. 4463 */ 4464 ahc_outb(ahc, CLRINT, CLRPARERR); 4465 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4466 #endif 4467 max_targ = 15; 4468 4469 /* 4470 * Assume we have a board at this stage and it has been reset. 4471 */ 4472 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4473 ahc->our_id = ahc->our_id_b = 7; 4474 4475 /* 4476 * Default to allowing initiator operations. 4477 */ 4478 ahc->flags |= AHC_INITIATORROLE; 4479 4480 /* 4481 * Only allow target mode features if this unit has them enabled. 4482 */ 4483 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4484 ahc->features &= ~AHC_TARGETMODE; 4485 4486 /* 4487 * DMA tag for our command fifos and other data in system memory 4488 * the card's sequencer must be able to access. For initiator 4489 * roles, we need to allocate space for the qinfifo and qoutfifo. 4490 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4491 * When providing for the target mode role, we must additionally 4492 * provide space for the incoming target command fifo and an extra 4493 * byte to deal with a dma bug in some chip versions. 4494 */ 4495 driver_data_size = 2 * 256 * sizeof(uint8_t); 4496 if ((ahc->features & AHC_TARGETMODE) != 0) 4497 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4498 + /*DMA WideOdd Bug Buffer*/1; 4499 4500 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4501 ahc->sc_dmaflags, 4502 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4503 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4504 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4505 return (ENOMEM); 4506 4507 ahc->init_level++; 4508 4509 if ((ahc->features & AHC_TARGETMODE) != 0) { 4510 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4511 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4512 ahc->dma_bug_buf = ahc->shared_data_busaddr 4513 + driver_data_size - 1; 4514 /* All target command blocks start out invalid. */ 4515 for (i = 0; i < AHC_TMODE_CMDS; i++) 4516 ahc->targetcmds[i].cmd_valid = 0; 4517 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4518 ahc->tqinfifonext = 1; 4519 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4520 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4521 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4522 } 4523 ahc->qinfifo = &ahc->qoutfifo[256]; 4524 4525 ahc->init_level++; 4526 4527 /* Allocate SCB data now that buffer_dmat is initialized */ 4528 if (ahc->scb_data->maxhscbs == 0) 4529 if (ahc_init_scbdata(ahc) != 0) 4530 return (ENOMEM); 4531 4532 if (bootverbose) 4533 printf("%s: found %d SCBs\n", ahc_name(ahc), 4534 ahc->scb_data->maxhscbs); 4535 4536 /* 4537 * Allocate a tstate to house information for our 4538 * initiator presence on the bus as well as the user 4539 * data for any target mode initiator. 4540 */ 4541 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4542 printf("%s: unable to allocate ahc_tmode_tstate. " 4543 "Failing attach\n", ahc_name(ahc)); 4544 return (ENOMEM); 4545 } 4546 4547 if ((ahc->features & AHC_TWIN) != 0) { 4548 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4549 printf("%s: unable to allocate ahc_tmode_tstate. " 4550 "Failing attach\n", ahc_name(ahc)); 4551 return (ENOMEM); 4552 } 4553 } 4554 4555 ahc_outb(ahc, SEQ_FLAGS, 0); 4556 ahc_outb(ahc, SEQ_FLAGS2, 0); 4557 4558 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4559 ahc->flags |= AHC_PAGESCBS; 4560 } else { 4561 ahc->flags &= ~AHC_PAGESCBS; 4562 } 4563 4564 #ifdef AHC_DEBUG 4565 if (ahc_debug & AHC_SHOW_MISC) { 4566 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 4567 "ahc_dma %lu bytes\n", 4568 ahc_name(ahc), 4569 (u_long)sizeof(struct hardware_scb), 4570 (u_long)sizeof(struct scb), 4571 (u_long)sizeof(struct ahc_dma_seg)); 4572 } 4573 #endif /* AHC_DEBUG */ 4574 4575 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4576 if (ahc->features & AHC_TWIN) { 4577 4578 /* 4579 * The device is gated to channel B after a chip reset, 4580 * so set those values first 4581 */ 4582 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4583 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4584 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4585 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4586 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4587 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4588 if ((ahc->features & AHC_ULTRA2) != 0) 4589 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4590 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4591 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4592 4593 if ((scsi_conf & RESET_SCSI) != 0 4594 && (ahc->flags & AHC_INITIATORROLE) != 0) 4595 ahc->flags |= AHC_RESET_BUS_B; 4596 4597 /* Select Channel A */ 4598 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4599 } 4600 4601 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4602 if ((ahc->features & AHC_ULTRA2) != 0) 4603 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4604 else 4605 ahc_outb(ahc, SCSIID, ahc->our_id); 4606 scsi_conf = ahc_inb(ahc, SCSICONF); 4607 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4608 |term|ahc->seltime 4609 |ENSTIMER|ACTNEGEN); 4610 if ((ahc->features & AHC_ULTRA2) != 0) 4611 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4612 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4613 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4614 4615 if ((scsi_conf & RESET_SCSI) != 0 4616 && (ahc->flags & AHC_INITIATORROLE) != 0) 4617 ahc->flags |= AHC_RESET_BUS_A; 4618 4619 /* 4620 * Look at the information that board initialization or 4621 * the board bios has left us. 4622 */ 4623 ultraenb = 0; 4624 tagenable = ALL_TARGETS_MASK; 4625 4626 /* Grab the disconnection disable table and invert it for our needs */ 4627 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4628 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4629 "device parameters\n", ahc_name(ahc)); 4630 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4631 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4632 discenable = ALL_TARGETS_MASK; 4633 if ((ahc->features & AHC_ULTRA) != 0) 4634 ultraenb = ALL_TARGETS_MASK; 4635 } else { 4636 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4637 | ahc_inb(ahc, DISC_DSB)); 4638 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4639 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4640 | ahc_inb(ahc, ULTRA_ENB); 4641 } 4642 4643 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4644 max_targ = 7; 4645 4646 for (i = 0; i <= max_targ; i++) { 4647 struct ahc_initiator_tinfo *tinfo; 4648 struct ahc_tmode_tstate *tstate; 4649 u_int our_id; 4650 u_int target_id; 4651 char channel; 4652 4653 channel = 'A'; 4654 our_id = ahc->our_id; 4655 target_id = i; 4656 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4657 channel = 'B'; 4658 our_id = ahc->our_id_b; 4659 target_id = i % 8; 4660 } 4661 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4662 target_id, &tstate); 4663 /* Default to async narrow across the board */ 4664 memset(tinfo, 0, sizeof(*tinfo)); 4665 if (ahc->flags & AHC_USEDEFAULTS) { 4666 if ((ahc->features & AHC_WIDE) != 0) 4667 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4668 4669 /* 4670 * These will be truncated when we determine the 4671 * connection type we have with the target. 4672 */ 4673 tinfo->user.period = ahc_syncrates->period; 4674 tinfo->user.offset = ~0; 4675 } else { 4676 u_int scsirate; 4677 uint16_t mask; 4678 4679 /* Take the settings leftover in scratch RAM. */ 4680 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4681 mask = (0x01 << i); 4682 if ((ahc->features & AHC_ULTRA2) != 0) { 4683 u_int offset; 4684 u_int maxsync; 4685 4686 if ((scsirate & SOFS) == 0x0F) { 4687 /* 4688 * Haven't negotiated yet, 4689 * so the format is different. 4690 */ 4691 scsirate = (scsirate & SXFR) >> 4 4692 | (ultraenb & mask) 4693 ? 0x08 : 0x0 4694 | (scsirate & WIDEXFER); 4695 offset = MAX_OFFSET_ULTRA2; 4696 } else 4697 offset = ahc_inb(ahc, TARG_OFFSET + i); 4698 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4699 /* Set to the lowest sync rate, 5MHz */ 4700 scsirate |= 0x1c; 4701 maxsync = AHC_SYNCRATE_ULTRA2; 4702 if ((ahc->features & AHC_DT) != 0) 4703 maxsync = AHC_SYNCRATE_DT; 4704 tinfo->user.period = 4705 ahc_find_period(ahc, scsirate, maxsync); 4706 if (offset == 0) 4707 tinfo->user.period = 0; 4708 else 4709 tinfo->user.offset = ~0; 4710 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4711 && (ahc->features & AHC_DT) != 0) 4712 tinfo->user.ppr_options = 4713 MSG_EXT_PPR_DT_REQ; 4714 } else if ((scsirate & SOFS) != 0) { 4715 if ((scsirate & SXFR) == 0x40 4716 && (ultraenb & mask) != 0) { 4717 /* Treat 10MHz as a non-ultra speed */ 4718 scsirate &= ~SXFR; 4719 ultraenb &= ~mask; 4720 } 4721 tinfo->user.period = 4722 ahc_find_period(ahc, scsirate, 4723 (ultraenb & mask) 4724 ? AHC_SYNCRATE_ULTRA 4725 : AHC_SYNCRATE_FAST); 4726 if (tinfo->user.period != 0) 4727 tinfo->user.offset = ~0; 4728 } 4729 if (tinfo->user.period == 0) 4730 tinfo->user.offset = 0; 4731 if ((scsirate & WIDEXFER) != 0 4732 && (ahc->features & AHC_WIDE) != 0) 4733 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4734 tinfo->user.protocol_version = 4; 4735 if ((ahc->features & AHC_DT) != 0) 4736 tinfo->user.transport_version = 3; 4737 else 4738 tinfo->user.transport_version = 2; 4739 tinfo->goal.protocol_version = 2; 4740 tinfo->goal.transport_version = 2; 4741 tinfo->curr.protocol_version = 2; 4742 tinfo->curr.transport_version = 2; 4743 } 4744 tstate->ultraenb = 0; 4745 tstate->discenable = discenable; 4746 } 4747 ahc->user_discenable = discenable; 4748 ahc->user_tagenable = tagenable; 4749 4750 /* There are no untagged SCBs active yet. */ 4751 for (i = 0; i < 16; i++) { 4752 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4753 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4754 int lun; 4755 4756 /* 4757 * The SCB based BTT allows an entry per 4758 * target and lun pair. 4759 */ 4760 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4761 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4762 } 4763 } 4764 4765 /* All of our queues are empty */ 4766 for (i = 0; i < 256; i++) 4767 ahc->qoutfifo[i] = SCB_LIST_NULL; 4768 4769 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4770 4771 for (i = 0; i < 256; i++) 4772 ahc->qinfifo[i] = SCB_LIST_NULL; 4773 4774 if ((ahc->features & AHC_MULTI_TID) != 0) { 4775 ahc_outb(ahc, TARGID, 0); 4776 ahc_outb(ahc, TARGID + 1, 0); 4777 } 4778 4779 /* 4780 * Tell the sequencer where it can find our arrays in memory. 4781 */ 4782 physaddr = ahc->scb_data->hscb_busaddr; 4783 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4784 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4785 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4786 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4787 4788 physaddr = ahc->shared_data_busaddr; 4789 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4790 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4791 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4792 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4793 4794 /* 4795 * Initialize the group code to command length table. 4796 * This overrides the values in TARG_SCSIRATE, so only 4797 * setup the table after we have processed that information. 4798 */ 4799 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4800 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4801 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4802 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4803 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4804 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4805 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4806 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4807 4808 /* Tell the sequencer of our initial queue positions */ 4809 ahc_outb(ahc, KERNEL_QINPOS, 0); 4810 ahc_outb(ahc, QINPOS, 0); 4811 ahc_outb(ahc, QOUTPOS, 0); 4812 4813 /* 4814 * Use the built in queue management registers 4815 * if they are available. 4816 */ 4817 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4818 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4819 ahc_outb(ahc, SDSCB_QOFF, 0); 4820 ahc_outb(ahc, SNSCB_QOFF, 0); 4821 ahc_outb(ahc, HNSCB_QOFF, 0); 4822 } 4823 4824 4825 /* We don't have any waiting selections */ 4826 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4827 4828 /* Our disconnection list is empty too */ 4829 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4830 4831 /* Message out buffer starts empty */ 4832 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4833 4834 /* 4835 * Setup the allowed SCSI Sequences based on operational mode. 4836 * If we are a target, we'll enalbe select in operations once 4837 * we've had a lun enabled. 4838 */ 4839 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4840 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4841 scsiseq_template |= ENRSELI; 4842 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4843 4844 /* 4845 * Load the Sequencer program and Enable the adapter 4846 * in "fast" mode. 4847 */ 4848 if (bootverbose) 4849 printf("%s: Downloading Sequencer Program...", 4850 ahc_name(ahc)); 4851 4852 ahc_loadseq(ahc); 4853 4854 if ((ahc->features & AHC_ULTRA2) != 0) { 4855 int wait; 4856 4857 /* 4858 * Wait for up to 500ms for our transceivers 4859 * to settle. If the adapter does not have 4860 * a cable attached, the tranceivers may 4861 * never settle, so don't complain if we 4862 * fail here. 4863 */ 4864 ahc_pause(ahc); 4865 for (wait = 5000; 4866 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4867 wait--) 4868 ahc_delay(100); 4869 ahc_unpause(ahc); 4870 } 4871 4872 /* We have to wait until after any system dumps... */ 4873 ahc->shutdown_hook = shutdownhook_establish(ahc_shutdown, ahc); 4874 4875 return (0); 4876 } 4877 4878 void 4879 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4880 { 4881 u_int hcntrl; 4882 4883 hcntrl = ahc_inb(ahc, HCNTRL); 4884 hcntrl &= ~INTEN; 4885 ahc->pause &= ~INTEN; 4886 ahc->unpause &= ~INTEN; 4887 if (enable) { 4888 hcntrl |= INTEN; 4889 ahc->pause |= INTEN; 4890 ahc->unpause |= INTEN; 4891 } 4892 ahc_outb(ahc, HCNTRL, hcntrl); 4893 } 4894 4895 /* 4896 * Ensure that the card is paused in a location 4897 * outside of all critical sections and that all 4898 * pending work is completed prior to returning. 4899 * This routine should only be called from outside 4900 * an interrupt context. 4901 */ 4902 void 4903 ahc_pause_and_flushwork(struct ahc_softc *ahc) 4904 { 4905 int intstat; 4906 int maxloops; 4907 int paused; 4908 4909 maxloops = 1000; 4910 ahc->flags |= AHC_ALL_INTERRUPTS; 4911 intstat = 0; 4912 paused = FALSE; 4913 do { 4914 if (paused) 4915 ahc_unpause(ahc); 4916 ahc_intr(ahc); 4917 ahc_pause(ahc); 4918 paused = TRUE; 4919 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 4920 ahc_clear_critical_section(ahc); 4921 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4922 break; 4923 } while (--maxloops 4924 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0 4925 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)))); 4926 if (maxloops == 0) { 4927 printf("Infinite interrupt loop, INTSTAT = %x", 4928 ahc_inb(ahc, INTSTAT)); 4929 } 4930 ahc_platform_flushwork(ahc); 4931 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4932 } 4933 4934 int 4935 ahc_suspend(struct ahc_softc *ahc) 4936 { 4937 uint8_t *ptr; 4938 int i; 4939 4940 ahc_pause_and_flushwork(ahc); 4941 4942 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4943 return (EBUSY); 4944 4945 #if AHC_TARGET_MODE 4946 /* 4947 * XXX What about ATIOs that have not yet been serviced? 4948 * Perhaps we should just refuse to be suspended if we 4949 * are acting in a target role. 4950 */ 4951 if (ahc->pending_device != NULL) 4952 return (EBUSY); 4953 #endif 4954 4955 /* Save volatile registers */ 4956 if ((ahc->features & AHC_TWIN) != 0) { 4957 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4958 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4959 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4960 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4961 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4962 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4963 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4964 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4965 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4966 } 4967 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4968 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4969 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4970 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4971 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4972 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4973 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4974 4975 if ((ahc->chip & AHC_PCI) != 0) { 4976 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4977 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4978 } 4979 4980 if ((ahc->features & AHC_DT) != 0) { 4981 u_int sfunct; 4982 4983 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4984 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4985 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4986 ahc_outb(ahc, SFUNCT, sfunct); 4987 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4988 } 4989 4990 if ((ahc->features & AHC_MULTI_FUNC) != 0) 4991 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 4992 4993 if ((ahc->features & AHC_ULTRA2) != 0) 4994 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 4995 4996 ptr = ahc->suspend_state.scratch_ram; 4997 for (i = 0; i < 64; i++) 4998 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 4999 5000 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5001 for (i = 0; i < 16; i++) 5002 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 5003 } 5004 5005 ptr = ahc->suspend_state.btt; 5006 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5007 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5008 int j; 5009 5010 for (j = 0;j < AHC_NUM_LUNS; j++) { 5011 u_int tcl; 5012 5013 tcl = BUILD_TCL(i << 4, j); 5014 *ptr = ahc_index_busy_tcl(ahc, tcl); 5015 } 5016 } 5017 } 5018 ahc_shutdown(ahc); 5019 return (0); 5020 } 5021 5022 int 5023 ahc_resume(struct ahc_softc *ahc) 5024 { 5025 uint8_t *ptr; 5026 int i; 5027 5028 ahc_reset(ahc); 5029 5030 ahc_build_free_scb_list(ahc); 5031 5032 /* Restore volatile registers */ 5033 if ((ahc->features & AHC_TWIN) != 0) { 5034 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5035 ahc_outb(ahc, SCSIID, ahc->our_id); 5036 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 5037 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 5038 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 5039 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 5040 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 5041 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 5042 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 5043 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5044 } 5045 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 5046 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 5047 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 5048 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 5049 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 5050 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 5051 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 5052 if ((ahc->features & AHC_ULTRA2) != 0) 5053 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5054 else 5055 ahc_outb(ahc, SCSIID, ahc->our_id); 5056 5057 if ((ahc->chip & AHC_PCI) != 0) { 5058 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 5059 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 5060 } 5061 5062 if ((ahc->features & AHC_DT) != 0) { 5063 u_int sfunct; 5064 5065 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 5066 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 5067 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 5068 ahc_outb(ahc, SFUNCT, sfunct); 5069 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 5070 } 5071 5072 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5073 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 5074 5075 if ((ahc->features & AHC_ULTRA2) != 0) 5076 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 5077 5078 ptr = ahc->suspend_state.scratch_ram; 5079 for (i = 0; i < 64; i++) 5080 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 5081 5082 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5083 for (i = 0; i < 16; i++) 5084 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 5085 } 5086 5087 ptr = ahc->suspend_state.btt; 5088 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5089 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5090 int j; 5091 5092 for (j = 0;j < AHC_NUM_LUNS; j++) { 5093 u_int tcl; 5094 5095 tcl = BUILD_TCL(i << 4, j); 5096 ahc_busy_tcl(ahc, tcl, *ptr); 5097 } 5098 } 5099 } 5100 return (0); 5101 } 5102 5103 /************************** Busy Target Table *********************************/ 5104 /* 5105 * Return the untagged transaction id for a given target/channel lun. 5106 * Optionally, clear the entry. 5107 */ 5108 u_int 5109 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5110 { 5111 u_int scbid; 5112 u_int target_offset; 5113 5114 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5115 u_int saved_scbptr; 5116 5117 saved_scbptr = ahc_inb(ahc, SCBPTR); 5118 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5119 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5120 ahc_outb(ahc, SCBPTR, saved_scbptr); 5121 } else { 5122 target_offset = TCL_TARGET_OFFSET(tcl); 5123 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5124 } 5125 5126 return (scbid); 5127 } 5128 5129 void 5130 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5131 { 5132 u_int target_offset; 5133 5134 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5135 u_int saved_scbptr; 5136 5137 saved_scbptr = ahc_inb(ahc, SCBPTR); 5138 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5139 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5140 ahc_outb(ahc, SCBPTR, saved_scbptr); 5141 } else { 5142 target_offset = TCL_TARGET_OFFSET(tcl); 5143 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5144 } 5145 } 5146 5147 void 5148 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5149 { 5150 u_int target_offset; 5151 5152 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5153 u_int saved_scbptr; 5154 5155 saved_scbptr = ahc_inb(ahc, SCBPTR); 5156 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5157 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5158 ahc_outb(ahc, SCBPTR, saved_scbptr); 5159 } else { 5160 target_offset = TCL_TARGET_OFFSET(tcl); 5161 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5162 } 5163 } 5164 5165 /************************** SCB and SCB queue management **********************/ 5166 int 5167 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5168 char channel, int lun, u_int tag, role_t role) 5169 { 5170 int targ = SCB_GET_TARGET(ahc, scb); 5171 char chan = SCB_GET_CHANNEL(ahc, scb); 5172 int slun = SCB_GET_LUN(scb); 5173 int match; 5174 5175 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5176 if (match != 0) 5177 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5178 if (match != 0) 5179 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5180 if (match != 0) { 5181 #if 0 5182 #if AHC_TARGET_MODE 5183 int group; 5184 5185 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5186 if (role == ROLE_INITIATOR) { 5187 match = (group != XPT_FC_GROUP_TMODE) 5188 && ((tag == scb->hscb->tag) 5189 || (tag == SCB_LIST_NULL)); 5190 } else if (role == ROLE_TARGET) { 5191 match = (group == XPT_FC_GROUP_TMODE) 5192 && ((tag == scb->io_ctx->csio.tag_id) 5193 || (tag == SCB_LIST_NULL)); 5194 } 5195 #else /* !AHC_TARGET_MODE */ 5196 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5197 #endif /* AHC_TARGET_MODE */ 5198 #endif 5199 } 5200 5201 return match; 5202 } 5203 5204 void 5205 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5206 { 5207 int target; 5208 char channel; 5209 int lun; 5210 5211 target = SCB_GET_TARGET(ahc, scb); 5212 lun = SCB_GET_LUN(scb); 5213 channel = SCB_GET_CHANNEL(ahc, scb); 5214 5215 ahc_search_qinfifo(ahc, target, channel, lun, 5216 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5217 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5218 5219 ahc_platform_freeze_devq(ahc, scb); 5220 } 5221 5222 void 5223 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5224 { 5225 struct scb *prev_scb; 5226 5227 prev_scb = NULL; 5228 if (ahc_qinfifo_count(ahc) != 0) { 5229 u_int prev_tag; 5230 uint8_t prev_pos; 5231 5232 prev_pos = ahc->qinfifonext - 1; 5233 prev_tag = ahc->qinfifo[prev_pos]; 5234 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5235 } 5236 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5237 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5238 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5239 } else { 5240 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5241 } 5242 } 5243 5244 static void 5245 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5246 struct scb *scb) 5247 { 5248 if (prev_scb == NULL) { 5249 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5250 } else { 5251 prev_scb->hscb->next = scb->hscb->tag; 5252 ahc_sync_scb(ahc, prev_scb, 5253 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5254 } 5255 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5256 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5257 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5258 } 5259 5260 static int 5261 ahc_qinfifo_count(struct ahc_softc *ahc) 5262 { 5263 uint8_t qinpos; 5264 uint8_t diff; 5265 5266 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5267 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5268 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5269 } else 5270 qinpos = ahc_inb(ahc, QINPOS); 5271 diff = ahc->qinfifonext - qinpos; 5272 return (diff); 5273 } 5274 5275 int 5276 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5277 int lun, u_int tag, role_t role, uint32_t status, 5278 ahc_search_action action) 5279 { 5280 struct scb *scb; 5281 struct scb *prev_scb; 5282 uint8_t qinstart; 5283 uint8_t qinpos; 5284 uint8_t qintail; 5285 uint8_t next; 5286 uint8_t prev; 5287 uint8_t curscbptr; 5288 int found; 5289 int have_qregs; 5290 5291 qintail = ahc->qinfifonext; 5292 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5293 if (have_qregs) { 5294 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5295 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5296 } else 5297 qinstart = ahc_inb(ahc, QINPOS); 5298 qinpos = qinstart; 5299 found = 0; 5300 prev_scb = NULL; 5301 5302 if (action == SEARCH_COMPLETE) { 5303 /* 5304 * Don't attempt to run any queued untagged transactions 5305 * until we are done with the abort process. 5306 */ 5307 ahc_freeze_untagged_queues(ahc); 5308 } 5309 5310 /* 5311 * Start with an empty queue. Entries that are not chosen 5312 * for removal will be re-added to the queue as we go. 5313 */ 5314 ahc->qinfifonext = qinpos; 5315 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5316 5317 while (qinpos != qintail) { 5318 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5319 if (scb == NULL) { 5320 printf("qinpos = %d, SCB index = %d\n", 5321 qinpos, ahc->qinfifo[qinpos]); 5322 panic("Loop 1\n"); 5323 } 5324 5325 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5326 /* 5327 * We found an scb that needs to be acted on. 5328 */ 5329 found++; 5330 switch (action) { 5331 case SEARCH_COMPLETE: 5332 { 5333 cam_status ostat; 5334 cam_status cstat; 5335 5336 ostat = ahc_get_transaction_status(scb); 5337 if (ostat == CAM_REQ_INPROG) 5338 ahc_set_transaction_status(scb, status); 5339 cstat = ahc_get_transaction_status(scb); 5340 if (cstat != CAM_REQ_CMP) 5341 ahc_freeze_scb(scb); 5342 if ((scb->flags & SCB_ACTIVE) == 0) 5343 printf("Inactive SCB in qinfifo\n"); 5344 ahc_done(ahc, scb); 5345 5346 /* FALLTHROUGH */ 5347 } 5348 case SEARCH_REMOVE: 5349 break; 5350 case SEARCH_COUNT: 5351 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5352 prev_scb = scb; 5353 break; 5354 } 5355 } else { 5356 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5357 prev_scb = scb; 5358 } 5359 qinpos++; 5360 } 5361 5362 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5363 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5364 } else { 5365 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5366 } 5367 5368 if (action != SEARCH_COUNT 5369 && (found != 0) 5370 && (qinstart != ahc->qinfifonext)) { 5371 /* 5372 * The sequencer may be in the process of dmaing 5373 * down the SCB at the beginning of the queue. 5374 * This could be problematic if either the first, 5375 * or the second SCB is removed from the queue 5376 * (the first SCB includes a pointer to the "next" 5377 * SCB to dma). If we have removed any entries, swap 5378 * the first element in the queue with the next HSCB 5379 * so the sequencer will notice that NEXT_QUEUED_SCB 5380 * has changed during its dma attempt and will retry 5381 * the DMA. 5382 */ 5383 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5384 5385 if (scb == NULL) { 5386 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5387 found, qinstart, ahc->qinfifonext); 5388 panic("First/Second Qinfifo fixup\n"); 5389 } 5390 /* 5391 * ahc_swap_with_next_hscb forces our next pointer to 5392 * point to the reserved SCB for future commands. Save 5393 * and restore our original next pointer to maintain 5394 * queue integrity. 5395 */ 5396 next = scb->hscb->next; 5397 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5398 ahc_swap_with_next_hscb(ahc, scb); 5399 scb->hscb->next = next; 5400 ahc->qinfifo[qinstart] = scb->hscb->tag; 5401 5402 /* Tell the card about the new head of the qinfifo. */ 5403 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5404 5405 /* Fixup the tail "next" pointer. */ 5406 qintail = ahc->qinfifonext - 1; 5407 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5408 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5409 } 5410 5411 /* 5412 * Search waiting for selection list. 5413 */ 5414 curscbptr = ahc_inb(ahc, SCBPTR); 5415 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5416 prev = SCB_LIST_NULL; 5417 5418 while (next != SCB_LIST_NULL) { 5419 uint8_t scb_index; 5420 5421 ahc_outb(ahc, SCBPTR, next); 5422 scb_index = ahc_inb(ahc, SCB_TAG); 5423 if (scb_index >= ahc->scb_data->numscbs) { 5424 printf("Waiting List inconsistency. " 5425 "SCB index == %d, yet numscbs == %d.", 5426 scb_index, ahc->scb_data->numscbs); 5427 ahc_dump_card_state(ahc); 5428 panic("for safety"); 5429 } 5430 scb = ahc_lookup_scb(ahc, scb_index); 5431 if (scb == NULL) { 5432 printf("scb_index = %d, next = %d\n", 5433 scb_index, next); 5434 panic("Waiting List traversal\n"); 5435 } 5436 if (ahc_match_scb(ahc, scb, target, channel, 5437 lun, SCB_LIST_NULL, role)) { 5438 /* 5439 * We found an scb that needs to be acted on. 5440 */ 5441 found++; 5442 switch (action) { 5443 case SEARCH_COMPLETE: 5444 { 5445 cam_status ostat; 5446 cam_status cstat; 5447 5448 ostat = ahc_get_transaction_status(scb); 5449 if (ostat == CAM_REQ_INPROG) 5450 ahc_set_transaction_status(scb, status); 5451 cstat = ahc_get_transaction_status(scb); 5452 if (cstat != CAM_REQ_CMP) 5453 ahc_freeze_scb(scb); 5454 if ((scb->flags & SCB_ACTIVE) == 0) 5455 printf("Inactive SCB in Waiting List\n"); 5456 ahc_done(ahc, scb); 5457 /* FALLTHROUGH */ 5458 } 5459 case SEARCH_REMOVE: 5460 next = ahc_rem_wscb(ahc, next, prev); 5461 break; 5462 case SEARCH_COUNT: 5463 prev = next; 5464 next = ahc_inb(ahc, SCB_NEXT); 5465 break; 5466 } 5467 } else { 5468 5469 prev = next; 5470 next = ahc_inb(ahc, SCB_NEXT); 5471 } 5472 } 5473 ahc_outb(ahc, SCBPTR, curscbptr); 5474 5475 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5476 channel, lun, status, action); 5477 5478 if (action == SEARCH_COMPLETE) 5479 ahc_release_untagged_queues(ahc); 5480 return (found); 5481 } 5482 5483 int 5484 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsipi_xfer *xs, /*ahc_io_ctx_t ctx,*/ 5485 int target, char channel, int lun, uint32_t status, 5486 ahc_search_action action) 5487 { 5488 struct scb *scb; 5489 int maxtarget; 5490 int found; 5491 int i; 5492 5493 if (action == SEARCH_COMPLETE) { 5494 /* 5495 * Don't attempt to run any queued untagged transactions 5496 * until we are done with the abort process. 5497 */ 5498 ahc_freeze_untagged_queues(ahc); 5499 } 5500 5501 found = 0; 5502 i = 0; 5503 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5504 5505 maxtarget = 16; 5506 if (target != CAM_TARGET_WILDCARD) { 5507 5508 i = target; 5509 if (channel == 'B') 5510 i += 8; 5511 maxtarget = i + 1; 5512 } 5513 } else { 5514 maxtarget = 0; 5515 } 5516 5517 for (; i < maxtarget; i++) { 5518 struct scb_tailq *untagged_q; 5519 struct scb *next_scb; 5520 5521 untagged_q = &(ahc->untagged_queues[i]); 5522 next_scb = TAILQ_FIRST(untagged_q); 5523 while (next_scb != NULL) { 5524 5525 scb = next_scb; 5526 next_scb = TAILQ_NEXT(scb, links.tqe); 5527 5528 /* 5529 * The head of the list may be the currently 5530 * active untagged command for a device. 5531 * We're only searching for commands that 5532 * have not been started. A transaction 5533 * marked active but still in the qinfifo 5534 * is removed by the qinfifo scanning code 5535 * above. 5536 */ 5537 if ((scb->flags & SCB_ACTIVE) != 0) 5538 continue; 5539 5540 if (ahc_match_scb(ahc, scb, target, channel, lun, 5541 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5542 /*|| (ctx != NULL && ctx != scb->io_ctx)*/) 5543 continue; 5544 5545 /* 5546 * We found an scb that needs to be acted on. 5547 */ 5548 found++; 5549 switch (action) { 5550 case SEARCH_COMPLETE: 5551 { 5552 cam_status ostat; 5553 cam_status cstat; 5554 5555 ostat = ahc_get_transaction_status(scb); 5556 if (ostat == CAM_REQ_INPROG) 5557 ahc_set_transaction_status(scb, status); 5558 cstat = ahc_get_transaction_status(scb); 5559 if (cstat != CAM_REQ_CMP) 5560 ahc_freeze_scb(scb); 5561 if ((scb->flags & SCB_ACTIVE) == 0) 5562 printf("Inactive SCB in untaggedQ\n"); 5563 ahc_done(ahc, scb); 5564 break; 5565 } 5566 case SEARCH_REMOVE: 5567 scb->flags &= ~SCB_UNTAGGEDQ; 5568 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5569 break; 5570 case SEARCH_COUNT: 5571 break; 5572 } 5573 } 5574 } 5575 5576 if (action == SEARCH_COMPLETE) 5577 ahc_release_untagged_queues(ahc); 5578 return (found); 5579 } 5580 5581 int 5582 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5583 int lun, u_int tag, int stop_on_first, int remove, 5584 int save_state) 5585 { 5586 struct scb *scbp; 5587 u_int next; 5588 u_int prev; 5589 u_int count; 5590 u_int active_scb; 5591 5592 count = 0; 5593 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5594 prev = SCB_LIST_NULL; 5595 5596 if (save_state) { 5597 /* restore this when we're done */ 5598 active_scb = ahc_inb(ahc, SCBPTR); 5599 } else 5600 /* Silence compiler */ 5601 active_scb = SCB_LIST_NULL; 5602 5603 while (next != SCB_LIST_NULL) { 5604 u_int scb_index; 5605 5606 ahc_outb(ahc, SCBPTR, next); 5607 scb_index = ahc_inb(ahc, SCB_TAG); 5608 if (scb_index >= ahc->scb_data->numscbs) { 5609 printf("Disconnected List inconsistency. " 5610 "SCB index == %d, yet numscbs == %d.", 5611 scb_index, ahc->scb_data->numscbs); 5612 ahc_dump_card_state(ahc); 5613 panic("for safety"); 5614 } 5615 5616 if (next == prev) { 5617 panic("Disconnected List Loop. " 5618 "cur SCBPTR == %x, prev SCBPTR == %x.", 5619 next, prev); 5620 } 5621 scbp = ahc_lookup_scb(ahc, scb_index); 5622 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5623 tag, ROLE_INITIATOR)) { 5624 count++; 5625 if (remove) { 5626 next = 5627 ahc_rem_scb_from_disc_list(ahc, prev, next); 5628 } else { 5629 prev = next; 5630 next = ahc_inb(ahc, SCB_NEXT); 5631 } 5632 if (stop_on_first) 5633 break; 5634 } else { 5635 prev = next; 5636 next = ahc_inb(ahc, SCB_NEXT); 5637 } 5638 } 5639 if (save_state) 5640 ahc_outb(ahc, SCBPTR, active_scb); 5641 return (count); 5642 } 5643 5644 /* 5645 * Remove an SCB from the on chip list of disconnected transactions. 5646 * This is empty/unused if we are not performing SCB paging. 5647 */ 5648 static u_int 5649 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5650 { 5651 u_int next; 5652 5653 ahc_outb(ahc, SCBPTR, scbptr); 5654 next = ahc_inb(ahc, SCB_NEXT); 5655 5656 ahc_outb(ahc, SCB_CONTROL, 0); 5657 5658 ahc_add_curscb_to_free_list(ahc); 5659 5660 if (prev != SCB_LIST_NULL) { 5661 ahc_outb(ahc, SCBPTR, prev); 5662 ahc_outb(ahc, SCB_NEXT, next); 5663 } else 5664 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5665 5666 return (next); 5667 } 5668 5669 /* 5670 * Add the SCB as selected by SCBPTR onto the on chip list of 5671 * free hardware SCBs. This list is empty/unused if we are not 5672 * performing SCB paging. 5673 */ 5674 static void 5675 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5676 { 5677 /* 5678 * Invalidate the tag so that our abort 5679 * routines don't think it's active. 5680 */ 5681 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5682 5683 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5684 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5685 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5686 } 5687 } 5688 5689 /* 5690 * Manipulate the waiting for selection list and return the 5691 * scb that follows the one that we remove. 5692 */ 5693 static u_int 5694 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5695 { 5696 u_int curscb, next; 5697 5698 /* 5699 * Select the SCB we want to abort and 5700 * pull the next pointer out of it. 5701 */ 5702 curscb = ahc_inb(ahc, SCBPTR); 5703 ahc_outb(ahc, SCBPTR, scbpos); 5704 next = ahc_inb(ahc, SCB_NEXT); 5705 5706 /* Clear the necessary fields */ 5707 ahc_outb(ahc, SCB_CONTROL, 0); 5708 5709 ahc_add_curscb_to_free_list(ahc); 5710 5711 /* update the waiting list */ 5712 if (prev == SCB_LIST_NULL) { 5713 /* First in the list */ 5714 ahc_outb(ahc, WAITING_SCBH, next); 5715 5716 /* 5717 * Ensure we aren't attempting to perform 5718 * selection for this entry. 5719 */ 5720 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5721 } else { 5722 /* 5723 * Select the scb that pointed to us 5724 * and update its next pointer. 5725 */ 5726 ahc_outb(ahc, SCBPTR, prev); 5727 ahc_outb(ahc, SCB_NEXT, next); 5728 } 5729 5730 /* 5731 * Point us back at the original scb position. 5732 */ 5733 ahc_outb(ahc, SCBPTR, curscb); 5734 return next; 5735 } 5736 5737 /******************************** Error Handling ******************************/ 5738 /* 5739 * Abort all SCBs that match the given description (target/channel/lun/tag), 5740 * setting their status to the passed in status if the status has not already 5741 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5742 * is paused before it is called. 5743 */ 5744 int 5745 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5746 int lun, u_int tag, role_t role, uint32_t status) 5747 { 5748 struct scb *scbp; 5749 struct scb *scbp_next; 5750 u_int active_scb; 5751 int i, j; 5752 int maxtarget; 5753 int minlun; 5754 int maxlun; 5755 5756 int found; 5757 5758 /* 5759 * Don't attempt to run any queued untagged transactions 5760 * until we are done with the abort process. 5761 */ 5762 ahc_freeze_untagged_queues(ahc); 5763 5764 /* restore this when we're done */ 5765 active_scb = ahc_inb(ahc, SCBPTR); 5766 5767 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5768 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5769 5770 /* 5771 * Clean out the busy target table for any untagged commands. 5772 */ 5773 i = 0; 5774 maxtarget = 16; 5775 if (target != CAM_TARGET_WILDCARD) { 5776 i = target; 5777 if (channel == 'B') 5778 i += 8; 5779 maxtarget = i + 1; 5780 } 5781 5782 if (lun == CAM_LUN_WILDCARD) { 5783 5784 /* 5785 * Unless we are using an SCB based 5786 * busy targets table, there is only 5787 * one table entry for all luns of 5788 * a target. 5789 */ 5790 minlun = 0; 5791 maxlun = 1; 5792 if ((ahc->flags & AHC_SCB_BTT) != 0) 5793 maxlun = AHC_NUM_LUNS; 5794 } else { 5795 minlun = lun; 5796 maxlun = lun + 1; 5797 } 5798 5799 if (role != ROLE_TARGET) { 5800 for (;i < maxtarget; i++) { 5801 for (j = minlun;j < maxlun; j++) { 5802 u_int scbid; 5803 u_int tcl; 5804 5805 tcl = BUILD_TCL(i << 4, j); 5806 scbid = ahc_index_busy_tcl(ahc, tcl); 5807 scbp = ahc_lookup_scb(ahc, scbid); 5808 if (scbp == NULL 5809 || ahc_match_scb(ahc, scbp, target, channel, 5810 lun, tag, role) == 0) 5811 continue; 5812 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5813 } 5814 } 5815 5816 /* 5817 * Go through the disconnected list and remove any entries we 5818 * have queued for completion, 0'ing their control byte too. 5819 * We save the active SCB and restore it ourselves, so there 5820 * is no reason for this search to restore it too. 5821 */ 5822 ahc_search_disc_list(ahc, target, channel, lun, tag, 5823 /*stop_on_first*/FALSE, /*remove*/TRUE, 5824 /*save_state*/FALSE); 5825 } 5826 5827 /* 5828 * Go through the hardware SCB array looking for commands that 5829 * were active but not on any list. In some cases, these remnants 5830 * might not still have mappings in the scbindex array (e.g. unexpected 5831 * bus free with the same scb queued for an abort). Don't hold this 5832 * against them. 5833 */ 5834 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5835 u_int scbid; 5836 5837 ahc_outb(ahc, SCBPTR, i); 5838 scbid = ahc_inb(ahc, SCB_TAG); 5839 scbp = ahc_lookup_scb(ahc, scbid); 5840 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5841 || (scbp != NULL 5842 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5843 ahc_add_curscb_to_free_list(ahc); 5844 } 5845 5846 /* 5847 * Go through the pending CCB list and look for 5848 * commands for this target that are still active. 5849 * These are other tagged commands that were 5850 * disconnected when the reset occurred. 5851 */ 5852 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5853 while (scbp_next != NULL) { 5854 scbp = scbp_next; 5855 scbp_next = LIST_NEXT(scbp, pending_links); 5856 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5857 cam_status ostat; 5858 5859 ostat = ahc_get_transaction_status(scbp); 5860 if (ostat == CAM_REQ_INPROG) 5861 ahc_set_transaction_status(scbp, status); 5862 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5863 ahc_freeze_scb(scbp); 5864 if ((scbp->flags & SCB_ACTIVE) == 0) 5865 printf("Inactive SCB on pending list\n"); 5866 ahc_done(ahc, scbp); 5867 found++; 5868 } 5869 } 5870 ahc_outb(ahc, SCBPTR, active_scb); 5871 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5872 ahc_release_untagged_queues(ahc); 5873 return found; 5874 } 5875 5876 static void 5877 ahc_reset_current_bus(struct ahc_softc *ahc) 5878 { 5879 uint8_t scsiseq; 5880 5881 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5882 scsiseq = ahc_inb(ahc, SCSISEQ); 5883 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5884 ahc_flush_device_writes(ahc); 5885 ahc_delay(AHC_BUSRESET_DELAY); 5886 /* Turn off the bus reset */ 5887 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5888 5889 ahc_clear_intstat(ahc); 5890 5891 /* Re-enable reset interrupts */ 5892 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5893 } 5894 5895 int 5896 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5897 { 5898 struct ahc_devinfo devinfo; 5899 u_int initiator, target, max_scsiid; 5900 u_int sblkctl; 5901 u_int scsiseq; 5902 u_int simode1; 5903 int found; 5904 int restart_needed; 5905 char cur_channel; 5906 5907 ahc->pending_device = NULL; 5908 5909 ahc_compile_devinfo(&devinfo, 5910 CAM_TARGET_WILDCARD, 5911 CAM_TARGET_WILDCARD, 5912 CAM_LUN_WILDCARD, 5913 channel, ROLE_UNKNOWN); 5914 ahc_pause(ahc); 5915 5916 /* Make sure the sequencer is in a safe location. */ 5917 ahc_clear_critical_section(ahc); 5918 5919 /* 5920 * Run our command complete fifos to ensure that we perform 5921 * completion processing on any commands that 'completed' 5922 * before the reset occurred. 5923 */ 5924 ahc_run_qoutfifo(ahc); 5925 #if AHC_TARGET_MODE 5926 /* 5927 * XXX - In Twin mode, the tqinfifo may have commands 5928 * for an unaffected channel in it. However, if 5929 * we have run out of ATIO resources to drain that 5930 * queue, we may not get them all out here. Further, 5931 * the blocked transactions for the reset channel 5932 * should just be killed off, irrespecitve of whether 5933 * we are blocked on ATIO resources. Write a routine 5934 * to compact the tqinfifo appropriately. 5935 */ 5936 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5937 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5938 } 5939 #endif 5940 5941 /* 5942 * Reset the bus if we are initiating this reset 5943 */ 5944 sblkctl = ahc_inb(ahc, SBLKCTL); 5945 cur_channel = 'A'; 5946 if ((ahc->features & AHC_TWIN) != 0 5947 && ((sblkctl & SELBUSB) != 0)) 5948 cur_channel = 'B'; 5949 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5950 if (cur_channel != channel) { 5951 /* Case 1: Command for another bus is active 5952 * Stealthily reset the other bus without 5953 * upsetting the current bus. 5954 */ 5955 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5956 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5957 #if AHC_TARGET_MODE 5958 /* 5959 * Bus resets clear ENSELI, so we cannot 5960 * defer re-enabling bus reset interrupts 5961 * if we are in target mode. 5962 */ 5963 if ((ahc->flags & AHC_TARGETROLE) != 0) 5964 simode1 |= ENSCSIRST; 5965 #endif 5966 ahc_outb(ahc, SIMODE1, simode1); 5967 if (initiate_reset) 5968 ahc_reset_current_bus(ahc); 5969 ahc_clear_intstat(ahc); 5970 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5971 ahc_outb(ahc, SBLKCTL, sblkctl); 5972 restart_needed = FALSE; 5973 } else { 5974 /* Case 2: A command from this bus is active or we're idle */ 5975 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5976 #if AHC_TARGET_MODE 5977 /* 5978 * Bus resets clear ENSELI, so we cannot 5979 * defer re-enabling bus reset interrupts 5980 * if we are in target mode. 5981 */ 5982 if ((ahc->flags & AHC_TARGETROLE) != 0) 5983 simode1 |= ENSCSIRST; 5984 #endif 5985 ahc_outb(ahc, SIMODE1, simode1); 5986 if (initiate_reset) 5987 ahc_reset_current_bus(ahc); 5988 ahc_clear_intstat(ahc); 5989 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5990 restart_needed = TRUE; 5991 } 5992 5993 /* 5994 * Clean up all the state information for the 5995 * pending transactions on this bus. 5996 */ 5997 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5998 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5999 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6000 6001 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6002 6003 #ifdef AHC_TARGET_MODE 6004 /* 6005 * Send an immediate notify ccb to all target more peripheral 6006 * drivers affected by this action. 6007 */ 6008 for (target = 0; target <= max_scsiid; target++) { 6009 struct ahc_tmode_tstate* tstate; 6010 u_int lun; 6011 6012 tstate = ahc->enabled_targets[target]; 6013 if (tstate == NULL) 6014 continue; 6015 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6016 struct ahc_tmode_lstate* lstate; 6017 6018 lstate = tstate->enabled_luns[lun]; 6019 if (lstate == NULL) 6020 continue; 6021 6022 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6023 EVENT_TYPE_BUS_RESET, /*arg*/0); 6024 ahc_send_lstate_events(ahc, lstate); 6025 } 6026 } 6027 #endif 6028 /* 6029 * Revert to async/narrow transfers until we renegotiate. 6030 */ 6031 for (target = 0; target <= max_scsiid; target++) { 6032 6033 if (ahc->enabled_targets[target] == NULL) 6034 continue; 6035 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6036 struct ahc_devinfo devinfo; 6037 6038 ahc_compile_devinfo(&devinfo, target, initiator, 6039 CAM_LUN_WILDCARD, 6040 channel, ROLE_UNKNOWN); 6041 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6042 AHC_TRANS_CUR, /*paused*/TRUE); 6043 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6044 /*period*/0, /*offset*/0, 6045 /*ppr_options*/0, AHC_TRANS_CUR, 6046 /*paused*/TRUE); 6047 } 6048 } 6049 6050 if (restart_needed) 6051 ahc_restart(ahc); 6052 else 6053 ahc_unpause(ahc); 6054 return found; 6055 } 6056 6057 6058 /***************************** Residual Processing ****************************/ 6059 /* 6060 * Calculate the residual for a just completed SCB. 6061 */ 6062 void 6063 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6064 { 6065 struct hardware_scb *hscb; 6066 struct status_pkt *spkt; 6067 uint32_t sgptr; 6068 uint32_t resid_sgptr; 6069 uint32_t resid; 6070 6071 /* 6072 * 5 cases. 6073 * 1) No residual. 6074 * SG_RESID_VALID clear in sgptr. 6075 * 2) Transferless command 6076 * 3) Never performed any transfers. 6077 * sgptr has SG_FULL_RESID set. 6078 * 4) No residual but target did not 6079 * save data pointers after the 6080 * last transfer, so sgptr was 6081 * never updated. 6082 * 5) We have a partial residual. 6083 * Use residual_sgptr to determine 6084 * where we are. 6085 */ 6086 6087 hscb = scb->hscb; 6088 sgptr = ahc_le32toh(hscb->sgptr); 6089 if ((sgptr & SG_RESID_VALID) == 0) 6090 /* Case 1 */ 6091 return; 6092 sgptr &= ~SG_RESID_VALID; 6093 6094 if ((sgptr & SG_LIST_NULL) != 0) 6095 /* Case 2 */ 6096 return; 6097 6098 spkt = &hscb->shared_data.status; 6099 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6100 if ((sgptr & SG_FULL_RESID) != 0) { 6101 /* Case 3 */ 6102 resid = ahc_get_transfer_length(scb); 6103 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6104 /* Case 4 */ 6105 return; 6106 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6107 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6108 } else { 6109 struct ahc_dma_seg *sg; 6110 6111 /* 6112 * Remainder of the SG where the transfer 6113 * stopped. 6114 */ 6115 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6116 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6117 6118 /* The residual sg_ptr always points to the next sg */ 6119 sg--; 6120 6121 /* 6122 * Add up the contents of all residual 6123 * SG segments that are after the SG where 6124 * the transfer stopped. 6125 */ 6126 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6127 sg++; 6128 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6129 } 6130 } 6131 if ((scb->flags & SCB_SENSE) == 0) 6132 ahc_set_residual(scb, resid); 6133 else 6134 ahc_set_sense_residual(scb, resid); 6135 6136 #ifdef AHC_DEBUG 6137 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6138 ahc_print_path(ahc, scb); 6139 printf("Handled %sResidual of %d bytes\n", 6140 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6141 } 6142 #endif 6143 } 6144 6145 /******************************* Target Mode **********************************/ 6146 #ifdef AHC_TARGET_MODE 6147 /* 6148 * Add a target mode event to this lun's queue 6149 */ 6150 static void 6151 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6152 u_int initiator_id, u_int event_type, u_int event_arg) 6153 { 6154 struct ahc_tmode_event *event; 6155 int pending; 6156 6157 xpt_freeze_devq(lstate->path, /*count*/1); 6158 if (lstate->event_w_idx >= lstate->event_r_idx) 6159 pending = lstate->event_w_idx - lstate->event_r_idx; 6160 else 6161 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6162 - (lstate->event_r_idx - lstate->event_w_idx); 6163 6164 if (event_type == EVENT_TYPE_BUS_RESET 6165 || event_type == MSG_BUS_DEV_RESET) { 6166 /* 6167 * Any earlier events are irrelevant, so reset our buffer. 6168 * This has the effect of allowing us to deal with reset 6169 * floods (an external device holding down the reset line) 6170 * without losing the event that is really interesting. 6171 */ 6172 lstate->event_r_idx = 0; 6173 lstate->event_w_idx = 0; 6174 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6175 } 6176 6177 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6178 xpt_print_path(lstate->path); 6179 printf("immediate event %x:%x lost\n", 6180 lstate->event_buffer[lstate->event_r_idx].event_type, 6181 lstate->event_buffer[lstate->event_r_idx].event_arg); 6182 lstate->event_r_idx++; 6183 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6184 lstate->event_r_idx = 0; 6185 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6186 } 6187 6188 event = &lstate->event_buffer[lstate->event_w_idx]; 6189 event->initiator_id = initiator_id; 6190 event->event_type = event_type; 6191 event->event_arg = event_arg; 6192 lstate->event_w_idx++; 6193 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6194 lstate->event_w_idx = 0; 6195 } 6196 6197 /* 6198 * Send any target mode events queued up waiting 6199 * for immediate notify resources. 6200 */ 6201 void 6202 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6203 { 6204 struct ccb_hdr *ccbh; 6205 struct ccb_immed_notify *inot; 6206 6207 while (lstate->event_r_idx != lstate->event_w_idx 6208 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6209 struct ahc_tmode_event *event; 6210 6211 event = &lstate->event_buffer[lstate->event_r_idx]; 6212 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6213 inot = (struct ccb_immed_notify *)ccbh; 6214 switch (event->event_type) { 6215 case EVENT_TYPE_BUS_RESET: 6216 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6217 break; 6218 default: 6219 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6220 inot->message_args[0] = event->event_type; 6221 inot->message_args[1] = event->event_arg; 6222 break; 6223 } 6224 inot->initiator_id = event->initiator_id; 6225 inot->sense_len = 0; 6226 xpt_done((union ccb *)inot); 6227 lstate->event_r_idx++; 6228 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6229 lstate->event_r_idx = 0; 6230 } 6231 } 6232 #endif 6233 6234 /******************** Sequencer Program Patching/Download *********************/ 6235 6236 #ifdef AHC_DUMP_SEQ 6237 void 6238 ahc_dumpseq(struct ahc_softc* ahc) 6239 { 6240 int i; 6241 int max_prog; 6242 6243 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 6244 max_prog = 448; 6245 else if ((ahc->features & AHC_ULTRA2) != 0) 6246 max_prog = 768; 6247 else 6248 max_prog = 512; 6249 6250 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6251 ahc_outb(ahc, SEQADDR0, 0); 6252 ahc_outb(ahc, SEQADDR1, 0); 6253 for (i = 0; i < max_prog; i++) { 6254 uint8_t ins_bytes[4]; 6255 6256 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6257 printf("0x%08x\n", ins_bytes[0] << 24 6258 | ins_bytes[1] << 16 6259 | ins_bytes[2] << 8 6260 | ins_bytes[3]); 6261 } 6262 } 6263 #endif 6264 6265 static void 6266 ahc_loadseq(struct ahc_softc *ahc) 6267 { 6268 struct cs cs_table[num_critical_sections]; 6269 u_int begin_set[num_critical_sections]; 6270 u_int end_set[num_critical_sections]; 6271 struct patch *cur_patch; 6272 u_int cs_count; 6273 u_int cur_cs; 6274 u_int i; 6275 int downloaded; 6276 u_int skip_addr; 6277 u_int sg_prefetch_cnt; 6278 uint8_t download_consts[7]; 6279 6280 /* 6281 * Start out with 0 critical sections 6282 * that apply to this firmware load. 6283 */ 6284 cs_count = 0; 6285 cur_cs = 0; 6286 memset(begin_set, 0, sizeof(begin_set)); 6287 memset(end_set, 0, sizeof(end_set)); 6288 6289 /* Setup downloadable constant table */ 6290 download_consts[QOUTFIFO_OFFSET] = 0; 6291 if (ahc->targetcmds != NULL) 6292 download_consts[QOUTFIFO_OFFSET] += 32; 6293 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6294 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6295 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6296 sg_prefetch_cnt = ahc->pci_cachesize; 6297 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6298 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6299 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6300 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6301 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6302 6303 cur_patch = patches; 6304 downloaded = 0; 6305 skip_addr = 0; 6306 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6307 ahc_outb(ahc, SEQADDR0, 0); 6308 ahc_outb(ahc, SEQADDR1, 0); 6309 6310 for (i = 0; i < sizeof(seqprog)/4; i++) { 6311 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6312 /* 6313 * Don't download this instruction as it 6314 * is in a patch that was removed. 6315 */ 6316 continue; 6317 } 6318 /* 6319 * Move through the CS table until we find a CS 6320 * that might apply to this instruction. 6321 */ 6322 for (; cur_cs < num_critical_sections; cur_cs++) { 6323 if (critical_sections[cur_cs].end <= i) { 6324 if (begin_set[cs_count] == TRUE 6325 && end_set[cs_count] == FALSE) { 6326 cs_table[cs_count].end = downloaded; 6327 end_set[cs_count] = TRUE; 6328 cs_count++; 6329 } 6330 continue; 6331 } 6332 if (critical_sections[cur_cs].begin <= i 6333 && begin_set[cs_count] == FALSE) { 6334 cs_table[cs_count].begin = downloaded; 6335 begin_set[cs_count] = TRUE; 6336 } 6337 break; 6338 } 6339 ahc_download_instr(ahc, i, download_consts); 6340 downloaded++; 6341 } 6342 6343 ahc->num_critical_sections = cs_count; 6344 if (cs_count != 0) { 6345 6346 cs_count *= sizeof(struct cs); 6347 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6348 if (ahc->critical_sections == NULL) 6349 panic("ahc_loadseq: Could not malloc"); 6350 memcpy(ahc->critical_sections, cs_table, cs_count); 6351 } 6352 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6353 ahc_restart(ahc); 6354 6355 if (bootverbose) { 6356 printf(" %d instructions downloaded\n", downloaded); 6357 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6358 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6359 } 6360 } 6361 6362 static int 6363 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6364 u_int start_instr, u_int *skip_addr) 6365 { 6366 struct patch *cur_patch; 6367 struct patch *last_patch; 6368 u_int num_patches; 6369 6370 num_patches = sizeof(patches)/sizeof(struct patch); 6371 last_patch = &patches[num_patches]; 6372 cur_patch = *start_patch; 6373 6374 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6375 6376 if (cur_patch->patch_func(ahc) == 0) { 6377 6378 /* Start rejecting code */ 6379 *skip_addr = start_instr + cur_patch->skip_instr; 6380 cur_patch += cur_patch->skip_patch; 6381 } else { 6382 /* Accepted this patch. Advance to the next 6383 * one and wait for our intruction pointer to 6384 * hit this point. 6385 */ 6386 cur_patch++; 6387 } 6388 } 6389 6390 *start_patch = cur_patch; 6391 if (start_instr < *skip_addr) 6392 /* Still skipping */ 6393 return (0); 6394 6395 return (1); 6396 } 6397 6398 static void 6399 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6400 { 6401 union ins_formats instr; 6402 struct ins_format1 *fmt1_ins; 6403 struct ins_format3 *fmt3_ins; 6404 u_int opcode; 6405 6406 /* 6407 * The firmware is always compiled into a little endian format. 6408 */ 6409 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6410 6411 fmt1_ins = &instr.format1; 6412 fmt3_ins = NULL; 6413 6414 /* Pull the opcode */ 6415 opcode = instr.format1.opcode; 6416 switch (opcode) { 6417 case AIC_OP_JMP: 6418 case AIC_OP_JC: 6419 case AIC_OP_JNC: 6420 case AIC_OP_CALL: 6421 case AIC_OP_JNE: 6422 case AIC_OP_JNZ: 6423 case AIC_OP_JE: 6424 case AIC_OP_JZ: 6425 { 6426 struct patch *cur_patch; 6427 int address_offset; 6428 u_int address; 6429 u_int skip_addr; 6430 u_int i; 6431 6432 fmt3_ins = &instr.format3; 6433 address_offset = 0; 6434 address = fmt3_ins->address; 6435 cur_patch = patches; 6436 skip_addr = 0; 6437 for (i = 0; i < address;) { 6438 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6439 6440 if (skip_addr > i) { 6441 int end_addr; 6442 6443 end_addr = MIN(address, skip_addr); 6444 address_offset += end_addr - i; 6445 i = skip_addr; 6446 } else { 6447 i++; 6448 } 6449 } 6450 address -= address_offset; 6451 fmt3_ins->address = address; 6452 /* FALLTHROUGH */ 6453 } 6454 case AIC_OP_OR: 6455 case AIC_OP_AND: 6456 case AIC_OP_XOR: 6457 case AIC_OP_ADD: 6458 case AIC_OP_ADC: 6459 case AIC_OP_BMOV: 6460 if (fmt1_ins->parity != 0) { 6461 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6462 } 6463 fmt1_ins->parity = 0; 6464 if ((ahc->features & AHC_CMD_CHAN) == 0 6465 && opcode == AIC_OP_BMOV) { 6466 /* 6467 * Block move was added at the same time 6468 * as the command channel. Verify that 6469 * this is only a move of a single element 6470 * and convert the BMOV to a MOV 6471 * (AND with an immediate of FF). 6472 */ 6473 if (fmt1_ins->immediate != 1) 6474 panic("%s: BMOV not supported\n", 6475 ahc_name(ahc)); 6476 fmt1_ins->opcode = AIC_OP_AND; 6477 fmt1_ins->immediate = 0xff; 6478 } 6479 /* FALLTHROUGH */ 6480 case AIC_OP_ROL: 6481 if ((ahc->features & AHC_ULTRA2) != 0) { 6482 int i, count; 6483 6484 /* Calculate odd parity for the instruction */ 6485 for (i = 0, count = 0; i < 31; i++) { 6486 uint32_t mask; 6487 6488 mask = 0x01 << i; 6489 if ((instr.integer & mask) != 0) 6490 count++; 6491 } 6492 if ((count & 0x01) == 0) 6493 instr.format1.parity = 1; 6494 } else { 6495 /* Compress the instruction for older sequencers */ 6496 if (fmt3_ins != NULL) { 6497 instr.integer = 6498 fmt3_ins->immediate 6499 | (fmt3_ins->source << 8) 6500 | (fmt3_ins->address << 16) 6501 | (fmt3_ins->opcode << 25); 6502 } else { 6503 instr.integer = 6504 fmt1_ins->immediate 6505 | (fmt1_ins->source << 8) 6506 | (fmt1_ins->destination << 16) 6507 | (fmt1_ins->ret << 24) 6508 | (fmt1_ins->opcode << 25); 6509 } 6510 } 6511 /* The sequencer is a little endian cpu */ 6512 instr.integer = ahc_htole32(instr.integer); 6513 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6514 break; 6515 default: 6516 panic("Unknown opcode encountered in seq program"); 6517 break; 6518 } 6519 } 6520 6521 int 6522 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6523 const char *name, u_int address, u_int value, 6524 u_int *cur_column, u_int wrap_point) 6525 { 6526 int printed; 6527 u_int printed_mask; 6528 char line[1024]; 6529 6530 line[0] = 0; 6531 6532 if (cur_column != NULL && *cur_column >= wrap_point) { 6533 printf("\n"); 6534 *cur_column = 0; 6535 } 6536 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 6537 if (table == NULL) { 6538 printed += snprintf(&line[printed], (sizeof line) - printed, 6539 " "); 6540 printf("%s", line); 6541 if (cur_column != NULL) 6542 *cur_column += printed; 6543 return (printed); 6544 } 6545 printed_mask = 0; 6546 while (printed_mask != 0xFF) { 6547 int entry; 6548 6549 for (entry = 0; entry < num_entries; entry++) { 6550 if (((value & table[entry].mask) 6551 != table[entry].value) 6552 || ((printed_mask & table[entry].mask) 6553 == table[entry].mask)) 6554 continue; 6555 printed += snprintf(&line[printed], 6556 (sizeof line) - printed, "%s%s", 6557 printed_mask == 0 ? ":(" : "|", 6558 table[entry].name); 6559 printed_mask |= table[entry].mask; 6560 6561 break; 6562 } 6563 if (entry >= num_entries) 6564 break; 6565 } 6566 if (printed_mask != 0) 6567 printed += snprintf(&line[printed], 6568 (sizeof line) - printed, ") "); 6569 else 6570 printed += snprintf(&line[printed], 6571 (sizeof line) - printed, " "); 6572 if (cur_column != NULL) 6573 *cur_column += printed; 6574 printf("%s", line); 6575 6576 return (printed); 6577 } 6578 6579 void 6580 ahc_dump_card_state(struct ahc_softc *ahc) 6581 { 6582 struct scb *scb; 6583 struct scb_tailq *untagged_q; 6584 u_int cur_col; 6585 int paused; 6586 int target; 6587 int maxtarget; 6588 int i; 6589 uint8_t last_phase; 6590 uint8_t qinpos; 6591 uint8_t qintail; 6592 uint8_t qoutpos; 6593 uint8_t scb_index; 6594 uint8_t saved_scbptr; 6595 6596 if (ahc_is_paused(ahc)) { 6597 paused = 1; 6598 } else { 6599 paused = 0; 6600 ahc_pause(ahc); 6601 } 6602 6603 saved_scbptr = ahc_inb(ahc, SCBPTR); 6604 last_phase = ahc_inb(ahc, LASTPHASE); 6605 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6606 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6607 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6608 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6609 if (paused) 6610 printf("Card was paused\n"); 6611 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6612 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6613 ahc_inb(ahc, ARG_2)); 6614 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6615 ahc_inb(ahc, SCBPTR)); 6616 cur_col = 0; 6617 if ((ahc->features & AHC_DT) != 0) 6618 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6619 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6620 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6621 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6622 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6623 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6624 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6625 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6626 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6627 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6628 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6629 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6630 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6631 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6632 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6633 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6634 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6635 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6636 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6637 if (cur_col != 0) 6638 printf("\n"); 6639 printf("STACK:"); 6640 for (i = 0; i < STACK_SIZE; i++) 6641 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6642 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6643 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6644 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6645 /* QINFIFO */ 6646 printf("QINFIFO entries: "); 6647 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6648 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6649 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6650 } else 6651 qinpos = ahc_inb(ahc, QINPOS); 6652 qintail = ahc->qinfifonext; 6653 while (qinpos != qintail) { 6654 printf("%d ", ahc->qinfifo[qinpos]); 6655 qinpos++; 6656 } 6657 printf("\n"); 6658 6659 printf("Waiting Queue entries: "); 6660 scb_index = ahc_inb(ahc, WAITING_SCBH); 6661 i = 0; 6662 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6663 ahc_outb(ahc, SCBPTR, scb_index); 6664 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6665 scb_index = ahc_inb(ahc, SCB_NEXT); 6666 } 6667 printf("\n"); 6668 6669 printf("Disconnected Queue entries: "); 6670 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6671 i = 0; 6672 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6673 ahc_outb(ahc, SCBPTR, scb_index); 6674 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6675 scb_index = ahc_inb(ahc, SCB_NEXT); 6676 } 6677 printf("\n"); 6678 6679 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6680 printf("QOUTFIFO entries: "); 6681 qoutpos = ahc->qoutfifonext; 6682 i = 0; 6683 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6684 printf("%d ", ahc->qoutfifo[qoutpos]); 6685 qoutpos++; 6686 } 6687 printf("\n"); 6688 6689 printf("Sequencer Free SCB List: "); 6690 scb_index = ahc_inb(ahc, FREE_SCBH); 6691 i = 0; 6692 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6693 ahc_outb(ahc, SCBPTR, scb_index); 6694 printf("%d ", scb_index); 6695 scb_index = ahc_inb(ahc, SCB_NEXT); 6696 } 6697 printf("\n"); 6698 6699 printf("Sequencer SCB Info: "); 6700 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6701 ahc_outb(ahc, SCBPTR, i); 6702 /*cur_col =*/ printf("\n%3d ", i); 6703 6704 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6705 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6706 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6707 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6708 } 6709 printf("\n"); 6710 6711 printf("Pending list: "); 6712 i = 0; 6713 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6714 if (i++ > 256) 6715 break; 6716 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6717 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6718 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6719 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6720 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6721 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6722 printf("("); 6723 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6724 &cur_col, 60); 6725 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6726 printf(")"); 6727 } 6728 } 6729 printf("\n"); 6730 6731 printf("Kernel Free SCB list: "); 6732 i = 0; 6733 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6734 if (i++ > 256) 6735 break; 6736 printf("%d ", scb->hscb->tag); 6737 } 6738 printf("\n"); 6739 6740 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6741 for (target = 0; target <= maxtarget; target++) { 6742 untagged_q = &ahc->untagged_queues[target]; 6743 if (TAILQ_FIRST(untagged_q) == NULL) 6744 continue; 6745 printf("Untagged Q(%d): ", target); 6746 i = 0; 6747 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6748 if (i++ > 256) 6749 break; 6750 printf("%d ", scb->hscb->tag); 6751 } 6752 printf("\n"); 6753 } 6754 6755 ahc_platform_dump_card_state(ahc); 6756 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6757 ahc_outb(ahc, SCBPTR, saved_scbptr); 6758 if (paused == 0) 6759 ahc_unpause(ahc); 6760 } 6761 6762 /************************* Target Mode ****************************************/ 6763 #ifdef AHC_TARGET_MODE 6764 cam_status 6765 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6766 struct ahc_tmode_tstate **tstate, 6767 struct ahc_tmode_lstate **lstate, 6768 int notfound_failure) 6769 { 6770 6771 if ((ahc->features & AHC_TARGETMODE) == 0) 6772 return (CAM_REQ_INVALID); 6773 6774 /* 6775 * Handle the 'black hole' device that sucks up 6776 * requests to unattached luns on enabled targets. 6777 */ 6778 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6779 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6780 *tstate = NULL; 6781 *lstate = ahc->black_hole; 6782 } else { 6783 u_int max_id; 6784 6785 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6786 if (ccb->ccb_h.target_id > max_id) 6787 return (CAM_TID_INVALID); 6788 6789 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6790 return (CAM_LUN_INVALID); 6791 6792 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6793 *lstate = NULL; 6794 if (*tstate != NULL) 6795 *lstate = 6796 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6797 } 6798 6799 if (notfound_failure != 0 && *lstate == NULL) 6800 return (CAM_PATH_INVALID); 6801 6802 return (CAM_REQ_CMP); 6803 } 6804 6805 void 6806 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6807 { 6808 struct ahc_tmode_tstate *tstate; 6809 struct ahc_tmode_lstate *lstate; 6810 struct ccb_en_lun *cel; 6811 cam_status status; 6812 u_int target; 6813 u_int lun; 6814 u_int target_mask; 6815 u_int our_id; 6816 u_long s; 6817 char channel; 6818 6819 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6820 /*notfound_failure*/FALSE); 6821 6822 if (status != CAM_REQ_CMP) { 6823 ccb->ccb_h.status = status; 6824 return; 6825 } 6826 6827 if (cam_sim_bus(sim) == 0) 6828 our_id = ahc->our_id; 6829 else 6830 our_id = ahc->our_id_b; 6831 6832 if (ccb->ccb_h.target_id != our_id) { 6833 /* 6834 * our_id represents our initiator ID, or 6835 * the ID of the first target to have an 6836 * enabled lun in target mode. There are 6837 * two cases that may preclude enabling a 6838 * target id other than our_id. 6839 * 6840 * o our_id is for an active initiator role. 6841 * Since the hardware does not support 6842 * reselections to the initiator role at 6843 * anything other than our_id, and our_id 6844 * is used by the hardware to indicate the 6845 * ID to use for both select-out and 6846 * reselect-out operations, the only target 6847 * ID we can support in this mode is our_id. 6848 * 6849 * o The MULTARGID feature is not available and 6850 * a previous target mode ID has been enabled. 6851 */ 6852 if ((ahc->features & AHC_MULTIROLE) != 0) { 6853 6854 if ((ahc->features & AHC_MULTI_TID) != 0 6855 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6856 /* 6857 * Only allow additional targets if 6858 * the initiator role is disabled. 6859 * The hardware cannot handle a re-select-in 6860 * on the initiator id during a re-select-out 6861 * on a different target id. 6862 */ 6863 status = CAM_TID_INVALID; 6864 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6865 || ahc->enabled_luns > 0) { 6866 /* 6867 * Only allow our target id to change 6868 * if the initiator role is not configured 6869 * and there are no enabled luns which 6870 * are attached to the currently registered 6871 * scsi id. 6872 */ 6873 status = CAM_TID_INVALID; 6874 } 6875 } else if ((ahc->features & AHC_MULTI_TID) == 0 6876 && ahc->enabled_luns > 0) { 6877 6878 status = CAM_TID_INVALID; 6879 } 6880 } 6881 6882 if (status != CAM_REQ_CMP) { 6883 ccb->ccb_h.status = status; 6884 return; 6885 } 6886 6887 /* 6888 * We now have an id that is valid. 6889 * If we aren't in target mode, switch modes. 6890 */ 6891 if ((ahc->flags & AHC_TARGETROLE) == 0 6892 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6893 u_long s; 6894 6895 printf("Configuring Target Mode\n"); 6896 ahc_lock(ahc, &s); 6897 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6898 ccb->ccb_h.status = CAM_BUSY; 6899 ahc_unlock(ahc, &s); 6900 return; 6901 } 6902 ahc->flags |= AHC_TARGETROLE; 6903 if ((ahc->features & AHC_MULTIROLE) == 0) 6904 ahc->flags &= ~AHC_INITIATORROLE; 6905 ahc_pause(ahc); 6906 ahc_loadseq(ahc); 6907 ahc_unlock(ahc, &s); 6908 } 6909 cel = &ccb->cel; 6910 target = ccb->ccb_h.target_id; 6911 lun = ccb->ccb_h.target_lun; 6912 channel = SIM_CHANNEL(ahc, sim); 6913 target_mask = 0x01 << target; 6914 if (channel == 'B') 6915 target_mask <<= 8; 6916 6917 if (cel->enable != 0) { 6918 u_int scsiseq; 6919 6920 /* Are we already enabled?? */ 6921 if (lstate != NULL) { 6922 xpt_print_path(ccb->ccb_h.path); 6923 printf("Lun already enabled\n"); 6924 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6925 return; 6926 } 6927 6928 if (cel->grp6_len != 0 6929 || cel->grp7_len != 0) { 6930 /* 6931 * Don't (yet?) support vendor 6932 * specific commands. 6933 */ 6934 ccb->ccb_h.status = CAM_REQ_INVALID; 6935 printf("Non-zero Group Codes\n"); 6936 return; 6937 } 6938 6939 /* 6940 * Seems to be okay. 6941 * Setup our data structures. 6942 */ 6943 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6944 tstate = ahc_alloc_tstate(ahc, target, channel); 6945 if (tstate == NULL) { 6946 xpt_print_path(ccb->ccb_h.path); 6947 printf("Couldn't allocate tstate\n"); 6948 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6949 return; 6950 } 6951 } 6952 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6953 if (lstate == NULL) { 6954 xpt_print_path(ccb->ccb_h.path); 6955 printf("Couldn't allocate lstate\n"); 6956 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6957 return; 6958 } 6959 memset(lstate, 0, sizeof(*lstate)); 6960 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6961 xpt_path_path_id(ccb->ccb_h.path), 6962 xpt_path_target_id(ccb->ccb_h.path), 6963 xpt_path_lun_id(ccb->ccb_h.path)); 6964 if (status != CAM_REQ_CMP) { 6965 free(lstate, M_DEVBUF); 6966 xpt_print_path(ccb->ccb_h.path); 6967 printf("Couldn't allocate path\n"); 6968 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6969 return; 6970 } 6971 SLIST_INIT(&lstate->accept_tios); 6972 SLIST_INIT(&lstate->immed_notifies); 6973 ahc_lock(ahc, &s); 6974 ahc_pause(ahc); 6975 if (target != CAM_TARGET_WILDCARD) { 6976 tstate->enabled_luns[lun] = lstate; 6977 ahc->enabled_luns++; 6978 6979 if ((ahc->features & AHC_MULTI_TID) != 0) { 6980 u_int targid_mask; 6981 6982 targid_mask = ahc_inb(ahc, TARGID) 6983 | (ahc_inb(ahc, TARGID + 1) << 8); 6984 6985 targid_mask |= target_mask; 6986 ahc_outb(ahc, TARGID, targid_mask); 6987 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6988 6989 ahc_update_scsiid(ahc, targid_mask); 6990 } else { 6991 u_int our_id; 6992 char channel; 6993 6994 channel = SIM_CHANNEL(ahc, sim); 6995 our_id = SIM_SCSI_ID(ahc, sim); 6996 6997 /* 6998 * This can only happen if selections 6999 * are not enabled 7000 */ 7001 if (target != our_id) { 7002 u_int sblkctl; 7003 char cur_channel; 7004 int swap; 7005 7006 sblkctl = ahc_inb(ahc, SBLKCTL); 7007 cur_channel = (sblkctl & SELBUSB) 7008 ? 'B' : 'A'; 7009 if ((ahc->features & AHC_TWIN) == 0) 7010 cur_channel = 'A'; 7011 swap = cur_channel != channel; 7012 if (channel == 'A') 7013 ahc->our_id = target; 7014 else 7015 ahc->our_id_b = target; 7016 7017 if (swap) 7018 ahc_outb(ahc, SBLKCTL, 7019 sblkctl ^ SELBUSB); 7020 7021 ahc_outb(ahc, SCSIID, target); 7022 7023 if (swap) 7024 ahc_outb(ahc, SBLKCTL, sblkctl); 7025 } 7026 } 7027 } else 7028 ahc->black_hole = lstate; 7029 /* Allow select-in operations */ 7030 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7031 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7032 scsiseq |= ENSELI; 7033 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7034 scsiseq = ahc_inb(ahc, SCSISEQ); 7035 scsiseq |= ENSELI; 7036 ahc_outb(ahc, SCSISEQ, scsiseq); 7037 } 7038 ahc_unpause(ahc); 7039 ahc_unlock(ahc, &s); 7040 ccb->ccb_h.status = CAM_REQ_CMP; 7041 xpt_print_path(ccb->ccb_h.path); 7042 printf("Lun now enabled for target mode\n"); 7043 } else { 7044 struct scb *scb; 7045 int i, empty; 7046 7047 if (lstate == NULL) { 7048 ccb->ccb_h.status = CAM_LUN_INVALID; 7049 return; 7050 } 7051 7052 ahc_lock(ahc, &s); 7053 7054 ccb->ccb_h.status = CAM_REQ_CMP; 7055 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7056 struct ccb_hdr *ccbh; 7057 7058 ccbh = &scb->io_ctx->ccb_h; 7059 if (ccbh->func_code == XPT_CONT_TARGET_IO 7060 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7061 printf("CTIO pending\n"); 7062 ccb->ccb_h.status = CAM_REQ_INVALID; 7063 ahc_unlock(ahc, &s); 7064 return; 7065 } 7066 } 7067 7068 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7069 printf("ATIOs pending\n"); 7070 ccb->ccb_h.status = CAM_REQ_INVALID; 7071 } 7072 7073 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7074 printf("INOTs pending\n"); 7075 ccb->ccb_h.status = CAM_REQ_INVALID; 7076 } 7077 7078 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7079 ahc_unlock(ahc, &s); 7080 return; 7081 } 7082 7083 xpt_print_path(ccb->ccb_h.path); 7084 printf("Target mode disabled\n"); 7085 xpt_free_path(lstate->path); 7086 free(lstate, M_DEVBUF); 7087 7088 ahc_pause(ahc); 7089 /* Can we clean up the target too? */ 7090 if (target != CAM_TARGET_WILDCARD) { 7091 tstate->enabled_luns[lun] = NULL; 7092 ahc->enabled_luns--; 7093 for (empty = 1, i = 0; i < 8; i++) 7094 if (tstate->enabled_luns[i] != NULL) { 7095 empty = 0; 7096 break; 7097 } 7098 7099 if (empty) { 7100 ahc_free_tstate(ahc, target, channel, 7101 /*force*/FALSE); 7102 if (ahc->features & AHC_MULTI_TID) { 7103 u_int targid_mask; 7104 7105 targid_mask = ahc_inb(ahc, TARGID) 7106 | (ahc_inb(ahc, TARGID + 1) 7107 << 8); 7108 7109 targid_mask &= ~target_mask; 7110 ahc_outb(ahc, TARGID, targid_mask); 7111 ahc_outb(ahc, TARGID+1, 7112 (targid_mask >> 8)); 7113 ahc_update_scsiid(ahc, targid_mask); 7114 } 7115 } 7116 } else { 7117 7118 ahc->black_hole = NULL; 7119 7120 /* 7121 * We can't allow selections without 7122 * our black hole device. 7123 */ 7124 empty = TRUE; 7125 } 7126 if (ahc->enabled_luns == 0) { 7127 /* Disallow select-in */ 7128 u_int scsiseq; 7129 7130 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7131 scsiseq &= ~ENSELI; 7132 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7133 scsiseq = ahc_inb(ahc, SCSISEQ); 7134 scsiseq &= ~ENSELI; 7135 ahc_outb(ahc, SCSISEQ, scsiseq); 7136 7137 if ((ahc->features & AHC_MULTIROLE) == 0) { 7138 printf("Configuring Initiator Mode\n"); 7139 ahc->flags &= ~AHC_TARGETROLE; 7140 ahc->flags |= AHC_INITIATORROLE; 7141 ahc_pause(ahc); 7142 ahc_loadseq(ahc); 7143 } 7144 } 7145 ahc_unpause(ahc); 7146 ahc_unlock(ahc, &s); 7147 } 7148 } 7149 7150 static void 7151 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7152 { 7153 u_int scsiid_mask; 7154 u_int scsiid; 7155 7156 if ((ahc->features & AHC_MULTI_TID) == 0) 7157 panic("ahc_update_scsiid called on non-multitid unit\n"); 7158 7159 /* 7160 * Since we will rely on the TARGID mask 7161 * for selection enables, ensure that OID 7162 * in SCSIID is not set to some other ID 7163 * that we don't want to allow selections on. 7164 */ 7165 if ((ahc->features & AHC_ULTRA2) != 0) 7166 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7167 else 7168 scsiid = ahc_inb(ahc, SCSIID); 7169 scsiid_mask = 0x1 << (scsiid & OID); 7170 if ((targid_mask & scsiid_mask) == 0) { 7171 u_int our_id; 7172 7173 /* ffs counts from 1 */ 7174 our_id = ffs(targid_mask); 7175 if (our_id == 0) 7176 our_id = ahc->our_id; 7177 else 7178 our_id--; 7179 scsiid &= TID; 7180 scsiid |= our_id; 7181 } 7182 if ((ahc->features & AHC_ULTRA2) != 0) 7183 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7184 else 7185 ahc_outb(ahc, SCSIID, scsiid); 7186 } 7187 7188 void 7189 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7190 { 7191 struct target_cmd *cmd; 7192 7193 /* 7194 * If the card supports auto-access pause, 7195 * we can access the card directly regardless 7196 * of whether it is paused or not. 7197 */ 7198 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7199 paused = TRUE; 7200 7201 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7202 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7203 7204 /* 7205 * Only advance through the queue if we 7206 * have the resources to process the command. 7207 */ 7208 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7209 break; 7210 7211 cmd->cmd_valid = 0; 7212 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7213 ahc->shared_data_dmamap, 7214 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7215 sizeof(struct target_cmd), 7216 BUS_DMASYNC_PREREAD); 7217 ahc->tqinfifonext++; 7218 7219 /* 7220 * Lazily update our position in the target mode incoming 7221 * command queue as seen by the sequencer. 7222 */ 7223 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7224 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7225 u_int hs_mailbox; 7226 7227 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7228 hs_mailbox &= ~HOST_TQINPOS; 7229 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7230 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7231 } else { 7232 if (!paused) 7233 ahc_pause(ahc); 7234 ahc_outb(ahc, KERNEL_TQINPOS, 7235 ahc->tqinfifonext & HOST_TQINPOS); 7236 if (!paused) 7237 ahc_unpause(ahc); 7238 } 7239 } 7240 } 7241 } 7242 7243 static int 7244 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7245 { 7246 struct ahc_tmode_tstate *tstate; 7247 struct ahc_tmode_lstate *lstate; 7248 struct ccb_accept_tio *atio; 7249 uint8_t *byte; 7250 int initiator; 7251 int target; 7252 int lun; 7253 7254 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7255 target = SCSIID_OUR_ID(cmd->scsiid); 7256 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7257 7258 byte = cmd->bytes; 7259 tstate = ahc->enabled_targets[target]; 7260 lstate = NULL; 7261 if (tstate != NULL) 7262 lstate = tstate->enabled_luns[lun]; 7263 7264 /* 7265 * Commands for disabled luns go to the black hole driver. 7266 */ 7267 if (lstate == NULL) 7268 lstate = ahc->black_hole; 7269 7270 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7271 if (atio == NULL) { 7272 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7273 /* 7274 * Wait for more ATIOs from the peripheral driver for this lun. 7275 */ 7276 if (bootverbose) 7277 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7278 return (1); 7279 } else 7280 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7281 #if 0 7282 printf("Incoming command from %d for %d:%d%s\n", 7283 initiator, target, lun, 7284 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7285 #endif 7286 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7287 7288 if (lstate == ahc->black_hole) { 7289 /* Fill in the wildcards */ 7290 atio->ccb_h.target_id = target; 7291 atio->ccb_h.target_lun = lun; 7292 } 7293 7294 /* 7295 * Package it up and send it off to 7296 * whomever has this lun enabled. 7297 */ 7298 atio->sense_len = 0; 7299 atio->init_id = initiator; 7300 if (byte[0] != 0xFF) { 7301 /* Tag was included */ 7302 atio->tag_action = *byte++; 7303 atio->tag_id = *byte++; 7304 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7305 } else { 7306 atio->ccb_h.flags = 0; 7307 } 7308 byte++; 7309 7310 /* Okay. Now determine the cdb size based on the command code */ 7311 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7312 case 0: 7313 atio->cdb_len = 6; 7314 break; 7315 case 1: 7316 case 2: 7317 atio->cdb_len = 10; 7318 break; 7319 case 4: 7320 atio->cdb_len = 16; 7321 break; 7322 case 5: 7323 atio->cdb_len = 12; 7324 break; 7325 case 3: 7326 default: 7327 /* Only copy the opcode. */ 7328 atio->cdb_len = 1; 7329 printf("Reserved or VU command code type encountered\n"); 7330 break; 7331 } 7332 7333 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7334 7335 atio->ccb_h.status |= CAM_CDB_RECVD; 7336 7337 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7338 /* 7339 * We weren't allowed to disconnect. 7340 * We're hanging on the bus until a 7341 * continue target I/O comes in response 7342 * to this accept tio. 7343 */ 7344 #if 0 7345 printf("Received Immediate Command %d:%d:%d - %p\n", 7346 initiator, target, lun, ahc->pending_device); 7347 #endif 7348 ahc->pending_device = lstate; 7349 ahc_freeze_ccb((union ccb *)atio); 7350 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7351 } 7352 xpt_done((union ccb*)atio); 7353 return (0); 7354 } 7355 #endif 7356 7357 static int 7358 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 7359 bus_dma_tag_t tag; 7360 int size; 7361 int flags; 7362 bus_dmamap_t *mapp; 7363 caddr_t *vaddr; 7364 bus_addr_t *baddr; 7365 bus_dma_segment_t *seg; 7366 int *nseg; 7367 const char *myname, *what; 7368 { 7369 int error, level = 0; 7370 7371 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7372 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7373 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7374 myname, what, error); 7375 goto out; 7376 } 7377 level++; 7378 7379 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7380 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7381 printf("%s: failed to map DMA mem for %s, error = %d\n", 7382 myname, what, error); 7383 goto out; 7384 } 7385 level++; 7386 7387 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7388 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7389 printf("%s: failed to create DMA map for %s, error = %d\n", 7390 myname, what, error); 7391 goto out; 7392 } 7393 level++; 7394 7395 7396 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7397 BUS_DMA_NOWAIT)) != 0) { 7398 printf("%s: failed to load DMA map for %s, error = %d\n", 7399 myname, what, error); 7400 goto out; 7401 } 7402 7403 *baddr = (*mapp)->dm_segs[0].ds_addr; 7404 7405 return 0; 7406 out: 7407 printf("ahc_createdmamem error (%d)\n", level); 7408 switch (level) { 7409 case 3: 7410 bus_dmamap_destroy(tag, *mapp); 7411 /* FALLTHROUGH */ 7412 case 2: 7413 bus_dmamem_unmap(tag, *vaddr, size); 7414 /* FALLTHROUGH */ 7415 case 1: 7416 bus_dmamem_free(tag, seg, *nseg); 7417 break; 7418 default: 7419 break; 7420 } 7421 7422 return error; 7423 } 7424 7425 static void 7426 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 7427 bus_dma_tag_t tag; 7428 int size; 7429 bus_dmamap_t map; 7430 caddr_t vaddr; 7431 bus_dma_segment_t *seg; 7432 int nseg; 7433 { 7434 7435 bus_dmamap_unload(tag, map); 7436 bus_dmamap_destroy(tag, map); 7437 bus_dmamem_unmap(tag, vaddr, size); 7438 bus_dmamem_free(tag, seg, nseg); 7439 } 7440
Indexes created Wed Oct 01 15:09:59 GMT 2025