aic7xxx.c revision 1.105
1 /* $NetBSD: aic7xxx.c,v 1.105 2003/05/03 18:11:14 wiz Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: aic7xxx.c,v 1.105 2003/05/03 18:11:14 wiz Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <dev/ic/aic7xxx_osm.h> 53 #include <dev/ic/aic7xxx_inline.h> 54 #include <dev/ic/aic7xxx_cam.h> 55 56 /****************************** Softc Data ************************************/ 57 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 58 59 /***************************** Lookup Tables **********************************/ 60 char *ahc_chip_names[] = 61 { 62 "NONE", 63 "aic7770", 64 "aic7850", 65 "aic7855", 66 "aic7859", 67 "aic7860", 68 "aic7870", 69 "aic7880", 70 "aic7895", 71 "aic7895C", 72 "aic7890/91", 73 "aic7896/97", 74 "aic7892", 75 "aic7899" 76 }; 77 78 /* 79 * Hardware error codes. 80 */ 81 struct ahc_hard_error_entry { 82 uint8_t errno; 83 char *errmesg; 84 }; 85 86 static struct ahc_hard_error_entry ahc_hard_errors[] = { 87 { ILLHADDR, "Illegal Host Access" }, 88 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 89 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 90 { SQPARERR, "Sequencer Parity Error" }, 91 { DPARERR, "Data-path Parity Error" }, 92 { MPARERR, "Scratch or SCB Memory Parity Error" }, 93 { PCIERRSTAT, "PCI Error detected" }, 94 { CIOPARERR, "CIOBUS Parity Error" }, 95 }; 96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 97 98 static struct ahc_phase_table_entry ahc_phase_table[] = 99 { 100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 104 { P_COMMAND, MSG_NOOP, "in Command phase" }, 105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 108 { P_BUSFREE, MSG_NOOP, "while idle" }, 109 { 0, MSG_NOOP, "in unknown phase" } 110 }; 111 112 /* 113 * In most cases we only wish to itterate over real phases, so 114 * exclude the last element from the count. 115 */ 116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 117 118 /* 119 * Valid SCSIRATE values. (p. 3-17) 120 * Provides a mapping of tranfer periods in ns to the proper value to 121 * stick in the scsixfer reg. 122 */ 123 static struct ahc_syncrate ahc_syncrates[] = 124 { 125 /* ultra2 fast/ultra period rate */ 126 { 0x42, 0x000, 9, "80.0" }, 127 { 0x03, 0x000, 10, "40.0" }, 128 { 0x04, 0x000, 11, "33.0" }, 129 { 0x05, 0x100, 12, "20.0" }, 130 { 0x06, 0x110, 15, "16.0" }, 131 { 0x07, 0x120, 18, "13.4" }, 132 { 0x08, 0x000, 25, "10.0" }, 133 { 0x19, 0x010, 31, "8.0" }, 134 { 0x1a, 0x020, 37, "6.67" }, 135 { 0x1b, 0x030, 43, "5.7" }, 136 { 0x1c, 0x040, 50, "5.0" }, 137 { 0x00, 0x050, 56, "4.4" }, 138 { 0x00, 0x060, 62, "4.0" }, 139 { 0x00, 0x070, 68, "3.6" }, 140 { 0x00, 0x000, 0, NULL } 141 }; 142 143 /* Our Sequencer Program */ 144 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 145 146 /**************************** Function Declarations ***************************/ 147 static void ahc_force_renegotiation(struct ahc_softc *ahc); 148 static struct ahc_tmode_tstate* 149 ahc_alloc_tstate(struct ahc_softc *ahc, 150 u_int scsi_id, char channel); 151 #ifdef AHC_TARGET_MODE 152 static void ahc_free_tstate(struct ahc_softc *ahc, 153 u_int scsi_id, char channel, int force); 154 #endif 155 static struct ahc_syncrate* 156 ahc_devlimited_syncrate(struct ahc_softc *ahc, 157 struct ahc_initiator_tinfo *, 158 u_int *period, 159 u_int *ppr_options, 160 role_t role); 161 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 162 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 163 struct ahc_devinfo *devinfo); 164 static void ahc_scb_devinfo(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo, 166 struct scb *scb); 167 static void ahc_assert_atn(struct ahc_softc *ahc); 168 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 169 struct ahc_devinfo *devinfo, 170 struct scb *scb); 171 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 172 struct ahc_devinfo *devinfo); 173 static void ahc_construct_sdtr(struct ahc_softc *ahc, 174 struct ahc_devinfo *devinfo, 175 u_int period, u_int offset); 176 static void ahc_construct_wdtr(struct ahc_softc *ahc, 177 struct ahc_devinfo *devinfo, 178 u_int bus_width); 179 static void ahc_construct_ppr(struct ahc_softc *ahc, 180 struct ahc_devinfo *devinfo, 181 u_int period, u_int offset, 182 u_int bus_width, u_int ppr_options); 183 static void ahc_clear_msg_state(struct ahc_softc *ahc); 184 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 185 static void ahc_handle_message_phase(struct ahc_softc *ahc); 186 typedef enum { 187 AHCMSG_1B, 188 AHCMSG_2B, 189 AHCMSG_EXT 190 } ahc_msgtype; 191 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 192 u_int msgval, int full); 193 static int ahc_parse_msg(struct ahc_softc *ahc, 194 struct ahc_devinfo *devinfo); 195 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 196 struct ahc_devinfo *devinfo); 197 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 198 struct ahc_devinfo *devinfo); 199 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 200 static void ahc_handle_devreset(struct ahc_softc *ahc, 201 struct ahc_devinfo *devinfo, 202 cam_status status, char *message, 203 int verbose_level); 204 #if AHC_TARGET_MODE 205 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 206 struct ahc_devinfo *devinfo, 207 struct scb *scb); 208 #endif 209 210 //static bus_dmamap_callback_t ahc_dmamap_cb; 211 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 212 static int ahc_init_scbdata(struct ahc_softc *ahc); 213 static void ahc_fini_scbdata(struct ahc_softc *ahc); 214 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 215 struct scb *prev_scb, 216 struct scb *scb); 217 static int ahc_qinfifo_count(struct ahc_softc *ahc); 218 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 219 u_int prev, u_int scbptr); 220 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 221 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 222 u_int scbpos, u_int prev); 223 static void ahc_reset_current_bus(struct ahc_softc *ahc); 224 #ifdef AHC_DUMP_SEQ 225 static void ahc_dumpseq(struct ahc_softc *ahc); 226 #endif 227 static void ahc_loadseq(struct ahc_softc *ahc); 228 static int ahc_check_patch(struct ahc_softc *ahc, 229 struct patch **start_patch, 230 u_int start_instr, u_int *skip_addr); 231 static void ahc_download_instr(struct ahc_softc *ahc, 232 u_int instrptr, uint8_t *dconsts); 233 #ifdef AHC_TARGET_MODE 234 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 235 struct ahc_tmode_lstate *lstate, 236 u_int initiator_id, 237 u_int event_type, 238 u_int event_arg); 239 static void ahc_update_scsiid(struct ahc_softc *ahc, 240 u_int targid_mask); 241 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 242 struct target_cmd *cmd); 243 #endif 244 245 /************************** Added for porting to NetBSD ***********************/ 246 static int ahc_createdmamem(bus_dma_tag_t tag, 247 int size, 248 int flags, 249 bus_dmamap_t *mapp, 250 caddr_t *vaddr, 251 bus_addr_t *baddr, 252 bus_dma_segment_t *seg, 253 int *nseg, 254 const char *myname, const char *what); 255 static void ahc_freedmamem(bus_dma_tag_t tag, 256 int size, 257 bus_dmamap_t map, 258 caddr_t vaddr, 259 bus_dma_segment_t *seg, 260 int nseg); 261 262 /************************* Sequencer Execution Control ************************/ 263 /* 264 * Restart the sequencer program from address zero 265 */ 266 void 267 ahc_restart(struct ahc_softc *ahc) 268 { 269 270 ahc_pause(ahc); 271 272 /* No more pending messages. */ 273 ahc_clear_msg_state(ahc); 274 275 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 276 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 277 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 278 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 279 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 280 ahc_outb(ahc, SAVED_LUN, 0xFF); 281 282 /* 283 * Ensure that the sequencer's idea of TQINPOS 284 * matches our own. The sequencer increments TQINPOS 285 * only after it sees a DMA complete and a reset could 286 * occur before the increment leaving the kernel to believe 287 * the command arrived but the sequencer to not. 288 */ 289 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 290 291 /* Always allow reselection */ 292 ahc_outb(ahc, SCSISEQ, 293 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 294 if ((ahc->features & AHC_CMD_CHAN) != 0) { 295 /* Ensure that no DMA operations are in progress */ 296 ahc_outb(ahc, CCSCBCNT, 0); 297 ahc_outb(ahc, CCSGCTL, 0); 298 ahc_outb(ahc, CCSCBCTL, 0); 299 } 300 /* 301 * If we were in the process of DMA'ing SCB data into 302 * an SCB, replace that SCB on the free list. This prevents 303 * an SCB leak. 304 */ 305 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 306 ahc_add_curscb_to_free_list(ahc); 307 ahc_outb(ahc, SEQ_FLAGS2, 308 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 309 } 310 ahc_outb(ahc, MWI_RESIDUAL, 0); 311 ahc_outb(ahc, SEQCTL, FASTMODE); 312 ahc_outb(ahc, SEQADDR0, 0); 313 ahc_outb(ahc, SEQADDR1, 0); 314 ahc_unpause(ahc); 315 } 316 317 /************************* Input/Output Queues ********************************/ 318 void 319 ahc_run_qoutfifo(struct ahc_softc *ahc) 320 { 321 struct scb *scb; 322 u_int scb_index; 323 324 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 325 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 326 327 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 328 if ((ahc->qoutfifonext & 0x03) == 0x03) { 329 u_int modnext; 330 331 /* 332 * Clear 32bits of QOUTFIFO at a time 333 * so that we don't clobber an incoming 334 * byte DMA to the array on architectures 335 * that only support 32bit load and store 336 * operations. 337 */ 338 modnext = ahc->qoutfifonext & ~0x3; 339 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 340 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 341 ahc->shared_data_dmamap, 342 /*offset*/modnext, /*len*/4, 343 BUS_DMASYNC_PREREAD); 344 } 345 ahc->qoutfifonext++; 346 347 scb = ahc_lookup_scb(ahc, scb_index); 348 if (scb == NULL) { 349 printf("%s: WARNING no command for scb %d " 350 "(cmdcmplt)\nQOUTPOS = %d\n", 351 ahc_name(ahc), scb_index, 352 (ahc->qoutfifonext - 1) & 0xFF); 353 continue; 354 } 355 356 /* 357 * Save off the residual 358 * if there is one. 359 */ 360 ahc_update_residual(ahc, scb); 361 ahc_done(ahc, scb); 362 } 363 } 364 365 void 366 ahc_run_untagged_queues(struct ahc_softc *ahc) 367 { 368 int i; 369 370 for (i = 0; i < 16; i++) 371 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 372 } 373 374 void 375 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 376 { 377 struct scb *scb; 378 379 if (ahc->untagged_queue_lock != 0) 380 return; 381 382 if ((scb = TAILQ_FIRST(queue)) != NULL 383 && (scb->flags & SCB_ACTIVE) == 0) { 384 scb->flags |= SCB_ACTIVE; 385 ahc_queue_scb(ahc, scb); 386 } 387 } 388 389 /************************* Interrupt Handling *********************************/ 390 void 391 ahc_handle_brkadrint(struct ahc_softc *ahc) 392 { 393 /* 394 * We upset the sequencer :-( 395 * Lookup the error message 396 */ 397 int i; 398 int error; 399 400 error = ahc_inb(ahc, ERROR); 401 for (i = 0; error != 1 && i < num_errors; i++) 402 error >>= 1; 403 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 404 ahc_name(ahc), ahc_hard_errors[i].errmesg, 405 ahc_inb(ahc, SEQADDR0) | 406 (ahc_inb(ahc, SEQADDR1) << 8)); 407 408 ahc_dump_card_state(ahc); 409 410 /* Tell everyone that this HBA is no longer availible */ 411 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 412 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 413 CAM_NO_HBA); 414 415 /* Disable all interrupt sources by resetting the controller */ 416 ahc_shutdown(ahc); 417 } 418 419 void 420 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 421 { 422 struct scb *scb; 423 struct ahc_devinfo devinfo; 424 425 ahc_fetch_devinfo(ahc, &devinfo); 426 427 /* 428 * Clear the upper byte that holds SEQINT status 429 * codes and clear the SEQINT bit. We will unpause 430 * the sequencer, if appropriate, after servicing 431 * the request. 432 */ 433 ahc_outb(ahc, CLRINT, CLRSEQINT); 434 switch (intstat & SEQINT_MASK) { 435 case BAD_STATUS: 436 { 437 u_int scb_index; 438 struct hardware_scb *hscb; 439 440 /* 441 * Set the default return value to 0 (don't 442 * send sense). The sense code will change 443 * this if needed. 444 */ 445 ahc_outb(ahc, RETURN_1, 0); 446 447 /* 448 * The sequencer will notify us when a command 449 * has an error that would be of interest to 450 * the kernel. This allows us to leave the sequencer 451 * running in the common case of command completes 452 * without error. The sequencer will already have 453 * DMA'd the SCB back up to us, so we can reference 454 * the in kernel copy directly. 455 */ 456 scb_index = ahc_inb(ahc, SCB_TAG); 457 scb = ahc_lookup_scb(ahc, scb_index); 458 if (scb == NULL) { 459 ahc_print_devinfo(ahc, &devinfo); 460 printf("ahc_intr - referenced scb " 461 "not valid during seqint 0x%x scb(%d)\n", 462 intstat, scb_index); 463 ahc_dump_card_state(ahc); 464 panic("for safety"); 465 goto unpause; 466 } 467 468 hscb = scb->hscb; 469 470 /* Don't want to clobber the original sense code */ 471 if ((scb->flags & SCB_SENSE) != 0) { 472 /* 473 * Clear the SCB_SENSE Flag and have 474 * the sequencer do a normal command 475 * complete. 476 */ 477 scb->flags &= ~SCB_SENSE; 478 break; 479 } 480 /* Freeze the queue until the client sees the error. */ 481 ahc_freeze_devq(ahc, scb); 482 ahc_freeze_scb(scb); 483 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 484 switch (hscb->shared_data.status.scsi_status) { 485 case SCSI_STATUS_OK: 486 printf("%s: Interrupted for status of 0 (?)\n", 487 ahc_name(ahc)); 488 break; 489 case SCSI_STATUS_CMD_TERMINATED: 490 case SCSI_STATUS_CHECK_COND: 491 { 492 struct ahc_dma_seg *sg; 493 struct scsipi_sense *sc; 494 struct ahc_initiator_tinfo *targ_info; 495 struct ahc_tmode_tstate *tstate; 496 struct ahc_transinfo *tinfo; 497 #ifdef AHC_DEBUG 498 if (ahc_debug & AHC_SHOW_SENSE) { 499 ahc_print_path(ahc, scb); 500 printf("SCB %d: requests Check Status\n", 501 scb->hscb->tag); 502 } 503 #endif 504 505 if (ahc_perform_autosense(scb) == 0) 506 break; 507 508 targ_info = ahc_fetch_transinfo(ahc, 509 devinfo.channel, 510 devinfo.our_scsiid, 511 devinfo.target, 512 &tstate); 513 tinfo = &targ_info->curr; 514 sg = scb->sg_list; 515 sc = (struct scsipi_sense *)(&hscb->shared_data.cdb); 516 /* 517 * Save off the residual if there is one. 518 */ 519 ahc_update_residual(ahc, scb); 520 #ifdef AHC_DEBUG 521 if (ahc_debug & AHC_SHOW_SENSE) { 522 ahc_print_path(ahc, scb); 523 printf("Sending Sense\n"); 524 } 525 #endif 526 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 527 sg->len = ahc_get_sense_bufsize(ahc, scb); 528 sg->len |= AHC_DMA_LAST_SEG; 529 530 /* Fixup byte order */ 531 sg->addr = ahc_htole32(sg->addr); 532 sg->len = ahc_htole32(sg->len); 533 534 sc->opcode = REQUEST_SENSE; 535 sc->byte2 = 0; 536 if (tinfo->protocol_version <= SCSI_REV_2 537 && SCB_GET_LUN(scb) < 8) 538 sc->byte2 = SCB_GET_LUN(scb) << 5; 539 sc->unused[0] = 0; 540 sc->unused[1] = 0; 541 sc->length = sg->len; 542 sc->control = 0; 543 544 /* 545 * We can't allow the target to disconnect. 546 * This will be an untagged transaction and 547 * having the target disconnect will make this 548 * transaction indestinguishable from outstanding 549 * tagged transactions. 550 */ 551 hscb->control = 0; 552 553 /* 554 * This request sense could be because the 555 * the device lost power or in some other 556 * way has lost our transfer negotiations. 557 * Renegotiate if appropriate. Unit attention 558 * errors will be reported before any data 559 * phases occur. 560 */ 561 if (ahc_get_residual(scb) 562 == ahc_get_transfer_length(scb)) { 563 ahc_update_neg_request(ahc, &devinfo, 564 tstate, targ_info, 565 AHC_NEG_IF_NON_ASYNC); 566 } 567 if (tstate->auto_negotiate & devinfo.target_mask) { 568 hscb->control |= MK_MESSAGE; 569 scb->flags &= ~SCB_NEGOTIATE; 570 scb->flags |= SCB_AUTO_NEGOTIATE; 571 } 572 hscb->cdb_len = sizeof(*sc); 573 hscb->dataptr = sg->addr; 574 hscb->datacnt = sg->len; 575 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 576 hscb->sgptr = ahc_htole32(hscb->sgptr); 577 scb->sg_count = 1; 578 scb->flags |= SCB_SENSE; 579 ahc_qinfifo_requeue_tail(ahc, scb); 580 ahc_outb(ahc, RETURN_1, SEND_SENSE); 581 /* 582 * Ensure we have enough time to actually 583 * retrieve the sense. 584 */ 585 ahc_scb_timer_reset(scb, 5 * 1000000); 586 break; 587 } 588 default: 589 break; 590 } 591 break; 592 } 593 case NO_MATCH: 594 { 595 /* Ensure we don't leave the selection hardware on */ 596 ahc_outb(ahc, SCSISEQ, 597 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 598 599 printf("%s:%c:%d: no active SCB for reconnecting " 600 "target - issuing BUS DEVICE RESET\n", 601 ahc_name(ahc), devinfo.channel, devinfo.target); 602 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 603 "ARG_1 == 0x%x ACCUM = 0x%x\n", 604 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 605 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 606 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 607 "SINDEX == 0x%x\n", 608 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 609 ahc_index_busy_tcl(ahc, 610 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 611 ahc_inb(ahc, SAVED_LUN))), 612 ahc_inb(ahc, SINDEX)); 613 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 614 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 615 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 616 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 617 ahc_inb(ahc, SCB_CONTROL)); 618 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 619 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 620 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 621 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 622 ahc_dump_card_state(ahc); 623 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 624 ahc->msgout_len = 1; 625 ahc->msgout_index = 0; 626 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 627 ahc_outb(ahc, MSG_OUT, HOST_MSG); 628 ahc_assert_atn(ahc); 629 break; 630 } 631 case SEND_REJECT: 632 { 633 u_int rejbyte = ahc_inb(ahc, ACCUM); 634 printf("%s:%c:%d: Warning - unknown message received from " 635 "target (0x%x). Rejecting\n", 636 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 637 break; 638 } 639 case PROTO_VIOLATION: 640 { 641 ahc_handle_proto_violation(ahc); 642 break; 643 } 644 case IGN_WIDE_RES: 645 ahc_handle_ign_wide_residue(ahc, &devinfo); 646 break; 647 case PDATA_REINIT: 648 ahc_reinitialize_dataptrs(ahc); 649 break; 650 case BAD_PHASE: 651 { 652 u_int lastphase; 653 654 lastphase = ahc_inb(ahc, LASTPHASE); 655 printf("%s:%c:%d: unknown scsi bus phase %x, " 656 "lastphase = 0x%x. Attempting to continue\n", 657 ahc_name(ahc), devinfo.channel, devinfo.target, 658 lastphase, ahc_inb(ahc, SCSISIGI)); 659 break; 660 } 661 case MISSED_BUSFREE: 662 { 663 u_int lastphase; 664 665 lastphase = ahc_inb(ahc, LASTPHASE); 666 printf("%s:%c:%d: Missed busfree. " 667 "Lastphase = 0x%x, Curphase = 0x%x\n", 668 ahc_name(ahc), devinfo.channel, devinfo.target, 669 lastphase, ahc_inb(ahc, SCSISIGI)); 670 ahc_restart(ahc); 671 return; 672 } 673 case HOST_MSG_LOOP: 674 { 675 /* 676 * The sequencer has encountered a message phase 677 * that requires host assistance for completion. 678 * While handling the message phase(s), we will be 679 * notified by the sequencer after each byte is 680 * transfered so we can track bus phase changes. 681 * 682 * If this is the first time we've seen a HOST_MSG_LOOP 683 * interrupt, initialize the state of the host message 684 * loop. 685 */ 686 if (ahc->msg_type == MSG_TYPE_NONE) { 687 struct scb *scb; 688 u_int scb_index; 689 u_int bus_phase; 690 691 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 692 if (bus_phase != P_MESGIN 693 && bus_phase != P_MESGOUT) { 694 printf("ahc_intr: HOST_MSG_LOOP bad " 695 "phase 0x%x\n", 696 bus_phase); 697 /* 698 * Probably transitioned to bus free before 699 * we got here. Just punt the message. 700 */ 701 ahc_clear_intstat(ahc); 702 ahc_restart(ahc); 703 return; 704 } 705 706 scb_index = ahc_inb(ahc, SCB_TAG); 707 scb = ahc_lookup_scb(ahc, scb_index); 708 if (devinfo.role == ROLE_INITIATOR) { 709 if (scb == NULL) 710 panic("HOST_MSG_LOOP with " 711 "invalid SCB %x\n", scb_index); 712 713 if (bus_phase == P_MESGOUT) 714 ahc_setup_initiator_msgout(ahc, 715 &devinfo, 716 scb); 717 else { 718 ahc->msg_type = 719 MSG_TYPE_INITIATOR_MSGIN; 720 ahc->msgin_index = 0; 721 } 722 } 723 #if AHC_TARGET_MODE 724 else { 725 if (bus_phase == P_MESGOUT) { 726 ahc->msg_type = 727 MSG_TYPE_TARGET_MSGOUT; 728 ahc->msgin_index = 0; 729 } 730 else 731 ahc_setup_target_msgin(ahc, 732 &devinfo, 733 scb); 734 } 735 #endif 736 } 737 738 ahc_handle_message_phase(ahc); 739 break; 740 } 741 case PERR_DETECTED: 742 { 743 /* 744 * If we've cleared the parity error interrupt 745 * but the sequencer still believes that SCSIPERR 746 * is true, it must be that the parity error is 747 * for the currently presented byte on the bus, 748 * and we are not in a phase (data-in) where we will 749 * eventually ack this byte. Ack the byte and 750 * throw it away in the hope that the target will 751 * take us to message out to deliver the appropriate 752 * error message. 753 */ 754 if ((intstat & SCSIINT) == 0 755 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 756 757 if ((ahc->features & AHC_DT) == 0) { 758 u_int curphase; 759 760 /* 761 * The hardware will only let you ack bytes 762 * if the expected phase in SCSISIGO matches 763 * the current phase. Make sure this is 764 * currently the case. 765 */ 766 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 767 ahc_outb(ahc, LASTPHASE, curphase); 768 ahc_outb(ahc, SCSISIGO, curphase); 769 } 770 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 771 int wait; 772 773 /* 774 * In a data phase. Faster to bitbucket 775 * the data than to individually ack each 776 * byte. This is also the only strategy 777 * that will work with AUTOACK enabled. 778 */ 779 ahc_outb(ahc, SXFRCTL1, 780 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 781 wait = 5000; 782 while (--wait != 0) { 783 if ((ahc_inb(ahc, SCSISIGI) 784 & (CDI|MSGI)) != 0) 785 break; 786 ahc_delay(100); 787 } 788 ahc_outb(ahc, SXFRCTL1, 789 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 790 if (wait == 0) { 791 struct scb *scb; 792 u_int scb_index; 793 794 ahc_print_devinfo(ahc, &devinfo); 795 printf("Unable to clear parity error. " 796 "Resetting bus.\n"); 797 scb_index = ahc_inb(ahc, SCB_TAG); 798 scb = ahc_lookup_scb(ahc, scb_index); 799 if (scb != NULL) 800 ahc_set_transaction_status(scb, 801 CAM_UNCOR_PARITY); 802 ahc_reset_channel(ahc, devinfo.channel, 803 /*init reset*/TRUE); 804 } 805 } else { 806 ahc_inb(ahc, SCSIDATL); 807 } 808 } 809 break; 810 } 811 case DATA_OVERRUN: 812 { 813 /* 814 * When the sequencer detects an overrun, it 815 * places the controller in "BITBUCKET" mode 816 * and allows the target to complete its transfer. 817 * Unfortunately, none of the counters get updated 818 * when the controller is in this mode, so we have 819 * no way of knowing how large the overrun was. 820 */ 821 u_int scbindex = ahc_inb(ahc, SCB_TAG); 822 u_int lastphase = ahc_inb(ahc, LASTPHASE); 823 u_int i; 824 825 scb = ahc_lookup_scb(ahc, scbindex); 826 for (i = 0; i < num_phases; i++) { 827 if (lastphase == ahc_phase_table[i].phase) 828 break; 829 } 830 ahc_print_path(ahc, scb); 831 printf("data overrun detected %s." 832 " Tag == 0x%x.\n", 833 ahc_phase_table[i].phasemsg, 834 scb->hscb->tag); 835 ahc_print_path(ahc, scb); 836 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 837 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 838 ahc_get_transfer_length(scb), scb->sg_count); 839 if (scb->sg_count > 0) { 840 for (i = 0; i < scb->sg_count; i++) { 841 842 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 843 i, 844 (ahc_le32toh(scb->sg_list[i].len) >> 24 845 & SG_HIGH_ADDR_BITS), 846 ahc_le32toh(scb->sg_list[i].addr), 847 ahc_le32toh(scb->sg_list[i].len) 848 & AHC_SG_LEN_MASK); 849 } 850 } 851 /* 852 * Set this and it will take effect when the 853 * target does a command complete. 854 */ 855 ahc_freeze_devq(ahc, scb); 856 if ((scb->flags & SCB_SENSE) == 0) { 857 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 858 } else { 859 scb->flags &= ~SCB_SENSE; 860 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 861 } 862 ahc_freeze_scb(scb); 863 864 if ((ahc->features & AHC_ULTRA2) != 0) { 865 /* 866 * Clear the channel in case we return 867 * to data phase later. 868 */ 869 ahc_outb(ahc, SXFRCTL0, 870 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 871 ahc_outb(ahc, SXFRCTL0, 872 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 873 } 874 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 875 u_int dscommand1; 876 877 /* Ensure HHADDR is 0 for future DMA operations. */ 878 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 879 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 880 ahc_outb(ahc, HADDR, 0); 881 ahc_outb(ahc, DSCOMMAND1, dscommand1); 882 } 883 break; 884 } 885 case MKMSG_FAILED: 886 { 887 u_int scbindex; 888 889 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 890 ahc_name(ahc), devinfo.channel, devinfo.target, 891 devinfo.lun); 892 scbindex = ahc_inb(ahc, SCB_TAG); 893 scb = ahc_lookup_scb(ahc, scbindex); 894 if (scb != NULL 895 && (scb->flags & SCB_RECOVERY_SCB) != 0) 896 /* 897 * Ensure that we didn't put a second instance of this 898 * SCB into the QINFIFO. 899 */ 900 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 901 SCB_GET_CHANNEL(ahc, scb), 902 SCB_GET_LUN(scb), scb->hscb->tag, 903 ROLE_INITIATOR, /*status*/0, 904 SEARCH_REMOVE); 905 break; 906 } 907 case NO_FREE_SCB: 908 { 909 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 910 ahc_dump_card_state(ahc); 911 panic("for safety"); 912 break; 913 } 914 case SCB_MISMATCH: 915 { 916 u_int scbptr; 917 918 scbptr = ahc_inb(ahc, SCBPTR); 919 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 920 scbptr, ahc_inb(ahc, ARG_1), 921 ahc->scb_data->hscbs[scbptr].tag); 922 ahc_dump_card_state(ahc); 923 panic("for saftey"); 924 break; 925 } 926 case OUT_OF_RANGE: 927 { 928 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 929 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 930 "ARG_1 == 0x%x ACCUM = 0x%x\n", 931 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 932 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 933 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 934 "SINDEX == 0x%x\n, A == 0x%x\n", 935 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 936 ahc_index_busy_tcl(ahc, 937 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 938 ahc_inb(ahc, SAVED_LUN))), 939 ahc_inb(ahc, SINDEX), 940 ahc_inb(ahc, ACCUM)); 941 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 942 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 943 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 944 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 945 ahc_inb(ahc, SCB_CONTROL)); 946 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 947 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 948 ahc_dump_card_state(ahc); 949 panic("for safety"); 950 break; 951 } 952 default: 953 printf("ahc_intr: seqint, " 954 "intstat == 0x%x, scsisigi = 0x%x\n", 955 intstat, ahc_inb(ahc, SCSISIGI)); 956 break; 957 } 958 unpause: 959 /* 960 * The sequencer is paused immediately on 961 * a SEQINT, so we should restart it when 962 * we're done. 963 */ 964 ahc_unpause(ahc); 965 } 966 967 void 968 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 969 { 970 u_int scb_index; 971 u_int status0; 972 u_int status; 973 struct scb *scb; 974 char cur_channel; 975 char intr_channel; 976 977 if ((ahc->features & AHC_TWIN) != 0 978 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 979 cur_channel = 'B'; 980 else 981 cur_channel = 'A'; 982 intr_channel = cur_channel; 983 984 if ((ahc->features & AHC_ULTRA2) != 0) 985 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 986 else 987 status0 = 0; 988 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 989 if (status == 0 && status0 == 0) { 990 if ((ahc->features & AHC_TWIN) != 0) { 991 /* Try the other channel */ 992 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 993 status = ahc_inb(ahc, SSTAT1) 994 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 995 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 996 } 997 if (status == 0) { 998 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 999 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1000 ahc_unpause(ahc); 1001 return; 1002 } 1003 } 1004 1005 /* Make sure the sequencer is in a safe location. */ 1006 ahc_clear_critical_section(ahc); 1007 1008 scb_index = ahc_inb(ahc, SCB_TAG); 1009 scb = ahc_lookup_scb(ahc, scb_index); 1010 if (scb != NULL 1011 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1012 scb = NULL; 1013 1014 if ((ahc->features & AHC_ULTRA2) != 0 1015 && (status0 & IOERR) != 0) { 1016 int now_lvd; 1017 1018 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1019 printf("%s: Transceiver State Has Changed to %s mode\n", 1020 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1021 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1022 /* 1023 * When transitioning to SE mode, the reset line 1024 * glitches, triggering an arbitration bug in some 1025 * Ultra2 controllers. This bug is cleared when we 1026 * assert the reset line. Since a reset glitch has 1027 * already occurred with this transition and a 1028 * transceiver state change is handled just like 1029 * a bus reset anyway, asserting the reset line 1030 * ourselves is safe. 1031 */ 1032 ahc_reset_channel(ahc, intr_channel, 1033 /*Initiate Reset*/now_lvd == 0); 1034 } else if ((status & SCSIRSTI) != 0) { 1035 printf("%s: Someone reset channel %c\n", 1036 ahc_name(ahc), intr_channel); 1037 if (intr_channel != cur_channel) 1038 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1039 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1040 } else if ((status & SCSIPERR) != 0) { 1041 /* 1042 * Determine the bus phase and queue an appropriate message. 1043 * SCSIPERR is latched true as soon as a parity error 1044 * occurs. If the sequencer acked the transfer that 1045 * caused the parity error and the currently presented 1046 * transfer on the bus has correct parity, SCSIPERR will 1047 * be cleared by CLRSCSIPERR. Use this to determine if 1048 * we should look at the last phase the sequencer recorded, 1049 * or the current phase presented on the bus. 1050 */ 1051 u_int mesg_out; 1052 u_int curphase; 1053 u_int errorphase; 1054 u_int lastphase; 1055 u_int scsirate; 1056 u_int i; 1057 u_int sstat2; 1058 int silent; 1059 1060 lastphase = ahc_inb(ahc, LASTPHASE); 1061 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1062 sstat2 = ahc_inb(ahc, SSTAT2); 1063 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1064 /* 1065 * For all phases save DATA, the sequencer won't 1066 * automatically ack a byte that has a parity error 1067 * in it. So the only way that the current phase 1068 * could be 'data-in' is if the parity error is for 1069 * an already acked byte in the data phase. During 1070 * synchronous data-in transfers, we may actually 1071 * ack bytes before latching the current phase in 1072 * LASTPHASE, leading to the discrepancy between 1073 * curphase and lastphase. 1074 */ 1075 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1076 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1077 errorphase = curphase; 1078 else 1079 errorphase = lastphase; 1080 1081 for (i = 0; i < num_phases; i++) { 1082 if (errorphase == ahc_phase_table[i].phase) 1083 break; 1084 } 1085 mesg_out = ahc_phase_table[i].mesg_out; 1086 silent = FALSE; 1087 if (scb != NULL) { 1088 if (SCB_IS_SILENT(scb)) 1089 silent = TRUE; 1090 else 1091 ahc_print_path(ahc, scb); 1092 scb->flags |= SCB_TRANSMISSION_ERROR; 1093 } else 1094 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1095 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1096 scsirate = ahc_inb(ahc, SCSIRATE); 1097 if (silent == FALSE) { 1098 printf("parity error detected %s. " 1099 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1100 ahc_phase_table[i].phasemsg, 1101 ahc_inw(ahc, SEQADDR0), 1102 scsirate); 1103 if ((ahc->features & AHC_DT) != 0) { 1104 if ((sstat2 & CRCVALERR) != 0) 1105 printf("\tCRC Value Mismatch\n"); 1106 if ((sstat2 & CRCENDERR) != 0) 1107 printf("\tNo terminal CRC packet " 1108 "recevied\n"); 1109 if ((sstat2 & CRCREQERR) != 0) 1110 printf("\tIllegal CRC packet " 1111 "request\n"); 1112 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1113 printf("\tUnexpected %sDT Data Phase\n", 1114 (scsirate & SINGLE_EDGE) 1115 ? "" : "non-"); 1116 } 1117 } 1118 1119 if ((ahc->features & AHC_DT) != 0 1120 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1121 /* 1122 * This error applies regardless of 1123 * data direction, so ignore the value 1124 * in the phase table. 1125 */ 1126 mesg_out = MSG_INITIATOR_DET_ERR; 1127 } 1128 1129 /* 1130 * We've set the hardware to assert ATN if we 1131 * get a parity error on "in" phases, so all we 1132 * need to do is stuff the message buffer with 1133 * the appropriate message. "In" phases have set 1134 * mesg_out to something other than MSG_NOP. 1135 */ 1136 if (mesg_out != MSG_NOOP) { 1137 if (ahc->msg_type != MSG_TYPE_NONE) 1138 ahc->send_msg_perror = TRUE; 1139 else 1140 ahc_outb(ahc, MSG_OUT, mesg_out); 1141 } 1142 /* 1143 * Force a renegotiation with this target just in 1144 * case we are out of sync for some external reason 1145 * unknown (or unreported) by the target. 1146 */ 1147 ahc_force_renegotiation(ahc); 1148 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1149 ahc_unpause(ahc); 1150 } else if ((status & SELTO) != 0) { 1151 u_int scbptr; 1152 1153 /* Stop the selection */ 1154 ahc_outb(ahc, SCSISEQ, 0); 1155 1156 /* No more pending messages */ 1157 ahc_clear_msg_state(ahc); 1158 1159 /* Clear interrupt state */ 1160 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1161 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1162 1163 /* 1164 * Although the driver does not care about the 1165 * 'Selection in Progress' status bit, the busy 1166 * LED does. SELINGO is only cleared by a sucessfull 1167 * selection, so we must manually clear it to insure 1168 * the LED turns off just incase no future successful 1169 * selections occur (e.g. no devices on the bus). 1170 */ 1171 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1172 1173 scbptr = ahc_inb(ahc, WAITING_SCBH); 1174 ahc_outb(ahc, SCBPTR, scbptr); 1175 scb_index = ahc_inb(ahc, SCB_TAG); 1176 1177 scb = ahc_lookup_scb(ahc, scb_index); 1178 if (scb == NULL) { 1179 printf("%s: ahc_intr - referenced scb not " 1180 "valid during SELTO scb(%d, %d)\n", 1181 ahc_name(ahc), scbptr, scb_index); 1182 ahc_dump_card_state(ahc); 1183 } else { 1184 #ifdef AHC_DEBUG 1185 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1186 ahc_print_path(ahc, scb); 1187 printf("Saw Selection Timeout for SCB 0x%x\n", 1188 scb_index); 1189 } 1190 #endif 1191 /* 1192 * Force a renegotiation with this target just in 1193 * case the cable was pulled and will later be 1194 * re-attached. The target may forget its negotiation 1195 * settings with us should it attempt to reselect 1196 * during the interruption. The target will not issue 1197 * a unit attention in this case, so we must always 1198 * renegotiate. 1199 */ 1200 ahc_force_renegotiation(ahc); 1201 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1202 ahc_freeze_devq(ahc, scb); 1203 } 1204 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1205 ahc_restart(ahc); 1206 } else if ((status & BUSFREE) != 0 1207 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1208 u_int lastphase; 1209 u_int saved_scsiid; 1210 u_int saved_lun; 1211 u_int target; 1212 u_int initiator_role_id; 1213 char channel; 1214 int printerror; 1215 1216 /* 1217 * Clear our selection hardware as soon as possible. 1218 * We may have an entry in the waiting Q for this target, 1219 * that is affected by this busfree and we don't want to 1220 * go about selecting the target while we handle the event. 1221 */ 1222 ahc_outb(ahc, SCSISEQ, 1223 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1224 1225 /* 1226 * Disable busfree interrupts and clear the busfree 1227 * interrupt status. We do this here so that several 1228 * bus transactions occur prior to clearing the SCSIINT 1229 * latch. It can take a bit for the clearing to take effect. 1230 */ 1231 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1232 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1233 1234 /* 1235 * Look at what phase we were last in. 1236 * If its message out, chances are pretty good 1237 * that the busfree was in response to one of 1238 * our abort requests. 1239 */ 1240 lastphase = ahc_inb(ahc, LASTPHASE); 1241 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1242 saved_lun = ahc_inb(ahc, SAVED_LUN); 1243 target = SCSIID_TARGET(ahc, saved_scsiid); 1244 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1245 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1246 printerror = 1; 1247 1248 if (lastphase == P_MESGOUT) { 1249 struct ahc_devinfo devinfo; 1250 u_int tag; 1251 1252 ahc_fetch_devinfo(ahc, &devinfo); 1253 tag = SCB_LIST_NULL; 1254 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1255 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1256 if (ahc->msgout_buf[ahc->msgout_index - 1] 1257 == MSG_ABORT_TAG) 1258 tag = scb->hscb->tag; 1259 ahc_print_path(ahc, scb); 1260 printf("SCB %d - Abort%s Completed.\n", 1261 scb->hscb->tag, tag == SCB_LIST_NULL ? 1262 "" : " Tag"); 1263 ahc_abort_scbs(ahc, target, channel, 1264 saved_lun, tag, 1265 ROLE_INITIATOR, 1266 CAM_REQ_ABORTED); 1267 printerror = 0; 1268 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1269 MSG_BUS_DEV_RESET, TRUE)) { 1270 #ifdef __FreeBSD__ 1271 /* 1272 * Don't mark the user's request for this BDR 1273 * as completing with CAM_BDR_SENT. CAM3 1274 * specifies CAM_REQ_CMP. 1275 */ 1276 if (scb != NULL 1277 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1278 && ahc_match_scb(ahc, scb, target, channel, 1279 CAM_LUN_WILDCARD, 1280 SCB_LIST_NULL, 1281 ROLE_INITIATOR)) { 1282 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1283 } 1284 #endif 1285 ahc_compile_devinfo(&devinfo, 1286 initiator_role_id, 1287 target, 1288 CAM_LUN_WILDCARD, 1289 channel, 1290 ROLE_INITIATOR); 1291 ahc_handle_devreset(ahc, &devinfo, 1292 CAM_BDR_SENT, 1293 "Bus Device Reset", 1294 /*verbose_level*/0); 1295 printerror = 0; 1296 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1297 MSG_EXT_PPR, FALSE)) { 1298 struct ahc_initiator_tinfo *tinfo; 1299 struct ahc_tmode_tstate *tstate; 1300 1301 /* 1302 * PPR Rejected. Try non-ppr negotiation 1303 * and retry command. 1304 */ 1305 tinfo = ahc_fetch_transinfo(ahc, 1306 devinfo.channel, 1307 devinfo.our_scsiid, 1308 devinfo.target, 1309 &tstate); 1310 tinfo->curr.transport_version = 2; 1311 tinfo->goal.transport_version = 2; 1312 tinfo->goal.ppr_options = 0; 1313 ahc_qinfifo_requeue_tail(ahc, scb); 1314 printerror = 0; 1315 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1316 MSG_EXT_WDTR, FALSE) 1317 || ahc_sent_msg(ahc, AHCMSG_EXT, 1318 MSG_EXT_SDTR, FALSE)) { 1319 /* 1320 * Negotiation Rejected. Go-async and 1321 * retry command. 1322 */ 1323 ahc_set_width(ahc, &devinfo, 1324 MSG_EXT_WDTR_BUS_8_BIT, 1325 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1326 /*paused*/TRUE); 1327 ahc_set_syncrate(ahc, &devinfo, 1328 /*syncrate*/NULL, 1329 /*period*/0, /*offset*/0, 1330 /*ppr_options*/0, 1331 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1332 /*paused*/TRUE); 1333 ahc_qinfifo_requeue_tail(ahc, scb); 1334 printerror = 0; 1335 } 1336 } 1337 if (printerror != 0) { 1338 u_int i; 1339 1340 if (scb != NULL) { 1341 u_int tag; 1342 1343 if ((scb->hscb->control & TAG_ENB) != 0) 1344 tag = scb->hscb->tag; 1345 else 1346 tag = SCB_LIST_NULL; 1347 ahc_print_path(ahc, scb); 1348 ahc_abort_scbs(ahc, target, channel, 1349 SCB_GET_LUN(scb), tag, 1350 ROLE_INITIATOR, 1351 CAM_UNEXP_BUSFREE); 1352 } else { 1353 /* 1354 * We had not fully identified this connection, 1355 * so we cannot abort anything. 1356 */ 1357 printf("%s: ", ahc_name(ahc)); 1358 } 1359 for (i = 0; i < num_phases; i++) { 1360 if (lastphase == ahc_phase_table[i].phase) 1361 break; 1362 } 1363 /* 1364 * Renegotiate with this device at the 1365 * next oportunity just in case this busfree 1366 * is due to a negotiation mismatch with the 1367 * device. 1368 */ 1369 ahc_force_renegotiation(ahc); 1370 printf("Unexpected busfree %s\n" 1371 "SEQADDR == 0x%x\n", 1372 ahc_phase_table[i].phasemsg, 1373 ahc_inb(ahc, SEQADDR0) 1374 | (ahc_inb(ahc, SEQADDR1) << 8)); 1375 } 1376 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1377 ahc_restart(ahc); 1378 } else { 1379 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1380 ahc_name(ahc), status); 1381 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1382 } 1383 } 1384 1385 /* 1386 * Force renegotiation to occur the next time we initiate 1387 * a command to the current device. 1388 */ 1389 static void 1390 ahc_force_renegotiation(struct ahc_softc *ahc) 1391 { 1392 struct ahc_devinfo devinfo; 1393 struct ahc_initiator_tinfo *targ_info; 1394 struct ahc_tmode_tstate *tstate; 1395 1396 ahc_fetch_devinfo(ahc, &devinfo); 1397 targ_info = ahc_fetch_transinfo(ahc, 1398 devinfo.channel, 1399 devinfo.our_scsiid, 1400 devinfo.target, 1401 &tstate); 1402 ahc_update_neg_request(ahc, &devinfo, tstate, 1403 targ_info, AHC_NEG_IF_NON_ASYNC); 1404 } 1405 1406 #define AHC_MAX_STEPS 2000 1407 void 1408 ahc_clear_critical_section(struct ahc_softc *ahc) 1409 { 1410 int stepping; 1411 int steps; 1412 u_int simode0; 1413 u_int simode1; 1414 1415 if (ahc->num_critical_sections == 0) 1416 return; 1417 1418 stepping = FALSE; 1419 steps = 0; 1420 simode0 = 0; 1421 simode1 = 0; 1422 for (;;) { 1423 struct cs *cs; 1424 u_int seqaddr; 1425 u_int i; 1426 1427 seqaddr = ahc_inb(ahc, SEQADDR0) 1428 | (ahc_inb(ahc, SEQADDR1) << 8); 1429 1430 /* 1431 * Seqaddr represents the next instruction to execute, 1432 * so we are really executing the instruction just 1433 * before it. 1434 */ 1435 if (seqaddr != 0) 1436 seqaddr -= 1; 1437 cs = ahc->critical_sections; 1438 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1439 1440 if (cs->begin < seqaddr && cs->end >= seqaddr) 1441 break; 1442 } 1443 1444 if (i == ahc->num_critical_sections) 1445 break; 1446 1447 if (steps > AHC_MAX_STEPS) { 1448 printf("%s: Infinite loop in critical section\n", 1449 ahc_name(ahc)); 1450 ahc_dump_card_state(ahc); 1451 panic("critical section loop"); 1452 } 1453 1454 steps++; 1455 if (stepping == FALSE) { 1456 1457 /* 1458 * Disable all interrupt sources so that the 1459 * sequencer will not be stuck by a pausing 1460 * interrupt condition while we attempt to 1461 * leave a critical section. 1462 */ 1463 simode0 = ahc_inb(ahc, SIMODE0); 1464 ahc_outb(ahc, SIMODE0, 0); 1465 simode1 = ahc_inb(ahc, SIMODE1); 1466 if ((ahc->features & AHC_DT) != 0) 1467 /* 1468 * On DT class controllers, we 1469 * use the enhanced busfree logic. 1470 * Unfortunately we cannot re-enable 1471 * busfree detection within the 1472 * current connection, so we must 1473 * leave it on while single stepping. 1474 */ 1475 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1476 else 1477 ahc_outb(ahc, SIMODE1, 0); 1478 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1479 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1480 stepping = TRUE; 1481 } 1482 if ((ahc->features & AHC_DT) != 0) { 1483 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1484 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1485 } 1486 ahc_outb(ahc, HCNTRL, ahc->unpause); 1487 while (!ahc_is_paused(ahc)) 1488 ahc_delay(200); 1489 } 1490 if (stepping) { 1491 ahc_outb(ahc, SIMODE0, simode0); 1492 ahc_outb(ahc, SIMODE1, simode1); 1493 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1494 } 1495 } 1496 1497 /* 1498 * Clear any pending interrupt status. 1499 */ 1500 void 1501 ahc_clear_intstat(struct ahc_softc *ahc) 1502 { 1503 /* Clear any interrupt conditions this may have caused */ 1504 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1505 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1506 CLRREQINIT); 1507 ahc_flush_device_writes(ahc); 1508 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1509 ahc_flush_device_writes(ahc); 1510 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1511 ahc_flush_device_writes(ahc); 1512 } 1513 1514 /**************************** Debugging Routines ******************************/ 1515 #ifdef AHC_DEBUG 1516 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1517 #endif 1518 1519 void 1520 ahc_print_scb(struct scb *scb) 1521 { 1522 int i; 1523 1524 struct hardware_scb *hscb = scb->hscb; 1525 1526 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1527 (void *)scb, 1528 hscb->control, 1529 hscb->scsiid, 1530 hscb->lun, 1531 hscb->cdb_len); 1532 printf("Shared Data: "); 1533 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1534 printf("%#02x", hscb->shared_data.cdb[i]); 1535 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1536 ahc_le32toh(hscb->dataptr), 1537 ahc_le32toh(hscb->datacnt), 1538 ahc_le32toh(hscb->sgptr), 1539 hscb->tag); 1540 if (scb->sg_count > 0) { 1541 for (i = 0; i < scb->sg_count; i++) { 1542 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1543 i, 1544 (ahc_le32toh(scb->sg_list[i].len) >> 24 1545 & SG_HIGH_ADDR_BITS), 1546 ahc_le32toh(scb->sg_list[i].addr), 1547 ahc_le32toh(scb->sg_list[i].len)); 1548 } 1549 } 1550 } 1551 1552 /************************* Transfer Negotiation *******************************/ 1553 /* 1554 * Allocate per target mode instance (ID we respond to as a target) 1555 * transfer negotiation data structures. 1556 */ 1557 static struct ahc_tmode_tstate * 1558 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1559 { 1560 struct ahc_tmode_tstate *master_tstate; 1561 struct ahc_tmode_tstate *tstate; 1562 int i; 1563 1564 master_tstate = ahc->enabled_targets[ahc->our_id]; 1565 if (channel == 'B') { 1566 scsi_id += 8; 1567 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1568 } 1569 if (ahc->enabled_targets[scsi_id] != NULL 1570 && ahc->enabled_targets[scsi_id] != master_tstate) 1571 panic("%s: ahc_alloc_tstate - Target already allocated", 1572 ahc_name(ahc)); 1573 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1574 M_DEVBUF, M_NOWAIT); 1575 if (tstate == NULL) 1576 return (NULL); 1577 1578 /* 1579 * If we have allocated a master tstate, copy user settings from 1580 * the master tstate (taken from SRAM or the EEPROM) for this 1581 * channel, but reset our current and goal settings to async/narrow 1582 * until an initiator talks to us. 1583 */ 1584 if (master_tstate != NULL) { 1585 memcpy(tstate, master_tstate, sizeof(*tstate)); 1586 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1587 tstate->ultraenb = 0; 1588 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1589 memset(&tstate->transinfo[i].curr, 0, 1590 sizeof(tstate->transinfo[i].curr)); 1591 memset(&tstate->transinfo[i].goal, 0, 1592 sizeof(tstate->transinfo[i].goal)); 1593 } 1594 } else 1595 memset(tstate, 0, sizeof(*tstate)); 1596 ahc->enabled_targets[scsi_id] = tstate; 1597 return (tstate); 1598 } 1599 1600 #ifdef AHC_TARGET_MODE 1601 /* 1602 * Free per target mode instance (ID we respond to as a target) 1603 * transfer negotiation data structures. 1604 */ 1605 static void 1606 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1607 { 1608 struct ahc_tmode_tstate *tstate; 1609 1610 /* 1611 * Don't clean up our "master" tstate. 1612 * It has our default user settings. 1613 */ 1614 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1615 || (channel == 'A' && scsi_id == ahc->our_id)) 1616 && force == FALSE) 1617 return; 1618 1619 if (channel == 'B') 1620 scsi_id += 8; 1621 tstate = ahc->enabled_targets[scsi_id]; 1622 if (tstate != NULL) 1623 free(tstate, M_DEVBUF); 1624 ahc->enabled_targets[scsi_id] = NULL; 1625 } 1626 #endif 1627 1628 /* 1629 * Called when we have an active connection to a target on the bus, 1630 * this function finds the nearest syncrate to the input period limited 1631 * by the capabilities of the bus connectivity of and sync settings for 1632 * the target. 1633 */ 1634 struct ahc_syncrate * 1635 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1636 struct ahc_initiator_tinfo *tinfo, 1637 u_int *period, u_int *ppr_options, role_t role) 1638 { 1639 struct ahc_transinfo *transinfo; 1640 u_int maxsync; 1641 1642 if ((ahc->features & AHC_ULTRA2) != 0) { 1643 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1644 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1645 maxsync = AHC_SYNCRATE_DT; 1646 } else { 1647 maxsync = AHC_SYNCRATE_ULTRA; 1648 /* Can't do DT on an SE bus */ 1649 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1650 } 1651 } else if ((ahc->features & AHC_ULTRA) != 0) { 1652 maxsync = AHC_SYNCRATE_ULTRA; 1653 } else { 1654 maxsync = AHC_SYNCRATE_FAST; 1655 } 1656 /* 1657 * Never allow a value higher than our current goal 1658 * period otherwise we may allow a target initiated 1659 * negotiation to go above the limit as set by the 1660 * user. In the case of an initiator initiated 1661 * sync negotiation, we limit based on the user 1662 * setting. This allows the system to still accept 1663 * incoming negotiations even if target initiated 1664 * negotiation is not performed. 1665 */ 1666 if (role == ROLE_TARGET) 1667 transinfo = &tinfo->user; 1668 else 1669 transinfo = &tinfo->goal; 1670 *ppr_options &= transinfo->ppr_options; 1671 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1672 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1673 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1674 } 1675 if (transinfo->period == 0) { 1676 *period = 0; 1677 *ppr_options = 0; 1678 return (NULL); 1679 } 1680 *period = MAX(*period, transinfo->period); 1681 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1682 } 1683 1684 /* 1685 * Look up the valid period to SCSIRATE conversion in our table. 1686 * Return the period and offset that should be sent to the target 1687 * if this was the beginning of an SDTR. 1688 */ 1689 struct ahc_syncrate * 1690 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1691 u_int *ppr_options, u_int maxsync) 1692 { 1693 struct ahc_syncrate *syncrate; 1694 1695 if ((ahc->features & AHC_DT) == 0) 1696 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1697 1698 /* Skip all DT only entries if DT is not available */ 1699 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1700 && maxsync < AHC_SYNCRATE_ULTRA2) 1701 maxsync = AHC_SYNCRATE_ULTRA2; 1702 1703 for (syncrate = &ahc_syncrates[maxsync]; 1704 syncrate->rate != NULL; 1705 syncrate++) { 1706 1707 /* 1708 * The Ultra2 table doesn't go as low 1709 * as for the Fast/Ultra cards. 1710 */ 1711 if ((ahc->features & AHC_ULTRA2) != 0 1712 && (syncrate->sxfr_u2 == 0)) 1713 break; 1714 1715 if (*period <= syncrate->period) { 1716 /* 1717 * When responding to a target that requests 1718 * sync, the requested rate may fall between 1719 * two rates that we can output, but still be 1720 * a rate that we can receive. Because of this, 1721 * we want to respond to the target with 1722 * the same rate that it sent to us even 1723 * if the period we use to send data to it 1724 * is lower. Only lower the response period 1725 * if we must. 1726 */ 1727 if (syncrate == &ahc_syncrates[maxsync]) 1728 *period = syncrate->period; 1729 1730 /* 1731 * At some speeds, we only support 1732 * ST transfers. 1733 */ 1734 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1735 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1736 break; 1737 } 1738 } 1739 1740 if ((*period == 0) 1741 || (syncrate->rate == NULL) 1742 || ((ahc->features & AHC_ULTRA2) != 0 1743 && (syncrate->sxfr_u2 == 0))) { 1744 /* Use asynchronous transfers. */ 1745 *period = 0; 1746 syncrate = NULL; 1747 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1748 } 1749 return (syncrate); 1750 } 1751 1752 /* 1753 * Convert from an entry in our syncrate table to the SCSI equivalent 1754 * sync "period" factor. 1755 */ 1756 u_int 1757 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1758 { 1759 struct ahc_syncrate *syncrate; 1760 1761 if ((ahc->features & AHC_ULTRA2) != 0) 1762 scsirate &= SXFR_ULTRA2; 1763 else 1764 scsirate &= SXFR; 1765 1766 syncrate = &ahc_syncrates[maxsync]; 1767 while (syncrate->rate != NULL) { 1768 1769 if ((ahc->features & AHC_ULTRA2) != 0) { 1770 if (syncrate->sxfr_u2 == 0) 1771 break; 1772 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1773 return (syncrate->period); 1774 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1775 return (syncrate->period); 1776 } 1777 syncrate++; 1778 } 1779 return (0); /* async */ 1780 } 1781 1782 /* 1783 * Truncate the given synchronous offset to a value the 1784 * current adapter type and syncrate are capable of. 1785 */ 1786 void 1787 ahc_validate_offset(struct ahc_softc *ahc, 1788 struct ahc_initiator_tinfo *tinfo, 1789 struct ahc_syncrate *syncrate, 1790 u_int *offset, int wide, role_t role) 1791 { 1792 u_int maxoffset; 1793 1794 /* Limit offset to what we can do */ 1795 if (syncrate == NULL) { 1796 maxoffset = 0; 1797 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1798 maxoffset = MAX_OFFSET_ULTRA2; 1799 } else { 1800 if (wide) 1801 maxoffset = MAX_OFFSET_16BIT; 1802 else 1803 maxoffset = MAX_OFFSET_8BIT; 1804 } 1805 *offset = MIN(*offset, maxoffset); 1806 if (tinfo != NULL) { 1807 if (role == ROLE_TARGET) 1808 *offset = MIN(*offset, tinfo->user.offset); 1809 else 1810 *offset = MIN(*offset, tinfo->goal.offset); 1811 } 1812 } 1813 1814 /* 1815 * Truncate the given transfer width parameter to a value the 1816 * current adapter type is capable of. 1817 */ 1818 void 1819 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1820 u_int *bus_width, role_t role) 1821 { 1822 switch (*bus_width) { 1823 default: 1824 if (ahc->features & AHC_WIDE) { 1825 /* Respond Wide */ 1826 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1827 break; 1828 } 1829 /* FALLTHROUGH */ 1830 case MSG_EXT_WDTR_BUS_8_BIT: 1831 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1832 break; 1833 } 1834 if (tinfo != NULL) { 1835 if (role == ROLE_TARGET) 1836 *bus_width = MIN(tinfo->user.width, *bus_width); 1837 else 1838 *bus_width = MIN(tinfo->goal.width, *bus_width); 1839 } 1840 } 1841 1842 /* 1843 * Update the bitmask of targets for which the controller should 1844 * negotiate with at the next convenient oportunity. This currently 1845 * means the next time we send the initial identify messages for 1846 * a new transaction. 1847 */ 1848 int 1849 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1850 struct ahc_tmode_tstate *tstate, 1851 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1852 { 1853 u_int auto_negotiate_orig; 1854 1855 auto_negotiate_orig = tstate->auto_negotiate; 1856 if (neg_type == AHC_NEG_ALWAYS) { 1857 /* 1858 * Force our "current" settings to be 1859 * unknown so that unless a bus reset 1860 * occurs the need to renegotiate is 1861 * recorded persistently. 1862 */ 1863 if ((ahc->features & AHC_WIDE) != 0) 1864 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1865 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1866 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1867 } 1868 if (tinfo->curr.period != tinfo->goal.period 1869 || tinfo->curr.width != tinfo->goal.width 1870 || tinfo->curr.offset != tinfo->goal.offset 1871 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1872 || (neg_type == AHC_NEG_IF_NON_ASYNC 1873 && (tinfo->goal.offset != 0 1874 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1875 || tinfo->goal.ppr_options != 0))) 1876 tstate->auto_negotiate |= devinfo->target_mask; 1877 else 1878 tstate->auto_negotiate &= ~devinfo->target_mask; 1879 1880 return (auto_negotiate_orig != tstate->auto_negotiate); 1881 } 1882 1883 /* 1884 * Update the user/goal/curr tables of synchronous negotiation 1885 * parameters as well as, in the case of a current or active update, 1886 * any data structures on the host controller. In the case of an 1887 * active update, the specified target is currently talking to us on 1888 * the bus, so the transfer parameter update must take effect 1889 * immediately. 1890 */ 1891 void 1892 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1893 struct ahc_syncrate *syncrate, u_int period, 1894 u_int offset, u_int ppr_options, u_int type, int paused) 1895 { 1896 struct ahc_initiator_tinfo *tinfo; 1897 struct ahc_tmode_tstate *tstate; 1898 u_int old_period; 1899 u_int old_offset; 1900 u_int old_ppr; 1901 int active; 1902 int update_needed; 1903 1904 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1905 update_needed = 0; 1906 1907 if (syncrate == NULL) { 1908 period = 0; 1909 offset = 0; 1910 } 1911 1912 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1913 devinfo->target, &tstate); 1914 1915 if ((type & AHC_TRANS_USER) != 0) { 1916 tinfo->user.period = period; 1917 tinfo->user.offset = offset; 1918 tinfo->user.ppr_options = ppr_options; 1919 } 1920 1921 if ((type & AHC_TRANS_GOAL) != 0) { 1922 tinfo->goal.period = period; 1923 tinfo->goal.offset = offset; 1924 tinfo->goal.ppr_options = ppr_options; 1925 } 1926 1927 old_period = tinfo->curr.period; 1928 old_offset = tinfo->curr.offset; 1929 old_ppr = tinfo->curr.ppr_options; 1930 1931 if ((type & AHC_TRANS_CUR) != 0 1932 && (old_period != period 1933 || old_offset != offset 1934 || old_ppr != ppr_options)) { 1935 u_int scsirate; 1936 1937 update_needed++; 1938 scsirate = tinfo->scsirate; 1939 if ((ahc->features & AHC_ULTRA2) != 0) { 1940 1941 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1942 if (syncrate != NULL) { 1943 scsirate |= syncrate->sxfr_u2; 1944 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1945 scsirate |= ENABLE_CRC; 1946 else 1947 scsirate |= SINGLE_EDGE; 1948 } 1949 } else { 1950 1951 scsirate &= ~(SXFR|SOFS); 1952 /* 1953 * Ensure Ultra mode is set properly for 1954 * this target. 1955 */ 1956 tstate->ultraenb &= ~devinfo->target_mask; 1957 if (syncrate != NULL) { 1958 if (syncrate->sxfr & ULTRA_SXFR) { 1959 tstate->ultraenb |= 1960 devinfo->target_mask; 1961 } 1962 scsirate |= syncrate->sxfr & SXFR; 1963 scsirate |= offset & SOFS; 1964 } 1965 if (active) { 1966 u_int sxfrctl0; 1967 1968 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1969 sxfrctl0 &= ~FAST20; 1970 if (tstate->ultraenb & devinfo->target_mask) 1971 sxfrctl0 |= FAST20; 1972 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1973 } 1974 } 1975 if (active) { 1976 ahc_outb(ahc, SCSIRATE, scsirate); 1977 if ((ahc->features & AHC_ULTRA2) != 0) 1978 ahc_outb(ahc, SCSIOFFSET, offset); 1979 } 1980 1981 tinfo->scsirate = scsirate; 1982 tinfo->curr.period = period; 1983 tinfo->curr.offset = offset; 1984 tinfo->curr.ppr_options = ppr_options; 1985 1986 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1987 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1988 if (bootverbose) { 1989 if (offset != 0) { 1990 printf("%s: target %d synchronous at %sMHz%s, " 1991 "offset = 0x%x\n", ahc_name(ahc), 1992 devinfo->target, syncrate->rate, 1993 (ppr_options & MSG_EXT_PPR_DT_REQ) 1994 ? " DT" : "", offset); 1995 } else { 1996 printf("%s: target %d using " 1997 "asynchronous transfers\n", 1998 ahc_name(ahc), devinfo->target); 1999 } 2000 } 2001 } 2002 2003 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2004 tinfo, AHC_NEG_TO_GOAL); 2005 2006 if (update_needed) 2007 ahc_update_pending_scbs(ahc); 2008 } 2009 2010 /* 2011 * Update the user/goal/curr tables of wide negotiation 2012 * parameters as well as, in the case of a current or active update, 2013 * any data structures on the host controller. In the case of an 2014 * active update, the specified target is currently talking to us on 2015 * the bus, so the transfer parameter update must take effect 2016 * immediately. 2017 */ 2018 void 2019 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2020 u_int width, u_int type, int paused) 2021 { 2022 struct ahc_initiator_tinfo *tinfo; 2023 struct ahc_tmode_tstate *tstate; 2024 u_int oldwidth; 2025 int active; 2026 int update_needed; 2027 2028 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2029 update_needed = 0; 2030 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2031 devinfo->target, &tstate); 2032 2033 if ((type & AHC_TRANS_USER) != 0) 2034 tinfo->user.width = width; 2035 2036 if ((type & AHC_TRANS_GOAL) != 0) 2037 tinfo->goal.width = width; 2038 2039 oldwidth = tinfo->curr.width; 2040 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2041 u_int scsirate; 2042 2043 update_needed++; 2044 scsirate = tinfo->scsirate; 2045 scsirate &= ~WIDEXFER; 2046 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2047 scsirate |= WIDEXFER; 2048 2049 tinfo->scsirate = scsirate; 2050 2051 if (active) 2052 ahc_outb(ahc, SCSIRATE, scsirate); 2053 2054 tinfo->curr.width = width; 2055 2056 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2057 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2058 if (bootverbose) { 2059 printf("%s: target %d using %dbit transfers\n", 2060 ahc_name(ahc), devinfo->target, 2061 8 * (0x01 << width)); 2062 } 2063 } 2064 2065 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2066 tinfo, AHC_NEG_TO_GOAL); 2067 if (update_needed) 2068 ahc_update_pending_scbs(ahc); 2069 } 2070 2071 /* 2072 * Update the current state of tagged queuing for a given target. 2073 */ 2074 void 2075 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2076 ahc_queue_alg alg) 2077 { 2078 ahc_platform_set_tags(ahc, devinfo, alg); 2079 } 2080 2081 /* 2082 * When the transfer settings for a connection change, update any 2083 * in-transit SCBs to contain the new data so the hardware will 2084 * be set correctly during future (re)selections. 2085 */ 2086 static void 2087 ahc_update_pending_scbs(struct ahc_softc *ahc) 2088 { 2089 struct scb *pending_scb; 2090 int pending_scb_count; 2091 int i; 2092 int paused; 2093 u_int saved_scbptr; 2094 2095 /* 2096 * Traverse the pending SCB list and ensure that all of the 2097 * SCBs there have the proper settings. 2098 */ 2099 pending_scb_count = 0; 2100 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2101 struct ahc_devinfo devinfo; 2102 struct hardware_scb *pending_hscb; 2103 struct ahc_initiator_tinfo *tinfo; 2104 struct ahc_tmode_tstate *tstate; 2105 2106 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2107 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2108 devinfo.our_scsiid, 2109 devinfo.target, &tstate); 2110 pending_hscb = pending_scb->hscb; 2111 pending_hscb->control &= ~ULTRAENB; 2112 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2113 pending_hscb->control |= ULTRAENB; 2114 pending_hscb->scsirate = tinfo->scsirate; 2115 pending_hscb->scsioffset = tinfo->curr.offset; 2116 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2117 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2118 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2119 pending_hscb->control &= ~MK_MESSAGE; 2120 } 2121 ahc_sync_scb(ahc, pending_scb, 2122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2123 pending_scb_count++; 2124 } 2125 2126 if (pending_scb_count == 0) 2127 return; 2128 2129 if (ahc_is_paused(ahc)) { 2130 paused = 1; 2131 } else { 2132 paused = 0; 2133 ahc_pause(ahc); 2134 } 2135 2136 saved_scbptr = ahc_inb(ahc, SCBPTR); 2137 /* Ensure that the hscbs down on the card match the new information */ 2138 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2139 struct hardware_scb *pending_hscb; 2140 u_int control; 2141 u_int scb_tag; 2142 2143 ahc_outb(ahc, SCBPTR, i); 2144 scb_tag = ahc_inb(ahc, SCB_TAG); 2145 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2146 if (pending_scb == NULL) 2147 continue; 2148 2149 pending_hscb = pending_scb->hscb; 2150 control = ahc_inb(ahc, SCB_CONTROL); 2151 control &= ~(ULTRAENB|MK_MESSAGE); 2152 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2153 ahc_outb(ahc, SCB_CONTROL, control); 2154 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2155 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2156 } 2157 ahc_outb(ahc, SCBPTR, saved_scbptr); 2158 2159 if (paused == 0) 2160 ahc_unpause(ahc); 2161 } 2162 2163 /**************************** Pathing Information *****************************/ 2164 static void 2165 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2166 { 2167 u_int saved_scsiid; 2168 role_t role; 2169 int our_id; 2170 2171 if (ahc_inb(ahc, SSTAT0) & TARGET) 2172 role = ROLE_TARGET; 2173 else 2174 role = ROLE_INITIATOR; 2175 2176 if (role == ROLE_TARGET 2177 && (ahc->features & AHC_MULTI_TID) != 0 2178 && (ahc_inb(ahc, SEQ_FLAGS) 2179 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2180 /* We were selected, so pull our id from TARGIDIN */ 2181 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2182 } else if ((ahc->features & AHC_ULTRA2) != 0) 2183 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2184 else 2185 our_id = ahc_inb(ahc, SCSIID) & OID; 2186 2187 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2188 ahc_compile_devinfo(devinfo, 2189 our_id, 2190 SCSIID_TARGET(ahc, saved_scsiid), 2191 ahc_inb(ahc, SAVED_LUN), 2192 SCSIID_CHANNEL(ahc, saved_scsiid), 2193 role); 2194 } 2195 2196 struct ahc_phase_table_entry* 2197 ahc_lookup_phase_entry(int phase) 2198 { 2199 struct ahc_phase_table_entry *entry; 2200 struct ahc_phase_table_entry *last_entry; 2201 2202 /* 2203 * num_phases doesn't include the default entry which 2204 * will be returned if the phase doesn't match. 2205 */ 2206 last_entry = &ahc_phase_table[num_phases]; 2207 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2208 if (phase == entry->phase) 2209 break; 2210 } 2211 return (entry); 2212 } 2213 2214 void 2215 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2216 u_int lun, char channel, role_t role) 2217 { 2218 devinfo->our_scsiid = our_id; 2219 devinfo->target = target; 2220 devinfo->lun = lun; 2221 devinfo->target_offset = target; 2222 devinfo->channel = channel; 2223 devinfo->role = role; 2224 if (channel == 'B') 2225 devinfo->target_offset += 8; 2226 devinfo->target_mask = (0x01 << devinfo->target_offset); 2227 } 2228 2229 void 2230 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2231 { 2232 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2233 devinfo->target, devinfo->lun); 2234 } 2235 2236 static void 2237 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2238 struct scb *scb) 2239 { 2240 role_t role; 2241 int our_id; 2242 2243 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2244 role = ROLE_INITIATOR; 2245 if ((scb->flags & SCB_TARGET_SCB) != 0) 2246 role = ROLE_TARGET; 2247 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2248 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2249 } 2250 2251 2252 /************************ Message Phase Processing ****************************/ 2253 static void 2254 ahc_assert_atn(struct ahc_softc *ahc) 2255 { 2256 u_int scsisigo; 2257 2258 scsisigo = ATNO; 2259 if ((ahc->features & AHC_DT) == 0) 2260 scsisigo |= ahc_inb(ahc, SCSISIGI); 2261 ahc_outb(ahc, SCSISIGO, scsisigo); 2262 } 2263 2264 /* 2265 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2266 * or enters the initial message out phase, we are interrupted. Fill our 2267 * outgoing message buffer with the appropriate message and beging handing 2268 * the message phase(s) manually. 2269 */ 2270 static void 2271 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2272 struct scb *scb) 2273 { 2274 /* 2275 * To facilitate adding multiple messages together, 2276 * each routine should increment the index and len 2277 * variables instead of setting them explicitly. 2278 */ 2279 ahc->msgout_index = 0; 2280 ahc->msgout_len = 0; 2281 2282 if ((scb->flags & SCB_DEVICE_RESET) == 0 2283 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2284 u_int identify_msg; 2285 2286 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2287 if ((scb->hscb->control & DISCENB) != 0) 2288 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2289 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2290 ahc->msgout_len++; 2291 2292 if ((scb->hscb->control & TAG_ENB) != 0) { 2293 ahc->msgout_buf[ahc->msgout_index++] = 2294 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2295 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2296 ahc->msgout_len += 2; 2297 } 2298 } 2299 2300 if (scb->flags & SCB_DEVICE_RESET) { 2301 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2302 ahc->msgout_len++; 2303 ahc_print_path(ahc, scb); 2304 printf("Bus Device Reset Message Sent\n"); 2305 /* 2306 * Clear our selection hardware in advance of 2307 * the busfree. We may have an entry in the waiting 2308 * Q for this target, and we don't want to go about 2309 * selecting while we handle the busfree and blow it 2310 * away. 2311 */ 2312 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2313 } else if ((scb->flags & SCB_ABORT) != 0) { 2314 if ((scb->hscb->control & TAG_ENB) != 0) 2315 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2316 else 2317 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2318 ahc->msgout_len++; 2319 ahc_print_path(ahc, scb); 2320 printf("Abort%s Message Sent\n", 2321 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2322 /* 2323 * Clear our selection hardware in advance of 2324 * the busfree. We may have an entry in the waiting 2325 * Q for this target, and we don't want to go about 2326 * selecting while we handle the busfree and blow it 2327 * away. 2328 */ 2329 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2330 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2331 ahc_build_transfer_msg(ahc, devinfo); 2332 } else { 2333 printf("ahc_intr: AWAITING_MSG for an SCB that " 2334 "does not have a waiting message\n"); 2335 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2336 devinfo->target_mask); 2337 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2338 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2339 ahc_inb(ahc, MSG_OUT), scb->flags); 2340 } 2341 2342 /* 2343 * Clear the MK_MESSAGE flag from the SCB so we aren't 2344 * asked to send this message again. 2345 */ 2346 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2347 scb->hscb->control &= ~MK_MESSAGE; 2348 ahc->msgout_index = 0; 2349 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2350 } 2351 2352 /* 2353 * Build an appropriate transfer negotiation message for the 2354 * currently active target. 2355 */ 2356 static void 2357 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2358 { 2359 /* 2360 * We need to initiate transfer negotiations. 2361 * If our current and goal settings are identical, 2362 * we want to renegotiate due to a check condition. 2363 */ 2364 struct ahc_initiator_tinfo *tinfo; 2365 struct ahc_tmode_tstate *tstate; 2366 struct ahc_syncrate *rate; 2367 int dowide; 2368 int dosync; 2369 int doppr; 2370 u_int period; 2371 u_int ppr_options; 2372 u_int offset; 2373 2374 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2375 devinfo->target, &tstate); 2376 /* 2377 * Filter our period based on the current connection. 2378 * If we can't perform DT transfers on this segment (not in LVD 2379 * mode for instance), then our decision to issue a PPR message 2380 * may change. 2381 */ 2382 period = tinfo->goal.period; 2383 ppr_options = tinfo->goal.ppr_options; 2384 /* Target initiated PPR is not allowed in the SCSI spec */ 2385 if (devinfo->role == ROLE_TARGET) 2386 ppr_options = 0; 2387 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2388 &ppr_options, devinfo->role); 2389 dowide = tinfo->curr.width != tinfo->goal.width; 2390 dosync = tinfo->curr.period != period; 2391 /* 2392 * Only use PPR if we have options that need it, even if the device 2393 * claims to support it. There might be an expander in the way 2394 * that doesn't. 2395 */ 2396 doppr = ppr_options != 0; 2397 2398 if (!dowide && !dosync && !doppr) { 2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2400 dosync = tinfo->goal.offset != 0; 2401 } 2402 2403 if (!dowide && !dosync && !doppr) { 2404 /* 2405 * Force async with a WDTR message if we have a wide bus, 2406 * or just issue an SDTR with a 0 offset. 2407 */ 2408 if ((ahc->features & AHC_WIDE) != 0) 2409 dowide = 1; 2410 else 2411 dosync = 1; 2412 2413 if (bootverbose) { 2414 ahc_print_devinfo(ahc, devinfo); 2415 printf("Ensuring async\n"); 2416 } 2417 } 2418 2419 /* Target initiated PPR is not allowed in the SCSI spec */ 2420 if (devinfo->role == ROLE_TARGET) 2421 doppr = 0; 2422 2423 /* 2424 * Both the PPR message and SDTR message require the 2425 * goal syncrate to be limited to what the target device 2426 * is capable of handling (based on whether an LVD->SE 2427 * expander is on the bus), so combine these two cases. 2428 * Regardless, guarantee that if we are using WDTR and SDTR 2429 * messages that WDTR comes first. 2430 */ 2431 if (doppr || (dosync && !dowide)) { 2432 2433 offset = tinfo->goal.offset; 2434 ahc_validate_offset(ahc, tinfo, rate, &offset, 2435 doppr ? tinfo->goal.width 2436 : tinfo->curr.width, 2437 devinfo->role); 2438 if (doppr) { 2439 ahc_construct_ppr(ahc, devinfo, period, offset, 2440 tinfo->goal.width, ppr_options); 2441 } else { 2442 ahc_construct_sdtr(ahc, devinfo, period, offset); 2443 } 2444 } else { 2445 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2446 } 2447 } 2448 2449 /* 2450 * Build a synchronous negotiation message in our message 2451 * buffer based on the input parameters. 2452 */ 2453 static void 2454 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2455 u_int period, u_int offset) 2456 { 2457 if (offset == 0) 2458 period = AHC_ASYNC_XFER_PERIOD; 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2462 ahc->msgout_buf[ahc->msgout_index++] = period; 2463 ahc->msgout_buf[ahc->msgout_index++] = offset; 2464 ahc->msgout_len += 5; 2465 if (bootverbose) { 2466 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2467 ahc_name(ahc), devinfo->channel, devinfo->target, 2468 devinfo->lun, period, offset); 2469 } 2470 } 2471 2472 /* 2473 * Build a wide negotiation message in our message 2474 * buffer based on the input parameters. 2475 */ 2476 static void 2477 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2478 u_int bus_width) 2479 { 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2483 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2484 ahc->msgout_len += 4; 2485 if (bootverbose) { 2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2487 ahc_name(ahc), devinfo->channel, devinfo->target, 2488 devinfo->lun, bus_width); 2489 } 2490 } 2491 2492 /* 2493 * Build a parallel protocol request message in our message 2494 * buffer based on the input parameters. 2495 */ 2496 static void 2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2498 u_int period, u_int offset, u_int bus_width, 2499 u_int ppr_options) 2500 { 2501 if (offset == 0) 2502 period = AHC_ASYNC_XFER_PERIOD; 2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2506 ahc->msgout_buf[ahc->msgout_index++] = period; 2507 ahc->msgout_buf[ahc->msgout_index++] = 0; 2508 ahc->msgout_buf[ahc->msgout_index++] = offset; 2509 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2510 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2511 ahc->msgout_len += 8; 2512 if (bootverbose) { 2513 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2514 "offset %x, ppr_options %x\n", ahc_name(ahc), 2515 devinfo->channel, devinfo->target, devinfo->lun, 2516 bus_width, period, offset, ppr_options); 2517 } 2518 } 2519 2520 /* 2521 * Clear any active message state. 2522 */ 2523 static void 2524 ahc_clear_msg_state(struct ahc_softc *ahc) 2525 { 2526 ahc->msgout_len = 0; 2527 ahc->msgin_index = 0; 2528 ahc->msg_type = MSG_TYPE_NONE; 2529 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2530 /* 2531 * The target didn't care to respond to our 2532 * message request, so clear ATN. 2533 */ 2534 ahc_outb(ahc, CLRSINT1, CLRATNO); 2535 } 2536 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2537 ahc_outb(ahc, SEQ_FLAGS2, 2538 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2539 } 2540 2541 static void 2542 ahc_handle_proto_violation(struct ahc_softc *ahc) 2543 { 2544 struct ahc_devinfo devinfo; 2545 struct scb *scb; 2546 u_int scbid; 2547 u_int seq_flags; 2548 u_int curphase; 2549 u_int lastphase; 2550 int found; 2551 2552 ahc_fetch_devinfo(ahc, &devinfo); 2553 scbid = ahc_inb(ahc, SCB_TAG); 2554 scb = ahc_lookup_scb(ahc, scbid); 2555 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2556 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2557 lastphase = ahc_inb(ahc, LASTPHASE); 2558 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2559 2560 /* 2561 * The reconnecting target either did not send an 2562 * identify message, or did, but we didn't find an SCB 2563 * to match. 2564 */ 2565 ahc_print_devinfo(ahc, &devinfo); 2566 printf("Target did not send an IDENTIFY message. " 2567 "LASTPHASE = 0x%x.\n", lastphase); 2568 scb = NULL; 2569 } else if (scb == NULL) { 2570 /* 2571 * We don't seem to have an SCB active for this 2572 * transaction. Print an error and reset the bus. 2573 */ 2574 ahc_print_devinfo(ahc, &devinfo); 2575 printf("No SCB found during protocol violation\n"); 2576 goto proto_violation_reset; 2577 } else { 2578 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2579 if ((seq_flags & NO_CDB_SENT) != 0) { 2580 ahc_print_path(ahc, scb); 2581 printf("No or incomplete CDB sent to device.\n"); 2582 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2583 /* 2584 * The target never bothered to provide status to 2585 * us prior to completing the command. Since we don't 2586 * know the disposition of this command, we must attempt 2587 * to abort it. Assert ATN and prepare to send an abort 2588 * message. 2589 */ 2590 ahc_print_path(ahc, scb); 2591 printf("Completed command without status.\n"); 2592 } else { 2593 ahc_print_path(ahc, scb); 2594 printf("Unknown protocol violation.\n"); 2595 ahc_dump_card_state(ahc); 2596 } 2597 } 2598 if ((lastphase & ~P_DATAIN_DT) == 0 2599 || lastphase == P_COMMAND) { 2600 proto_violation_reset: 2601 /* 2602 * Target either went directly to data/command 2603 * phase or didn't respond to our ATN. 2604 * The only safe thing to do is to blow 2605 * it away with a bus reset. 2606 */ 2607 found = ahc_reset_channel(ahc, 'A', TRUE); 2608 printf("%s: Issued Channel %c Bus Reset. " 2609 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2610 } else { 2611 /* 2612 * Leave the selection hardware off in case 2613 * this abort attempt will affect yet to 2614 * be sent commands. 2615 */ 2616 ahc_outb(ahc, SCSISEQ, 2617 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2618 ahc_assert_atn(ahc); 2619 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2620 if (scb == NULL) { 2621 ahc_print_devinfo(ahc, &devinfo); 2622 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2623 ahc->msgout_len = 1; 2624 ahc->msgout_index = 0; 2625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2626 } else { 2627 ahc_print_path(ahc, scb); 2628 scb->flags |= SCB_ABORT; 2629 } 2630 printf("Protocol violation %s. Attempting to abort.\n", 2631 ahc_lookup_phase_entry(curphase)->phasemsg); 2632 } 2633 } 2634 2635 /* 2636 * Manual message loop handler. 2637 */ 2638 static void 2639 ahc_handle_message_phase(struct ahc_softc *ahc) 2640 { 2641 struct ahc_devinfo devinfo; 2642 u_int bus_phase; 2643 int end_session; 2644 2645 ahc_fetch_devinfo(ahc, &devinfo); 2646 end_session = FALSE; 2647 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2648 2649 reswitch: 2650 switch (ahc->msg_type) { 2651 case MSG_TYPE_INITIATOR_MSGOUT: 2652 { 2653 int lastbyte; 2654 int phasemis; 2655 int msgdone; 2656 2657 if (ahc->msgout_len == 0) 2658 panic("HOST_MSG_LOOP interrupt with no active message"); 2659 2660 #ifdef AHC_DEBUG 2661 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2662 ahc_print_devinfo(ahc, &devinfo); 2663 printf("INITIATOR_MSG_OUT"); 2664 } 2665 #endif 2666 phasemis = bus_phase != P_MESGOUT; 2667 if (phasemis) { 2668 #ifdef AHC_DEBUG 2669 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2670 printf(" PHASEMIS %s\n", 2671 ahc_lookup_phase_entry(bus_phase) 2672 ->phasemsg); 2673 } 2674 #endif 2675 if (bus_phase == P_MESGIN) { 2676 /* 2677 * Change gears and see if 2678 * this messages is of interest to 2679 * us or should be passed back to 2680 * the sequencer. 2681 */ 2682 ahc_outb(ahc, CLRSINT1, CLRATNO); 2683 ahc->send_msg_perror = FALSE; 2684 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2685 ahc->msgin_index = 0; 2686 goto reswitch; 2687 } 2688 end_session = TRUE; 2689 break; 2690 } 2691 2692 if (ahc->send_msg_perror) { 2693 ahc_outb(ahc, CLRSINT1, CLRATNO); 2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2695 #ifdef AHC_DEBUG 2696 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2697 printf(" byte 0x%x\n", ahc->send_msg_perror); 2698 #endif 2699 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2700 break; 2701 } 2702 2703 msgdone = ahc->msgout_index == ahc->msgout_len; 2704 if (msgdone) { 2705 /* 2706 * The target has requested a retry. 2707 * Re-assert ATN, reset our message index to 2708 * 0, and try again. 2709 */ 2710 ahc->msgout_index = 0; 2711 ahc_assert_atn(ahc); 2712 } 2713 2714 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2715 if (lastbyte) { 2716 /* Last byte is signified by dropping ATN */ 2717 ahc_outb(ahc, CLRSINT1, CLRATNO); 2718 } 2719 2720 /* 2721 * Clear our interrupt status and present 2722 * the next byte on the bus. 2723 */ 2724 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2725 #ifdef AHC_DEBUG 2726 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2727 printf(" byte 0x%x\n", 2728 ahc->msgout_buf[ahc->msgout_index]); 2729 #endif 2730 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2731 break; 2732 } 2733 case MSG_TYPE_INITIATOR_MSGIN: 2734 { 2735 int phasemis; 2736 int message_done; 2737 2738 #ifdef AHC_DEBUG 2739 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2740 ahc_print_devinfo(ahc, &devinfo); 2741 printf("INITIATOR_MSG_IN"); 2742 } 2743 #endif 2744 phasemis = bus_phase != P_MESGIN; 2745 if (phasemis) { 2746 #ifdef AHC_DEBUG 2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2748 printf(" PHASEMIS %s\n", 2749 ahc_lookup_phase_entry(bus_phase) 2750 ->phasemsg); 2751 } 2752 #endif 2753 ahc->msgin_index = 0; 2754 if (bus_phase == P_MESGOUT 2755 && (ahc->send_msg_perror == TRUE 2756 || (ahc->msgout_len != 0 2757 && ahc->msgout_index == 0))) { 2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2759 goto reswitch; 2760 } 2761 end_session = TRUE; 2762 break; 2763 } 2764 2765 /* Pull the byte in without acking it */ 2766 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2767 #ifdef AHC_DEBUG 2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2769 printf(" byte 0x%x\n", 2770 ahc->msgin_buf[ahc->msgin_index]); 2771 #endif 2772 2773 message_done = ahc_parse_msg(ahc, &devinfo); 2774 2775 if (message_done) { 2776 /* 2777 * Clear our incoming message buffer in case there 2778 * is another message following this one. 2779 */ 2780 ahc->msgin_index = 0; 2781 2782 /* 2783 * If this message illicited a response, 2784 * assert ATN so the target takes us to the 2785 * message out phase. 2786 */ 2787 if (ahc->msgout_len != 0) { 2788 #ifdef AHC_DEBUG 2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2790 ahc_print_devinfo(ahc, &devinfo); 2791 printf("Asserting ATN for response\n"); 2792 } 2793 #endif 2794 ahc_assert_atn(ahc); 2795 } 2796 } else 2797 ahc->msgin_index++; 2798 2799 if (message_done == MSGLOOP_TERMINATED) { 2800 end_session = TRUE; 2801 } else { 2802 /* Ack the byte */ 2803 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2804 ahc_inb(ahc, SCSIDATL); 2805 } 2806 break; 2807 } 2808 case MSG_TYPE_TARGET_MSGIN: 2809 { 2810 int msgdone; 2811 int msgout_request; 2812 2813 if (ahc->msgout_len == 0) 2814 panic("Target MSGIN with no active message"); 2815 2816 /* 2817 * If we interrupted a mesgout session, the initiator 2818 * will not know this until our first REQ. So, we 2819 * only honor mesgout requests after we've sent our 2820 * first byte. 2821 */ 2822 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2823 && ahc->msgout_index > 0) 2824 msgout_request = TRUE; 2825 else 2826 msgout_request = FALSE; 2827 2828 if (msgout_request) { 2829 2830 /* 2831 * Change gears and see if 2832 * this messages is of interest to 2833 * us or should be passed back to 2834 * the sequencer. 2835 */ 2836 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2837 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2838 ahc->msgin_index = 0; 2839 /* Dummy read to REQ for first byte */ 2840 ahc_inb(ahc, SCSIDATL); 2841 ahc_outb(ahc, SXFRCTL0, 2842 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2843 break; 2844 } 2845 2846 msgdone = ahc->msgout_index == ahc->msgout_len; 2847 if (msgdone) { 2848 ahc_outb(ahc, SXFRCTL0, 2849 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2850 end_session = TRUE; 2851 break; 2852 } 2853 2854 /* 2855 * Present the next byte on the bus. 2856 */ 2857 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2858 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2859 break; 2860 } 2861 case MSG_TYPE_TARGET_MSGOUT: 2862 { 2863 int lastbyte; 2864 int msgdone; 2865 2866 /* 2867 * The initiator signals that this is 2868 * the last byte by dropping ATN. 2869 */ 2870 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2871 2872 /* 2873 * Read the latched byte, but turn off SPIOEN first 2874 * so that we don't inadvertently cause a REQ for the 2875 * next byte. 2876 */ 2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2878 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2879 msgdone = ahc_parse_msg(ahc, &devinfo); 2880 if (msgdone == MSGLOOP_TERMINATED) { 2881 /* 2882 * The message is *really* done in that it caused 2883 * us to go to bus free. The sequencer has already 2884 * been reset at this point, so pull the ejection 2885 * handle. 2886 */ 2887 return; 2888 } 2889 2890 ahc->msgin_index++; 2891 2892 /* 2893 * XXX Read spec about initiator dropping ATN too soon 2894 * and use msgdone to detect it. 2895 */ 2896 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2897 ahc->msgin_index = 0; 2898 2899 /* 2900 * If this message illicited a response, transition 2901 * to the Message in phase and send it. 2902 */ 2903 if (ahc->msgout_len != 0) { 2904 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2905 ahc_outb(ahc, SXFRCTL0, 2906 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2907 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2908 ahc->msgin_index = 0; 2909 break; 2910 } 2911 } 2912 2913 if (lastbyte) 2914 end_session = TRUE; 2915 else { 2916 /* Ask for the next byte. */ 2917 ahc_outb(ahc, SXFRCTL0, 2918 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2919 } 2920 2921 break; 2922 } 2923 default: 2924 panic("Unknown REQINIT message type"); 2925 } 2926 2927 if (end_session) { 2928 ahc_clear_msg_state(ahc); 2929 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2930 } else 2931 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2932 } 2933 2934 /* 2935 * See if we sent a particular extended message to the target. 2936 * If "full" is true, return true only if the target saw the full 2937 * message. If "full" is false, return true if the target saw at 2938 * least the first byte of the message. 2939 */ 2940 static int 2941 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2942 { 2943 int found; 2944 u_int index; 2945 2946 found = FALSE; 2947 index = 0; 2948 2949 while (index < ahc->msgout_len) { 2950 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2951 u_int end_index; 2952 2953 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2954 if (ahc->msgout_buf[index+2] == msgval 2955 && type == AHCMSG_EXT) { 2956 2957 if (full) { 2958 if (ahc->msgout_index > end_index) 2959 found = TRUE; 2960 } else if (ahc->msgout_index > index) 2961 found = TRUE; 2962 } 2963 index = end_index; 2964 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2965 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2966 2967 /* Skip tag type and tag id or residue param*/ 2968 index += 2; 2969 } else { 2970 /* Single byte message */ 2971 if (type == AHCMSG_1B 2972 && ahc->msgout_buf[index] == msgval 2973 && ahc->msgout_index > index) 2974 found = TRUE; 2975 index++; 2976 } 2977 2978 if (found) 2979 break; 2980 } 2981 return (found); 2982 } 2983 2984 /* 2985 * Wait for a complete incoming message, parse it, and respond accordingly. 2986 */ 2987 static int 2988 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2989 { 2990 struct ahc_initiator_tinfo *tinfo; 2991 struct ahc_tmode_tstate *tstate; 2992 int reject; 2993 int done; 2994 int response; 2995 u_int targ_scsirate; 2996 2997 done = MSGLOOP_IN_PROG; 2998 response = FALSE; 2999 reject = FALSE; 3000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3001 devinfo->target, &tstate); 3002 targ_scsirate = tinfo->scsirate; 3003 3004 /* 3005 * Parse as much of the message as is availible, 3006 * rejecting it if we don't support it. When 3007 * the entire message is availible and has been 3008 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3009 * that we have parsed an entire message. 3010 * 3011 * In the case of extended messages, we accept the length 3012 * byte outright and perform more checking once we know the 3013 * extended message type. 3014 */ 3015 switch (ahc->msgin_buf[0]) { 3016 case MSG_DISCONNECT: 3017 case MSG_SAVEDATAPOINTER: 3018 case MSG_CMDCOMPLETE: 3019 case MSG_RESTOREPOINTERS: 3020 case MSG_IGN_WIDE_RESIDUE: 3021 /* 3022 * End our message loop as these are messages 3023 * the sequencer handles on its own. 3024 */ 3025 done = MSGLOOP_TERMINATED; 3026 break; 3027 case MSG_MESSAGE_REJECT: 3028 response = ahc_handle_msg_reject(ahc, devinfo); 3029 /* FALLTHROUGH */ 3030 case MSG_NOOP: 3031 done = MSGLOOP_MSGCOMPLETE; 3032 break; 3033 case MSG_EXTENDED: 3034 { 3035 /* Wait for enough of the message to begin validation */ 3036 if (ahc->msgin_index < 2) 3037 break; 3038 switch (ahc->msgin_buf[2]) { 3039 case MSG_EXT_SDTR: 3040 { 3041 struct ahc_syncrate *syncrate; 3042 u_int period; 3043 u_int ppr_options; 3044 u_int offset; 3045 u_int saved_offset; 3046 3047 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3048 reject = TRUE; 3049 break; 3050 } 3051 3052 /* 3053 * Wait until we have both args before validating 3054 * and acting on this message. 3055 * 3056 * Add one to MSG_EXT_SDTR_LEN to account for 3057 * the extended message preamble. 3058 */ 3059 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3060 break; 3061 3062 period = ahc->msgin_buf[3]; 3063 ppr_options = 0; 3064 saved_offset = offset = ahc->msgin_buf[4]; 3065 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3066 &ppr_options, 3067 devinfo->role); 3068 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3069 targ_scsirate & WIDEXFER, 3070 devinfo->role); 3071 if (bootverbose) { 3072 printf("(%s:%c:%d:%d): Received " 3073 "SDTR period %x, offset %x\n\t" 3074 "Filtered to period %x, offset %x\n", 3075 ahc_name(ahc), devinfo->channel, 3076 devinfo->target, devinfo->lun, 3077 ahc->msgin_buf[3], saved_offset, 3078 period, offset); 3079 } 3080 ahc_set_syncrate(ahc, devinfo, 3081 syncrate, period, 3082 offset, ppr_options, 3083 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3084 /*paused*/TRUE); 3085 3086 /* 3087 * See if we initiated Sync Negotiation 3088 * and didn't have to fall down to async 3089 * transfers. 3090 */ 3091 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3092 /* We started it */ 3093 if (saved_offset != offset) { 3094 /* Went too low - force async */ 3095 reject = TRUE; 3096 } 3097 } else { 3098 /* 3099 * Send our own SDTR in reply 3100 */ 3101 if (bootverbose 3102 && devinfo->role == ROLE_INITIATOR) { 3103 printf("(%s:%c:%d:%d): Target " 3104 "Initiated SDTR\n", 3105 ahc_name(ahc), devinfo->channel, 3106 devinfo->target, devinfo->lun); 3107 } 3108 ahc->msgout_index = 0; 3109 ahc->msgout_len = 0; 3110 ahc_construct_sdtr(ahc, devinfo, 3111 period, offset); 3112 ahc->msgout_index = 0; 3113 response = TRUE; 3114 } 3115 done = MSGLOOP_MSGCOMPLETE; 3116 break; 3117 } 3118 case MSG_EXT_WDTR: 3119 { 3120 u_int bus_width; 3121 u_int saved_width; 3122 u_int sending_reply; 3123 3124 sending_reply = FALSE; 3125 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3126 reject = TRUE; 3127 break; 3128 } 3129 3130 /* 3131 * Wait until we have our arg before validating 3132 * and acting on this message. 3133 * 3134 * Add one to MSG_EXT_WDTR_LEN to account for 3135 * the extended message preamble. 3136 */ 3137 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3138 break; 3139 3140 bus_width = ahc->msgin_buf[3]; 3141 saved_width = bus_width; 3142 ahc_validate_width(ahc, tinfo, &bus_width, 3143 devinfo->role); 3144 if (bootverbose) { 3145 printf("(%s:%c:%d:%d): Received WDTR " 3146 "%x filtered to %x\n", 3147 ahc_name(ahc), devinfo->channel, 3148 devinfo->target, devinfo->lun, 3149 saved_width, bus_width); 3150 } 3151 3152 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3153 /* 3154 * Don't send a WDTR back to the 3155 * target, since we asked first. 3156 * If the width went higher than our 3157 * request, reject it. 3158 */ 3159 if (saved_width > bus_width) { 3160 reject = TRUE; 3161 printf("(%s:%c:%d:%d): requested %dBit " 3162 "transfers. Rejecting...\n", 3163 ahc_name(ahc), devinfo->channel, 3164 devinfo->target, devinfo->lun, 3165 8 * (0x01 << bus_width)); 3166 bus_width = 0; 3167 } 3168 } else { 3169 /* 3170 * Send our own WDTR in reply 3171 */ 3172 if (bootverbose 3173 && devinfo->role == ROLE_INITIATOR) { 3174 printf("(%s:%c:%d:%d): Target " 3175 "Initiated WDTR\n", 3176 ahc_name(ahc), devinfo->channel, 3177 devinfo->target, devinfo->lun); 3178 } 3179 ahc->msgout_index = 0; 3180 ahc->msgout_len = 0; 3181 ahc_construct_wdtr(ahc, devinfo, bus_width); 3182 ahc->msgout_index = 0; 3183 response = TRUE; 3184 sending_reply = TRUE; 3185 } 3186 ahc_set_width(ahc, devinfo, bus_width, 3187 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3188 /*paused*/TRUE); 3189 /* After a wide message, we are async */ 3190 ahc_set_syncrate(ahc, devinfo, 3191 /*syncrate*/NULL, /*period*/0, 3192 /*offset*/0, /*ppr_options*/0, 3193 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3194 if (sending_reply == FALSE && reject == FALSE) { 3195 3196 if (tinfo->goal.offset) { 3197 ahc->msgout_index = 0; 3198 ahc->msgout_len = 0; 3199 ahc_build_transfer_msg(ahc, devinfo); 3200 ahc->msgout_index = 0; 3201 response = TRUE; 3202 } 3203 } 3204 done = MSGLOOP_MSGCOMPLETE; 3205 break; 3206 } 3207 case MSG_EXT_PPR: 3208 { 3209 struct ahc_syncrate *syncrate; 3210 u_int period; 3211 u_int offset; 3212 u_int bus_width; 3213 u_int ppr_options; 3214 u_int saved_width; 3215 u_int saved_offset; 3216 u_int saved_ppr_options; 3217 3218 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3219 reject = TRUE; 3220 break; 3221 } 3222 3223 /* 3224 * Wait until we have all args before validating 3225 * and acting on this message. 3226 * 3227 * Add one to MSG_EXT_PPR_LEN to account for 3228 * the extended message preamble. 3229 */ 3230 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3231 break; 3232 3233 period = ahc->msgin_buf[3]; 3234 offset = ahc->msgin_buf[5]; 3235 bus_width = ahc->msgin_buf[6]; 3236 saved_width = bus_width; 3237 ppr_options = ahc->msgin_buf[7]; 3238 /* 3239 * According to the spec, a DT only 3240 * period factor with no DT option 3241 * set implies async. 3242 */ 3243 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3244 && period == 9) 3245 offset = 0; 3246 saved_ppr_options = ppr_options; 3247 saved_offset = offset; 3248 3249 /* 3250 * Mask out any options we don't support 3251 * on any controller. Transfer options are 3252 * only available if we are negotiating wide. 3253 */ 3254 ppr_options &= MSG_EXT_PPR_DT_REQ; 3255 if (bus_width == 0) 3256 ppr_options = 0; 3257 3258 ahc_validate_width(ahc, tinfo, &bus_width, 3259 devinfo->role); 3260 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3261 &ppr_options, 3262 devinfo->role); 3263 ahc_validate_offset(ahc, tinfo, syncrate, 3264 &offset, bus_width, 3265 devinfo->role); 3266 3267 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3268 /* 3269 * If we are unable to do any of the 3270 * requested options (we went too low), 3271 * then we'll have to reject the message. 3272 */ 3273 if (saved_width > bus_width 3274 || saved_offset != offset 3275 || saved_ppr_options != ppr_options) { 3276 reject = TRUE; 3277 period = 0; 3278 offset = 0; 3279 bus_width = 0; 3280 ppr_options = 0; 3281 syncrate = NULL; 3282 } 3283 } else { 3284 if (devinfo->role != ROLE_TARGET) 3285 printf("(%s:%c:%d:%d): Target " 3286 "Initiated PPR\n", 3287 ahc_name(ahc), devinfo->channel, 3288 devinfo->target, devinfo->lun); 3289 else 3290 printf("(%s:%c:%d:%d): Initiator " 3291 "Initiated PPR\n", 3292 ahc_name(ahc), devinfo->channel, 3293 devinfo->target, devinfo->lun); 3294 ahc->msgout_index = 0; 3295 ahc->msgout_len = 0; 3296 ahc_construct_ppr(ahc, devinfo, period, offset, 3297 bus_width, ppr_options); 3298 ahc->msgout_index = 0; 3299 response = TRUE; 3300 } 3301 if (bootverbose) { 3302 printf("(%s:%c:%d:%d): Received PPR width %x, " 3303 "period %x, offset %x,options %x\n" 3304 "\tFiltered to width %x, period %x, " 3305 "offset %x, options %x\n", 3306 ahc_name(ahc), devinfo->channel, 3307 devinfo->target, devinfo->lun, 3308 saved_width, ahc->msgin_buf[3], 3309 saved_offset, saved_ppr_options, 3310 bus_width, period, offset, ppr_options); 3311 } 3312 ahc_set_width(ahc, devinfo, bus_width, 3313 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3314 /*paused*/TRUE); 3315 ahc_set_syncrate(ahc, devinfo, 3316 syncrate, period, 3317 offset, ppr_options, 3318 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3319 /*paused*/TRUE); 3320 done = MSGLOOP_MSGCOMPLETE; 3321 break; 3322 } 3323 default: 3324 /* Unknown extended message. Reject it. */ 3325 reject = TRUE; 3326 break; 3327 } 3328 break; 3329 } 3330 #ifdef AHC_TARGET_MODE 3331 case MSG_BUS_DEV_RESET: 3332 ahc_handle_devreset(ahc, devinfo, 3333 CAM_BDR_SENT, 3334 "Bus Device Reset Received", 3335 /*verbose_level*/0); 3336 ahc_restart(ahc); 3337 done = MSGLOOP_TERMINATED; 3338 break; 3339 case MSG_ABORT_TAG: 3340 case MSG_ABORT: 3341 case MSG_CLEAR_QUEUE: 3342 { 3343 int tag; 3344 3345 /* Target mode messages */ 3346 if (devinfo->role != ROLE_TARGET) { 3347 reject = TRUE; 3348 break; 3349 } 3350 tag = SCB_LIST_NULL; 3351 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3352 tag = ahc_inb(ahc, INITIATOR_TAG); 3353 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3354 devinfo->lun, tag, ROLE_TARGET, 3355 CAM_REQ_ABORTED); 3356 3357 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3358 if (tstate != NULL) { 3359 struct ahc_tmode_lstate* lstate; 3360 3361 lstate = tstate->enabled_luns[devinfo->lun]; 3362 if (lstate != NULL) { 3363 ahc_queue_lstate_event(ahc, lstate, 3364 devinfo->our_scsiid, 3365 ahc->msgin_buf[0], 3366 /*arg*/tag); 3367 ahc_send_lstate_events(ahc, lstate); 3368 } 3369 } 3370 ahc_restart(ahc); 3371 done = MSGLOOP_TERMINATED; 3372 break; 3373 } 3374 #endif 3375 case MSG_TERM_IO_PROC: 3376 default: 3377 reject = TRUE; 3378 break; 3379 } 3380 3381 if (reject) { 3382 /* 3383 * Setup to reject the message. 3384 */ 3385 ahc->msgout_index = 0; 3386 ahc->msgout_len = 1; 3387 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3388 done = MSGLOOP_MSGCOMPLETE; 3389 response = TRUE; 3390 } 3391 3392 if (done != MSGLOOP_IN_PROG && !response) 3393 /* Clear the outgoing message buffer */ 3394 ahc->msgout_len = 0; 3395 3396 return (done); 3397 } 3398 3399 /* 3400 * Process a message reject message. 3401 */ 3402 static int 3403 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3404 { 3405 /* 3406 * What we care about here is if we had an 3407 * outstanding SDTR or WDTR message for this 3408 * target. If we did, this is a signal that 3409 * the target is refusing negotiation. 3410 */ 3411 struct scb *scb; 3412 struct ahc_initiator_tinfo *tinfo; 3413 struct ahc_tmode_tstate *tstate; 3414 u_int scb_index; 3415 u_int last_msg; 3416 int response = 0; 3417 3418 scb_index = ahc_inb(ahc, SCB_TAG); 3419 scb = ahc_lookup_scb(ahc, scb_index); 3420 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3421 devinfo->our_scsiid, 3422 devinfo->target, &tstate); 3423 /* Might be necessary */ 3424 last_msg = ahc_inb(ahc, LAST_MSG); 3425 3426 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3427 /* 3428 * Target does not support the PPR message. 3429 * Attempt to negotiate SPI-2 style. 3430 */ 3431 if (bootverbose) { 3432 printf("(%s:%c:%d:%d): PPR Rejected. " 3433 "Trying WDTR/SDTR\n", 3434 ahc_name(ahc), devinfo->channel, 3435 devinfo->target, devinfo->lun); 3436 } 3437 tinfo->goal.ppr_options = 0; 3438 tinfo->curr.transport_version = 2; 3439 tinfo->goal.transport_version = 2; 3440 ahc->msgout_index = 0; 3441 ahc->msgout_len = 0; 3442 ahc_build_transfer_msg(ahc, devinfo); 3443 ahc->msgout_index = 0; 3444 response = 1; 3445 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3446 3447 /* note 8bit xfers */ 3448 if (bootverbose) 3449 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3450 "8bit transfers\n", ahc_name(ahc), 3451 devinfo->channel, devinfo->target, devinfo->lun); 3452 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3453 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3454 /*paused*/TRUE); 3455 /* 3456 * No need to clear the sync rate. If the target 3457 * did not accept the command, our syncrate is 3458 * unaffected. If the target started the negotiation, 3459 * but rejected our response, we already cleared the 3460 * sync rate before sending our WDTR. 3461 */ 3462 if (tinfo->goal.offset != tinfo->curr.offset) { 3463 3464 /* Start the sync negotiation */ 3465 ahc->msgout_index = 0; 3466 ahc->msgout_len = 0; 3467 ahc_build_transfer_msg(ahc, devinfo); 3468 ahc->msgout_index = 0; 3469 response = 1; 3470 } 3471 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3472 /* note asynch xfers and clear flag */ 3473 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3474 /*offset*/0, /*ppr_options*/0, 3475 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3476 /*paused*/TRUE); 3477 if (bootverbose) 3478 printf("(%s:%c:%d:%d): refuses synchronous negotiation." 3479 " Using asynchronous transfers\n", 3480 ahc_name(ahc), devinfo->channel, 3481 devinfo->target, devinfo->lun); 3482 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3483 int tag_type; 3484 int mask; 3485 3486 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3487 3488 if (tag_type == MSG_SIMPLE_TASK) { 3489 if (bootverbose) 3490 printf("(%s:%c:%d:%d): refuses tagged commands." 3491 " Performing non-tagged I/O\n", 3492 ahc_name(ahc), devinfo->channel, 3493 devinfo->target, devinfo->lun); 3494 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3495 mask = ~0x23; 3496 } else { 3497 if (bootverbose) 3498 printf("(%s:%c:%d:%d): refuses %s tagged " 3499 "commands. Performing simple queue " 3500 "tagged I/O only\n", 3501 ahc_name(ahc), devinfo->channel, 3502 devinfo->target, devinfo->lun, 3503 tag_type == MSG_ORDERED_TASK 3504 ? "ordered" : "head of queue"); 3505 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3506 mask = ~0x03; 3507 } 3508 3509 /* 3510 * Resend the identify for this CCB as the target 3511 * may believe that the selection is invalid otherwise. 3512 */ 3513 ahc_outb(ahc, SCB_CONTROL, 3514 ahc_inb(ahc, SCB_CONTROL) & mask); 3515 scb->hscb->control &= mask; 3516 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3517 /*type*/MSG_SIMPLE_TASK); 3518 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3519 ahc_assert_atn(ahc); 3520 3521 /* 3522 * This transaction is now at the head of 3523 * the untagged queue for this target. 3524 */ 3525 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3526 struct scb_tailq *untagged_q; 3527 3528 untagged_q = 3529 &(ahc->untagged_queues[devinfo->target_offset]); 3530 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3531 scb->flags |= SCB_UNTAGGEDQ; 3532 } 3533 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3534 scb->hscb->tag); 3535 3536 /* 3537 * Requeue all tagged commands for this target 3538 * currently in our posession so they can be 3539 * converted to untagged commands. 3540 */ 3541 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3542 SCB_GET_CHANNEL(ahc, scb), 3543 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3544 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3545 SEARCH_COMPLETE); 3546 } else { 3547 /* 3548 * Otherwise, we ignore it. 3549 */ 3550 if (bootverbose) 3551 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3552 ahc_name(ahc), devinfo->channel, devinfo->target, 3553 last_msg); 3554 } 3555 return (response); 3556 } 3557 3558 /* 3559 * Process an ingnore wide residue message. 3560 */ 3561 static void 3562 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3563 { 3564 u_int scb_index; 3565 struct scb *scb; 3566 3567 scb_index = ahc_inb(ahc, SCB_TAG); 3568 scb = ahc_lookup_scb(ahc, scb_index); 3569 /* 3570 * XXX Actually check data direction in the sequencer? 3571 * Perhaps add datadir to some spare bits in the hscb? 3572 */ 3573 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3574 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3575 /* 3576 * Ignore the message if we haven't 3577 * seen an appropriate data phase yet. 3578 */ 3579 } else { 3580 /* 3581 * If the residual occurred on the last 3582 * transfer and the transfer request was 3583 * expected to end on an odd count, do 3584 * nothing. Otherwise, subtract a byte 3585 * and update the residual count accordingly. 3586 */ 3587 uint32_t sgptr; 3588 3589 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3590 if ((sgptr & SG_LIST_NULL) != 0 3591 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3592 /* 3593 * If the residual occurred on the last 3594 * transfer and the transfer request was 3595 * expected to end on an odd count, do 3596 * nothing. 3597 */ 3598 } else { 3599 struct ahc_dma_seg *sg; 3600 uint32_t data_cnt; 3601 uint32_t data_addr; 3602 uint32_t sglen; 3603 3604 /* Pull in the rest of the sgptr */ 3605 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3606 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3607 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3608 sgptr &= SG_PTR_MASK; 3609 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3610 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3611 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3612 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3613 3614 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3615 | (ahc_inb(ahc, SHADDR + 2) << 16) 3616 | (ahc_inb(ahc, SHADDR + 1) << 8) 3617 | (ahc_inb(ahc, SHADDR)); 3618 3619 data_cnt += 1; 3620 data_addr -= 1; 3621 3622 sg = ahc_sg_bus_to_virt(scb, sgptr); 3623 /* 3624 * The residual sg ptr points to the next S/G 3625 * to load so we must go back one. 3626 */ 3627 sg--; 3628 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3629 if (sg != scb->sg_list 3630 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3631 3632 sg--; 3633 sglen = ahc_le32toh(sg->len); 3634 /* 3635 * Preserve High Address and SG_LIST bits 3636 * while setting the count to 1. 3637 */ 3638 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3639 data_addr = ahc_le32toh(sg->addr) 3640 + (sglen & AHC_SG_LEN_MASK) - 1; 3641 3642 /* 3643 * Increment sg so it points to the 3644 * "next" sg. 3645 */ 3646 sg++; 3647 sgptr = ahc_sg_virt_to_bus(scb, sg); 3648 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3649 sgptr >> 24); 3650 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3651 sgptr >> 16); 3652 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3653 sgptr >> 8); 3654 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3655 } 3656 3657 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3658 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3659 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3660 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3661 } 3662 } 3663 } 3664 3665 3666 /* 3667 * Reinitialize the data pointers for the active transfer 3668 * based on its current residual. 3669 */ 3670 static void 3671 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3672 { 3673 struct scb *scb; 3674 struct ahc_dma_seg *sg; 3675 u_int scb_index; 3676 uint32_t sgptr; 3677 uint32_t resid; 3678 uint32_t dataptr; 3679 3680 scb_index = ahc_inb(ahc, SCB_TAG); 3681 scb = ahc_lookup_scb(ahc, scb_index); 3682 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3683 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3684 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3685 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3686 3687 sgptr &= SG_PTR_MASK; 3688 sg = ahc_sg_bus_to_virt(scb, sgptr); 3689 3690 /* The residual sg_ptr always points to the next sg */ 3691 sg--; 3692 3693 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3694 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3695 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3696 3697 dataptr = ahc_le32toh(sg->addr) 3698 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3699 - resid; 3700 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3701 u_int dscommand1; 3702 3703 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3704 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3705 ahc_outb(ahc, HADDR, 3706 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3707 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3708 } 3709 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3710 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3711 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3712 ahc_outb(ahc, HADDR, dataptr); 3713 ahc_outb(ahc, HCNT + 2, resid >> 16); 3714 ahc_outb(ahc, HCNT + 1, resid >> 8); 3715 ahc_outb(ahc, HCNT, resid); 3716 if ((ahc->features & AHC_ULTRA2) == 0) { 3717 ahc_outb(ahc, STCNT + 2, resid >> 16); 3718 ahc_outb(ahc, STCNT + 1, resid >> 8); 3719 ahc_outb(ahc, STCNT, resid); 3720 } 3721 } 3722 3723 /* 3724 * Handle the effects of issuing a bus device reset message. 3725 */ 3726 static void 3727 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3728 cam_status status, char *message, int verbose_level) 3729 { 3730 #ifdef AHC_TARGET_MODE 3731 struct ahc_tmode_tstate* tstate; 3732 u_int lun; 3733 #endif 3734 int found; 3735 3736 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3737 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3738 status); 3739 3740 #ifdef AHC_TARGET_MODE 3741 /* 3742 * Send an immediate notify ccb to all target mord peripheral 3743 * drivers affected by this action. 3744 */ 3745 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3746 if (tstate != NULL) { 3747 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3748 struct ahc_tmode_lstate* lstate; 3749 3750 lstate = tstate->enabled_luns[lun]; 3751 if (lstate == NULL) 3752 continue; 3753 3754 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3755 MSG_BUS_DEV_RESET, /*arg*/0); 3756 ahc_send_lstate_events(ahc, lstate); 3757 } 3758 } 3759 #endif 3760 3761 /* 3762 * Go back to async/narrow transfers and renegotiate. 3763 */ 3764 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3765 AHC_TRANS_CUR, /*paused*/TRUE); 3766 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3767 /*period*/0, /*offset*/0, /*ppr_options*/0, 3768 AHC_TRANS_CUR, /*paused*/TRUE); 3769 3770 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3771 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3772 3773 if (message != NULL 3774 && (verbose_level <= bootverbose)) 3775 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3776 message, devinfo->channel, devinfo->target, found); 3777 } 3778 3779 #ifdef AHC_TARGET_MODE 3780 static void 3781 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3782 struct scb *scb) 3783 { 3784 3785 /* 3786 * To facilitate adding multiple messages together, 3787 * each routine should increment the index and len 3788 * variables instead of setting them explicitly. 3789 */ 3790 ahc->msgout_index = 0; 3791 ahc->msgout_len = 0; 3792 3793 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3794 ahc_build_transfer_msg(ahc, devinfo); 3795 else 3796 panic("ahc_intr: AWAITING target message with no message"); 3797 3798 ahc->msgout_index = 0; 3799 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3800 } 3801 #endif 3802 3803 int 3804 ahc_softc_init(struct ahc_softc *ahc) 3805 { 3806 3807 /* The IRQMS bit is only valid on VL and EISA chips */ 3808 if ((ahc->chip & AHC_PCI) == 0) 3809 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3810 else 3811 ahc->unpause = 0; 3812 ahc->pause = ahc->unpause | PAUSE; 3813 /* XXX The shared scb data stuff should be deprecated */ 3814 if (ahc->scb_data == NULL) { 3815 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3816 M_DEVBUF, M_NOWAIT); 3817 if (ahc->scb_data == NULL) 3818 return (ENOMEM); 3819 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3820 } 3821 3822 return (0); 3823 } 3824 3825 void 3826 ahc_softc_insert(struct ahc_softc *ahc) 3827 { 3828 struct ahc_softc *list_ahc; 3829 3830 #if AHC_PCI_CONFIG > 0 3831 /* 3832 * Second Function PCI devices need to inherit some 3833 * settings from function 0. 3834 */ 3835 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3836 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3837 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3838 ahc_dev_softc_t list_pci; 3839 ahc_dev_softc_t pci; 3840 3841 list_pci = list_ahc->dev_softc; 3842 pci = ahc->dev_softc; 3843 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3844 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3845 struct ahc_softc *master; 3846 struct ahc_softc *slave; 3847 3848 if (ahc_get_pci_function(list_pci) == 0) { 3849 master = list_ahc; 3850 slave = ahc; 3851 } else { 3852 master = ahc; 3853 slave = list_ahc; 3854 } 3855 slave->flags &= ~AHC_BIOS_ENABLED; 3856 slave->flags |= 3857 master->flags & AHC_BIOS_ENABLED; 3858 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3859 slave->flags |= 3860 master->flags & AHC_PRIMARY_CHANNEL; 3861 break; 3862 } 3863 } 3864 } 3865 #endif 3866 3867 /* 3868 * Insertion sort into our list of softcs. 3869 */ 3870 list_ahc = TAILQ_FIRST(&ahc_tailq); 3871 while (list_ahc != NULL 3872 && ahc_softc_comp(list_ahc, ahc) <= 0) 3873 list_ahc = TAILQ_NEXT(list_ahc, links); 3874 if (list_ahc != NULL) 3875 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3876 else 3877 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3878 ahc->init_level++; 3879 } 3880 3881 /* 3882 * Verify that the passed in softc pointer is for a 3883 * controller that is still configured. 3884 */ 3885 struct ahc_softc * 3886 ahc_find_softc(struct ahc_softc *ahc) 3887 { 3888 struct ahc_softc *list_ahc; 3889 3890 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3891 if (list_ahc == ahc) 3892 return (ahc); 3893 } 3894 return (NULL); 3895 } 3896 3897 void 3898 ahc_set_unit(struct ahc_softc *ahc, int unit) 3899 { 3900 ahc->unit = unit; 3901 } 3902 3903 void 3904 ahc_set_name(struct ahc_softc *ahc, char *name) 3905 { 3906 if (ahc->name != NULL) 3907 free(ahc->name, M_DEVBUF); 3908 ahc->name = name; 3909 } 3910 3911 void 3912 ahc_free(struct ahc_softc *ahc) 3913 { 3914 int i; 3915 3916 ahc_fini_scbdata(ahc); 3917 switch (ahc->init_level) { 3918 default: 3919 case 2: 3920 ahc_shutdown(ahc); 3921 /* TAILQ_REMOVE(&ahc_tailq, ahc, links); XXX */ 3922 /* FALLTHROUGH */ 3923 case 1: 3924 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3925 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3926 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3927 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3928 break; 3929 case 0: 3930 break; 3931 } 3932 3933 ahc_platform_free(ahc); 3934 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3935 struct ahc_tmode_tstate *tstate; 3936 3937 tstate = ahc->enabled_targets[i]; 3938 if (tstate != NULL) { 3939 #if AHC_TARGET_MODE 3940 int j; 3941 3942 for (j = 0; j < AHC_NUM_LUNS; j++) { 3943 struct ahc_tmode_lstate *lstate; 3944 3945 lstate = tstate->enabled_luns[j]; 3946 if (lstate != NULL) { 3947 /*xpt_free_path(lstate->path);*/ 3948 free(lstate, M_DEVBUF); 3949 } 3950 } 3951 #endif 3952 free(tstate, M_DEVBUF); 3953 } 3954 } 3955 #if AHC_TARGET_MODE 3956 if (ahc->black_hole != NULL) { 3957 /*xpt_free_path(ahc->black_hole->path);*/ 3958 free(ahc->black_hole, M_DEVBUF); 3959 } 3960 #endif 3961 #ifndef __NetBSD__ 3962 if (ahc->name != NULL) 3963 free(ahc->name, M_DEVBUF); 3964 #endif 3965 if (ahc->seep_config != NULL) 3966 free(ahc->seep_config, M_DEVBUF); 3967 #ifndef __FreeBSD__ 3968 free(ahc, M_DEVBUF); 3969 #endif 3970 return; 3971 } 3972 3973 void 3974 ahc_shutdown(void *arg) 3975 { 3976 struct ahc_softc *ahc; 3977 int i; 3978 3979 ahc = (struct ahc_softc *)arg; 3980 3981 /* This will reset most registers to 0, but not all */ 3982 ahc_reset(ahc); 3983 ahc_outb(ahc, SCSISEQ, 0); 3984 ahc_outb(ahc, SXFRCTL0, 0); 3985 ahc_outb(ahc, DSPCISTATUS, 0); 3986 3987 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3988 ahc_outb(ahc, i, 0); 3989 } 3990 3991 /* 3992 * Reset the controller and record some information about it 3993 * that is only available just after a reset. 3994 */ 3995 int 3996 ahc_reset(struct ahc_softc *ahc) 3997 { 3998 u_int sblkctl; 3999 u_int sxfrctl1_a, sxfrctl1_b; 4000 int wait; 4001 4002 /* 4003 * Preserve the value of the SXFRCTL1 register for all channels. 4004 * It contains settings that affect termination and we don't want 4005 * to disturb the integrity of the bus. 4006 */ 4007 ahc_pause(ahc); 4008 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4009 /* 4010 * The chip has not been initialized since 4011 * PCI/EISA/VLB bus reset. Don't trust 4012 * "left over BIOS data". 4013 */ 4014 ahc->flags |= AHC_NO_BIOS_INIT; 4015 } 4016 sxfrctl1_b = 0; 4017 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4018 u_int sblkctl; 4019 4020 /* 4021 * Save channel B's settings in case this chip 4022 * is setup for TWIN channel operation. 4023 */ 4024 sblkctl = ahc_inb(ahc, SBLKCTL); 4025 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4026 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4027 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4028 } 4029 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4030 4031 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4032 4033 /* 4034 * Ensure that the reset has finished. We delay 1000us 4035 * prior to reading the register to make sure the chip 4036 * has sufficiently completed its reset to handle register 4037 * accesses. 4038 */ 4039 wait = 1000; 4040 do { 4041 ahc_delay(1000); 4042 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4043 4044 if (wait == 0) { 4045 printf("%s: WARNING - Failed chip reset! " 4046 "Trying to initialize anyway.\n", ahc_name(ahc)); 4047 } 4048 ahc_outb(ahc, HCNTRL, ahc->pause); 4049 4050 /* Determine channel configuration */ 4051 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4052 /* No Twin Channel PCI cards */ 4053 if ((ahc->chip & AHC_PCI) != 0) 4054 sblkctl &= ~SELBUSB; 4055 switch (sblkctl) { 4056 case 0: 4057 /* Single Narrow Channel */ 4058 break; 4059 case 2: 4060 /* Wide Channel */ 4061 ahc->features |= AHC_WIDE; 4062 break; 4063 case 8: 4064 /* Twin Channel */ 4065 ahc->features |= AHC_TWIN; 4066 break; 4067 default: 4068 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4069 return(-1); 4070 } 4071 4072 /* 4073 * Reload sxfrctl1. 4074 * 4075 * We must always initialize STPWEN to 1 before we 4076 * restore the saved values. STPWEN is initialized 4077 * to a tri-state condition which can only be cleared 4078 * by turning it on. 4079 */ 4080 if ((ahc->features & AHC_TWIN) != 0) { 4081 u_int sblkctl; 4082 4083 sblkctl = ahc_inb(ahc, SBLKCTL); 4084 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4085 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4086 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4087 } 4088 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4089 4090 #ifdef AHC_DUMP_SEQ 4091 if (ahc->init_level == 0) 4092 ahc_dumpseq(ahc); 4093 #endif 4094 4095 return (0); 4096 } 4097 4098 /* 4099 * Determine the number of SCBs available on the controller 4100 */ 4101 int 4102 ahc_probe_scbs(struct ahc_softc *ahc) { 4103 int i; 4104 4105 for (i = 0; i < AHC_SCB_MAX; i++) { 4106 4107 ahc_outb(ahc, SCBPTR, i); 4108 ahc_outb(ahc, SCB_BASE, i); 4109 if (ahc_inb(ahc, SCB_BASE) != i) 4110 break; 4111 ahc_outb(ahc, SCBPTR, 0); 4112 if (ahc_inb(ahc, SCB_BASE) != 0) 4113 break; 4114 } 4115 return (i); 4116 } 4117 4118 #if 0 4119 static void 4120 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4121 { 4122 bus_addr_t *baddr; 4123 4124 baddr = (bus_addr_t *)arg; 4125 *baddr = segs->ds_addr; 4126 } 4127 #endif 4128 4129 static void 4130 ahc_build_free_scb_list(struct ahc_softc *ahc) 4131 { 4132 int scbsize; 4133 int i; 4134 4135 scbsize = 32; 4136 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4137 scbsize = 64; 4138 4139 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4140 int j; 4141 4142 ahc_outb(ahc, SCBPTR, i); 4143 4144 /* 4145 * Touch all SCB bytes to avoid parity errors 4146 * should one of our debugging routines read 4147 * an otherwise uninitiatlized byte. 4148 */ 4149 for (j = 0; j < scbsize; j++) 4150 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4151 4152 /* Clear the control byte. */ 4153 ahc_outb(ahc, SCB_CONTROL, 0); 4154 4155 /* Set the next pointer */ 4156 if ((ahc->flags & AHC_PAGESCBS) != 0) 4157 ahc_outb(ahc, SCB_NEXT, i+1); 4158 else 4159 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4160 4161 /* Make the tag number, SCSIID, and lun invalid */ 4162 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4163 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4164 ahc_outb(ahc, SCB_LUN, 0xFF); 4165 } 4166 4167 /* Make sure that the last SCB terminates the free list */ 4168 ahc_outb(ahc, SCBPTR, i-1); 4169 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4170 } 4171 4172 static int 4173 ahc_init_scbdata(struct ahc_softc *ahc) 4174 { 4175 struct scb_data *scb_data; 4176 4177 scb_data = ahc->scb_data; 4178 SLIST_INIT(&scb_data->free_scbs); 4179 SLIST_INIT(&scb_data->sg_maps); 4180 4181 /* Allocate SCB resources */ 4182 scb_data->scbarray = 4183 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4184 M_DEVBUF, M_NOWAIT); 4185 if (scb_data->scbarray == NULL) 4186 return (ENOMEM); 4187 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4188 4189 /* Determine the number of hardware SCBs and initialize them */ 4190 4191 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4192 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4193 /* SCB 0 heads the free list */ 4194 ahc_outb(ahc, FREE_SCBH, 0); 4195 } else { 4196 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4197 } 4198 4199 if (ahc->scb_data->maxhscbs == 0) { 4200 printf("%s: No SCB space found\n", ahc_name(ahc)); 4201 return (ENXIO); 4202 } 4203 4204 ahc_build_free_scb_list(ahc); 4205 4206 /* 4207 * Create our DMA tags. These tags define the kinds of device 4208 * accessible memory allocations and memory mappings we will 4209 * need to perform during normal operation. 4210 * 4211 * Unless we need to further restrict the allocation, we rely 4212 * on the restrictions of the parent dmat, hence the common 4213 * use of MAXADDR and MAXSIZE. 4214 */ 4215 4216 if (ahc_createdmamem(ahc->parent_dmat, 4217 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4218 &scb_data->hscb_dmamap, 4219 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4220 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4221 "hardware SCB structures") < 0) 4222 goto error_exit; 4223 4224 scb_data->init_level++; 4225 4226 if (ahc_createdmamem(ahc->parent_dmat, 4227 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 4228 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4229 &scb_data->sense_busaddr, &scb_data->sense_seg, 4230 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4231 goto error_exit; 4232 4233 scb_data->init_level++; 4234 4235 /* Perform initial CCB allocation */ 4236 memset(scb_data->hscbs, 0, 4237 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4238 ahc_alloc_scbs(ahc); 4239 scb_data->init_level++; 4240 4241 if (scb_data->numscbs == 0) { 4242 printf("%s: ahc_init_scbdata - " 4243 "Unable to allocate initial scbs\n", 4244 ahc_name(ahc)); 4245 goto error_exit; 4246 } 4247 4248 /* 4249 * Tell the sequencer which SCB will be the next one it receives. 4250 */ 4251 ahc->next_queued_scb = ahc_get_scb(ahc); 4252 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4253 4254 /* 4255 * Note that we were successfull 4256 */ 4257 return (0); 4258 4259 error_exit: 4260 4261 return (ENOMEM); 4262 } 4263 4264 static void 4265 ahc_fini_scbdata(struct ahc_softc *ahc) 4266 { 4267 struct scb_data *scb_data; 4268 4269 scb_data = ahc->scb_data; 4270 if (scb_data == NULL) 4271 return; 4272 4273 switch (scb_data->init_level) { 4274 default: 4275 case 5: 4276 { 4277 struct sg_map_node *sg_map; 4278 4279 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4280 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4281 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4282 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4283 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4284 free(sg_map, M_DEVBUF); 4285 } 4286 } 4287 /*FALLTHROUGH*/ 4288 case 4: 4289 ahc_freedmamem(ahc->parent_dmat, 4290 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 4291 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4292 &scb_data->sense_seg, scb_data->sense_nseg); 4293 /*FALLTHROUGH*/ 4294 case 3: 4295 ahc_freedmamem(ahc->parent_dmat, 4296 AHC_SCB_MAX * sizeof(struct hardware_scb), 4297 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4298 &scb_data->hscb_seg, scb_data->hscb_nseg); 4299 /*FALLTHROUGH*/ 4300 case 2: 4301 case 1: 4302 case 0: 4303 break; 4304 } 4305 if (scb_data->scbarray != NULL) 4306 free(scb_data->scbarray, M_DEVBUF); 4307 } 4308 4309 void 4310 ahc_alloc_scbs(struct ahc_softc *ahc) 4311 { 4312 struct scb_data *scb_data; 4313 struct scb *next_scb; 4314 struct sg_map_node *sg_map; 4315 bus_addr_t physaddr; 4316 struct ahc_dma_seg *segs; 4317 int newcount; 4318 int i; 4319 4320 scb_data = ahc->scb_data; 4321 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4322 /* Can't allocate any more */ 4323 return; 4324 4325 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4326 4327 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4328 4329 if (sg_map == NULL) 4330 return; 4331 4332 /* Allocate S/G space for the next batch of SCBS */ 4333 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4334 &sg_map->sg_dmamap, 4335 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4336 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4337 "SG space") < 0) { 4338 free(sg_map, M_DEVBUF); 4339 return; 4340 } 4341 4342 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4343 4344 segs = sg_map->sg_vaddr; 4345 physaddr = sg_map->sg_physaddr; 4346 4347 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4348 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4349 for (i = 0; i < newcount; i++) { 4350 struct scb_platform_data *pdata; 4351 int error; 4352 4353 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4354 M_DEVBUF, M_NOWAIT); 4355 if (pdata == NULL) 4356 break; 4357 next_scb->platform_data = pdata; 4358 next_scb->sg_map = sg_map; 4359 next_scb->sg_list = segs; 4360 /* 4361 * The sequencer always starts with the second entry. 4362 * The first entry is embedded in the scb. 4363 */ 4364 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4365 next_scb->ahc_softc = ahc; 4366 next_scb->flags = SCB_FREE; 4367 4368 error = bus_dmamap_create(ahc->parent_dmat, 4369 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0, 4370 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 4371 &next_scb->dmamap); 4372 if (error != 0) 4373 break; 4374 4375 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4376 next_scb->hscb->tag = ahc->scb_data->numscbs; 4377 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4378 next_scb, links.sle); 4379 segs += AHC_NSEG; 4380 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4381 next_scb++; 4382 ahc->scb_data->numscbs++; 4383 } 4384 } 4385 4386 void 4387 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4388 { 4389 int len; 4390 4391 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4392 buf += len; 4393 if ((ahc->features & AHC_TWIN) != 0) 4394 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4395 "B SCSI Id=%d, primary %c, ", 4396 ahc->our_id, ahc->our_id_b, 4397 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4398 else { 4399 const char *speed; 4400 const char *type; 4401 4402 speed = ""; 4403 if ((ahc->features & AHC_ULTRA) != 0) { 4404 speed = "Ultra "; 4405 } else if ((ahc->features & AHC_DT) != 0) { 4406 speed = "Ultra160 "; 4407 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4408 speed = "Ultra2 "; 4409 } 4410 if ((ahc->features & AHC_WIDE) != 0) { 4411 type = "Wide"; 4412 } else { 4413 type = "Single"; 4414 } 4415 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4416 speed, type, ahc->channel, ahc->our_id); 4417 } 4418 buf += len; 4419 4420 if ((ahc->flags & AHC_PAGESCBS) != 0) 4421 sprintf(buf, "%d/%d SCBs", 4422 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4423 else 4424 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4425 } 4426 4427 /* 4428 * Start the board, ready for normal operation 4429 */ 4430 int 4431 ahc_init(struct ahc_softc *ahc) 4432 { 4433 int max_targ; 4434 int i; 4435 int term; 4436 u_int scsi_conf; 4437 u_int scsiseq_template; 4438 u_int ultraenb; 4439 u_int discenable; 4440 u_int tagenable; 4441 size_t driver_data_size; 4442 uint32_t physaddr; 4443 4444 #ifdef AHC_DEBUG 4445 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4446 ahc->flags |= AHC_SEQUENCER_DEBUG; 4447 #endif 4448 4449 #ifdef AHC_PRINT_SRAM 4450 printf("Scratch Ram:"); 4451 for (i = 0x20; i < 0x5f; i++) { 4452 if (((i % 8) == 0) && (i != 0)) { 4453 printf ("\n "); 4454 } 4455 printf (" 0x%x", ahc_inb(ahc, i)); 4456 } 4457 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4458 for (i = 0x70; i < 0x7f; i++) { 4459 if (((i % 8) == 0) && (i != 0)) { 4460 printf ("\n "); 4461 } 4462 printf (" 0x%x", ahc_inb(ahc, i)); 4463 } 4464 } 4465 printf ("\n"); 4466 /* 4467 * Reading uninitialized scratch ram may 4468 * generate parity errors. 4469 */ 4470 ahc_outb(ahc, CLRINT, CLRPARERR); 4471 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4472 #endif 4473 max_targ = 15; 4474 4475 /* 4476 * Assume we have a board at this stage and it has been reset. 4477 */ 4478 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4479 ahc->our_id = ahc->our_id_b = 7; 4480 4481 /* 4482 * Default to allowing initiator operations. 4483 */ 4484 ahc->flags |= AHC_INITIATORROLE; 4485 4486 /* 4487 * Only allow target mode features if this unit has them enabled. 4488 */ 4489 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4490 ahc->features &= ~AHC_TARGETMODE; 4491 4492 /* 4493 * DMA tag for our command fifos and other data in system memory 4494 * the card's sequencer must be able to access. For initiator 4495 * roles, we need to allocate space for the qinfifo and qoutfifo. 4496 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4497 * When providing for the target mode role, we must additionally 4498 * provide space for the incoming target command fifo and an extra 4499 * byte to deal with a DMA bug in some chip versions. 4500 */ 4501 driver_data_size = 2 * 256 * sizeof(uint8_t); 4502 if ((ahc->features & AHC_TARGETMODE) != 0) 4503 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4504 + /*DMA WideOdd Bug Buffer*/1; 4505 4506 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4507 ahc->sc_dmaflags, 4508 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4509 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4510 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4511 return (ENOMEM); 4512 4513 ahc->init_level++; 4514 4515 if ((ahc->features & AHC_TARGETMODE) != 0) { 4516 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4517 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4518 ahc->dma_bug_buf = ahc->shared_data_busaddr 4519 + driver_data_size - 1; 4520 /* All target command blocks start out invalid. */ 4521 for (i = 0; i < AHC_TMODE_CMDS; i++) 4522 ahc->targetcmds[i].cmd_valid = 0; 4523 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4524 ahc->tqinfifonext = 1; 4525 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4526 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4527 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4528 } 4529 ahc->qinfifo = &ahc->qoutfifo[256]; 4530 4531 ahc->init_level++; 4532 4533 /* Allocate SCB data now that buffer_dmat is initialized */ 4534 if (ahc->scb_data->maxhscbs == 0) 4535 if (ahc_init_scbdata(ahc) != 0) 4536 return (ENOMEM); 4537 4538 if (bootverbose) 4539 printf("%s: found %d SCBs\n", ahc_name(ahc), 4540 ahc->scb_data->maxhscbs); 4541 4542 /* 4543 * Allocate a tstate to house information for our 4544 * initiator presence on the bus as well as the user 4545 * data for any target mode initiator. 4546 */ 4547 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4548 printf("%s: unable to allocate ahc_tmode_tstate. " 4549 "Failing attach\n", ahc_name(ahc)); 4550 return (ENOMEM); 4551 } 4552 4553 if ((ahc->features & AHC_TWIN) != 0) { 4554 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4555 printf("%s: unable to allocate ahc_tmode_tstate. " 4556 "Failing attach\n", ahc_name(ahc)); 4557 return (ENOMEM); 4558 } 4559 } 4560 4561 ahc_outb(ahc, SEQ_FLAGS, 0); 4562 ahc_outb(ahc, SEQ_FLAGS2, 0); 4563 4564 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4565 ahc->flags |= AHC_PAGESCBS; 4566 } else { 4567 ahc->flags &= ~AHC_PAGESCBS; 4568 } 4569 4570 #ifdef AHC_DEBUG 4571 if (ahc_debug & AHC_SHOW_MISC) { 4572 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 4573 "ahc_dma %lu bytes\n", 4574 ahc_name(ahc), 4575 (u_long)sizeof(struct hardware_scb), 4576 (u_long)sizeof(struct scb), 4577 (u_long)sizeof(struct ahc_dma_seg)); 4578 } 4579 #endif /* AHC_DEBUG */ 4580 4581 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4582 if (ahc->features & AHC_TWIN) { 4583 4584 /* 4585 * The device is gated to channel B after a chip reset, 4586 * so set those values first 4587 */ 4588 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4589 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4590 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4591 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4592 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4593 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4594 if ((ahc->features & AHC_ULTRA2) != 0) 4595 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4596 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4597 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4598 4599 if ((scsi_conf & RESET_SCSI) != 0 4600 && (ahc->flags & AHC_INITIATORROLE) != 0) 4601 ahc->flags |= AHC_RESET_BUS_B; 4602 4603 /* Select Channel A */ 4604 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4605 } 4606 4607 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4608 if ((ahc->features & AHC_ULTRA2) != 0) 4609 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4610 else 4611 ahc_outb(ahc, SCSIID, ahc->our_id); 4612 scsi_conf = ahc_inb(ahc, SCSICONF); 4613 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4614 |term|ahc->seltime 4615 |ENSTIMER|ACTNEGEN); 4616 if ((ahc->features & AHC_ULTRA2) != 0) 4617 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4618 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4619 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4620 4621 if ((scsi_conf & RESET_SCSI) != 0 4622 && (ahc->flags & AHC_INITIATORROLE) != 0) 4623 ahc->flags |= AHC_RESET_BUS_A; 4624 4625 /* 4626 * Look at the information that board initialization or 4627 * the board bios has left us. 4628 */ 4629 ultraenb = 0; 4630 tagenable = ALL_TARGETS_MASK; 4631 4632 /* Grab the disconnection disable table and invert it for our needs */ 4633 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4634 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4635 "device parameters\n", ahc_name(ahc)); 4636 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4637 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4638 discenable = ALL_TARGETS_MASK; 4639 if ((ahc->features & AHC_ULTRA) != 0) 4640 ultraenb = ALL_TARGETS_MASK; 4641 } else { 4642 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4643 | ahc_inb(ahc, DISC_DSB)); 4644 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4645 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4646 | ahc_inb(ahc, ULTRA_ENB); 4647 } 4648 4649 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4650 max_targ = 7; 4651 4652 for (i = 0; i <= max_targ; i++) { 4653 struct ahc_initiator_tinfo *tinfo; 4654 struct ahc_tmode_tstate *tstate; 4655 u_int our_id; 4656 u_int target_id; 4657 char channel; 4658 4659 channel = 'A'; 4660 our_id = ahc->our_id; 4661 target_id = i; 4662 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4663 channel = 'B'; 4664 our_id = ahc->our_id_b; 4665 target_id = i % 8; 4666 } 4667 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4668 target_id, &tstate); 4669 /* Default to async narrow across the board */ 4670 memset(tinfo, 0, sizeof(*tinfo)); 4671 if (ahc->flags & AHC_USEDEFAULTS) { 4672 if ((ahc->features & AHC_WIDE) != 0) 4673 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4674 4675 /* 4676 * These will be truncated when we determine the 4677 * connection type we have with the target. 4678 */ 4679 tinfo->user.period = ahc_syncrates->period; 4680 tinfo->user.offset = ~0; 4681 } else { 4682 u_int scsirate; 4683 uint16_t mask; 4684 4685 /* Take the settings leftover in scratch RAM. */ 4686 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4687 mask = (0x01 << i); 4688 if ((ahc->features & AHC_ULTRA2) != 0) { 4689 u_int offset; 4690 u_int maxsync; 4691 4692 if ((scsirate & SOFS) == 0x0F) { 4693 /* 4694 * Haven't negotiated yet, 4695 * so the format is different. 4696 */ 4697 scsirate = (scsirate & SXFR) >> 4 4698 | (ultraenb & mask) 4699 ? 0x08 : 0x0 4700 | (scsirate & WIDEXFER); 4701 offset = MAX_OFFSET_ULTRA2; 4702 } else 4703 offset = ahc_inb(ahc, TARG_OFFSET + i); 4704 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4705 /* Set to the lowest sync rate, 5MHz */ 4706 scsirate |= 0x1c; 4707 maxsync = AHC_SYNCRATE_ULTRA2; 4708 if ((ahc->features & AHC_DT) != 0) 4709 maxsync = AHC_SYNCRATE_DT; 4710 tinfo->user.period = 4711 ahc_find_period(ahc, scsirate, maxsync); 4712 if (offset == 0) 4713 tinfo->user.period = 0; 4714 else 4715 tinfo->user.offset = ~0; 4716 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4717 && (ahc->features & AHC_DT) != 0) 4718 tinfo->user.ppr_options = 4719 MSG_EXT_PPR_DT_REQ; 4720 } else if ((scsirate & SOFS) != 0) { 4721 if ((scsirate & SXFR) == 0x40 4722 && (ultraenb & mask) != 0) { 4723 /* Treat 10MHz as a non-ultra speed */ 4724 scsirate &= ~SXFR; 4725 ultraenb &= ~mask; 4726 } 4727 tinfo->user.period = 4728 ahc_find_period(ahc, scsirate, 4729 (ultraenb & mask) 4730 ? AHC_SYNCRATE_ULTRA 4731 : AHC_SYNCRATE_FAST); 4732 if (tinfo->user.period != 0) 4733 tinfo->user.offset = ~0; 4734 } 4735 if (tinfo->user.period == 0) 4736 tinfo->user.offset = 0; 4737 if ((scsirate & WIDEXFER) != 0 4738 && (ahc->features & AHC_WIDE) != 0) 4739 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4740 tinfo->user.protocol_version = 4; 4741 if ((ahc->features & AHC_DT) != 0) 4742 tinfo->user.transport_version = 3; 4743 else 4744 tinfo->user.transport_version = 2; 4745 tinfo->goal.protocol_version = 2; 4746 tinfo->goal.transport_version = 2; 4747 tinfo->curr.protocol_version = 2; 4748 tinfo->curr.transport_version = 2; 4749 } 4750 tstate->ultraenb = 0; 4751 tstate->discenable = discenable; 4752 } 4753 ahc->user_discenable = discenable; 4754 ahc->user_tagenable = tagenable; 4755 4756 /* There are no untagged SCBs active yet. */ 4757 for (i = 0; i < 16; i++) { 4758 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4759 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4760 int lun; 4761 4762 /* 4763 * The SCB based BTT allows an entry per 4764 * target and lun pair. 4765 */ 4766 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4767 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4768 } 4769 } 4770 4771 /* All of our queues are empty */ 4772 for (i = 0; i < 256; i++) 4773 ahc->qoutfifo[i] = SCB_LIST_NULL; 4774 4775 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4776 4777 for (i = 0; i < 256; i++) 4778 ahc->qinfifo[i] = SCB_LIST_NULL; 4779 4780 if ((ahc->features & AHC_MULTI_TID) != 0) { 4781 ahc_outb(ahc, TARGID, 0); 4782 ahc_outb(ahc, TARGID + 1, 0); 4783 } 4784 4785 /* 4786 * Tell the sequencer where it can find our arrays in memory. 4787 */ 4788 physaddr = ahc->scb_data->hscb_busaddr; 4789 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4790 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4791 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4792 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4793 4794 physaddr = ahc->shared_data_busaddr; 4795 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4796 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4797 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4798 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4799 4800 /* 4801 * Initialize the group code to command length table. 4802 * This overrides the values in TARG_SCSIRATE, so only 4803 * setup the table after we have processed that information. 4804 */ 4805 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4806 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4807 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4808 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4809 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4810 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4811 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4812 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4813 4814 /* Tell the sequencer of our initial queue positions */ 4815 ahc_outb(ahc, KERNEL_QINPOS, 0); 4816 ahc_outb(ahc, QINPOS, 0); 4817 ahc_outb(ahc, QOUTPOS, 0); 4818 4819 /* 4820 * Use the built in queue management registers 4821 * if they are available. 4822 */ 4823 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4824 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4825 ahc_outb(ahc, SDSCB_QOFF, 0); 4826 ahc_outb(ahc, SNSCB_QOFF, 0); 4827 ahc_outb(ahc, HNSCB_QOFF, 0); 4828 } 4829 4830 4831 /* We don't have any waiting selections */ 4832 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4833 4834 /* Our disconnection list is empty too */ 4835 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4836 4837 /* Message out buffer starts empty */ 4838 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4839 4840 /* 4841 * Setup the allowed SCSI Sequences based on operational mode. 4842 * If we are a target, we'll enalbe select in operations once 4843 * we've had a lun enabled. 4844 */ 4845 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4846 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4847 scsiseq_template |= ENRSELI; 4848 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4849 4850 /* 4851 * Load the Sequencer program and Enable the adapter 4852 * in "fast" mode. 4853 */ 4854 if (bootverbose) 4855 printf("%s: Downloading Sequencer Program...", 4856 ahc_name(ahc)); 4857 4858 ahc_loadseq(ahc); 4859 4860 if ((ahc->features & AHC_ULTRA2) != 0) { 4861 int wait; 4862 4863 /* 4864 * Wait for up to 500ms for our transceivers 4865 * to settle. If the adapter does not have 4866 * a cable attached, the tranceivers may 4867 * never settle, so don't complain if we 4868 * fail here. 4869 */ 4870 ahc_pause(ahc); 4871 for (wait = 5000; 4872 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4873 wait--) 4874 ahc_delay(100); 4875 ahc_unpause(ahc); 4876 } 4877 4878 /* We have to wait until after any system dumps... */ 4879 ahc->shutdown_hook = shutdownhook_establish(ahc_shutdown, ahc); 4880 4881 return (0); 4882 } 4883 4884 void 4885 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4886 { 4887 u_int hcntrl; 4888 4889 hcntrl = ahc_inb(ahc, HCNTRL); 4890 hcntrl &= ~INTEN; 4891 ahc->pause &= ~INTEN; 4892 ahc->unpause &= ~INTEN; 4893 if (enable) { 4894 hcntrl |= INTEN; 4895 ahc->pause |= INTEN; 4896 ahc->unpause |= INTEN; 4897 } 4898 ahc_outb(ahc, HCNTRL, hcntrl); 4899 } 4900 4901 /* 4902 * Ensure that the card is paused in a location 4903 * outside of all critical sections and that all 4904 * pending work is completed prior to returning. 4905 * This routine should only be called from outside 4906 * an interrupt context. 4907 */ 4908 void 4909 ahc_pause_and_flushwork(struct ahc_softc *ahc) 4910 { 4911 int intstat; 4912 int maxloops; 4913 int paused; 4914 4915 maxloops = 1000; 4916 ahc->flags |= AHC_ALL_INTERRUPTS; 4917 intstat = 0; 4918 paused = FALSE; 4919 do { 4920 if (paused) 4921 ahc_unpause(ahc); 4922 ahc_intr(ahc); 4923 ahc_pause(ahc); 4924 paused = TRUE; 4925 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 4926 ahc_clear_critical_section(ahc); 4927 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4928 break; 4929 } while (--maxloops 4930 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0 4931 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)))); 4932 if (maxloops == 0) { 4933 printf("Infinite interrupt loop, INTSTAT = %x", 4934 ahc_inb(ahc, INTSTAT)); 4935 } 4936 ahc_platform_flushwork(ahc); 4937 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4938 } 4939 4940 int 4941 ahc_suspend(struct ahc_softc *ahc) 4942 { 4943 uint8_t *ptr; 4944 int i; 4945 4946 ahc_pause_and_flushwork(ahc); 4947 4948 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4949 return (EBUSY); 4950 4951 #if AHC_TARGET_MODE 4952 /* 4953 * XXX What about ATIOs that have not yet been serviced? 4954 * Perhaps we should just refuse to be suspended if we 4955 * are acting in a target role. 4956 */ 4957 if (ahc->pending_device != NULL) 4958 return (EBUSY); 4959 #endif 4960 4961 /* Save volatile registers */ 4962 if ((ahc->features & AHC_TWIN) != 0) { 4963 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4964 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4965 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4966 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4967 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4968 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4969 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4970 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4971 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4972 } 4973 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4974 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4975 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4976 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4977 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4978 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4979 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4980 4981 if ((ahc->chip & AHC_PCI) != 0) { 4982 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4983 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4984 } 4985 4986 if ((ahc->features & AHC_DT) != 0) { 4987 u_int sfunct; 4988 4989 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4990 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4991 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4992 ahc_outb(ahc, SFUNCT, sfunct); 4993 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4994 } 4995 4996 if ((ahc->features & AHC_MULTI_FUNC) != 0) 4997 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 4998 4999 if ((ahc->features & AHC_ULTRA2) != 0) 5000 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 5001 5002 ptr = ahc->suspend_state.scratch_ram; 5003 for (i = 0; i < 64; i++) 5004 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 5005 5006 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5007 for (i = 0; i < 16; i++) 5008 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 5009 } 5010 5011 ptr = ahc->suspend_state.btt; 5012 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5013 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5014 int j; 5015 5016 for (j = 0;j < AHC_NUM_LUNS; j++) { 5017 u_int tcl; 5018 5019 tcl = BUILD_TCL(i << 4, j); 5020 *ptr = ahc_index_busy_tcl(ahc, tcl); 5021 } 5022 } 5023 } 5024 ahc_shutdown(ahc); 5025 return (0); 5026 } 5027 5028 int 5029 ahc_resume(struct ahc_softc *ahc) 5030 { 5031 uint8_t *ptr; 5032 int i; 5033 5034 ahc_reset(ahc); 5035 5036 ahc_build_free_scb_list(ahc); 5037 5038 /* Restore volatile registers */ 5039 if ((ahc->features & AHC_TWIN) != 0) { 5040 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5041 ahc_outb(ahc, SCSIID, ahc->our_id); 5042 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 5043 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 5044 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 5045 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 5046 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 5047 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 5048 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 5049 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5050 } 5051 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 5052 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 5053 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 5054 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 5055 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 5056 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 5057 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 5058 if ((ahc->features & AHC_ULTRA2) != 0) 5059 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5060 else 5061 ahc_outb(ahc, SCSIID, ahc->our_id); 5062 5063 if ((ahc->chip & AHC_PCI) != 0) { 5064 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 5065 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 5066 } 5067 5068 if ((ahc->features & AHC_DT) != 0) { 5069 u_int sfunct; 5070 5071 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 5072 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 5073 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 5074 ahc_outb(ahc, SFUNCT, sfunct); 5075 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 5076 } 5077 5078 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5079 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 5080 5081 if ((ahc->features & AHC_ULTRA2) != 0) 5082 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 5083 5084 ptr = ahc->suspend_state.scratch_ram; 5085 for (i = 0; i < 64; i++) 5086 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 5087 5088 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5089 for (i = 0; i < 16; i++) 5090 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 5091 } 5092 5093 ptr = ahc->suspend_state.btt; 5094 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5095 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5096 int j; 5097 5098 for (j = 0;j < AHC_NUM_LUNS; j++) { 5099 u_int tcl; 5100 5101 tcl = BUILD_TCL(i << 4, j); 5102 ahc_busy_tcl(ahc, tcl, *ptr); 5103 } 5104 } 5105 } 5106 return (0); 5107 } 5108 5109 /************************** Busy Target Table *********************************/ 5110 /* 5111 * Return the untagged transaction id for a given target/channel lun. 5112 * Optionally, clear the entry. 5113 */ 5114 u_int 5115 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5116 { 5117 u_int scbid; 5118 u_int target_offset; 5119 5120 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5121 u_int saved_scbptr; 5122 5123 saved_scbptr = ahc_inb(ahc, SCBPTR); 5124 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5125 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5126 ahc_outb(ahc, SCBPTR, saved_scbptr); 5127 } else { 5128 target_offset = TCL_TARGET_OFFSET(tcl); 5129 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5130 } 5131 5132 return (scbid); 5133 } 5134 5135 void 5136 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5137 { 5138 u_int target_offset; 5139 5140 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5141 u_int saved_scbptr; 5142 5143 saved_scbptr = ahc_inb(ahc, SCBPTR); 5144 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5145 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5146 ahc_outb(ahc, SCBPTR, saved_scbptr); 5147 } else { 5148 target_offset = TCL_TARGET_OFFSET(tcl); 5149 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5150 } 5151 } 5152 5153 void 5154 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5155 { 5156 u_int target_offset; 5157 5158 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5159 u_int saved_scbptr; 5160 5161 saved_scbptr = ahc_inb(ahc, SCBPTR); 5162 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5163 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5164 ahc_outb(ahc, SCBPTR, saved_scbptr); 5165 } else { 5166 target_offset = TCL_TARGET_OFFSET(tcl); 5167 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5168 } 5169 } 5170 5171 /************************** SCB and SCB queue management **********************/ 5172 int 5173 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5174 char channel, int lun, u_int tag, role_t role) 5175 { 5176 int targ = SCB_GET_TARGET(ahc, scb); 5177 char chan = SCB_GET_CHANNEL(ahc, scb); 5178 int slun = SCB_GET_LUN(scb); 5179 int match; 5180 5181 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5182 if (match != 0) 5183 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5184 if (match != 0) 5185 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5186 if (match != 0) { 5187 #if 0 5188 #if AHC_TARGET_MODE 5189 int group; 5190 5191 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5192 if (role == ROLE_INITIATOR) { 5193 match = (group != XPT_FC_GROUP_TMODE) 5194 && ((tag == scb->hscb->tag) 5195 || (tag == SCB_LIST_NULL)); 5196 } else if (role == ROLE_TARGET) { 5197 match = (group == XPT_FC_GROUP_TMODE) 5198 && ((tag == scb->io_ctx->csio.tag_id) 5199 || (tag == SCB_LIST_NULL)); 5200 } 5201 #else /* !AHC_TARGET_MODE */ 5202 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5203 #endif /* AHC_TARGET_MODE */ 5204 #endif 5205 } 5206 5207 return match; 5208 } 5209 5210 void 5211 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5212 { 5213 int target; 5214 char channel; 5215 int lun; 5216 5217 target = SCB_GET_TARGET(ahc, scb); 5218 lun = SCB_GET_LUN(scb); 5219 channel = SCB_GET_CHANNEL(ahc, scb); 5220 5221 ahc_search_qinfifo(ahc, target, channel, lun, 5222 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5223 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5224 5225 ahc_platform_freeze_devq(ahc, scb); 5226 } 5227 5228 void 5229 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5230 { 5231 struct scb *prev_scb; 5232 5233 prev_scb = NULL; 5234 if (ahc_qinfifo_count(ahc) != 0) { 5235 u_int prev_tag; 5236 uint8_t prev_pos; 5237 5238 prev_pos = ahc->qinfifonext - 1; 5239 prev_tag = ahc->qinfifo[prev_pos]; 5240 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5241 } 5242 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5243 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5244 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5245 } else { 5246 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5247 } 5248 } 5249 5250 static void 5251 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5252 struct scb *scb) 5253 { 5254 if (prev_scb == NULL) { 5255 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5256 } else { 5257 prev_scb->hscb->next = scb->hscb->tag; 5258 ahc_sync_scb(ahc, prev_scb, 5259 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5260 } 5261 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5262 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5263 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5264 } 5265 5266 static int 5267 ahc_qinfifo_count(struct ahc_softc *ahc) 5268 { 5269 uint8_t qinpos; 5270 uint8_t diff; 5271 5272 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5273 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5274 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5275 } else 5276 qinpos = ahc_inb(ahc, QINPOS); 5277 diff = ahc->qinfifonext - qinpos; 5278 return (diff); 5279 } 5280 5281 int 5282 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5283 int lun, u_int tag, role_t role, uint32_t status, 5284 ahc_search_action action) 5285 { 5286 struct scb *scb; 5287 struct scb *prev_scb; 5288 uint8_t qinstart; 5289 uint8_t qinpos; 5290 uint8_t qintail; 5291 uint8_t next; 5292 uint8_t prev; 5293 uint8_t curscbptr; 5294 int found; 5295 int have_qregs; 5296 5297 qintail = ahc->qinfifonext; 5298 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5299 if (have_qregs) { 5300 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5301 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5302 } else 5303 qinstart = ahc_inb(ahc, QINPOS); 5304 qinpos = qinstart; 5305 found = 0; 5306 prev_scb = NULL; 5307 5308 if (action == SEARCH_COMPLETE) { 5309 /* 5310 * Don't attempt to run any queued untagged transactions 5311 * until we are done with the abort process. 5312 */ 5313 ahc_freeze_untagged_queues(ahc); 5314 } 5315 5316 /* 5317 * Start with an empty queue. Entries that are not chosen 5318 * for removal will be re-added to the queue as we go. 5319 */ 5320 ahc->qinfifonext = qinpos; 5321 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5322 5323 while (qinpos != qintail) { 5324 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5325 if (scb == NULL) { 5326 printf("qinpos = %d, SCB index = %d\n", 5327 qinpos, ahc->qinfifo[qinpos]); 5328 panic("Loop 1\n"); 5329 } 5330 5331 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5332 /* 5333 * We found an scb that needs to be acted on. 5334 */ 5335 found++; 5336 switch (action) { 5337 case SEARCH_COMPLETE: 5338 { 5339 cam_status ostat; 5340 cam_status cstat; 5341 5342 ostat = ahc_get_transaction_status(scb); 5343 if (ostat == CAM_REQ_INPROG) 5344 ahc_set_transaction_status(scb, status); 5345 cstat = ahc_get_transaction_status(scb); 5346 if (cstat != CAM_REQ_CMP) 5347 ahc_freeze_scb(scb); 5348 if ((scb->flags & SCB_ACTIVE) == 0) 5349 printf("Inactive SCB in qinfifo\n"); 5350 ahc_done(ahc, scb); 5351 5352 /* FALLTHROUGH */ 5353 } 5354 case SEARCH_REMOVE: 5355 break; 5356 case SEARCH_COUNT: 5357 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5358 prev_scb = scb; 5359 break; 5360 } 5361 } else { 5362 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5363 prev_scb = scb; 5364 } 5365 qinpos++; 5366 } 5367 5368 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5369 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5370 } else { 5371 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5372 } 5373 5374 if (action != SEARCH_COUNT 5375 && (found != 0) 5376 && (qinstart != ahc->qinfifonext)) { 5377 /* 5378 * The sequencer may be in the process of DMA'ing 5379 * down the SCB at the beginning of the queue. 5380 * This could be problematic if either the first, 5381 * or the second SCB is removed from the queue 5382 * (the first SCB includes a pointer to the "next" 5383 * SCB to DMA). If we have removed any entries, swap 5384 * the first element in the queue with the next HSCB 5385 * so the sequencer will notice that NEXT_QUEUED_SCB 5386 * has changed during its DMA attempt and will retry 5387 * the DMA. 5388 */ 5389 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5390 5391 if (scb == NULL) { 5392 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5393 found, qinstart, ahc->qinfifonext); 5394 panic("First/Second Qinfifo fixup\n"); 5395 } 5396 /* 5397 * ahc_swap_with_next_hscb forces our next pointer to 5398 * point to the reserved SCB for future commands. Save 5399 * and restore our original next pointer to maintain 5400 * queue integrity. 5401 */ 5402 next = scb->hscb->next; 5403 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5404 ahc_swap_with_next_hscb(ahc, scb); 5405 scb->hscb->next = next; 5406 ahc->qinfifo[qinstart] = scb->hscb->tag; 5407 5408 /* Tell the card about the new head of the qinfifo. */ 5409 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5410 5411 /* Fixup the tail "next" pointer. */ 5412 qintail = ahc->qinfifonext - 1; 5413 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5414 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5415 } 5416 5417 /* 5418 * Search waiting for selection list. 5419 */ 5420 curscbptr = ahc_inb(ahc, SCBPTR); 5421 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5422 prev = SCB_LIST_NULL; 5423 5424 while (next != SCB_LIST_NULL) { 5425 uint8_t scb_index; 5426 5427 ahc_outb(ahc, SCBPTR, next); 5428 scb_index = ahc_inb(ahc, SCB_TAG); 5429 if (scb_index >= ahc->scb_data->numscbs) { 5430 printf("Waiting List inconsistency. " 5431 "SCB index == %d, yet numscbs == %d.", 5432 scb_index, ahc->scb_data->numscbs); 5433 ahc_dump_card_state(ahc); 5434 panic("for safety"); 5435 } 5436 scb = ahc_lookup_scb(ahc, scb_index); 5437 if (scb == NULL) { 5438 printf("scb_index = %d, next = %d\n", 5439 scb_index, next); 5440 panic("Waiting List traversal\n"); 5441 } 5442 if (ahc_match_scb(ahc, scb, target, channel, 5443 lun, SCB_LIST_NULL, role)) { 5444 /* 5445 * We found an scb that needs to be acted on. 5446 */ 5447 found++; 5448 switch (action) { 5449 case SEARCH_COMPLETE: 5450 { 5451 cam_status ostat; 5452 cam_status cstat; 5453 5454 ostat = ahc_get_transaction_status(scb); 5455 if (ostat == CAM_REQ_INPROG) 5456 ahc_set_transaction_status(scb, status); 5457 cstat = ahc_get_transaction_status(scb); 5458 if (cstat != CAM_REQ_CMP) 5459 ahc_freeze_scb(scb); 5460 if ((scb->flags & SCB_ACTIVE) == 0) 5461 printf("Inactive SCB in Waiting List\n"); 5462 ahc_done(ahc, scb); 5463 /* FALLTHROUGH */ 5464 } 5465 case SEARCH_REMOVE: 5466 next = ahc_rem_wscb(ahc, next, prev); 5467 break; 5468 case SEARCH_COUNT: 5469 prev = next; 5470 next = ahc_inb(ahc, SCB_NEXT); 5471 break; 5472 } 5473 } else { 5474 5475 prev = next; 5476 next = ahc_inb(ahc, SCB_NEXT); 5477 } 5478 } 5479 ahc_outb(ahc, SCBPTR, curscbptr); 5480 5481 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5482 channel, lun, status, action); 5483 5484 if (action == SEARCH_COMPLETE) 5485 ahc_release_untagged_queues(ahc); 5486 return (found); 5487 } 5488 5489 int 5490 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsipi_xfer *xs, /*ahc_io_ctx_t ctx,*/ 5491 int target, char channel, int lun, uint32_t status, 5492 ahc_search_action action) 5493 { 5494 struct scb *scb; 5495 int maxtarget; 5496 int found; 5497 int i; 5498 5499 if (action == SEARCH_COMPLETE) { 5500 /* 5501 * Don't attempt to run any queued untagged transactions 5502 * until we are done with the abort process. 5503 */ 5504 ahc_freeze_untagged_queues(ahc); 5505 } 5506 5507 found = 0; 5508 i = 0; 5509 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5510 5511 maxtarget = 16; 5512 if (target != CAM_TARGET_WILDCARD) { 5513 5514 i = target; 5515 if (channel == 'B') 5516 i += 8; 5517 maxtarget = i + 1; 5518 } 5519 } else { 5520 maxtarget = 0; 5521 } 5522 5523 for (; i < maxtarget; i++) { 5524 struct scb_tailq *untagged_q; 5525 struct scb *next_scb; 5526 5527 untagged_q = &(ahc->untagged_queues[i]); 5528 next_scb = TAILQ_FIRST(untagged_q); 5529 while (next_scb != NULL) { 5530 5531 scb = next_scb; 5532 next_scb = TAILQ_NEXT(scb, links.tqe); 5533 5534 /* 5535 * The head of the list may be the currently 5536 * active untagged command for a device. 5537 * We're only searching for commands that 5538 * have not been started. A transaction 5539 * marked active but still in the qinfifo 5540 * is removed by the qinfifo scanning code 5541 * above. 5542 */ 5543 if ((scb->flags & SCB_ACTIVE) != 0) 5544 continue; 5545 5546 if (ahc_match_scb(ahc, scb, target, channel, lun, 5547 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5548 /*|| (ctx != NULL && ctx != scb->io_ctx)*/) 5549 continue; 5550 5551 /* 5552 * We found an scb that needs to be acted on. 5553 */ 5554 found++; 5555 switch (action) { 5556 case SEARCH_COMPLETE: 5557 { 5558 cam_status ostat; 5559 cam_status cstat; 5560 5561 ostat = ahc_get_transaction_status(scb); 5562 if (ostat == CAM_REQ_INPROG) 5563 ahc_set_transaction_status(scb, status); 5564 cstat = ahc_get_transaction_status(scb); 5565 if (cstat != CAM_REQ_CMP) 5566 ahc_freeze_scb(scb); 5567 if ((scb->flags & SCB_ACTIVE) == 0) 5568 printf("Inactive SCB in untaggedQ\n"); 5569 ahc_done(ahc, scb); 5570 break; 5571 } 5572 case SEARCH_REMOVE: 5573 scb->flags &= ~SCB_UNTAGGEDQ; 5574 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5575 break; 5576 case SEARCH_COUNT: 5577 break; 5578 } 5579 } 5580 } 5581 5582 if (action == SEARCH_COMPLETE) 5583 ahc_release_untagged_queues(ahc); 5584 return (found); 5585 } 5586 5587 int 5588 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5589 int lun, u_int tag, int stop_on_first, int remove, 5590 int save_state) 5591 { 5592 struct scb *scbp; 5593 u_int next; 5594 u_int prev; 5595 u_int count; 5596 u_int active_scb; 5597 5598 count = 0; 5599 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5600 prev = SCB_LIST_NULL; 5601 5602 if (save_state) { 5603 /* restore this when we're done */ 5604 active_scb = ahc_inb(ahc, SCBPTR); 5605 } else 5606 /* Silence compiler */ 5607 active_scb = SCB_LIST_NULL; 5608 5609 while (next != SCB_LIST_NULL) { 5610 u_int scb_index; 5611 5612 ahc_outb(ahc, SCBPTR, next); 5613 scb_index = ahc_inb(ahc, SCB_TAG); 5614 if (scb_index >= ahc->scb_data->numscbs) { 5615 printf("Disconnected List inconsistency. " 5616 "SCB index == %d, yet numscbs == %d.", 5617 scb_index, ahc->scb_data->numscbs); 5618 ahc_dump_card_state(ahc); 5619 panic("for safety"); 5620 } 5621 5622 if (next == prev) { 5623 panic("Disconnected List Loop. " 5624 "cur SCBPTR == %x, prev SCBPTR == %x.", 5625 next, prev); 5626 } 5627 scbp = ahc_lookup_scb(ahc, scb_index); 5628 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5629 tag, ROLE_INITIATOR)) { 5630 count++; 5631 if (remove) { 5632 next = 5633 ahc_rem_scb_from_disc_list(ahc, prev, next); 5634 } else { 5635 prev = next; 5636 next = ahc_inb(ahc, SCB_NEXT); 5637 } 5638 if (stop_on_first) 5639 break; 5640 } else { 5641 prev = next; 5642 next = ahc_inb(ahc, SCB_NEXT); 5643 } 5644 } 5645 if (save_state) 5646 ahc_outb(ahc, SCBPTR, active_scb); 5647 return (count); 5648 } 5649 5650 /* 5651 * Remove an SCB from the on chip list of disconnected transactions. 5652 * This is empty/unused if we are not performing SCB paging. 5653 */ 5654 static u_int 5655 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5656 { 5657 u_int next; 5658 5659 ahc_outb(ahc, SCBPTR, scbptr); 5660 next = ahc_inb(ahc, SCB_NEXT); 5661 5662 ahc_outb(ahc, SCB_CONTROL, 0); 5663 5664 ahc_add_curscb_to_free_list(ahc); 5665 5666 if (prev != SCB_LIST_NULL) { 5667 ahc_outb(ahc, SCBPTR, prev); 5668 ahc_outb(ahc, SCB_NEXT, next); 5669 } else 5670 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5671 5672 return (next); 5673 } 5674 5675 /* 5676 * Add the SCB as selected by SCBPTR onto the on chip list of 5677 * free hardware SCBs. This list is empty/unused if we are not 5678 * performing SCB paging. 5679 */ 5680 static void 5681 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5682 { 5683 /* 5684 * Invalidate the tag so that our abort 5685 * routines don't think it's active. 5686 */ 5687 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5688 5689 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5690 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5691 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5692 } 5693 } 5694 5695 /* 5696 * Manipulate the waiting for selection list and return the 5697 * scb that follows the one that we remove. 5698 */ 5699 static u_int 5700 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5701 { 5702 u_int curscb, next; 5703 5704 /* 5705 * Select the SCB we want to abort and 5706 * pull the next pointer out of it. 5707 */ 5708 curscb = ahc_inb(ahc, SCBPTR); 5709 ahc_outb(ahc, SCBPTR, scbpos); 5710 next = ahc_inb(ahc, SCB_NEXT); 5711 5712 /* Clear the necessary fields */ 5713 ahc_outb(ahc, SCB_CONTROL, 0); 5714 5715 ahc_add_curscb_to_free_list(ahc); 5716 5717 /* update the waiting list */ 5718 if (prev == SCB_LIST_NULL) { 5719 /* First in the list */ 5720 ahc_outb(ahc, WAITING_SCBH, next); 5721 5722 /* 5723 * Ensure we aren't attempting to perform 5724 * selection for this entry. 5725 */ 5726 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5727 } else { 5728 /* 5729 * Select the scb that pointed to us 5730 * and update its next pointer. 5731 */ 5732 ahc_outb(ahc, SCBPTR, prev); 5733 ahc_outb(ahc, SCB_NEXT, next); 5734 } 5735 5736 /* 5737 * Point us back at the original scb position. 5738 */ 5739 ahc_outb(ahc, SCBPTR, curscb); 5740 return next; 5741 } 5742 5743 /******************************** Error Handling ******************************/ 5744 /* 5745 * Abort all SCBs that match the given description (target/channel/lun/tag), 5746 * setting their status to the passed in status if the status has not already 5747 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5748 * is paused before it is called. 5749 */ 5750 int 5751 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5752 int lun, u_int tag, role_t role, uint32_t status) 5753 { 5754 struct scb *scbp; 5755 struct scb *scbp_next; 5756 u_int active_scb; 5757 int i, j; 5758 int maxtarget; 5759 int minlun; 5760 int maxlun; 5761 5762 int found; 5763 5764 /* 5765 * Don't attempt to run any queued untagged transactions 5766 * until we are done with the abort process. 5767 */ 5768 ahc_freeze_untagged_queues(ahc); 5769 5770 /* restore this when we're done */ 5771 active_scb = ahc_inb(ahc, SCBPTR); 5772 5773 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5774 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5775 5776 /* 5777 * Clean out the busy target table for any untagged commands. 5778 */ 5779 i = 0; 5780 maxtarget = 16; 5781 if (target != CAM_TARGET_WILDCARD) { 5782 i = target; 5783 if (channel == 'B') 5784 i += 8; 5785 maxtarget = i + 1; 5786 } 5787 5788 if (lun == CAM_LUN_WILDCARD) { 5789 5790 /* 5791 * Unless we are using an SCB based 5792 * busy targets table, there is only 5793 * one table entry for all luns of 5794 * a target. 5795 */ 5796 minlun = 0; 5797 maxlun = 1; 5798 if ((ahc->flags & AHC_SCB_BTT) != 0) 5799 maxlun = AHC_NUM_LUNS; 5800 } else { 5801 minlun = lun; 5802 maxlun = lun + 1; 5803 } 5804 5805 if (role != ROLE_TARGET) { 5806 for (;i < maxtarget; i++) { 5807 for (j = minlun;j < maxlun; j++) { 5808 u_int scbid; 5809 u_int tcl; 5810 5811 tcl = BUILD_TCL(i << 4, j); 5812 scbid = ahc_index_busy_tcl(ahc, tcl); 5813 scbp = ahc_lookup_scb(ahc, scbid); 5814 if (scbp == NULL 5815 || ahc_match_scb(ahc, scbp, target, channel, 5816 lun, tag, role) == 0) 5817 continue; 5818 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5819 } 5820 } 5821 5822 /* 5823 * Go through the disconnected list and remove any entries we 5824 * have queued for completion, 0'ing their control byte too. 5825 * We save the active SCB and restore it ourselves, so there 5826 * is no reason for this search to restore it too. 5827 */ 5828 ahc_search_disc_list(ahc, target, channel, lun, tag, 5829 /*stop_on_first*/FALSE, /*remove*/TRUE, 5830 /*save_state*/FALSE); 5831 } 5832 5833 /* 5834 * Go through the hardware SCB array looking for commands that 5835 * were active but not on any list. In some cases, these remnants 5836 * might not still have mappings in the scbindex array (e.g. unexpected 5837 * bus free with the same scb queued for an abort). Don't hold this 5838 * against them. 5839 */ 5840 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5841 u_int scbid; 5842 5843 ahc_outb(ahc, SCBPTR, i); 5844 scbid = ahc_inb(ahc, SCB_TAG); 5845 scbp = ahc_lookup_scb(ahc, scbid); 5846 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5847 || (scbp != NULL 5848 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5849 ahc_add_curscb_to_free_list(ahc); 5850 } 5851 5852 /* 5853 * Go through the pending CCB list and look for 5854 * commands for this target that are still active. 5855 * These are other tagged commands that were 5856 * disconnected when the reset occurred. 5857 */ 5858 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5859 while (scbp_next != NULL) { 5860 scbp = scbp_next; 5861 scbp_next = LIST_NEXT(scbp, pending_links); 5862 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5863 cam_status ostat; 5864 5865 ostat = ahc_get_transaction_status(scbp); 5866 if (ostat == CAM_REQ_INPROG) 5867 ahc_set_transaction_status(scbp, status); 5868 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5869 ahc_freeze_scb(scbp); 5870 if ((scbp->flags & SCB_ACTIVE) == 0) 5871 printf("Inactive SCB on pending list\n"); 5872 ahc_done(ahc, scbp); 5873 found++; 5874 } 5875 } 5876 ahc_outb(ahc, SCBPTR, active_scb); 5877 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5878 ahc_release_untagged_queues(ahc); 5879 return found; 5880 } 5881 5882 static void 5883 ahc_reset_current_bus(struct ahc_softc *ahc) 5884 { 5885 uint8_t scsiseq; 5886 5887 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5888 scsiseq = ahc_inb(ahc, SCSISEQ); 5889 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5890 ahc_flush_device_writes(ahc); 5891 ahc_delay(AHC_BUSRESET_DELAY); 5892 /* Turn off the bus reset */ 5893 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5894 5895 ahc_clear_intstat(ahc); 5896 5897 /* Re-enable reset interrupts */ 5898 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5899 } 5900 5901 int 5902 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5903 { 5904 struct ahc_devinfo devinfo; 5905 u_int initiator, target, max_scsiid; 5906 u_int sblkctl; 5907 u_int scsiseq; 5908 u_int simode1; 5909 int found; 5910 int restart_needed; 5911 char cur_channel; 5912 5913 ahc->pending_device = NULL; 5914 5915 ahc_compile_devinfo(&devinfo, 5916 CAM_TARGET_WILDCARD, 5917 CAM_TARGET_WILDCARD, 5918 CAM_LUN_WILDCARD, 5919 channel, ROLE_UNKNOWN); 5920 ahc_pause(ahc); 5921 5922 /* Make sure the sequencer is in a safe location. */ 5923 ahc_clear_critical_section(ahc); 5924 5925 /* 5926 * Run our command complete fifos to ensure that we perform 5927 * completion processing on any commands that 'completed' 5928 * before the reset occurred. 5929 */ 5930 ahc_run_qoutfifo(ahc); 5931 #if AHC_TARGET_MODE 5932 /* 5933 * XXX - In Twin mode, the tqinfifo may have commands 5934 * for an unaffected channel in it. However, if 5935 * we have run out of ATIO resources to drain that 5936 * queue, we may not get them all out here. Further, 5937 * the blocked transactions for the reset channel 5938 * should just be killed off, irrespecitve of whether 5939 * we are blocked on ATIO resources. Write a routine 5940 * to compact the tqinfifo appropriately. 5941 */ 5942 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5943 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5944 } 5945 #endif 5946 5947 /* 5948 * Reset the bus if we are initiating this reset 5949 */ 5950 sblkctl = ahc_inb(ahc, SBLKCTL); 5951 cur_channel = 'A'; 5952 if ((ahc->features & AHC_TWIN) != 0 5953 && ((sblkctl & SELBUSB) != 0)) 5954 cur_channel = 'B'; 5955 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5956 if (cur_channel != channel) { 5957 /* Case 1: Command for another bus is active 5958 * Stealthily reset the other bus without 5959 * upsetting the current bus. 5960 */ 5961 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5962 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5963 #if AHC_TARGET_MODE 5964 /* 5965 * Bus resets clear ENSELI, so we cannot 5966 * defer re-enabling bus reset interrupts 5967 * if we are in target mode. 5968 */ 5969 if ((ahc->flags & AHC_TARGETROLE) != 0) 5970 simode1 |= ENSCSIRST; 5971 #endif 5972 ahc_outb(ahc, SIMODE1, simode1); 5973 if (initiate_reset) 5974 ahc_reset_current_bus(ahc); 5975 ahc_clear_intstat(ahc); 5976 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5977 ahc_outb(ahc, SBLKCTL, sblkctl); 5978 restart_needed = FALSE; 5979 } else { 5980 /* Case 2: A command from this bus is active or we're idle */ 5981 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5982 #if AHC_TARGET_MODE 5983 /* 5984 * Bus resets clear ENSELI, so we cannot 5985 * defer re-enabling bus reset interrupts 5986 * if we are in target mode. 5987 */ 5988 if ((ahc->flags & AHC_TARGETROLE) != 0) 5989 simode1 |= ENSCSIRST; 5990 #endif 5991 ahc_outb(ahc, SIMODE1, simode1); 5992 if (initiate_reset) 5993 ahc_reset_current_bus(ahc); 5994 ahc_clear_intstat(ahc); 5995 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5996 restart_needed = TRUE; 5997 } 5998 5999 /* 6000 * Clean up all the state information for the 6001 * pending transactions on this bus. 6002 */ 6003 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6004 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6005 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6006 6007 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6008 6009 #ifdef AHC_TARGET_MODE 6010 /* 6011 * Send an immediate notify ccb to all target more peripheral 6012 * drivers affected by this action. 6013 */ 6014 for (target = 0; target <= max_scsiid; target++) { 6015 struct ahc_tmode_tstate* tstate; 6016 u_int lun; 6017 6018 tstate = ahc->enabled_targets[target]; 6019 if (tstate == NULL) 6020 continue; 6021 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6022 struct ahc_tmode_lstate* lstate; 6023 6024 lstate = tstate->enabled_luns[lun]; 6025 if (lstate == NULL) 6026 continue; 6027 6028 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6029 EVENT_TYPE_BUS_RESET, /*arg*/0); 6030 ahc_send_lstate_events(ahc, lstate); 6031 } 6032 } 6033 #endif 6034 /* 6035 * Revert to async/narrow transfers until we renegotiate. 6036 */ 6037 for (target = 0; target <= max_scsiid; target++) { 6038 6039 if (ahc->enabled_targets[target] == NULL) 6040 continue; 6041 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6042 struct ahc_devinfo devinfo; 6043 6044 ahc_compile_devinfo(&devinfo, target, initiator, 6045 CAM_LUN_WILDCARD, 6046 channel, ROLE_UNKNOWN); 6047 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6048 AHC_TRANS_CUR, /*paused*/TRUE); 6049 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6050 /*period*/0, /*offset*/0, 6051 /*ppr_options*/0, AHC_TRANS_CUR, 6052 /*paused*/TRUE); 6053 } 6054 } 6055 6056 if (restart_needed) 6057 ahc_restart(ahc); 6058 else 6059 ahc_unpause(ahc); 6060 return found; 6061 } 6062 6063 6064 /***************************** Residual Processing ****************************/ 6065 /* 6066 * Calculate the residual for a just completed SCB. 6067 */ 6068 void 6069 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6070 { 6071 struct hardware_scb *hscb; 6072 struct status_pkt *spkt; 6073 uint32_t sgptr; 6074 uint32_t resid_sgptr; 6075 uint32_t resid; 6076 6077 /* 6078 * 5 cases. 6079 * 1) No residual. 6080 * SG_RESID_VALID clear in sgptr. 6081 * 2) Transferless command 6082 * 3) Never performed any transfers. 6083 * sgptr has SG_FULL_RESID set. 6084 * 4) No residual but target did not 6085 * save data pointers after the 6086 * last transfer, so sgptr was 6087 * never updated. 6088 * 5) We have a partial residual. 6089 * Use residual_sgptr to determine 6090 * where we are. 6091 */ 6092 6093 hscb = scb->hscb; 6094 sgptr = ahc_le32toh(hscb->sgptr); 6095 if ((sgptr & SG_RESID_VALID) == 0) 6096 /* Case 1 */ 6097 return; 6098 sgptr &= ~SG_RESID_VALID; 6099 6100 if ((sgptr & SG_LIST_NULL) != 0) 6101 /* Case 2 */ 6102 return; 6103 6104 spkt = &hscb->shared_data.status; 6105 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6106 if ((sgptr & SG_FULL_RESID) != 0) { 6107 /* Case 3 */ 6108 resid = ahc_get_transfer_length(scb); 6109 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6110 /* Case 4 */ 6111 return; 6112 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6113 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6114 } else { 6115 struct ahc_dma_seg *sg; 6116 6117 /* 6118 * Remainder of the SG where the transfer 6119 * stopped. 6120 */ 6121 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6122 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6123 6124 /* The residual sg_ptr always points to the next sg */ 6125 sg--; 6126 6127 /* 6128 * Add up the contents of all residual 6129 * SG segments that are after the SG where 6130 * the transfer stopped. 6131 */ 6132 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6133 sg++; 6134 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6135 } 6136 } 6137 if ((scb->flags & SCB_SENSE) == 0) 6138 ahc_set_residual(scb, resid); 6139 else 6140 ahc_set_sense_residual(scb, resid); 6141 6142 #ifdef AHC_DEBUG 6143 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6144 ahc_print_path(ahc, scb); 6145 printf("Handled %sResidual of %d bytes\n", 6146 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6147 } 6148 #endif 6149 } 6150 6151 /******************************* Target Mode **********************************/ 6152 #ifdef AHC_TARGET_MODE 6153 /* 6154 * Add a target mode event to this lun's queue 6155 */ 6156 static void 6157 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6158 u_int initiator_id, u_int event_type, u_int event_arg) 6159 { 6160 struct ahc_tmode_event *event; 6161 int pending; 6162 6163 xpt_freeze_devq(lstate->path, /*count*/1); 6164 if (lstate->event_w_idx >= lstate->event_r_idx) 6165 pending = lstate->event_w_idx - lstate->event_r_idx; 6166 else 6167 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6168 - (lstate->event_r_idx - lstate->event_w_idx); 6169 6170 if (event_type == EVENT_TYPE_BUS_RESET 6171 || event_type == MSG_BUS_DEV_RESET) { 6172 /* 6173 * Any earlier events are irrelevant, so reset our buffer. 6174 * This has the effect of allowing us to deal with reset 6175 * floods (an external device holding down the reset line) 6176 * without losing the event that is really interesting. 6177 */ 6178 lstate->event_r_idx = 0; 6179 lstate->event_w_idx = 0; 6180 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6181 } 6182 6183 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6184 xpt_print_path(lstate->path); 6185 printf("immediate event %x:%x lost\n", 6186 lstate->event_buffer[lstate->event_r_idx].event_type, 6187 lstate->event_buffer[lstate->event_r_idx].event_arg); 6188 lstate->event_r_idx++; 6189 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6190 lstate->event_r_idx = 0; 6191 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6192 } 6193 6194 event = &lstate->event_buffer[lstate->event_w_idx]; 6195 event->initiator_id = initiator_id; 6196 event->event_type = event_type; 6197 event->event_arg = event_arg; 6198 lstate->event_w_idx++; 6199 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6200 lstate->event_w_idx = 0; 6201 } 6202 6203 /* 6204 * Send any target mode events queued up waiting 6205 * for immediate notify resources. 6206 */ 6207 void 6208 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6209 { 6210 struct ccb_hdr *ccbh; 6211 struct ccb_immed_notify *inot; 6212 6213 while (lstate->event_r_idx != lstate->event_w_idx 6214 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6215 struct ahc_tmode_event *event; 6216 6217 event = &lstate->event_buffer[lstate->event_r_idx]; 6218 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6219 inot = (struct ccb_immed_notify *)ccbh; 6220 switch (event->event_type) { 6221 case EVENT_TYPE_BUS_RESET: 6222 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6223 break; 6224 default: 6225 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6226 inot->message_args[0] = event->event_type; 6227 inot->message_args[1] = event->event_arg; 6228 break; 6229 } 6230 inot->initiator_id = event->initiator_id; 6231 inot->sense_len = 0; 6232 xpt_done((union ccb *)inot); 6233 lstate->event_r_idx++; 6234 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6235 lstate->event_r_idx = 0; 6236 } 6237 } 6238 #endif 6239 6240 /******************** Sequencer Program Patching/Download *********************/ 6241 6242 #ifdef AHC_DUMP_SEQ 6243 void 6244 ahc_dumpseq(struct ahc_softc* ahc) 6245 { 6246 int i; 6247 int max_prog; 6248 6249 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 6250 max_prog = 448; 6251 else if ((ahc->features & AHC_ULTRA2) != 0) 6252 max_prog = 768; 6253 else 6254 max_prog = 512; 6255 6256 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6257 ahc_outb(ahc, SEQADDR0, 0); 6258 ahc_outb(ahc, SEQADDR1, 0); 6259 for (i = 0; i < max_prog; i++) { 6260 uint8_t ins_bytes[4]; 6261 6262 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6263 printf("0x%08x\n", ins_bytes[0] << 24 6264 | ins_bytes[1] << 16 6265 | ins_bytes[2] << 8 6266 | ins_bytes[3]); 6267 } 6268 } 6269 #endif 6270 6271 static void 6272 ahc_loadseq(struct ahc_softc *ahc) 6273 { 6274 struct cs cs_table[num_critical_sections]; 6275 u_int begin_set[num_critical_sections]; 6276 u_int end_set[num_critical_sections]; 6277 struct patch *cur_patch; 6278 u_int cs_count; 6279 u_int cur_cs; 6280 u_int i; 6281 int downloaded; 6282 u_int skip_addr; 6283 u_int sg_prefetch_cnt; 6284 uint8_t download_consts[7]; 6285 6286 /* 6287 * Start out with 0 critical sections 6288 * that apply to this firmware load. 6289 */ 6290 cs_count = 0; 6291 cur_cs = 0; 6292 memset(begin_set, 0, sizeof(begin_set)); 6293 memset(end_set, 0, sizeof(end_set)); 6294 6295 /* Setup downloadable constant table */ 6296 download_consts[QOUTFIFO_OFFSET] = 0; 6297 if (ahc->targetcmds != NULL) 6298 download_consts[QOUTFIFO_OFFSET] += 32; 6299 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6300 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6301 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6302 sg_prefetch_cnt = ahc->pci_cachesize; 6303 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6304 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6305 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6306 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6307 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6308 6309 cur_patch = patches; 6310 downloaded = 0; 6311 skip_addr = 0; 6312 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6313 ahc_outb(ahc, SEQADDR0, 0); 6314 ahc_outb(ahc, SEQADDR1, 0); 6315 6316 for (i = 0; i < sizeof(seqprog)/4; i++) { 6317 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6318 /* 6319 * Don't download this instruction as it 6320 * is in a patch that was removed. 6321 */ 6322 continue; 6323 } 6324 /* 6325 * Move through the CS table until we find a CS 6326 * that might apply to this instruction. 6327 */ 6328 for (; cur_cs < num_critical_sections; cur_cs++) { 6329 if (critical_sections[cur_cs].end <= i) { 6330 if (begin_set[cs_count] == TRUE 6331 && end_set[cs_count] == FALSE) { 6332 cs_table[cs_count].end = downloaded; 6333 end_set[cs_count] = TRUE; 6334 cs_count++; 6335 } 6336 continue; 6337 } 6338 if (critical_sections[cur_cs].begin <= i 6339 && begin_set[cs_count] == FALSE) { 6340 cs_table[cs_count].begin = downloaded; 6341 begin_set[cs_count] = TRUE; 6342 } 6343 break; 6344 } 6345 ahc_download_instr(ahc, i, download_consts); 6346 downloaded++; 6347 } 6348 6349 ahc->num_critical_sections = cs_count; 6350 if (cs_count != 0) { 6351 6352 cs_count *= sizeof(struct cs); 6353 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6354 if (ahc->critical_sections == NULL) 6355 panic("ahc_loadseq: Could not malloc"); 6356 memcpy(ahc->critical_sections, cs_table, cs_count); 6357 } 6358 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6359 ahc_restart(ahc); 6360 6361 if (bootverbose) { 6362 printf(" %d instructions downloaded\n", downloaded); 6363 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6364 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6365 } 6366 } 6367 6368 static int 6369 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6370 u_int start_instr, u_int *skip_addr) 6371 { 6372 struct patch *cur_patch; 6373 struct patch *last_patch; 6374 u_int num_patches; 6375 6376 num_patches = sizeof(patches)/sizeof(struct patch); 6377 last_patch = &patches[num_patches]; 6378 cur_patch = *start_patch; 6379 6380 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6381 6382 if (cur_patch->patch_func(ahc) == 0) { 6383 6384 /* Start rejecting code */ 6385 *skip_addr = start_instr + cur_patch->skip_instr; 6386 cur_patch += cur_patch->skip_patch; 6387 } else { 6388 /* Accepted this patch. Advance to the next 6389 * one and wait for our intruction pointer to 6390 * hit this point. 6391 */ 6392 cur_patch++; 6393 } 6394 } 6395 6396 *start_patch = cur_patch; 6397 if (start_instr < *skip_addr) 6398 /* Still skipping */ 6399 return (0); 6400 6401 return (1); 6402 } 6403 6404 static void 6405 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6406 { 6407 union ins_formats instr; 6408 struct ins_format1 *fmt1_ins; 6409 struct ins_format3 *fmt3_ins; 6410 u_int opcode; 6411 6412 /* 6413 * The firmware is always compiled into a little endian format. 6414 */ 6415 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6416 6417 fmt1_ins = &instr.format1; 6418 fmt3_ins = NULL; 6419 6420 /* Pull the opcode */ 6421 opcode = instr.format1.opcode; 6422 switch (opcode) { 6423 case AIC_OP_JMP: 6424 case AIC_OP_JC: 6425 case AIC_OP_JNC: 6426 case AIC_OP_CALL: 6427 case AIC_OP_JNE: 6428 case AIC_OP_JNZ: 6429 case AIC_OP_JE: 6430 case AIC_OP_JZ: 6431 { 6432 struct patch *cur_patch; 6433 int address_offset; 6434 u_int address; 6435 u_int skip_addr; 6436 u_int i; 6437 6438 fmt3_ins = &instr.format3; 6439 address_offset = 0; 6440 address = fmt3_ins->address; 6441 cur_patch = patches; 6442 skip_addr = 0; 6443 for (i = 0; i < address;) { 6444 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6445 6446 if (skip_addr > i) { 6447 int end_addr; 6448 6449 end_addr = MIN(address, skip_addr); 6450 address_offset += end_addr - i; 6451 i = skip_addr; 6452 } else { 6453 i++; 6454 } 6455 } 6456 address -= address_offset; 6457 fmt3_ins->address = address; 6458 /* FALLTHROUGH */ 6459 } 6460 case AIC_OP_OR: 6461 case AIC_OP_AND: 6462 case AIC_OP_XOR: 6463 case AIC_OP_ADD: 6464 case AIC_OP_ADC: 6465 case AIC_OP_BMOV: 6466 if (fmt1_ins->parity != 0) { 6467 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6468 } 6469 fmt1_ins->parity = 0; 6470 if ((ahc->features & AHC_CMD_CHAN) == 0 6471 && opcode == AIC_OP_BMOV) { 6472 /* 6473 * Block move was added at the same time 6474 * as the command channel. Verify that 6475 * this is only a move of a single element 6476 * and convert the BMOV to a MOV 6477 * (AND with an immediate of FF). 6478 */ 6479 if (fmt1_ins->immediate != 1) 6480 panic("%s: BMOV not supported\n", 6481 ahc_name(ahc)); 6482 fmt1_ins->opcode = AIC_OP_AND; 6483 fmt1_ins->immediate = 0xff; 6484 } 6485 /* FALLTHROUGH */ 6486 case AIC_OP_ROL: 6487 if ((ahc->features & AHC_ULTRA2) != 0) { 6488 int i, count; 6489 6490 /* Calculate odd parity for the instruction */ 6491 for (i = 0, count = 0; i < 31; i++) { 6492 uint32_t mask; 6493 6494 mask = 0x01 << i; 6495 if ((instr.integer & mask) != 0) 6496 count++; 6497 } 6498 if ((count & 0x01) == 0) 6499 instr.format1.parity = 1; 6500 } else { 6501 /* Compress the instruction for older sequencers */ 6502 if (fmt3_ins != NULL) { 6503 instr.integer = 6504 fmt3_ins->immediate 6505 | (fmt3_ins->source << 8) 6506 | (fmt3_ins->address << 16) 6507 | (fmt3_ins->opcode << 25); 6508 } else { 6509 instr.integer = 6510 fmt1_ins->immediate 6511 | (fmt1_ins->source << 8) 6512 | (fmt1_ins->destination << 16) 6513 | (fmt1_ins->ret << 24) 6514 | (fmt1_ins->opcode << 25); 6515 } 6516 } 6517 /* The sequencer is a little endian cpu */ 6518 instr.integer = ahc_htole32(instr.integer); 6519 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6520 break; 6521 default: 6522 panic("Unknown opcode encountered in seq program"); 6523 break; 6524 } 6525 } 6526 6527 int 6528 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6529 const char *name, u_int address, u_int value, 6530 u_int *cur_column, u_int wrap_point) 6531 { 6532 int printed; 6533 u_int printed_mask; 6534 char line[1024]; 6535 6536 line[0] = 0; 6537 6538 if (cur_column != NULL && *cur_column >= wrap_point) { 6539 printf("\n"); 6540 *cur_column = 0; 6541 } 6542 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 6543 if (table == NULL) { 6544 printed += snprintf(&line[printed], (sizeof line) - printed, 6545 " "); 6546 printf("%s", line); 6547 if (cur_column != NULL) 6548 *cur_column += printed; 6549 return (printed); 6550 } 6551 printed_mask = 0; 6552 while (printed_mask != 0xFF) { 6553 int entry; 6554 6555 for (entry = 0; entry < num_entries; entry++) { 6556 if (((value & table[entry].mask) 6557 != table[entry].value) 6558 || ((printed_mask & table[entry].mask) 6559 == table[entry].mask)) 6560 continue; 6561 printed += snprintf(&line[printed], 6562 (sizeof line) - printed, "%s%s", 6563 printed_mask == 0 ? ":(" : "|", 6564 table[entry].name); 6565 printed_mask |= table[entry].mask; 6566 6567 break; 6568 } 6569 if (entry >= num_entries) 6570 break; 6571 } 6572 if (printed_mask != 0) 6573 printed += snprintf(&line[printed], 6574 (sizeof line) - printed, ") "); 6575 else 6576 printed += snprintf(&line[printed], 6577 (sizeof line) - printed, " "); 6578 if (cur_column != NULL) 6579 *cur_column += printed; 6580 printf("%s", line); 6581 6582 return (printed); 6583 } 6584 6585 void 6586 ahc_dump_card_state(struct ahc_softc *ahc) 6587 { 6588 struct scb *scb; 6589 struct scb_tailq *untagged_q; 6590 u_int cur_col; 6591 int paused; 6592 int target; 6593 int maxtarget; 6594 int i; 6595 uint8_t last_phase; 6596 uint8_t qinpos; 6597 uint8_t qintail; 6598 uint8_t qoutpos; 6599 uint8_t scb_index; 6600 uint8_t saved_scbptr; 6601 6602 if (ahc_is_paused(ahc)) { 6603 paused = 1; 6604 } else { 6605 paused = 0; 6606 ahc_pause(ahc); 6607 } 6608 6609 saved_scbptr = ahc_inb(ahc, SCBPTR); 6610 last_phase = ahc_inb(ahc, LASTPHASE); 6611 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6612 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6613 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6614 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6615 if (paused) 6616 printf("Card was paused\n"); 6617 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6618 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6619 ahc_inb(ahc, ARG_2)); 6620 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6621 ahc_inb(ahc, SCBPTR)); 6622 cur_col = 0; 6623 if ((ahc->features & AHC_DT) != 0) 6624 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6625 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6626 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6627 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6628 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6629 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6630 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6631 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6632 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6633 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6634 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6635 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6636 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6637 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6638 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6639 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6640 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6641 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6642 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6643 if (cur_col != 0) 6644 printf("\n"); 6645 printf("STACK:"); 6646 for (i = 0; i < STACK_SIZE; i++) 6647 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6648 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6649 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6650 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6651 /* QINFIFO */ 6652 printf("QINFIFO entries: "); 6653 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6654 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6655 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6656 } else 6657 qinpos = ahc_inb(ahc, QINPOS); 6658 qintail = ahc->qinfifonext; 6659 while (qinpos != qintail) { 6660 printf("%d ", ahc->qinfifo[qinpos]); 6661 qinpos++; 6662 } 6663 printf("\n"); 6664 6665 printf("Waiting Queue entries: "); 6666 scb_index = ahc_inb(ahc, WAITING_SCBH); 6667 i = 0; 6668 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6669 ahc_outb(ahc, SCBPTR, scb_index); 6670 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6671 scb_index = ahc_inb(ahc, SCB_NEXT); 6672 } 6673 printf("\n"); 6674 6675 printf("Disconnected Queue entries: "); 6676 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6677 i = 0; 6678 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6679 ahc_outb(ahc, SCBPTR, scb_index); 6680 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6681 scb_index = ahc_inb(ahc, SCB_NEXT); 6682 } 6683 printf("\n"); 6684 6685 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6686 printf("QOUTFIFO entries: "); 6687 qoutpos = ahc->qoutfifonext; 6688 i = 0; 6689 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6690 printf("%d ", ahc->qoutfifo[qoutpos]); 6691 qoutpos++; 6692 } 6693 printf("\n"); 6694 6695 printf("Sequencer Free SCB List: "); 6696 scb_index = ahc_inb(ahc, FREE_SCBH); 6697 i = 0; 6698 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6699 ahc_outb(ahc, SCBPTR, scb_index); 6700 printf("%d ", scb_index); 6701 scb_index = ahc_inb(ahc, SCB_NEXT); 6702 } 6703 printf("\n"); 6704 6705 printf("Sequencer SCB Info: "); 6706 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6707 ahc_outb(ahc, SCBPTR, i); 6708 /*cur_col =*/ printf("\n%3d ", i); 6709 6710 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6711 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6712 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6713 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6714 } 6715 printf("\n"); 6716 6717 printf("Pending list: "); 6718 i = 0; 6719 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6720 if (i++ > 256) 6721 break; 6722 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6723 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6724 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6725 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6726 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6727 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6728 printf("("); 6729 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6730 &cur_col, 60); 6731 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6732 printf(")"); 6733 } 6734 } 6735 printf("\n"); 6736 6737 printf("Kernel Free SCB list: "); 6738 i = 0; 6739 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6740 if (i++ > 256) 6741 break; 6742 printf("%d ", scb->hscb->tag); 6743 } 6744 printf("\n"); 6745 6746 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6747 for (target = 0; target <= maxtarget; target++) { 6748 untagged_q = &ahc->untagged_queues[target]; 6749 if (TAILQ_FIRST(untagged_q) == NULL) 6750 continue; 6751 printf("Untagged Q(%d): ", target); 6752 i = 0; 6753 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6754 if (i++ > 256) 6755 break; 6756 printf("%d ", scb->hscb->tag); 6757 } 6758 printf("\n"); 6759 } 6760 6761 ahc_platform_dump_card_state(ahc); 6762 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6763 ahc_outb(ahc, SCBPTR, saved_scbptr); 6764 if (paused == 0) 6765 ahc_unpause(ahc); 6766 } 6767 6768 /************************* Target Mode ****************************************/ 6769 #ifdef AHC_TARGET_MODE 6770 cam_status 6771 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6772 struct ahc_tmode_tstate **tstate, 6773 struct ahc_tmode_lstate **lstate, 6774 int notfound_failure) 6775 { 6776 6777 if ((ahc->features & AHC_TARGETMODE) == 0) 6778 return (CAM_REQ_INVALID); 6779 6780 /* 6781 * Handle the 'black hole' device that sucks up 6782 * requests to unattached luns on enabled targets. 6783 */ 6784 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6785 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6786 *tstate = NULL; 6787 *lstate = ahc->black_hole; 6788 } else { 6789 u_int max_id; 6790 6791 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6792 if (ccb->ccb_h.target_id > max_id) 6793 return (CAM_TID_INVALID); 6794 6795 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6796 return (CAM_LUN_INVALID); 6797 6798 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6799 *lstate = NULL; 6800 if (*tstate != NULL) 6801 *lstate = 6802 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6803 } 6804 6805 if (notfound_failure != 0 && *lstate == NULL) 6806 return (CAM_PATH_INVALID); 6807 6808 return (CAM_REQ_CMP); 6809 } 6810 6811 void 6812 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6813 { 6814 struct ahc_tmode_tstate *tstate; 6815 struct ahc_tmode_lstate *lstate; 6816 struct ccb_en_lun *cel; 6817 cam_status status; 6818 u_int target; 6819 u_int lun; 6820 u_int target_mask; 6821 u_int our_id; 6822 u_long s; 6823 char channel; 6824 6825 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6826 /*notfound_failure*/FALSE); 6827 6828 if (status != CAM_REQ_CMP) { 6829 ccb->ccb_h.status = status; 6830 return; 6831 } 6832 6833 if (cam_sim_bus(sim) == 0) 6834 our_id = ahc->our_id; 6835 else 6836 our_id = ahc->our_id_b; 6837 6838 if (ccb->ccb_h.target_id != our_id) { 6839 /* 6840 * our_id represents our initiator ID, or 6841 * the ID of the first target to have an 6842 * enabled lun in target mode. There are 6843 * two cases that may preclude enabling a 6844 * target id other than our_id. 6845 * 6846 * o our_id is for an active initiator role. 6847 * Since the hardware does not support 6848 * reselections to the initiator role at 6849 * anything other than our_id, and our_id 6850 * is used by the hardware to indicate the 6851 * ID to use for both select-out and 6852 * reselect-out operations, the only target 6853 * ID we can support in this mode is our_id. 6854 * 6855 * o The MULTARGID feature is not available and 6856 * a previous target mode ID has been enabled. 6857 */ 6858 if ((ahc->features & AHC_MULTIROLE) != 0) { 6859 6860 if ((ahc->features & AHC_MULTI_TID) != 0 6861 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6862 /* 6863 * Only allow additional targets if 6864 * the initiator role is disabled. 6865 * The hardware cannot handle a re-select-in 6866 * on the initiator id during a re-select-out 6867 * on a different target id. 6868 */ 6869 status = CAM_TID_INVALID; 6870 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6871 || ahc->enabled_luns > 0) { 6872 /* 6873 * Only allow our target id to change 6874 * if the initiator role is not configured 6875 * and there are no enabled luns which 6876 * are attached to the currently registered 6877 * scsi id. 6878 */ 6879 status = CAM_TID_INVALID; 6880 } 6881 } else if ((ahc->features & AHC_MULTI_TID) == 0 6882 && ahc->enabled_luns > 0) { 6883 6884 status = CAM_TID_INVALID; 6885 } 6886 } 6887 6888 if (status != CAM_REQ_CMP) { 6889 ccb->ccb_h.status = status; 6890 return; 6891 } 6892 6893 /* 6894 * We now have an id that is valid. 6895 * If we aren't in target mode, switch modes. 6896 */ 6897 if ((ahc->flags & AHC_TARGETROLE) == 0 6898 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6899 u_long s; 6900 6901 printf("Configuring Target Mode\n"); 6902 ahc_lock(ahc, &s); 6903 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6904 ccb->ccb_h.status = CAM_BUSY; 6905 ahc_unlock(ahc, &s); 6906 return; 6907 } 6908 ahc->flags |= AHC_TARGETROLE; 6909 if ((ahc->features & AHC_MULTIROLE) == 0) 6910 ahc->flags &= ~AHC_INITIATORROLE; 6911 ahc_pause(ahc); 6912 ahc_loadseq(ahc); 6913 ahc_unlock(ahc, &s); 6914 } 6915 cel = &ccb->cel; 6916 target = ccb->ccb_h.target_id; 6917 lun = ccb->ccb_h.target_lun; 6918 channel = SIM_CHANNEL(ahc, sim); 6919 target_mask = 0x01 << target; 6920 if (channel == 'B') 6921 target_mask <<= 8; 6922 6923 if (cel->enable != 0) { 6924 u_int scsiseq; 6925 6926 /* Are we already enabled?? */ 6927 if (lstate != NULL) { 6928 xpt_print_path(ccb->ccb_h.path); 6929 printf("Lun already enabled\n"); 6930 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6931 return; 6932 } 6933 6934 if (cel->grp6_len != 0 6935 || cel->grp7_len != 0) { 6936 /* 6937 * Don't (yet?) support vendor 6938 * specific commands. 6939 */ 6940 ccb->ccb_h.status = CAM_REQ_INVALID; 6941 printf("Non-zero Group Codes\n"); 6942 return; 6943 } 6944 6945 /* 6946 * Seems to be okay. 6947 * Setup our data structures. 6948 */ 6949 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6950 tstate = ahc_alloc_tstate(ahc, target, channel); 6951 if (tstate == NULL) { 6952 xpt_print_path(ccb->ccb_h.path); 6953 printf("Couldn't allocate tstate\n"); 6954 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6955 return; 6956 } 6957 } 6958 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6959 if (lstate == NULL) { 6960 xpt_print_path(ccb->ccb_h.path); 6961 printf("Couldn't allocate lstate\n"); 6962 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6963 return; 6964 } 6965 memset(lstate, 0, sizeof(*lstate)); 6966 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6967 xpt_path_path_id(ccb->ccb_h.path), 6968 xpt_path_target_id(ccb->ccb_h.path), 6969 xpt_path_lun_id(ccb->ccb_h.path)); 6970 if (status != CAM_REQ_CMP) { 6971 free(lstate, M_DEVBUF); 6972 xpt_print_path(ccb->ccb_h.path); 6973 printf("Couldn't allocate path\n"); 6974 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6975 return; 6976 } 6977 SLIST_INIT(&lstate->accept_tios); 6978 SLIST_INIT(&lstate->immed_notifies); 6979 ahc_lock(ahc, &s); 6980 ahc_pause(ahc); 6981 if (target != CAM_TARGET_WILDCARD) { 6982 tstate->enabled_luns[lun] = lstate; 6983 ahc->enabled_luns++; 6984 6985 if ((ahc->features & AHC_MULTI_TID) != 0) { 6986 u_int targid_mask; 6987 6988 targid_mask = ahc_inb(ahc, TARGID) 6989 | (ahc_inb(ahc, TARGID + 1) << 8); 6990 6991 targid_mask |= target_mask; 6992 ahc_outb(ahc, TARGID, targid_mask); 6993 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6994 6995 ahc_update_scsiid(ahc, targid_mask); 6996 } else { 6997 u_int our_id; 6998 char channel; 6999 7000 channel = SIM_CHANNEL(ahc, sim); 7001 our_id = SIM_SCSI_ID(ahc, sim); 7002 7003 /* 7004 * This can only happen if selections 7005 * are not enabled 7006 */ 7007 if (target != our_id) { 7008 u_int sblkctl; 7009 char cur_channel; 7010 int swap; 7011 7012 sblkctl = ahc_inb(ahc, SBLKCTL); 7013 cur_channel = (sblkctl & SELBUSB) 7014 ? 'B' : 'A'; 7015 if ((ahc->features & AHC_TWIN) == 0) 7016 cur_channel = 'A'; 7017 swap = cur_channel != channel; 7018 if (channel == 'A') 7019 ahc->our_id = target; 7020 else 7021 ahc->our_id_b = target; 7022 7023 if (swap) 7024 ahc_outb(ahc, SBLKCTL, 7025 sblkctl ^ SELBUSB); 7026 7027 ahc_outb(ahc, SCSIID, target); 7028 7029 if (swap) 7030 ahc_outb(ahc, SBLKCTL, sblkctl); 7031 } 7032 } 7033 } else 7034 ahc->black_hole = lstate; 7035 /* Allow select-in operations */ 7036 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7037 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7038 scsiseq |= ENSELI; 7039 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7040 scsiseq = ahc_inb(ahc, SCSISEQ); 7041 scsiseq |= ENSELI; 7042 ahc_outb(ahc, SCSISEQ, scsiseq); 7043 } 7044 ahc_unpause(ahc); 7045 ahc_unlock(ahc, &s); 7046 ccb->ccb_h.status = CAM_REQ_CMP; 7047 xpt_print_path(ccb->ccb_h.path); 7048 printf("Lun now enabled for target mode\n"); 7049 } else { 7050 struct scb *scb; 7051 int i, empty; 7052 7053 if (lstate == NULL) { 7054 ccb->ccb_h.status = CAM_LUN_INVALID; 7055 return; 7056 } 7057 7058 ahc_lock(ahc, &s); 7059 7060 ccb->ccb_h.status = CAM_REQ_CMP; 7061 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7062 struct ccb_hdr *ccbh; 7063 7064 ccbh = &scb->io_ctx->ccb_h; 7065 if (ccbh->func_code == XPT_CONT_TARGET_IO 7066 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7067 printf("CTIO pending\n"); 7068 ccb->ccb_h.status = CAM_REQ_INVALID; 7069 ahc_unlock(ahc, &s); 7070 return; 7071 } 7072 } 7073 7074 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7075 printf("ATIOs pending\n"); 7076 ccb->ccb_h.status = CAM_REQ_INVALID; 7077 } 7078 7079 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7080 printf("INOTs pending\n"); 7081 ccb->ccb_h.status = CAM_REQ_INVALID; 7082 } 7083 7084 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7085 ahc_unlock(ahc, &s); 7086 return; 7087 } 7088 7089 xpt_print_path(ccb->ccb_h.path); 7090 printf("Target mode disabled\n"); 7091 xpt_free_path(lstate->path); 7092 free(lstate, M_DEVBUF); 7093 7094 ahc_pause(ahc); 7095 /* Can we clean up the target too? */ 7096 if (target != CAM_TARGET_WILDCARD) { 7097 tstate->enabled_luns[lun] = NULL; 7098 ahc->enabled_luns--; 7099 for (empty = 1, i = 0; i < 8; i++) 7100 if (tstate->enabled_luns[i] != NULL) { 7101 empty = 0; 7102 break; 7103 } 7104 7105 if (empty) { 7106 ahc_free_tstate(ahc, target, channel, 7107 /*force*/FALSE); 7108 if (ahc->features & AHC_MULTI_TID) { 7109 u_int targid_mask; 7110 7111 targid_mask = ahc_inb(ahc, TARGID) 7112 | (ahc_inb(ahc, TARGID + 1) 7113 << 8); 7114 7115 targid_mask &= ~target_mask; 7116 ahc_outb(ahc, TARGID, targid_mask); 7117 ahc_outb(ahc, TARGID+1, 7118 (targid_mask >> 8)); 7119 ahc_update_scsiid(ahc, targid_mask); 7120 } 7121 } 7122 } else { 7123 7124 ahc->black_hole = NULL; 7125 7126 /* 7127 * We can't allow selections without 7128 * our black hole device. 7129 */ 7130 empty = TRUE; 7131 } 7132 if (ahc->enabled_luns == 0) { 7133 /* Disallow select-in */ 7134 u_int scsiseq; 7135 7136 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7137 scsiseq &= ~ENSELI; 7138 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7139 scsiseq = ahc_inb(ahc, SCSISEQ); 7140 scsiseq &= ~ENSELI; 7141 ahc_outb(ahc, SCSISEQ, scsiseq); 7142 7143 if ((ahc->features & AHC_MULTIROLE) == 0) { 7144 printf("Configuring Initiator Mode\n"); 7145 ahc->flags &= ~AHC_TARGETROLE; 7146 ahc->flags |= AHC_INITIATORROLE; 7147 ahc_pause(ahc); 7148 ahc_loadseq(ahc); 7149 } 7150 } 7151 ahc_unpause(ahc); 7152 ahc_unlock(ahc, &s); 7153 } 7154 } 7155 7156 static void 7157 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7158 { 7159 u_int scsiid_mask; 7160 u_int scsiid; 7161 7162 if ((ahc->features & AHC_MULTI_TID) == 0) 7163 panic("ahc_update_scsiid called on non-multitid unit\n"); 7164 7165 /* 7166 * Since we will rely on the TARGID mask 7167 * for selection enables, ensure that OID 7168 * in SCSIID is not set to some other ID 7169 * that we don't want to allow selections on. 7170 */ 7171 if ((ahc->features & AHC_ULTRA2) != 0) 7172 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7173 else 7174 scsiid = ahc_inb(ahc, SCSIID); 7175 scsiid_mask = 0x1 << (scsiid & OID); 7176 if ((targid_mask & scsiid_mask) == 0) { 7177 u_int our_id; 7178 7179 /* ffs counts from 1 */ 7180 our_id = ffs(targid_mask); 7181 if (our_id == 0) 7182 our_id = ahc->our_id; 7183 else 7184 our_id--; 7185 scsiid &= TID; 7186 scsiid |= our_id; 7187 } 7188 if ((ahc->features & AHC_ULTRA2) != 0) 7189 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7190 else 7191 ahc_outb(ahc, SCSIID, scsiid); 7192 } 7193 7194 void 7195 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7196 { 7197 struct target_cmd *cmd; 7198 7199 /* 7200 * If the card supports auto-access pause, 7201 * we can access the card directly regardless 7202 * of whether it is paused or not. 7203 */ 7204 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7205 paused = TRUE; 7206 7207 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7208 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7209 7210 /* 7211 * Only advance through the queue if we 7212 * have the resources to process the command. 7213 */ 7214 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7215 break; 7216 7217 cmd->cmd_valid = 0; 7218 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7219 ahc->shared_data_dmamap, 7220 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7221 sizeof(struct target_cmd), 7222 BUS_DMASYNC_PREREAD); 7223 ahc->tqinfifonext++; 7224 7225 /* 7226 * Lazily update our position in the target mode incoming 7227 * command queue as seen by the sequencer. 7228 */ 7229 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7230 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7231 u_int hs_mailbox; 7232 7233 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7234 hs_mailbox &= ~HOST_TQINPOS; 7235 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7236 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7237 } else { 7238 if (!paused) 7239 ahc_pause(ahc); 7240 ahc_outb(ahc, KERNEL_TQINPOS, 7241 ahc->tqinfifonext & HOST_TQINPOS); 7242 if (!paused) 7243 ahc_unpause(ahc); 7244 } 7245 } 7246 } 7247 } 7248 7249 static int 7250 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7251 { 7252 struct ahc_tmode_tstate *tstate; 7253 struct ahc_tmode_lstate *lstate; 7254 struct ccb_accept_tio *atio; 7255 uint8_t *byte; 7256 int initiator; 7257 int target; 7258 int lun; 7259 7260 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7261 target = SCSIID_OUR_ID(cmd->scsiid); 7262 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7263 7264 byte = cmd->bytes; 7265 tstate = ahc->enabled_targets[target]; 7266 lstate = NULL; 7267 if (tstate != NULL) 7268 lstate = tstate->enabled_luns[lun]; 7269 7270 /* 7271 * Commands for disabled luns go to the black hole driver. 7272 */ 7273 if (lstate == NULL) 7274 lstate = ahc->black_hole; 7275 7276 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7277 if (atio == NULL) { 7278 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7279 /* 7280 * Wait for more ATIOs from the peripheral driver for this lun. 7281 */ 7282 if (bootverbose) 7283 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7284 return (1); 7285 } else 7286 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7287 #if 0 7288 printf("Incoming command from %d for %d:%d%s\n", 7289 initiator, target, lun, 7290 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7291 #endif 7292 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7293 7294 if (lstate == ahc->black_hole) { 7295 /* Fill in the wildcards */ 7296 atio->ccb_h.target_id = target; 7297 atio->ccb_h.target_lun = lun; 7298 } 7299 7300 /* 7301 * Package it up and send it off to 7302 * whomever has this lun enabled. 7303 */ 7304 atio->sense_len = 0; 7305 atio->init_id = initiator; 7306 if (byte[0] != 0xFF) { 7307 /* Tag was included */ 7308 atio->tag_action = *byte++; 7309 atio->tag_id = *byte++; 7310 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7311 } else { 7312 atio->ccb_h.flags = 0; 7313 } 7314 byte++; 7315 7316 /* Okay. Now determine the cdb size based on the command code */ 7317 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7318 case 0: 7319 atio->cdb_len = 6; 7320 break; 7321 case 1: 7322 case 2: 7323 atio->cdb_len = 10; 7324 break; 7325 case 4: 7326 atio->cdb_len = 16; 7327 break; 7328 case 5: 7329 atio->cdb_len = 12; 7330 break; 7331 case 3: 7332 default: 7333 /* Only copy the opcode. */ 7334 atio->cdb_len = 1; 7335 printf("Reserved or VU command code type encountered\n"); 7336 break; 7337 } 7338 7339 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7340 7341 atio->ccb_h.status |= CAM_CDB_RECVD; 7342 7343 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7344 /* 7345 * We weren't allowed to disconnect. 7346 * We're hanging on the bus until a 7347 * continue target I/O comes in response 7348 * to this accept tio. 7349 */ 7350 #if 0 7351 printf("Received Immediate Command %d:%d:%d - %p\n", 7352 initiator, target, lun, ahc->pending_device); 7353 #endif 7354 ahc->pending_device = lstate; 7355 ahc_freeze_ccb((union ccb *)atio); 7356 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7357 } 7358 xpt_done((union ccb*)atio); 7359 return (0); 7360 } 7361 #endif 7362 7363 static int 7364 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 7365 bus_dma_tag_t tag; 7366 int size; 7367 int flags; 7368 bus_dmamap_t *mapp; 7369 caddr_t *vaddr; 7370 bus_addr_t *baddr; 7371 bus_dma_segment_t *seg; 7372 int *nseg; 7373 const char *myname, *what; 7374 { 7375 int error, level = 0; 7376 7377 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7378 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7379 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7380 myname, what, error); 7381 goto out; 7382 } 7383 level++; 7384 7385 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7386 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7387 printf("%s: failed to map DMA mem for %s, error = %d\n", 7388 myname, what, error); 7389 goto out; 7390 } 7391 level++; 7392 7393 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7394 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7395 printf("%s: failed to create DMA map for %s, error = %d\n", 7396 myname, what, error); 7397 goto out; 7398 } 7399 level++; 7400 7401 7402 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7403 BUS_DMA_NOWAIT)) != 0) { 7404 printf("%s: failed to load DMA map for %s, error = %d\n", 7405 myname, what, error); 7406 goto out; 7407 } 7408 7409 *baddr = (*mapp)->dm_segs[0].ds_addr; 7410 7411 return 0; 7412 out: 7413 printf("ahc_createdmamem error (%d)\n", level); 7414 switch (level) { 7415 case 3: 7416 bus_dmamap_destroy(tag, *mapp); 7417 /* FALLTHROUGH */ 7418 case 2: 7419 bus_dmamem_unmap(tag, *vaddr, size); 7420 /* FALLTHROUGH */ 7421 case 1: 7422 bus_dmamem_free(tag, seg, *nseg); 7423 break; 7424 default: 7425 break; 7426 } 7427 7428 return error; 7429 } 7430 7431 static void 7432 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 7433 bus_dma_tag_t tag; 7434 int size; 7435 bus_dmamap_t map; 7436 caddr_t vaddr; 7437 bus_dma_segment_t *seg; 7438 int nseg; 7439 { 7440 7441 bus_dmamap_unload(tag, map); 7442 bus_dmamap_destroy(tag, map); 7443 bus_dmamem_unmap(tag, vaddr, size); 7444 bus_dmamem_free(tag, seg, nseg); 7445 } 7446
Indexes created Wed Oct 01 15:09:59 GMT 2025