aic7xxx.c revision 1.106
1 /* $NetBSD: aic7xxx.c,v 1.106 2003/07/14 15:47:06 lukem Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: aic7xxx.c,v 1.106 2003/07/14 15:47:06 lukem Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.106 2003/07/14 15:47:06 lukem Exp $"); 54 55 #include <dev/ic/aic7xxx_osm.h> 56 #include <dev/ic/aic7xxx_inline.h> 57 #include <dev/ic/aic7xxx_cam.h> 58 59 /****************************** Softc Data ************************************/ 60 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 61 62 /***************************** Lookup Tables **********************************/ 63 char *ahc_chip_names[] = 64 { 65 "NONE", 66 "aic7770", 67 "aic7850", 68 "aic7855", 69 "aic7859", 70 "aic7860", 71 "aic7870", 72 "aic7880", 73 "aic7895", 74 "aic7895C", 75 "aic7890/91", 76 "aic7896/97", 77 "aic7892", 78 "aic7899" 79 }; 80 81 /* 82 * Hardware error codes. 83 */ 84 struct ahc_hard_error_entry { 85 uint8_t errno; 86 char *errmesg; 87 }; 88 89 static struct ahc_hard_error_entry ahc_hard_errors[] = { 90 { ILLHADDR, "Illegal Host Access" }, 91 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 92 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 93 { SQPARERR, "Sequencer Parity Error" }, 94 { DPARERR, "Data-path Parity Error" }, 95 { MPARERR, "Scratch or SCB Memory Parity Error" }, 96 { PCIERRSTAT, "PCI Error detected" }, 97 { CIOPARERR, "CIOBUS Parity Error" }, 98 }; 99 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 100 101 static struct ahc_phase_table_entry ahc_phase_table[] = 102 { 103 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 104 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 105 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 106 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 107 { P_COMMAND, MSG_NOOP, "in Command phase" }, 108 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 109 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 110 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 111 { P_BUSFREE, MSG_NOOP, "while idle" }, 112 { 0, MSG_NOOP, "in unknown phase" } 113 }; 114 115 /* 116 * In most cases we only wish to itterate over real phases, so 117 * exclude the last element from the count. 118 */ 119 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 120 121 /* 122 * Valid SCSIRATE values. (p. 3-17) 123 * Provides a mapping of tranfer periods in ns to the proper value to 124 * stick in the scsixfer reg. 125 */ 126 static struct ahc_syncrate ahc_syncrates[] = 127 { 128 /* ultra2 fast/ultra period rate */ 129 { 0x42, 0x000, 9, "80.0" }, 130 { 0x03, 0x000, 10, "40.0" }, 131 { 0x04, 0x000, 11, "33.0" }, 132 { 0x05, 0x100, 12, "20.0" }, 133 { 0x06, 0x110, 15, "16.0" }, 134 { 0x07, 0x120, 18, "13.4" }, 135 { 0x08, 0x000, 25, "10.0" }, 136 { 0x19, 0x010, 31, "8.0" }, 137 { 0x1a, 0x020, 37, "6.67" }, 138 { 0x1b, 0x030, 43, "5.7" }, 139 { 0x1c, 0x040, 50, "5.0" }, 140 { 0x00, 0x050, 56, "4.4" }, 141 { 0x00, 0x060, 62, "4.0" }, 142 { 0x00, 0x070, 68, "3.6" }, 143 { 0x00, 0x000, 0, NULL } 144 }; 145 146 /* Our Sequencer Program */ 147 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 148 149 /**************************** Function Declarations ***************************/ 150 static void ahc_force_renegotiation(struct ahc_softc *ahc); 151 static struct ahc_tmode_tstate* 152 ahc_alloc_tstate(struct ahc_softc *ahc, 153 u_int scsi_id, char channel); 154 #ifdef AHC_TARGET_MODE 155 static void ahc_free_tstate(struct ahc_softc *ahc, 156 u_int scsi_id, char channel, int force); 157 #endif 158 static struct ahc_syncrate* 159 ahc_devlimited_syncrate(struct ahc_softc *ahc, 160 struct ahc_initiator_tinfo *, 161 u_int *period, 162 u_int *ppr_options, 163 role_t role); 164 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 165 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo); 167 static void ahc_scb_devinfo(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo, 169 struct scb *scb); 170 static void ahc_assert_atn(struct ahc_softc *ahc); 171 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 172 struct ahc_devinfo *devinfo, 173 struct scb *scb); 174 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo); 176 static void ahc_construct_sdtr(struct ahc_softc *ahc, 177 struct ahc_devinfo *devinfo, 178 u_int period, u_int offset); 179 static void ahc_construct_wdtr(struct ahc_softc *ahc, 180 struct ahc_devinfo *devinfo, 181 u_int bus_width); 182 static void ahc_construct_ppr(struct ahc_softc *ahc, 183 struct ahc_devinfo *devinfo, 184 u_int period, u_int offset, 185 u_int bus_width, u_int ppr_options); 186 static void ahc_clear_msg_state(struct ahc_softc *ahc); 187 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 188 static void ahc_handle_message_phase(struct ahc_softc *ahc); 189 typedef enum { 190 AHCMSG_1B, 191 AHCMSG_2B, 192 AHCMSG_EXT 193 } ahc_msgtype; 194 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 195 u_int msgval, int full); 196 static int ahc_parse_msg(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 201 struct ahc_devinfo *devinfo); 202 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 203 static void ahc_handle_devreset(struct ahc_softc *ahc, 204 struct ahc_devinfo *devinfo, 205 cam_status status, char *message, 206 int verbose_level); 207 #if AHC_TARGET_MODE 208 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 209 struct ahc_devinfo *devinfo, 210 struct scb *scb); 211 #endif 212 213 //static bus_dmamap_callback_t ahc_dmamap_cb; 214 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 215 static int ahc_init_scbdata(struct ahc_softc *ahc); 216 static void ahc_fini_scbdata(struct ahc_softc *ahc); 217 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 218 struct scb *prev_scb, 219 struct scb *scb); 220 static int ahc_qinfifo_count(struct ahc_softc *ahc); 221 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 222 u_int prev, u_int scbptr); 223 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 224 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 225 u_int scbpos, u_int prev); 226 static void ahc_reset_current_bus(struct ahc_softc *ahc); 227 #ifdef AHC_DUMP_SEQ 228 static void ahc_dumpseq(struct ahc_softc *ahc); 229 #endif 230 static void ahc_loadseq(struct ahc_softc *ahc); 231 static int ahc_check_patch(struct ahc_softc *ahc, 232 struct patch **start_patch, 233 u_int start_instr, u_int *skip_addr); 234 static void ahc_download_instr(struct ahc_softc *ahc, 235 u_int instrptr, uint8_t *dconsts); 236 #ifdef AHC_TARGET_MODE 237 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 238 struct ahc_tmode_lstate *lstate, 239 u_int initiator_id, 240 u_int event_type, 241 u_int event_arg); 242 static void ahc_update_scsiid(struct ahc_softc *ahc, 243 u_int targid_mask); 244 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 245 struct target_cmd *cmd); 246 #endif 247 248 /************************** Added for porting to NetBSD ***********************/ 249 static int ahc_createdmamem(bus_dma_tag_t tag, 250 int size, 251 int flags, 252 bus_dmamap_t *mapp, 253 caddr_t *vaddr, 254 bus_addr_t *baddr, 255 bus_dma_segment_t *seg, 256 int *nseg, 257 const char *myname, const char *what); 258 static void ahc_freedmamem(bus_dma_tag_t tag, 259 int size, 260 bus_dmamap_t map, 261 caddr_t vaddr, 262 bus_dma_segment_t *seg, 263 int nseg); 264 265 /************************* Sequencer Execution Control ************************/ 266 /* 267 * Restart the sequencer program from address zero 268 */ 269 void 270 ahc_restart(struct ahc_softc *ahc) 271 { 272 273 ahc_pause(ahc); 274 275 /* No more pending messages. */ 276 ahc_clear_msg_state(ahc); 277 278 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 279 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 280 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 281 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 282 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 283 ahc_outb(ahc, SAVED_LUN, 0xFF); 284 285 /* 286 * Ensure that the sequencer's idea of TQINPOS 287 * matches our own. The sequencer increments TQINPOS 288 * only after it sees a DMA complete and a reset could 289 * occur before the increment leaving the kernel to believe 290 * the command arrived but the sequencer to not. 291 */ 292 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 293 294 /* Always allow reselection */ 295 ahc_outb(ahc, SCSISEQ, 296 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 297 if ((ahc->features & AHC_CMD_CHAN) != 0) { 298 /* Ensure that no DMA operations are in progress */ 299 ahc_outb(ahc, CCSCBCNT, 0); 300 ahc_outb(ahc, CCSGCTL, 0); 301 ahc_outb(ahc, CCSCBCTL, 0); 302 } 303 /* 304 * If we were in the process of DMA'ing SCB data into 305 * an SCB, replace that SCB on the free list. This prevents 306 * an SCB leak. 307 */ 308 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 309 ahc_add_curscb_to_free_list(ahc); 310 ahc_outb(ahc, SEQ_FLAGS2, 311 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 312 } 313 ahc_outb(ahc, MWI_RESIDUAL, 0); 314 ahc_outb(ahc, SEQCTL, FASTMODE); 315 ahc_outb(ahc, SEQADDR0, 0); 316 ahc_outb(ahc, SEQADDR1, 0); 317 ahc_unpause(ahc); 318 } 319 320 /************************* Input/Output Queues ********************************/ 321 void 322 ahc_run_qoutfifo(struct ahc_softc *ahc) 323 { 324 struct scb *scb; 325 u_int scb_index; 326 327 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 328 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 329 330 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 331 if ((ahc->qoutfifonext & 0x03) == 0x03) { 332 u_int modnext; 333 334 /* 335 * Clear 32bits of QOUTFIFO at a time 336 * so that we don't clobber an incoming 337 * byte DMA to the array on architectures 338 * that only support 32bit load and store 339 * operations. 340 */ 341 modnext = ahc->qoutfifonext & ~0x3; 342 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 343 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 344 ahc->shared_data_dmamap, 345 /*offset*/modnext, /*len*/4, 346 BUS_DMASYNC_PREREAD); 347 } 348 ahc->qoutfifonext++; 349 350 scb = ahc_lookup_scb(ahc, scb_index); 351 if (scb == NULL) { 352 printf("%s: WARNING no command for scb %d " 353 "(cmdcmplt)\nQOUTPOS = %d\n", 354 ahc_name(ahc), scb_index, 355 (ahc->qoutfifonext - 1) & 0xFF); 356 continue; 357 } 358 359 /* 360 * Save off the residual 361 * if there is one. 362 */ 363 ahc_update_residual(ahc, scb); 364 ahc_done(ahc, scb); 365 } 366 } 367 368 void 369 ahc_run_untagged_queues(struct ahc_softc *ahc) 370 { 371 int i; 372 373 for (i = 0; i < 16; i++) 374 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 375 } 376 377 void 378 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 379 { 380 struct scb *scb; 381 382 if (ahc->untagged_queue_lock != 0) 383 return; 384 385 if ((scb = TAILQ_FIRST(queue)) != NULL 386 && (scb->flags & SCB_ACTIVE) == 0) { 387 scb->flags |= SCB_ACTIVE; 388 ahc_queue_scb(ahc, scb); 389 } 390 } 391 392 /************************* Interrupt Handling *********************************/ 393 void 394 ahc_handle_brkadrint(struct ahc_softc *ahc) 395 { 396 /* 397 * We upset the sequencer :-( 398 * Lookup the error message 399 */ 400 int i; 401 int error; 402 403 error = ahc_inb(ahc, ERROR); 404 for (i = 0; error != 1 && i < num_errors; i++) 405 error >>= 1; 406 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 407 ahc_name(ahc), ahc_hard_errors[i].errmesg, 408 ahc_inb(ahc, SEQADDR0) | 409 (ahc_inb(ahc, SEQADDR1) << 8)); 410 411 ahc_dump_card_state(ahc); 412 413 /* Tell everyone that this HBA is no longer availible */ 414 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 415 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 416 CAM_NO_HBA); 417 418 /* Disable all interrupt sources by resetting the controller */ 419 ahc_shutdown(ahc); 420 } 421 422 void 423 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 424 { 425 struct scb *scb; 426 struct ahc_devinfo devinfo; 427 428 ahc_fetch_devinfo(ahc, &devinfo); 429 430 /* 431 * Clear the upper byte that holds SEQINT status 432 * codes and clear the SEQINT bit. We will unpause 433 * the sequencer, if appropriate, after servicing 434 * the request. 435 */ 436 ahc_outb(ahc, CLRINT, CLRSEQINT); 437 switch (intstat & SEQINT_MASK) { 438 case BAD_STATUS: 439 { 440 u_int scb_index; 441 struct hardware_scb *hscb; 442 443 /* 444 * Set the default return value to 0 (don't 445 * send sense). The sense code will change 446 * this if needed. 447 */ 448 ahc_outb(ahc, RETURN_1, 0); 449 450 /* 451 * The sequencer will notify us when a command 452 * has an error that would be of interest to 453 * the kernel. This allows us to leave the sequencer 454 * running in the common case of command completes 455 * without error. The sequencer will already have 456 * DMA'd the SCB back up to us, so we can reference 457 * the in kernel copy directly. 458 */ 459 scb_index = ahc_inb(ahc, SCB_TAG); 460 scb = ahc_lookup_scb(ahc, scb_index); 461 if (scb == NULL) { 462 ahc_print_devinfo(ahc, &devinfo); 463 printf("ahc_intr - referenced scb " 464 "not valid during seqint 0x%x scb(%d)\n", 465 intstat, scb_index); 466 ahc_dump_card_state(ahc); 467 panic("for safety"); 468 goto unpause; 469 } 470 471 hscb = scb->hscb; 472 473 /* Don't want to clobber the original sense code */ 474 if ((scb->flags & SCB_SENSE) != 0) { 475 /* 476 * Clear the SCB_SENSE Flag and have 477 * the sequencer do a normal command 478 * complete. 479 */ 480 scb->flags &= ~SCB_SENSE; 481 break; 482 } 483 /* Freeze the queue until the client sees the error. */ 484 ahc_freeze_devq(ahc, scb); 485 ahc_freeze_scb(scb); 486 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 487 switch (hscb->shared_data.status.scsi_status) { 488 case SCSI_STATUS_OK: 489 printf("%s: Interrupted for status of 0 (?)\n", 490 ahc_name(ahc)); 491 break; 492 case SCSI_STATUS_CMD_TERMINATED: 493 case SCSI_STATUS_CHECK_COND: 494 { 495 struct ahc_dma_seg *sg; 496 struct scsipi_sense *sc; 497 struct ahc_initiator_tinfo *targ_info; 498 struct ahc_tmode_tstate *tstate; 499 struct ahc_transinfo *tinfo; 500 #ifdef AHC_DEBUG 501 if (ahc_debug & AHC_SHOW_SENSE) { 502 ahc_print_path(ahc, scb); 503 printf("SCB %d: requests Check Status\n", 504 scb->hscb->tag); 505 } 506 #endif 507 508 if (ahc_perform_autosense(scb) == 0) 509 break; 510 511 targ_info = ahc_fetch_transinfo(ahc, 512 devinfo.channel, 513 devinfo.our_scsiid, 514 devinfo.target, 515 &tstate); 516 tinfo = &targ_info->curr; 517 sg = scb->sg_list; 518 sc = (struct scsipi_sense *)(&hscb->shared_data.cdb); 519 /* 520 * Save off the residual if there is one. 521 */ 522 ahc_update_residual(ahc, scb); 523 #ifdef AHC_DEBUG 524 if (ahc_debug & AHC_SHOW_SENSE) { 525 ahc_print_path(ahc, scb); 526 printf("Sending Sense\n"); 527 } 528 #endif 529 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 530 sg->len = ahc_get_sense_bufsize(ahc, scb); 531 sg->len |= AHC_DMA_LAST_SEG; 532 533 /* Fixup byte order */ 534 sg->addr = ahc_htole32(sg->addr); 535 sg->len = ahc_htole32(sg->len); 536 537 sc->opcode = REQUEST_SENSE; 538 sc->byte2 = 0; 539 if (tinfo->protocol_version <= SCSI_REV_2 540 && SCB_GET_LUN(scb) < 8) 541 sc->byte2 = SCB_GET_LUN(scb) << 5; 542 sc->unused[0] = 0; 543 sc->unused[1] = 0; 544 sc->length = sg->len; 545 sc->control = 0; 546 547 /* 548 * We can't allow the target to disconnect. 549 * This will be an untagged transaction and 550 * having the target disconnect will make this 551 * transaction indestinguishable from outstanding 552 * tagged transactions. 553 */ 554 hscb->control = 0; 555 556 /* 557 * This request sense could be because the 558 * the device lost power or in some other 559 * way has lost our transfer negotiations. 560 * Renegotiate if appropriate. Unit attention 561 * errors will be reported before any data 562 * phases occur. 563 */ 564 if (ahc_get_residual(scb) 565 == ahc_get_transfer_length(scb)) { 566 ahc_update_neg_request(ahc, &devinfo, 567 tstate, targ_info, 568 AHC_NEG_IF_NON_ASYNC); 569 } 570 if (tstate->auto_negotiate & devinfo.target_mask) { 571 hscb->control |= MK_MESSAGE; 572 scb->flags &= ~SCB_NEGOTIATE; 573 scb->flags |= SCB_AUTO_NEGOTIATE; 574 } 575 hscb->cdb_len = sizeof(*sc); 576 hscb->dataptr = sg->addr; 577 hscb->datacnt = sg->len; 578 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 579 hscb->sgptr = ahc_htole32(hscb->sgptr); 580 scb->sg_count = 1; 581 scb->flags |= SCB_SENSE; 582 ahc_qinfifo_requeue_tail(ahc, scb); 583 ahc_outb(ahc, RETURN_1, SEND_SENSE); 584 /* 585 * Ensure we have enough time to actually 586 * retrieve the sense. 587 */ 588 ahc_scb_timer_reset(scb, 5 * 1000000); 589 break; 590 } 591 default: 592 break; 593 } 594 break; 595 } 596 case NO_MATCH: 597 { 598 /* Ensure we don't leave the selection hardware on */ 599 ahc_outb(ahc, SCSISEQ, 600 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 601 602 printf("%s:%c:%d: no active SCB for reconnecting " 603 "target - issuing BUS DEVICE RESET\n", 604 ahc_name(ahc), devinfo.channel, devinfo.target); 605 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 606 "ARG_1 == 0x%x ACCUM = 0x%x\n", 607 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 608 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 609 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 610 "SINDEX == 0x%x\n", 611 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 612 ahc_index_busy_tcl(ahc, 613 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 614 ahc_inb(ahc, SAVED_LUN))), 615 ahc_inb(ahc, SINDEX)); 616 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 617 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 618 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 619 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 620 ahc_inb(ahc, SCB_CONTROL)); 621 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 622 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 623 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 624 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 625 ahc_dump_card_state(ahc); 626 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 627 ahc->msgout_len = 1; 628 ahc->msgout_index = 0; 629 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 630 ahc_outb(ahc, MSG_OUT, HOST_MSG); 631 ahc_assert_atn(ahc); 632 break; 633 } 634 case SEND_REJECT: 635 { 636 u_int rejbyte = ahc_inb(ahc, ACCUM); 637 printf("%s:%c:%d: Warning - unknown message received from " 638 "target (0x%x). Rejecting\n", 639 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 640 break; 641 } 642 case PROTO_VIOLATION: 643 { 644 ahc_handle_proto_violation(ahc); 645 break; 646 } 647 case IGN_WIDE_RES: 648 ahc_handle_ign_wide_residue(ahc, &devinfo); 649 break; 650 case PDATA_REINIT: 651 ahc_reinitialize_dataptrs(ahc); 652 break; 653 case BAD_PHASE: 654 { 655 u_int lastphase; 656 657 lastphase = ahc_inb(ahc, LASTPHASE); 658 printf("%s:%c:%d: unknown scsi bus phase %x, " 659 "lastphase = 0x%x. Attempting to continue\n", 660 ahc_name(ahc), devinfo.channel, devinfo.target, 661 lastphase, ahc_inb(ahc, SCSISIGI)); 662 break; 663 } 664 case MISSED_BUSFREE: 665 { 666 u_int lastphase; 667 668 lastphase = ahc_inb(ahc, LASTPHASE); 669 printf("%s:%c:%d: Missed busfree. " 670 "Lastphase = 0x%x, Curphase = 0x%x\n", 671 ahc_name(ahc), devinfo.channel, devinfo.target, 672 lastphase, ahc_inb(ahc, SCSISIGI)); 673 ahc_restart(ahc); 674 return; 675 } 676 case HOST_MSG_LOOP: 677 { 678 /* 679 * The sequencer has encountered a message phase 680 * that requires host assistance for completion. 681 * While handling the message phase(s), we will be 682 * notified by the sequencer after each byte is 683 * transfered so we can track bus phase changes. 684 * 685 * If this is the first time we've seen a HOST_MSG_LOOP 686 * interrupt, initialize the state of the host message 687 * loop. 688 */ 689 if (ahc->msg_type == MSG_TYPE_NONE) { 690 struct scb *scb; 691 u_int scb_index; 692 u_int bus_phase; 693 694 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 695 if (bus_phase != P_MESGIN 696 && bus_phase != P_MESGOUT) { 697 printf("ahc_intr: HOST_MSG_LOOP bad " 698 "phase 0x%x\n", 699 bus_phase); 700 /* 701 * Probably transitioned to bus free before 702 * we got here. Just punt the message. 703 */ 704 ahc_clear_intstat(ahc); 705 ahc_restart(ahc); 706 return; 707 } 708 709 scb_index = ahc_inb(ahc, SCB_TAG); 710 scb = ahc_lookup_scb(ahc, scb_index); 711 if (devinfo.role == ROLE_INITIATOR) { 712 if (scb == NULL) 713 panic("HOST_MSG_LOOP with " 714 "invalid SCB %x\n", scb_index); 715 716 if (bus_phase == P_MESGOUT) 717 ahc_setup_initiator_msgout(ahc, 718 &devinfo, 719 scb); 720 else { 721 ahc->msg_type = 722 MSG_TYPE_INITIATOR_MSGIN; 723 ahc->msgin_index = 0; 724 } 725 } 726 #if AHC_TARGET_MODE 727 else { 728 if (bus_phase == P_MESGOUT) { 729 ahc->msg_type = 730 MSG_TYPE_TARGET_MSGOUT; 731 ahc->msgin_index = 0; 732 } 733 else 734 ahc_setup_target_msgin(ahc, 735 &devinfo, 736 scb); 737 } 738 #endif 739 } 740 741 ahc_handle_message_phase(ahc); 742 break; 743 } 744 case PERR_DETECTED: 745 { 746 /* 747 * If we've cleared the parity error interrupt 748 * but the sequencer still believes that SCSIPERR 749 * is true, it must be that the parity error is 750 * for the currently presented byte on the bus, 751 * and we are not in a phase (data-in) where we will 752 * eventually ack this byte. Ack the byte and 753 * throw it away in the hope that the target will 754 * take us to message out to deliver the appropriate 755 * error message. 756 */ 757 if ((intstat & SCSIINT) == 0 758 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 759 760 if ((ahc->features & AHC_DT) == 0) { 761 u_int curphase; 762 763 /* 764 * The hardware will only let you ack bytes 765 * if the expected phase in SCSISIGO matches 766 * the current phase. Make sure this is 767 * currently the case. 768 */ 769 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 770 ahc_outb(ahc, LASTPHASE, curphase); 771 ahc_outb(ahc, SCSISIGO, curphase); 772 } 773 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 774 int wait; 775 776 /* 777 * In a data phase. Faster to bitbucket 778 * the data than to individually ack each 779 * byte. This is also the only strategy 780 * that will work with AUTOACK enabled. 781 */ 782 ahc_outb(ahc, SXFRCTL1, 783 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 784 wait = 5000; 785 while (--wait != 0) { 786 if ((ahc_inb(ahc, SCSISIGI) 787 & (CDI|MSGI)) != 0) 788 break; 789 ahc_delay(100); 790 } 791 ahc_outb(ahc, SXFRCTL1, 792 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 793 if (wait == 0) { 794 struct scb *scb; 795 u_int scb_index; 796 797 ahc_print_devinfo(ahc, &devinfo); 798 printf("Unable to clear parity error. " 799 "Resetting bus.\n"); 800 scb_index = ahc_inb(ahc, SCB_TAG); 801 scb = ahc_lookup_scb(ahc, scb_index); 802 if (scb != NULL) 803 ahc_set_transaction_status(scb, 804 CAM_UNCOR_PARITY); 805 ahc_reset_channel(ahc, devinfo.channel, 806 /*init reset*/TRUE); 807 } 808 } else { 809 ahc_inb(ahc, SCSIDATL); 810 } 811 } 812 break; 813 } 814 case DATA_OVERRUN: 815 { 816 /* 817 * When the sequencer detects an overrun, it 818 * places the controller in "BITBUCKET" mode 819 * and allows the target to complete its transfer. 820 * Unfortunately, none of the counters get updated 821 * when the controller is in this mode, so we have 822 * no way of knowing how large the overrun was. 823 */ 824 u_int scbindex = ahc_inb(ahc, SCB_TAG); 825 u_int lastphase = ahc_inb(ahc, LASTPHASE); 826 u_int i; 827 828 scb = ahc_lookup_scb(ahc, scbindex); 829 for (i = 0; i < num_phases; i++) { 830 if (lastphase == ahc_phase_table[i].phase) 831 break; 832 } 833 ahc_print_path(ahc, scb); 834 printf("data overrun detected %s." 835 " Tag == 0x%x.\n", 836 ahc_phase_table[i].phasemsg, 837 scb->hscb->tag); 838 ahc_print_path(ahc, scb); 839 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 840 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 841 ahc_get_transfer_length(scb), scb->sg_count); 842 if (scb->sg_count > 0) { 843 for (i = 0; i < scb->sg_count; i++) { 844 845 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 846 i, 847 (ahc_le32toh(scb->sg_list[i].len) >> 24 848 & SG_HIGH_ADDR_BITS), 849 ahc_le32toh(scb->sg_list[i].addr), 850 ahc_le32toh(scb->sg_list[i].len) 851 & AHC_SG_LEN_MASK); 852 } 853 } 854 /* 855 * Set this and it will take effect when the 856 * target does a command complete. 857 */ 858 ahc_freeze_devq(ahc, scb); 859 if ((scb->flags & SCB_SENSE) == 0) { 860 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 861 } else { 862 scb->flags &= ~SCB_SENSE; 863 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 864 } 865 ahc_freeze_scb(scb); 866 867 if ((ahc->features & AHC_ULTRA2) != 0) { 868 /* 869 * Clear the channel in case we return 870 * to data phase later. 871 */ 872 ahc_outb(ahc, SXFRCTL0, 873 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 874 ahc_outb(ahc, SXFRCTL0, 875 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 876 } 877 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 878 u_int dscommand1; 879 880 /* Ensure HHADDR is 0 for future DMA operations. */ 881 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 882 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 883 ahc_outb(ahc, HADDR, 0); 884 ahc_outb(ahc, DSCOMMAND1, dscommand1); 885 } 886 break; 887 } 888 case MKMSG_FAILED: 889 { 890 u_int scbindex; 891 892 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 893 ahc_name(ahc), devinfo.channel, devinfo.target, 894 devinfo.lun); 895 scbindex = ahc_inb(ahc, SCB_TAG); 896 scb = ahc_lookup_scb(ahc, scbindex); 897 if (scb != NULL 898 && (scb->flags & SCB_RECOVERY_SCB) != 0) 899 /* 900 * Ensure that we didn't put a second instance of this 901 * SCB into the QINFIFO. 902 */ 903 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 904 SCB_GET_CHANNEL(ahc, scb), 905 SCB_GET_LUN(scb), scb->hscb->tag, 906 ROLE_INITIATOR, /*status*/0, 907 SEARCH_REMOVE); 908 break; 909 } 910 case NO_FREE_SCB: 911 { 912 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 913 ahc_dump_card_state(ahc); 914 panic("for safety"); 915 break; 916 } 917 case SCB_MISMATCH: 918 { 919 u_int scbptr; 920 921 scbptr = ahc_inb(ahc, SCBPTR); 922 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 923 scbptr, ahc_inb(ahc, ARG_1), 924 ahc->scb_data->hscbs[scbptr].tag); 925 ahc_dump_card_state(ahc); 926 panic("for saftey"); 927 break; 928 } 929 case OUT_OF_RANGE: 930 { 931 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 932 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 933 "ARG_1 == 0x%x ACCUM = 0x%x\n", 934 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 935 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 936 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 937 "SINDEX == 0x%x\n, A == 0x%x\n", 938 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 939 ahc_index_busy_tcl(ahc, 940 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 941 ahc_inb(ahc, SAVED_LUN))), 942 ahc_inb(ahc, SINDEX), 943 ahc_inb(ahc, ACCUM)); 944 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 945 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 946 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 947 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 948 ahc_inb(ahc, SCB_CONTROL)); 949 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 950 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 951 ahc_dump_card_state(ahc); 952 panic("for safety"); 953 break; 954 } 955 default: 956 printf("ahc_intr: seqint, " 957 "intstat == 0x%x, scsisigi = 0x%x\n", 958 intstat, ahc_inb(ahc, SCSISIGI)); 959 break; 960 } 961 unpause: 962 /* 963 * The sequencer is paused immediately on 964 * a SEQINT, so we should restart it when 965 * we're done. 966 */ 967 ahc_unpause(ahc); 968 } 969 970 void 971 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 972 { 973 u_int scb_index; 974 u_int status0; 975 u_int status; 976 struct scb *scb; 977 char cur_channel; 978 char intr_channel; 979 980 if ((ahc->features & AHC_TWIN) != 0 981 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 982 cur_channel = 'B'; 983 else 984 cur_channel = 'A'; 985 intr_channel = cur_channel; 986 987 if ((ahc->features & AHC_ULTRA2) != 0) 988 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 989 else 990 status0 = 0; 991 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 992 if (status == 0 && status0 == 0) { 993 if ((ahc->features & AHC_TWIN) != 0) { 994 /* Try the other channel */ 995 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 996 status = ahc_inb(ahc, SSTAT1) 997 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 998 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 999 } 1000 if (status == 0) { 1001 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1002 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1003 ahc_unpause(ahc); 1004 return; 1005 } 1006 } 1007 1008 /* Make sure the sequencer is in a safe location. */ 1009 ahc_clear_critical_section(ahc); 1010 1011 scb_index = ahc_inb(ahc, SCB_TAG); 1012 scb = ahc_lookup_scb(ahc, scb_index); 1013 if (scb != NULL 1014 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1015 scb = NULL; 1016 1017 if ((ahc->features & AHC_ULTRA2) != 0 1018 && (status0 & IOERR) != 0) { 1019 int now_lvd; 1020 1021 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1022 printf("%s: Transceiver State Has Changed to %s mode\n", 1023 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1024 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1025 /* 1026 * When transitioning to SE mode, the reset line 1027 * glitches, triggering an arbitration bug in some 1028 * Ultra2 controllers. This bug is cleared when we 1029 * assert the reset line. Since a reset glitch has 1030 * already occurred with this transition and a 1031 * transceiver state change is handled just like 1032 * a bus reset anyway, asserting the reset line 1033 * ourselves is safe. 1034 */ 1035 ahc_reset_channel(ahc, intr_channel, 1036 /*Initiate Reset*/now_lvd == 0); 1037 } else if ((status & SCSIRSTI) != 0) { 1038 printf("%s: Someone reset channel %c\n", 1039 ahc_name(ahc), intr_channel); 1040 if (intr_channel != cur_channel) 1041 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1042 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1043 } else if ((status & SCSIPERR) != 0) { 1044 /* 1045 * Determine the bus phase and queue an appropriate message. 1046 * SCSIPERR is latched true as soon as a parity error 1047 * occurs. If the sequencer acked the transfer that 1048 * caused the parity error and the currently presented 1049 * transfer on the bus has correct parity, SCSIPERR will 1050 * be cleared by CLRSCSIPERR. Use this to determine if 1051 * we should look at the last phase the sequencer recorded, 1052 * or the current phase presented on the bus. 1053 */ 1054 u_int mesg_out; 1055 u_int curphase; 1056 u_int errorphase; 1057 u_int lastphase; 1058 u_int scsirate; 1059 u_int i; 1060 u_int sstat2; 1061 int silent; 1062 1063 lastphase = ahc_inb(ahc, LASTPHASE); 1064 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1065 sstat2 = ahc_inb(ahc, SSTAT2); 1066 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1067 /* 1068 * For all phases save DATA, the sequencer won't 1069 * automatically ack a byte that has a parity error 1070 * in it. So the only way that the current phase 1071 * could be 'data-in' is if the parity error is for 1072 * an already acked byte in the data phase. During 1073 * synchronous data-in transfers, we may actually 1074 * ack bytes before latching the current phase in 1075 * LASTPHASE, leading to the discrepancy between 1076 * curphase and lastphase. 1077 */ 1078 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1079 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1080 errorphase = curphase; 1081 else 1082 errorphase = lastphase; 1083 1084 for (i = 0; i < num_phases; i++) { 1085 if (errorphase == ahc_phase_table[i].phase) 1086 break; 1087 } 1088 mesg_out = ahc_phase_table[i].mesg_out; 1089 silent = FALSE; 1090 if (scb != NULL) { 1091 if (SCB_IS_SILENT(scb)) 1092 silent = TRUE; 1093 else 1094 ahc_print_path(ahc, scb); 1095 scb->flags |= SCB_TRANSMISSION_ERROR; 1096 } else 1097 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1098 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1099 scsirate = ahc_inb(ahc, SCSIRATE); 1100 if (silent == FALSE) { 1101 printf("parity error detected %s. " 1102 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1103 ahc_phase_table[i].phasemsg, 1104 ahc_inw(ahc, SEQADDR0), 1105 scsirate); 1106 if ((ahc->features & AHC_DT) != 0) { 1107 if ((sstat2 & CRCVALERR) != 0) 1108 printf("\tCRC Value Mismatch\n"); 1109 if ((sstat2 & CRCENDERR) != 0) 1110 printf("\tNo terminal CRC packet " 1111 "recevied\n"); 1112 if ((sstat2 & CRCREQERR) != 0) 1113 printf("\tIllegal CRC packet " 1114 "request\n"); 1115 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1116 printf("\tUnexpected %sDT Data Phase\n", 1117 (scsirate & SINGLE_EDGE) 1118 ? "" : "non-"); 1119 } 1120 } 1121 1122 if ((ahc->features & AHC_DT) != 0 1123 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1124 /* 1125 * This error applies regardless of 1126 * data direction, so ignore the value 1127 * in the phase table. 1128 */ 1129 mesg_out = MSG_INITIATOR_DET_ERR; 1130 } 1131 1132 /* 1133 * We've set the hardware to assert ATN if we 1134 * get a parity error on "in" phases, so all we 1135 * need to do is stuff the message buffer with 1136 * the appropriate message. "In" phases have set 1137 * mesg_out to something other than MSG_NOP. 1138 */ 1139 if (mesg_out != MSG_NOOP) { 1140 if (ahc->msg_type != MSG_TYPE_NONE) 1141 ahc->send_msg_perror = TRUE; 1142 else 1143 ahc_outb(ahc, MSG_OUT, mesg_out); 1144 } 1145 /* 1146 * Force a renegotiation with this target just in 1147 * case we are out of sync for some external reason 1148 * unknown (or unreported) by the target. 1149 */ 1150 ahc_force_renegotiation(ahc); 1151 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1152 ahc_unpause(ahc); 1153 } else if ((status & SELTO) != 0) { 1154 u_int scbptr; 1155 1156 /* Stop the selection */ 1157 ahc_outb(ahc, SCSISEQ, 0); 1158 1159 /* No more pending messages */ 1160 ahc_clear_msg_state(ahc); 1161 1162 /* Clear interrupt state */ 1163 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1164 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1165 1166 /* 1167 * Although the driver does not care about the 1168 * 'Selection in Progress' status bit, the busy 1169 * LED does. SELINGO is only cleared by a sucessfull 1170 * selection, so we must manually clear it to insure 1171 * the LED turns off just incase no future successful 1172 * selections occur (e.g. no devices on the bus). 1173 */ 1174 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1175 1176 scbptr = ahc_inb(ahc, WAITING_SCBH); 1177 ahc_outb(ahc, SCBPTR, scbptr); 1178 scb_index = ahc_inb(ahc, SCB_TAG); 1179 1180 scb = ahc_lookup_scb(ahc, scb_index); 1181 if (scb == NULL) { 1182 printf("%s: ahc_intr - referenced scb not " 1183 "valid during SELTO scb(%d, %d)\n", 1184 ahc_name(ahc), scbptr, scb_index); 1185 ahc_dump_card_state(ahc); 1186 } else { 1187 #ifdef AHC_DEBUG 1188 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1189 ahc_print_path(ahc, scb); 1190 printf("Saw Selection Timeout for SCB 0x%x\n", 1191 scb_index); 1192 } 1193 #endif 1194 /* 1195 * Force a renegotiation with this target just in 1196 * case the cable was pulled and will later be 1197 * re-attached. The target may forget its negotiation 1198 * settings with us should it attempt to reselect 1199 * during the interruption. The target will not issue 1200 * a unit attention in this case, so we must always 1201 * renegotiate. 1202 */ 1203 ahc_force_renegotiation(ahc); 1204 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1205 ahc_freeze_devq(ahc, scb); 1206 } 1207 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1208 ahc_restart(ahc); 1209 } else if ((status & BUSFREE) != 0 1210 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1211 u_int lastphase; 1212 u_int saved_scsiid; 1213 u_int saved_lun; 1214 u_int target; 1215 u_int initiator_role_id; 1216 char channel; 1217 int printerror; 1218 1219 /* 1220 * Clear our selection hardware as soon as possible. 1221 * We may have an entry in the waiting Q for this target, 1222 * that is affected by this busfree and we don't want to 1223 * go about selecting the target while we handle the event. 1224 */ 1225 ahc_outb(ahc, SCSISEQ, 1226 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1227 1228 /* 1229 * Disable busfree interrupts and clear the busfree 1230 * interrupt status. We do this here so that several 1231 * bus transactions occur prior to clearing the SCSIINT 1232 * latch. It can take a bit for the clearing to take effect. 1233 */ 1234 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1235 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1236 1237 /* 1238 * Look at what phase we were last in. 1239 * If its message out, chances are pretty good 1240 * that the busfree was in response to one of 1241 * our abort requests. 1242 */ 1243 lastphase = ahc_inb(ahc, LASTPHASE); 1244 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1245 saved_lun = ahc_inb(ahc, SAVED_LUN); 1246 target = SCSIID_TARGET(ahc, saved_scsiid); 1247 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1248 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1249 printerror = 1; 1250 1251 if (lastphase == P_MESGOUT) { 1252 struct ahc_devinfo devinfo; 1253 u_int tag; 1254 1255 ahc_fetch_devinfo(ahc, &devinfo); 1256 tag = SCB_LIST_NULL; 1257 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1258 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1259 if (ahc->msgout_buf[ahc->msgout_index - 1] 1260 == MSG_ABORT_TAG) 1261 tag = scb->hscb->tag; 1262 ahc_print_path(ahc, scb); 1263 printf("SCB %d - Abort%s Completed.\n", 1264 scb->hscb->tag, tag == SCB_LIST_NULL ? 1265 "" : " Tag"); 1266 ahc_abort_scbs(ahc, target, channel, 1267 saved_lun, tag, 1268 ROLE_INITIATOR, 1269 CAM_REQ_ABORTED); 1270 printerror = 0; 1271 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1272 MSG_BUS_DEV_RESET, TRUE)) { 1273 #ifdef __FreeBSD__ 1274 /* 1275 * Don't mark the user's request for this BDR 1276 * as completing with CAM_BDR_SENT. CAM3 1277 * specifies CAM_REQ_CMP. 1278 */ 1279 if (scb != NULL 1280 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1281 && ahc_match_scb(ahc, scb, target, channel, 1282 CAM_LUN_WILDCARD, 1283 SCB_LIST_NULL, 1284 ROLE_INITIATOR)) { 1285 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1286 } 1287 #endif 1288 ahc_compile_devinfo(&devinfo, 1289 initiator_role_id, 1290 target, 1291 CAM_LUN_WILDCARD, 1292 channel, 1293 ROLE_INITIATOR); 1294 ahc_handle_devreset(ahc, &devinfo, 1295 CAM_BDR_SENT, 1296 "Bus Device Reset", 1297 /*verbose_level*/0); 1298 printerror = 0; 1299 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1300 MSG_EXT_PPR, FALSE)) { 1301 struct ahc_initiator_tinfo *tinfo; 1302 struct ahc_tmode_tstate *tstate; 1303 1304 /* 1305 * PPR Rejected. Try non-ppr negotiation 1306 * and retry command. 1307 */ 1308 tinfo = ahc_fetch_transinfo(ahc, 1309 devinfo.channel, 1310 devinfo.our_scsiid, 1311 devinfo.target, 1312 &tstate); 1313 tinfo->curr.transport_version = 2; 1314 tinfo->goal.transport_version = 2; 1315 tinfo->goal.ppr_options = 0; 1316 ahc_qinfifo_requeue_tail(ahc, scb); 1317 printerror = 0; 1318 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1319 MSG_EXT_WDTR, FALSE) 1320 || ahc_sent_msg(ahc, AHCMSG_EXT, 1321 MSG_EXT_SDTR, FALSE)) { 1322 /* 1323 * Negotiation Rejected. Go-async and 1324 * retry command. 1325 */ 1326 ahc_set_width(ahc, &devinfo, 1327 MSG_EXT_WDTR_BUS_8_BIT, 1328 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1329 /*paused*/TRUE); 1330 ahc_set_syncrate(ahc, &devinfo, 1331 /*syncrate*/NULL, 1332 /*period*/0, /*offset*/0, 1333 /*ppr_options*/0, 1334 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1335 /*paused*/TRUE); 1336 ahc_qinfifo_requeue_tail(ahc, scb); 1337 printerror = 0; 1338 } 1339 } 1340 if (printerror != 0) { 1341 u_int i; 1342 1343 if (scb != NULL) { 1344 u_int tag; 1345 1346 if ((scb->hscb->control & TAG_ENB) != 0) 1347 tag = scb->hscb->tag; 1348 else 1349 tag = SCB_LIST_NULL; 1350 ahc_print_path(ahc, scb); 1351 ahc_abort_scbs(ahc, target, channel, 1352 SCB_GET_LUN(scb), tag, 1353 ROLE_INITIATOR, 1354 CAM_UNEXP_BUSFREE); 1355 } else { 1356 /* 1357 * We had not fully identified this connection, 1358 * so we cannot abort anything. 1359 */ 1360 printf("%s: ", ahc_name(ahc)); 1361 } 1362 for (i = 0; i < num_phases; i++) { 1363 if (lastphase == ahc_phase_table[i].phase) 1364 break; 1365 } 1366 /* 1367 * Renegotiate with this device at the 1368 * next oportunity just in case this busfree 1369 * is due to a negotiation mismatch with the 1370 * device. 1371 */ 1372 ahc_force_renegotiation(ahc); 1373 printf("Unexpected busfree %s\n" 1374 "SEQADDR == 0x%x\n", 1375 ahc_phase_table[i].phasemsg, 1376 ahc_inb(ahc, SEQADDR0) 1377 | (ahc_inb(ahc, SEQADDR1) << 8)); 1378 } 1379 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1380 ahc_restart(ahc); 1381 } else { 1382 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1383 ahc_name(ahc), status); 1384 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1385 } 1386 } 1387 1388 /* 1389 * Force renegotiation to occur the next time we initiate 1390 * a command to the current device. 1391 */ 1392 static void 1393 ahc_force_renegotiation(struct ahc_softc *ahc) 1394 { 1395 struct ahc_devinfo devinfo; 1396 struct ahc_initiator_tinfo *targ_info; 1397 struct ahc_tmode_tstate *tstate; 1398 1399 ahc_fetch_devinfo(ahc, &devinfo); 1400 targ_info = ahc_fetch_transinfo(ahc, 1401 devinfo.channel, 1402 devinfo.our_scsiid, 1403 devinfo.target, 1404 &tstate); 1405 ahc_update_neg_request(ahc, &devinfo, tstate, 1406 targ_info, AHC_NEG_IF_NON_ASYNC); 1407 } 1408 1409 #define AHC_MAX_STEPS 2000 1410 void 1411 ahc_clear_critical_section(struct ahc_softc *ahc) 1412 { 1413 int stepping; 1414 int steps; 1415 u_int simode0; 1416 u_int simode1; 1417 1418 if (ahc->num_critical_sections == 0) 1419 return; 1420 1421 stepping = FALSE; 1422 steps = 0; 1423 simode0 = 0; 1424 simode1 = 0; 1425 for (;;) { 1426 struct cs *cs; 1427 u_int seqaddr; 1428 u_int i; 1429 1430 seqaddr = ahc_inb(ahc, SEQADDR0) 1431 | (ahc_inb(ahc, SEQADDR1) << 8); 1432 1433 /* 1434 * Seqaddr represents the next instruction to execute, 1435 * so we are really executing the instruction just 1436 * before it. 1437 */ 1438 if (seqaddr != 0) 1439 seqaddr -= 1; 1440 cs = ahc->critical_sections; 1441 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1442 1443 if (cs->begin < seqaddr && cs->end >= seqaddr) 1444 break; 1445 } 1446 1447 if (i == ahc->num_critical_sections) 1448 break; 1449 1450 if (steps > AHC_MAX_STEPS) { 1451 printf("%s: Infinite loop in critical section\n", 1452 ahc_name(ahc)); 1453 ahc_dump_card_state(ahc); 1454 panic("critical section loop"); 1455 } 1456 1457 steps++; 1458 if (stepping == FALSE) { 1459 1460 /* 1461 * Disable all interrupt sources so that the 1462 * sequencer will not be stuck by a pausing 1463 * interrupt condition while we attempt to 1464 * leave a critical section. 1465 */ 1466 simode0 = ahc_inb(ahc, SIMODE0); 1467 ahc_outb(ahc, SIMODE0, 0); 1468 simode1 = ahc_inb(ahc, SIMODE1); 1469 if ((ahc->features & AHC_DT) != 0) 1470 /* 1471 * On DT class controllers, we 1472 * use the enhanced busfree logic. 1473 * Unfortunately we cannot re-enable 1474 * busfree detection within the 1475 * current connection, so we must 1476 * leave it on while single stepping. 1477 */ 1478 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1479 else 1480 ahc_outb(ahc, SIMODE1, 0); 1481 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1482 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1483 stepping = TRUE; 1484 } 1485 if ((ahc->features & AHC_DT) != 0) { 1486 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1487 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1488 } 1489 ahc_outb(ahc, HCNTRL, ahc->unpause); 1490 while (!ahc_is_paused(ahc)) 1491 ahc_delay(200); 1492 } 1493 if (stepping) { 1494 ahc_outb(ahc, SIMODE0, simode0); 1495 ahc_outb(ahc, SIMODE1, simode1); 1496 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1497 } 1498 } 1499 1500 /* 1501 * Clear any pending interrupt status. 1502 */ 1503 void 1504 ahc_clear_intstat(struct ahc_softc *ahc) 1505 { 1506 /* Clear any interrupt conditions this may have caused */ 1507 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1508 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1509 CLRREQINIT); 1510 ahc_flush_device_writes(ahc); 1511 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1512 ahc_flush_device_writes(ahc); 1513 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1514 ahc_flush_device_writes(ahc); 1515 } 1516 1517 /**************************** Debugging Routines ******************************/ 1518 #ifdef AHC_DEBUG 1519 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1520 #endif 1521 1522 void 1523 ahc_print_scb(struct scb *scb) 1524 { 1525 int i; 1526 1527 struct hardware_scb *hscb = scb->hscb; 1528 1529 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1530 (void *)scb, 1531 hscb->control, 1532 hscb->scsiid, 1533 hscb->lun, 1534 hscb->cdb_len); 1535 printf("Shared Data: "); 1536 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1537 printf("%#02x", hscb->shared_data.cdb[i]); 1538 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1539 ahc_le32toh(hscb->dataptr), 1540 ahc_le32toh(hscb->datacnt), 1541 ahc_le32toh(hscb->sgptr), 1542 hscb->tag); 1543 if (scb->sg_count > 0) { 1544 for (i = 0; i < scb->sg_count; i++) { 1545 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1546 i, 1547 (ahc_le32toh(scb->sg_list[i].len) >> 24 1548 & SG_HIGH_ADDR_BITS), 1549 ahc_le32toh(scb->sg_list[i].addr), 1550 ahc_le32toh(scb->sg_list[i].len)); 1551 } 1552 } 1553 } 1554 1555 /************************* Transfer Negotiation *******************************/ 1556 /* 1557 * Allocate per target mode instance (ID we respond to as a target) 1558 * transfer negotiation data structures. 1559 */ 1560 static struct ahc_tmode_tstate * 1561 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1562 { 1563 struct ahc_tmode_tstate *master_tstate; 1564 struct ahc_tmode_tstate *tstate; 1565 int i; 1566 1567 master_tstate = ahc->enabled_targets[ahc->our_id]; 1568 if (channel == 'B') { 1569 scsi_id += 8; 1570 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1571 } 1572 if (ahc->enabled_targets[scsi_id] != NULL 1573 && ahc->enabled_targets[scsi_id] != master_tstate) 1574 panic("%s: ahc_alloc_tstate - Target already allocated", 1575 ahc_name(ahc)); 1576 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1577 M_DEVBUF, M_NOWAIT); 1578 if (tstate == NULL) 1579 return (NULL); 1580 1581 /* 1582 * If we have allocated a master tstate, copy user settings from 1583 * the master tstate (taken from SRAM or the EEPROM) for this 1584 * channel, but reset our current and goal settings to async/narrow 1585 * until an initiator talks to us. 1586 */ 1587 if (master_tstate != NULL) { 1588 memcpy(tstate, master_tstate, sizeof(*tstate)); 1589 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1590 tstate->ultraenb = 0; 1591 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1592 memset(&tstate->transinfo[i].curr, 0, 1593 sizeof(tstate->transinfo[i].curr)); 1594 memset(&tstate->transinfo[i].goal, 0, 1595 sizeof(tstate->transinfo[i].goal)); 1596 } 1597 } else 1598 memset(tstate, 0, sizeof(*tstate)); 1599 ahc->enabled_targets[scsi_id] = tstate; 1600 return (tstate); 1601 } 1602 1603 #ifdef AHC_TARGET_MODE 1604 /* 1605 * Free per target mode instance (ID we respond to as a target) 1606 * transfer negotiation data structures. 1607 */ 1608 static void 1609 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1610 { 1611 struct ahc_tmode_tstate *tstate; 1612 1613 /* 1614 * Don't clean up our "master" tstate. 1615 * It has our default user settings. 1616 */ 1617 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1618 || (channel == 'A' && scsi_id == ahc->our_id)) 1619 && force == FALSE) 1620 return; 1621 1622 if (channel == 'B') 1623 scsi_id += 8; 1624 tstate = ahc->enabled_targets[scsi_id]; 1625 if (tstate != NULL) 1626 free(tstate, M_DEVBUF); 1627 ahc->enabled_targets[scsi_id] = NULL; 1628 } 1629 #endif 1630 1631 /* 1632 * Called when we have an active connection to a target on the bus, 1633 * this function finds the nearest syncrate to the input period limited 1634 * by the capabilities of the bus connectivity of and sync settings for 1635 * the target. 1636 */ 1637 struct ahc_syncrate * 1638 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1639 struct ahc_initiator_tinfo *tinfo, 1640 u_int *period, u_int *ppr_options, role_t role) 1641 { 1642 struct ahc_transinfo *transinfo; 1643 u_int maxsync; 1644 1645 if ((ahc->features & AHC_ULTRA2) != 0) { 1646 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1647 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1648 maxsync = AHC_SYNCRATE_DT; 1649 } else { 1650 maxsync = AHC_SYNCRATE_ULTRA; 1651 /* Can't do DT on an SE bus */ 1652 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1653 } 1654 } else if ((ahc->features & AHC_ULTRA) != 0) { 1655 maxsync = AHC_SYNCRATE_ULTRA; 1656 } else { 1657 maxsync = AHC_SYNCRATE_FAST; 1658 } 1659 /* 1660 * Never allow a value higher than our current goal 1661 * period otherwise we may allow a target initiated 1662 * negotiation to go above the limit as set by the 1663 * user. In the case of an initiator initiated 1664 * sync negotiation, we limit based on the user 1665 * setting. This allows the system to still accept 1666 * incoming negotiations even if target initiated 1667 * negotiation is not performed. 1668 */ 1669 if (role == ROLE_TARGET) 1670 transinfo = &tinfo->user; 1671 else 1672 transinfo = &tinfo->goal; 1673 *ppr_options &= transinfo->ppr_options; 1674 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1675 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1676 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1677 } 1678 if (transinfo->period == 0) { 1679 *period = 0; 1680 *ppr_options = 0; 1681 return (NULL); 1682 } 1683 *period = MAX(*period, transinfo->period); 1684 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1685 } 1686 1687 /* 1688 * Look up the valid period to SCSIRATE conversion in our table. 1689 * Return the period and offset that should be sent to the target 1690 * if this was the beginning of an SDTR. 1691 */ 1692 struct ahc_syncrate * 1693 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1694 u_int *ppr_options, u_int maxsync) 1695 { 1696 struct ahc_syncrate *syncrate; 1697 1698 if ((ahc->features & AHC_DT) == 0) 1699 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1700 1701 /* Skip all DT only entries if DT is not available */ 1702 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1703 && maxsync < AHC_SYNCRATE_ULTRA2) 1704 maxsync = AHC_SYNCRATE_ULTRA2; 1705 1706 for (syncrate = &ahc_syncrates[maxsync]; 1707 syncrate->rate != NULL; 1708 syncrate++) { 1709 1710 /* 1711 * The Ultra2 table doesn't go as low 1712 * as for the Fast/Ultra cards. 1713 */ 1714 if ((ahc->features & AHC_ULTRA2) != 0 1715 && (syncrate->sxfr_u2 == 0)) 1716 break; 1717 1718 if (*period <= syncrate->period) { 1719 /* 1720 * When responding to a target that requests 1721 * sync, the requested rate may fall between 1722 * two rates that we can output, but still be 1723 * a rate that we can receive. Because of this, 1724 * we want to respond to the target with 1725 * the same rate that it sent to us even 1726 * if the period we use to send data to it 1727 * is lower. Only lower the response period 1728 * if we must. 1729 */ 1730 if (syncrate == &ahc_syncrates[maxsync]) 1731 *period = syncrate->period; 1732 1733 /* 1734 * At some speeds, we only support 1735 * ST transfers. 1736 */ 1737 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1738 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1739 break; 1740 } 1741 } 1742 1743 if ((*period == 0) 1744 || (syncrate->rate == NULL) 1745 || ((ahc->features & AHC_ULTRA2) != 0 1746 && (syncrate->sxfr_u2 == 0))) { 1747 /* Use asynchronous transfers. */ 1748 *period = 0; 1749 syncrate = NULL; 1750 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1751 } 1752 return (syncrate); 1753 } 1754 1755 /* 1756 * Convert from an entry in our syncrate table to the SCSI equivalent 1757 * sync "period" factor. 1758 */ 1759 u_int 1760 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1761 { 1762 struct ahc_syncrate *syncrate; 1763 1764 if ((ahc->features & AHC_ULTRA2) != 0) 1765 scsirate &= SXFR_ULTRA2; 1766 else 1767 scsirate &= SXFR; 1768 1769 syncrate = &ahc_syncrates[maxsync]; 1770 while (syncrate->rate != NULL) { 1771 1772 if ((ahc->features & AHC_ULTRA2) != 0) { 1773 if (syncrate->sxfr_u2 == 0) 1774 break; 1775 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1776 return (syncrate->period); 1777 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1778 return (syncrate->period); 1779 } 1780 syncrate++; 1781 } 1782 return (0); /* async */ 1783 } 1784 1785 /* 1786 * Truncate the given synchronous offset to a value the 1787 * current adapter type and syncrate are capable of. 1788 */ 1789 void 1790 ahc_validate_offset(struct ahc_softc *ahc, 1791 struct ahc_initiator_tinfo *tinfo, 1792 struct ahc_syncrate *syncrate, 1793 u_int *offset, int wide, role_t role) 1794 { 1795 u_int maxoffset; 1796 1797 /* Limit offset to what we can do */ 1798 if (syncrate == NULL) { 1799 maxoffset = 0; 1800 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1801 maxoffset = MAX_OFFSET_ULTRA2; 1802 } else { 1803 if (wide) 1804 maxoffset = MAX_OFFSET_16BIT; 1805 else 1806 maxoffset = MAX_OFFSET_8BIT; 1807 } 1808 *offset = MIN(*offset, maxoffset); 1809 if (tinfo != NULL) { 1810 if (role == ROLE_TARGET) 1811 *offset = MIN(*offset, tinfo->user.offset); 1812 else 1813 *offset = MIN(*offset, tinfo->goal.offset); 1814 } 1815 } 1816 1817 /* 1818 * Truncate the given transfer width parameter to a value the 1819 * current adapter type is capable of. 1820 */ 1821 void 1822 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1823 u_int *bus_width, role_t role) 1824 { 1825 switch (*bus_width) { 1826 default: 1827 if (ahc->features & AHC_WIDE) { 1828 /* Respond Wide */ 1829 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1830 break; 1831 } 1832 /* FALLTHROUGH */ 1833 case MSG_EXT_WDTR_BUS_8_BIT: 1834 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1835 break; 1836 } 1837 if (tinfo != NULL) { 1838 if (role == ROLE_TARGET) 1839 *bus_width = MIN(tinfo->user.width, *bus_width); 1840 else 1841 *bus_width = MIN(tinfo->goal.width, *bus_width); 1842 } 1843 } 1844 1845 /* 1846 * Update the bitmask of targets for which the controller should 1847 * negotiate with at the next convenient oportunity. This currently 1848 * means the next time we send the initial identify messages for 1849 * a new transaction. 1850 */ 1851 int 1852 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1853 struct ahc_tmode_tstate *tstate, 1854 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1855 { 1856 u_int auto_negotiate_orig; 1857 1858 auto_negotiate_orig = tstate->auto_negotiate; 1859 if (neg_type == AHC_NEG_ALWAYS) { 1860 /* 1861 * Force our "current" settings to be 1862 * unknown so that unless a bus reset 1863 * occurs the need to renegotiate is 1864 * recorded persistently. 1865 */ 1866 if ((ahc->features & AHC_WIDE) != 0) 1867 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1868 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1869 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1870 } 1871 if (tinfo->curr.period != tinfo->goal.period 1872 || tinfo->curr.width != tinfo->goal.width 1873 || tinfo->curr.offset != tinfo->goal.offset 1874 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1875 || (neg_type == AHC_NEG_IF_NON_ASYNC 1876 && (tinfo->goal.offset != 0 1877 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1878 || tinfo->goal.ppr_options != 0))) 1879 tstate->auto_negotiate |= devinfo->target_mask; 1880 else 1881 tstate->auto_negotiate &= ~devinfo->target_mask; 1882 1883 return (auto_negotiate_orig != tstate->auto_negotiate); 1884 } 1885 1886 /* 1887 * Update the user/goal/curr tables of synchronous negotiation 1888 * parameters as well as, in the case of a current or active update, 1889 * any data structures on the host controller. In the case of an 1890 * active update, the specified target is currently talking to us on 1891 * the bus, so the transfer parameter update must take effect 1892 * immediately. 1893 */ 1894 void 1895 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1896 struct ahc_syncrate *syncrate, u_int period, 1897 u_int offset, u_int ppr_options, u_int type, int paused) 1898 { 1899 struct ahc_initiator_tinfo *tinfo; 1900 struct ahc_tmode_tstate *tstate; 1901 u_int old_period; 1902 u_int old_offset; 1903 u_int old_ppr; 1904 int active; 1905 int update_needed; 1906 1907 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1908 update_needed = 0; 1909 1910 if (syncrate == NULL) { 1911 period = 0; 1912 offset = 0; 1913 } 1914 1915 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1916 devinfo->target, &tstate); 1917 1918 if ((type & AHC_TRANS_USER) != 0) { 1919 tinfo->user.period = period; 1920 tinfo->user.offset = offset; 1921 tinfo->user.ppr_options = ppr_options; 1922 } 1923 1924 if ((type & AHC_TRANS_GOAL) != 0) { 1925 tinfo->goal.period = period; 1926 tinfo->goal.offset = offset; 1927 tinfo->goal.ppr_options = ppr_options; 1928 } 1929 1930 old_period = tinfo->curr.period; 1931 old_offset = tinfo->curr.offset; 1932 old_ppr = tinfo->curr.ppr_options; 1933 1934 if ((type & AHC_TRANS_CUR) != 0 1935 && (old_period != period 1936 || old_offset != offset 1937 || old_ppr != ppr_options)) { 1938 u_int scsirate; 1939 1940 update_needed++; 1941 scsirate = tinfo->scsirate; 1942 if ((ahc->features & AHC_ULTRA2) != 0) { 1943 1944 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1945 if (syncrate != NULL) { 1946 scsirate |= syncrate->sxfr_u2; 1947 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1948 scsirate |= ENABLE_CRC; 1949 else 1950 scsirate |= SINGLE_EDGE; 1951 } 1952 } else { 1953 1954 scsirate &= ~(SXFR|SOFS); 1955 /* 1956 * Ensure Ultra mode is set properly for 1957 * this target. 1958 */ 1959 tstate->ultraenb &= ~devinfo->target_mask; 1960 if (syncrate != NULL) { 1961 if (syncrate->sxfr & ULTRA_SXFR) { 1962 tstate->ultraenb |= 1963 devinfo->target_mask; 1964 } 1965 scsirate |= syncrate->sxfr & SXFR; 1966 scsirate |= offset & SOFS; 1967 } 1968 if (active) { 1969 u_int sxfrctl0; 1970 1971 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1972 sxfrctl0 &= ~FAST20; 1973 if (tstate->ultraenb & devinfo->target_mask) 1974 sxfrctl0 |= FAST20; 1975 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1976 } 1977 } 1978 if (active) { 1979 ahc_outb(ahc, SCSIRATE, scsirate); 1980 if ((ahc->features & AHC_ULTRA2) != 0) 1981 ahc_outb(ahc, SCSIOFFSET, offset); 1982 } 1983 1984 tinfo->scsirate = scsirate; 1985 tinfo->curr.period = period; 1986 tinfo->curr.offset = offset; 1987 tinfo->curr.ppr_options = ppr_options; 1988 1989 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1990 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1991 if (bootverbose) { 1992 if (offset != 0) { 1993 printf("%s: target %d synchronous at %sMHz%s, " 1994 "offset = 0x%x\n", ahc_name(ahc), 1995 devinfo->target, syncrate->rate, 1996 (ppr_options & MSG_EXT_PPR_DT_REQ) 1997 ? " DT" : "", offset); 1998 } else { 1999 printf("%s: target %d using " 2000 "asynchronous transfers\n", 2001 ahc_name(ahc), devinfo->target); 2002 } 2003 } 2004 } 2005 2006 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2007 tinfo, AHC_NEG_TO_GOAL); 2008 2009 if (update_needed) 2010 ahc_update_pending_scbs(ahc); 2011 } 2012 2013 /* 2014 * Update the user/goal/curr tables of wide negotiation 2015 * parameters as well as, in the case of a current or active update, 2016 * any data structures on the host controller. In the case of an 2017 * active update, the specified target is currently talking to us on 2018 * the bus, so the transfer parameter update must take effect 2019 * immediately. 2020 */ 2021 void 2022 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2023 u_int width, u_int type, int paused) 2024 { 2025 struct ahc_initiator_tinfo *tinfo; 2026 struct ahc_tmode_tstate *tstate; 2027 u_int oldwidth; 2028 int active; 2029 int update_needed; 2030 2031 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2032 update_needed = 0; 2033 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2034 devinfo->target, &tstate); 2035 2036 if ((type & AHC_TRANS_USER) != 0) 2037 tinfo->user.width = width; 2038 2039 if ((type & AHC_TRANS_GOAL) != 0) 2040 tinfo->goal.width = width; 2041 2042 oldwidth = tinfo->curr.width; 2043 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2044 u_int scsirate; 2045 2046 update_needed++; 2047 scsirate = tinfo->scsirate; 2048 scsirate &= ~WIDEXFER; 2049 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2050 scsirate |= WIDEXFER; 2051 2052 tinfo->scsirate = scsirate; 2053 2054 if (active) 2055 ahc_outb(ahc, SCSIRATE, scsirate); 2056 2057 tinfo->curr.width = width; 2058 2059 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2060 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2061 if (bootverbose) { 2062 printf("%s: target %d using %dbit transfers\n", 2063 ahc_name(ahc), devinfo->target, 2064 8 * (0x01 << width)); 2065 } 2066 } 2067 2068 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2069 tinfo, AHC_NEG_TO_GOAL); 2070 if (update_needed) 2071 ahc_update_pending_scbs(ahc); 2072 } 2073 2074 /* 2075 * Update the current state of tagged queuing for a given target. 2076 */ 2077 void 2078 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2079 ahc_queue_alg alg) 2080 { 2081 ahc_platform_set_tags(ahc, devinfo, alg); 2082 } 2083 2084 /* 2085 * When the transfer settings for a connection change, update any 2086 * in-transit SCBs to contain the new data so the hardware will 2087 * be set correctly during future (re)selections. 2088 */ 2089 static void 2090 ahc_update_pending_scbs(struct ahc_softc *ahc) 2091 { 2092 struct scb *pending_scb; 2093 int pending_scb_count; 2094 int i; 2095 int paused; 2096 u_int saved_scbptr; 2097 2098 /* 2099 * Traverse the pending SCB list and ensure that all of the 2100 * SCBs there have the proper settings. 2101 */ 2102 pending_scb_count = 0; 2103 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2104 struct ahc_devinfo devinfo; 2105 struct hardware_scb *pending_hscb; 2106 struct ahc_initiator_tinfo *tinfo; 2107 struct ahc_tmode_tstate *tstate; 2108 2109 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2110 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2111 devinfo.our_scsiid, 2112 devinfo.target, &tstate); 2113 pending_hscb = pending_scb->hscb; 2114 pending_hscb->control &= ~ULTRAENB; 2115 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2116 pending_hscb->control |= ULTRAENB; 2117 pending_hscb->scsirate = tinfo->scsirate; 2118 pending_hscb->scsioffset = tinfo->curr.offset; 2119 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2120 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2121 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2122 pending_hscb->control &= ~MK_MESSAGE; 2123 } 2124 ahc_sync_scb(ahc, pending_scb, 2125 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2126 pending_scb_count++; 2127 } 2128 2129 if (pending_scb_count == 0) 2130 return; 2131 2132 if (ahc_is_paused(ahc)) { 2133 paused = 1; 2134 } else { 2135 paused = 0; 2136 ahc_pause(ahc); 2137 } 2138 2139 saved_scbptr = ahc_inb(ahc, SCBPTR); 2140 /* Ensure that the hscbs down on the card match the new information */ 2141 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2142 struct hardware_scb *pending_hscb; 2143 u_int control; 2144 u_int scb_tag; 2145 2146 ahc_outb(ahc, SCBPTR, i); 2147 scb_tag = ahc_inb(ahc, SCB_TAG); 2148 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2149 if (pending_scb == NULL) 2150 continue; 2151 2152 pending_hscb = pending_scb->hscb; 2153 control = ahc_inb(ahc, SCB_CONTROL); 2154 control &= ~(ULTRAENB|MK_MESSAGE); 2155 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2156 ahc_outb(ahc, SCB_CONTROL, control); 2157 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2158 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2159 } 2160 ahc_outb(ahc, SCBPTR, saved_scbptr); 2161 2162 if (paused == 0) 2163 ahc_unpause(ahc); 2164 } 2165 2166 /**************************** Pathing Information *****************************/ 2167 static void 2168 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2169 { 2170 u_int saved_scsiid; 2171 role_t role; 2172 int our_id; 2173 2174 if (ahc_inb(ahc, SSTAT0) & TARGET) 2175 role = ROLE_TARGET; 2176 else 2177 role = ROLE_INITIATOR; 2178 2179 if (role == ROLE_TARGET 2180 && (ahc->features & AHC_MULTI_TID) != 0 2181 && (ahc_inb(ahc, SEQ_FLAGS) 2182 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2183 /* We were selected, so pull our id from TARGIDIN */ 2184 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2185 } else if ((ahc->features & AHC_ULTRA2) != 0) 2186 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2187 else 2188 our_id = ahc_inb(ahc, SCSIID) & OID; 2189 2190 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2191 ahc_compile_devinfo(devinfo, 2192 our_id, 2193 SCSIID_TARGET(ahc, saved_scsiid), 2194 ahc_inb(ahc, SAVED_LUN), 2195 SCSIID_CHANNEL(ahc, saved_scsiid), 2196 role); 2197 } 2198 2199 struct ahc_phase_table_entry* 2200 ahc_lookup_phase_entry(int phase) 2201 { 2202 struct ahc_phase_table_entry *entry; 2203 struct ahc_phase_table_entry *last_entry; 2204 2205 /* 2206 * num_phases doesn't include the default entry which 2207 * will be returned if the phase doesn't match. 2208 */ 2209 last_entry = &ahc_phase_table[num_phases]; 2210 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2211 if (phase == entry->phase) 2212 break; 2213 } 2214 return (entry); 2215 } 2216 2217 void 2218 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2219 u_int lun, char channel, role_t role) 2220 { 2221 devinfo->our_scsiid = our_id; 2222 devinfo->target = target; 2223 devinfo->lun = lun; 2224 devinfo->target_offset = target; 2225 devinfo->channel = channel; 2226 devinfo->role = role; 2227 if (channel == 'B') 2228 devinfo->target_offset += 8; 2229 devinfo->target_mask = (0x01 << devinfo->target_offset); 2230 } 2231 2232 void 2233 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2234 { 2235 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2236 devinfo->target, devinfo->lun); 2237 } 2238 2239 static void 2240 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2241 struct scb *scb) 2242 { 2243 role_t role; 2244 int our_id; 2245 2246 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2247 role = ROLE_INITIATOR; 2248 if ((scb->flags & SCB_TARGET_SCB) != 0) 2249 role = ROLE_TARGET; 2250 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2251 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2252 } 2253 2254 2255 /************************ Message Phase Processing ****************************/ 2256 static void 2257 ahc_assert_atn(struct ahc_softc *ahc) 2258 { 2259 u_int scsisigo; 2260 2261 scsisigo = ATNO; 2262 if ((ahc->features & AHC_DT) == 0) 2263 scsisigo |= ahc_inb(ahc, SCSISIGI); 2264 ahc_outb(ahc, SCSISIGO, scsisigo); 2265 } 2266 2267 /* 2268 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2269 * or enters the initial message out phase, we are interrupted. Fill our 2270 * outgoing message buffer with the appropriate message and beging handing 2271 * the message phase(s) manually. 2272 */ 2273 static void 2274 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2275 struct scb *scb) 2276 { 2277 /* 2278 * To facilitate adding multiple messages together, 2279 * each routine should increment the index and len 2280 * variables instead of setting them explicitly. 2281 */ 2282 ahc->msgout_index = 0; 2283 ahc->msgout_len = 0; 2284 2285 if ((scb->flags & SCB_DEVICE_RESET) == 0 2286 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2287 u_int identify_msg; 2288 2289 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2290 if ((scb->hscb->control & DISCENB) != 0) 2291 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2292 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2293 ahc->msgout_len++; 2294 2295 if ((scb->hscb->control & TAG_ENB) != 0) { 2296 ahc->msgout_buf[ahc->msgout_index++] = 2297 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2298 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2299 ahc->msgout_len += 2; 2300 } 2301 } 2302 2303 if (scb->flags & SCB_DEVICE_RESET) { 2304 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2305 ahc->msgout_len++; 2306 ahc_print_path(ahc, scb); 2307 printf("Bus Device Reset Message Sent\n"); 2308 /* 2309 * Clear our selection hardware in advance of 2310 * the busfree. We may have an entry in the waiting 2311 * Q for this target, and we don't want to go about 2312 * selecting while we handle the busfree and blow it 2313 * away. 2314 */ 2315 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2316 } else if ((scb->flags & SCB_ABORT) != 0) { 2317 if ((scb->hscb->control & TAG_ENB) != 0) 2318 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2319 else 2320 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2321 ahc->msgout_len++; 2322 ahc_print_path(ahc, scb); 2323 printf("Abort%s Message Sent\n", 2324 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2325 /* 2326 * Clear our selection hardware in advance of 2327 * the busfree. We may have an entry in the waiting 2328 * Q for this target, and we don't want to go about 2329 * selecting while we handle the busfree and blow it 2330 * away. 2331 */ 2332 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2333 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2334 ahc_build_transfer_msg(ahc, devinfo); 2335 } else { 2336 printf("ahc_intr: AWAITING_MSG for an SCB that " 2337 "does not have a waiting message\n"); 2338 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2339 devinfo->target_mask); 2340 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2341 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2342 ahc_inb(ahc, MSG_OUT), scb->flags); 2343 } 2344 2345 /* 2346 * Clear the MK_MESSAGE flag from the SCB so we aren't 2347 * asked to send this message again. 2348 */ 2349 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2350 scb->hscb->control &= ~MK_MESSAGE; 2351 ahc->msgout_index = 0; 2352 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2353 } 2354 2355 /* 2356 * Build an appropriate transfer negotiation message for the 2357 * currently active target. 2358 */ 2359 static void 2360 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2361 { 2362 /* 2363 * We need to initiate transfer negotiations. 2364 * If our current and goal settings are identical, 2365 * we want to renegotiate due to a check condition. 2366 */ 2367 struct ahc_initiator_tinfo *tinfo; 2368 struct ahc_tmode_tstate *tstate; 2369 struct ahc_syncrate *rate; 2370 int dowide; 2371 int dosync; 2372 int doppr; 2373 u_int period; 2374 u_int ppr_options; 2375 u_int offset; 2376 2377 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2378 devinfo->target, &tstate); 2379 /* 2380 * Filter our period based on the current connection. 2381 * If we can't perform DT transfers on this segment (not in LVD 2382 * mode for instance), then our decision to issue a PPR message 2383 * may change. 2384 */ 2385 period = tinfo->goal.period; 2386 ppr_options = tinfo->goal.ppr_options; 2387 /* Target initiated PPR is not allowed in the SCSI spec */ 2388 if (devinfo->role == ROLE_TARGET) 2389 ppr_options = 0; 2390 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2391 &ppr_options, devinfo->role); 2392 dowide = tinfo->curr.width != tinfo->goal.width; 2393 dosync = tinfo->curr.period != period; 2394 /* 2395 * Only use PPR if we have options that need it, even if the device 2396 * claims to support it. There might be an expander in the way 2397 * that doesn't. 2398 */ 2399 doppr = ppr_options != 0; 2400 2401 if (!dowide && !dosync && !doppr) { 2402 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2403 dosync = tinfo->goal.offset != 0; 2404 } 2405 2406 if (!dowide && !dosync && !doppr) { 2407 /* 2408 * Force async with a WDTR message if we have a wide bus, 2409 * or just issue an SDTR with a 0 offset. 2410 */ 2411 if ((ahc->features & AHC_WIDE) != 0) 2412 dowide = 1; 2413 else 2414 dosync = 1; 2415 2416 if (bootverbose) { 2417 ahc_print_devinfo(ahc, devinfo); 2418 printf("Ensuring async\n"); 2419 } 2420 } 2421 2422 /* Target initiated PPR is not allowed in the SCSI spec */ 2423 if (devinfo->role == ROLE_TARGET) 2424 doppr = 0; 2425 2426 /* 2427 * Both the PPR message and SDTR message require the 2428 * goal syncrate to be limited to what the target device 2429 * is capable of handling (based on whether an LVD->SE 2430 * expander is on the bus), so combine these two cases. 2431 * Regardless, guarantee that if we are using WDTR and SDTR 2432 * messages that WDTR comes first. 2433 */ 2434 if (doppr || (dosync && !dowide)) { 2435 2436 offset = tinfo->goal.offset; 2437 ahc_validate_offset(ahc, tinfo, rate, &offset, 2438 doppr ? tinfo->goal.width 2439 : tinfo->curr.width, 2440 devinfo->role); 2441 if (doppr) { 2442 ahc_construct_ppr(ahc, devinfo, period, offset, 2443 tinfo->goal.width, ppr_options); 2444 } else { 2445 ahc_construct_sdtr(ahc, devinfo, period, offset); 2446 } 2447 } else { 2448 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2449 } 2450 } 2451 2452 /* 2453 * Build a synchronous negotiation message in our message 2454 * buffer based on the input parameters. 2455 */ 2456 static void 2457 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2458 u_int period, u_int offset) 2459 { 2460 if (offset == 0) 2461 period = AHC_ASYNC_XFER_PERIOD; 2462 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2463 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2464 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2465 ahc->msgout_buf[ahc->msgout_index++] = period; 2466 ahc->msgout_buf[ahc->msgout_index++] = offset; 2467 ahc->msgout_len += 5; 2468 if (bootverbose) { 2469 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2470 ahc_name(ahc), devinfo->channel, devinfo->target, 2471 devinfo->lun, period, offset); 2472 } 2473 } 2474 2475 /* 2476 * Build a wide negotiation message in our message 2477 * buffer based on the input parameters. 2478 */ 2479 static void 2480 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2481 u_int bus_width) 2482 { 2483 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2484 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2485 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2486 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2487 ahc->msgout_len += 4; 2488 if (bootverbose) { 2489 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2490 ahc_name(ahc), devinfo->channel, devinfo->target, 2491 devinfo->lun, bus_width); 2492 } 2493 } 2494 2495 /* 2496 * Build a parallel protocol request message in our message 2497 * buffer based on the input parameters. 2498 */ 2499 static void 2500 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2501 u_int period, u_int offset, u_int bus_width, 2502 u_int ppr_options) 2503 { 2504 if (offset == 0) 2505 period = AHC_ASYNC_XFER_PERIOD; 2506 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2507 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2508 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2509 ahc->msgout_buf[ahc->msgout_index++] = period; 2510 ahc->msgout_buf[ahc->msgout_index++] = 0; 2511 ahc->msgout_buf[ahc->msgout_index++] = offset; 2512 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2513 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2514 ahc->msgout_len += 8; 2515 if (bootverbose) { 2516 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2517 "offset %x, ppr_options %x\n", ahc_name(ahc), 2518 devinfo->channel, devinfo->target, devinfo->lun, 2519 bus_width, period, offset, ppr_options); 2520 } 2521 } 2522 2523 /* 2524 * Clear any active message state. 2525 */ 2526 static void 2527 ahc_clear_msg_state(struct ahc_softc *ahc) 2528 { 2529 ahc->msgout_len = 0; 2530 ahc->msgin_index = 0; 2531 ahc->msg_type = MSG_TYPE_NONE; 2532 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2533 /* 2534 * The target didn't care to respond to our 2535 * message request, so clear ATN. 2536 */ 2537 ahc_outb(ahc, CLRSINT1, CLRATNO); 2538 } 2539 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2540 ahc_outb(ahc, SEQ_FLAGS2, 2541 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2542 } 2543 2544 static void 2545 ahc_handle_proto_violation(struct ahc_softc *ahc) 2546 { 2547 struct ahc_devinfo devinfo; 2548 struct scb *scb; 2549 u_int scbid; 2550 u_int seq_flags; 2551 u_int curphase; 2552 u_int lastphase; 2553 int found; 2554 2555 ahc_fetch_devinfo(ahc, &devinfo); 2556 scbid = ahc_inb(ahc, SCB_TAG); 2557 scb = ahc_lookup_scb(ahc, scbid); 2558 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2559 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2560 lastphase = ahc_inb(ahc, LASTPHASE); 2561 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2562 2563 /* 2564 * The reconnecting target either did not send an 2565 * identify message, or did, but we didn't find an SCB 2566 * to match. 2567 */ 2568 ahc_print_devinfo(ahc, &devinfo); 2569 printf("Target did not send an IDENTIFY message. " 2570 "LASTPHASE = 0x%x.\n", lastphase); 2571 scb = NULL; 2572 } else if (scb == NULL) { 2573 /* 2574 * We don't seem to have an SCB active for this 2575 * transaction. Print an error and reset the bus. 2576 */ 2577 ahc_print_devinfo(ahc, &devinfo); 2578 printf("No SCB found during protocol violation\n"); 2579 goto proto_violation_reset; 2580 } else { 2581 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2582 if ((seq_flags & NO_CDB_SENT) != 0) { 2583 ahc_print_path(ahc, scb); 2584 printf("No or incomplete CDB sent to device.\n"); 2585 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2586 /* 2587 * The target never bothered to provide status to 2588 * us prior to completing the command. Since we don't 2589 * know the disposition of this command, we must attempt 2590 * to abort it. Assert ATN and prepare to send an abort 2591 * message. 2592 */ 2593 ahc_print_path(ahc, scb); 2594 printf("Completed command without status.\n"); 2595 } else { 2596 ahc_print_path(ahc, scb); 2597 printf("Unknown protocol violation.\n"); 2598 ahc_dump_card_state(ahc); 2599 } 2600 } 2601 if ((lastphase & ~P_DATAIN_DT) == 0 2602 || lastphase == P_COMMAND) { 2603 proto_violation_reset: 2604 /* 2605 * Target either went directly to data/command 2606 * phase or didn't respond to our ATN. 2607 * The only safe thing to do is to blow 2608 * it away with a bus reset. 2609 */ 2610 found = ahc_reset_channel(ahc, 'A', TRUE); 2611 printf("%s: Issued Channel %c Bus Reset. " 2612 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2613 } else { 2614 /* 2615 * Leave the selection hardware off in case 2616 * this abort attempt will affect yet to 2617 * be sent commands. 2618 */ 2619 ahc_outb(ahc, SCSISEQ, 2620 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2621 ahc_assert_atn(ahc); 2622 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2623 if (scb == NULL) { 2624 ahc_print_devinfo(ahc, &devinfo); 2625 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2626 ahc->msgout_len = 1; 2627 ahc->msgout_index = 0; 2628 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2629 } else { 2630 ahc_print_path(ahc, scb); 2631 scb->flags |= SCB_ABORT; 2632 } 2633 printf("Protocol violation %s. Attempting to abort.\n", 2634 ahc_lookup_phase_entry(curphase)->phasemsg); 2635 } 2636 } 2637 2638 /* 2639 * Manual message loop handler. 2640 */ 2641 static void 2642 ahc_handle_message_phase(struct ahc_softc *ahc) 2643 { 2644 struct ahc_devinfo devinfo; 2645 u_int bus_phase; 2646 int end_session; 2647 2648 ahc_fetch_devinfo(ahc, &devinfo); 2649 end_session = FALSE; 2650 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2651 2652 reswitch: 2653 switch (ahc->msg_type) { 2654 case MSG_TYPE_INITIATOR_MSGOUT: 2655 { 2656 int lastbyte; 2657 int phasemis; 2658 int msgdone; 2659 2660 if (ahc->msgout_len == 0) 2661 panic("HOST_MSG_LOOP interrupt with no active message"); 2662 2663 #ifdef AHC_DEBUG 2664 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2665 ahc_print_devinfo(ahc, &devinfo); 2666 printf("INITIATOR_MSG_OUT"); 2667 } 2668 #endif 2669 phasemis = bus_phase != P_MESGOUT; 2670 if (phasemis) { 2671 #ifdef AHC_DEBUG 2672 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2673 printf(" PHASEMIS %s\n", 2674 ahc_lookup_phase_entry(bus_phase) 2675 ->phasemsg); 2676 } 2677 #endif 2678 if (bus_phase == P_MESGIN) { 2679 /* 2680 * Change gears and see if 2681 * this messages is of interest to 2682 * us or should be passed back to 2683 * the sequencer. 2684 */ 2685 ahc_outb(ahc, CLRSINT1, CLRATNO); 2686 ahc->send_msg_perror = FALSE; 2687 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2688 ahc->msgin_index = 0; 2689 goto reswitch; 2690 } 2691 end_session = TRUE; 2692 break; 2693 } 2694 2695 if (ahc->send_msg_perror) { 2696 ahc_outb(ahc, CLRSINT1, CLRATNO); 2697 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2698 #ifdef AHC_DEBUG 2699 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2700 printf(" byte 0x%x\n", ahc->send_msg_perror); 2701 #endif 2702 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2703 break; 2704 } 2705 2706 msgdone = ahc->msgout_index == ahc->msgout_len; 2707 if (msgdone) { 2708 /* 2709 * The target has requested a retry. 2710 * Re-assert ATN, reset our message index to 2711 * 0, and try again. 2712 */ 2713 ahc->msgout_index = 0; 2714 ahc_assert_atn(ahc); 2715 } 2716 2717 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2718 if (lastbyte) { 2719 /* Last byte is signified by dropping ATN */ 2720 ahc_outb(ahc, CLRSINT1, CLRATNO); 2721 } 2722 2723 /* 2724 * Clear our interrupt status and present 2725 * the next byte on the bus. 2726 */ 2727 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2728 #ifdef AHC_DEBUG 2729 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2730 printf(" byte 0x%x\n", 2731 ahc->msgout_buf[ahc->msgout_index]); 2732 #endif 2733 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2734 break; 2735 } 2736 case MSG_TYPE_INITIATOR_MSGIN: 2737 { 2738 int phasemis; 2739 int message_done; 2740 2741 #ifdef AHC_DEBUG 2742 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2743 ahc_print_devinfo(ahc, &devinfo); 2744 printf("INITIATOR_MSG_IN"); 2745 } 2746 #endif 2747 phasemis = bus_phase != P_MESGIN; 2748 if (phasemis) { 2749 #ifdef AHC_DEBUG 2750 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2751 printf(" PHASEMIS %s\n", 2752 ahc_lookup_phase_entry(bus_phase) 2753 ->phasemsg); 2754 } 2755 #endif 2756 ahc->msgin_index = 0; 2757 if (bus_phase == P_MESGOUT 2758 && (ahc->send_msg_perror == TRUE 2759 || (ahc->msgout_len != 0 2760 && ahc->msgout_index == 0))) { 2761 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2762 goto reswitch; 2763 } 2764 end_session = TRUE; 2765 break; 2766 } 2767 2768 /* Pull the byte in without acking it */ 2769 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2770 #ifdef AHC_DEBUG 2771 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2772 printf(" byte 0x%x\n", 2773 ahc->msgin_buf[ahc->msgin_index]); 2774 #endif 2775 2776 message_done = ahc_parse_msg(ahc, &devinfo); 2777 2778 if (message_done) { 2779 /* 2780 * Clear our incoming message buffer in case there 2781 * is another message following this one. 2782 */ 2783 ahc->msgin_index = 0; 2784 2785 /* 2786 * If this message illicited a response, 2787 * assert ATN so the target takes us to the 2788 * message out phase. 2789 */ 2790 if (ahc->msgout_len != 0) { 2791 #ifdef AHC_DEBUG 2792 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2793 ahc_print_devinfo(ahc, &devinfo); 2794 printf("Asserting ATN for response\n"); 2795 } 2796 #endif 2797 ahc_assert_atn(ahc); 2798 } 2799 } else 2800 ahc->msgin_index++; 2801 2802 if (message_done == MSGLOOP_TERMINATED) { 2803 end_session = TRUE; 2804 } else { 2805 /* Ack the byte */ 2806 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2807 ahc_inb(ahc, SCSIDATL); 2808 } 2809 break; 2810 } 2811 case MSG_TYPE_TARGET_MSGIN: 2812 { 2813 int msgdone; 2814 int msgout_request; 2815 2816 if (ahc->msgout_len == 0) 2817 panic("Target MSGIN with no active message"); 2818 2819 /* 2820 * If we interrupted a mesgout session, the initiator 2821 * will not know this until our first REQ. So, we 2822 * only honor mesgout requests after we've sent our 2823 * first byte. 2824 */ 2825 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2826 && ahc->msgout_index > 0) 2827 msgout_request = TRUE; 2828 else 2829 msgout_request = FALSE; 2830 2831 if (msgout_request) { 2832 2833 /* 2834 * Change gears and see if 2835 * this messages is of interest to 2836 * us or should be passed back to 2837 * the sequencer. 2838 */ 2839 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2840 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2841 ahc->msgin_index = 0; 2842 /* Dummy read to REQ for first byte */ 2843 ahc_inb(ahc, SCSIDATL); 2844 ahc_outb(ahc, SXFRCTL0, 2845 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2846 break; 2847 } 2848 2849 msgdone = ahc->msgout_index == ahc->msgout_len; 2850 if (msgdone) { 2851 ahc_outb(ahc, SXFRCTL0, 2852 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2853 end_session = TRUE; 2854 break; 2855 } 2856 2857 /* 2858 * Present the next byte on the bus. 2859 */ 2860 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2861 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2862 break; 2863 } 2864 case MSG_TYPE_TARGET_MSGOUT: 2865 { 2866 int lastbyte; 2867 int msgdone; 2868 2869 /* 2870 * The initiator signals that this is 2871 * the last byte by dropping ATN. 2872 */ 2873 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2874 2875 /* 2876 * Read the latched byte, but turn off SPIOEN first 2877 * so that we don't inadvertently cause a REQ for the 2878 * next byte. 2879 */ 2880 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2881 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2882 msgdone = ahc_parse_msg(ahc, &devinfo); 2883 if (msgdone == MSGLOOP_TERMINATED) { 2884 /* 2885 * The message is *really* done in that it caused 2886 * us to go to bus free. The sequencer has already 2887 * been reset at this point, so pull the ejection 2888 * handle. 2889 */ 2890 return; 2891 } 2892 2893 ahc->msgin_index++; 2894 2895 /* 2896 * XXX Read spec about initiator dropping ATN too soon 2897 * and use msgdone to detect it. 2898 */ 2899 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2900 ahc->msgin_index = 0; 2901 2902 /* 2903 * If this message illicited a response, transition 2904 * to the Message in phase and send it. 2905 */ 2906 if (ahc->msgout_len != 0) { 2907 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2908 ahc_outb(ahc, SXFRCTL0, 2909 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2910 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2911 ahc->msgin_index = 0; 2912 break; 2913 } 2914 } 2915 2916 if (lastbyte) 2917 end_session = TRUE; 2918 else { 2919 /* Ask for the next byte. */ 2920 ahc_outb(ahc, SXFRCTL0, 2921 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2922 } 2923 2924 break; 2925 } 2926 default: 2927 panic("Unknown REQINIT message type"); 2928 } 2929 2930 if (end_session) { 2931 ahc_clear_msg_state(ahc); 2932 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2933 } else 2934 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2935 } 2936 2937 /* 2938 * See if we sent a particular extended message to the target. 2939 * If "full" is true, return true only if the target saw the full 2940 * message. If "full" is false, return true if the target saw at 2941 * least the first byte of the message. 2942 */ 2943 static int 2944 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2945 { 2946 int found; 2947 u_int index; 2948 2949 found = FALSE; 2950 index = 0; 2951 2952 while (index < ahc->msgout_len) { 2953 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2954 u_int end_index; 2955 2956 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2957 if (ahc->msgout_buf[index+2] == msgval 2958 && type == AHCMSG_EXT) { 2959 2960 if (full) { 2961 if (ahc->msgout_index > end_index) 2962 found = TRUE; 2963 } else if (ahc->msgout_index > index) 2964 found = TRUE; 2965 } 2966 index = end_index; 2967 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2968 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2969 2970 /* Skip tag type and tag id or residue param*/ 2971 index += 2; 2972 } else { 2973 /* Single byte message */ 2974 if (type == AHCMSG_1B 2975 && ahc->msgout_buf[index] == msgval 2976 && ahc->msgout_index > index) 2977 found = TRUE; 2978 index++; 2979 } 2980 2981 if (found) 2982 break; 2983 } 2984 return (found); 2985 } 2986 2987 /* 2988 * Wait for a complete incoming message, parse it, and respond accordingly. 2989 */ 2990 static int 2991 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2992 { 2993 struct ahc_initiator_tinfo *tinfo; 2994 struct ahc_tmode_tstate *tstate; 2995 int reject; 2996 int done; 2997 int response; 2998 u_int targ_scsirate; 2999 3000 done = MSGLOOP_IN_PROG; 3001 response = FALSE; 3002 reject = FALSE; 3003 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3004 devinfo->target, &tstate); 3005 targ_scsirate = tinfo->scsirate; 3006 3007 /* 3008 * Parse as much of the message as is availible, 3009 * rejecting it if we don't support it. When 3010 * the entire message is availible and has been 3011 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3012 * that we have parsed an entire message. 3013 * 3014 * In the case of extended messages, we accept the length 3015 * byte outright and perform more checking once we know the 3016 * extended message type. 3017 */ 3018 switch (ahc->msgin_buf[0]) { 3019 case MSG_DISCONNECT: 3020 case MSG_SAVEDATAPOINTER: 3021 case MSG_CMDCOMPLETE: 3022 case MSG_RESTOREPOINTERS: 3023 case MSG_IGN_WIDE_RESIDUE: 3024 /* 3025 * End our message loop as these are messages 3026 * the sequencer handles on its own. 3027 */ 3028 done = MSGLOOP_TERMINATED; 3029 break; 3030 case MSG_MESSAGE_REJECT: 3031 response = ahc_handle_msg_reject(ahc, devinfo); 3032 /* FALLTHROUGH */ 3033 case MSG_NOOP: 3034 done = MSGLOOP_MSGCOMPLETE; 3035 break; 3036 case MSG_EXTENDED: 3037 { 3038 /* Wait for enough of the message to begin validation */ 3039 if (ahc->msgin_index < 2) 3040 break; 3041 switch (ahc->msgin_buf[2]) { 3042 case MSG_EXT_SDTR: 3043 { 3044 struct ahc_syncrate *syncrate; 3045 u_int period; 3046 u_int ppr_options; 3047 u_int offset; 3048 u_int saved_offset; 3049 3050 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3051 reject = TRUE; 3052 break; 3053 } 3054 3055 /* 3056 * Wait until we have both args before validating 3057 * and acting on this message. 3058 * 3059 * Add one to MSG_EXT_SDTR_LEN to account for 3060 * the extended message preamble. 3061 */ 3062 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3063 break; 3064 3065 period = ahc->msgin_buf[3]; 3066 ppr_options = 0; 3067 saved_offset = offset = ahc->msgin_buf[4]; 3068 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3069 &ppr_options, 3070 devinfo->role); 3071 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3072 targ_scsirate & WIDEXFER, 3073 devinfo->role); 3074 if (bootverbose) { 3075 printf("(%s:%c:%d:%d): Received " 3076 "SDTR period %x, offset %x\n\t" 3077 "Filtered to period %x, offset %x\n", 3078 ahc_name(ahc), devinfo->channel, 3079 devinfo->target, devinfo->lun, 3080 ahc->msgin_buf[3], saved_offset, 3081 period, offset); 3082 } 3083 ahc_set_syncrate(ahc, devinfo, 3084 syncrate, period, 3085 offset, ppr_options, 3086 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3087 /*paused*/TRUE); 3088 3089 /* 3090 * See if we initiated Sync Negotiation 3091 * and didn't have to fall down to async 3092 * transfers. 3093 */ 3094 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3095 /* We started it */ 3096 if (saved_offset != offset) { 3097 /* Went too low - force async */ 3098 reject = TRUE; 3099 } 3100 } else { 3101 /* 3102 * Send our own SDTR in reply 3103 */ 3104 if (bootverbose 3105 && devinfo->role == ROLE_INITIATOR) { 3106 printf("(%s:%c:%d:%d): Target " 3107 "Initiated SDTR\n", 3108 ahc_name(ahc), devinfo->channel, 3109 devinfo->target, devinfo->lun); 3110 } 3111 ahc->msgout_index = 0; 3112 ahc->msgout_len = 0; 3113 ahc_construct_sdtr(ahc, devinfo, 3114 period, offset); 3115 ahc->msgout_index = 0; 3116 response = TRUE; 3117 } 3118 done = MSGLOOP_MSGCOMPLETE; 3119 break; 3120 } 3121 case MSG_EXT_WDTR: 3122 { 3123 u_int bus_width; 3124 u_int saved_width; 3125 u_int sending_reply; 3126 3127 sending_reply = FALSE; 3128 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3129 reject = TRUE; 3130 break; 3131 } 3132 3133 /* 3134 * Wait until we have our arg before validating 3135 * and acting on this message. 3136 * 3137 * Add one to MSG_EXT_WDTR_LEN to account for 3138 * the extended message preamble. 3139 */ 3140 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3141 break; 3142 3143 bus_width = ahc->msgin_buf[3]; 3144 saved_width = bus_width; 3145 ahc_validate_width(ahc, tinfo, &bus_width, 3146 devinfo->role); 3147 if (bootverbose) { 3148 printf("(%s:%c:%d:%d): Received WDTR " 3149 "%x filtered to %x\n", 3150 ahc_name(ahc), devinfo->channel, 3151 devinfo->target, devinfo->lun, 3152 saved_width, bus_width); 3153 } 3154 3155 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3156 /* 3157 * Don't send a WDTR back to the 3158 * target, since we asked first. 3159 * If the width went higher than our 3160 * request, reject it. 3161 */ 3162 if (saved_width > bus_width) { 3163 reject = TRUE; 3164 printf("(%s:%c:%d:%d): requested %dBit " 3165 "transfers. Rejecting...\n", 3166 ahc_name(ahc), devinfo->channel, 3167 devinfo->target, devinfo->lun, 3168 8 * (0x01 << bus_width)); 3169 bus_width = 0; 3170 } 3171 } else { 3172 /* 3173 * Send our own WDTR in reply 3174 */ 3175 if (bootverbose 3176 && devinfo->role == ROLE_INITIATOR) { 3177 printf("(%s:%c:%d:%d): Target " 3178 "Initiated WDTR\n", 3179 ahc_name(ahc), devinfo->channel, 3180 devinfo->target, devinfo->lun); 3181 } 3182 ahc->msgout_index = 0; 3183 ahc->msgout_len = 0; 3184 ahc_construct_wdtr(ahc, devinfo, bus_width); 3185 ahc->msgout_index = 0; 3186 response = TRUE; 3187 sending_reply = TRUE; 3188 } 3189 ahc_set_width(ahc, devinfo, bus_width, 3190 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3191 /*paused*/TRUE); 3192 /* After a wide message, we are async */ 3193 ahc_set_syncrate(ahc, devinfo, 3194 /*syncrate*/NULL, /*period*/0, 3195 /*offset*/0, /*ppr_options*/0, 3196 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3197 if (sending_reply == FALSE && reject == FALSE) { 3198 3199 if (tinfo->goal.offset) { 3200 ahc->msgout_index = 0; 3201 ahc->msgout_len = 0; 3202 ahc_build_transfer_msg(ahc, devinfo); 3203 ahc->msgout_index = 0; 3204 response = TRUE; 3205 } 3206 } 3207 done = MSGLOOP_MSGCOMPLETE; 3208 break; 3209 } 3210 case MSG_EXT_PPR: 3211 { 3212 struct ahc_syncrate *syncrate; 3213 u_int period; 3214 u_int offset; 3215 u_int bus_width; 3216 u_int ppr_options; 3217 u_int saved_width; 3218 u_int saved_offset; 3219 u_int saved_ppr_options; 3220 3221 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3222 reject = TRUE; 3223 break; 3224 } 3225 3226 /* 3227 * Wait until we have all args before validating 3228 * and acting on this message. 3229 * 3230 * Add one to MSG_EXT_PPR_LEN to account for 3231 * the extended message preamble. 3232 */ 3233 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3234 break; 3235 3236 period = ahc->msgin_buf[3]; 3237 offset = ahc->msgin_buf[5]; 3238 bus_width = ahc->msgin_buf[6]; 3239 saved_width = bus_width; 3240 ppr_options = ahc->msgin_buf[7]; 3241 /* 3242 * According to the spec, a DT only 3243 * period factor with no DT option 3244 * set implies async. 3245 */ 3246 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3247 && period == 9) 3248 offset = 0; 3249 saved_ppr_options = ppr_options; 3250 saved_offset = offset; 3251 3252 /* 3253 * Mask out any options we don't support 3254 * on any controller. Transfer options are 3255 * only available if we are negotiating wide. 3256 */ 3257 ppr_options &= MSG_EXT_PPR_DT_REQ; 3258 if (bus_width == 0) 3259 ppr_options = 0; 3260 3261 ahc_validate_width(ahc, tinfo, &bus_width, 3262 devinfo->role); 3263 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3264 &ppr_options, 3265 devinfo->role); 3266 ahc_validate_offset(ahc, tinfo, syncrate, 3267 &offset, bus_width, 3268 devinfo->role); 3269 3270 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3271 /* 3272 * If we are unable to do any of the 3273 * requested options (we went too low), 3274 * then we'll have to reject the message. 3275 */ 3276 if (saved_width > bus_width 3277 || saved_offset != offset 3278 || saved_ppr_options != ppr_options) { 3279 reject = TRUE; 3280 period = 0; 3281 offset = 0; 3282 bus_width = 0; 3283 ppr_options = 0; 3284 syncrate = NULL; 3285 } 3286 } else { 3287 if (devinfo->role != ROLE_TARGET) 3288 printf("(%s:%c:%d:%d): Target " 3289 "Initiated PPR\n", 3290 ahc_name(ahc), devinfo->channel, 3291 devinfo->target, devinfo->lun); 3292 else 3293 printf("(%s:%c:%d:%d): Initiator " 3294 "Initiated PPR\n", 3295 ahc_name(ahc), devinfo->channel, 3296 devinfo->target, devinfo->lun); 3297 ahc->msgout_index = 0; 3298 ahc->msgout_len = 0; 3299 ahc_construct_ppr(ahc, devinfo, period, offset, 3300 bus_width, ppr_options); 3301 ahc->msgout_index = 0; 3302 response = TRUE; 3303 } 3304 if (bootverbose) { 3305 printf("(%s:%c:%d:%d): Received PPR width %x, " 3306 "period %x, offset %x,options %x\n" 3307 "\tFiltered to width %x, period %x, " 3308 "offset %x, options %x\n", 3309 ahc_name(ahc), devinfo->channel, 3310 devinfo->target, devinfo->lun, 3311 saved_width, ahc->msgin_buf[3], 3312 saved_offset, saved_ppr_options, 3313 bus_width, period, offset, ppr_options); 3314 } 3315 ahc_set_width(ahc, devinfo, bus_width, 3316 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3317 /*paused*/TRUE); 3318 ahc_set_syncrate(ahc, devinfo, 3319 syncrate, period, 3320 offset, ppr_options, 3321 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3322 /*paused*/TRUE); 3323 done = MSGLOOP_MSGCOMPLETE; 3324 break; 3325 } 3326 default: 3327 /* Unknown extended message. Reject it. */ 3328 reject = TRUE; 3329 break; 3330 } 3331 break; 3332 } 3333 #ifdef AHC_TARGET_MODE 3334 case MSG_BUS_DEV_RESET: 3335 ahc_handle_devreset(ahc, devinfo, 3336 CAM_BDR_SENT, 3337 "Bus Device Reset Received", 3338 /*verbose_level*/0); 3339 ahc_restart(ahc); 3340 done = MSGLOOP_TERMINATED; 3341 break; 3342 case MSG_ABORT_TAG: 3343 case MSG_ABORT: 3344 case MSG_CLEAR_QUEUE: 3345 { 3346 int tag; 3347 3348 /* Target mode messages */ 3349 if (devinfo->role != ROLE_TARGET) { 3350 reject = TRUE; 3351 break; 3352 } 3353 tag = SCB_LIST_NULL; 3354 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3355 tag = ahc_inb(ahc, INITIATOR_TAG); 3356 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3357 devinfo->lun, tag, ROLE_TARGET, 3358 CAM_REQ_ABORTED); 3359 3360 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3361 if (tstate != NULL) { 3362 struct ahc_tmode_lstate* lstate; 3363 3364 lstate = tstate->enabled_luns[devinfo->lun]; 3365 if (lstate != NULL) { 3366 ahc_queue_lstate_event(ahc, lstate, 3367 devinfo->our_scsiid, 3368 ahc->msgin_buf[0], 3369 /*arg*/tag); 3370 ahc_send_lstate_events(ahc, lstate); 3371 } 3372 } 3373 ahc_restart(ahc); 3374 done = MSGLOOP_TERMINATED; 3375 break; 3376 } 3377 #endif 3378 case MSG_TERM_IO_PROC: 3379 default: 3380 reject = TRUE; 3381 break; 3382 } 3383 3384 if (reject) { 3385 /* 3386 * Setup to reject the message. 3387 */ 3388 ahc->msgout_index = 0; 3389 ahc->msgout_len = 1; 3390 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3391 done = MSGLOOP_MSGCOMPLETE; 3392 response = TRUE; 3393 } 3394 3395 if (done != MSGLOOP_IN_PROG && !response) 3396 /* Clear the outgoing message buffer */ 3397 ahc->msgout_len = 0; 3398 3399 return (done); 3400 } 3401 3402 /* 3403 * Process a message reject message. 3404 */ 3405 static int 3406 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3407 { 3408 /* 3409 * What we care about here is if we had an 3410 * outstanding SDTR or WDTR message for this 3411 * target. If we did, this is a signal that 3412 * the target is refusing negotiation. 3413 */ 3414 struct scb *scb; 3415 struct ahc_initiator_tinfo *tinfo; 3416 struct ahc_tmode_tstate *tstate; 3417 u_int scb_index; 3418 u_int last_msg; 3419 int response = 0; 3420 3421 scb_index = ahc_inb(ahc, SCB_TAG); 3422 scb = ahc_lookup_scb(ahc, scb_index); 3423 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3424 devinfo->our_scsiid, 3425 devinfo->target, &tstate); 3426 /* Might be necessary */ 3427 last_msg = ahc_inb(ahc, LAST_MSG); 3428 3429 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3430 /* 3431 * Target does not support the PPR message. 3432 * Attempt to negotiate SPI-2 style. 3433 */ 3434 if (bootverbose) { 3435 printf("(%s:%c:%d:%d): PPR Rejected. " 3436 "Trying WDTR/SDTR\n", 3437 ahc_name(ahc), devinfo->channel, 3438 devinfo->target, devinfo->lun); 3439 } 3440 tinfo->goal.ppr_options = 0; 3441 tinfo->curr.transport_version = 2; 3442 tinfo->goal.transport_version = 2; 3443 ahc->msgout_index = 0; 3444 ahc->msgout_len = 0; 3445 ahc_build_transfer_msg(ahc, devinfo); 3446 ahc->msgout_index = 0; 3447 response = 1; 3448 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3449 3450 /* note 8bit xfers */ 3451 if (bootverbose) 3452 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3453 "8bit transfers\n", ahc_name(ahc), 3454 devinfo->channel, devinfo->target, devinfo->lun); 3455 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3456 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3457 /*paused*/TRUE); 3458 /* 3459 * No need to clear the sync rate. If the target 3460 * did not accept the command, our syncrate is 3461 * unaffected. If the target started the negotiation, 3462 * but rejected our response, we already cleared the 3463 * sync rate before sending our WDTR. 3464 */ 3465 if (tinfo->goal.offset != tinfo->curr.offset) { 3466 3467 /* Start the sync negotiation */ 3468 ahc->msgout_index = 0; 3469 ahc->msgout_len = 0; 3470 ahc_build_transfer_msg(ahc, devinfo); 3471 ahc->msgout_index = 0; 3472 response = 1; 3473 } 3474 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3475 /* note asynch xfers and clear flag */ 3476 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3477 /*offset*/0, /*ppr_options*/0, 3478 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3479 /*paused*/TRUE); 3480 if (bootverbose) 3481 printf("(%s:%c:%d:%d): refuses synchronous negotiation." 3482 " Using asynchronous transfers\n", 3483 ahc_name(ahc), devinfo->channel, 3484 devinfo->target, devinfo->lun); 3485 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3486 int tag_type; 3487 int mask; 3488 3489 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3490 3491 if (tag_type == MSG_SIMPLE_TASK) { 3492 if (bootverbose) 3493 printf("(%s:%c:%d:%d): refuses tagged commands." 3494 " Performing non-tagged I/O\n", 3495 ahc_name(ahc), devinfo->channel, 3496 devinfo->target, devinfo->lun); 3497 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3498 mask = ~0x23; 3499 } else { 3500 if (bootverbose) 3501 printf("(%s:%c:%d:%d): refuses %s tagged " 3502 "commands. Performing simple queue " 3503 "tagged I/O only\n", 3504 ahc_name(ahc), devinfo->channel, 3505 devinfo->target, devinfo->lun, 3506 tag_type == MSG_ORDERED_TASK 3507 ? "ordered" : "head of queue"); 3508 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3509 mask = ~0x03; 3510 } 3511 3512 /* 3513 * Resend the identify for this CCB as the target 3514 * may believe that the selection is invalid otherwise. 3515 */ 3516 ahc_outb(ahc, SCB_CONTROL, 3517 ahc_inb(ahc, SCB_CONTROL) & mask); 3518 scb->hscb->control &= mask; 3519 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3520 /*type*/MSG_SIMPLE_TASK); 3521 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3522 ahc_assert_atn(ahc); 3523 3524 /* 3525 * This transaction is now at the head of 3526 * the untagged queue for this target. 3527 */ 3528 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3529 struct scb_tailq *untagged_q; 3530 3531 untagged_q = 3532 &(ahc->untagged_queues[devinfo->target_offset]); 3533 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3534 scb->flags |= SCB_UNTAGGEDQ; 3535 } 3536 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3537 scb->hscb->tag); 3538 3539 /* 3540 * Requeue all tagged commands for this target 3541 * currently in our posession so they can be 3542 * converted to untagged commands. 3543 */ 3544 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3545 SCB_GET_CHANNEL(ahc, scb), 3546 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3547 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3548 SEARCH_COMPLETE); 3549 } else { 3550 /* 3551 * Otherwise, we ignore it. 3552 */ 3553 if (bootverbose) 3554 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3555 ahc_name(ahc), devinfo->channel, devinfo->target, 3556 last_msg); 3557 } 3558 return (response); 3559 } 3560 3561 /* 3562 * Process an ingnore wide residue message. 3563 */ 3564 static void 3565 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3566 { 3567 u_int scb_index; 3568 struct scb *scb; 3569 3570 scb_index = ahc_inb(ahc, SCB_TAG); 3571 scb = ahc_lookup_scb(ahc, scb_index); 3572 /* 3573 * XXX Actually check data direction in the sequencer? 3574 * Perhaps add datadir to some spare bits in the hscb? 3575 */ 3576 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3577 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3578 /* 3579 * Ignore the message if we haven't 3580 * seen an appropriate data phase yet. 3581 */ 3582 } else { 3583 /* 3584 * If the residual occurred on the last 3585 * transfer and the transfer request was 3586 * expected to end on an odd count, do 3587 * nothing. Otherwise, subtract a byte 3588 * and update the residual count accordingly. 3589 */ 3590 uint32_t sgptr; 3591 3592 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3593 if ((sgptr & SG_LIST_NULL) != 0 3594 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3595 /* 3596 * If the residual occurred on the last 3597 * transfer and the transfer request was 3598 * expected to end on an odd count, do 3599 * nothing. 3600 */ 3601 } else { 3602 struct ahc_dma_seg *sg; 3603 uint32_t data_cnt; 3604 uint32_t data_addr; 3605 uint32_t sglen; 3606 3607 /* Pull in the rest of the sgptr */ 3608 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3609 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3610 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3611 sgptr &= SG_PTR_MASK; 3612 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3613 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3614 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3615 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3616 3617 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3618 | (ahc_inb(ahc, SHADDR + 2) << 16) 3619 | (ahc_inb(ahc, SHADDR + 1) << 8) 3620 | (ahc_inb(ahc, SHADDR)); 3621 3622 data_cnt += 1; 3623 data_addr -= 1; 3624 3625 sg = ahc_sg_bus_to_virt(scb, sgptr); 3626 /* 3627 * The residual sg ptr points to the next S/G 3628 * to load so we must go back one. 3629 */ 3630 sg--; 3631 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3632 if (sg != scb->sg_list 3633 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3634 3635 sg--; 3636 sglen = ahc_le32toh(sg->len); 3637 /* 3638 * Preserve High Address and SG_LIST bits 3639 * while setting the count to 1. 3640 */ 3641 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3642 data_addr = ahc_le32toh(sg->addr) 3643 + (sglen & AHC_SG_LEN_MASK) - 1; 3644 3645 /* 3646 * Increment sg so it points to the 3647 * "next" sg. 3648 */ 3649 sg++; 3650 sgptr = ahc_sg_virt_to_bus(scb, sg); 3651 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3652 sgptr >> 24); 3653 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3654 sgptr >> 16); 3655 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3656 sgptr >> 8); 3657 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3658 } 3659 3660 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3661 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3662 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3663 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3664 } 3665 } 3666 } 3667 3668 3669 /* 3670 * Reinitialize the data pointers for the active transfer 3671 * based on its current residual. 3672 */ 3673 static void 3674 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3675 { 3676 struct scb *scb; 3677 struct ahc_dma_seg *sg; 3678 u_int scb_index; 3679 uint32_t sgptr; 3680 uint32_t resid; 3681 uint32_t dataptr; 3682 3683 scb_index = ahc_inb(ahc, SCB_TAG); 3684 scb = ahc_lookup_scb(ahc, scb_index); 3685 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3686 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3687 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3688 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3689 3690 sgptr &= SG_PTR_MASK; 3691 sg = ahc_sg_bus_to_virt(scb, sgptr); 3692 3693 /* The residual sg_ptr always points to the next sg */ 3694 sg--; 3695 3696 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3697 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3698 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3699 3700 dataptr = ahc_le32toh(sg->addr) 3701 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3702 - resid; 3703 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3704 u_int dscommand1; 3705 3706 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3707 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3708 ahc_outb(ahc, HADDR, 3709 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3710 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3711 } 3712 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3713 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3714 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3715 ahc_outb(ahc, HADDR, dataptr); 3716 ahc_outb(ahc, HCNT + 2, resid >> 16); 3717 ahc_outb(ahc, HCNT + 1, resid >> 8); 3718 ahc_outb(ahc, HCNT, resid); 3719 if ((ahc->features & AHC_ULTRA2) == 0) { 3720 ahc_outb(ahc, STCNT + 2, resid >> 16); 3721 ahc_outb(ahc, STCNT + 1, resid >> 8); 3722 ahc_outb(ahc, STCNT, resid); 3723 } 3724 } 3725 3726 /* 3727 * Handle the effects of issuing a bus device reset message. 3728 */ 3729 static void 3730 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3731 cam_status status, char *message, int verbose_level) 3732 { 3733 #ifdef AHC_TARGET_MODE 3734 struct ahc_tmode_tstate* tstate; 3735 u_int lun; 3736 #endif 3737 int found; 3738 3739 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3740 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3741 status); 3742 3743 #ifdef AHC_TARGET_MODE 3744 /* 3745 * Send an immediate notify ccb to all target mord peripheral 3746 * drivers affected by this action. 3747 */ 3748 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3749 if (tstate != NULL) { 3750 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3751 struct ahc_tmode_lstate* lstate; 3752 3753 lstate = tstate->enabled_luns[lun]; 3754 if (lstate == NULL) 3755 continue; 3756 3757 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3758 MSG_BUS_DEV_RESET, /*arg*/0); 3759 ahc_send_lstate_events(ahc, lstate); 3760 } 3761 } 3762 #endif 3763 3764 /* 3765 * Go back to async/narrow transfers and renegotiate. 3766 */ 3767 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3768 AHC_TRANS_CUR, /*paused*/TRUE); 3769 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3770 /*period*/0, /*offset*/0, /*ppr_options*/0, 3771 AHC_TRANS_CUR, /*paused*/TRUE); 3772 3773 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3774 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3775 3776 if (message != NULL 3777 && (verbose_level <= bootverbose)) 3778 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3779 message, devinfo->channel, devinfo->target, found); 3780 } 3781 3782 #ifdef AHC_TARGET_MODE 3783 static void 3784 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3785 struct scb *scb) 3786 { 3787 3788 /* 3789 * To facilitate adding multiple messages together, 3790 * each routine should increment the index and len 3791 * variables instead of setting them explicitly. 3792 */ 3793 ahc->msgout_index = 0; 3794 ahc->msgout_len = 0; 3795 3796 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3797 ahc_build_transfer_msg(ahc, devinfo); 3798 else 3799 panic("ahc_intr: AWAITING target message with no message"); 3800 3801 ahc->msgout_index = 0; 3802 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3803 } 3804 #endif 3805 3806 int 3807 ahc_softc_init(struct ahc_softc *ahc) 3808 { 3809 3810 /* The IRQMS bit is only valid on VL and EISA chips */ 3811 if ((ahc->chip & AHC_PCI) == 0) 3812 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3813 else 3814 ahc->unpause = 0; 3815 ahc->pause = ahc->unpause | PAUSE; 3816 /* XXX The shared scb data stuff should be deprecated */ 3817 if (ahc->scb_data == NULL) { 3818 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3819 M_DEVBUF, M_NOWAIT); 3820 if (ahc->scb_data == NULL) 3821 return (ENOMEM); 3822 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3823 } 3824 3825 return (0); 3826 } 3827 3828 void 3829 ahc_softc_insert(struct ahc_softc *ahc) 3830 { 3831 struct ahc_softc *list_ahc; 3832 3833 #if AHC_PCI_CONFIG > 0 3834 /* 3835 * Second Function PCI devices need to inherit some 3836 * settings from function 0. 3837 */ 3838 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3839 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3840 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3841 ahc_dev_softc_t list_pci; 3842 ahc_dev_softc_t pci; 3843 3844 list_pci = list_ahc->dev_softc; 3845 pci = ahc->dev_softc; 3846 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3847 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3848 struct ahc_softc *master; 3849 struct ahc_softc *slave; 3850 3851 if (ahc_get_pci_function(list_pci) == 0) { 3852 master = list_ahc; 3853 slave = ahc; 3854 } else { 3855 master = ahc; 3856 slave = list_ahc; 3857 } 3858 slave->flags &= ~AHC_BIOS_ENABLED; 3859 slave->flags |= 3860 master->flags & AHC_BIOS_ENABLED; 3861 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3862 slave->flags |= 3863 master->flags & AHC_PRIMARY_CHANNEL; 3864 break; 3865 } 3866 } 3867 } 3868 #endif 3869 3870 /* 3871 * Insertion sort into our list of softcs. 3872 */ 3873 list_ahc = TAILQ_FIRST(&ahc_tailq); 3874 while (list_ahc != NULL 3875 && ahc_softc_comp(list_ahc, ahc) <= 0) 3876 list_ahc = TAILQ_NEXT(list_ahc, links); 3877 if (list_ahc != NULL) 3878 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3879 else 3880 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3881 ahc->init_level++; 3882 } 3883 3884 /* 3885 * Verify that the passed in softc pointer is for a 3886 * controller that is still configured. 3887 */ 3888 struct ahc_softc * 3889 ahc_find_softc(struct ahc_softc *ahc) 3890 { 3891 struct ahc_softc *list_ahc; 3892 3893 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3894 if (list_ahc == ahc) 3895 return (ahc); 3896 } 3897 return (NULL); 3898 } 3899 3900 void 3901 ahc_set_unit(struct ahc_softc *ahc, int unit) 3902 { 3903 ahc->unit = unit; 3904 } 3905 3906 void 3907 ahc_set_name(struct ahc_softc *ahc, char *name) 3908 { 3909 if (ahc->name != NULL) 3910 free(ahc->name, M_DEVBUF); 3911 ahc->name = name; 3912 } 3913 3914 void 3915 ahc_free(struct ahc_softc *ahc) 3916 { 3917 int i; 3918 3919 ahc_fini_scbdata(ahc); 3920 switch (ahc->init_level) { 3921 default: 3922 case 2: 3923 ahc_shutdown(ahc); 3924 /* TAILQ_REMOVE(&ahc_tailq, ahc, links); XXX */ 3925 /* FALLTHROUGH */ 3926 case 1: 3927 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3928 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3929 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3930 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3931 break; 3932 case 0: 3933 break; 3934 } 3935 3936 ahc_platform_free(ahc); 3937 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3938 struct ahc_tmode_tstate *tstate; 3939 3940 tstate = ahc->enabled_targets[i]; 3941 if (tstate != NULL) { 3942 #if AHC_TARGET_MODE 3943 int j; 3944 3945 for (j = 0; j < AHC_NUM_LUNS; j++) { 3946 struct ahc_tmode_lstate *lstate; 3947 3948 lstate = tstate->enabled_luns[j]; 3949 if (lstate != NULL) { 3950 /*xpt_free_path(lstate->path);*/ 3951 free(lstate, M_DEVBUF); 3952 } 3953 } 3954 #endif 3955 free(tstate, M_DEVBUF); 3956 } 3957 } 3958 #if AHC_TARGET_MODE 3959 if (ahc->black_hole != NULL) { 3960 /*xpt_free_path(ahc->black_hole->path);*/ 3961 free(ahc->black_hole, M_DEVBUF); 3962 } 3963 #endif 3964 #ifndef __NetBSD__ 3965 if (ahc->name != NULL) 3966 free(ahc->name, M_DEVBUF); 3967 #endif 3968 if (ahc->seep_config != NULL) 3969 free(ahc->seep_config, M_DEVBUF); 3970 #ifndef __FreeBSD__ 3971 free(ahc, M_DEVBUF); 3972 #endif 3973 return; 3974 } 3975 3976 void 3977 ahc_shutdown(void *arg) 3978 { 3979 struct ahc_softc *ahc; 3980 int i; 3981 3982 ahc = (struct ahc_softc *)arg; 3983 3984 /* This will reset most registers to 0, but not all */ 3985 ahc_reset(ahc); 3986 ahc_outb(ahc, SCSISEQ, 0); 3987 ahc_outb(ahc, SXFRCTL0, 0); 3988 ahc_outb(ahc, DSPCISTATUS, 0); 3989 3990 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3991 ahc_outb(ahc, i, 0); 3992 } 3993 3994 /* 3995 * Reset the controller and record some information about it 3996 * that is only available just after a reset. 3997 */ 3998 int 3999 ahc_reset(struct ahc_softc *ahc) 4000 { 4001 u_int sblkctl; 4002 u_int sxfrctl1_a, sxfrctl1_b; 4003 int wait; 4004 4005 /* 4006 * Preserve the value of the SXFRCTL1 register for all channels. 4007 * It contains settings that affect termination and we don't want 4008 * to disturb the integrity of the bus. 4009 */ 4010 ahc_pause(ahc); 4011 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4012 /* 4013 * The chip has not been initialized since 4014 * PCI/EISA/VLB bus reset. Don't trust 4015 * "left over BIOS data". 4016 */ 4017 ahc->flags |= AHC_NO_BIOS_INIT; 4018 } 4019 sxfrctl1_b = 0; 4020 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4021 u_int sblkctl; 4022 4023 /* 4024 * Save channel B's settings in case this chip 4025 * is setup for TWIN channel operation. 4026 */ 4027 sblkctl = ahc_inb(ahc, SBLKCTL); 4028 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4029 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4030 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4031 } 4032 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4033 4034 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4035 4036 /* 4037 * Ensure that the reset has finished. We delay 1000us 4038 * prior to reading the register to make sure the chip 4039 * has sufficiently completed its reset to handle register 4040 * accesses. 4041 */ 4042 wait = 1000; 4043 do { 4044 ahc_delay(1000); 4045 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4046 4047 if (wait == 0) { 4048 printf("%s: WARNING - Failed chip reset! " 4049 "Trying to initialize anyway.\n", ahc_name(ahc)); 4050 } 4051 ahc_outb(ahc, HCNTRL, ahc->pause); 4052 4053 /* Determine channel configuration */ 4054 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4055 /* No Twin Channel PCI cards */ 4056 if ((ahc->chip & AHC_PCI) != 0) 4057 sblkctl &= ~SELBUSB; 4058 switch (sblkctl) { 4059 case 0: 4060 /* Single Narrow Channel */ 4061 break; 4062 case 2: 4063 /* Wide Channel */ 4064 ahc->features |= AHC_WIDE; 4065 break; 4066 case 8: 4067 /* Twin Channel */ 4068 ahc->features |= AHC_TWIN; 4069 break; 4070 default: 4071 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4072 return(-1); 4073 } 4074 4075 /* 4076 * Reload sxfrctl1. 4077 * 4078 * We must always initialize STPWEN to 1 before we 4079 * restore the saved values. STPWEN is initialized 4080 * to a tri-state condition which can only be cleared 4081 * by turning it on. 4082 */ 4083 if ((ahc->features & AHC_TWIN) != 0) { 4084 u_int sblkctl; 4085 4086 sblkctl = ahc_inb(ahc, SBLKCTL); 4087 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4088 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4089 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4090 } 4091 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4092 4093 #ifdef AHC_DUMP_SEQ 4094 if (ahc->init_level == 0) 4095 ahc_dumpseq(ahc); 4096 #endif 4097 4098 return (0); 4099 } 4100 4101 /* 4102 * Determine the number of SCBs available on the controller 4103 */ 4104 int 4105 ahc_probe_scbs(struct ahc_softc *ahc) { 4106 int i; 4107 4108 for (i = 0; i < AHC_SCB_MAX; i++) { 4109 4110 ahc_outb(ahc, SCBPTR, i); 4111 ahc_outb(ahc, SCB_BASE, i); 4112 if (ahc_inb(ahc, SCB_BASE) != i) 4113 break; 4114 ahc_outb(ahc, SCBPTR, 0); 4115 if (ahc_inb(ahc, SCB_BASE) != 0) 4116 break; 4117 } 4118 return (i); 4119 } 4120 4121 #if 0 4122 static void 4123 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4124 { 4125 bus_addr_t *baddr; 4126 4127 baddr = (bus_addr_t *)arg; 4128 *baddr = segs->ds_addr; 4129 } 4130 #endif 4131 4132 static void 4133 ahc_build_free_scb_list(struct ahc_softc *ahc) 4134 { 4135 int scbsize; 4136 int i; 4137 4138 scbsize = 32; 4139 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4140 scbsize = 64; 4141 4142 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4143 int j; 4144 4145 ahc_outb(ahc, SCBPTR, i); 4146 4147 /* 4148 * Touch all SCB bytes to avoid parity errors 4149 * should one of our debugging routines read 4150 * an otherwise uninitiatlized byte. 4151 */ 4152 for (j = 0; j < scbsize; j++) 4153 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4154 4155 /* Clear the control byte. */ 4156 ahc_outb(ahc, SCB_CONTROL, 0); 4157 4158 /* Set the next pointer */ 4159 if ((ahc->flags & AHC_PAGESCBS) != 0) 4160 ahc_outb(ahc, SCB_NEXT, i+1); 4161 else 4162 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4163 4164 /* Make the tag number, SCSIID, and lun invalid */ 4165 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4166 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4167 ahc_outb(ahc, SCB_LUN, 0xFF); 4168 } 4169 4170 /* Make sure that the last SCB terminates the free list */ 4171 ahc_outb(ahc, SCBPTR, i-1); 4172 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4173 } 4174 4175 static int 4176 ahc_init_scbdata(struct ahc_softc *ahc) 4177 { 4178 struct scb_data *scb_data; 4179 4180 scb_data = ahc->scb_data; 4181 SLIST_INIT(&scb_data->free_scbs); 4182 SLIST_INIT(&scb_data->sg_maps); 4183 4184 /* Allocate SCB resources */ 4185 scb_data->scbarray = 4186 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4187 M_DEVBUF, M_NOWAIT); 4188 if (scb_data->scbarray == NULL) 4189 return (ENOMEM); 4190 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4191 4192 /* Determine the number of hardware SCBs and initialize them */ 4193 4194 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4195 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4196 /* SCB 0 heads the free list */ 4197 ahc_outb(ahc, FREE_SCBH, 0); 4198 } else { 4199 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4200 } 4201 4202 if (ahc->scb_data->maxhscbs == 0) { 4203 printf("%s: No SCB space found\n", ahc_name(ahc)); 4204 return (ENXIO); 4205 } 4206 4207 ahc_build_free_scb_list(ahc); 4208 4209 /* 4210 * Create our DMA tags. These tags define the kinds of device 4211 * accessible memory allocations and memory mappings we will 4212 * need to perform during normal operation. 4213 * 4214 * Unless we need to further restrict the allocation, we rely 4215 * on the restrictions of the parent dmat, hence the common 4216 * use of MAXADDR and MAXSIZE. 4217 */ 4218 4219 if (ahc_createdmamem(ahc->parent_dmat, 4220 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4221 &scb_data->hscb_dmamap, 4222 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4223 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4224 "hardware SCB structures") < 0) 4225 goto error_exit; 4226 4227 scb_data->init_level++; 4228 4229 if (ahc_createdmamem(ahc->parent_dmat, 4230 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 4231 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4232 &scb_data->sense_busaddr, &scb_data->sense_seg, 4233 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4234 goto error_exit; 4235 4236 scb_data->init_level++; 4237 4238 /* Perform initial CCB allocation */ 4239 memset(scb_data->hscbs, 0, 4240 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4241 ahc_alloc_scbs(ahc); 4242 scb_data->init_level++; 4243 4244 if (scb_data->numscbs == 0) { 4245 printf("%s: ahc_init_scbdata - " 4246 "Unable to allocate initial scbs\n", 4247 ahc_name(ahc)); 4248 goto error_exit; 4249 } 4250 4251 /* 4252 * Tell the sequencer which SCB will be the next one it receives. 4253 */ 4254 ahc->next_queued_scb = ahc_get_scb(ahc); 4255 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4256 4257 /* 4258 * Note that we were successfull 4259 */ 4260 return (0); 4261 4262 error_exit: 4263 4264 return (ENOMEM); 4265 } 4266 4267 static void 4268 ahc_fini_scbdata(struct ahc_softc *ahc) 4269 { 4270 struct scb_data *scb_data; 4271 4272 scb_data = ahc->scb_data; 4273 if (scb_data == NULL) 4274 return; 4275 4276 switch (scb_data->init_level) { 4277 default: 4278 case 5: 4279 { 4280 struct sg_map_node *sg_map; 4281 4282 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4283 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4284 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4285 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4286 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4287 free(sg_map, M_DEVBUF); 4288 } 4289 } 4290 /*FALLTHROUGH*/ 4291 case 4: 4292 ahc_freedmamem(ahc->parent_dmat, 4293 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 4294 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4295 &scb_data->sense_seg, scb_data->sense_nseg); 4296 /*FALLTHROUGH*/ 4297 case 3: 4298 ahc_freedmamem(ahc->parent_dmat, 4299 AHC_SCB_MAX * sizeof(struct hardware_scb), 4300 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4301 &scb_data->hscb_seg, scb_data->hscb_nseg); 4302 /*FALLTHROUGH*/ 4303 case 2: 4304 case 1: 4305 case 0: 4306 break; 4307 } 4308 if (scb_data->scbarray != NULL) 4309 free(scb_data->scbarray, M_DEVBUF); 4310 } 4311 4312 void 4313 ahc_alloc_scbs(struct ahc_softc *ahc) 4314 { 4315 struct scb_data *scb_data; 4316 struct scb *next_scb; 4317 struct sg_map_node *sg_map; 4318 bus_addr_t physaddr; 4319 struct ahc_dma_seg *segs; 4320 int newcount; 4321 int i; 4322 4323 scb_data = ahc->scb_data; 4324 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4325 /* Can't allocate any more */ 4326 return; 4327 4328 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4329 4330 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4331 4332 if (sg_map == NULL) 4333 return; 4334 4335 /* Allocate S/G space for the next batch of SCBS */ 4336 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4337 &sg_map->sg_dmamap, 4338 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4339 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4340 "SG space") < 0) { 4341 free(sg_map, M_DEVBUF); 4342 return; 4343 } 4344 4345 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4346 4347 segs = sg_map->sg_vaddr; 4348 physaddr = sg_map->sg_physaddr; 4349 4350 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4351 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4352 for (i = 0; i < newcount; i++) { 4353 struct scb_platform_data *pdata; 4354 int error; 4355 4356 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4357 M_DEVBUF, M_NOWAIT); 4358 if (pdata == NULL) 4359 break; 4360 next_scb->platform_data = pdata; 4361 next_scb->sg_map = sg_map; 4362 next_scb->sg_list = segs; 4363 /* 4364 * The sequencer always starts with the second entry. 4365 * The first entry is embedded in the scb. 4366 */ 4367 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4368 next_scb->ahc_softc = ahc; 4369 next_scb->flags = SCB_FREE; 4370 4371 error = bus_dmamap_create(ahc->parent_dmat, 4372 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0, 4373 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 4374 &next_scb->dmamap); 4375 if (error != 0) 4376 break; 4377 4378 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4379 next_scb->hscb->tag = ahc->scb_data->numscbs; 4380 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4381 next_scb, links.sle); 4382 segs += AHC_NSEG; 4383 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4384 next_scb++; 4385 ahc->scb_data->numscbs++; 4386 } 4387 } 4388 4389 void 4390 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4391 { 4392 int len; 4393 4394 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4395 buf += len; 4396 if ((ahc->features & AHC_TWIN) != 0) 4397 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4398 "B SCSI Id=%d, primary %c, ", 4399 ahc->our_id, ahc->our_id_b, 4400 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4401 else { 4402 const char *speed; 4403 const char *type; 4404 4405 speed = ""; 4406 if ((ahc->features & AHC_ULTRA) != 0) { 4407 speed = "Ultra "; 4408 } else if ((ahc->features & AHC_DT) != 0) { 4409 speed = "Ultra160 "; 4410 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4411 speed = "Ultra2 "; 4412 } 4413 if ((ahc->features & AHC_WIDE) != 0) { 4414 type = "Wide"; 4415 } else { 4416 type = "Single"; 4417 } 4418 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4419 speed, type, ahc->channel, ahc->our_id); 4420 } 4421 buf += len; 4422 4423 if ((ahc->flags & AHC_PAGESCBS) != 0) 4424 sprintf(buf, "%d/%d SCBs", 4425 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4426 else 4427 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4428 } 4429 4430 /* 4431 * Start the board, ready for normal operation 4432 */ 4433 int 4434 ahc_init(struct ahc_softc *ahc) 4435 { 4436 int max_targ; 4437 int i; 4438 int term; 4439 u_int scsi_conf; 4440 u_int scsiseq_template; 4441 u_int ultraenb; 4442 u_int discenable; 4443 u_int tagenable; 4444 size_t driver_data_size; 4445 uint32_t physaddr; 4446 4447 #ifdef AHC_DEBUG 4448 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4449 ahc->flags |= AHC_SEQUENCER_DEBUG; 4450 #endif 4451 4452 #ifdef AHC_PRINT_SRAM 4453 printf("Scratch Ram:"); 4454 for (i = 0x20; i < 0x5f; i++) { 4455 if (((i % 8) == 0) && (i != 0)) { 4456 printf ("\n "); 4457 } 4458 printf (" 0x%x", ahc_inb(ahc, i)); 4459 } 4460 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4461 for (i = 0x70; i < 0x7f; i++) { 4462 if (((i % 8) == 0) && (i != 0)) { 4463 printf ("\n "); 4464 } 4465 printf (" 0x%x", ahc_inb(ahc, i)); 4466 } 4467 } 4468 printf ("\n"); 4469 /* 4470 * Reading uninitialized scratch ram may 4471 * generate parity errors. 4472 */ 4473 ahc_outb(ahc, CLRINT, CLRPARERR); 4474 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4475 #endif 4476 max_targ = 15; 4477 4478 /* 4479 * Assume we have a board at this stage and it has been reset. 4480 */ 4481 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4482 ahc->our_id = ahc->our_id_b = 7; 4483 4484 /* 4485 * Default to allowing initiator operations. 4486 */ 4487 ahc->flags |= AHC_INITIATORROLE; 4488 4489 /* 4490 * Only allow target mode features if this unit has them enabled. 4491 */ 4492 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4493 ahc->features &= ~AHC_TARGETMODE; 4494 4495 /* 4496 * DMA tag for our command fifos and other data in system memory 4497 * the card's sequencer must be able to access. For initiator 4498 * roles, we need to allocate space for the qinfifo and qoutfifo. 4499 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4500 * When providing for the target mode role, we must additionally 4501 * provide space for the incoming target command fifo and an extra 4502 * byte to deal with a DMA bug in some chip versions. 4503 */ 4504 driver_data_size = 2 * 256 * sizeof(uint8_t); 4505 if ((ahc->features & AHC_TARGETMODE) != 0) 4506 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4507 + /*DMA WideOdd Bug Buffer*/1; 4508 4509 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4510 ahc->sc_dmaflags, 4511 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4512 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4513 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4514 return (ENOMEM); 4515 4516 ahc->init_level++; 4517 4518 if ((ahc->features & AHC_TARGETMODE) != 0) { 4519 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4520 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4521 ahc->dma_bug_buf = ahc->shared_data_busaddr 4522 + driver_data_size - 1; 4523 /* All target command blocks start out invalid. */ 4524 for (i = 0; i < AHC_TMODE_CMDS; i++) 4525 ahc->targetcmds[i].cmd_valid = 0; 4526 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4527 ahc->tqinfifonext = 1; 4528 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4529 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4530 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4531 } 4532 ahc->qinfifo = &ahc->qoutfifo[256]; 4533 4534 ahc->init_level++; 4535 4536 /* Allocate SCB data now that buffer_dmat is initialized */ 4537 if (ahc->scb_data->maxhscbs == 0) 4538 if (ahc_init_scbdata(ahc) != 0) 4539 return (ENOMEM); 4540 4541 if (bootverbose) 4542 printf("%s: found %d SCBs\n", ahc_name(ahc), 4543 ahc->scb_data->maxhscbs); 4544 4545 /* 4546 * Allocate a tstate to house information for our 4547 * initiator presence on the bus as well as the user 4548 * data for any target mode initiator. 4549 */ 4550 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4551 printf("%s: unable to allocate ahc_tmode_tstate. " 4552 "Failing attach\n", ahc_name(ahc)); 4553 return (ENOMEM); 4554 } 4555 4556 if ((ahc->features & AHC_TWIN) != 0) { 4557 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4558 printf("%s: unable to allocate ahc_tmode_tstate. " 4559 "Failing attach\n", ahc_name(ahc)); 4560 return (ENOMEM); 4561 } 4562 } 4563 4564 ahc_outb(ahc, SEQ_FLAGS, 0); 4565 ahc_outb(ahc, SEQ_FLAGS2, 0); 4566 4567 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4568 ahc->flags |= AHC_PAGESCBS; 4569 } else { 4570 ahc->flags &= ~AHC_PAGESCBS; 4571 } 4572 4573 #ifdef AHC_DEBUG 4574 if (ahc_debug & AHC_SHOW_MISC) { 4575 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 4576 "ahc_dma %lu bytes\n", 4577 ahc_name(ahc), 4578 (u_long)sizeof(struct hardware_scb), 4579 (u_long)sizeof(struct scb), 4580 (u_long)sizeof(struct ahc_dma_seg)); 4581 } 4582 #endif /* AHC_DEBUG */ 4583 4584 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4585 if (ahc->features & AHC_TWIN) { 4586 4587 /* 4588 * The device is gated to channel B after a chip reset, 4589 * so set those values first 4590 */ 4591 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4592 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4593 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4594 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4595 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4596 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4597 if ((ahc->features & AHC_ULTRA2) != 0) 4598 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4599 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4600 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4601 4602 if ((scsi_conf & RESET_SCSI) != 0 4603 && (ahc->flags & AHC_INITIATORROLE) != 0) 4604 ahc->flags |= AHC_RESET_BUS_B; 4605 4606 /* Select Channel A */ 4607 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4608 } 4609 4610 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4611 if ((ahc->features & AHC_ULTRA2) != 0) 4612 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4613 else 4614 ahc_outb(ahc, SCSIID, ahc->our_id); 4615 scsi_conf = ahc_inb(ahc, SCSICONF); 4616 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4617 |term|ahc->seltime 4618 |ENSTIMER|ACTNEGEN); 4619 if ((ahc->features & AHC_ULTRA2) != 0) 4620 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4621 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4622 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4623 4624 if ((scsi_conf & RESET_SCSI) != 0 4625 && (ahc->flags & AHC_INITIATORROLE) != 0) 4626 ahc->flags |= AHC_RESET_BUS_A; 4627 4628 /* 4629 * Look at the information that board initialization or 4630 * the board bios has left us. 4631 */ 4632 ultraenb = 0; 4633 tagenable = ALL_TARGETS_MASK; 4634 4635 /* Grab the disconnection disable table and invert it for our needs */ 4636 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4637 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4638 "device parameters\n", ahc_name(ahc)); 4639 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4640 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4641 discenable = ALL_TARGETS_MASK; 4642 if ((ahc->features & AHC_ULTRA) != 0) 4643 ultraenb = ALL_TARGETS_MASK; 4644 } else { 4645 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4646 | ahc_inb(ahc, DISC_DSB)); 4647 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4648 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4649 | ahc_inb(ahc, ULTRA_ENB); 4650 } 4651 4652 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4653 max_targ = 7; 4654 4655 for (i = 0; i <= max_targ; i++) { 4656 struct ahc_initiator_tinfo *tinfo; 4657 struct ahc_tmode_tstate *tstate; 4658 u_int our_id; 4659 u_int target_id; 4660 char channel; 4661 4662 channel = 'A'; 4663 our_id = ahc->our_id; 4664 target_id = i; 4665 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4666 channel = 'B'; 4667 our_id = ahc->our_id_b; 4668 target_id = i % 8; 4669 } 4670 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4671 target_id, &tstate); 4672 /* Default to async narrow across the board */ 4673 memset(tinfo, 0, sizeof(*tinfo)); 4674 if (ahc->flags & AHC_USEDEFAULTS) { 4675 if ((ahc->features & AHC_WIDE) != 0) 4676 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4677 4678 /* 4679 * These will be truncated when we determine the 4680 * connection type we have with the target. 4681 */ 4682 tinfo->user.period = ahc_syncrates->period; 4683 tinfo->user.offset = ~0; 4684 } else { 4685 u_int scsirate; 4686 uint16_t mask; 4687 4688 /* Take the settings leftover in scratch RAM. */ 4689 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4690 mask = (0x01 << i); 4691 if ((ahc->features & AHC_ULTRA2) != 0) { 4692 u_int offset; 4693 u_int maxsync; 4694 4695 if ((scsirate & SOFS) == 0x0F) { 4696 /* 4697 * Haven't negotiated yet, 4698 * so the format is different. 4699 */ 4700 scsirate = (scsirate & SXFR) >> 4 4701 | (ultraenb & mask) 4702 ? 0x08 : 0x0 4703 | (scsirate & WIDEXFER); 4704 offset = MAX_OFFSET_ULTRA2; 4705 } else 4706 offset = ahc_inb(ahc, TARG_OFFSET + i); 4707 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4708 /* Set to the lowest sync rate, 5MHz */ 4709 scsirate |= 0x1c; 4710 maxsync = AHC_SYNCRATE_ULTRA2; 4711 if ((ahc->features & AHC_DT) != 0) 4712 maxsync = AHC_SYNCRATE_DT; 4713 tinfo->user.period = 4714 ahc_find_period(ahc, scsirate, maxsync); 4715 if (offset == 0) 4716 tinfo->user.period = 0; 4717 else 4718 tinfo->user.offset = ~0; 4719 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4720 && (ahc->features & AHC_DT) != 0) 4721 tinfo->user.ppr_options = 4722 MSG_EXT_PPR_DT_REQ; 4723 } else if ((scsirate & SOFS) != 0) { 4724 if ((scsirate & SXFR) == 0x40 4725 && (ultraenb & mask) != 0) { 4726 /* Treat 10MHz as a non-ultra speed */ 4727 scsirate &= ~SXFR; 4728 ultraenb &= ~mask; 4729 } 4730 tinfo->user.period = 4731 ahc_find_period(ahc, scsirate, 4732 (ultraenb & mask) 4733 ? AHC_SYNCRATE_ULTRA 4734 : AHC_SYNCRATE_FAST); 4735 if (tinfo->user.period != 0) 4736 tinfo->user.offset = ~0; 4737 } 4738 if (tinfo->user.period == 0) 4739 tinfo->user.offset = 0; 4740 if ((scsirate & WIDEXFER) != 0 4741 && (ahc->features & AHC_WIDE) != 0) 4742 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4743 tinfo->user.protocol_version = 4; 4744 if ((ahc->features & AHC_DT) != 0) 4745 tinfo->user.transport_version = 3; 4746 else 4747 tinfo->user.transport_version = 2; 4748 tinfo->goal.protocol_version = 2; 4749 tinfo->goal.transport_version = 2; 4750 tinfo->curr.protocol_version = 2; 4751 tinfo->curr.transport_version = 2; 4752 } 4753 tstate->ultraenb = 0; 4754 tstate->discenable = discenable; 4755 } 4756 ahc->user_discenable = discenable; 4757 ahc->user_tagenable = tagenable; 4758 4759 /* There are no untagged SCBs active yet. */ 4760 for (i = 0; i < 16; i++) { 4761 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4762 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4763 int lun; 4764 4765 /* 4766 * The SCB based BTT allows an entry per 4767 * target and lun pair. 4768 */ 4769 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4770 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4771 } 4772 } 4773 4774 /* All of our queues are empty */ 4775 for (i = 0; i < 256; i++) 4776 ahc->qoutfifo[i] = SCB_LIST_NULL; 4777 4778 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4779 4780 for (i = 0; i < 256; i++) 4781 ahc->qinfifo[i] = SCB_LIST_NULL; 4782 4783 if ((ahc->features & AHC_MULTI_TID) != 0) { 4784 ahc_outb(ahc, TARGID, 0); 4785 ahc_outb(ahc, TARGID + 1, 0); 4786 } 4787 4788 /* 4789 * Tell the sequencer where it can find our arrays in memory. 4790 */ 4791 physaddr = ahc->scb_data->hscb_busaddr; 4792 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4793 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4794 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4795 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4796 4797 physaddr = ahc->shared_data_busaddr; 4798 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4799 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4800 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4801 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4802 4803 /* 4804 * Initialize the group code to command length table. 4805 * This overrides the values in TARG_SCSIRATE, so only 4806 * setup the table after we have processed that information. 4807 */ 4808 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4809 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4810 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4811 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4812 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4813 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4814 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4815 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4816 4817 /* Tell the sequencer of our initial queue positions */ 4818 ahc_outb(ahc, KERNEL_QINPOS, 0); 4819 ahc_outb(ahc, QINPOS, 0); 4820 ahc_outb(ahc, QOUTPOS, 0); 4821 4822 /* 4823 * Use the built in queue management registers 4824 * if they are available. 4825 */ 4826 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4827 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4828 ahc_outb(ahc, SDSCB_QOFF, 0); 4829 ahc_outb(ahc, SNSCB_QOFF, 0); 4830 ahc_outb(ahc, HNSCB_QOFF, 0); 4831 } 4832 4833 4834 /* We don't have any waiting selections */ 4835 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4836 4837 /* Our disconnection list is empty too */ 4838 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4839 4840 /* Message out buffer starts empty */ 4841 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4842 4843 /* 4844 * Setup the allowed SCSI Sequences based on operational mode. 4845 * If we are a target, we'll enalbe select in operations once 4846 * we've had a lun enabled. 4847 */ 4848 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4849 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4850 scsiseq_template |= ENRSELI; 4851 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4852 4853 /* 4854 * Load the Sequencer program and Enable the adapter 4855 * in "fast" mode. 4856 */ 4857 if (bootverbose) 4858 printf("%s: Downloading Sequencer Program...", 4859 ahc_name(ahc)); 4860 4861 ahc_loadseq(ahc); 4862 4863 if ((ahc->features & AHC_ULTRA2) != 0) { 4864 int wait; 4865 4866 /* 4867 * Wait for up to 500ms for our transceivers 4868 * to settle. If the adapter does not have 4869 * a cable attached, the tranceivers may 4870 * never settle, so don't complain if we 4871 * fail here. 4872 */ 4873 ahc_pause(ahc); 4874 for (wait = 5000; 4875 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4876 wait--) 4877 ahc_delay(100); 4878 ahc_unpause(ahc); 4879 } 4880 4881 /* We have to wait until after any system dumps... */ 4882 ahc->shutdown_hook = shutdownhook_establish(ahc_shutdown, ahc); 4883 4884 return (0); 4885 } 4886 4887 void 4888 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4889 { 4890 u_int hcntrl; 4891 4892 hcntrl = ahc_inb(ahc, HCNTRL); 4893 hcntrl &= ~INTEN; 4894 ahc->pause &= ~INTEN; 4895 ahc->unpause &= ~INTEN; 4896 if (enable) { 4897 hcntrl |= INTEN; 4898 ahc->pause |= INTEN; 4899 ahc->unpause |= INTEN; 4900 } 4901 ahc_outb(ahc, HCNTRL, hcntrl); 4902 } 4903 4904 /* 4905 * Ensure that the card is paused in a location 4906 * outside of all critical sections and that all 4907 * pending work is completed prior to returning. 4908 * This routine should only be called from outside 4909 * an interrupt context. 4910 */ 4911 void 4912 ahc_pause_and_flushwork(struct ahc_softc *ahc) 4913 { 4914 int intstat; 4915 int maxloops; 4916 int paused; 4917 4918 maxloops = 1000; 4919 ahc->flags |= AHC_ALL_INTERRUPTS; 4920 intstat = 0; 4921 paused = FALSE; 4922 do { 4923 if (paused) 4924 ahc_unpause(ahc); 4925 ahc_intr(ahc); 4926 ahc_pause(ahc); 4927 paused = TRUE; 4928 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 4929 ahc_clear_critical_section(ahc); 4930 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4931 break; 4932 } while (--maxloops 4933 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0 4934 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)))); 4935 if (maxloops == 0) { 4936 printf("Infinite interrupt loop, INTSTAT = %x", 4937 ahc_inb(ahc, INTSTAT)); 4938 } 4939 ahc_platform_flushwork(ahc); 4940 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4941 } 4942 4943 int 4944 ahc_suspend(struct ahc_softc *ahc) 4945 { 4946 uint8_t *ptr; 4947 int i; 4948 4949 ahc_pause_and_flushwork(ahc); 4950 4951 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4952 return (EBUSY); 4953 4954 #if AHC_TARGET_MODE 4955 /* 4956 * XXX What about ATIOs that have not yet been serviced? 4957 * Perhaps we should just refuse to be suspended if we 4958 * are acting in a target role. 4959 */ 4960 if (ahc->pending_device != NULL) 4961 return (EBUSY); 4962 #endif 4963 4964 /* Save volatile registers */ 4965 if ((ahc->features & AHC_TWIN) != 0) { 4966 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4967 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4968 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4969 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4970 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4971 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4972 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4973 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4974 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4975 } 4976 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4977 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4978 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4979 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4980 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4981 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4982 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4983 4984 if ((ahc->chip & AHC_PCI) != 0) { 4985 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4986 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4987 } 4988 4989 if ((ahc->features & AHC_DT) != 0) { 4990 u_int sfunct; 4991 4992 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4993 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4994 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4995 ahc_outb(ahc, SFUNCT, sfunct); 4996 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4997 } 4998 4999 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5000 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 5001 5002 if ((ahc->features & AHC_ULTRA2) != 0) 5003 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 5004 5005 ptr = ahc->suspend_state.scratch_ram; 5006 for (i = 0; i < 64; i++) 5007 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 5008 5009 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5010 for (i = 0; i < 16; i++) 5011 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 5012 } 5013 5014 ptr = ahc->suspend_state.btt; 5015 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5016 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5017 int j; 5018 5019 for (j = 0;j < AHC_NUM_LUNS; j++) { 5020 u_int tcl; 5021 5022 tcl = BUILD_TCL(i << 4, j); 5023 *ptr = ahc_index_busy_tcl(ahc, tcl); 5024 } 5025 } 5026 } 5027 ahc_shutdown(ahc); 5028 return (0); 5029 } 5030 5031 int 5032 ahc_resume(struct ahc_softc *ahc) 5033 { 5034 uint8_t *ptr; 5035 int i; 5036 5037 ahc_reset(ahc); 5038 5039 ahc_build_free_scb_list(ahc); 5040 5041 /* Restore volatile registers */ 5042 if ((ahc->features & AHC_TWIN) != 0) { 5043 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5044 ahc_outb(ahc, SCSIID, ahc->our_id); 5045 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 5046 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 5047 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 5048 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 5049 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 5050 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 5051 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 5052 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5053 } 5054 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 5055 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 5056 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 5057 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 5058 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 5059 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 5060 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 5061 if ((ahc->features & AHC_ULTRA2) != 0) 5062 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5063 else 5064 ahc_outb(ahc, SCSIID, ahc->our_id); 5065 5066 if ((ahc->chip & AHC_PCI) != 0) { 5067 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 5068 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 5069 } 5070 5071 if ((ahc->features & AHC_DT) != 0) { 5072 u_int sfunct; 5073 5074 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 5075 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 5076 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 5077 ahc_outb(ahc, SFUNCT, sfunct); 5078 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 5079 } 5080 5081 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5082 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 5083 5084 if ((ahc->features & AHC_ULTRA2) != 0) 5085 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 5086 5087 ptr = ahc->suspend_state.scratch_ram; 5088 for (i = 0; i < 64; i++) 5089 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 5090 5091 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5092 for (i = 0; i < 16; i++) 5093 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 5094 } 5095 5096 ptr = ahc->suspend_state.btt; 5097 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5098 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5099 int j; 5100 5101 for (j = 0;j < AHC_NUM_LUNS; j++) { 5102 u_int tcl; 5103 5104 tcl = BUILD_TCL(i << 4, j); 5105 ahc_busy_tcl(ahc, tcl, *ptr); 5106 } 5107 } 5108 } 5109 return (0); 5110 } 5111 5112 /************************** Busy Target Table *********************************/ 5113 /* 5114 * Return the untagged transaction id for a given target/channel lun. 5115 * Optionally, clear the entry. 5116 */ 5117 u_int 5118 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5119 { 5120 u_int scbid; 5121 u_int target_offset; 5122 5123 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5124 u_int saved_scbptr; 5125 5126 saved_scbptr = ahc_inb(ahc, SCBPTR); 5127 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5128 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5129 ahc_outb(ahc, SCBPTR, saved_scbptr); 5130 } else { 5131 target_offset = TCL_TARGET_OFFSET(tcl); 5132 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5133 } 5134 5135 return (scbid); 5136 } 5137 5138 void 5139 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5140 { 5141 u_int target_offset; 5142 5143 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5144 u_int saved_scbptr; 5145 5146 saved_scbptr = ahc_inb(ahc, SCBPTR); 5147 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5148 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5149 ahc_outb(ahc, SCBPTR, saved_scbptr); 5150 } else { 5151 target_offset = TCL_TARGET_OFFSET(tcl); 5152 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5153 } 5154 } 5155 5156 void 5157 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5158 { 5159 u_int target_offset; 5160 5161 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5162 u_int saved_scbptr; 5163 5164 saved_scbptr = ahc_inb(ahc, SCBPTR); 5165 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5166 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5167 ahc_outb(ahc, SCBPTR, saved_scbptr); 5168 } else { 5169 target_offset = TCL_TARGET_OFFSET(tcl); 5170 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5171 } 5172 } 5173 5174 /************************** SCB and SCB queue management **********************/ 5175 int 5176 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5177 char channel, int lun, u_int tag, role_t role) 5178 { 5179 int targ = SCB_GET_TARGET(ahc, scb); 5180 char chan = SCB_GET_CHANNEL(ahc, scb); 5181 int slun = SCB_GET_LUN(scb); 5182 int match; 5183 5184 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5185 if (match != 0) 5186 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5187 if (match != 0) 5188 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5189 if (match != 0) { 5190 #if 0 5191 #if AHC_TARGET_MODE 5192 int group; 5193 5194 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5195 if (role == ROLE_INITIATOR) { 5196 match = (group != XPT_FC_GROUP_TMODE) 5197 && ((tag == scb->hscb->tag) 5198 || (tag == SCB_LIST_NULL)); 5199 } else if (role == ROLE_TARGET) { 5200 match = (group == XPT_FC_GROUP_TMODE) 5201 && ((tag == scb->io_ctx->csio.tag_id) 5202 || (tag == SCB_LIST_NULL)); 5203 } 5204 #else /* !AHC_TARGET_MODE */ 5205 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5206 #endif /* AHC_TARGET_MODE */ 5207 #endif 5208 } 5209 5210 return match; 5211 } 5212 5213 void 5214 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5215 { 5216 int target; 5217 char channel; 5218 int lun; 5219 5220 target = SCB_GET_TARGET(ahc, scb); 5221 lun = SCB_GET_LUN(scb); 5222 channel = SCB_GET_CHANNEL(ahc, scb); 5223 5224 ahc_search_qinfifo(ahc, target, channel, lun, 5225 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5226 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5227 5228 ahc_platform_freeze_devq(ahc, scb); 5229 } 5230 5231 void 5232 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5233 { 5234 struct scb *prev_scb; 5235 5236 prev_scb = NULL; 5237 if (ahc_qinfifo_count(ahc) != 0) { 5238 u_int prev_tag; 5239 uint8_t prev_pos; 5240 5241 prev_pos = ahc->qinfifonext - 1; 5242 prev_tag = ahc->qinfifo[prev_pos]; 5243 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5244 } 5245 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5246 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5247 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5248 } else { 5249 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5250 } 5251 } 5252 5253 static void 5254 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5255 struct scb *scb) 5256 { 5257 if (prev_scb == NULL) { 5258 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5259 } else { 5260 prev_scb->hscb->next = scb->hscb->tag; 5261 ahc_sync_scb(ahc, prev_scb, 5262 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5263 } 5264 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5265 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5266 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5267 } 5268 5269 static int 5270 ahc_qinfifo_count(struct ahc_softc *ahc) 5271 { 5272 uint8_t qinpos; 5273 uint8_t diff; 5274 5275 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5276 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5277 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5278 } else 5279 qinpos = ahc_inb(ahc, QINPOS); 5280 diff = ahc->qinfifonext - qinpos; 5281 return (diff); 5282 } 5283 5284 int 5285 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5286 int lun, u_int tag, role_t role, uint32_t status, 5287 ahc_search_action action) 5288 { 5289 struct scb *scb; 5290 struct scb *prev_scb; 5291 uint8_t qinstart; 5292 uint8_t qinpos; 5293 uint8_t qintail; 5294 uint8_t next; 5295 uint8_t prev; 5296 uint8_t curscbptr; 5297 int found; 5298 int have_qregs; 5299 5300 qintail = ahc->qinfifonext; 5301 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5302 if (have_qregs) { 5303 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5304 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5305 } else 5306 qinstart = ahc_inb(ahc, QINPOS); 5307 qinpos = qinstart; 5308 found = 0; 5309 prev_scb = NULL; 5310 5311 if (action == SEARCH_COMPLETE) { 5312 /* 5313 * Don't attempt to run any queued untagged transactions 5314 * until we are done with the abort process. 5315 */ 5316 ahc_freeze_untagged_queues(ahc); 5317 } 5318 5319 /* 5320 * Start with an empty queue. Entries that are not chosen 5321 * for removal will be re-added to the queue as we go. 5322 */ 5323 ahc->qinfifonext = qinpos; 5324 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5325 5326 while (qinpos != qintail) { 5327 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5328 if (scb == NULL) { 5329 printf("qinpos = %d, SCB index = %d\n", 5330 qinpos, ahc->qinfifo[qinpos]); 5331 panic("Loop 1\n"); 5332 } 5333 5334 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5335 /* 5336 * We found an scb that needs to be acted on. 5337 */ 5338 found++; 5339 switch (action) { 5340 case SEARCH_COMPLETE: 5341 { 5342 cam_status ostat; 5343 cam_status cstat; 5344 5345 ostat = ahc_get_transaction_status(scb); 5346 if (ostat == CAM_REQ_INPROG) 5347 ahc_set_transaction_status(scb, status); 5348 cstat = ahc_get_transaction_status(scb); 5349 if (cstat != CAM_REQ_CMP) 5350 ahc_freeze_scb(scb); 5351 if ((scb->flags & SCB_ACTIVE) == 0) 5352 printf("Inactive SCB in qinfifo\n"); 5353 ahc_done(ahc, scb); 5354 5355 /* FALLTHROUGH */ 5356 } 5357 case SEARCH_REMOVE: 5358 break; 5359 case SEARCH_COUNT: 5360 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5361 prev_scb = scb; 5362 break; 5363 } 5364 } else { 5365 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5366 prev_scb = scb; 5367 } 5368 qinpos++; 5369 } 5370 5371 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5372 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5373 } else { 5374 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5375 } 5376 5377 if (action != SEARCH_COUNT 5378 && (found != 0) 5379 && (qinstart != ahc->qinfifonext)) { 5380 /* 5381 * The sequencer may be in the process of DMA'ing 5382 * down the SCB at the beginning of the queue. 5383 * This could be problematic if either the first, 5384 * or the second SCB is removed from the queue 5385 * (the first SCB includes a pointer to the "next" 5386 * SCB to DMA). If we have removed any entries, swap 5387 * the first element in the queue with the next HSCB 5388 * so the sequencer will notice that NEXT_QUEUED_SCB 5389 * has changed during its DMA attempt and will retry 5390 * the DMA. 5391 */ 5392 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5393 5394 if (scb == NULL) { 5395 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5396 found, qinstart, ahc->qinfifonext); 5397 panic("First/Second Qinfifo fixup\n"); 5398 } 5399 /* 5400 * ahc_swap_with_next_hscb forces our next pointer to 5401 * point to the reserved SCB for future commands. Save 5402 * and restore our original next pointer to maintain 5403 * queue integrity. 5404 */ 5405 next = scb->hscb->next; 5406 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5407 ahc_swap_with_next_hscb(ahc, scb); 5408 scb->hscb->next = next; 5409 ahc->qinfifo[qinstart] = scb->hscb->tag; 5410 5411 /* Tell the card about the new head of the qinfifo. */ 5412 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5413 5414 /* Fixup the tail "next" pointer. */ 5415 qintail = ahc->qinfifonext - 1; 5416 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5417 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5418 } 5419 5420 /* 5421 * Search waiting for selection list. 5422 */ 5423 curscbptr = ahc_inb(ahc, SCBPTR); 5424 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5425 prev = SCB_LIST_NULL; 5426 5427 while (next != SCB_LIST_NULL) { 5428 uint8_t scb_index; 5429 5430 ahc_outb(ahc, SCBPTR, next); 5431 scb_index = ahc_inb(ahc, SCB_TAG); 5432 if (scb_index >= ahc->scb_data->numscbs) { 5433 printf("Waiting List inconsistency. " 5434 "SCB index == %d, yet numscbs == %d.", 5435 scb_index, ahc->scb_data->numscbs); 5436 ahc_dump_card_state(ahc); 5437 panic("for safety"); 5438 } 5439 scb = ahc_lookup_scb(ahc, scb_index); 5440 if (scb == NULL) { 5441 printf("scb_index = %d, next = %d\n", 5442 scb_index, next); 5443 panic("Waiting List traversal\n"); 5444 } 5445 if (ahc_match_scb(ahc, scb, target, channel, 5446 lun, SCB_LIST_NULL, role)) { 5447 /* 5448 * We found an scb that needs to be acted on. 5449 */ 5450 found++; 5451 switch (action) { 5452 case SEARCH_COMPLETE: 5453 { 5454 cam_status ostat; 5455 cam_status cstat; 5456 5457 ostat = ahc_get_transaction_status(scb); 5458 if (ostat == CAM_REQ_INPROG) 5459 ahc_set_transaction_status(scb, status); 5460 cstat = ahc_get_transaction_status(scb); 5461 if (cstat != CAM_REQ_CMP) 5462 ahc_freeze_scb(scb); 5463 if ((scb->flags & SCB_ACTIVE) == 0) 5464 printf("Inactive SCB in Waiting List\n"); 5465 ahc_done(ahc, scb); 5466 /* FALLTHROUGH */ 5467 } 5468 case SEARCH_REMOVE: 5469 next = ahc_rem_wscb(ahc, next, prev); 5470 break; 5471 case SEARCH_COUNT: 5472 prev = next; 5473 next = ahc_inb(ahc, SCB_NEXT); 5474 break; 5475 } 5476 } else { 5477 5478 prev = next; 5479 next = ahc_inb(ahc, SCB_NEXT); 5480 } 5481 } 5482 ahc_outb(ahc, SCBPTR, curscbptr); 5483 5484 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5485 channel, lun, status, action); 5486 5487 if (action == SEARCH_COMPLETE) 5488 ahc_release_untagged_queues(ahc); 5489 return (found); 5490 } 5491 5492 int 5493 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsipi_xfer *xs, /*ahc_io_ctx_t ctx,*/ 5494 int target, char channel, int lun, uint32_t status, 5495 ahc_search_action action) 5496 { 5497 struct scb *scb; 5498 int maxtarget; 5499 int found; 5500 int i; 5501 5502 if (action == SEARCH_COMPLETE) { 5503 /* 5504 * Don't attempt to run any queued untagged transactions 5505 * until we are done with the abort process. 5506 */ 5507 ahc_freeze_untagged_queues(ahc); 5508 } 5509 5510 found = 0; 5511 i = 0; 5512 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5513 5514 maxtarget = 16; 5515 if (target != CAM_TARGET_WILDCARD) { 5516 5517 i = target; 5518 if (channel == 'B') 5519 i += 8; 5520 maxtarget = i + 1; 5521 } 5522 } else { 5523 maxtarget = 0; 5524 } 5525 5526 for (; i < maxtarget; i++) { 5527 struct scb_tailq *untagged_q; 5528 struct scb *next_scb; 5529 5530 untagged_q = &(ahc->untagged_queues[i]); 5531 next_scb = TAILQ_FIRST(untagged_q); 5532 while (next_scb != NULL) { 5533 5534 scb = next_scb; 5535 next_scb = TAILQ_NEXT(scb, links.tqe); 5536 5537 /* 5538 * The head of the list may be the currently 5539 * active untagged command for a device. 5540 * We're only searching for commands that 5541 * have not been started. A transaction 5542 * marked active but still in the qinfifo 5543 * is removed by the qinfifo scanning code 5544 * above. 5545 */ 5546 if ((scb->flags & SCB_ACTIVE) != 0) 5547 continue; 5548 5549 if (ahc_match_scb(ahc, scb, target, channel, lun, 5550 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5551 /*|| (ctx != NULL && ctx != scb->io_ctx)*/) 5552 continue; 5553 5554 /* 5555 * We found an scb that needs to be acted on. 5556 */ 5557 found++; 5558 switch (action) { 5559 case SEARCH_COMPLETE: 5560 { 5561 cam_status ostat; 5562 cam_status cstat; 5563 5564 ostat = ahc_get_transaction_status(scb); 5565 if (ostat == CAM_REQ_INPROG) 5566 ahc_set_transaction_status(scb, status); 5567 cstat = ahc_get_transaction_status(scb); 5568 if (cstat != CAM_REQ_CMP) 5569 ahc_freeze_scb(scb); 5570 if ((scb->flags & SCB_ACTIVE) == 0) 5571 printf("Inactive SCB in untaggedQ\n"); 5572 ahc_done(ahc, scb); 5573 break; 5574 } 5575 case SEARCH_REMOVE: 5576 scb->flags &= ~SCB_UNTAGGEDQ; 5577 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5578 break; 5579 case SEARCH_COUNT: 5580 break; 5581 } 5582 } 5583 } 5584 5585 if (action == SEARCH_COMPLETE) 5586 ahc_release_untagged_queues(ahc); 5587 return (found); 5588 } 5589 5590 int 5591 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5592 int lun, u_int tag, int stop_on_first, int remove, 5593 int save_state) 5594 { 5595 struct scb *scbp; 5596 u_int next; 5597 u_int prev; 5598 u_int count; 5599 u_int active_scb; 5600 5601 count = 0; 5602 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5603 prev = SCB_LIST_NULL; 5604 5605 if (save_state) { 5606 /* restore this when we're done */ 5607 active_scb = ahc_inb(ahc, SCBPTR); 5608 } else 5609 /* Silence compiler */ 5610 active_scb = SCB_LIST_NULL; 5611 5612 while (next != SCB_LIST_NULL) { 5613 u_int scb_index; 5614 5615 ahc_outb(ahc, SCBPTR, next); 5616 scb_index = ahc_inb(ahc, SCB_TAG); 5617 if (scb_index >= ahc->scb_data->numscbs) { 5618 printf("Disconnected List inconsistency. " 5619 "SCB index == %d, yet numscbs == %d.", 5620 scb_index, ahc->scb_data->numscbs); 5621 ahc_dump_card_state(ahc); 5622 panic("for safety"); 5623 } 5624 5625 if (next == prev) { 5626 panic("Disconnected List Loop. " 5627 "cur SCBPTR == %x, prev SCBPTR == %x.", 5628 next, prev); 5629 } 5630 scbp = ahc_lookup_scb(ahc, scb_index); 5631 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5632 tag, ROLE_INITIATOR)) { 5633 count++; 5634 if (remove) { 5635 next = 5636 ahc_rem_scb_from_disc_list(ahc, prev, next); 5637 } else { 5638 prev = next; 5639 next = ahc_inb(ahc, SCB_NEXT); 5640 } 5641 if (stop_on_first) 5642 break; 5643 } else { 5644 prev = next; 5645 next = ahc_inb(ahc, SCB_NEXT); 5646 } 5647 } 5648 if (save_state) 5649 ahc_outb(ahc, SCBPTR, active_scb); 5650 return (count); 5651 } 5652 5653 /* 5654 * Remove an SCB from the on chip list of disconnected transactions. 5655 * This is empty/unused if we are not performing SCB paging. 5656 */ 5657 static u_int 5658 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5659 { 5660 u_int next; 5661 5662 ahc_outb(ahc, SCBPTR, scbptr); 5663 next = ahc_inb(ahc, SCB_NEXT); 5664 5665 ahc_outb(ahc, SCB_CONTROL, 0); 5666 5667 ahc_add_curscb_to_free_list(ahc); 5668 5669 if (prev != SCB_LIST_NULL) { 5670 ahc_outb(ahc, SCBPTR, prev); 5671 ahc_outb(ahc, SCB_NEXT, next); 5672 } else 5673 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5674 5675 return (next); 5676 } 5677 5678 /* 5679 * Add the SCB as selected by SCBPTR onto the on chip list of 5680 * free hardware SCBs. This list is empty/unused if we are not 5681 * performing SCB paging. 5682 */ 5683 static void 5684 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5685 { 5686 /* 5687 * Invalidate the tag so that our abort 5688 * routines don't think it's active. 5689 */ 5690 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5691 5692 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5693 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5694 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5695 } 5696 } 5697 5698 /* 5699 * Manipulate the waiting for selection list and return the 5700 * scb that follows the one that we remove. 5701 */ 5702 static u_int 5703 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5704 { 5705 u_int curscb, next; 5706 5707 /* 5708 * Select the SCB we want to abort and 5709 * pull the next pointer out of it. 5710 */ 5711 curscb = ahc_inb(ahc, SCBPTR); 5712 ahc_outb(ahc, SCBPTR, scbpos); 5713 next = ahc_inb(ahc, SCB_NEXT); 5714 5715 /* Clear the necessary fields */ 5716 ahc_outb(ahc, SCB_CONTROL, 0); 5717 5718 ahc_add_curscb_to_free_list(ahc); 5719 5720 /* update the waiting list */ 5721 if (prev == SCB_LIST_NULL) { 5722 /* First in the list */ 5723 ahc_outb(ahc, WAITING_SCBH, next); 5724 5725 /* 5726 * Ensure we aren't attempting to perform 5727 * selection for this entry. 5728 */ 5729 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5730 } else { 5731 /* 5732 * Select the scb that pointed to us 5733 * and update its next pointer. 5734 */ 5735 ahc_outb(ahc, SCBPTR, prev); 5736 ahc_outb(ahc, SCB_NEXT, next); 5737 } 5738 5739 /* 5740 * Point us back at the original scb position. 5741 */ 5742 ahc_outb(ahc, SCBPTR, curscb); 5743 return next; 5744 } 5745 5746 /******************************** Error Handling ******************************/ 5747 /* 5748 * Abort all SCBs that match the given description (target/channel/lun/tag), 5749 * setting their status to the passed in status if the status has not already 5750 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5751 * is paused before it is called. 5752 */ 5753 int 5754 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5755 int lun, u_int tag, role_t role, uint32_t status) 5756 { 5757 struct scb *scbp; 5758 struct scb *scbp_next; 5759 u_int active_scb; 5760 int i, j; 5761 int maxtarget; 5762 int minlun; 5763 int maxlun; 5764 5765 int found; 5766 5767 /* 5768 * Don't attempt to run any queued untagged transactions 5769 * until we are done with the abort process. 5770 */ 5771 ahc_freeze_untagged_queues(ahc); 5772 5773 /* restore this when we're done */ 5774 active_scb = ahc_inb(ahc, SCBPTR); 5775 5776 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5777 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5778 5779 /* 5780 * Clean out the busy target table for any untagged commands. 5781 */ 5782 i = 0; 5783 maxtarget = 16; 5784 if (target != CAM_TARGET_WILDCARD) { 5785 i = target; 5786 if (channel == 'B') 5787 i += 8; 5788 maxtarget = i + 1; 5789 } 5790 5791 if (lun == CAM_LUN_WILDCARD) { 5792 5793 /* 5794 * Unless we are using an SCB based 5795 * busy targets table, there is only 5796 * one table entry for all luns of 5797 * a target. 5798 */ 5799 minlun = 0; 5800 maxlun = 1; 5801 if ((ahc->flags & AHC_SCB_BTT) != 0) 5802 maxlun = AHC_NUM_LUNS; 5803 } else { 5804 minlun = lun; 5805 maxlun = lun + 1; 5806 } 5807 5808 if (role != ROLE_TARGET) { 5809 for (;i < maxtarget; i++) { 5810 for (j = minlun;j < maxlun; j++) { 5811 u_int scbid; 5812 u_int tcl; 5813 5814 tcl = BUILD_TCL(i << 4, j); 5815 scbid = ahc_index_busy_tcl(ahc, tcl); 5816 scbp = ahc_lookup_scb(ahc, scbid); 5817 if (scbp == NULL 5818 || ahc_match_scb(ahc, scbp, target, channel, 5819 lun, tag, role) == 0) 5820 continue; 5821 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5822 } 5823 } 5824 5825 /* 5826 * Go through the disconnected list and remove any entries we 5827 * have queued for completion, 0'ing their control byte too. 5828 * We save the active SCB and restore it ourselves, so there 5829 * is no reason for this search to restore it too. 5830 */ 5831 ahc_search_disc_list(ahc, target, channel, lun, tag, 5832 /*stop_on_first*/FALSE, /*remove*/TRUE, 5833 /*save_state*/FALSE); 5834 } 5835 5836 /* 5837 * Go through the hardware SCB array looking for commands that 5838 * were active but not on any list. In some cases, these remnants 5839 * might not still have mappings in the scbindex array (e.g. unexpected 5840 * bus free with the same scb queued for an abort). Don't hold this 5841 * against them. 5842 */ 5843 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5844 u_int scbid; 5845 5846 ahc_outb(ahc, SCBPTR, i); 5847 scbid = ahc_inb(ahc, SCB_TAG); 5848 scbp = ahc_lookup_scb(ahc, scbid); 5849 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5850 || (scbp != NULL 5851 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5852 ahc_add_curscb_to_free_list(ahc); 5853 } 5854 5855 /* 5856 * Go through the pending CCB list and look for 5857 * commands for this target that are still active. 5858 * These are other tagged commands that were 5859 * disconnected when the reset occurred. 5860 */ 5861 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5862 while (scbp_next != NULL) { 5863 scbp = scbp_next; 5864 scbp_next = LIST_NEXT(scbp, pending_links); 5865 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5866 cam_status ostat; 5867 5868 ostat = ahc_get_transaction_status(scbp); 5869 if (ostat == CAM_REQ_INPROG) 5870 ahc_set_transaction_status(scbp, status); 5871 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5872 ahc_freeze_scb(scbp); 5873 if ((scbp->flags & SCB_ACTIVE) == 0) 5874 printf("Inactive SCB on pending list\n"); 5875 ahc_done(ahc, scbp); 5876 found++; 5877 } 5878 } 5879 ahc_outb(ahc, SCBPTR, active_scb); 5880 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5881 ahc_release_untagged_queues(ahc); 5882 return found; 5883 } 5884 5885 static void 5886 ahc_reset_current_bus(struct ahc_softc *ahc) 5887 { 5888 uint8_t scsiseq; 5889 5890 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5891 scsiseq = ahc_inb(ahc, SCSISEQ); 5892 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5893 ahc_flush_device_writes(ahc); 5894 ahc_delay(AHC_BUSRESET_DELAY); 5895 /* Turn off the bus reset */ 5896 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5897 5898 ahc_clear_intstat(ahc); 5899 5900 /* Re-enable reset interrupts */ 5901 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5902 } 5903 5904 int 5905 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5906 { 5907 struct ahc_devinfo devinfo; 5908 u_int initiator, target, max_scsiid; 5909 u_int sblkctl; 5910 u_int scsiseq; 5911 u_int simode1; 5912 int found; 5913 int restart_needed; 5914 char cur_channel; 5915 5916 ahc->pending_device = NULL; 5917 5918 ahc_compile_devinfo(&devinfo, 5919 CAM_TARGET_WILDCARD, 5920 CAM_TARGET_WILDCARD, 5921 CAM_LUN_WILDCARD, 5922 channel, ROLE_UNKNOWN); 5923 ahc_pause(ahc); 5924 5925 /* Make sure the sequencer is in a safe location. */ 5926 ahc_clear_critical_section(ahc); 5927 5928 /* 5929 * Run our command complete fifos to ensure that we perform 5930 * completion processing on any commands that 'completed' 5931 * before the reset occurred. 5932 */ 5933 ahc_run_qoutfifo(ahc); 5934 #if AHC_TARGET_MODE 5935 /* 5936 * XXX - In Twin mode, the tqinfifo may have commands 5937 * for an unaffected channel in it. However, if 5938 * we have run out of ATIO resources to drain that 5939 * queue, we may not get them all out here. Further, 5940 * the blocked transactions for the reset channel 5941 * should just be killed off, irrespecitve of whether 5942 * we are blocked on ATIO resources. Write a routine 5943 * to compact the tqinfifo appropriately. 5944 */ 5945 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5946 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5947 } 5948 #endif 5949 5950 /* 5951 * Reset the bus if we are initiating this reset 5952 */ 5953 sblkctl = ahc_inb(ahc, SBLKCTL); 5954 cur_channel = 'A'; 5955 if ((ahc->features & AHC_TWIN) != 0 5956 && ((sblkctl & SELBUSB) != 0)) 5957 cur_channel = 'B'; 5958 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5959 if (cur_channel != channel) { 5960 /* Case 1: Command for another bus is active 5961 * Stealthily reset the other bus without 5962 * upsetting the current bus. 5963 */ 5964 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5965 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5966 #if AHC_TARGET_MODE 5967 /* 5968 * Bus resets clear ENSELI, so we cannot 5969 * defer re-enabling bus reset interrupts 5970 * if we are in target mode. 5971 */ 5972 if ((ahc->flags & AHC_TARGETROLE) != 0) 5973 simode1 |= ENSCSIRST; 5974 #endif 5975 ahc_outb(ahc, SIMODE1, simode1); 5976 if (initiate_reset) 5977 ahc_reset_current_bus(ahc); 5978 ahc_clear_intstat(ahc); 5979 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5980 ahc_outb(ahc, SBLKCTL, sblkctl); 5981 restart_needed = FALSE; 5982 } else { 5983 /* Case 2: A command from this bus is active or we're idle */ 5984 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5985 #if AHC_TARGET_MODE 5986 /* 5987 * Bus resets clear ENSELI, so we cannot 5988 * defer re-enabling bus reset interrupts 5989 * if we are in target mode. 5990 */ 5991 if ((ahc->flags & AHC_TARGETROLE) != 0) 5992 simode1 |= ENSCSIRST; 5993 #endif 5994 ahc_outb(ahc, SIMODE1, simode1); 5995 if (initiate_reset) 5996 ahc_reset_current_bus(ahc); 5997 ahc_clear_intstat(ahc); 5998 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5999 restart_needed = TRUE; 6000 } 6001 6002 /* 6003 * Clean up all the state information for the 6004 * pending transactions on this bus. 6005 */ 6006 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6007 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6008 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6009 6010 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6011 6012 #ifdef AHC_TARGET_MODE 6013 /* 6014 * Send an immediate notify ccb to all target more peripheral 6015 * drivers affected by this action. 6016 */ 6017 for (target = 0; target <= max_scsiid; target++) { 6018 struct ahc_tmode_tstate* tstate; 6019 u_int lun; 6020 6021 tstate = ahc->enabled_targets[target]; 6022 if (tstate == NULL) 6023 continue; 6024 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6025 struct ahc_tmode_lstate* lstate; 6026 6027 lstate = tstate->enabled_luns[lun]; 6028 if (lstate == NULL) 6029 continue; 6030 6031 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6032 EVENT_TYPE_BUS_RESET, /*arg*/0); 6033 ahc_send_lstate_events(ahc, lstate); 6034 } 6035 } 6036 #endif 6037 /* 6038 * Revert to async/narrow transfers until we renegotiate. 6039 */ 6040 for (target = 0; target <= max_scsiid; target++) { 6041 6042 if (ahc->enabled_targets[target] == NULL) 6043 continue; 6044 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6045 struct ahc_devinfo devinfo; 6046 6047 ahc_compile_devinfo(&devinfo, target, initiator, 6048 CAM_LUN_WILDCARD, 6049 channel, ROLE_UNKNOWN); 6050 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6051 AHC_TRANS_CUR, /*paused*/TRUE); 6052 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6053 /*period*/0, /*offset*/0, 6054 /*ppr_options*/0, AHC_TRANS_CUR, 6055 /*paused*/TRUE); 6056 } 6057 } 6058 6059 if (restart_needed) 6060 ahc_restart(ahc); 6061 else 6062 ahc_unpause(ahc); 6063 return found; 6064 } 6065 6066 6067 /***************************** Residual Processing ****************************/ 6068 /* 6069 * Calculate the residual for a just completed SCB. 6070 */ 6071 void 6072 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6073 { 6074 struct hardware_scb *hscb; 6075 struct status_pkt *spkt; 6076 uint32_t sgptr; 6077 uint32_t resid_sgptr; 6078 uint32_t resid; 6079 6080 /* 6081 * 5 cases. 6082 * 1) No residual. 6083 * SG_RESID_VALID clear in sgptr. 6084 * 2) Transferless command 6085 * 3) Never performed any transfers. 6086 * sgptr has SG_FULL_RESID set. 6087 * 4) No residual but target did not 6088 * save data pointers after the 6089 * last transfer, so sgptr was 6090 * never updated. 6091 * 5) We have a partial residual. 6092 * Use residual_sgptr to determine 6093 * where we are. 6094 */ 6095 6096 hscb = scb->hscb; 6097 sgptr = ahc_le32toh(hscb->sgptr); 6098 if ((sgptr & SG_RESID_VALID) == 0) 6099 /* Case 1 */ 6100 return; 6101 sgptr &= ~SG_RESID_VALID; 6102 6103 if ((sgptr & SG_LIST_NULL) != 0) 6104 /* Case 2 */ 6105 return; 6106 6107 spkt = &hscb->shared_data.status; 6108 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6109 if ((sgptr & SG_FULL_RESID) != 0) { 6110 /* Case 3 */ 6111 resid = ahc_get_transfer_length(scb); 6112 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6113 /* Case 4 */ 6114 return; 6115 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6116 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6117 } else { 6118 struct ahc_dma_seg *sg; 6119 6120 /* 6121 * Remainder of the SG where the transfer 6122 * stopped. 6123 */ 6124 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6125 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6126 6127 /* The residual sg_ptr always points to the next sg */ 6128 sg--; 6129 6130 /* 6131 * Add up the contents of all residual 6132 * SG segments that are after the SG where 6133 * the transfer stopped. 6134 */ 6135 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6136 sg++; 6137 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6138 } 6139 } 6140 if ((scb->flags & SCB_SENSE) == 0) 6141 ahc_set_residual(scb, resid); 6142 else 6143 ahc_set_sense_residual(scb, resid); 6144 6145 #ifdef AHC_DEBUG 6146 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6147 ahc_print_path(ahc, scb); 6148 printf("Handled %sResidual of %d bytes\n", 6149 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6150 } 6151 #endif 6152 } 6153 6154 /******************************* Target Mode **********************************/ 6155 #ifdef AHC_TARGET_MODE 6156 /* 6157 * Add a target mode event to this lun's queue 6158 */ 6159 static void 6160 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6161 u_int initiator_id, u_int event_type, u_int event_arg) 6162 { 6163 struct ahc_tmode_event *event; 6164 int pending; 6165 6166 xpt_freeze_devq(lstate->path, /*count*/1); 6167 if (lstate->event_w_idx >= lstate->event_r_idx) 6168 pending = lstate->event_w_idx - lstate->event_r_idx; 6169 else 6170 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6171 - (lstate->event_r_idx - lstate->event_w_idx); 6172 6173 if (event_type == EVENT_TYPE_BUS_RESET 6174 || event_type == MSG_BUS_DEV_RESET) { 6175 /* 6176 * Any earlier events are irrelevant, so reset our buffer. 6177 * This has the effect of allowing us to deal with reset 6178 * floods (an external device holding down the reset line) 6179 * without losing the event that is really interesting. 6180 */ 6181 lstate->event_r_idx = 0; 6182 lstate->event_w_idx = 0; 6183 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6184 } 6185 6186 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6187 xpt_print_path(lstate->path); 6188 printf("immediate event %x:%x lost\n", 6189 lstate->event_buffer[lstate->event_r_idx].event_type, 6190 lstate->event_buffer[lstate->event_r_idx].event_arg); 6191 lstate->event_r_idx++; 6192 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6193 lstate->event_r_idx = 0; 6194 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6195 } 6196 6197 event = &lstate->event_buffer[lstate->event_w_idx]; 6198 event->initiator_id = initiator_id; 6199 event->event_type = event_type; 6200 event->event_arg = event_arg; 6201 lstate->event_w_idx++; 6202 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6203 lstate->event_w_idx = 0; 6204 } 6205 6206 /* 6207 * Send any target mode events queued up waiting 6208 * for immediate notify resources. 6209 */ 6210 void 6211 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6212 { 6213 struct ccb_hdr *ccbh; 6214 struct ccb_immed_notify *inot; 6215 6216 while (lstate->event_r_idx != lstate->event_w_idx 6217 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6218 struct ahc_tmode_event *event; 6219 6220 event = &lstate->event_buffer[lstate->event_r_idx]; 6221 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6222 inot = (struct ccb_immed_notify *)ccbh; 6223 switch (event->event_type) { 6224 case EVENT_TYPE_BUS_RESET: 6225 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6226 break; 6227 default: 6228 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6229 inot->message_args[0] = event->event_type; 6230 inot->message_args[1] = event->event_arg; 6231 break; 6232 } 6233 inot->initiator_id = event->initiator_id; 6234 inot->sense_len = 0; 6235 xpt_done((union ccb *)inot); 6236 lstate->event_r_idx++; 6237 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6238 lstate->event_r_idx = 0; 6239 } 6240 } 6241 #endif 6242 6243 /******************** Sequencer Program Patching/Download *********************/ 6244 6245 #ifdef AHC_DUMP_SEQ 6246 void 6247 ahc_dumpseq(struct ahc_softc* ahc) 6248 { 6249 int i; 6250 int max_prog; 6251 6252 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 6253 max_prog = 448; 6254 else if ((ahc->features & AHC_ULTRA2) != 0) 6255 max_prog = 768; 6256 else 6257 max_prog = 512; 6258 6259 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6260 ahc_outb(ahc, SEQADDR0, 0); 6261 ahc_outb(ahc, SEQADDR1, 0); 6262 for (i = 0; i < max_prog; i++) { 6263 uint8_t ins_bytes[4]; 6264 6265 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6266 printf("0x%08x\n", ins_bytes[0] << 24 6267 | ins_bytes[1] << 16 6268 | ins_bytes[2] << 8 6269 | ins_bytes[3]); 6270 } 6271 } 6272 #endif 6273 6274 static void 6275 ahc_loadseq(struct ahc_softc *ahc) 6276 { 6277 struct cs cs_table[num_critical_sections]; 6278 u_int begin_set[num_critical_sections]; 6279 u_int end_set[num_critical_sections]; 6280 struct patch *cur_patch; 6281 u_int cs_count; 6282 u_int cur_cs; 6283 u_int i; 6284 int downloaded; 6285 u_int skip_addr; 6286 u_int sg_prefetch_cnt; 6287 uint8_t download_consts[7]; 6288 6289 /* 6290 * Start out with 0 critical sections 6291 * that apply to this firmware load. 6292 */ 6293 cs_count = 0; 6294 cur_cs = 0; 6295 memset(begin_set, 0, sizeof(begin_set)); 6296 memset(end_set, 0, sizeof(end_set)); 6297 6298 /* Setup downloadable constant table */ 6299 download_consts[QOUTFIFO_OFFSET] = 0; 6300 if (ahc->targetcmds != NULL) 6301 download_consts[QOUTFIFO_OFFSET] += 32; 6302 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6303 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6304 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6305 sg_prefetch_cnt = ahc->pci_cachesize; 6306 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6307 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6308 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6309 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6310 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6311 6312 cur_patch = patches; 6313 downloaded = 0; 6314 skip_addr = 0; 6315 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6316 ahc_outb(ahc, SEQADDR0, 0); 6317 ahc_outb(ahc, SEQADDR1, 0); 6318 6319 for (i = 0; i < sizeof(seqprog)/4; i++) { 6320 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6321 /* 6322 * Don't download this instruction as it 6323 * is in a patch that was removed. 6324 */ 6325 continue; 6326 } 6327 /* 6328 * Move through the CS table until we find a CS 6329 * that might apply to this instruction. 6330 */ 6331 for (; cur_cs < num_critical_sections; cur_cs++) { 6332 if (critical_sections[cur_cs].end <= i) { 6333 if (begin_set[cs_count] == TRUE 6334 && end_set[cs_count] == FALSE) { 6335 cs_table[cs_count].end = downloaded; 6336 end_set[cs_count] = TRUE; 6337 cs_count++; 6338 } 6339 continue; 6340 } 6341 if (critical_sections[cur_cs].begin <= i 6342 && begin_set[cs_count] == FALSE) { 6343 cs_table[cs_count].begin = downloaded; 6344 begin_set[cs_count] = TRUE; 6345 } 6346 break; 6347 } 6348 ahc_download_instr(ahc, i, download_consts); 6349 downloaded++; 6350 } 6351 6352 ahc->num_critical_sections = cs_count; 6353 if (cs_count != 0) { 6354 6355 cs_count *= sizeof(struct cs); 6356 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6357 if (ahc->critical_sections == NULL) 6358 panic("ahc_loadseq: Could not malloc"); 6359 memcpy(ahc->critical_sections, cs_table, cs_count); 6360 } 6361 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6362 ahc_restart(ahc); 6363 6364 if (bootverbose) { 6365 printf(" %d instructions downloaded\n", downloaded); 6366 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6367 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6368 } 6369 } 6370 6371 static int 6372 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6373 u_int start_instr, u_int *skip_addr) 6374 { 6375 struct patch *cur_patch; 6376 struct patch *last_patch; 6377 u_int num_patches; 6378 6379 num_patches = sizeof(patches)/sizeof(struct patch); 6380 last_patch = &patches[num_patches]; 6381 cur_patch = *start_patch; 6382 6383 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6384 6385 if (cur_patch->patch_func(ahc) == 0) { 6386 6387 /* Start rejecting code */ 6388 *skip_addr = start_instr + cur_patch->skip_instr; 6389 cur_patch += cur_patch->skip_patch; 6390 } else { 6391 /* Accepted this patch. Advance to the next 6392 * one and wait for our intruction pointer to 6393 * hit this point. 6394 */ 6395 cur_patch++; 6396 } 6397 } 6398 6399 *start_patch = cur_patch; 6400 if (start_instr < *skip_addr) 6401 /* Still skipping */ 6402 return (0); 6403 6404 return (1); 6405 } 6406 6407 static void 6408 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6409 { 6410 union ins_formats instr; 6411 struct ins_format1 *fmt1_ins; 6412 struct ins_format3 *fmt3_ins; 6413 u_int opcode; 6414 6415 /* 6416 * The firmware is always compiled into a little endian format. 6417 */ 6418 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6419 6420 fmt1_ins = &instr.format1; 6421 fmt3_ins = NULL; 6422 6423 /* Pull the opcode */ 6424 opcode = instr.format1.opcode; 6425 switch (opcode) { 6426 case AIC_OP_JMP: 6427 case AIC_OP_JC: 6428 case AIC_OP_JNC: 6429 case AIC_OP_CALL: 6430 case AIC_OP_JNE: 6431 case AIC_OP_JNZ: 6432 case AIC_OP_JE: 6433 case AIC_OP_JZ: 6434 { 6435 struct patch *cur_patch; 6436 int address_offset; 6437 u_int address; 6438 u_int skip_addr; 6439 u_int i; 6440 6441 fmt3_ins = &instr.format3; 6442 address_offset = 0; 6443 address = fmt3_ins->address; 6444 cur_patch = patches; 6445 skip_addr = 0; 6446 for (i = 0; i < address;) { 6447 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6448 6449 if (skip_addr > i) { 6450 int end_addr; 6451 6452 end_addr = MIN(address, skip_addr); 6453 address_offset += end_addr - i; 6454 i = skip_addr; 6455 } else { 6456 i++; 6457 } 6458 } 6459 address -= address_offset; 6460 fmt3_ins->address = address; 6461 /* FALLTHROUGH */ 6462 } 6463 case AIC_OP_OR: 6464 case AIC_OP_AND: 6465 case AIC_OP_XOR: 6466 case AIC_OP_ADD: 6467 case AIC_OP_ADC: 6468 case AIC_OP_BMOV: 6469 if (fmt1_ins->parity != 0) { 6470 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6471 } 6472 fmt1_ins->parity = 0; 6473 if ((ahc->features & AHC_CMD_CHAN) == 0 6474 && opcode == AIC_OP_BMOV) { 6475 /* 6476 * Block move was added at the same time 6477 * as the command channel. Verify that 6478 * this is only a move of a single element 6479 * and convert the BMOV to a MOV 6480 * (AND with an immediate of FF). 6481 */ 6482 if (fmt1_ins->immediate != 1) 6483 panic("%s: BMOV not supported\n", 6484 ahc_name(ahc)); 6485 fmt1_ins->opcode = AIC_OP_AND; 6486 fmt1_ins->immediate = 0xff; 6487 } 6488 /* FALLTHROUGH */ 6489 case AIC_OP_ROL: 6490 if ((ahc->features & AHC_ULTRA2) != 0) { 6491 int i, count; 6492 6493 /* Calculate odd parity for the instruction */ 6494 for (i = 0, count = 0; i < 31; i++) { 6495 uint32_t mask; 6496 6497 mask = 0x01 << i; 6498 if ((instr.integer & mask) != 0) 6499 count++; 6500 } 6501 if ((count & 0x01) == 0) 6502 instr.format1.parity = 1; 6503 } else { 6504 /* Compress the instruction for older sequencers */ 6505 if (fmt3_ins != NULL) { 6506 instr.integer = 6507 fmt3_ins->immediate 6508 | (fmt3_ins->source << 8) 6509 | (fmt3_ins->address << 16) 6510 | (fmt3_ins->opcode << 25); 6511 } else { 6512 instr.integer = 6513 fmt1_ins->immediate 6514 | (fmt1_ins->source << 8) 6515 | (fmt1_ins->destination << 16) 6516 | (fmt1_ins->ret << 24) 6517 | (fmt1_ins->opcode << 25); 6518 } 6519 } 6520 /* The sequencer is a little endian cpu */ 6521 instr.integer = ahc_htole32(instr.integer); 6522 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6523 break; 6524 default: 6525 panic("Unknown opcode encountered in seq program"); 6526 break; 6527 } 6528 } 6529 6530 int 6531 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6532 const char *name, u_int address, u_int value, 6533 u_int *cur_column, u_int wrap_point) 6534 { 6535 int printed; 6536 u_int printed_mask; 6537 char line[1024]; 6538 6539 line[0] = 0; 6540 6541 if (cur_column != NULL && *cur_column >= wrap_point) { 6542 printf("\n"); 6543 *cur_column = 0; 6544 } 6545 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 6546 if (table == NULL) { 6547 printed += snprintf(&line[printed], (sizeof line) - printed, 6548 " "); 6549 printf("%s", line); 6550 if (cur_column != NULL) 6551 *cur_column += printed; 6552 return (printed); 6553 } 6554 printed_mask = 0; 6555 while (printed_mask != 0xFF) { 6556 int entry; 6557 6558 for (entry = 0; entry < num_entries; entry++) { 6559 if (((value & table[entry].mask) 6560 != table[entry].value) 6561 || ((printed_mask & table[entry].mask) 6562 == table[entry].mask)) 6563 continue; 6564 printed += snprintf(&line[printed], 6565 (sizeof line) - printed, "%s%s", 6566 printed_mask == 0 ? ":(" : "|", 6567 table[entry].name); 6568 printed_mask |= table[entry].mask; 6569 6570 break; 6571 } 6572 if (entry >= num_entries) 6573 break; 6574 } 6575 if (printed_mask != 0) 6576 printed += snprintf(&line[printed], 6577 (sizeof line) - printed, ") "); 6578 else 6579 printed += snprintf(&line[printed], 6580 (sizeof line) - printed, " "); 6581 if (cur_column != NULL) 6582 *cur_column += printed; 6583 printf("%s", line); 6584 6585 return (printed); 6586 } 6587 6588 void 6589 ahc_dump_card_state(struct ahc_softc *ahc) 6590 { 6591 struct scb *scb; 6592 struct scb_tailq *untagged_q; 6593 u_int cur_col; 6594 int paused; 6595 int target; 6596 int maxtarget; 6597 int i; 6598 uint8_t last_phase; 6599 uint8_t qinpos; 6600 uint8_t qintail; 6601 uint8_t qoutpos; 6602 uint8_t scb_index; 6603 uint8_t saved_scbptr; 6604 6605 if (ahc_is_paused(ahc)) { 6606 paused = 1; 6607 } else { 6608 paused = 0; 6609 ahc_pause(ahc); 6610 } 6611 6612 saved_scbptr = ahc_inb(ahc, SCBPTR); 6613 last_phase = ahc_inb(ahc, LASTPHASE); 6614 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6615 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6616 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6617 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6618 if (paused) 6619 printf("Card was paused\n"); 6620 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6621 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6622 ahc_inb(ahc, ARG_2)); 6623 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6624 ahc_inb(ahc, SCBPTR)); 6625 cur_col = 0; 6626 if ((ahc->features & AHC_DT) != 0) 6627 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6628 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6629 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6630 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6631 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6632 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6633 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6634 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6635 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6636 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6637 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6638 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6639 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6640 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6641 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6642 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6643 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6644 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6645 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6646 if (cur_col != 0) 6647 printf("\n"); 6648 printf("STACK:"); 6649 for (i = 0; i < STACK_SIZE; i++) 6650 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6651 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6652 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6653 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6654 /* QINFIFO */ 6655 printf("QINFIFO entries: "); 6656 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6657 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6658 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6659 } else 6660 qinpos = ahc_inb(ahc, QINPOS); 6661 qintail = ahc->qinfifonext; 6662 while (qinpos != qintail) { 6663 printf("%d ", ahc->qinfifo[qinpos]); 6664 qinpos++; 6665 } 6666 printf("\n"); 6667 6668 printf("Waiting Queue entries: "); 6669 scb_index = ahc_inb(ahc, WAITING_SCBH); 6670 i = 0; 6671 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6672 ahc_outb(ahc, SCBPTR, scb_index); 6673 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6674 scb_index = ahc_inb(ahc, SCB_NEXT); 6675 } 6676 printf("\n"); 6677 6678 printf("Disconnected Queue entries: "); 6679 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6680 i = 0; 6681 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6682 ahc_outb(ahc, SCBPTR, scb_index); 6683 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6684 scb_index = ahc_inb(ahc, SCB_NEXT); 6685 } 6686 printf("\n"); 6687 6688 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6689 printf("QOUTFIFO entries: "); 6690 qoutpos = ahc->qoutfifonext; 6691 i = 0; 6692 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6693 printf("%d ", ahc->qoutfifo[qoutpos]); 6694 qoutpos++; 6695 } 6696 printf("\n"); 6697 6698 printf("Sequencer Free SCB List: "); 6699 scb_index = ahc_inb(ahc, FREE_SCBH); 6700 i = 0; 6701 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6702 ahc_outb(ahc, SCBPTR, scb_index); 6703 printf("%d ", scb_index); 6704 scb_index = ahc_inb(ahc, SCB_NEXT); 6705 } 6706 printf("\n"); 6707 6708 printf("Sequencer SCB Info: "); 6709 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6710 ahc_outb(ahc, SCBPTR, i); 6711 /*cur_col =*/ printf("\n%3d ", i); 6712 6713 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6714 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6715 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6716 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6717 } 6718 printf("\n"); 6719 6720 printf("Pending list: "); 6721 i = 0; 6722 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6723 if (i++ > 256) 6724 break; 6725 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6726 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6727 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6728 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6729 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6730 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6731 printf("("); 6732 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6733 &cur_col, 60); 6734 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6735 printf(")"); 6736 } 6737 } 6738 printf("\n"); 6739 6740 printf("Kernel Free SCB list: "); 6741 i = 0; 6742 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6743 if (i++ > 256) 6744 break; 6745 printf("%d ", scb->hscb->tag); 6746 } 6747 printf("\n"); 6748 6749 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6750 for (target = 0; target <= maxtarget; target++) { 6751 untagged_q = &ahc->untagged_queues[target]; 6752 if (TAILQ_FIRST(untagged_q) == NULL) 6753 continue; 6754 printf("Untagged Q(%d): ", target); 6755 i = 0; 6756 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6757 if (i++ > 256) 6758 break; 6759 printf("%d ", scb->hscb->tag); 6760 } 6761 printf("\n"); 6762 } 6763 6764 ahc_platform_dump_card_state(ahc); 6765 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6766 ahc_outb(ahc, SCBPTR, saved_scbptr); 6767 if (paused == 0) 6768 ahc_unpause(ahc); 6769 } 6770 6771 /************************* Target Mode ****************************************/ 6772 #ifdef AHC_TARGET_MODE 6773 cam_status 6774 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6775 struct ahc_tmode_tstate **tstate, 6776 struct ahc_tmode_lstate **lstate, 6777 int notfound_failure) 6778 { 6779 6780 if ((ahc->features & AHC_TARGETMODE) == 0) 6781 return (CAM_REQ_INVALID); 6782 6783 /* 6784 * Handle the 'black hole' device that sucks up 6785 * requests to unattached luns on enabled targets. 6786 */ 6787 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6788 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6789 *tstate = NULL; 6790 *lstate = ahc->black_hole; 6791 } else { 6792 u_int max_id; 6793 6794 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6795 if (ccb->ccb_h.target_id > max_id) 6796 return (CAM_TID_INVALID); 6797 6798 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6799 return (CAM_LUN_INVALID); 6800 6801 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6802 *lstate = NULL; 6803 if (*tstate != NULL) 6804 *lstate = 6805 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6806 } 6807 6808 if (notfound_failure != 0 && *lstate == NULL) 6809 return (CAM_PATH_INVALID); 6810 6811 return (CAM_REQ_CMP); 6812 } 6813 6814 void 6815 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6816 { 6817 struct ahc_tmode_tstate *tstate; 6818 struct ahc_tmode_lstate *lstate; 6819 struct ccb_en_lun *cel; 6820 cam_status status; 6821 u_int target; 6822 u_int lun; 6823 u_int target_mask; 6824 u_int our_id; 6825 u_long s; 6826 char channel; 6827 6828 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6829 /*notfound_failure*/FALSE); 6830 6831 if (status != CAM_REQ_CMP) { 6832 ccb->ccb_h.status = status; 6833 return; 6834 } 6835 6836 if (cam_sim_bus(sim) == 0) 6837 our_id = ahc->our_id; 6838 else 6839 our_id = ahc->our_id_b; 6840 6841 if (ccb->ccb_h.target_id != our_id) { 6842 /* 6843 * our_id represents our initiator ID, or 6844 * the ID of the first target to have an 6845 * enabled lun in target mode. There are 6846 * two cases that may preclude enabling a 6847 * target id other than our_id. 6848 * 6849 * o our_id is for an active initiator role. 6850 * Since the hardware does not support 6851 * reselections to the initiator role at 6852 * anything other than our_id, and our_id 6853 * is used by the hardware to indicate the 6854 * ID to use for both select-out and 6855 * reselect-out operations, the only target 6856 * ID we can support in this mode is our_id. 6857 * 6858 * o The MULTARGID feature is not available and 6859 * a previous target mode ID has been enabled. 6860 */ 6861 if ((ahc->features & AHC_MULTIROLE) != 0) { 6862 6863 if ((ahc->features & AHC_MULTI_TID) != 0 6864 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6865 /* 6866 * Only allow additional targets if 6867 * the initiator role is disabled. 6868 * The hardware cannot handle a re-select-in 6869 * on the initiator id during a re-select-out 6870 * on a different target id. 6871 */ 6872 status = CAM_TID_INVALID; 6873 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6874 || ahc->enabled_luns > 0) { 6875 /* 6876 * Only allow our target id to change 6877 * if the initiator role is not configured 6878 * and there are no enabled luns which 6879 * are attached to the currently registered 6880 * scsi id. 6881 */ 6882 status = CAM_TID_INVALID; 6883 } 6884 } else if ((ahc->features & AHC_MULTI_TID) == 0 6885 && ahc->enabled_luns > 0) { 6886 6887 status = CAM_TID_INVALID; 6888 } 6889 } 6890 6891 if (status != CAM_REQ_CMP) { 6892 ccb->ccb_h.status = status; 6893 return; 6894 } 6895 6896 /* 6897 * We now have an id that is valid. 6898 * If we aren't in target mode, switch modes. 6899 */ 6900 if ((ahc->flags & AHC_TARGETROLE) == 0 6901 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6902 u_long s; 6903 6904 printf("Configuring Target Mode\n"); 6905 ahc_lock(ahc, &s); 6906 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6907 ccb->ccb_h.status = CAM_BUSY; 6908 ahc_unlock(ahc, &s); 6909 return; 6910 } 6911 ahc->flags |= AHC_TARGETROLE; 6912 if ((ahc->features & AHC_MULTIROLE) == 0) 6913 ahc->flags &= ~AHC_INITIATORROLE; 6914 ahc_pause(ahc); 6915 ahc_loadseq(ahc); 6916 ahc_unlock(ahc, &s); 6917 } 6918 cel = &ccb->cel; 6919 target = ccb->ccb_h.target_id; 6920 lun = ccb->ccb_h.target_lun; 6921 channel = SIM_CHANNEL(ahc, sim); 6922 target_mask = 0x01 << target; 6923 if (channel == 'B') 6924 target_mask <<= 8; 6925 6926 if (cel->enable != 0) { 6927 u_int scsiseq; 6928 6929 /* Are we already enabled?? */ 6930 if (lstate != NULL) { 6931 xpt_print_path(ccb->ccb_h.path); 6932 printf("Lun already enabled\n"); 6933 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6934 return; 6935 } 6936 6937 if (cel->grp6_len != 0 6938 || cel->grp7_len != 0) { 6939 /* 6940 * Don't (yet?) support vendor 6941 * specific commands. 6942 */ 6943 ccb->ccb_h.status = CAM_REQ_INVALID; 6944 printf("Non-zero Group Codes\n"); 6945 return; 6946 } 6947 6948 /* 6949 * Seems to be okay. 6950 * Setup our data structures. 6951 */ 6952 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6953 tstate = ahc_alloc_tstate(ahc, target, channel); 6954 if (tstate == NULL) { 6955 xpt_print_path(ccb->ccb_h.path); 6956 printf("Couldn't allocate tstate\n"); 6957 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6958 return; 6959 } 6960 } 6961 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6962 if (lstate == NULL) { 6963 xpt_print_path(ccb->ccb_h.path); 6964 printf("Couldn't allocate lstate\n"); 6965 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6966 return; 6967 } 6968 memset(lstate, 0, sizeof(*lstate)); 6969 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6970 xpt_path_path_id(ccb->ccb_h.path), 6971 xpt_path_target_id(ccb->ccb_h.path), 6972 xpt_path_lun_id(ccb->ccb_h.path)); 6973 if (status != CAM_REQ_CMP) { 6974 free(lstate, M_DEVBUF); 6975 xpt_print_path(ccb->ccb_h.path); 6976 printf("Couldn't allocate path\n"); 6977 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6978 return; 6979 } 6980 SLIST_INIT(&lstate->accept_tios); 6981 SLIST_INIT(&lstate->immed_notifies); 6982 ahc_lock(ahc, &s); 6983 ahc_pause(ahc); 6984 if (target != CAM_TARGET_WILDCARD) { 6985 tstate->enabled_luns[lun] = lstate; 6986 ahc->enabled_luns++; 6987 6988 if ((ahc->features & AHC_MULTI_TID) != 0) { 6989 u_int targid_mask; 6990 6991 targid_mask = ahc_inb(ahc, TARGID) 6992 | (ahc_inb(ahc, TARGID + 1) << 8); 6993 6994 targid_mask |= target_mask; 6995 ahc_outb(ahc, TARGID, targid_mask); 6996 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6997 6998 ahc_update_scsiid(ahc, targid_mask); 6999 } else { 7000 u_int our_id; 7001 char channel; 7002 7003 channel = SIM_CHANNEL(ahc, sim); 7004 our_id = SIM_SCSI_ID(ahc, sim); 7005 7006 /* 7007 * This can only happen if selections 7008 * are not enabled 7009 */ 7010 if (target != our_id) { 7011 u_int sblkctl; 7012 char cur_channel; 7013 int swap; 7014 7015 sblkctl = ahc_inb(ahc, SBLKCTL); 7016 cur_channel = (sblkctl & SELBUSB) 7017 ? 'B' : 'A'; 7018 if ((ahc->features & AHC_TWIN) == 0) 7019 cur_channel = 'A'; 7020 swap = cur_channel != channel; 7021 if (channel == 'A') 7022 ahc->our_id = target; 7023 else 7024 ahc->our_id_b = target; 7025 7026 if (swap) 7027 ahc_outb(ahc, SBLKCTL, 7028 sblkctl ^ SELBUSB); 7029 7030 ahc_outb(ahc, SCSIID, target); 7031 7032 if (swap) 7033 ahc_outb(ahc, SBLKCTL, sblkctl); 7034 } 7035 } 7036 } else 7037 ahc->black_hole = lstate; 7038 /* Allow select-in operations */ 7039 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7040 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7041 scsiseq |= ENSELI; 7042 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7043 scsiseq = ahc_inb(ahc, SCSISEQ); 7044 scsiseq |= ENSELI; 7045 ahc_outb(ahc, SCSISEQ, scsiseq); 7046 } 7047 ahc_unpause(ahc); 7048 ahc_unlock(ahc, &s); 7049 ccb->ccb_h.status = CAM_REQ_CMP; 7050 xpt_print_path(ccb->ccb_h.path); 7051 printf("Lun now enabled for target mode\n"); 7052 } else { 7053 struct scb *scb; 7054 int i, empty; 7055 7056 if (lstate == NULL) { 7057 ccb->ccb_h.status = CAM_LUN_INVALID; 7058 return; 7059 } 7060 7061 ahc_lock(ahc, &s); 7062 7063 ccb->ccb_h.status = CAM_REQ_CMP; 7064 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7065 struct ccb_hdr *ccbh; 7066 7067 ccbh = &scb->io_ctx->ccb_h; 7068 if (ccbh->func_code == XPT_CONT_TARGET_IO 7069 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7070 printf("CTIO pending\n"); 7071 ccb->ccb_h.status = CAM_REQ_INVALID; 7072 ahc_unlock(ahc, &s); 7073 return; 7074 } 7075 } 7076 7077 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7078 printf("ATIOs pending\n"); 7079 ccb->ccb_h.status = CAM_REQ_INVALID; 7080 } 7081 7082 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7083 printf("INOTs pending\n"); 7084 ccb->ccb_h.status = CAM_REQ_INVALID; 7085 } 7086 7087 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7088 ahc_unlock(ahc, &s); 7089 return; 7090 } 7091 7092 xpt_print_path(ccb->ccb_h.path); 7093 printf("Target mode disabled\n"); 7094 xpt_free_path(lstate->path); 7095 free(lstate, M_DEVBUF); 7096 7097 ahc_pause(ahc); 7098 /* Can we clean up the target too? */ 7099 if (target != CAM_TARGET_WILDCARD) { 7100 tstate->enabled_luns[lun] = NULL; 7101 ahc->enabled_luns--; 7102 for (empty = 1, i = 0; i < 8; i++) 7103 if (tstate->enabled_luns[i] != NULL) { 7104 empty = 0; 7105 break; 7106 } 7107 7108 if (empty) { 7109 ahc_free_tstate(ahc, target, channel, 7110 /*force*/FALSE); 7111 if (ahc->features & AHC_MULTI_TID) { 7112 u_int targid_mask; 7113 7114 targid_mask = ahc_inb(ahc, TARGID) 7115 | (ahc_inb(ahc, TARGID + 1) 7116 << 8); 7117 7118 targid_mask &= ~target_mask; 7119 ahc_outb(ahc, TARGID, targid_mask); 7120 ahc_outb(ahc, TARGID+1, 7121 (targid_mask >> 8)); 7122 ahc_update_scsiid(ahc, targid_mask); 7123 } 7124 } 7125 } else { 7126 7127 ahc->black_hole = NULL; 7128 7129 /* 7130 * We can't allow selections without 7131 * our black hole device. 7132 */ 7133 empty = TRUE; 7134 } 7135 if (ahc->enabled_luns == 0) { 7136 /* Disallow select-in */ 7137 u_int scsiseq; 7138 7139 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7140 scsiseq &= ~ENSELI; 7141 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7142 scsiseq = ahc_inb(ahc, SCSISEQ); 7143 scsiseq &= ~ENSELI; 7144 ahc_outb(ahc, SCSISEQ, scsiseq); 7145 7146 if ((ahc->features & AHC_MULTIROLE) == 0) { 7147 printf("Configuring Initiator Mode\n"); 7148 ahc->flags &= ~AHC_TARGETROLE; 7149 ahc->flags |= AHC_INITIATORROLE; 7150 ahc_pause(ahc); 7151 ahc_loadseq(ahc); 7152 } 7153 } 7154 ahc_unpause(ahc); 7155 ahc_unlock(ahc, &s); 7156 } 7157 } 7158 7159 static void 7160 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7161 { 7162 u_int scsiid_mask; 7163 u_int scsiid; 7164 7165 if ((ahc->features & AHC_MULTI_TID) == 0) 7166 panic("ahc_update_scsiid called on non-multitid unit\n"); 7167 7168 /* 7169 * Since we will rely on the TARGID mask 7170 * for selection enables, ensure that OID 7171 * in SCSIID is not set to some other ID 7172 * that we don't want to allow selections on. 7173 */ 7174 if ((ahc->features & AHC_ULTRA2) != 0) 7175 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7176 else 7177 scsiid = ahc_inb(ahc, SCSIID); 7178 scsiid_mask = 0x1 << (scsiid & OID); 7179 if ((targid_mask & scsiid_mask) == 0) { 7180 u_int our_id; 7181 7182 /* ffs counts from 1 */ 7183 our_id = ffs(targid_mask); 7184 if (our_id == 0) 7185 our_id = ahc->our_id; 7186 else 7187 our_id--; 7188 scsiid &= TID; 7189 scsiid |= our_id; 7190 } 7191 if ((ahc->features & AHC_ULTRA2) != 0) 7192 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7193 else 7194 ahc_outb(ahc, SCSIID, scsiid); 7195 } 7196 7197 void 7198 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7199 { 7200 struct target_cmd *cmd; 7201 7202 /* 7203 * If the card supports auto-access pause, 7204 * we can access the card directly regardless 7205 * of whether it is paused or not. 7206 */ 7207 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7208 paused = TRUE; 7209 7210 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7211 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7212 7213 /* 7214 * Only advance through the queue if we 7215 * have the resources to process the command. 7216 */ 7217 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7218 break; 7219 7220 cmd->cmd_valid = 0; 7221 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7222 ahc->shared_data_dmamap, 7223 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7224 sizeof(struct target_cmd), 7225 BUS_DMASYNC_PREREAD); 7226 ahc->tqinfifonext++; 7227 7228 /* 7229 * Lazily update our position in the target mode incoming 7230 * command queue as seen by the sequencer. 7231 */ 7232 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7233 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7234 u_int hs_mailbox; 7235 7236 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7237 hs_mailbox &= ~HOST_TQINPOS; 7238 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7239 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7240 } else { 7241 if (!paused) 7242 ahc_pause(ahc); 7243 ahc_outb(ahc, KERNEL_TQINPOS, 7244 ahc->tqinfifonext & HOST_TQINPOS); 7245 if (!paused) 7246 ahc_unpause(ahc); 7247 } 7248 } 7249 } 7250 } 7251 7252 static int 7253 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7254 { 7255 struct ahc_tmode_tstate *tstate; 7256 struct ahc_tmode_lstate *lstate; 7257 struct ccb_accept_tio *atio; 7258 uint8_t *byte; 7259 int initiator; 7260 int target; 7261 int lun; 7262 7263 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7264 target = SCSIID_OUR_ID(cmd->scsiid); 7265 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7266 7267 byte = cmd->bytes; 7268 tstate = ahc->enabled_targets[target]; 7269 lstate = NULL; 7270 if (tstate != NULL) 7271 lstate = tstate->enabled_luns[lun]; 7272 7273 /* 7274 * Commands for disabled luns go to the black hole driver. 7275 */ 7276 if (lstate == NULL) 7277 lstate = ahc->black_hole; 7278 7279 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7280 if (atio == NULL) { 7281 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7282 /* 7283 * Wait for more ATIOs from the peripheral driver for this lun. 7284 */ 7285 if (bootverbose) 7286 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7287 return (1); 7288 } else 7289 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7290 #if 0 7291 printf("Incoming command from %d for %d:%d%s\n", 7292 initiator, target, lun, 7293 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7294 #endif 7295 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7296 7297 if (lstate == ahc->black_hole) { 7298 /* Fill in the wildcards */ 7299 atio->ccb_h.target_id = target; 7300 atio->ccb_h.target_lun = lun; 7301 } 7302 7303 /* 7304 * Package it up and send it off to 7305 * whomever has this lun enabled. 7306 */ 7307 atio->sense_len = 0; 7308 atio->init_id = initiator; 7309 if (byte[0] != 0xFF) { 7310 /* Tag was included */ 7311 atio->tag_action = *byte++; 7312 atio->tag_id = *byte++; 7313 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7314 } else { 7315 atio->ccb_h.flags = 0; 7316 } 7317 byte++; 7318 7319 /* Okay. Now determine the cdb size based on the command code */ 7320 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7321 case 0: 7322 atio->cdb_len = 6; 7323 break; 7324 case 1: 7325 case 2: 7326 atio->cdb_len = 10; 7327 break; 7328 case 4: 7329 atio->cdb_len = 16; 7330 break; 7331 case 5: 7332 atio->cdb_len = 12; 7333 break; 7334 case 3: 7335 default: 7336 /* Only copy the opcode. */ 7337 atio->cdb_len = 1; 7338 printf("Reserved or VU command code type encountered\n"); 7339 break; 7340 } 7341 7342 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7343 7344 atio->ccb_h.status |= CAM_CDB_RECVD; 7345 7346 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7347 /* 7348 * We weren't allowed to disconnect. 7349 * We're hanging on the bus until a 7350 * continue target I/O comes in response 7351 * to this accept tio. 7352 */ 7353 #if 0 7354 printf("Received Immediate Command %d:%d:%d - %p\n", 7355 initiator, target, lun, ahc->pending_device); 7356 #endif 7357 ahc->pending_device = lstate; 7358 ahc_freeze_ccb((union ccb *)atio); 7359 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7360 } 7361 xpt_done((union ccb*)atio); 7362 return (0); 7363 } 7364 #endif 7365 7366 static int 7367 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 7368 bus_dma_tag_t tag; 7369 int size; 7370 int flags; 7371 bus_dmamap_t *mapp; 7372 caddr_t *vaddr; 7373 bus_addr_t *baddr; 7374 bus_dma_segment_t *seg; 7375 int *nseg; 7376 const char *myname, *what; 7377 { 7378 int error, level = 0; 7379 7380 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7381 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7382 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7383 myname, what, error); 7384 goto out; 7385 } 7386 level++; 7387 7388 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7389 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7390 printf("%s: failed to map DMA mem for %s, error = %d\n", 7391 myname, what, error); 7392 goto out; 7393 } 7394 level++; 7395 7396 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7397 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7398 printf("%s: failed to create DMA map for %s, error = %d\n", 7399 myname, what, error); 7400 goto out; 7401 } 7402 level++; 7403 7404 7405 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7406 BUS_DMA_NOWAIT)) != 0) { 7407 printf("%s: failed to load DMA map for %s, error = %d\n", 7408 myname, what, error); 7409 goto out; 7410 } 7411 7412 *baddr = (*mapp)->dm_segs[0].ds_addr; 7413 7414 return 0; 7415 out: 7416 printf("ahc_createdmamem error (%d)\n", level); 7417 switch (level) { 7418 case 3: 7419 bus_dmamap_destroy(tag, *mapp); 7420 /* FALLTHROUGH */ 7421 case 2: 7422 bus_dmamem_unmap(tag, *vaddr, size); 7423 /* FALLTHROUGH */ 7424 case 1: 7425 bus_dmamem_free(tag, seg, *nseg); 7426 break; 7427 default: 7428 break; 7429 } 7430 7431 return error; 7432 } 7433 7434 static void 7435 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 7436 bus_dma_tag_t tag; 7437 int size; 7438 bus_dmamap_t map; 7439 caddr_t vaddr; 7440 bus_dma_segment_t *seg; 7441 int nseg; 7442 { 7443 7444 bus_dmamap_unload(tag, map); 7445 bus_dmamap_destroy(tag, map); 7446 bus_dmamem_unmap(tag, vaddr, size); 7447 bus_dmamem_free(tag, seg, nseg); 7448 } 7449
Indexes created Tue Sep 30 17:09:57 GMT 2025