aic7xxx.c revision 1.112
1 /* $NetBSD: aic7xxx.c,v 1.112 2005/02/27 00:27:00 perry Exp $ */ 2 3 /* 4 * Core routines and tables shareable across OS platforms. 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: aic7xxx.c,v 1.112 2005/02/27 00:27:00 perry Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.112 2005/02/27 00:27:00 perry Exp $"); 54 55 #include <dev/ic/aic7xxx_osm.h> 56 #include <dev/ic/aic7xxx_inline.h> 57 #include <dev/ic/aic7xxx_cam.h> 58 59 /****************************** Softc Data ************************************/ 60 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 61 62 /***************************** Lookup Tables **********************************/ 63 char *ahc_chip_names[] = 64 { 65 "NONE", 66 "aic7770", 67 "aic7850", 68 "aic7855", 69 "aic7859", 70 "aic7860", 71 "aic7870", 72 "aic7880", 73 "aic7895", 74 "aic7895C", 75 "aic7890/91", 76 "aic7896/97", 77 "aic7892", 78 "aic7899" 79 }; 80 81 /* 82 * Hardware error codes. 83 */ 84 struct ahc_hard_error_entry { 85 uint8_t errno; 86 char *errmesg; 87 }; 88 89 static struct ahc_hard_error_entry ahc_hard_errors[] = { 90 { ILLHADDR, "Illegal Host Access" }, 91 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 92 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 93 { SQPARERR, "Sequencer Parity Error" }, 94 { DPARERR, "Data-path Parity Error" }, 95 { MPARERR, "Scratch or SCB Memory Parity Error" }, 96 { PCIERRSTAT, "PCI Error detected" }, 97 { CIOPARERR, "CIOBUS Parity Error" }, 98 }; 99 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 100 101 static struct ahc_phase_table_entry ahc_phase_table[] = 102 { 103 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 104 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 105 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 106 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 107 { P_COMMAND, MSG_NOOP, "in Command phase" }, 108 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 109 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 110 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 111 { P_BUSFREE, MSG_NOOP, "while idle" }, 112 { 0, MSG_NOOP, "in unknown phase" } 113 }; 114 115 /* 116 * In most cases we only wish to itterate over real phases, so 117 * exclude the last element from the count. 118 */ 119 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 120 121 /* 122 * Valid SCSIRATE values. (p. 3-17) 123 * Provides a mapping of transfer periods in ns to the proper value to 124 * stick in the scsixfer reg. 125 */ 126 static struct ahc_syncrate ahc_syncrates[] = 127 { 128 /* ultra2 fast/ultra period rate */ 129 { 0x42, 0x000, 9, "80.0" }, 130 { 0x03, 0x000, 10, "40.0" }, 131 { 0x04, 0x000, 11, "33.0" }, 132 { 0x05, 0x100, 12, "20.0" }, 133 { 0x06, 0x110, 15, "16.0" }, 134 { 0x07, 0x120, 18, "13.4" }, 135 { 0x08, 0x000, 25, "10.0" }, 136 { 0x19, 0x010, 31, "8.0" }, 137 { 0x1a, 0x020, 37, "6.67" }, 138 { 0x1b, 0x030, 43, "5.7" }, 139 { 0x1c, 0x040, 50, "5.0" }, 140 { 0x00, 0x050, 56, "4.4" }, 141 { 0x00, 0x060, 62, "4.0" }, 142 { 0x00, 0x070, 68, "3.6" }, 143 { 0x00, 0x000, 0, NULL } 144 }; 145 146 /* Our Sequencer Program */ 147 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 148 149 /**************************** Function Declarations ***************************/ 150 static void ahc_force_renegotiation(struct ahc_softc *ahc); 151 static struct ahc_tmode_tstate* 152 ahc_alloc_tstate(struct ahc_softc *ahc, 153 u_int scsi_id, char channel); 154 #ifdef AHC_TARGET_MODE 155 static void ahc_free_tstate(struct ahc_softc *ahc, 156 u_int scsi_id, char channel, int force); 157 #endif 158 static struct ahc_syncrate* 159 ahc_devlimited_syncrate(struct ahc_softc *ahc, 160 struct ahc_initiator_tinfo *, 161 u_int *period, 162 u_int *ppr_options, 163 role_t role); 164 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 165 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo); 167 static void ahc_scb_devinfo(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo, 169 struct scb *scb); 170 static void ahc_assert_atn(struct ahc_softc *ahc); 171 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 172 struct ahc_devinfo *devinfo, 173 struct scb *scb); 174 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo); 176 static void ahc_construct_sdtr(struct ahc_softc *ahc, 177 struct ahc_devinfo *devinfo, 178 u_int period, u_int offset); 179 static void ahc_construct_wdtr(struct ahc_softc *ahc, 180 struct ahc_devinfo *devinfo, 181 u_int bus_width); 182 static void ahc_construct_ppr(struct ahc_softc *ahc, 183 struct ahc_devinfo *devinfo, 184 u_int period, u_int offset, 185 u_int bus_width, u_int ppr_options); 186 static void ahc_clear_msg_state(struct ahc_softc *ahc); 187 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 188 static void ahc_handle_message_phase(struct ahc_softc *ahc); 189 typedef enum { 190 AHCMSG_1B, 191 AHCMSG_2B, 192 AHCMSG_EXT 193 } ahc_msgtype; 194 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 195 u_int msgval, int full); 196 static int ahc_parse_msg(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 201 struct ahc_devinfo *devinfo); 202 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 203 static void ahc_handle_devreset(struct ahc_softc *ahc, 204 struct ahc_devinfo *devinfo, 205 cam_status status, char *message, 206 int verbose_level); 207 #if AHC_TARGET_MODE 208 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 209 struct ahc_devinfo *devinfo, 210 struct scb *scb); 211 #endif 212 213 //static bus_dmamap_callback_t ahc_dmamap_cb; 214 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 215 static int ahc_init_scbdata(struct ahc_softc *ahc); 216 static void ahc_fini_scbdata(struct ahc_softc *ahc); 217 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 218 struct scb *prev_scb, 219 struct scb *scb); 220 static int ahc_qinfifo_count(struct ahc_softc *ahc); 221 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 222 u_int prev, u_int scbptr); 223 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 224 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 225 u_int scbpos, u_int prev); 226 static void ahc_reset_current_bus(struct ahc_softc *ahc); 227 #ifdef AHC_DUMP_SEQ 228 static void ahc_dumpseq(struct ahc_softc *ahc); 229 #endif 230 static void ahc_loadseq(struct ahc_softc *ahc); 231 static int ahc_check_patch(struct ahc_softc *ahc, 232 struct patch **start_patch, 233 u_int start_instr, u_int *skip_addr); 234 static void ahc_download_instr(struct ahc_softc *ahc, 235 u_int instrptr, uint8_t *dconsts); 236 #ifdef AHC_TARGET_MODE 237 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 238 struct ahc_tmode_lstate *lstate, 239 u_int initiator_id, 240 u_int event_type, 241 u_int event_arg); 242 static void ahc_update_scsiid(struct ahc_softc *ahc, 243 u_int targid_mask); 244 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 245 struct target_cmd *cmd); 246 #endif 247 248 /************************** Added for porting to NetBSD ***********************/ 249 static int ahc_createdmamem(bus_dma_tag_t tag, 250 int size, 251 int flags, 252 bus_dmamap_t *mapp, 253 caddr_t *vaddr, 254 bus_addr_t *baddr, 255 bus_dma_segment_t *seg, 256 int *nseg, 257 const char *myname, const char *what); 258 static void ahc_freedmamem(bus_dma_tag_t tag, 259 int size, 260 bus_dmamap_t map, 261 caddr_t vaddr, 262 bus_dma_segment_t *seg, 263 int nseg); 264 265 /************************* Sequencer Execution Control ************************/ 266 /* 267 * Restart the sequencer program from address zero 268 */ 269 void 270 ahc_restart(struct ahc_softc *ahc) 271 { 272 273 ahc_pause(ahc); 274 275 /* No more pending messages. */ 276 ahc_clear_msg_state(ahc); 277 278 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 279 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 280 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 281 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 282 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 283 ahc_outb(ahc, SAVED_LUN, 0xFF); 284 285 /* 286 * Ensure that the sequencer's idea of TQINPOS 287 * matches our own. The sequencer increments TQINPOS 288 * only after it sees a DMA complete and a reset could 289 * occur before the increment leaving the kernel to believe 290 * the command arrived but the sequencer to not. 291 */ 292 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 293 294 /* Always allow reselection */ 295 ahc_outb(ahc, SCSISEQ, 296 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 297 if ((ahc->features & AHC_CMD_CHAN) != 0) { 298 /* Ensure that no DMA operations are in progress */ 299 ahc_outb(ahc, CCSCBCNT, 0); 300 ahc_outb(ahc, CCSGCTL, 0); 301 ahc_outb(ahc, CCSCBCTL, 0); 302 } 303 /* 304 * If we were in the process of DMA'ing SCB data into 305 * an SCB, replace that SCB on the free list. This prevents 306 * an SCB leak. 307 */ 308 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 309 ahc_add_curscb_to_free_list(ahc); 310 ahc_outb(ahc, SEQ_FLAGS2, 311 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 312 } 313 ahc_outb(ahc, MWI_RESIDUAL, 0); 314 ahc_outb(ahc, SEQCTL, FASTMODE); 315 ahc_outb(ahc, SEQADDR0, 0); 316 ahc_outb(ahc, SEQADDR1, 0); 317 ahc_unpause(ahc); 318 } 319 320 /************************* Input/Output Queues ********************************/ 321 void 322 ahc_run_qoutfifo(struct ahc_softc *ahc) 323 { 324 struct scb *scb; 325 u_int scb_index; 326 327 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 328 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 329 330 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 331 if ((ahc->qoutfifonext & 0x03) == 0x03) { 332 u_int modnext; 333 334 /* 335 * Clear 32bits of QOUTFIFO at a time 336 * so that we don't clobber an incoming 337 * byte DMA to the array on architectures 338 * that only support 32bit load and store 339 * operations. 340 */ 341 modnext = ahc->qoutfifonext & ~0x3; 342 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 343 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 344 ahc->shared_data_dmamap, 345 /*offset*/modnext, /*len*/4, 346 BUS_DMASYNC_PREREAD); 347 } 348 ahc->qoutfifonext++; 349 350 scb = ahc_lookup_scb(ahc, scb_index); 351 if (scb == NULL) { 352 printf("%s: WARNING no command for scb %d " 353 "(cmdcmplt)\nQOUTPOS = %d\n", 354 ahc_name(ahc), scb_index, 355 (ahc->qoutfifonext - 1) & 0xFF); 356 continue; 357 } 358 359 /* 360 * Save off the residual 361 * if there is one. 362 */ 363 ahc_update_residual(ahc, scb); 364 ahc_done(ahc, scb); 365 } 366 } 367 368 void 369 ahc_run_untagged_queues(struct ahc_softc *ahc) 370 { 371 int i; 372 373 for (i = 0; i < 16; i++) 374 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 375 } 376 377 void 378 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 379 { 380 struct scb *scb; 381 382 if (ahc->untagged_queue_lock != 0) 383 return; 384 385 if ((scb = TAILQ_FIRST(queue)) != NULL 386 && (scb->flags & SCB_ACTIVE) == 0) { 387 scb->flags |= SCB_ACTIVE; 388 ahc_queue_scb(ahc, scb); 389 } 390 } 391 392 /************************* Interrupt Handling *********************************/ 393 void 394 ahc_handle_brkadrint(struct ahc_softc *ahc) 395 { 396 /* 397 * We upset the sequencer :-( 398 * Lookup the error message 399 */ 400 int i; 401 int error; 402 403 error = ahc_inb(ahc, ERROR); 404 for (i = 0; error != 1 && i < num_errors; i++) 405 error >>= 1; 406 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 407 ahc_name(ahc), ahc_hard_errors[i].errmesg, 408 ahc_inb(ahc, SEQADDR0) | 409 (ahc_inb(ahc, SEQADDR1) << 8)); 410 411 ahc_dump_card_state(ahc); 412 413 /* Tell everyone that this HBA is no longer available */ 414 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 415 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 416 CAM_NO_HBA); 417 418 /* Disable all interrupt sources by resetting the controller */ 419 ahc_shutdown(ahc); 420 } 421 422 void 423 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 424 { 425 struct scb *scb; 426 struct ahc_devinfo devinfo; 427 428 ahc_fetch_devinfo(ahc, &devinfo); 429 430 /* 431 * Clear the upper byte that holds SEQINT status 432 * codes and clear the SEQINT bit. We will unpause 433 * the sequencer, if appropriate, after servicing 434 * the request. 435 */ 436 ahc_outb(ahc, CLRINT, CLRSEQINT); 437 switch (intstat & SEQINT_MASK) { 438 case BAD_STATUS: 439 { 440 u_int scb_index; 441 struct hardware_scb *hscb; 442 443 /* 444 * Set the default return value to 0 (don't 445 * send sense). The sense code will change 446 * this if needed. 447 */ 448 ahc_outb(ahc, RETURN_1, 0); 449 450 /* 451 * The sequencer will notify us when a command 452 * has an error that would be of interest to 453 * the kernel. This allows us to leave the sequencer 454 * running in the common case of command completes 455 * without error. The sequencer will already have 456 * DMA'd the SCB back up to us, so we can reference 457 * the in kernel copy directly. 458 */ 459 scb_index = ahc_inb(ahc, SCB_TAG); 460 scb = ahc_lookup_scb(ahc, scb_index); 461 if (scb == NULL) { 462 ahc_print_devinfo(ahc, &devinfo); 463 printf("ahc_intr - referenced scb " 464 "not valid during seqint 0x%x scb(%d)\n", 465 intstat, scb_index); 466 ahc_dump_card_state(ahc); 467 panic("for safety"); 468 goto unpause; 469 } 470 471 hscb = scb->hscb; 472 473 /* Don't want to clobber the original sense code */ 474 if ((scb->flags & SCB_SENSE) != 0) { 475 /* 476 * Clear the SCB_SENSE Flag and have 477 * the sequencer do a normal command 478 * complete. 479 */ 480 scb->flags &= ~SCB_SENSE; 481 break; 482 } 483 /* Freeze the queue until the client sees the error. */ 484 ahc_freeze_devq(ahc, scb); 485 ahc_freeze_scb(scb); 486 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 487 switch (hscb->shared_data.status.scsi_status) { 488 case SCSI_STATUS_OK: 489 printf("%s: Interrupted for status of 0 (?)\n", 490 ahc_name(ahc)); 491 break; 492 case SCSI_STATUS_CMD_TERMINATED: 493 case SCSI_STATUS_CHECK_COND: 494 { 495 struct ahc_dma_seg *sg; 496 struct scsi_request_sense *sc; 497 struct ahc_initiator_tinfo *targ_info; 498 struct ahc_tmode_tstate *tstate; 499 struct ahc_transinfo *tinfo; 500 #ifdef AHC_DEBUG 501 if (ahc_debug & AHC_SHOW_SENSE) { 502 ahc_print_path(ahc, scb); 503 printf("SCB %d: requests Check Status\n", 504 scb->hscb->tag); 505 } 506 #endif 507 508 if (ahc_perform_autosense(scb) == 0) 509 break; 510 511 targ_info = ahc_fetch_transinfo(ahc, 512 devinfo.channel, 513 devinfo.our_scsiid, 514 devinfo.target, 515 &tstate); 516 tinfo = &targ_info->curr; 517 sg = scb->sg_list; 518 sc = (struct scsi_request_sense *)(&hscb->shared_data.cdb); 519 /* 520 * Save off the residual if there is one. 521 */ 522 ahc_update_residual(ahc, scb); 523 #ifdef AHC_DEBUG 524 if (ahc_debug & AHC_SHOW_SENSE) { 525 ahc_print_path(ahc, scb); 526 printf("Sending Sense\n"); 527 } 528 #endif 529 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 530 sg->len = ahc_get_sense_bufsize(ahc, scb); 531 sg->len |= AHC_DMA_LAST_SEG; 532 533 /* Fixup byte order */ 534 sg->addr = ahc_htole32(sg->addr); 535 sg->len = ahc_htole32(sg->len); 536 537 memset(sc, 0, sizeof(*sc)); 538 sc->opcode = SCSI_REQUEST_SENSE; 539 if (tinfo->protocol_version <= SCSI_REV_2 540 && SCB_GET_LUN(scb) < 8) 541 sc->byte2 = SCB_GET_LUN(scb) << 5; 542 sc->length = sg->len; 543 544 /* 545 * We can't allow the target to disconnect. 546 * This will be an untagged transaction and 547 * having the target disconnect will make this 548 * transaction indistinguishable from outstanding 549 * tagged transactions. 550 */ 551 hscb->control = 0; 552 553 /* 554 * This request sense could be because the 555 * the device lost power or in some other 556 * way has lost our transfer negotiations. 557 * Renegotiate if appropriate. Unit attention 558 * errors will be reported before any data 559 * phases occur. 560 */ 561 if (ahc_get_residual(scb) 562 == ahc_get_transfer_length(scb)) { 563 ahc_update_neg_request(ahc, &devinfo, 564 tstate, targ_info, 565 AHC_NEG_IF_NON_ASYNC); 566 } 567 if (tstate->auto_negotiate & devinfo.target_mask) { 568 hscb->control |= MK_MESSAGE; 569 scb->flags &= ~SCB_NEGOTIATE; 570 scb->flags |= SCB_AUTO_NEGOTIATE; 571 } 572 hscb->cdb_len = sizeof(*sc); 573 hscb->dataptr = sg->addr; 574 hscb->datacnt = sg->len; 575 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 576 hscb->sgptr = ahc_htole32(hscb->sgptr); 577 scb->sg_count = 1; 578 scb->flags |= SCB_SENSE; 579 ahc_qinfifo_requeue_tail(ahc, scb); 580 ahc_outb(ahc, RETURN_1, SEND_SENSE); 581 /* 582 * Ensure we have enough time to actually 583 * retrieve the sense. 584 */ 585 ahc_scb_timer_reset(scb, 5 * 1000000); 586 break; 587 } 588 default: 589 break; 590 } 591 break; 592 } 593 case NO_MATCH: 594 { 595 /* Ensure we don't leave the selection hardware on */ 596 ahc_outb(ahc, SCSISEQ, 597 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 598 599 printf("%s:%c:%d: no active SCB for reconnecting " 600 "target - issuing BUS DEVICE RESET\n", 601 ahc_name(ahc), devinfo.channel, devinfo.target); 602 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 603 "ARG_1 == 0x%x ACCUM = 0x%x\n", 604 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 605 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 606 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 607 "SINDEX == 0x%x\n", 608 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 609 ahc_index_busy_tcl(ahc, 610 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 611 ahc_inb(ahc, SAVED_LUN))), 612 ahc_inb(ahc, SINDEX)); 613 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 614 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 615 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 616 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 617 ahc_inb(ahc, SCB_CONTROL)); 618 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 619 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 620 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 621 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 622 ahc_dump_card_state(ahc); 623 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 624 ahc->msgout_len = 1; 625 ahc->msgout_index = 0; 626 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 627 ahc_outb(ahc, MSG_OUT, HOST_MSG); 628 ahc_assert_atn(ahc); 629 break; 630 } 631 case SEND_REJECT: 632 { 633 u_int rejbyte = ahc_inb(ahc, ACCUM); 634 printf("%s:%c:%d: Warning - unknown message received from " 635 "target (0x%x). Rejecting\n", 636 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 637 break; 638 } 639 case PROTO_VIOLATION: 640 { 641 ahc_handle_proto_violation(ahc); 642 break; 643 } 644 case IGN_WIDE_RES: 645 ahc_handle_ign_wide_residue(ahc, &devinfo); 646 break; 647 case PDATA_REINIT: 648 ahc_reinitialize_dataptrs(ahc); 649 break; 650 case BAD_PHASE: 651 { 652 u_int lastphase; 653 654 lastphase = ahc_inb(ahc, LASTPHASE); 655 printf("%s:%c:%d: unknown scsi bus phase %x, " 656 "lastphase = 0x%x. Attempting to continue\n", 657 ahc_name(ahc), devinfo.channel, devinfo.target, 658 lastphase, ahc_inb(ahc, SCSISIGI)); 659 break; 660 } 661 case MISSED_BUSFREE: 662 { 663 u_int lastphase; 664 665 lastphase = ahc_inb(ahc, LASTPHASE); 666 printf("%s:%c:%d: Missed busfree. " 667 "Lastphase = 0x%x, Curphase = 0x%x\n", 668 ahc_name(ahc), devinfo.channel, devinfo.target, 669 lastphase, ahc_inb(ahc, SCSISIGI)); 670 ahc_restart(ahc); 671 return; 672 } 673 case HOST_MSG_LOOP: 674 { 675 /* 676 * The sequencer has encountered a message phase 677 * that requires host assistance for completion. 678 * While handling the message phase(s), we will be 679 * notified by the sequencer after each byte is 680 * transferred so we can track bus phase changes. 681 * 682 * If this is the first time we've seen a HOST_MSG_LOOP 683 * interrupt, initialize the state of the host message 684 * loop. 685 */ 686 if (ahc->msg_type == MSG_TYPE_NONE) { 687 struct scb *scb; 688 u_int scb_index; 689 u_int bus_phase; 690 691 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 692 if (bus_phase != P_MESGIN 693 && bus_phase != P_MESGOUT) { 694 printf("ahc_intr: HOST_MSG_LOOP bad " 695 "phase 0x%x\n", 696 bus_phase); 697 /* 698 * Probably transitioned to bus free before 699 * we got here. Just punt the message. 700 */ 701 ahc_clear_intstat(ahc); 702 ahc_restart(ahc); 703 return; 704 } 705 706 scb_index = ahc_inb(ahc, SCB_TAG); 707 scb = ahc_lookup_scb(ahc, scb_index); 708 if (devinfo.role == ROLE_INITIATOR) { 709 if (scb == NULL) 710 panic("HOST_MSG_LOOP with " 711 "invalid SCB %x\n", scb_index); 712 713 if (bus_phase == P_MESGOUT) 714 ahc_setup_initiator_msgout(ahc, 715 &devinfo, 716 scb); 717 else { 718 ahc->msg_type = 719 MSG_TYPE_INITIATOR_MSGIN; 720 ahc->msgin_index = 0; 721 } 722 } 723 #if AHC_TARGET_MODE 724 else { 725 if (bus_phase == P_MESGOUT) { 726 ahc->msg_type = 727 MSG_TYPE_TARGET_MSGOUT; 728 ahc->msgin_index = 0; 729 } 730 else 731 ahc_setup_target_msgin(ahc, 732 &devinfo, 733 scb); 734 } 735 #endif 736 } 737 738 ahc_handle_message_phase(ahc); 739 break; 740 } 741 case PERR_DETECTED: 742 { 743 /* 744 * If we've cleared the parity error interrupt 745 * but the sequencer still believes that SCSIPERR 746 * is true, it must be that the parity error is 747 * for the currently presented byte on the bus, 748 * and we are not in a phase (data-in) where we will 749 * eventually ack this byte. Ack the byte and 750 * throw it away in the hope that the target will 751 * take us to message out to deliver the appropriate 752 * error message. 753 */ 754 if ((intstat & SCSIINT) == 0 755 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 756 757 if ((ahc->features & AHC_DT) == 0) { 758 u_int curphase; 759 760 /* 761 * The hardware will only let you ack bytes 762 * if the expected phase in SCSISIGO matches 763 * the current phase. Make sure this is 764 * currently the case. 765 */ 766 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 767 ahc_outb(ahc, LASTPHASE, curphase); 768 ahc_outb(ahc, SCSISIGO, curphase); 769 } 770 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 771 int wait; 772 773 /* 774 * In a data phase. Faster to bitbucket 775 * the data than to individually ack each 776 * byte. This is also the only strategy 777 * that will work with AUTOACK enabled. 778 */ 779 ahc_outb(ahc, SXFRCTL1, 780 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 781 wait = 5000; 782 while (--wait != 0) { 783 if ((ahc_inb(ahc, SCSISIGI) 784 & (CDI|MSGI)) != 0) 785 break; 786 ahc_delay(100); 787 } 788 ahc_outb(ahc, SXFRCTL1, 789 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 790 if (wait == 0) { 791 struct scb *scb; 792 u_int scb_index; 793 794 ahc_print_devinfo(ahc, &devinfo); 795 printf("Unable to clear parity error. " 796 "Resetting bus.\n"); 797 scb_index = ahc_inb(ahc, SCB_TAG); 798 scb = ahc_lookup_scb(ahc, scb_index); 799 if (scb != NULL) 800 ahc_set_transaction_status(scb, 801 CAM_UNCOR_PARITY); 802 ahc_reset_channel(ahc, devinfo.channel, 803 /*init reset*/TRUE); 804 } 805 } else { 806 ahc_inb(ahc, SCSIDATL); 807 } 808 } 809 break; 810 } 811 case DATA_OVERRUN: 812 { 813 /* 814 * When the sequencer detects an overrun, it 815 * places the controller in "BITBUCKET" mode 816 * and allows the target to complete its transfer. 817 * Unfortunately, none of the counters get updated 818 * when the controller is in this mode, so we have 819 * no way of knowing how large the overrun was. 820 */ 821 u_int scbindex = ahc_inb(ahc, SCB_TAG); 822 u_int lastphase = ahc_inb(ahc, LASTPHASE); 823 u_int i; 824 825 scb = ahc_lookup_scb(ahc, scbindex); 826 for (i = 0; i < num_phases; i++) { 827 if (lastphase == ahc_phase_table[i].phase) 828 break; 829 } 830 ahc_print_path(ahc, scb); 831 printf("data overrun detected %s." 832 " Tag == 0x%x.\n", 833 ahc_phase_table[i].phasemsg, 834 scb->hscb->tag); 835 ahc_print_path(ahc, scb); 836 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 837 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 838 ahc_get_transfer_length(scb), scb->sg_count); 839 if (scb->sg_count > 0) { 840 for (i = 0; i < scb->sg_count; i++) { 841 842 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 843 i, 844 (ahc_le32toh(scb->sg_list[i].len) >> 24 845 & SG_HIGH_ADDR_BITS), 846 ahc_le32toh(scb->sg_list[i].addr), 847 ahc_le32toh(scb->sg_list[i].len) 848 & AHC_SG_LEN_MASK); 849 } 850 } 851 /* 852 * Set this and it will take effect when the 853 * target does a command complete. 854 */ 855 ahc_freeze_devq(ahc, scb); 856 if ((scb->flags & SCB_SENSE) == 0) { 857 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 858 } else { 859 scb->flags &= ~SCB_SENSE; 860 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 861 } 862 ahc_freeze_scb(scb); 863 864 if ((ahc->features & AHC_ULTRA2) != 0) { 865 /* 866 * Clear the channel in case we return 867 * to data phase later. 868 */ 869 ahc_outb(ahc, SXFRCTL0, 870 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 871 ahc_outb(ahc, SXFRCTL0, 872 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 873 } 874 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 875 u_int dscommand1; 876 877 /* Ensure HHADDR is 0 for future DMA operations. */ 878 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 879 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 880 ahc_outb(ahc, HADDR, 0); 881 ahc_outb(ahc, DSCOMMAND1, dscommand1); 882 } 883 break; 884 } 885 case MKMSG_FAILED: 886 { 887 u_int scbindex; 888 889 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 890 ahc_name(ahc), devinfo.channel, devinfo.target, 891 devinfo.lun); 892 scbindex = ahc_inb(ahc, SCB_TAG); 893 scb = ahc_lookup_scb(ahc, scbindex); 894 if (scb != NULL 895 && (scb->flags & SCB_RECOVERY_SCB) != 0) 896 /* 897 * Ensure that we didn't put a second instance of this 898 * SCB into the QINFIFO. 899 */ 900 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 901 SCB_GET_CHANNEL(ahc, scb), 902 SCB_GET_LUN(scb), scb->hscb->tag, 903 ROLE_INITIATOR, /*status*/0, 904 SEARCH_REMOVE); 905 break; 906 } 907 case NO_FREE_SCB: 908 { 909 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 910 ahc_dump_card_state(ahc); 911 panic("for safety"); 912 break; 913 } 914 case SCB_MISMATCH: 915 { 916 u_int scbptr; 917 918 scbptr = ahc_inb(ahc, SCBPTR); 919 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 920 scbptr, ahc_inb(ahc, ARG_1), 921 ahc->scb_data->hscbs[scbptr].tag); 922 ahc_dump_card_state(ahc); 923 panic("for saftey"); 924 break; 925 } 926 case OUT_OF_RANGE: 927 { 928 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 929 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 930 "ARG_1 == 0x%x ACCUM = 0x%x\n", 931 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 932 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 933 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 934 "SINDEX == 0x%x\n, A == 0x%x\n", 935 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 936 ahc_index_busy_tcl(ahc, 937 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 938 ahc_inb(ahc, SAVED_LUN))), 939 ahc_inb(ahc, SINDEX), 940 ahc_inb(ahc, ACCUM)); 941 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 942 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 943 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 944 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 945 ahc_inb(ahc, SCB_CONTROL)); 946 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 947 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 948 ahc_dump_card_state(ahc); 949 panic("for safety"); 950 break; 951 } 952 default: 953 printf("ahc_intr: seqint, " 954 "intstat == 0x%x, scsisigi = 0x%x\n", 955 intstat, ahc_inb(ahc, SCSISIGI)); 956 break; 957 } 958 unpause: 959 /* 960 * The sequencer is paused immediately on 961 * a SEQINT, so we should restart it when 962 * we're done. 963 */ 964 ahc_unpause(ahc); 965 } 966 967 void 968 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 969 { 970 u_int scb_index; 971 u_int status0; 972 u_int status; 973 struct scb *scb; 974 char cur_channel; 975 char intr_channel; 976 977 if ((ahc->features & AHC_TWIN) != 0 978 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 979 cur_channel = 'B'; 980 else 981 cur_channel = 'A'; 982 intr_channel = cur_channel; 983 984 if ((ahc->features & AHC_ULTRA2) != 0) 985 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 986 else 987 status0 = 0; 988 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 989 if (status == 0 && status0 == 0) { 990 if ((ahc->features & AHC_TWIN) != 0) { 991 /* Try the other channel */ 992 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 993 status = ahc_inb(ahc, SSTAT1) 994 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 995 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 996 } 997 if (status == 0) { 998 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 999 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1000 ahc_unpause(ahc); 1001 return; 1002 } 1003 } 1004 1005 /* Make sure the sequencer is in a safe location. */ 1006 ahc_clear_critical_section(ahc); 1007 1008 scb_index = ahc_inb(ahc, SCB_TAG); 1009 scb = ahc_lookup_scb(ahc, scb_index); 1010 if (scb != NULL 1011 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1012 scb = NULL; 1013 1014 if ((ahc->features & AHC_ULTRA2) != 0 1015 && (status0 & IOERR) != 0) { 1016 int now_lvd; 1017 1018 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1019 printf("%s: Transceiver State Has Changed to %s mode\n", 1020 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1021 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1022 /* 1023 * When transitioning to SE mode, the reset line 1024 * glitches, triggering an arbitration bug in some 1025 * Ultra2 controllers. This bug is cleared when we 1026 * assert the reset line. Since a reset glitch has 1027 * already occurred with this transition and a 1028 * transceiver state change is handled just like 1029 * a bus reset anyway, asserting the reset line 1030 * ourselves is safe. 1031 */ 1032 ahc_reset_channel(ahc, intr_channel, 1033 /*Initiate Reset*/now_lvd == 0); 1034 } else if ((status & SCSIRSTI) != 0) { 1035 printf("%s: Someone reset channel %c\n", 1036 ahc_name(ahc), intr_channel); 1037 if (intr_channel != cur_channel) 1038 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1039 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1040 } else if ((status & SCSIPERR) != 0) { 1041 /* 1042 * Determine the bus phase and queue an appropriate message. 1043 * SCSIPERR is latched true as soon as a parity error 1044 * occurs. If the sequencer acked the transfer that 1045 * caused the parity error and the currently presented 1046 * transfer on the bus has correct parity, SCSIPERR will 1047 * be cleared by CLRSCSIPERR. Use this to determine if 1048 * we should look at the last phase the sequencer recorded, 1049 * or the current phase presented on the bus. 1050 */ 1051 u_int mesg_out; 1052 u_int curphase; 1053 u_int errorphase; 1054 u_int lastphase; 1055 u_int scsirate; 1056 u_int i; 1057 u_int sstat2; 1058 int silent; 1059 1060 lastphase = ahc_inb(ahc, LASTPHASE); 1061 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1062 sstat2 = ahc_inb(ahc, SSTAT2); 1063 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1064 /* 1065 * For all phases save DATA, the sequencer won't 1066 * automatically ack a byte that has a parity error 1067 * in it. So the only way that the current phase 1068 * could be 'data-in' is if the parity error is for 1069 * an already acked byte in the data phase. During 1070 * synchronous data-in transfers, we may actually 1071 * ack bytes before latching the current phase in 1072 * LASTPHASE, leading to the discrepancy between 1073 * curphase and lastphase. 1074 */ 1075 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1076 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1077 errorphase = curphase; 1078 else 1079 errorphase = lastphase; 1080 1081 for (i = 0; i < num_phases; i++) { 1082 if (errorphase == ahc_phase_table[i].phase) 1083 break; 1084 } 1085 mesg_out = ahc_phase_table[i].mesg_out; 1086 silent = FALSE; 1087 if (scb != NULL) { 1088 if (SCB_IS_SILENT(scb)) 1089 silent = TRUE; 1090 else 1091 ahc_print_path(ahc, scb); 1092 scb->flags |= SCB_TRANSMISSION_ERROR; 1093 } else 1094 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1095 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1096 scsirate = ahc_inb(ahc, SCSIRATE); 1097 if (silent == FALSE) { 1098 printf("parity error detected %s. " 1099 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1100 ahc_phase_table[i].phasemsg, 1101 ahc_inw(ahc, SEQADDR0), 1102 scsirate); 1103 if ((ahc->features & AHC_DT) != 0) { 1104 if ((sstat2 & CRCVALERR) != 0) 1105 printf("\tCRC Value Mismatch\n"); 1106 if ((sstat2 & CRCENDERR) != 0) 1107 printf("\tNo terminal CRC packet " 1108 "recevied\n"); 1109 if ((sstat2 & CRCREQERR) != 0) 1110 printf("\tIllegal CRC packet " 1111 "request\n"); 1112 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1113 printf("\tUnexpected %sDT Data Phase\n", 1114 (scsirate & SINGLE_EDGE) 1115 ? "" : "non-"); 1116 } 1117 } 1118 1119 if ((ahc->features & AHC_DT) != 0 1120 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1121 /* 1122 * This error applies regardless of 1123 * data direction, so ignore the value 1124 * in the phase table. 1125 */ 1126 mesg_out = MSG_INITIATOR_DET_ERR; 1127 } 1128 1129 /* 1130 * We've set the hardware to assert ATN if we 1131 * get a parity error on "in" phases, so all we 1132 * need to do is stuff the message buffer with 1133 * the appropriate message. "In" phases have set 1134 * mesg_out to something other than MSG_NOP. 1135 */ 1136 if (mesg_out != MSG_NOOP) { 1137 if (ahc->msg_type != MSG_TYPE_NONE) 1138 ahc->send_msg_perror = TRUE; 1139 else 1140 ahc_outb(ahc, MSG_OUT, mesg_out); 1141 } 1142 /* 1143 * Force a renegotiation with this target just in 1144 * case we are out of sync for some external reason 1145 * unknown (or unreported) by the target. 1146 */ 1147 ahc_force_renegotiation(ahc); 1148 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1149 ahc_unpause(ahc); 1150 } else if ((status & SELTO) != 0) { 1151 u_int scbptr; 1152 1153 /* Stop the selection */ 1154 ahc_outb(ahc, SCSISEQ, 0); 1155 1156 /* No more pending messages */ 1157 ahc_clear_msg_state(ahc); 1158 1159 /* Clear interrupt state */ 1160 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1161 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1162 1163 /* 1164 * Although the driver does not care about the 1165 * 'Selection in Progress' status bit, the busy 1166 * LED does. SELINGO is only cleared by a sucessfull 1167 * selection, so we must manually clear it to insure 1168 * the LED turns off just incase no future successful 1169 * selections occur (e.g. no devices on the bus). 1170 */ 1171 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1172 1173 scbptr = ahc_inb(ahc, WAITING_SCBH); 1174 ahc_outb(ahc, SCBPTR, scbptr); 1175 scb_index = ahc_inb(ahc, SCB_TAG); 1176 1177 scb = ahc_lookup_scb(ahc, scb_index); 1178 if (scb == NULL) { 1179 printf("%s: ahc_intr - referenced scb not " 1180 "valid during SELTO scb(%d, %d)\n", 1181 ahc_name(ahc), scbptr, scb_index); 1182 ahc_dump_card_state(ahc); 1183 } else { 1184 #ifdef AHC_DEBUG 1185 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1186 ahc_print_path(ahc, scb); 1187 printf("Saw Selection Timeout for SCB 0x%x\n", 1188 scb_index); 1189 } 1190 #endif 1191 /* 1192 * Force a renegotiation with this target just in 1193 * case the cable was pulled and will later be 1194 * re-attached. The target may forget its negotiation 1195 * settings with us should it attempt to reselect 1196 * during the interruption. The target will not issue 1197 * a unit attention in this case, so we must always 1198 * renegotiate. 1199 */ 1200 ahc_force_renegotiation(ahc); 1201 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1202 ahc_freeze_devq(ahc, scb); 1203 } 1204 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1205 ahc_restart(ahc); 1206 } else if ((status & BUSFREE) != 0 1207 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1208 u_int lastphase; 1209 u_int saved_scsiid; 1210 u_int saved_lun; 1211 u_int target; 1212 u_int initiator_role_id; 1213 char channel; 1214 int printerror; 1215 1216 /* 1217 * Clear our selection hardware as soon as possible. 1218 * We may have an entry in the waiting Q for this target, 1219 * that is affected by this busfree and we don't want to 1220 * go about selecting the target while we handle the event. 1221 */ 1222 ahc_outb(ahc, SCSISEQ, 1223 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1224 1225 /* 1226 * Disable busfree interrupts and clear the busfree 1227 * interrupt status. We do this here so that several 1228 * bus transactions occur prior to clearing the SCSIINT 1229 * latch. It can take a bit for the clearing to take effect. 1230 */ 1231 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1232 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1233 1234 /* 1235 * Look at what phase we were last in. 1236 * If its message out, chances are pretty good 1237 * that the busfree was in response to one of 1238 * our abort requests. 1239 */ 1240 lastphase = ahc_inb(ahc, LASTPHASE); 1241 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1242 saved_lun = ahc_inb(ahc, SAVED_LUN); 1243 target = SCSIID_TARGET(ahc, saved_scsiid); 1244 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1245 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1246 printerror = 1; 1247 1248 if (lastphase == P_MESGOUT) { 1249 struct ahc_devinfo devinfo; 1250 u_int tag; 1251 1252 ahc_fetch_devinfo(ahc, &devinfo); 1253 tag = SCB_LIST_NULL; 1254 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1255 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1256 if (ahc->msgout_buf[ahc->msgout_index - 1] 1257 == MSG_ABORT_TAG) 1258 tag = scb->hscb->tag; 1259 ahc_print_path(ahc, scb); 1260 printf("SCB %d - Abort%s Completed.\n", 1261 scb->hscb->tag, tag == SCB_LIST_NULL ? 1262 "" : " Tag"); 1263 ahc_abort_scbs(ahc, target, channel, 1264 saved_lun, tag, 1265 ROLE_INITIATOR, 1266 CAM_REQ_ABORTED); 1267 printerror = 0; 1268 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1269 MSG_BUS_DEV_RESET, TRUE)) { 1270 #ifdef __FreeBSD__ 1271 /* 1272 * Don't mark the user's request for this BDR 1273 * as completing with CAM_BDR_SENT. CAM3 1274 * specifies CAM_REQ_CMP. 1275 */ 1276 if (scb != NULL 1277 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1278 && ahc_match_scb(ahc, scb, target, channel, 1279 CAM_LUN_WILDCARD, 1280 SCB_LIST_NULL, 1281 ROLE_INITIATOR)) { 1282 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1283 } 1284 #endif 1285 ahc_compile_devinfo(&devinfo, 1286 initiator_role_id, 1287 target, 1288 CAM_LUN_WILDCARD, 1289 channel, 1290 ROLE_INITIATOR); 1291 ahc_handle_devreset(ahc, &devinfo, 1292 CAM_BDR_SENT, 1293 "Bus Device Reset", 1294 /*verbose_level*/0); 1295 printerror = 0; 1296 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1297 MSG_EXT_PPR, FALSE)) { 1298 struct ahc_initiator_tinfo *tinfo; 1299 struct ahc_tmode_tstate *tstate; 1300 1301 /* 1302 * PPR Rejected. Try non-ppr negotiation 1303 * and retry command. 1304 */ 1305 tinfo = ahc_fetch_transinfo(ahc, 1306 devinfo.channel, 1307 devinfo.our_scsiid, 1308 devinfo.target, 1309 &tstate); 1310 tinfo->curr.transport_version = 2; 1311 tinfo->goal.transport_version = 2; 1312 tinfo->goal.ppr_options = 0; 1313 ahc_qinfifo_requeue_tail(ahc, scb); 1314 printerror = 0; 1315 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1316 MSG_EXT_WDTR, FALSE) 1317 || ahc_sent_msg(ahc, AHCMSG_EXT, 1318 MSG_EXT_SDTR, FALSE)) { 1319 /* 1320 * Negotiation Rejected. Go-async and 1321 * retry command. 1322 */ 1323 ahc_set_width(ahc, &devinfo, 1324 MSG_EXT_WDTR_BUS_8_BIT, 1325 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1326 /*paused*/TRUE); 1327 ahc_set_syncrate(ahc, &devinfo, 1328 /*syncrate*/NULL, 1329 /*period*/0, /*offset*/0, 1330 /*ppr_options*/0, 1331 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1332 /*paused*/TRUE); 1333 ahc_qinfifo_requeue_tail(ahc, scb); 1334 printerror = 0; 1335 } 1336 } 1337 if (printerror != 0) { 1338 u_int i; 1339 1340 if (scb != NULL) { 1341 u_int tag; 1342 1343 if ((scb->hscb->control & TAG_ENB) != 0) 1344 tag = scb->hscb->tag; 1345 else 1346 tag = SCB_LIST_NULL; 1347 ahc_print_path(ahc, scb); 1348 ahc_abort_scbs(ahc, target, channel, 1349 SCB_GET_LUN(scb), tag, 1350 ROLE_INITIATOR, 1351 CAM_UNEXP_BUSFREE); 1352 } else { 1353 /* 1354 * We had not fully identified this connection, 1355 * so we cannot abort anything. 1356 */ 1357 printf("%s: ", ahc_name(ahc)); 1358 } 1359 for (i = 0; i < num_phases; i++) { 1360 if (lastphase == ahc_phase_table[i].phase) 1361 break; 1362 } 1363 /* 1364 * Renegotiate with this device at the 1365 * next opportunity just in case this busfree 1366 * is due to a negotiation mismatch with the 1367 * device. 1368 */ 1369 ahc_force_renegotiation(ahc); 1370 printf("Unexpected busfree %s\n" 1371 "SEQADDR == 0x%x\n", 1372 ahc_phase_table[i].phasemsg, 1373 ahc_inb(ahc, SEQADDR0) 1374 | (ahc_inb(ahc, SEQADDR1) << 8)); 1375 } 1376 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1377 ahc_restart(ahc); 1378 } else { 1379 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1380 ahc_name(ahc), status); 1381 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1382 } 1383 } 1384 1385 /* 1386 * Force renegotiation to occur the next time we initiate 1387 * a command to the current device. 1388 */ 1389 static void 1390 ahc_force_renegotiation(struct ahc_softc *ahc) 1391 { 1392 struct ahc_devinfo devinfo; 1393 struct ahc_initiator_tinfo *targ_info; 1394 struct ahc_tmode_tstate *tstate; 1395 1396 ahc_fetch_devinfo(ahc, &devinfo); 1397 targ_info = ahc_fetch_transinfo(ahc, 1398 devinfo.channel, 1399 devinfo.our_scsiid, 1400 devinfo.target, 1401 &tstate); 1402 ahc_update_neg_request(ahc, &devinfo, tstate, 1403 targ_info, AHC_NEG_IF_NON_ASYNC); 1404 } 1405 1406 #define AHC_MAX_STEPS 2000 1407 void 1408 ahc_clear_critical_section(struct ahc_softc *ahc) 1409 { 1410 int stepping; 1411 int steps; 1412 u_int simode0; 1413 u_int simode1; 1414 1415 if (ahc->num_critical_sections == 0) 1416 return; 1417 1418 stepping = FALSE; 1419 steps = 0; 1420 simode0 = 0; 1421 simode1 = 0; 1422 for (;;) { 1423 struct cs *cs; 1424 u_int seqaddr; 1425 u_int i; 1426 1427 seqaddr = ahc_inb(ahc, SEQADDR0) 1428 | (ahc_inb(ahc, SEQADDR1) << 8); 1429 1430 /* 1431 * Seqaddr represents the next instruction to execute, 1432 * so we are really executing the instruction just 1433 * before it. 1434 */ 1435 if (seqaddr != 0) 1436 seqaddr -= 1; 1437 cs = ahc->critical_sections; 1438 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1439 1440 if (cs->begin < seqaddr && cs->end >= seqaddr) 1441 break; 1442 } 1443 1444 if (i == ahc->num_critical_sections) 1445 break; 1446 1447 if (steps > AHC_MAX_STEPS) { 1448 printf("%s: Infinite loop in critical section\n", 1449 ahc_name(ahc)); 1450 ahc_dump_card_state(ahc); 1451 panic("critical section loop"); 1452 } 1453 1454 steps++; 1455 if (stepping == FALSE) { 1456 1457 /* 1458 * Disable all interrupt sources so that the 1459 * sequencer will not be stuck by a pausing 1460 * interrupt condition while we attempt to 1461 * leave a critical section. 1462 */ 1463 simode0 = ahc_inb(ahc, SIMODE0); 1464 ahc_outb(ahc, SIMODE0, 0); 1465 simode1 = ahc_inb(ahc, SIMODE1); 1466 if ((ahc->features & AHC_DT) != 0) 1467 /* 1468 * On DT class controllers, we 1469 * use the enhanced busfree logic. 1470 * Unfortunately we cannot re-enable 1471 * busfree detection within the 1472 * current connection, so we must 1473 * leave it on while single stepping. 1474 */ 1475 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1476 else 1477 ahc_outb(ahc, SIMODE1, 0); 1478 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1479 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1480 stepping = TRUE; 1481 } 1482 if ((ahc->features & AHC_DT) != 0) { 1483 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1484 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1485 } 1486 ahc_outb(ahc, HCNTRL, ahc->unpause); 1487 while (!ahc_is_paused(ahc)) 1488 ahc_delay(200); 1489 } 1490 if (stepping) { 1491 ahc_outb(ahc, SIMODE0, simode0); 1492 ahc_outb(ahc, SIMODE1, simode1); 1493 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1494 } 1495 } 1496 1497 /* 1498 * Clear any pending interrupt status. 1499 */ 1500 void 1501 ahc_clear_intstat(struct ahc_softc *ahc) 1502 { 1503 /* Clear any interrupt conditions this may have caused */ 1504 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1505 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1506 CLRREQINIT); 1507 ahc_flush_device_writes(ahc); 1508 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1509 ahc_flush_device_writes(ahc); 1510 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1511 ahc_flush_device_writes(ahc); 1512 } 1513 1514 /**************************** Debugging Routines ******************************/ 1515 #ifdef AHC_DEBUG 1516 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1517 #endif 1518 1519 void 1520 ahc_print_scb(struct scb *scb) 1521 { 1522 int i; 1523 1524 struct hardware_scb *hscb = scb->hscb; 1525 1526 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1527 (void *)scb, 1528 hscb->control, 1529 hscb->scsiid, 1530 hscb->lun, 1531 hscb->cdb_len); 1532 printf("Shared Data: "); 1533 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1534 printf("%#02x", hscb->shared_data.cdb[i]); 1535 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1536 ahc_le32toh(hscb->dataptr), 1537 ahc_le32toh(hscb->datacnt), 1538 ahc_le32toh(hscb->sgptr), 1539 hscb->tag); 1540 if (scb->sg_count > 0) { 1541 for (i = 0; i < scb->sg_count; i++) { 1542 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1543 i, 1544 (ahc_le32toh(scb->sg_list[i].len) >> 24 1545 & SG_HIGH_ADDR_BITS), 1546 ahc_le32toh(scb->sg_list[i].addr), 1547 ahc_le32toh(scb->sg_list[i].len)); 1548 } 1549 } 1550 } 1551 1552 /************************* Transfer Negotiation *******************************/ 1553 /* 1554 * Allocate per target mode instance (ID we respond to as a target) 1555 * transfer negotiation data structures. 1556 */ 1557 static struct ahc_tmode_tstate * 1558 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1559 { 1560 struct ahc_tmode_tstate *master_tstate; 1561 struct ahc_tmode_tstate *tstate; 1562 int i; 1563 1564 master_tstate = ahc->enabled_targets[ahc->our_id]; 1565 if (channel == 'B') { 1566 scsi_id += 8; 1567 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1568 } 1569 if (ahc->enabled_targets[scsi_id] != NULL 1570 && ahc->enabled_targets[scsi_id] != master_tstate) 1571 panic("%s: ahc_alloc_tstate - Target already allocated", 1572 ahc_name(ahc)); 1573 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1574 M_DEVBUF, M_NOWAIT); 1575 if (tstate == NULL) 1576 return (NULL); 1577 1578 /* 1579 * If we have allocated a master tstate, copy user settings from 1580 * the master tstate (taken from SRAM or the EEPROM) for this 1581 * channel, but reset our current and goal settings to async/narrow 1582 * until an initiator talks to us. 1583 */ 1584 if (master_tstate != NULL) { 1585 memcpy(tstate, master_tstate, sizeof(*tstate)); 1586 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1587 tstate->ultraenb = 0; 1588 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1589 memset(&tstate->transinfo[i].curr, 0, 1590 sizeof(tstate->transinfo[i].curr)); 1591 memset(&tstate->transinfo[i].goal, 0, 1592 sizeof(tstate->transinfo[i].goal)); 1593 } 1594 } else 1595 memset(tstate, 0, sizeof(*tstate)); 1596 ahc->enabled_targets[scsi_id] = tstate; 1597 return (tstate); 1598 } 1599 1600 #ifdef AHC_TARGET_MODE 1601 /* 1602 * Free per target mode instance (ID we respond to as a target) 1603 * transfer negotiation data structures. 1604 */ 1605 static void 1606 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1607 { 1608 struct ahc_tmode_tstate *tstate; 1609 1610 /* 1611 * Don't clean up our "master" tstate. 1612 * It has our default user settings. 1613 */ 1614 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1615 || (channel == 'A' && scsi_id == ahc->our_id)) 1616 && force == FALSE) 1617 return; 1618 1619 if (channel == 'B') 1620 scsi_id += 8; 1621 tstate = ahc->enabled_targets[scsi_id]; 1622 if (tstate != NULL) 1623 free(tstate, M_DEVBUF); 1624 ahc->enabled_targets[scsi_id] = NULL; 1625 } 1626 #endif 1627 1628 /* 1629 * Called when we have an active connection to a target on the bus, 1630 * this function finds the nearest syncrate to the input period limited 1631 * by the capabilities of the bus connectivity of and sync settings for 1632 * the target. 1633 */ 1634 struct ahc_syncrate * 1635 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1636 struct ahc_initiator_tinfo *tinfo, 1637 u_int *period, u_int *ppr_options, role_t role) 1638 { 1639 struct ahc_transinfo *transinfo; 1640 u_int maxsync; 1641 1642 if ((ahc->features & AHC_ULTRA2) != 0) { 1643 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1644 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1645 maxsync = AHC_SYNCRATE_DT; 1646 } else { 1647 maxsync = AHC_SYNCRATE_ULTRA; 1648 /* Can't do DT on an SE bus */ 1649 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1650 } 1651 } else if ((ahc->features & AHC_ULTRA) != 0) { 1652 maxsync = AHC_SYNCRATE_ULTRA; 1653 } else { 1654 maxsync = AHC_SYNCRATE_FAST; 1655 } 1656 /* 1657 * Never allow a value higher than our current goal 1658 * period otherwise we may allow a target initiated 1659 * negotiation to go above the limit as set by the 1660 * user. In the case of an initiator initiated 1661 * sync negotiation, we limit based on the user 1662 * setting. This allows the system to still accept 1663 * incoming negotiations even if target initiated 1664 * negotiation is not performed. 1665 */ 1666 if (role == ROLE_TARGET) 1667 transinfo = &tinfo->user; 1668 else 1669 transinfo = &tinfo->goal; 1670 *ppr_options &= transinfo->ppr_options; 1671 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1672 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1673 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1674 } 1675 if (transinfo->period == 0) { 1676 *period = 0; 1677 *ppr_options = 0; 1678 return (NULL); 1679 } 1680 *period = MAX(*period, transinfo->period); 1681 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1682 } 1683 1684 /* 1685 * Look up the valid period to SCSIRATE conversion in our table. 1686 * Return the period and offset that should be sent to the target 1687 * if this was the beginning of an SDTR. 1688 */ 1689 struct ahc_syncrate * 1690 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1691 u_int *ppr_options, u_int maxsync) 1692 { 1693 struct ahc_syncrate *syncrate; 1694 1695 if ((ahc->features & AHC_DT) == 0) 1696 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1697 1698 /* Skip all DT only entries if DT is not available */ 1699 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1700 && maxsync < AHC_SYNCRATE_ULTRA2) 1701 maxsync = AHC_SYNCRATE_ULTRA2; 1702 1703 for (syncrate = &ahc_syncrates[maxsync]; 1704 syncrate->rate != NULL; 1705 syncrate++) { 1706 1707 /* 1708 * The Ultra2 table doesn't go as low 1709 * as for the Fast/Ultra cards. 1710 */ 1711 if ((ahc->features & AHC_ULTRA2) != 0 1712 && (syncrate->sxfr_u2 == 0)) 1713 break; 1714 1715 if (*period <= syncrate->period) { 1716 /* 1717 * When responding to a target that requests 1718 * sync, the requested rate may fall between 1719 * two rates that we can output, but still be 1720 * a rate that we can receive. Because of this, 1721 * we want to respond to the target with 1722 * the same rate that it sent to us even 1723 * if the period we use to send data to it 1724 * is lower. Only lower the response period 1725 * if we must. 1726 */ 1727 if (syncrate == &ahc_syncrates[maxsync]) 1728 *period = syncrate->period; 1729 1730 /* 1731 * At some speeds, we only support 1732 * ST transfers. 1733 */ 1734 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1735 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1736 break; 1737 } 1738 } 1739 1740 if ((*period == 0) 1741 || (syncrate->rate == NULL) 1742 || ((ahc->features & AHC_ULTRA2) != 0 1743 && (syncrate->sxfr_u2 == 0))) { 1744 /* Use asynchronous transfers. */ 1745 *period = 0; 1746 syncrate = NULL; 1747 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1748 } 1749 return (syncrate); 1750 } 1751 1752 /* 1753 * Convert from an entry in our syncrate table to the SCSI equivalent 1754 * sync "period" factor. 1755 */ 1756 u_int 1757 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1758 { 1759 struct ahc_syncrate *syncrate; 1760 1761 if ((ahc->features & AHC_ULTRA2) != 0) 1762 scsirate &= SXFR_ULTRA2; 1763 else 1764 scsirate &= SXFR; 1765 1766 syncrate = &ahc_syncrates[maxsync]; 1767 while (syncrate->rate != NULL) { 1768 1769 if ((ahc->features & AHC_ULTRA2) != 0) { 1770 if (syncrate->sxfr_u2 == 0) 1771 break; 1772 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1773 return (syncrate->period); 1774 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1775 return (syncrate->period); 1776 } 1777 syncrate++; 1778 } 1779 return (0); /* async */ 1780 } 1781 1782 /* 1783 * Truncate the given synchronous offset to a value the 1784 * current adapter type and syncrate are capable of. 1785 */ 1786 void 1787 ahc_validate_offset(struct ahc_softc *ahc, 1788 struct ahc_initiator_tinfo *tinfo, 1789 struct ahc_syncrate *syncrate, 1790 u_int *offset, int wide, role_t role) 1791 { 1792 u_int maxoffset; 1793 1794 /* Limit offset to what we can do */ 1795 if (syncrate == NULL) { 1796 maxoffset = 0; 1797 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1798 maxoffset = MAX_OFFSET_ULTRA2; 1799 } else { 1800 if (wide) 1801 maxoffset = MAX_OFFSET_16BIT; 1802 else 1803 maxoffset = MAX_OFFSET_8BIT; 1804 } 1805 *offset = MIN(*offset, maxoffset); 1806 if (tinfo != NULL) { 1807 if (role == ROLE_TARGET) 1808 *offset = MIN(*offset, tinfo->user.offset); 1809 else 1810 *offset = MIN(*offset, tinfo->goal.offset); 1811 } 1812 } 1813 1814 /* 1815 * Truncate the given transfer width parameter to a value the 1816 * current adapter type is capable of. 1817 */ 1818 void 1819 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1820 u_int *bus_width, role_t role) 1821 { 1822 switch (*bus_width) { 1823 default: 1824 if (ahc->features & AHC_WIDE) { 1825 /* Respond Wide */ 1826 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1827 break; 1828 } 1829 /* FALLTHROUGH */ 1830 case MSG_EXT_WDTR_BUS_8_BIT: 1831 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1832 break; 1833 } 1834 if (tinfo != NULL) { 1835 if (role == ROLE_TARGET) 1836 *bus_width = MIN(tinfo->user.width, *bus_width); 1837 else 1838 *bus_width = MIN(tinfo->goal.width, *bus_width); 1839 } 1840 } 1841 1842 /* 1843 * Update the bitmask of targets for which the controller should 1844 * negotiate with at the next convenient opportunity. This currently 1845 * means the next time we send the initial identify messages for 1846 * a new transaction. 1847 */ 1848 int 1849 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1850 struct ahc_tmode_tstate *tstate, 1851 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1852 { 1853 u_int auto_negotiate_orig; 1854 1855 auto_negotiate_orig = tstate->auto_negotiate; 1856 if (neg_type == AHC_NEG_ALWAYS) { 1857 /* 1858 * Force our "current" settings to be 1859 * unknown so that unless a bus reset 1860 * occurs the need to renegotiate is 1861 * recorded persistently. 1862 */ 1863 if ((ahc->features & AHC_WIDE) != 0) 1864 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1865 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1866 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1867 } 1868 if (tinfo->curr.period != tinfo->goal.period 1869 || tinfo->curr.width != tinfo->goal.width 1870 || tinfo->curr.offset != tinfo->goal.offset 1871 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1872 || (neg_type == AHC_NEG_IF_NON_ASYNC 1873 && (tinfo->goal.offset != 0 1874 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1875 || tinfo->goal.ppr_options != 0))) 1876 tstate->auto_negotiate |= devinfo->target_mask; 1877 else 1878 tstate->auto_negotiate &= ~devinfo->target_mask; 1879 1880 return (auto_negotiate_orig != tstate->auto_negotiate); 1881 } 1882 1883 /* 1884 * Update the user/goal/curr tables of synchronous negotiation 1885 * parameters as well as, in the case of a current or active update, 1886 * any data structures on the host controller. In the case of an 1887 * active update, the specified target is currently talking to us on 1888 * the bus, so the transfer parameter update must take effect 1889 * immediately. 1890 */ 1891 void 1892 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1893 struct ahc_syncrate *syncrate, u_int period, 1894 u_int offset, u_int ppr_options, u_int type, int paused) 1895 { 1896 struct ahc_initiator_tinfo *tinfo; 1897 struct ahc_tmode_tstate *tstate; 1898 u_int old_period; 1899 u_int old_offset; 1900 u_int old_ppr; 1901 int active; 1902 int update_needed; 1903 1904 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1905 update_needed = 0; 1906 1907 if (syncrate == NULL) { 1908 period = 0; 1909 offset = 0; 1910 } 1911 1912 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1913 devinfo->target, &tstate); 1914 1915 if ((type & AHC_TRANS_USER) != 0) { 1916 tinfo->user.period = period; 1917 tinfo->user.offset = offset; 1918 tinfo->user.ppr_options = ppr_options; 1919 } 1920 1921 if ((type & AHC_TRANS_GOAL) != 0) { 1922 tinfo->goal.period = period; 1923 tinfo->goal.offset = offset; 1924 tinfo->goal.ppr_options = ppr_options; 1925 } 1926 1927 old_period = tinfo->curr.period; 1928 old_offset = tinfo->curr.offset; 1929 old_ppr = tinfo->curr.ppr_options; 1930 1931 if ((type & AHC_TRANS_CUR) != 0 1932 && (old_period != period 1933 || old_offset != offset 1934 || old_ppr != ppr_options)) { 1935 u_int scsirate; 1936 1937 update_needed++; 1938 scsirate = tinfo->scsirate; 1939 if ((ahc->features & AHC_ULTRA2) != 0) { 1940 1941 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1942 if (syncrate != NULL) { 1943 scsirate |= syncrate->sxfr_u2; 1944 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1945 scsirate |= ENABLE_CRC; 1946 else 1947 scsirate |= SINGLE_EDGE; 1948 } 1949 } else { 1950 1951 scsirate &= ~(SXFR|SOFS); 1952 /* 1953 * Ensure Ultra mode is set properly for 1954 * this target. 1955 */ 1956 tstate->ultraenb &= ~devinfo->target_mask; 1957 if (syncrate != NULL) { 1958 if (syncrate->sxfr & ULTRA_SXFR) { 1959 tstate->ultraenb |= 1960 devinfo->target_mask; 1961 } 1962 scsirate |= syncrate->sxfr & SXFR; 1963 scsirate |= offset & SOFS; 1964 } 1965 if (active) { 1966 u_int sxfrctl0; 1967 1968 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1969 sxfrctl0 &= ~FAST20; 1970 if (tstate->ultraenb & devinfo->target_mask) 1971 sxfrctl0 |= FAST20; 1972 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1973 } 1974 } 1975 if (active) { 1976 ahc_outb(ahc, SCSIRATE, scsirate); 1977 if ((ahc->features & AHC_ULTRA2) != 0) 1978 ahc_outb(ahc, SCSIOFFSET, offset); 1979 } 1980 1981 tinfo->scsirate = scsirate; 1982 tinfo->curr.period = period; 1983 tinfo->curr.offset = offset; 1984 tinfo->curr.ppr_options = ppr_options; 1985 1986 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1987 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1988 if (bootverbose) { 1989 if (offset != 0) { 1990 printf("%s: target %d synchronous at %sMHz%s, " 1991 "offset = 0x%x\n", ahc_name(ahc), 1992 devinfo->target, syncrate->rate, 1993 (ppr_options & MSG_EXT_PPR_DT_REQ) 1994 ? " DT" : "", offset); 1995 } else { 1996 printf("%s: target %d using " 1997 "asynchronous transfers\n", 1998 ahc_name(ahc), devinfo->target); 1999 } 2000 } 2001 } 2002 2003 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2004 tinfo, AHC_NEG_TO_GOAL); 2005 2006 if (update_needed) 2007 ahc_update_pending_scbs(ahc); 2008 } 2009 2010 /* 2011 * Update the user/goal/curr tables of wide negotiation 2012 * parameters as well as, in the case of a current or active update, 2013 * any data structures on the host controller. In the case of an 2014 * active update, the specified target is currently talking to us on 2015 * the bus, so the transfer parameter update must take effect 2016 * immediately. 2017 */ 2018 void 2019 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2020 u_int width, u_int type, int paused) 2021 { 2022 struct ahc_initiator_tinfo *tinfo; 2023 struct ahc_tmode_tstate *tstate; 2024 u_int oldwidth; 2025 int active; 2026 int update_needed; 2027 2028 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2029 update_needed = 0; 2030 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2031 devinfo->target, &tstate); 2032 2033 if ((type & AHC_TRANS_USER) != 0) 2034 tinfo->user.width = width; 2035 2036 if ((type & AHC_TRANS_GOAL) != 0) 2037 tinfo->goal.width = width; 2038 2039 oldwidth = tinfo->curr.width; 2040 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2041 u_int scsirate; 2042 2043 update_needed++; 2044 scsirate = tinfo->scsirate; 2045 scsirate &= ~WIDEXFER; 2046 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2047 scsirate |= WIDEXFER; 2048 2049 tinfo->scsirate = scsirate; 2050 2051 if (active) 2052 ahc_outb(ahc, SCSIRATE, scsirate); 2053 2054 tinfo->curr.width = width; 2055 2056 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2057 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2058 if (bootverbose) { 2059 printf("%s: target %d using %dbit transfers\n", 2060 ahc_name(ahc), devinfo->target, 2061 8 * (0x01 << width)); 2062 } 2063 } 2064 2065 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2066 tinfo, AHC_NEG_TO_GOAL); 2067 if (update_needed) 2068 ahc_update_pending_scbs(ahc); 2069 } 2070 2071 /* 2072 * Update the current state of tagged queuing for a given target. 2073 */ 2074 void 2075 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2076 ahc_queue_alg alg) 2077 { 2078 ahc_platform_set_tags(ahc, devinfo, alg); 2079 } 2080 2081 /* 2082 * When the transfer settings for a connection change, update any 2083 * in-transit SCBs to contain the new data so the hardware will 2084 * be set correctly during future (re)selections. 2085 */ 2086 static void 2087 ahc_update_pending_scbs(struct ahc_softc *ahc) 2088 { 2089 struct scb *pending_scb; 2090 int pending_scb_count; 2091 int i; 2092 int paused; 2093 u_int saved_scbptr; 2094 2095 /* 2096 * Traverse the pending SCB list and ensure that all of the 2097 * SCBs there have the proper settings. 2098 */ 2099 pending_scb_count = 0; 2100 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2101 struct ahc_devinfo devinfo; 2102 struct hardware_scb *pending_hscb; 2103 struct ahc_initiator_tinfo *tinfo; 2104 struct ahc_tmode_tstate *tstate; 2105 2106 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2107 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2108 devinfo.our_scsiid, 2109 devinfo.target, &tstate); 2110 pending_hscb = pending_scb->hscb; 2111 pending_hscb->control &= ~ULTRAENB; 2112 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2113 pending_hscb->control |= ULTRAENB; 2114 pending_hscb->scsirate = tinfo->scsirate; 2115 pending_hscb->scsioffset = tinfo->curr.offset; 2116 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2117 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2118 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2119 pending_hscb->control &= ~MK_MESSAGE; 2120 } 2121 ahc_sync_scb(ahc, pending_scb, 2122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2123 pending_scb_count++; 2124 } 2125 2126 if (pending_scb_count == 0) 2127 return; 2128 2129 if (ahc_is_paused(ahc)) { 2130 paused = 1; 2131 } else { 2132 paused = 0; 2133 ahc_pause(ahc); 2134 } 2135 2136 saved_scbptr = ahc_inb(ahc, SCBPTR); 2137 /* Ensure that the hscbs down on the card match the new information */ 2138 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2139 struct hardware_scb *pending_hscb; 2140 u_int control; 2141 u_int scb_tag; 2142 2143 ahc_outb(ahc, SCBPTR, i); 2144 scb_tag = ahc_inb(ahc, SCB_TAG); 2145 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2146 if (pending_scb == NULL) 2147 continue; 2148 2149 pending_hscb = pending_scb->hscb; 2150 control = ahc_inb(ahc, SCB_CONTROL); 2151 control &= ~(ULTRAENB|MK_MESSAGE); 2152 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2153 ahc_outb(ahc, SCB_CONTROL, control); 2154 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2155 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2156 } 2157 ahc_outb(ahc, SCBPTR, saved_scbptr); 2158 2159 if (paused == 0) 2160 ahc_unpause(ahc); 2161 } 2162 2163 /**************************** Pathing Information *****************************/ 2164 static void 2165 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2166 { 2167 u_int saved_scsiid; 2168 role_t role; 2169 int our_id; 2170 2171 if (ahc_inb(ahc, SSTAT0) & TARGET) 2172 role = ROLE_TARGET; 2173 else 2174 role = ROLE_INITIATOR; 2175 2176 if (role == ROLE_TARGET 2177 && (ahc->features & AHC_MULTI_TID) != 0 2178 && (ahc_inb(ahc, SEQ_FLAGS) 2179 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2180 /* We were selected, so pull our id from TARGIDIN */ 2181 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2182 } else if ((ahc->features & AHC_ULTRA2) != 0) 2183 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2184 else 2185 our_id = ahc_inb(ahc, SCSIID) & OID; 2186 2187 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2188 ahc_compile_devinfo(devinfo, 2189 our_id, 2190 SCSIID_TARGET(ahc, saved_scsiid), 2191 ahc_inb(ahc, SAVED_LUN), 2192 SCSIID_CHANNEL(ahc, saved_scsiid), 2193 role); 2194 } 2195 2196 struct ahc_phase_table_entry* 2197 ahc_lookup_phase_entry(int phase) 2198 { 2199 struct ahc_phase_table_entry *entry; 2200 struct ahc_phase_table_entry *last_entry; 2201 2202 /* 2203 * num_phases doesn't include the default entry which 2204 * will be returned if the phase doesn't match. 2205 */ 2206 last_entry = &ahc_phase_table[num_phases]; 2207 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2208 if (phase == entry->phase) 2209 break; 2210 } 2211 return (entry); 2212 } 2213 2214 void 2215 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2216 u_int lun, char channel, role_t role) 2217 { 2218 devinfo->our_scsiid = our_id; 2219 devinfo->target = target; 2220 devinfo->lun = lun; 2221 devinfo->target_offset = target; 2222 devinfo->channel = channel; 2223 devinfo->role = role; 2224 if (channel == 'B') 2225 devinfo->target_offset += 8; 2226 devinfo->target_mask = (0x01 << devinfo->target_offset); 2227 } 2228 2229 void 2230 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2231 { 2232 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2233 devinfo->target, devinfo->lun); 2234 } 2235 2236 static void 2237 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2238 struct scb *scb) 2239 { 2240 role_t role; 2241 int our_id; 2242 2243 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2244 role = ROLE_INITIATOR; 2245 if ((scb->flags & SCB_TARGET_SCB) != 0) 2246 role = ROLE_TARGET; 2247 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2248 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2249 } 2250 2251 2252 /************************ Message Phase Processing ****************************/ 2253 static void 2254 ahc_assert_atn(struct ahc_softc *ahc) 2255 { 2256 u_int scsisigo; 2257 2258 scsisigo = ATNO; 2259 if ((ahc->features & AHC_DT) == 0) 2260 scsisigo |= ahc_inb(ahc, SCSISIGI); 2261 ahc_outb(ahc, SCSISIGO, scsisigo); 2262 } 2263 2264 /* 2265 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2266 * or enters the initial message out phase, we are interrupted. Fill our 2267 * outgoing message buffer with the appropriate message and begin handing 2268 * the message phase(s) manually. 2269 */ 2270 static void 2271 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2272 struct scb *scb) 2273 { 2274 /* 2275 * To facilitate adding multiple messages together, 2276 * each routine should increment the index and len 2277 * variables instead of setting them explicitly. 2278 */ 2279 ahc->msgout_index = 0; 2280 ahc->msgout_len = 0; 2281 2282 if ((scb->flags & SCB_DEVICE_RESET) == 0 2283 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2284 u_int identify_msg; 2285 2286 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2287 if ((scb->hscb->control & DISCENB) != 0) 2288 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2289 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2290 ahc->msgout_len++; 2291 2292 if ((scb->hscb->control & TAG_ENB) != 0) { 2293 ahc->msgout_buf[ahc->msgout_index++] = 2294 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2295 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2296 ahc->msgout_len += 2; 2297 } 2298 } 2299 2300 if (scb->flags & SCB_DEVICE_RESET) { 2301 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2302 ahc->msgout_len++; 2303 ahc_print_path(ahc, scb); 2304 printf("Bus Device Reset Message Sent\n"); 2305 /* 2306 * Clear our selection hardware in advance of 2307 * the busfree. We may have an entry in the waiting 2308 * Q for this target, and we don't want to go about 2309 * selecting while we handle the busfree and blow it 2310 * away. 2311 */ 2312 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2313 } else if ((scb->flags & SCB_ABORT) != 0) { 2314 if ((scb->hscb->control & TAG_ENB) != 0) 2315 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2316 else 2317 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2318 ahc->msgout_len++; 2319 ahc_print_path(ahc, scb); 2320 printf("Abort%s Message Sent\n", 2321 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2322 /* 2323 * Clear our selection hardware in advance of 2324 * the busfree. We may have an entry in the waiting 2325 * Q for this target, and we don't want to go about 2326 * selecting while we handle the busfree and blow it 2327 * away. 2328 */ 2329 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2330 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2331 ahc_build_transfer_msg(ahc, devinfo); 2332 } else { 2333 printf("ahc_intr: AWAITING_MSG for an SCB that " 2334 "does not have a waiting message\n"); 2335 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2336 devinfo->target_mask); 2337 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2338 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2339 ahc_inb(ahc, MSG_OUT), scb->flags); 2340 } 2341 2342 /* 2343 * Clear the MK_MESSAGE flag from the SCB so we aren't 2344 * asked to send this message again. 2345 */ 2346 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2347 scb->hscb->control &= ~MK_MESSAGE; 2348 ahc->msgout_index = 0; 2349 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2350 } 2351 2352 /* 2353 * Build an appropriate transfer negotiation message for the 2354 * currently active target. 2355 */ 2356 static void 2357 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2358 { 2359 /* 2360 * We need to initiate transfer negotiations. 2361 * If our current and goal settings are identical, 2362 * we want to renegotiate due to a check condition. 2363 */ 2364 struct ahc_initiator_tinfo *tinfo; 2365 struct ahc_tmode_tstate *tstate; 2366 struct ahc_syncrate *rate; 2367 int dowide; 2368 int dosync; 2369 int doppr; 2370 u_int period; 2371 u_int ppr_options; 2372 u_int offset; 2373 2374 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2375 devinfo->target, &tstate); 2376 /* 2377 * Filter our period based on the current connection. 2378 * If we can't perform DT transfers on this segment (not in LVD 2379 * mode for instance), then our decision to issue a PPR message 2380 * may change. 2381 */ 2382 period = tinfo->goal.period; 2383 ppr_options = tinfo->goal.ppr_options; 2384 /* Target initiated PPR is not allowed in the SCSI spec */ 2385 if (devinfo->role == ROLE_TARGET) 2386 ppr_options = 0; 2387 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2388 &ppr_options, devinfo->role); 2389 dowide = tinfo->curr.width != tinfo->goal.width; 2390 dosync = tinfo->curr.period != period; 2391 /* 2392 * Only use PPR if we have options that need it, even if the device 2393 * claims to support it. There might be an expander in the way 2394 * that doesn't. 2395 */ 2396 doppr = ppr_options != 0; 2397 2398 if (!dowide && !dosync && !doppr) { 2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2400 dosync = tinfo->goal.offset != 0; 2401 } 2402 2403 if (!dowide && !dosync && !doppr) { 2404 /* 2405 * Force async with a WDTR message if we have a wide bus, 2406 * or just issue an SDTR with a 0 offset. 2407 */ 2408 if ((ahc->features & AHC_WIDE) != 0) 2409 dowide = 1; 2410 else 2411 dosync = 1; 2412 2413 if (bootverbose) { 2414 ahc_print_devinfo(ahc, devinfo); 2415 printf("Ensuring async\n"); 2416 } 2417 } 2418 2419 /* Target initiated PPR is not allowed in the SCSI spec */ 2420 if (devinfo->role == ROLE_TARGET) 2421 doppr = 0; 2422 2423 /* 2424 * Both the PPR message and SDTR message require the 2425 * goal syncrate to be limited to what the target device 2426 * is capable of handling (based on whether an LVD->SE 2427 * expander is on the bus), so combine these two cases. 2428 * Regardless, guarantee that if we are using WDTR and SDTR 2429 * messages that WDTR comes first. 2430 */ 2431 if (doppr || (dosync && !dowide)) { 2432 2433 offset = tinfo->goal.offset; 2434 ahc_validate_offset(ahc, tinfo, rate, &offset, 2435 doppr ? tinfo->goal.width 2436 : tinfo->curr.width, 2437 devinfo->role); 2438 if (doppr) { 2439 ahc_construct_ppr(ahc, devinfo, period, offset, 2440 tinfo->goal.width, ppr_options); 2441 } else { 2442 ahc_construct_sdtr(ahc, devinfo, period, offset); 2443 } 2444 } else { 2445 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2446 } 2447 } 2448 2449 /* 2450 * Build a synchronous negotiation message in our message 2451 * buffer based on the input parameters. 2452 */ 2453 static void 2454 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2455 u_int period, u_int offset) 2456 { 2457 if (offset == 0) 2458 period = AHC_ASYNC_XFER_PERIOD; 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2462 ahc->msgout_buf[ahc->msgout_index++] = period; 2463 ahc->msgout_buf[ahc->msgout_index++] = offset; 2464 ahc->msgout_len += 5; 2465 if (bootverbose) { 2466 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2467 ahc_name(ahc), devinfo->channel, devinfo->target, 2468 devinfo->lun, period, offset); 2469 } 2470 } 2471 2472 /* 2473 * Build a wide negotiation message in our message 2474 * buffer based on the input parameters. 2475 */ 2476 static void 2477 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2478 u_int bus_width) 2479 { 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2483 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2484 ahc->msgout_len += 4; 2485 if (bootverbose) { 2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2487 ahc_name(ahc), devinfo->channel, devinfo->target, 2488 devinfo->lun, bus_width); 2489 } 2490 } 2491 2492 /* 2493 * Build a parallel protocol request message in our message 2494 * buffer based on the input parameters. 2495 */ 2496 static void 2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2498 u_int period, u_int offset, u_int bus_width, 2499 u_int ppr_options) 2500 { 2501 if (offset == 0) 2502 period = AHC_ASYNC_XFER_PERIOD; 2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2506 ahc->msgout_buf[ahc->msgout_index++] = period; 2507 ahc->msgout_buf[ahc->msgout_index++] = 0; 2508 ahc->msgout_buf[ahc->msgout_index++] = offset; 2509 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2510 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2511 ahc->msgout_len += 8; 2512 if (bootverbose) { 2513 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2514 "offset %x, ppr_options %x\n", ahc_name(ahc), 2515 devinfo->channel, devinfo->target, devinfo->lun, 2516 bus_width, period, offset, ppr_options); 2517 } 2518 } 2519 2520 /* 2521 * Clear any active message state. 2522 */ 2523 static void 2524 ahc_clear_msg_state(struct ahc_softc *ahc) 2525 { 2526 ahc->msgout_len = 0; 2527 ahc->msgin_index = 0; 2528 ahc->msg_type = MSG_TYPE_NONE; 2529 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2530 /* 2531 * The target didn't care to respond to our 2532 * message request, so clear ATN. 2533 */ 2534 ahc_outb(ahc, CLRSINT1, CLRATNO); 2535 } 2536 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2537 ahc_outb(ahc, SEQ_FLAGS2, 2538 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2539 } 2540 2541 static void 2542 ahc_handle_proto_violation(struct ahc_softc *ahc) 2543 { 2544 struct ahc_devinfo devinfo; 2545 struct scb *scb; 2546 u_int scbid; 2547 u_int seq_flags; 2548 u_int curphase; 2549 u_int lastphase; 2550 int found; 2551 2552 ahc_fetch_devinfo(ahc, &devinfo); 2553 scbid = ahc_inb(ahc, SCB_TAG); 2554 scb = ahc_lookup_scb(ahc, scbid); 2555 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2556 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2557 lastphase = ahc_inb(ahc, LASTPHASE); 2558 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2559 2560 /* 2561 * The reconnecting target either did not send an 2562 * identify message, or did, but we didn't find an SCB 2563 * to match. 2564 */ 2565 ahc_print_devinfo(ahc, &devinfo); 2566 printf("Target did not send an IDENTIFY message. " 2567 "LASTPHASE = 0x%x.\n", lastphase); 2568 scb = NULL; 2569 } else if (scb == NULL) { 2570 /* 2571 * We don't seem to have an SCB active for this 2572 * transaction. Print an error and reset the bus. 2573 */ 2574 ahc_print_devinfo(ahc, &devinfo); 2575 printf("No SCB found during protocol violation\n"); 2576 goto proto_violation_reset; 2577 } else { 2578 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2579 if ((seq_flags & NO_CDB_SENT) != 0) { 2580 ahc_print_path(ahc, scb); 2581 printf("No or incomplete CDB sent to device.\n"); 2582 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2583 /* 2584 * The target never bothered to provide status to 2585 * us prior to completing the command. Since we don't 2586 * know the disposition of this command, we must attempt 2587 * to abort it. Assert ATN and prepare to send an abort 2588 * message. 2589 */ 2590 ahc_print_path(ahc, scb); 2591 printf("Completed command without status.\n"); 2592 } else { 2593 ahc_print_path(ahc, scb); 2594 printf("Unknown protocol violation.\n"); 2595 ahc_dump_card_state(ahc); 2596 } 2597 } 2598 if ((lastphase & ~P_DATAIN_DT) == 0 2599 || lastphase == P_COMMAND) { 2600 proto_violation_reset: 2601 /* 2602 * Target either went directly to data/command 2603 * phase or didn't respond to our ATN. 2604 * The only safe thing to do is to blow 2605 * it away with a bus reset. 2606 */ 2607 found = ahc_reset_channel(ahc, 'A', TRUE); 2608 printf("%s: Issued Channel %c Bus Reset. " 2609 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2610 } else { 2611 /* 2612 * Leave the selection hardware off in case 2613 * this abort attempt will affect yet to 2614 * be sent commands. 2615 */ 2616 ahc_outb(ahc, SCSISEQ, 2617 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2618 ahc_assert_atn(ahc); 2619 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2620 if (scb == NULL) { 2621 ahc_print_devinfo(ahc, &devinfo); 2622 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2623 ahc->msgout_len = 1; 2624 ahc->msgout_index = 0; 2625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2626 } else { 2627 ahc_print_path(ahc, scb); 2628 scb->flags |= SCB_ABORT; 2629 } 2630 printf("Protocol violation %s. Attempting to abort.\n", 2631 ahc_lookup_phase_entry(curphase)->phasemsg); 2632 } 2633 } 2634 2635 /* 2636 * Manual message loop handler. 2637 */ 2638 static void 2639 ahc_handle_message_phase(struct ahc_softc *ahc) 2640 { 2641 struct ahc_devinfo devinfo; 2642 u_int bus_phase; 2643 int end_session; 2644 2645 ahc_fetch_devinfo(ahc, &devinfo); 2646 end_session = FALSE; 2647 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2648 2649 reswitch: 2650 switch (ahc->msg_type) { 2651 case MSG_TYPE_INITIATOR_MSGOUT: 2652 { 2653 int lastbyte; 2654 int phasemis; 2655 int msgdone; 2656 2657 if (ahc->msgout_len == 0) 2658 panic("HOST_MSG_LOOP interrupt with no active message"); 2659 2660 #ifdef AHC_DEBUG 2661 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2662 ahc_print_devinfo(ahc, &devinfo); 2663 printf("INITIATOR_MSG_OUT"); 2664 } 2665 #endif 2666 phasemis = bus_phase != P_MESGOUT; 2667 if (phasemis) { 2668 #ifdef AHC_DEBUG 2669 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2670 printf(" PHASEMIS %s\n", 2671 ahc_lookup_phase_entry(bus_phase) 2672 ->phasemsg); 2673 } 2674 #endif 2675 if (bus_phase == P_MESGIN) { 2676 /* 2677 * Change gears and see if 2678 * this messages is of interest to 2679 * us or should be passed back to 2680 * the sequencer. 2681 */ 2682 ahc_outb(ahc, CLRSINT1, CLRATNO); 2683 ahc->send_msg_perror = FALSE; 2684 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2685 ahc->msgin_index = 0; 2686 goto reswitch; 2687 } 2688 end_session = TRUE; 2689 break; 2690 } 2691 2692 if (ahc->send_msg_perror) { 2693 ahc_outb(ahc, CLRSINT1, CLRATNO); 2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2695 #ifdef AHC_DEBUG 2696 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2697 printf(" byte 0x%x\n", ahc->send_msg_perror); 2698 #endif 2699 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2700 break; 2701 } 2702 2703 msgdone = ahc->msgout_index == ahc->msgout_len; 2704 if (msgdone) { 2705 /* 2706 * The target has requested a retry. 2707 * Re-assert ATN, reset our message index to 2708 * 0, and try again. 2709 */ 2710 ahc->msgout_index = 0; 2711 ahc_assert_atn(ahc); 2712 } 2713 2714 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2715 if (lastbyte) { 2716 /* Last byte is signified by dropping ATN */ 2717 ahc_outb(ahc, CLRSINT1, CLRATNO); 2718 } 2719 2720 /* 2721 * Clear our interrupt status and present 2722 * the next byte on the bus. 2723 */ 2724 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2725 #ifdef AHC_DEBUG 2726 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2727 printf(" byte 0x%x\n", 2728 ahc->msgout_buf[ahc->msgout_index]); 2729 #endif 2730 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2731 break; 2732 } 2733 case MSG_TYPE_INITIATOR_MSGIN: 2734 { 2735 int phasemis; 2736 int message_done; 2737 2738 #ifdef AHC_DEBUG 2739 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2740 ahc_print_devinfo(ahc, &devinfo); 2741 printf("INITIATOR_MSG_IN"); 2742 } 2743 #endif 2744 phasemis = bus_phase != P_MESGIN; 2745 if (phasemis) { 2746 #ifdef AHC_DEBUG 2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2748 printf(" PHASEMIS %s\n", 2749 ahc_lookup_phase_entry(bus_phase) 2750 ->phasemsg); 2751 } 2752 #endif 2753 ahc->msgin_index = 0; 2754 if (bus_phase == P_MESGOUT 2755 && (ahc->send_msg_perror == TRUE 2756 || (ahc->msgout_len != 0 2757 && ahc->msgout_index == 0))) { 2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2759 goto reswitch; 2760 } 2761 end_session = TRUE; 2762 break; 2763 } 2764 2765 /* Pull the byte in without acking it */ 2766 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2767 #ifdef AHC_DEBUG 2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2769 printf(" byte 0x%x\n", 2770 ahc->msgin_buf[ahc->msgin_index]); 2771 #endif 2772 2773 message_done = ahc_parse_msg(ahc, &devinfo); 2774 2775 if (message_done) { 2776 /* 2777 * Clear our incoming message buffer in case there 2778 * is another message following this one. 2779 */ 2780 ahc->msgin_index = 0; 2781 2782 /* 2783 * If this message illicited a response, 2784 * assert ATN so the target takes us to the 2785 * message out phase. 2786 */ 2787 if (ahc->msgout_len != 0) { 2788 #ifdef AHC_DEBUG 2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2790 ahc_print_devinfo(ahc, &devinfo); 2791 printf("Asserting ATN for response\n"); 2792 } 2793 #endif 2794 ahc_assert_atn(ahc); 2795 } 2796 } else 2797 ahc->msgin_index++; 2798 2799 if (message_done == MSGLOOP_TERMINATED) { 2800 end_session = TRUE; 2801 } else { 2802 /* Ack the byte */ 2803 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2804 ahc_inb(ahc, SCSIDATL); 2805 } 2806 break; 2807 } 2808 case MSG_TYPE_TARGET_MSGIN: 2809 { 2810 int msgdone; 2811 int msgout_request; 2812 2813 if (ahc->msgout_len == 0) 2814 panic("Target MSGIN with no active message"); 2815 2816 /* 2817 * If we interrupted a mesgout session, the initiator 2818 * will not know this until our first REQ. So, we 2819 * only honor mesgout requests after we've sent our 2820 * first byte. 2821 */ 2822 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2823 && ahc->msgout_index > 0) 2824 msgout_request = TRUE; 2825 else 2826 msgout_request = FALSE; 2827 2828 if (msgout_request) { 2829 2830 /* 2831 * Change gears and see if 2832 * this messages is of interest to 2833 * us or should be passed back to 2834 * the sequencer. 2835 */ 2836 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2837 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2838 ahc->msgin_index = 0; 2839 /* Dummy read to REQ for first byte */ 2840 ahc_inb(ahc, SCSIDATL); 2841 ahc_outb(ahc, SXFRCTL0, 2842 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2843 break; 2844 } 2845 2846 msgdone = ahc->msgout_index == ahc->msgout_len; 2847 if (msgdone) { 2848 ahc_outb(ahc, SXFRCTL0, 2849 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2850 end_session = TRUE; 2851 break; 2852 } 2853 2854 /* 2855 * Present the next byte on the bus. 2856 */ 2857 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2858 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2859 break; 2860 } 2861 case MSG_TYPE_TARGET_MSGOUT: 2862 { 2863 int lastbyte; 2864 int msgdone; 2865 2866 /* 2867 * The initiator signals that this is 2868 * the last byte by dropping ATN. 2869 */ 2870 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2871 2872 /* 2873 * Read the latched byte, but turn off SPIOEN first 2874 * so that we don't inadvertently cause a REQ for the 2875 * next byte. 2876 */ 2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2878 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2879 msgdone = ahc_parse_msg(ahc, &devinfo); 2880 if (msgdone == MSGLOOP_TERMINATED) { 2881 /* 2882 * The message is *really* done in that it caused 2883 * us to go to bus free. The sequencer has already 2884 * been reset at this point, so pull the ejection 2885 * handle. 2886 */ 2887 return; 2888 } 2889 2890 ahc->msgin_index++; 2891 2892 /* 2893 * XXX Read spec about initiator dropping ATN too soon 2894 * and use msgdone to detect it. 2895 */ 2896 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2897 ahc->msgin_index = 0; 2898 2899 /* 2900 * If this message illicited a response, transition 2901 * to the Message in phase and send it. 2902 */ 2903 if (ahc->msgout_len != 0) { 2904 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2905 ahc_outb(ahc, SXFRCTL0, 2906 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2907 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2908 ahc->msgin_index = 0; 2909 break; 2910 } 2911 } 2912 2913 if (lastbyte) 2914 end_session = TRUE; 2915 else { 2916 /* Ask for the next byte. */ 2917 ahc_outb(ahc, SXFRCTL0, 2918 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2919 } 2920 2921 break; 2922 } 2923 default: 2924 panic("Unknown REQINIT message type"); 2925 } 2926 2927 if (end_session) { 2928 ahc_clear_msg_state(ahc); 2929 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2930 } else 2931 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2932 } 2933 2934 /* 2935 * See if we sent a particular extended message to the target. 2936 * If "full" is true, return true only if the target saw the full 2937 * message. If "full" is false, return true if the target saw at 2938 * least the first byte of the message. 2939 */ 2940 static int 2941 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2942 { 2943 int found; 2944 u_int index; 2945 2946 found = FALSE; 2947 index = 0; 2948 2949 while (index < ahc->msgout_len) { 2950 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2951 u_int end_index; 2952 2953 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2954 if (ahc->msgout_buf[index+2] == msgval 2955 && type == AHCMSG_EXT) { 2956 2957 if (full) { 2958 if (ahc->msgout_index > end_index) 2959 found = TRUE; 2960 } else if (ahc->msgout_index > index) 2961 found = TRUE; 2962 } 2963 index = end_index; 2964 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2965 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2966 2967 /* Skip tag type and tag id or residue param*/ 2968 index += 2; 2969 } else { 2970 /* Single byte message */ 2971 if (type == AHCMSG_1B 2972 && ahc->msgout_buf[index] == msgval 2973 && ahc->msgout_index > index) 2974 found = TRUE; 2975 index++; 2976 } 2977 2978 if (found) 2979 break; 2980 } 2981 return (found); 2982 } 2983 2984 /* 2985 * Wait for a complete incoming message, parse it, and respond accordingly. 2986 */ 2987 static int 2988 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2989 { 2990 struct ahc_initiator_tinfo *tinfo; 2991 struct ahc_tmode_tstate *tstate; 2992 int reject; 2993 int done; 2994 int response; 2995 u_int targ_scsirate; 2996 2997 done = MSGLOOP_IN_PROG; 2998 response = FALSE; 2999 reject = FALSE; 3000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3001 devinfo->target, &tstate); 3002 targ_scsirate = tinfo->scsirate; 3003 3004 /* 3005 * Parse as much of the message as is available, 3006 * rejecting it if we don't support it. When 3007 * the entire message is available and has been 3008 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3009 * that we have parsed an entire message. 3010 * 3011 * In the case of extended messages, we accept the length 3012 * byte outright and perform more checking once we know the 3013 * extended message type. 3014 */ 3015 switch (ahc->msgin_buf[0]) { 3016 case MSG_DISCONNECT: 3017 case MSG_SAVEDATAPOINTER: 3018 case MSG_CMDCOMPLETE: 3019 case MSG_RESTOREPOINTERS: 3020 case MSG_IGN_WIDE_RESIDUE: 3021 /* 3022 * End our message loop as these are messages 3023 * the sequencer handles on its own. 3024 */ 3025 done = MSGLOOP_TERMINATED; 3026 break; 3027 case MSG_MESSAGE_REJECT: 3028 response = ahc_handle_msg_reject(ahc, devinfo); 3029 /* FALLTHROUGH */ 3030 case MSG_NOOP: 3031 done = MSGLOOP_MSGCOMPLETE; 3032 break; 3033 case MSG_EXTENDED: 3034 { 3035 /* Wait for enough of the message to begin validation */ 3036 if (ahc->msgin_index < 2) 3037 break; 3038 switch (ahc->msgin_buf[2]) { 3039 case MSG_EXT_SDTR: 3040 { 3041 struct ahc_syncrate *syncrate; 3042 u_int period; 3043 u_int ppr_options; 3044 u_int offset; 3045 u_int saved_offset; 3046 3047 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3048 reject = TRUE; 3049 break; 3050 } 3051 3052 /* 3053 * Wait until we have both args before validating 3054 * and acting on this message. 3055 * 3056 * Add one to MSG_EXT_SDTR_LEN to account for 3057 * the extended message preamble. 3058 */ 3059 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3060 break; 3061 3062 period = ahc->msgin_buf[3]; 3063 ppr_options = 0; 3064 saved_offset = offset = ahc->msgin_buf[4]; 3065 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3066 &ppr_options, 3067 devinfo->role); 3068 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3069 targ_scsirate & WIDEXFER, 3070 devinfo->role); 3071 if (bootverbose) { 3072 printf("(%s:%c:%d:%d): Received " 3073 "SDTR period %x, offset %x\n\t" 3074 "Filtered to period %x, offset %x\n", 3075 ahc_name(ahc), devinfo->channel, 3076 devinfo->target, devinfo->lun, 3077 ahc->msgin_buf[3], saved_offset, 3078 period, offset); 3079 } 3080 ahc_set_syncrate(ahc, devinfo, 3081 syncrate, period, 3082 offset, ppr_options, 3083 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3084 /*paused*/TRUE); 3085 3086 /* 3087 * See if we initiated Sync Negotiation 3088 * and didn't have to fall down to async 3089 * transfers. 3090 */ 3091 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3092 /* We started it */ 3093 if (saved_offset != offset) { 3094 /* Went too low - force async */ 3095 reject = TRUE; 3096 } 3097 } else { 3098 /* 3099 * Send our own SDTR in reply 3100 */ 3101 if (bootverbose 3102 && devinfo->role == ROLE_INITIATOR) { 3103 printf("(%s:%c:%d:%d): Target " 3104 "Initiated SDTR\n", 3105 ahc_name(ahc), devinfo->channel, 3106 devinfo->target, devinfo->lun); 3107 } 3108 ahc->msgout_index = 0; 3109 ahc->msgout_len = 0; 3110 ahc_construct_sdtr(ahc, devinfo, 3111 period, offset); 3112 ahc->msgout_index = 0; 3113 response = TRUE; 3114 } 3115 done = MSGLOOP_MSGCOMPLETE; 3116 break; 3117 } 3118 case MSG_EXT_WDTR: 3119 { 3120 u_int bus_width; 3121 u_int saved_width; 3122 u_int sending_reply; 3123 3124 sending_reply = FALSE; 3125 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3126 reject = TRUE; 3127 break; 3128 } 3129 3130 /* 3131 * Wait until we have our arg before validating 3132 * and acting on this message. 3133 * 3134 * Add one to MSG_EXT_WDTR_LEN to account for 3135 * the extended message preamble. 3136 */ 3137 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3138 break; 3139 3140 bus_width = ahc->msgin_buf[3]; 3141 saved_width = bus_width; 3142 ahc_validate_width(ahc, tinfo, &bus_width, 3143 devinfo->role); 3144 if (bootverbose) { 3145 printf("(%s:%c:%d:%d): Received WDTR " 3146 "%x filtered to %x\n", 3147 ahc_name(ahc), devinfo->channel, 3148 devinfo->target, devinfo->lun, 3149 saved_width, bus_width); 3150 } 3151 3152 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3153 /* 3154 * Don't send a WDTR back to the 3155 * target, since we asked first. 3156 * If the width went higher than our 3157 * request, reject it. 3158 */ 3159 if (saved_width > bus_width) { 3160 reject = TRUE; 3161 printf("(%s:%c:%d:%d): requested %dBit " 3162 "transfers. Rejecting...\n", 3163 ahc_name(ahc), devinfo->channel, 3164 devinfo->target, devinfo->lun, 3165 8 * (0x01 << bus_width)); 3166 bus_width = 0; 3167 } 3168 } else { 3169 /* 3170 * Send our own WDTR in reply 3171 */ 3172 if (bootverbose 3173 && devinfo->role == ROLE_INITIATOR) { 3174 printf("(%s:%c:%d:%d): Target " 3175 "Initiated WDTR\n", 3176 ahc_name(ahc), devinfo->channel, 3177 devinfo->target, devinfo->lun); 3178 } 3179 ahc->msgout_index = 0; 3180 ahc->msgout_len = 0; 3181 ahc_construct_wdtr(ahc, devinfo, bus_width); 3182 ahc->msgout_index = 0; 3183 response = TRUE; 3184 sending_reply = TRUE; 3185 } 3186 ahc_set_width(ahc, devinfo, bus_width, 3187 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3188 /*paused*/TRUE); 3189 /* After a wide message, we are async */ 3190 ahc_set_syncrate(ahc, devinfo, 3191 /*syncrate*/NULL, /*period*/0, 3192 /*offset*/0, /*ppr_options*/0, 3193 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3194 if (sending_reply == FALSE && reject == FALSE) { 3195 3196 if (tinfo->goal.offset) { 3197 ahc->msgout_index = 0; 3198 ahc->msgout_len = 0; 3199 ahc_build_transfer_msg(ahc, devinfo); 3200 ahc->msgout_index = 0; 3201 response = TRUE; 3202 } 3203 } 3204 done = MSGLOOP_MSGCOMPLETE; 3205 break; 3206 } 3207 case MSG_EXT_PPR: 3208 { 3209 struct ahc_syncrate *syncrate; 3210 u_int period; 3211 u_int offset; 3212 u_int bus_width; 3213 u_int ppr_options; 3214 u_int saved_width; 3215 u_int saved_offset; 3216 u_int saved_ppr_options; 3217 3218 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3219 reject = TRUE; 3220 break; 3221 } 3222 3223 /* 3224 * Wait until we have all args before validating 3225 * and acting on this message. 3226 * 3227 * Add one to MSG_EXT_PPR_LEN to account for 3228 * the extended message preamble. 3229 */ 3230 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3231 break; 3232 3233 period = ahc->msgin_buf[3]; 3234 offset = ahc->msgin_buf[5]; 3235 bus_width = ahc->msgin_buf[6]; 3236 saved_width = bus_width; 3237 ppr_options = ahc->msgin_buf[7]; 3238 /* 3239 * According to the spec, a DT only 3240 * period factor with no DT option 3241 * set implies async. 3242 */ 3243 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3244 && period == 9) 3245 offset = 0; 3246 saved_ppr_options = ppr_options; 3247 saved_offset = offset; 3248 3249 /* 3250 * Mask out any options we don't support 3251 * on any controller. Transfer options are 3252 * only available if we are negotiating wide. 3253 */ 3254 ppr_options &= MSG_EXT_PPR_DT_REQ; 3255 if (bus_width == 0) 3256 ppr_options = 0; 3257 3258 ahc_validate_width(ahc, tinfo, &bus_width, 3259 devinfo->role); 3260 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3261 &ppr_options, 3262 devinfo->role); 3263 ahc_validate_offset(ahc, tinfo, syncrate, 3264 &offset, bus_width, 3265 devinfo->role); 3266 3267 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3268 /* 3269 * If we are unable to do any of the 3270 * requested options (we went too low), 3271 * then we'll have to reject the message. 3272 */ 3273 if (saved_width > bus_width 3274 || saved_offset != offset 3275 || saved_ppr_options != ppr_options) { 3276 reject = TRUE; 3277 period = 0; 3278 offset = 0; 3279 bus_width = 0; 3280 ppr_options = 0; 3281 syncrate = NULL; 3282 } 3283 } else { 3284 if (devinfo->role != ROLE_TARGET) 3285 printf("(%s:%c:%d:%d): Target " 3286 "Initiated PPR\n", 3287 ahc_name(ahc), devinfo->channel, 3288 devinfo->target, devinfo->lun); 3289 else 3290 printf("(%s:%c:%d:%d): Initiator " 3291 "Initiated PPR\n", 3292 ahc_name(ahc), devinfo->channel, 3293 devinfo->target, devinfo->lun); 3294 ahc->msgout_index = 0; 3295 ahc->msgout_len = 0; 3296 ahc_construct_ppr(ahc, devinfo, period, offset, 3297 bus_width, ppr_options); 3298 ahc->msgout_index = 0; 3299 response = TRUE; 3300 } 3301 if (bootverbose) { 3302 printf("(%s:%c:%d:%d): Received PPR width %x, " 3303 "period %x, offset %x,options %x\n" 3304 "\tFiltered to width %x, period %x, " 3305 "offset %x, options %x\n", 3306 ahc_name(ahc), devinfo->channel, 3307 devinfo->target, devinfo->lun, 3308 saved_width, ahc->msgin_buf[3], 3309 saved_offset, saved_ppr_options, 3310 bus_width, period, offset, ppr_options); 3311 } 3312 ahc_set_width(ahc, devinfo, bus_width, 3313 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3314 /*paused*/TRUE); 3315 ahc_set_syncrate(ahc, devinfo, 3316 syncrate, period, 3317 offset, ppr_options, 3318 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3319 /*paused*/TRUE); 3320 done = MSGLOOP_MSGCOMPLETE; 3321 break; 3322 } 3323 default: 3324 /* Unknown extended message. Reject it. */ 3325 reject = TRUE; 3326 break; 3327 } 3328 break; 3329 } 3330 #ifdef AHC_TARGET_MODE 3331 case MSG_BUS_DEV_RESET: 3332 ahc_handle_devreset(ahc, devinfo, 3333 CAM_BDR_SENT, 3334 "Bus Device Reset Received", 3335 /*verbose_level*/0); 3336 ahc_restart(ahc); 3337 done = MSGLOOP_TERMINATED; 3338 break; 3339 case MSG_ABORT_TAG: 3340 case MSG_ABORT: 3341 case MSG_CLEAR_QUEUE: 3342 { 3343 int tag; 3344 3345 /* Target mode messages */ 3346 if (devinfo->role != ROLE_TARGET) { 3347 reject = TRUE; 3348 break; 3349 } 3350 tag = SCB_LIST_NULL; 3351 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3352 tag = ahc_inb(ahc, INITIATOR_TAG); 3353 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3354 devinfo->lun, tag, ROLE_TARGET, 3355 CAM_REQ_ABORTED); 3356 3357 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3358 if (tstate != NULL) { 3359 struct ahc_tmode_lstate* lstate; 3360 3361 lstate = tstate->enabled_luns[devinfo->lun]; 3362 if (lstate != NULL) { 3363 ahc_queue_lstate_event(ahc, lstate, 3364 devinfo->our_scsiid, 3365 ahc->msgin_buf[0], 3366 /*arg*/tag); 3367 ahc_send_lstate_events(ahc, lstate); 3368 } 3369 } 3370 ahc_restart(ahc); 3371 done = MSGLOOP_TERMINATED; 3372 break; 3373 } 3374 #endif 3375 case MSG_TERM_IO_PROC: 3376 default: 3377 reject = TRUE; 3378 break; 3379 } 3380 3381 if (reject) { 3382 /* 3383 * Setup to reject the message. 3384 */ 3385 ahc->msgout_index = 0; 3386 ahc->msgout_len = 1; 3387 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3388 done = MSGLOOP_MSGCOMPLETE; 3389 response = TRUE; 3390 } 3391 3392 if (done != MSGLOOP_IN_PROG && !response) 3393 /* Clear the outgoing message buffer */ 3394 ahc->msgout_len = 0; 3395 3396 return (done); 3397 } 3398 3399 /* 3400 * Process a message reject message. 3401 */ 3402 static int 3403 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3404 { 3405 /* 3406 * What we care about here is if we had an 3407 * outstanding SDTR or WDTR message for this 3408 * target. If we did, this is a signal that 3409 * the target is refusing negotiation. 3410 */ 3411 struct scb *scb; 3412 struct ahc_initiator_tinfo *tinfo; 3413 struct ahc_tmode_tstate *tstate; 3414 u_int scb_index; 3415 u_int last_msg; 3416 int response = 0; 3417 3418 scb_index = ahc_inb(ahc, SCB_TAG); 3419 scb = ahc_lookup_scb(ahc, scb_index); 3420 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3421 devinfo->our_scsiid, 3422 devinfo->target, &tstate); 3423 /* Might be necessary */ 3424 last_msg = ahc_inb(ahc, LAST_MSG); 3425 3426 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3427 /* 3428 * Target does not support the PPR message. 3429 * Attempt to negotiate SPI-2 style. 3430 */ 3431 if (bootverbose) { 3432 printf("(%s:%c:%d:%d): PPR Rejected. " 3433 "Trying WDTR/SDTR\n", 3434 ahc_name(ahc), devinfo->channel, 3435 devinfo->target, devinfo->lun); 3436 } 3437 tinfo->goal.ppr_options = 0; 3438 tinfo->curr.transport_version = 2; 3439 tinfo->goal.transport_version = 2; 3440 ahc->msgout_index = 0; 3441 ahc->msgout_len = 0; 3442 ahc_build_transfer_msg(ahc, devinfo); 3443 ahc->msgout_index = 0; 3444 response = 1; 3445 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3446 3447 /* note 8bit xfers */ 3448 if (bootverbose) 3449 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3450 "8bit transfers\n", ahc_name(ahc), 3451 devinfo->channel, devinfo->target, devinfo->lun); 3452 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3453 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3454 /*paused*/TRUE); 3455 /* 3456 * No need to clear the sync rate. If the target 3457 * did not accept the command, our syncrate is 3458 * unaffected. If the target started the negotiation, 3459 * but rejected our response, we already cleared the 3460 * sync rate before sending our WDTR. 3461 */ 3462 if (tinfo->goal.offset != tinfo->curr.offset) { 3463 3464 /* Start the sync negotiation */ 3465 ahc->msgout_index = 0; 3466 ahc->msgout_len = 0; 3467 ahc_build_transfer_msg(ahc, devinfo); 3468 ahc->msgout_index = 0; 3469 response = 1; 3470 } 3471 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3472 /* note asynch xfers and clear flag */ 3473 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3474 /*offset*/0, /*ppr_options*/0, 3475 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3476 /*paused*/TRUE); 3477 if (bootverbose) 3478 printf("(%s:%c:%d:%d): refuses synchronous negotiation." 3479 " Using asynchronous transfers\n", 3480 ahc_name(ahc), devinfo->channel, 3481 devinfo->target, devinfo->lun); 3482 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3483 int tag_type; 3484 int mask; 3485 3486 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3487 3488 if (tag_type == MSG_SIMPLE_TASK) { 3489 if (bootverbose) 3490 printf("(%s:%c:%d:%d): refuses tagged commands." 3491 " Performing non-tagged I/O\n", 3492 ahc_name(ahc), devinfo->channel, 3493 devinfo->target, devinfo->lun); 3494 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3495 mask = ~0x23; 3496 } else { 3497 if (bootverbose) 3498 printf("(%s:%c:%d:%d): refuses %s tagged " 3499 "commands. Performing simple queue " 3500 "tagged I/O only\n", 3501 ahc_name(ahc), devinfo->channel, 3502 devinfo->target, devinfo->lun, 3503 tag_type == MSG_ORDERED_TASK 3504 ? "ordered" : "head of queue"); 3505 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3506 mask = ~0x03; 3507 } 3508 3509 /* 3510 * Resend the identify for this CCB as the target 3511 * may believe that the selection is invalid otherwise. 3512 */ 3513 ahc_outb(ahc, SCB_CONTROL, 3514 ahc_inb(ahc, SCB_CONTROL) & mask); 3515 scb->hscb->control &= mask; 3516 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3517 /*type*/MSG_SIMPLE_TASK); 3518 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3519 ahc_assert_atn(ahc); 3520 3521 /* 3522 * This transaction is now at the head of 3523 * the untagged queue for this target. 3524 */ 3525 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3526 struct scb_tailq *untagged_q; 3527 3528 untagged_q = 3529 &(ahc->untagged_queues[devinfo->target_offset]); 3530 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3531 scb->flags |= SCB_UNTAGGEDQ; 3532 } 3533 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3534 scb->hscb->tag); 3535 3536 /* 3537 * Requeue all tagged commands for this target 3538 * currently in our possession so they can be 3539 * converted to untagged commands. 3540 */ 3541 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3542 SCB_GET_CHANNEL(ahc, scb), 3543 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3544 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3545 SEARCH_COMPLETE); 3546 } else { 3547 /* 3548 * Otherwise, we ignore it. 3549 */ 3550 if (bootverbose) 3551 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3552 ahc_name(ahc), devinfo->channel, devinfo->target, 3553 last_msg); 3554 } 3555 return (response); 3556 } 3557 3558 /* 3559 * Process an ingnore wide residue message. 3560 */ 3561 static void 3562 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3563 { 3564 u_int scb_index; 3565 struct scb *scb; 3566 3567 scb_index = ahc_inb(ahc, SCB_TAG); 3568 scb = ahc_lookup_scb(ahc, scb_index); 3569 /* 3570 * XXX Actually check data direction in the sequencer? 3571 * Perhaps add datadir to some spare bits in the hscb? 3572 */ 3573 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3574 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3575 /* 3576 * Ignore the message if we haven't 3577 * seen an appropriate data phase yet. 3578 */ 3579 } else { 3580 /* 3581 * If the residual occurred on the last 3582 * transfer and the transfer request was 3583 * expected to end on an odd count, do 3584 * nothing. Otherwise, subtract a byte 3585 * and update the residual count accordingly. 3586 */ 3587 uint32_t sgptr; 3588 3589 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3590 if ((sgptr & SG_LIST_NULL) != 0 3591 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3592 /* 3593 * If the residual occurred on the last 3594 * transfer and the transfer request was 3595 * expected to end on an odd count, do 3596 * nothing. 3597 */ 3598 } else { 3599 struct ahc_dma_seg *sg; 3600 uint32_t data_cnt; 3601 uint32_t data_addr; 3602 uint32_t sglen; 3603 3604 /* Pull in the rest of the sgptr */ 3605 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3606 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3607 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3608 sgptr &= SG_PTR_MASK; 3609 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3610 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3611 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3612 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3613 3614 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3615 | (ahc_inb(ahc, SHADDR + 2) << 16) 3616 | (ahc_inb(ahc, SHADDR + 1) << 8) 3617 | (ahc_inb(ahc, SHADDR)); 3618 3619 data_cnt += 1; 3620 data_addr -= 1; 3621 3622 sg = ahc_sg_bus_to_virt(scb, sgptr); 3623 /* 3624 * The residual sg ptr points to the next S/G 3625 * to load so we must go back one. 3626 */ 3627 sg--; 3628 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3629 if (sg != scb->sg_list 3630 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3631 3632 sg--; 3633 sglen = ahc_le32toh(sg->len); 3634 /* 3635 * Preserve High Address and SG_LIST bits 3636 * while setting the count to 1. 3637 */ 3638 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3639 data_addr = ahc_le32toh(sg->addr) 3640 + (sglen & AHC_SG_LEN_MASK) - 1; 3641 3642 /* 3643 * Increment sg so it points to the 3644 * "next" sg. 3645 */ 3646 sg++; 3647 sgptr = ahc_sg_virt_to_bus(scb, sg); 3648 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3649 sgptr >> 24); 3650 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3651 sgptr >> 16); 3652 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3653 sgptr >> 8); 3654 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3655 } 3656 3657 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3658 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3659 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3660 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3661 } 3662 } 3663 } 3664 3665 3666 /* 3667 * Reinitialize the data pointers for the active transfer 3668 * based on its current residual. 3669 */ 3670 static void 3671 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3672 { 3673 struct scb *scb; 3674 struct ahc_dma_seg *sg; 3675 u_int scb_index; 3676 uint32_t sgptr; 3677 uint32_t resid; 3678 uint32_t dataptr; 3679 3680 scb_index = ahc_inb(ahc, SCB_TAG); 3681 scb = ahc_lookup_scb(ahc, scb_index); 3682 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3683 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3684 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3685 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3686 3687 sgptr &= SG_PTR_MASK; 3688 sg = ahc_sg_bus_to_virt(scb, sgptr); 3689 3690 /* The residual sg_ptr always points to the next sg */ 3691 sg--; 3692 3693 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3694 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3695 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3696 3697 dataptr = ahc_le32toh(sg->addr) 3698 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3699 - resid; 3700 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3701 u_int dscommand1; 3702 3703 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3704 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3705 ahc_outb(ahc, HADDR, 3706 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3707 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3708 } 3709 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3710 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3711 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3712 ahc_outb(ahc, HADDR, dataptr); 3713 ahc_outb(ahc, HCNT + 2, resid >> 16); 3714 ahc_outb(ahc, HCNT + 1, resid >> 8); 3715 ahc_outb(ahc, HCNT, resid); 3716 if ((ahc->features & AHC_ULTRA2) == 0) { 3717 ahc_outb(ahc, STCNT + 2, resid >> 16); 3718 ahc_outb(ahc, STCNT + 1, resid >> 8); 3719 ahc_outb(ahc, STCNT, resid); 3720 } 3721 } 3722 3723 /* 3724 * Handle the effects of issuing a bus device reset message. 3725 */ 3726 static void 3727 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3728 cam_status status, char *message, int verbose_level) 3729 { 3730 #ifdef AHC_TARGET_MODE 3731 struct ahc_tmode_tstate* tstate; 3732 u_int lun; 3733 #endif 3734 int found; 3735 3736 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3737 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3738 status); 3739 3740 #ifdef AHC_TARGET_MODE 3741 /* 3742 * Send an immediate notify ccb to all target mord peripheral 3743 * drivers affected by this action. 3744 */ 3745 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3746 if (tstate != NULL) { 3747 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3748 struct ahc_tmode_lstate* lstate; 3749 3750 lstate = tstate->enabled_luns[lun]; 3751 if (lstate == NULL) 3752 continue; 3753 3754 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3755 MSG_BUS_DEV_RESET, /*arg*/0); 3756 ahc_send_lstate_events(ahc, lstate); 3757 } 3758 } 3759 #endif 3760 3761 /* 3762 * Go back to async/narrow transfers and renegotiate. 3763 */ 3764 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3765 AHC_TRANS_CUR, /*paused*/TRUE); 3766 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3767 /*period*/0, /*offset*/0, /*ppr_options*/0, 3768 AHC_TRANS_CUR, /*paused*/TRUE); 3769 3770 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3771 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3772 3773 if (message != NULL 3774 && (verbose_level <= bootverbose)) 3775 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3776 message, devinfo->channel, devinfo->target, found); 3777 } 3778 3779 #ifdef AHC_TARGET_MODE 3780 static void 3781 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3782 struct scb *scb) 3783 { 3784 3785 /* 3786 * To facilitate adding multiple messages together, 3787 * each routine should increment the index and len 3788 * variables instead of setting them explicitly. 3789 */ 3790 ahc->msgout_index = 0; 3791 ahc->msgout_len = 0; 3792 3793 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3794 ahc_build_transfer_msg(ahc, devinfo); 3795 else 3796 panic("ahc_intr: AWAITING target message with no message"); 3797 3798 ahc->msgout_index = 0; 3799 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3800 } 3801 #endif 3802 3803 int 3804 ahc_softc_init(struct ahc_softc *ahc) 3805 { 3806 3807 /* The IRQMS bit is only valid on VL and EISA chips */ 3808 if ((ahc->chip & AHC_PCI) == 0) 3809 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3810 else 3811 ahc->unpause = 0; 3812 ahc->pause = ahc->unpause | PAUSE; 3813 /* XXX The shared scb data stuff should be deprecated */ 3814 if (ahc->scb_data == NULL) { 3815 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3816 M_DEVBUF, M_NOWAIT); 3817 if (ahc->scb_data == NULL) 3818 return (ENOMEM); 3819 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3820 } 3821 3822 return (0); 3823 } 3824 3825 void 3826 ahc_softc_insert(struct ahc_softc *ahc) 3827 { 3828 struct ahc_softc *list_ahc; 3829 3830 #if AHC_PCI_CONFIG > 0 3831 /* 3832 * Second Function PCI devices need to inherit some 3833 * settings from function 0. 3834 */ 3835 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3836 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3837 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3838 ahc_dev_softc_t list_pci; 3839 ahc_dev_softc_t pci; 3840 3841 list_pci = list_ahc->dev_softc; 3842 pci = ahc->dev_softc; 3843 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3844 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3845 struct ahc_softc *master; 3846 struct ahc_softc *slave; 3847 3848 if (ahc_get_pci_function(list_pci) == 0) { 3849 master = list_ahc; 3850 slave = ahc; 3851 } else { 3852 master = ahc; 3853 slave = list_ahc; 3854 } 3855 slave->flags &= ~AHC_BIOS_ENABLED; 3856 slave->flags |= 3857 master->flags & AHC_BIOS_ENABLED; 3858 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3859 slave->flags |= 3860 master->flags & AHC_PRIMARY_CHANNEL; 3861 break; 3862 } 3863 } 3864 } 3865 #endif 3866 3867 /* 3868 * Insertion sort into our list of softcs. 3869 */ 3870 list_ahc = TAILQ_FIRST(&ahc_tailq); 3871 while (list_ahc != NULL 3872 && ahc_softc_comp(list_ahc, ahc) <= 0) 3873 list_ahc = TAILQ_NEXT(list_ahc, links); 3874 if (list_ahc != NULL) 3875 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3876 else 3877 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3878 ahc->init_level++; 3879 } 3880 3881 /* 3882 * Verify that the passed in softc pointer is for a 3883 * controller that is still configured. 3884 */ 3885 struct ahc_softc * 3886 ahc_find_softc(struct ahc_softc *ahc) 3887 { 3888 struct ahc_softc *list_ahc; 3889 3890 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3891 if (list_ahc == ahc) 3892 return (ahc); 3893 } 3894 return (NULL); 3895 } 3896 3897 void 3898 ahc_set_unit(struct ahc_softc *ahc, int unit) 3899 { 3900 ahc->unit = unit; 3901 } 3902 3903 void 3904 ahc_set_name(struct ahc_softc *ahc, char *name) 3905 { 3906 if (ahc->name != NULL) 3907 free(ahc->name, M_DEVBUF); 3908 ahc->name = name; 3909 } 3910 3911 void 3912 ahc_free(struct ahc_softc *ahc) 3913 { 3914 int i; 3915 3916 ahc_fini_scbdata(ahc); 3917 switch (ahc->init_level) { 3918 default: 3919 case 2: 3920 ahc_shutdown(ahc); 3921 /* TAILQ_REMOVE(&ahc_tailq, ahc, links); XXX */ 3922 /* FALLTHROUGH */ 3923 case 1: 3924 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3925 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3926 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3927 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3928 break; 3929 case 0: 3930 break; 3931 } 3932 3933 ahc_platform_free(ahc); 3934 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3935 struct ahc_tmode_tstate *tstate; 3936 3937 tstate = ahc->enabled_targets[i]; 3938 if (tstate != NULL) { 3939 #if AHC_TARGET_MODE 3940 int j; 3941 3942 for (j = 0; j < AHC_NUM_LUNS; j++) { 3943 struct ahc_tmode_lstate *lstate; 3944 3945 lstate = tstate->enabled_luns[j]; 3946 if (lstate != NULL) { 3947 /*xpt_free_path(lstate->path);*/ 3948 free(lstate, M_DEVBUF); 3949 } 3950 } 3951 #endif 3952 free(tstate, M_DEVBUF); 3953 } 3954 } 3955 #if AHC_TARGET_MODE 3956 if (ahc->black_hole != NULL) { 3957 /*xpt_free_path(ahc->black_hole->path);*/ 3958 free(ahc->black_hole, M_DEVBUF); 3959 } 3960 #endif 3961 #ifndef __NetBSD__ 3962 if (ahc->name != NULL) 3963 free(ahc->name, M_DEVBUF); 3964 #endif 3965 if (ahc->seep_config != NULL) 3966 free(ahc->seep_config, M_DEVBUF); 3967 #ifndef __FreeBSD__ 3968 free(ahc, M_DEVBUF); 3969 #endif 3970 return; 3971 } 3972 3973 void 3974 ahc_shutdown(void *arg) 3975 { 3976 struct ahc_softc *ahc; 3977 int i; 3978 3979 ahc = (struct ahc_softc *)arg; 3980 3981 /* This will reset most registers to 0, but not all */ 3982 ahc_reset(ahc); 3983 ahc_outb(ahc, SCSISEQ, 0); 3984 ahc_outb(ahc, SXFRCTL0, 0); 3985 ahc_outb(ahc, DSPCISTATUS, 0); 3986 3987 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3988 ahc_outb(ahc, i, 0); 3989 } 3990 3991 /* 3992 * Reset the controller and record some information about it 3993 * that is only available just after a reset. 3994 */ 3995 int 3996 ahc_reset(struct ahc_softc *ahc) 3997 { 3998 u_int sblkctl; 3999 u_int sxfrctl1_a, sxfrctl1_b; 4000 int wait; 4001 4002 /* 4003 * Preserve the value of the SXFRCTL1 register for all channels. 4004 * It contains settings that affect termination and we don't want 4005 * to disturb the integrity of the bus. 4006 */ 4007 ahc_pause(ahc); 4008 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4009 /* 4010 * The chip has not been initialized since 4011 * PCI/EISA/VLB bus reset. Don't trust 4012 * "left over BIOS data". 4013 */ 4014 ahc->flags |= AHC_NO_BIOS_INIT; 4015 } 4016 sxfrctl1_b = 0; 4017 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4018 u_int sblkctl; 4019 4020 /* 4021 * Save channel B's settings in case this chip 4022 * is setup for TWIN channel operation. 4023 */ 4024 sblkctl = ahc_inb(ahc, SBLKCTL); 4025 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4026 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4027 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4028 } 4029 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4030 4031 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4032 4033 /* 4034 * Ensure that the reset has finished. We delay 1000us 4035 * prior to reading the register to make sure the chip 4036 * has sufficiently completed its reset to handle register 4037 * accesses. 4038 */ 4039 wait = 1000; 4040 do { 4041 ahc_delay(1000); 4042 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4043 4044 if (wait == 0) { 4045 printf("%s: WARNING - Failed chip reset! " 4046 "Trying to initialize anyway.\n", ahc_name(ahc)); 4047 } 4048 ahc_outb(ahc, HCNTRL, ahc->pause); 4049 4050 /* Determine channel configuration */ 4051 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4052 /* No Twin Channel PCI cards */ 4053 if ((ahc->chip & AHC_PCI) != 0) 4054 sblkctl &= ~SELBUSB; 4055 switch (sblkctl) { 4056 case 0: 4057 /* Single Narrow Channel */ 4058 break; 4059 case 2: 4060 /* Wide Channel */ 4061 ahc->features |= AHC_WIDE; 4062 break; 4063 case 8: 4064 /* Twin Channel */ 4065 ahc->features |= AHC_TWIN; 4066 break; 4067 default: 4068 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4069 return(-1); 4070 } 4071 4072 /* 4073 * Reload sxfrctl1. 4074 * 4075 * We must always initialize STPWEN to 1 before we 4076 * restore the saved values. STPWEN is initialized 4077 * to a tri-state condition which can only be cleared 4078 * by turning it on. 4079 */ 4080 if ((ahc->features & AHC_TWIN) != 0) { 4081 u_int sblkctl; 4082 4083 sblkctl = ahc_inb(ahc, SBLKCTL); 4084 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4085 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4086 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4087 } 4088 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4089 4090 #ifdef AHC_DUMP_SEQ 4091 if (ahc->init_level == 0) 4092 ahc_dumpseq(ahc); 4093 #endif 4094 4095 return (0); 4096 } 4097 4098 /* 4099 * Determine the number of SCBs available on the controller 4100 */ 4101 int 4102 ahc_probe_scbs(struct ahc_softc *ahc) { 4103 int i; 4104 4105 for (i = 0; i < AHC_SCB_MAX; i++) { 4106 4107 ahc_outb(ahc, SCBPTR, i); 4108 ahc_outb(ahc, SCB_BASE, i); 4109 if (ahc_inb(ahc, SCB_BASE) != i) 4110 break; 4111 ahc_outb(ahc, SCBPTR, 0); 4112 if (ahc_inb(ahc, SCB_BASE) != 0) 4113 break; 4114 } 4115 return (i); 4116 } 4117 4118 #if 0 4119 static void 4120 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4121 { 4122 bus_addr_t *baddr; 4123 4124 baddr = (bus_addr_t *)arg; 4125 *baddr = segs->ds_addr; 4126 } 4127 #endif 4128 4129 static void 4130 ahc_build_free_scb_list(struct ahc_softc *ahc) 4131 { 4132 int scbsize; 4133 int i; 4134 4135 scbsize = 32; 4136 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4137 scbsize = 64; 4138 4139 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4140 int j; 4141 4142 ahc_outb(ahc, SCBPTR, i); 4143 4144 /* 4145 * Touch all SCB bytes to avoid parity errors 4146 * should one of our debugging routines read 4147 * an otherwise uninitiatlized byte. 4148 */ 4149 for (j = 0; j < scbsize; j++) 4150 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4151 4152 /* Clear the control byte. */ 4153 ahc_outb(ahc, SCB_CONTROL, 0); 4154 4155 /* Set the next pointer */ 4156 if ((ahc->flags & AHC_PAGESCBS) != 0) 4157 ahc_outb(ahc, SCB_NEXT, i+1); 4158 else 4159 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4160 4161 /* Make the tag number, SCSIID, and lun invalid */ 4162 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4163 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4164 ahc_outb(ahc, SCB_LUN, 0xFF); 4165 } 4166 4167 /* Make sure that the last SCB terminates the free list */ 4168 ahc_outb(ahc, SCBPTR, i-1); 4169 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4170 } 4171 4172 static int 4173 ahc_init_scbdata(struct ahc_softc *ahc) 4174 { 4175 struct scb_data *scb_data; 4176 4177 scb_data = ahc->scb_data; 4178 SLIST_INIT(&scb_data->free_scbs); 4179 SLIST_INIT(&scb_data->sg_maps); 4180 4181 /* Allocate SCB resources */ 4182 scb_data->scbarray = 4183 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4184 M_DEVBUF, M_NOWAIT); 4185 if (scb_data->scbarray == NULL) 4186 return (ENOMEM); 4187 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4188 4189 /* Determine the number of hardware SCBs and initialize them */ 4190 4191 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4192 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4193 /* SCB 0 heads the free list */ 4194 ahc_outb(ahc, FREE_SCBH, 0); 4195 } else { 4196 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4197 } 4198 4199 if (ahc->scb_data->maxhscbs == 0) { 4200 printf("%s: No SCB space found\n", ahc_name(ahc)); 4201 return (ENXIO); 4202 } 4203 4204 ahc_build_free_scb_list(ahc); 4205 4206 /* 4207 * Create our DMA tags. These tags define the kinds of device 4208 * accessible memory allocations and memory mappings we will 4209 * need to perform during normal operation. 4210 * 4211 * Unless we need to further restrict the allocation, we rely 4212 * on the restrictions of the parent dmat, hence the common 4213 * use of MAXADDR and MAXSIZE. 4214 */ 4215 4216 if (ahc_createdmamem(ahc->parent_dmat, 4217 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4218 &scb_data->hscb_dmamap, 4219 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4220 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4221 "hardware SCB structures") < 0) 4222 goto error_exit; 4223 4224 scb_data->init_level++; 4225 4226 if (ahc_createdmamem(ahc->parent_dmat, 4227 AHC_SCB_MAX * sizeof(struct scsi_sense_data), ahc->sc_dmaflags, 4228 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4229 &scb_data->sense_busaddr, &scb_data->sense_seg, 4230 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4231 goto error_exit; 4232 4233 scb_data->init_level++; 4234 4235 /* Perform initial CCB allocation */ 4236 memset(scb_data->hscbs, 0, 4237 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4238 ahc_alloc_scbs(ahc); 4239 scb_data->init_level++; 4240 4241 if (scb_data->numscbs == 0) { 4242 printf("%s: ahc_init_scbdata - " 4243 "Unable to allocate initial scbs\n", 4244 ahc_name(ahc)); 4245 goto error_exit; 4246 } 4247 4248 /* 4249 * Tell the sequencer which SCB will be the next one it receives. 4250 */ 4251 ahc->next_queued_scb = ahc_get_scb(ahc); 4252 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4253 4254 /* 4255 * Note that we were successfull 4256 */ 4257 return (0); 4258 4259 error_exit: 4260 4261 return (ENOMEM); 4262 } 4263 4264 static void 4265 ahc_fini_scbdata(struct ahc_softc *ahc) 4266 { 4267 struct scb_data *scb_data; 4268 4269 scb_data = ahc->scb_data; 4270 if (scb_data == NULL) 4271 return; 4272 4273 switch (scb_data->init_level) { 4274 default: 4275 case 5: 4276 { 4277 struct sg_map_node *sg_map; 4278 4279 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4280 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4281 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4282 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4283 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4284 free(sg_map, M_DEVBUF); 4285 } 4286 } 4287 /*FALLTHROUGH*/ 4288 case 4: 4289 ahc_freedmamem(ahc->parent_dmat, 4290 AHC_SCB_MAX * sizeof(struct scsi_sense_data), 4291 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4292 &scb_data->sense_seg, scb_data->sense_nseg); 4293 /*FALLTHROUGH*/ 4294 case 3: 4295 ahc_freedmamem(ahc->parent_dmat, 4296 AHC_SCB_MAX * sizeof(struct hardware_scb), 4297 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4298 &scb_data->hscb_seg, scb_data->hscb_nseg); 4299 /*FALLTHROUGH*/ 4300 case 2: 4301 case 1: 4302 case 0: 4303 break; 4304 } 4305 if (scb_data->scbarray != NULL) 4306 free(scb_data->scbarray, M_DEVBUF); 4307 } 4308 4309 void 4310 ahc_alloc_scbs(struct ahc_softc *ahc) 4311 { 4312 struct scb_data *scb_data; 4313 struct scb *next_scb; 4314 struct sg_map_node *sg_map; 4315 bus_addr_t physaddr; 4316 struct ahc_dma_seg *segs; 4317 int newcount; 4318 int i; 4319 4320 scb_data = ahc->scb_data; 4321 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4322 /* Can't allocate any more */ 4323 return; 4324 4325 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4326 4327 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4328 4329 if (sg_map == NULL) 4330 return; 4331 4332 /* Allocate S/G space for the next batch of SCBS */ 4333 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4334 &sg_map->sg_dmamap, 4335 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4336 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4337 "SG space") < 0) { 4338 free(sg_map, M_DEVBUF); 4339 return; 4340 } 4341 4342 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4343 4344 segs = sg_map->sg_vaddr; 4345 physaddr = sg_map->sg_physaddr; 4346 4347 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4348 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4349 for (i = 0; i < newcount; i++) { 4350 struct scb_platform_data *pdata; 4351 int error; 4352 4353 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4354 M_DEVBUF, M_NOWAIT); 4355 if (pdata == NULL) 4356 break; 4357 next_scb->platform_data = pdata; 4358 next_scb->sg_map = sg_map; 4359 next_scb->sg_list = segs; 4360 /* 4361 * The sequencer always starts with the second entry. 4362 * The first entry is embedded in the scb. 4363 */ 4364 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4365 next_scb->ahc_softc = ahc; 4366 next_scb->flags = SCB_FREE; 4367 4368 error = bus_dmamap_create(ahc->parent_dmat, 4369 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0, 4370 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4371 &next_scb->dmamap); 4372 if (error != 0) 4373 break; 4374 4375 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4376 next_scb->hscb->tag = ahc->scb_data->numscbs; 4377 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4378 next_scb, links.sle); 4379 segs += AHC_NSEG; 4380 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4381 next_scb++; 4382 ahc->scb_data->numscbs++; 4383 } 4384 } 4385 4386 void 4387 ahc_controller_info(struct ahc_softc *ahc, char *buf, size_t l) 4388 { 4389 int len; 4390 char *ep; 4391 4392 ep = buf + l; 4393 4394 len = snprintf(buf, ep - buf, "%s: ", 4395 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4396 buf += len; 4397 if ((ahc->features & AHC_TWIN) != 0) 4398 len = snprintf(buf, ep - buf, "Twin Channel, A SCSI Id=%d, " 4399 "B SCSI Id=%d, primary %c, ", 4400 ahc->our_id, ahc->our_id_b, 4401 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4402 else { 4403 const char *speed; 4404 const char *type; 4405 4406 speed = ""; 4407 if ((ahc->features & AHC_ULTRA) != 0) { 4408 speed = "Ultra "; 4409 } else if ((ahc->features & AHC_DT) != 0) { 4410 speed = "Ultra160 "; 4411 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4412 speed = "Ultra2 "; 4413 } 4414 if ((ahc->features & AHC_WIDE) != 0) { 4415 type = "Wide"; 4416 } else { 4417 type = "Single"; 4418 } 4419 len = snprintf(buf, ep - buf, "%s%s Channel %c, SCSI Id=%d, ", 4420 speed, type, ahc->channel, ahc->our_id); 4421 } 4422 buf += len; 4423 4424 if ((ahc->flags & AHC_PAGESCBS) != 0) 4425 snprintf(buf, ep - buf, "%d/%d SCBs", 4426 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4427 else 4428 snprintf(buf, ep - buf, "%d SCBs", ahc->scb_data->maxhscbs); 4429 } 4430 4431 /* 4432 * Start the board, ready for normal operation 4433 */ 4434 int 4435 ahc_init(struct ahc_softc *ahc) 4436 { 4437 int max_targ; 4438 int i; 4439 int term; 4440 u_int scsi_conf; 4441 u_int scsiseq_template; 4442 u_int ultraenb; 4443 u_int discenable; 4444 u_int tagenable; 4445 size_t driver_data_size; 4446 uint32_t physaddr; 4447 4448 #ifdef AHC_DEBUG 4449 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4450 ahc->flags |= AHC_SEQUENCER_DEBUG; 4451 #endif 4452 4453 #ifdef AHC_PRINT_SRAM 4454 printf("Scratch Ram:"); 4455 for (i = 0x20; i < 0x5f; i++) { 4456 if (((i % 8) == 0) && (i != 0)) { 4457 printf ("\n "); 4458 } 4459 printf (" 0x%x", ahc_inb(ahc, i)); 4460 } 4461 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4462 for (i = 0x70; i < 0x7f; i++) { 4463 if (((i % 8) == 0) && (i != 0)) { 4464 printf ("\n "); 4465 } 4466 printf (" 0x%x", ahc_inb(ahc, i)); 4467 } 4468 } 4469 printf ("\n"); 4470 /* 4471 * Reading uninitialized scratch ram may 4472 * generate parity errors. 4473 */ 4474 ahc_outb(ahc, CLRINT, CLRPARERR); 4475 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4476 #endif 4477 max_targ = 15; 4478 4479 /* 4480 * Assume we have a board at this stage and it has been reset. 4481 */ 4482 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4483 ahc->our_id = ahc->our_id_b = 7; 4484 4485 /* 4486 * Default to allowing initiator operations. 4487 */ 4488 ahc->flags |= AHC_INITIATORROLE; 4489 4490 /* 4491 * Only allow target mode features if this unit has them enabled. 4492 */ 4493 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4494 ahc->features &= ~AHC_TARGETMODE; 4495 4496 /* 4497 * DMA tag for our command fifos and other data in system memory 4498 * the card's sequencer must be able to access. For initiator 4499 * roles, we need to allocate space for the qinfifo and qoutfifo. 4500 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4501 * When providing for the target mode role, we must additionally 4502 * provide space for the incoming target command fifo and an extra 4503 * byte to deal with a DMA bug in some chip versions. 4504 */ 4505 driver_data_size = 2 * 256 * sizeof(uint8_t); 4506 if ((ahc->features & AHC_TARGETMODE) != 0) 4507 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4508 + /*DMA WideOdd Bug Buffer*/1; 4509 4510 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4511 ahc->sc_dmaflags, 4512 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4513 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4514 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4515 return (ENOMEM); 4516 4517 ahc->init_level++; 4518 4519 if ((ahc->features & AHC_TARGETMODE) != 0) { 4520 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4521 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4522 ahc->dma_bug_buf = ahc->shared_data_busaddr 4523 + driver_data_size - 1; 4524 /* All target command blocks start out invalid. */ 4525 for (i = 0; i < AHC_TMODE_CMDS; i++) 4526 ahc->targetcmds[i].cmd_valid = 0; 4527 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4528 ahc->tqinfifonext = 1; 4529 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4530 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4531 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4532 } 4533 ahc->qinfifo = &ahc->qoutfifo[256]; 4534 4535 ahc->init_level++; 4536 4537 /* Allocate SCB data now that buffer_dmat is initialized */ 4538 if (ahc->scb_data->maxhscbs == 0) 4539 if (ahc_init_scbdata(ahc) != 0) 4540 return (ENOMEM); 4541 4542 if (bootverbose) 4543 printf("%s: found %d SCBs\n", ahc_name(ahc), 4544 ahc->scb_data->maxhscbs); 4545 4546 /* 4547 * Allocate a tstate to house information for our 4548 * initiator presence on the bus as well as the user 4549 * data for any target mode initiator. 4550 */ 4551 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4552 printf("%s: unable to allocate ahc_tmode_tstate. " 4553 "Failing attach\n", ahc_name(ahc)); 4554 return (ENOMEM); 4555 } 4556 4557 if ((ahc->features & AHC_TWIN) != 0) { 4558 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4559 printf("%s: unable to allocate ahc_tmode_tstate. " 4560 "Failing attach\n", ahc_name(ahc)); 4561 return (ENOMEM); 4562 } 4563 } 4564 4565 ahc_outb(ahc, SEQ_FLAGS, 0); 4566 ahc_outb(ahc, SEQ_FLAGS2, 0); 4567 4568 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4569 ahc->flags |= AHC_PAGESCBS; 4570 } else { 4571 ahc->flags &= ~AHC_PAGESCBS; 4572 } 4573 4574 #ifdef AHC_DEBUG 4575 if (ahc_debug & AHC_SHOW_MISC) { 4576 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 4577 "ahc_dma %lu bytes\n", 4578 ahc_name(ahc), 4579 (u_long)sizeof(struct hardware_scb), 4580 (u_long)sizeof(struct scb), 4581 (u_long)sizeof(struct ahc_dma_seg)); 4582 } 4583 #endif /* AHC_DEBUG */ 4584 4585 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4586 if (ahc->features & AHC_TWIN) { 4587 4588 /* 4589 * The device is gated to channel B after a chip reset, 4590 * so set those values first 4591 */ 4592 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4593 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4594 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4595 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4596 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4597 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4598 if ((ahc->features & AHC_ULTRA2) != 0) 4599 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4600 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4601 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4602 4603 if ((scsi_conf & RESET_SCSI) != 0 4604 && (ahc->flags & AHC_INITIATORROLE) != 0) 4605 ahc->flags |= AHC_RESET_BUS_B; 4606 4607 /* Select Channel A */ 4608 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4609 } 4610 4611 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4612 if ((ahc->features & AHC_ULTRA2) != 0) 4613 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4614 else 4615 ahc_outb(ahc, SCSIID, ahc->our_id); 4616 scsi_conf = ahc_inb(ahc, SCSICONF); 4617 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4618 |term|ahc->seltime 4619 |ENSTIMER|ACTNEGEN); 4620 if ((ahc->features & AHC_ULTRA2) != 0) 4621 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4622 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4623 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4624 4625 if ((scsi_conf & RESET_SCSI) != 0 4626 && (ahc->flags & AHC_INITIATORROLE) != 0) 4627 ahc->flags |= AHC_RESET_BUS_A; 4628 4629 /* 4630 * Look at the information that board initialization or 4631 * the board bios has left us. 4632 */ 4633 ultraenb = 0; 4634 tagenable = ALL_TARGETS_MASK; 4635 4636 /* Grab the disconnection disable table and invert it for our needs */ 4637 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4638 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4639 "device parameters\n", ahc_name(ahc)); 4640 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4641 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4642 discenable = ALL_TARGETS_MASK; 4643 if ((ahc->features & AHC_ULTRA) != 0) 4644 ultraenb = ALL_TARGETS_MASK; 4645 } else { 4646 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4647 | ahc_inb(ahc, DISC_DSB)); 4648 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4649 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4650 | ahc_inb(ahc, ULTRA_ENB); 4651 } 4652 4653 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4654 max_targ = 7; 4655 4656 for (i = 0; i <= max_targ; i++) { 4657 struct ahc_initiator_tinfo *tinfo; 4658 struct ahc_tmode_tstate *tstate; 4659 u_int our_id; 4660 u_int target_id; 4661 char channel; 4662 4663 channel = 'A'; 4664 our_id = ahc->our_id; 4665 target_id = i; 4666 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4667 channel = 'B'; 4668 our_id = ahc->our_id_b; 4669 target_id = i % 8; 4670 } 4671 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4672 target_id, &tstate); 4673 /* Default to async narrow across the board */ 4674 memset(tinfo, 0, sizeof(*tinfo)); 4675 if (ahc->flags & AHC_USEDEFAULTS) { 4676 if ((ahc->features & AHC_WIDE) != 0) 4677 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4678 4679 /* 4680 * These will be truncated when we determine the 4681 * connection type we have with the target. 4682 */ 4683 tinfo->user.period = ahc_syncrates->period; 4684 tinfo->user.offset = ~0; 4685 } else { 4686 u_int scsirate; 4687 uint16_t mask; 4688 4689 /* Take the settings leftover in scratch RAM. */ 4690 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4691 mask = (0x01 << i); 4692 if ((ahc->features & AHC_ULTRA2) != 0) { 4693 u_int offset; 4694 u_int maxsync; 4695 4696 if ((scsirate & SOFS) == 0x0F) { 4697 /* 4698 * Haven't negotiated yet, 4699 * so the format is different. 4700 */ 4701 scsirate = (scsirate & SXFR) >> 4 4702 | (ultraenb & mask) 4703 ? 0x08 : 0x0 4704 | (scsirate & WIDEXFER); 4705 offset = MAX_OFFSET_ULTRA2; 4706 } else 4707 offset = ahc_inb(ahc, TARG_OFFSET + i); 4708 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4709 /* Set to the lowest sync rate, 5MHz */ 4710 scsirate |= 0x1c; 4711 maxsync = AHC_SYNCRATE_ULTRA2; 4712 if ((ahc->features & AHC_DT) != 0) 4713 maxsync = AHC_SYNCRATE_DT; 4714 tinfo->user.period = 4715 ahc_find_period(ahc, scsirate, maxsync); 4716 if (offset == 0) 4717 tinfo->user.period = 0; 4718 else 4719 tinfo->user.offset = ~0; 4720 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4721 && (ahc->features & AHC_DT) != 0) 4722 tinfo->user.ppr_options = 4723 MSG_EXT_PPR_DT_REQ; 4724 } else if ((scsirate & SOFS) != 0) { 4725 if ((scsirate & SXFR) == 0x40 4726 && (ultraenb & mask) != 0) { 4727 /* Treat 10MHz as a non-ultra speed */ 4728 scsirate &= ~SXFR; 4729 ultraenb &= ~mask; 4730 } 4731 tinfo->user.period = 4732 ahc_find_period(ahc, scsirate, 4733 (ultraenb & mask) 4734 ? AHC_SYNCRATE_ULTRA 4735 : AHC_SYNCRATE_FAST); 4736 if (tinfo->user.period != 0) 4737 tinfo->user.offset = ~0; 4738 } 4739 if (tinfo->user.period == 0) 4740 tinfo->user.offset = 0; 4741 if ((scsirate & WIDEXFER) != 0 4742 && (ahc->features & AHC_WIDE) != 0) 4743 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4744 tinfo->user.protocol_version = 4; 4745 if ((ahc->features & AHC_DT) != 0) 4746 tinfo->user.transport_version = 3; 4747 else 4748 tinfo->user.transport_version = 2; 4749 tinfo->goal.protocol_version = 2; 4750 tinfo->goal.transport_version = 2; 4751 tinfo->curr.protocol_version = 2; 4752 tinfo->curr.transport_version = 2; 4753 } 4754 tstate->ultraenb = 0; 4755 tstate->discenable = discenable; 4756 } 4757 ahc->user_discenable = discenable; 4758 ahc->user_tagenable = tagenable; 4759 4760 /* There are no untagged SCBs active yet. */ 4761 for (i = 0; i < 16; i++) { 4762 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4763 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4764 int lun; 4765 4766 /* 4767 * The SCB based BTT allows an entry per 4768 * target and lun pair. 4769 */ 4770 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4771 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4772 } 4773 } 4774 4775 /* All of our queues are empty */ 4776 for (i = 0; i < 256; i++) 4777 ahc->qoutfifo[i] = SCB_LIST_NULL; 4778 4779 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4780 4781 for (i = 0; i < 256; i++) 4782 ahc->qinfifo[i] = SCB_LIST_NULL; 4783 4784 if ((ahc->features & AHC_MULTI_TID) != 0) { 4785 ahc_outb(ahc, TARGID, 0); 4786 ahc_outb(ahc, TARGID + 1, 0); 4787 } 4788 4789 /* 4790 * Tell the sequencer where it can find our arrays in memory. 4791 */ 4792 physaddr = ahc->scb_data->hscb_busaddr; 4793 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4794 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4795 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4796 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4797 4798 physaddr = ahc->shared_data_busaddr; 4799 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4800 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4801 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4802 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4803 4804 /* 4805 * Initialize the group code to command length table. 4806 * This overrides the values in TARG_SCSIRATE, so only 4807 * setup the table after we have processed that information. 4808 */ 4809 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4810 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4811 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4812 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4813 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4814 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4815 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4816 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4817 4818 /* Tell the sequencer of our initial queue positions */ 4819 ahc_outb(ahc, KERNEL_QINPOS, 0); 4820 ahc_outb(ahc, QINPOS, 0); 4821 ahc_outb(ahc, QOUTPOS, 0); 4822 4823 /* 4824 * Use the built in queue management registers 4825 * if they are available. 4826 */ 4827 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4828 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4829 ahc_outb(ahc, SDSCB_QOFF, 0); 4830 ahc_outb(ahc, SNSCB_QOFF, 0); 4831 ahc_outb(ahc, HNSCB_QOFF, 0); 4832 } 4833 4834 4835 /* We don't have any waiting selections */ 4836 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4837 4838 /* Our disconnection list is empty too */ 4839 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4840 4841 /* Message out buffer starts empty */ 4842 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4843 4844 /* 4845 * Setup the allowed SCSI Sequences based on operational mode. 4846 * If we are a target, we'll enalbe select in operations once 4847 * we've had a lun enabled. 4848 */ 4849 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4850 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4851 scsiseq_template |= ENRSELI; 4852 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4853 4854 /* 4855 * Load the Sequencer program and Enable the adapter 4856 * in "fast" mode. 4857 */ 4858 if (bootverbose) 4859 printf("%s: Downloading Sequencer Program...", 4860 ahc_name(ahc)); 4861 4862 ahc_loadseq(ahc); 4863 4864 if ((ahc->features & AHC_ULTRA2) != 0) { 4865 int wait; 4866 4867 /* 4868 * Wait for up to 500ms for our transceivers 4869 * to settle. If the adapter does not have 4870 * a cable attached, the transceivers may 4871 * never settle, so don't complain if we 4872 * fail here. 4873 */ 4874 ahc_pause(ahc); 4875 for (wait = 5000; 4876 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4877 wait--) 4878 ahc_delay(100); 4879 ahc_unpause(ahc); 4880 } 4881 4882 /* We have to wait until after any system dumps... */ 4883 ahc->shutdown_hook = shutdownhook_establish(ahc_shutdown, ahc); 4884 4885 return (0); 4886 } 4887 4888 void 4889 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4890 { 4891 u_int hcntrl; 4892 4893 hcntrl = ahc_inb(ahc, HCNTRL); 4894 hcntrl &= ~INTEN; 4895 ahc->pause &= ~INTEN; 4896 ahc->unpause &= ~INTEN; 4897 if (enable) { 4898 hcntrl |= INTEN; 4899 ahc->pause |= INTEN; 4900 ahc->unpause |= INTEN; 4901 } 4902 ahc_outb(ahc, HCNTRL, hcntrl); 4903 } 4904 4905 /* 4906 * Ensure that the card is paused in a location 4907 * outside of all critical sections and that all 4908 * pending work is completed prior to returning. 4909 * This routine should only be called from outside 4910 * an interrupt context. 4911 */ 4912 void 4913 ahc_pause_and_flushwork(struct ahc_softc *ahc) 4914 { 4915 int intstat; 4916 int maxloops; 4917 int paused; 4918 4919 maxloops = 1000; 4920 ahc->flags |= AHC_ALL_INTERRUPTS; 4921 intstat = 0; 4922 paused = FALSE; 4923 do { 4924 if (paused) 4925 ahc_unpause(ahc); 4926 ahc_intr(ahc); 4927 ahc_pause(ahc); 4928 paused = TRUE; 4929 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 4930 ahc_clear_critical_section(ahc); 4931 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4932 break; 4933 } while (--maxloops 4934 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0 4935 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)))); 4936 if (maxloops == 0) { 4937 printf("Infinite interrupt loop, INTSTAT = %x", 4938 ahc_inb(ahc, INTSTAT)); 4939 } 4940 ahc_platform_flushwork(ahc); 4941 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4942 } 4943 4944 int 4945 ahc_suspend(struct ahc_softc *ahc) 4946 { 4947 uint8_t *ptr; 4948 int i; 4949 4950 ahc_pause_and_flushwork(ahc); 4951 4952 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4953 return (EBUSY); 4954 4955 #if AHC_TARGET_MODE 4956 /* 4957 * XXX What about ATIOs that have not yet been serviced? 4958 * Perhaps we should just refuse to be suspended if we 4959 * are acting in a target role. 4960 */ 4961 if (ahc->pending_device != NULL) 4962 return (EBUSY); 4963 #endif 4964 4965 /* Save volatile registers */ 4966 if ((ahc->features & AHC_TWIN) != 0) { 4967 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4968 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4969 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4970 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4971 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4972 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4973 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4974 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4975 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4976 } 4977 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4978 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4979 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4980 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4981 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4982 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4983 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4984 4985 if ((ahc->chip & AHC_PCI) != 0) { 4986 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4987 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4988 } 4989 4990 if ((ahc->features & AHC_DT) != 0) { 4991 u_int sfunct; 4992 4993 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4994 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4995 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4996 ahc_outb(ahc, SFUNCT, sfunct); 4997 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4998 } 4999 5000 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5001 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 5002 5003 if ((ahc->features & AHC_ULTRA2) != 0) 5004 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 5005 5006 ptr = ahc->suspend_state.scratch_ram; 5007 for (i = 0; i < 64; i++) 5008 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 5009 5010 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5011 for (i = 0; i < 16; i++) 5012 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 5013 } 5014 5015 ptr = ahc->suspend_state.btt; 5016 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5017 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5018 int j; 5019 5020 for (j = 0;j < AHC_NUM_LUNS; j++) { 5021 u_int tcl; 5022 5023 tcl = BUILD_TCL(i << 4, j); 5024 *ptr = ahc_index_busy_tcl(ahc, tcl); 5025 } 5026 } 5027 } 5028 ahc_shutdown(ahc); 5029 return (0); 5030 } 5031 5032 int 5033 ahc_resume(struct ahc_softc *ahc) 5034 { 5035 uint8_t *ptr; 5036 int i; 5037 5038 ahc_reset(ahc); 5039 5040 ahc_build_free_scb_list(ahc); 5041 5042 /* Restore volatile registers */ 5043 if ((ahc->features & AHC_TWIN) != 0) { 5044 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5045 ahc_outb(ahc, SCSIID, ahc->our_id); 5046 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 5047 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 5048 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 5049 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 5050 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 5051 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 5052 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 5053 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5054 } 5055 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 5056 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 5057 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 5058 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 5059 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 5060 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 5061 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 5062 if ((ahc->features & AHC_ULTRA2) != 0) 5063 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5064 else 5065 ahc_outb(ahc, SCSIID, ahc->our_id); 5066 5067 if ((ahc->chip & AHC_PCI) != 0) { 5068 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 5069 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 5070 } 5071 5072 if ((ahc->features & AHC_DT) != 0) { 5073 u_int sfunct; 5074 5075 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 5076 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 5077 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 5078 ahc_outb(ahc, SFUNCT, sfunct); 5079 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 5080 } 5081 5082 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5083 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 5084 5085 if ((ahc->features & AHC_ULTRA2) != 0) 5086 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 5087 5088 ptr = ahc->suspend_state.scratch_ram; 5089 for (i = 0; i < 64; i++) 5090 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 5091 5092 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5093 for (i = 0; i < 16; i++) 5094 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 5095 } 5096 5097 ptr = ahc->suspend_state.btt; 5098 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5099 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5100 int j; 5101 5102 for (j = 0;j < AHC_NUM_LUNS; j++) { 5103 u_int tcl; 5104 5105 tcl = BUILD_TCL(i << 4, j); 5106 ahc_busy_tcl(ahc, tcl, *ptr); 5107 } 5108 } 5109 } 5110 return (0); 5111 } 5112 5113 /************************** Busy Target Table *********************************/ 5114 /* 5115 * Return the untagged transaction id for a given target/channel lun. 5116 * Optionally, clear the entry. 5117 */ 5118 u_int 5119 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5120 { 5121 u_int scbid; 5122 u_int target_offset; 5123 5124 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5125 u_int saved_scbptr; 5126 5127 saved_scbptr = ahc_inb(ahc, SCBPTR); 5128 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5129 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5130 ahc_outb(ahc, SCBPTR, saved_scbptr); 5131 } else { 5132 target_offset = TCL_TARGET_OFFSET(tcl); 5133 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5134 } 5135 5136 return (scbid); 5137 } 5138 5139 void 5140 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5141 { 5142 u_int target_offset; 5143 5144 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5145 u_int saved_scbptr; 5146 5147 saved_scbptr = ahc_inb(ahc, SCBPTR); 5148 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5149 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5150 ahc_outb(ahc, SCBPTR, saved_scbptr); 5151 } else { 5152 target_offset = TCL_TARGET_OFFSET(tcl); 5153 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5154 } 5155 } 5156 5157 void 5158 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5159 { 5160 u_int target_offset; 5161 5162 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5163 u_int saved_scbptr; 5164 5165 saved_scbptr = ahc_inb(ahc, SCBPTR); 5166 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5167 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5168 ahc_outb(ahc, SCBPTR, saved_scbptr); 5169 } else { 5170 target_offset = TCL_TARGET_OFFSET(tcl); 5171 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5172 } 5173 } 5174 5175 /************************** SCB and SCB queue management **********************/ 5176 int 5177 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5178 char channel, int lun, u_int tag, role_t role) 5179 { 5180 int targ = SCB_GET_TARGET(ahc, scb); 5181 char chan = SCB_GET_CHANNEL(ahc, scb); 5182 int slun = SCB_GET_LUN(scb); 5183 int match; 5184 5185 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5186 if (match != 0) 5187 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5188 if (match != 0) 5189 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5190 if (match != 0) { 5191 #if 0 5192 #if AHC_TARGET_MODE 5193 int group; 5194 5195 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5196 if (role == ROLE_INITIATOR) { 5197 match = (group != XPT_FC_GROUP_TMODE) 5198 && ((tag == scb->hscb->tag) 5199 || (tag == SCB_LIST_NULL)); 5200 } else if (role == ROLE_TARGET) { 5201 match = (group == XPT_FC_GROUP_TMODE) 5202 && ((tag == scb->io_ctx->csio.tag_id) 5203 || (tag == SCB_LIST_NULL)); 5204 } 5205 #else /* !AHC_TARGET_MODE */ 5206 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5207 #endif /* AHC_TARGET_MODE */ 5208 #endif 5209 } 5210 5211 return match; 5212 } 5213 5214 void 5215 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5216 { 5217 int target; 5218 char channel; 5219 int lun; 5220 5221 target = SCB_GET_TARGET(ahc, scb); 5222 lun = SCB_GET_LUN(scb); 5223 channel = SCB_GET_CHANNEL(ahc, scb); 5224 5225 ahc_search_qinfifo(ahc, target, channel, lun, 5226 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5227 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5228 5229 ahc_platform_freeze_devq(ahc, scb); 5230 } 5231 5232 void 5233 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5234 { 5235 struct scb *prev_scb; 5236 5237 prev_scb = NULL; 5238 if (ahc_qinfifo_count(ahc) != 0) { 5239 u_int prev_tag; 5240 uint8_t prev_pos; 5241 5242 prev_pos = ahc->qinfifonext - 1; 5243 prev_tag = ahc->qinfifo[prev_pos]; 5244 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5245 } 5246 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5247 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5248 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5249 } else { 5250 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5251 } 5252 } 5253 5254 static void 5255 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5256 struct scb *scb) 5257 { 5258 if (prev_scb == NULL) { 5259 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5260 } else { 5261 prev_scb->hscb->next = scb->hscb->tag; 5262 ahc_sync_scb(ahc, prev_scb, 5263 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5264 } 5265 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5266 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5267 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5268 } 5269 5270 static int 5271 ahc_qinfifo_count(struct ahc_softc *ahc) 5272 { 5273 uint8_t qinpos; 5274 uint8_t diff; 5275 5276 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5277 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5278 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5279 } else 5280 qinpos = ahc_inb(ahc, QINPOS); 5281 diff = ahc->qinfifonext - qinpos; 5282 return (diff); 5283 } 5284 5285 int 5286 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5287 int lun, u_int tag, role_t role, uint32_t status, 5288 ahc_search_action action) 5289 { 5290 struct scb *scb; 5291 struct scb *prev_scb; 5292 uint8_t qinstart; 5293 uint8_t qinpos; 5294 uint8_t qintail; 5295 uint8_t next; 5296 uint8_t prev; 5297 uint8_t curscbptr; 5298 int found; 5299 int have_qregs; 5300 5301 qintail = ahc->qinfifonext; 5302 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5303 if (have_qregs) { 5304 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5305 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5306 } else 5307 qinstart = ahc_inb(ahc, QINPOS); 5308 qinpos = qinstart; 5309 found = 0; 5310 prev_scb = NULL; 5311 5312 if (action == SEARCH_COMPLETE) { 5313 /* 5314 * Don't attempt to run any queued untagged transactions 5315 * until we are done with the abort process. 5316 */ 5317 ahc_freeze_untagged_queues(ahc); 5318 } 5319 5320 /* 5321 * Start with an empty queue. Entries that are not chosen 5322 * for removal will be re-added to the queue as we go. 5323 */ 5324 ahc->qinfifonext = qinpos; 5325 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5326 5327 while (qinpos != qintail) { 5328 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5329 if (scb == NULL) { 5330 printf("qinpos = %d, SCB index = %d\n", 5331 qinpos, ahc->qinfifo[qinpos]); 5332 panic("Loop 1\n"); 5333 } 5334 5335 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5336 /* 5337 * We found an scb that needs to be acted on. 5338 */ 5339 found++; 5340 switch (action) { 5341 case SEARCH_COMPLETE: 5342 { 5343 cam_status ostat; 5344 cam_status cstat; 5345 5346 ostat = ahc_get_transaction_status(scb); 5347 if (ostat == CAM_REQ_INPROG) 5348 ahc_set_transaction_status(scb, status); 5349 cstat = ahc_get_transaction_status(scb); 5350 if (cstat != CAM_REQ_CMP) 5351 ahc_freeze_scb(scb); 5352 if ((scb->flags & SCB_ACTIVE) == 0) 5353 printf("Inactive SCB in qinfifo\n"); 5354 ahc_done(ahc, scb); 5355 5356 /* FALLTHROUGH */ 5357 } 5358 case SEARCH_REMOVE: 5359 break; 5360 case SEARCH_COUNT: 5361 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5362 prev_scb = scb; 5363 break; 5364 } 5365 } else { 5366 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5367 prev_scb = scb; 5368 } 5369 qinpos++; 5370 } 5371 5372 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5373 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5374 } else { 5375 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5376 } 5377 5378 if (action != SEARCH_COUNT 5379 && (found != 0) 5380 && (qinstart != ahc->qinfifonext)) { 5381 /* 5382 * The sequencer may be in the process of DMA'ing 5383 * down the SCB at the beginning of the queue. 5384 * This could be problematic if either the first, 5385 * or the second SCB is removed from the queue 5386 * (the first SCB includes a pointer to the "next" 5387 * SCB to DMA). If we have removed any entries, swap 5388 * the first element in the queue with the next HSCB 5389 * so the sequencer will notice that NEXT_QUEUED_SCB 5390 * has changed during its DMA attempt and will retry 5391 * the DMA. 5392 */ 5393 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5394 5395 if (scb == NULL) { 5396 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5397 found, qinstart, ahc->qinfifonext); 5398 panic("First/Second Qinfifo fixup\n"); 5399 } 5400 /* 5401 * ahc_swap_with_next_hscb forces our next pointer to 5402 * point to the reserved SCB for future commands. Save 5403 * and restore our original next pointer to maintain 5404 * queue integrity. 5405 */ 5406 next = scb->hscb->next; 5407 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5408 ahc_swap_with_next_hscb(ahc, scb); 5409 scb->hscb->next = next; 5410 ahc->qinfifo[qinstart] = scb->hscb->tag; 5411 5412 /* Tell the card about the new head of the qinfifo. */ 5413 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5414 5415 /* Fixup the tail "next" pointer. */ 5416 qintail = ahc->qinfifonext - 1; 5417 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5418 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5419 } 5420 5421 /* 5422 * Search waiting for selection list. 5423 */ 5424 curscbptr = ahc_inb(ahc, SCBPTR); 5425 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5426 prev = SCB_LIST_NULL; 5427 5428 while (next != SCB_LIST_NULL) { 5429 uint8_t scb_index; 5430 5431 ahc_outb(ahc, SCBPTR, next); 5432 scb_index = ahc_inb(ahc, SCB_TAG); 5433 if (scb_index >= ahc->scb_data->numscbs) { 5434 printf("Waiting List inconsistency. " 5435 "SCB index == %d, yet numscbs == %d.", 5436 scb_index, ahc->scb_data->numscbs); 5437 ahc_dump_card_state(ahc); 5438 panic("for safety"); 5439 } 5440 scb = ahc_lookup_scb(ahc, scb_index); 5441 if (scb == NULL) { 5442 printf("scb_index = %d, next = %d\n", 5443 scb_index, next); 5444 panic("Waiting List traversal\n"); 5445 } 5446 if (ahc_match_scb(ahc, scb, target, channel, 5447 lun, SCB_LIST_NULL, role)) { 5448 /* 5449 * We found an scb that needs to be acted on. 5450 */ 5451 found++; 5452 switch (action) { 5453 case SEARCH_COMPLETE: 5454 { 5455 cam_status ostat; 5456 cam_status cstat; 5457 5458 ostat = ahc_get_transaction_status(scb); 5459 if (ostat == CAM_REQ_INPROG) 5460 ahc_set_transaction_status(scb, status); 5461 cstat = ahc_get_transaction_status(scb); 5462 if (cstat != CAM_REQ_CMP) 5463 ahc_freeze_scb(scb); 5464 if ((scb->flags & SCB_ACTIVE) == 0) 5465 printf("Inactive SCB in Waiting List\n"); 5466 ahc_done(ahc, scb); 5467 /* FALLTHROUGH */ 5468 } 5469 case SEARCH_REMOVE: 5470 next = ahc_rem_wscb(ahc, next, prev); 5471 break; 5472 case SEARCH_COUNT: 5473 prev = next; 5474 next = ahc_inb(ahc, SCB_NEXT); 5475 break; 5476 } 5477 } else { 5478 5479 prev = next; 5480 next = ahc_inb(ahc, SCB_NEXT); 5481 } 5482 } 5483 ahc_outb(ahc, SCBPTR, curscbptr); 5484 5485 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5486 channel, lun, status, action); 5487 5488 if (action == SEARCH_COMPLETE) 5489 ahc_release_untagged_queues(ahc); 5490 return (found); 5491 } 5492 5493 int 5494 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsipi_xfer *xs, /*ahc_io_ctx_t ctx,*/ 5495 int target, char channel, int lun, uint32_t status, 5496 ahc_search_action action) 5497 { 5498 struct scb *scb; 5499 int maxtarget; 5500 int found; 5501 int i; 5502 5503 if (action == SEARCH_COMPLETE) { 5504 /* 5505 * Don't attempt to run any queued untagged transactions 5506 * until we are done with the abort process. 5507 */ 5508 ahc_freeze_untagged_queues(ahc); 5509 } 5510 5511 found = 0; 5512 i = 0; 5513 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5514 5515 maxtarget = 16; 5516 if (target != CAM_TARGET_WILDCARD) { 5517 5518 i = target; 5519 if (channel == 'B') 5520 i += 8; 5521 maxtarget = i + 1; 5522 } 5523 } else { 5524 maxtarget = 0; 5525 } 5526 5527 for (; i < maxtarget; i++) { 5528 struct scb_tailq *untagged_q; 5529 struct scb *next_scb; 5530 5531 untagged_q = &(ahc->untagged_queues[i]); 5532 next_scb = TAILQ_FIRST(untagged_q); 5533 while (next_scb != NULL) { 5534 5535 scb = next_scb; 5536 next_scb = TAILQ_NEXT(scb, links.tqe); 5537 5538 /* 5539 * The head of the list may be the currently 5540 * active untagged command for a device. 5541 * We're only searching for commands that 5542 * have not been started. A transaction 5543 * marked active but still in the qinfifo 5544 * is removed by the qinfifo scanning code 5545 * above. 5546 */ 5547 if ((scb->flags & SCB_ACTIVE) != 0) 5548 continue; 5549 5550 if (ahc_match_scb(ahc, scb, target, channel, lun, 5551 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5552 /*|| (ctx != NULL && ctx != scb->io_ctx)*/) 5553 continue; 5554 5555 /* 5556 * We found an scb that needs to be acted on. 5557 */ 5558 found++; 5559 switch (action) { 5560 case SEARCH_COMPLETE: 5561 { 5562 cam_status ostat; 5563 cam_status cstat; 5564 5565 ostat = ahc_get_transaction_status(scb); 5566 if (ostat == CAM_REQ_INPROG) 5567 ahc_set_transaction_status(scb, status); 5568 cstat = ahc_get_transaction_status(scb); 5569 if (cstat != CAM_REQ_CMP) 5570 ahc_freeze_scb(scb); 5571 if ((scb->flags & SCB_ACTIVE) == 0) 5572 printf("Inactive SCB in untaggedQ\n"); 5573 ahc_done(ahc, scb); 5574 break; 5575 } 5576 case SEARCH_REMOVE: 5577 scb->flags &= ~SCB_UNTAGGEDQ; 5578 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5579 break; 5580 case SEARCH_COUNT: 5581 break; 5582 } 5583 } 5584 } 5585 5586 if (action == SEARCH_COMPLETE) 5587 ahc_release_untagged_queues(ahc); 5588 return (found); 5589 } 5590 5591 int 5592 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5593 int lun, u_int tag, int stop_on_first, int remove, 5594 int save_state) 5595 { 5596 struct scb *scbp; 5597 u_int next; 5598 u_int prev; 5599 u_int count; 5600 u_int active_scb; 5601 5602 count = 0; 5603 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5604 prev = SCB_LIST_NULL; 5605 5606 if (save_state) { 5607 /* restore this when we're done */ 5608 active_scb = ahc_inb(ahc, SCBPTR); 5609 } else 5610 /* Silence compiler */ 5611 active_scb = SCB_LIST_NULL; 5612 5613 while (next != SCB_LIST_NULL) { 5614 u_int scb_index; 5615 5616 ahc_outb(ahc, SCBPTR, next); 5617 scb_index = ahc_inb(ahc, SCB_TAG); 5618 if (scb_index >= ahc->scb_data->numscbs) { 5619 printf("Disconnected List inconsistency. " 5620 "SCB index == %d, yet numscbs == %d.", 5621 scb_index, ahc->scb_data->numscbs); 5622 ahc_dump_card_state(ahc); 5623 panic("for safety"); 5624 } 5625 5626 if (next == prev) { 5627 panic("Disconnected List Loop. " 5628 "cur SCBPTR == %x, prev SCBPTR == %x.", 5629 next, prev); 5630 } 5631 scbp = ahc_lookup_scb(ahc, scb_index); 5632 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5633 tag, ROLE_INITIATOR)) { 5634 count++; 5635 if (remove) { 5636 next = 5637 ahc_rem_scb_from_disc_list(ahc, prev, next); 5638 } else { 5639 prev = next; 5640 next = ahc_inb(ahc, SCB_NEXT); 5641 } 5642 if (stop_on_first) 5643 break; 5644 } else { 5645 prev = next; 5646 next = ahc_inb(ahc, SCB_NEXT); 5647 } 5648 } 5649 if (save_state) 5650 ahc_outb(ahc, SCBPTR, active_scb); 5651 return (count); 5652 } 5653 5654 /* 5655 * Remove an SCB from the on chip list of disconnected transactions. 5656 * This is empty/unused if we are not performing SCB paging. 5657 */ 5658 static u_int 5659 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5660 { 5661 u_int next; 5662 5663 ahc_outb(ahc, SCBPTR, scbptr); 5664 next = ahc_inb(ahc, SCB_NEXT); 5665 5666 ahc_outb(ahc, SCB_CONTROL, 0); 5667 5668 ahc_add_curscb_to_free_list(ahc); 5669 5670 if (prev != SCB_LIST_NULL) { 5671 ahc_outb(ahc, SCBPTR, prev); 5672 ahc_outb(ahc, SCB_NEXT, next); 5673 } else 5674 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5675 5676 return (next); 5677 } 5678 5679 /* 5680 * Add the SCB as selected by SCBPTR onto the on chip list of 5681 * free hardware SCBs. This list is empty/unused if we are not 5682 * performing SCB paging. 5683 */ 5684 static void 5685 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5686 { 5687 /* 5688 * Invalidate the tag so that our abort 5689 * routines don't think it's active. 5690 */ 5691 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5692 5693 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5694 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5695 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5696 } 5697 } 5698 5699 /* 5700 * Manipulate the waiting for selection list and return the 5701 * scb that follows the one that we remove. 5702 */ 5703 static u_int 5704 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5705 { 5706 u_int curscb, next; 5707 5708 /* 5709 * Select the SCB we want to abort and 5710 * pull the next pointer out of it. 5711 */ 5712 curscb = ahc_inb(ahc, SCBPTR); 5713 ahc_outb(ahc, SCBPTR, scbpos); 5714 next = ahc_inb(ahc, SCB_NEXT); 5715 5716 /* Clear the necessary fields */ 5717 ahc_outb(ahc, SCB_CONTROL, 0); 5718 5719 ahc_add_curscb_to_free_list(ahc); 5720 5721 /* update the waiting list */ 5722 if (prev == SCB_LIST_NULL) { 5723 /* First in the list */ 5724 ahc_outb(ahc, WAITING_SCBH, next); 5725 5726 /* 5727 * Ensure we aren't attempting to perform 5728 * selection for this entry. 5729 */ 5730 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5731 } else { 5732 /* 5733 * Select the scb that pointed to us 5734 * and update its next pointer. 5735 */ 5736 ahc_outb(ahc, SCBPTR, prev); 5737 ahc_outb(ahc, SCB_NEXT, next); 5738 } 5739 5740 /* 5741 * Point us back at the original scb position. 5742 */ 5743 ahc_outb(ahc, SCBPTR, curscb); 5744 return next; 5745 } 5746 5747 /******************************** Error Handling ******************************/ 5748 /* 5749 * Abort all SCBs that match the given description (target/channel/lun/tag), 5750 * setting their status to the passed in status if the status has not already 5751 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5752 * is paused before it is called. 5753 */ 5754 int 5755 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5756 int lun, u_int tag, role_t role, uint32_t status) 5757 { 5758 struct scb *scbp; 5759 struct scb *scbp_next; 5760 u_int active_scb; 5761 int i, j; 5762 int maxtarget; 5763 int minlun; 5764 int maxlun; 5765 5766 int found; 5767 5768 /* 5769 * Don't attempt to run any queued untagged transactions 5770 * until we are done with the abort process. 5771 */ 5772 ahc_freeze_untagged_queues(ahc); 5773 5774 /* restore this when we're done */ 5775 active_scb = ahc_inb(ahc, SCBPTR); 5776 5777 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5778 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5779 5780 /* 5781 * Clean out the busy target table for any untagged commands. 5782 */ 5783 i = 0; 5784 maxtarget = 16; 5785 if (target != CAM_TARGET_WILDCARD) { 5786 i = target; 5787 if (channel == 'B') 5788 i += 8; 5789 maxtarget = i + 1; 5790 } 5791 5792 if (lun == CAM_LUN_WILDCARD) { 5793 5794 /* 5795 * Unless we are using an SCB based 5796 * busy targets table, there is only 5797 * one table entry for all luns of 5798 * a target. 5799 */ 5800 minlun = 0; 5801 maxlun = 1; 5802 if ((ahc->flags & AHC_SCB_BTT) != 0) 5803 maxlun = AHC_NUM_LUNS; 5804 } else { 5805 minlun = lun; 5806 maxlun = lun + 1; 5807 } 5808 5809 if (role != ROLE_TARGET) { 5810 for (;i < maxtarget; i++) { 5811 for (j = minlun;j < maxlun; j++) { 5812 u_int scbid; 5813 u_int tcl; 5814 5815 tcl = BUILD_TCL(i << 4, j); 5816 scbid = ahc_index_busy_tcl(ahc, tcl); 5817 scbp = ahc_lookup_scb(ahc, scbid); 5818 if (scbp == NULL 5819 || ahc_match_scb(ahc, scbp, target, channel, 5820 lun, tag, role) == 0) 5821 continue; 5822 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5823 } 5824 } 5825 5826 /* 5827 * Go through the disconnected list and remove any entries we 5828 * have queued for completion, 0'ing their control byte too. 5829 * We save the active SCB and restore it ourselves, so there 5830 * is no reason for this search to restore it too. 5831 */ 5832 ahc_search_disc_list(ahc, target, channel, lun, tag, 5833 /*stop_on_first*/FALSE, /*remove*/TRUE, 5834 /*save_state*/FALSE); 5835 } 5836 5837 /* 5838 * Go through the hardware SCB array looking for commands that 5839 * were active but not on any list. In some cases, these remnants 5840 * might not still have mappings in the scbindex array (e.g. unexpected 5841 * bus free with the same scb queued for an abort). Don't hold this 5842 * against them. 5843 */ 5844 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5845 u_int scbid; 5846 5847 ahc_outb(ahc, SCBPTR, i); 5848 scbid = ahc_inb(ahc, SCB_TAG); 5849 scbp = ahc_lookup_scb(ahc, scbid); 5850 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5851 || (scbp != NULL 5852 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5853 ahc_add_curscb_to_free_list(ahc); 5854 } 5855 5856 /* 5857 * Go through the pending CCB list and look for 5858 * commands for this target that are still active. 5859 * These are other tagged commands that were 5860 * disconnected when the reset occurred. 5861 */ 5862 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5863 while (scbp_next != NULL) { 5864 scbp = scbp_next; 5865 scbp_next = LIST_NEXT(scbp, pending_links); 5866 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5867 cam_status ostat; 5868 5869 ostat = ahc_get_transaction_status(scbp); 5870 if (ostat == CAM_REQ_INPROG) 5871 ahc_set_transaction_status(scbp, status); 5872 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5873 ahc_freeze_scb(scbp); 5874 if ((scbp->flags & SCB_ACTIVE) == 0) 5875 printf("Inactive SCB on pending list\n"); 5876 ahc_done(ahc, scbp); 5877 found++; 5878 } 5879 } 5880 ahc_outb(ahc, SCBPTR, active_scb); 5881 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5882 ahc_release_untagged_queues(ahc); 5883 return found; 5884 } 5885 5886 static void 5887 ahc_reset_current_bus(struct ahc_softc *ahc) 5888 { 5889 uint8_t scsiseq; 5890 5891 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5892 scsiseq = ahc_inb(ahc, SCSISEQ); 5893 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5894 ahc_flush_device_writes(ahc); 5895 ahc_delay(AHC_BUSRESET_DELAY); 5896 /* Turn off the bus reset */ 5897 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5898 5899 ahc_clear_intstat(ahc); 5900 5901 /* Re-enable reset interrupts */ 5902 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5903 } 5904 5905 int 5906 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5907 { 5908 struct ahc_devinfo devinfo; 5909 u_int initiator, target, max_scsiid; 5910 u_int sblkctl; 5911 u_int scsiseq; 5912 u_int simode1; 5913 int found; 5914 int restart_needed; 5915 char cur_channel; 5916 5917 ahc->pending_device = NULL; 5918 5919 ahc_compile_devinfo(&devinfo, 5920 CAM_TARGET_WILDCARD, 5921 CAM_TARGET_WILDCARD, 5922 CAM_LUN_WILDCARD, 5923 channel, ROLE_UNKNOWN); 5924 ahc_pause(ahc); 5925 5926 /* Make sure the sequencer is in a safe location. */ 5927 ahc_clear_critical_section(ahc); 5928 5929 /* 5930 * Run our command complete fifos to ensure that we perform 5931 * completion processing on any commands that 'completed' 5932 * before the reset occurred. 5933 */ 5934 ahc_run_qoutfifo(ahc); 5935 #if AHC_TARGET_MODE 5936 /* 5937 * XXX - In Twin mode, the tqinfifo may have commands 5938 * for an unaffected channel in it. However, if 5939 * we have run out of ATIO resources to drain that 5940 * queue, we may not get them all out here. Further, 5941 * the blocked transactions for the reset channel 5942 * should just be killed off, irrespecitve of whether 5943 * we are blocked on ATIO resources. Write a routine 5944 * to compact the tqinfifo appropriately. 5945 */ 5946 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5947 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5948 } 5949 #endif 5950 5951 /* 5952 * Reset the bus if we are initiating this reset 5953 */ 5954 sblkctl = ahc_inb(ahc, SBLKCTL); 5955 cur_channel = 'A'; 5956 if ((ahc->features & AHC_TWIN) != 0 5957 && ((sblkctl & SELBUSB) != 0)) 5958 cur_channel = 'B'; 5959 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5960 if (cur_channel != channel) { 5961 /* Case 1: Command for another bus is active 5962 * Stealthily reset the other bus without 5963 * upsetting the current bus. 5964 */ 5965 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5966 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5967 #if AHC_TARGET_MODE 5968 /* 5969 * Bus resets clear ENSELI, so we cannot 5970 * defer re-enabling bus reset interrupts 5971 * if we are in target mode. 5972 */ 5973 if ((ahc->flags & AHC_TARGETROLE) != 0) 5974 simode1 |= ENSCSIRST; 5975 #endif 5976 ahc_outb(ahc, SIMODE1, simode1); 5977 if (initiate_reset) 5978 ahc_reset_current_bus(ahc); 5979 ahc_clear_intstat(ahc); 5980 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5981 ahc_outb(ahc, SBLKCTL, sblkctl); 5982 restart_needed = FALSE; 5983 } else { 5984 /* Case 2: A command from this bus is active or we're idle */ 5985 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5986 #if AHC_TARGET_MODE 5987 /* 5988 * Bus resets clear ENSELI, so we cannot 5989 * defer re-enabling bus reset interrupts 5990 * if we are in target mode. 5991 */ 5992 if ((ahc->flags & AHC_TARGETROLE) != 0) 5993 simode1 |= ENSCSIRST; 5994 #endif 5995 ahc_outb(ahc, SIMODE1, simode1); 5996 if (initiate_reset) 5997 ahc_reset_current_bus(ahc); 5998 ahc_clear_intstat(ahc); 5999 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6000 restart_needed = TRUE; 6001 } 6002 6003 /* 6004 * Clean up all the state information for the 6005 * pending transactions on this bus. 6006 */ 6007 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6008 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6009 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6010 6011 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6012 6013 #ifdef AHC_TARGET_MODE 6014 /* 6015 * Send an immediate notify ccb to all target more peripheral 6016 * drivers affected by this action. 6017 */ 6018 for (target = 0; target <= max_scsiid; target++) { 6019 struct ahc_tmode_tstate* tstate; 6020 u_int lun; 6021 6022 tstate = ahc->enabled_targets[target]; 6023 if (tstate == NULL) 6024 continue; 6025 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6026 struct ahc_tmode_lstate* lstate; 6027 6028 lstate = tstate->enabled_luns[lun]; 6029 if (lstate == NULL) 6030 continue; 6031 6032 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6033 EVENT_TYPE_BUS_RESET, /*arg*/0); 6034 ahc_send_lstate_events(ahc, lstate); 6035 } 6036 } 6037 #endif 6038 /* 6039 * Revert to async/narrow transfers until we renegotiate. 6040 */ 6041 for (target = 0; target <= max_scsiid; target++) { 6042 6043 if (ahc->enabled_targets[target] == NULL) 6044 continue; 6045 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6046 struct ahc_devinfo devinfo; 6047 6048 ahc_compile_devinfo(&devinfo, target, initiator, 6049 CAM_LUN_WILDCARD, 6050 channel, ROLE_UNKNOWN); 6051 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6052 AHC_TRANS_CUR, /*paused*/TRUE); 6053 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6054 /*period*/0, /*offset*/0, 6055 /*ppr_options*/0, AHC_TRANS_CUR, 6056 /*paused*/TRUE); 6057 } 6058 } 6059 6060 if (restart_needed) 6061 ahc_restart(ahc); 6062 else 6063 ahc_unpause(ahc); 6064 return found; 6065 } 6066 6067 6068 /***************************** Residual Processing ****************************/ 6069 /* 6070 * Calculate the residual for a just completed SCB. 6071 */ 6072 void 6073 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6074 { 6075 struct hardware_scb *hscb; 6076 struct status_pkt *spkt; 6077 uint32_t sgptr; 6078 uint32_t resid_sgptr; 6079 uint32_t resid; 6080 6081 /* 6082 * 5 cases. 6083 * 1) No residual. 6084 * SG_RESID_VALID clear in sgptr. 6085 * 2) Transferless command 6086 * 3) Never performed any transfers. 6087 * sgptr has SG_FULL_RESID set. 6088 * 4) No residual but target did not 6089 * save data pointers after the 6090 * last transfer, so sgptr was 6091 * never updated. 6092 * 5) We have a partial residual. 6093 * Use residual_sgptr to determine 6094 * where we are. 6095 */ 6096 6097 hscb = scb->hscb; 6098 sgptr = ahc_le32toh(hscb->sgptr); 6099 if ((sgptr & SG_RESID_VALID) == 0) 6100 /* Case 1 */ 6101 return; 6102 sgptr &= ~SG_RESID_VALID; 6103 6104 if ((sgptr & SG_LIST_NULL) != 0) 6105 /* Case 2 */ 6106 return; 6107 6108 spkt = &hscb->shared_data.status; 6109 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6110 if ((sgptr & SG_FULL_RESID) != 0) { 6111 /* Case 3 */ 6112 resid = ahc_get_transfer_length(scb); 6113 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6114 /* Case 4 */ 6115 return; 6116 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6117 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6118 } else { 6119 struct ahc_dma_seg *sg; 6120 6121 /* 6122 * Remainder of the SG where the transfer 6123 * stopped. 6124 */ 6125 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6126 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6127 6128 /* The residual sg_ptr always points to the next sg */ 6129 sg--; 6130 6131 /* 6132 * Add up the contents of all residual 6133 * SG segments that are after the SG where 6134 * the transfer stopped. 6135 */ 6136 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6137 sg++; 6138 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6139 } 6140 } 6141 if ((scb->flags & SCB_SENSE) == 0) 6142 ahc_set_residual(scb, resid); 6143 else 6144 ahc_set_sense_residual(scb, resid); 6145 6146 #ifdef AHC_DEBUG 6147 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6148 ahc_print_path(ahc, scb); 6149 printf("Handled %sResidual of %d bytes\n", 6150 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6151 } 6152 #endif 6153 } 6154 6155 /******************************* Target Mode **********************************/ 6156 #ifdef AHC_TARGET_MODE 6157 /* 6158 * Add a target mode event to this lun's queue 6159 */ 6160 static void 6161 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6162 u_int initiator_id, u_int event_type, u_int event_arg) 6163 { 6164 struct ahc_tmode_event *event; 6165 int pending; 6166 6167 xpt_freeze_devq(lstate->path, /*count*/1); 6168 if (lstate->event_w_idx >= lstate->event_r_idx) 6169 pending = lstate->event_w_idx - lstate->event_r_idx; 6170 else 6171 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6172 - (lstate->event_r_idx - lstate->event_w_idx); 6173 6174 if (event_type == EVENT_TYPE_BUS_RESET 6175 || event_type == MSG_BUS_DEV_RESET) { 6176 /* 6177 * Any earlier events are irrelevant, so reset our buffer. 6178 * This has the effect of allowing us to deal with reset 6179 * floods (an external device holding down the reset line) 6180 * without losing the event that is really interesting. 6181 */ 6182 lstate->event_r_idx = 0; 6183 lstate->event_w_idx = 0; 6184 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6185 } 6186 6187 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6188 xpt_print_path(lstate->path); 6189 printf("immediate event %x:%x lost\n", 6190 lstate->event_buffer[lstate->event_r_idx].event_type, 6191 lstate->event_buffer[lstate->event_r_idx].event_arg); 6192 lstate->event_r_idx++; 6193 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6194 lstate->event_r_idx = 0; 6195 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6196 } 6197 6198 event = &lstate->event_buffer[lstate->event_w_idx]; 6199 event->initiator_id = initiator_id; 6200 event->event_type = event_type; 6201 event->event_arg = event_arg; 6202 lstate->event_w_idx++; 6203 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6204 lstate->event_w_idx = 0; 6205 } 6206 6207 /* 6208 * Send any target mode events queued up waiting 6209 * for immediate notify resources. 6210 */ 6211 void 6212 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6213 { 6214 struct ccb_hdr *ccbh; 6215 struct ccb_immed_notify *inot; 6216 6217 while (lstate->event_r_idx != lstate->event_w_idx 6218 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6219 struct ahc_tmode_event *event; 6220 6221 event = &lstate->event_buffer[lstate->event_r_idx]; 6222 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6223 inot = (struct ccb_immed_notify *)ccbh; 6224 switch (event->event_type) { 6225 case EVENT_TYPE_BUS_RESET: 6226 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6227 break; 6228 default: 6229 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6230 inot->message_args[0] = event->event_type; 6231 inot->message_args[1] = event->event_arg; 6232 break; 6233 } 6234 inot->initiator_id = event->initiator_id; 6235 inot->sense_len = 0; 6236 xpt_done((union ccb *)inot); 6237 lstate->event_r_idx++; 6238 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6239 lstate->event_r_idx = 0; 6240 } 6241 } 6242 #endif 6243 6244 /******************** Sequencer Program Patching/Download *********************/ 6245 6246 #ifdef AHC_DUMP_SEQ 6247 void 6248 ahc_dumpseq(struct ahc_softc* ahc) 6249 { 6250 int i; 6251 int max_prog; 6252 6253 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 6254 max_prog = 448; 6255 else if ((ahc->features & AHC_ULTRA2) != 0) 6256 max_prog = 768; 6257 else 6258 max_prog = 512; 6259 6260 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6261 ahc_outb(ahc, SEQADDR0, 0); 6262 ahc_outb(ahc, SEQADDR1, 0); 6263 for (i = 0; i < max_prog; i++) { 6264 uint8_t ins_bytes[4]; 6265 6266 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6267 printf("0x%08x\n", ins_bytes[0] << 24 6268 | ins_bytes[1] << 16 6269 | ins_bytes[2] << 8 6270 | ins_bytes[3]); 6271 } 6272 } 6273 #endif 6274 6275 static void 6276 ahc_loadseq(struct ahc_softc *ahc) 6277 { 6278 struct cs cs_table[num_critical_sections]; 6279 u_int begin_set[num_critical_sections]; 6280 u_int end_set[num_critical_sections]; 6281 struct patch *cur_patch; 6282 u_int cs_count; 6283 u_int cur_cs; 6284 u_int i; 6285 int downloaded; 6286 u_int skip_addr; 6287 u_int sg_prefetch_cnt; 6288 uint8_t download_consts[7]; 6289 6290 /* 6291 * Start out with 0 critical sections 6292 * that apply to this firmware load. 6293 */ 6294 cs_count = 0; 6295 cur_cs = 0; 6296 memset(begin_set, 0, sizeof(begin_set)); 6297 memset(end_set, 0, sizeof(end_set)); 6298 6299 /* Setup downloadable constant table */ 6300 download_consts[QOUTFIFO_OFFSET] = 0; 6301 if (ahc->targetcmds != NULL) 6302 download_consts[QOUTFIFO_OFFSET] += 32; 6303 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6304 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6305 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6306 sg_prefetch_cnt = ahc->pci_cachesize; 6307 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6308 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6309 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6310 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6311 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6312 6313 cur_patch = patches; 6314 downloaded = 0; 6315 skip_addr = 0; 6316 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6317 ahc_outb(ahc, SEQADDR0, 0); 6318 ahc_outb(ahc, SEQADDR1, 0); 6319 6320 for (i = 0; i < sizeof(seqprog)/4; i++) { 6321 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6322 /* 6323 * Don't download this instruction as it 6324 * is in a patch that was removed. 6325 */ 6326 continue; 6327 } 6328 /* 6329 * Move through the CS table until we find a CS 6330 * that might apply to this instruction. 6331 */ 6332 for (; cur_cs < num_critical_sections; cur_cs++) { 6333 if (critical_sections[cur_cs].end <= i) { 6334 if (begin_set[cs_count] == TRUE 6335 && end_set[cs_count] == FALSE) { 6336 cs_table[cs_count].end = downloaded; 6337 end_set[cs_count] = TRUE; 6338 cs_count++; 6339 } 6340 continue; 6341 } 6342 if (critical_sections[cur_cs].begin <= i 6343 && begin_set[cs_count] == FALSE) { 6344 cs_table[cs_count].begin = downloaded; 6345 begin_set[cs_count] = TRUE; 6346 } 6347 break; 6348 } 6349 ahc_download_instr(ahc, i, download_consts); 6350 downloaded++; 6351 } 6352 6353 ahc->num_critical_sections = cs_count; 6354 if (cs_count != 0) { 6355 6356 cs_count *= sizeof(struct cs); 6357 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6358 if (ahc->critical_sections == NULL) 6359 panic("ahc_loadseq: Could not malloc"); 6360 memcpy(ahc->critical_sections, cs_table, cs_count); 6361 } 6362 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6363 ahc_restart(ahc); 6364 6365 if (bootverbose) { 6366 printf(" %d instructions downloaded\n", downloaded); 6367 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6368 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6369 } 6370 } 6371 6372 static int 6373 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6374 u_int start_instr, u_int *skip_addr) 6375 { 6376 struct patch *cur_patch; 6377 struct patch *last_patch; 6378 u_int num_patches; 6379 6380 num_patches = sizeof(patches)/sizeof(struct patch); 6381 last_patch = &patches[num_patches]; 6382 cur_patch = *start_patch; 6383 6384 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6385 6386 if (cur_patch->patch_func(ahc) == 0) { 6387 6388 /* Start rejecting code */ 6389 *skip_addr = start_instr + cur_patch->skip_instr; 6390 cur_patch += cur_patch->skip_patch; 6391 } else { 6392 /* Accepted this patch. Advance to the next 6393 * one and wait for our intruction pointer to 6394 * hit this point. 6395 */ 6396 cur_patch++; 6397 } 6398 } 6399 6400 *start_patch = cur_patch; 6401 if (start_instr < *skip_addr) 6402 /* Still skipping */ 6403 return (0); 6404 6405 return (1); 6406 } 6407 6408 static void 6409 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6410 { 6411 union ins_formats instr; 6412 struct ins_format1 *fmt1_ins; 6413 struct ins_format3 *fmt3_ins; 6414 u_int opcode; 6415 6416 /* 6417 * The firmware is always compiled into a little endian format. 6418 */ 6419 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6420 6421 fmt1_ins = &instr.format1; 6422 fmt3_ins = NULL; 6423 6424 /* Pull the opcode */ 6425 opcode = instr.format1.opcode; 6426 switch (opcode) { 6427 case AIC_OP_JMP: 6428 case AIC_OP_JC: 6429 case AIC_OP_JNC: 6430 case AIC_OP_CALL: 6431 case AIC_OP_JNE: 6432 case AIC_OP_JNZ: 6433 case AIC_OP_JE: 6434 case AIC_OP_JZ: 6435 { 6436 struct patch *cur_patch; 6437 int address_offset; 6438 u_int address; 6439 u_int skip_addr; 6440 u_int i; 6441 6442 fmt3_ins = &instr.format3; 6443 address_offset = 0; 6444 address = fmt3_ins->address; 6445 cur_patch = patches; 6446 skip_addr = 0; 6447 for (i = 0; i < address;) { 6448 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6449 6450 if (skip_addr > i) { 6451 int end_addr; 6452 6453 end_addr = MIN(address, skip_addr); 6454 address_offset += end_addr - i; 6455 i = skip_addr; 6456 } else { 6457 i++; 6458 } 6459 } 6460 address -= address_offset; 6461 fmt3_ins->address = address; 6462 /* FALLTHROUGH */ 6463 } 6464 case AIC_OP_OR: 6465 case AIC_OP_AND: 6466 case AIC_OP_XOR: 6467 case AIC_OP_ADD: 6468 case AIC_OP_ADC: 6469 case AIC_OP_BMOV: 6470 if (fmt1_ins->parity != 0) { 6471 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6472 } 6473 fmt1_ins->parity = 0; 6474 if ((ahc->features & AHC_CMD_CHAN) == 0 6475 && opcode == AIC_OP_BMOV) { 6476 /* 6477 * Block move was added at the same time 6478 * as the command channel. Verify that 6479 * this is only a move of a single element 6480 * and convert the BMOV to a MOV 6481 * (AND with an immediate of FF). 6482 */ 6483 if (fmt1_ins->immediate != 1) 6484 panic("%s: BMOV not supported\n", 6485 ahc_name(ahc)); 6486 fmt1_ins->opcode = AIC_OP_AND; 6487 fmt1_ins->immediate = 0xff; 6488 } 6489 /* FALLTHROUGH */ 6490 case AIC_OP_ROL: 6491 if ((ahc->features & AHC_ULTRA2) != 0) { 6492 int i, count; 6493 6494 /* Calculate odd parity for the instruction */ 6495 for (i = 0, count = 0; i < 31; i++) { 6496 uint32_t mask; 6497 6498 mask = 0x01 << i; 6499 if ((instr.integer & mask) != 0) 6500 count++; 6501 } 6502 if ((count & 0x01) == 0) 6503 instr.format1.parity = 1; 6504 } else { 6505 /* Compress the instruction for older sequencers */ 6506 if (fmt3_ins != NULL) { 6507 instr.integer = 6508 fmt3_ins->immediate 6509 | (fmt3_ins->source << 8) 6510 | (fmt3_ins->address << 16) 6511 | (fmt3_ins->opcode << 25); 6512 } else { 6513 instr.integer = 6514 fmt1_ins->immediate 6515 | (fmt1_ins->source << 8) 6516 | (fmt1_ins->destination << 16) 6517 | (fmt1_ins->ret << 24) 6518 | (fmt1_ins->opcode << 25); 6519 } 6520 } 6521 /* The sequencer is a little endian CPU */ 6522 instr.integer = ahc_htole32(instr.integer); 6523 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6524 break; 6525 default: 6526 panic("Unknown opcode encountered in seq program"); 6527 break; 6528 } 6529 } 6530 6531 int 6532 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6533 const char *name, u_int address, u_int value, 6534 u_int *cur_column, u_int wrap_point) 6535 { 6536 int printed; 6537 u_int printed_mask; 6538 char line[1024]; 6539 6540 line[0] = 0; 6541 6542 if (cur_column != NULL && *cur_column >= wrap_point) { 6543 printf("\n"); 6544 *cur_column = 0; 6545 } 6546 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value); 6547 if (table == NULL) { 6548 printed += snprintf(&line[printed], (sizeof line) - printed, 6549 " "); 6550 printf("%s", line); 6551 if (cur_column != NULL) 6552 *cur_column += printed; 6553 return (printed); 6554 } 6555 printed_mask = 0; 6556 while (printed_mask != 0xFF) { 6557 int entry; 6558 6559 for (entry = 0; entry < num_entries; entry++) { 6560 if (((value & table[entry].mask) 6561 != table[entry].value) 6562 || ((printed_mask & table[entry].mask) 6563 == table[entry].mask)) 6564 continue; 6565 printed += snprintf(&line[printed], 6566 (sizeof line) - printed, "%s%s", 6567 printed_mask == 0 ? ":(" : "|", 6568 table[entry].name); 6569 printed_mask |= table[entry].mask; 6570 6571 break; 6572 } 6573 if (entry >= num_entries) 6574 break; 6575 } 6576 if (printed_mask != 0) 6577 printed += snprintf(&line[printed], 6578 (sizeof line) - printed, ") "); 6579 else 6580 printed += snprintf(&line[printed], 6581 (sizeof line) - printed, " "); 6582 if (cur_column != NULL) 6583 *cur_column += printed; 6584 printf("%s", line); 6585 6586 return (printed); 6587 } 6588 6589 void 6590 ahc_dump_card_state(struct ahc_softc *ahc) 6591 { 6592 struct scb *scb; 6593 struct scb_tailq *untagged_q; 6594 u_int cur_col; 6595 int paused; 6596 int target; 6597 int maxtarget; 6598 int i; 6599 uint8_t last_phase; 6600 uint8_t qinpos; 6601 uint8_t qintail; 6602 uint8_t qoutpos; 6603 uint8_t scb_index; 6604 uint8_t saved_scbptr; 6605 6606 if (ahc_is_paused(ahc)) { 6607 paused = 1; 6608 } else { 6609 paused = 0; 6610 ahc_pause(ahc); 6611 } 6612 6613 saved_scbptr = ahc_inb(ahc, SCBPTR); 6614 last_phase = ahc_inb(ahc, LASTPHASE); 6615 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6616 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6617 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6618 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6619 if (paused) 6620 printf("Card was paused\n"); 6621 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6622 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6623 ahc_inb(ahc, ARG_2)); 6624 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6625 ahc_inb(ahc, SCBPTR)); 6626 cur_col = 0; 6627 if ((ahc->features & AHC_DT) != 0) 6628 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6629 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6630 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6631 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6632 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6633 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6634 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6635 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6636 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6637 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6638 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6639 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6640 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6641 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6642 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6643 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6644 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6645 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6646 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6647 if (cur_col != 0) 6648 printf("\n"); 6649 printf("STACK:"); 6650 for (i = 0; i < STACK_SIZE; i++) 6651 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6652 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6653 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6654 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6655 /* QINFIFO */ 6656 printf("QINFIFO entries: "); 6657 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6658 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6659 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6660 } else 6661 qinpos = ahc_inb(ahc, QINPOS); 6662 qintail = ahc->qinfifonext; 6663 while (qinpos != qintail) { 6664 printf("%d ", ahc->qinfifo[qinpos]); 6665 qinpos++; 6666 } 6667 printf("\n"); 6668 6669 printf("Waiting Queue entries: "); 6670 scb_index = ahc_inb(ahc, WAITING_SCBH); 6671 i = 0; 6672 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6673 ahc_outb(ahc, SCBPTR, scb_index); 6674 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6675 scb_index = ahc_inb(ahc, SCB_NEXT); 6676 } 6677 printf("\n"); 6678 6679 printf("Disconnected Queue entries: "); 6680 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6681 i = 0; 6682 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6683 ahc_outb(ahc, SCBPTR, scb_index); 6684 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6685 scb_index = ahc_inb(ahc, SCB_NEXT); 6686 } 6687 printf("\n"); 6688 6689 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6690 printf("QOUTFIFO entries: "); 6691 qoutpos = ahc->qoutfifonext; 6692 i = 0; 6693 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6694 printf("%d ", ahc->qoutfifo[qoutpos]); 6695 qoutpos++; 6696 } 6697 printf("\n"); 6698 6699 printf("Sequencer Free SCB List: "); 6700 scb_index = ahc_inb(ahc, FREE_SCBH); 6701 i = 0; 6702 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6703 ahc_outb(ahc, SCBPTR, scb_index); 6704 printf("%d ", scb_index); 6705 scb_index = ahc_inb(ahc, SCB_NEXT); 6706 } 6707 printf("\n"); 6708 6709 printf("Sequencer SCB Info: "); 6710 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6711 ahc_outb(ahc, SCBPTR, i); 6712 /*cur_col =*/ printf("\n%3d ", i); 6713 6714 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6715 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6716 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6717 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6718 } 6719 printf("\n"); 6720 6721 printf("Pending list: "); 6722 i = 0; 6723 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6724 if (i++ > 256) 6725 break; 6726 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6727 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6728 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6729 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6730 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6731 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6732 printf("("); 6733 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6734 &cur_col, 60); 6735 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6736 printf(")"); 6737 } 6738 } 6739 printf("\n"); 6740 6741 printf("Kernel Free SCB list: "); 6742 i = 0; 6743 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6744 if (i++ > 256) 6745 break; 6746 printf("%d ", scb->hscb->tag); 6747 } 6748 printf("\n"); 6749 6750 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6751 for (target = 0; target <= maxtarget; target++) { 6752 untagged_q = &ahc->untagged_queues[target]; 6753 if (TAILQ_FIRST(untagged_q) == NULL) 6754 continue; 6755 printf("Untagged Q(%d): ", target); 6756 i = 0; 6757 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6758 if (i++ > 256) 6759 break; 6760 printf("%d ", scb->hscb->tag); 6761 } 6762 printf("\n"); 6763 } 6764 6765 ahc_platform_dump_card_state(ahc); 6766 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6767 ahc_outb(ahc, SCBPTR, saved_scbptr); 6768 if (paused == 0) 6769 ahc_unpause(ahc); 6770 } 6771 6772 /************************* Target Mode ****************************************/ 6773 #ifdef AHC_TARGET_MODE 6774 cam_status 6775 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6776 struct ahc_tmode_tstate **tstate, 6777 struct ahc_tmode_lstate **lstate, 6778 int notfound_failure) 6779 { 6780 6781 if ((ahc->features & AHC_TARGETMODE) == 0) 6782 return (CAM_REQ_INVALID); 6783 6784 /* 6785 * Handle the 'black hole' device that sucks up 6786 * requests to unattached luns on enabled targets. 6787 */ 6788 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6789 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6790 *tstate = NULL; 6791 *lstate = ahc->black_hole; 6792 } else { 6793 u_int max_id; 6794 6795 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6796 if (ccb->ccb_h.target_id > max_id) 6797 return (CAM_TID_INVALID); 6798 6799 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6800 return (CAM_LUN_INVALID); 6801 6802 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6803 *lstate = NULL; 6804 if (*tstate != NULL) 6805 *lstate = 6806 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6807 } 6808 6809 if (notfound_failure != 0 && *lstate == NULL) 6810 return (CAM_PATH_INVALID); 6811 6812 return (CAM_REQ_CMP); 6813 } 6814 6815 void 6816 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6817 { 6818 struct ahc_tmode_tstate *tstate; 6819 struct ahc_tmode_lstate *lstate; 6820 struct ccb_en_lun *cel; 6821 cam_status status; 6822 u_int target; 6823 u_int lun; 6824 u_int target_mask; 6825 u_int our_id; 6826 u_long s; 6827 char channel; 6828 6829 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6830 /*notfound_failure*/FALSE); 6831 6832 if (status != CAM_REQ_CMP) { 6833 ccb->ccb_h.status = status; 6834 return; 6835 } 6836 6837 if (cam_sim_bus(sim) == 0) 6838 our_id = ahc->our_id; 6839 else 6840 our_id = ahc->our_id_b; 6841 6842 if (ccb->ccb_h.target_id != our_id) { 6843 /* 6844 * our_id represents our initiator ID, or 6845 * the ID of the first target to have an 6846 * enabled lun in target mode. There are 6847 * two cases that may preclude enabling a 6848 * target id other than our_id. 6849 * 6850 * o our_id is for an active initiator role. 6851 * Since the hardware does not support 6852 * reselections to the initiator role at 6853 * anything other than our_id, and our_id 6854 * is used by the hardware to indicate the 6855 * ID to use for both select-out and 6856 * reselect-out operations, the only target 6857 * ID we can support in this mode is our_id. 6858 * 6859 * o The MULTARGID feature is not available and 6860 * a previous target mode ID has been enabled. 6861 */ 6862 if ((ahc->features & AHC_MULTIROLE) != 0) { 6863 6864 if ((ahc->features & AHC_MULTI_TID) != 0 6865 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6866 /* 6867 * Only allow additional targets if 6868 * the initiator role is disabled. 6869 * The hardware cannot handle a re-select-in 6870 * on the initiator id during a re-select-out 6871 * on a different target id. 6872 */ 6873 status = CAM_TID_INVALID; 6874 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6875 || ahc->enabled_luns > 0) { 6876 /* 6877 * Only allow our target id to change 6878 * if the initiator role is not configured 6879 * and there are no enabled luns which 6880 * are attached to the currently registered 6881 * scsi id. 6882 */ 6883 status = CAM_TID_INVALID; 6884 } 6885 } else if ((ahc->features & AHC_MULTI_TID) == 0 6886 && ahc->enabled_luns > 0) { 6887 6888 status = CAM_TID_INVALID; 6889 } 6890 } 6891 6892 if (status != CAM_REQ_CMP) { 6893 ccb->ccb_h.status = status; 6894 return; 6895 } 6896 6897 /* 6898 * We now have an id that is valid. 6899 * If we aren't in target mode, switch modes. 6900 */ 6901 if ((ahc->flags & AHC_TARGETROLE) == 0 6902 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6903 u_long s; 6904 6905 printf("Configuring Target Mode\n"); 6906 ahc_lock(ahc, &s); 6907 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6908 ccb->ccb_h.status = CAM_BUSY; 6909 ahc_unlock(ahc, &s); 6910 return; 6911 } 6912 ahc->flags |= AHC_TARGETROLE; 6913 if ((ahc->features & AHC_MULTIROLE) == 0) 6914 ahc->flags &= ~AHC_INITIATORROLE; 6915 ahc_pause(ahc); 6916 ahc_loadseq(ahc); 6917 ahc_unlock(ahc, &s); 6918 } 6919 cel = &ccb->cel; 6920 target = ccb->ccb_h.target_id; 6921 lun = ccb->ccb_h.target_lun; 6922 channel = SIM_CHANNEL(ahc, sim); 6923 target_mask = 0x01 << target; 6924 if (channel == 'B') 6925 target_mask <<= 8; 6926 6927 if (cel->enable != 0) { 6928 u_int scsiseq; 6929 6930 /* Are we already enabled?? */ 6931 if (lstate != NULL) { 6932 xpt_print_path(ccb->ccb_h.path); 6933 printf("Lun already enabled\n"); 6934 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6935 return; 6936 } 6937 6938 if (cel->grp6_len != 0 6939 || cel->grp7_len != 0) { 6940 /* 6941 * Don't (yet?) support vendor 6942 * specific commands. 6943 */ 6944 ccb->ccb_h.status = CAM_REQ_INVALID; 6945 printf("Non-zero Group Codes\n"); 6946 return; 6947 } 6948 6949 /* 6950 * Seems to be okay. 6951 * Setup our data structures. 6952 */ 6953 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6954 tstate = ahc_alloc_tstate(ahc, target, channel); 6955 if (tstate == NULL) { 6956 xpt_print_path(ccb->ccb_h.path); 6957 printf("Couldn't allocate tstate\n"); 6958 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6959 return; 6960 } 6961 } 6962 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6963 if (lstate == NULL) { 6964 xpt_print_path(ccb->ccb_h.path); 6965 printf("Couldn't allocate lstate\n"); 6966 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6967 return; 6968 } 6969 memset(lstate, 0, sizeof(*lstate)); 6970 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6971 xpt_path_path_id(ccb->ccb_h.path), 6972 xpt_path_target_id(ccb->ccb_h.path), 6973 xpt_path_lun_id(ccb->ccb_h.path)); 6974 if (status != CAM_REQ_CMP) { 6975 free(lstate, M_DEVBUF); 6976 xpt_print_path(ccb->ccb_h.path); 6977 printf("Couldn't allocate path\n"); 6978 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6979 return; 6980 } 6981 SLIST_INIT(&lstate->accept_tios); 6982 SLIST_INIT(&lstate->immed_notifies); 6983 ahc_lock(ahc, &s); 6984 ahc_pause(ahc); 6985 if (target != CAM_TARGET_WILDCARD) { 6986 tstate->enabled_luns[lun] = lstate; 6987 ahc->enabled_luns++; 6988 6989 if ((ahc->features & AHC_MULTI_TID) != 0) { 6990 u_int targid_mask; 6991 6992 targid_mask = ahc_inb(ahc, TARGID) 6993 | (ahc_inb(ahc, TARGID + 1) << 8); 6994 6995 targid_mask |= target_mask; 6996 ahc_outb(ahc, TARGID, targid_mask); 6997 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6998 6999 ahc_update_scsiid(ahc, targid_mask); 7000 } else { 7001 u_int our_id; 7002 char channel; 7003 7004 channel = SIM_CHANNEL(ahc, sim); 7005 our_id = SIM_SCSI_ID(ahc, sim); 7006 7007 /* 7008 * This can only happen if selections 7009 * are not enabled 7010 */ 7011 if (target != our_id) { 7012 u_int sblkctl; 7013 char cur_channel; 7014 int swap; 7015 7016 sblkctl = ahc_inb(ahc, SBLKCTL); 7017 cur_channel = (sblkctl & SELBUSB) 7018 ? 'B' : 'A'; 7019 if ((ahc->features & AHC_TWIN) == 0) 7020 cur_channel = 'A'; 7021 swap = cur_channel != channel; 7022 if (channel == 'A') 7023 ahc->our_id = target; 7024 else 7025 ahc->our_id_b = target; 7026 7027 if (swap) 7028 ahc_outb(ahc, SBLKCTL, 7029 sblkctl ^ SELBUSB); 7030 7031 ahc_outb(ahc, SCSIID, target); 7032 7033 if (swap) 7034 ahc_outb(ahc, SBLKCTL, sblkctl); 7035 } 7036 } 7037 } else 7038 ahc->black_hole = lstate; 7039 /* Allow select-in operations */ 7040 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7041 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7042 scsiseq |= ENSELI; 7043 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7044 scsiseq = ahc_inb(ahc, SCSISEQ); 7045 scsiseq |= ENSELI; 7046 ahc_outb(ahc, SCSISEQ, scsiseq); 7047 } 7048 ahc_unpause(ahc); 7049 ahc_unlock(ahc, &s); 7050 ccb->ccb_h.status = CAM_REQ_CMP; 7051 xpt_print_path(ccb->ccb_h.path); 7052 printf("Lun now enabled for target mode\n"); 7053 } else { 7054 struct scb *scb; 7055 int i, empty; 7056 7057 if (lstate == NULL) { 7058 ccb->ccb_h.status = CAM_LUN_INVALID; 7059 return; 7060 } 7061 7062 ahc_lock(ahc, &s); 7063 7064 ccb->ccb_h.status = CAM_REQ_CMP; 7065 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7066 struct ccb_hdr *ccbh; 7067 7068 ccbh = &scb->io_ctx->ccb_h; 7069 if (ccbh->func_code == XPT_CONT_TARGET_IO 7070 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7071 printf("CTIO pending\n"); 7072 ccb->ccb_h.status = CAM_REQ_INVALID; 7073 ahc_unlock(ahc, &s); 7074 return; 7075 } 7076 } 7077 7078 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7079 printf("ATIOs pending\n"); 7080 ccb->ccb_h.status = CAM_REQ_INVALID; 7081 } 7082 7083 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7084 printf("INOTs pending\n"); 7085 ccb->ccb_h.status = CAM_REQ_INVALID; 7086 } 7087 7088 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7089 ahc_unlock(ahc, &s); 7090 return; 7091 } 7092 7093 xpt_print_path(ccb->ccb_h.path); 7094 printf("Target mode disabled\n"); 7095 xpt_free_path(lstate->path); 7096 free(lstate, M_DEVBUF); 7097 7098 ahc_pause(ahc); 7099 /* Can we clean up the target too? */ 7100 if (target != CAM_TARGET_WILDCARD) { 7101 tstate->enabled_luns[lun] = NULL; 7102 ahc->enabled_luns--; 7103 for (empty = 1, i = 0; i < 8; i++) 7104 if (tstate->enabled_luns[i] != NULL) { 7105 empty = 0; 7106 break; 7107 } 7108 7109 if (empty) { 7110 ahc_free_tstate(ahc, target, channel, 7111 /*force*/FALSE); 7112 if (ahc->features & AHC_MULTI_TID) { 7113 u_int targid_mask; 7114 7115 targid_mask = ahc_inb(ahc, TARGID) 7116 | (ahc_inb(ahc, TARGID + 1) 7117 << 8); 7118 7119 targid_mask &= ~target_mask; 7120 ahc_outb(ahc, TARGID, targid_mask); 7121 ahc_outb(ahc, TARGID+1, 7122 (targid_mask >> 8)); 7123 ahc_update_scsiid(ahc, targid_mask); 7124 } 7125 } 7126 } else { 7127 7128 ahc->black_hole = NULL; 7129 7130 /* 7131 * We can't allow selections without 7132 * our black hole device. 7133 */ 7134 empty = TRUE; 7135 } 7136 if (ahc->enabled_luns == 0) { 7137 /* Disallow select-in */ 7138 u_int scsiseq; 7139 7140 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7141 scsiseq &= ~ENSELI; 7142 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7143 scsiseq = ahc_inb(ahc, SCSISEQ); 7144 scsiseq &= ~ENSELI; 7145 ahc_outb(ahc, SCSISEQ, scsiseq); 7146 7147 if ((ahc->features & AHC_MULTIROLE) == 0) { 7148 printf("Configuring Initiator Mode\n"); 7149 ahc->flags &= ~AHC_TARGETROLE; 7150 ahc->flags |= AHC_INITIATORROLE; 7151 ahc_pause(ahc); 7152 ahc_loadseq(ahc); 7153 } 7154 } 7155 ahc_unpause(ahc); 7156 ahc_unlock(ahc, &s); 7157 } 7158 } 7159 7160 static void 7161 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7162 { 7163 u_int scsiid_mask; 7164 u_int scsiid; 7165 7166 if ((ahc->features & AHC_MULTI_TID) == 0) 7167 panic("ahc_update_scsiid called on non-multitid unit\n"); 7168 7169 /* 7170 * Since we will rely on the TARGID mask 7171 * for selection enables, ensure that OID 7172 * in SCSIID is not set to some other ID 7173 * that we don't want to allow selections on. 7174 */ 7175 if ((ahc->features & AHC_ULTRA2) != 0) 7176 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7177 else 7178 scsiid = ahc_inb(ahc, SCSIID); 7179 scsiid_mask = 0x1 << (scsiid & OID); 7180 if ((targid_mask & scsiid_mask) == 0) { 7181 u_int our_id; 7182 7183 /* ffs counts from 1 */ 7184 our_id = ffs(targid_mask); 7185 if (our_id == 0) 7186 our_id = ahc->our_id; 7187 else 7188 our_id--; 7189 scsiid &= TID; 7190 scsiid |= our_id; 7191 } 7192 if ((ahc->features & AHC_ULTRA2) != 0) 7193 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7194 else 7195 ahc_outb(ahc, SCSIID, scsiid); 7196 } 7197 7198 void 7199 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7200 { 7201 struct target_cmd *cmd; 7202 7203 /* 7204 * If the card supports auto-access pause, 7205 * we can access the card directly regardless 7206 * of whether it is paused or not. 7207 */ 7208 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7209 paused = TRUE; 7210 7211 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7212 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7213 7214 /* 7215 * Only advance through the queue if we 7216 * have the resources to process the command. 7217 */ 7218 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7219 break; 7220 7221 cmd->cmd_valid = 0; 7222 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7223 ahc->shared_data_dmamap, 7224 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7225 sizeof(struct target_cmd), 7226 BUS_DMASYNC_PREREAD); 7227 ahc->tqinfifonext++; 7228 7229 /* 7230 * Lazily update our position in the target mode incoming 7231 * command queue as seen by the sequencer. 7232 */ 7233 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7234 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7235 u_int hs_mailbox; 7236 7237 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7238 hs_mailbox &= ~HOST_TQINPOS; 7239 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7240 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7241 } else { 7242 if (!paused) 7243 ahc_pause(ahc); 7244 ahc_outb(ahc, KERNEL_TQINPOS, 7245 ahc->tqinfifonext & HOST_TQINPOS); 7246 if (!paused) 7247 ahc_unpause(ahc); 7248 } 7249 } 7250 } 7251 } 7252 7253 static int 7254 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7255 { 7256 struct ahc_tmode_tstate *tstate; 7257 struct ahc_tmode_lstate *lstate; 7258 struct ccb_accept_tio *atio; 7259 uint8_t *byte; 7260 int initiator; 7261 int target; 7262 int lun; 7263 7264 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7265 target = SCSIID_OUR_ID(cmd->scsiid); 7266 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7267 7268 byte = cmd->bytes; 7269 tstate = ahc->enabled_targets[target]; 7270 lstate = NULL; 7271 if (tstate != NULL) 7272 lstate = tstate->enabled_luns[lun]; 7273 7274 /* 7275 * Commands for disabled luns go to the black hole driver. 7276 */ 7277 if (lstate == NULL) 7278 lstate = ahc->black_hole; 7279 7280 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7281 if (atio == NULL) { 7282 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7283 /* 7284 * Wait for more ATIOs from the peripheral driver for this lun. 7285 */ 7286 if (bootverbose) 7287 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7288 return (1); 7289 } else 7290 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7291 #if 0 7292 printf("Incoming command from %d for %d:%d%s\n", 7293 initiator, target, lun, 7294 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7295 #endif 7296 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7297 7298 if (lstate == ahc->black_hole) { 7299 /* Fill in the wildcards */ 7300 atio->ccb_h.target_id = target; 7301 atio->ccb_h.target_lun = lun; 7302 } 7303 7304 /* 7305 * Package it up and send it off to 7306 * whomever has this lun enabled. 7307 */ 7308 atio->sense_len = 0; 7309 atio->init_id = initiator; 7310 if (byte[0] != 0xFF) { 7311 /* Tag was included */ 7312 atio->tag_action = *byte++; 7313 atio->tag_id = *byte++; 7314 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7315 } else { 7316 atio->ccb_h.flags = 0; 7317 } 7318 byte++; 7319 7320 /* Okay. Now determine the cdb size based on the command code */ 7321 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7322 case 0: 7323 atio->cdb_len = 6; 7324 break; 7325 case 1: 7326 case 2: 7327 atio->cdb_len = 10; 7328 break; 7329 case 4: 7330 atio->cdb_len = 16; 7331 break; 7332 case 5: 7333 atio->cdb_len = 12; 7334 break; 7335 case 3: 7336 default: 7337 /* Only copy the opcode. */ 7338 atio->cdb_len = 1; 7339 printf("Reserved or VU command code type encountered\n"); 7340 break; 7341 } 7342 7343 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7344 7345 atio->ccb_h.status |= CAM_CDB_RECVD; 7346 7347 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7348 /* 7349 * We weren't allowed to disconnect. 7350 * We're hanging on the bus until a 7351 * continue target I/O comes in response 7352 * to this accept tio. 7353 */ 7354 #if 0 7355 printf("Received Immediate Command %d:%d:%d - %p\n", 7356 initiator, target, lun, ahc->pending_device); 7357 #endif 7358 ahc->pending_device = lstate; 7359 ahc_freeze_ccb((union ccb *)atio); 7360 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7361 } 7362 xpt_done((union ccb*)atio); 7363 return (0); 7364 } 7365 #endif 7366 7367 static int 7368 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 7369 bus_dma_tag_t tag; 7370 int size; 7371 int flags; 7372 bus_dmamap_t *mapp; 7373 caddr_t *vaddr; 7374 bus_addr_t *baddr; 7375 bus_dma_segment_t *seg; 7376 int *nseg; 7377 const char *myname, *what; 7378 { 7379 int error, level = 0; 7380 7381 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7382 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7383 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7384 myname, what, error); 7385 goto out; 7386 } 7387 level++; 7388 7389 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7390 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7391 printf("%s: failed to map DMA mem for %s, error = %d\n", 7392 myname, what, error); 7393 goto out; 7394 } 7395 level++; 7396 7397 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7398 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7399 printf("%s: failed to create DMA map for %s, error = %d\n", 7400 myname, what, error); 7401 goto out; 7402 } 7403 level++; 7404 7405 7406 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7407 BUS_DMA_NOWAIT)) != 0) { 7408 printf("%s: failed to load DMA map for %s, error = %d\n", 7409 myname, what, error); 7410 goto out; 7411 } 7412 7413 *baddr = (*mapp)->dm_segs[0].ds_addr; 7414 7415 return 0; 7416 out: 7417 printf("ahc_createdmamem error (%d)\n", level); 7418 switch (level) { 7419 case 3: 7420 bus_dmamap_destroy(tag, *mapp); 7421 /* FALLTHROUGH */ 7422 case 2: 7423 bus_dmamem_unmap(tag, *vaddr, size); 7424 /* FALLTHROUGH */ 7425 case 1: 7426 bus_dmamem_free(tag, seg, *nseg); 7427 break; 7428 default: 7429 break; 7430 } 7431 7432 return error; 7433 } 7434 7435 static void 7436 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 7437 bus_dma_tag_t tag; 7438 int size; 7439 bus_dmamap_t map; 7440 caddr_t vaddr; 7441 bus_dma_segment_t *seg; 7442 int nseg; 7443 { 7444 7445 bus_dmamap_unload(tag, map); 7446 bus_dmamap_destroy(tag, map); 7447 bus_dmamem_unmap(tag, vaddr, size); 7448 bus_dmamem_free(tag, seg, nseg); 7449 } 7450
Indexes created Tue Sep 30 17:09:57 GMT 2025