aic7xxx.c revision 1.4
1 /* $NetBSD: aic7xxx.c,v 1.4 1996/03/28 22:39:08 mycroft Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Copyright (c) 1994, 1995 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Product specific probe and attach routines can be found in: 9 * i386/isa/aic7770.c 27/284X and aic7770 motherboard controllers 10 * /pci/aic7870.c 294x and aic7870 motherboard controllers 11 * 12 * Portions of this driver are based on the FreeBSD 1742 Driver: 13 * 14 * Written by Julian Elischer (julian (at) tfs.com) 15 * for TRW Financial Systems for use under the MACH(2.5) operating system. 16 * 17 * TRW Financial Systems, in accordance with their agreement with Carnegie 18 * Mellon University, makes this software available to CMU to distribute 19 * or use in any manner that they see fit as long as this message is kept with 20 * the software. For this reason TFS also grants any other persons or 21 * organisations permission to use or modify this software. 22 * 23 * TFS supplies this software to be publicly redistributed 24 * on the understanding that TFS is not responsible for the correct 25 * functioning of this software in any circumstances. 26 * 27 * commenced: Sun Sep 27 18:14:01 PDT 1992 28 */ 29 /* 30 * TODO: 31 * Add target reset capabilities 32 * Implement Target Mode 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/proc.h> 43 #include <sys/user.h> 44 45 #include <machine/pio.h> 46 47 #include <scsi/scsi_all.h> 48 #include <scsi/scsi_debug.h> 49 #include <scsi/scsiconf.h> 50 51 #include <dev/ic/aic7xxxvar.h> 52 53 int ahc_init __P((struct ahc_softc *)); 54 void ahc_loadseq __P((int)); 55 int ahc_scsi_cmd __P((struct scsi_xfer *)); 56 void ahc_timeout __P((void *)); 57 void ahc_done __P((struct ahc_softc *, struct ahc_scb *)); 58 struct ahc_scb *ahc_get_scb __P((struct ahc_softc *, int)); 59 void ahc_free_scb __P((struct ahc_softc *, struct ahc_scb *, int)); 60 void ahc_abort_scb __P((struct ahc_softc *, struct ahc_scb *)); 61 void ahcminphys __P((struct buf *)); 62 int ahc_poll __P((struct ahc_softc *, struct scsi_xfer *, int)); 63 64 /* Different debugging levels */ 65 #define AHC_SHOWMISC 0x0001 66 #define AHC_SHOWCMDS 0x0002 67 #define AHC_SHOWSCBS 0x0004 68 /*#define AHC_DEBUG /**/ 69 int ahc_debug = AHC_SHOWMISC; 70 71 /*#define AHC_MORE_DEBUG /**/ 72 73 #ifdef AHC_MORE_DEBUG 74 #define DEBUGLEVEL -1 75 #define DEBUGTARGET 0x0 76 #endif 77 78 /**** bit definitions for SCSIDEF ****/ 79 #define HSCSIID 0x07 /* our SCSI ID */ 80 #define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 81 82 struct scsi_adapter ahc_switch = { 83 ahc_scsi_cmd, 84 ahcminphys, 85 0, 86 0, 87 }; 88 89 90 /* the below structure is so we have a default dev struct for our link struct */ 91 struct scsi_device ahc_dev = { 92 NULL, /* Use default error handler */ 93 NULL, /* have a queue, served by this */ 94 NULL, /* have no async handler */ 95 NULL, /* Use default 'done' routine */ 96 }; 97 98 99 /* 100 * All of these should be in a separate header file shared by the sequencer 101 * code and the kernel level driver. The only catch is that we would need to 102 * add an additional 0xc00 offset when using them in the kernel driver. The 103 * aic7770 assembler must be modified to allow include files as well. All 104 * page numbers refer to the Adaptec AIC-7770 Data Book available from 105 * Adaptec's Technical Documents Department 1-800-934-2766 106 */ 107 108 /* -------------------- AIC-7770 offset definitions ----------------------- */ 109 110 /* 111 * SCSI Sequence Control (p. 3-11). 112 * Each bit, when set starts a specific SCSI sequence on the bus 113 */ 114 #define SCSISEQ 0xc00ul 115 #define TEMODEO 0x80 116 #define ENSELO 0x40 117 #define ENSELI 0x20 118 #define ENRSELI 0x10 119 #define ENAUTOATNO 0x08 120 #define ENAUTOATNI 0x04 121 #define ENAUTOATNP 0x02 122 #define SCSIRSTO 0x01 123 124 /* 125 * SCSI Transfer Control 1 Register (pp. 3-14,15). 126 * Controls the SCSI module data path. 127 */ 128 #define SXFRCTL1 0xc02ul 129 #define BITBUCKET 0x80 130 #define SWRAPEN 0x40 131 #define ENSPCHK 0x20 132 #define STIMESEL 0x18 133 #define ENSTIMER 0x04 134 #define ACTNEGEN 0x02 135 #define STPWEN 0x01 /* Powered Termination */ 136 137 /* 138 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 139 * Set bits in this register enable the corresponding 140 * interrupt source. 141 */ 142 #define SIMODE1 0xc11ul 143 #define ENSELTIMO 0x80 144 #define ENATNTARG 0x40 145 #define ENSCSIRST 0x20 146 #define ENPHASEMIS 0x10 147 #define ENBUSFREE 0x08 148 #define ENSCSIPERR 0x04 149 #define ENPHASECHG 0x02 150 #define ENREQINIT 0x01 151 152 /* 153 * SCSI Control Signal Read Register (p. 3-15). 154 * Reads the actual state of the SCSI bus pins 155 */ 156 #define SCSISIGI 0xc03ul 157 #define CDI 0x80 158 #define IOI 0x40 159 #define MSGI 0x20 160 #define ATNI 0x10 161 #define SELI 0x08 162 #define BSYI 0x04 163 #define REQI 0x02 164 #define ACKI 0x01 165 166 /* 167 * SCSI Contol Signal Write Register (p. 3-16). 168 * Writing to this register modifies the control signals on the bus. Only 169 * those signals that are allowed in the current mode (Initiator/Target) are 170 * asserted. 171 */ 172 #define SCSISIGO 0xc03ul 173 #define CDO 0x80 174 #define IOO 0x40 175 #define MSGO 0x20 176 #define ATNO 0x10 177 #define SELO 0x08 178 #define BSYO 0x04 179 #define REQO 0x02 180 #define ACKO 0x01 181 182 /* XXX document this thing */ 183 #define SCSIRATE 0xc04ul 184 185 /* 186 * SCSI ID (p. 3-18). 187 * Contains the ID of the board and the current target on the 188 * selected channel 189 */ 190 #define SCSIID 0xc05ul 191 #define TID 0xf0 /* Target ID mask */ 192 #define OID 0x0f /* Our ID mask */ 193 194 /* 195 * SCSI Status 0 (p. 3-21) 196 * Contains one set of SCSI Interrupt codes 197 * These are most likely of interest to the sequencer 198 */ 199 #define SSTAT0 0xc0bul 200 #define TARGET 0x80 /* Board is a target */ 201 #define SELDO 0x40 /* Selection Done */ 202 #define SELDI 0x20 /* Board has been selected */ 203 #define SELINGO 0x10 /* Selection In Progress */ 204 #define SWRAP 0x08 /* 24bit counter wrap */ 205 #define SDONE 0x04 /* STCNT = 0x000000 */ 206 #define SPIORDY 0x02 /* SCSI PIO Ready */ 207 #define DMADONE 0x01 /* DMA transfer completed */ 208 209 /* 210 * Clear SCSI Interrupt 1 (p. 3-23) 211 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 212 */ 213 #define CLRSINT1 0xc0cul 214 #define CLRSELTIMEO 0x80 215 #define CLRATNO 0x40 216 #define CLRSCSIRSTI 0x20 217 /* UNUSED 0x10 */ 218 #define CLRBUSFREE 0x08 219 #define CLRSCSIPERR 0x04 220 #define CLRPHASECHG 0x02 221 #define CLRREQINIT 0x01 222 223 /* 224 * SCSI Status 1 (p. 3-24) 225 * These interrupt bits are of interest to the kernel driver 226 */ 227 #define SSTAT1 0xc0cul 228 #define SELTO 0x80 229 #define ATNTARG 0x40 230 #define SCSIRSTI 0x20 231 #define PHASEMIS 0x10 232 #define BUSFREE 0x08 233 #define SCSIPERR 0x04 234 #define PHASECHG 0x02 235 #define REQINIT 0x01 236 237 /* 238 * Selection/Reselection ID (p. 3-31) 239 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 240 * device did not set its own ID. 241 */ 242 #define SELID 0xc19ul 243 #define SELID_MASK 0xf0 244 #define ONEBIT 0x08 245 /* UNUSED 0x07 */ 246 247 /* 248 * SCSI Block Control (p. 3-32) 249 * Controls Bus type and channel selection. In a twin channel configuration 250 * addresses 0x00-0x1e are gated to the appropriate channel based on this 251 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 252 * on a wide bus. 253 */ 254 #define SBLKCTL 0xc1ful 255 /* UNUSED 0xc0 */ 256 #define AUTOFLUSHDIS 0x20 257 /* UNUSED 0x10 */ 258 #define SELBUSB 0x08 259 /* UNUSED 0x04 */ 260 #define SELWIDE 0x02 261 /* UNUSED 0x01 */ 262 263 /* 264 * Sequencer Control (p. 3-33) 265 * Error detection mode and speed configuration 266 */ 267 #define SEQCTL 0xc60ul 268 #define PERRORDIS 0x80 269 #define PAUSEDIS 0x40 270 #define FAILDIS 0x20 271 #define FASTMODE 0x10 272 #define BRKADRINTEN 0x08 273 #define STEP 0x04 274 #define SEQRESET 0x02 275 #define LOADRAM 0x01 276 277 /* 278 * Sequencer RAM Data (p. 3-34) 279 * Single byte window into the Scratch Ram area starting at the address 280 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 281 * four bytes in sucessesion. The SEQADDRs will increment after the most 282 * significant byte is written 283 */ 284 #define SEQRAM 0xc61ul 285 286 /* 287 * Sequencer Address Registers (p. 3-35) 288 * Only the first bit of SEQADDR1 holds addressing information 289 */ 290 #define SEQADDR0 0xc62ul 291 #define SEQADDR1 0xc63ul 292 #define SEQADDR1_MASK 0x01 293 294 /* 295 * Accumulator 296 * We cheat by passing arguments in the Accumulator up to the kernel driver 297 */ 298 #define ACCUM 0xc64ul 299 300 #define SINDEX 0xc65ul 301 302 /* 303 * Board Control (p. 3-43) 304 */ 305 #define BCTL 0xc84ul 306 /* RSVD 0xf0 */ 307 #define ACE 0x08 /* Support for external processors */ 308 /* RSVD 0x06 */ 309 #define ENABLE 0x01 310 311 /* 312 * Host Control (p. 3-47) R/W 313 * Overal host control of the device. 314 */ 315 #define HCNTRL 0xc87ul 316 /* UNUSED 0x80 */ 317 #define POWRDN 0x40 318 /* UNUSED 0x20 */ 319 #define SWINT 0x10 320 #define IRQMS 0x08 321 #define PAUSE 0x04 322 #define INTEN 0x02 323 #define CHIPRST 0x01 324 325 /* 326 * SCB Pointer (p. 3-49) 327 * Gate one of the four SCBs into the SCBARRAY window. 328 */ 329 #define SCBPTR 0xc90ul 330 331 /* 332 * Interrupt Status (p. 3-50) 333 * Status for system interrupts 334 */ 335 #define INTSTAT 0xc91ul 336 #define SEQINT_MASK 0xf0 /* SEQINT Status Codes */ 337 #define BAD_PHASE 0x00 338 #define SEND_REJECT 0x10 339 #define NO_IDENT 0x20 340 #define NO_MATCH 0x30 341 #define MSG_SDTR 0x40 342 #define MSG_WDTR 0x50 343 #define MSG_REJECT 0x60 344 #define BAD_STATUS 0x70 345 #define RESIDUAL 0x80 346 #define ABORT_TAG 0x90 347 #define BRKADRINT 0x08 348 #define SCSIINT 0x04 349 #define CMDCMPLT 0x02 350 #define SEQINT 0x01 351 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 352 353 /* 354 * Hard Error (p. 3-53) 355 * Reporting of catastrophic errors. You usually cannot recover from 356 * these without a full board reset. 357 */ 358 #define ERROR 0xc92ul 359 /* UNUSED 0xf0 */ 360 #define PARERR 0x08 361 #define ILLOPCODE 0x04 362 #define ILLSADDR 0x02 363 #define ILLHADDR 0x01 364 365 /* 366 * Clear Interrupt Status (p. 3-52) 367 */ 368 #define CLRINT 0xc92ul 369 #define CLRBRKADRINT 0x08 370 #define CLRSCSIINT 0x04 371 #define CLRCMDINT 0x02 372 #define CLRSEQINT 0x01 373 374 /* 375 * SCB Auto Increment (p. 3-59) 376 * Byte offset into the SCB Array and an optional bit to allow auto 377 * incrementing of the address during download and upload operations 378 */ 379 #define SCBCNT 0xc9aul 380 #define SCBAUTO 0x80 381 #define SCBCNT_MASK 0x1f 382 383 /* 384 * Queue In FIFO (p. 3-60) 385 * Input queue for queued SCBs (commands that the seqencer has yet to start) 386 */ 387 #define QINFIFO 0xc9bul 388 389 /* 390 * Queue In Count (p. 3-60) 391 * Number of queued SCBs 392 */ 393 #define QINCNT 0xc9cul 394 395 /* 396 * Queue Out FIFO (p. 3-61) 397 * Queue of SCBs that have completed and await the host 398 */ 399 #define QOUTFIFO 0xc9dul 400 401 /* 402 * Queue Out Count (p. 3-61) 403 * Number of queued SCBs in the Out FIFO 404 */ 405 #define QOUTCNT 0xc9eul 406 407 #define SCBARRAY 0xca0ul 408 409 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 410 411 /* --------------------- AIC-7870-only definitions -------------------- */ 412 413 #define DSPCISTATUS 0xc86ul 414 415 /* ---------------------- Scratch RAM Offsets ------------------------- */ 416 /* These offsets are either to values that are initialized by the board's 417 * BIOS or are specified by the Linux sequencer code. If I can figure out 418 * how to read the EISA configuration info at probe time, the cards could 419 * be run without BIOS support installed 420 */ 421 422 /* 423 * 1 byte per target starting at this address for configuration values 424 */ 425 #define HA_TARG_SCRATCH 0xc20ul 426 427 /* 428 * The sequencer will stick the frist byte of any rejected message here so 429 * we can see what is getting thrown away. 430 */ 431 #define HA_REJBYTE 0xc31ul 432 433 /* 434 * Length of pending message 435 */ 436 #define HA_MSG_LEN 0xc34ul 437 438 /* 439 * message body 440 */ 441 #define HA_MSG_START 0xc35ul /* outgoing message body */ 442 443 /* 444 * These are offsets into the card's scratch ram. Some of the values are 445 * specified in the AHA2742 technical reference manual and are initialized 446 * by the BIOS at boot time. 447 */ 448 #define HA_ARG_1 0xc4aul 449 #define HA_RETURN_1 0xc4aul 450 #define SEND_SENSE 0x80 451 #define SEND_WDTR 0x80 452 #define SEND_SDTR 0x80 453 #define SEND_REJ 0x40 454 455 #define HA_SIGSTATE 0xc4bul 456 457 #define HA_SCBCOUNT 0xc52ul 458 #define HA_FLAGS 0xc53ul 459 #define SINGLE_BUS 0x00 460 #define TWIN_BUS 0x01 461 #define WIDE_BUS 0x02 462 #define ACTIVE_MSG 0x20 463 #define IDENTIFY_SEEN 0x40 464 #define RESELECTING 0x80 465 466 #define HA_ACTIVE0 0xc54ul 467 #define HA_ACTIVE1 0xc55ul 468 #define SAVED_TCL 0xc56ul 469 #define WAITING_SCBH 0xc57ul 470 #define WAITING_SCBT 0xc58ul 471 472 #define HA_SCSICONF 0xc5aul 473 #define INTDEF 0xc5cul 474 #define HA_HOSTCONF 0xc5dul 475 476 #define MSG_ABORT 0x06 477 #define BUS_8_BIT 0x00 478 #define BUS_16_BIT 0x01 479 #define BUS_32_BIT 0x02 480 481 /* 482 * Since the sequencer can disable pausing in a critical section, we 483 * must loop until it actually stops. 484 * XXX Should add a timeout in here?? 485 */ 486 #define PAUSE_SEQUENCER(ahc) \ 487 do { \ 488 outb(HCNTRL + ahc->sc_iobase, ahc->pause); \ 489 while ((inb(HCNTRL + ahc->sc_iobase) & PAUSE) == 0) \ 490 ; \ 491 } while (0) 492 493 #define UNPAUSE_SEQUENCER(ahc) \ 494 do { \ 495 outb(HCNTRL + ahc->sc_iobase, ahc->unpause); \ 496 } while (0) 497 498 /* 499 * Restart the sequencer program from address zero 500 * XXX Should add a timeout in here?? 501 */ 502 #define RESET_SEQUENCER(ahc) \ 503 do { \ 504 do { \ 505 outb(SEQCTL + ahc->sc_iobase, SEQRESET|FASTMODE); \ 506 } while (inb(SEQADDR0 + ahc->sc_iobase) != 0 && \ 507 inb(SEQADDR1 + ahc->sc_iobase) != 0); \ 508 } while (0) 509 510 #define RESTART_SEQUENCER(ahc) \ 511 do { \ 512 RESET_SEQUENCER(ahc); \ 513 UNPAUSE_SEQUENCER(ahc); \ 514 } while (0) 515 516 #ifdef AHC_DEBUG 517 void 518 ahc_print_scb(scb) 519 struct ahc_scb *scb; 520 { 521 522 printf("scb:0x%x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n", 523 scb, 524 scb->control, 525 scb->target_channel_lun, 526 scb->cmdlen, 527 scb->cmdpointer); 528 printf("\tdatlen:%d data:0x%x res:0x%x segs:0x%x segp:0x%x\n", 529 scb->datalen[2] << 16 | scb->datalen[1] << 8 | scb->datalen[0], 530 scb->data, 531 scb->RESERVED[1] << 8 | scb->RESERVED[0], 532 scb->SG_segment_count, 533 scb->SG_list_pointer); 534 printf("\tsg_addr:%x sg_len:%d\n", 535 scb->ahc_dma[0].seg_addr, 536 scb->ahc_dma[0].seg_len); 537 printf(" size:%d\n", 538 (int)&scb->next_waiting - (int)scb); 539 } 540 541 void 542 ahc_print_active_scb(ahc) 543 struct ahc_softc *ahc; 544 { 545 int iobase = ahc->sc_iobase; 546 int scb_index; 547 548 PAUSE_SEQUENCER(ahc); 549 scb_index = inb(SCBPTR + iobase); 550 UNPAUSE_SEQUENCER(ahc); 551 552 ahc_print_scb(ahc->scbarray[scb_index]); 553 } 554 #endif 555 556 #define PARERR 0x08 557 #define ILLOPCODE 0x04 558 #define ILLSADDR 0x02 559 #define ILLHADDR 0x01 560 561 static struct { 562 u_char errno; 563 char *errmesg; 564 } hard_error[] = { 565 { ILLHADDR, "Illegal Host Access" }, 566 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 567 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 568 { PARERR, "Sequencer Ram Parity Error" } 569 }; 570 571 572 /* 573 * Valid SCSIRATE values. (p. 3-17) 574 * Provides a mapping of tranfer periods in ns to the proper value to 575 * stick in the scsiscfr reg to use that transfer rate. 576 */ 577 static struct { 578 u_char sxfr; 579 int period; /* in ns */ 580 char *rate; 581 } ahc_syncrates[] = { 582 { 0x00, 100, "10.0" }, 583 { 0x10, 125, "8.0" }, 584 { 0x20, 150, "6.67" }, 585 { 0x30, 175, "5.7" }, 586 { 0x40, 200, "5.0" }, 587 { 0x50, 225, "4.4" }, 588 { 0x60, 250, "4.0" }, 589 { 0x70, 275, "3.6" } 590 }; 591 592 static int ahc_num_syncrates = 593 sizeof(ahc_syncrates) / sizeof(ahc_syncrates[0]); 594 595 /* 596 * Check if the device can be found at the port given 597 * and if so, determine configuration and set it up for further work. 598 */ 599 600 int 601 ahcprobe(ahc, iobase) 602 struct ahc_softc *ahc; 603 int iobase; 604 { 605 606 ahc->sc_iobase = iobase; 607 608 /* 609 * Try to initialize a unit at this location 610 * reset the AIC-7770, read its registers, 611 * and fill in the dev structure accordingly 612 */ 613 614 if (ahc_init(ahc) != 0) 615 return (0); 616 617 return (1); 618 } 619 620 621 /* 622 * Look up the valid period to SCSIRATE conversion in our table. 623 */ 624 static u_char 625 ahc_scsirate(offset, period, ahc, target) 626 u_char offset; 627 int period; 628 struct ahc_softc *ahc; 629 int target; 630 { 631 u_char scsirate; 632 int i; 633 634 for (i = 0; i < ahc_num_syncrates; i++) { 635 if ((ahc_syncrates[i].period - period) >= 0) { 636 printf("%s: target %d synchronous at %sMB/s, " 637 "offset = %d\n", 638 ahc->sc_dev.dv_xname, target, 639 ahc_syncrates[i].rate, offset); 640 #ifdef AHC_DEBUG 641 #endif /* AHC_DEBUG */ 642 return ((ahc_syncrates[i].sxfr) | (offset & 0x0f)); 643 } 644 } 645 646 /* Default to asyncronous transfers. Also reject this SDTR request. */ 647 printf("%s: target %d using asyncronous transfers\n", 648 ahc->sc_dev.dv_xname, target); 649 return (0); 650 #ifdef AHC_DEBUG 651 #endif /* AHC_DEBUG */ 652 } 653 654 int 655 ahcprint(aux, name) 656 void *aux; 657 char *name; 658 { 659 660 if (name != NULL) 661 printf("%s: scsibus ", name); 662 return UNCONF; 663 } 664 665 /* 666 * Attach all the sub-devices we can find 667 */ 668 int 669 ahcattach(ahc) 670 struct ahc_softc *ahc; 671 { 672 673 TAILQ_INIT(&ahc->free_scb); 674 675 /* 676 * fill in the prototype scsi_link. 677 */ 678 ahc->sc_link.adapter_softc = ahc; 679 ahc->sc_link.adapter_target = ahc->ahc_scsi_dev; 680 ahc->sc_link.adapter = &ahc_switch; 681 ahc->sc_link.device = &ahc_dev; 682 ahc->sc_link.openings = 1; 683 ahc->sc_link.flags = DEBUGLEVEL; 684 ahc->sc_link.quirks = 0; 685 686 /* 687 * ask the adapter what subunits are present 688 */ 689 printf("%s: Probing channel A\n", ahc->sc_dev.dv_xname); 690 config_found((void *)ahc, &ahc->sc_link, ahcprint); 691 if (ahc->type & AHC_TWIN) { 692 /* Configure the second scsi bus */ 693 ahc->sc_link_b = ahc->sc_link; 694 /* XXXX Didn't do this before. */ 695 ahc->sc_link_b.adapter_target = ahc->ahc_scsi_dev_b; 696 ahc->sc_link_b.quirks = 0x0008; /**/ 697 printf("%s: Probing channel B\n", ahc->sc_dev.dv_xname); 698 config_found((void *)ahc, &ahc->sc_link_b, ahcprint); 699 } 700 701 return 1; 702 } 703 704 void 705 ahc_send_scb(ahc, scb) 706 struct ahc_softc *ahc; 707 struct ahc_scb *scb; 708 { 709 int iobase = ahc->sc_iobase; 710 711 PAUSE_SEQUENCER(ahc); 712 outb(QINFIFO + iobase, scb->position); 713 UNPAUSE_SEQUENCER(ahc); 714 } 715 716 static void 717 ahc_getscb(iobase, scb) 718 int iobase; 719 struct ahc_scb *scb; 720 { 721 722 outb(SCBCNT + iobase, SCBAUTO); 723 insb(SCBARRAY + iobase, scb, SCB_UP_SIZE); 724 outb(SCBCNT + iobase, 0); 725 } 726 727 /* 728 * Catch an interrupt from the adaptor 729 */ 730 int 731 ahcintr(ahc) 732 struct ahc_softc *ahc; 733 { 734 int iobase = ahc->sc_iobase; 735 u_char intstat = inb(INTSTAT + iobase); 736 u_char status; 737 struct ahc_scb *scb = NULL; 738 struct scsi_xfer *xs = NULL; 739 740 /* 741 * Is this interrupt for me? or for 742 * someone who is sharing my interrupt 743 */ 744 if ((intstat & INT_PEND) == 0) 745 return 0; 746 747 if (intstat & BRKADRINT) { 748 /* We upset the sequencer :-( */ 749 750 /* Lookup the error message */ 751 int i, error = inb(ERROR + iobase); 752 int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 753 for (i = 0; error != 1 && i < num_errors; i++) 754 error >>= 1; 755 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 756 ahc->sc_dev.dv_xname, hard_error[i].errmesg, 757 (inb(SEQADDR1 + iobase) << 8) | 758 (inb(SEQADDR0 + iobase) << 0)); 759 } 760 761 if (intstat & SEQINT) { 762 switch (intstat & SEQINT_MASK) { 763 case BAD_PHASE: 764 panic("%s: unknown scsi bus phase. " 765 "Attempting to continue\n", 766 ahc->sc_dev.dv_xname); 767 break; 768 case SEND_REJECT: 769 printf("%s: Warning - " 770 "message reject, message type: 0x%x\n", 771 ahc->sc_dev.dv_xname, 772 inb(HA_REJBYTE + iobase)); 773 break; 774 case NO_IDENT: 775 panic("%s: No IDENTIFY message from reconnecting " 776 "target %d at seqaddr = 0x%lx " 777 "SAVED_TCL == 0x%x\n", 778 ahc->sc_dev.dv_xname, 779 (inb(SELID + iobase) >> 4) & 0xf, 780 (inb(SEQADDR1 + iobase) << 8) | 781 (inb(SEQADDR0 + iobase) << 0), 782 inb(SAVED_TCL + iobase)); 783 break; 784 case NO_MATCH: { 785 u_char active; 786 int active_port = HA_ACTIVE0 + iobase; 787 int tcl = inb(SCBARRAY+1 + iobase); 788 int target = (tcl >> 4) & 0x0f; 789 printf("%s: no active SCB for reconnecting " 790 "target %d, channel %c - issuing ABORT\n", 791 ahc->sc_dev.dv_xname, 792 target, tcl & 0x08 ? 'B' : 'A'); 793 printf("SAVED_TCL == 0x%x\n", inb(SAVED_TCL + iobase)); 794 if (tcl & 0x88) { 795 /* Second channel stores its info 796 * in byte two of HA_ACTIVE 797 */ 798 active_port++; 799 } 800 active = inb(active_port); 801 active &= ~(0x01 << (target & 0x07)); 802 outb(SCBARRAY + iobase, SCB_NEEDDMA); 803 outb(active_port, active); 804 outb(CLRSINT1 + iobase, CLRSELTIMEO); 805 RESTART_SEQUENCER(ahc); 806 break; 807 } 808 case MSG_SDTR: { 809 u_char scsi_id = 810 (inb(SCSIID + iobase) >> 0x4) | 811 (inb(SBLKCTL + iobase) & 0x08); 812 u_char scratch, offset; 813 int period; 814 815 /* 816 * Help the sequencer to translate the 817 * negotiated transfer rate. Transfer is 818 * 1/4 the period in ns as is returned by 819 * the sync negotiation message. So, we must 820 * multiply by four 821 */ 822 period = inb(HA_ARG_1 + iobase) << 2; 823 /* The bottom half of SCSIXFER */ 824 offset = inb(ACCUM + iobase); 825 826 printf("%s: SDTR, target %d period %d offset %d\n", 827 ahc->sc_dev.dv_xname, scsi_id, period, offset); 828 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 829 scratch &= 0x80; 830 scratch |= ahc_scsirate(offset, period, ahc, scsi_id); 831 832 if ((scratch & 0x7f) == 0) { 833 /* 834 * The requested rate was so low 835 * that asyncronous transfers are 836 * faster (not to mention the 837 * controller won't support them), 838 * so we issue a message reject to 839 * ensure we go to asyncronous 840 * transfers. 841 */ 842 outb(HA_RETURN_1 + iobase, SEND_REJ); 843 } else if (ahc->sdtrpending & (0x01 << scsi_id)) { 844 /* 845 * Don't send an SDTR back to the 846 * target, since we asked first. 847 */ 848 outb(HA_RETURN_1 + iobase, 0); 849 } else { 850 /* 851 * Send our own SDTR in reply 852 */ 853 #ifdef AHC_DEBUG 854 if (ahc_debug & AHC_SHOWMISC) 855 printf("Sending SDTR!!\n"); 856 #endif 857 outb(HA_RETURN_1 + iobase, SEND_SDTR); 858 } 859 /* 860 * Negate the flags 861 */ 862 ahc->needsdtr &= ~(0x01 << scsi_id); 863 ahc->sdtrpending &= ~(0x01 << scsi_id); 864 865 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 866 outb(SCSIRATE + iobase, scratch); 867 break; 868 } 869 case MSG_WDTR: { 870 u_char scsi_id = 871 (inb(SCSIID + iobase) >> 0x4) | 872 (inb(SBLKCTL + iobase) & 0x08); 873 u_char scratch, width; 874 875 width = inb(ACCUM + iobase); 876 877 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 878 879 if (ahc->wdtrpending & (0x01 << scsi_id)) { 880 /* 881 * Don't send a WDTR back to the 882 * target, since we asked first. 883 */ 884 outb(HA_RETURN_1 + iobase, 0); 885 switch (width) { 886 case BUS_8_BIT: 887 scratch &= 0x7f; 888 break; 889 case BUS_16_BIT: 890 printf("%s: target %d using 16Bit " 891 "transfers\n", 892 ahc->sc_dev.dv_xname, scsi_id); 893 scratch &= 0xf8; 894 scratch |= 0x88; 895 break; 896 case BUS_32_BIT: 897 /* XXXX */ 898 } 899 } else { 900 /* 901 * Send our own WDTR in reply 902 */ 903 switch (width) { 904 case BUS_8_BIT: 905 scratch &= 0x7f; 906 break; 907 case BUS_32_BIT: 908 /* Negotiate 16_BITS */ 909 width = BUS_16_BIT; 910 case BUS_16_BIT: 911 printf("%s: target %d using 16Bit " 912 "transfers\n", 913 ahc->sc_dev.dv_xname, scsi_id); 914 scratch &= 0xf8; 915 scratch |= 0x88; 916 break; 917 } 918 outb(HA_RETURN_1 + iobase, 919 width | SEND_WDTR); 920 } 921 ahc->needwdtr &= ~(0x01 << scsi_id); 922 ahc->wdtrpending &= ~(0x01 << scsi_id); 923 924 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 925 outb(SCSIRATE + iobase, scratch); 926 break; 927 } 928 case MSG_REJECT: { 929 /* 930 * What we care about here is if we had an 931 * outstanding SDTR or WDTR message for this 932 * target. If we did, this is a signal that 933 * the target is refusing negotiation. 934 */ 935 936 u_char scsi_id = 937 (inb(SCSIID + iobase) >> 0x4) | 938 (inb(SBLKCTL + iobase) & 0x08); 939 u_char scratch; 940 u_short mask; 941 942 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 943 944 mask = (0x01 << scsi_id); 945 if (ahc->wdtrpending & mask) { 946 /* note 8bit xfers and clear flag */ 947 scratch &= 0x7f; 948 ahc->needwdtr &= ~mask; 949 ahc->wdtrpending &= ~mask; 950 printf("%s: target %d refusing " 951 "WIDE negotiation. Using " 952 "8bit transfers\n", 953 ahc->sc_dev.dv_xname, scsi_id); 954 } else if (ahc->sdtrpending & mask) { 955 /* note asynch xfers and clear flag */ 956 scratch &= 0xf0; 957 ahc->needsdtr &= ~mask; 958 ahc->sdtrpending &= ~mask; 959 printf("%s: target %d refusing " 960 "syncronous negotiation; using " 961 "asyncronous transfers\n", 962 ahc->sc_dev.dv_xname, scsi_id); 963 } else { 964 /* 965 * Otherwise, we ignore it. 966 */ 967 #ifdef AHC_DEBUG 968 if (ahc_debug & AHC_SHOWMISC) 969 printf("Message reject -- ignored\n"); 970 #endif 971 break; 972 } 973 974 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 975 outb(SCSIRATE + iobase, scratch); 976 break; 977 } 978 case BAD_STATUS: { 979 int scb_index = inb(SCBPTR + iobase); 980 scb = ahc->scbarray[scb_index]; 981 982 /* 983 * The sequencer will notify us when a command 984 * has an error that would be of interest to 985 * the kernel. This allows us to leave the sequencer 986 * running in the common case of command completes 987 * without error. 988 */ 989 990 /* 991 * Set the default return value to 0 (don't 992 * send sense). The sense code with change 993 * this if needed and this reduces code 994 * duplication. 995 */ 996 outb(HA_RETURN_1 + iobase, 0); 997 if (!scb || scb->flags == SCB_FREE) { 998 printf("%s: ahcintr: referenced scb not " 999 "valid during seqint 0x%x scb(%d)\n", 1000 ahc->sc_dev.dv_xname, intstat, scb_index); 1001 goto clear; 1002 } 1003 1004 xs = scb->xs; 1005 1006 ahc_getscb(iobase, scb); 1007 1008 #ifdef AHC_MORE_DEBUG 1009 if (xs->sc_link->target == DEBUGTARGET) 1010 ahc_print_scb(scb); 1011 #endif 1012 xs->status = scb->target_status; 1013 switch (scb->target_status) { 1014 case SCSI_OK: 1015 printf("%s: Interrupted for status of 0???\n", 1016 ahc->sc_dev.dv_xname); 1017 break; 1018 case SCSI_CHECK: 1019 #ifdef AHC_DEBUG 1020 sc_print_addr(xs->sc_link); 1021 printf("requests Check Status\n"); 1022 #endif 1023 1024 if (xs->error == XS_NOERROR && 1025 scb->flags != SCB_CHKSENSE) { 1026 u_char flags; 1027 u_char head; 1028 u_char tail; 1029 struct ahc_dma_seg *sg = scb->ahc_dma; 1030 struct scsi_sense *sc = &(scb->sense_cmd); 1031 u_char control = scb->control; 1032 u_char tcl = scb->target_channel_lun; 1033 #ifdef AHC_DEBUG 1034 sc_print_addr(xs->sc_link); 1035 printf("Sending Sense\n"); 1036 #endif 1037 bzero(scb, SCB_DOWN_SIZE); 1038 scb->flags = SCB_CHKSENSE; 1039 scb->control = (control & SCB_TE); 1040 sc->opcode = REQUEST_SENSE; 1041 sc->byte2 = xs->sc_link->lun << 5; 1042 sc->length = sizeof(struct scsi_sense_data); 1043 sc->control = 0; 1044 1045 sg->seg_addr = vtophys(&xs->sense); 1046 sg->seg_len = sizeof(struct scsi_sense_data); 1047 1048 scb->target_channel_lun = tcl; 1049 scb->SG_segment_count = 1; 1050 scb->SG_list_pointer = vtophys(sg); 1051 scb->cmdpointer = vtophys(sc); 1052 scb->cmdlen = sizeof(*sc); 1053 1054 outb(SCBCNT + iobase, SCBAUTO); 1055 outsb(SCBARRAY + iobase, scb, 1056 SCB_DOWN_SIZE); 1057 outb(SCBCNT + iobase, 0); 1058 outb(SCBARRAY + iobase + 30, 1059 SCB_LIST_NULL); 1060 1061 /* 1062 * Add this SCB to the "waiting for 1063 * selection" list. 1064 */ 1065 head = inb(WAITING_SCBH + iobase); 1066 tail = inb(WAITING_SCBT + iobase); 1067 if (head & SCB_LIST_NULL) { 1068 /* List was empty */ 1069 head = scb->position; 1070 tail = SCB_LIST_NULL; 1071 } else if (tail & SCB_LIST_NULL) { 1072 /* List had one element */ 1073 tail = scb->position; 1074 outb(SCBPTR + iobase, head); 1075 outb(SCBARRAY + iobase + 30, 1076 tail); 1077 } else { 1078 outb(SCBPTR + iobase, tail); 1079 tail = scb->position; 1080 outb(SCBARRAY + iobase + 30, 1081 tail); 1082 } 1083 outb(WAITING_SCBH + iobase, head); 1084 outb(WAITING_SCBT + iobase, tail); 1085 outb(HA_RETURN_1 + iobase, SEND_SENSE); 1086 break; 1087 } 1088 /* 1089 * Have the sequencer do a normal command 1090 * complete with either a "DRIVER_STUFFUP" 1091 * error or whatever other error condition 1092 * we already had. 1093 */ 1094 if (xs->error == XS_NOERROR) 1095 xs->error = XS_DRIVER_STUFFUP; 1096 break; 1097 case SCSI_BUSY: 1098 sc_print_addr(xs->sc_link); 1099 printf("Target Busy\n"); 1100 xs->error = XS_BUSY; 1101 break; 1102 #if 0 1103 case SCSI_QUEUE_FULL: 1104 /* 1105 * The upper level SCSI code will eventually 1106 * handle this properly. 1107 */ 1108 sc_print_addr(xs->sc_link); 1109 printf("Queue Full\n"); 1110 xs->error = XS_BUSY; 1111 break; 1112 #endif 1113 default: 1114 sc_print_addr(xs->sc_link); 1115 printf("unexpected targ_status: %x\n", 1116 scb->target_status); 1117 xs->error = XS_DRIVER_STUFFUP; 1118 break; 1119 } 1120 break; 1121 } 1122 case RESIDUAL: { 1123 int scb_index = inb(SCBPTR + iobase); 1124 scb = ahc->scbarray[scb_index]; 1125 1126 /* 1127 * Don't clobber valid resid info with 1128 * a resid coming from a check sense 1129 * operation. 1130 */ 1131 if (scb->flags != SCB_CHKSENSE) 1132 scb->xs->resid = 1133 (inb(iobase + SCBARRAY + 17) << 16) | 1134 (inb(iobase + SCBARRAY + 16) << 8) | 1135 (inb(iobase + SCBARRAY + 15) << 0); 1136 #ifdef AHC_MORE_DEBUG 1137 printf("ahc: Handled Residual\n"); 1138 #endif 1139 break; 1140 } 1141 case ABORT_TAG: { 1142 int scb_index = inb(SCBPTR + iobase); 1143 scb = ahc->scbarray[scb_index]; 1144 1145 /* 1146 * We didn't recieve a valid tag back from 1147 * the target on a reconnect. 1148 */ 1149 sc_print_addr(xs->sc_link); 1150 printf("invalid tag recieved on channel %c " 1151 "-- sending ABORT_TAG\n", 1152 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1153 scb->xs->error = XS_DRIVER_STUFFUP; 1154 untimeout(ahc_timeout, scb); 1155 ahc_done(ahc, scb); 1156 break; 1157 } 1158 default: 1159 printf("%s: seqint, intstat == 0x%x, scsisigi = 0x%x\n", 1160 ahc->sc_dev.dv_xname, 1161 intstat, inb(SCSISIGI + iobase)); 1162 break; 1163 } 1164 1165 clear: 1166 /* 1167 * Clear the upper byte that holds SEQINT status 1168 * codes and clear the SEQINT bit. 1169 */ 1170 outb(CLRINT + iobase, CLRSEQINT); 1171 1172 /* 1173 * The sequencer is paused immediately on 1174 * a SEQINT, so we should restart it when 1175 * we leave this section. 1176 */ 1177 UNPAUSE_SEQUENCER(ahc); 1178 } 1179 1180 if (intstat & SCSIINT) { 1181 int scb_index = inb(SCBPTR + iobase); 1182 scb = ahc->scbarray[scb_index]; 1183 1184 status = inb(SSTAT1 + iobase); 1185 1186 if (!scb || scb->flags == SCB_FREE) { 1187 printf("%s: ahcintr - referenced scb not " 1188 "valid during scsiint 0x%x scb(%d)\n", 1189 ahc->sc_dev.dv_xname, status, scb_index); 1190 outb(CLRSINT1 + iobase, status); 1191 UNPAUSE_SEQUENCER(ahc); 1192 outb(CLRINT + iobase, CLRSCSIINT); 1193 scb = NULL; 1194 goto cmdcomplete; 1195 } 1196 xs = scb->xs; 1197 1198 #ifdef AHC_MORE_DEBUG 1199 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) 1200 printf("Intr status %x\n", status); 1201 #endif 1202 1203 if (status & SELTO) { 1204 u_char active; 1205 u_char waiting; 1206 u_char flags; 1207 int active_port = HA_ACTIVE0 + iobase; 1208 1209 outb(SCSISEQ + iobase, ENRSELI); 1210 xs->error = XS_SELTIMEOUT; 1211 /* 1212 * Clear any pending messages for the timed out 1213 * target, and mark the target as free 1214 */ 1215 flags = inb(HA_FLAGS + iobase); 1216 outb(HA_FLAGS + iobase, flags & ~ACTIVE_MSG); 1217 1218 if (scb->target_channel_lun & 0x88) 1219 active_port++; 1220 1221 active = inb(active_port) & 1222 ~(0x01 << (xs->sc_link->target & 0x07)); 1223 outb(active_port, active); 1224 1225 outb(SCBARRAY + iobase, SCB_NEEDDMA); 1226 1227 outb(CLRSINT1 + iobase, CLRSELTIMEO); 1228 1229 outb(CLRINT + iobase, CLRSCSIINT); 1230 1231 /* Shift the waiting for selection queue forward */ 1232 waiting = inb(WAITING_SCBH + iobase); 1233 outb(SCBPTR + iobase, waiting); 1234 waiting = inb(SCBARRAY + iobase + 30); 1235 outb(WAITING_SCBH + iobase, waiting); 1236 1237 RESTART_SEQUENCER(ahc); 1238 } 1239 1240 if (status & SCSIPERR) { 1241 sc_print_addr(xs->sc_link); 1242 printf("parity error on channel %c\n", 1243 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1244 xs->error = XS_DRIVER_STUFFUP; 1245 1246 outb(CLRSINT1 + iobase, CLRSCSIPERR); 1247 UNPAUSE_SEQUENCER(ahc); 1248 1249 outb(CLRINT + iobase, CLRSCSIINT); 1250 scb = NULL; 1251 } 1252 if (status & BUSFREE) { 1253 #if 0 1254 /* 1255 * Has seen busfree since selection, i.e. 1256 * a "spurious" selection. Shouldn't happen. 1257 */ 1258 printf("ahc: unexpected busfree\n"); 1259 #if 0 1260 xs->error = XS_DRIVER_STUFFUP; 1261 outb(CLRSINT1 + iobase, BUSFREE); /* CLRBUSFREE */ 1262 #endif 1263 #endif 1264 } else { 1265 printf("%s: Unknown SCSIINT. Status = 0x%x\n", 1266 ahc->sc_dev.dv_xname, status); 1267 outb(CLRSINT1 + iobase, status); 1268 UNPAUSE_SEQUENCER(ahc); 1269 outb(CLRINT + iobase, CLRSCSIINT); 1270 scb = NULL; 1271 } 1272 if (scb != NULL) { 1273 /* We want to process the command */ 1274 untimeout(ahc_timeout, scb); 1275 ahc_done(ahc, scb); 1276 } 1277 } 1278 1279 cmdcomplete: 1280 if (intstat & CMDCMPLT) { 1281 int scb_index; 1282 1283 do { 1284 scb_index = inb(QOUTFIFO + iobase); 1285 scb = ahc->scbarray[scb_index]; 1286 1287 if (!scb || scb->flags == SCB_FREE) { 1288 printf("%s: WARNING " 1289 "no command for scb %d (cmdcmplt)\n" 1290 "QOUTCNT == %d\n", 1291 ahc->sc_dev.dv_xname, 1292 scb_index, inb(QOUTCNT + iobase)); 1293 outb(CLRINT + iobase, CLRCMDINT); 1294 continue; 1295 } 1296 1297 /* XXXX Should do this before reading FIFO? */ 1298 outb(CLRINT + iobase, CLRCMDINT); 1299 untimeout(ahc_timeout, scb); 1300 ahc_done(ahc, scb); 1301 } while (inb(QOUTCNT + iobase)); 1302 } 1303 1304 return 1; 1305 } 1306 1307 /* 1308 * We have a scb which has been processed by the 1309 * adaptor, now we look to see how the operation 1310 * went. 1311 */ 1312 void 1313 ahc_done(ahc, scb) 1314 struct ahc_softc *ahc; 1315 struct ahc_scb *scb; 1316 { 1317 struct scsi_xfer *xs = scb->xs; 1318 1319 #ifdef AHC_MORE_DEBUG 1320 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) { 1321 xs->sc_link->flags |= 0xf0; 1322 SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); 1323 printf("%x %x %x %x\n", 1324 scb->flags, 1325 scb->target_status, 1326 xs->flags, 1327 xs->error); 1328 } 1329 #endif 1330 1331 /* 1332 * Put the results of the operation 1333 * into the xfer and call whoever started it 1334 */ 1335 if (xs->error == XS_NOERROR) { 1336 if (scb->flags == SCB_ABORTED) 1337 xs->error = XS_DRIVER_STUFFUP; 1338 else if (scb->flags == SCB_CHKSENSE) 1339 xs->error = XS_SENSE; 1340 } 1341 1342 xs->flags |= ITSDONE; 1343 1344 #ifdef AHC_TAGENABLE 1345 if (xs->cmd->opcode == 0x12 && xs->error == XS_NOERROR) { 1346 struct scsi_inquiry_data *inq_data; 1347 u_short mask = 0x01 << (xs->sc_link->target | 1348 (scb->target_channel_lun & 0x08)); 1349 /* 1350 * Sneak a look at the results of the SCSI Inquiry 1351 * command and see if we can do Tagged queing. XXX This 1352 * should really be done by the higher level drivers. 1353 */ 1354 inq_data = (struct scsi_inquiry_data *)xs->data; 1355 if (((inq_data->device & SID_TYPE) == 0) 1356 && (inq_data->flags & SID_CmdQue) 1357 && !(ahc->tagenable & mask)) { 1358 /* 1359 * Disk type device and can tag 1360 */ 1361 sc_print_addr(xs->sc_link); 1362 printf("Tagged Queuing Device\n"); 1363 ahc->tagenable |= mask; 1364 #ifdef QUEUE_FULL_SUPPORTED 1365 xs->sc_link->openings += 2; */ 1366 #endif 1367 } 1368 } 1369 #endif 1370 1371 ahc_free_scb(ahc, scb, xs->flags); 1372 scsi_done(xs); 1373 } 1374 1375 /* 1376 * Start the board, ready for normal operation 1377 */ 1378 /* XXXX clean */ 1379 int 1380 ahc_init(ahc) 1381 struct ahc_softc *ahc; 1382 { 1383 int iobase = ahc->sc_iobase; 1384 u_char scsi_conf, sblkctl, i; 1385 int intdef, max_targ = 16, wait; 1386 1387 /* 1388 * Assume we have a board at this stage 1389 * Find out the configured interupt and the card type. 1390 */ 1391 1392 #ifdef AHC_DEBUG 1393 printf("%s: scb %d bytes; SCB_SIZE %d bytes, ahc_dma %d bytes\n", 1394 ahc->sc_dev.dv_xname, sizeof(struct ahc_scb), SCB_DOWN_SIZE, 1395 sizeof(struct ahc_dma_seg)); 1396 #endif /* AHC_DEBUG */ 1397 /*printf("%s: reading board settings\n", ahc->sc_dev.dv_xname);/**/ 1398 1399 /* Save the IRQ type before we do a chip reset */ 1400 1401 ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN; 1402 ahc->pause = ahc->unpause | PAUSE; 1403 outb(HCNTRL + iobase, CHIPRST | ahc->pause); 1404 1405 /* 1406 * Ensure that the reset has finished 1407 */ 1408 wait = 1000; 1409 while (wait--) { 1410 delay(1000); 1411 if (!(inb(HCNTRL + iobase) & CHIPRST)) 1412 break; 1413 } 1414 if (wait == 0) { 1415 printf("\n%s: WARNING - Failed chip reset! " 1416 "Trying to initialize anyway.\n", ahc->sc_dev.dv_xname); 1417 /* Forcibly clear CHIPRST */ 1418 outb(HCNTRL + iobase, ahc->pause); 1419 } 1420 1421 switch (ahc->type) { 1422 case AHC_274: 1423 printf("%s: 274x ", ahc->sc_dev.dv_xname); 1424 ahc->maxscbs = 0x4; 1425 break; 1426 case AHC_284: 1427 printf("%s: 284x ", ahc->sc_dev.dv_xname); 1428 ahc->maxscbs = 0x4; 1429 break; 1430 case AHC_AIC7870: 1431 case AHC_294: 1432 if (ahc->type == AHC_AIC7870) 1433 printf("%s: aic7870 ", ahc->sc_dev.dv_xname); 1434 else 1435 printf("%s: 294x ", ahc->sc_dev.dv_xname); 1436 ahc->maxscbs = 0x10; 1437 #define DFTHRESH 3 1438 outb(DSPCISTATUS + iobase, DFTHRESH << 6); 1439 /* 1440 * XXX Hard coded SCSI ID until we can read it from the 1441 * SEEPROM or NVRAM. 1442 */ 1443 outb(HA_SCSICONF + iobase, 0x07 | (DFTHRESH << 6)); 1444 /* In case we are a wide card */ 1445 outb(HA_SCSICONF + 1 + iobase, 0x07); 1446 break; 1447 default: 1448 printf("%s: unknown(0x%x) ", ahc->sc_dev.dv_xname, ahc->type); 1449 break; 1450 } 1451 1452 /* Determine channel configuration and who we are on the scsi bus. */ 1453 switch ((sblkctl = inb(SBLKCTL + iobase) & 0x0f)) { 1454 case 0: 1455 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1456 printf("Single Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1457 outb(HA_FLAGS + iobase, SINGLE_BUS); 1458 break; 1459 case 2: 1460 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + 1 + iobase) & HWSCSIID); 1461 printf("Wide Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1462 ahc->type |= AHC_WIDE; 1463 outb(HA_FLAGS + iobase, WIDE_BUS); 1464 break; 1465 case 8: 1466 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1467 ahc->ahc_scsi_dev_b = (inb(HA_SCSICONF + 1 + iobase) & HSCSIID); 1468 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ", 1469 ahc->ahc_scsi_dev, ahc->ahc_scsi_dev_b); 1470 ahc->type |= AHC_TWIN; 1471 outb(HA_FLAGS + iobase, TWIN_BUS); 1472 break; 1473 default: 1474 printf(" Unsupported adapter type. %x Ignoring\n", sblkctl); 1475 return(-1); 1476 } 1477 1478 /* 1479 * Take the bus led out of diagnostic mode 1480 */ 1481 outb(SBLKCTL + iobase, sblkctl); 1482 1483 /* 1484 * Number of SCBs that will be used. Rev E aic7770s and 1485 * aic7870s have 16. The rest have 4. 1486 */ 1487 if (!(ahc->type & AHC_AIC7870)) { 1488 /* 1489 * See if we have a Rev E or higher 1490 * aic7770. Anything below a Rev E will 1491 * have a R/O autoflush disable configuration 1492 * bit. 1493 */ 1494 u_char sblkctl_orig; 1495 sblkctl_orig = inb(SBLKCTL + iobase); 1496 sblkctl = sblkctl_orig ^ AUTOFLUSHDIS; 1497 outb(SBLKCTL + iobase, sblkctl); 1498 sblkctl = inb(SBLKCTL + iobase); 1499 if (sblkctl != sblkctl_orig) { 1500 printf("aic7770 >= Rev E, "); 1501 /* 1502 * Ensure autoflush is enabled 1503 */ 1504 sblkctl &= ~AUTOFLUSHDIS; 1505 outb(SBLKCTL + iobase, sblkctl); 1506 } else 1507 printf("aic7770 <= Rev C, "); 1508 } else 1509 printf("aic7870, "); 1510 printf("%d SCBs\n", ahc->maxscbs); 1511 1512 if (ahc->pause & IRQMS) 1513 printf("%s: Using Level Sensitive Interrupts\n", 1514 ahc->sc_dev.dv_xname); 1515 else 1516 printf("%s: Using Edge Triggered Interrupts\n", 1517 ahc->sc_dev.dv_xname); 1518 1519 if (!(ahc->type & AHC_AIC7870)) { 1520 /* 1521 * The 294x cards are PCI, so we get their interrupt from the 1522 * PCI BIOS. 1523 */ 1524 1525 intdef = inb(INTDEF + iobase); 1526 switch (intdef & 0xf) { 1527 case 9: 1528 ahc->sc_irq = 9; 1529 break; 1530 case 10: 1531 ahc->sc_irq = 10; 1532 break; 1533 case 11: 1534 ahc->sc_irq = 11; 1535 break; 1536 case 12: 1537 ahc->sc_irq = 12; 1538 break; 1539 case 14: 1540 ahc->sc_irq = 14; 1541 break; 1542 case 15: 1543 ahc->sc_irq = 15; 1544 break; 1545 default: 1546 printf("illegal irq setting\n"); 1547 return (EIO); 1548 } 1549 } 1550 1551 /* Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels */ 1552 if (ahc->type & AHC_TWIN) { 1553 /* 1554 * The device is gated to channel B after a chip reset, 1555 * so set those values first 1556 */ 1557 outb(SCSIID + iobase, ahc->ahc_scsi_dev_b); 1558 scsi_conf = inb(HA_SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL); 1559 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1560 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1561 /* Select Channel A */ 1562 outb(SBLKCTL + iobase, 0); 1563 } 1564 outb(SCSIID + iobase, ahc->ahc_scsi_dev); 1565 scsi_conf = inb(HA_SCSICONF + iobase) & (ENSPCHK|STIMESEL); 1566 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1567 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1568 1569 /* 1570 * Look at the information that board initialization or 1571 * the board bios has left us. In the lower four bits of each 1572 * target's scratch space any value other than 0 indicates 1573 * that we should initiate syncronous transfers. If it's zero, 1574 * the user or the BIOS has decided to disable syncronous 1575 * negotiation to that target so we don't activate the needsdr 1576 * flag. 1577 */ 1578 ahc->needsdtr_orig = 0; 1579 ahc->needwdtr_orig = 0; 1580 if (!(ahc->type & AHC_WIDE)) 1581 max_targ = 8; 1582 1583 for (i = 0; i < max_targ; i++) { 1584 u_char target_settings = inb(HA_TARG_SCRATCH + i + iobase); 1585 #if 0 /* XXXX */ 1586 target_settings |= 0x8f; 1587 #endif 1588 if (target_settings & 0x0f) { 1589 ahc->needsdtr_orig |= (0x01 << i); 1590 /* Default to a asyncronous transfers (0 offset) */ 1591 target_settings &= 0xf0; 1592 } 1593 if (target_settings & 0x80) { 1594 ahc->needwdtr_orig |= (0x01 << i); 1595 /* 1596 * We'll set the Wide flag when we 1597 * are successful with Wide negotiation, 1598 * so turn it off for now so we aren't 1599 * confused. 1600 */ 1601 target_settings &= 0x7f; 1602 } 1603 outb(HA_TARG_SCRATCH + i + iobase, target_settings); 1604 } 1605 /* 1606 * If we are not a WIDE device, forget WDTR. This 1607 * makes the driver work on some cards that don't 1608 * leave these fields cleared when the BIOS is not 1609 * installed. 1610 */ 1611 if (!(ahc->type & AHC_WIDE)) 1612 ahc->needwdtr_orig = 0; 1613 ahc->needsdtr = ahc->needsdtr_orig; 1614 ahc->needwdtr = ahc->needwdtr_orig; 1615 ahc->sdtrpending = 0; 1616 ahc->wdtrpending = 0; 1617 ahc->tagenable = 0; 1618 1619 /* 1620 * Clear the control byte for every SCB so that the sequencer 1621 * doesn't get confused and think that one of them is valid 1622 */ 1623 for (i = 0; i < ahc->maxscbs; i++) { 1624 outb(SCBPTR + iobase, i); 1625 outb(SCBARRAY + iobase, 0); 1626 } 1627 1628 #ifdef AHC_DEBUG 1629 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n", ahc->needsdtr, 1630 ahc->needwdtr); 1631 #endif 1632 1633 /* 1634 * Set the number of availible SCBs 1635 */ 1636 outb(HA_SCBCOUNT + iobase, ahc->maxscbs); 1637 1638 /* We don't have any busy targets right now */ 1639 outb(HA_ACTIVE0 + iobase, 0); 1640 outb(HA_ACTIVE1 + iobase, 0); 1641 1642 /* We don't have any waiting selections */ 1643 outb(WAITING_SCBH + iobase, SCB_LIST_NULL); 1644 outb(WAITING_SCBT + iobase, SCB_LIST_NULL); 1645 /* 1646 * Load the Sequencer program and Enable the adapter. 1647 * Place the aic7770 in fastmode which makes a big 1648 * difference when doing many small block transfers. 1649 */ 1650 1651 printf("%s: Downloading Sequencer Program...", ahc->sc_dev.dv_xname); 1652 ahc_loadseq(iobase); 1653 printf("Done\n"); 1654 1655 if (!(ahc->type & AHC_AIC7870)) 1656 outb(BCTL + iobase, ENABLE); 1657 1658 /* Reset the bus */ 1659 outb(SCSISEQ + iobase, SCSIRSTO); 1660 delay(1000); 1661 outb(SCSISEQ + iobase, 0); 1662 1663 RESTART_SEQUENCER(ahc); 1664 1665 return (0); 1666 } 1667 1668 void 1669 ahcminphys(bp) 1670 struct buf *bp; 1671 { 1672 1673 if (bp->b_bcount > ((AHC_NSEG - 1) << PGSHIFT)) 1674 bp->b_bcount = ((AHC_NSEG - 1) << PGSHIFT); 1675 minphys(bp); 1676 } 1677 1678 /* 1679 * start a scsi operation given the command and 1680 * the data address, target, and lun all of which 1681 * are stored in the scsi_xfer struct 1682 */ 1683 int 1684 ahc_scsi_cmd(xs) 1685 struct scsi_xfer *xs; 1686 { 1687 struct scsi_link *sc_link = xs->sc_link; 1688 struct ahc_softc *ahc = sc_link->adapter_softc; 1689 struct ahc_scb *scb; 1690 struct ahc_dma_seg *sg; 1691 int seg; /* scatter gather seg being worked on */ 1692 u_long thiskv, thisphys, nextphys; 1693 int bytes_this_seg, bytes_this_page, datalen, flags; 1694 int s; 1695 u_short mask = (0x01 << (sc_link->target | (sc_link->quirks & 0x08))); 1696 1697 #ifdef AHC_MORE_DEBUG 1698 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1699 printf("ahc ahc_scsi_cmd for %x\n", sc_link->target); 1700 sc_link->flags = 0xf0; 1701 SC_DEBUG(sc_link, SDEV_DB2, ("ahc_scsi_cmd\n")); 1702 } 1703 #endif 1704 1705 /* 1706 * get a scb to use. If the transfer 1707 * is from a buf (possibly from interrupt time) 1708 * then we can't allow it to sleep 1709 */ 1710 flags = xs->flags; 1711 if ((flags & (ITSDONE|INUSE)) != INUSE) { 1712 printf("%s: done or not in use?\n", ahc->sc_dev.dv_xname); 1713 xs->flags &= ~ITSDONE; 1714 xs->flags |= INUSE; 1715 } 1716 if ((scb = ahc_get_scb(ahc, flags)) == NULL) { 1717 xs->error = XS_DRIVER_STUFFUP; 1718 return (TRY_AGAIN_LATER); 1719 } 1720 scb->xs = xs; 1721 1722 #ifdef AHC_MORE_DEBUG 1723 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1724 sc_link->flags = 0xf0; 1725 SC_DEBUG(sc_link, SDEV_DB3, ("start scb(%x)\n", scb)); 1726 } 1727 #endif 1728 1729 if (flags & SCSI_RESET) { 1730 /* XXX: Needs Implementation */ 1731 printf("ahc: SCSI_RESET called.\n"); 1732 } 1733 1734 /* 1735 * Put all the arguments for the xfer in the scb 1736 */ 1737 scb->control = 0; 1738 if (ahc->tagenable & mask) 1739 scb->control |= SCB_TE; 1740 if ((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask)) { 1741 scb->control |= SCB_NEEDWDTR; 1742 ahc->wdtrpending |= mask; 1743 } 1744 if ((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask)) { 1745 scb->control |= SCB_NEEDSDTR; 1746 ahc->sdtrpending |= mask; 1747 } 1748 scb->target_channel_lun = ((sc_link->target << 4) & 0xF0) | 1749 (sc_link->quirks & 0x08) | (sc_link->lun & 0x07); 1750 scb->cmdlen = xs->cmdlen; 1751 scb->cmdpointer = vtophys(xs->cmd); 1752 1753 xs->resid = 0; 1754 if (xs->datalen) { 1755 scb->SG_list_pointer = vtophys(scb->ahc_dma); 1756 sg = scb->ahc_dma; 1757 seg = 0; 1758 { 1759 /* 1760 * Set up the scatter gather block 1761 */ 1762 #ifdef AHC_MORE_DEBUG 1763 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1764 sc_link->flags = 0xf0; 1765 SC_DEBUG(sc_link, SDEV_DB4, 1766 ("%ld @%x:- ", xs->datalen, xs->data)); 1767 } 1768 #endif 1769 datalen = xs->datalen; 1770 thiskv = (long) xs->data; 1771 thisphys = vtophys(thiskv); 1772 1773 while (datalen && seg < AHC_NSEG) { 1774 bytes_this_seg = 0; 1775 1776 /* put in the base address */ 1777 sg->seg_addr = thisphys; 1778 1779 #ifdef AHC_MORE_DEBUG 1780 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1781 sc_link->flags = 0xf0; 1782 SC_DEBUGN(sc_link, SDEV_DB4, ("0x%lx", 1783 thisphys)); 1784 } 1785 #endif 1786 1787 /* do it at least once */ 1788 nextphys = thisphys; 1789 while (datalen && thisphys == nextphys) { 1790 /* 1791 * This page is contiguous (physically) 1792 * with the the last, just extend the 1793 * length 1794 */ 1795 /* how far to the end of the page */ 1796 nextphys = (thisphys & ~PGOFSET) + NBPG; 1797 bytes_this_page = nextphys - thisphys; 1798 /**** or the data ****/ 1799 bytes_this_page = min(bytes_this_page, 1800 datalen); 1801 bytes_this_seg += bytes_this_page; 1802 datalen -= bytes_this_page; 1803 1804 /* get more ready for the next page */ 1805 thiskv = (thiskv & ~PGOFSET) + NBPG; 1806 if (datalen) 1807 thisphys = vtophys(thiskv); 1808 } 1809 /* 1810 * next page isn't contiguous, finish the seg 1811 */ 1812 #ifdef AHC_MORE_DEBUG 1813 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1814 sc_link->flags = 0xf0; 1815 SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x)", 1816 bytes_this_seg)); 1817 } 1818 #endif 1819 sg->seg_len = bytes_this_seg; 1820 sg++; 1821 seg++; 1822 } 1823 } 1824 /*end of iov/kv decision */ 1825 scb->SG_segment_count = seg; 1826 #ifdef AHC_MORE_DEBUG 1827 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1828 sc_link->flags = 0xf0; 1829 SC_DEBUGN(sc_link, SDEV_DB4, ("\n")); 1830 } 1831 #endif 1832 if (datalen) { 1833 /* 1834 * there's still data, must have run out of segs! 1835 */ 1836 printf("%s: ahc_scsi_cmd: more than %d dma segs\n", 1837 ahc->sc_dev.dv_xname, AHC_NSEG); 1838 xs->error = XS_DRIVER_STUFFUP; 1839 ahc_free_scb(ahc, scb, flags); 1840 return (COMPLETE); 1841 } 1842 } else { 1843 scb->SG_list_pointer = (physaddr)0; 1844 scb->SG_segment_count = 0; 1845 } 1846 1847 #ifdef AHC_MORE_DEBUG 1848 if (sc_link->target == DEBUGTARGET) 1849 ahc_print_scb(scb); 1850 #endif 1851 1852 s = splbio(); 1853 1854 ahc_send_scb(ahc, scb); 1855 1856 /* 1857 * Usually return SUCCESSFULLY QUEUED 1858 */ 1859 if ((flags & SCSI_POLL) == 0) { 1860 timeout(ahc_timeout, scb, (xs->timeout * hz) / 1000); 1861 splx(s); 1862 #ifdef AHC_MORE_DEBUG 1863 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1864 sc_link->flags = 0xf0; 1865 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n")); 1866 } 1867 #endif 1868 return (SUCCESSFULLY_QUEUED); 1869 } 1870 1871 splx(s); 1872 1873 /* 1874 * If we can't use interrupts, poll on completion 1875 */ 1876 #ifdef AHC_MORE_DEBUG 1877 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1878 sc_link->flags = 0xf0; 1879 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_wait\n")); 1880 } 1881 #endif 1882 if (ahc_poll(ahc, xs, xs->timeout)) { 1883 ahc_timeout(scb); 1884 if (ahc_poll(ahc, xs, 2000)) 1885 ahc_timeout(scb); 1886 } 1887 return (COMPLETE); 1888 } 1889 1890 1891 /* 1892 * A scb (and hence an scb entry on the board is put onto the 1893 * free list. 1894 */ 1895 void 1896 ahc_free_scb(ahc, scb, flags) 1897 struct ahc_softc *ahc; 1898 struct ahc_scb *scb; 1899 int flags; 1900 { 1901 int s; 1902 1903 s = splbio(); 1904 1905 scb->flags = SCB_FREE; 1906 TAILQ_INSERT_TAIL(&ahc->free_scb, scb, chain); 1907 #ifdef AHC_DEBUG 1908 ahc->activescbs--; 1909 #endif 1910 1911 /* 1912 * If there were none, wake anybody waiting for one to come free, 1913 * starting with queued entries. 1914 */ 1915 if (scb->chain.tqe_next == 0) 1916 wakeup(&ahc->free_scb); 1917 1918 splx(s); 1919 } 1920 1921 /* XXXX check */ 1922 static inline void 1923 ahc_init_scb(ahc, scb) 1924 struct ahc_softc *ahc; 1925 struct ahc_scb *scb; 1926 { 1927 int iobase = ahc->sc_iobase; 1928 u_char scb_index; 1929 1930 bzero(scb, sizeof(struct ahc_scb)); 1931 scb->position = ahc->numscbs; 1932 /* 1933 * Place in the scbarray 1934 * Never is removed. Position 1935 * in ahc->scbarray is the scbarray 1936 * position on the board we will 1937 * load it into. 1938 */ 1939 ahc->scbarray[scb->position] = scb; 1940 1941 /* 1942 * Initialize the host memory location 1943 * of this SCB down on the board and 1944 * flag that it should be DMA's before 1945 * reference. Also set its psuedo 1946 * next pointer (for use in the psuedo 1947 * list of SCBs waiting for selection) 1948 * to SCB_LIST_NULL. 1949 */ 1950 scb->control = SCB_NEEDDMA; 1951 scb->host_scb = vtophys(scb); 1952 scb->next_waiting = SCB_LIST_NULL; 1953 PAUSE_SEQUENCER(ahc); 1954 scb_index = inb(SCBPTR + iobase); 1955 outb(SCBPTR + iobase, scb->position); 1956 outb(SCBCNT + iobase, SCBAUTO); 1957 outsb(SCBARRAY + iobase, scb, 31); 1958 outb(SCBCNT + iobase, 0); 1959 outb(SCBPTR + iobase, scb_index); 1960 UNPAUSE_SEQUENCER(ahc); 1961 scb->control = 0; 1962 } 1963 1964 static inline void 1965 ahc_reset_scb(ahc, scb) 1966 struct ahc_softc *ahc; 1967 struct ahc_scb *scb; 1968 { 1969 1970 bzero(scb, SCB_BZERO_SIZE); 1971 } 1972 1973 /* 1974 * Get a free scb 1975 * 1976 * If there are none, see if we can allocate a new one. 1977 */ 1978 struct ahc_scb * 1979 ahc_get_scb(ahc, flags) 1980 struct ahc_softc *ahc; 1981 int flags; 1982 { 1983 struct ahc_scb *scb; 1984 int s; 1985 1986 s = splbio(); 1987 1988 /* 1989 * If we can and have to, sleep waiting for one to come free 1990 * but only if we can't allocate a new one. 1991 */ 1992 for (;;) { 1993 scb = ahc->free_scb.tqh_first; 1994 if (scb) { 1995 TAILQ_REMOVE(&ahc->free_scb, scb, chain); 1996 break; 1997 } 1998 if (ahc->numscbs < ahc->maxscbs) { 1999 if (scb = (struct ahc_scb *) malloc(sizeof(struct ahc_scb), 2000 M_TEMP, M_NOWAIT)) { 2001 ahc_init_scb(ahc, scb); 2002 ahc->numscbs++; 2003 } else { 2004 printf("%s: can't malloc scb\n", 2005 ahc->sc_dev.dv_xname); 2006 goto out; 2007 } 2008 break; 2009 } 2010 if ((flags & SCSI_NOSLEEP) != 0) 2011 goto out; 2012 tsleep(&ahc->free_scb, PRIBIO, "ahcscb", 0); 2013 } 2014 2015 ahc_reset_scb(ahc, scb); 2016 scb->flags = SCB_ACTIVE; 2017 #ifdef AHC_DEBUG 2018 ahc->activescbs++; 2019 if (ahc->activescbs == ahc->maxscbs) 2020 printf("%s: Max SCBs active\n", ahc->sc_dev.dv_xname); 2021 #endif 2022 2023 out: 2024 splx(s); 2025 return (scb); 2026 } 2027 2028 /* XXXX check */ 2029 void 2030 ahc_loadseq(iobase) 2031 int iobase; 2032 { 2033 static u_char seqprog[] = { 2034 # include "aic7xxx_seq.h" 2035 }; 2036 2037 outb(SEQCTL + iobase, PERRORDIS|SEQRESET|LOADRAM); 2038 outsb(SEQRAM + iobase, seqprog, sizeof(seqprog)); 2039 outb(SEQCTL + iobase, FASTMODE|SEQRESET); 2040 } 2041 2042 /* 2043 * Function to poll for command completion when in poll mode 2044 */ 2045 int 2046 ahc_poll(ahc, xs, count) 2047 struct ahc_softc *ahc; 2048 struct scsi_xfer *xs; 2049 int count; 2050 { /* in msec */ 2051 int iobase = ahc->sc_iobase; 2052 int stport = INTSTAT + iobase; 2053 2054 while (count) { 2055 /* 2056 * If we had interrupts enabled, would we 2057 * have got an interrupt? 2058 */ 2059 if (inb(stport) & INT_PEND) 2060 ahcintr(ahc); 2061 if (xs->flags & ITSDONE) 2062 return 0; 2063 delay(1000); 2064 count--; 2065 } 2066 return 1; 2067 } 2068 2069 /* XXXX check */ 2070 void 2071 ahc_abort_scb(ahc, scb) 2072 struct ahc_softc *ahc; 2073 struct ahc_scb *scb; 2074 { 2075 int iobase = ahc->sc_iobase; 2076 int found = 0; 2077 int scb_index; 2078 u_char flags; 2079 u_char scb_control; 2080 2081 PAUSE_SEQUENCER(ahc); 2082 /* 2083 * Case 1: In the QINFIFO 2084 */ 2085 { 2086 int saved_queue[AHC_SCB_MAX]; 2087 int i; 2088 int queued = inb(QINCNT + iobase); 2089 2090 for (i = 0; i < (queued - found); i++) { 2091 saved_queue[i] = inb(QINFIFO + iobase); 2092 if (saved_queue[i] == scb->position) { 2093 i--; 2094 found = 1; 2095 } 2096 } 2097 /* Re-insert entries back into the queue */ 2098 for (queued = 0; queued < i; queued++) 2099 outb(QINFIFO + iobase, saved_queue[queued]); 2100 2101 if (found) 2102 goto done; 2103 } 2104 2105 scb_index = inb(SCBPTR + iobase); 2106 /* 2107 * Case 2: Not the active command 2108 */ 2109 if (scb_index != scb->position) { 2110 /* 2111 * Select the SCB we want to abort 2112 * and turn off the disconnected bit. 2113 * the driver will then abort the command 2114 * and notify us of the abort. 2115 */ 2116 outb(SCBPTR + iobase, scb->position); 2117 scb_control = inb(SCBARRAY + iobase); 2118 scb_control &= ~SCB_DIS; 2119 outb(SCBARRAY + iobase, scb_control); 2120 outb(SCBPTR + iobase, scb_index); 2121 goto done; 2122 } 2123 scb_control = inb(SCBARRAY + iobase); 2124 if (scb_control & SCB_DIS) { 2125 scb_control &= ~SCB_DIS; 2126 outb(SCBARRAY + iobase, scb_control); 2127 goto done; 2128 } 2129 /* 2130 * Case 3: Currently active command 2131 */ 2132 if ((flags = inb(HA_FLAGS + iobase)) & ACTIVE_MSG) { 2133 /* 2134 * If there's a message in progress, 2135 * reset the bus and have all devices renegotiate. 2136 */ 2137 if (scb->target_channel_lun & 0x08) { 2138 ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00); 2139 ahc->sdtrpending &= 0x00ff; 2140 outb(HA_ACTIVE1, 0); 2141 } else if (ahc->type & AHC_WIDE) { 2142 ahc->needsdtr = ahc->needsdtr_orig; 2143 ahc->needwdtr = ahc->needwdtr_orig; 2144 ahc->sdtrpending = 0; 2145 ahc->wdtrpending = 0; 2146 outb(HA_ACTIVE0, 0); 2147 outb(HA_ACTIVE1, 0); 2148 } else { 2149 ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff); 2150 ahc->sdtrpending &= 0xff00; 2151 outb(HA_ACTIVE0, 0); 2152 } 2153 2154 /* Reset the bus */ 2155 outb(SCSISEQ + iobase, SCSIRSTO); 2156 delay(1000); 2157 outb(SCSISEQ + iobase, 0); 2158 goto done; 2159 } 2160 2161 /* 2162 * Otherwise, set up an abort message and have the sequencer 2163 * clean up 2164 */ 2165 outb(HA_FLAGS + iobase, flags | ACTIVE_MSG); 2166 outb(HA_MSG_LEN + iobase, 1); 2167 outb(HA_MSG_START + iobase, MSG_ABORT); 2168 2169 outb(SCSISIGO + iobase, inb(HA_SIGSTATE + iobase) | 0x10); 2170 2171 done: 2172 scb->flags = SCB_ABORTED; 2173 UNPAUSE_SEQUENCER(ahc); 2174 ahc_done(ahc, scb); 2175 return; 2176 } 2177 2178 void 2179 ahc_timeout(arg) 2180 void *arg; 2181 { 2182 struct ahc_scb *scb = arg; 2183 struct scsi_xfer *xs = scb->xs; 2184 struct scsi_link *sc_link = xs->sc_link; 2185 struct ahc_softc *ahc = sc_link->adapter_softc; 2186 int s; 2187 2188 sc_print_addr(sc_link); 2189 printf("timed out"); 2190 2191 s = splbio(); 2192 2193 #ifdef SCSIDEBUG 2194 show_scsi_cmd(scb->xs); 2195 #endif 2196 #ifdef AHC_DEBUG 2197 if (ahc_debug & AHC_SHOWSCBS) 2198 ahc_print_active_scb(ahc); 2199 #endif /*AHC_DEBUG */ 2200 2201 if (scb->flags & SCB_IMMED) { 2202 printf("\n"); 2203 scb->xs->retries = 0; /* I MEAN IT ! */ 2204 scb->flags |= SCB_IMMED_FAIL; 2205 ahc_done(ahc, scb); 2206 splx(s); 2207 return; 2208 } 2209 2210 /* 2211 * If it has been through before, then 2212 * a previous abort has failed, don't 2213 * try abort again 2214 */ 2215 if (scb->flags == SCB_ABORTED) { 2216 /* abort timed out */ 2217 printf(" AGAIN\n"); 2218 scb->xs->retries = 0; /* I MEAN IT ! */ 2219 ahc_done(ahc, scb); 2220 } else { 2221 /* abort the operation that has timed out */ 2222 printf("\n"); 2223 scb->xs->error = XS_TIMEOUT; 2224 scb->flags = SCB_ABORTED; 2225 ahc_abort_scb(ahc, scb); 2226 /* 2 secs for the abort */ 2227 if ((xs->flags & SCSI_POLL) == 0) 2228 timeout(ahc_timeout, scb, 2 * hz); 2229 } 2230 2231 splx(s); 2232 } 2233
Indexes created Tue Sep 30 20:09:53 GMT 2025