aic7xxx.c revision 1.42
1 /* $NetBSD: aic7xxx.c,v 1.42 2000/03/15 02:08:28 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.41 2000/02/09 21:24:58 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include "pci.h" 92 93 #include <sys/param.h> 94 #include <sys/kernel.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 #include <sys/buf.h> 99 #include <sys/proc.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <vm/vm.h> 111 #include <vm/vm_param.h> 112 #include <vm/pmap.h> 113 114 #include <dev/ic/aic7xxxvar.h> 115 #include <dev/microcode/aic7xxx/sequencer.h> 116 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 117 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 118 119 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 120 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 121 #define ALL_CHANNELS '\0' 122 #define ALL_TARGETS_MASK 0xFFFF 123 #define INITIATOR_WILDCARD (~0) 124 125 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 126 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 127 #define SIM_CHANNEL(ahc, sc_link) \ 128 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 129 #define SIM_SCSI_ID(ahc, sc_link) \ 130 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 131 #define SCB_IS_SCSIBUS_B(scb) \ 132 (((scb)->hscb->tcl & SELBUSB) != 0) 133 #define SCB_TARGET(scb) \ 134 (((scb)->hscb->tcl & TID) >> 4) 135 #define SCB_CHANNEL(scb) \ 136 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 137 #define SCB_LUN(scb) \ 138 ((scb)->hscb->tcl & LID) 139 #define SCB_TARGET_OFFSET(scb) \ 140 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 141 #define SCB_TARGET_MASK(scb) \ 142 (0x01 << (SCB_TARGET_OFFSET(scb))) 143 #define TCL_CHANNEL(ahc, tcl) \ 144 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 145 #define TCL_SCSI_ID(ahc, tcl) \ 146 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 147 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 148 #define TCL_LUN(tcl) ((tcl) & LID) 149 150 #define XS_TCL(ahc, xs) \ 151 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 152 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 153 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 154 155 char *ahc_chip_names[] = 156 { 157 "NONE", 158 "aic7770", 159 "aic7850", 160 "aic7855", 161 "aic7859", 162 "aic7860", 163 "aic7870", 164 "aic7880", 165 "aic7890/91", 166 "aic7892", 167 "aic7895", 168 "aic7896/97", 169 "aic7899" 170 }; 171 172 typedef enum { 173 ROLE_UNKNOWN, 174 ROLE_INITIATOR, 175 ROLE_TARGET 176 } role_t; 177 178 struct ahc_devinfo { 179 int our_scsiid; 180 int target_offset; 181 u_int16_t target_mask; 182 u_int8_t target; 183 u_int8_t lun; 184 char channel; 185 role_t role; /* 186 * Only guaranteed to be correct if not 187 * in the busfree state. 188 */ 189 }; 190 191 typedef enum { 192 SEARCH_COMPLETE, 193 SEARCH_COUNT, 194 SEARCH_REMOVE 195 } ahc_search_action; 196 197 #ifdef AHC_DEBUG 198 static int ahc_debug = AHC_DEBUG; 199 #endif 200 201 #if NPCI > 0 202 extern void ahc_pci_intr(struct ahc_softc *); 203 #endif 204 205 static int ahcinitscbdata(struct ahc_softc *); 206 static void ahcfiniscbdata(struct ahc_softc *); 207 208 #if UNUSED 209 static void ahc_dump_targcmd(struct target_cmd *); 210 #endif 211 static void ahc_shutdown(void *arg); 212 static int32_t ahc_action(struct scsipi_xfer *); 213 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 214 static int ahc_poll(struct ahc_softc *, int); 215 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 216 struct scb *); 217 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 218 static void ahcallocscbs(struct ahc_softc *); 219 #if UNUSED 220 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 221 struct scb *); 222 #endif 223 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 224 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 225 char, role_t); 226 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 227 static void ahc_done(struct ahc_softc *, struct scb *); 228 static struct tmode_tstate * 229 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 230 #if UNUSED 231 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 232 #endif 233 static void ahc_handle_seqint(struct ahc_softc *, u_int); 234 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 235 static void ahc_build_transfer_msg(struct ahc_softc *, 236 struct ahc_devinfo *); 237 static void ahc_setup_initiator_msgout(struct ahc_softc *, 238 struct ahc_devinfo *, 239 struct scb *); 240 static void ahc_setup_target_msgin(struct ahc_softc *, 241 struct ahc_devinfo *); 242 static void ahc_clear_msg_state(struct ahc_softc *); 243 static void ahc_handle_message_phase(struct ahc_softc *, 244 struct scsipi_link *); 245 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 246 247 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 248 struct ahc_devinfo *); 249 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 250 struct ahc_devinfo *); 251 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 252 int, char *, int); 253 #ifdef AHC_DUMP_SEQ 254 static void ahc_dumpseq(struct ahc_softc *); 255 #endif 256 static void ahc_loadseq(struct ahc_softc *); 257 static int ahc_check_patch(struct ahc_softc *, struct patch **, 258 int, int *); 259 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 260 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 261 #if defined(AHC_DEBUG) 262 static void ahc_print_scb(struct scb *); 263 #endif 264 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 265 role_t, scb_flag, ahc_search_action); 266 static int ahc_reset_channel(struct ahc_softc *, char, int); 267 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 268 role_t, int); 269 static int ahc_search_disc_list(struct ahc_softc *, int, 270 char, int, u_int, int, int, int); 271 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 272 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 273 static void ahc_clear_intstat(struct ahc_softc *); 274 static void ahc_reset_current_bus(struct ahc_softc *); 275 static struct ahc_syncrate * 276 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 277 static struct ahc_syncrate * 278 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 279 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 280 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 281 u_int *, int); 282 static void ahc_update_target_msg_request(struct ahc_softc *, 283 struct ahc_devinfo *, 284 struct ahc_initiator_tinfo *, 285 int, int); 286 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 287 struct ahc_syncrate *, u_int, u_int, u_int, 288 int, int); 289 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 290 u_int, u_int, int, int); 291 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 292 int); 293 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 294 295 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 296 297 static void ahc_calc_residual(struct scb *); 298 299 static void ahc_update_pending_syncrates(struct ahc_softc *); 300 301 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 302 303 static void ahc_timeout (void *); 304 static __inline int sequencer_paused(struct ahc_softc *); 305 static __inline void pause_sequencer(struct ahc_softc *); 306 static __inline void unpause_sequencer(struct ahc_softc *); 307 static void restart_sequencer(struct ahc_softc *); 308 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 309 310 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 311 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 312 313 static __inline void ahc_freeze_ccb(struct scb *); 314 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 315 static void ahc_run_qoutfifo(struct ahc_softc *); 316 317 static __inline struct ahc_initiator_tinfo * 318 ahc_fetch_transinfo(struct ahc_softc *, 319 char, u_int, u_int, 320 struct tmode_tstate **); 321 static void ahcfreescb(struct ahc_softc *, struct scb *); 322 static __inline struct scb *ahcgetscb(struct ahc_softc *); 323 324 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 325 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 326 int *, const char *, const char *); 327 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 328 caddr_t, bus_dma_segment_t *, int); 329 static void ahcminphys(struct buf *); 330 331 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 332 static __inline void ahc_swap_hscb(struct hardware_scb *); 333 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 334 335 #if defined(AHC_DEBUG) && 0 336 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 337 #endif 338 339 static struct scsipi_device ahc_dev = 340 { 341 NULL, /* Use default error handler */ 342 NULL, /* have a queue, served by this */ 343 NULL, /* have no async handler */ 344 NULL, /* Use default 'done' routine */ 345 }; 346 347 /* 348 * Pick the first xs for a non-blocked target. 349 */ 350 static __inline struct scsipi_xfer * 351 ahc_first_xs(struct ahc_softc *ahc) 352 { 353 int target; 354 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 355 356 if (ahc->queue_blocked) 357 return NULL; 358 359 while (xs != NULL) { 360 target = xs->sc_link->scsipi_scsi.target; 361 if (ahc->devqueue_blocked[target] == 0 && 362 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 363 SCB_LIST_NULL) 364 break; 365 xs = TAILQ_NEXT(xs, adapter_q); 366 } 367 368 return xs; 369 } 370 371 static __inline void 372 ahc_swap_hscb(struct hardware_scb *hscb) 373 { 374 hscb->SG_pointer = htole32(hscb->SG_pointer); 375 hscb->data = htole32(hscb->data); 376 hscb->datalen = htole32(hscb->datalen); 377 /* 378 * No need to swap cmdpointer; it's either NULL or set to 379 * cmdstore_busaddr, which is already swapped. 380 */ 381 } 382 383 static __inline void 384 ahc_swap_sg(struct ahc_dma_seg *sg) 385 { 386 sg->addr = htole32(sg->addr); 387 sg->len = htole32(sg->len); 388 } 389 390 static void 391 ahcminphys(bp) 392 struct buf *bp; 393 { 394 /* 395 * Even though the card can transfer up to 16megs per command 396 * we are limited by the number of segments in the dma segment 397 * list that we can hold. The worst case is that all pages are 398 * discontinuous physically, hense the "page per segment" limit 399 * enforced here. 400 */ 401 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 402 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 403 } 404 minphys(bp); 405 } 406 407 408 static __inline u_int32_t 409 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 410 { 411 return (ahc->scb_data->hscb_busaddr 412 + (sizeof(struct hardware_scb) * index)); 413 } 414 415 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 416 417 static __inline int 418 sequencer_paused(struct ahc_softc *ahc) 419 { 420 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 421 } 422 423 static __inline void 424 pause_sequencer(struct ahc_softc *ahc) 425 { 426 ahc_outb(ahc, HCNTRL, ahc->pause); 427 428 /* 429 * Since the sequencer can disable pausing in a critical section, we 430 * must loop until it actually stops. 431 */ 432 while (sequencer_paused(ahc) == 0) 433 ; 434 } 435 436 static __inline void 437 unpause_sequencer(struct ahc_softc *ahc) 438 { 439 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 440 ahc_outb(ahc, HCNTRL, ahc->unpause); 441 } 442 443 /* 444 * Restart the sequencer program from address zero 445 */ 446 static void 447 restart_sequencer(struct ahc_softc *ahc) 448 { 449 u_int i; 450 451 pause_sequencer(ahc); 452 453 /* 454 * Everytime we restart the sequencer, there 455 * is the possiblitity that we have restarted 456 * within a three instruction window where an 457 * SCB has been marked free but has not made it 458 * onto the free list. Since SCSI events(bus reset, 459 * unexpected bus free) will always freeze the 460 * sequencer, we cannot close this window. To 461 * avoid losing an SCB, we reconsitute the free 462 * list every time we restart the sequencer. 463 */ 464 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 465 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 466 467 ahc_outb(ahc, SCBPTR, i); 468 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 469 ahc_add_curscb_to_free_list(ahc); 470 } 471 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 472 unpause_sequencer(ahc); 473 } 474 475 static __inline u_int 476 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 477 { 478 u_int scbid; 479 480 scbid = ahc->untagged_scbs[tcl]; 481 if (unbusy) { 482 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 483 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 484 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 485 } 486 487 return (scbid); 488 } 489 490 static __inline void 491 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 492 { 493 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 494 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 495 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 496 } 497 498 static __inline int 499 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 500 { 501 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 502 } 503 504 static __inline void 505 ahc_freeze_ccb(struct scb *scb) 506 { 507 struct scsipi_xfer *xs = scb->xs; 508 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 509 int target; 510 511 target = xs->sc_link->scsipi_scsi.target; 512 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 513 ahc->devqueue_blocked[target]++; 514 scb->flags |= SCB_FREEZE_QUEUE; 515 } 516 } 517 518 static __inline void 519 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 520 { 521 xs->error = status; 522 } 523 524 static __inline struct ahc_initiator_tinfo * 525 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 526 u_int remote_id, struct tmode_tstate **tstate) 527 { 528 /* 529 * Transfer data structures are stored from the perspective 530 * of the target role. Since the parameters for a connection 531 * in the initiator role to a given target are the same as 532 * when the roles are reversed, we pretend we are the target. 533 */ 534 if (channel == 'B') 535 our_id += 8; 536 *tstate = ahc->enabled_targets[our_id]; 537 return (&(*tstate)->transinfo[remote_id]); 538 } 539 540 static void 541 ahc_run_qoutfifo(struct ahc_softc *ahc) 542 { 543 struct scb *scb; 544 u_int scb_index; 545 546 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 547 256, BUS_DMASYNC_POSTREAD); 548 549 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 550 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 551 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 552 553 scb = &ahc->scb_data->scbarray[scb_index]; 554 if (scb_index >= ahc->scb_data->numscbs 555 || (scb->flags & SCB_ACTIVE) == 0) { 556 printf("%s: WARNING no command for scb %d " 557 "(cmdcmplt)\nQOUTPOS = %d\n", 558 ahc_name(ahc), scb_index, 559 ahc->qoutfifonext - 1); 560 continue; 561 } 562 563 /* 564 * Save off the residual 565 * if there is one. 566 */ 567 if (scb->hscb->residual_SG_count != 0) 568 ahc_calc_residual(scb); 569 else 570 scb->xs->resid = 0; 571 #ifdef AHC_DEBUG 572 if (ahc_debug & AHC_SHOWSCBS) { 573 scsi_print_addr(scb->xs->sc_link); 574 printf("run_qoutfifo: SCB %x complete\n", 575 scb->hscb->tag); 576 } 577 #endif 578 ahc_done(ahc, scb); 579 } 580 } 581 582 583 /* 584 * An scb (and hence an scb entry on the board) is put onto the 585 * free list. 586 */ 587 static void 588 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 589 { 590 struct hardware_scb *hscb; 591 int opri; 592 593 hscb = scb->hscb; 594 595 #ifdef AHC_DEBUG 596 if (ahc_debug & AHC_SHOWSCBALLOC) 597 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 598 #endif 599 600 opri = splbio(); 601 602 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 603 (scb->flags & SCB_RECOVERY_SCB) != 0) { 604 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 605 ahc->queue_blocked = 0; 606 } 607 608 /* Clean up for the next user */ 609 scb->flags = SCB_FREE; 610 hscb->control = 0; 611 hscb->status = 0; 612 613 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 614 615 splx(opri); 616 } 617 618 /* 619 * Get a free scb, either one already assigned to a hardware slot 620 * on the adapter or one that will require an SCB to be paged out before 621 * use. If there are none, see if we can allocate a new SCB. Otherwise 622 * either return an error or sleep. 623 */ 624 static __inline struct scb * 625 ahcgetscb(struct ahc_softc *ahc) 626 { 627 struct scb *scbp; 628 int opri;; 629 630 opri = splbio(); 631 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 632 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 633 } else { 634 ahcallocscbs(ahc); 635 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 636 if (scbp != NULL) 637 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 638 } 639 640 splx(opri); 641 642 #ifdef AHC_DEBUG 643 if (ahc_debug & AHC_SHOWSCBALLOC) { 644 if (scbp != NULL) 645 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 646 scbp->hscb->tag); 647 else 648 printf("%s: failed to allocate new SCB\n", 649 ahc_name(ahc)); 650 } 651 #endif 652 653 return (scbp); 654 } 655 656 static int 657 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 658 bus_dma_tag_t tag; 659 int size; 660 int flags; 661 bus_dmamap_t *mapp; 662 caddr_t *vaddr; 663 bus_addr_t *baddr; 664 bus_dma_segment_t *seg; 665 int *nseg; 666 const char *myname, *what; 667 { 668 int error, level = 0; 669 670 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 671 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 672 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 673 myname, what, error); 674 goto out; 675 } 676 level++; 677 678 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 679 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 680 printf("%s: failed to map DMA mem for %s, error = %d\n", 681 myname, what, error); 682 goto out; 683 } 684 level++; 685 686 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 687 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 688 printf("%s: failed to create DMA map for %s, error = %d\n", 689 myname, what, error); 690 goto out; 691 } 692 level++; 693 694 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 695 BUS_DMA_NOWAIT)) != 0) { 696 printf("%s: failed to load DMA map for %s, error = %d\n", 697 myname, what, error); 698 goto out; 699 } 700 701 *baddr = (*mapp)->dm_segs[0].ds_addr; 702 703 #ifdef AHC_DEBUG 704 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 705 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 706 *nseg, size); 707 #endif 708 709 return 0; 710 out: 711 switch (level) { 712 case 3: 713 bus_dmamap_destroy(tag, *mapp); 714 /* FALLTHROUGH */ 715 case 2: 716 bus_dmamem_unmap(tag, *vaddr, size); 717 /* FALLTHROUGH */ 718 case 1: 719 bus_dmamem_free(tag, seg, *nseg); 720 break; 721 default: 722 break; 723 } 724 725 return error; 726 } 727 728 static void 729 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 730 bus_dma_tag_t tag; 731 int size; 732 bus_dmamap_t map; 733 caddr_t vaddr; 734 bus_dma_segment_t *seg; 735 int nseg; 736 { 737 738 bus_dmamap_unload(tag, map); 739 bus_dmamap_destroy(tag, map); 740 bus_dmamem_unmap(tag, vaddr, size); 741 bus_dmamem_free(tag, seg, nseg); 742 } 743 744 char * 745 ahc_name(struct ahc_softc *ahc) 746 { 747 return (ahc->sc_dev.dv_xname); 748 } 749 750 #ifdef AHC_DEBUG 751 static void 752 ahc_print_scb(struct scb *scb) 753 { 754 struct hardware_scb *hscb = scb->hscb; 755 756 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 757 scb, 758 hscb->tag, 759 hscb->control, 760 hscb->tcl, 761 hscb->cmdlen, 762 (unsigned long)le32toh(hscb->cmdpointer)); 763 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 764 le32toh(hscb->datalen), 765 (unsigned long)(le32toh(hscb->data)), 766 hscb->SG_count, 767 (unsigned long)(le32toh(hscb->SG_pointer))); 768 printf(" sg_addr:%lx sg_len:%lu\n", 769 (unsigned long)(le32toh(scb->sg_list[0].addr)), 770 (unsigned long)(le32toh(scb->sg_list[0].len)); 771 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 772 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 773 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 774 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 775 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 776 } 777 #endif 778 779 static struct { 780 u_int8_t errno; 781 char *errmesg; 782 } hard_error[] = { 783 { ILLHADDR, "Illegal Host Access" }, 784 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 785 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 786 { SQPARERR, "Sequencer Parity Error" }, 787 { DPARERR, "Data-path Parity Error" }, 788 { MPARERR, "Scratch or SCB Memory Parity Error" }, 789 { PCIERRSTAT, "PCI Error detected" }, 790 { CIOPARERR, "CIOBUS Parity Error" }, 791 }; 792 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 793 794 static struct { 795 u_int8_t phase; 796 u_int8_t mesg_out; /* Message response to parity errors */ 797 char *phasemsg; 798 } phase_table[] = { 799 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 800 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 801 { P_COMMAND, MSG_NOOP, "in Command phase" }, 802 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 803 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 804 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 805 { P_BUSFREE, MSG_NOOP, "while idle" }, 806 { 0, MSG_NOOP, "in unknown phase" } 807 }; 808 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 809 810 /* 811 * Valid SCSIRATE values. (p. 3-17) 812 * Provides a mapping of tranfer periods in ns to the proper value to 813 * stick in the scsiscfr reg to use that transfer rate. 814 */ 815 #define AHC_SYNCRATE_DT 0 816 #define AHC_SYNCRATE_ULTRA2 1 817 #define AHC_SYNCRATE_ULTRA 2 818 #define AHC_SYNCRATE_FAST 5 819 static struct ahc_syncrate ahc_syncrates[] = { 820 /* ultra2 fast/ultra period rate */ 821 { 0x42, 0x000, 9, "80.0" }, 822 { 0x03, 0x000, 10, "40.0" }, 823 { 0x04, 0x000, 11, "33.0" }, 824 { 0x05, 0x100, 12, "20.0" }, 825 { 0x06, 0x110, 15, "16.0" }, 826 { 0x07, 0x120, 18, "13.4" }, 827 { 0x08, 0x000, 25, "10.0" }, 828 { 0x19, 0x010, 31, "8.0" }, 829 { 0x1a, 0x020, 37, "6.67" }, 830 { 0x1b, 0x030, 43, "5.7" }, 831 { 0x1c, 0x040, 50, "5.0" }, 832 { 0x00, 0x050, 56, "4.4" }, 833 { 0x00, 0x060, 62, "4.0" }, 834 { 0x00, 0x070, 68, "3.6" }, 835 { 0x00, 0x000, 0, NULL } 836 }; 837 838 /* 839 * Allocate a controller structure for a new device and initialize it. 840 */ 841 int 842 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 843 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 844 ahc_flag flags) 845 { 846 struct scb_data *scb_data; 847 848 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 849 if (scb_data == NULL) { 850 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 851 return -1; 852 } 853 bzero(scb_data, sizeof (struct scb_data)); 854 LIST_INIT(&ahc->pending_ccbs); 855 ahc->tag = st; 856 ahc->bsh = sh; 857 ahc->parent_dmat = parent_dmat; 858 ahc->chip = chip; 859 ahc->features = features; 860 ahc->flags = flags; 861 ahc->scb_data = scb_data; 862 863 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 864 /* The IRQMS bit is only valid on VL and EISA chips */ 865 if ((ahc->chip & AHC_PCI) != 0) 866 ahc->unpause &= ~IRQMS; 867 ahc->pause = ahc->unpause | PAUSE; 868 return (0); 869 } 870 871 void 872 ahc_free(ahc) 873 struct ahc_softc *ahc; 874 { 875 ahcfiniscbdata(ahc); 876 if (ahc->init_level != 0) 877 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 878 ahc->shared_data_dmamap, ahc->qoutfifo, 879 &ahc->shared_data_seg, ahc->shared_data_nseg); 880 881 if (ahc->scb_data != NULL) 882 free(ahc->scb_data, M_DEVBUF); 883 if (ahc->bus_data != NULL) 884 free(ahc->bus_data, M_DEVBUF); 885 return; 886 } 887 888 static int 889 ahcinitscbdata(struct ahc_softc *ahc) 890 { 891 struct scb_data *scb_data; 892 int i; 893 894 scb_data = ahc->scb_data; 895 SLIST_INIT(&scb_data->free_scbs); 896 SLIST_INIT(&scb_data->sg_maps); 897 898 /* Allocate SCB resources */ 899 scb_data->scbarray = 900 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 901 M_DEVBUF, M_NOWAIT); 902 if (scb_data->scbarray == NULL) 903 return (ENOMEM); 904 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 905 906 /* Determine the number of hardware SCBs and initialize them */ 907 908 scb_data->maxhscbs = ahc_probe_scbs(ahc); 909 /* SCB 0 heads the free list */ 910 ahc_outb(ahc, FREE_SCBH, 0); 911 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 912 ahc_outb(ahc, SCBPTR, i); 913 914 /* Clear the control byte. */ 915 ahc_outb(ahc, SCB_CONTROL, 0); 916 917 /* Set the next pointer */ 918 ahc_outb(ahc, SCB_NEXT, i+1); 919 920 /* Make the tag number invalid */ 921 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 922 } 923 924 /* Make sure that the last SCB terminates the free list */ 925 ahc_outb(ahc, SCBPTR, i-1); 926 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 927 928 /* Ensure we clear the 0 SCB's control byte. */ 929 ahc_outb(ahc, SCBPTR, 0); 930 ahc_outb(ahc, SCB_CONTROL, 0); 931 932 scb_data->maxhscbs = i; 933 934 if (ahc->scb_data->maxhscbs == 0) 935 panic("%s: No SCB space found", ahc_name(ahc)); 936 937 /* 938 * Create our DMA tags. These tags define the kinds of device 939 * accessable memory allocations and memory mappings we will 940 * need to perform during normal operation. 941 * 942 * Unless we need to further restrict the allocation, we rely 943 * on the restrictions of the parent dmat, hence the common 944 * use of MAXADDR and MAXSIZE. 945 */ 946 947 if (ahc_createdmamem(ahc->parent_dmat, 948 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 949 &scb_data->hscb_dmamap, 950 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 951 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 952 "hardware SCB structures") < 0) 953 goto error_exit; 954 955 scb_data->init_level++; 956 957 if (ahc_createdmamem(ahc->parent_dmat, 958 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 959 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 960 &scb_data->sense_busaddr, &scb_data->sense_seg, 961 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 962 goto error_exit; 963 964 scb_data->init_level++; 965 966 /* Perform initial CCB allocation */ 967 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 968 ahcallocscbs(ahc); 969 970 if (scb_data->numscbs == 0) { 971 printf("%s: ahc_init_scb_data - " 972 "Unable to allocate initial scbs\n", 973 ahc_name(ahc)); 974 goto error_exit; 975 } 976 977 scb_data->init_level++; 978 979 /* 980 * Note that we were successfull 981 */ 982 return 0; 983 984 error_exit: 985 986 return ENOMEM; 987 } 988 989 static void 990 ahcfiniscbdata(struct ahc_softc *ahc) 991 { 992 struct scb_data *scb_data; 993 994 scb_data = ahc->scb_data; 995 996 switch (scb_data->init_level) { 997 default: 998 case 3: 999 { 1000 struct sg_map_node *sg_map; 1001 1002 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1003 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1004 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1005 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1006 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1007 free(sg_map, M_DEVBUF); 1008 } 1009 } 1010 /*FALLTHROUGH*/ 1011 case 2: 1012 ahc_freedmamem(ahc->parent_dmat, 1013 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1014 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1015 &scb_data->sense_seg, scb_data->sense_nseg); 1016 /*FALLTHROUGH*/ 1017 case 1: 1018 ahc_freedmamem(ahc->parent_dmat, 1019 AHC_SCB_MAX * sizeof(struct hardware_scb), 1020 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1021 &scb_data->hscb_seg, scb_data->hscb_nseg); 1022 /*FALLTHROUGH*/ 1023 } 1024 if (scb_data->scbarray != NULL) 1025 free(scb_data->scbarray, M_DEVBUF); 1026 } 1027 1028 int 1029 ahc_reset(struct ahc_softc *ahc) 1030 { 1031 u_int sblkctl; 1032 int wait; 1033 1034 #ifdef AHC_DUMP_SEQ 1035 if (ahc->init_level == 0) 1036 ahc_dumpseq(ahc); 1037 #endif 1038 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1039 /* 1040 * Ensure that the reset has finished 1041 */ 1042 wait = 1000; 1043 do { 1044 DELAY(1000); 1045 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1046 1047 if (wait == 0) { 1048 printf("%s: WARNING - Failed chip reset! " 1049 "Trying to initialize anyway.\n", ahc_name(ahc)); 1050 } 1051 ahc_outb(ahc, HCNTRL, ahc->pause); 1052 1053 /* Determine channel configuration */ 1054 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1055 /* No Twin Channel PCI cards */ 1056 if ((ahc->chip & AHC_PCI) != 0) 1057 sblkctl &= ~SELBUSB; 1058 switch (sblkctl) { 1059 case 0: 1060 /* Single Narrow Channel */ 1061 break; 1062 case 2: 1063 /* Wide Channel */ 1064 ahc->features |= AHC_WIDE; 1065 break; 1066 case 8: 1067 /* Twin Channel */ 1068 ahc->features |= AHC_TWIN; 1069 break; 1070 default: 1071 printf(" Unsupported adapter type. Ignoring\n"); 1072 return(-1); 1073 } 1074 1075 return (0); 1076 } 1077 1078 /* 1079 * Called when we have an active connection to a target on the bus, 1080 * this function finds the nearest syncrate to the input period limited 1081 * by the capabilities of the bus connectivity of the target. 1082 */ 1083 static struct ahc_syncrate * 1084 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1085 u_int maxsync; 1086 1087 if ((ahc->features & AHC_ULTRA2) != 0) { 1088 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1089 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1090 maxsync = AHC_SYNCRATE_ULTRA2; 1091 } else { 1092 maxsync = AHC_SYNCRATE_ULTRA; 1093 } 1094 } else if ((ahc->features & AHC_ULTRA) != 0) { 1095 maxsync = AHC_SYNCRATE_ULTRA; 1096 } else { 1097 maxsync = AHC_SYNCRATE_FAST; 1098 } 1099 return (ahc_find_syncrate(ahc, period, maxsync)); 1100 } 1101 1102 /* 1103 * Look up the valid period to SCSIRATE conversion in our table. 1104 * Return the period and offset that should be sent to the target 1105 * if this was the beginning of an SDTR. 1106 */ 1107 static struct ahc_syncrate * 1108 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1109 { 1110 struct ahc_syncrate *syncrate; 1111 1112 syncrate = &ahc_syncrates[maxsync]; 1113 while ((syncrate->rate != NULL) 1114 && ((ahc->features & AHC_ULTRA2) == 0 1115 || (syncrate->sxfr_u2 != 0))) { 1116 1117 if (*period <= syncrate->period) { 1118 /* 1119 * When responding to a target that requests 1120 * sync, the requested rate may fall between 1121 * two rates that we can output, but still be 1122 * a rate that we can receive. Because of this, 1123 * we want to respond to the target with 1124 * the same rate that it sent to us even 1125 * if the period we use to send data to it 1126 * is lower. Only lower the response period 1127 * if we must. 1128 */ 1129 if (syncrate == &ahc_syncrates[maxsync]) 1130 *period = syncrate->period; 1131 break; 1132 } 1133 syncrate++; 1134 } 1135 1136 if ((*period == 0) 1137 || (syncrate->rate == NULL) 1138 || ((ahc->features & AHC_ULTRA2) != 0 1139 && (syncrate->sxfr_u2 == 0))) { 1140 /* Use asynchronous transfers. */ 1141 *period = 0; 1142 syncrate = NULL; 1143 } 1144 return (syncrate); 1145 } 1146 1147 static u_int 1148 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1149 { 1150 struct ahc_syncrate *syncrate; 1151 1152 if ((ahc->features & AHC_ULTRA2) != 0) 1153 scsirate &= SXFR_ULTRA2; 1154 else 1155 scsirate &= SXFR; 1156 1157 syncrate = &ahc_syncrates[maxsync]; 1158 while (syncrate->rate != NULL) { 1159 1160 if ((ahc->features & AHC_ULTRA2) != 0) { 1161 if (syncrate->sxfr_u2 == 0) 1162 break; 1163 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1164 return (syncrate->period); 1165 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1166 return (syncrate->period); 1167 } 1168 syncrate++; 1169 } 1170 return (0); /* async */ 1171 } 1172 1173 static void 1174 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1175 u_int *offset, int wide) 1176 { 1177 u_int maxoffset; 1178 1179 /* Limit offset to what we can do */ 1180 if (syncrate == NULL) { 1181 maxoffset = 0; 1182 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1183 maxoffset = MAX_OFFSET_ULTRA2; 1184 } else { 1185 if (wide) 1186 maxoffset = MAX_OFFSET_16BIT; 1187 else 1188 maxoffset = MAX_OFFSET_8BIT; 1189 } 1190 *offset = MIN(*offset, maxoffset); 1191 } 1192 1193 static void 1194 ahc_update_target_msg_request(struct ahc_softc *ahc, 1195 struct ahc_devinfo *devinfo, 1196 struct ahc_initiator_tinfo *tinfo, 1197 int force, int paused) 1198 { 1199 u_int targ_msg_req_orig; 1200 1201 targ_msg_req_orig = ahc->targ_msg_req; 1202 if (tinfo->current.period != tinfo->goal.period 1203 || tinfo->current.width != tinfo->goal.width 1204 || tinfo->current.offset != tinfo->goal.offset 1205 || (force 1206 && (tinfo->goal.period != 0 1207 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1208 ahc->targ_msg_req |= devinfo->target_mask; 1209 } else { 1210 ahc->targ_msg_req &= ~devinfo->target_mask; 1211 } 1212 1213 if (ahc->targ_msg_req != targ_msg_req_orig) { 1214 /* Update the message request bit for this target */ 1215 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1216 if (paused) { 1217 ahc_outb(ahc, TARGET_MSG_REQUEST, 1218 ahc->targ_msg_req & 0xFF); 1219 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1220 (ahc->targ_msg_req >> 8) & 0xFF); 1221 } else { 1222 ahc_outb(ahc, HS_MAILBOX, 1223 0x01 << HOST_MAILBOX_SHIFT); 1224 } 1225 } else { 1226 if (!paused) 1227 pause_sequencer(ahc); 1228 1229 ahc_outb(ahc, TARGET_MSG_REQUEST, 1230 ahc->targ_msg_req & 0xFF); 1231 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1232 (ahc->targ_msg_req >> 8) & 0xFF); 1233 1234 if (!paused) 1235 unpause_sequencer(ahc); 1236 } 1237 } 1238 } 1239 1240 static void 1241 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1242 struct ahc_syncrate *syncrate, 1243 u_int period, u_int offset, u_int type, int paused, int done) 1244 { 1245 struct ahc_initiator_tinfo *tinfo; 1246 struct tmode_tstate *tstate; 1247 u_int old_period; 1248 u_int old_offset; 1249 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1250 1251 if (syncrate == NULL) { 1252 period = 0; 1253 offset = 0; 1254 } 1255 1256 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1257 devinfo->target, &tstate); 1258 old_period = tinfo->current.period; 1259 old_offset = tinfo->current.offset; 1260 1261 if ((type & AHC_TRANS_CUR) != 0 1262 && (old_period != period || old_offset != offset)) { 1263 u_int scsirate; 1264 1265 scsirate = tinfo->scsirate; 1266 if ((ahc->features & AHC_ULTRA2) != 0) { 1267 1268 /* XXX */ 1269 /* Force single edge until DT is fully implemented */ 1270 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1271 if (syncrate != NULL) 1272 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1273 1274 if (active) 1275 ahc_outb(ahc, SCSIOFFSET, offset); 1276 } else { 1277 1278 scsirate &= ~(SXFR|SOFS); 1279 /* 1280 * Ensure Ultra mode is set properly for 1281 * this target. 1282 */ 1283 tstate->ultraenb &= ~devinfo->target_mask; 1284 if (syncrate != NULL) { 1285 if (syncrate->sxfr & ULTRA_SXFR) { 1286 tstate->ultraenb |= 1287 devinfo->target_mask; 1288 } 1289 scsirate |= syncrate->sxfr & SXFR; 1290 scsirate |= offset & SOFS; 1291 } 1292 if (active) { 1293 u_int sxfrctl0; 1294 1295 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1296 sxfrctl0 &= ~FAST20; 1297 if (tstate->ultraenb & devinfo->target_mask) 1298 sxfrctl0 |= FAST20; 1299 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1300 } 1301 } 1302 if (active) 1303 ahc_outb(ahc, SCSIRATE, scsirate); 1304 1305 tinfo->scsirate = scsirate; 1306 tinfo->current.period = period; 1307 tinfo->current.offset = offset; 1308 1309 /* Update the syncrates in any pending scbs */ 1310 ahc_update_pending_syncrates(ahc); 1311 } 1312 1313 /* 1314 * Print messages if we're verbose and at the end of a negotiation 1315 * cycle. 1316 */ 1317 if (done) { 1318 if (offset != 0) { 1319 printf("%s: target %d synchronous at %sMHz, " 1320 "offset = 0x%x\n", ahc_name(ahc), 1321 devinfo->target, syncrate->rate, offset); 1322 } else { 1323 printf("%s: target %d using " 1324 "asynchronous transfers\n", 1325 ahc_name(ahc), devinfo->target); 1326 } 1327 } 1328 1329 if ((type & AHC_TRANS_GOAL) != 0) { 1330 tinfo->goal.period = period; 1331 tinfo->goal.offset = offset; 1332 } 1333 1334 if ((type & AHC_TRANS_USER) != 0) { 1335 tinfo->user.period = period; 1336 tinfo->user.offset = offset; 1337 } 1338 1339 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1340 /*force*/FALSE, 1341 paused); 1342 } 1343 1344 static void 1345 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1346 u_int width, u_int type, int paused, int done) 1347 { 1348 struct ahc_initiator_tinfo *tinfo; 1349 struct tmode_tstate *tstate; 1350 u_int oldwidth; 1351 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1352 1353 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1354 devinfo->target, &tstate); 1355 oldwidth = tinfo->current.width; 1356 1357 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1358 u_int scsirate; 1359 1360 scsirate = tinfo->scsirate; 1361 scsirate &= ~WIDEXFER; 1362 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1363 scsirate |= WIDEXFER; 1364 1365 tinfo->scsirate = scsirate; 1366 1367 if (active) 1368 ahc_outb(ahc, SCSIRATE, scsirate); 1369 1370 tinfo->current.width = width; 1371 } 1372 1373 if (done) { 1374 printf("%s: target %d using %dbit transfers\n", 1375 ahc_name(ahc), devinfo->target, 1376 8 * (0x01 << width)); 1377 } 1378 1379 if ((type & AHC_TRANS_GOAL) != 0) 1380 tinfo->goal.width = width; 1381 if ((type & AHC_TRANS_USER) != 0) 1382 tinfo->user.width = width; 1383 1384 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1385 /*force*/FALSE, paused); 1386 } 1387 1388 static void 1389 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1390 { 1391 struct ahc_initiator_tinfo *tinfo; 1392 struct tmode_tstate *tstate; 1393 1394 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1395 devinfo->target, &tstate); 1396 1397 if (enable) 1398 tstate->tagenable |= devinfo->target_mask; 1399 else 1400 tstate->tagenable &= ~devinfo->target_mask; 1401 } 1402 1403 /* 1404 * Attach all the sub-devices we can find 1405 */ 1406 int 1407 ahc_attach(struct ahc_softc *ahc) 1408 { 1409 TAILQ_INIT(&ahc->sc_q); 1410 1411 ahc->sc_adapter.scsipi_cmd = ahc_action; 1412 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1413 ahc->sc_link.type = BUS_SCSI; 1414 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1415 ahc->sc_link.scsipi_scsi.channel = 0; 1416 ahc->sc_link.scsipi_scsi.max_target = 1417 (ahc->features & AHC_WIDE) ? 15 : 7; 1418 ahc->sc_link.scsipi_scsi.max_lun = 7; 1419 ahc->sc_link.adapter_softc = ahc; 1420 ahc->sc_link.adapter = &ahc->sc_adapter; 1421 ahc->sc_link.openings = 2; 1422 ahc->sc_link.device = &ahc_dev; 1423 1424 if (ahc->features & AHC_TWIN) { 1425 ahc->sc_link_b = ahc->sc_link; 1426 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1427 ahc->sc_link_b.scsipi_scsi.channel = 1; 1428 } 1429 1430 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1431 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1432 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1433 if (ahc->features & AHC_TWIN) 1434 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1435 } else { 1436 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1437 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1438 } 1439 return 1; 1440 } 1441 1442 static void 1443 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1444 { 1445 u_int saved_tcl; 1446 role_t role; 1447 int our_id; 1448 1449 if (ahc_inb(ahc, SSTAT0) & TARGET) 1450 role = ROLE_TARGET; 1451 else 1452 role = ROLE_INITIATOR; 1453 1454 if (role == ROLE_TARGET 1455 && (ahc->features & AHC_MULTI_TID) != 0 1456 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1457 /* We were selected, so pull our id from TARGIDIN */ 1458 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1459 } else if ((ahc->features & AHC_ULTRA2) != 0) 1460 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1461 else 1462 our_id = ahc_inb(ahc, SCSIID) & OID; 1463 1464 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1465 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1466 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1467 role); 1468 } 1469 1470 static void 1471 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1472 u_int lun, char channel, role_t role) 1473 { 1474 devinfo->our_scsiid = our_id; 1475 devinfo->target = target; 1476 devinfo->lun = lun; 1477 devinfo->target_offset = target; 1478 devinfo->channel = channel; 1479 devinfo->role = role; 1480 if (channel == 'B') 1481 devinfo->target_offset += 8; 1482 devinfo->target_mask = (0x01 << devinfo->target_offset); 1483 } 1484 1485 /* 1486 * Catch an interrupt from the adapter 1487 */ 1488 int 1489 ahc_intr(void *arg) 1490 { 1491 struct ahc_softc *ahc; 1492 u_int intstat; 1493 1494 ahc = (struct ahc_softc *)arg; 1495 1496 intstat = ahc_inb(ahc, INTSTAT); 1497 1498 /* 1499 * Any interrupts to process? 1500 */ 1501 if ((intstat & INT_PEND) == 0) { 1502 #if NPCI > 0 1503 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) { 1504 #ifdef AHC_PCI_DEBUG 1505 printf("%s: PCI intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1506 ahc_name(ahc), 1507 ahc_inb(ahc, CCHADDR) | 1508 (ahc_inb(ahc, CCHADDR+1) << 8) 1509 | (ahc_inb(ahc, CCHADDR+2) << 16) 1510 | (ahc_inb(ahc, CCHADDR+3) << 24), 1511 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1512 | (ahc_inb(ahc, HADDR+2) << 16) 1513 | (ahc_inb(ahc, HADDR+3) << 24), 1514 ahc_inb(ahc, SEQADDR0) | 1515 (ahc_inb(ahc, SEQADDR1) << 8)); 1516 #endif 1517 ahc_pci_intr(ahc); 1518 return 1; 1519 } 1520 #endif 1521 return 0; 1522 } 1523 1524 #ifdef AHC_DEBUG 1525 if (ahc_debug & AHC_SHOWINTR) { 1526 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1527 } 1528 #endif 1529 1530 if (intstat & CMDCMPLT) { 1531 ahc_outb(ahc, CLRINT, CLRCMDINT); 1532 ahc_run_qoutfifo(ahc); 1533 } 1534 if (intstat & BRKADRINT) { 1535 /* 1536 * We upset the sequencer :-( 1537 * Lookup the error message 1538 */ 1539 int i, error, num_errors; 1540 1541 error = ahc_inb(ahc, ERROR); 1542 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1543 for (i = 0; error != 1 && i < num_errors; i++) 1544 error >>= 1; 1545 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1546 ahc_name(ahc), hard_error[i].errmesg, 1547 ahc_inb(ahc, SEQADDR0) | 1548 (ahc_inb(ahc, SEQADDR1) << 8)); 1549 1550 /* Tell everyone that this HBA is no longer availible */ 1551 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1552 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1553 XS_DRIVER_STUFFUP); 1554 } 1555 if (intstat & SEQINT) 1556 ahc_handle_seqint(ahc, intstat); 1557 1558 if (intstat & SCSIINT) 1559 ahc_handle_scsiint(ahc, intstat); 1560 1561 return 1; 1562 } 1563 1564 static struct tmode_tstate * 1565 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1566 { 1567 struct tmode_tstate *master_tstate; 1568 struct tmode_tstate *tstate; 1569 int i, s; 1570 1571 master_tstate = ahc->enabled_targets[ahc->our_id]; 1572 if (channel == 'B') { 1573 scsi_id += 8; 1574 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1575 } 1576 if (ahc->enabled_targets[scsi_id] != NULL 1577 && ahc->enabled_targets[scsi_id] != master_tstate) 1578 panic("%s: ahc_alloc_tstate - Target already allocated", 1579 ahc_name(ahc)); 1580 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1581 if (tstate == NULL) 1582 return (NULL); 1583 1584 /* 1585 * If we have allocated a master tstate, copy user settings from 1586 * the master tstate (taken from SRAM or the EEPROM) for this 1587 * channel, but reset our current and goal settings to async/narrow 1588 * until an initiator talks to us. 1589 */ 1590 if (master_tstate != NULL) { 1591 bcopy(master_tstate, tstate, sizeof(*tstate)); 1592 tstate->ultraenb = 0; 1593 for (i = 0; i < 16; i++) { 1594 bzero(&tstate->transinfo[i].current, 1595 sizeof(tstate->transinfo[i].current)); 1596 bzero(&tstate->transinfo[i].goal, 1597 sizeof(tstate->transinfo[i].goal)); 1598 } 1599 } else 1600 bzero(tstate, sizeof(*tstate)); 1601 s = splbio(); 1602 ahc->enabled_targets[scsi_id] = tstate; 1603 splx(s); 1604 return (tstate); 1605 } 1606 1607 #if UNUSED 1608 static void 1609 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1610 { 1611 struct tmode_tstate *tstate; 1612 1613 /* Don't clean up the entry for our initiator role */ 1614 if ((ahc->flags & AHC_INITIATORMODE) != 0 1615 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1616 || (channel == 'A' && scsi_id == ahc->our_id)) 1617 && force == FALSE) 1618 return; 1619 1620 if (channel == 'B') 1621 scsi_id += 8; 1622 tstate = ahc->enabled_targets[scsi_id]; 1623 if (tstate != NULL) 1624 free(tstate, M_DEVBUF); 1625 ahc->enabled_targets[scsi_id] = NULL; 1626 } 1627 #endif 1628 1629 static void 1630 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1631 { 1632 struct scb *scb; 1633 struct ahc_devinfo devinfo; 1634 1635 ahc_fetch_devinfo(ahc, &devinfo); 1636 1637 /* 1638 * Clear the upper byte that holds SEQINT status 1639 * codes and clear the SEQINT bit. We will unpause 1640 * the sequencer, if appropriate, after servicing 1641 * the request. 1642 */ 1643 ahc_outb(ahc, CLRINT, CLRSEQINT); 1644 switch (intstat & SEQINT_MASK) { 1645 case NO_MATCH: 1646 { 1647 /* Ensure we don't leave the selection hardware on */ 1648 ahc_outb(ahc, SCSISEQ, 1649 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1650 1651 printf("%s:%c:%d: no active SCB for reconnecting " 1652 "target - issuing BUS DEVICE RESET\n", 1653 ahc_name(ahc), devinfo.channel, devinfo.target); 1654 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1655 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1656 ahc_inb(ahc, SEQ_FLAGS)); 1657 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1658 ahc->msgout_len = 1; 1659 ahc->msgout_index = 0; 1660 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1661 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1662 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1663 break; 1664 } 1665 case UPDATE_TMSG_REQ: 1666 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1667 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1668 (ahc->targ_msg_req >> 8) & 0xFF); 1669 ahc_outb(ahc, HS_MAILBOX, 0); 1670 break; 1671 case SEND_REJECT: 1672 { 1673 u_int rejbyte = ahc_inb(ahc, ACCUM); 1674 printf("%s:%c:%d: Warning - unknown message received from " 1675 "target (0x%x). Rejecting\n", 1676 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1677 break; 1678 } 1679 case NO_IDENT: 1680 { 1681 /* 1682 * The reconnecting target either did not send an identify 1683 * message, or did, but we didn't find and SCB to match and 1684 * before it could respond to our ATN/abort, it hit a dataphase. 1685 * The only safe thing to do is to blow it away with a bus 1686 * reset. 1687 */ 1688 int found; 1689 1690 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1691 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1692 ahc_name(ahc), devinfo.channel, devinfo.target, 1693 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1694 found = ahc_reset_channel(ahc, devinfo.channel, 1695 /*initiate reset*/TRUE); 1696 printf("%s: Issued Channel %c Bus Reset. " 1697 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1698 found); 1699 return; 1700 } 1701 case BAD_PHASE: 1702 { 1703 u_int lastphase; 1704 1705 lastphase = ahc_inb(ahc, LASTPHASE); 1706 if (lastphase == P_BUSFREE) { 1707 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1708 ahc_name(ahc), devinfo.channel, devinfo.target, 1709 ahc_inb(ahc, SCSISIGI)); 1710 restart_sequencer(ahc); 1711 return; 1712 } else { 1713 printf("%s:%c:%d: unknown scsi bus phase %x. " 1714 "Attempting to continue\n", 1715 ahc_name(ahc), devinfo.channel, devinfo.target, 1716 ahc_inb(ahc, SCSISIGI)); 1717 } 1718 break; 1719 } 1720 case BAD_STATUS: 1721 { 1722 u_int scb_index; 1723 struct hardware_scb *hscb; 1724 struct scsipi_xfer *xs; 1725 /* 1726 * The sequencer will notify us when a command 1727 * has an error that would be of interest to 1728 * the kernel. This allows us to leave the sequencer 1729 * running in the common case of command completes 1730 * without error. The sequencer will already have 1731 * dma'd the SCB back up to us, so we can reference 1732 * the in kernel copy directly. 1733 */ 1734 scb_index = ahc_inb(ahc, SCB_TAG); 1735 scb = &ahc->scb_data->scbarray[scb_index]; 1736 1737 /* ahc_print_scb(scb); */ 1738 1739 /* 1740 * Set the default return value to 0 (don't 1741 * send sense). The sense code will change 1742 * this if needed. 1743 */ 1744 ahc_outb(ahc, RETURN_1, 0); 1745 if (!(scb_index < ahc->scb_data->numscbs 1746 && (scb->flags & SCB_ACTIVE) != 0)) { 1747 printf("%s:%c:%d: ahc_intr - referenced scb " 1748 "not valid during seqint 0x%x scb(%d)\n", 1749 ahc_name(ahc), devinfo.channel, 1750 devinfo.target, intstat, scb_index); 1751 goto unpause; 1752 } 1753 1754 hscb = scb->hscb; 1755 xs = scb->xs; 1756 1757 /* Don't want to clobber the original sense code */ 1758 if ((scb->flags & SCB_SENSE) != 0) { 1759 /* 1760 * Clear the SCB_SENSE Flag and have 1761 * the sequencer do a normal command 1762 * complete. 1763 */ 1764 scb->flags &= ~SCB_SENSE; 1765 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1766 break; 1767 } 1768 /* Freeze the queue unit the client sees the error. */ 1769 ahc_freeze_devq(ahc, xs->sc_link); 1770 ahc_freeze_ccb(scb); 1771 xs->status = hscb->status; 1772 switch (hscb->status) { 1773 case SCSI_STATUS_OK: 1774 printf("%s: Interrupted for status of 0???\n", 1775 ahc_name(ahc)); 1776 break; 1777 case SCSI_STATUS_CMD_TERMINATED: 1778 case SCSI_STATUS_CHECK_COND: 1779 #if defined(AHC_DEBUG) 1780 if (ahc_debug & AHC_SHOWSENSE) { 1781 scsi_print_addr(xs->sc_link); 1782 printf("Check Status, resid %d datalen %d\n", 1783 xs->resid, xs->datalen); 1784 } 1785 #endif 1786 1787 if (xs->error == XS_NOERROR && 1788 !(scb->flags & SCB_SENSE)) { 1789 struct ahc_dma_seg *sg; 1790 struct scsipi_sense *sc; 1791 struct ahc_initiator_tinfo *tinfo; 1792 struct tmode_tstate *tstate; 1793 1794 sg = scb->sg_list; 1795 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1796 /* 1797 * Save off the residual if there is one. 1798 */ 1799 if (hscb->residual_SG_count != 0) 1800 ahc_calc_residual(scb); 1801 else 1802 xs->resid = 0; 1803 1804 #ifdef AHC_DEBUG 1805 if (ahc_debug & AHC_SHOWSENSE) { 1806 scsi_print_addr(xs->sc_link); 1807 printf("Sending Sense\n"); 1808 } 1809 #endif 1810 sg->addr = ahc->scb_data->sense_busaddr + 1811 (hscb->tag*sizeof(struct scsipi_sense_data)); 1812 sg->len = sizeof (struct scsipi_sense_data); 1813 1814 sc->opcode = REQUEST_SENSE; 1815 sc->byte2 = SCB_LUN(scb) << 5; 1816 sc->unused[0] = 0; 1817 sc->unused[1] = 0; 1818 sc->length = sg->len; 1819 sc->control = 0; 1820 1821 /* 1822 * Would be nice to preserve DISCENB here, 1823 * but due to the way we page SCBs, we can't. 1824 */ 1825 hscb->control = 0; 1826 1827 /* 1828 * This request sense could be because the 1829 * the device lost power or in some other 1830 * way has lost our transfer negotiations. 1831 * Renegotiate if appropriate. Unit attention 1832 * errors will be reported before any data 1833 * phases occur. 1834 */ 1835 ahc_calc_residual(scb); 1836 #if defined(AHC_DEBUG) 1837 if (ahc_debug & AHC_SHOWSENSE) { 1838 scsi_print_addr(xs->sc_link); 1839 printf("Sense: datalen %d resid %d" 1840 "chan %d id %d targ %d\n", 1841 xs->datalen, xs->resid, 1842 devinfo.channel, devinfo.our_scsiid, 1843 devinfo.target); 1844 } 1845 #endif 1846 if (xs->datalen > 0 && 1847 xs->resid == xs->datalen) { 1848 tinfo = ahc_fetch_transinfo(ahc, 1849 devinfo.channel, 1850 devinfo.our_scsiid, 1851 devinfo.target, 1852 &tstate); 1853 ahc_update_target_msg_request(ahc, 1854 &devinfo, 1855 tinfo, 1856 /*force*/TRUE, 1857 /*paused*/TRUE); 1858 } 1859 hscb->status = 0; 1860 hscb->SG_count = 1; 1861 hscb->SG_pointer = scb->sg_list_phys; 1862 hscb->data = sg->addr; 1863 hscb->datalen = sg->len; 1864 hscb->cmdpointer = hscb->cmdstore_busaddr; 1865 hscb->cmdlen = sizeof(*sc); 1866 scb->sg_count = hscb->SG_count; 1867 ahc_swap_hscb(hscb); 1868 ahc_swap_sg(scb->sg_list); 1869 scb->flags |= SCB_SENSE; 1870 /* 1871 * Ensure the target is busy since this 1872 * will be an untagged request. 1873 */ 1874 ahc_busy_tcl(ahc, scb); 1875 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1876 1877 /* 1878 * Ensure we have enough time to actually 1879 * retrieve the sense. 1880 */ 1881 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1882 untimeout(ahc_timeout, (caddr_t)scb); 1883 timeout(ahc_timeout, (caddr_t)scb, 1884 5 * hz); 1885 } 1886 } 1887 break; 1888 case SCSI_STATUS_BUSY: 1889 case SCSI_STATUS_QUEUE_FULL: 1890 /* 1891 * Requeue any transactions that haven't been 1892 * sent yet. 1893 */ 1894 ahc_freeze_devq(ahc, xs->sc_link); 1895 ahc_freeze_ccb(scb); 1896 break; 1897 } 1898 break; 1899 } 1900 case TRACE_POINT: 1901 { 1902 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1903 ahc_inb(ahc, DFCNTRL)); 1904 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1905 ahc_inb(ahc, DFSTATUS)); 1906 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1907 ahc_inb(ahc, SSTAT0), 1908 ahc_inb(ahc, SCB_DATACNT)); 1909 break; 1910 } 1911 case HOST_MSG_LOOP: 1912 { 1913 /* 1914 * The sequencer has encountered a message phase 1915 * that requires host assistance for completion. 1916 * While handling the message phase(s), we will be 1917 * notified by the sequencer after each byte is 1918 * transfered so we can track bus phases. 1919 * 1920 * If this is the first time we've seen a HOST_MSG_LOOP, 1921 * initialize the state of the host message loop. 1922 */ 1923 if (ahc->msg_type == MSG_TYPE_NONE) { 1924 u_int bus_phase; 1925 1926 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1927 if (bus_phase != P_MESGIN 1928 && bus_phase != P_MESGOUT) { 1929 printf("ahc_intr: HOST_MSG_LOOP bad " 1930 "phase 0x%x\n", 1931 bus_phase); 1932 /* 1933 * Probably transitioned to bus free before 1934 * we got here. Just punt the message. 1935 */ 1936 ahc_clear_intstat(ahc); 1937 restart_sequencer(ahc); 1938 } 1939 1940 if (devinfo.role == ROLE_INITIATOR) { 1941 struct scb *scb; 1942 u_int scb_index; 1943 1944 scb_index = ahc_inb(ahc, SCB_TAG); 1945 scb = &ahc->scb_data->scbarray[scb_index]; 1946 1947 if (bus_phase == P_MESGOUT) 1948 ahc_setup_initiator_msgout(ahc, 1949 &devinfo, 1950 scb); 1951 else { 1952 ahc->msg_type = 1953 MSG_TYPE_INITIATOR_MSGIN; 1954 ahc->msgin_index = 0; 1955 } 1956 } else { 1957 if (bus_phase == P_MESGOUT) { 1958 ahc->msg_type = 1959 MSG_TYPE_TARGET_MSGOUT; 1960 ahc->msgin_index = 0; 1961 } else 1962 /* XXX Ever executed??? */ 1963 ahc_setup_target_msgin(ahc, &devinfo); 1964 } 1965 } 1966 1967 /* Pass a NULL path so that handlers generate their own */ 1968 ahc_handle_message_phase(ahc, /*path*/NULL); 1969 break; 1970 } 1971 case PERR_DETECTED: 1972 { 1973 /* 1974 * If we've cleared the parity error interrupt 1975 * but the sequencer still believes that SCSIPERR 1976 * is true, it must be that the parity error is 1977 * for the currently presented byte on the bus, 1978 * and we are not in a phase (data-in) where we will 1979 * eventually ack this byte. Ack the byte and 1980 * throw it away in the hope that the target will 1981 * take us to message out to deliver the appropriate 1982 * error message. 1983 */ 1984 if ((intstat & SCSIINT) == 0 1985 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1986 u_int curphase; 1987 1988 /* 1989 * The hardware will only let you ack bytes 1990 * if the expected phase in SCSISIGO matches 1991 * the current phase. Make sure this is 1992 * currently the case. 1993 */ 1994 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1995 ahc_outb(ahc, LASTPHASE, curphase); 1996 ahc_outb(ahc, SCSISIGO, curphase); 1997 ahc_inb(ahc, SCSIDATL); 1998 } 1999 break; 2000 } 2001 case DATA_OVERRUN: 2002 { 2003 /* 2004 * When the sequencer detects an overrun, it 2005 * places the controller in "BITBUCKET" mode 2006 * and allows the target to complete its transfer. 2007 * Unfortunately, none of the counters get updated 2008 * when the controller is in this mode, so we have 2009 * no way of knowing how large the overrun was. 2010 */ 2011 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2012 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2013 int i; 2014 2015 scb = &ahc->scb_data->scbarray[scbindex]; 2016 for (i = 0; i < num_phases; i++) { 2017 if (lastphase == phase_table[i].phase) 2018 break; 2019 } 2020 scsi_print_addr(scb->xs->sc_link); 2021 printf("data overrun detected %s." 2022 " Tag == 0x%x.\n", 2023 phase_table[i].phasemsg, 2024 scb->hscb->tag); 2025 scsi_print_addr(scb->xs->sc_link); 2026 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2027 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2028 scb->xs->datalen, scb->sg_count); 2029 if (scb->sg_count > 0) { 2030 for (i = 0; i < scb->sg_count; i++) { 2031 printf("sg[%d] - Addr 0x%x : Length %d\n", 2032 i, 2033 le32toh(scb->sg_list[i].addr), 2034 le32toh(scb->sg_list[i].len)); 2035 } 2036 } 2037 /* 2038 * Set this and it will take affect when the 2039 * target does a command complete. 2040 */ 2041 ahc_freeze_devq(ahc, scb->xs->sc_link); 2042 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2043 ahc_freeze_ccb(scb); 2044 break; 2045 } 2046 case TRACEPOINT: 2047 { 2048 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2049 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2050 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2051 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2052 printf("TRACEPOINT: CCHADDR = %x\n", 2053 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2054 | (ahc_inb(ahc, CCHADDR+2) << 16) 2055 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2056 #if 0 2057 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2058 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2059 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2060 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2061 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2062 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2063 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2064 ahc_inb(ahc, CCHADDR) 2065 | (ahc_inb(ahc, CCHADDR+1) << 8) 2066 | (ahc_inb(ahc, CCHADDR+2) << 16) 2067 | (ahc_inb(ahc, CCHADDR+3) << 24), 2068 ahc_inb(ahc, CCHCNT) 2069 | (ahc_inb(ahc, CCHCNT+1) << 8) 2070 | (ahc_inb(ahc, CCHCNT+2) << 16), 2071 ahc_inb(ahc, SCBPTR)); 2072 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2073 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2074 #if DDB > 0 2075 cpu_Debugger(); 2076 #endif 2077 #endif 2078 break; 2079 } 2080 #if NOT_YET 2081 /* XXX Fill these in later */ 2082 case MESG_BUFFER_BUSY: 2083 break; 2084 case MSGIN_PHASEMIS: 2085 break; 2086 #endif 2087 default: 2088 printf("ahc_intr: seqint, " 2089 "intstat == 0x%x, scsisigi = 0x%x\n", 2090 intstat, ahc_inb(ahc, SCSISIGI)); 2091 break; 2092 } 2093 2094 unpause: 2095 /* 2096 * The sequencer is paused immediately on 2097 * a SEQINT, so we should restart it when 2098 * we're done. 2099 */ 2100 unpause_sequencer(ahc); 2101 } 2102 2103 static void 2104 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2105 { 2106 u_int scb_index; 2107 u_int status; 2108 struct scb *scb; 2109 char cur_channel; 2110 char intr_channel; 2111 2112 if ((ahc->features & AHC_TWIN) != 0 2113 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2114 cur_channel = 'B'; 2115 else 2116 cur_channel = 'A'; 2117 intr_channel = cur_channel; 2118 2119 status = ahc_inb(ahc, SSTAT1); 2120 if (status == 0) { 2121 if ((ahc->features & AHC_TWIN) != 0) { 2122 /* Try the other channel */ 2123 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2124 status = ahc_inb(ahc, SSTAT1); 2125 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2126 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2127 } 2128 if (status == 0) { 2129 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2130 return; 2131 } 2132 } 2133 2134 scb_index = ahc_inb(ahc, SCB_TAG); 2135 if (scb_index < ahc->scb_data->numscbs) { 2136 scb = &ahc->scb_data->scbarray[scb_index]; 2137 if ((scb->flags & SCB_ACTIVE) == 0 2138 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2139 scb = NULL; 2140 } else 2141 scb = NULL; 2142 2143 if ((status & SCSIRSTI) != 0) { 2144 printf("%s: Someone reset channel %c\n", 2145 ahc_name(ahc), intr_channel); 2146 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2147 } else if ((status & SCSIPERR) != 0) { 2148 /* 2149 * Determine the bus phase and queue an appropriate message. 2150 * SCSIPERR is latched true as soon as a parity error 2151 * occurs. If the sequencer acked the transfer that 2152 * caused the parity error and the currently presented 2153 * transfer on the bus has correct parity, SCSIPERR will 2154 * be cleared by CLRSCSIPERR. Use this to determine if 2155 * we should look at the last phase the sequencer recorded, 2156 * or the current phase presented on the bus. 2157 */ 2158 u_int mesg_out; 2159 u_int curphase; 2160 u_int errorphase; 2161 u_int lastphase; 2162 int i; 2163 2164 lastphase = ahc_inb(ahc, LASTPHASE); 2165 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2166 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2167 /* 2168 * For all phases save DATA, the sequencer won't 2169 * automatically ack a byte that has a parity error 2170 * in it. So the only way that the current phase 2171 * could be 'data-in' is if the parity error is for 2172 * an already acked byte in the data phase. During 2173 * synchronous data-in transfers, we may actually 2174 * ack bytes before latching the current phase in 2175 * LASTPHASE, leading to the discrepancy between 2176 * curphase and lastphase. 2177 */ 2178 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2179 || curphase == P_DATAIN) 2180 errorphase = curphase; 2181 else 2182 errorphase = lastphase; 2183 2184 for (i = 0; i < num_phases; i++) { 2185 if (errorphase == phase_table[i].phase) 2186 break; 2187 } 2188 mesg_out = phase_table[i].mesg_out; 2189 if (scb != NULL) 2190 scsi_print_addr(scb->xs->sc_link); 2191 else 2192 printf("%s:%c:%d: ", ahc_name(ahc), 2193 intr_channel, 2194 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2195 2196 printf("parity error detected %s. " 2197 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2198 phase_table[i].phasemsg, 2199 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2200 ahc_inb(ahc, SCSIRATE)); 2201 2202 /* 2203 * We've set the hardware to assert ATN if we 2204 * get a parity error on "in" phases, so all we 2205 * need to do is stuff the message buffer with 2206 * the appropriate message. "In" phases have set 2207 * mesg_out to something other than MSG_NOP. 2208 */ 2209 if (mesg_out != MSG_NOOP) { 2210 if (ahc->msg_type != MSG_TYPE_NONE) 2211 ahc->send_msg_perror = TRUE; 2212 else 2213 ahc_outb(ahc, MSG_OUT, mesg_out); 2214 } 2215 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2216 unpause_sequencer(ahc); 2217 } else if ((status & BUSFREE) != 0 2218 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2219 /* 2220 * First look at what phase we were last in. 2221 * If its message out, chances are pretty good 2222 * that the busfree was in response to one of 2223 * our abort requests. 2224 */ 2225 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2226 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2227 u_int target = TCL_TARGET(saved_tcl); 2228 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2229 char channel = TCL_CHANNEL(ahc, saved_tcl); 2230 int printerror = 1; 2231 2232 ahc_outb(ahc, SCSISEQ, 2233 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2234 if (lastphase == P_MESGOUT) { 2235 u_int message; 2236 u_int tag; 2237 2238 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2239 tag = SCB_LIST_NULL; 2240 switch (message) { 2241 case MSG_ABORT_TAG: 2242 tag = scb->hscb->tag; 2243 /* FALLTRHOUGH */ 2244 case MSG_ABORT: 2245 scsi_print_addr(scb->xs->sc_link); 2246 printf("SCB %x - Abort %s Completed.\n", 2247 scb->hscb->tag, tag == SCB_LIST_NULL ? 2248 "" : "Tag"); 2249 ahc_abort_scbs(ahc, target, channel, 2250 TCL_LUN(saved_tcl), tag, 2251 ROLE_INITIATOR, 2252 XS_DRIVER_STUFFUP); 2253 printerror = 0; 2254 break; 2255 case MSG_BUS_DEV_RESET: 2256 { 2257 struct ahc_devinfo devinfo; 2258 2259 if (scb != NULL && 2260 (scb->xs->xs_control & XS_CTL_RESET) 2261 && ahc_match_scb(scb, target, channel, 2262 TCL_LUN(saved_tcl), 2263 SCB_LIST_NULL, 2264 ROLE_INITIATOR)) { 2265 ahcsetccbstatus(scb->xs, XS_NOERROR); 2266 } 2267 ahc_compile_devinfo(&devinfo, 2268 initiator_role_id, 2269 target, 2270 TCL_LUN(saved_tcl), 2271 channel, 2272 ROLE_INITIATOR); 2273 ahc_handle_devreset(ahc, &devinfo, 2274 XS_RESET, 2275 "Bus Device Reset", 2276 /*verbose_level*/0); 2277 printerror = 0; 2278 break; 2279 } 2280 default: 2281 break; 2282 } 2283 } 2284 if (printerror != 0) { 2285 int i; 2286 2287 if (scb != NULL) { 2288 u_int tag; 2289 2290 if ((scb->hscb->control & TAG_ENB) != 0) 2291 tag = scb->hscb->tag; 2292 else 2293 tag = SCB_LIST_NULL; 2294 ahc_abort_scbs(ahc, target, channel, 2295 SCB_LUN(scb), tag, 2296 ROLE_INITIATOR, 2297 XS_DRIVER_STUFFUP); 2298 scsi_print_addr(scb->xs->sc_link); 2299 } else { 2300 /* 2301 * We had not fully identified this connection, 2302 * so we cannot abort anything. 2303 */ 2304 printf("%s: ", ahc_name(ahc)); 2305 } 2306 for (i = 0; i < num_phases; i++) { 2307 if (lastphase == phase_table[i].phase) 2308 break; 2309 } 2310 printf("Unexpected busfree %s\n" 2311 "SEQADDR == 0x%x\n", 2312 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2313 | (ahc_inb(ahc, SEQADDR1) << 8)); 2314 } 2315 ahc_clear_msg_state(ahc); 2316 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2317 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2318 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2319 restart_sequencer(ahc); 2320 } else if ((status & SELTO) != 0) { 2321 u_int scbptr; 2322 2323 scbptr = ahc_inb(ahc, WAITING_SCBH); 2324 ahc_outb(ahc, SCBPTR, scbptr); 2325 scb_index = ahc_inb(ahc, SCB_TAG); 2326 2327 if (scb_index < ahc->scb_data->numscbs) { 2328 scb = &ahc->scb_data->scbarray[scb_index]; 2329 if ((scb->flags & SCB_ACTIVE) == 0) 2330 scb = NULL; 2331 } else 2332 scb = NULL; 2333 2334 if (scb == NULL) { 2335 printf("%s: ahc_intr - referenced scb not " 2336 "valid during SELTO scb(%d, %d)\n", 2337 ahc_name(ahc), scbptr, scb_index); 2338 } else { 2339 u_int tag; 2340 2341 tag = SCB_LIST_NULL; 2342 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2343 tag = scb->hscb->tag; 2344 2345 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2346 SCB_LUN(scb), tag, 2347 ROLE_INITIATOR, XS_SELTIMEOUT); 2348 } 2349 /* Stop the selection */ 2350 ahc_outb(ahc, SCSISEQ, 0); 2351 2352 /* No more pending messages */ 2353 ahc_clear_msg_state(ahc); 2354 2355 /* 2356 * Although the driver does not care about the 2357 * 'Selection in Progress' status bit, the busy 2358 * LED does. SELINGO is only cleared by a sucessful 2359 * selection, so we must manually clear it to ensure 2360 * the LED turns off just incase no future successful 2361 * selections occur (e.g. no devices on the bus). 2362 */ 2363 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2364 2365 /* Clear interrupt state */ 2366 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2367 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2368 restart_sequencer(ahc); 2369 } else { 2370 scsi_print_addr(scb->xs->sc_link); 2371 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2372 ahc_outb(ahc, CLRSINT1, status); 2373 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2374 unpause_sequencer(ahc); 2375 } 2376 } 2377 2378 static void 2379 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2380 { 2381 /* 2382 * We need to initiate transfer negotiations. 2383 * If our current and goal settings are identical, 2384 * we want to renegotiate due to a check condition. 2385 */ 2386 struct ahc_initiator_tinfo *tinfo; 2387 struct tmode_tstate *tstate; 2388 int dowide; 2389 int dosync; 2390 2391 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2392 devinfo->target, &tstate); 2393 dowide = tinfo->current.width != tinfo->goal.width; 2394 dosync = tinfo->current.period != tinfo->goal.period; 2395 2396 if (!dowide && !dosync) { 2397 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2398 dosync = tinfo->goal.period != 0; 2399 } 2400 2401 if (dowide) { 2402 ahc_construct_wdtr(ahc, tinfo->goal.width); 2403 } else if (dosync) { 2404 struct ahc_syncrate *rate; 2405 u_int period; 2406 u_int offset; 2407 2408 period = tinfo->goal.period; 2409 rate = ahc_devlimited_syncrate(ahc, &period); 2410 offset = tinfo->goal.offset; 2411 ahc_validate_offset(ahc, rate, &offset, 2412 tinfo->current.width); 2413 ahc_construct_sdtr(ahc, period, offset); 2414 } else { 2415 panic("ahc_intr: AWAITING_MSG for negotiation, " 2416 "but no negotiation needed\n"); 2417 } 2418 } 2419 2420 static void 2421 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2422 struct scb *scb) 2423 { 2424 /* 2425 * To facilitate adding multiple messages together, 2426 * each routine should increment the index and len 2427 * variables instead of setting them explicitly. 2428 */ 2429 ahc->msgout_index = 0; 2430 ahc->msgout_len = 0; 2431 2432 if ((scb->flags & SCB_DEVICE_RESET) == 0 2433 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2434 u_int identify_msg; 2435 2436 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2437 if ((scb->hscb->control & DISCENB) != 0) 2438 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2439 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2440 ahc->msgout_len++; 2441 2442 if ((scb->hscb->control & TAG_ENB) != 0) { 2443 /* XXX fvdl FreeBSD has tag action passed down */ 2444 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2445 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2446 ahc->msgout_len += 2; 2447 } 2448 } 2449 2450 if (scb->flags & SCB_DEVICE_RESET) { 2451 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2452 ahc->msgout_len++; 2453 scsi_print_addr(scb->xs->sc_link); 2454 printf("Bus Device Reset Message Sent\n"); 2455 } else if (scb->flags & SCB_ABORT) { 2456 if ((scb->hscb->control & TAG_ENB) != 0) 2457 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2458 else 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2460 ahc->msgout_len++; 2461 scsi_print_addr(scb->xs->sc_link); 2462 printf("Abort Message Sent\n"); 2463 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2464 ahc_build_transfer_msg(ahc, devinfo); 2465 } else { 2466 printf("ahc_intr: AWAITING_MSG for an SCB that " 2467 "does not have a waiting message"); 2468 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2469 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2470 ahc_inb(ahc, MSG_OUT), scb->flags); 2471 } 2472 2473 /* 2474 * Clear the MK_MESSAGE flag from the SCB so we aren't 2475 * asked to send this message again. 2476 */ 2477 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2478 ahc->msgout_index = 0; 2479 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2480 } 2481 2482 static void 2483 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2484 { 2485 /* 2486 * To facilitate adding multiple messages together, 2487 * each routine should increment the index and len 2488 * variables instead of setting them explicitly. 2489 */ 2490 ahc->msgout_index = 0; 2491 ahc->msgout_len = 0; 2492 2493 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2494 ahc_build_transfer_msg(ahc, devinfo); 2495 else 2496 panic("ahc_intr: AWAITING target message with no message"); 2497 2498 ahc->msgout_index = 0; 2499 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2500 } 2501 2502 static int 2503 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2504 { 2505 /* 2506 * What we care about here is if we had an 2507 * outstanding SDTR or WDTR message for this 2508 * target. If we did, this is a signal that 2509 * the target is refusing negotiation. 2510 */ 2511 struct scb *scb; 2512 u_int scb_index; 2513 u_int last_msg; 2514 int response = 0; 2515 2516 scb_index = ahc_inb(ahc, SCB_TAG); 2517 scb = &ahc->scb_data->scbarray[scb_index]; 2518 2519 /* Might be necessary */ 2520 last_msg = ahc_inb(ahc, LAST_MSG); 2521 2522 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2523 struct ahc_initiator_tinfo *tinfo; 2524 struct tmode_tstate *tstate; 2525 2526 #ifdef AHC_DEBUG_NEG 2527 /* note 8bit xfers */ 2528 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2529 "8bit transfers\n", ahc_name(ahc), 2530 devinfo->channel, devinfo->target); 2531 #endif 2532 ahc_set_width(ahc, devinfo, 2533 MSG_EXT_WDTR_BUS_8_BIT, 2534 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2535 /*paused*/TRUE, /*done*/TRUE); 2536 /* 2537 * No need to clear the sync rate. If the target 2538 * did not accept the command, our syncrate is 2539 * unaffected. If the target started the negotiation, 2540 * but rejected our response, we already cleared the 2541 * sync rate before sending our WDTR. 2542 */ 2543 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2544 devinfo->our_scsiid, 2545 devinfo->target, &tstate); 2546 if (tinfo->goal.period) { 2547 u_int period; 2548 2549 /* Start the sync negotiation */ 2550 period = tinfo->goal.period; 2551 ahc_devlimited_syncrate(ahc, &period); 2552 ahc->msgout_index = 0; 2553 ahc->msgout_len = 0; 2554 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2555 ahc->msgout_index = 0; 2556 response = 1; 2557 } 2558 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2559 /* note asynch xfers and clear flag */ 2560 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2561 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2562 /*paused*/TRUE, /*done*/TRUE); 2563 #ifdef AHC_DEBUG_NEG 2564 printf("%s:%c:%d: refuses synchronous negotiation. " 2565 "Using asynchronous transfers\n", 2566 ahc_name(ahc), 2567 devinfo->channel, devinfo->target); 2568 #endif 2569 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2570 printf("%s:%c:%d: refuses tagged commands. Performing " 2571 "non-tagged I/O\n", ahc_name(ahc), 2572 devinfo->channel, devinfo->target); 2573 2574 ahc_set_tags(ahc, devinfo, FALSE); 2575 2576 /* 2577 * Resend the identify for this CCB as the target 2578 * may believe that the selection is invalid otherwise. 2579 */ 2580 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2581 & ~MSG_SIMPLE_Q_TAG); 2582 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2583 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2584 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2585 2586 /* 2587 * Requeue all tagged commands for this target 2588 * currently in our posession so they can be 2589 * converted to untagged commands. 2590 */ 2591 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2592 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2593 ROLE_INITIATOR, SCB_REQUEUE, 2594 SEARCH_COMPLETE); 2595 } else { 2596 /* 2597 * Otherwise, we ignore it. 2598 */ 2599 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2600 ahc_name(ahc), devinfo->channel, devinfo->target, 2601 last_msg); 2602 } 2603 return (response); 2604 } 2605 2606 static void 2607 ahc_clear_msg_state(struct ahc_softc *ahc) 2608 { 2609 ahc->msgout_len = 0; 2610 ahc->msgin_index = 0; 2611 ahc->msg_type = MSG_TYPE_NONE; 2612 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2613 } 2614 2615 static void 2616 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2617 { 2618 struct ahc_devinfo devinfo; 2619 u_int bus_phase; 2620 int end_session; 2621 2622 ahc_fetch_devinfo(ahc, &devinfo); 2623 end_session = FALSE; 2624 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2625 2626 reswitch: 2627 switch (ahc->msg_type) { 2628 case MSG_TYPE_INITIATOR_MSGOUT: 2629 { 2630 int lastbyte; 2631 int phasemis; 2632 int msgdone; 2633 2634 if (ahc->msgout_len == 0) 2635 panic("REQINIT interrupt with no active message"); 2636 2637 phasemis = bus_phase != P_MESGOUT; 2638 if (phasemis) { 2639 if (bus_phase == P_MESGIN) { 2640 /* 2641 * Change gears and see if 2642 * this messages is of interest to 2643 * us or should be passed back to 2644 * the sequencer. 2645 */ 2646 ahc_outb(ahc, CLRSINT1, CLRATNO); 2647 ahc->send_msg_perror = FALSE; 2648 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2649 ahc->msgin_index = 0; 2650 goto reswitch; 2651 } 2652 end_session = TRUE; 2653 break; 2654 } 2655 2656 if (ahc->send_msg_perror) { 2657 ahc_outb(ahc, CLRSINT1, CLRATNO); 2658 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2659 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2660 break; 2661 } 2662 2663 msgdone = ahc->msgout_index == ahc->msgout_len; 2664 if (msgdone) { 2665 /* 2666 * The target has requested a retry. 2667 * Re-assert ATN, reset our message index to 2668 * 0, and try again. 2669 */ 2670 ahc->msgout_index = 0; 2671 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2672 } 2673 2674 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2675 if (lastbyte) { 2676 /* Last byte is signified by dropping ATN */ 2677 ahc_outb(ahc, CLRSINT1, CLRATNO); 2678 } 2679 2680 /* 2681 * Clear our interrupt status and present 2682 * the next byte on the bus. 2683 */ 2684 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2685 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2686 break; 2687 } 2688 case MSG_TYPE_INITIATOR_MSGIN: 2689 { 2690 int phasemis; 2691 int message_done; 2692 2693 phasemis = bus_phase != P_MESGIN; 2694 2695 if (phasemis) { 2696 ahc->msgin_index = 0; 2697 if (bus_phase == P_MESGOUT 2698 && (ahc->send_msg_perror == TRUE 2699 || (ahc->msgout_len != 0 2700 && ahc->msgout_index == 0))) { 2701 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2702 goto reswitch; 2703 } 2704 end_session = TRUE; 2705 break; 2706 } 2707 2708 /* Pull the byte in without acking it */ 2709 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2710 2711 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2712 2713 if (message_done) { 2714 /* 2715 * Clear our incoming message buffer in case there 2716 * is another message following this one. 2717 */ 2718 ahc->msgin_index = 0; 2719 2720 /* 2721 * If this message illicited a response, 2722 * assert ATN so the target takes us to the 2723 * message out phase. 2724 */ 2725 if (ahc->msgout_len != 0) 2726 ahc_outb(ahc, SCSISIGO, 2727 ahc_inb(ahc, SCSISIGO) | ATNO); 2728 } else 2729 ahc->msgin_index++; 2730 2731 /* Ack the byte */ 2732 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2733 ahc_inb(ahc, SCSIDATL); 2734 break; 2735 } 2736 case MSG_TYPE_TARGET_MSGIN: 2737 { 2738 int msgdone; 2739 int msgout_request; 2740 2741 if (ahc->msgout_len == 0) 2742 panic("Target MSGIN with no active message"); 2743 2744 /* 2745 * If we interrupted a mesgout session, the initiator 2746 * will not know this until our first REQ. So, we 2747 * only honor mesgout requests after we've sent our 2748 * first byte. 2749 */ 2750 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2751 && ahc->msgout_index > 0) 2752 msgout_request = TRUE; 2753 else 2754 msgout_request = FALSE; 2755 2756 if (msgout_request) { 2757 2758 /* 2759 * Change gears and see if 2760 * this messages is of interest to 2761 * us or should be passed back to 2762 * the sequencer. 2763 */ 2764 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2765 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2766 ahc->msgin_index = 0; 2767 /* Dummy read to REQ for first byte */ 2768 ahc_inb(ahc, SCSIDATL); 2769 ahc_outb(ahc, SXFRCTL0, 2770 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2771 break; 2772 } 2773 2774 msgdone = ahc->msgout_index == ahc->msgout_len; 2775 if (msgdone) { 2776 ahc_outb(ahc, SXFRCTL0, 2777 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2778 end_session = TRUE; 2779 break; 2780 } 2781 2782 /* 2783 * Present the next byte on the bus. 2784 */ 2785 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2786 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2787 break; 2788 } 2789 case MSG_TYPE_TARGET_MSGOUT: 2790 { 2791 int lastbyte; 2792 int msgdone; 2793 2794 /* 2795 * The initiator signals that this is 2796 * the last byte by dropping ATN. 2797 */ 2798 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2799 2800 /* 2801 * Read the latched byte, but turn off SPIOEN first 2802 * so that we don't inadvertantly cause a REQ for the 2803 * next byte. 2804 */ 2805 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2806 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2807 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2808 if (msgdone == MSGLOOP_TERMINATED) { 2809 /* 2810 * The message is *really* done in that it caused 2811 * us to go to bus free. The sequencer has already 2812 * been reset at this point, so pull the ejection 2813 * handle. 2814 */ 2815 return; 2816 } 2817 2818 ahc->msgin_index++; 2819 2820 /* 2821 * XXX Read spec about initiator dropping ATN too soon 2822 * and use msgdone to detect it. 2823 */ 2824 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2825 ahc->msgin_index = 0; 2826 2827 /* 2828 * If this message illicited a response, transition 2829 * to the Message in phase and send it. 2830 */ 2831 if (ahc->msgout_len != 0) { 2832 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2833 ahc_outb(ahc, SXFRCTL0, 2834 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2835 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2836 ahc->msgin_index = 0; 2837 break; 2838 } 2839 } 2840 2841 if (lastbyte) 2842 end_session = TRUE; 2843 else { 2844 /* Ask for the next byte. */ 2845 ahc_outb(ahc, SXFRCTL0, 2846 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2847 } 2848 2849 break; 2850 } 2851 default: 2852 panic("Unknown REQINIT message type"); 2853 } 2854 2855 if (end_session) { 2856 ahc_clear_msg_state(ahc); 2857 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2858 } else 2859 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2860 } 2861 2862 /* 2863 * See if we sent a particular extended message to the target. 2864 * If "full" is true, the target saw the full message. 2865 * If "full" is false, the target saw at least the first 2866 * byte of the message. 2867 */ 2868 static int 2869 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2870 { 2871 int found; 2872 int index; 2873 2874 found = FALSE; 2875 index = 0; 2876 2877 while (index < ahc->msgout_len) { 2878 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2879 2880 /* Found a candidate */ 2881 if (ahc->msgout_buf[index+2] == msgtype) { 2882 u_int end_index; 2883 2884 end_index = index + 1 2885 + ahc->msgout_buf[index + 1]; 2886 if (full) { 2887 if (ahc->msgout_index > end_index) 2888 found = TRUE; 2889 } else if (ahc->msgout_index > index) 2890 found = TRUE; 2891 } 2892 break; 2893 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2894 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2895 2896 /* Skip tag type and tag id or residue param*/ 2897 index += 2; 2898 } else { 2899 /* Single byte message */ 2900 index++; 2901 } 2902 } 2903 return (found); 2904 } 2905 2906 static int 2907 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2908 struct ahc_devinfo *devinfo) 2909 { 2910 struct ahc_initiator_tinfo *tinfo; 2911 struct tmode_tstate *tstate; 2912 int reject; 2913 int done; 2914 int response; 2915 u_int targ_scsirate; 2916 2917 done = MSGLOOP_IN_PROG; 2918 response = FALSE; 2919 reject = FALSE; 2920 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2921 devinfo->target, &tstate); 2922 targ_scsirate = tinfo->scsirate; 2923 2924 /* 2925 * Parse as much of the message as is availible, 2926 * rejecting it if we don't support it. When 2927 * the entire message is availible and has been 2928 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2929 * that we have parsed an entire message. 2930 * 2931 * In the case of extended messages, we accept the length 2932 * byte outright and perform more checking once we know the 2933 * extended message type. 2934 */ 2935 switch (ahc->msgin_buf[0]) { 2936 case MSG_MESSAGE_REJECT: 2937 response = ahc_handle_msg_reject(ahc, devinfo); 2938 /* FALLTHROUGH */ 2939 case MSG_NOOP: 2940 done = MSGLOOP_MSGCOMPLETE; 2941 break; 2942 case MSG_IGN_WIDE_RESIDUE: 2943 { 2944 /* Wait for the whole message */ 2945 if (ahc->msgin_index >= 1) { 2946 if (ahc->msgin_buf[1] != 1 2947 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2948 reject = TRUE; 2949 done = MSGLOOP_MSGCOMPLETE; 2950 } else 2951 ahc_handle_ign_wide_residue(ahc, devinfo); 2952 } 2953 break; 2954 } 2955 case MSG_EXTENDED: 2956 { 2957 /* Wait for enough of the message to begin validation */ 2958 if (ahc->msgin_index < 2) 2959 break; 2960 switch (ahc->msgin_buf[2]) { 2961 case MSG_EXT_SDTR: 2962 { 2963 struct ahc_syncrate *syncrate; 2964 u_int period; 2965 u_int offset; 2966 u_int saved_offset; 2967 2968 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2969 reject = TRUE; 2970 break; 2971 } 2972 2973 /* 2974 * Wait until we have both args before validating 2975 * and acting on this message. 2976 * 2977 * Add one to MSG_EXT_SDTR_LEN to account for 2978 * the extended message preamble. 2979 */ 2980 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2981 break; 2982 2983 period = ahc->msgin_buf[3]; 2984 saved_offset = offset = ahc->msgin_buf[4]; 2985 syncrate = ahc_devlimited_syncrate(ahc, &period); 2986 ahc_validate_offset(ahc, syncrate, &offset, 2987 targ_scsirate & WIDEXFER); 2988 ahc_set_syncrate(ahc, devinfo, 2989 syncrate, period, offset, 2990 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2991 /*paused*/TRUE, /*done*/TRUE); 2992 2993 /* 2994 * See if we initiated Sync Negotiation 2995 * and didn't have to fall down to async 2996 * transfers. 2997 */ 2998 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2999 /* We started it */ 3000 if (saved_offset != offset) { 3001 /* Went too low - force async */ 3002 reject = TRUE; 3003 } 3004 } else { 3005 /* 3006 * Send our own SDTR in reply 3007 */ 3008 ahc->msgout_index = 0; 3009 ahc->msgout_len = 0; 3010 ahc_construct_sdtr(ahc, period, offset); 3011 ahc->msgout_index = 0; 3012 response = TRUE; 3013 } 3014 done = MSGLOOP_MSGCOMPLETE; 3015 break; 3016 } 3017 case MSG_EXT_WDTR: 3018 { 3019 u_int bus_width; 3020 u_int sending_reply; 3021 3022 sending_reply = FALSE; 3023 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3024 reject = TRUE; 3025 break; 3026 } 3027 3028 /* 3029 * Wait until we have our arg before validating 3030 * and acting on this message. 3031 * 3032 * Add one to MSG_EXT_WDTR_LEN to account for 3033 * the extended message preamble. 3034 */ 3035 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3036 break; 3037 3038 bus_width = ahc->msgin_buf[3]; 3039 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3040 /* 3041 * Don't send a WDTR back to the 3042 * target, since we asked first. 3043 */ 3044 switch (bus_width){ 3045 default: 3046 /* 3047 * How can we do anything greater 3048 * than 16bit transfers on a 16bit 3049 * bus? 3050 */ 3051 reject = TRUE; 3052 printf("%s: target %d requested %dBit " 3053 "transfers. Rejecting...\n", 3054 ahc_name(ahc), devinfo->target, 3055 8 * (0x01 << bus_width)); 3056 /* FALLTHROUGH */ 3057 case MSG_EXT_WDTR_BUS_8_BIT: 3058 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3059 break; 3060 case MSG_EXT_WDTR_BUS_16_BIT: 3061 break; 3062 } 3063 } else { 3064 /* 3065 * Send our own WDTR in reply 3066 */ 3067 switch (bus_width) { 3068 default: 3069 if (ahc->features & AHC_WIDE) { 3070 /* Respond Wide */ 3071 bus_width = 3072 MSG_EXT_WDTR_BUS_16_BIT; 3073 break; 3074 } 3075 /* FALLTHROUGH */ 3076 case MSG_EXT_WDTR_BUS_8_BIT: 3077 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3078 break; 3079 } 3080 ahc->msgout_index = 0; 3081 ahc->msgout_len = 0; 3082 ahc_construct_wdtr(ahc, bus_width); 3083 ahc->msgout_index = 0; 3084 response = TRUE; 3085 sending_reply = TRUE; 3086 } 3087 ahc_set_width(ahc, devinfo, bus_width, 3088 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3089 /*paused*/TRUE, /*done*/TRUE); 3090 3091 /* After a wide message, we are async */ 3092 ahc_set_syncrate(ahc, devinfo, 3093 /*syncrate*/NULL, /*period*/0, 3094 /*offset*/0, AHC_TRANS_ACTIVE, 3095 /*paused*/TRUE, /*done*/FALSE); 3096 if (sending_reply == FALSE && reject == FALSE) { 3097 3098 if (tinfo->goal.period) { 3099 struct ahc_syncrate *rate; 3100 u_int period; 3101 u_int offset; 3102 3103 /* Start the sync negotiation */ 3104 period = tinfo->goal.period; 3105 rate = ahc_devlimited_syncrate(ahc, 3106 &period); 3107 offset = tinfo->goal.offset; 3108 ahc_validate_offset(ahc, rate, &offset, 3109 tinfo->current.width); 3110 ahc->msgout_index = 0; 3111 ahc->msgout_len = 0; 3112 ahc_construct_sdtr(ahc, period, offset); 3113 ahc->msgout_index = 0; 3114 response = TRUE; 3115 } 3116 } 3117 done = MSGLOOP_MSGCOMPLETE; 3118 break; 3119 } 3120 default: 3121 /* Unknown extended message. Reject it. */ 3122 reject = TRUE; 3123 break; 3124 } 3125 break; 3126 } 3127 case MSG_BUS_DEV_RESET: 3128 ahc_handle_devreset(ahc, devinfo, 3129 XS_RESET, "Bus Device Reset Received", 3130 /*verbose_level*/0); 3131 restart_sequencer(ahc); 3132 done = MSGLOOP_TERMINATED; 3133 break; 3134 case MSG_ABORT_TAG: 3135 case MSG_ABORT: 3136 case MSG_CLEAR_QUEUE: 3137 /* Target mode messages */ 3138 if (devinfo->role != ROLE_TARGET) { 3139 reject = TRUE; 3140 break; 3141 } 3142 #if AHC_TARGET_MODE 3143 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3144 devinfo->lun, 3145 ahc->msgin_buf[0] == MSG_ABORT_TAG 3146 ? SCB_LIST_NULL 3147 : ahc_inb(ahc, INITIATOR_TAG), 3148 ROLE_TARGET, XS_DRIVER_STUFFUP); 3149 3150 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3151 if (tstate != NULL) { 3152 struct tmode_lstate* lstate; 3153 3154 lstate = tstate->enabled_luns[devinfo->lun]; 3155 if (lstate != NULL) { 3156 ahc_queue_lstate_event(ahc, lstate, 3157 devinfo->our_scsiid, 3158 ahc->msgin_buf[0], 3159 /*arg*/0); 3160 ahc_send_lstate_events(ahc, lstate); 3161 } 3162 } 3163 done = MSGLOOP_MSGCOMPLETE; 3164 #else 3165 panic("ahc: got target mode message"); 3166 #endif 3167 break; 3168 case MSG_TERM_IO_PROC: 3169 default: 3170 reject = TRUE; 3171 break; 3172 } 3173 3174 if (reject) { 3175 /* 3176 * Setup to reject the message. 3177 */ 3178 ahc->msgout_index = 0; 3179 ahc->msgout_len = 1; 3180 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3181 done = MSGLOOP_MSGCOMPLETE; 3182 response = TRUE; 3183 } 3184 3185 if (done != MSGLOOP_IN_PROG && !response) 3186 /* Clear the outgoing message buffer */ 3187 ahc->msgout_len = 0; 3188 3189 return (done); 3190 } 3191 3192 static void 3193 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3194 { 3195 u_int scb_index; 3196 struct scb *scb; 3197 3198 scb_index = ahc_inb(ahc, SCB_TAG); 3199 scb = &ahc->scb_data->scbarray[scb_index]; 3200 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3201 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3202 /* 3203 * Ignore the message if we haven't 3204 * seen an appropriate data phase yet. 3205 */ 3206 } else { 3207 /* 3208 * If the residual occurred on the last 3209 * transfer and the transfer request was 3210 * expected to end on an odd count, do 3211 * nothing. Otherwise, subtract a byte 3212 * and update the residual count accordingly. 3213 */ 3214 u_int resid_sgcnt; 3215 3216 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3217 if (resid_sgcnt == 0 3218 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3219 /* 3220 * If the residual occurred on the last 3221 * transfer and the transfer request was 3222 * expected to end on an odd count, do 3223 * nothing. 3224 */ 3225 } else { 3226 u_int data_cnt; 3227 u_int32_t data_addr; 3228 u_int sg_index; 3229 3230 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3231 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3232 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3233 3234 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3235 | (ahc_inb(ahc, SHADDR + 2) << 16) 3236 | (ahc_inb(ahc, SHADDR + 1) << 8) 3237 | (ahc_inb(ahc, SHADDR)); 3238 3239 data_cnt += 1; 3240 data_addr -= 1; 3241 3242 sg_index = scb->sg_count - resid_sgcnt; 3243 3244 if (sg_index != 0 3245 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3246 u_int32_t sg_addr; 3247 3248 sg_index--; 3249 data_cnt = 1; 3250 data_addr = le32toh(scb->sg_list[sg_index].addr) 3251 + le32toh(scb->sg_list[sg_index].len) 3252 - 1; 3253 3254 /* 3255 * The physical address base points to the 3256 * second entry as it is always used for 3257 * calculating the "next S/G pointer". 3258 */ 3259 sg_addr = scb->sg_list_phys 3260 + (sg_index* sizeof(*scb->sg_list)); 3261 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3262 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3263 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3264 ahc_outb(ahc, SG_NEXT, sg_addr); 3265 } 3266 3267 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3268 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3269 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3270 3271 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3272 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3273 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3274 ahc_outb(ahc, SHADDR, data_addr); 3275 } 3276 } 3277 } 3278 3279 static void 3280 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3281 int status, char *message, 3282 int verbose_level) 3283 { 3284 int found; 3285 3286 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3287 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3288 status); 3289 3290 /* 3291 * Go back to async/narrow transfers and renegotiate. 3292 * ahc_set_width and ahc_set_syncrate can cope with NULL 3293 * paths. 3294 */ 3295 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3296 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3297 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3298 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3299 /*paused*/TRUE, /*done*/FALSE); 3300 3301 if (message != NULL && (verbose_level <= 0)) 3302 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3303 message, devinfo->channel, devinfo->target, found); 3304 } 3305 3306 /* 3307 * We have an scb which has been processed by the 3308 * adaptor, now we look to see how the operation 3309 * went. 3310 */ 3311 static void 3312 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3313 { 3314 struct scsipi_xfer *xs; 3315 struct scsipi_link *sc_link; 3316 int requeue = 0; 3317 int target; 3318 3319 3320 xs = scb->xs; 3321 sc_link = xs->sc_link; 3322 LIST_REMOVE(scb, plinks); 3323 3324 untimeout(ahc_timeout, (caddr_t)scb); 3325 3326 #ifdef AHC_DEBUG 3327 if (ahc_debug & AHC_SHOWCMDS) { 3328 scsi_print_addr(sc_link); 3329 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3330 scb->hscb->tag); 3331 } 3332 #endif 3333 3334 target = sc_link->scsipi_scsi.target; 3335 3336 if (xs->datalen) { 3337 int op; 3338 3339 if (xs->xs_control & XS_CTL_DATA_IN) 3340 op = BUS_DMASYNC_POSTREAD; 3341 else 3342 op = BUS_DMASYNC_POSTWRITE; 3343 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3344 scb->dmamap->dm_mapsize, op); 3345 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3346 } 3347 3348 /* 3349 * Unbusy this target/channel/lun. 3350 * XXX if we are holding two commands per lun, 3351 * send the next command. 3352 */ 3353 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3354 3355 /* 3356 * If the recovery SCB completes, we have to be 3357 * out of our timeout. 3358 */ 3359 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3360 3361 struct scb *scbp; 3362 3363 /* 3364 * We were able to complete the command successfully, 3365 * so reinstate the timeouts for all other pending 3366 * commands. 3367 */ 3368 scbp = ahc->pending_ccbs.lh_first; 3369 while (scbp != NULL) { 3370 struct scsipi_xfer *txs = scbp->xs; 3371 3372 if (!(txs->xs_control & XS_CTL_POLL)) { 3373 timeout(ahc_timeout, scbp, 3374 (scbp->xs->timeout * hz)/1000); 3375 } 3376 scbp = LIST_NEXT(scbp, plinks); 3377 } 3378 3379 /* 3380 * Ensure that we didn't put a second instance of this 3381 * SCB into the QINFIFO. 3382 */ 3383 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3384 SCB_LUN(scb), scb->hscb->tag, 3385 ROLE_INITIATOR, /*status*/0, 3386 SEARCH_REMOVE); 3387 if (xs->error != XS_NOERROR) 3388 ahcsetccbstatus(xs, XS_TIMEOUT); 3389 scsi_print_addr(xs->sc_link); 3390 printf("no longer in timeout, status = %x\n", xs->status); 3391 } 3392 3393 if (xs->error != XS_NOERROR) { 3394 /* Don't clobber any existing error state */ 3395 } else if ((scb->flags & SCB_SENSE) != 0) { 3396 /* 3397 * We performed autosense retrieval. 3398 * 3399 * bzero the sense data before having 3400 * the drive fill it. The SCSI spec mandates 3401 * that any untransfered data should be 3402 * assumed to be zero. Complete the 'bounce' 3403 * of sense information through buffers accessible 3404 * via bus-space by copying it into the clients 3405 * csio. 3406 */ 3407 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3408 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3409 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3410 xs->error = XS_SENSE; 3411 } 3412 if (scb->flags & SCB_FREEZE_QUEUE) { 3413 ahc->devqueue_blocked[target]--; 3414 scb->flags &= ~SCB_FREEZE_QUEUE; 3415 } 3416 3417 requeue = scb->flags & SCB_REQUEUE; 3418 ahcfreescb(ahc, scb); 3419 3420 if (requeue) { 3421 /* 3422 * Re-insert at the front of the private queue to 3423 * preserve order. 3424 */ 3425 int s; 3426 3427 s = splbio(); 3428 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3429 splx(s); 3430 } else { 3431 xs->xs_status |= XS_STS_DONE; 3432 scsipi_done(xs); 3433 } 3434 3435 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3436 ahc_action(xs); 3437 } 3438 3439 /* 3440 * Determine the number of SCBs available on the controller 3441 */ 3442 int 3443 ahc_probe_scbs(struct ahc_softc *ahc) { 3444 int i; 3445 3446 for (i = 0; i < AHC_SCB_MAX; i++) { 3447 ahc_outb(ahc, SCBPTR, i); 3448 ahc_outb(ahc, SCB_CONTROL, i); 3449 if (ahc_inb(ahc, SCB_CONTROL) != i) 3450 break; 3451 ahc_outb(ahc, SCBPTR, 0); 3452 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3453 break; 3454 } 3455 return (i); 3456 } 3457 3458 /* 3459 * Start the board, ready for normal operation 3460 */ 3461 int 3462 ahc_init(struct ahc_softc *ahc) 3463 { 3464 int max_targ = 15; 3465 int i; 3466 int term; 3467 u_int scsi_conf; 3468 u_int scsiseq_template; 3469 u_int ultraenb; 3470 u_int discenable; 3471 u_int tagenable; 3472 size_t driver_data_size; 3473 u_int32_t physaddr; 3474 3475 #ifdef AHC_PRINT_SRAM 3476 printf("Scratch Ram:"); 3477 for (i = 0x20; i < 0x5f; i++) { 3478 if (((i % 8) == 0) && (i != 0)) { 3479 printf ("\n "); 3480 } 3481 printf (" 0x%x", ahc_inb(ahc, i)); 3482 } 3483 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3484 for (i = 0x70; i < 0x7f; i++) { 3485 if (((i % 8) == 0) && (i != 0)) { 3486 printf ("\n "); 3487 } 3488 printf (" 0x%x", ahc_inb(ahc, i)); 3489 } 3490 } 3491 printf ("\n"); 3492 #endif 3493 3494 /* 3495 * Assume we have a board at this stage and it has been reset. 3496 */ 3497 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3498 ahc->our_id = ahc->our_id_b = 7; 3499 3500 /* 3501 * Default to allowing initiator operations. 3502 */ 3503 ahc->flags |= AHC_INITIATORMODE; 3504 3505 /* 3506 * DMA tag for our command fifos and other data in system memory 3507 * the card's sequencer must be able to access. For initiator 3508 * roles, we need to allocate space for the qinfifo, qoutfifo, 3509 * and untagged_scb arrays each of which are composed of 256 3510 * 1 byte elements. When providing for the target mode role, 3511 * we additionally must provide space for the incoming target 3512 * command fifo. 3513 */ 3514 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3515 3516 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3517 ahc->sc_dmaflags, 3518 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3519 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3520 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3521 return (ENOMEM); 3522 3523 ahc->init_level++; 3524 3525 /* Allocate SCB data now that parent_dmat is initialized */ 3526 if (ahc->scb_data->maxhscbs == 0) 3527 if (ahcinitscbdata(ahc) != 0) 3528 return (ENOMEM); 3529 3530 ahc->qinfifo = &ahc->qoutfifo[256]; 3531 ahc->untagged_scbs = &ahc->qinfifo[256]; 3532 /* There are no untagged SCBs active yet. */ 3533 for (i = 0; i < 256; i++) 3534 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3535 3536 /* All of our queues are empty */ 3537 for (i = 0; i < 256; i++) 3538 ahc->qoutfifo[i] = SCB_LIST_NULL; 3539 3540 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3541 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3542 3543 /* 3544 * Allocate a tstate to house information for our 3545 * initiator presence on the bus as well as the user 3546 * data for any target mode initiator. 3547 */ 3548 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3549 printf("%s: unable to allocate tmode_tstate. " 3550 "Failing attach\n", ahc_name(ahc)); 3551 return (-1); 3552 } 3553 3554 if ((ahc->features & AHC_TWIN) != 0) { 3555 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3556 printf("%s: unable to allocate tmode_tstate. " 3557 "Failing attach\n", ahc_name(ahc)); 3558 return (-1); 3559 } 3560 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3561 ahc->our_id, ahc->our_id_b, 3562 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3563 } else { 3564 if ((ahc->features & AHC_WIDE) != 0) { 3565 printf("Wide "); 3566 } else { 3567 printf("Single "); 3568 } 3569 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3570 } 3571 3572 ahc_outb(ahc, SEQ_FLAGS, 0); 3573 3574 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3575 ahc->flags |= AHC_PAGESCBS; 3576 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3577 } else { 3578 ahc->flags &= ~AHC_PAGESCBS; 3579 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3580 } 3581 3582 #ifdef AHC_DEBUG 3583 if (ahc_debug & AHC_SHOWMISC) { 3584 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3585 "ahc_dma %d bytes\n", 3586 ahc_name(ahc), 3587 sizeof(struct hardware_scb), 3588 sizeof(struct scb), 3589 sizeof(struct ahc_dma_seg)); 3590 } 3591 #endif /* AHC_DEBUG */ 3592 3593 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3594 if (ahc->features & AHC_TWIN) { 3595 3596 /* 3597 * The device is gated to channel B after a chip reset, 3598 * so set those values first 3599 */ 3600 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3601 if ((ahc->features & AHC_ULTRA2) != 0) 3602 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3603 else 3604 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3605 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3606 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3607 |term|ENSTIMER|ACTNEGEN); 3608 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3609 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3610 3611 if ((scsi_conf & RESET_SCSI) != 0 3612 && (ahc->flags & AHC_INITIATORMODE) != 0) 3613 ahc->flags |= AHC_RESET_BUS_B; 3614 3615 /* Select Channel A */ 3616 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3617 } 3618 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3619 if ((ahc->features & AHC_ULTRA2) != 0) 3620 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3621 else 3622 ahc_outb(ahc, SCSIID, ahc->our_id); 3623 scsi_conf = ahc_inb(ahc, SCSICONF); 3624 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3625 |term 3626 |ENSTIMER|ACTNEGEN); 3627 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3628 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3629 3630 if ((scsi_conf & RESET_SCSI) != 0 3631 && (ahc->flags & AHC_INITIATORMODE) != 0) 3632 ahc->flags |= AHC_RESET_BUS_A; 3633 3634 /* 3635 * Look at the information that board initialization or 3636 * the board bios has left us. 3637 */ 3638 ultraenb = 0; 3639 tagenable = ALL_TARGETS_MASK; 3640 3641 /* Grab the disconnection disable table and invert it for our needs */ 3642 if (ahc->flags & AHC_USEDEFAULTS) { 3643 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3644 "device parameters\n", ahc_name(ahc)); 3645 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3646 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3647 discenable = ALL_TARGETS_MASK; 3648 if ((ahc->features & AHC_ULTRA) != 0) 3649 ultraenb = ALL_TARGETS_MASK; 3650 } else { 3651 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3652 | ahc_inb(ahc, DISC_DSB)); 3653 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3654 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3655 | ahc_inb(ahc, ULTRA_ENB); 3656 } 3657 3658 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3659 max_targ = 7; 3660 3661 for (i = 0; i <= max_targ; i++) { 3662 struct ahc_initiator_tinfo *tinfo; 3663 struct tmode_tstate *tstate; 3664 u_int our_id; 3665 u_int target_id; 3666 char channel; 3667 3668 channel = 'A'; 3669 our_id = ahc->our_id; 3670 target_id = i; 3671 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3672 channel = 'B'; 3673 our_id = ahc->our_id_b; 3674 target_id = i % 8; 3675 } 3676 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3677 target_id, &tstate); 3678 /* Default to async narrow across the board */ 3679 bzero(tinfo, sizeof(*tinfo)); 3680 if (ahc->flags & AHC_USEDEFAULTS) { 3681 if ((ahc->features & AHC_WIDE) != 0) 3682 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3683 3684 /* 3685 * These will be truncated when we determine the 3686 * connection type we have with the target. 3687 */ 3688 tinfo->user.period = ahc_syncrates->period; 3689 tinfo->user.offset = ~0; 3690 } else { 3691 u_int scsirate; 3692 u_int16_t mask; 3693 3694 /* Take the settings leftover in scratch RAM. */ 3695 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3696 mask = (0x01 << i); 3697 if ((ahc->features & AHC_ULTRA2) != 0) { 3698 u_int offset; 3699 u_int maxsync; 3700 3701 if ((scsirate & SOFS) == 0x0F) { 3702 /* 3703 * Haven't negotiated yet, 3704 * so the format is different. 3705 */ 3706 scsirate = (scsirate & SXFR) >> 4 3707 | (ultraenb & mask) 3708 ? 0x08 : 0x0 3709 | (scsirate & WIDEXFER); 3710 offset = MAX_OFFSET_ULTRA2; 3711 } else 3712 offset = ahc_inb(ahc, TARG_OFFSET + i); 3713 maxsync = AHC_SYNCRATE_ULTRA2; 3714 if ((ahc->features & AHC_DT) != 0) 3715 maxsync = AHC_SYNCRATE_DT; 3716 tinfo->user.period = 3717 ahc_find_period(ahc, scsirate, maxsync); 3718 if (offset == 0) 3719 tinfo->user.period = 0; 3720 else 3721 tinfo->user.offset = ~0; 3722 } else if ((scsirate & SOFS) != 0) { 3723 tinfo->user.period = 3724 ahc_find_period(ahc, scsirate, 3725 (ultraenb & mask) 3726 ? AHC_SYNCRATE_ULTRA 3727 : AHC_SYNCRATE_FAST); 3728 if (tinfo->user.period != 0) 3729 tinfo->user.offset = ~0; 3730 } 3731 if ((scsirate & WIDEXFER) != 0 3732 && (ahc->features & AHC_WIDE) != 0) 3733 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3734 } 3735 tinfo->goal = tinfo->user; /* force negotiation */ 3736 tstate->ultraenb = ultraenb; 3737 tstate->discenable = discenable; 3738 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3739 } 3740 ahc->user_discenable = discenable; 3741 ahc->user_tagenable = tagenable; 3742 3743 /* 3744 * Tell the sequencer where it can find our arrays in memory. 3745 */ 3746 physaddr = ahc->scb_data->hscb_busaddr; 3747 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3748 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3749 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3750 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3751 3752 physaddr = ahc->shared_data_busaddr; 3753 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3754 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3755 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3756 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3757 3758 /* Target mode incomding command fifo */ 3759 physaddr += 3 * 256 * sizeof(u_int8_t); 3760 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3761 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3762 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3763 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3764 3765 /* 3766 * Initialize the group code to command length table. 3767 * This overrides the values in TARG_SCSIRATE, so only 3768 * setup the table after we have processed that information. 3769 */ 3770 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3771 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3772 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3773 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3774 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3775 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3778 3779 /* Tell the sequencer of our initial queue positions */ 3780 ahc_outb(ahc, KERNEL_QINPOS, 0); 3781 ahc_outb(ahc, QINPOS, 0); 3782 ahc_outb(ahc, QOUTPOS, 0); 3783 3784 #ifdef AHC_DEBUG 3785 if (ahc_debug & AHC_SHOWMISC) 3786 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3787 discenable, ultraenb); 3788 #endif 3789 3790 /* Don't have any special messages to send to targets */ 3791 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3792 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3793 3794 /* 3795 * Use the built in queue management registers 3796 * if they are available. 3797 */ 3798 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3799 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3800 ahc_outb(ahc, SDSCB_QOFF, 0); 3801 ahc_outb(ahc, SNSCB_QOFF, 0); 3802 ahc_outb(ahc, HNSCB_QOFF, 0); 3803 } 3804 3805 3806 /* We don't have any waiting selections */ 3807 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3808 3809 /* Our disconnection list is empty too */ 3810 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3811 3812 /* Message out buffer starts empty */ 3813 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3814 3815 /* 3816 * Setup the allowed SCSI Sequences based on operational mode. 3817 * If we are a target, we'll enalbe select in operations once 3818 * we've had a lun enabled. 3819 */ 3820 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3821 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3822 scsiseq_template |= ENRSELI; 3823 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3824 3825 /* 3826 * Load the Sequencer program and Enable the adapter 3827 * in "fast" mode. 3828 */ 3829 #ifdef AHC_DEBUG 3830 printf("%s: Downloading Sequencer Program...", 3831 ahc_name(ahc)); 3832 #endif 3833 3834 ahc_loadseq(ahc); 3835 3836 /* We have to wait until after any system dumps... */ 3837 shutdownhook_establish(ahc_shutdown, ahc); 3838 3839 return (0); 3840 } 3841 3842 /* 3843 * XXX fvdl the busy_tcl checks and settings should only be done 3844 * for the non-tagged queueing case, but we don't do tagged queueing 3845 * yet, so.. 3846 */ 3847 static int32_t 3848 ahc_action(struct scsipi_xfer *xs) 3849 { 3850 struct scsipi_xfer *first_xs, *next_xs = NULL; 3851 struct ahc_softc *ahc; 3852 struct scb *scb; 3853 struct hardware_scb *hscb; 3854 struct ahc_initiator_tinfo *tinfo; 3855 struct tmode_tstate *tstate; 3856 u_int target_id; 3857 u_int our_id; 3858 int s, tcl; 3859 u_int16_t mask; 3860 int dontqueue = 0, fromqueue = 0; 3861 3862 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3863 3864 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3865 3866 /* must protect the queue */ 3867 s = splbio(); 3868 3869 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3870 /* 3871 * Called from ahc_done. Calling with the first entry in 3872 * the queue is really just a way of seeing where we're 3873 * called from. Now, find the first eligible SCB to send, 3874 * e.g. one which will be accepted immediately. 3875 */ 3876 3877 if (ahc->queue_blocked) { 3878 splx(s); 3879 return (TRY_AGAIN_LATER); 3880 } 3881 3882 xs = ahc_first_xs(ahc); 3883 if (xs == NULL) { 3884 splx(s); 3885 return (TRY_AGAIN_LATER); 3886 } 3887 3888 next_xs = TAILQ_NEXT(xs, adapter_q); 3889 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3890 fromqueue = 1; 3891 goto get_scb; 3892 } 3893 3894 /* 3895 * If no new requests are accepted, just insert into the 3896 * private queue to wait for our turn. 3897 */ 3898 tcl = XS_TCL(ahc, xs); 3899 3900 if (ahc->queue_blocked || 3901 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3902 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3903 if (dontqueue) { 3904 splx(s); 3905 xs->error = XS_DRIVER_STUFFUP; 3906 return TRY_AGAIN_LATER; 3907 } 3908 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3909 splx(s); 3910 return SUCCESSFULLY_QUEUED; 3911 } 3912 3913 first_xs = ahc_first_xs(ahc); 3914 3915 /* determine safety of software queueing */ 3916 dontqueue = xs->xs_control & XS_CTL_POLL; 3917 3918 /* 3919 * Handle situations where there's already entries in the 3920 * queue. 3921 */ 3922 if (first_xs != NULL) { 3923 /* 3924 * If we can't queue, we have to abort, since 3925 * we have to preserve order. 3926 */ 3927 if (dontqueue) { 3928 splx(s); 3929 xs->error = XS_DRIVER_STUFFUP; 3930 return (TRY_AGAIN_LATER); 3931 } 3932 3933 /* 3934 * Swap with the first queue entry. 3935 */ 3936 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3937 xs = first_xs; 3938 next_xs = TAILQ_NEXT(xs, adapter_q); 3939 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3940 fromqueue = 1; 3941 3942 } 3943 3944 get_scb: 3945 3946 target_id = xs->sc_link->scsipi_scsi.target; 3947 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3948 3949 /* 3950 * get an scb to use. 3951 */ 3952 if ((scb = ahcgetscb(ahc)) == NULL) { 3953 3954 if (dontqueue) { 3955 splx(s); 3956 xs->error = XS_DRIVER_STUFFUP; 3957 return (TRY_AGAIN_LATER); 3958 } 3959 3960 /* 3961 * If we were pulled off the queue, put ourselves 3962 * back to where we came from, otherwise tack ourselves 3963 * onto the end. 3964 */ 3965 if (fromqueue && next_xs != NULL) 3966 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3967 else 3968 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3969 3970 splx(s); 3971 return (SUCCESSFULLY_QUEUED); 3972 } 3973 3974 tcl = XS_TCL(ahc, xs); 3975 3976 #ifdef DIAGNOSTIC 3977 if (ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3978 panic("ahc: queuing for busy target"); 3979 #endif 3980 3981 scb->xs = xs; 3982 hscb = scb->hscb; 3983 hscb->tcl = tcl; 3984 3985 ahc_busy_tcl(ahc, scb); 3986 3987 splx(s); 3988 3989 /* 3990 * Put all the arguments for the xfer in the scb 3991 */ 3992 3993 mask = SCB_TARGET_MASK(scb); 3994 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 3995 target_id, &tstate); 3996 if (ahc->inited_targets[target_id] == 0) { 3997 struct ahc_devinfo devinfo; 3998 3999 s = splbio(); 4000 ahc_compile_devinfo(&devinfo, our_id, target_id, 4001 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4002 ROLE_INITIATOR); 4003 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4004 FALSE); 4005 ahc->inited_targets[target_id] = 1; 4006 splx(s); 4007 } 4008 4009 hscb->scsirate = tinfo->scsirate; 4010 hscb->scsioffset = tinfo->current.offset; 4011 if ((tstate->ultraenb & mask) != 0) 4012 hscb->control |= ULTRAENB; 4013 4014 if ((tstate->discenable & mask) != 0) 4015 hscb->control |= DISCENB; 4016 4017 if (xs->xs_control & XS_CTL_RESET) { 4018 hscb->cmdpointer = NULL; 4019 scb->flags |= SCB_DEVICE_RESET; 4020 hscb->control |= MK_MESSAGE; 4021 return ahc_execute_scb(scb, NULL, 0); 4022 } 4023 4024 return ahc_setup_data(ahc, xs, scb); 4025 } 4026 4027 static int 4028 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4029 { 4030 struct scb *scb; 4031 struct scsipi_xfer *xs; 4032 struct ahc_softc *ahc; 4033 int s; 4034 4035 scb = (struct scb *)arg; 4036 xs = scb->xs; 4037 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4038 4039 4040 if (nsegments != 0) { 4041 struct ahc_dma_seg *sg; 4042 bus_dma_segment_t *end_seg; 4043 int op; 4044 4045 end_seg = dm_segs + nsegments; 4046 4047 /* Copy the first SG into the data pointer area */ 4048 scb->hscb->data = dm_segs->ds_addr; 4049 scb->hscb->datalen = dm_segs->ds_len; 4050 4051 /* Copy the segments into our SG list */ 4052 sg = scb->sg_list; 4053 while (dm_segs < end_seg) { 4054 sg->addr = dm_segs->ds_addr; 4055 sg->len = dm_segs->ds_len; 4056 ahc_swap_sg(sg); 4057 sg++; 4058 dm_segs++; 4059 } 4060 4061 /* Note where to find the SG entries in bus space */ 4062 scb->hscb->SG_pointer = scb->sg_list_phys; 4063 4064 if (xs->xs_control & XS_CTL_DATA_IN) 4065 op = BUS_DMASYNC_PREREAD; 4066 else 4067 op = BUS_DMASYNC_PREWRITE; 4068 4069 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4070 scb->dmamap->dm_mapsize, op); 4071 4072 } else { 4073 scb->hscb->SG_pointer = 0; 4074 scb->hscb->data = 0; 4075 scb->hscb->datalen = 0; 4076 } 4077 4078 scb->sg_count = scb->hscb->SG_count = nsegments; 4079 4080 s = splbio(); 4081 4082 /* 4083 * Last time we need to check if this SCB needs to 4084 * be aborted. 4085 */ 4086 if (xs->xs_status & XS_STS_DONE) { 4087 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4088 if (nsegments != 0) 4089 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4090 ahcfreescb(ahc, scb); 4091 splx(s); 4092 return (COMPLETE); 4093 } 4094 4095 #ifdef DIAGNOSTIC 4096 if (scb->sg_count > 255) 4097 panic("ahc bad sg_count"); 4098 #endif 4099 4100 ahc_swap_hscb(scb->hscb); 4101 4102 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4103 4104 scb->flags |= SCB_ACTIVE; 4105 4106 if (!(xs->xs_control & XS_CTL_POLL)) 4107 timeout(ahc_timeout, (caddr_t)scb, 4108 (xs->timeout * hz) / 1000); 4109 4110 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4111 #if 0 4112 printf("Continueing Immediate Command %d:%d\n", 4113 xs->sc_link->scsipi_scsi.target, 4114 xs->sc_link->scsipi_scsi.lun); 4115 #endif 4116 pause_sequencer(ahc); 4117 if ((ahc->flags & AHC_PAGESCBS) == 0) 4118 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4119 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4120 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4121 unpause_sequencer(ahc); 4122 } else { 4123 4124 #if 0 4125 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4126 scb->hscb->tag, ahc->qinfifonext, 4127 &ahc->qinfifo[ahc->qinfifonext], 4128 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4129 #endif 4130 4131 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4132 4133 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4134 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4135 4136 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4137 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4138 } else { 4139 pause_sequencer(ahc); 4140 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4141 unpause_sequencer(ahc); 4142 } 4143 } 4144 4145 #ifdef AHC_DEBUG 4146 if (ahc_debug & AHC_SHOWCMDS) { 4147 scsi_print_addr(xs->sc_link); 4148 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4149 " rate %x\n", 4150 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4151 scb->flags, scb->hscb->control, ahc->qinfifonext, 4152 scb->hscb->scsirate); 4153 } 4154 #endif 4155 4156 if (!(xs->xs_control & XS_CTL_POLL)) { 4157 splx(s); 4158 return (SUCCESSFULLY_QUEUED); 4159 } 4160 /* 4161 * If we can't use interrupts, poll for completion 4162 */ 4163 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4164 do { 4165 if (ahc_poll(ahc, xs->timeout)) { 4166 if (!(xs->xs_control & XS_CTL_SILENT)) 4167 printf("cmd fail\n"); 4168 ahc_timeout(scb); 4169 break; 4170 } 4171 } while (!(xs->xs_status & XS_STS_DONE)); 4172 splx(s); 4173 return (COMPLETE); 4174 } 4175 4176 static int 4177 ahc_poll(struct ahc_softc *ahc, int wait) 4178 { 4179 while (--wait) { 4180 DELAY(1000); 4181 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4182 break; 4183 } 4184 4185 if (wait == 0) { 4186 printf("%s: board is not responding\n", ahc_name(ahc)); 4187 return (EIO); 4188 } 4189 4190 ahc_intr((void *)ahc); 4191 return (0); 4192 } 4193 4194 static int 4195 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4196 struct scb *scb) 4197 { 4198 struct hardware_scb *hscb; 4199 4200 hscb = scb->hscb; 4201 xs->resid = xs->status = 0; 4202 4203 hscb->cmdlen = xs->cmdlen; 4204 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4205 hscb->cmdpointer = hscb->cmdstore_busaddr; 4206 4207 /* Only use S/G if there is a transfer */ 4208 if (xs->datalen) { 4209 int error; 4210 4211 error = bus_dmamap_load(ahc->parent_dmat, 4212 scb->dmamap, xs->data, 4213 xs->datalen, NULL, 4214 (xs->xs_control & XS_CTL_NOSLEEP) ? 4215 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4216 if (error) { 4217 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4218 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4219 } 4220 error = ahc_execute_scb(scb, 4221 scb->dmamap->dm_segs, 4222 scb->dmamap->dm_nsegs); 4223 return error; 4224 } else { 4225 return ahc_execute_scb(scb, NULL, 0); 4226 } 4227 } 4228 4229 static void 4230 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4231 { 4232 int target; 4233 char channel; 4234 int lun; 4235 4236 target = sc_link->scsipi_scsi.target; 4237 lun = sc_link->scsipi_scsi.lun; 4238 channel = sc_link->scsipi_scsi.channel; 4239 4240 ahc_search_qinfifo(ahc, target, channel, lun, 4241 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4242 SCB_REQUEUE, SEARCH_COMPLETE); 4243 } 4244 4245 static void 4246 ahcallocscbs(struct ahc_softc *ahc) 4247 { 4248 struct scb_data *scb_data; 4249 struct scb *next_scb; 4250 struct sg_map_node *sg_map; 4251 bus_addr_t physaddr; 4252 struct ahc_dma_seg *segs; 4253 int newcount; 4254 int i; 4255 4256 scb_data = ahc->scb_data; 4257 if (scb_data->numscbs >= AHC_SCB_MAX) 4258 /* Can't allocate any more */ 4259 return; 4260 4261 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4262 4263 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4264 4265 if (sg_map == NULL) 4266 return; 4267 4268 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4269 &sg_map->sg_dmamap, 4270 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4271 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4272 "SG space") < 0) { 4273 free(sg_map, M_DEVBUF); 4274 return; 4275 } 4276 4277 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4278 4279 segs = sg_map->sg_vaddr; 4280 physaddr = sg_map->sg_physaddr; 4281 4282 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4283 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4284 int error; 4285 4286 next_scb->sg_list = segs; 4287 /* 4288 * The sequencer always starts with the second entry. 4289 * The first entry is embedded in the scb. 4290 */ 4291 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4292 next_scb->flags = SCB_FREE; 4293 error = bus_dmamap_create(ahc->parent_dmat, 4294 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4295 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4296 &next_scb->dmamap); 4297 if (error != 0) 4298 break; 4299 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4300 next_scb->hscb->tag = ahc->scb_data->numscbs; 4301 next_scb->hscb->cmdstore_busaddr = 4302 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4303 + offsetof(struct hardware_scb, cmdstore); 4304 next_scb->hscb->cmdstore_busaddr = 4305 htole32(next_scb->hscb->cmdstore_busaddr); 4306 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4307 segs += AHC_NSEG; 4308 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4309 next_scb++; 4310 ahc->scb_data->numscbs++; 4311 } 4312 #ifdef AHC_DEBUG 4313 if (ahc_debug & AHC_SHOWSCBALLOC) 4314 printf("%s: allocated %d new SCBs count now %d\n", 4315 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4316 #endif 4317 } 4318 4319 #ifdef AHC_DUMP_SEQ 4320 static void 4321 ahc_dumpseq(struct ahc_softc* ahc) 4322 { 4323 int i; 4324 int max_prog; 4325 4326 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4327 max_prog = 448; 4328 else if ((ahc->features & AHC_ULTRA2) != 0) 4329 max_prog = 768; 4330 else 4331 max_prog = 512; 4332 4333 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4334 ahc_outb(ahc, SEQADDR0, 0); 4335 ahc_outb(ahc, SEQADDR1, 0); 4336 for (i = 0; i < max_prog; i++) { 4337 u_int8_t ins_bytes[4]; 4338 4339 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4340 printf("0x%08x\n", ins_bytes[0] << 24 4341 | ins_bytes[1] << 16 4342 | ins_bytes[2] << 8 4343 | ins_bytes[3]); 4344 } 4345 } 4346 #endif 4347 4348 static void 4349 ahc_loadseq(struct ahc_softc *ahc) 4350 { 4351 struct patch *cur_patch; 4352 int i; 4353 int downloaded; 4354 int skip_addr; 4355 u_int8_t download_consts[4]; 4356 4357 /* Setup downloadable constant table */ 4358 #if 0 4359 /* No downloaded constants are currently defined. */ 4360 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4361 #endif 4362 4363 cur_patch = patches; 4364 downloaded = 0; 4365 skip_addr = 0; 4366 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4367 ahc_outb(ahc, SEQADDR0, 0); 4368 ahc_outb(ahc, SEQADDR1, 0); 4369 4370 for (i = 0; i < sizeof(seqprog)/4; i++) { 4371 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4372 /* 4373 * Don't download this instruction as it 4374 * is in a patch that was removed. 4375 */ 4376 continue; 4377 } 4378 ahc_download_instr(ahc, i, download_consts); 4379 downloaded++; 4380 } 4381 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4382 restart_sequencer(ahc); 4383 4384 #ifdef AHC_DEBUG 4385 printf(" %d instructions downloaded\n", downloaded); 4386 #endif 4387 } 4388 4389 static int 4390 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4391 int start_instr, int *skip_addr) 4392 { 4393 struct patch *cur_patch; 4394 struct patch *last_patch; 4395 int num_patches; 4396 4397 num_patches = sizeof(patches)/sizeof(struct patch); 4398 last_patch = &patches[num_patches]; 4399 cur_patch = *start_patch; 4400 4401 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4402 4403 if (cur_patch->patch_func(ahc) == 0) { 4404 4405 /* Start rejecting code */ 4406 *skip_addr = start_instr + cur_patch->skip_instr; 4407 cur_patch += cur_patch->skip_patch; 4408 } else { 4409 /* Accepted this patch. Advance to the next 4410 * one and wait for our intruction pointer to 4411 * hit this point. 4412 */ 4413 cur_patch++; 4414 } 4415 } 4416 4417 *start_patch = cur_patch; 4418 if (start_instr < *skip_addr) 4419 /* Still skipping */ 4420 return (0); 4421 4422 return (1); 4423 } 4424 4425 static void 4426 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4427 { 4428 union ins_formats instr; 4429 struct ins_format1 *fmt1_ins; 4430 struct ins_format3 *fmt3_ins; 4431 u_int opcode; 4432 4433 /* Structure copy */ 4434 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4435 4436 instr.integer = le32toh(instr.integer); 4437 4438 fmt1_ins = &instr.format1; 4439 fmt3_ins = NULL; 4440 4441 /* Pull the opcode */ 4442 opcode = instr.format1.opcode; 4443 switch (opcode) { 4444 case AIC_OP_JMP: 4445 case AIC_OP_JC: 4446 case AIC_OP_JNC: 4447 case AIC_OP_CALL: 4448 case AIC_OP_JNE: 4449 case AIC_OP_JNZ: 4450 case AIC_OP_JE: 4451 case AIC_OP_JZ: 4452 { 4453 struct patch *cur_patch; 4454 int address_offset; 4455 u_int address; 4456 int skip_addr; 4457 int i; 4458 4459 fmt3_ins = &instr.format3; 4460 address_offset = 0; 4461 address = fmt3_ins->address; 4462 cur_patch = patches; 4463 skip_addr = 0; 4464 4465 for (i = 0; i < address;) { 4466 4467 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4468 4469 if (skip_addr > i) { 4470 int end_addr; 4471 4472 end_addr = MIN(address, skip_addr); 4473 address_offset += end_addr - i; 4474 i = skip_addr; 4475 } else { 4476 i++; 4477 } 4478 } 4479 address -= address_offset; 4480 fmt3_ins->address = address; 4481 /* FALLTHROUGH */ 4482 } 4483 case AIC_OP_OR: 4484 case AIC_OP_AND: 4485 case AIC_OP_XOR: 4486 case AIC_OP_ADD: 4487 case AIC_OP_ADC: 4488 case AIC_OP_BMOV: 4489 if (fmt1_ins->parity != 0) { 4490 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4491 } 4492 fmt1_ins->parity = 0; 4493 /* FALLTHROUGH */ 4494 case AIC_OP_ROL: 4495 if ((ahc->features & AHC_ULTRA2) != 0) { 4496 int i, count; 4497 4498 /* Calculate odd parity for the instruction */ 4499 for (i = 0, count = 0; i < 31; i++) { 4500 u_int32_t mask; 4501 4502 mask = 0x01 << i; 4503 if ((instr.integer & mask) != 0) 4504 count++; 4505 } 4506 if ((count & 0x01) == 0) 4507 instr.format1.parity = 1; 4508 } else { 4509 /* Compress the instruction for older sequencers */ 4510 if (fmt3_ins != NULL) { 4511 instr.integer = 4512 fmt3_ins->immediate 4513 | (fmt3_ins->source << 8) 4514 | (fmt3_ins->address << 16) 4515 | (fmt3_ins->opcode << 25); 4516 } else { 4517 instr.integer = 4518 fmt1_ins->immediate 4519 | (fmt1_ins->source << 8) 4520 | (fmt1_ins->destination << 16) 4521 | (fmt1_ins->ret << 24) 4522 | (fmt1_ins->opcode << 25); 4523 } 4524 } 4525 instr.integer = htole32(instr.integer); 4526 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4527 break; 4528 default: 4529 panic("Unknown opcode encountered in seq program"); 4530 break; 4531 } 4532 } 4533 4534 static void 4535 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4536 { 4537 4538 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4539 struct scb *scbp; 4540 4541 scb->flags |= SCB_RECOVERY_SCB; 4542 4543 /* 4544 * Take all queued, but not sent SCBs out of the equation. 4545 * Also ensure that no new CCBs are queued to us while we 4546 * try to fix this problem. 4547 */ 4548 ahc->queue_blocked = 1; 4549 4550 /* 4551 * Go through all of our pending SCBs and remove 4552 * any scheduled timeouts for them. We will reschedule 4553 * them after we've successfully fixed this problem. 4554 */ 4555 scbp = ahc->pending_ccbs.lh_first; 4556 while (scbp != NULL) { 4557 untimeout(ahc_timeout, scbp); 4558 scbp = scbp->plinks.le_next; 4559 } 4560 } 4561 } 4562 4563 static void 4564 ahc_timeout(void *arg) 4565 { 4566 struct scb *scb; 4567 struct ahc_softc *ahc; 4568 int s, found; 4569 u_int last_phase; 4570 int target; 4571 int lun; 4572 int i; 4573 char channel; 4574 4575 scb = (struct scb *)arg; 4576 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4577 4578 s = splbio(); 4579 4580 /* 4581 * Ensure that the card doesn't do anything 4582 * behind our back. Also make sure that we 4583 * didn't "just" miss an interrupt that would 4584 * affect this timeout. 4585 */ 4586 do { 4587 ahc_intr(ahc); 4588 pause_sequencer(ahc); 4589 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4590 4591 if ((scb->flags & SCB_ACTIVE) == 0) { 4592 /* Previous timeout took care of me already */ 4593 printf("Timedout SCB handled by another timeout\n"); 4594 unpause_sequencer(ahc); 4595 splx(s); 4596 return; 4597 } 4598 4599 target = SCB_TARGET(scb); 4600 channel = SCB_CHANNEL(scb); 4601 lun = SCB_LUN(scb); 4602 4603 scsi_print_addr(scb->xs->sc_link); 4604 printf("SCB %x - timed out ", scb->hscb->tag); 4605 /* 4606 * Take a snapshot of the bus state and print out 4607 * some information so we can track down driver bugs. 4608 */ 4609 last_phase = ahc_inb(ahc, LASTPHASE); 4610 4611 for (i = 0; i < num_phases; i++) { 4612 if (last_phase == phase_table[i].phase) 4613 break; 4614 } 4615 printf("%s", phase_table[i].phasemsg); 4616 4617 printf(", SEQADDR == 0x%x\n", 4618 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4619 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4620 4621 #ifdef AHC_DEBUG 4622 ahc_print_scb(scb); 4623 #endif 4624 4625 #if 0 4626 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4627 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4628 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4629 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4630 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4631 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4632 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4633 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4634 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4635 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4636 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4637 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4638 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4639 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4640 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4641 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4642 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4643 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4644 if (scb->sg_count > 0) { 4645 for (i = 0; i < scb->sg_count; i++) { 4646 printf("sg[%d] - Addr 0x%x : Length %d\n", 4647 i, 4648 le32toh(scb->sg_list[i].addr), 4649 le32toh(scb->sg_list[i].len)); 4650 } 4651 } 4652 #endif 4653 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4654 /* 4655 * Been down this road before. 4656 * Do a full bus reset. 4657 */ 4658 bus_reset: 4659 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4660 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4661 printf("%s: Issued Channel %c Bus Reset. " 4662 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4663 } else { 4664 /* 4665 * If we are a target, transition to bus free and report 4666 * the timeout. 4667 * 4668 * The target/initiator that is holding up the bus may not 4669 * be the same as the one that triggered this timeout 4670 * (different commands have different timeout lengths). 4671 * If the bus is idle and we are actiing as the initiator 4672 * for this request, queue a BDR message to the timed out 4673 * target. Otherwise, if the timed out transaction is 4674 * active: 4675 * Initiator transaction: 4676 * Stuff the message buffer with a BDR message and assert 4677 * ATN in the hopes that the target will let go of the bus 4678 * and go to the mesgout phase. If this fails, we'll 4679 * get another timeout 2 seconds later which will attempt 4680 * a bus reset. 4681 * 4682 * Target transaction: 4683 * Transition to BUS FREE and report the error. 4684 * It's good to be the target! 4685 */ 4686 u_int active_scb_index; 4687 4688 active_scb_index = ahc_inb(ahc, SCB_TAG); 4689 4690 if (last_phase != P_BUSFREE 4691 && (active_scb_index < ahc->scb_data->numscbs)) { 4692 struct scb *active_scb; 4693 4694 /* 4695 * If the active SCB is not from our device, 4696 * assume that another device is hogging the bus 4697 * and wait for it's timeout to expire before 4698 * taking additional action. 4699 */ 4700 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4701 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4702 u_int newtimeout; 4703 4704 scsi_print_addr(scb->xs->sc_link); 4705 printf("Other SCB Timeout%s", 4706 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4707 ? " again\n" : "\n"); 4708 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4709 newtimeout = MAX(active_scb->xs->timeout, 4710 scb->xs->timeout); 4711 timeout(ahc_timeout, scb, 4712 (newtimeout * hz) / 1000); 4713 splx(s); 4714 return; 4715 } 4716 4717 /* It's us */ 4718 if ((scb->hscb->control & TARGET_SCB) != 0) { 4719 4720 /* 4721 * Send back any queued up transactions 4722 * and properly record the error condition. 4723 */ 4724 ahc_freeze_devq(ahc, scb->xs->sc_link); 4725 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4726 ahc_freeze_ccb(scb); 4727 ahc_done(ahc, scb); 4728 4729 /* Will clear us from the bus */ 4730 restart_sequencer(ahc); 4731 return; 4732 } 4733 4734 ahc_set_recoveryscb(ahc, active_scb); 4735 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4736 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4737 scsi_print_addr(active_scb->xs->sc_link); 4738 printf("BDR message in message buffer\n"); 4739 active_scb->flags |= SCB_DEVICE_RESET; 4740 timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); 4741 unpause_sequencer(ahc); 4742 } else { 4743 int disconnected; 4744 4745 /* XXX Shouldn't panic. Just punt instead */ 4746 if ((scb->hscb->control & TARGET_SCB) != 0) 4747 panic("Timed-out target SCB but bus idle"); 4748 4749 if (last_phase != P_BUSFREE 4750 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4751 /* XXX What happened to the SCB? */ 4752 /* Hung target selection. Goto busfree */ 4753 printf("%s: Hung target selection\n", 4754 ahc_name(ahc)); 4755 restart_sequencer(ahc); 4756 return; 4757 } 4758 4759 if (ahc_search_qinfifo(ahc, target, channel, lun, 4760 scb->hscb->tag, ROLE_INITIATOR, 4761 /*status*/0, SEARCH_COUNT) > 0) { 4762 disconnected = FALSE; 4763 } else { 4764 disconnected = TRUE; 4765 } 4766 4767 if (disconnected) { 4768 u_int active_scb; 4769 4770 ahc_set_recoveryscb(ahc, scb); 4771 /* 4772 * Simply set the MK_MESSAGE control bit. 4773 */ 4774 scb->hscb->control |= MK_MESSAGE; 4775 scb->flags |= SCB_QUEUED_MSG 4776 | SCB_DEVICE_RESET; 4777 4778 /* 4779 * Mark the cached copy of this SCB in the 4780 * disconnected list too, so that a reconnect 4781 * at this point causes a BDR or abort. 4782 */ 4783 active_scb = ahc_inb(ahc, SCBPTR); 4784 if (ahc_search_disc_list(ahc, target, 4785 channel, lun, 4786 scb->hscb->tag, 4787 /*stop_on_first*/TRUE, 4788 /*remove*/FALSE, 4789 /*save_state*/FALSE)) { 4790 u_int scb_control; 4791 4792 scb_control = ahc_inb(ahc, SCB_CONTROL); 4793 scb_control |= MK_MESSAGE; 4794 ahc_outb(ahc, SCB_CONTROL, scb_control); 4795 } 4796 ahc_outb(ahc, SCBPTR, active_scb); 4797 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4798 /*unbusy*/TRUE); 4799 4800 /* 4801 * Actually re-queue this SCB in case we can 4802 * select the device before it reconnects. 4803 * Clear out any entries in the QINFIFO first 4804 * so we are the next SCB for this target 4805 * to run. 4806 */ 4807 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4808 channel, SCB_LUN(scb), 4809 SCB_LIST_NULL, 4810 ROLE_INITIATOR, 4811 SCB_REQUEUE, 4812 SEARCH_COMPLETE); 4813 scsi_print_addr(scb->xs->sc_link); 4814 printf("Queuing a BDR SCB\n"); 4815 ahc->qinfifo[ahc->qinfifonext++] = 4816 scb->hscb->tag; 4817 4818 bus_dmamap_sync(ahc->parent_dmat, 4819 ahc->shared_data_dmamap, 4820 QINFIFO_OFFSET * 256, 256, 4821 BUS_DMASYNC_PREWRITE); 4822 4823 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4824 ahc_outb(ahc, HNSCB_QOFF, 4825 ahc->qinfifonext); 4826 } else { 4827 ahc_outb(ahc, KERNEL_QINPOS, 4828 ahc->qinfifonext); 4829 } 4830 timeout(ahc_timeout, (caddr_t)scb, 2 * hz); 4831 unpause_sequencer(ahc); 4832 } else { 4833 /* Go "immediatly" to the bus reset */ 4834 /* This shouldn't happen */ 4835 ahc_set_recoveryscb(ahc, scb); 4836 scsi_print_addr(scb->xs->sc_link); 4837 printf("SCB %x: Immediate reset. " 4838 "Flags = 0x%x\n", scb->hscb->tag, 4839 scb->flags); 4840 goto bus_reset; 4841 } 4842 } 4843 } 4844 splx(s); 4845 } 4846 4847 static int 4848 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4849 int lun, u_int tag, role_t role, scb_flag status, 4850 ahc_search_action action) 4851 { 4852 struct scb *scbp; 4853 u_int8_t qinpos; 4854 u_int8_t qintail; 4855 int found; 4856 4857 qinpos = ahc_inb(ahc, QINPOS); 4858 qintail = ahc->qinfifonext; 4859 found = 0; 4860 4861 /* 4862 * Start with an empty queue. Entries that are not chosen 4863 * for removal will be re-added to the queue as we go. 4864 */ 4865 ahc->qinfifonext = qinpos; 4866 4867 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4868 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4869 4870 while (qinpos != qintail) { 4871 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4872 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4873 /* 4874 * We found an scb that needs to be removed. 4875 */ 4876 switch (action) { 4877 case SEARCH_COMPLETE: 4878 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4879 scbp->flags |= status; 4880 scbp->xs->error = XS_NOERROR; 4881 } 4882 ahc_freeze_ccb(scbp); 4883 ahc_done(ahc, scbp); 4884 break; 4885 case SEARCH_COUNT: 4886 ahc->qinfifo[ahc->qinfifonext++] = 4887 scbp->hscb->tag; 4888 break; 4889 case SEARCH_REMOVE: 4890 break; 4891 } 4892 found++; 4893 } else { 4894 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4895 } 4896 qinpos++; 4897 } 4898 4899 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4900 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4901 4902 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4903 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4904 } else { 4905 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4906 } 4907 4908 return (found); 4909 } 4910 4911 /* 4912 * Abort all SCBs that match the given description (target/channel/lun/tag), 4913 * setting their status to the passed in status if the status has not already 4914 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4915 * is paused before it is called. 4916 */ 4917 static int 4918 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4919 int lun, u_int tag, role_t role, int status) 4920 { 4921 struct scb *scbp; 4922 u_int active_scb; 4923 int i; 4924 int found; 4925 4926 /* restore this when we're done */ 4927 active_scb = ahc_inb(ahc, SCBPTR); 4928 4929 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4930 role, SCB_REQUEUE, SEARCH_COMPLETE); 4931 4932 /* 4933 * Search waiting for selection list. 4934 */ 4935 { 4936 u_int8_t next, prev; 4937 4938 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4939 prev = SCB_LIST_NULL; 4940 4941 while (next != SCB_LIST_NULL) { 4942 u_int8_t scb_index; 4943 4944 ahc_outb(ahc, SCBPTR, next); 4945 scb_index = ahc_inb(ahc, SCB_TAG); 4946 if (scb_index >= ahc->scb_data->numscbs) { 4947 panic("Waiting List inconsistency. " 4948 "SCB index == %d, yet numscbs == %d.", 4949 scb_index, ahc->scb_data->numscbs); 4950 } 4951 scbp = &ahc->scb_data->scbarray[scb_index]; 4952 if (ahc_match_scb(scbp, target, channel, 4953 lun, SCB_LIST_NULL, role)) { 4954 4955 next = ahc_abort_wscb(ahc, next, prev); 4956 } else { 4957 4958 prev = next; 4959 next = ahc_inb(ahc, SCB_NEXT); 4960 } 4961 } 4962 } 4963 /* 4964 * Go through the disconnected list and remove any entries we 4965 * have queued for completion, 0'ing their control byte too. 4966 * We save the active SCB and restore it ourselves, so there 4967 * is no reason for this search to restore it too. 4968 */ 4969 ahc_search_disc_list(ahc, target, channel, lun, tag, 4970 /*stop_on_first*/FALSE, /*remove*/TRUE, 4971 /*save_state*/FALSE); 4972 4973 /* 4974 * Go through the hardware SCB array looking for commands that 4975 * were active but not on any list. 4976 */ 4977 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4978 u_int scbid; 4979 4980 ahc_outb(ahc, SCBPTR, i); 4981 scbid = ahc_inb(ahc, SCB_TAG); 4982 scbp = &ahc->scb_data->scbarray[scbid]; 4983 if (scbid < ahc->scb_data->numscbs 4984 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4985 ahc_add_curscb_to_free_list(ahc); 4986 } 4987 4988 /* 4989 * Go through the pending CCB list and look for 4990 * commands for this target that are still active. 4991 * These are other tagged commands that were 4992 * disconnected when the reset occured. 4993 */ 4994 { 4995 struct scb *scb; 4996 4997 scb = ahc->pending_ccbs.lh_first; 4998 while (scb != NULL) { 4999 scbp = scb; 5000 scb = scb->plinks.le_next; 5001 if (ahc_match_scb(scbp, target, channel, 5002 lun, tag, role)) { 5003 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5004 ahcsetccbstatus(scbp->xs, status); 5005 ahc_freeze_ccb(scbp); 5006 ahc_done(ahc, scbp); 5007 found++; 5008 } 5009 } 5010 } 5011 ahc_outb(ahc, SCBPTR, active_scb); 5012 return found; 5013 } 5014 5015 static int 5016 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5017 int lun, u_int tag, int stop_on_first, int remove, 5018 int save_state) 5019 { 5020 struct scb *scbp; 5021 u_int next; 5022 u_int prev; 5023 u_int count; 5024 u_int active_scb; 5025 5026 count = 0; 5027 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5028 prev = SCB_LIST_NULL; 5029 5030 if (save_state) { 5031 /* restore this when we're done */ 5032 active_scb = ahc_inb(ahc, SCBPTR); 5033 } else 5034 /* Silence compiler */ 5035 active_scb = SCB_LIST_NULL; 5036 5037 while (next != SCB_LIST_NULL) { 5038 u_int scb_index; 5039 5040 ahc_outb(ahc, SCBPTR, next); 5041 scb_index = ahc_inb(ahc, SCB_TAG); 5042 if (scb_index >= ahc->scb_data->numscbs) { 5043 panic("Disconnected List inconsistency. " 5044 "SCB index == %d, yet numscbs == %d.", 5045 scb_index, ahc->scb_data->numscbs); 5046 } 5047 scbp = &ahc->scb_data->scbarray[scb_index]; 5048 if (ahc_match_scb(scbp, target, channel, lun, 5049 tag, ROLE_INITIATOR)) { 5050 count++; 5051 if (remove) { 5052 next = 5053 ahc_rem_scb_from_disc_list(ahc, prev, next); 5054 } else { 5055 prev = next; 5056 next = ahc_inb(ahc, SCB_NEXT); 5057 } 5058 if (stop_on_first) 5059 break; 5060 } else { 5061 prev = next; 5062 next = ahc_inb(ahc, SCB_NEXT); 5063 } 5064 } 5065 if (save_state) 5066 ahc_outb(ahc, SCBPTR, active_scb); 5067 return (count); 5068 } 5069 5070 static u_int 5071 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5072 { 5073 u_int next; 5074 5075 ahc_outb(ahc, SCBPTR, scbptr); 5076 next = ahc_inb(ahc, SCB_NEXT); 5077 5078 ahc_outb(ahc, SCB_CONTROL, 0); 5079 5080 ahc_add_curscb_to_free_list(ahc); 5081 5082 if (prev != SCB_LIST_NULL) { 5083 ahc_outb(ahc, SCBPTR, prev); 5084 ahc_outb(ahc, SCB_NEXT, next); 5085 } else 5086 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5087 5088 return (next); 5089 } 5090 5091 static void 5092 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5093 { 5094 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5095 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5096 5097 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5098 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5099 } 5100 5101 /* 5102 * Manipulate the waiting for selection list and return the 5103 * scb that follows the one that we remove. 5104 */ 5105 static u_int 5106 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5107 { 5108 u_int curscb, next; 5109 5110 /* 5111 * Select the SCB we want to abort and 5112 * pull the next pointer out of it. 5113 */ 5114 curscb = ahc_inb(ahc, SCBPTR); 5115 ahc_outb(ahc, SCBPTR, scbpos); 5116 next = ahc_inb(ahc, SCB_NEXT); 5117 5118 /* Clear the necessary fields */ 5119 ahc_outb(ahc, SCB_CONTROL, 0); 5120 5121 ahc_add_curscb_to_free_list(ahc); 5122 5123 /* update the waiting list */ 5124 if (prev == SCB_LIST_NULL) { 5125 /* First in the list */ 5126 ahc_outb(ahc, WAITING_SCBH, next); 5127 5128 /* 5129 * Ensure we aren't attempting to perform 5130 * selection for this entry. 5131 */ 5132 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5133 } else { 5134 /* 5135 * Select the scb that pointed to us 5136 * and update its next pointer. 5137 */ 5138 ahc_outb(ahc, SCBPTR, prev); 5139 ahc_outb(ahc, SCB_NEXT, next); 5140 } 5141 5142 /* 5143 * Point us back at the original scb position. 5144 */ 5145 ahc_outb(ahc, SCBPTR, curscb); 5146 return next; 5147 } 5148 5149 static void 5150 ahc_clear_intstat(struct ahc_softc *ahc) 5151 { 5152 /* Clear any interrupt conditions this may have caused */ 5153 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5154 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5155 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5156 CLRREQINIT); 5157 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5158 } 5159 5160 static void 5161 ahc_reset_current_bus(struct ahc_softc *ahc) 5162 { 5163 u_int8_t scsiseq; 5164 5165 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5166 scsiseq = ahc_inb(ahc, SCSISEQ); 5167 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5168 DELAY(AHC_BUSRESET_DELAY); 5169 /* Turn off the bus reset */ 5170 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5171 5172 ahc_clear_intstat(ahc); 5173 5174 /* Re-enable reset interrupts */ 5175 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5176 } 5177 5178 static int 5179 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5180 { 5181 u_int initiator, target, max_scsiid; 5182 u_int sblkctl; 5183 u_int our_id; 5184 int found; 5185 int restart_needed; 5186 char cur_channel; 5187 5188 ahc->pending_device = NULL; 5189 5190 pause_sequencer(ahc); 5191 5192 /* 5193 * Run our command complete fifos to ensure that we perform 5194 * completion processing on any commands that 'completed' 5195 * before the reset occurred. 5196 */ 5197 ahc_run_qoutfifo(ahc); 5198 5199 /* 5200 * Reset the bus if we are initiating this reset 5201 */ 5202 sblkctl = ahc_inb(ahc, SBLKCTL); 5203 cur_channel = 'A'; 5204 if ((ahc->features & AHC_TWIN) != 0 5205 && ((sblkctl & SELBUSB) != 0)) 5206 cur_channel = 'B'; 5207 if (cur_channel != channel) { 5208 /* Case 1: Command for another bus is active 5209 * Stealthily reset the other bus without 5210 * upsetting the current bus. 5211 */ 5212 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5213 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5214 ahc_outb(ahc, SCSISEQ, 5215 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5216 if (initiate_reset) 5217 ahc_reset_current_bus(ahc); 5218 ahc_clear_intstat(ahc); 5219 ahc_outb(ahc, SBLKCTL, sblkctl); 5220 restart_needed = FALSE; 5221 } else { 5222 /* Case 2: A command from this bus is active or we're idle */ 5223 ahc_clear_msg_state(ahc); 5224 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5225 ahc_outb(ahc, SCSISEQ, 5226 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5227 if (initiate_reset) 5228 ahc_reset_current_bus(ahc); 5229 ahc_clear_intstat(ahc); 5230 5231 /* 5232 * Since we are going to restart the sequencer, avoid 5233 * a race in the sequencer that could cause corruption 5234 * of our Q pointers by starting over from index 0. 5235 */ 5236 ahc->qoutfifonext = 0; 5237 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5238 ahc_outb(ahc, SDSCB_QOFF, 0); 5239 else 5240 ahc_outb(ahc, QOUTPOS, 0); 5241 restart_needed = TRUE; 5242 } 5243 5244 /* 5245 * Clean up all the state information for the 5246 * pending transactions on this bus. 5247 */ 5248 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5249 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5250 ROLE_UNKNOWN, XS_RESET); 5251 if (channel == 'B') { 5252 our_id = ahc->our_id_b; 5253 } else { 5254 our_id = ahc->our_id; 5255 } 5256 5257 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5258 5259 /* 5260 * Revert to async/narrow transfers until we renegotiate. 5261 */ 5262 for (target = 0; target <= max_scsiid; target++) { 5263 5264 if (ahc->enabled_targets[target] == NULL) 5265 continue; 5266 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5267 struct ahc_devinfo devinfo; 5268 5269 ahc_compile_devinfo(&devinfo, target, initiator, 5270 AHC_LUN_WILDCARD, 5271 channel, ROLE_UNKNOWN); 5272 ahc_set_width(ahc, &devinfo, 5273 MSG_EXT_WDTR_BUS_8_BIT, 5274 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5275 ahc_set_syncrate(ahc, &devinfo, 5276 /*syncrate*/NULL, /*period*/0, 5277 /*offset*/0, AHC_TRANS_CUR, 5278 /*paused*/TRUE, FALSE); 5279 } 5280 } 5281 5282 if (restart_needed) 5283 restart_sequencer(ahc); 5284 else 5285 unpause_sequencer(ahc); 5286 return found; 5287 } 5288 5289 static int 5290 ahc_match_scb(struct scb *scb, int target, char channel, 5291 int lun, u_int tag, role_t role) 5292 { 5293 int targ = SCB_TARGET(scb); 5294 char chan = SCB_CHANNEL(scb); 5295 int slun = SCB_LUN(scb); 5296 int match; 5297 5298 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5299 if (match != 0) 5300 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5301 if (match != 0) 5302 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5303 5304 return match; 5305 } 5306 5307 static void 5308 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5309 { 5310 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5311 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5312 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5313 ahc->msgout_buf[ahc->msgout_index++] = period; 5314 ahc->msgout_buf[ahc->msgout_index++] = offset; 5315 ahc->msgout_len += 5; 5316 } 5317 5318 static void 5319 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5320 { 5321 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5322 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5323 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5324 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5325 ahc->msgout_len += 4; 5326 } 5327 5328 static void 5329 ahc_calc_residual(struct scb *scb) 5330 { 5331 struct hardware_scb *hscb; 5332 5333 hscb = scb->hscb; 5334 5335 /* 5336 * If the disconnected flag is still set, this is bogus 5337 * residual information left over from a sequencer 5338 * pagin/pageout, so ignore this case. 5339 */ 5340 if ((scb->hscb->control & DISCONNECTED) == 0) { 5341 u_int32_t resid; 5342 int resid_sgs; 5343 int sg; 5344 5345 /* 5346 * Remainder of the SG where the transfer 5347 * stopped. 5348 */ 5349 resid = (hscb->residual_data_count[2] << 16) 5350 | (hscb->residual_data_count[1] <<8) 5351 | (hscb->residual_data_count[0]); 5352 5353 /* 5354 * Add up the contents of all residual 5355 * SG segments that are after the SG where 5356 * the transfer stopped. 5357 */ 5358 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5359 sg = scb->sg_count - resid_sgs; 5360 while (resid_sgs > 0) { 5361 5362 resid += le32toh(scb->sg_list[sg].len); 5363 sg++; 5364 resid_sgs--; 5365 } 5366 scb->xs->resid = resid; 5367 } 5368 5369 /* 5370 * Clean out the residual information in this SCB for its 5371 * next consumer. 5372 */ 5373 hscb->residual_SG_count = 0; 5374 5375 #ifdef AHC_DEBUG 5376 if (ahc_debug & AHC_SHOWMISC) { 5377 scsi_print_addr(scb->xs->sc_link); 5378 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5379 } 5380 #endif 5381 } 5382 5383 static void 5384 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5385 { 5386 struct scb *scb; 5387 int pending_ccb_count; 5388 int i; 5389 u_int saved_scbptr; 5390 5391 /* 5392 * Traverse the pending SCB list and ensure that all of the 5393 * SCBs there have the proper settings. 5394 */ 5395 scb = LIST_FIRST(&ahc->pending_ccbs); 5396 pending_ccb_count = 0; 5397 while (scb != NULL) { 5398 struct ahc_devinfo devinfo; 5399 struct scsipi_xfer *xs; 5400 struct scb *pending_scb; 5401 struct hardware_scb *pending_hscb; 5402 struct ahc_initiator_tinfo *tinfo; 5403 struct tmode_tstate *tstate; 5404 u_int our_id, remote_id; 5405 5406 xs = scb->xs; 5407 pending_scb = scb; 5408 pending_hscb = pending_scb->hscb; 5409 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5410 ? ahc->our_id_b : ahc->our_id; 5411 remote_id = xs->sc_link->scsipi_scsi.target; 5412 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5413 SCB_LUN(pending_scb), 5414 SCB_CHANNEL(pending_scb), 5415 ROLE_UNKNOWN); 5416 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5417 our_id, remote_id, &tstate); 5418 pending_hscb->control &= ~ULTRAENB; 5419 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5420 pending_hscb->control |= ULTRAENB; 5421 pending_hscb->scsirate = tinfo->scsirate; 5422 pending_hscb->scsioffset = tinfo->current.offset; 5423 pending_ccb_count++; 5424 scb = LIST_NEXT(scb, plinks); 5425 } 5426 5427 if (pending_ccb_count == 0) 5428 return; 5429 5430 saved_scbptr = ahc_inb(ahc, SCBPTR); 5431 /* Ensure that the hscbs down on the card match the new information */ 5432 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5433 u_int scb_tag; 5434 5435 ahc_outb(ahc, SCBPTR, i); 5436 scb_tag = ahc_inb(ahc, SCB_TAG); 5437 if (scb_tag != SCB_LIST_NULL) { 5438 struct ahc_devinfo devinfo; 5439 struct scb *pending_scb; 5440 struct scsipi_xfer *xs; 5441 struct hardware_scb *pending_hscb; 5442 struct ahc_initiator_tinfo *tinfo; 5443 struct tmode_tstate *tstate; 5444 u_int our_id, remote_id; 5445 u_int control; 5446 5447 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5448 if (pending_scb->flags == SCB_FREE) 5449 continue; 5450 pending_hscb = pending_scb->hscb; 5451 xs = pending_scb->xs; 5452 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5453 ? ahc->our_id_b : ahc->our_id; 5454 remote_id = xs->sc_link->scsipi_scsi.target; 5455 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5456 SCB_LUN(pending_scb), 5457 SCB_CHANNEL(pending_scb), 5458 ROLE_UNKNOWN); 5459 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5460 our_id, remote_id, &tstate); 5461 control = ahc_inb(ahc, SCB_CONTROL); 5462 control &= ~ULTRAENB; 5463 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5464 control |= ULTRAENB; 5465 ahc_outb(ahc, SCB_CONTROL, control); 5466 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5467 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5468 } 5469 } 5470 ahc_outb(ahc, SCBPTR, saved_scbptr); 5471 } 5472 5473 #if UNUSED 5474 static void 5475 ahc_dump_targcmd(struct target_cmd *cmd) 5476 { 5477 u_int8_t *byte; 5478 u_int8_t *last_byte; 5479 int i; 5480 5481 byte = &cmd->initiator_channel; 5482 /* Debugging info for received commands */ 5483 last_byte = &cmd[1].initiator_channel; 5484 5485 i = 0; 5486 while (byte < last_byte) { 5487 if (i == 0) 5488 printf("\t"); 5489 printf("%#x", *byte++); 5490 i++; 5491 if (i == 8) { 5492 printf("\n"); 5493 i = 0; 5494 } else { 5495 printf(", "); 5496 } 5497 } 5498 } 5499 #endif 5500 5501 static void 5502 ahc_shutdown(void *arg) 5503 { 5504 struct ahc_softc *ahc; 5505 int i; 5506 u_int sxfrctl1_a, sxfrctl1_b; 5507 5508 ahc = (struct ahc_softc *)arg; 5509 5510 pause_sequencer(ahc); 5511 5512 /* 5513 * Preserve the value of the SXFRCTL1 register for all channels. 5514 * It contains settings that affect termination and we don't want 5515 * to disturb the integrity of the bus during shutdown in case 5516 * we are in a multi-initiator setup. 5517 */ 5518 sxfrctl1_b = 0; 5519 if ((ahc->features & AHC_TWIN) != 0) { 5520 u_int sblkctl; 5521 5522 sblkctl = ahc_inb(ahc, SBLKCTL); 5523 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5524 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5525 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5526 } 5527 5528 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5529 5530 /* This will reset most registers to 0, but not all */ 5531 ahc_reset(ahc); 5532 5533 if ((ahc->features & AHC_TWIN) != 0) { 5534 u_int sblkctl; 5535 5536 sblkctl = ahc_inb(ahc, SBLKCTL); 5537 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5538 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5539 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5540 } 5541 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5542 5543 ahc_outb(ahc, SCSISEQ, 0); 5544 ahc_outb(ahc, SXFRCTL0, 0); 5545 ahc_outb(ahc, DSPCISTATUS, 0); 5546 5547 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5548 ahc_outb(ahc, i, 0); 5549 } 5550 5551 #if defined(AHC_DEBUG) && 0 5552 static void 5553 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5554 { 5555 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5556 5557 printf("\tcurrent:\n"); 5558 printf("\t\twidth %u period %u offset %u flags %x\n", 5559 tinfo->current.width, tinfo->current.period, 5560 tinfo->current.offset, tinfo->current.ppr_flags); 5561 5562 printf("\tgoal:\n"); 5563 printf("\t\twidth %u period %u offset %u flags %x\n", 5564 tinfo->goal.width, tinfo->goal.period, 5565 tinfo->goal.offset, tinfo->goal.ppr_flags); 5566 5567 printf("\tuser:\n"); 5568 printf("\t\twidth %u period %u offset %u flags %x\n", 5569 tinfo->user.width, tinfo->user.period, 5570 tinfo->user.offset, tinfo->user.ppr_flags); 5571 } 5572 #endif 5573
Indexes created Wed Oct 01 19:09:53 GMT 2025