aic7xxx.c revision 1.43
1 /* $NetBSD: aic7xxx.c,v 1.43 2000/03/16 10:33:45 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.41 2000/02/09 21:24:58 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 102 #include <dev/scsipi/scsi_all.h> 103 #include <dev/scsipi/scsipi_all.h> 104 #include <dev/scsipi/scsi_message.h> 105 #include <dev/scsipi/scsipi_debug.h> 106 #include <dev/scsipi/scsiconf.h> 107 108 #include <vm/vm.h> 109 #include <vm/vm_param.h> 110 #include <vm/pmap.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 118 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 119 #define ALL_CHANNELS '\0' 120 #define ALL_TARGETS_MASK 0xFFFF 121 #define INITIATOR_WILDCARD (~0) 122 123 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 124 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 125 #define SIM_CHANNEL(ahc, sc_link) \ 126 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 127 #define SIM_SCSI_ID(ahc, sc_link) \ 128 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 129 #define SCB_IS_SCSIBUS_B(scb) \ 130 (((scb)->hscb->tcl & SELBUSB) != 0) 131 #define SCB_TARGET(scb) \ 132 (((scb)->hscb->tcl & TID) >> 4) 133 #define SCB_CHANNEL(scb) \ 134 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 135 #define SCB_LUN(scb) \ 136 ((scb)->hscb->tcl & LID) 137 #define SCB_TARGET_OFFSET(scb) \ 138 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 139 #define SCB_TARGET_MASK(scb) \ 140 (0x01 << (SCB_TARGET_OFFSET(scb))) 141 #define TCL_CHANNEL(ahc, tcl) \ 142 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 143 #define TCL_SCSI_ID(ahc, tcl) \ 144 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 145 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 146 #define TCL_LUN(tcl) ((tcl) & LID) 147 148 #define XS_TCL(ahc, xs) \ 149 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 150 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 151 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 152 153 char *ahc_chip_names[] = 154 { 155 "NONE", 156 "aic7770", 157 "aic7850", 158 "aic7855", 159 "aic7859", 160 "aic7860", 161 "aic7870", 162 "aic7880", 163 "aic7890/91", 164 "aic7892", 165 "aic7895", 166 "aic7896/97", 167 "aic7899" 168 }; 169 170 typedef enum { 171 ROLE_UNKNOWN, 172 ROLE_INITIATOR, 173 ROLE_TARGET 174 } role_t; 175 176 struct ahc_devinfo { 177 int our_scsiid; 178 int target_offset; 179 u_int16_t target_mask; 180 u_int8_t target; 181 u_int8_t lun; 182 char channel; 183 role_t role; /* 184 * Only guaranteed to be correct if not 185 * in the busfree state. 186 */ 187 }; 188 189 typedef enum { 190 SEARCH_COMPLETE, 191 SEARCH_COUNT, 192 SEARCH_REMOVE 193 } ahc_search_action; 194 195 #ifdef AHC_DEBUG 196 static int ahc_debug = AHC_DEBUG; 197 #endif 198 199 static int ahcinitscbdata(struct ahc_softc *); 200 static void ahcfiniscbdata(struct ahc_softc *); 201 202 #if UNUSED 203 static void ahc_dump_targcmd(struct target_cmd *); 204 #endif 205 static void ahc_shutdown(void *arg); 206 static int32_t ahc_action(struct scsipi_xfer *); 207 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 208 static int ahc_poll(struct ahc_softc *, int); 209 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 210 struct scb *); 211 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 212 static void ahcallocscbs(struct ahc_softc *); 213 #if UNUSED 214 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 215 struct scb *); 216 #endif 217 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 218 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 219 char, role_t); 220 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 221 static void ahc_done(struct ahc_softc *, struct scb *); 222 static struct tmode_tstate * 223 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 224 #if UNUSED 225 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 226 #endif 227 static void ahc_handle_seqint(struct ahc_softc *, u_int); 228 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 229 static void ahc_build_transfer_msg(struct ahc_softc *, 230 struct ahc_devinfo *); 231 static void ahc_setup_initiator_msgout(struct ahc_softc *, 232 struct ahc_devinfo *, 233 struct scb *); 234 static void ahc_setup_target_msgin(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_clear_msg_state(struct ahc_softc *); 237 static void ahc_handle_message_phase(struct ahc_softc *, 238 struct scsipi_link *); 239 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 240 241 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 242 struct ahc_devinfo *); 243 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 244 struct ahc_devinfo *); 245 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 246 int, char *, int); 247 #ifdef AHC_DUMP_SEQ 248 static void ahc_dumpseq(struct ahc_softc *); 249 #endif 250 static void ahc_loadseq(struct ahc_softc *); 251 static int ahc_check_patch(struct ahc_softc *, struct patch **, 252 int, int *); 253 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 254 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 255 #if defined(AHC_DEBUG) 256 static void ahc_print_scb(struct scb *); 257 #endif 258 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 259 role_t, scb_flag, ahc_search_action); 260 static int ahc_reset_channel(struct ahc_softc *, char, int); 261 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 262 role_t, int); 263 static int ahc_search_disc_list(struct ahc_softc *, int, 264 char, int, u_int, int, int, int); 265 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 266 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 267 static void ahc_clear_intstat(struct ahc_softc *); 268 static void ahc_reset_current_bus(struct ahc_softc *); 269 static struct ahc_syncrate * 270 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 271 static struct ahc_syncrate * 272 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 273 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 274 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 275 u_int *, int); 276 static void ahc_update_target_msg_request(struct ahc_softc *, 277 struct ahc_devinfo *, 278 struct ahc_initiator_tinfo *, 279 int, int); 280 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 281 struct ahc_syncrate *, u_int, u_int, u_int, 282 int, int); 283 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 284 u_int, u_int, int, int); 285 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 286 int); 287 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 288 289 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 290 291 static void ahc_calc_residual(struct scb *); 292 293 static void ahc_update_pending_syncrates(struct ahc_softc *); 294 295 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 296 297 static void ahc_timeout (void *); 298 static __inline int sequencer_paused(struct ahc_softc *); 299 static __inline void pause_sequencer(struct ahc_softc *); 300 static __inline void unpause_sequencer(struct ahc_softc *); 301 static void restart_sequencer(struct ahc_softc *); 302 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 303 304 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 305 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 306 307 static __inline void ahc_freeze_ccb(struct scb *); 308 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 309 static void ahc_run_qoutfifo(struct ahc_softc *); 310 311 static __inline struct ahc_initiator_tinfo * 312 ahc_fetch_transinfo(struct ahc_softc *, 313 char, u_int, u_int, 314 struct tmode_tstate **); 315 static void ahcfreescb(struct ahc_softc *, struct scb *); 316 static __inline struct scb *ahcgetscb(struct ahc_softc *); 317 318 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 319 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 320 int *, const char *, const char *); 321 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 322 caddr_t, bus_dma_segment_t *, int); 323 static void ahcminphys(struct buf *); 324 325 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 329 #if defined(AHC_DEBUG) && 0 330 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 331 #endif 332 333 static struct scsipi_device ahc_dev = 334 { 335 NULL, /* Use default error handler */ 336 NULL, /* have a queue, served by this */ 337 NULL, /* have no async handler */ 338 NULL, /* Use default 'done' routine */ 339 }; 340 341 /* 342 * Pick the first xs for a non-blocked target. 343 */ 344 static __inline struct scsipi_xfer * 345 ahc_first_xs(struct ahc_softc *ahc) 346 { 347 int target; 348 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 349 350 if (ahc->queue_blocked) 351 return NULL; 352 353 while (xs != NULL) { 354 target = xs->sc_link->scsipi_scsi.target; 355 if (ahc->devqueue_blocked[target] == 0 && 356 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 357 SCB_LIST_NULL) 358 break; 359 xs = TAILQ_NEXT(xs, adapter_q); 360 } 361 362 return xs; 363 } 364 365 static __inline void 366 ahc_swap_hscb(struct hardware_scb *hscb) 367 { 368 hscb->SG_pointer = htole32(hscb->SG_pointer); 369 hscb->data = htole32(hscb->data); 370 hscb->datalen = htole32(hscb->datalen); 371 /* 372 * No need to swap cmdpointer; it's either NULL or set to 373 * cmdstore_busaddr, which is already swapped. 374 */ 375 } 376 377 static __inline void 378 ahc_swap_sg(struct ahc_dma_seg *sg) 379 { 380 sg->addr = htole32(sg->addr); 381 sg->len = htole32(sg->len); 382 } 383 384 static void 385 ahcminphys(bp) 386 struct buf *bp; 387 { 388 /* 389 * Even though the card can transfer up to 16megs per command 390 * we are limited by the number of segments in the dma segment 391 * list that we can hold. The worst case is that all pages are 392 * discontinuous physically, hense the "page per segment" limit 393 * enforced here. 394 */ 395 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 396 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 397 } 398 minphys(bp); 399 } 400 401 402 static __inline u_int32_t 403 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 404 { 405 return (ahc->scb_data->hscb_busaddr 406 + (sizeof(struct hardware_scb) * index)); 407 } 408 409 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 410 411 static __inline int 412 sequencer_paused(struct ahc_softc *ahc) 413 { 414 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 415 } 416 417 static __inline void 418 pause_sequencer(struct ahc_softc *ahc) 419 { 420 ahc_outb(ahc, HCNTRL, ahc->pause); 421 422 /* 423 * Since the sequencer can disable pausing in a critical section, we 424 * must loop until it actually stops. 425 */ 426 while (sequencer_paused(ahc) == 0) 427 ; 428 } 429 430 static __inline void 431 unpause_sequencer(struct ahc_softc *ahc) 432 { 433 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 434 ahc_outb(ahc, HCNTRL, ahc->unpause); 435 } 436 437 /* 438 * Restart the sequencer program from address zero 439 */ 440 static void 441 restart_sequencer(struct ahc_softc *ahc) 442 { 443 u_int i; 444 445 pause_sequencer(ahc); 446 447 /* 448 * Everytime we restart the sequencer, there 449 * is the possiblitity that we have restarted 450 * within a three instruction window where an 451 * SCB has been marked free but has not made it 452 * onto the free list. Since SCSI events(bus reset, 453 * unexpected bus free) will always freeze the 454 * sequencer, we cannot close this window. To 455 * avoid losing an SCB, we reconsitute the free 456 * list every time we restart the sequencer. 457 */ 458 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 459 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 460 461 ahc_outb(ahc, SCBPTR, i); 462 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 463 ahc_add_curscb_to_free_list(ahc); 464 } 465 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 466 unpause_sequencer(ahc); 467 } 468 469 static __inline u_int 470 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 471 { 472 u_int scbid; 473 474 scbid = ahc->untagged_scbs[tcl]; 475 if (unbusy) { 476 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 477 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 478 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 479 } 480 481 return (scbid); 482 } 483 484 static __inline void 485 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 486 { 487 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 488 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 489 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 490 } 491 492 static __inline int 493 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 494 { 495 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 496 } 497 498 static __inline void 499 ahc_freeze_ccb(struct scb *scb) 500 { 501 struct scsipi_xfer *xs = scb->xs; 502 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 503 int target; 504 505 target = xs->sc_link->scsipi_scsi.target; 506 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 507 ahc->devqueue_blocked[target]++; 508 scb->flags |= SCB_FREEZE_QUEUE; 509 } 510 } 511 512 static __inline void 513 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 514 { 515 xs->error = status; 516 } 517 518 static __inline struct ahc_initiator_tinfo * 519 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 520 u_int remote_id, struct tmode_tstate **tstate) 521 { 522 /* 523 * Transfer data structures are stored from the perspective 524 * of the target role. Since the parameters for a connection 525 * in the initiator role to a given target are the same as 526 * when the roles are reversed, we pretend we are the target. 527 */ 528 if (channel == 'B') 529 our_id += 8; 530 *tstate = ahc->enabled_targets[our_id]; 531 return (&(*tstate)->transinfo[remote_id]); 532 } 533 534 static void 535 ahc_run_qoutfifo(struct ahc_softc *ahc) 536 { 537 struct scb *scb; 538 u_int scb_index; 539 540 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 541 256, BUS_DMASYNC_POSTREAD); 542 543 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 544 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 545 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 546 547 scb = &ahc->scb_data->scbarray[scb_index]; 548 if (scb_index >= ahc->scb_data->numscbs 549 || (scb->flags & SCB_ACTIVE) == 0) { 550 printf("%s: WARNING no command for scb %d " 551 "(cmdcmplt)\nQOUTPOS = %d\n", 552 ahc_name(ahc), scb_index, 553 ahc->qoutfifonext - 1); 554 continue; 555 } 556 557 /* 558 * Save off the residual 559 * if there is one. 560 */ 561 if (scb->hscb->residual_SG_count != 0) 562 ahc_calc_residual(scb); 563 else 564 scb->xs->resid = 0; 565 #ifdef AHC_DEBUG 566 if (ahc_debug & AHC_SHOWSCBS) { 567 scsi_print_addr(scb->xs->sc_link); 568 printf("run_qoutfifo: SCB %x complete\n", 569 scb->hscb->tag); 570 } 571 #endif 572 ahc_done(ahc, scb); 573 } 574 } 575 576 577 /* 578 * An scb (and hence an scb entry on the board) is put onto the 579 * free list. 580 */ 581 static void 582 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 583 { 584 struct hardware_scb *hscb; 585 int opri; 586 587 hscb = scb->hscb; 588 589 #ifdef AHC_DEBUG 590 if (ahc_debug & AHC_SHOWSCBALLOC) 591 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 592 #endif 593 594 opri = splbio(); 595 596 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 597 (scb->flags & SCB_RECOVERY_SCB) != 0) { 598 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 599 ahc->queue_blocked = 0; 600 } 601 602 /* Clean up for the next user */ 603 scb->flags = SCB_FREE; 604 hscb->control = 0; 605 hscb->status = 0; 606 607 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 608 609 splx(opri); 610 } 611 612 /* 613 * Get a free scb, either one already assigned to a hardware slot 614 * on the adapter or one that will require an SCB to be paged out before 615 * use. If there are none, see if we can allocate a new SCB. Otherwise 616 * either return an error or sleep. 617 */ 618 static __inline struct scb * 619 ahcgetscb(struct ahc_softc *ahc) 620 { 621 struct scb *scbp; 622 int opri;; 623 624 opri = splbio(); 625 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 626 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 627 } else { 628 ahcallocscbs(ahc); 629 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 630 if (scbp != NULL) 631 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 632 } 633 634 splx(opri); 635 636 #ifdef AHC_DEBUG 637 if (ahc_debug & AHC_SHOWSCBALLOC) { 638 if (scbp != NULL) 639 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 640 scbp->hscb->tag); 641 else 642 printf("%s: failed to allocate new SCB\n", 643 ahc_name(ahc)); 644 } 645 #endif 646 647 return (scbp); 648 } 649 650 static int 651 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 652 bus_dma_tag_t tag; 653 int size; 654 int flags; 655 bus_dmamap_t *mapp; 656 caddr_t *vaddr; 657 bus_addr_t *baddr; 658 bus_dma_segment_t *seg; 659 int *nseg; 660 const char *myname, *what; 661 { 662 int error, level = 0; 663 664 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 665 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 666 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 667 myname, what, error); 668 goto out; 669 } 670 level++; 671 672 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 673 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 674 printf("%s: failed to map DMA mem for %s, error = %d\n", 675 myname, what, error); 676 goto out; 677 } 678 level++; 679 680 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 681 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 682 printf("%s: failed to create DMA map for %s, error = %d\n", 683 myname, what, error); 684 goto out; 685 } 686 level++; 687 688 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 689 BUS_DMA_NOWAIT)) != 0) { 690 printf("%s: failed to load DMA map for %s, error = %d\n", 691 myname, what, error); 692 goto out; 693 } 694 695 *baddr = (*mapp)->dm_segs[0].ds_addr; 696 697 #ifdef AHC_DEBUG 698 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 699 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 700 *nseg, size); 701 #endif 702 703 return 0; 704 out: 705 switch (level) { 706 case 3: 707 bus_dmamap_destroy(tag, *mapp); 708 /* FALLTHROUGH */ 709 case 2: 710 bus_dmamem_unmap(tag, *vaddr, size); 711 /* FALLTHROUGH */ 712 case 1: 713 bus_dmamem_free(tag, seg, *nseg); 714 break; 715 default: 716 break; 717 } 718 719 return error; 720 } 721 722 static void 723 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 724 bus_dma_tag_t tag; 725 int size; 726 bus_dmamap_t map; 727 caddr_t vaddr; 728 bus_dma_segment_t *seg; 729 int nseg; 730 { 731 732 bus_dmamap_unload(tag, map); 733 bus_dmamap_destroy(tag, map); 734 bus_dmamem_unmap(tag, vaddr, size); 735 bus_dmamem_free(tag, seg, nseg); 736 } 737 738 char * 739 ahc_name(struct ahc_softc *ahc) 740 { 741 return (ahc->sc_dev.dv_xname); 742 } 743 744 #ifdef AHC_DEBUG 745 static void 746 ahc_print_scb(struct scb *scb) 747 { 748 struct hardware_scb *hscb = scb->hscb; 749 750 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 751 scb, 752 hscb->tag, 753 hscb->control, 754 hscb->tcl, 755 hscb->cmdlen, 756 (unsigned long)le32toh(hscb->cmdpointer)); 757 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 758 le32toh(hscb->datalen), 759 (unsigned long)(le32toh(hscb->data)), 760 hscb->SG_count, 761 (unsigned long)(le32toh(hscb->SG_pointer))); 762 printf(" sg_addr:%lx sg_len:%lu\n", 763 (unsigned long)(le32toh(scb->sg_list[0].addr)), 764 (unsigned long)(le32toh(scb->sg_list[0].len)); 765 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 766 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 767 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 768 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 769 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 770 } 771 #endif 772 773 static struct { 774 u_int8_t errno; 775 char *errmesg; 776 } hard_error[] = { 777 { ILLHADDR, "Illegal Host Access" }, 778 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 779 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 780 { SQPARERR, "Sequencer Parity Error" }, 781 { DPARERR, "Data-path Parity Error" }, 782 { MPARERR, "Scratch or SCB Memory Parity Error" }, 783 { PCIERRSTAT, "PCI Error detected" }, 784 { CIOPARERR, "CIOBUS Parity Error" }, 785 }; 786 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 787 788 static struct { 789 u_int8_t phase; 790 u_int8_t mesg_out; /* Message response to parity errors */ 791 char *phasemsg; 792 } phase_table[] = { 793 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 794 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 795 { P_COMMAND, MSG_NOOP, "in Command phase" }, 796 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 797 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 798 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 799 { P_BUSFREE, MSG_NOOP, "while idle" }, 800 { 0, MSG_NOOP, "in unknown phase" } 801 }; 802 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 803 804 /* 805 * Valid SCSIRATE values. (p. 3-17) 806 * Provides a mapping of tranfer periods in ns to the proper value to 807 * stick in the scsiscfr reg to use that transfer rate. 808 */ 809 #define AHC_SYNCRATE_DT 0 810 #define AHC_SYNCRATE_ULTRA2 1 811 #define AHC_SYNCRATE_ULTRA 2 812 #define AHC_SYNCRATE_FAST 5 813 static struct ahc_syncrate ahc_syncrates[] = { 814 /* ultra2 fast/ultra period rate */ 815 { 0x42, 0x000, 9, "80.0" }, 816 { 0x03, 0x000, 10, "40.0" }, 817 { 0x04, 0x000, 11, "33.0" }, 818 { 0x05, 0x100, 12, "20.0" }, 819 { 0x06, 0x110, 15, "16.0" }, 820 { 0x07, 0x120, 18, "13.4" }, 821 { 0x08, 0x000, 25, "10.0" }, 822 { 0x19, 0x010, 31, "8.0" }, 823 { 0x1a, 0x020, 37, "6.67" }, 824 { 0x1b, 0x030, 43, "5.7" }, 825 { 0x1c, 0x040, 50, "5.0" }, 826 { 0x00, 0x050, 56, "4.4" }, 827 { 0x00, 0x060, 62, "4.0" }, 828 { 0x00, 0x070, 68, "3.6" }, 829 { 0x00, 0x000, 0, NULL } 830 }; 831 832 /* 833 * Allocate a controller structure for a new device and initialize it. 834 */ 835 int 836 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 837 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 838 ahc_flag flags) 839 { 840 struct scb_data *scb_data; 841 842 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 843 if (scb_data == NULL) { 844 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 845 return -1; 846 } 847 bzero(scb_data, sizeof (struct scb_data)); 848 LIST_INIT(&ahc->pending_ccbs); 849 ahc->tag = st; 850 ahc->bsh = sh; 851 ahc->parent_dmat = parent_dmat; 852 ahc->chip = chip; 853 ahc->features = features; 854 ahc->flags = flags; 855 ahc->scb_data = scb_data; 856 857 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 858 /* The IRQMS bit is only valid on VL and EISA chips */ 859 if ((ahc->chip & AHC_PCI) != 0) 860 ahc->unpause &= ~IRQMS; 861 ahc->pause = ahc->unpause | PAUSE; 862 return (0); 863 } 864 865 void 866 ahc_free(ahc) 867 struct ahc_softc *ahc; 868 { 869 ahcfiniscbdata(ahc); 870 if (ahc->init_level != 0) 871 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 872 ahc->shared_data_dmamap, ahc->qoutfifo, 873 &ahc->shared_data_seg, ahc->shared_data_nseg); 874 875 if (ahc->scb_data != NULL) 876 free(ahc->scb_data, M_DEVBUF); 877 if (ahc->bus_data != NULL) 878 free(ahc->bus_data, M_DEVBUF); 879 return; 880 } 881 882 static int 883 ahcinitscbdata(struct ahc_softc *ahc) 884 { 885 struct scb_data *scb_data; 886 int i; 887 888 scb_data = ahc->scb_data; 889 SLIST_INIT(&scb_data->free_scbs); 890 SLIST_INIT(&scb_data->sg_maps); 891 892 /* Allocate SCB resources */ 893 scb_data->scbarray = 894 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 895 M_DEVBUF, M_NOWAIT); 896 if (scb_data->scbarray == NULL) 897 return (ENOMEM); 898 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 899 900 /* Determine the number of hardware SCBs and initialize them */ 901 902 scb_data->maxhscbs = ahc_probe_scbs(ahc); 903 /* SCB 0 heads the free list */ 904 ahc_outb(ahc, FREE_SCBH, 0); 905 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 906 ahc_outb(ahc, SCBPTR, i); 907 908 /* Clear the control byte. */ 909 ahc_outb(ahc, SCB_CONTROL, 0); 910 911 /* Set the next pointer */ 912 ahc_outb(ahc, SCB_NEXT, i+1); 913 914 /* Make the tag number invalid */ 915 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 916 } 917 918 /* Make sure that the last SCB terminates the free list */ 919 ahc_outb(ahc, SCBPTR, i-1); 920 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 921 922 /* Ensure we clear the 0 SCB's control byte. */ 923 ahc_outb(ahc, SCBPTR, 0); 924 ahc_outb(ahc, SCB_CONTROL, 0); 925 926 scb_data->maxhscbs = i; 927 928 if (ahc->scb_data->maxhscbs == 0) 929 panic("%s: No SCB space found", ahc_name(ahc)); 930 931 /* 932 * Create our DMA tags. These tags define the kinds of device 933 * accessable memory allocations and memory mappings we will 934 * need to perform during normal operation. 935 * 936 * Unless we need to further restrict the allocation, we rely 937 * on the restrictions of the parent dmat, hence the common 938 * use of MAXADDR and MAXSIZE. 939 */ 940 941 if (ahc_createdmamem(ahc->parent_dmat, 942 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 943 &scb_data->hscb_dmamap, 944 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 945 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 946 "hardware SCB structures") < 0) 947 goto error_exit; 948 949 scb_data->init_level++; 950 951 if (ahc_createdmamem(ahc->parent_dmat, 952 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 953 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 954 &scb_data->sense_busaddr, &scb_data->sense_seg, 955 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 956 goto error_exit; 957 958 scb_data->init_level++; 959 960 /* Perform initial CCB allocation */ 961 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 962 ahcallocscbs(ahc); 963 964 if (scb_data->numscbs == 0) { 965 printf("%s: ahc_init_scb_data - " 966 "Unable to allocate initial scbs\n", 967 ahc_name(ahc)); 968 goto error_exit; 969 } 970 971 scb_data->init_level++; 972 973 /* 974 * Note that we were successfull 975 */ 976 return 0; 977 978 error_exit: 979 980 return ENOMEM; 981 } 982 983 static void 984 ahcfiniscbdata(struct ahc_softc *ahc) 985 { 986 struct scb_data *scb_data; 987 988 scb_data = ahc->scb_data; 989 990 switch (scb_data->init_level) { 991 default: 992 case 3: 993 { 994 struct sg_map_node *sg_map; 995 996 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 997 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 998 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 999 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1000 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1001 free(sg_map, M_DEVBUF); 1002 } 1003 } 1004 /*FALLTHROUGH*/ 1005 case 2: 1006 ahc_freedmamem(ahc->parent_dmat, 1007 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1008 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1009 &scb_data->sense_seg, scb_data->sense_nseg); 1010 /*FALLTHROUGH*/ 1011 case 1: 1012 ahc_freedmamem(ahc->parent_dmat, 1013 AHC_SCB_MAX * sizeof(struct hardware_scb), 1014 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1015 &scb_data->hscb_seg, scb_data->hscb_nseg); 1016 /*FALLTHROUGH*/ 1017 } 1018 if (scb_data->scbarray != NULL) 1019 free(scb_data->scbarray, M_DEVBUF); 1020 } 1021 1022 int 1023 ahc_reset(struct ahc_softc *ahc) 1024 { 1025 u_int sblkctl; 1026 int wait; 1027 1028 #ifdef AHC_DUMP_SEQ 1029 if (ahc->init_level == 0) 1030 ahc_dumpseq(ahc); 1031 #endif 1032 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1033 /* 1034 * Ensure that the reset has finished 1035 */ 1036 wait = 1000; 1037 do { 1038 DELAY(1000); 1039 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1040 1041 if (wait == 0) { 1042 printf("%s: WARNING - Failed chip reset! " 1043 "Trying to initialize anyway.\n", ahc_name(ahc)); 1044 } 1045 ahc_outb(ahc, HCNTRL, ahc->pause); 1046 1047 /* Determine channel configuration */ 1048 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1049 /* No Twin Channel PCI cards */ 1050 if ((ahc->chip & AHC_PCI) != 0) 1051 sblkctl &= ~SELBUSB; 1052 switch (sblkctl) { 1053 case 0: 1054 /* Single Narrow Channel */ 1055 break; 1056 case 2: 1057 /* Wide Channel */ 1058 ahc->features |= AHC_WIDE; 1059 break; 1060 case 8: 1061 /* Twin Channel */ 1062 ahc->features |= AHC_TWIN; 1063 break; 1064 default: 1065 printf(" Unsupported adapter type. Ignoring\n"); 1066 return(-1); 1067 } 1068 1069 return (0); 1070 } 1071 1072 /* 1073 * Called when we have an active connection to a target on the bus, 1074 * this function finds the nearest syncrate to the input period limited 1075 * by the capabilities of the bus connectivity of the target. 1076 */ 1077 static struct ahc_syncrate * 1078 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1079 u_int maxsync; 1080 1081 if ((ahc->features & AHC_ULTRA2) != 0) { 1082 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1083 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1084 maxsync = AHC_SYNCRATE_ULTRA2; 1085 } else { 1086 maxsync = AHC_SYNCRATE_ULTRA; 1087 } 1088 } else if ((ahc->features & AHC_ULTRA) != 0) { 1089 maxsync = AHC_SYNCRATE_ULTRA; 1090 } else { 1091 maxsync = AHC_SYNCRATE_FAST; 1092 } 1093 return (ahc_find_syncrate(ahc, period, maxsync)); 1094 } 1095 1096 /* 1097 * Look up the valid period to SCSIRATE conversion in our table. 1098 * Return the period and offset that should be sent to the target 1099 * if this was the beginning of an SDTR. 1100 */ 1101 static struct ahc_syncrate * 1102 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1103 { 1104 struct ahc_syncrate *syncrate; 1105 1106 syncrate = &ahc_syncrates[maxsync]; 1107 while ((syncrate->rate != NULL) 1108 && ((ahc->features & AHC_ULTRA2) == 0 1109 || (syncrate->sxfr_u2 != 0))) { 1110 1111 if (*period <= syncrate->period) { 1112 /* 1113 * When responding to a target that requests 1114 * sync, the requested rate may fall between 1115 * two rates that we can output, but still be 1116 * a rate that we can receive. Because of this, 1117 * we want to respond to the target with 1118 * the same rate that it sent to us even 1119 * if the period we use to send data to it 1120 * is lower. Only lower the response period 1121 * if we must. 1122 */ 1123 if (syncrate == &ahc_syncrates[maxsync]) 1124 *period = syncrate->period; 1125 break; 1126 } 1127 syncrate++; 1128 } 1129 1130 if ((*period == 0) 1131 || (syncrate->rate == NULL) 1132 || ((ahc->features & AHC_ULTRA2) != 0 1133 && (syncrate->sxfr_u2 == 0))) { 1134 /* Use asynchronous transfers. */ 1135 *period = 0; 1136 syncrate = NULL; 1137 } 1138 return (syncrate); 1139 } 1140 1141 static u_int 1142 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1143 { 1144 struct ahc_syncrate *syncrate; 1145 1146 if ((ahc->features & AHC_ULTRA2) != 0) 1147 scsirate &= SXFR_ULTRA2; 1148 else 1149 scsirate &= SXFR; 1150 1151 syncrate = &ahc_syncrates[maxsync]; 1152 while (syncrate->rate != NULL) { 1153 1154 if ((ahc->features & AHC_ULTRA2) != 0) { 1155 if (syncrate->sxfr_u2 == 0) 1156 break; 1157 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1158 return (syncrate->period); 1159 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1160 return (syncrate->period); 1161 } 1162 syncrate++; 1163 } 1164 return (0); /* async */ 1165 } 1166 1167 static void 1168 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1169 u_int *offset, int wide) 1170 { 1171 u_int maxoffset; 1172 1173 /* Limit offset to what we can do */ 1174 if (syncrate == NULL) { 1175 maxoffset = 0; 1176 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1177 maxoffset = MAX_OFFSET_ULTRA2; 1178 } else { 1179 if (wide) 1180 maxoffset = MAX_OFFSET_16BIT; 1181 else 1182 maxoffset = MAX_OFFSET_8BIT; 1183 } 1184 *offset = MIN(*offset, maxoffset); 1185 } 1186 1187 static void 1188 ahc_update_target_msg_request(struct ahc_softc *ahc, 1189 struct ahc_devinfo *devinfo, 1190 struct ahc_initiator_tinfo *tinfo, 1191 int force, int paused) 1192 { 1193 u_int targ_msg_req_orig; 1194 1195 targ_msg_req_orig = ahc->targ_msg_req; 1196 if (tinfo->current.period != tinfo->goal.period 1197 || tinfo->current.width != tinfo->goal.width 1198 || tinfo->current.offset != tinfo->goal.offset 1199 || (force 1200 && (tinfo->goal.period != 0 1201 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1202 ahc->targ_msg_req |= devinfo->target_mask; 1203 } else { 1204 ahc->targ_msg_req &= ~devinfo->target_mask; 1205 } 1206 1207 if (ahc->targ_msg_req != targ_msg_req_orig) { 1208 /* Update the message request bit for this target */ 1209 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1210 if (paused) { 1211 ahc_outb(ahc, TARGET_MSG_REQUEST, 1212 ahc->targ_msg_req & 0xFF); 1213 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1214 (ahc->targ_msg_req >> 8) & 0xFF); 1215 } else { 1216 ahc_outb(ahc, HS_MAILBOX, 1217 0x01 << HOST_MAILBOX_SHIFT); 1218 } 1219 } else { 1220 if (!paused) 1221 pause_sequencer(ahc); 1222 1223 ahc_outb(ahc, TARGET_MSG_REQUEST, 1224 ahc->targ_msg_req & 0xFF); 1225 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1226 (ahc->targ_msg_req >> 8) & 0xFF); 1227 1228 if (!paused) 1229 unpause_sequencer(ahc); 1230 } 1231 } 1232 } 1233 1234 static void 1235 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1236 struct ahc_syncrate *syncrate, 1237 u_int period, u_int offset, u_int type, int paused, int done) 1238 { 1239 struct ahc_initiator_tinfo *tinfo; 1240 struct tmode_tstate *tstate; 1241 u_int old_period; 1242 u_int old_offset; 1243 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1244 1245 if (syncrate == NULL) { 1246 period = 0; 1247 offset = 0; 1248 } 1249 1250 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1251 devinfo->target, &tstate); 1252 old_period = tinfo->current.period; 1253 old_offset = tinfo->current.offset; 1254 1255 if ((type & AHC_TRANS_CUR) != 0 1256 && (old_period != period || old_offset != offset)) { 1257 u_int scsirate; 1258 1259 scsirate = tinfo->scsirate; 1260 if ((ahc->features & AHC_ULTRA2) != 0) { 1261 1262 /* XXX */ 1263 /* Force single edge until DT is fully implemented */ 1264 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1265 if (syncrate != NULL) 1266 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1267 1268 if (active) 1269 ahc_outb(ahc, SCSIOFFSET, offset); 1270 } else { 1271 1272 scsirate &= ~(SXFR|SOFS); 1273 /* 1274 * Ensure Ultra mode is set properly for 1275 * this target. 1276 */ 1277 tstate->ultraenb &= ~devinfo->target_mask; 1278 if (syncrate != NULL) { 1279 if (syncrate->sxfr & ULTRA_SXFR) { 1280 tstate->ultraenb |= 1281 devinfo->target_mask; 1282 } 1283 scsirate |= syncrate->sxfr & SXFR; 1284 scsirate |= offset & SOFS; 1285 } 1286 if (active) { 1287 u_int sxfrctl0; 1288 1289 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1290 sxfrctl0 &= ~FAST20; 1291 if (tstate->ultraenb & devinfo->target_mask) 1292 sxfrctl0 |= FAST20; 1293 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1294 } 1295 } 1296 if (active) 1297 ahc_outb(ahc, SCSIRATE, scsirate); 1298 1299 tinfo->scsirate = scsirate; 1300 tinfo->current.period = period; 1301 tinfo->current.offset = offset; 1302 1303 /* Update the syncrates in any pending scbs */ 1304 ahc_update_pending_syncrates(ahc); 1305 } 1306 1307 /* 1308 * Print messages if we're verbose and at the end of a negotiation 1309 * cycle. 1310 */ 1311 if (done) { 1312 if (offset != 0) { 1313 printf("%s: target %d synchronous at %sMHz, " 1314 "offset = 0x%x\n", ahc_name(ahc), 1315 devinfo->target, syncrate->rate, offset); 1316 } else { 1317 printf("%s: target %d using " 1318 "asynchronous transfers\n", 1319 ahc_name(ahc), devinfo->target); 1320 } 1321 } 1322 1323 if ((type & AHC_TRANS_GOAL) != 0) { 1324 tinfo->goal.period = period; 1325 tinfo->goal.offset = offset; 1326 } 1327 1328 if ((type & AHC_TRANS_USER) != 0) { 1329 tinfo->user.period = period; 1330 tinfo->user.offset = offset; 1331 } 1332 1333 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1334 /*force*/FALSE, 1335 paused); 1336 } 1337 1338 static void 1339 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1340 u_int width, u_int type, int paused, int done) 1341 { 1342 struct ahc_initiator_tinfo *tinfo; 1343 struct tmode_tstate *tstate; 1344 u_int oldwidth; 1345 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1346 1347 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1348 devinfo->target, &tstate); 1349 oldwidth = tinfo->current.width; 1350 1351 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1352 u_int scsirate; 1353 1354 scsirate = tinfo->scsirate; 1355 scsirate &= ~WIDEXFER; 1356 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1357 scsirate |= WIDEXFER; 1358 1359 tinfo->scsirate = scsirate; 1360 1361 if (active) 1362 ahc_outb(ahc, SCSIRATE, scsirate); 1363 1364 tinfo->current.width = width; 1365 } 1366 1367 if (done) { 1368 printf("%s: target %d using %dbit transfers\n", 1369 ahc_name(ahc), devinfo->target, 1370 8 * (0x01 << width)); 1371 } 1372 1373 if ((type & AHC_TRANS_GOAL) != 0) 1374 tinfo->goal.width = width; 1375 if ((type & AHC_TRANS_USER) != 0) 1376 tinfo->user.width = width; 1377 1378 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1379 /*force*/FALSE, paused); 1380 } 1381 1382 static void 1383 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1384 { 1385 struct ahc_initiator_tinfo *tinfo; 1386 struct tmode_tstate *tstate; 1387 1388 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1389 devinfo->target, &tstate); 1390 1391 if (enable) 1392 tstate->tagenable |= devinfo->target_mask; 1393 else 1394 tstate->tagenable &= ~devinfo->target_mask; 1395 } 1396 1397 /* 1398 * Attach all the sub-devices we can find 1399 */ 1400 int 1401 ahc_attach(struct ahc_softc *ahc) 1402 { 1403 TAILQ_INIT(&ahc->sc_q); 1404 1405 ahc->sc_adapter.scsipi_cmd = ahc_action; 1406 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1407 ahc->sc_link.type = BUS_SCSI; 1408 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1409 ahc->sc_link.scsipi_scsi.channel = 0; 1410 ahc->sc_link.scsipi_scsi.max_target = 1411 (ahc->features & AHC_WIDE) ? 15 : 7; 1412 ahc->sc_link.scsipi_scsi.max_lun = 7; 1413 ahc->sc_link.adapter_softc = ahc; 1414 ahc->sc_link.adapter = &ahc->sc_adapter; 1415 ahc->sc_link.openings = 2; 1416 ahc->sc_link.device = &ahc_dev; 1417 1418 if (ahc->features & AHC_TWIN) { 1419 ahc->sc_link_b = ahc->sc_link; 1420 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1421 ahc->sc_link_b.scsipi_scsi.channel = 1; 1422 } 1423 1424 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1425 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1426 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1427 if (ahc->features & AHC_TWIN) 1428 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1429 } else { 1430 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1431 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1432 } 1433 return 1; 1434 } 1435 1436 static void 1437 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1438 { 1439 u_int saved_tcl; 1440 role_t role; 1441 int our_id; 1442 1443 if (ahc_inb(ahc, SSTAT0) & TARGET) 1444 role = ROLE_TARGET; 1445 else 1446 role = ROLE_INITIATOR; 1447 1448 if (role == ROLE_TARGET 1449 && (ahc->features & AHC_MULTI_TID) != 0 1450 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1451 /* We were selected, so pull our id from TARGIDIN */ 1452 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1453 } else if ((ahc->features & AHC_ULTRA2) != 0) 1454 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1455 else 1456 our_id = ahc_inb(ahc, SCSIID) & OID; 1457 1458 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1459 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1460 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1461 role); 1462 } 1463 1464 static void 1465 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1466 u_int lun, char channel, role_t role) 1467 { 1468 devinfo->our_scsiid = our_id; 1469 devinfo->target = target; 1470 devinfo->lun = lun; 1471 devinfo->target_offset = target; 1472 devinfo->channel = channel; 1473 devinfo->role = role; 1474 if (channel == 'B') 1475 devinfo->target_offset += 8; 1476 devinfo->target_mask = (0x01 << devinfo->target_offset); 1477 } 1478 1479 /* 1480 * Catch an interrupt from the adapter 1481 */ 1482 int 1483 ahc_intr(void *arg) 1484 { 1485 struct ahc_softc *ahc; 1486 u_int intstat; 1487 1488 ahc = (struct ahc_softc *)arg; 1489 1490 intstat = ahc_inb(ahc, INTSTAT); 1491 1492 /* 1493 * Any interrupts to process? 1494 */ 1495 if ((intstat & INT_PEND) == 0) { 1496 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1497 #ifdef AHC_DEBUG 1498 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1499 ahc_name(ahc), 1500 ahc_inb(ahc, CCHADDR) | 1501 (ahc_inb(ahc, CCHADDR+1) << 8) 1502 | (ahc_inb(ahc, CCHADDR+2) << 16) 1503 | (ahc_inb(ahc, CCHADDR+3) << 24), 1504 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1505 | (ahc_inb(ahc, HADDR+2) << 16) 1506 | (ahc_inb(ahc, HADDR+3) << 24), 1507 ahc_inb(ahc, SEQADDR0) | 1508 (ahc_inb(ahc, SEQADDR1) << 8)); 1509 #endif 1510 return 1; 1511 } 1512 return 0; 1513 } 1514 1515 #ifdef AHC_DEBUG 1516 if (ahc_debug & AHC_SHOWINTR) { 1517 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1518 } 1519 #endif 1520 1521 if (intstat & CMDCMPLT) { 1522 ahc_outb(ahc, CLRINT, CLRCMDINT); 1523 ahc_run_qoutfifo(ahc); 1524 } 1525 if (intstat & BRKADRINT) { 1526 /* 1527 * We upset the sequencer :-( 1528 * Lookup the error message 1529 */ 1530 int i, error, num_errors; 1531 1532 error = ahc_inb(ahc, ERROR); 1533 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1534 for (i = 0; error != 1 && i < num_errors; i++) 1535 error >>= 1; 1536 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1537 ahc_name(ahc), hard_error[i].errmesg, 1538 ahc_inb(ahc, SEQADDR0) | 1539 (ahc_inb(ahc, SEQADDR1) << 8)); 1540 1541 /* Tell everyone that this HBA is no longer availible */ 1542 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1543 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1544 XS_DRIVER_STUFFUP); 1545 } 1546 if (intstat & SEQINT) 1547 ahc_handle_seqint(ahc, intstat); 1548 1549 if (intstat & SCSIINT) 1550 ahc_handle_scsiint(ahc, intstat); 1551 1552 return 1; 1553 } 1554 1555 static struct tmode_tstate * 1556 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1557 { 1558 struct tmode_tstate *master_tstate; 1559 struct tmode_tstate *tstate; 1560 int i, s; 1561 1562 master_tstate = ahc->enabled_targets[ahc->our_id]; 1563 if (channel == 'B') { 1564 scsi_id += 8; 1565 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1566 } 1567 if (ahc->enabled_targets[scsi_id] != NULL 1568 && ahc->enabled_targets[scsi_id] != master_tstate) 1569 panic("%s: ahc_alloc_tstate - Target already allocated", 1570 ahc_name(ahc)); 1571 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1572 if (tstate == NULL) 1573 return (NULL); 1574 1575 /* 1576 * If we have allocated a master tstate, copy user settings from 1577 * the master tstate (taken from SRAM or the EEPROM) for this 1578 * channel, but reset our current and goal settings to async/narrow 1579 * until an initiator talks to us. 1580 */ 1581 if (master_tstate != NULL) { 1582 bcopy(master_tstate, tstate, sizeof(*tstate)); 1583 tstate->ultraenb = 0; 1584 for (i = 0; i < 16; i++) { 1585 bzero(&tstate->transinfo[i].current, 1586 sizeof(tstate->transinfo[i].current)); 1587 bzero(&tstate->transinfo[i].goal, 1588 sizeof(tstate->transinfo[i].goal)); 1589 } 1590 } else 1591 bzero(tstate, sizeof(*tstate)); 1592 s = splbio(); 1593 ahc->enabled_targets[scsi_id] = tstate; 1594 splx(s); 1595 return (tstate); 1596 } 1597 1598 #if UNUSED 1599 static void 1600 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1601 { 1602 struct tmode_tstate *tstate; 1603 1604 /* Don't clean up the entry for our initiator role */ 1605 if ((ahc->flags & AHC_INITIATORMODE) != 0 1606 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1607 || (channel == 'A' && scsi_id == ahc->our_id)) 1608 && force == FALSE) 1609 return; 1610 1611 if (channel == 'B') 1612 scsi_id += 8; 1613 tstate = ahc->enabled_targets[scsi_id]; 1614 if (tstate != NULL) 1615 free(tstate, M_DEVBUF); 1616 ahc->enabled_targets[scsi_id] = NULL; 1617 } 1618 #endif 1619 1620 static void 1621 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1622 { 1623 struct scb *scb; 1624 struct ahc_devinfo devinfo; 1625 1626 ahc_fetch_devinfo(ahc, &devinfo); 1627 1628 /* 1629 * Clear the upper byte that holds SEQINT status 1630 * codes and clear the SEQINT bit. We will unpause 1631 * the sequencer, if appropriate, after servicing 1632 * the request. 1633 */ 1634 ahc_outb(ahc, CLRINT, CLRSEQINT); 1635 switch (intstat & SEQINT_MASK) { 1636 case NO_MATCH: 1637 { 1638 /* Ensure we don't leave the selection hardware on */ 1639 ahc_outb(ahc, SCSISEQ, 1640 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1641 1642 printf("%s:%c:%d: no active SCB for reconnecting " 1643 "target - issuing BUS DEVICE RESET\n", 1644 ahc_name(ahc), devinfo.channel, devinfo.target); 1645 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1646 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1647 ahc_inb(ahc, SEQ_FLAGS)); 1648 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1649 ahc->msgout_len = 1; 1650 ahc->msgout_index = 0; 1651 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1652 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1653 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1654 break; 1655 } 1656 case UPDATE_TMSG_REQ: 1657 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1658 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1659 (ahc->targ_msg_req >> 8) & 0xFF); 1660 ahc_outb(ahc, HS_MAILBOX, 0); 1661 break; 1662 case SEND_REJECT: 1663 { 1664 u_int rejbyte = ahc_inb(ahc, ACCUM); 1665 printf("%s:%c:%d: Warning - unknown message received from " 1666 "target (0x%x). Rejecting\n", 1667 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1668 break; 1669 } 1670 case NO_IDENT: 1671 { 1672 /* 1673 * The reconnecting target either did not send an identify 1674 * message, or did, but we didn't find and SCB to match and 1675 * before it could respond to our ATN/abort, it hit a dataphase. 1676 * The only safe thing to do is to blow it away with a bus 1677 * reset. 1678 */ 1679 int found; 1680 1681 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1682 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1683 ahc_name(ahc), devinfo.channel, devinfo.target, 1684 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1685 found = ahc_reset_channel(ahc, devinfo.channel, 1686 /*initiate reset*/TRUE); 1687 printf("%s: Issued Channel %c Bus Reset. " 1688 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1689 found); 1690 return; 1691 } 1692 case BAD_PHASE: 1693 { 1694 u_int lastphase; 1695 1696 lastphase = ahc_inb(ahc, LASTPHASE); 1697 if (lastphase == P_BUSFREE) { 1698 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1699 ahc_name(ahc), devinfo.channel, devinfo.target, 1700 ahc_inb(ahc, SCSISIGI)); 1701 restart_sequencer(ahc); 1702 return; 1703 } else { 1704 printf("%s:%c:%d: unknown scsi bus phase %x. " 1705 "Attempting to continue\n", 1706 ahc_name(ahc), devinfo.channel, devinfo.target, 1707 ahc_inb(ahc, SCSISIGI)); 1708 } 1709 break; 1710 } 1711 case BAD_STATUS: 1712 { 1713 u_int scb_index; 1714 struct hardware_scb *hscb; 1715 struct scsipi_xfer *xs; 1716 /* 1717 * The sequencer will notify us when a command 1718 * has an error that would be of interest to 1719 * the kernel. This allows us to leave the sequencer 1720 * running in the common case of command completes 1721 * without error. The sequencer will already have 1722 * dma'd the SCB back up to us, so we can reference 1723 * the in kernel copy directly. 1724 */ 1725 scb_index = ahc_inb(ahc, SCB_TAG); 1726 scb = &ahc->scb_data->scbarray[scb_index]; 1727 1728 /* ahc_print_scb(scb); */ 1729 1730 /* 1731 * Set the default return value to 0 (don't 1732 * send sense). The sense code will change 1733 * this if needed. 1734 */ 1735 ahc_outb(ahc, RETURN_1, 0); 1736 if (!(scb_index < ahc->scb_data->numscbs 1737 && (scb->flags & SCB_ACTIVE) != 0)) { 1738 printf("%s:%c:%d: ahc_intr - referenced scb " 1739 "not valid during seqint 0x%x scb(%d)\n", 1740 ahc_name(ahc), devinfo.channel, 1741 devinfo.target, intstat, scb_index); 1742 goto unpause; 1743 } 1744 1745 hscb = scb->hscb; 1746 xs = scb->xs; 1747 1748 /* Don't want to clobber the original sense code */ 1749 if ((scb->flags & SCB_SENSE) != 0) { 1750 /* 1751 * Clear the SCB_SENSE Flag and have 1752 * the sequencer do a normal command 1753 * complete. 1754 */ 1755 scb->flags &= ~SCB_SENSE; 1756 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1757 break; 1758 } 1759 /* Freeze the queue unit the client sees the error. */ 1760 ahc_freeze_devq(ahc, xs->sc_link); 1761 ahc_freeze_ccb(scb); 1762 xs->status = hscb->status; 1763 switch (hscb->status) { 1764 case SCSI_STATUS_OK: 1765 printf("%s: Interrupted for status of 0???\n", 1766 ahc_name(ahc)); 1767 break; 1768 case SCSI_STATUS_CMD_TERMINATED: 1769 case SCSI_STATUS_CHECK_COND: 1770 #if defined(AHC_DEBUG) 1771 if (ahc_debug & AHC_SHOWSENSE) { 1772 scsi_print_addr(xs->sc_link); 1773 printf("Check Status, resid %d datalen %d\n", 1774 xs->resid, xs->datalen); 1775 } 1776 #endif 1777 1778 if (xs->error == XS_NOERROR && 1779 !(scb->flags & SCB_SENSE)) { 1780 struct ahc_dma_seg *sg; 1781 struct scsipi_sense *sc; 1782 struct ahc_initiator_tinfo *tinfo; 1783 struct tmode_tstate *tstate; 1784 1785 sg = scb->sg_list; 1786 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1787 /* 1788 * Save off the residual if there is one. 1789 */ 1790 if (hscb->residual_SG_count != 0) 1791 ahc_calc_residual(scb); 1792 else 1793 xs->resid = 0; 1794 1795 #ifdef AHC_DEBUG 1796 if (ahc_debug & AHC_SHOWSENSE) { 1797 scsi_print_addr(xs->sc_link); 1798 printf("Sending Sense\n"); 1799 } 1800 #endif 1801 sg->addr = ahc->scb_data->sense_busaddr + 1802 (hscb->tag*sizeof(struct scsipi_sense_data)); 1803 sg->len = sizeof (struct scsipi_sense_data); 1804 1805 sc->opcode = REQUEST_SENSE; 1806 sc->byte2 = SCB_LUN(scb) << 5; 1807 sc->unused[0] = 0; 1808 sc->unused[1] = 0; 1809 sc->length = sg->len; 1810 sc->control = 0; 1811 1812 /* 1813 * Would be nice to preserve DISCENB here, 1814 * but due to the way we page SCBs, we can't. 1815 */ 1816 hscb->control = 0; 1817 1818 /* 1819 * This request sense could be because the 1820 * the device lost power or in some other 1821 * way has lost our transfer negotiations. 1822 * Renegotiate if appropriate. Unit attention 1823 * errors will be reported before any data 1824 * phases occur. 1825 */ 1826 ahc_calc_residual(scb); 1827 #if defined(AHC_DEBUG) 1828 if (ahc_debug & AHC_SHOWSENSE) { 1829 scsi_print_addr(xs->sc_link); 1830 printf("Sense: datalen %d resid %d" 1831 "chan %d id %d targ %d\n", 1832 xs->datalen, xs->resid, 1833 devinfo.channel, devinfo.our_scsiid, 1834 devinfo.target); 1835 } 1836 #endif 1837 if (xs->datalen > 0 && 1838 xs->resid == xs->datalen) { 1839 tinfo = ahc_fetch_transinfo(ahc, 1840 devinfo.channel, 1841 devinfo.our_scsiid, 1842 devinfo.target, 1843 &tstate); 1844 ahc_update_target_msg_request(ahc, 1845 &devinfo, 1846 tinfo, 1847 /*force*/TRUE, 1848 /*paused*/TRUE); 1849 } 1850 hscb->status = 0; 1851 hscb->SG_count = 1; 1852 hscb->SG_pointer = scb->sg_list_phys; 1853 hscb->data = sg->addr; 1854 hscb->datalen = sg->len; 1855 hscb->cmdpointer = hscb->cmdstore_busaddr; 1856 hscb->cmdlen = sizeof(*sc); 1857 scb->sg_count = hscb->SG_count; 1858 ahc_swap_hscb(hscb); 1859 ahc_swap_sg(scb->sg_list); 1860 scb->flags |= SCB_SENSE; 1861 /* 1862 * Ensure the target is busy since this 1863 * will be an untagged request. 1864 */ 1865 ahc_busy_tcl(ahc, scb); 1866 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1867 1868 /* 1869 * Ensure we have enough time to actually 1870 * retrieve the sense. 1871 */ 1872 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1873 untimeout(ahc_timeout, (caddr_t)scb); 1874 timeout(ahc_timeout, (caddr_t)scb, 1875 5 * hz); 1876 } 1877 } 1878 break; 1879 case SCSI_STATUS_BUSY: 1880 case SCSI_STATUS_QUEUE_FULL: 1881 /* 1882 * Requeue any transactions that haven't been 1883 * sent yet. 1884 */ 1885 ahc_freeze_devq(ahc, xs->sc_link); 1886 ahc_freeze_ccb(scb); 1887 break; 1888 } 1889 break; 1890 } 1891 case TRACE_POINT: 1892 { 1893 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1894 ahc_inb(ahc, DFCNTRL)); 1895 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1896 ahc_inb(ahc, DFSTATUS)); 1897 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1898 ahc_inb(ahc, SSTAT0), 1899 ahc_inb(ahc, SCB_DATACNT)); 1900 break; 1901 } 1902 case HOST_MSG_LOOP: 1903 { 1904 /* 1905 * The sequencer has encountered a message phase 1906 * that requires host assistance for completion. 1907 * While handling the message phase(s), we will be 1908 * notified by the sequencer after each byte is 1909 * transfered so we can track bus phases. 1910 * 1911 * If this is the first time we've seen a HOST_MSG_LOOP, 1912 * initialize the state of the host message loop. 1913 */ 1914 if (ahc->msg_type == MSG_TYPE_NONE) { 1915 u_int bus_phase; 1916 1917 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1918 if (bus_phase != P_MESGIN 1919 && bus_phase != P_MESGOUT) { 1920 printf("ahc_intr: HOST_MSG_LOOP bad " 1921 "phase 0x%x\n", 1922 bus_phase); 1923 /* 1924 * Probably transitioned to bus free before 1925 * we got here. Just punt the message. 1926 */ 1927 ahc_clear_intstat(ahc); 1928 restart_sequencer(ahc); 1929 } 1930 1931 if (devinfo.role == ROLE_INITIATOR) { 1932 struct scb *scb; 1933 u_int scb_index; 1934 1935 scb_index = ahc_inb(ahc, SCB_TAG); 1936 scb = &ahc->scb_data->scbarray[scb_index]; 1937 1938 if (bus_phase == P_MESGOUT) 1939 ahc_setup_initiator_msgout(ahc, 1940 &devinfo, 1941 scb); 1942 else { 1943 ahc->msg_type = 1944 MSG_TYPE_INITIATOR_MSGIN; 1945 ahc->msgin_index = 0; 1946 } 1947 } else { 1948 if (bus_phase == P_MESGOUT) { 1949 ahc->msg_type = 1950 MSG_TYPE_TARGET_MSGOUT; 1951 ahc->msgin_index = 0; 1952 } else 1953 /* XXX Ever executed??? */ 1954 ahc_setup_target_msgin(ahc, &devinfo); 1955 } 1956 } 1957 1958 /* Pass a NULL path so that handlers generate their own */ 1959 ahc_handle_message_phase(ahc, /*path*/NULL); 1960 break; 1961 } 1962 case PERR_DETECTED: 1963 { 1964 /* 1965 * If we've cleared the parity error interrupt 1966 * but the sequencer still believes that SCSIPERR 1967 * is true, it must be that the parity error is 1968 * for the currently presented byte on the bus, 1969 * and we are not in a phase (data-in) where we will 1970 * eventually ack this byte. Ack the byte and 1971 * throw it away in the hope that the target will 1972 * take us to message out to deliver the appropriate 1973 * error message. 1974 */ 1975 if ((intstat & SCSIINT) == 0 1976 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1977 u_int curphase; 1978 1979 /* 1980 * The hardware will only let you ack bytes 1981 * if the expected phase in SCSISIGO matches 1982 * the current phase. Make sure this is 1983 * currently the case. 1984 */ 1985 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1986 ahc_outb(ahc, LASTPHASE, curphase); 1987 ahc_outb(ahc, SCSISIGO, curphase); 1988 ahc_inb(ahc, SCSIDATL); 1989 } 1990 break; 1991 } 1992 case DATA_OVERRUN: 1993 { 1994 /* 1995 * When the sequencer detects an overrun, it 1996 * places the controller in "BITBUCKET" mode 1997 * and allows the target to complete its transfer. 1998 * Unfortunately, none of the counters get updated 1999 * when the controller is in this mode, so we have 2000 * no way of knowing how large the overrun was. 2001 */ 2002 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2003 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2004 int i; 2005 2006 scb = &ahc->scb_data->scbarray[scbindex]; 2007 for (i = 0; i < num_phases; i++) { 2008 if (lastphase == phase_table[i].phase) 2009 break; 2010 } 2011 scsi_print_addr(scb->xs->sc_link); 2012 printf("data overrun detected %s." 2013 " Tag == 0x%x.\n", 2014 phase_table[i].phasemsg, 2015 scb->hscb->tag); 2016 scsi_print_addr(scb->xs->sc_link); 2017 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2018 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2019 scb->xs->datalen, scb->sg_count); 2020 if (scb->sg_count > 0) { 2021 for (i = 0; i < scb->sg_count; i++) { 2022 printf("sg[%d] - Addr 0x%x : Length %d\n", 2023 i, 2024 le32toh(scb->sg_list[i].addr), 2025 le32toh(scb->sg_list[i].len)); 2026 } 2027 } 2028 /* 2029 * Set this and it will take affect when the 2030 * target does a command complete. 2031 */ 2032 ahc_freeze_devq(ahc, scb->xs->sc_link); 2033 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2034 ahc_freeze_ccb(scb); 2035 break; 2036 } 2037 case TRACEPOINT: 2038 { 2039 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2040 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2041 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2042 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2043 printf("TRACEPOINT: CCHADDR = %x\n", 2044 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2045 | (ahc_inb(ahc, CCHADDR+2) << 16) 2046 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2047 #if 0 2048 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2049 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2050 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2051 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2052 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2053 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2054 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2055 ahc_inb(ahc, CCHADDR) 2056 | (ahc_inb(ahc, CCHADDR+1) << 8) 2057 | (ahc_inb(ahc, CCHADDR+2) << 16) 2058 | (ahc_inb(ahc, CCHADDR+3) << 24), 2059 ahc_inb(ahc, CCHCNT) 2060 | (ahc_inb(ahc, CCHCNT+1) << 8) 2061 | (ahc_inb(ahc, CCHCNT+2) << 16), 2062 ahc_inb(ahc, SCBPTR)); 2063 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2064 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2065 #if DDB > 0 2066 cpu_Debugger(); 2067 #endif 2068 #endif 2069 break; 2070 } 2071 #if NOT_YET 2072 /* XXX Fill these in later */ 2073 case MESG_BUFFER_BUSY: 2074 break; 2075 case MSGIN_PHASEMIS: 2076 break; 2077 #endif 2078 default: 2079 printf("ahc_intr: seqint, " 2080 "intstat == 0x%x, scsisigi = 0x%x\n", 2081 intstat, ahc_inb(ahc, SCSISIGI)); 2082 break; 2083 } 2084 2085 unpause: 2086 /* 2087 * The sequencer is paused immediately on 2088 * a SEQINT, so we should restart it when 2089 * we're done. 2090 */ 2091 unpause_sequencer(ahc); 2092 } 2093 2094 static void 2095 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2096 { 2097 u_int scb_index; 2098 u_int status; 2099 struct scb *scb; 2100 char cur_channel; 2101 char intr_channel; 2102 2103 if ((ahc->features & AHC_TWIN) != 0 2104 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2105 cur_channel = 'B'; 2106 else 2107 cur_channel = 'A'; 2108 intr_channel = cur_channel; 2109 2110 status = ahc_inb(ahc, SSTAT1); 2111 if (status == 0) { 2112 if ((ahc->features & AHC_TWIN) != 0) { 2113 /* Try the other channel */ 2114 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2115 status = ahc_inb(ahc, SSTAT1); 2116 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2117 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2118 } 2119 if (status == 0) { 2120 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2121 return; 2122 } 2123 } 2124 2125 scb_index = ahc_inb(ahc, SCB_TAG); 2126 if (scb_index < ahc->scb_data->numscbs) { 2127 scb = &ahc->scb_data->scbarray[scb_index]; 2128 if ((scb->flags & SCB_ACTIVE) == 0 2129 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2130 scb = NULL; 2131 } else 2132 scb = NULL; 2133 2134 if ((status & SCSIRSTI) != 0) { 2135 printf("%s: Someone reset channel %c\n", 2136 ahc_name(ahc), intr_channel); 2137 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2138 } else if ((status & SCSIPERR) != 0) { 2139 /* 2140 * Determine the bus phase and queue an appropriate message. 2141 * SCSIPERR is latched true as soon as a parity error 2142 * occurs. If the sequencer acked the transfer that 2143 * caused the parity error and the currently presented 2144 * transfer on the bus has correct parity, SCSIPERR will 2145 * be cleared by CLRSCSIPERR. Use this to determine if 2146 * we should look at the last phase the sequencer recorded, 2147 * or the current phase presented on the bus. 2148 */ 2149 u_int mesg_out; 2150 u_int curphase; 2151 u_int errorphase; 2152 u_int lastphase; 2153 int i; 2154 2155 lastphase = ahc_inb(ahc, LASTPHASE); 2156 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2157 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2158 /* 2159 * For all phases save DATA, the sequencer won't 2160 * automatically ack a byte that has a parity error 2161 * in it. So the only way that the current phase 2162 * could be 'data-in' is if the parity error is for 2163 * an already acked byte in the data phase. During 2164 * synchronous data-in transfers, we may actually 2165 * ack bytes before latching the current phase in 2166 * LASTPHASE, leading to the discrepancy between 2167 * curphase and lastphase. 2168 */ 2169 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2170 || curphase == P_DATAIN) 2171 errorphase = curphase; 2172 else 2173 errorphase = lastphase; 2174 2175 for (i = 0; i < num_phases; i++) { 2176 if (errorphase == phase_table[i].phase) 2177 break; 2178 } 2179 mesg_out = phase_table[i].mesg_out; 2180 if (scb != NULL) 2181 scsi_print_addr(scb->xs->sc_link); 2182 else 2183 printf("%s:%c:%d: ", ahc_name(ahc), 2184 intr_channel, 2185 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2186 2187 printf("parity error detected %s. " 2188 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2189 phase_table[i].phasemsg, 2190 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2191 ahc_inb(ahc, SCSIRATE)); 2192 2193 /* 2194 * We've set the hardware to assert ATN if we 2195 * get a parity error on "in" phases, so all we 2196 * need to do is stuff the message buffer with 2197 * the appropriate message. "In" phases have set 2198 * mesg_out to something other than MSG_NOP. 2199 */ 2200 if (mesg_out != MSG_NOOP) { 2201 if (ahc->msg_type != MSG_TYPE_NONE) 2202 ahc->send_msg_perror = TRUE; 2203 else 2204 ahc_outb(ahc, MSG_OUT, mesg_out); 2205 } 2206 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2207 unpause_sequencer(ahc); 2208 } else if ((status & BUSFREE) != 0 2209 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2210 /* 2211 * First look at what phase we were last in. 2212 * If its message out, chances are pretty good 2213 * that the busfree was in response to one of 2214 * our abort requests. 2215 */ 2216 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2217 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2218 u_int target = TCL_TARGET(saved_tcl); 2219 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2220 char channel = TCL_CHANNEL(ahc, saved_tcl); 2221 int printerror = 1; 2222 2223 ahc_outb(ahc, SCSISEQ, 2224 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2225 if (lastphase == P_MESGOUT) { 2226 u_int message; 2227 u_int tag; 2228 2229 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2230 tag = SCB_LIST_NULL; 2231 switch (message) { 2232 case MSG_ABORT_TAG: 2233 tag = scb->hscb->tag; 2234 /* FALLTRHOUGH */ 2235 case MSG_ABORT: 2236 scsi_print_addr(scb->xs->sc_link); 2237 printf("SCB %x - Abort %s Completed.\n", 2238 scb->hscb->tag, tag == SCB_LIST_NULL ? 2239 "" : "Tag"); 2240 ahc_abort_scbs(ahc, target, channel, 2241 TCL_LUN(saved_tcl), tag, 2242 ROLE_INITIATOR, 2243 XS_DRIVER_STUFFUP); 2244 printerror = 0; 2245 break; 2246 case MSG_BUS_DEV_RESET: 2247 { 2248 struct ahc_devinfo devinfo; 2249 2250 if (scb != NULL && 2251 (scb->xs->xs_control & XS_CTL_RESET) 2252 && ahc_match_scb(scb, target, channel, 2253 TCL_LUN(saved_tcl), 2254 SCB_LIST_NULL, 2255 ROLE_INITIATOR)) { 2256 ahcsetccbstatus(scb->xs, XS_NOERROR); 2257 } 2258 ahc_compile_devinfo(&devinfo, 2259 initiator_role_id, 2260 target, 2261 TCL_LUN(saved_tcl), 2262 channel, 2263 ROLE_INITIATOR); 2264 ahc_handle_devreset(ahc, &devinfo, 2265 XS_RESET, 2266 "Bus Device Reset", 2267 /*verbose_level*/0); 2268 printerror = 0; 2269 break; 2270 } 2271 default: 2272 break; 2273 } 2274 } 2275 if (printerror != 0) { 2276 int i; 2277 2278 if (scb != NULL) { 2279 u_int tag; 2280 2281 if ((scb->hscb->control & TAG_ENB) != 0) 2282 tag = scb->hscb->tag; 2283 else 2284 tag = SCB_LIST_NULL; 2285 ahc_abort_scbs(ahc, target, channel, 2286 SCB_LUN(scb), tag, 2287 ROLE_INITIATOR, 2288 XS_DRIVER_STUFFUP); 2289 scsi_print_addr(scb->xs->sc_link); 2290 } else { 2291 /* 2292 * We had not fully identified this connection, 2293 * so we cannot abort anything. 2294 */ 2295 printf("%s: ", ahc_name(ahc)); 2296 } 2297 for (i = 0; i < num_phases; i++) { 2298 if (lastphase == phase_table[i].phase) 2299 break; 2300 } 2301 printf("Unexpected busfree %s\n" 2302 "SEQADDR == 0x%x\n", 2303 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2304 | (ahc_inb(ahc, SEQADDR1) << 8)); 2305 } 2306 ahc_clear_msg_state(ahc); 2307 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2308 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2309 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2310 restart_sequencer(ahc); 2311 } else if ((status & SELTO) != 0) { 2312 u_int scbptr; 2313 2314 scbptr = ahc_inb(ahc, WAITING_SCBH); 2315 ahc_outb(ahc, SCBPTR, scbptr); 2316 scb_index = ahc_inb(ahc, SCB_TAG); 2317 2318 if (scb_index < ahc->scb_data->numscbs) { 2319 scb = &ahc->scb_data->scbarray[scb_index]; 2320 if ((scb->flags & SCB_ACTIVE) == 0) 2321 scb = NULL; 2322 } else 2323 scb = NULL; 2324 2325 if (scb == NULL) { 2326 printf("%s: ahc_intr - referenced scb not " 2327 "valid during SELTO scb(%d, %d)\n", 2328 ahc_name(ahc), scbptr, scb_index); 2329 } else { 2330 u_int tag; 2331 2332 tag = SCB_LIST_NULL; 2333 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2334 tag = scb->hscb->tag; 2335 2336 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2337 SCB_LUN(scb), tag, 2338 ROLE_INITIATOR, XS_SELTIMEOUT); 2339 } 2340 /* Stop the selection */ 2341 ahc_outb(ahc, SCSISEQ, 0); 2342 2343 /* No more pending messages */ 2344 ahc_clear_msg_state(ahc); 2345 2346 /* 2347 * Although the driver does not care about the 2348 * 'Selection in Progress' status bit, the busy 2349 * LED does. SELINGO is only cleared by a sucessful 2350 * selection, so we must manually clear it to ensure 2351 * the LED turns off just incase no future successful 2352 * selections occur (e.g. no devices on the bus). 2353 */ 2354 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2355 2356 /* Clear interrupt state */ 2357 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2358 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2359 restart_sequencer(ahc); 2360 } else { 2361 scsi_print_addr(scb->xs->sc_link); 2362 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2363 ahc_outb(ahc, CLRSINT1, status); 2364 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2365 unpause_sequencer(ahc); 2366 } 2367 } 2368 2369 static void 2370 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2371 { 2372 /* 2373 * We need to initiate transfer negotiations. 2374 * If our current and goal settings are identical, 2375 * we want to renegotiate due to a check condition. 2376 */ 2377 struct ahc_initiator_tinfo *tinfo; 2378 struct tmode_tstate *tstate; 2379 int dowide; 2380 int dosync; 2381 2382 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2383 devinfo->target, &tstate); 2384 dowide = tinfo->current.width != tinfo->goal.width; 2385 dosync = tinfo->current.period != tinfo->goal.period; 2386 2387 if (!dowide && !dosync) { 2388 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2389 dosync = tinfo->goal.period != 0; 2390 } 2391 2392 if (dowide) { 2393 ahc_construct_wdtr(ahc, tinfo->goal.width); 2394 } else if (dosync) { 2395 struct ahc_syncrate *rate; 2396 u_int period; 2397 u_int offset; 2398 2399 period = tinfo->goal.period; 2400 rate = ahc_devlimited_syncrate(ahc, &period); 2401 offset = tinfo->goal.offset; 2402 ahc_validate_offset(ahc, rate, &offset, 2403 tinfo->current.width); 2404 ahc_construct_sdtr(ahc, period, offset); 2405 } else { 2406 panic("ahc_intr: AWAITING_MSG for negotiation, " 2407 "but no negotiation needed\n"); 2408 } 2409 } 2410 2411 static void 2412 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2413 struct scb *scb) 2414 { 2415 /* 2416 * To facilitate adding multiple messages together, 2417 * each routine should increment the index and len 2418 * variables instead of setting them explicitly. 2419 */ 2420 ahc->msgout_index = 0; 2421 ahc->msgout_len = 0; 2422 2423 if ((scb->flags & SCB_DEVICE_RESET) == 0 2424 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2425 u_int identify_msg; 2426 2427 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2428 if ((scb->hscb->control & DISCENB) != 0) 2429 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2430 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2431 ahc->msgout_len++; 2432 2433 if ((scb->hscb->control & TAG_ENB) != 0) { 2434 /* XXX fvdl FreeBSD has tag action passed down */ 2435 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2436 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2437 ahc->msgout_len += 2; 2438 } 2439 } 2440 2441 if (scb->flags & SCB_DEVICE_RESET) { 2442 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2443 ahc->msgout_len++; 2444 scsi_print_addr(scb->xs->sc_link); 2445 printf("Bus Device Reset Message Sent\n"); 2446 } else if (scb->flags & SCB_ABORT) { 2447 if ((scb->hscb->control & TAG_ENB) != 0) 2448 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2449 else 2450 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2451 ahc->msgout_len++; 2452 scsi_print_addr(scb->xs->sc_link); 2453 printf("Abort Message Sent\n"); 2454 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2455 ahc_build_transfer_msg(ahc, devinfo); 2456 } else { 2457 printf("ahc_intr: AWAITING_MSG for an SCB that " 2458 "does not have a waiting message"); 2459 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2460 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2461 ahc_inb(ahc, MSG_OUT), scb->flags); 2462 } 2463 2464 /* 2465 * Clear the MK_MESSAGE flag from the SCB so we aren't 2466 * asked to send this message again. 2467 */ 2468 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2469 ahc->msgout_index = 0; 2470 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2471 } 2472 2473 static void 2474 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2475 { 2476 /* 2477 * To facilitate adding multiple messages together, 2478 * each routine should increment the index and len 2479 * variables instead of setting them explicitly. 2480 */ 2481 ahc->msgout_index = 0; 2482 ahc->msgout_len = 0; 2483 2484 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2485 ahc_build_transfer_msg(ahc, devinfo); 2486 else 2487 panic("ahc_intr: AWAITING target message with no message"); 2488 2489 ahc->msgout_index = 0; 2490 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2491 } 2492 2493 static int 2494 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2495 { 2496 /* 2497 * What we care about here is if we had an 2498 * outstanding SDTR or WDTR message for this 2499 * target. If we did, this is a signal that 2500 * the target is refusing negotiation. 2501 */ 2502 struct scb *scb; 2503 u_int scb_index; 2504 u_int last_msg; 2505 int response = 0; 2506 2507 scb_index = ahc_inb(ahc, SCB_TAG); 2508 scb = &ahc->scb_data->scbarray[scb_index]; 2509 2510 /* Might be necessary */ 2511 last_msg = ahc_inb(ahc, LAST_MSG); 2512 2513 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2514 struct ahc_initiator_tinfo *tinfo; 2515 struct tmode_tstate *tstate; 2516 2517 #ifdef AHC_DEBUG_NEG 2518 /* note 8bit xfers */ 2519 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2520 "8bit transfers\n", ahc_name(ahc), 2521 devinfo->channel, devinfo->target); 2522 #endif 2523 ahc_set_width(ahc, devinfo, 2524 MSG_EXT_WDTR_BUS_8_BIT, 2525 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2526 /*paused*/TRUE, /*done*/TRUE); 2527 /* 2528 * No need to clear the sync rate. If the target 2529 * did not accept the command, our syncrate is 2530 * unaffected. If the target started the negotiation, 2531 * but rejected our response, we already cleared the 2532 * sync rate before sending our WDTR. 2533 */ 2534 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2535 devinfo->our_scsiid, 2536 devinfo->target, &tstate); 2537 if (tinfo->goal.period) { 2538 u_int period; 2539 2540 /* Start the sync negotiation */ 2541 period = tinfo->goal.period; 2542 ahc_devlimited_syncrate(ahc, &period); 2543 ahc->msgout_index = 0; 2544 ahc->msgout_len = 0; 2545 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2546 ahc->msgout_index = 0; 2547 response = 1; 2548 } 2549 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2550 /* note asynch xfers and clear flag */ 2551 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2552 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2553 /*paused*/TRUE, /*done*/TRUE); 2554 #ifdef AHC_DEBUG_NEG 2555 printf("%s:%c:%d: refuses synchronous negotiation. " 2556 "Using asynchronous transfers\n", 2557 ahc_name(ahc), 2558 devinfo->channel, devinfo->target); 2559 #endif 2560 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2561 printf("%s:%c:%d: refuses tagged commands. Performing " 2562 "non-tagged I/O\n", ahc_name(ahc), 2563 devinfo->channel, devinfo->target); 2564 2565 ahc_set_tags(ahc, devinfo, FALSE); 2566 2567 /* 2568 * Resend the identify for this CCB as the target 2569 * may believe that the selection is invalid otherwise. 2570 */ 2571 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2572 & ~MSG_SIMPLE_Q_TAG); 2573 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2574 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2575 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2576 2577 /* 2578 * Requeue all tagged commands for this target 2579 * currently in our posession so they can be 2580 * converted to untagged commands. 2581 */ 2582 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2583 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2584 ROLE_INITIATOR, SCB_REQUEUE, 2585 SEARCH_COMPLETE); 2586 } else { 2587 /* 2588 * Otherwise, we ignore it. 2589 */ 2590 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2591 ahc_name(ahc), devinfo->channel, devinfo->target, 2592 last_msg); 2593 } 2594 return (response); 2595 } 2596 2597 static void 2598 ahc_clear_msg_state(struct ahc_softc *ahc) 2599 { 2600 ahc->msgout_len = 0; 2601 ahc->msgin_index = 0; 2602 ahc->msg_type = MSG_TYPE_NONE; 2603 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2604 } 2605 2606 static void 2607 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2608 { 2609 struct ahc_devinfo devinfo; 2610 u_int bus_phase; 2611 int end_session; 2612 2613 ahc_fetch_devinfo(ahc, &devinfo); 2614 end_session = FALSE; 2615 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2616 2617 reswitch: 2618 switch (ahc->msg_type) { 2619 case MSG_TYPE_INITIATOR_MSGOUT: 2620 { 2621 int lastbyte; 2622 int phasemis; 2623 int msgdone; 2624 2625 if (ahc->msgout_len == 0) 2626 panic("REQINIT interrupt with no active message"); 2627 2628 phasemis = bus_phase != P_MESGOUT; 2629 if (phasemis) { 2630 if (bus_phase == P_MESGIN) { 2631 /* 2632 * Change gears and see if 2633 * this messages is of interest to 2634 * us or should be passed back to 2635 * the sequencer. 2636 */ 2637 ahc_outb(ahc, CLRSINT1, CLRATNO); 2638 ahc->send_msg_perror = FALSE; 2639 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2640 ahc->msgin_index = 0; 2641 goto reswitch; 2642 } 2643 end_session = TRUE; 2644 break; 2645 } 2646 2647 if (ahc->send_msg_perror) { 2648 ahc_outb(ahc, CLRSINT1, CLRATNO); 2649 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2650 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2651 break; 2652 } 2653 2654 msgdone = ahc->msgout_index == ahc->msgout_len; 2655 if (msgdone) { 2656 /* 2657 * The target has requested a retry. 2658 * Re-assert ATN, reset our message index to 2659 * 0, and try again. 2660 */ 2661 ahc->msgout_index = 0; 2662 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2663 } 2664 2665 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2666 if (lastbyte) { 2667 /* Last byte is signified by dropping ATN */ 2668 ahc_outb(ahc, CLRSINT1, CLRATNO); 2669 } 2670 2671 /* 2672 * Clear our interrupt status and present 2673 * the next byte on the bus. 2674 */ 2675 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2676 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2677 break; 2678 } 2679 case MSG_TYPE_INITIATOR_MSGIN: 2680 { 2681 int phasemis; 2682 int message_done; 2683 2684 phasemis = bus_phase != P_MESGIN; 2685 2686 if (phasemis) { 2687 ahc->msgin_index = 0; 2688 if (bus_phase == P_MESGOUT 2689 && (ahc->send_msg_perror == TRUE 2690 || (ahc->msgout_len != 0 2691 && ahc->msgout_index == 0))) { 2692 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2693 goto reswitch; 2694 } 2695 end_session = TRUE; 2696 break; 2697 } 2698 2699 /* Pull the byte in without acking it */ 2700 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2701 2702 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2703 2704 if (message_done) { 2705 /* 2706 * Clear our incoming message buffer in case there 2707 * is another message following this one. 2708 */ 2709 ahc->msgin_index = 0; 2710 2711 /* 2712 * If this message illicited a response, 2713 * assert ATN so the target takes us to the 2714 * message out phase. 2715 */ 2716 if (ahc->msgout_len != 0) 2717 ahc_outb(ahc, SCSISIGO, 2718 ahc_inb(ahc, SCSISIGO) | ATNO); 2719 } else 2720 ahc->msgin_index++; 2721 2722 /* Ack the byte */ 2723 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2724 ahc_inb(ahc, SCSIDATL); 2725 break; 2726 } 2727 case MSG_TYPE_TARGET_MSGIN: 2728 { 2729 int msgdone; 2730 int msgout_request; 2731 2732 if (ahc->msgout_len == 0) 2733 panic("Target MSGIN with no active message"); 2734 2735 /* 2736 * If we interrupted a mesgout session, the initiator 2737 * will not know this until our first REQ. So, we 2738 * only honor mesgout requests after we've sent our 2739 * first byte. 2740 */ 2741 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2742 && ahc->msgout_index > 0) 2743 msgout_request = TRUE; 2744 else 2745 msgout_request = FALSE; 2746 2747 if (msgout_request) { 2748 2749 /* 2750 * Change gears and see if 2751 * this messages is of interest to 2752 * us or should be passed back to 2753 * the sequencer. 2754 */ 2755 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2756 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2757 ahc->msgin_index = 0; 2758 /* Dummy read to REQ for first byte */ 2759 ahc_inb(ahc, SCSIDATL); 2760 ahc_outb(ahc, SXFRCTL0, 2761 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2762 break; 2763 } 2764 2765 msgdone = ahc->msgout_index == ahc->msgout_len; 2766 if (msgdone) { 2767 ahc_outb(ahc, SXFRCTL0, 2768 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2769 end_session = TRUE; 2770 break; 2771 } 2772 2773 /* 2774 * Present the next byte on the bus. 2775 */ 2776 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2777 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2778 break; 2779 } 2780 case MSG_TYPE_TARGET_MSGOUT: 2781 { 2782 int lastbyte; 2783 int msgdone; 2784 2785 /* 2786 * The initiator signals that this is 2787 * the last byte by dropping ATN. 2788 */ 2789 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2790 2791 /* 2792 * Read the latched byte, but turn off SPIOEN first 2793 * so that we don't inadvertantly cause a REQ for the 2794 * next byte. 2795 */ 2796 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2797 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2798 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2799 if (msgdone == MSGLOOP_TERMINATED) { 2800 /* 2801 * The message is *really* done in that it caused 2802 * us to go to bus free. The sequencer has already 2803 * been reset at this point, so pull the ejection 2804 * handle. 2805 */ 2806 return; 2807 } 2808 2809 ahc->msgin_index++; 2810 2811 /* 2812 * XXX Read spec about initiator dropping ATN too soon 2813 * and use msgdone to detect it. 2814 */ 2815 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2816 ahc->msgin_index = 0; 2817 2818 /* 2819 * If this message illicited a response, transition 2820 * to the Message in phase and send it. 2821 */ 2822 if (ahc->msgout_len != 0) { 2823 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2824 ahc_outb(ahc, SXFRCTL0, 2825 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2826 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2827 ahc->msgin_index = 0; 2828 break; 2829 } 2830 } 2831 2832 if (lastbyte) 2833 end_session = TRUE; 2834 else { 2835 /* Ask for the next byte. */ 2836 ahc_outb(ahc, SXFRCTL0, 2837 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2838 } 2839 2840 break; 2841 } 2842 default: 2843 panic("Unknown REQINIT message type"); 2844 } 2845 2846 if (end_session) { 2847 ahc_clear_msg_state(ahc); 2848 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2849 } else 2850 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2851 } 2852 2853 /* 2854 * See if we sent a particular extended message to the target. 2855 * If "full" is true, the target saw the full message. 2856 * If "full" is false, the target saw at least the first 2857 * byte of the message. 2858 */ 2859 static int 2860 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2861 { 2862 int found; 2863 int index; 2864 2865 found = FALSE; 2866 index = 0; 2867 2868 while (index < ahc->msgout_len) { 2869 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2870 2871 /* Found a candidate */ 2872 if (ahc->msgout_buf[index+2] == msgtype) { 2873 u_int end_index; 2874 2875 end_index = index + 1 2876 + ahc->msgout_buf[index + 1]; 2877 if (full) { 2878 if (ahc->msgout_index > end_index) 2879 found = TRUE; 2880 } else if (ahc->msgout_index > index) 2881 found = TRUE; 2882 } 2883 break; 2884 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2885 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2886 2887 /* Skip tag type and tag id or residue param*/ 2888 index += 2; 2889 } else { 2890 /* Single byte message */ 2891 index++; 2892 } 2893 } 2894 return (found); 2895 } 2896 2897 static int 2898 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2899 struct ahc_devinfo *devinfo) 2900 { 2901 struct ahc_initiator_tinfo *tinfo; 2902 struct tmode_tstate *tstate; 2903 int reject; 2904 int done; 2905 int response; 2906 u_int targ_scsirate; 2907 2908 done = MSGLOOP_IN_PROG; 2909 response = FALSE; 2910 reject = FALSE; 2911 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2912 devinfo->target, &tstate); 2913 targ_scsirate = tinfo->scsirate; 2914 2915 /* 2916 * Parse as much of the message as is availible, 2917 * rejecting it if we don't support it. When 2918 * the entire message is availible and has been 2919 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2920 * that we have parsed an entire message. 2921 * 2922 * In the case of extended messages, we accept the length 2923 * byte outright and perform more checking once we know the 2924 * extended message type. 2925 */ 2926 switch (ahc->msgin_buf[0]) { 2927 case MSG_MESSAGE_REJECT: 2928 response = ahc_handle_msg_reject(ahc, devinfo); 2929 /* FALLTHROUGH */ 2930 case MSG_NOOP: 2931 done = MSGLOOP_MSGCOMPLETE; 2932 break; 2933 case MSG_IGN_WIDE_RESIDUE: 2934 { 2935 /* Wait for the whole message */ 2936 if (ahc->msgin_index >= 1) { 2937 if (ahc->msgin_buf[1] != 1 2938 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2939 reject = TRUE; 2940 done = MSGLOOP_MSGCOMPLETE; 2941 } else 2942 ahc_handle_ign_wide_residue(ahc, devinfo); 2943 } 2944 break; 2945 } 2946 case MSG_EXTENDED: 2947 { 2948 /* Wait for enough of the message to begin validation */ 2949 if (ahc->msgin_index < 2) 2950 break; 2951 switch (ahc->msgin_buf[2]) { 2952 case MSG_EXT_SDTR: 2953 { 2954 struct ahc_syncrate *syncrate; 2955 u_int period; 2956 u_int offset; 2957 u_int saved_offset; 2958 2959 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2960 reject = TRUE; 2961 break; 2962 } 2963 2964 /* 2965 * Wait until we have both args before validating 2966 * and acting on this message. 2967 * 2968 * Add one to MSG_EXT_SDTR_LEN to account for 2969 * the extended message preamble. 2970 */ 2971 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2972 break; 2973 2974 period = ahc->msgin_buf[3]; 2975 saved_offset = offset = ahc->msgin_buf[4]; 2976 syncrate = ahc_devlimited_syncrate(ahc, &period); 2977 ahc_validate_offset(ahc, syncrate, &offset, 2978 targ_scsirate & WIDEXFER); 2979 ahc_set_syncrate(ahc, devinfo, 2980 syncrate, period, offset, 2981 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2982 /*paused*/TRUE, /*done*/TRUE); 2983 2984 /* 2985 * See if we initiated Sync Negotiation 2986 * and didn't have to fall down to async 2987 * transfers. 2988 */ 2989 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2990 /* We started it */ 2991 if (saved_offset != offset) { 2992 /* Went too low - force async */ 2993 reject = TRUE; 2994 } 2995 } else { 2996 /* 2997 * Send our own SDTR in reply 2998 */ 2999 ahc->msgout_index = 0; 3000 ahc->msgout_len = 0; 3001 ahc_construct_sdtr(ahc, period, offset); 3002 ahc->msgout_index = 0; 3003 response = TRUE; 3004 } 3005 done = MSGLOOP_MSGCOMPLETE; 3006 break; 3007 } 3008 case MSG_EXT_WDTR: 3009 { 3010 u_int bus_width; 3011 u_int sending_reply; 3012 3013 sending_reply = FALSE; 3014 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3015 reject = TRUE; 3016 break; 3017 } 3018 3019 /* 3020 * Wait until we have our arg before validating 3021 * and acting on this message. 3022 * 3023 * Add one to MSG_EXT_WDTR_LEN to account for 3024 * the extended message preamble. 3025 */ 3026 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3027 break; 3028 3029 bus_width = ahc->msgin_buf[3]; 3030 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3031 /* 3032 * Don't send a WDTR back to the 3033 * target, since we asked first. 3034 */ 3035 switch (bus_width){ 3036 default: 3037 /* 3038 * How can we do anything greater 3039 * than 16bit transfers on a 16bit 3040 * bus? 3041 */ 3042 reject = TRUE; 3043 printf("%s: target %d requested %dBit " 3044 "transfers. Rejecting...\n", 3045 ahc_name(ahc), devinfo->target, 3046 8 * (0x01 << bus_width)); 3047 /* FALLTHROUGH */ 3048 case MSG_EXT_WDTR_BUS_8_BIT: 3049 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3050 break; 3051 case MSG_EXT_WDTR_BUS_16_BIT: 3052 break; 3053 } 3054 } else { 3055 /* 3056 * Send our own WDTR in reply 3057 */ 3058 switch (bus_width) { 3059 default: 3060 if (ahc->features & AHC_WIDE) { 3061 /* Respond Wide */ 3062 bus_width = 3063 MSG_EXT_WDTR_BUS_16_BIT; 3064 break; 3065 } 3066 /* FALLTHROUGH */ 3067 case MSG_EXT_WDTR_BUS_8_BIT: 3068 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3069 break; 3070 } 3071 ahc->msgout_index = 0; 3072 ahc->msgout_len = 0; 3073 ahc_construct_wdtr(ahc, bus_width); 3074 ahc->msgout_index = 0; 3075 response = TRUE; 3076 sending_reply = TRUE; 3077 } 3078 ahc_set_width(ahc, devinfo, bus_width, 3079 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3080 /*paused*/TRUE, /*done*/TRUE); 3081 3082 /* After a wide message, we are async */ 3083 ahc_set_syncrate(ahc, devinfo, 3084 /*syncrate*/NULL, /*period*/0, 3085 /*offset*/0, AHC_TRANS_ACTIVE, 3086 /*paused*/TRUE, /*done*/FALSE); 3087 if (sending_reply == FALSE && reject == FALSE) { 3088 3089 if (tinfo->goal.period) { 3090 struct ahc_syncrate *rate; 3091 u_int period; 3092 u_int offset; 3093 3094 /* Start the sync negotiation */ 3095 period = tinfo->goal.period; 3096 rate = ahc_devlimited_syncrate(ahc, 3097 &period); 3098 offset = tinfo->goal.offset; 3099 ahc_validate_offset(ahc, rate, &offset, 3100 tinfo->current.width); 3101 ahc->msgout_index = 0; 3102 ahc->msgout_len = 0; 3103 ahc_construct_sdtr(ahc, period, offset); 3104 ahc->msgout_index = 0; 3105 response = TRUE; 3106 } 3107 } 3108 done = MSGLOOP_MSGCOMPLETE; 3109 break; 3110 } 3111 default: 3112 /* Unknown extended message. Reject it. */ 3113 reject = TRUE; 3114 break; 3115 } 3116 break; 3117 } 3118 case MSG_BUS_DEV_RESET: 3119 ahc_handle_devreset(ahc, devinfo, 3120 XS_RESET, "Bus Device Reset Received", 3121 /*verbose_level*/0); 3122 restart_sequencer(ahc); 3123 done = MSGLOOP_TERMINATED; 3124 break; 3125 case MSG_ABORT_TAG: 3126 case MSG_ABORT: 3127 case MSG_CLEAR_QUEUE: 3128 /* Target mode messages */ 3129 if (devinfo->role != ROLE_TARGET) { 3130 reject = TRUE; 3131 break; 3132 } 3133 #if AHC_TARGET_MODE 3134 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3135 devinfo->lun, 3136 ahc->msgin_buf[0] == MSG_ABORT_TAG 3137 ? SCB_LIST_NULL 3138 : ahc_inb(ahc, INITIATOR_TAG), 3139 ROLE_TARGET, XS_DRIVER_STUFFUP); 3140 3141 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3142 if (tstate != NULL) { 3143 struct tmode_lstate* lstate; 3144 3145 lstate = tstate->enabled_luns[devinfo->lun]; 3146 if (lstate != NULL) { 3147 ahc_queue_lstate_event(ahc, lstate, 3148 devinfo->our_scsiid, 3149 ahc->msgin_buf[0], 3150 /*arg*/0); 3151 ahc_send_lstate_events(ahc, lstate); 3152 } 3153 } 3154 done = MSGLOOP_MSGCOMPLETE; 3155 #else 3156 panic("ahc: got target mode message"); 3157 #endif 3158 break; 3159 case MSG_TERM_IO_PROC: 3160 default: 3161 reject = TRUE; 3162 break; 3163 } 3164 3165 if (reject) { 3166 /* 3167 * Setup to reject the message. 3168 */ 3169 ahc->msgout_index = 0; 3170 ahc->msgout_len = 1; 3171 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3172 done = MSGLOOP_MSGCOMPLETE; 3173 response = TRUE; 3174 } 3175 3176 if (done != MSGLOOP_IN_PROG && !response) 3177 /* Clear the outgoing message buffer */ 3178 ahc->msgout_len = 0; 3179 3180 return (done); 3181 } 3182 3183 static void 3184 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3185 { 3186 u_int scb_index; 3187 struct scb *scb; 3188 3189 scb_index = ahc_inb(ahc, SCB_TAG); 3190 scb = &ahc->scb_data->scbarray[scb_index]; 3191 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3192 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3193 /* 3194 * Ignore the message if we haven't 3195 * seen an appropriate data phase yet. 3196 */ 3197 } else { 3198 /* 3199 * If the residual occurred on the last 3200 * transfer and the transfer request was 3201 * expected to end on an odd count, do 3202 * nothing. Otherwise, subtract a byte 3203 * and update the residual count accordingly. 3204 */ 3205 u_int resid_sgcnt; 3206 3207 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3208 if (resid_sgcnt == 0 3209 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3210 /* 3211 * If the residual occurred on the last 3212 * transfer and the transfer request was 3213 * expected to end on an odd count, do 3214 * nothing. 3215 */ 3216 } else { 3217 u_int data_cnt; 3218 u_int32_t data_addr; 3219 u_int sg_index; 3220 3221 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3222 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3223 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3224 3225 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3226 | (ahc_inb(ahc, SHADDR + 2) << 16) 3227 | (ahc_inb(ahc, SHADDR + 1) << 8) 3228 | (ahc_inb(ahc, SHADDR)); 3229 3230 data_cnt += 1; 3231 data_addr -= 1; 3232 3233 sg_index = scb->sg_count - resid_sgcnt; 3234 3235 if (sg_index != 0 3236 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3237 u_int32_t sg_addr; 3238 3239 sg_index--; 3240 data_cnt = 1; 3241 data_addr = le32toh(scb->sg_list[sg_index].addr) 3242 + le32toh(scb->sg_list[sg_index].len) 3243 - 1; 3244 3245 /* 3246 * The physical address base points to the 3247 * second entry as it is always used for 3248 * calculating the "next S/G pointer". 3249 */ 3250 sg_addr = scb->sg_list_phys 3251 + (sg_index* sizeof(*scb->sg_list)); 3252 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3253 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3254 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3255 ahc_outb(ahc, SG_NEXT, sg_addr); 3256 } 3257 3258 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3259 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3260 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3261 3262 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3263 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3264 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3265 ahc_outb(ahc, SHADDR, data_addr); 3266 } 3267 } 3268 } 3269 3270 static void 3271 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3272 int status, char *message, 3273 int verbose_level) 3274 { 3275 int found; 3276 3277 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3278 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3279 status); 3280 3281 /* 3282 * Go back to async/narrow transfers and renegotiate. 3283 * ahc_set_width and ahc_set_syncrate can cope with NULL 3284 * paths. 3285 */ 3286 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3287 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3288 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3289 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3290 /*paused*/TRUE, /*done*/FALSE); 3291 3292 if (message != NULL && (verbose_level <= 0)) 3293 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3294 message, devinfo->channel, devinfo->target, found); 3295 } 3296 3297 /* 3298 * We have an scb which has been processed by the 3299 * adaptor, now we look to see how the operation 3300 * went. 3301 */ 3302 static void 3303 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3304 { 3305 struct scsipi_xfer *xs; 3306 struct scsipi_link *sc_link; 3307 int requeue = 0; 3308 int target; 3309 3310 3311 xs = scb->xs; 3312 sc_link = xs->sc_link; 3313 LIST_REMOVE(scb, plinks); 3314 3315 untimeout(ahc_timeout, (caddr_t)scb); 3316 3317 #ifdef AHC_DEBUG 3318 if (ahc_debug & AHC_SHOWCMDS) { 3319 scsi_print_addr(sc_link); 3320 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3321 scb->hscb->tag); 3322 } 3323 #endif 3324 3325 target = sc_link->scsipi_scsi.target; 3326 3327 if (xs->datalen) { 3328 int op; 3329 3330 if (xs->xs_control & XS_CTL_DATA_IN) 3331 op = BUS_DMASYNC_POSTREAD; 3332 else 3333 op = BUS_DMASYNC_POSTWRITE; 3334 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3335 scb->dmamap->dm_mapsize, op); 3336 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3337 } 3338 3339 /* 3340 * Unbusy this target/channel/lun. 3341 * XXX if we are holding two commands per lun, 3342 * send the next command. 3343 */ 3344 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3345 3346 /* 3347 * If the recovery SCB completes, we have to be 3348 * out of our timeout. 3349 */ 3350 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3351 3352 struct scb *scbp; 3353 3354 /* 3355 * We were able to complete the command successfully, 3356 * so reinstate the timeouts for all other pending 3357 * commands. 3358 */ 3359 scbp = ahc->pending_ccbs.lh_first; 3360 while (scbp != NULL) { 3361 struct scsipi_xfer *txs = scbp->xs; 3362 3363 if (!(txs->xs_control & XS_CTL_POLL)) { 3364 timeout(ahc_timeout, scbp, 3365 (scbp->xs->timeout * hz)/1000); 3366 } 3367 scbp = LIST_NEXT(scbp, plinks); 3368 } 3369 3370 /* 3371 * Ensure that we didn't put a second instance of this 3372 * SCB into the QINFIFO. 3373 */ 3374 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3375 SCB_LUN(scb), scb->hscb->tag, 3376 ROLE_INITIATOR, /*status*/0, 3377 SEARCH_REMOVE); 3378 if (xs->error != XS_NOERROR) 3379 ahcsetccbstatus(xs, XS_TIMEOUT); 3380 scsi_print_addr(xs->sc_link); 3381 printf("no longer in timeout, status = %x\n", xs->status); 3382 } 3383 3384 if (xs->error != XS_NOERROR) { 3385 /* Don't clobber any existing error state */ 3386 } else if ((scb->flags & SCB_SENSE) != 0) { 3387 /* 3388 * We performed autosense retrieval. 3389 * 3390 * bzero the sense data before having 3391 * the drive fill it. The SCSI spec mandates 3392 * that any untransfered data should be 3393 * assumed to be zero. Complete the 'bounce' 3394 * of sense information through buffers accessible 3395 * via bus-space by copying it into the clients 3396 * csio. 3397 */ 3398 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3399 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3400 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3401 xs->error = XS_SENSE; 3402 } 3403 if (scb->flags & SCB_FREEZE_QUEUE) { 3404 ahc->devqueue_blocked[target]--; 3405 scb->flags &= ~SCB_FREEZE_QUEUE; 3406 } 3407 3408 requeue = scb->flags & SCB_REQUEUE; 3409 ahcfreescb(ahc, scb); 3410 3411 if (requeue) { 3412 /* 3413 * Re-insert at the front of the private queue to 3414 * preserve order. 3415 */ 3416 int s; 3417 3418 s = splbio(); 3419 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3420 splx(s); 3421 } else { 3422 xs->xs_status |= XS_STS_DONE; 3423 scsipi_done(xs); 3424 } 3425 3426 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3427 ahc_action(xs); 3428 } 3429 3430 /* 3431 * Determine the number of SCBs available on the controller 3432 */ 3433 int 3434 ahc_probe_scbs(struct ahc_softc *ahc) { 3435 int i; 3436 3437 for (i = 0; i < AHC_SCB_MAX; i++) { 3438 ahc_outb(ahc, SCBPTR, i); 3439 ahc_outb(ahc, SCB_CONTROL, i); 3440 if (ahc_inb(ahc, SCB_CONTROL) != i) 3441 break; 3442 ahc_outb(ahc, SCBPTR, 0); 3443 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3444 break; 3445 } 3446 return (i); 3447 } 3448 3449 /* 3450 * Start the board, ready for normal operation 3451 */ 3452 int 3453 ahc_init(struct ahc_softc *ahc) 3454 { 3455 int max_targ = 15; 3456 int i; 3457 int term; 3458 u_int scsi_conf; 3459 u_int scsiseq_template; 3460 u_int ultraenb; 3461 u_int discenable; 3462 u_int tagenable; 3463 size_t driver_data_size; 3464 u_int32_t physaddr; 3465 3466 #ifdef AHC_PRINT_SRAM 3467 printf("Scratch Ram:"); 3468 for (i = 0x20; i < 0x5f; i++) { 3469 if (((i % 8) == 0) && (i != 0)) { 3470 printf ("\n "); 3471 } 3472 printf (" 0x%x", ahc_inb(ahc, i)); 3473 } 3474 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3475 for (i = 0x70; i < 0x7f; i++) { 3476 if (((i % 8) == 0) && (i != 0)) { 3477 printf ("\n "); 3478 } 3479 printf (" 0x%x", ahc_inb(ahc, i)); 3480 } 3481 } 3482 printf ("\n"); 3483 #endif 3484 3485 /* 3486 * Assume we have a board at this stage and it has been reset. 3487 */ 3488 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3489 ahc->our_id = ahc->our_id_b = 7; 3490 3491 /* 3492 * Default to allowing initiator operations. 3493 */ 3494 ahc->flags |= AHC_INITIATORMODE; 3495 3496 /* 3497 * DMA tag for our command fifos and other data in system memory 3498 * the card's sequencer must be able to access. For initiator 3499 * roles, we need to allocate space for the qinfifo, qoutfifo, 3500 * and untagged_scb arrays each of which are composed of 256 3501 * 1 byte elements. When providing for the target mode role, 3502 * we additionally must provide space for the incoming target 3503 * command fifo. 3504 */ 3505 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3506 3507 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3508 ahc->sc_dmaflags, 3509 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3510 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3511 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3512 return (ENOMEM); 3513 3514 ahc->init_level++; 3515 3516 /* Allocate SCB data now that parent_dmat is initialized */ 3517 if (ahc->scb_data->maxhscbs == 0) 3518 if (ahcinitscbdata(ahc) != 0) 3519 return (ENOMEM); 3520 3521 ahc->qinfifo = &ahc->qoutfifo[256]; 3522 ahc->untagged_scbs = &ahc->qinfifo[256]; 3523 /* There are no untagged SCBs active yet. */ 3524 for (i = 0; i < 256; i++) 3525 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3526 3527 /* All of our queues are empty */ 3528 for (i = 0; i < 256; i++) 3529 ahc->qoutfifo[i] = SCB_LIST_NULL; 3530 3531 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3532 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3533 3534 /* 3535 * Allocate a tstate to house information for our 3536 * initiator presence on the bus as well as the user 3537 * data for any target mode initiator. 3538 */ 3539 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3540 printf("%s: unable to allocate tmode_tstate. " 3541 "Failing attach\n", ahc_name(ahc)); 3542 return (-1); 3543 } 3544 3545 if ((ahc->features & AHC_TWIN) != 0) { 3546 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3547 printf("%s: unable to allocate tmode_tstate. " 3548 "Failing attach\n", ahc_name(ahc)); 3549 return (-1); 3550 } 3551 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3552 ahc->our_id, ahc->our_id_b, 3553 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3554 } else { 3555 if ((ahc->features & AHC_WIDE) != 0) { 3556 printf("Wide "); 3557 } else { 3558 printf("Single "); 3559 } 3560 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3561 } 3562 3563 ahc_outb(ahc, SEQ_FLAGS, 0); 3564 3565 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3566 ahc->flags |= AHC_PAGESCBS; 3567 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3568 } else { 3569 ahc->flags &= ~AHC_PAGESCBS; 3570 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3571 } 3572 3573 #ifdef AHC_DEBUG 3574 if (ahc_debug & AHC_SHOWMISC) { 3575 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3576 "ahc_dma %d bytes\n", 3577 ahc_name(ahc), 3578 sizeof(struct hardware_scb), 3579 sizeof(struct scb), 3580 sizeof(struct ahc_dma_seg)); 3581 } 3582 #endif /* AHC_DEBUG */ 3583 3584 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3585 if (ahc->features & AHC_TWIN) { 3586 3587 /* 3588 * The device is gated to channel B after a chip reset, 3589 * so set those values first 3590 */ 3591 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3592 if ((ahc->features & AHC_ULTRA2) != 0) 3593 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3594 else 3595 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3596 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3597 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3598 |term|ENSTIMER|ACTNEGEN); 3599 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3600 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3601 3602 if ((scsi_conf & RESET_SCSI) != 0 3603 && (ahc->flags & AHC_INITIATORMODE) != 0) 3604 ahc->flags |= AHC_RESET_BUS_B; 3605 3606 /* Select Channel A */ 3607 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3608 } 3609 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3610 if ((ahc->features & AHC_ULTRA2) != 0) 3611 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3612 else 3613 ahc_outb(ahc, SCSIID, ahc->our_id); 3614 scsi_conf = ahc_inb(ahc, SCSICONF); 3615 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3616 |term 3617 |ENSTIMER|ACTNEGEN); 3618 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3619 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3620 3621 if ((scsi_conf & RESET_SCSI) != 0 3622 && (ahc->flags & AHC_INITIATORMODE) != 0) 3623 ahc->flags |= AHC_RESET_BUS_A; 3624 3625 /* 3626 * Look at the information that board initialization or 3627 * the board bios has left us. 3628 */ 3629 ultraenb = 0; 3630 tagenable = ALL_TARGETS_MASK; 3631 3632 /* Grab the disconnection disable table and invert it for our needs */ 3633 if (ahc->flags & AHC_USEDEFAULTS) { 3634 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3635 "device parameters\n", ahc_name(ahc)); 3636 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3637 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3638 discenable = ALL_TARGETS_MASK; 3639 if ((ahc->features & AHC_ULTRA) != 0) 3640 ultraenb = ALL_TARGETS_MASK; 3641 } else { 3642 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3643 | ahc_inb(ahc, DISC_DSB)); 3644 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3645 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3646 | ahc_inb(ahc, ULTRA_ENB); 3647 } 3648 3649 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3650 max_targ = 7; 3651 3652 for (i = 0; i <= max_targ; i++) { 3653 struct ahc_initiator_tinfo *tinfo; 3654 struct tmode_tstate *tstate; 3655 u_int our_id; 3656 u_int target_id; 3657 char channel; 3658 3659 channel = 'A'; 3660 our_id = ahc->our_id; 3661 target_id = i; 3662 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3663 channel = 'B'; 3664 our_id = ahc->our_id_b; 3665 target_id = i % 8; 3666 } 3667 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3668 target_id, &tstate); 3669 /* Default to async narrow across the board */ 3670 bzero(tinfo, sizeof(*tinfo)); 3671 if (ahc->flags & AHC_USEDEFAULTS) { 3672 if ((ahc->features & AHC_WIDE) != 0) 3673 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3674 3675 /* 3676 * These will be truncated when we determine the 3677 * connection type we have with the target. 3678 */ 3679 tinfo->user.period = ahc_syncrates->period; 3680 tinfo->user.offset = ~0; 3681 } else { 3682 u_int scsirate; 3683 u_int16_t mask; 3684 3685 /* Take the settings leftover in scratch RAM. */ 3686 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3687 mask = (0x01 << i); 3688 if ((ahc->features & AHC_ULTRA2) != 0) { 3689 u_int offset; 3690 u_int maxsync; 3691 3692 if ((scsirate & SOFS) == 0x0F) { 3693 /* 3694 * Haven't negotiated yet, 3695 * so the format is different. 3696 */ 3697 scsirate = (scsirate & SXFR) >> 4 3698 | (ultraenb & mask) 3699 ? 0x08 : 0x0 3700 | (scsirate & WIDEXFER); 3701 offset = MAX_OFFSET_ULTRA2; 3702 } else 3703 offset = ahc_inb(ahc, TARG_OFFSET + i); 3704 maxsync = AHC_SYNCRATE_ULTRA2; 3705 if ((ahc->features & AHC_DT) != 0) 3706 maxsync = AHC_SYNCRATE_DT; 3707 tinfo->user.period = 3708 ahc_find_period(ahc, scsirate, maxsync); 3709 if (offset == 0) 3710 tinfo->user.period = 0; 3711 else 3712 tinfo->user.offset = ~0; 3713 } else if ((scsirate & SOFS) != 0) { 3714 tinfo->user.period = 3715 ahc_find_period(ahc, scsirate, 3716 (ultraenb & mask) 3717 ? AHC_SYNCRATE_ULTRA 3718 : AHC_SYNCRATE_FAST); 3719 if (tinfo->user.period != 0) 3720 tinfo->user.offset = ~0; 3721 } 3722 if ((scsirate & WIDEXFER) != 0 3723 && (ahc->features & AHC_WIDE) != 0) 3724 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3725 } 3726 tinfo->goal = tinfo->user; /* force negotiation */ 3727 tstate->ultraenb = ultraenb; 3728 tstate->discenable = discenable; 3729 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3730 } 3731 ahc->user_discenable = discenable; 3732 ahc->user_tagenable = tagenable; 3733 3734 /* 3735 * Tell the sequencer where it can find our arrays in memory. 3736 */ 3737 physaddr = ahc->scb_data->hscb_busaddr; 3738 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3739 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3740 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3741 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3742 3743 physaddr = ahc->shared_data_busaddr; 3744 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3745 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3746 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3747 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3748 3749 /* Target mode incomding command fifo */ 3750 physaddr += 3 * 256 * sizeof(u_int8_t); 3751 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3752 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3753 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3754 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3755 3756 /* 3757 * Initialize the group code to command length table. 3758 * This overrides the values in TARG_SCSIRATE, so only 3759 * setup the table after we have processed that information. 3760 */ 3761 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3762 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3763 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3764 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3765 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3766 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3767 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3768 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3769 3770 /* Tell the sequencer of our initial queue positions */ 3771 ahc_outb(ahc, KERNEL_QINPOS, 0); 3772 ahc_outb(ahc, QINPOS, 0); 3773 ahc_outb(ahc, QOUTPOS, 0); 3774 3775 #ifdef AHC_DEBUG 3776 if (ahc_debug & AHC_SHOWMISC) 3777 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3778 discenable, ultraenb); 3779 #endif 3780 3781 /* Don't have any special messages to send to targets */ 3782 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3783 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3784 3785 /* 3786 * Use the built in queue management registers 3787 * if they are available. 3788 */ 3789 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3790 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3791 ahc_outb(ahc, SDSCB_QOFF, 0); 3792 ahc_outb(ahc, SNSCB_QOFF, 0); 3793 ahc_outb(ahc, HNSCB_QOFF, 0); 3794 } 3795 3796 3797 /* We don't have any waiting selections */ 3798 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3799 3800 /* Our disconnection list is empty too */ 3801 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3802 3803 /* Message out buffer starts empty */ 3804 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3805 3806 /* 3807 * Setup the allowed SCSI Sequences based on operational mode. 3808 * If we are a target, we'll enalbe select in operations once 3809 * we've had a lun enabled. 3810 */ 3811 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3812 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3813 scsiseq_template |= ENRSELI; 3814 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3815 3816 /* 3817 * Load the Sequencer program and Enable the adapter 3818 * in "fast" mode. 3819 */ 3820 #ifdef AHC_DEBUG 3821 printf("%s: Downloading Sequencer Program...", 3822 ahc_name(ahc)); 3823 #endif 3824 3825 ahc_loadseq(ahc); 3826 3827 /* We have to wait until after any system dumps... */ 3828 shutdownhook_establish(ahc_shutdown, ahc); 3829 3830 return (0); 3831 } 3832 3833 /* 3834 * XXX fvdl the busy_tcl checks and settings should only be done 3835 * for the non-tagged queueing case, but we don't do tagged queueing 3836 * yet, so.. 3837 */ 3838 static int32_t 3839 ahc_action(struct scsipi_xfer *xs) 3840 { 3841 struct scsipi_xfer *first_xs, *next_xs = NULL; 3842 struct ahc_softc *ahc; 3843 struct scb *scb; 3844 struct hardware_scb *hscb; 3845 struct ahc_initiator_tinfo *tinfo; 3846 struct tmode_tstate *tstate; 3847 u_int target_id; 3848 u_int our_id; 3849 int s, tcl; 3850 u_int16_t mask; 3851 int dontqueue = 0, fromqueue = 0; 3852 3853 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3854 3855 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3856 3857 /* must protect the queue */ 3858 s = splbio(); 3859 3860 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3861 /* 3862 * Called from ahc_done. Calling with the first entry in 3863 * the queue is really just a way of seeing where we're 3864 * called from. Now, find the first eligible SCB to send, 3865 * e.g. one which will be accepted immediately. 3866 */ 3867 3868 if (ahc->queue_blocked) { 3869 splx(s); 3870 return (TRY_AGAIN_LATER); 3871 } 3872 3873 xs = ahc_first_xs(ahc); 3874 if (xs == NULL) { 3875 splx(s); 3876 return (TRY_AGAIN_LATER); 3877 } 3878 3879 next_xs = TAILQ_NEXT(xs, adapter_q); 3880 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3881 fromqueue = 1; 3882 goto get_scb; 3883 } 3884 3885 /* 3886 * If no new requests are accepted, just insert into the 3887 * private queue to wait for our turn. 3888 */ 3889 tcl = XS_TCL(ahc, xs); 3890 3891 if (ahc->queue_blocked || 3892 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3893 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3894 if (dontqueue) { 3895 splx(s); 3896 xs->error = XS_DRIVER_STUFFUP; 3897 return TRY_AGAIN_LATER; 3898 } 3899 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3900 splx(s); 3901 return SUCCESSFULLY_QUEUED; 3902 } 3903 3904 first_xs = ahc_first_xs(ahc); 3905 3906 /* determine safety of software queueing */ 3907 dontqueue = xs->xs_control & XS_CTL_POLL; 3908 3909 /* 3910 * Handle situations where there's already entries in the 3911 * queue. 3912 */ 3913 if (first_xs != NULL) { 3914 /* 3915 * If we can't queue, we have to abort, since 3916 * we have to preserve order. 3917 */ 3918 if (dontqueue) { 3919 splx(s); 3920 xs->error = XS_DRIVER_STUFFUP; 3921 return (TRY_AGAIN_LATER); 3922 } 3923 3924 /* 3925 * Swap with the first queue entry. 3926 */ 3927 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3928 xs = first_xs; 3929 next_xs = TAILQ_NEXT(xs, adapter_q); 3930 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3931 fromqueue = 1; 3932 3933 } 3934 3935 get_scb: 3936 3937 target_id = xs->sc_link->scsipi_scsi.target; 3938 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3939 3940 /* 3941 * get an scb to use. 3942 */ 3943 if ((scb = ahcgetscb(ahc)) == NULL) { 3944 3945 if (dontqueue) { 3946 splx(s); 3947 xs->error = XS_DRIVER_STUFFUP; 3948 return (TRY_AGAIN_LATER); 3949 } 3950 3951 /* 3952 * If we were pulled off the queue, put ourselves 3953 * back to where we came from, otherwise tack ourselves 3954 * onto the end. 3955 */ 3956 if (fromqueue && next_xs != NULL) 3957 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3958 else 3959 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3960 3961 splx(s); 3962 return (SUCCESSFULLY_QUEUED); 3963 } 3964 3965 tcl = XS_TCL(ahc, xs); 3966 3967 #ifdef DIAGNOSTIC 3968 if (ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3969 panic("ahc: queuing for busy target"); 3970 #endif 3971 3972 scb->xs = xs; 3973 hscb = scb->hscb; 3974 hscb->tcl = tcl; 3975 3976 ahc_busy_tcl(ahc, scb); 3977 3978 splx(s); 3979 3980 /* 3981 * Put all the arguments for the xfer in the scb 3982 */ 3983 3984 mask = SCB_TARGET_MASK(scb); 3985 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 3986 target_id, &tstate); 3987 if (ahc->inited_targets[target_id] == 0) { 3988 struct ahc_devinfo devinfo; 3989 3990 s = splbio(); 3991 ahc_compile_devinfo(&devinfo, our_id, target_id, 3992 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 3993 ROLE_INITIATOR); 3994 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 3995 FALSE); 3996 ahc->inited_targets[target_id] = 1; 3997 splx(s); 3998 } 3999 4000 hscb->scsirate = tinfo->scsirate; 4001 hscb->scsioffset = tinfo->current.offset; 4002 if ((tstate->ultraenb & mask) != 0) 4003 hscb->control |= ULTRAENB; 4004 4005 if ((tstate->discenable & mask) != 0) 4006 hscb->control |= DISCENB; 4007 4008 if (xs->xs_control & XS_CTL_RESET) { 4009 hscb->cmdpointer = NULL; 4010 scb->flags |= SCB_DEVICE_RESET; 4011 hscb->control |= MK_MESSAGE; 4012 return ahc_execute_scb(scb, NULL, 0); 4013 } 4014 4015 return ahc_setup_data(ahc, xs, scb); 4016 } 4017 4018 static int 4019 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4020 { 4021 struct scb *scb; 4022 struct scsipi_xfer *xs; 4023 struct ahc_softc *ahc; 4024 int s; 4025 4026 scb = (struct scb *)arg; 4027 xs = scb->xs; 4028 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4029 4030 4031 if (nsegments != 0) { 4032 struct ahc_dma_seg *sg; 4033 bus_dma_segment_t *end_seg; 4034 int op; 4035 4036 end_seg = dm_segs + nsegments; 4037 4038 /* Copy the first SG into the data pointer area */ 4039 scb->hscb->data = dm_segs->ds_addr; 4040 scb->hscb->datalen = dm_segs->ds_len; 4041 4042 /* Copy the segments into our SG list */ 4043 sg = scb->sg_list; 4044 while (dm_segs < end_seg) { 4045 sg->addr = dm_segs->ds_addr; 4046 sg->len = dm_segs->ds_len; 4047 ahc_swap_sg(sg); 4048 sg++; 4049 dm_segs++; 4050 } 4051 4052 /* Note where to find the SG entries in bus space */ 4053 scb->hscb->SG_pointer = scb->sg_list_phys; 4054 4055 if (xs->xs_control & XS_CTL_DATA_IN) 4056 op = BUS_DMASYNC_PREREAD; 4057 else 4058 op = BUS_DMASYNC_PREWRITE; 4059 4060 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4061 scb->dmamap->dm_mapsize, op); 4062 4063 } else { 4064 scb->hscb->SG_pointer = 0; 4065 scb->hscb->data = 0; 4066 scb->hscb->datalen = 0; 4067 } 4068 4069 scb->sg_count = scb->hscb->SG_count = nsegments; 4070 4071 s = splbio(); 4072 4073 /* 4074 * Last time we need to check if this SCB needs to 4075 * be aborted. 4076 */ 4077 if (xs->xs_status & XS_STS_DONE) { 4078 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4079 if (nsegments != 0) 4080 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4081 ahcfreescb(ahc, scb); 4082 splx(s); 4083 return (COMPLETE); 4084 } 4085 4086 #ifdef DIAGNOSTIC 4087 if (scb->sg_count > 255) 4088 panic("ahc bad sg_count"); 4089 #endif 4090 4091 ahc_swap_hscb(scb->hscb); 4092 4093 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4094 4095 scb->flags |= SCB_ACTIVE; 4096 4097 if (!(xs->xs_control & XS_CTL_POLL)) 4098 timeout(ahc_timeout, (caddr_t)scb, 4099 (xs->timeout * hz) / 1000); 4100 4101 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4102 #if 0 4103 printf("Continueing Immediate Command %d:%d\n", 4104 xs->sc_link->scsipi_scsi.target, 4105 xs->sc_link->scsipi_scsi.lun); 4106 #endif 4107 pause_sequencer(ahc); 4108 if ((ahc->flags & AHC_PAGESCBS) == 0) 4109 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4110 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4111 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4112 unpause_sequencer(ahc); 4113 } else { 4114 4115 #if 0 4116 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4117 scb->hscb->tag, ahc->qinfifonext, 4118 &ahc->qinfifo[ahc->qinfifonext], 4119 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4120 #endif 4121 4122 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4123 4124 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4125 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4126 4127 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4128 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4129 } else { 4130 pause_sequencer(ahc); 4131 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4132 unpause_sequencer(ahc); 4133 } 4134 } 4135 4136 #ifdef AHC_DEBUG 4137 if (ahc_debug & AHC_SHOWCMDS) { 4138 scsi_print_addr(xs->sc_link); 4139 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4140 " rate %x\n", 4141 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4142 scb->flags, scb->hscb->control, ahc->qinfifonext, 4143 scb->hscb->scsirate); 4144 } 4145 #endif 4146 4147 if (!(xs->xs_control & XS_CTL_POLL)) { 4148 splx(s); 4149 return (SUCCESSFULLY_QUEUED); 4150 } 4151 /* 4152 * If we can't use interrupts, poll for completion 4153 */ 4154 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4155 do { 4156 if (ahc_poll(ahc, xs->timeout)) { 4157 if (!(xs->xs_control & XS_CTL_SILENT)) 4158 printf("cmd fail\n"); 4159 ahc_timeout(scb); 4160 break; 4161 } 4162 } while (!(xs->xs_status & XS_STS_DONE)); 4163 splx(s); 4164 return (COMPLETE); 4165 } 4166 4167 static int 4168 ahc_poll(struct ahc_softc *ahc, int wait) 4169 { 4170 while (--wait) { 4171 DELAY(1000); 4172 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4173 break; 4174 } 4175 4176 if (wait == 0) { 4177 printf("%s: board is not responding\n", ahc_name(ahc)); 4178 return (EIO); 4179 } 4180 4181 ahc_intr((void *)ahc); 4182 return (0); 4183 } 4184 4185 static int 4186 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4187 struct scb *scb) 4188 { 4189 struct hardware_scb *hscb; 4190 4191 hscb = scb->hscb; 4192 xs->resid = xs->status = 0; 4193 4194 hscb->cmdlen = xs->cmdlen; 4195 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4196 hscb->cmdpointer = hscb->cmdstore_busaddr; 4197 4198 /* Only use S/G if there is a transfer */ 4199 if (xs->datalen) { 4200 int error; 4201 4202 error = bus_dmamap_load(ahc->parent_dmat, 4203 scb->dmamap, xs->data, 4204 xs->datalen, NULL, 4205 (xs->xs_control & XS_CTL_NOSLEEP) ? 4206 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4207 if (error) { 4208 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4209 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4210 } 4211 error = ahc_execute_scb(scb, 4212 scb->dmamap->dm_segs, 4213 scb->dmamap->dm_nsegs); 4214 return error; 4215 } else { 4216 return ahc_execute_scb(scb, NULL, 0); 4217 } 4218 } 4219 4220 static void 4221 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4222 { 4223 int target; 4224 char channel; 4225 int lun; 4226 4227 target = sc_link->scsipi_scsi.target; 4228 lun = sc_link->scsipi_scsi.lun; 4229 channel = sc_link->scsipi_scsi.channel; 4230 4231 ahc_search_qinfifo(ahc, target, channel, lun, 4232 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4233 SCB_REQUEUE, SEARCH_COMPLETE); 4234 } 4235 4236 static void 4237 ahcallocscbs(struct ahc_softc *ahc) 4238 { 4239 struct scb_data *scb_data; 4240 struct scb *next_scb; 4241 struct sg_map_node *sg_map; 4242 bus_addr_t physaddr; 4243 struct ahc_dma_seg *segs; 4244 int newcount; 4245 int i; 4246 4247 scb_data = ahc->scb_data; 4248 if (scb_data->numscbs >= AHC_SCB_MAX) 4249 /* Can't allocate any more */ 4250 return; 4251 4252 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4253 4254 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4255 4256 if (sg_map == NULL) 4257 return; 4258 4259 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4260 &sg_map->sg_dmamap, 4261 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4262 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4263 "SG space") < 0) { 4264 free(sg_map, M_DEVBUF); 4265 return; 4266 } 4267 4268 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4269 4270 segs = sg_map->sg_vaddr; 4271 physaddr = sg_map->sg_physaddr; 4272 4273 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4274 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4275 int error; 4276 4277 next_scb->sg_list = segs; 4278 /* 4279 * The sequencer always starts with the second entry. 4280 * The first entry is embedded in the scb. 4281 */ 4282 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4283 next_scb->flags = SCB_FREE; 4284 error = bus_dmamap_create(ahc->parent_dmat, 4285 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4286 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4287 &next_scb->dmamap); 4288 if (error != 0) 4289 break; 4290 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4291 next_scb->hscb->tag = ahc->scb_data->numscbs; 4292 next_scb->hscb->cmdstore_busaddr = 4293 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4294 + offsetof(struct hardware_scb, cmdstore); 4295 next_scb->hscb->cmdstore_busaddr = 4296 htole32(next_scb->hscb->cmdstore_busaddr); 4297 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4298 segs += AHC_NSEG; 4299 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4300 next_scb++; 4301 ahc->scb_data->numscbs++; 4302 } 4303 #ifdef AHC_DEBUG 4304 if (ahc_debug & AHC_SHOWSCBALLOC) 4305 printf("%s: allocated %d new SCBs count now %d\n", 4306 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4307 #endif 4308 } 4309 4310 #ifdef AHC_DUMP_SEQ 4311 static void 4312 ahc_dumpseq(struct ahc_softc* ahc) 4313 { 4314 int i; 4315 int max_prog; 4316 4317 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4318 max_prog = 448; 4319 else if ((ahc->features & AHC_ULTRA2) != 0) 4320 max_prog = 768; 4321 else 4322 max_prog = 512; 4323 4324 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4325 ahc_outb(ahc, SEQADDR0, 0); 4326 ahc_outb(ahc, SEQADDR1, 0); 4327 for (i = 0; i < max_prog; i++) { 4328 u_int8_t ins_bytes[4]; 4329 4330 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4331 printf("0x%08x\n", ins_bytes[0] << 24 4332 | ins_bytes[1] << 16 4333 | ins_bytes[2] << 8 4334 | ins_bytes[3]); 4335 } 4336 } 4337 #endif 4338 4339 static void 4340 ahc_loadseq(struct ahc_softc *ahc) 4341 { 4342 struct patch *cur_patch; 4343 int i; 4344 int downloaded; 4345 int skip_addr; 4346 u_int8_t download_consts[4]; 4347 4348 /* Setup downloadable constant table */ 4349 #if 0 4350 /* No downloaded constants are currently defined. */ 4351 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4352 #endif 4353 4354 cur_patch = patches; 4355 downloaded = 0; 4356 skip_addr = 0; 4357 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4358 ahc_outb(ahc, SEQADDR0, 0); 4359 ahc_outb(ahc, SEQADDR1, 0); 4360 4361 for (i = 0; i < sizeof(seqprog)/4; i++) { 4362 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4363 /* 4364 * Don't download this instruction as it 4365 * is in a patch that was removed. 4366 */ 4367 continue; 4368 } 4369 ahc_download_instr(ahc, i, download_consts); 4370 downloaded++; 4371 } 4372 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4373 restart_sequencer(ahc); 4374 4375 #ifdef AHC_DEBUG 4376 printf(" %d instructions downloaded\n", downloaded); 4377 #endif 4378 } 4379 4380 static int 4381 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4382 int start_instr, int *skip_addr) 4383 { 4384 struct patch *cur_patch; 4385 struct patch *last_patch; 4386 int num_patches; 4387 4388 num_patches = sizeof(patches)/sizeof(struct patch); 4389 last_patch = &patches[num_patches]; 4390 cur_patch = *start_patch; 4391 4392 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4393 4394 if (cur_patch->patch_func(ahc) == 0) { 4395 4396 /* Start rejecting code */ 4397 *skip_addr = start_instr + cur_patch->skip_instr; 4398 cur_patch += cur_patch->skip_patch; 4399 } else { 4400 /* Accepted this patch. Advance to the next 4401 * one and wait for our intruction pointer to 4402 * hit this point. 4403 */ 4404 cur_patch++; 4405 } 4406 } 4407 4408 *start_patch = cur_patch; 4409 if (start_instr < *skip_addr) 4410 /* Still skipping */ 4411 return (0); 4412 4413 return (1); 4414 } 4415 4416 static void 4417 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4418 { 4419 union ins_formats instr; 4420 struct ins_format1 *fmt1_ins; 4421 struct ins_format3 *fmt3_ins; 4422 u_int opcode; 4423 4424 /* Structure copy */ 4425 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4426 4427 instr.integer = le32toh(instr.integer); 4428 4429 fmt1_ins = &instr.format1; 4430 fmt3_ins = NULL; 4431 4432 /* Pull the opcode */ 4433 opcode = instr.format1.opcode; 4434 switch (opcode) { 4435 case AIC_OP_JMP: 4436 case AIC_OP_JC: 4437 case AIC_OP_JNC: 4438 case AIC_OP_CALL: 4439 case AIC_OP_JNE: 4440 case AIC_OP_JNZ: 4441 case AIC_OP_JE: 4442 case AIC_OP_JZ: 4443 { 4444 struct patch *cur_patch; 4445 int address_offset; 4446 u_int address; 4447 int skip_addr; 4448 int i; 4449 4450 fmt3_ins = &instr.format3; 4451 address_offset = 0; 4452 address = fmt3_ins->address; 4453 cur_patch = patches; 4454 skip_addr = 0; 4455 4456 for (i = 0; i < address;) { 4457 4458 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4459 4460 if (skip_addr > i) { 4461 int end_addr; 4462 4463 end_addr = MIN(address, skip_addr); 4464 address_offset += end_addr - i; 4465 i = skip_addr; 4466 } else { 4467 i++; 4468 } 4469 } 4470 address -= address_offset; 4471 fmt3_ins->address = address; 4472 /* FALLTHROUGH */ 4473 } 4474 case AIC_OP_OR: 4475 case AIC_OP_AND: 4476 case AIC_OP_XOR: 4477 case AIC_OP_ADD: 4478 case AIC_OP_ADC: 4479 case AIC_OP_BMOV: 4480 if (fmt1_ins->parity != 0) { 4481 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4482 } 4483 fmt1_ins->parity = 0; 4484 /* FALLTHROUGH */ 4485 case AIC_OP_ROL: 4486 if ((ahc->features & AHC_ULTRA2) != 0) { 4487 int i, count; 4488 4489 /* Calculate odd parity for the instruction */ 4490 for (i = 0, count = 0; i < 31; i++) { 4491 u_int32_t mask; 4492 4493 mask = 0x01 << i; 4494 if ((instr.integer & mask) != 0) 4495 count++; 4496 } 4497 if ((count & 0x01) == 0) 4498 instr.format1.parity = 1; 4499 } else { 4500 /* Compress the instruction for older sequencers */ 4501 if (fmt3_ins != NULL) { 4502 instr.integer = 4503 fmt3_ins->immediate 4504 | (fmt3_ins->source << 8) 4505 | (fmt3_ins->address << 16) 4506 | (fmt3_ins->opcode << 25); 4507 } else { 4508 instr.integer = 4509 fmt1_ins->immediate 4510 | (fmt1_ins->source << 8) 4511 | (fmt1_ins->destination << 16) 4512 | (fmt1_ins->ret << 24) 4513 | (fmt1_ins->opcode << 25); 4514 } 4515 } 4516 instr.integer = htole32(instr.integer); 4517 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4518 break; 4519 default: 4520 panic("Unknown opcode encountered in seq program"); 4521 break; 4522 } 4523 } 4524 4525 static void 4526 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4527 { 4528 4529 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4530 struct scb *scbp; 4531 4532 scb->flags |= SCB_RECOVERY_SCB; 4533 4534 /* 4535 * Take all queued, but not sent SCBs out of the equation. 4536 * Also ensure that no new CCBs are queued to us while we 4537 * try to fix this problem. 4538 */ 4539 ahc->queue_blocked = 1; 4540 4541 /* 4542 * Go through all of our pending SCBs and remove 4543 * any scheduled timeouts for them. We will reschedule 4544 * them after we've successfully fixed this problem. 4545 */ 4546 scbp = ahc->pending_ccbs.lh_first; 4547 while (scbp != NULL) { 4548 untimeout(ahc_timeout, scbp); 4549 scbp = scbp->plinks.le_next; 4550 } 4551 } 4552 } 4553 4554 static void 4555 ahc_timeout(void *arg) 4556 { 4557 struct scb *scb; 4558 struct ahc_softc *ahc; 4559 int s, found; 4560 u_int last_phase; 4561 int target; 4562 int lun; 4563 int i; 4564 char channel; 4565 4566 scb = (struct scb *)arg; 4567 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4568 4569 s = splbio(); 4570 4571 /* 4572 * Ensure that the card doesn't do anything 4573 * behind our back. Also make sure that we 4574 * didn't "just" miss an interrupt that would 4575 * affect this timeout. 4576 */ 4577 do { 4578 ahc_intr(ahc); 4579 pause_sequencer(ahc); 4580 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4581 4582 if ((scb->flags & SCB_ACTIVE) == 0) { 4583 /* Previous timeout took care of me already */ 4584 printf("Timedout SCB handled by another timeout\n"); 4585 unpause_sequencer(ahc); 4586 splx(s); 4587 return; 4588 } 4589 4590 target = SCB_TARGET(scb); 4591 channel = SCB_CHANNEL(scb); 4592 lun = SCB_LUN(scb); 4593 4594 scsi_print_addr(scb->xs->sc_link); 4595 printf("SCB %x - timed out ", scb->hscb->tag); 4596 /* 4597 * Take a snapshot of the bus state and print out 4598 * some information so we can track down driver bugs. 4599 */ 4600 last_phase = ahc_inb(ahc, LASTPHASE); 4601 4602 for (i = 0; i < num_phases; i++) { 4603 if (last_phase == phase_table[i].phase) 4604 break; 4605 } 4606 printf("%s", phase_table[i].phasemsg); 4607 4608 printf(", SEQADDR == 0x%x\n", 4609 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4610 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4611 4612 #ifdef AHC_DEBUG 4613 ahc_print_scb(scb); 4614 #endif 4615 4616 #if 0 4617 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4618 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4619 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4620 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4621 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4622 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4623 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4624 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4625 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4626 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4627 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4628 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4629 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4630 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4631 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4632 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4633 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4634 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4635 if (scb->sg_count > 0) { 4636 for (i = 0; i < scb->sg_count; i++) { 4637 printf("sg[%d] - Addr 0x%x : Length %d\n", 4638 i, 4639 le32toh(scb->sg_list[i].addr), 4640 le32toh(scb->sg_list[i].len)); 4641 } 4642 } 4643 #endif 4644 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4645 /* 4646 * Been down this road before. 4647 * Do a full bus reset. 4648 */ 4649 bus_reset: 4650 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4651 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4652 printf("%s: Issued Channel %c Bus Reset. " 4653 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4654 } else { 4655 /* 4656 * If we are a target, transition to bus free and report 4657 * the timeout. 4658 * 4659 * The target/initiator that is holding up the bus may not 4660 * be the same as the one that triggered this timeout 4661 * (different commands have different timeout lengths). 4662 * If the bus is idle and we are actiing as the initiator 4663 * for this request, queue a BDR message to the timed out 4664 * target. Otherwise, if the timed out transaction is 4665 * active: 4666 * Initiator transaction: 4667 * Stuff the message buffer with a BDR message and assert 4668 * ATN in the hopes that the target will let go of the bus 4669 * and go to the mesgout phase. If this fails, we'll 4670 * get another timeout 2 seconds later which will attempt 4671 * a bus reset. 4672 * 4673 * Target transaction: 4674 * Transition to BUS FREE and report the error. 4675 * It's good to be the target! 4676 */ 4677 u_int active_scb_index; 4678 4679 active_scb_index = ahc_inb(ahc, SCB_TAG); 4680 4681 if (last_phase != P_BUSFREE 4682 && (active_scb_index < ahc->scb_data->numscbs)) { 4683 struct scb *active_scb; 4684 4685 /* 4686 * If the active SCB is not from our device, 4687 * assume that another device is hogging the bus 4688 * and wait for it's timeout to expire before 4689 * taking additional action. 4690 */ 4691 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4692 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4693 u_int newtimeout; 4694 4695 scsi_print_addr(scb->xs->sc_link); 4696 printf("Other SCB Timeout%s", 4697 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4698 ? " again\n" : "\n"); 4699 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4700 newtimeout = MAX(active_scb->xs->timeout, 4701 scb->xs->timeout); 4702 timeout(ahc_timeout, scb, 4703 (newtimeout * hz) / 1000); 4704 splx(s); 4705 return; 4706 } 4707 4708 /* It's us */ 4709 if ((scb->hscb->control & TARGET_SCB) != 0) { 4710 4711 /* 4712 * Send back any queued up transactions 4713 * and properly record the error condition. 4714 */ 4715 ahc_freeze_devq(ahc, scb->xs->sc_link); 4716 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4717 ahc_freeze_ccb(scb); 4718 ahc_done(ahc, scb); 4719 4720 /* Will clear us from the bus */ 4721 restart_sequencer(ahc); 4722 return; 4723 } 4724 4725 ahc_set_recoveryscb(ahc, active_scb); 4726 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4727 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4728 scsi_print_addr(active_scb->xs->sc_link); 4729 printf("BDR message in message buffer\n"); 4730 active_scb->flags |= SCB_DEVICE_RESET; 4731 timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); 4732 unpause_sequencer(ahc); 4733 } else { 4734 int disconnected; 4735 4736 /* XXX Shouldn't panic. Just punt instead */ 4737 if ((scb->hscb->control & TARGET_SCB) != 0) 4738 panic("Timed-out target SCB but bus idle"); 4739 4740 if (last_phase != P_BUSFREE 4741 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4742 /* XXX What happened to the SCB? */ 4743 /* Hung target selection. Goto busfree */ 4744 printf("%s: Hung target selection\n", 4745 ahc_name(ahc)); 4746 restart_sequencer(ahc); 4747 return; 4748 } 4749 4750 if (ahc_search_qinfifo(ahc, target, channel, lun, 4751 scb->hscb->tag, ROLE_INITIATOR, 4752 /*status*/0, SEARCH_COUNT) > 0) { 4753 disconnected = FALSE; 4754 } else { 4755 disconnected = TRUE; 4756 } 4757 4758 if (disconnected) { 4759 u_int active_scb; 4760 4761 ahc_set_recoveryscb(ahc, scb); 4762 /* 4763 * Simply set the MK_MESSAGE control bit. 4764 */ 4765 scb->hscb->control |= MK_MESSAGE; 4766 scb->flags |= SCB_QUEUED_MSG 4767 | SCB_DEVICE_RESET; 4768 4769 /* 4770 * Mark the cached copy of this SCB in the 4771 * disconnected list too, so that a reconnect 4772 * at this point causes a BDR or abort. 4773 */ 4774 active_scb = ahc_inb(ahc, SCBPTR); 4775 if (ahc_search_disc_list(ahc, target, 4776 channel, lun, 4777 scb->hscb->tag, 4778 /*stop_on_first*/TRUE, 4779 /*remove*/FALSE, 4780 /*save_state*/FALSE)) { 4781 u_int scb_control; 4782 4783 scb_control = ahc_inb(ahc, SCB_CONTROL); 4784 scb_control |= MK_MESSAGE; 4785 ahc_outb(ahc, SCB_CONTROL, scb_control); 4786 } 4787 ahc_outb(ahc, SCBPTR, active_scb); 4788 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4789 /*unbusy*/TRUE); 4790 4791 /* 4792 * Actually re-queue this SCB in case we can 4793 * select the device before it reconnects. 4794 * Clear out any entries in the QINFIFO first 4795 * so we are the next SCB for this target 4796 * to run. 4797 */ 4798 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4799 channel, SCB_LUN(scb), 4800 SCB_LIST_NULL, 4801 ROLE_INITIATOR, 4802 SCB_REQUEUE, 4803 SEARCH_COMPLETE); 4804 scsi_print_addr(scb->xs->sc_link); 4805 printf("Queuing a BDR SCB\n"); 4806 ahc->qinfifo[ahc->qinfifonext++] = 4807 scb->hscb->tag; 4808 4809 bus_dmamap_sync(ahc->parent_dmat, 4810 ahc->shared_data_dmamap, 4811 QINFIFO_OFFSET * 256, 256, 4812 BUS_DMASYNC_PREWRITE); 4813 4814 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4815 ahc_outb(ahc, HNSCB_QOFF, 4816 ahc->qinfifonext); 4817 } else { 4818 ahc_outb(ahc, KERNEL_QINPOS, 4819 ahc->qinfifonext); 4820 } 4821 timeout(ahc_timeout, (caddr_t)scb, 2 * hz); 4822 unpause_sequencer(ahc); 4823 } else { 4824 /* Go "immediatly" to the bus reset */ 4825 /* This shouldn't happen */ 4826 ahc_set_recoveryscb(ahc, scb); 4827 scsi_print_addr(scb->xs->sc_link); 4828 printf("SCB %x: Immediate reset. " 4829 "Flags = 0x%x\n", scb->hscb->tag, 4830 scb->flags); 4831 goto bus_reset; 4832 } 4833 } 4834 } 4835 splx(s); 4836 } 4837 4838 static int 4839 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4840 int lun, u_int tag, role_t role, scb_flag status, 4841 ahc_search_action action) 4842 { 4843 struct scb *scbp; 4844 u_int8_t qinpos; 4845 u_int8_t qintail; 4846 int found; 4847 4848 qinpos = ahc_inb(ahc, QINPOS); 4849 qintail = ahc->qinfifonext; 4850 found = 0; 4851 4852 /* 4853 * Start with an empty queue. Entries that are not chosen 4854 * for removal will be re-added to the queue as we go. 4855 */ 4856 ahc->qinfifonext = qinpos; 4857 4858 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4859 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4860 4861 while (qinpos != qintail) { 4862 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4863 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4864 /* 4865 * We found an scb that needs to be removed. 4866 */ 4867 switch (action) { 4868 case SEARCH_COMPLETE: 4869 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4870 scbp->flags |= status; 4871 scbp->xs->error = XS_NOERROR; 4872 } 4873 ahc_freeze_ccb(scbp); 4874 ahc_done(ahc, scbp); 4875 break; 4876 case SEARCH_COUNT: 4877 ahc->qinfifo[ahc->qinfifonext++] = 4878 scbp->hscb->tag; 4879 break; 4880 case SEARCH_REMOVE: 4881 break; 4882 } 4883 found++; 4884 } else { 4885 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4886 } 4887 qinpos++; 4888 } 4889 4890 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4891 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4892 4893 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4894 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4895 } else { 4896 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4897 } 4898 4899 return (found); 4900 } 4901 4902 /* 4903 * Abort all SCBs that match the given description (target/channel/lun/tag), 4904 * setting their status to the passed in status if the status has not already 4905 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4906 * is paused before it is called. 4907 */ 4908 static int 4909 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4910 int lun, u_int tag, role_t role, int status) 4911 { 4912 struct scb *scbp; 4913 u_int active_scb; 4914 int i; 4915 int found; 4916 4917 /* restore this when we're done */ 4918 active_scb = ahc_inb(ahc, SCBPTR); 4919 4920 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4921 role, SCB_REQUEUE, SEARCH_COMPLETE); 4922 4923 /* 4924 * Search waiting for selection list. 4925 */ 4926 { 4927 u_int8_t next, prev; 4928 4929 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4930 prev = SCB_LIST_NULL; 4931 4932 while (next != SCB_LIST_NULL) { 4933 u_int8_t scb_index; 4934 4935 ahc_outb(ahc, SCBPTR, next); 4936 scb_index = ahc_inb(ahc, SCB_TAG); 4937 if (scb_index >= ahc->scb_data->numscbs) { 4938 panic("Waiting List inconsistency. " 4939 "SCB index == %d, yet numscbs == %d.", 4940 scb_index, ahc->scb_data->numscbs); 4941 } 4942 scbp = &ahc->scb_data->scbarray[scb_index]; 4943 if (ahc_match_scb(scbp, target, channel, 4944 lun, SCB_LIST_NULL, role)) { 4945 4946 next = ahc_abort_wscb(ahc, next, prev); 4947 } else { 4948 4949 prev = next; 4950 next = ahc_inb(ahc, SCB_NEXT); 4951 } 4952 } 4953 } 4954 /* 4955 * Go through the disconnected list and remove any entries we 4956 * have queued for completion, 0'ing their control byte too. 4957 * We save the active SCB and restore it ourselves, so there 4958 * is no reason for this search to restore it too. 4959 */ 4960 ahc_search_disc_list(ahc, target, channel, lun, tag, 4961 /*stop_on_first*/FALSE, /*remove*/TRUE, 4962 /*save_state*/FALSE); 4963 4964 /* 4965 * Go through the hardware SCB array looking for commands that 4966 * were active but not on any list. 4967 */ 4968 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4969 u_int scbid; 4970 4971 ahc_outb(ahc, SCBPTR, i); 4972 scbid = ahc_inb(ahc, SCB_TAG); 4973 scbp = &ahc->scb_data->scbarray[scbid]; 4974 if (scbid < ahc->scb_data->numscbs 4975 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4976 ahc_add_curscb_to_free_list(ahc); 4977 } 4978 4979 /* 4980 * Go through the pending CCB list and look for 4981 * commands for this target that are still active. 4982 * These are other tagged commands that were 4983 * disconnected when the reset occured. 4984 */ 4985 { 4986 struct scb *scb; 4987 4988 scb = ahc->pending_ccbs.lh_first; 4989 while (scb != NULL) { 4990 scbp = scb; 4991 scb = scb->plinks.le_next; 4992 if (ahc_match_scb(scbp, target, channel, 4993 lun, tag, role)) { 4994 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4995 ahcsetccbstatus(scbp->xs, status); 4996 ahc_freeze_ccb(scbp); 4997 ahc_done(ahc, scbp); 4998 found++; 4999 } 5000 } 5001 } 5002 ahc_outb(ahc, SCBPTR, active_scb); 5003 return found; 5004 } 5005 5006 static int 5007 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5008 int lun, u_int tag, int stop_on_first, int remove, 5009 int save_state) 5010 { 5011 struct scb *scbp; 5012 u_int next; 5013 u_int prev; 5014 u_int count; 5015 u_int active_scb; 5016 5017 count = 0; 5018 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5019 prev = SCB_LIST_NULL; 5020 5021 if (save_state) { 5022 /* restore this when we're done */ 5023 active_scb = ahc_inb(ahc, SCBPTR); 5024 } else 5025 /* Silence compiler */ 5026 active_scb = SCB_LIST_NULL; 5027 5028 while (next != SCB_LIST_NULL) { 5029 u_int scb_index; 5030 5031 ahc_outb(ahc, SCBPTR, next); 5032 scb_index = ahc_inb(ahc, SCB_TAG); 5033 if (scb_index >= ahc->scb_data->numscbs) { 5034 panic("Disconnected List inconsistency. " 5035 "SCB index == %d, yet numscbs == %d.", 5036 scb_index, ahc->scb_data->numscbs); 5037 } 5038 scbp = &ahc->scb_data->scbarray[scb_index]; 5039 if (ahc_match_scb(scbp, target, channel, lun, 5040 tag, ROLE_INITIATOR)) { 5041 count++; 5042 if (remove) { 5043 next = 5044 ahc_rem_scb_from_disc_list(ahc, prev, next); 5045 } else { 5046 prev = next; 5047 next = ahc_inb(ahc, SCB_NEXT); 5048 } 5049 if (stop_on_first) 5050 break; 5051 } else { 5052 prev = next; 5053 next = ahc_inb(ahc, SCB_NEXT); 5054 } 5055 } 5056 if (save_state) 5057 ahc_outb(ahc, SCBPTR, active_scb); 5058 return (count); 5059 } 5060 5061 static u_int 5062 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5063 { 5064 u_int next; 5065 5066 ahc_outb(ahc, SCBPTR, scbptr); 5067 next = ahc_inb(ahc, SCB_NEXT); 5068 5069 ahc_outb(ahc, SCB_CONTROL, 0); 5070 5071 ahc_add_curscb_to_free_list(ahc); 5072 5073 if (prev != SCB_LIST_NULL) { 5074 ahc_outb(ahc, SCBPTR, prev); 5075 ahc_outb(ahc, SCB_NEXT, next); 5076 } else 5077 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5078 5079 return (next); 5080 } 5081 5082 static void 5083 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5084 { 5085 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5086 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5087 5088 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5089 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5090 } 5091 5092 /* 5093 * Manipulate the waiting for selection list and return the 5094 * scb that follows the one that we remove. 5095 */ 5096 static u_int 5097 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5098 { 5099 u_int curscb, next; 5100 5101 /* 5102 * Select the SCB we want to abort and 5103 * pull the next pointer out of it. 5104 */ 5105 curscb = ahc_inb(ahc, SCBPTR); 5106 ahc_outb(ahc, SCBPTR, scbpos); 5107 next = ahc_inb(ahc, SCB_NEXT); 5108 5109 /* Clear the necessary fields */ 5110 ahc_outb(ahc, SCB_CONTROL, 0); 5111 5112 ahc_add_curscb_to_free_list(ahc); 5113 5114 /* update the waiting list */ 5115 if (prev == SCB_LIST_NULL) { 5116 /* First in the list */ 5117 ahc_outb(ahc, WAITING_SCBH, next); 5118 5119 /* 5120 * Ensure we aren't attempting to perform 5121 * selection for this entry. 5122 */ 5123 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5124 } else { 5125 /* 5126 * Select the scb that pointed to us 5127 * and update its next pointer. 5128 */ 5129 ahc_outb(ahc, SCBPTR, prev); 5130 ahc_outb(ahc, SCB_NEXT, next); 5131 } 5132 5133 /* 5134 * Point us back at the original scb position. 5135 */ 5136 ahc_outb(ahc, SCBPTR, curscb); 5137 return next; 5138 } 5139 5140 static void 5141 ahc_clear_intstat(struct ahc_softc *ahc) 5142 { 5143 /* Clear any interrupt conditions this may have caused */ 5144 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5145 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5146 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5147 CLRREQINIT); 5148 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5149 } 5150 5151 static void 5152 ahc_reset_current_bus(struct ahc_softc *ahc) 5153 { 5154 u_int8_t scsiseq; 5155 5156 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5157 scsiseq = ahc_inb(ahc, SCSISEQ); 5158 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5159 DELAY(AHC_BUSRESET_DELAY); 5160 /* Turn off the bus reset */ 5161 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5162 5163 ahc_clear_intstat(ahc); 5164 5165 /* Re-enable reset interrupts */ 5166 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5167 } 5168 5169 static int 5170 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5171 { 5172 u_int initiator, target, max_scsiid; 5173 u_int sblkctl; 5174 u_int our_id; 5175 int found; 5176 int restart_needed; 5177 char cur_channel; 5178 5179 ahc->pending_device = NULL; 5180 5181 pause_sequencer(ahc); 5182 5183 /* 5184 * Run our command complete fifos to ensure that we perform 5185 * completion processing on any commands that 'completed' 5186 * before the reset occurred. 5187 */ 5188 ahc_run_qoutfifo(ahc); 5189 5190 /* 5191 * Reset the bus if we are initiating this reset 5192 */ 5193 sblkctl = ahc_inb(ahc, SBLKCTL); 5194 cur_channel = 'A'; 5195 if ((ahc->features & AHC_TWIN) != 0 5196 && ((sblkctl & SELBUSB) != 0)) 5197 cur_channel = 'B'; 5198 if (cur_channel != channel) { 5199 /* Case 1: Command for another bus is active 5200 * Stealthily reset the other bus without 5201 * upsetting the current bus. 5202 */ 5203 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5204 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5205 ahc_outb(ahc, SCSISEQ, 5206 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5207 if (initiate_reset) 5208 ahc_reset_current_bus(ahc); 5209 ahc_clear_intstat(ahc); 5210 ahc_outb(ahc, SBLKCTL, sblkctl); 5211 restart_needed = FALSE; 5212 } else { 5213 /* Case 2: A command from this bus is active or we're idle */ 5214 ahc_clear_msg_state(ahc); 5215 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5216 ahc_outb(ahc, SCSISEQ, 5217 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5218 if (initiate_reset) 5219 ahc_reset_current_bus(ahc); 5220 ahc_clear_intstat(ahc); 5221 5222 /* 5223 * Since we are going to restart the sequencer, avoid 5224 * a race in the sequencer that could cause corruption 5225 * of our Q pointers by starting over from index 0. 5226 */ 5227 ahc->qoutfifonext = 0; 5228 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5229 ahc_outb(ahc, SDSCB_QOFF, 0); 5230 else 5231 ahc_outb(ahc, QOUTPOS, 0); 5232 restart_needed = TRUE; 5233 } 5234 5235 /* 5236 * Clean up all the state information for the 5237 * pending transactions on this bus. 5238 */ 5239 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5240 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5241 ROLE_UNKNOWN, XS_RESET); 5242 if (channel == 'B') { 5243 our_id = ahc->our_id_b; 5244 } else { 5245 our_id = ahc->our_id; 5246 } 5247 5248 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5249 5250 /* 5251 * Revert to async/narrow transfers until we renegotiate. 5252 */ 5253 for (target = 0; target <= max_scsiid; target++) { 5254 5255 if (ahc->enabled_targets[target] == NULL) 5256 continue; 5257 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5258 struct ahc_devinfo devinfo; 5259 5260 ahc_compile_devinfo(&devinfo, target, initiator, 5261 AHC_LUN_WILDCARD, 5262 channel, ROLE_UNKNOWN); 5263 ahc_set_width(ahc, &devinfo, 5264 MSG_EXT_WDTR_BUS_8_BIT, 5265 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5266 ahc_set_syncrate(ahc, &devinfo, 5267 /*syncrate*/NULL, /*period*/0, 5268 /*offset*/0, AHC_TRANS_CUR, 5269 /*paused*/TRUE, FALSE); 5270 } 5271 } 5272 5273 if (restart_needed) 5274 restart_sequencer(ahc); 5275 else 5276 unpause_sequencer(ahc); 5277 return found; 5278 } 5279 5280 static int 5281 ahc_match_scb(struct scb *scb, int target, char channel, 5282 int lun, u_int tag, role_t role) 5283 { 5284 int targ = SCB_TARGET(scb); 5285 char chan = SCB_CHANNEL(scb); 5286 int slun = SCB_LUN(scb); 5287 int match; 5288 5289 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5290 if (match != 0) 5291 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5292 if (match != 0) 5293 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5294 5295 return match; 5296 } 5297 5298 static void 5299 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5300 { 5301 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5302 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5303 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5304 ahc->msgout_buf[ahc->msgout_index++] = period; 5305 ahc->msgout_buf[ahc->msgout_index++] = offset; 5306 ahc->msgout_len += 5; 5307 } 5308 5309 static void 5310 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5311 { 5312 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5313 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5314 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5315 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5316 ahc->msgout_len += 4; 5317 } 5318 5319 static void 5320 ahc_calc_residual(struct scb *scb) 5321 { 5322 struct hardware_scb *hscb; 5323 5324 hscb = scb->hscb; 5325 5326 /* 5327 * If the disconnected flag is still set, this is bogus 5328 * residual information left over from a sequencer 5329 * pagin/pageout, so ignore this case. 5330 */ 5331 if ((scb->hscb->control & DISCONNECTED) == 0) { 5332 u_int32_t resid; 5333 int resid_sgs; 5334 int sg; 5335 5336 /* 5337 * Remainder of the SG where the transfer 5338 * stopped. 5339 */ 5340 resid = (hscb->residual_data_count[2] << 16) 5341 | (hscb->residual_data_count[1] <<8) 5342 | (hscb->residual_data_count[0]); 5343 5344 /* 5345 * Add up the contents of all residual 5346 * SG segments that are after the SG where 5347 * the transfer stopped. 5348 */ 5349 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5350 sg = scb->sg_count - resid_sgs; 5351 while (resid_sgs > 0) { 5352 5353 resid += le32toh(scb->sg_list[sg].len); 5354 sg++; 5355 resid_sgs--; 5356 } 5357 scb->xs->resid = resid; 5358 } 5359 5360 /* 5361 * Clean out the residual information in this SCB for its 5362 * next consumer. 5363 */ 5364 hscb->residual_SG_count = 0; 5365 5366 #ifdef AHC_DEBUG 5367 if (ahc_debug & AHC_SHOWMISC) { 5368 scsi_print_addr(scb->xs->sc_link); 5369 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5370 } 5371 #endif 5372 } 5373 5374 static void 5375 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5376 { 5377 struct scb *scb; 5378 int pending_ccb_count; 5379 int i; 5380 u_int saved_scbptr; 5381 5382 /* 5383 * Traverse the pending SCB list and ensure that all of the 5384 * SCBs there have the proper settings. 5385 */ 5386 scb = LIST_FIRST(&ahc->pending_ccbs); 5387 pending_ccb_count = 0; 5388 while (scb != NULL) { 5389 struct ahc_devinfo devinfo; 5390 struct scsipi_xfer *xs; 5391 struct scb *pending_scb; 5392 struct hardware_scb *pending_hscb; 5393 struct ahc_initiator_tinfo *tinfo; 5394 struct tmode_tstate *tstate; 5395 u_int our_id, remote_id; 5396 5397 xs = scb->xs; 5398 pending_scb = scb; 5399 pending_hscb = pending_scb->hscb; 5400 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5401 ? ahc->our_id_b : ahc->our_id; 5402 remote_id = xs->sc_link->scsipi_scsi.target; 5403 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5404 SCB_LUN(pending_scb), 5405 SCB_CHANNEL(pending_scb), 5406 ROLE_UNKNOWN); 5407 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5408 our_id, remote_id, &tstate); 5409 pending_hscb->control &= ~ULTRAENB; 5410 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5411 pending_hscb->control |= ULTRAENB; 5412 pending_hscb->scsirate = tinfo->scsirate; 5413 pending_hscb->scsioffset = tinfo->current.offset; 5414 pending_ccb_count++; 5415 scb = LIST_NEXT(scb, plinks); 5416 } 5417 5418 if (pending_ccb_count == 0) 5419 return; 5420 5421 saved_scbptr = ahc_inb(ahc, SCBPTR); 5422 /* Ensure that the hscbs down on the card match the new information */ 5423 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5424 u_int scb_tag; 5425 5426 ahc_outb(ahc, SCBPTR, i); 5427 scb_tag = ahc_inb(ahc, SCB_TAG); 5428 if (scb_tag != SCB_LIST_NULL) { 5429 struct ahc_devinfo devinfo; 5430 struct scb *pending_scb; 5431 struct scsipi_xfer *xs; 5432 struct hardware_scb *pending_hscb; 5433 struct ahc_initiator_tinfo *tinfo; 5434 struct tmode_tstate *tstate; 5435 u_int our_id, remote_id; 5436 u_int control; 5437 5438 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5439 if (pending_scb->flags == SCB_FREE) 5440 continue; 5441 pending_hscb = pending_scb->hscb; 5442 xs = pending_scb->xs; 5443 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5444 ? ahc->our_id_b : ahc->our_id; 5445 remote_id = xs->sc_link->scsipi_scsi.target; 5446 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5447 SCB_LUN(pending_scb), 5448 SCB_CHANNEL(pending_scb), 5449 ROLE_UNKNOWN); 5450 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5451 our_id, remote_id, &tstate); 5452 control = ahc_inb(ahc, SCB_CONTROL); 5453 control &= ~ULTRAENB; 5454 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5455 control |= ULTRAENB; 5456 ahc_outb(ahc, SCB_CONTROL, control); 5457 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5458 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5459 } 5460 } 5461 ahc_outb(ahc, SCBPTR, saved_scbptr); 5462 } 5463 5464 #if UNUSED 5465 static void 5466 ahc_dump_targcmd(struct target_cmd *cmd) 5467 { 5468 u_int8_t *byte; 5469 u_int8_t *last_byte; 5470 int i; 5471 5472 byte = &cmd->initiator_channel; 5473 /* Debugging info for received commands */ 5474 last_byte = &cmd[1].initiator_channel; 5475 5476 i = 0; 5477 while (byte < last_byte) { 5478 if (i == 0) 5479 printf("\t"); 5480 printf("%#x", *byte++); 5481 i++; 5482 if (i == 8) { 5483 printf("\n"); 5484 i = 0; 5485 } else { 5486 printf(", "); 5487 } 5488 } 5489 } 5490 #endif 5491 5492 static void 5493 ahc_shutdown(void *arg) 5494 { 5495 struct ahc_softc *ahc; 5496 int i; 5497 u_int sxfrctl1_a, sxfrctl1_b; 5498 5499 ahc = (struct ahc_softc *)arg; 5500 5501 pause_sequencer(ahc); 5502 5503 /* 5504 * Preserve the value of the SXFRCTL1 register for all channels. 5505 * It contains settings that affect termination and we don't want 5506 * to disturb the integrity of the bus during shutdown in case 5507 * we are in a multi-initiator setup. 5508 */ 5509 sxfrctl1_b = 0; 5510 if ((ahc->features & AHC_TWIN) != 0) { 5511 u_int sblkctl; 5512 5513 sblkctl = ahc_inb(ahc, SBLKCTL); 5514 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5515 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5516 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5517 } 5518 5519 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5520 5521 /* This will reset most registers to 0, but not all */ 5522 ahc_reset(ahc); 5523 5524 if ((ahc->features & AHC_TWIN) != 0) { 5525 u_int sblkctl; 5526 5527 sblkctl = ahc_inb(ahc, SBLKCTL); 5528 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5529 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5530 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5531 } 5532 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5533 5534 ahc_outb(ahc, SCSISEQ, 0); 5535 ahc_outb(ahc, SXFRCTL0, 0); 5536 ahc_outb(ahc, DSPCISTATUS, 0); 5537 5538 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5539 ahc_outb(ahc, i, 0); 5540 } 5541 5542 #if defined(AHC_DEBUG) && 0 5543 static void 5544 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5545 { 5546 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5547 5548 printf("\tcurrent:\n"); 5549 printf("\t\twidth %u period %u offset %u flags %x\n", 5550 tinfo->current.width, tinfo->current.period, 5551 tinfo->current.offset, tinfo->current.ppr_flags); 5552 5553 printf("\tgoal:\n"); 5554 printf("\t\twidth %u period %u offset %u flags %x\n", 5555 tinfo->goal.width, tinfo->goal.period, 5556 tinfo->goal.offset, tinfo->goal.ppr_flags); 5557 5558 printf("\tuser:\n"); 5559 printf("\t\twidth %u period %u offset %u flags %x\n", 5560 tinfo->user.width, tinfo->user.period, 5561 tinfo->user.offset, tinfo->user.ppr_flags); 5562 } 5563 #endif 5564
Indexes created Wed Oct 01 13:09:50 GMT 2025