aic7xxx.c revision 1.46
1 /* $NetBSD: aic7xxx.c,v 1.46 2000/03/25 21:09:08 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 102 #include <dev/scsipi/scsi_all.h> 103 #include <dev/scsipi/scsipi_all.h> 104 #include <dev/scsipi/scsi_message.h> 105 #include <dev/scsipi/scsipi_debug.h> 106 #include <dev/scsipi/scsiconf.h> 107 108 #include <vm/vm.h> 109 #include <vm/vm_param.h> 110 #include <vm/pmap.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 118 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 119 #define ALL_CHANNELS '\0' 120 #define ALL_TARGETS_MASK 0xFFFF 121 #define INITIATOR_WILDCARD (~0) 122 123 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 124 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 125 #define SIM_CHANNEL(ahc, sc_link) \ 126 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 127 #define SIM_SCSI_ID(ahc, sc_link) \ 128 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 129 #define SCB_IS_SCSIBUS_B(scb) \ 130 (((scb)->hscb->tcl & SELBUSB) != 0) 131 #define SCB_TARGET(scb) \ 132 (((scb)->hscb->tcl & TID) >> 4) 133 #define SCB_CHANNEL(scb) \ 134 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 135 #define SCB_LUN(scb) \ 136 ((scb)->hscb->tcl & LID) 137 #define SCB_TARGET_OFFSET(scb) \ 138 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 139 #define SCB_TARGET_MASK(scb) \ 140 (0x01 << (SCB_TARGET_OFFSET(scb))) 141 #define TCL_CHANNEL(ahc, tcl) \ 142 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 143 #define TCL_SCSI_ID(ahc, tcl) \ 144 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 145 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 146 #define TCL_LUN(tcl) ((tcl) & LID) 147 148 #define XS_TCL(ahc, xs) \ 149 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 150 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 151 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 152 153 char *ahc_chip_names[] = 154 { 155 "NONE", 156 "aic7770", 157 "aic7850", 158 "aic7855", 159 "aic7859", 160 "aic7860", 161 "aic7870", 162 "aic7880", 163 "aic7890/91", 164 "aic7892", 165 "aic7895", 166 "aic7896/97", 167 "aic7899" 168 }; 169 170 typedef enum { 171 ROLE_UNKNOWN, 172 ROLE_INITIATOR, 173 ROLE_TARGET 174 } role_t; 175 176 struct ahc_devinfo { 177 int our_scsiid; 178 int target_offset; 179 u_int16_t target_mask; 180 u_int8_t target; 181 u_int8_t lun; 182 char channel; 183 role_t role; /* 184 * Only guaranteed to be correct if not 185 * in the busfree state. 186 */ 187 }; 188 189 typedef enum { 190 SEARCH_COMPLETE, 191 SEARCH_COUNT, 192 SEARCH_REMOVE 193 } ahc_search_action; 194 195 #ifdef AHC_DEBUG 196 static int ahc_debug = AHC_DEBUG; 197 #endif 198 199 static int ahcinitscbdata(struct ahc_softc *); 200 static void ahcfiniscbdata(struct ahc_softc *); 201 202 #if UNUSED 203 static void ahc_dump_targcmd(struct target_cmd *); 204 #endif 205 static void ahc_shutdown(void *arg); 206 static int32_t ahc_action(struct scsipi_xfer *); 207 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 208 static int ahc_poll(struct ahc_softc *, int); 209 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 210 struct scb *); 211 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 212 static void ahcallocscbs(struct ahc_softc *); 213 #if UNUSED 214 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 215 struct scb *); 216 #endif 217 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 218 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 219 char, role_t); 220 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 221 static void ahc_done(struct ahc_softc *, struct scb *); 222 static struct tmode_tstate * 223 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 224 #if UNUSED 225 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 226 #endif 227 static void ahc_handle_seqint(struct ahc_softc *, u_int); 228 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 229 static void ahc_build_transfer_msg(struct ahc_softc *, 230 struct ahc_devinfo *); 231 static void ahc_setup_initiator_msgout(struct ahc_softc *, 232 struct ahc_devinfo *, 233 struct scb *); 234 static void ahc_setup_target_msgin(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_clear_msg_state(struct ahc_softc *); 237 static void ahc_handle_message_phase(struct ahc_softc *, 238 struct scsipi_link *); 239 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 240 241 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 242 struct ahc_devinfo *); 243 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 244 struct ahc_devinfo *); 245 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 246 int, char *, int); 247 #ifdef AHC_DUMP_SEQ 248 static void ahc_dumpseq(struct ahc_softc *); 249 #endif 250 static void ahc_loadseq(struct ahc_softc *); 251 static int ahc_check_patch(struct ahc_softc *, struct patch **, 252 int, int *); 253 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 254 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 255 #if defined(AHC_DEBUG) 256 static void ahc_print_scb(struct scb *); 257 #endif 258 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 259 role_t, scb_flag, ahc_search_action); 260 static int ahc_reset_channel(struct ahc_softc *, char, int); 261 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 262 role_t, int); 263 static int ahc_search_disc_list(struct ahc_softc *, int, 264 char, int, u_int, int, int, int); 265 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 266 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 267 static void ahc_clear_intstat(struct ahc_softc *); 268 static void ahc_reset_current_bus(struct ahc_softc *); 269 static struct ahc_syncrate * 270 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 271 static struct ahc_syncrate * 272 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 273 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 274 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 275 u_int *, int); 276 static void ahc_update_target_msg_request(struct ahc_softc *, 277 struct ahc_devinfo *, 278 struct ahc_initiator_tinfo *, 279 int, int); 280 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 281 struct ahc_syncrate *, u_int, u_int, u_int, 282 int, int); 283 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 284 u_int, u_int, int, int); 285 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 286 int); 287 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 288 289 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 290 291 static void ahc_calc_residual(struct scb *); 292 293 static void ahc_update_pending_syncrates(struct ahc_softc *); 294 295 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 296 297 static void ahc_timeout (void *); 298 static __inline int sequencer_paused(struct ahc_softc *); 299 static __inline void pause_sequencer(struct ahc_softc *); 300 static __inline void unpause_sequencer(struct ahc_softc *); 301 static void restart_sequencer(struct ahc_softc *); 302 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 303 304 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 305 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 306 307 static __inline void ahc_freeze_ccb(struct scb *); 308 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 309 static void ahc_run_qoutfifo(struct ahc_softc *); 310 311 static __inline struct ahc_initiator_tinfo * 312 ahc_fetch_transinfo(struct ahc_softc *, 313 char, u_int, u_int, 314 struct tmode_tstate **); 315 static void ahcfreescb(struct ahc_softc *, struct scb *); 316 static __inline struct scb *ahcgetscb(struct ahc_softc *); 317 318 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 319 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 320 int *, const char *, const char *); 321 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 322 caddr_t, bus_dma_segment_t *, int); 323 static void ahcminphys(struct buf *); 324 325 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 329 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *); 330 331 #if defined(AHC_DEBUG) && 0 332 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 333 #endif 334 335 static struct scsipi_device ahc_dev = 336 { 337 NULL, /* Use default error handler */ 338 NULL, /* have a queue, served by this */ 339 NULL, /* have no async handler */ 340 NULL, /* Use default 'done' routine */ 341 }; 342 343 /* 344 * Pick the first xs for a non-blocked target. 345 */ 346 static __inline struct scsipi_xfer * 347 ahc_first_xs(struct ahc_softc *ahc) 348 { 349 int target; 350 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 351 352 if (ahc->queue_blocked) 353 return NULL; 354 355 while (xs != NULL) { 356 target = xs->sc_link->scsipi_scsi.target; 357 if (ahc->devqueue_blocked[target] == 0 && 358 (!ahc_istagged_device(ahc, xs) && 359 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 360 SCB_LIST_NULL)) 361 break; 362 xs = TAILQ_NEXT(xs, adapter_q); 363 } 364 365 return xs; 366 } 367 368 static __inline void 369 ahc_swap_hscb(struct hardware_scb *hscb) 370 { 371 hscb->SG_pointer = htole32(hscb->SG_pointer); 372 hscb->data = htole32(hscb->data); 373 hscb->datalen = htole32(hscb->datalen); 374 /* 375 * No need to swap cmdpointer; it's either NULL or set to 376 * cmdstore_busaddr, which is already swapped. 377 */ 378 } 379 380 static __inline void 381 ahc_swap_sg(struct ahc_dma_seg *sg) 382 { 383 sg->addr = htole32(sg->addr); 384 sg->len = htole32(sg->len); 385 } 386 387 static void 388 ahcminphys(bp) 389 struct buf *bp; 390 { 391 /* 392 * Even though the card can transfer up to 16megs per command 393 * we are limited by the number of segments in the dma segment 394 * list that we can hold. The worst case is that all pages are 395 * discontinuous physically, hense the "page per segment" limit 396 * enforced here. 397 */ 398 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 399 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 400 } 401 minphys(bp); 402 } 403 404 405 static __inline u_int32_t 406 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 407 { 408 return (ahc->scb_data->hscb_busaddr 409 + (sizeof(struct hardware_scb) * index)); 410 } 411 412 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 413 414 static __inline int 415 sequencer_paused(struct ahc_softc *ahc) 416 { 417 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 418 } 419 420 static __inline void 421 pause_sequencer(struct ahc_softc *ahc) 422 { 423 ahc_outb(ahc, HCNTRL, ahc->pause); 424 425 /* 426 * Since the sequencer can disable pausing in a critical section, we 427 * must loop until it actually stops. 428 */ 429 while (sequencer_paused(ahc) == 0) 430 ; 431 } 432 433 static __inline void 434 unpause_sequencer(struct ahc_softc *ahc) 435 { 436 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 437 ahc_outb(ahc, HCNTRL, ahc->unpause); 438 } 439 440 /* 441 * Restart the sequencer program from address zero 442 */ 443 static void 444 restart_sequencer(struct ahc_softc *ahc) 445 { 446 u_int i; 447 448 pause_sequencer(ahc); 449 450 /* 451 * Everytime we restart the sequencer, there 452 * is the possiblitity that we have restarted 453 * within a three instruction window where an 454 * SCB has been marked free but has not made it 455 * onto the free list. Since SCSI events(bus reset, 456 * unexpected bus free) will always freeze the 457 * sequencer, we cannot close this window. To 458 * avoid losing an SCB, we reconsitute the free 459 * list every time we restart the sequencer. 460 */ 461 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 462 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 463 464 ahc_outb(ahc, SCBPTR, i); 465 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 466 ahc_add_curscb_to_free_list(ahc); 467 } 468 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 469 unpause_sequencer(ahc); 470 } 471 472 static __inline u_int 473 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 474 { 475 u_int scbid; 476 477 scbid = ahc->untagged_scbs[tcl]; 478 if (unbusy) { 479 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 480 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 481 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 482 } 483 484 return (scbid); 485 } 486 487 static __inline void 488 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 489 { 490 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 491 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 492 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 493 } 494 495 static __inline int 496 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 497 { 498 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 499 } 500 501 static __inline void 502 ahc_freeze_ccb(struct scb *scb) 503 { 504 struct scsipi_xfer *xs = scb->xs; 505 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 506 int target; 507 508 target = xs->sc_link->scsipi_scsi.target; 509 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 510 ahc->devqueue_blocked[target]++; 511 scb->flags |= SCB_FREEZE_QUEUE; 512 } 513 } 514 515 static __inline void 516 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 517 { 518 xs->error = status; 519 } 520 521 static __inline struct ahc_initiator_tinfo * 522 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 523 u_int remote_id, struct tmode_tstate **tstate) 524 { 525 /* 526 * Transfer data structures are stored from the perspective 527 * of the target role. Since the parameters for a connection 528 * in the initiator role to a given target are the same as 529 * when the roles are reversed, we pretend we are the target. 530 */ 531 if (channel == 'B') 532 our_id += 8; 533 *tstate = ahc->enabled_targets[our_id]; 534 return (&(*tstate)->transinfo[remote_id]); 535 } 536 537 static void 538 ahc_run_qoutfifo(struct ahc_softc *ahc) 539 { 540 struct scb *scb; 541 u_int scb_index; 542 543 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 544 256, BUS_DMASYNC_POSTREAD); 545 546 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 547 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 548 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 549 550 scb = &ahc->scb_data->scbarray[scb_index]; 551 if (scb_index >= ahc->scb_data->numscbs 552 || (scb->flags & SCB_ACTIVE) == 0) { 553 printf("%s: WARNING no command for scb %d " 554 "(cmdcmplt)\nQOUTPOS = %d\n", 555 ahc_name(ahc), scb_index, 556 ahc->qoutfifonext - 1); 557 continue; 558 } 559 560 /* 561 * Save off the residual 562 * if there is one. 563 */ 564 if (scb->hscb->residual_SG_count != 0) 565 ahc_calc_residual(scb); 566 else 567 scb->xs->resid = 0; 568 #ifdef AHC_DEBUG 569 if (ahc_debug & AHC_SHOWSCBS) { 570 scsi_print_addr(scb->xs->sc_link); 571 printf("run_qoutfifo: SCB %x complete\n", 572 scb->hscb->tag); 573 } 574 #endif 575 ahc_done(ahc, scb); 576 } 577 } 578 579 580 /* 581 * An scb (and hence an scb entry on the board) is put onto the 582 * free list. 583 */ 584 static void 585 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 586 { 587 struct hardware_scb *hscb; 588 int opri; 589 590 hscb = scb->hscb; 591 592 #ifdef AHC_DEBUG 593 if (ahc_debug & AHC_SHOWSCBALLOC) 594 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 595 #endif 596 597 opri = splbio(); 598 599 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 600 (scb->flags & SCB_RECOVERY_SCB) != 0) { 601 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 602 ahc->queue_blocked = 0; 603 } 604 605 /* Clean up for the next user */ 606 scb->flags = SCB_FREE; 607 hscb->control = 0; 608 hscb->status = 0; 609 610 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 611 612 splx(opri); 613 } 614 615 /* 616 * Get a free scb, either one already assigned to a hardware slot 617 * on the adapter or one that will require an SCB to be paged out before 618 * use. If there are none, see if we can allocate a new SCB. Otherwise 619 * either return an error or sleep. 620 */ 621 static __inline struct scb * 622 ahcgetscb(struct ahc_softc *ahc) 623 { 624 struct scb *scbp; 625 int opri;; 626 627 opri = splbio(); 628 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 629 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 630 } else { 631 ahcallocscbs(ahc); 632 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 633 if (scbp != NULL) 634 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 635 } 636 637 splx(opri); 638 639 #ifdef AHC_DEBUG 640 if (ahc_debug & AHC_SHOWSCBALLOC) { 641 if (scbp != NULL) 642 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 643 scbp->hscb->tag); 644 else 645 printf("%s: failed to allocate new SCB\n", 646 ahc_name(ahc)); 647 } 648 #endif 649 650 return (scbp); 651 } 652 653 static int 654 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 655 bus_dma_tag_t tag; 656 int size; 657 int flags; 658 bus_dmamap_t *mapp; 659 caddr_t *vaddr; 660 bus_addr_t *baddr; 661 bus_dma_segment_t *seg; 662 int *nseg; 663 const char *myname, *what; 664 { 665 int error, level = 0; 666 667 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 668 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 669 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 670 myname, what, error); 671 goto out; 672 } 673 level++; 674 675 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 676 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 677 printf("%s: failed to map DMA mem for %s, error = %d\n", 678 myname, what, error); 679 goto out; 680 } 681 level++; 682 683 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 684 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 685 printf("%s: failed to create DMA map for %s, error = %d\n", 686 myname, what, error); 687 goto out; 688 } 689 level++; 690 691 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 692 BUS_DMA_NOWAIT)) != 0) { 693 printf("%s: failed to load DMA map for %s, error = %d\n", 694 myname, what, error); 695 goto out; 696 } 697 698 *baddr = (*mapp)->dm_segs[0].ds_addr; 699 700 #ifdef AHC_DEBUG 701 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 702 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 703 *nseg, size); 704 #endif 705 706 return 0; 707 out: 708 switch (level) { 709 case 3: 710 bus_dmamap_destroy(tag, *mapp); 711 /* FALLTHROUGH */ 712 case 2: 713 bus_dmamem_unmap(tag, *vaddr, size); 714 /* FALLTHROUGH */ 715 case 1: 716 bus_dmamem_free(tag, seg, *nseg); 717 break; 718 default: 719 break; 720 } 721 722 return error; 723 } 724 725 static void 726 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 727 bus_dma_tag_t tag; 728 int size; 729 bus_dmamap_t map; 730 caddr_t vaddr; 731 bus_dma_segment_t *seg; 732 int nseg; 733 { 734 735 bus_dmamap_unload(tag, map); 736 bus_dmamap_destroy(tag, map); 737 bus_dmamem_unmap(tag, vaddr, size); 738 bus_dmamem_free(tag, seg, nseg); 739 } 740 741 char * 742 ahc_name(struct ahc_softc *ahc) 743 { 744 return (ahc->sc_dev.dv_xname); 745 } 746 747 #ifdef AHC_DEBUG 748 static void 749 ahc_print_scb(struct scb *scb) 750 { 751 struct hardware_scb *hscb = scb->hscb; 752 753 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 754 scb, 755 hscb->tag, 756 hscb->control, 757 hscb->tcl, 758 hscb->cmdlen, 759 (unsigned long)le32toh(hscb->cmdpointer)); 760 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 761 le32toh(hscb->datalen), 762 (unsigned long)(le32toh(hscb->data)), 763 hscb->SG_count, 764 (unsigned long)(le32toh(hscb->SG_pointer))); 765 printf(" sg_addr:%lx sg_len:%lu\n", 766 (unsigned long)(le32toh(scb->sg_list[0].addr)), 767 (unsigned long)(le32toh(scb->sg_list[0].len)); 768 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 769 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 770 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 771 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 772 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 773 } 774 #endif 775 776 static struct { 777 u_int8_t errno; 778 char *errmesg; 779 } hard_error[] = { 780 { ILLHADDR, "Illegal Host Access" }, 781 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 782 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 783 { SQPARERR, "Sequencer Parity Error" }, 784 { DPARERR, "Data-path Parity Error" }, 785 { MPARERR, "Scratch or SCB Memory Parity Error" }, 786 { PCIERRSTAT, "PCI Error detected" }, 787 { CIOPARERR, "CIOBUS Parity Error" }, 788 }; 789 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 790 791 static struct { 792 u_int8_t phase; 793 u_int8_t mesg_out; /* Message response to parity errors */ 794 char *phasemsg; 795 } phase_table[] = { 796 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 797 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 798 { P_COMMAND, MSG_NOOP, "in Command phase" }, 799 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 800 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 801 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 802 { P_BUSFREE, MSG_NOOP, "while idle" }, 803 { 0, MSG_NOOP, "in unknown phase" } 804 }; 805 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 806 807 /* 808 * Valid SCSIRATE values. (p. 3-17) 809 * Provides a mapping of tranfer periods in ns to the proper value to 810 * stick in the scsiscfr reg to use that transfer rate. 811 */ 812 #define AHC_SYNCRATE_DT 0 813 #define AHC_SYNCRATE_ULTRA2 1 814 #define AHC_SYNCRATE_ULTRA 3 815 #define AHC_SYNCRATE_FAST 6 816 static struct ahc_syncrate ahc_syncrates[] = { 817 /* ultra2 fast/ultra period rate */ 818 { 0x42, 0x000, 9, "80.0" }, 819 { 0x03, 0x000, 10, "40.0" }, 820 { 0x04, 0x000, 11, "33.0" }, 821 { 0x05, 0x100, 12, "20.0" }, 822 { 0x06, 0x110, 15, "16.0" }, 823 { 0x07, 0x120, 18, "13.4" }, 824 { 0x08, 0x000, 25, "10.0" }, 825 { 0x19, 0x010, 31, "8.0" }, 826 { 0x1a, 0x020, 37, "6.67" }, 827 { 0x1b, 0x030, 43, "5.7" }, 828 { 0x1c, 0x040, 50, "5.0" }, 829 { 0x00, 0x050, 56, "4.4" }, 830 { 0x00, 0x060, 62, "4.0" }, 831 { 0x00, 0x070, 68, "3.6" }, 832 { 0x00, 0x000, 0, NULL } 833 }; 834 835 /* 836 * Allocate a controller structure for a new device and initialize it. 837 */ 838 int 839 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 840 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 841 ahc_flag flags) 842 { 843 struct scb_data *scb_data; 844 845 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 846 if (scb_data == NULL) { 847 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 848 return -1; 849 } 850 bzero(scb_data, sizeof (struct scb_data)); 851 LIST_INIT(&ahc->pending_ccbs); 852 ahc->tag = st; 853 ahc->bsh = sh; 854 ahc->parent_dmat = parent_dmat; 855 ahc->chip = chip; 856 ahc->features = features; 857 ahc->flags = flags; 858 ahc->scb_data = scb_data; 859 860 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 861 /* The IRQMS bit is only valid on VL and EISA chips */ 862 if ((ahc->chip & AHC_PCI) != 0) 863 ahc->unpause &= ~IRQMS; 864 ahc->pause = ahc->unpause | PAUSE; 865 return (0); 866 } 867 868 void 869 ahc_free(ahc) 870 struct ahc_softc *ahc; 871 { 872 ahcfiniscbdata(ahc); 873 if (ahc->init_level != 0) 874 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 875 ahc->shared_data_dmamap, ahc->qoutfifo, 876 &ahc->shared_data_seg, ahc->shared_data_nseg); 877 878 if (ahc->scb_data != NULL) 879 free(ahc->scb_data, M_DEVBUF); 880 if (ahc->bus_data != NULL) 881 free(ahc->bus_data, M_DEVBUF); 882 return; 883 } 884 885 static int 886 ahcinitscbdata(struct ahc_softc *ahc) 887 { 888 struct scb_data *scb_data; 889 int i; 890 891 scb_data = ahc->scb_data; 892 SLIST_INIT(&scb_data->free_scbs); 893 SLIST_INIT(&scb_data->sg_maps); 894 895 /* Allocate SCB resources */ 896 scb_data->scbarray = 897 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 898 M_DEVBUF, M_NOWAIT); 899 if (scb_data->scbarray == NULL) 900 return (ENOMEM); 901 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 902 903 /* Determine the number of hardware SCBs and initialize them */ 904 905 scb_data->maxhscbs = ahc_probe_scbs(ahc); 906 /* SCB 0 heads the free list */ 907 ahc_outb(ahc, FREE_SCBH, 0); 908 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 909 ahc_outb(ahc, SCBPTR, i); 910 911 /* Clear the control byte. */ 912 ahc_outb(ahc, SCB_CONTROL, 0); 913 914 /* Set the next pointer */ 915 ahc_outb(ahc, SCB_NEXT, i+1); 916 917 /* Make the tag number invalid */ 918 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 919 } 920 921 /* Make sure that the last SCB terminates the free list */ 922 ahc_outb(ahc, SCBPTR, i-1); 923 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 924 925 /* Ensure we clear the 0 SCB's control byte. */ 926 ahc_outb(ahc, SCBPTR, 0); 927 ahc_outb(ahc, SCB_CONTROL, 0); 928 929 scb_data->maxhscbs = i; 930 931 if (ahc->scb_data->maxhscbs == 0) 932 panic("%s: No SCB space found", ahc_name(ahc)); 933 934 /* 935 * Create our DMA tags. These tags define the kinds of device 936 * accessable memory allocations and memory mappings we will 937 * need to perform during normal operation. 938 * 939 * Unless we need to further restrict the allocation, we rely 940 * on the restrictions of the parent dmat, hence the common 941 * use of MAXADDR and MAXSIZE. 942 */ 943 944 if (ahc_createdmamem(ahc->parent_dmat, 945 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 946 &scb_data->hscb_dmamap, 947 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 948 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 949 "hardware SCB structures") < 0) 950 goto error_exit; 951 952 scb_data->init_level++; 953 954 if (ahc_createdmamem(ahc->parent_dmat, 955 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 956 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 957 &scb_data->sense_busaddr, &scb_data->sense_seg, 958 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 959 goto error_exit; 960 961 scb_data->init_level++; 962 963 /* Perform initial CCB allocation */ 964 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 965 ahcallocscbs(ahc); 966 967 if (scb_data->numscbs == 0) { 968 printf("%s: ahc_init_scb_data - " 969 "Unable to allocate initial scbs\n", 970 ahc_name(ahc)); 971 goto error_exit; 972 } 973 974 scb_data->init_level++; 975 976 /* 977 * Note that we were successfull 978 */ 979 return 0; 980 981 error_exit: 982 983 return ENOMEM; 984 } 985 986 static void 987 ahcfiniscbdata(struct ahc_softc *ahc) 988 { 989 struct scb_data *scb_data; 990 991 scb_data = ahc->scb_data; 992 993 switch (scb_data->init_level) { 994 default: 995 case 3: 996 { 997 struct sg_map_node *sg_map; 998 999 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1000 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1001 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1002 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1003 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1004 free(sg_map, M_DEVBUF); 1005 } 1006 } 1007 /*FALLTHROUGH*/ 1008 case 2: 1009 ahc_freedmamem(ahc->parent_dmat, 1010 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1011 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1012 &scb_data->sense_seg, scb_data->sense_nseg); 1013 /*FALLTHROUGH*/ 1014 case 1: 1015 ahc_freedmamem(ahc->parent_dmat, 1016 AHC_SCB_MAX * sizeof(struct hardware_scb), 1017 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1018 &scb_data->hscb_seg, scb_data->hscb_nseg); 1019 /*FALLTHROUGH*/ 1020 } 1021 if (scb_data->scbarray != NULL) 1022 free(scb_data->scbarray, M_DEVBUF); 1023 } 1024 1025 int 1026 ahc_reset(struct ahc_softc *ahc) 1027 { 1028 u_int sblkctl; 1029 int wait; 1030 1031 #ifdef AHC_DUMP_SEQ 1032 if (ahc->init_level == 0) 1033 ahc_dumpseq(ahc); 1034 #endif 1035 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1036 /* 1037 * Ensure that the reset has finished 1038 */ 1039 wait = 1000; 1040 do { 1041 DELAY(1000); 1042 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1043 1044 if (wait == 0) { 1045 printf("%s: WARNING - Failed chip reset! " 1046 "Trying to initialize anyway.\n", ahc_name(ahc)); 1047 } 1048 ahc_outb(ahc, HCNTRL, ahc->pause); 1049 1050 /* Determine channel configuration */ 1051 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1052 /* No Twin Channel PCI cards */ 1053 if ((ahc->chip & AHC_PCI) != 0) 1054 sblkctl &= ~SELBUSB; 1055 switch (sblkctl) { 1056 case 0: 1057 /* Single Narrow Channel */ 1058 break; 1059 case 2: 1060 /* Wide Channel */ 1061 ahc->features |= AHC_WIDE; 1062 break; 1063 case 8: 1064 /* Twin Channel */ 1065 ahc->features |= AHC_TWIN; 1066 break; 1067 default: 1068 printf(" Unsupported adapter type. Ignoring\n"); 1069 return(-1); 1070 } 1071 1072 return (0); 1073 } 1074 1075 /* 1076 * Called when we have an active connection to a target on the bus, 1077 * this function finds the nearest syncrate to the input period limited 1078 * by the capabilities of the bus connectivity of the target. 1079 */ 1080 static struct ahc_syncrate * 1081 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1082 u_int maxsync; 1083 1084 if ((ahc->features & AHC_ULTRA2) != 0) { 1085 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1086 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1087 maxsync = AHC_SYNCRATE_ULTRA2; 1088 } else { 1089 maxsync = AHC_SYNCRATE_ULTRA; 1090 } 1091 } else if ((ahc->features & AHC_ULTRA) != 0) { 1092 maxsync = AHC_SYNCRATE_ULTRA; 1093 } else { 1094 maxsync = AHC_SYNCRATE_FAST; 1095 } 1096 return (ahc_find_syncrate(ahc, period, maxsync)); 1097 } 1098 1099 /* 1100 * Look up the valid period to SCSIRATE conversion in our table. 1101 * Return the period and offset that should be sent to the target 1102 * if this was the beginning of an SDTR. 1103 */ 1104 static struct ahc_syncrate * 1105 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1106 { 1107 struct ahc_syncrate *syncrate; 1108 1109 syncrate = &ahc_syncrates[maxsync]; 1110 while ((syncrate->rate != NULL) 1111 && ((ahc->features & AHC_ULTRA2) == 0 1112 || (syncrate->sxfr_u2 != 0))) { 1113 1114 if (*period <= syncrate->period) { 1115 /* 1116 * When responding to a target that requests 1117 * sync, the requested rate may fall between 1118 * two rates that we can output, but still be 1119 * a rate that we can receive. Because of this, 1120 * we want to respond to the target with 1121 * the same rate that it sent to us even 1122 * if the period we use to send data to it 1123 * is lower. Only lower the response period 1124 * if we must. 1125 */ 1126 if (syncrate == &ahc_syncrates[maxsync]) 1127 *period = syncrate->period; 1128 break; 1129 } 1130 syncrate++; 1131 } 1132 1133 if ((*period == 0) 1134 || (syncrate->rate == NULL) 1135 || ((ahc->features & AHC_ULTRA2) != 0 1136 && (syncrate->sxfr_u2 == 0))) { 1137 /* Use asynchronous transfers. */ 1138 *period = 0; 1139 syncrate = NULL; 1140 } 1141 return (syncrate); 1142 } 1143 1144 static u_int 1145 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1146 { 1147 struct ahc_syncrate *syncrate; 1148 1149 if ((ahc->features & AHC_ULTRA2) != 0) 1150 scsirate &= SXFR_ULTRA2; 1151 else 1152 scsirate &= SXFR; 1153 1154 syncrate = &ahc_syncrates[maxsync]; 1155 while (syncrate->rate != NULL) { 1156 1157 if ((ahc->features & AHC_ULTRA2) != 0) { 1158 if (syncrate->sxfr_u2 == 0) 1159 break; 1160 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1161 return (syncrate->period); 1162 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1163 return (syncrate->period); 1164 } 1165 syncrate++; 1166 } 1167 return (0); /* async */ 1168 } 1169 1170 static void 1171 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1172 u_int *offset, int wide) 1173 { 1174 u_int maxoffset; 1175 1176 /* Limit offset to what we can do */ 1177 if (syncrate == NULL) { 1178 maxoffset = 0; 1179 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1180 maxoffset = MAX_OFFSET_ULTRA2; 1181 } else { 1182 if (wide) 1183 maxoffset = MAX_OFFSET_16BIT; 1184 else 1185 maxoffset = MAX_OFFSET_8BIT; 1186 } 1187 *offset = MIN(*offset, maxoffset); 1188 } 1189 1190 static void 1191 ahc_update_target_msg_request(struct ahc_softc *ahc, 1192 struct ahc_devinfo *devinfo, 1193 struct ahc_initiator_tinfo *tinfo, 1194 int force, int paused) 1195 { 1196 u_int targ_msg_req_orig; 1197 1198 targ_msg_req_orig = ahc->targ_msg_req; 1199 if (tinfo->current.period != tinfo->goal.period 1200 || tinfo->current.width != tinfo->goal.width 1201 || tinfo->current.offset != tinfo->goal.offset 1202 || (force 1203 && (tinfo->goal.period != 0 1204 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1205 ahc->targ_msg_req |= devinfo->target_mask; 1206 } else { 1207 ahc->targ_msg_req &= ~devinfo->target_mask; 1208 } 1209 1210 if (ahc->targ_msg_req != targ_msg_req_orig) { 1211 /* Update the message request bit for this target */ 1212 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1213 if (paused) { 1214 ahc_outb(ahc, TARGET_MSG_REQUEST, 1215 ahc->targ_msg_req & 0xFF); 1216 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1217 (ahc->targ_msg_req >> 8) & 0xFF); 1218 } else { 1219 ahc_outb(ahc, HS_MAILBOX, 1220 0x01 << HOST_MAILBOX_SHIFT); 1221 } 1222 } else { 1223 if (!paused) 1224 pause_sequencer(ahc); 1225 1226 ahc_outb(ahc, TARGET_MSG_REQUEST, 1227 ahc->targ_msg_req & 0xFF); 1228 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1229 (ahc->targ_msg_req >> 8) & 0xFF); 1230 1231 if (!paused) 1232 unpause_sequencer(ahc); 1233 } 1234 } 1235 } 1236 1237 static void 1238 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1239 struct ahc_syncrate *syncrate, 1240 u_int period, u_int offset, u_int type, int paused, int done) 1241 { 1242 struct ahc_initiator_tinfo *tinfo; 1243 struct tmode_tstate *tstate; 1244 u_int old_period; 1245 u_int old_offset; 1246 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1247 1248 if (syncrate == NULL) { 1249 period = 0; 1250 offset = 0; 1251 } 1252 1253 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1254 devinfo->target, &tstate); 1255 old_period = tinfo->current.period; 1256 old_offset = tinfo->current.offset; 1257 1258 if ((type & AHC_TRANS_CUR) != 0 1259 && (old_period != period || old_offset != offset)) { 1260 u_int scsirate; 1261 1262 scsirate = tinfo->scsirate; 1263 if ((ahc->features & AHC_ULTRA2) != 0) { 1264 1265 /* XXX */ 1266 /* Force single edge until DT is fully implemented */ 1267 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1268 if (syncrate != NULL) 1269 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1270 1271 if (active) 1272 ahc_outb(ahc, SCSIOFFSET, offset); 1273 } else { 1274 1275 scsirate &= ~(SXFR|SOFS); 1276 /* 1277 * Ensure Ultra mode is set properly for 1278 * this target. 1279 */ 1280 tstate->ultraenb &= ~devinfo->target_mask; 1281 if (syncrate != NULL) { 1282 if (syncrate->sxfr & ULTRA_SXFR) { 1283 tstate->ultraenb |= 1284 devinfo->target_mask; 1285 } 1286 scsirate |= syncrate->sxfr & SXFR; 1287 scsirate |= offset & SOFS; 1288 } 1289 if (active) { 1290 u_int sxfrctl0; 1291 1292 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1293 sxfrctl0 &= ~FAST20; 1294 if (tstate->ultraenb & devinfo->target_mask) 1295 sxfrctl0 |= FAST20; 1296 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1297 } 1298 } 1299 if (active) 1300 ahc_outb(ahc, SCSIRATE, scsirate); 1301 1302 tinfo->scsirate = scsirate; 1303 tinfo->current.period = period; 1304 tinfo->current.offset = offset; 1305 1306 /* Update the syncrates in any pending scbs */ 1307 ahc_update_pending_syncrates(ahc); 1308 } 1309 1310 /* 1311 * Print messages if we're verbose and at the end of a negotiation 1312 * cycle. 1313 */ 1314 if (done) { 1315 if (offset != 0) { 1316 printf("%s: target %d synchronous at %sMHz, " 1317 "offset = 0x%x\n", ahc_name(ahc), 1318 devinfo->target, syncrate->rate, offset); 1319 } else { 1320 printf("%s: target %d using " 1321 "asynchronous transfers\n", 1322 ahc_name(ahc), devinfo->target); 1323 } 1324 } 1325 1326 if ((type & AHC_TRANS_GOAL) != 0) { 1327 tinfo->goal.period = period; 1328 tinfo->goal.offset = offset; 1329 } 1330 1331 if ((type & AHC_TRANS_USER) != 0) { 1332 tinfo->user.period = period; 1333 tinfo->user.offset = offset; 1334 } 1335 1336 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1337 /*force*/FALSE, 1338 paused); 1339 } 1340 1341 static void 1342 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1343 u_int width, u_int type, int paused, int done) 1344 { 1345 struct ahc_initiator_tinfo *tinfo; 1346 struct tmode_tstate *tstate; 1347 u_int oldwidth; 1348 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1349 1350 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1351 devinfo->target, &tstate); 1352 oldwidth = tinfo->current.width; 1353 1354 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1355 u_int scsirate; 1356 1357 scsirate = tinfo->scsirate; 1358 scsirate &= ~WIDEXFER; 1359 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1360 scsirate |= WIDEXFER; 1361 1362 tinfo->scsirate = scsirate; 1363 1364 if (active) 1365 ahc_outb(ahc, SCSIRATE, scsirate); 1366 1367 tinfo->current.width = width; 1368 } 1369 1370 if (done) { 1371 printf("%s: target %d using %dbit transfers\n", 1372 ahc_name(ahc), devinfo->target, 1373 8 * (0x01 << width)); 1374 } 1375 1376 if ((type & AHC_TRANS_GOAL) != 0) 1377 tinfo->goal.width = width; 1378 if ((type & AHC_TRANS_USER) != 0) 1379 tinfo->user.width = width; 1380 1381 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1382 /*force*/FALSE, paused); 1383 } 1384 1385 static void 1386 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1387 { 1388 struct ahc_initiator_tinfo *tinfo; 1389 struct tmode_tstate *tstate; 1390 1391 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1392 devinfo->target, &tstate); 1393 1394 if (enable) 1395 tstate->tagenable |= devinfo->target_mask; 1396 else 1397 tstate->tagenable &= ~devinfo->target_mask; 1398 } 1399 1400 /* 1401 * Attach all the sub-devices we can find 1402 */ 1403 int 1404 ahc_attach(struct ahc_softc *ahc) 1405 { 1406 TAILQ_INIT(&ahc->sc_q); 1407 1408 ahc->sc_adapter.scsipi_cmd = ahc_action; 1409 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1410 ahc->sc_link.type = BUS_SCSI; 1411 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1412 ahc->sc_link.scsipi_scsi.channel = 0; 1413 ahc->sc_link.scsipi_scsi.max_target = 1414 (ahc->features & AHC_WIDE) ? 15 : 7; 1415 ahc->sc_link.scsipi_scsi.max_lun = 7; 1416 ahc->sc_link.adapter_softc = ahc; 1417 ahc->sc_link.adapter = &ahc->sc_adapter; 1418 ahc->sc_link.openings = 2; 1419 ahc->sc_link.device = &ahc_dev; 1420 1421 if (ahc->features & AHC_TWIN) { 1422 ahc->sc_link_b = ahc->sc_link; 1423 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1424 ahc->sc_link_b.scsipi_scsi.channel = 1; 1425 } 1426 1427 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1428 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1429 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1430 if (ahc->features & AHC_TWIN) 1431 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1432 } else { 1433 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1434 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1435 } 1436 return 1; 1437 } 1438 1439 static void 1440 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1441 { 1442 u_int saved_tcl; 1443 role_t role; 1444 int our_id; 1445 1446 if (ahc_inb(ahc, SSTAT0) & TARGET) 1447 role = ROLE_TARGET; 1448 else 1449 role = ROLE_INITIATOR; 1450 1451 if (role == ROLE_TARGET 1452 && (ahc->features & AHC_MULTI_TID) != 0 1453 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1454 /* We were selected, so pull our id from TARGIDIN */ 1455 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1456 } else if ((ahc->features & AHC_ULTRA2) != 0) 1457 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1458 else 1459 our_id = ahc_inb(ahc, SCSIID) & OID; 1460 1461 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1462 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1463 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1464 role); 1465 } 1466 1467 static void 1468 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1469 u_int lun, char channel, role_t role) 1470 { 1471 devinfo->our_scsiid = our_id; 1472 devinfo->target = target; 1473 devinfo->lun = lun; 1474 devinfo->target_offset = target; 1475 devinfo->channel = channel; 1476 devinfo->role = role; 1477 if (channel == 'B') 1478 devinfo->target_offset += 8; 1479 devinfo->target_mask = (0x01 << devinfo->target_offset); 1480 } 1481 1482 /* 1483 * Catch an interrupt from the adapter 1484 */ 1485 int 1486 ahc_intr(void *arg) 1487 { 1488 struct ahc_softc *ahc; 1489 u_int intstat; 1490 1491 ahc = (struct ahc_softc *)arg; 1492 1493 intstat = ahc_inb(ahc, INTSTAT); 1494 1495 /* 1496 * Any interrupts to process? 1497 */ 1498 if ((intstat & INT_PEND) == 0) { 1499 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1500 #ifdef AHC_DEBUG 1501 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1502 ahc_name(ahc), 1503 ahc_inb(ahc, CCHADDR) | 1504 (ahc_inb(ahc, CCHADDR+1) << 8) 1505 | (ahc_inb(ahc, CCHADDR+2) << 16) 1506 | (ahc_inb(ahc, CCHADDR+3) << 24), 1507 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1508 | (ahc_inb(ahc, HADDR+2) << 16) 1509 | (ahc_inb(ahc, HADDR+3) << 24), 1510 ahc_inb(ahc, SEQADDR0) | 1511 (ahc_inb(ahc, SEQADDR1) << 8)); 1512 #endif 1513 return 1; 1514 } 1515 return 0; 1516 } 1517 1518 #ifdef AHC_DEBUG 1519 if (ahc_debug & AHC_SHOWINTR) { 1520 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1521 } 1522 #endif 1523 1524 if (intstat & CMDCMPLT) { 1525 ahc_outb(ahc, CLRINT, CLRCMDINT); 1526 ahc_run_qoutfifo(ahc); 1527 } 1528 if (intstat & BRKADRINT) { 1529 /* 1530 * We upset the sequencer :-( 1531 * Lookup the error message 1532 */ 1533 int i, error, num_errors; 1534 1535 error = ahc_inb(ahc, ERROR); 1536 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1537 for (i = 0; error != 1 && i < num_errors; i++) 1538 error >>= 1; 1539 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1540 ahc_name(ahc), hard_error[i].errmesg, 1541 ahc_inb(ahc, SEQADDR0) | 1542 (ahc_inb(ahc, SEQADDR1) << 8)); 1543 1544 /* Tell everyone that this HBA is no longer availible */ 1545 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1546 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1547 XS_DRIVER_STUFFUP); 1548 } 1549 if (intstat & SEQINT) 1550 ahc_handle_seqint(ahc, intstat); 1551 1552 if (intstat & SCSIINT) 1553 ahc_handle_scsiint(ahc, intstat); 1554 1555 return 1; 1556 } 1557 1558 static struct tmode_tstate * 1559 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1560 { 1561 struct tmode_tstate *master_tstate; 1562 struct tmode_tstate *tstate; 1563 int i, s; 1564 1565 master_tstate = ahc->enabled_targets[ahc->our_id]; 1566 if (channel == 'B') { 1567 scsi_id += 8; 1568 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1569 } 1570 if (ahc->enabled_targets[scsi_id] != NULL 1571 && ahc->enabled_targets[scsi_id] != master_tstate) 1572 panic("%s: ahc_alloc_tstate - Target already allocated", 1573 ahc_name(ahc)); 1574 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1575 if (tstate == NULL) 1576 return (NULL); 1577 1578 /* 1579 * If we have allocated a master tstate, copy user settings from 1580 * the master tstate (taken from SRAM or the EEPROM) for this 1581 * channel, but reset our current and goal settings to async/narrow 1582 * until an initiator talks to us. 1583 */ 1584 if (master_tstate != NULL) { 1585 bcopy(master_tstate, tstate, sizeof(*tstate)); 1586 tstate->ultraenb = 0; 1587 for (i = 0; i < 16; i++) { 1588 bzero(&tstate->transinfo[i].current, 1589 sizeof(tstate->transinfo[i].current)); 1590 bzero(&tstate->transinfo[i].goal, 1591 sizeof(tstate->transinfo[i].goal)); 1592 } 1593 } else 1594 bzero(tstate, sizeof(*tstate)); 1595 s = splbio(); 1596 ahc->enabled_targets[scsi_id] = tstate; 1597 splx(s); 1598 return (tstate); 1599 } 1600 1601 #if UNUSED 1602 static void 1603 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1604 { 1605 struct tmode_tstate *tstate; 1606 1607 /* Don't clean up the entry for our initiator role */ 1608 if ((ahc->flags & AHC_INITIATORMODE) != 0 1609 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1610 || (channel == 'A' && scsi_id == ahc->our_id)) 1611 && force == FALSE) 1612 return; 1613 1614 if (channel == 'B') 1615 scsi_id += 8; 1616 tstate = ahc->enabled_targets[scsi_id]; 1617 if (tstate != NULL) 1618 free(tstate, M_DEVBUF); 1619 ahc->enabled_targets[scsi_id] = NULL; 1620 } 1621 #endif 1622 1623 static void 1624 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1625 { 1626 struct scb *scb; 1627 struct ahc_devinfo devinfo; 1628 1629 ahc_fetch_devinfo(ahc, &devinfo); 1630 1631 /* 1632 * Clear the upper byte that holds SEQINT status 1633 * codes and clear the SEQINT bit. We will unpause 1634 * the sequencer, if appropriate, after servicing 1635 * the request. 1636 */ 1637 ahc_outb(ahc, CLRINT, CLRSEQINT); 1638 switch (intstat & SEQINT_MASK) { 1639 case NO_MATCH: 1640 { 1641 /* Ensure we don't leave the selection hardware on */ 1642 ahc_outb(ahc, SCSISEQ, 1643 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1644 1645 printf("%s:%c:%d: no active SCB for reconnecting " 1646 "target - issuing BUS DEVICE RESET\n", 1647 ahc_name(ahc), devinfo.channel, devinfo.target); 1648 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1649 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1650 ahc_inb(ahc, SEQ_FLAGS)); 1651 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1652 ahc->msgout_len = 1; 1653 ahc->msgout_index = 0; 1654 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1655 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1656 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1657 break; 1658 } 1659 case UPDATE_TMSG_REQ: 1660 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1661 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1662 (ahc->targ_msg_req >> 8) & 0xFF); 1663 ahc_outb(ahc, HS_MAILBOX, 0); 1664 break; 1665 case SEND_REJECT: 1666 { 1667 u_int rejbyte = ahc_inb(ahc, ACCUM); 1668 printf("%s:%c:%d: Warning - unknown message received from " 1669 "target (0x%x). Rejecting\n", 1670 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1671 break; 1672 } 1673 case NO_IDENT: 1674 { 1675 /* 1676 * The reconnecting target either did not send an identify 1677 * message, or did, but we didn't find and SCB to match and 1678 * before it could respond to our ATN/abort, it hit a dataphase. 1679 * The only safe thing to do is to blow it away with a bus 1680 * reset. 1681 */ 1682 int found; 1683 1684 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1685 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1686 ahc_name(ahc), devinfo.channel, devinfo.target, 1687 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1688 found = ahc_reset_channel(ahc, devinfo.channel, 1689 /*initiate reset*/TRUE); 1690 printf("%s: Issued Channel %c Bus Reset. " 1691 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1692 found); 1693 return; 1694 } 1695 case BAD_PHASE: 1696 { 1697 u_int lastphase; 1698 1699 lastphase = ahc_inb(ahc, LASTPHASE); 1700 if (lastphase == P_BUSFREE) { 1701 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1702 ahc_name(ahc), devinfo.channel, devinfo.target, 1703 ahc_inb(ahc, SCSISIGI)); 1704 restart_sequencer(ahc); 1705 return; 1706 } else { 1707 printf("%s:%c:%d: unknown scsi bus phase %x. " 1708 "Attempting to continue\n", 1709 ahc_name(ahc), devinfo.channel, devinfo.target, 1710 ahc_inb(ahc, SCSISIGI)); 1711 } 1712 break; 1713 } 1714 case BAD_STATUS: 1715 { 1716 u_int scb_index; 1717 struct hardware_scb *hscb; 1718 struct scsipi_xfer *xs; 1719 /* 1720 * The sequencer will notify us when a command 1721 * has an error that would be of interest to 1722 * the kernel. This allows us to leave the sequencer 1723 * running in the common case of command completes 1724 * without error. The sequencer will already have 1725 * dma'd the SCB back up to us, so we can reference 1726 * the in kernel copy directly. 1727 */ 1728 scb_index = ahc_inb(ahc, SCB_TAG); 1729 scb = &ahc->scb_data->scbarray[scb_index]; 1730 1731 /* ahc_print_scb(scb); */ 1732 1733 /* 1734 * Set the default return value to 0 (don't 1735 * send sense). The sense code will change 1736 * this if needed. 1737 */ 1738 ahc_outb(ahc, RETURN_1, 0); 1739 if (!(scb_index < ahc->scb_data->numscbs 1740 && (scb->flags & SCB_ACTIVE) != 0)) { 1741 printf("%s:%c:%d: ahc_intr - referenced scb " 1742 "not valid during seqint 0x%x scb(%d)\n", 1743 ahc_name(ahc), devinfo.channel, 1744 devinfo.target, intstat, scb_index); 1745 goto unpause; 1746 } 1747 1748 hscb = scb->hscb; 1749 xs = scb->xs; 1750 1751 /* Don't want to clobber the original sense code */ 1752 if ((scb->flags & SCB_SENSE) != 0) { 1753 /* 1754 * Clear the SCB_SENSE Flag and have 1755 * the sequencer do a normal command 1756 * complete. 1757 */ 1758 scb->flags &= ~SCB_SENSE; 1759 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1760 break; 1761 } 1762 /* Freeze the queue unit the client sees the error. */ 1763 ahc_freeze_devq(ahc, xs->sc_link); 1764 ahc_freeze_ccb(scb); 1765 xs->status = hscb->status; 1766 switch (hscb->status) { 1767 case SCSI_STATUS_OK: 1768 printf("%s: Interrupted for status of 0???\n", 1769 ahc_name(ahc)); 1770 break; 1771 case SCSI_STATUS_CMD_TERMINATED: 1772 case SCSI_STATUS_CHECK_COND: 1773 #if defined(AHC_DEBUG) 1774 if (ahc_debug & AHC_SHOWSENSE) { 1775 scsi_print_addr(xs->sc_link); 1776 printf("Check Status, resid %d datalen %d\n", 1777 xs->resid, xs->datalen); 1778 } 1779 #endif 1780 1781 if (xs->error == XS_NOERROR && 1782 !(scb->flags & SCB_SENSE)) { 1783 struct ahc_dma_seg *sg; 1784 struct scsipi_sense *sc; 1785 struct ahc_initiator_tinfo *tinfo; 1786 struct tmode_tstate *tstate; 1787 1788 sg = scb->sg_list; 1789 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1790 /* 1791 * Save off the residual if there is one. 1792 */ 1793 if (hscb->residual_SG_count != 0) 1794 ahc_calc_residual(scb); 1795 else 1796 xs->resid = 0; 1797 1798 #ifdef AHC_DEBUG 1799 if (ahc_debug & AHC_SHOWSENSE) { 1800 scsi_print_addr(xs->sc_link); 1801 printf("Sending Sense\n"); 1802 } 1803 #endif 1804 sg->addr = ahc->scb_data->sense_busaddr + 1805 (hscb->tag*sizeof(struct scsipi_sense_data)); 1806 sg->len = sizeof (struct scsipi_sense_data); 1807 1808 sc->opcode = REQUEST_SENSE; 1809 sc->byte2 = SCB_LUN(scb) << 5; 1810 sc->unused[0] = 0; 1811 sc->unused[1] = 0; 1812 sc->length = sg->len; 1813 sc->control = 0; 1814 1815 /* 1816 * Would be nice to preserve DISCENB here, 1817 * but due to the way we page SCBs, we can't. 1818 */ 1819 hscb->control = 0; 1820 1821 /* 1822 * This request sense could be because the 1823 * the device lost power or in some other 1824 * way has lost our transfer negotiations. 1825 * Renegotiate if appropriate. Unit attention 1826 * errors will be reported before any data 1827 * phases occur. 1828 */ 1829 ahc_calc_residual(scb); 1830 #if defined(AHC_DEBUG) 1831 if (ahc_debug & AHC_SHOWSENSE) { 1832 scsi_print_addr(xs->sc_link); 1833 printf("Sense: datalen %d resid %d" 1834 "chan %d id %d targ %d\n", 1835 xs->datalen, xs->resid, 1836 devinfo.channel, devinfo.our_scsiid, 1837 devinfo.target); 1838 } 1839 #endif 1840 if (xs->datalen > 0 && 1841 xs->resid == xs->datalen) { 1842 tinfo = ahc_fetch_transinfo(ahc, 1843 devinfo.channel, 1844 devinfo.our_scsiid, 1845 devinfo.target, 1846 &tstate); 1847 ahc_update_target_msg_request(ahc, 1848 &devinfo, 1849 tinfo, 1850 /*force*/TRUE, 1851 /*paused*/TRUE); 1852 } 1853 hscb->status = 0; 1854 hscb->SG_count = 1; 1855 hscb->SG_pointer = scb->sg_list_phys; 1856 hscb->data = sg->addr; 1857 hscb->datalen = sg->len; 1858 hscb->cmdpointer = hscb->cmdstore_busaddr; 1859 hscb->cmdlen = sizeof(*sc); 1860 scb->sg_count = hscb->SG_count; 1861 ahc_swap_hscb(hscb); 1862 ahc_swap_sg(scb->sg_list); 1863 scb->flags |= SCB_SENSE; 1864 /* 1865 * Ensure the target is busy since this 1866 * will be an untagged request. 1867 */ 1868 ahc_busy_tcl(ahc, scb); 1869 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1870 1871 /* 1872 * Ensure we have enough time to actually 1873 * retrieve the sense. 1874 */ 1875 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1876 callout_reset(&scb->xs->xs_callout, 1877 5 * hz, ahc_timeout, scb); 1878 } 1879 } 1880 break; 1881 case SCSI_STATUS_BUSY: 1882 case SCSI_STATUS_QUEUE_FULL: 1883 /* 1884 * Requeue any transactions that haven't been 1885 * sent yet. 1886 */ 1887 ahc_freeze_devq(ahc, xs->sc_link); 1888 ahc_freeze_ccb(scb); 1889 break; 1890 } 1891 break; 1892 } 1893 case TRACE_POINT: 1894 { 1895 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1896 ahc_inb(ahc, DFCNTRL)); 1897 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1898 ahc_inb(ahc, DFSTATUS)); 1899 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1900 ahc_inb(ahc, SSTAT0), 1901 ahc_inb(ahc, SCB_DATACNT)); 1902 break; 1903 } 1904 case HOST_MSG_LOOP: 1905 { 1906 /* 1907 * The sequencer has encountered a message phase 1908 * that requires host assistance for completion. 1909 * While handling the message phase(s), we will be 1910 * notified by the sequencer after each byte is 1911 * transfered so we can track bus phases. 1912 * 1913 * If this is the first time we've seen a HOST_MSG_LOOP, 1914 * initialize the state of the host message loop. 1915 */ 1916 if (ahc->msg_type == MSG_TYPE_NONE) { 1917 u_int bus_phase; 1918 1919 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1920 if (bus_phase != P_MESGIN 1921 && bus_phase != P_MESGOUT) { 1922 printf("ahc_intr: HOST_MSG_LOOP bad " 1923 "phase 0x%x\n", 1924 bus_phase); 1925 /* 1926 * Probably transitioned to bus free before 1927 * we got here. Just punt the message. 1928 */ 1929 ahc_clear_intstat(ahc); 1930 restart_sequencer(ahc); 1931 } 1932 1933 if (devinfo.role == ROLE_INITIATOR) { 1934 struct scb *scb; 1935 u_int scb_index; 1936 1937 scb_index = ahc_inb(ahc, SCB_TAG); 1938 scb = &ahc->scb_data->scbarray[scb_index]; 1939 1940 if (bus_phase == P_MESGOUT) 1941 ahc_setup_initiator_msgout(ahc, 1942 &devinfo, 1943 scb); 1944 else { 1945 ahc->msg_type = 1946 MSG_TYPE_INITIATOR_MSGIN; 1947 ahc->msgin_index = 0; 1948 } 1949 } else { 1950 if (bus_phase == P_MESGOUT) { 1951 ahc->msg_type = 1952 MSG_TYPE_TARGET_MSGOUT; 1953 ahc->msgin_index = 0; 1954 } else 1955 /* XXX Ever executed??? */ 1956 ahc_setup_target_msgin(ahc, &devinfo); 1957 } 1958 } 1959 1960 /* Pass a NULL path so that handlers generate their own */ 1961 ahc_handle_message_phase(ahc, /*path*/NULL); 1962 break; 1963 } 1964 case PERR_DETECTED: 1965 { 1966 /* 1967 * If we've cleared the parity error interrupt 1968 * but the sequencer still believes that SCSIPERR 1969 * is true, it must be that the parity error is 1970 * for the currently presented byte on the bus, 1971 * and we are not in a phase (data-in) where we will 1972 * eventually ack this byte. Ack the byte and 1973 * throw it away in the hope that the target will 1974 * take us to message out to deliver the appropriate 1975 * error message. 1976 */ 1977 if ((intstat & SCSIINT) == 0 1978 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1979 u_int curphase; 1980 1981 /* 1982 * The hardware will only let you ack bytes 1983 * if the expected phase in SCSISIGO matches 1984 * the current phase. Make sure this is 1985 * currently the case. 1986 */ 1987 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1988 ahc_outb(ahc, LASTPHASE, curphase); 1989 ahc_outb(ahc, SCSISIGO, curphase); 1990 ahc_inb(ahc, SCSIDATL); 1991 } 1992 break; 1993 } 1994 case DATA_OVERRUN: 1995 { 1996 /* 1997 * When the sequencer detects an overrun, it 1998 * places the controller in "BITBUCKET" mode 1999 * and allows the target to complete its transfer. 2000 * Unfortunately, none of the counters get updated 2001 * when the controller is in this mode, so we have 2002 * no way of knowing how large the overrun was. 2003 */ 2004 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2005 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2006 int i; 2007 2008 scb = &ahc->scb_data->scbarray[scbindex]; 2009 for (i = 0; i < num_phases; i++) { 2010 if (lastphase == phase_table[i].phase) 2011 break; 2012 } 2013 scsi_print_addr(scb->xs->sc_link); 2014 printf("data overrun detected %s." 2015 " Tag == 0x%x.\n", 2016 phase_table[i].phasemsg, 2017 scb->hscb->tag); 2018 scsi_print_addr(scb->xs->sc_link); 2019 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2020 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2021 scb->xs->datalen, scb->sg_count); 2022 if (scb->sg_count > 0) { 2023 for (i = 0; i < scb->sg_count; i++) { 2024 printf("sg[%d] - Addr 0x%x : Length %d\n", 2025 i, 2026 le32toh(scb->sg_list[i].addr), 2027 le32toh(scb->sg_list[i].len)); 2028 } 2029 } 2030 /* 2031 * Set this and it will take affect when the 2032 * target does a command complete. 2033 */ 2034 ahc_freeze_devq(ahc, scb->xs->sc_link); 2035 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2036 ahc_freeze_ccb(scb); 2037 break; 2038 } 2039 case TRACEPOINT: 2040 { 2041 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2042 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2043 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2044 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2045 printf("TRACEPOINT: CCHADDR = %x\n", 2046 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2047 | (ahc_inb(ahc, CCHADDR+2) << 16) 2048 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2049 #if 0 2050 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2051 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2052 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2053 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2054 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2055 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2056 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2057 ahc_inb(ahc, CCHADDR) 2058 | (ahc_inb(ahc, CCHADDR+1) << 8) 2059 | (ahc_inb(ahc, CCHADDR+2) << 16) 2060 | (ahc_inb(ahc, CCHADDR+3) << 24), 2061 ahc_inb(ahc, CCHCNT) 2062 | (ahc_inb(ahc, CCHCNT+1) << 8) 2063 | (ahc_inb(ahc, CCHCNT+2) << 16), 2064 ahc_inb(ahc, SCBPTR)); 2065 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2066 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2067 #if DDB > 0 2068 cpu_Debugger(); 2069 #endif 2070 #endif 2071 break; 2072 } 2073 #if NOT_YET 2074 /* XXX Fill these in later */ 2075 case MESG_BUFFER_BUSY: 2076 break; 2077 case MSGIN_PHASEMIS: 2078 break; 2079 #endif 2080 default: 2081 printf("ahc_intr: seqint, " 2082 "intstat == 0x%x, scsisigi = 0x%x\n", 2083 intstat, ahc_inb(ahc, SCSISIGI)); 2084 break; 2085 } 2086 2087 unpause: 2088 /* 2089 * The sequencer is paused immediately on 2090 * a SEQINT, so we should restart it when 2091 * we're done. 2092 */ 2093 unpause_sequencer(ahc); 2094 } 2095 2096 static void 2097 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2098 { 2099 u_int scb_index; 2100 u_int status; 2101 struct scb *scb; 2102 char cur_channel; 2103 char intr_channel; 2104 2105 if ((ahc->features & AHC_TWIN) != 0 2106 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2107 cur_channel = 'B'; 2108 else 2109 cur_channel = 'A'; 2110 intr_channel = cur_channel; 2111 2112 status = ahc_inb(ahc, SSTAT1); 2113 if (status == 0) { 2114 if ((ahc->features & AHC_TWIN) != 0) { 2115 /* Try the other channel */ 2116 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2117 status = ahc_inb(ahc, SSTAT1); 2118 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2119 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2120 } 2121 if (status == 0) { 2122 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2123 return; 2124 } 2125 } 2126 2127 scb_index = ahc_inb(ahc, SCB_TAG); 2128 if (scb_index < ahc->scb_data->numscbs) { 2129 scb = &ahc->scb_data->scbarray[scb_index]; 2130 if ((scb->flags & SCB_ACTIVE) == 0 2131 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2132 scb = NULL; 2133 } else 2134 scb = NULL; 2135 2136 if ((status & SCSIRSTI) != 0) { 2137 printf("%s: Someone reset channel %c\n", 2138 ahc_name(ahc), intr_channel); 2139 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2140 } else if ((status & SCSIPERR) != 0) { 2141 /* 2142 * Determine the bus phase and queue an appropriate message. 2143 * SCSIPERR is latched true as soon as a parity error 2144 * occurs. If the sequencer acked the transfer that 2145 * caused the parity error and the currently presented 2146 * transfer on the bus has correct parity, SCSIPERR will 2147 * be cleared by CLRSCSIPERR. Use this to determine if 2148 * we should look at the last phase the sequencer recorded, 2149 * or the current phase presented on the bus. 2150 */ 2151 u_int mesg_out; 2152 u_int curphase; 2153 u_int errorphase; 2154 u_int lastphase; 2155 int i; 2156 2157 lastphase = ahc_inb(ahc, LASTPHASE); 2158 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2159 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2160 /* 2161 * For all phases save DATA, the sequencer won't 2162 * automatically ack a byte that has a parity error 2163 * in it. So the only way that the current phase 2164 * could be 'data-in' is if the parity error is for 2165 * an already acked byte in the data phase. During 2166 * synchronous data-in transfers, we may actually 2167 * ack bytes before latching the current phase in 2168 * LASTPHASE, leading to the discrepancy between 2169 * curphase and lastphase. 2170 */ 2171 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2172 || curphase == P_DATAIN) 2173 errorphase = curphase; 2174 else 2175 errorphase = lastphase; 2176 2177 for (i = 0; i < num_phases; i++) { 2178 if (errorphase == phase_table[i].phase) 2179 break; 2180 } 2181 mesg_out = phase_table[i].mesg_out; 2182 if (scb != NULL) 2183 scsi_print_addr(scb->xs->sc_link); 2184 else 2185 printf("%s:%c:%d: ", ahc_name(ahc), 2186 intr_channel, 2187 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2188 2189 printf("parity error detected %s. " 2190 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2191 phase_table[i].phasemsg, 2192 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2193 ahc_inb(ahc, SCSIRATE)); 2194 2195 /* 2196 * We've set the hardware to assert ATN if we 2197 * get a parity error on "in" phases, so all we 2198 * need to do is stuff the message buffer with 2199 * the appropriate message. "In" phases have set 2200 * mesg_out to something other than MSG_NOP. 2201 */ 2202 if (mesg_out != MSG_NOOP) { 2203 if (ahc->msg_type != MSG_TYPE_NONE) 2204 ahc->send_msg_perror = TRUE; 2205 else 2206 ahc_outb(ahc, MSG_OUT, mesg_out); 2207 } 2208 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2209 unpause_sequencer(ahc); 2210 } else if ((status & BUSFREE) != 0 2211 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2212 /* 2213 * First look at what phase we were last in. 2214 * If its message out, chances are pretty good 2215 * that the busfree was in response to one of 2216 * our abort requests. 2217 */ 2218 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2219 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2220 u_int target = TCL_TARGET(saved_tcl); 2221 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2222 char channel = TCL_CHANNEL(ahc, saved_tcl); 2223 int printerror = 1; 2224 2225 ahc_outb(ahc, SCSISEQ, 2226 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2227 if (lastphase == P_MESGOUT) { 2228 u_int message; 2229 u_int tag; 2230 2231 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2232 tag = SCB_LIST_NULL; 2233 switch (message) { 2234 case MSG_ABORT_TAG: 2235 tag = scb->hscb->tag; 2236 /* FALLTRHOUGH */ 2237 case MSG_ABORT: 2238 scsi_print_addr(scb->xs->sc_link); 2239 printf("SCB %x - Abort %s Completed.\n", 2240 scb->hscb->tag, tag == SCB_LIST_NULL ? 2241 "" : "Tag"); 2242 ahc_abort_scbs(ahc, target, channel, 2243 TCL_LUN(saved_tcl), tag, 2244 ROLE_INITIATOR, 2245 XS_DRIVER_STUFFUP); 2246 printerror = 0; 2247 break; 2248 case MSG_BUS_DEV_RESET: 2249 { 2250 struct ahc_devinfo devinfo; 2251 2252 if (scb != NULL && 2253 (scb->xs->xs_control & XS_CTL_RESET) 2254 && ahc_match_scb(scb, target, channel, 2255 TCL_LUN(saved_tcl), 2256 SCB_LIST_NULL, 2257 ROLE_INITIATOR)) { 2258 ahcsetccbstatus(scb->xs, XS_NOERROR); 2259 } 2260 ahc_compile_devinfo(&devinfo, 2261 initiator_role_id, 2262 target, 2263 TCL_LUN(saved_tcl), 2264 channel, 2265 ROLE_INITIATOR); 2266 ahc_handle_devreset(ahc, &devinfo, 2267 XS_RESET, 2268 "Bus Device Reset", 2269 /*verbose_level*/0); 2270 printerror = 0; 2271 break; 2272 } 2273 default: 2274 break; 2275 } 2276 } 2277 if (printerror != 0) { 2278 int i; 2279 2280 if (scb != NULL) { 2281 u_int tag; 2282 2283 if ((scb->hscb->control & TAG_ENB) != 0) 2284 tag = scb->hscb->tag; 2285 else 2286 tag = SCB_LIST_NULL; 2287 ahc_abort_scbs(ahc, target, channel, 2288 SCB_LUN(scb), tag, 2289 ROLE_INITIATOR, 2290 XS_DRIVER_STUFFUP); 2291 scsi_print_addr(scb->xs->sc_link); 2292 } else { 2293 /* 2294 * We had not fully identified this connection, 2295 * so we cannot abort anything. 2296 */ 2297 printf("%s: ", ahc_name(ahc)); 2298 } 2299 for (i = 0; i < num_phases; i++) { 2300 if (lastphase == phase_table[i].phase) 2301 break; 2302 } 2303 printf("Unexpected busfree %s\n" 2304 "SEQADDR == 0x%x\n", 2305 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2306 | (ahc_inb(ahc, SEQADDR1) << 8)); 2307 } 2308 ahc_clear_msg_state(ahc); 2309 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2310 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2311 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2312 restart_sequencer(ahc); 2313 } else if ((status & SELTO) != 0) { 2314 u_int scbptr; 2315 2316 scbptr = ahc_inb(ahc, WAITING_SCBH); 2317 ahc_outb(ahc, SCBPTR, scbptr); 2318 scb_index = ahc_inb(ahc, SCB_TAG); 2319 2320 if (scb_index < ahc->scb_data->numscbs) { 2321 scb = &ahc->scb_data->scbarray[scb_index]; 2322 if ((scb->flags & SCB_ACTIVE) == 0) 2323 scb = NULL; 2324 } else 2325 scb = NULL; 2326 2327 if (scb == NULL) { 2328 printf("%s: ahc_intr - referenced scb not " 2329 "valid during SELTO scb(%d, %d)\n", 2330 ahc_name(ahc), scbptr, scb_index); 2331 } else { 2332 u_int tag; 2333 2334 tag = SCB_LIST_NULL; 2335 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2336 tag = scb->hscb->tag; 2337 2338 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2339 SCB_LUN(scb), tag, 2340 ROLE_INITIATOR, XS_SELTIMEOUT); 2341 } 2342 /* Stop the selection */ 2343 ahc_outb(ahc, SCSISEQ, 0); 2344 2345 /* No more pending messages */ 2346 ahc_clear_msg_state(ahc); 2347 2348 /* 2349 * Although the driver does not care about the 2350 * 'Selection in Progress' status bit, the busy 2351 * LED does. SELINGO is only cleared by a sucessful 2352 * selection, so we must manually clear it to ensure 2353 * the LED turns off just incase no future successful 2354 * selections occur (e.g. no devices on the bus). 2355 */ 2356 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2357 2358 /* Clear interrupt state */ 2359 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2360 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2361 restart_sequencer(ahc); 2362 } else { 2363 scsi_print_addr(scb->xs->sc_link); 2364 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2365 ahc_outb(ahc, CLRSINT1, status); 2366 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2367 unpause_sequencer(ahc); 2368 } 2369 } 2370 2371 static void 2372 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2373 { 2374 /* 2375 * We need to initiate transfer negotiations. 2376 * If our current and goal settings are identical, 2377 * we want to renegotiate due to a check condition. 2378 */ 2379 struct ahc_initiator_tinfo *tinfo; 2380 struct tmode_tstate *tstate; 2381 int dowide; 2382 int dosync; 2383 2384 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2385 devinfo->target, &tstate); 2386 dowide = tinfo->current.width != tinfo->goal.width; 2387 dosync = tinfo->current.period != tinfo->goal.period; 2388 2389 if (!dowide && !dosync) { 2390 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2391 dosync = tinfo->goal.period != 0; 2392 } 2393 2394 if (dowide) { 2395 ahc_construct_wdtr(ahc, tinfo->goal.width); 2396 } else if (dosync) { 2397 struct ahc_syncrate *rate; 2398 u_int period; 2399 u_int offset; 2400 2401 period = tinfo->goal.period; 2402 rate = ahc_devlimited_syncrate(ahc, &period); 2403 offset = tinfo->goal.offset; 2404 ahc_validate_offset(ahc, rate, &offset, 2405 tinfo->current.width); 2406 ahc_construct_sdtr(ahc, period, offset); 2407 } else { 2408 panic("ahc_intr: AWAITING_MSG for negotiation, " 2409 "but no negotiation needed\n"); 2410 } 2411 } 2412 2413 static void 2414 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2415 struct scb *scb) 2416 { 2417 /* 2418 * To facilitate adding multiple messages together, 2419 * each routine should increment the index and len 2420 * variables instead of setting them explicitly. 2421 */ 2422 ahc->msgout_index = 0; 2423 ahc->msgout_len = 0; 2424 2425 if ((scb->flags & SCB_DEVICE_RESET) == 0 2426 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2427 u_int identify_msg; 2428 2429 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2430 if ((scb->hscb->control & DISCENB) != 0) 2431 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2432 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2433 ahc->msgout_len++; 2434 2435 if ((scb->hscb->control & TAG_ENB) != 0) { 2436 /* XXX fvdl FreeBSD has tag action passed down */ 2437 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2438 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2439 ahc->msgout_len += 2; 2440 } 2441 } 2442 2443 if (scb->flags & SCB_DEVICE_RESET) { 2444 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2445 ahc->msgout_len++; 2446 scsi_print_addr(scb->xs->sc_link); 2447 printf("Bus Device Reset Message Sent\n"); 2448 } else if (scb->flags & SCB_ABORT) { 2449 if ((scb->hscb->control & TAG_ENB) != 0) 2450 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2451 else 2452 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2453 ahc->msgout_len++; 2454 scsi_print_addr(scb->xs->sc_link); 2455 printf("Abort Message Sent\n"); 2456 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2457 ahc_build_transfer_msg(ahc, devinfo); 2458 } else { 2459 printf("ahc_intr: AWAITING_MSG for an SCB that " 2460 "does not have a waiting message"); 2461 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2462 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2463 ahc_inb(ahc, MSG_OUT), scb->flags); 2464 } 2465 2466 /* 2467 * Clear the MK_MESSAGE flag from the SCB so we aren't 2468 * asked to send this message again. 2469 */ 2470 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2471 ahc->msgout_index = 0; 2472 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2473 } 2474 2475 static void 2476 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2477 { 2478 /* 2479 * To facilitate adding multiple messages together, 2480 * each routine should increment the index and len 2481 * variables instead of setting them explicitly. 2482 */ 2483 ahc->msgout_index = 0; 2484 ahc->msgout_len = 0; 2485 2486 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2487 ahc_build_transfer_msg(ahc, devinfo); 2488 else 2489 panic("ahc_intr: AWAITING target message with no message"); 2490 2491 ahc->msgout_index = 0; 2492 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2493 } 2494 2495 static int 2496 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2497 { 2498 /* 2499 * What we care about here is if we had an 2500 * outstanding SDTR or WDTR message for this 2501 * target. If we did, this is a signal that 2502 * the target is refusing negotiation. 2503 */ 2504 struct scb *scb; 2505 u_int scb_index; 2506 u_int last_msg; 2507 int response = 0; 2508 2509 scb_index = ahc_inb(ahc, SCB_TAG); 2510 scb = &ahc->scb_data->scbarray[scb_index]; 2511 2512 /* Might be necessary */ 2513 last_msg = ahc_inb(ahc, LAST_MSG); 2514 2515 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2516 struct ahc_initiator_tinfo *tinfo; 2517 struct tmode_tstate *tstate; 2518 2519 #ifdef AHC_DEBUG_NEG 2520 /* note 8bit xfers */ 2521 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2522 "8bit transfers\n", ahc_name(ahc), 2523 devinfo->channel, devinfo->target); 2524 #endif 2525 ahc_set_width(ahc, devinfo, 2526 MSG_EXT_WDTR_BUS_8_BIT, 2527 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2528 /*paused*/TRUE, /*done*/TRUE); 2529 /* 2530 * No need to clear the sync rate. If the target 2531 * did not accept the command, our syncrate is 2532 * unaffected. If the target started the negotiation, 2533 * but rejected our response, we already cleared the 2534 * sync rate before sending our WDTR. 2535 */ 2536 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2537 devinfo->our_scsiid, 2538 devinfo->target, &tstate); 2539 if (tinfo->goal.period) { 2540 u_int period; 2541 2542 /* Start the sync negotiation */ 2543 period = tinfo->goal.period; 2544 ahc_devlimited_syncrate(ahc, &period); 2545 ahc->msgout_index = 0; 2546 ahc->msgout_len = 0; 2547 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2548 ahc->msgout_index = 0; 2549 response = 1; 2550 } 2551 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2552 /* note asynch xfers and clear flag */ 2553 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2554 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2555 /*paused*/TRUE, /*done*/TRUE); 2556 #ifdef AHC_DEBUG_NEG 2557 printf("%s:%c:%d: refuses synchronous negotiation. " 2558 "Using asynchronous transfers\n", 2559 ahc_name(ahc), 2560 devinfo->channel, devinfo->target); 2561 #endif 2562 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2563 printf("%s:%c:%d: refuses tagged commands. Performing " 2564 "non-tagged I/O\n", ahc_name(ahc), 2565 devinfo->channel, devinfo->target); 2566 2567 ahc_set_tags(ahc, devinfo, FALSE); 2568 2569 /* 2570 * Resend the identify for this CCB as the target 2571 * may believe that the selection is invalid otherwise. 2572 */ 2573 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2574 & ~MSG_SIMPLE_Q_TAG); 2575 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2576 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2577 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2578 2579 /* 2580 * Requeue all tagged commands for this target 2581 * currently in our posession so they can be 2582 * converted to untagged commands. 2583 */ 2584 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2585 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2586 ROLE_INITIATOR, SCB_REQUEUE, 2587 SEARCH_COMPLETE); 2588 } else { 2589 /* 2590 * Otherwise, we ignore it. 2591 */ 2592 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2593 ahc_name(ahc), devinfo->channel, devinfo->target, 2594 last_msg); 2595 } 2596 return (response); 2597 } 2598 2599 static void 2600 ahc_clear_msg_state(struct ahc_softc *ahc) 2601 { 2602 ahc->msgout_len = 0; 2603 ahc->msgin_index = 0; 2604 ahc->msg_type = MSG_TYPE_NONE; 2605 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2606 } 2607 2608 static void 2609 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2610 { 2611 struct ahc_devinfo devinfo; 2612 u_int bus_phase; 2613 int end_session; 2614 2615 ahc_fetch_devinfo(ahc, &devinfo); 2616 end_session = FALSE; 2617 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2618 2619 reswitch: 2620 switch (ahc->msg_type) { 2621 case MSG_TYPE_INITIATOR_MSGOUT: 2622 { 2623 int lastbyte; 2624 int phasemis; 2625 int msgdone; 2626 2627 if (ahc->msgout_len == 0) 2628 panic("REQINIT interrupt with no active message"); 2629 2630 phasemis = bus_phase != P_MESGOUT; 2631 if (phasemis) { 2632 if (bus_phase == P_MESGIN) { 2633 /* 2634 * Change gears and see if 2635 * this messages is of interest to 2636 * us or should be passed back to 2637 * the sequencer. 2638 */ 2639 ahc_outb(ahc, CLRSINT1, CLRATNO); 2640 ahc->send_msg_perror = FALSE; 2641 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2642 ahc->msgin_index = 0; 2643 goto reswitch; 2644 } 2645 end_session = TRUE; 2646 break; 2647 } 2648 2649 if (ahc->send_msg_perror) { 2650 ahc_outb(ahc, CLRSINT1, CLRATNO); 2651 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2652 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2653 break; 2654 } 2655 2656 msgdone = ahc->msgout_index == ahc->msgout_len; 2657 if (msgdone) { 2658 /* 2659 * The target has requested a retry. 2660 * Re-assert ATN, reset our message index to 2661 * 0, and try again. 2662 */ 2663 ahc->msgout_index = 0; 2664 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2665 } 2666 2667 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2668 if (lastbyte) { 2669 /* Last byte is signified by dropping ATN */ 2670 ahc_outb(ahc, CLRSINT1, CLRATNO); 2671 } 2672 2673 /* 2674 * Clear our interrupt status and present 2675 * the next byte on the bus. 2676 */ 2677 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2678 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2679 break; 2680 } 2681 case MSG_TYPE_INITIATOR_MSGIN: 2682 { 2683 int phasemis; 2684 int message_done; 2685 2686 phasemis = bus_phase != P_MESGIN; 2687 2688 if (phasemis) { 2689 ahc->msgin_index = 0; 2690 if (bus_phase == P_MESGOUT 2691 && (ahc->send_msg_perror == TRUE 2692 || (ahc->msgout_len != 0 2693 && ahc->msgout_index == 0))) { 2694 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2695 goto reswitch; 2696 } 2697 end_session = TRUE; 2698 break; 2699 } 2700 2701 /* Pull the byte in without acking it */ 2702 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2703 2704 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2705 2706 if (message_done) { 2707 /* 2708 * Clear our incoming message buffer in case there 2709 * is another message following this one. 2710 */ 2711 ahc->msgin_index = 0; 2712 2713 /* 2714 * If this message illicited a response, 2715 * assert ATN so the target takes us to the 2716 * message out phase. 2717 */ 2718 if (ahc->msgout_len != 0) 2719 ahc_outb(ahc, SCSISIGO, 2720 ahc_inb(ahc, SCSISIGO) | ATNO); 2721 } else 2722 ahc->msgin_index++; 2723 2724 /* Ack the byte */ 2725 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2726 ahc_inb(ahc, SCSIDATL); 2727 break; 2728 } 2729 case MSG_TYPE_TARGET_MSGIN: 2730 { 2731 int msgdone; 2732 int msgout_request; 2733 2734 if (ahc->msgout_len == 0) 2735 panic("Target MSGIN with no active message"); 2736 2737 /* 2738 * If we interrupted a mesgout session, the initiator 2739 * will not know this until our first REQ. So, we 2740 * only honor mesgout requests after we've sent our 2741 * first byte. 2742 */ 2743 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2744 && ahc->msgout_index > 0) 2745 msgout_request = TRUE; 2746 else 2747 msgout_request = FALSE; 2748 2749 if (msgout_request) { 2750 2751 /* 2752 * Change gears and see if 2753 * this messages is of interest to 2754 * us or should be passed back to 2755 * the sequencer. 2756 */ 2757 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2758 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2759 ahc->msgin_index = 0; 2760 /* Dummy read to REQ for first byte */ 2761 ahc_inb(ahc, SCSIDATL); 2762 ahc_outb(ahc, SXFRCTL0, 2763 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2764 break; 2765 } 2766 2767 msgdone = ahc->msgout_index == ahc->msgout_len; 2768 if (msgdone) { 2769 ahc_outb(ahc, SXFRCTL0, 2770 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2771 end_session = TRUE; 2772 break; 2773 } 2774 2775 /* 2776 * Present the next byte on the bus. 2777 */ 2778 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2779 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2780 break; 2781 } 2782 case MSG_TYPE_TARGET_MSGOUT: 2783 { 2784 int lastbyte; 2785 int msgdone; 2786 2787 /* 2788 * The initiator signals that this is 2789 * the last byte by dropping ATN. 2790 */ 2791 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2792 2793 /* 2794 * Read the latched byte, but turn off SPIOEN first 2795 * so that we don't inadvertantly cause a REQ for the 2796 * next byte. 2797 */ 2798 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2799 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2800 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2801 if (msgdone == MSGLOOP_TERMINATED) { 2802 /* 2803 * The message is *really* done in that it caused 2804 * us to go to bus free. The sequencer has already 2805 * been reset at this point, so pull the ejection 2806 * handle. 2807 */ 2808 return; 2809 } 2810 2811 ahc->msgin_index++; 2812 2813 /* 2814 * XXX Read spec about initiator dropping ATN too soon 2815 * and use msgdone to detect it. 2816 */ 2817 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2818 ahc->msgin_index = 0; 2819 2820 /* 2821 * If this message illicited a response, transition 2822 * to the Message in phase and send it. 2823 */ 2824 if (ahc->msgout_len != 0) { 2825 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2826 ahc_outb(ahc, SXFRCTL0, 2827 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2828 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2829 ahc->msgin_index = 0; 2830 break; 2831 } 2832 } 2833 2834 if (lastbyte) 2835 end_session = TRUE; 2836 else { 2837 /* Ask for the next byte. */ 2838 ahc_outb(ahc, SXFRCTL0, 2839 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2840 } 2841 2842 break; 2843 } 2844 default: 2845 panic("Unknown REQINIT message type"); 2846 } 2847 2848 if (end_session) { 2849 ahc_clear_msg_state(ahc); 2850 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2851 } else 2852 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2853 } 2854 2855 /* 2856 * See if we sent a particular extended message to the target. 2857 * If "full" is true, the target saw the full message. 2858 * If "full" is false, the target saw at least the first 2859 * byte of the message. 2860 */ 2861 static int 2862 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2863 { 2864 int found; 2865 int index; 2866 2867 found = FALSE; 2868 index = 0; 2869 2870 while (index < ahc->msgout_len) { 2871 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2872 2873 /* Found a candidate */ 2874 if (ahc->msgout_buf[index+2] == msgtype) { 2875 u_int end_index; 2876 2877 end_index = index + 1 2878 + ahc->msgout_buf[index + 1]; 2879 if (full) { 2880 if (ahc->msgout_index > end_index) 2881 found = TRUE; 2882 } else if (ahc->msgout_index > index) 2883 found = TRUE; 2884 } 2885 break; 2886 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2887 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2888 2889 /* Skip tag type and tag id or residue param*/ 2890 index += 2; 2891 } else { 2892 /* Single byte message */ 2893 index++; 2894 } 2895 } 2896 return (found); 2897 } 2898 2899 static int 2900 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2901 struct ahc_devinfo *devinfo) 2902 { 2903 struct ahc_initiator_tinfo *tinfo; 2904 struct tmode_tstate *tstate; 2905 int reject; 2906 int done; 2907 int response; 2908 u_int targ_scsirate; 2909 2910 done = MSGLOOP_IN_PROG; 2911 response = FALSE; 2912 reject = FALSE; 2913 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2914 devinfo->target, &tstate); 2915 targ_scsirate = tinfo->scsirate; 2916 2917 /* 2918 * Parse as much of the message as is availible, 2919 * rejecting it if we don't support it. When 2920 * the entire message is availible and has been 2921 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2922 * that we have parsed an entire message. 2923 * 2924 * In the case of extended messages, we accept the length 2925 * byte outright and perform more checking once we know the 2926 * extended message type. 2927 */ 2928 switch (ahc->msgin_buf[0]) { 2929 case MSG_MESSAGE_REJECT: 2930 response = ahc_handle_msg_reject(ahc, devinfo); 2931 /* FALLTHROUGH */ 2932 case MSG_NOOP: 2933 done = MSGLOOP_MSGCOMPLETE; 2934 break; 2935 case MSG_IGN_WIDE_RESIDUE: 2936 { 2937 /* Wait for the whole message */ 2938 if (ahc->msgin_index >= 1) { 2939 if (ahc->msgin_buf[1] != 1 2940 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2941 reject = TRUE; 2942 done = MSGLOOP_MSGCOMPLETE; 2943 } else 2944 ahc_handle_ign_wide_residue(ahc, devinfo); 2945 } 2946 break; 2947 } 2948 case MSG_EXTENDED: 2949 { 2950 /* Wait for enough of the message to begin validation */ 2951 if (ahc->msgin_index < 2) 2952 break; 2953 switch (ahc->msgin_buf[2]) { 2954 case MSG_EXT_SDTR: 2955 { 2956 struct ahc_syncrate *syncrate; 2957 u_int period; 2958 u_int offset; 2959 u_int saved_offset; 2960 2961 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2962 reject = TRUE; 2963 break; 2964 } 2965 2966 /* 2967 * Wait until we have both args before validating 2968 * and acting on this message. 2969 * 2970 * Add one to MSG_EXT_SDTR_LEN to account for 2971 * the extended message preamble. 2972 */ 2973 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2974 break; 2975 2976 period = ahc->msgin_buf[3]; 2977 saved_offset = offset = ahc->msgin_buf[4]; 2978 syncrate = ahc_devlimited_syncrate(ahc, &period); 2979 ahc_validate_offset(ahc, syncrate, &offset, 2980 targ_scsirate & WIDEXFER); 2981 ahc_set_syncrate(ahc, devinfo, 2982 syncrate, period, offset, 2983 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2984 /*paused*/TRUE, /*done*/TRUE); 2985 2986 /* 2987 * See if we initiated Sync Negotiation 2988 * and didn't have to fall down to async 2989 * transfers. 2990 */ 2991 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2992 /* We started it */ 2993 if (saved_offset != offset) { 2994 /* Went too low - force async */ 2995 reject = TRUE; 2996 } 2997 } else { 2998 /* 2999 * Send our own SDTR in reply 3000 */ 3001 ahc->msgout_index = 0; 3002 ahc->msgout_len = 0; 3003 ahc_construct_sdtr(ahc, period, offset); 3004 ahc->msgout_index = 0; 3005 response = TRUE; 3006 } 3007 done = MSGLOOP_MSGCOMPLETE; 3008 break; 3009 } 3010 case MSG_EXT_WDTR: 3011 { 3012 u_int bus_width; 3013 u_int sending_reply; 3014 3015 sending_reply = FALSE; 3016 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3017 reject = TRUE; 3018 break; 3019 } 3020 3021 /* 3022 * Wait until we have our arg before validating 3023 * and acting on this message. 3024 * 3025 * Add one to MSG_EXT_WDTR_LEN to account for 3026 * the extended message preamble. 3027 */ 3028 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3029 break; 3030 3031 bus_width = ahc->msgin_buf[3]; 3032 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3033 /* 3034 * Don't send a WDTR back to the 3035 * target, since we asked first. 3036 */ 3037 switch (bus_width){ 3038 default: 3039 /* 3040 * How can we do anything greater 3041 * than 16bit transfers on a 16bit 3042 * bus? 3043 */ 3044 reject = TRUE; 3045 printf("%s: target %d requested %dBit " 3046 "transfers. Rejecting...\n", 3047 ahc_name(ahc), devinfo->target, 3048 8 * (0x01 << bus_width)); 3049 /* FALLTHROUGH */ 3050 case MSG_EXT_WDTR_BUS_8_BIT: 3051 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3052 break; 3053 case MSG_EXT_WDTR_BUS_16_BIT: 3054 break; 3055 } 3056 } else { 3057 /* 3058 * Send our own WDTR in reply 3059 */ 3060 switch (bus_width) { 3061 default: 3062 if (ahc->features & AHC_WIDE) { 3063 /* Respond Wide */ 3064 bus_width = 3065 MSG_EXT_WDTR_BUS_16_BIT; 3066 break; 3067 } 3068 /* FALLTHROUGH */ 3069 case MSG_EXT_WDTR_BUS_8_BIT: 3070 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3071 break; 3072 } 3073 ahc->msgout_index = 0; 3074 ahc->msgout_len = 0; 3075 ahc_construct_wdtr(ahc, bus_width); 3076 ahc->msgout_index = 0; 3077 response = TRUE; 3078 sending_reply = TRUE; 3079 } 3080 ahc_set_width(ahc, devinfo, bus_width, 3081 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3082 /*paused*/TRUE, /*done*/TRUE); 3083 3084 /* After a wide message, we are async */ 3085 ahc_set_syncrate(ahc, devinfo, 3086 /*syncrate*/NULL, /*period*/0, 3087 /*offset*/0, AHC_TRANS_ACTIVE, 3088 /*paused*/TRUE, /*done*/FALSE); 3089 if (sending_reply == FALSE && reject == FALSE) { 3090 3091 if (tinfo->goal.period) { 3092 struct ahc_syncrate *rate; 3093 u_int period; 3094 u_int offset; 3095 3096 /* Start the sync negotiation */ 3097 period = tinfo->goal.period; 3098 rate = ahc_devlimited_syncrate(ahc, 3099 &period); 3100 offset = tinfo->goal.offset; 3101 ahc_validate_offset(ahc, rate, &offset, 3102 tinfo->current.width); 3103 ahc->msgout_index = 0; 3104 ahc->msgout_len = 0; 3105 ahc_construct_sdtr(ahc, period, offset); 3106 ahc->msgout_index = 0; 3107 response = TRUE; 3108 } 3109 } 3110 done = MSGLOOP_MSGCOMPLETE; 3111 break; 3112 } 3113 default: 3114 /* Unknown extended message. Reject it. */ 3115 reject = TRUE; 3116 break; 3117 } 3118 break; 3119 } 3120 case MSG_BUS_DEV_RESET: 3121 ahc_handle_devreset(ahc, devinfo, 3122 XS_RESET, "Bus Device Reset Received", 3123 /*verbose_level*/0); 3124 restart_sequencer(ahc); 3125 done = MSGLOOP_TERMINATED; 3126 break; 3127 case MSG_ABORT_TAG: 3128 case MSG_ABORT: 3129 case MSG_CLEAR_QUEUE: 3130 /* Target mode messages */ 3131 if (devinfo->role != ROLE_TARGET) { 3132 reject = TRUE; 3133 break; 3134 } 3135 #if AHC_TARGET_MODE 3136 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3137 devinfo->lun, 3138 ahc->msgin_buf[0] == MSG_ABORT_TAG 3139 ? SCB_LIST_NULL 3140 : ahc_inb(ahc, INITIATOR_TAG), 3141 ROLE_TARGET, XS_DRIVER_STUFFUP); 3142 3143 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3144 if (tstate != NULL) { 3145 struct tmode_lstate* lstate; 3146 3147 lstate = tstate->enabled_luns[devinfo->lun]; 3148 if (lstate != NULL) { 3149 ahc_queue_lstate_event(ahc, lstate, 3150 devinfo->our_scsiid, 3151 ahc->msgin_buf[0], 3152 /*arg*/0); 3153 ahc_send_lstate_events(ahc, lstate); 3154 } 3155 } 3156 done = MSGLOOP_MSGCOMPLETE; 3157 #else 3158 panic("ahc: got target mode message"); 3159 #endif 3160 break; 3161 case MSG_TERM_IO_PROC: 3162 default: 3163 reject = TRUE; 3164 break; 3165 } 3166 3167 if (reject) { 3168 /* 3169 * Setup to reject the message. 3170 */ 3171 ahc->msgout_index = 0; 3172 ahc->msgout_len = 1; 3173 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3174 done = MSGLOOP_MSGCOMPLETE; 3175 response = TRUE; 3176 } 3177 3178 if (done != MSGLOOP_IN_PROG && !response) 3179 /* Clear the outgoing message buffer */ 3180 ahc->msgout_len = 0; 3181 3182 return (done); 3183 } 3184 3185 static void 3186 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3187 { 3188 u_int scb_index; 3189 struct scb *scb; 3190 3191 scb_index = ahc_inb(ahc, SCB_TAG); 3192 scb = &ahc->scb_data->scbarray[scb_index]; 3193 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3194 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3195 /* 3196 * Ignore the message if we haven't 3197 * seen an appropriate data phase yet. 3198 */ 3199 } else { 3200 /* 3201 * If the residual occurred on the last 3202 * transfer and the transfer request was 3203 * expected to end on an odd count, do 3204 * nothing. Otherwise, subtract a byte 3205 * and update the residual count accordingly. 3206 */ 3207 u_int resid_sgcnt; 3208 3209 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3210 if (resid_sgcnt == 0 3211 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3212 /* 3213 * If the residual occurred on the last 3214 * transfer and the transfer request was 3215 * expected to end on an odd count, do 3216 * nothing. 3217 */ 3218 } else { 3219 u_int data_cnt; 3220 u_int32_t data_addr; 3221 u_int sg_index; 3222 3223 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3224 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3225 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3226 3227 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3228 | (ahc_inb(ahc, SHADDR + 2) << 16) 3229 | (ahc_inb(ahc, SHADDR + 1) << 8) 3230 | (ahc_inb(ahc, SHADDR)); 3231 3232 data_cnt += 1; 3233 data_addr -= 1; 3234 3235 sg_index = scb->sg_count - resid_sgcnt; 3236 3237 if (sg_index != 0 3238 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3239 u_int32_t sg_addr; 3240 3241 sg_index--; 3242 data_cnt = 1; 3243 data_addr = le32toh(scb->sg_list[sg_index].addr) 3244 + le32toh(scb->sg_list[sg_index].len) 3245 - 1; 3246 3247 /* 3248 * The physical address base points to the 3249 * second entry as it is always used for 3250 * calculating the "next S/G pointer". 3251 */ 3252 sg_addr = scb->sg_list_phys 3253 + (sg_index* sizeof(*scb->sg_list)); 3254 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3255 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3256 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3257 ahc_outb(ahc, SG_NEXT, sg_addr); 3258 } 3259 3260 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3261 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3262 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3263 3264 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3265 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3266 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3267 ahc_outb(ahc, SHADDR, data_addr); 3268 } 3269 } 3270 } 3271 3272 static void 3273 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3274 int status, char *message, 3275 int verbose_level) 3276 { 3277 int found; 3278 3279 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3280 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3281 status); 3282 3283 /* 3284 * Go back to async/narrow transfers and renegotiate. 3285 * ahc_set_width and ahc_set_syncrate can cope with NULL 3286 * paths. 3287 */ 3288 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3289 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3290 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3291 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3292 /*paused*/TRUE, /*done*/FALSE); 3293 3294 if (message != NULL && (verbose_level <= 0)) 3295 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3296 message, devinfo->channel, devinfo->target, found); 3297 } 3298 3299 /* 3300 * We have an scb which has been processed by the 3301 * adaptor, now we look to see how the operation 3302 * went. 3303 */ 3304 static void 3305 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3306 { 3307 struct scsipi_xfer *xs; 3308 struct scsipi_link *sc_link; 3309 int requeue = 0; 3310 int target; 3311 3312 3313 xs = scb->xs; 3314 sc_link = xs->sc_link; 3315 LIST_REMOVE(scb, plinks); 3316 3317 callout_stop(&scb->xs->xs_callout); 3318 3319 #ifdef AHC_DEBUG 3320 if (ahc_debug & AHC_SHOWCMDS) { 3321 scsi_print_addr(sc_link); 3322 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3323 scb->hscb->tag); 3324 } 3325 #endif 3326 3327 target = sc_link->scsipi_scsi.target; 3328 3329 if (xs->datalen) { 3330 int op; 3331 3332 if (xs->xs_control & XS_CTL_DATA_IN) 3333 op = BUS_DMASYNC_POSTREAD; 3334 else 3335 op = BUS_DMASYNC_POSTWRITE; 3336 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3337 scb->dmamap->dm_mapsize, op); 3338 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3339 } 3340 3341 /* 3342 * Unbusy this target/channel/lun. 3343 * XXX if we are holding two commands per lun, 3344 * send the next command. 3345 */ 3346 if (!(scb->hscb->control & TAG_ENB)) 3347 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3348 3349 /* 3350 * If the recovery SCB completes, we have to be 3351 * out of our timeout. 3352 */ 3353 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3354 3355 struct scb *scbp; 3356 3357 /* 3358 * We were able to complete the command successfully, 3359 * so reinstate the timeouts for all other pending 3360 * commands. 3361 */ 3362 scbp = ahc->pending_ccbs.lh_first; 3363 while (scbp != NULL) { 3364 struct scsipi_xfer *txs = scbp->xs; 3365 3366 if (!(txs->xs_control & XS_CTL_POLL)) { 3367 callout_reset(&scbp->xs->xs_callout, 3368 (scbp->xs->timeout * hz) / 1000, 3369 ahc_timeout, scbp); 3370 } 3371 scbp = LIST_NEXT(scbp, plinks); 3372 } 3373 3374 /* 3375 * Ensure that we didn't put a second instance of this 3376 * SCB into the QINFIFO. 3377 */ 3378 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3379 SCB_LUN(scb), scb->hscb->tag, 3380 ROLE_INITIATOR, /*status*/0, 3381 SEARCH_REMOVE); 3382 if (xs->error != XS_NOERROR) 3383 ahcsetccbstatus(xs, XS_TIMEOUT); 3384 scsi_print_addr(xs->sc_link); 3385 printf("no longer in timeout, status = %x\n", xs->status); 3386 } 3387 3388 if (xs->error != XS_NOERROR) { 3389 /* Don't clobber any existing error state */ 3390 } else if ((scb->flags & SCB_SENSE) != 0) { 3391 /* 3392 * We performed autosense retrieval. 3393 * 3394 * bzero the sense data before having 3395 * the drive fill it. The SCSI spec mandates 3396 * that any untransfered data should be 3397 * assumed to be zero. Complete the 'bounce' 3398 * of sense information through buffers accessible 3399 * via bus-space by copying it into the clients 3400 * csio. 3401 */ 3402 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3403 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3404 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3405 xs->error = XS_SENSE; 3406 } 3407 if (scb->flags & SCB_FREEZE_QUEUE) { 3408 ahc->devqueue_blocked[target]--; 3409 scb->flags &= ~SCB_FREEZE_QUEUE; 3410 } 3411 3412 requeue = scb->flags & SCB_REQUEUE; 3413 ahcfreescb(ahc, scb); 3414 3415 if (requeue) { 3416 /* 3417 * Re-insert at the front of the private queue to 3418 * preserve order. 3419 */ 3420 int s; 3421 3422 s = splbio(); 3423 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3424 splx(s); 3425 } else { 3426 xs->xs_status |= XS_STS_DONE; 3427 ahc_check_tags(ahc, xs); 3428 scsipi_done(xs); 3429 } 3430 3431 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3432 ahc_action(xs); 3433 } 3434 3435 /* 3436 * Determine the number of SCBs available on the controller 3437 */ 3438 int 3439 ahc_probe_scbs(struct ahc_softc *ahc) { 3440 int i; 3441 3442 for (i = 0; i < AHC_SCB_MAX; i++) { 3443 ahc_outb(ahc, SCBPTR, i); 3444 ahc_outb(ahc, SCB_CONTROL, i); 3445 if (ahc_inb(ahc, SCB_CONTROL) != i) 3446 break; 3447 ahc_outb(ahc, SCBPTR, 0); 3448 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3449 break; 3450 } 3451 return (i); 3452 } 3453 3454 /* 3455 * Start the board, ready for normal operation 3456 */ 3457 int 3458 ahc_init(struct ahc_softc *ahc) 3459 { 3460 int max_targ = 15; 3461 int i; 3462 int term; 3463 u_int scsi_conf; 3464 u_int scsiseq_template; 3465 u_int ultraenb; 3466 u_int discenable; 3467 u_int tagenable; 3468 size_t driver_data_size; 3469 u_int32_t physaddr; 3470 3471 #ifdef AHC_PRINT_SRAM 3472 printf("Scratch Ram:"); 3473 for (i = 0x20; i < 0x5f; i++) { 3474 if (((i % 8) == 0) && (i != 0)) { 3475 printf ("\n "); 3476 } 3477 printf (" 0x%x", ahc_inb(ahc, i)); 3478 } 3479 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3480 for (i = 0x70; i < 0x7f; i++) { 3481 if (((i % 8) == 0) && (i != 0)) { 3482 printf ("\n "); 3483 } 3484 printf (" 0x%x", ahc_inb(ahc, i)); 3485 } 3486 } 3487 printf ("\n"); 3488 #endif 3489 3490 /* 3491 * Assume we have a board at this stage and it has been reset. 3492 */ 3493 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3494 ahc->our_id = ahc->our_id_b = 7; 3495 3496 /* 3497 * Default to allowing initiator operations. 3498 */ 3499 ahc->flags |= AHC_INITIATORMODE; 3500 3501 /* 3502 * DMA tag for our command fifos and other data in system memory 3503 * the card's sequencer must be able to access. For initiator 3504 * roles, we need to allocate space for the qinfifo, qoutfifo, 3505 * and untagged_scb arrays each of which are composed of 256 3506 * 1 byte elements. When providing for the target mode role, 3507 * we additionally must provide space for the incoming target 3508 * command fifo. 3509 */ 3510 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3511 3512 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3513 ahc->sc_dmaflags, 3514 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3515 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3516 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3517 return (ENOMEM); 3518 3519 ahc->init_level++; 3520 3521 /* Allocate SCB data now that parent_dmat is initialized */ 3522 if (ahc->scb_data->maxhscbs == 0) 3523 if (ahcinitscbdata(ahc) != 0) 3524 return (ENOMEM); 3525 3526 ahc->qinfifo = &ahc->qoutfifo[256]; 3527 ahc->untagged_scbs = &ahc->qinfifo[256]; 3528 /* There are no untagged SCBs active yet. */ 3529 for (i = 0; i < 256; i++) 3530 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3531 3532 /* All of our queues are empty */ 3533 for (i = 0; i < 256; i++) 3534 ahc->qoutfifo[i] = SCB_LIST_NULL; 3535 3536 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3537 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3538 3539 /* 3540 * Allocate a tstate to house information for our 3541 * initiator presence on the bus as well as the user 3542 * data for any target mode initiator. 3543 */ 3544 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3545 printf("%s: unable to allocate tmode_tstate. " 3546 "Failing attach\n", ahc_name(ahc)); 3547 return (-1); 3548 } 3549 3550 if ((ahc->features & AHC_TWIN) != 0) { 3551 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3552 printf("%s: unable to allocate tmode_tstate. " 3553 "Failing attach\n", ahc_name(ahc)); 3554 return (-1); 3555 } 3556 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3557 ahc->our_id, ahc->our_id_b, 3558 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3559 } else { 3560 if ((ahc->features & AHC_WIDE) != 0) { 3561 printf("Wide "); 3562 } else { 3563 printf("Single "); 3564 } 3565 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3566 } 3567 3568 ahc_outb(ahc, SEQ_FLAGS, 0); 3569 3570 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3571 ahc->flags |= AHC_PAGESCBS; 3572 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3573 } else { 3574 ahc->flags &= ~AHC_PAGESCBS; 3575 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3576 } 3577 3578 #ifdef AHC_DEBUG 3579 if (ahc_debug & AHC_SHOWMISC) { 3580 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3581 "ahc_dma %d bytes\n", 3582 ahc_name(ahc), 3583 sizeof(struct hardware_scb), 3584 sizeof(struct scb), 3585 sizeof(struct ahc_dma_seg)); 3586 } 3587 #endif /* AHC_DEBUG */ 3588 3589 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3590 if (ahc->features & AHC_TWIN) { 3591 3592 /* 3593 * The device is gated to channel B after a chip reset, 3594 * so set those values first 3595 */ 3596 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3597 if ((ahc->features & AHC_ULTRA2) != 0) 3598 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3599 else 3600 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3601 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3602 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3603 |term|ENSTIMER|ACTNEGEN); 3604 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3605 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3606 3607 if ((scsi_conf & RESET_SCSI) != 0 3608 && (ahc->flags & AHC_INITIATORMODE) != 0) 3609 ahc->flags |= AHC_RESET_BUS_B; 3610 3611 /* Select Channel A */ 3612 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3613 } 3614 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3615 if ((ahc->features & AHC_ULTRA2) != 0) 3616 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3617 else 3618 ahc_outb(ahc, SCSIID, ahc->our_id); 3619 scsi_conf = ahc_inb(ahc, SCSICONF); 3620 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3621 |term 3622 |ENSTIMER|ACTNEGEN); 3623 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3624 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3625 3626 if ((scsi_conf & RESET_SCSI) != 0 3627 && (ahc->flags & AHC_INITIATORMODE) != 0) 3628 ahc->flags |= AHC_RESET_BUS_A; 3629 3630 /* 3631 * Look at the information that board initialization or 3632 * the board bios has left us. 3633 */ 3634 ultraenb = 0; 3635 tagenable = ALL_TARGETS_MASK; 3636 3637 /* Grab the disconnection disable table and invert it for our needs */ 3638 if (ahc->flags & AHC_USEDEFAULTS) { 3639 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3640 "device parameters\n", ahc_name(ahc)); 3641 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3642 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3643 discenable = ALL_TARGETS_MASK; 3644 if ((ahc->features & AHC_ULTRA) != 0) 3645 ultraenb = ALL_TARGETS_MASK; 3646 } else { 3647 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3648 | ahc_inb(ahc, DISC_DSB)); 3649 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3650 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3651 | ahc_inb(ahc, ULTRA_ENB); 3652 } 3653 3654 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3655 max_targ = 7; 3656 3657 for (i = 0; i <= max_targ; i++) { 3658 struct ahc_initiator_tinfo *tinfo; 3659 struct tmode_tstate *tstate; 3660 u_int our_id; 3661 u_int target_id; 3662 char channel; 3663 3664 channel = 'A'; 3665 our_id = ahc->our_id; 3666 target_id = i; 3667 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3668 channel = 'B'; 3669 our_id = ahc->our_id_b; 3670 target_id = i % 8; 3671 } 3672 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3673 target_id, &tstate); 3674 /* Default to async narrow across the board */ 3675 bzero(tinfo, sizeof(*tinfo)); 3676 if (ahc->flags & AHC_USEDEFAULTS) { 3677 if ((ahc->features & AHC_WIDE) != 0) 3678 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3679 3680 /* 3681 * These will be truncated when we determine the 3682 * connection type we have with the target. 3683 */ 3684 tinfo->user.period = ahc_syncrates->period; 3685 tinfo->user.offset = ~0; 3686 } else { 3687 u_int scsirate; 3688 u_int16_t mask; 3689 3690 /* Take the settings leftover in scratch RAM. */ 3691 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3692 mask = (0x01 << i); 3693 if ((ahc->features & AHC_ULTRA2) != 0) { 3694 u_int offset; 3695 u_int maxsync; 3696 3697 if ((scsirate & SOFS) == 0x0F) { 3698 /* 3699 * Haven't negotiated yet, 3700 * so the format is different. 3701 */ 3702 scsirate = (scsirate & SXFR) >> 4 3703 | (ultraenb & mask) 3704 ? 0x08 : 0x0 3705 | (scsirate & WIDEXFER); 3706 offset = MAX_OFFSET_ULTRA2; 3707 } else 3708 offset = ahc_inb(ahc, TARG_OFFSET + i); 3709 maxsync = AHC_SYNCRATE_ULTRA2; 3710 if ((ahc->features & AHC_DT) != 0) 3711 maxsync = AHC_SYNCRATE_DT; 3712 tinfo->user.period = 3713 ahc_find_period(ahc, scsirate, maxsync); 3714 if (offset == 0) 3715 tinfo->user.period = 0; 3716 else 3717 tinfo->user.offset = ~0; 3718 } else if ((scsirate & SOFS) != 0) { 3719 tinfo->user.period = 3720 ahc_find_period(ahc, scsirate, 3721 (ultraenb & mask) 3722 ? AHC_SYNCRATE_ULTRA 3723 : AHC_SYNCRATE_FAST); 3724 if (tinfo->user.period != 0) 3725 tinfo->user.offset = ~0; 3726 } 3727 if ((scsirate & WIDEXFER) != 0 3728 && (ahc->features & AHC_WIDE) != 0) 3729 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3730 } 3731 tinfo->goal = tinfo->user; /* force negotiation */ 3732 tstate->ultraenb = ultraenb; 3733 tstate->discenable = discenable; 3734 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3735 } 3736 ahc->user_discenable = discenable; 3737 ahc->user_tagenable = tagenable; 3738 3739 /* 3740 * Tell the sequencer where it can find our arrays in memory. 3741 */ 3742 physaddr = ahc->scb_data->hscb_busaddr; 3743 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3744 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3745 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3746 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3747 3748 physaddr = ahc->shared_data_busaddr; 3749 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3750 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3751 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3752 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3753 3754 /* Target mode incomding command fifo */ 3755 physaddr += 3 * 256 * sizeof(u_int8_t); 3756 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3757 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3758 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3759 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3760 3761 /* 3762 * Initialize the group code to command length table. 3763 * This overrides the values in TARG_SCSIRATE, so only 3764 * setup the table after we have processed that information. 3765 */ 3766 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3767 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3768 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3769 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3770 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3771 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3772 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3773 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3774 3775 /* Tell the sequencer of our initial queue positions */ 3776 ahc_outb(ahc, KERNEL_QINPOS, 0); 3777 ahc_outb(ahc, QINPOS, 0); 3778 ahc_outb(ahc, QOUTPOS, 0); 3779 3780 #ifdef AHC_DEBUG 3781 if (ahc_debug & AHC_SHOWMISC) 3782 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3783 discenable, ultraenb); 3784 #endif 3785 3786 /* Don't have any special messages to send to targets */ 3787 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3788 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3789 3790 /* 3791 * Use the built in queue management registers 3792 * if they are available. 3793 */ 3794 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3795 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3796 ahc_outb(ahc, SDSCB_QOFF, 0); 3797 ahc_outb(ahc, SNSCB_QOFF, 0); 3798 ahc_outb(ahc, HNSCB_QOFF, 0); 3799 } 3800 3801 3802 /* We don't have any waiting selections */ 3803 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3804 3805 /* Our disconnection list is empty too */ 3806 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3807 3808 /* Message out buffer starts empty */ 3809 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3810 3811 /* 3812 * Setup the allowed SCSI Sequences based on operational mode. 3813 * If we are a target, we'll enalbe select in operations once 3814 * we've had a lun enabled. 3815 */ 3816 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3817 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3818 scsiseq_template |= ENRSELI; 3819 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3820 3821 /* 3822 * Load the Sequencer program and Enable the adapter 3823 * in "fast" mode. 3824 */ 3825 #ifdef AHC_DEBUG 3826 printf("%s: Downloading Sequencer Program...", 3827 ahc_name(ahc)); 3828 #endif 3829 3830 ahc_loadseq(ahc); 3831 3832 /* We have to wait until after any system dumps... */ 3833 shutdownhook_establish(ahc_shutdown, ahc); 3834 3835 return (0); 3836 } 3837 3838 /* 3839 * XXX fvdl the busy_tcl checks and settings should only be done 3840 * for the non-tagged queueing case, but we don't do tagged queueing 3841 * yet, so.. 3842 */ 3843 static int32_t 3844 ahc_action(struct scsipi_xfer *xs) 3845 { 3846 struct scsipi_xfer *first_xs, *next_xs = NULL; 3847 struct ahc_softc *ahc; 3848 struct scb *scb; 3849 struct hardware_scb *hscb; 3850 struct ahc_initiator_tinfo *tinfo; 3851 struct tmode_tstate *tstate; 3852 u_int target_id; 3853 u_int our_id; 3854 int s, tcl; 3855 u_int16_t mask; 3856 int dontqueue = 0, fromqueue = 0; 3857 3858 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3859 3860 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3861 3862 /* must protect the queue */ 3863 s = splbio(); 3864 3865 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3866 /* 3867 * Called from ahc_done. Calling with the first entry in 3868 * the queue is really just a way of seeing where we're 3869 * called from. Now, find the first eligible SCB to send, 3870 * e.g. one which will be accepted immediately. 3871 */ 3872 3873 if (ahc->queue_blocked) { 3874 splx(s); 3875 return (TRY_AGAIN_LATER); 3876 } 3877 3878 xs = ahc_first_xs(ahc); 3879 if (xs == NULL) { 3880 splx(s); 3881 return (TRY_AGAIN_LATER); 3882 } 3883 3884 next_xs = TAILQ_NEXT(xs, adapter_q); 3885 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3886 fromqueue = 1; 3887 goto get_scb; 3888 } 3889 3890 /* 3891 * If no new requests are accepted, just insert into the 3892 * private queue to wait for our turn. 3893 */ 3894 tcl = XS_TCL(ahc, xs); 3895 3896 if (ahc->queue_blocked || 3897 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3898 (!ahc_istagged_device(ahc, xs) && 3899 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3900 if (dontqueue) { 3901 splx(s); 3902 xs->error = XS_DRIVER_STUFFUP; 3903 return TRY_AGAIN_LATER; 3904 } 3905 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3906 splx(s); 3907 return SUCCESSFULLY_QUEUED; 3908 } 3909 3910 first_xs = ahc_first_xs(ahc); 3911 3912 /* determine safety of software queueing */ 3913 dontqueue = xs->xs_control & XS_CTL_POLL; 3914 3915 /* 3916 * Handle situations where there's already entries in the 3917 * queue. 3918 */ 3919 if (first_xs != NULL) { 3920 /* 3921 * If we can't queue, we have to abort, since 3922 * we have to preserve order. 3923 */ 3924 if (dontqueue) { 3925 splx(s); 3926 xs->error = XS_DRIVER_STUFFUP; 3927 return (TRY_AGAIN_LATER); 3928 } 3929 3930 /* 3931 * Swap with the first queue entry. 3932 */ 3933 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3934 xs = first_xs; 3935 next_xs = TAILQ_NEXT(xs, adapter_q); 3936 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3937 fromqueue = 1; 3938 3939 } 3940 3941 get_scb: 3942 3943 target_id = xs->sc_link->scsipi_scsi.target; 3944 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3945 3946 /* 3947 * get an scb to use. 3948 */ 3949 if ((scb = ahcgetscb(ahc)) == NULL) { 3950 3951 if (dontqueue) { 3952 splx(s); 3953 xs->error = XS_DRIVER_STUFFUP; 3954 return (TRY_AGAIN_LATER); 3955 } 3956 3957 /* 3958 * If we were pulled off the queue, put ourselves 3959 * back to where we came from, otherwise tack ourselves 3960 * onto the end. 3961 */ 3962 if (fromqueue && next_xs != NULL) 3963 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3964 else 3965 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3966 3967 splx(s); 3968 return (SUCCESSFULLY_QUEUED); 3969 } 3970 3971 tcl = XS_TCL(ahc, xs); 3972 3973 #ifdef DIAGNOSTIC 3974 if (!ahc_istagged_device(ahc, xs) && 3975 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3976 panic("ahc: queuing for busy target"); 3977 #endif 3978 3979 scb->xs = xs; 3980 hscb = scb->hscb; 3981 hscb->tcl = tcl; 3982 3983 if (ahc_istagged_device(ahc, xs)) 3984 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 3985 else 3986 ahc_busy_tcl(ahc, scb); 3987 3988 splx(s); 3989 3990 /* 3991 * Put all the arguments for the xfer in the scb 3992 */ 3993 3994 mask = SCB_TARGET_MASK(scb); 3995 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 3996 target_id, &tstate); 3997 if (ahc->inited_targets[target_id] == 0) { 3998 struct ahc_devinfo devinfo; 3999 4000 s = splbio(); 4001 ahc_compile_devinfo(&devinfo, our_id, target_id, 4002 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4003 ROLE_INITIATOR); 4004 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4005 FALSE); 4006 ahc->inited_targets[target_id] = 1; 4007 splx(s); 4008 } 4009 4010 hscb->scsirate = tinfo->scsirate; 4011 hscb->scsioffset = tinfo->current.offset; 4012 if ((tstate->ultraenb & mask) != 0) 4013 hscb->control |= ULTRAENB; 4014 4015 if ((tstate->discenable & mask) != 0) 4016 hscb->control |= DISCENB; 4017 4018 if (xs->xs_control & XS_CTL_RESET) { 4019 hscb->cmdpointer = NULL; 4020 scb->flags |= SCB_DEVICE_RESET; 4021 hscb->control |= MK_MESSAGE; 4022 return ahc_execute_scb(scb, NULL, 0); 4023 } 4024 4025 return ahc_setup_data(ahc, xs, scb); 4026 } 4027 4028 static int 4029 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4030 { 4031 struct scb *scb; 4032 struct scsipi_xfer *xs; 4033 struct ahc_softc *ahc; 4034 int s; 4035 4036 scb = (struct scb *)arg; 4037 xs = scb->xs; 4038 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4039 4040 4041 if (nsegments != 0) { 4042 struct ahc_dma_seg *sg; 4043 bus_dma_segment_t *end_seg; 4044 int op; 4045 4046 end_seg = dm_segs + nsegments; 4047 4048 /* Copy the first SG into the data pointer area */ 4049 scb->hscb->data = dm_segs->ds_addr; 4050 scb->hscb->datalen = dm_segs->ds_len; 4051 4052 /* Copy the segments into our SG list */ 4053 sg = scb->sg_list; 4054 while (dm_segs < end_seg) { 4055 sg->addr = dm_segs->ds_addr; 4056 sg->len = dm_segs->ds_len; 4057 ahc_swap_sg(sg); 4058 sg++; 4059 dm_segs++; 4060 } 4061 4062 /* Note where to find the SG entries in bus space */ 4063 scb->hscb->SG_pointer = scb->sg_list_phys; 4064 4065 if (xs->xs_control & XS_CTL_DATA_IN) 4066 op = BUS_DMASYNC_PREREAD; 4067 else 4068 op = BUS_DMASYNC_PREWRITE; 4069 4070 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4071 scb->dmamap->dm_mapsize, op); 4072 4073 } else { 4074 scb->hscb->SG_pointer = 0; 4075 scb->hscb->data = 0; 4076 scb->hscb->datalen = 0; 4077 } 4078 4079 scb->sg_count = scb->hscb->SG_count = nsegments; 4080 4081 s = splbio(); 4082 4083 /* 4084 * Last time we need to check if this SCB needs to 4085 * be aborted. 4086 */ 4087 if (xs->xs_status & XS_STS_DONE) { 4088 if (!ahc_istagged_device(ahc, xs)) 4089 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4090 if (nsegments != 0) 4091 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4092 ahcfreescb(ahc, scb); 4093 splx(s); 4094 return (COMPLETE); 4095 } 4096 4097 #ifdef DIAGNOSTIC 4098 if (scb->sg_count > 255) 4099 panic("ahc bad sg_count"); 4100 #endif 4101 4102 ahc_swap_hscb(scb->hscb); 4103 4104 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4105 4106 scb->flags |= SCB_ACTIVE; 4107 4108 if (!(xs->xs_control & XS_CTL_POLL)) 4109 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4110 ahc_timeout, scb); 4111 4112 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4113 #if 0 4114 printf("Continueing Immediate Command %d:%d\n", 4115 xs->sc_link->scsipi_scsi.target, 4116 xs->sc_link->scsipi_scsi.lun); 4117 #endif 4118 pause_sequencer(ahc); 4119 if ((ahc->flags & AHC_PAGESCBS) == 0) 4120 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4121 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4122 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4123 unpause_sequencer(ahc); 4124 } else { 4125 4126 #if 0 4127 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4128 scb->hscb->tag, ahc->qinfifonext, 4129 &ahc->qinfifo[ahc->qinfifonext], 4130 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4131 #endif 4132 4133 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4134 4135 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4136 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4137 4138 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4139 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4140 } else { 4141 pause_sequencer(ahc); 4142 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4143 unpause_sequencer(ahc); 4144 } 4145 } 4146 4147 #ifdef AHC_DEBUG 4148 if (ahc_debug & AHC_SHOWCMDS) { 4149 scsi_print_addr(xs->sc_link); 4150 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4151 " rate %x\n", 4152 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4153 scb->flags, scb->hscb->control, ahc->qinfifonext, 4154 scb->hscb->scsirate); 4155 } 4156 #endif 4157 4158 if (!(xs->xs_control & XS_CTL_POLL)) { 4159 splx(s); 4160 return (SUCCESSFULLY_QUEUED); 4161 } 4162 /* 4163 * If we can't use interrupts, poll for completion 4164 */ 4165 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4166 do { 4167 if (ahc_poll(ahc, xs->timeout)) { 4168 if (!(xs->xs_control & XS_CTL_SILENT)) 4169 printf("cmd fail\n"); 4170 ahc_timeout(scb); 4171 break; 4172 } 4173 } while (!(xs->xs_status & XS_STS_DONE)); 4174 splx(s); 4175 return (COMPLETE); 4176 } 4177 4178 static int 4179 ahc_poll(struct ahc_softc *ahc, int wait) 4180 { 4181 while (--wait) { 4182 DELAY(1000); 4183 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4184 break; 4185 } 4186 4187 if (wait == 0) { 4188 printf("%s: board is not responding\n", ahc_name(ahc)); 4189 return (EIO); 4190 } 4191 4192 ahc_intr((void *)ahc); 4193 return (0); 4194 } 4195 4196 static int 4197 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4198 struct scb *scb) 4199 { 4200 struct hardware_scb *hscb; 4201 4202 hscb = scb->hscb; 4203 xs->resid = xs->status = 0; 4204 4205 hscb->cmdlen = xs->cmdlen; 4206 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4207 hscb->cmdpointer = hscb->cmdstore_busaddr; 4208 4209 /* Only use S/G if there is a transfer */ 4210 if (xs->datalen) { 4211 int error; 4212 4213 error = bus_dmamap_load(ahc->parent_dmat, 4214 scb->dmamap, xs->data, 4215 xs->datalen, NULL, 4216 (xs->xs_control & XS_CTL_NOSLEEP) ? 4217 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4218 if (error) { 4219 if (!ahc_istagged_device(ahc, xs)) 4220 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4221 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4222 } 4223 error = ahc_execute_scb(scb, 4224 scb->dmamap->dm_segs, 4225 scb->dmamap->dm_nsegs); 4226 return error; 4227 } else { 4228 return ahc_execute_scb(scb, NULL, 0); 4229 } 4230 } 4231 4232 static void 4233 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4234 { 4235 int target; 4236 char channel; 4237 int lun; 4238 4239 target = sc_link->scsipi_scsi.target; 4240 lun = sc_link->scsipi_scsi.lun; 4241 channel = sc_link->scsipi_scsi.channel; 4242 4243 ahc_search_qinfifo(ahc, target, channel, lun, 4244 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4245 SCB_REQUEUE, SEARCH_COMPLETE); 4246 } 4247 4248 static void 4249 ahcallocscbs(struct ahc_softc *ahc) 4250 { 4251 struct scb_data *scb_data; 4252 struct scb *next_scb; 4253 struct sg_map_node *sg_map; 4254 bus_addr_t physaddr; 4255 struct ahc_dma_seg *segs; 4256 int newcount; 4257 int i; 4258 4259 scb_data = ahc->scb_data; 4260 if (scb_data->numscbs >= AHC_SCB_MAX) 4261 /* Can't allocate any more */ 4262 return; 4263 4264 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4265 4266 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4267 4268 if (sg_map == NULL) 4269 return; 4270 4271 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4272 &sg_map->sg_dmamap, 4273 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4274 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4275 "SG space") < 0) { 4276 free(sg_map, M_DEVBUF); 4277 return; 4278 } 4279 4280 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4281 4282 segs = sg_map->sg_vaddr; 4283 physaddr = sg_map->sg_physaddr; 4284 4285 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4286 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4287 int error; 4288 4289 next_scb->sg_list = segs; 4290 /* 4291 * The sequencer always starts with the second entry. 4292 * The first entry is embedded in the scb. 4293 */ 4294 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4295 next_scb->flags = SCB_FREE; 4296 error = bus_dmamap_create(ahc->parent_dmat, 4297 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4298 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4299 &next_scb->dmamap); 4300 if (error != 0) 4301 break; 4302 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4303 next_scb->hscb->tag = ahc->scb_data->numscbs; 4304 next_scb->hscb->cmdstore_busaddr = 4305 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4306 + offsetof(struct hardware_scb, cmdstore); 4307 next_scb->hscb->cmdstore_busaddr = 4308 htole32(next_scb->hscb->cmdstore_busaddr); 4309 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4310 segs += AHC_NSEG; 4311 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4312 next_scb++; 4313 ahc->scb_data->numscbs++; 4314 } 4315 #ifdef AHC_DEBUG 4316 if (ahc_debug & AHC_SHOWSCBALLOC) 4317 printf("%s: allocated %d new SCBs count now %d\n", 4318 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4319 #endif 4320 } 4321 4322 #ifdef AHC_DUMP_SEQ 4323 static void 4324 ahc_dumpseq(struct ahc_softc* ahc) 4325 { 4326 int i; 4327 int max_prog; 4328 4329 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4330 max_prog = 448; 4331 else if ((ahc->features & AHC_ULTRA2) != 0) 4332 max_prog = 768; 4333 else 4334 max_prog = 512; 4335 4336 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4337 ahc_outb(ahc, SEQADDR0, 0); 4338 ahc_outb(ahc, SEQADDR1, 0); 4339 for (i = 0; i < max_prog; i++) { 4340 u_int8_t ins_bytes[4]; 4341 4342 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4343 printf("0x%08x\n", ins_bytes[0] << 24 4344 | ins_bytes[1] << 16 4345 | ins_bytes[2] << 8 4346 | ins_bytes[3]); 4347 } 4348 } 4349 #endif 4350 4351 static void 4352 ahc_loadseq(struct ahc_softc *ahc) 4353 { 4354 struct patch *cur_patch; 4355 int i; 4356 int downloaded; 4357 int skip_addr; 4358 u_int8_t download_consts[4]; 4359 4360 /* Setup downloadable constant table */ 4361 #if 0 4362 /* No downloaded constants are currently defined. */ 4363 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4364 #endif 4365 4366 cur_patch = patches; 4367 downloaded = 0; 4368 skip_addr = 0; 4369 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4370 ahc_outb(ahc, SEQADDR0, 0); 4371 ahc_outb(ahc, SEQADDR1, 0); 4372 4373 for (i = 0; i < sizeof(seqprog)/4; i++) { 4374 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4375 /* 4376 * Don't download this instruction as it 4377 * is in a patch that was removed. 4378 */ 4379 continue; 4380 } 4381 ahc_download_instr(ahc, i, download_consts); 4382 downloaded++; 4383 } 4384 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4385 restart_sequencer(ahc); 4386 4387 #ifdef AHC_DEBUG 4388 printf(" %d instructions downloaded\n", downloaded); 4389 #endif 4390 } 4391 4392 static int 4393 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4394 int start_instr, int *skip_addr) 4395 { 4396 struct patch *cur_patch; 4397 struct patch *last_patch; 4398 int num_patches; 4399 4400 num_patches = sizeof(patches)/sizeof(struct patch); 4401 last_patch = &patches[num_patches]; 4402 cur_patch = *start_patch; 4403 4404 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4405 4406 if (cur_patch->patch_func(ahc) == 0) { 4407 4408 /* Start rejecting code */ 4409 *skip_addr = start_instr + cur_patch->skip_instr; 4410 cur_patch += cur_patch->skip_patch; 4411 } else { 4412 /* Accepted this patch. Advance to the next 4413 * one and wait for our intruction pointer to 4414 * hit this point. 4415 */ 4416 cur_patch++; 4417 } 4418 } 4419 4420 *start_patch = cur_patch; 4421 if (start_instr < *skip_addr) 4422 /* Still skipping */ 4423 return (0); 4424 4425 return (1); 4426 } 4427 4428 static void 4429 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4430 { 4431 union ins_formats instr; 4432 struct ins_format1 *fmt1_ins; 4433 struct ins_format3 *fmt3_ins; 4434 u_int opcode; 4435 4436 /* Structure copy */ 4437 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4438 4439 instr.integer = le32toh(instr.integer); 4440 4441 fmt1_ins = &instr.format1; 4442 fmt3_ins = NULL; 4443 4444 /* Pull the opcode */ 4445 opcode = instr.format1.opcode; 4446 switch (opcode) { 4447 case AIC_OP_JMP: 4448 case AIC_OP_JC: 4449 case AIC_OP_JNC: 4450 case AIC_OP_CALL: 4451 case AIC_OP_JNE: 4452 case AIC_OP_JNZ: 4453 case AIC_OP_JE: 4454 case AIC_OP_JZ: 4455 { 4456 struct patch *cur_patch; 4457 int address_offset; 4458 u_int address; 4459 int skip_addr; 4460 int i; 4461 4462 fmt3_ins = &instr.format3; 4463 address_offset = 0; 4464 address = fmt3_ins->address; 4465 cur_patch = patches; 4466 skip_addr = 0; 4467 4468 for (i = 0; i < address;) { 4469 4470 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4471 4472 if (skip_addr > i) { 4473 int end_addr; 4474 4475 end_addr = MIN(address, skip_addr); 4476 address_offset += end_addr - i; 4477 i = skip_addr; 4478 } else { 4479 i++; 4480 } 4481 } 4482 address -= address_offset; 4483 fmt3_ins->address = address; 4484 /* FALLTHROUGH */ 4485 } 4486 case AIC_OP_OR: 4487 case AIC_OP_AND: 4488 case AIC_OP_XOR: 4489 case AIC_OP_ADD: 4490 case AIC_OP_ADC: 4491 case AIC_OP_BMOV: 4492 if (fmt1_ins->parity != 0) { 4493 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4494 } 4495 fmt1_ins->parity = 0; 4496 /* FALLTHROUGH */ 4497 case AIC_OP_ROL: 4498 if ((ahc->features & AHC_ULTRA2) != 0) { 4499 int i, count; 4500 4501 /* Calculate odd parity for the instruction */ 4502 for (i = 0, count = 0; i < 31; i++) { 4503 u_int32_t mask; 4504 4505 mask = 0x01 << i; 4506 if ((instr.integer & mask) != 0) 4507 count++; 4508 } 4509 if ((count & 0x01) == 0) 4510 instr.format1.parity = 1; 4511 } else { 4512 /* Compress the instruction for older sequencers */ 4513 if (fmt3_ins != NULL) { 4514 instr.integer = 4515 fmt3_ins->immediate 4516 | (fmt3_ins->source << 8) 4517 | (fmt3_ins->address << 16) 4518 | (fmt3_ins->opcode << 25); 4519 } else { 4520 instr.integer = 4521 fmt1_ins->immediate 4522 | (fmt1_ins->source << 8) 4523 | (fmt1_ins->destination << 16) 4524 | (fmt1_ins->ret << 24) 4525 | (fmt1_ins->opcode << 25); 4526 } 4527 } 4528 instr.integer = htole32(instr.integer); 4529 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4530 break; 4531 default: 4532 panic("Unknown opcode encountered in seq program"); 4533 break; 4534 } 4535 } 4536 4537 static void 4538 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4539 { 4540 4541 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4542 struct scb *scbp; 4543 4544 scb->flags |= SCB_RECOVERY_SCB; 4545 4546 /* 4547 * Take all queued, but not sent SCBs out of the equation. 4548 * Also ensure that no new CCBs are queued to us while we 4549 * try to fix this problem. 4550 */ 4551 ahc->queue_blocked = 1; 4552 4553 /* 4554 * Go through all of our pending SCBs and remove 4555 * any scheduled timeouts for them. We will reschedule 4556 * them after we've successfully fixed this problem. 4557 */ 4558 scbp = ahc->pending_ccbs.lh_first; 4559 while (scbp != NULL) { 4560 callout_stop(&scbp->xs->xs_callout); 4561 scbp = scbp->plinks.le_next; 4562 } 4563 } 4564 } 4565 4566 static void 4567 ahc_timeout(void *arg) 4568 { 4569 struct scb *scb; 4570 struct ahc_softc *ahc; 4571 int s, found; 4572 u_int last_phase; 4573 int target; 4574 int lun; 4575 int i; 4576 char channel; 4577 4578 scb = (struct scb *)arg; 4579 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4580 4581 s = splbio(); 4582 4583 /* 4584 * Ensure that the card doesn't do anything 4585 * behind our back. Also make sure that we 4586 * didn't "just" miss an interrupt that would 4587 * affect this timeout. 4588 */ 4589 do { 4590 ahc_intr(ahc); 4591 pause_sequencer(ahc); 4592 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4593 4594 if ((scb->flags & SCB_ACTIVE) == 0) { 4595 /* Previous timeout took care of me already */ 4596 printf("Timedout SCB handled by another timeout\n"); 4597 unpause_sequencer(ahc); 4598 splx(s); 4599 return; 4600 } 4601 4602 target = SCB_TARGET(scb); 4603 channel = SCB_CHANNEL(scb); 4604 lun = SCB_LUN(scb); 4605 4606 scsi_print_addr(scb->xs->sc_link); 4607 printf("SCB %x - timed out ", scb->hscb->tag); 4608 /* 4609 * Take a snapshot of the bus state and print out 4610 * some information so we can track down driver bugs. 4611 */ 4612 last_phase = ahc_inb(ahc, LASTPHASE); 4613 4614 for (i = 0; i < num_phases; i++) { 4615 if (last_phase == phase_table[i].phase) 4616 break; 4617 } 4618 printf("%s", phase_table[i].phasemsg); 4619 4620 printf(", SEQADDR == 0x%x\n", 4621 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4622 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4623 4624 #ifdef AHC_DEBUG 4625 ahc_print_scb(scb); 4626 #endif 4627 4628 #if 0 4629 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4630 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4631 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4632 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4633 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4634 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4635 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4636 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4637 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4638 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4639 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4640 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4641 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4642 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4643 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4644 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4645 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4646 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4647 if (scb->sg_count > 0) { 4648 for (i = 0; i < scb->sg_count; i++) { 4649 printf("sg[%d] - Addr 0x%x : Length %d\n", 4650 i, 4651 le32toh(scb->sg_list[i].addr), 4652 le32toh(scb->sg_list[i].len)); 4653 } 4654 } 4655 #endif 4656 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4657 /* 4658 * Been down this road before. 4659 * Do a full bus reset. 4660 */ 4661 bus_reset: 4662 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4663 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4664 printf("%s: Issued Channel %c Bus Reset. " 4665 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4666 } else { 4667 /* 4668 * If we are a target, transition to bus free and report 4669 * the timeout. 4670 * 4671 * The target/initiator that is holding up the bus may not 4672 * be the same as the one that triggered this timeout 4673 * (different commands have different timeout lengths). 4674 * If the bus is idle and we are actiing as the initiator 4675 * for this request, queue a BDR message to the timed out 4676 * target. Otherwise, if the timed out transaction is 4677 * active: 4678 * Initiator transaction: 4679 * Stuff the message buffer with a BDR message and assert 4680 * ATN in the hopes that the target will let go of the bus 4681 * and go to the mesgout phase. If this fails, we'll 4682 * get another timeout 2 seconds later which will attempt 4683 * a bus reset. 4684 * 4685 * Target transaction: 4686 * Transition to BUS FREE and report the error. 4687 * It's good to be the target! 4688 */ 4689 u_int active_scb_index; 4690 4691 active_scb_index = ahc_inb(ahc, SCB_TAG); 4692 4693 if (last_phase != P_BUSFREE 4694 && (active_scb_index < ahc->scb_data->numscbs)) { 4695 struct scb *active_scb; 4696 4697 /* 4698 * If the active SCB is not from our device, 4699 * assume that another device is hogging the bus 4700 * and wait for it's timeout to expire before 4701 * taking additional action. 4702 */ 4703 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4704 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4705 u_int newtimeout; 4706 4707 scsi_print_addr(scb->xs->sc_link); 4708 printf("Other SCB Timeout%s", 4709 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4710 ? " again\n" : "\n"); 4711 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4712 newtimeout = MAX(active_scb->xs->timeout, 4713 scb->xs->timeout); 4714 callout_reset(&scb->xs->xs_callout, 4715 (newtimeout * hz) / 1000, 4716 ahc_timeout, scb); 4717 splx(s); 4718 return; 4719 } 4720 4721 /* It's us */ 4722 if ((scb->hscb->control & TARGET_SCB) != 0) { 4723 4724 /* 4725 * Send back any queued up transactions 4726 * and properly record the error condition. 4727 */ 4728 ahc_freeze_devq(ahc, scb->xs->sc_link); 4729 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4730 ahc_freeze_ccb(scb); 4731 ahc_done(ahc, scb); 4732 4733 /* Will clear us from the bus */ 4734 restart_sequencer(ahc); 4735 return; 4736 } 4737 4738 ahc_set_recoveryscb(ahc, active_scb); 4739 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4740 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4741 scsi_print_addr(active_scb->xs->sc_link); 4742 printf("BDR message in message buffer\n"); 4743 active_scb->flags |= SCB_DEVICE_RESET; 4744 callout_reset(&active_scb->xs->xs_callout, 4745 2 * hz, ahc_timeout, active_scb); 4746 unpause_sequencer(ahc); 4747 } else { 4748 int disconnected; 4749 4750 /* XXX Shouldn't panic. Just punt instead */ 4751 if ((scb->hscb->control & TARGET_SCB) != 0) 4752 panic("Timed-out target SCB but bus idle"); 4753 4754 if (last_phase != P_BUSFREE 4755 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4756 /* XXX What happened to the SCB? */ 4757 /* Hung target selection. Goto busfree */ 4758 printf("%s: Hung target selection\n", 4759 ahc_name(ahc)); 4760 restart_sequencer(ahc); 4761 return; 4762 } 4763 4764 if (ahc_search_qinfifo(ahc, target, channel, lun, 4765 scb->hscb->tag, ROLE_INITIATOR, 4766 /*status*/0, SEARCH_COUNT) > 0) { 4767 disconnected = FALSE; 4768 } else { 4769 disconnected = TRUE; 4770 } 4771 4772 if (disconnected) { 4773 u_int active_scb; 4774 4775 ahc_set_recoveryscb(ahc, scb); 4776 /* 4777 * Simply set the MK_MESSAGE control bit. 4778 */ 4779 scb->hscb->control |= MK_MESSAGE; 4780 scb->flags |= SCB_QUEUED_MSG 4781 | SCB_DEVICE_RESET; 4782 4783 /* 4784 * Mark the cached copy of this SCB in the 4785 * disconnected list too, so that a reconnect 4786 * at this point causes a BDR or abort. 4787 */ 4788 active_scb = ahc_inb(ahc, SCBPTR); 4789 if (ahc_search_disc_list(ahc, target, 4790 channel, lun, 4791 scb->hscb->tag, 4792 /*stop_on_first*/TRUE, 4793 /*remove*/FALSE, 4794 /*save_state*/FALSE)) { 4795 u_int scb_control; 4796 4797 scb_control = ahc_inb(ahc, SCB_CONTROL); 4798 scb_control |= MK_MESSAGE; 4799 ahc_outb(ahc, SCB_CONTROL, scb_control); 4800 } 4801 ahc_outb(ahc, SCBPTR, active_scb); 4802 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4803 /*unbusy*/TRUE); 4804 4805 /* 4806 * Actually re-queue this SCB in case we can 4807 * select the device before it reconnects. 4808 * Clear out any entries in the QINFIFO first 4809 * so we are the next SCB for this target 4810 * to run. 4811 */ 4812 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4813 channel, SCB_LUN(scb), 4814 SCB_LIST_NULL, 4815 ROLE_INITIATOR, 4816 SCB_REQUEUE, 4817 SEARCH_COMPLETE); 4818 scsi_print_addr(scb->xs->sc_link); 4819 printf("Queuing a BDR SCB\n"); 4820 ahc->qinfifo[ahc->qinfifonext++] = 4821 scb->hscb->tag; 4822 4823 bus_dmamap_sync(ahc->parent_dmat, 4824 ahc->shared_data_dmamap, 4825 QINFIFO_OFFSET * 256, 256, 4826 BUS_DMASYNC_PREWRITE); 4827 4828 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4829 ahc_outb(ahc, HNSCB_QOFF, 4830 ahc->qinfifonext); 4831 } else { 4832 ahc_outb(ahc, KERNEL_QINPOS, 4833 ahc->qinfifonext); 4834 } 4835 callout_reset(&scb->xs->xs_callout, 2 * hz, 4836 ahc_timeout, scb); 4837 unpause_sequencer(ahc); 4838 } else { 4839 /* Go "immediatly" to the bus reset */ 4840 /* This shouldn't happen */ 4841 ahc_set_recoveryscb(ahc, scb); 4842 scsi_print_addr(scb->xs->sc_link); 4843 printf("SCB %x: Immediate reset. " 4844 "Flags = 0x%x\n", scb->hscb->tag, 4845 scb->flags); 4846 goto bus_reset; 4847 } 4848 } 4849 } 4850 splx(s); 4851 } 4852 4853 static int 4854 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4855 int lun, u_int tag, role_t role, scb_flag status, 4856 ahc_search_action action) 4857 { 4858 struct scb *scbp; 4859 u_int8_t qinpos; 4860 u_int8_t qintail; 4861 int found; 4862 4863 qinpos = ahc_inb(ahc, QINPOS); 4864 qintail = ahc->qinfifonext; 4865 found = 0; 4866 4867 /* 4868 * Start with an empty queue. Entries that are not chosen 4869 * for removal will be re-added to the queue as we go. 4870 */ 4871 ahc->qinfifonext = qinpos; 4872 4873 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4874 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4875 4876 while (qinpos != qintail) { 4877 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4878 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4879 /* 4880 * We found an scb that needs to be removed. 4881 */ 4882 switch (action) { 4883 case SEARCH_COMPLETE: 4884 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4885 scbp->flags |= status; 4886 scbp->xs->error = XS_NOERROR; 4887 } 4888 ahc_freeze_ccb(scbp); 4889 ahc_done(ahc, scbp); 4890 break; 4891 case SEARCH_COUNT: 4892 ahc->qinfifo[ahc->qinfifonext++] = 4893 scbp->hscb->tag; 4894 break; 4895 case SEARCH_REMOVE: 4896 break; 4897 } 4898 found++; 4899 } else { 4900 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4901 } 4902 qinpos++; 4903 } 4904 4905 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4906 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4907 4908 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4909 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4910 } else { 4911 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4912 } 4913 4914 return (found); 4915 } 4916 4917 /* 4918 * Abort all SCBs that match the given description (target/channel/lun/tag), 4919 * setting their status to the passed in status if the status has not already 4920 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4921 * is paused before it is called. 4922 */ 4923 static int 4924 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4925 int lun, u_int tag, role_t role, int status) 4926 { 4927 struct scb *scbp; 4928 u_int active_scb; 4929 int i; 4930 int found; 4931 4932 /* restore this when we're done */ 4933 active_scb = ahc_inb(ahc, SCBPTR); 4934 4935 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4936 role, SCB_REQUEUE, SEARCH_COMPLETE); 4937 4938 /* 4939 * Search waiting for selection list. 4940 */ 4941 { 4942 u_int8_t next, prev; 4943 4944 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4945 prev = SCB_LIST_NULL; 4946 4947 while (next != SCB_LIST_NULL) { 4948 u_int8_t scb_index; 4949 4950 ahc_outb(ahc, SCBPTR, next); 4951 scb_index = ahc_inb(ahc, SCB_TAG); 4952 if (scb_index >= ahc->scb_data->numscbs) { 4953 panic("Waiting List inconsistency. " 4954 "SCB index == %d, yet numscbs == %d.", 4955 scb_index, ahc->scb_data->numscbs); 4956 } 4957 scbp = &ahc->scb_data->scbarray[scb_index]; 4958 if (ahc_match_scb(scbp, target, channel, 4959 lun, SCB_LIST_NULL, role)) { 4960 4961 next = ahc_abort_wscb(ahc, next, prev); 4962 } else { 4963 4964 prev = next; 4965 next = ahc_inb(ahc, SCB_NEXT); 4966 } 4967 } 4968 } 4969 /* 4970 * Go through the disconnected list and remove any entries we 4971 * have queued for completion, 0'ing their control byte too. 4972 * We save the active SCB and restore it ourselves, so there 4973 * is no reason for this search to restore it too. 4974 */ 4975 ahc_search_disc_list(ahc, target, channel, lun, tag, 4976 /*stop_on_first*/FALSE, /*remove*/TRUE, 4977 /*save_state*/FALSE); 4978 4979 /* 4980 * Go through the hardware SCB array looking for commands that 4981 * were active but not on any list. 4982 */ 4983 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4984 u_int scbid; 4985 4986 ahc_outb(ahc, SCBPTR, i); 4987 scbid = ahc_inb(ahc, SCB_TAG); 4988 scbp = &ahc->scb_data->scbarray[scbid]; 4989 if (scbid < ahc->scb_data->numscbs 4990 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4991 ahc_add_curscb_to_free_list(ahc); 4992 } 4993 4994 /* 4995 * Go through the pending CCB list and look for 4996 * commands for this target that are still active. 4997 * These are other tagged commands that were 4998 * disconnected when the reset occured. 4999 */ 5000 { 5001 struct scb *scb; 5002 5003 scb = ahc->pending_ccbs.lh_first; 5004 while (scb != NULL) { 5005 scbp = scb; 5006 scb = scb->plinks.le_next; 5007 if (ahc_match_scb(scbp, target, channel, 5008 lun, tag, role)) { 5009 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5010 ahcsetccbstatus(scbp->xs, status); 5011 ahc_freeze_ccb(scbp); 5012 ahc_done(ahc, scbp); 5013 found++; 5014 } 5015 } 5016 } 5017 ahc_outb(ahc, SCBPTR, active_scb); 5018 return found; 5019 } 5020 5021 static int 5022 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5023 int lun, u_int tag, int stop_on_first, int remove, 5024 int save_state) 5025 { 5026 struct scb *scbp; 5027 u_int next; 5028 u_int prev; 5029 u_int count; 5030 u_int active_scb; 5031 5032 count = 0; 5033 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5034 prev = SCB_LIST_NULL; 5035 5036 if (save_state) { 5037 /* restore this when we're done */ 5038 active_scb = ahc_inb(ahc, SCBPTR); 5039 } else 5040 /* Silence compiler */ 5041 active_scb = SCB_LIST_NULL; 5042 5043 while (next != SCB_LIST_NULL) { 5044 u_int scb_index; 5045 5046 ahc_outb(ahc, SCBPTR, next); 5047 scb_index = ahc_inb(ahc, SCB_TAG); 5048 if (scb_index >= ahc->scb_data->numscbs) { 5049 panic("Disconnected List inconsistency. " 5050 "SCB index == %d, yet numscbs == %d.", 5051 scb_index, ahc->scb_data->numscbs); 5052 } 5053 scbp = &ahc->scb_data->scbarray[scb_index]; 5054 if (ahc_match_scb(scbp, target, channel, lun, 5055 tag, ROLE_INITIATOR)) { 5056 count++; 5057 if (remove) { 5058 next = 5059 ahc_rem_scb_from_disc_list(ahc, prev, next); 5060 } else { 5061 prev = next; 5062 next = ahc_inb(ahc, SCB_NEXT); 5063 } 5064 if (stop_on_first) 5065 break; 5066 } else { 5067 prev = next; 5068 next = ahc_inb(ahc, SCB_NEXT); 5069 } 5070 } 5071 if (save_state) 5072 ahc_outb(ahc, SCBPTR, active_scb); 5073 return (count); 5074 } 5075 5076 static u_int 5077 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5078 { 5079 u_int next; 5080 5081 ahc_outb(ahc, SCBPTR, scbptr); 5082 next = ahc_inb(ahc, SCB_NEXT); 5083 5084 ahc_outb(ahc, SCB_CONTROL, 0); 5085 5086 ahc_add_curscb_to_free_list(ahc); 5087 5088 if (prev != SCB_LIST_NULL) { 5089 ahc_outb(ahc, SCBPTR, prev); 5090 ahc_outb(ahc, SCB_NEXT, next); 5091 } else 5092 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5093 5094 return (next); 5095 } 5096 5097 static void 5098 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5099 { 5100 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5101 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5102 5103 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5104 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5105 } 5106 5107 /* 5108 * Manipulate the waiting for selection list and return the 5109 * scb that follows the one that we remove. 5110 */ 5111 static u_int 5112 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5113 { 5114 u_int curscb, next; 5115 5116 /* 5117 * Select the SCB we want to abort and 5118 * pull the next pointer out of it. 5119 */ 5120 curscb = ahc_inb(ahc, SCBPTR); 5121 ahc_outb(ahc, SCBPTR, scbpos); 5122 next = ahc_inb(ahc, SCB_NEXT); 5123 5124 /* Clear the necessary fields */ 5125 ahc_outb(ahc, SCB_CONTROL, 0); 5126 5127 ahc_add_curscb_to_free_list(ahc); 5128 5129 /* update the waiting list */ 5130 if (prev == SCB_LIST_NULL) { 5131 /* First in the list */ 5132 ahc_outb(ahc, WAITING_SCBH, next); 5133 5134 /* 5135 * Ensure we aren't attempting to perform 5136 * selection for this entry. 5137 */ 5138 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5139 } else { 5140 /* 5141 * Select the scb that pointed to us 5142 * and update its next pointer. 5143 */ 5144 ahc_outb(ahc, SCBPTR, prev); 5145 ahc_outb(ahc, SCB_NEXT, next); 5146 } 5147 5148 /* 5149 * Point us back at the original scb position. 5150 */ 5151 ahc_outb(ahc, SCBPTR, curscb); 5152 return next; 5153 } 5154 5155 static void 5156 ahc_clear_intstat(struct ahc_softc *ahc) 5157 { 5158 /* Clear any interrupt conditions this may have caused */ 5159 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5160 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5161 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5162 CLRREQINIT); 5163 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5164 } 5165 5166 static void 5167 ahc_reset_current_bus(struct ahc_softc *ahc) 5168 { 5169 u_int8_t scsiseq; 5170 5171 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5172 scsiseq = ahc_inb(ahc, SCSISEQ); 5173 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5174 DELAY(AHC_BUSRESET_DELAY); 5175 /* Turn off the bus reset */ 5176 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5177 5178 ahc_clear_intstat(ahc); 5179 5180 /* Re-enable reset interrupts */ 5181 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5182 } 5183 5184 static int 5185 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5186 { 5187 u_int initiator, target, max_scsiid; 5188 u_int sblkctl; 5189 u_int our_id; 5190 int found; 5191 int restart_needed; 5192 char cur_channel; 5193 5194 ahc->pending_device = NULL; 5195 5196 pause_sequencer(ahc); 5197 5198 /* 5199 * Run our command complete fifos to ensure that we perform 5200 * completion processing on any commands that 'completed' 5201 * before the reset occurred. 5202 */ 5203 ahc_run_qoutfifo(ahc); 5204 5205 /* 5206 * Reset the bus if we are initiating this reset 5207 */ 5208 sblkctl = ahc_inb(ahc, SBLKCTL); 5209 cur_channel = 'A'; 5210 if ((ahc->features & AHC_TWIN) != 0 5211 && ((sblkctl & SELBUSB) != 0)) 5212 cur_channel = 'B'; 5213 if (cur_channel != channel) { 5214 /* Case 1: Command for another bus is active 5215 * Stealthily reset the other bus without 5216 * upsetting the current bus. 5217 */ 5218 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5219 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5220 ahc_outb(ahc, SCSISEQ, 5221 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5222 if (initiate_reset) 5223 ahc_reset_current_bus(ahc); 5224 ahc_clear_intstat(ahc); 5225 ahc_outb(ahc, SBLKCTL, sblkctl); 5226 restart_needed = FALSE; 5227 } else { 5228 /* Case 2: A command from this bus is active or we're idle */ 5229 ahc_clear_msg_state(ahc); 5230 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5231 ahc_outb(ahc, SCSISEQ, 5232 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5233 if (initiate_reset) 5234 ahc_reset_current_bus(ahc); 5235 ahc_clear_intstat(ahc); 5236 5237 /* 5238 * Since we are going to restart the sequencer, avoid 5239 * a race in the sequencer that could cause corruption 5240 * of our Q pointers by starting over from index 0. 5241 */ 5242 ahc->qoutfifonext = 0; 5243 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5244 ahc_outb(ahc, SDSCB_QOFF, 0); 5245 else 5246 ahc_outb(ahc, QOUTPOS, 0); 5247 restart_needed = TRUE; 5248 } 5249 5250 /* 5251 * Clean up all the state information for the 5252 * pending transactions on this bus. 5253 */ 5254 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5255 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5256 ROLE_UNKNOWN, XS_RESET); 5257 if (channel == 'B') { 5258 our_id = ahc->our_id_b; 5259 } else { 5260 our_id = ahc->our_id; 5261 } 5262 5263 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5264 5265 /* 5266 * Revert to async/narrow transfers until we renegotiate. 5267 */ 5268 for (target = 0; target <= max_scsiid; target++) { 5269 5270 if (ahc->enabled_targets[target] == NULL) 5271 continue; 5272 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5273 struct ahc_devinfo devinfo; 5274 5275 ahc_compile_devinfo(&devinfo, target, initiator, 5276 AHC_LUN_WILDCARD, 5277 channel, ROLE_UNKNOWN); 5278 ahc_set_width(ahc, &devinfo, 5279 MSG_EXT_WDTR_BUS_8_BIT, 5280 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5281 ahc_set_syncrate(ahc, &devinfo, 5282 /*syncrate*/NULL, /*period*/0, 5283 /*offset*/0, AHC_TRANS_CUR, 5284 /*paused*/TRUE, FALSE); 5285 } 5286 } 5287 5288 if (restart_needed) 5289 restart_sequencer(ahc); 5290 else 5291 unpause_sequencer(ahc); 5292 return found; 5293 } 5294 5295 static int 5296 ahc_match_scb(struct scb *scb, int target, char channel, 5297 int lun, u_int tag, role_t role) 5298 { 5299 int targ = SCB_TARGET(scb); 5300 char chan = SCB_CHANNEL(scb); 5301 int slun = SCB_LUN(scb); 5302 int match; 5303 5304 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5305 if (match != 0) 5306 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5307 if (match != 0) 5308 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5309 5310 return match; 5311 } 5312 5313 static void 5314 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5315 { 5316 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5317 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5318 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5319 ahc->msgout_buf[ahc->msgout_index++] = period; 5320 ahc->msgout_buf[ahc->msgout_index++] = offset; 5321 ahc->msgout_len += 5; 5322 } 5323 5324 static void 5325 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5326 { 5327 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5328 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5329 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5330 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5331 ahc->msgout_len += 4; 5332 } 5333 5334 static void 5335 ahc_calc_residual(struct scb *scb) 5336 { 5337 struct hardware_scb *hscb; 5338 5339 hscb = scb->hscb; 5340 5341 /* 5342 * If the disconnected flag is still set, this is bogus 5343 * residual information left over from a sequencer 5344 * pagin/pageout, so ignore this case. 5345 */ 5346 if ((scb->hscb->control & DISCONNECTED) == 0) { 5347 u_int32_t resid; 5348 int resid_sgs; 5349 int sg; 5350 5351 /* 5352 * Remainder of the SG where the transfer 5353 * stopped. 5354 */ 5355 resid = (hscb->residual_data_count[2] << 16) 5356 | (hscb->residual_data_count[1] <<8) 5357 | (hscb->residual_data_count[0]); 5358 5359 /* 5360 * Add up the contents of all residual 5361 * SG segments that are after the SG where 5362 * the transfer stopped. 5363 */ 5364 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5365 sg = scb->sg_count - resid_sgs; 5366 while (resid_sgs > 0) { 5367 5368 resid += le32toh(scb->sg_list[sg].len); 5369 sg++; 5370 resid_sgs--; 5371 } 5372 scb->xs->resid = resid; 5373 } 5374 5375 /* 5376 * Clean out the residual information in this SCB for its 5377 * next consumer. 5378 */ 5379 hscb->residual_SG_count = 0; 5380 5381 #ifdef AHC_DEBUG 5382 if (ahc_debug & AHC_SHOWMISC) { 5383 scsi_print_addr(scb->xs->sc_link); 5384 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5385 } 5386 #endif 5387 } 5388 5389 static void 5390 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5391 { 5392 struct scb *scb; 5393 int pending_ccb_count; 5394 int i; 5395 u_int saved_scbptr; 5396 5397 /* 5398 * Traverse the pending SCB list and ensure that all of the 5399 * SCBs there have the proper settings. 5400 */ 5401 scb = LIST_FIRST(&ahc->pending_ccbs); 5402 pending_ccb_count = 0; 5403 while (scb != NULL) { 5404 struct ahc_devinfo devinfo; 5405 struct scsipi_xfer *xs; 5406 struct scb *pending_scb; 5407 struct hardware_scb *pending_hscb; 5408 struct ahc_initiator_tinfo *tinfo; 5409 struct tmode_tstate *tstate; 5410 u_int our_id, remote_id; 5411 5412 xs = scb->xs; 5413 pending_scb = scb; 5414 pending_hscb = pending_scb->hscb; 5415 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5416 ? ahc->our_id_b : ahc->our_id; 5417 remote_id = xs->sc_link->scsipi_scsi.target; 5418 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5419 SCB_LUN(pending_scb), 5420 SCB_CHANNEL(pending_scb), 5421 ROLE_UNKNOWN); 5422 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5423 our_id, remote_id, &tstate); 5424 pending_hscb->control &= ~ULTRAENB; 5425 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5426 pending_hscb->control |= ULTRAENB; 5427 pending_hscb->scsirate = tinfo->scsirate; 5428 pending_hscb->scsioffset = tinfo->current.offset; 5429 pending_ccb_count++; 5430 scb = LIST_NEXT(scb, plinks); 5431 } 5432 5433 if (pending_ccb_count == 0) 5434 return; 5435 5436 saved_scbptr = ahc_inb(ahc, SCBPTR); 5437 /* Ensure that the hscbs down on the card match the new information */ 5438 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5439 u_int scb_tag; 5440 5441 ahc_outb(ahc, SCBPTR, i); 5442 scb_tag = ahc_inb(ahc, SCB_TAG); 5443 if (scb_tag != SCB_LIST_NULL) { 5444 struct ahc_devinfo devinfo; 5445 struct scb *pending_scb; 5446 struct scsipi_xfer *xs; 5447 struct hardware_scb *pending_hscb; 5448 struct ahc_initiator_tinfo *tinfo; 5449 struct tmode_tstate *tstate; 5450 u_int our_id, remote_id; 5451 u_int control; 5452 5453 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5454 if (pending_scb->flags == SCB_FREE) 5455 continue; 5456 pending_hscb = pending_scb->hscb; 5457 xs = pending_scb->xs; 5458 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5459 ? ahc->our_id_b : ahc->our_id; 5460 remote_id = xs->sc_link->scsipi_scsi.target; 5461 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5462 SCB_LUN(pending_scb), 5463 SCB_CHANNEL(pending_scb), 5464 ROLE_UNKNOWN); 5465 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5466 our_id, remote_id, &tstate); 5467 control = ahc_inb(ahc, SCB_CONTROL); 5468 control &= ~ULTRAENB; 5469 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5470 control |= ULTRAENB; 5471 ahc_outb(ahc, SCB_CONTROL, control); 5472 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5473 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5474 } 5475 } 5476 ahc_outb(ahc, SCBPTR, saved_scbptr); 5477 } 5478 5479 #if UNUSED 5480 static void 5481 ahc_dump_targcmd(struct target_cmd *cmd) 5482 { 5483 u_int8_t *byte; 5484 u_int8_t *last_byte; 5485 int i; 5486 5487 byte = &cmd->initiator_channel; 5488 /* Debugging info for received commands */ 5489 last_byte = &cmd[1].initiator_channel; 5490 5491 i = 0; 5492 while (byte < last_byte) { 5493 if (i == 0) 5494 printf("\t"); 5495 printf("%#x", *byte++); 5496 i++; 5497 if (i == 8) { 5498 printf("\n"); 5499 i = 0; 5500 } else { 5501 printf(", "); 5502 } 5503 } 5504 } 5505 #endif 5506 5507 static void 5508 ahc_shutdown(void *arg) 5509 { 5510 struct ahc_softc *ahc; 5511 int i; 5512 u_int sxfrctl1_a, sxfrctl1_b; 5513 5514 ahc = (struct ahc_softc *)arg; 5515 5516 pause_sequencer(ahc); 5517 5518 /* 5519 * Preserve the value of the SXFRCTL1 register for all channels. 5520 * It contains settings that affect termination and we don't want 5521 * to disturb the integrity of the bus during shutdown in case 5522 * we are in a multi-initiator setup. 5523 */ 5524 sxfrctl1_b = 0; 5525 if ((ahc->features & AHC_TWIN) != 0) { 5526 u_int sblkctl; 5527 5528 sblkctl = ahc_inb(ahc, SBLKCTL); 5529 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5530 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5531 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5532 } 5533 5534 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5535 5536 /* This will reset most registers to 0, but not all */ 5537 ahc_reset(ahc); 5538 5539 if ((ahc->features & AHC_TWIN) != 0) { 5540 u_int sblkctl; 5541 5542 sblkctl = ahc_inb(ahc, SBLKCTL); 5543 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5544 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5545 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5546 } 5547 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5548 5549 ahc_outb(ahc, SCSISEQ, 0); 5550 ahc_outb(ahc, SXFRCTL0, 0); 5551 ahc_outb(ahc, DSPCISTATUS, 0); 5552 5553 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5554 ahc_outb(ahc, i, 0); 5555 } 5556 5557 #if defined(AHC_DEBUG) && 0 5558 static void 5559 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5560 { 5561 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5562 5563 printf("\tcurrent:\n"); 5564 printf("\t\twidth %u period %u offset %u flags %x\n", 5565 tinfo->current.width, tinfo->current.period, 5566 tinfo->current.offset, tinfo->current.ppr_flags); 5567 5568 printf("\tgoal:\n"); 5569 printf("\t\twidth %u period %u offset %u flags %x\n", 5570 tinfo->goal.width, tinfo->goal.period, 5571 tinfo->goal.offset, tinfo->goal.ppr_flags); 5572 5573 printf("\tuser:\n"); 5574 printf("\t\twidth %u period %u offset %u flags %x\n", 5575 tinfo->user.width, tinfo->user.period, 5576 tinfo->user.offset, tinfo->user.ppr_flags); 5577 } 5578 #endif 5579 5580 static void 5581 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5582 { 5583 struct scsipi_inquiry_data *inq; 5584 struct ahc_devinfo devinfo; 5585 int target_id, our_id; 5586 5587 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5588 return; 5589 5590 target_id = xs->sc_link->scsipi_scsi.target; 5591 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5592 5593 /* 5594 * Sneak a look at the results of the SCSI Inquiry 5595 * command and see if we can do Tagged queing. This 5596 * should really be done by the higher level drivers. 5597 */ 5598 inq = (struct scsipi_inquiry_data *)xs->data; 5599 if ((inq->flags & SID_CmdQue) && !(ahc_istagged_device(ahc, xs))) { 5600 printf("%s: target %d using tagged queuing\n", 5601 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5602 5603 ahc_compile_devinfo(&devinfo, 5604 our_id, target_id, xs->sc_link->scsipi_scsi.lun, 5605 SIM_CHANNEL(ahc, xs->sc_link), ROLE_INITIATOR); 5606 ahc_set_tags(ahc, &devinfo, TRUE); 5607 5608 if (ahc->scb_data->maxhscbs >= 16 || 5609 (ahc->flags & AHC_PAGESCBS)) { 5610 /* Default to 16 tags */ 5611 xs->sc_link->openings += 14; 5612 } else { 5613 /* 5614 * Default to 4 tags on whimpy 5615 * cards that don't have much SCB 5616 * space and can't page. This prevents 5617 * a single device from hogging all 5618 * slots. We should really have a better 5619 * way of providing fairness. 5620 */ 5621 xs->sc_link->openings += 2; 5622 } 5623 } 5624 } 5625 5626 static int 5627 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5628 { 5629 char channel; 5630 u_int our_id, target; 5631 struct tmode_tstate *tstate; 5632 struct ahc_devinfo devinfo; 5633 5634 channel = SIM_CHANNEL(ahc, xs->sc_link); 5635 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5636 target = xs->sc_link->scsipi_scsi.target; 5637 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5638 5639 ahc_compile_devinfo(&devinfo, our_id, target, 5640 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5641 5642 return (tstate->tagenable & devinfo.target_mask); 5643 } 5644
Indexes created Wed Oct 01 13:09:50 GMT 2025