aic7xxx.c revision 1.5
1 /* $NetBSD: aic7xxx.c,v 1.5 1996/03/29 00:24:58 mycroft Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Copyright (c) 1994, 1995 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Product specific probe and attach routines can be found in: 9 * i386/isa/aic7770.c 27/284X and aic7770 motherboard controllers 10 * /pci/aic7870.c 294x and aic7870 motherboard controllers 11 * 12 * Portions of this driver are based on the FreeBSD 1742 Driver: 13 * 14 * Written by Julian Elischer (julian (at) tfs.com) 15 * for TRW Financial Systems for use under the MACH(2.5) operating system. 16 * 17 * TRW Financial Systems, in accordance with their agreement with Carnegie 18 * Mellon University, makes this software available to CMU to distribute 19 * or use in any manner that they see fit as long as this message is kept with 20 * the software. For this reason TFS also grants any other persons or 21 * organisations permission to use or modify this software. 22 * 23 * TFS supplies this software to be publicly redistributed 24 * on the understanding that TFS is not responsible for the correct 25 * functioning of this software in any circumstances. 26 * 27 * commenced: Sun Sep 27 18:14:01 PDT 1992 28 */ 29 /* 30 * TODO: 31 * Add target reset capabilities 32 * Implement Target Mode 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/proc.h> 43 #include <sys/user.h> 44 45 #include <machine/pio.h> 46 47 #include <scsi/scsi_all.h> 48 #include <scsi/scsi_debug.h> 49 #include <scsi/scsiconf.h> 50 51 #include <dev/ic/aic7xxxvar.h> 52 53 int ahc_init __P((struct ahc_softc *)); 54 void ahc_loadseq __P((int)); 55 int ahc_scsi_cmd __P((struct scsi_xfer *)); 56 void ahc_timeout __P((void *)); 57 void ahc_done __P((struct ahc_softc *, struct ahc_scb *)); 58 struct ahc_scb *ahc_get_scb __P((struct ahc_softc *, int)); 59 void ahc_free_scb __P((struct ahc_softc *, struct ahc_scb *, int)); 60 void ahc_abort_scb __P((struct ahc_softc *, struct ahc_scb *)); 61 void ahcminphys __P((struct buf *)); 62 int ahc_poll __P((struct ahc_softc *, struct scsi_xfer *, int)); 63 64 /* Different debugging levels */ 65 #ifdef AHC_DEBUG 66 #define AHC_SHOWMISC 0x0001 67 #define AHC_SHOWCMDS 0x0002 68 #define AHC_SHOWSCBS 0x0004 69 int ahc_debug = AHC_SHOWMISC; 70 #endif 71 72 #ifdef AHC_MORE_DEBUG 73 #define DEBUGLEVEL -1 74 #define DEBUGTARGET 0x0 75 #endif 76 77 /**** bit definitions for SCSIDEF ****/ 78 #define HSCSIID 0x07 /* our SCSI ID */ 79 #define HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 80 81 struct scsi_adapter ahc_switch = { 82 ahc_scsi_cmd, 83 ahcminphys, 84 0, 85 0, 86 }; 87 88 89 /* the below structure is so we have a default dev struct for our link struct */ 90 struct scsi_device ahc_dev = { 91 NULL, /* Use default error handler */ 92 NULL, /* have a queue, served by this */ 93 NULL, /* have no async handler */ 94 NULL, /* Use default 'done' routine */ 95 }; 96 97 98 /* 99 * All of these should be in a separate header file shared by the sequencer 100 * code and the kernel level driver. The only catch is that we would need to 101 * add an additional 0xc00 offset when using them in the kernel driver. The 102 * aic7770 assembler must be modified to allow include files as well. All 103 * page numbers refer to the Adaptec AIC-7770 Data Book available from 104 * Adaptec's Technical Documents Department 1-800-934-2766 105 */ 106 107 /* -------------------- AIC-7770 offset definitions ----------------------- */ 108 109 /* 110 * SCSI Sequence Control (p. 3-11). 111 * Each bit, when set starts a specific SCSI sequence on the bus 112 */ 113 #define SCSISEQ 0xc00ul 114 #define TEMODEO 0x80 115 #define ENSELO 0x40 116 #define ENSELI 0x20 117 #define ENRSELI 0x10 118 #define ENAUTOATNO 0x08 119 #define ENAUTOATNI 0x04 120 #define ENAUTOATNP 0x02 121 #define SCSIRSTO 0x01 122 123 /* 124 * SCSI Transfer Control 1 Register (pp. 3-14,15). 125 * Controls the SCSI module data path. 126 */ 127 #define SXFRCTL1 0xc02ul 128 #define BITBUCKET 0x80 129 #define SWRAPEN 0x40 130 #define ENSPCHK 0x20 131 #define STIMESEL 0x18 132 #define ENSTIMER 0x04 133 #define ACTNEGEN 0x02 134 #define STPWEN 0x01 /* Powered Termination */ 135 136 /* 137 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 138 * Set bits in this register enable the corresponding 139 * interrupt source. 140 */ 141 #define SIMODE1 0xc11ul 142 #define ENSELTIMO 0x80 143 #define ENATNTARG 0x40 144 #define ENSCSIRST 0x20 145 #define ENPHASEMIS 0x10 146 #define ENBUSFREE 0x08 147 #define ENSCSIPERR 0x04 148 #define ENPHASECHG 0x02 149 #define ENREQINIT 0x01 150 151 /* 152 * SCSI Control Signal Read Register (p. 3-15). 153 * Reads the actual state of the SCSI bus pins 154 */ 155 #define SCSISIGI 0xc03ul 156 #define CDI 0x80 157 #define IOI 0x40 158 #define MSGI 0x20 159 #define ATNI 0x10 160 #define SELI 0x08 161 #define BSYI 0x04 162 #define REQI 0x02 163 #define ACKI 0x01 164 165 /* 166 * SCSI Contol Signal Write Register (p. 3-16). 167 * Writing to this register modifies the control signals on the bus. Only 168 * those signals that are allowed in the current mode (Initiator/Target) are 169 * asserted. 170 */ 171 #define SCSISIGO 0xc03ul 172 #define CDO 0x80 173 #define IOO 0x40 174 #define MSGO 0x20 175 #define ATNO 0x10 176 #define SELO 0x08 177 #define BSYO 0x04 178 #define REQO 0x02 179 #define ACKO 0x01 180 181 /* XXX document this thing */ 182 #define SCSIRATE 0xc04ul 183 184 /* 185 * SCSI ID (p. 3-18). 186 * Contains the ID of the board and the current target on the 187 * selected channel 188 */ 189 #define SCSIID 0xc05ul 190 #define TID 0xf0 /* Target ID mask */ 191 #define OID 0x0f /* Our ID mask */ 192 193 /* 194 * SCSI Status 0 (p. 3-21) 195 * Contains one set of SCSI Interrupt codes 196 * These are most likely of interest to the sequencer 197 */ 198 #define SSTAT0 0xc0bul 199 #define TARGET 0x80 /* Board is a target */ 200 #define SELDO 0x40 /* Selection Done */ 201 #define SELDI 0x20 /* Board has been selected */ 202 #define SELINGO 0x10 /* Selection In Progress */ 203 #define SWRAP 0x08 /* 24bit counter wrap */ 204 #define SDONE 0x04 /* STCNT = 0x000000 */ 205 #define SPIORDY 0x02 /* SCSI PIO Ready */ 206 #define DMADONE 0x01 /* DMA transfer completed */ 207 208 /* 209 * Clear SCSI Interrupt 1 (p. 3-23) 210 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 211 */ 212 #define CLRSINT1 0xc0cul 213 #define CLRSELTIMEO 0x80 214 #define CLRATNO 0x40 215 #define CLRSCSIRSTI 0x20 216 /* UNUSED 0x10 */ 217 #define CLRBUSFREE 0x08 218 #define CLRSCSIPERR 0x04 219 #define CLRPHASECHG 0x02 220 #define CLRREQINIT 0x01 221 222 /* 223 * SCSI Status 1 (p. 3-24) 224 * These interrupt bits are of interest to the kernel driver 225 */ 226 #define SSTAT1 0xc0cul 227 #define SELTO 0x80 228 #define ATNTARG 0x40 229 #define SCSIRSTI 0x20 230 #define PHASEMIS 0x10 231 #define BUSFREE 0x08 232 #define SCSIPERR 0x04 233 #define PHASECHG 0x02 234 #define REQINIT 0x01 235 236 /* 237 * Selection/Reselection ID (p. 3-31) 238 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 239 * device did not set its own ID. 240 */ 241 #define SELID 0xc19ul 242 #define SELID_MASK 0xf0 243 #define ONEBIT 0x08 244 /* UNUSED 0x07 */ 245 246 /* 247 * SCSI Block Control (p. 3-32) 248 * Controls Bus type and channel selection. In a twin channel configuration 249 * addresses 0x00-0x1e are gated to the appropriate channel based on this 250 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 251 * on a wide bus. 252 */ 253 #define SBLKCTL 0xc1ful 254 /* UNUSED 0xc0 */ 255 #define AUTOFLUSHDIS 0x20 256 /* UNUSED 0x10 */ 257 #define SELBUSB 0x08 258 /* UNUSED 0x04 */ 259 #define SELWIDE 0x02 260 /* UNUSED 0x01 */ 261 262 /* 263 * Sequencer Control (p. 3-33) 264 * Error detection mode and speed configuration 265 */ 266 #define SEQCTL 0xc60ul 267 #define PERRORDIS 0x80 268 #define PAUSEDIS 0x40 269 #define FAILDIS 0x20 270 #define FASTMODE 0x10 271 #define BRKADRINTEN 0x08 272 #define STEP 0x04 273 #define SEQRESET 0x02 274 #define LOADRAM 0x01 275 276 /* 277 * Sequencer RAM Data (p. 3-34) 278 * Single byte window into the Scratch Ram area starting at the address 279 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 280 * four bytes in sucessesion. The SEQADDRs will increment after the most 281 * significant byte is written 282 */ 283 #define SEQRAM 0xc61ul 284 285 /* 286 * Sequencer Address Registers (p. 3-35) 287 * Only the first bit of SEQADDR1 holds addressing information 288 */ 289 #define SEQADDR0 0xc62ul 290 #define SEQADDR1 0xc63ul 291 #define SEQADDR1_MASK 0x01 292 293 /* 294 * Accumulator 295 * We cheat by passing arguments in the Accumulator up to the kernel driver 296 */ 297 #define ACCUM 0xc64ul 298 299 #define SINDEX 0xc65ul 300 301 /* 302 * Board Control (p. 3-43) 303 */ 304 #define BCTL 0xc84ul 305 /* RSVD 0xf0 */ 306 #define ACE 0x08 /* Support for external processors */ 307 /* RSVD 0x06 */ 308 #define ENABLE 0x01 309 310 /* 311 * Host Control (p. 3-47) R/W 312 * Overal host control of the device. 313 */ 314 #define HCNTRL 0xc87ul 315 /* UNUSED 0x80 */ 316 #define POWRDN 0x40 317 /* UNUSED 0x20 */ 318 #define SWINT 0x10 319 #define IRQMS 0x08 320 #define PAUSE 0x04 321 #define INTEN 0x02 322 #define CHIPRST 0x01 323 324 /* 325 * SCB Pointer (p. 3-49) 326 * Gate one of the four SCBs into the SCBARRAY window. 327 */ 328 #define SCBPTR 0xc90ul 329 330 /* 331 * Interrupt Status (p. 3-50) 332 * Status for system interrupts 333 */ 334 #define INTSTAT 0xc91ul 335 #define SEQINT_MASK 0xf0 /* SEQINT Status Codes */ 336 #define BAD_PHASE 0x00 337 #define SEND_REJECT 0x10 338 #define NO_IDENT 0x20 339 #define NO_MATCH 0x30 340 #define MSG_SDTR 0x40 341 #define MSG_WDTR 0x50 342 #define MSG_REJECT 0x60 343 #define BAD_STATUS 0x70 344 #define RESIDUAL 0x80 345 #define ABORT_TAG 0x90 346 #define BRKADRINT 0x08 347 #define SCSIINT 0x04 348 #define CMDCMPLT 0x02 349 #define SEQINT 0x01 350 #define INT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT) 351 352 /* 353 * Hard Error (p. 3-53) 354 * Reporting of catastrophic errors. You usually cannot recover from 355 * these without a full board reset. 356 */ 357 #define ERROR 0xc92ul 358 /* UNUSED 0xf0 */ 359 #define PARERR 0x08 360 #define ILLOPCODE 0x04 361 #define ILLSADDR 0x02 362 #define ILLHADDR 0x01 363 364 /* 365 * Clear Interrupt Status (p. 3-52) 366 */ 367 #define CLRINT 0xc92ul 368 #define CLRBRKADRINT 0x08 369 #define CLRSCSIINT 0x04 370 #define CLRCMDINT 0x02 371 #define CLRSEQINT 0x01 372 373 /* 374 * SCB Auto Increment (p. 3-59) 375 * Byte offset into the SCB Array and an optional bit to allow auto 376 * incrementing of the address during download and upload operations 377 */ 378 #define SCBCNT 0xc9aul 379 #define SCBAUTO 0x80 380 #define SCBCNT_MASK 0x1f 381 382 /* 383 * Queue In FIFO (p. 3-60) 384 * Input queue for queued SCBs (commands that the seqencer has yet to start) 385 */ 386 #define QINFIFO 0xc9bul 387 388 /* 389 * Queue In Count (p. 3-60) 390 * Number of queued SCBs 391 */ 392 #define QINCNT 0xc9cul 393 394 /* 395 * Queue Out FIFO (p. 3-61) 396 * Queue of SCBs that have completed and await the host 397 */ 398 #define QOUTFIFO 0xc9dul 399 400 /* 401 * Queue Out Count (p. 3-61) 402 * Number of queued SCBs in the Out FIFO 403 */ 404 #define QOUTCNT 0xc9eul 405 406 #define SCBARRAY 0xca0ul 407 408 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 409 410 /* --------------------- AIC-7870-only definitions -------------------- */ 411 412 #define DSPCISTATUS 0xc86ul 413 414 /* ---------------------- Scratch RAM Offsets ------------------------- */ 415 /* These offsets are either to values that are initialized by the board's 416 * BIOS or are specified by the Linux sequencer code. If I can figure out 417 * how to read the EISA configuration info at probe time, the cards could 418 * be run without BIOS support installed 419 */ 420 421 /* 422 * 1 byte per target starting at this address for configuration values 423 */ 424 #define HA_TARG_SCRATCH 0xc20ul 425 426 /* 427 * The sequencer will stick the frist byte of any rejected message here so 428 * we can see what is getting thrown away. 429 */ 430 #define HA_REJBYTE 0xc31ul 431 432 /* 433 * Length of pending message 434 */ 435 #define HA_MSG_LEN 0xc34ul 436 437 /* 438 * message body 439 */ 440 #define HA_MSG_START 0xc35ul /* outgoing message body */ 441 442 /* 443 * These are offsets into the card's scratch ram. Some of the values are 444 * specified in the AHA2742 technical reference manual and are initialized 445 * by the BIOS at boot time. 446 */ 447 #define HA_ARG_1 0xc4aul 448 #define HA_RETURN_1 0xc4aul 449 #define SEND_SENSE 0x80 450 #define SEND_WDTR 0x80 451 #define SEND_SDTR 0x80 452 #define SEND_REJ 0x40 453 454 #define HA_SIGSTATE 0xc4bul 455 456 #define HA_SCBCOUNT 0xc52ul 457 #define HA_FLAGS 0xc53ul 458 #define SINGLE_BUS 0x00 459 #define TWIN_BUS 0x01 460 #define WIDE_BUS 0x02 461 #define ACTIVE_MSG 0x20 462 #define IDENTIFY_SEEN 0x40 463 #define RESELECTING 0x80 464 465 #define HA_ACTIVE0 0xc54ul 466 #define HA_ACTIVE1 0xc55ul 467 #define SAVED_TCL 0xc56ul 468 #define WAITING_SCBH 0xc57ul 469 #define WAITING_SCBT 0xc58ul 470 471 #define HA_SCSICONF 0xc5aul 472 #define INTDEF 0xc5cul 473 #define HA_HOSTCONF 0xc5dul 474 475 #define MSG_ABORT 0x06 476 #define BUS_8_BIT 0x00 477 #define BUS_16_BIT 0x01 478 #define BUS_32_BIT 0x02 479 480 /* 481 * Since the sequencer can disable pausing in a critical section, we 482 * must loop until it actually stops. 483 * XXX Should add a timeout in here?? 484 */ 485 #define PAUSE_SEQUENCER(ahc) \ 486 do { \ 487 outb(HCNTRL + ahc->sc_iobase, ahc->pause); \ 488 while ((inb(HCNTRL + ahc->sc_iobase) & PAUSE) == 0) \ 489 ; \ 490 } while (0) 491 492 #define UNPAUSE_SEQUENCER(ahc) \ 493 do { \ 494 outb(HCNTRL + ahc->sc_iobase, ahc->unpause); \ 495 } while (0) 496 497 /* 498 * Restart the sequencer program from address zero 499 * XXX Should add a timeout in here?? 500 */ 501 #define RESET_SEQUENCER(ahc) \ 502 do { \ 503 do { \ 504 outb(SEQCTL + ahc->sc_iobase, SEQRESET|FASTMODE); \ 505 } while (inb(SEQADDR0 + ahc->sc_iobase) != 0 && \ 506 inb(SEQADDR1 + ahc->sc_iobase) != 0); \ 507 } while (0) 508 509 #define RESTART_SEQUENCER(ahc) \ 510 do { \ 511 RESET_SEQUENCER(ahc); \ 512 UNPAUSE_SEQUENCER(ahc); \ 513 } while (0) 514 515 #ifdef AHC_DEBUG 516 void 517 ahc_print_scb(scb) 518 struct ahc_scb *scb; 519 { 520 521 printf("scb:0x%x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%x\n", 522 scb, 523 scb->control, 524 scb->target_channel_lun, 525 scb->cmdlen, 526 scb->cmdpointer); 527 printf("\tdatlen:%d data:0x%x res:0x%x segs:0x%x segp:0x%x\n", 528 scb->datalen[2] << 16 | scb->datalen[1] << 8 | scb->datalen[0], 529 scb->data, 530 scb->RESERVED[1] << 8 | scb->RESERVED[0], 531 scb->SG_segment_count, 532 scb->SG_list_pointer); 533 printf("\tsg_addr:%x sg_len:%d\n", 534 scb->ahc_dma[0].seg_addr, 535 scb->ahc_dma[0].seg_len); 536 printf(" size:%d\n", 537 (int)&scb->next_waiting - (int)scb); 538 } 539 540 void 541 ahc_print_active_scb(ahc) 542 struct ahc_softc *ahc; 543 { 544 int iobase = ahc->sc_iobase; 545 int scb_index; 546 547 PAUSE_SEQUENCER(ahc); 548 scb_index = inb(SCBPTR + iobase); 549 UNPAUSE_SEQUENCER(ahc); 550 551 ahc_print_scb(ahc->scbarray[scb_index]); 552 } 553 #endif 554 555 #define PARERR 0x08 556 #define ILLOPCODE 0x04 557 #define ILLSADDR 0x02 558 #define ILLHADDR 0x01 559 560 static struct { 561 u_char errno; 562 char *errmesg; 563 } hard_error[] = { 564 { ILLHADDR, "Illegal Host Access" }, 565 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 566 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 567 { PARERR, "Sequencer Ram Parity Error" } 568 }; 569 570 571 /* 572 * Valid SCSIRATE values. (p. 3-17) 573 * Provides a mapping of tranfer periods in ns to the proper value to 574 * stick in the scsiscfr reg to use that transfer rate. 575 */ 576 static struct { 577 u_char sxfr; 578 int period; /* in ns */ 579 char *rate; 580 } ahc_syncrates[] = { 581 { 0x00, 100, "10.0" }, 582 { 0x10, 125, "8.0" }, 583 { 0x20, 150, "6.67" }, 584 { 0x30, 175, "5.7" }, 585 { 0x40, 200, "5.0" }, 586 { 0x50, 225, "4.4" }, 587 { 0x60, 250, "4.0" }, 588 { 0x70, 275, "3.6" } 589 }; 590 591 static int ahc_num_syncrates = 592 sizeof(ahc_syncrates) / sizeof(ahc_syncrates[0]); 593 594 /* 595 * Check if the device can be found at the port given 596 * and if so, determine configuration and set it up for further work. 597 */ 598 599 int 600 ahcprobe(ahc, iobase) 601 struct ahc_softc *ahc; 602 int iobase; 603 { 604 605 ahc->sc_iobase = iobase; 606 607 /* 608 * Try to initialize a unit at this location 609 * reset the AIC-7770, read its registers, 610 * and fill in the dev structure accordingly 611 */ 612 613 if (ahc_init(ahc) != 0) 614 return (0); 615 616 return (1); 617 } 618 619 620 /* 621 * Look up the valid period to SCSIRATE conversion in our table. 622 */ 623 static u_char 624 ahc_scsirate(offset, period, ahc, target) 625 u_char offset; 626 int period; 627 struct ahc_softc *ahc; 628 int target; 629 { 630 int i; 631 632 for (i = 0; i < ahc_num_syncrates; i++) { 633 if ((ahc_syncrates[i].period - period) >= 0) { 634 printf("%s: target %d synchronous at %sMB/s, " 635 "offset = %d\n", 636 ahc->sc_dev.dv_xname, target, 637 ahc_syncrates[i].rate, offset); 638 #ifdef AHC_DEBUG 639 #endif /* AHC_DEBUG */ 640 return ((ahc_syncrates[i].sxfr) | (offset & 0x0f)); 641 } 642 } 643 644 /* Default to asyncronous transfers. Also reject this SDTR request. */ 645 printf("%s: target %d using asyncronous transfers\n", 646 ahc->sc_dev.dv_xname, target); 647 return (0); 648 #ifdef AHC_DEBUG 649 #endif /* AHC_DEBUG */ 650 } 651 652 int 653 ahcprint(aux, name) 654 void *aux; 655 char *name; 656 { 657 658 if (name != NULL) 659 printf("%s: scsibus ", name); 660 return UNCONF; 661 } 662 663 /* 664 * Attach all the sub-devices we can find 665 */ 666 int 667 ahcattach(ahc) 668 struct ahc_softc *ahc; 669 { 670 671 TAILQ_INIT(&ahc->free_scb); 672 673 /* 674 * fill in the prototype scsi_link. 675 */ 676 ahc->sc_link.adapter_softc = ahc; 677 ahc->sc_link.adapter_target = ahc->ahc_scsi_dev; 678 ahc->sc_link.adapter = &ahc_switch; 679 ahc->sc_link.device = &ahc_dev; 680 ahc->sc_link.openings = 1; 681 ahc->sc_link.flags = DEBUGLEVEL; 682 ahc->sc_link.quirks = 0; 683 684 /* 685 * ask the adapter what subunits are present 686 */ 687 printf("%s: Probing channel A\n", ahc->sc_dev.dv_xname); 688 config_found((void *)ahc, &ahc->sc_link, ahcprint); 689 if (ahc->type & AHC_TWIN) { 690 /* Configure the second scsi bus */ 691 ahc->sc_link_b = ahc->sc_link; 692 /* XXXX Didn't do this before. */ 693 ahc->sc_link_b.adapter_target = ahc->ahc_scsi_dev_b; 694 ahc->sc_link_b.quirks = 0x0008; /**/ 695 printf("%s: Probing channel B\n", ahc->sc_dev.dv_xname); 696 config_found((void *)ahc, &ahc->sc_link_b, ahcprint); 697 } 698 699 return 1; 700 } 701 702 void 703 ahc_send_scb(ahc, scb) 704 struct ahc_softc *ahc; 705 struct ahc_scb *scb; 706 { 707 int iobase = ahc->sc_iobase; 708 709 PAUSE_SEQUENCER(ahc); 710 outb(QINFIFO + iobase, scb->position); 711 UNPAUSE_SEQUENCER(ahc); 712 } 713 714 static void 715 ahc_getscb(iobase, scb) 716 int iobase; 717 struct ahc_scb *scb; 718 { 719 720 outb(SCBCNT + iobase, SCBAUTO); 721 insb(SCBARRAY + iobase, scb, SCB_UP_SIZE); 722 outb(SCBCNT + iobase, 0); 723 } 724 725 /* 726 * Catch an interrupt from the adaptor 727 */ 728 int 729 ahcintr(ahc) 730 struct ahc_softc *ahc; 731 { 732 int iobase = ahc->sc_iobase; 733 u_char intstat = inb(INTSTAT + iobase); 734 u_char status; 735 struct ahc_scb *scb = NULL; 736 struct scsi_xfer *xs = NULL; 737 738 /* 739 * Is this interrupt for me? or for 740 * someone who is sharing my interrupt 741 */ 742 if ((intstat & INT_PEND) == 0) 743 return 0; 744 745 if (intstat & BRKADRINT) { 746 /* We upset the sequencer :-( */ 747 748 /* Lookup the error message */ 749 int i, error = inb(ERROR + iobase); 750 int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 751 for (i = 0; error != 1 && i < num_errors; i++) 752 error >>= 1; 753 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 754 ahc->sc_dev.dv_xname, hard_error[i].errmesg, 755 (inb(SEQADDR1 + iobase) << 8) | 756 (inb(SEQADDR0 + iobase) << 0)); 757 } 758 759 if (intstat & SEQINT) { 760 switch (intstat & SEQINT_MASK) { 761 case BAD_PHASE: 762 panic("%s: unknown scsi bus phase. " 763 "Attempting to continue\n", 764 ahc->sc_dev.dv_xname); 765 break; 766 case SEND_REJECT: 767 printf("%s: Warning - " 768 "message reject, message type: 0x%x\n", 769 ahc->sc_dev.dv_xname, 770 inb(HA_REJBYTE + iobase)); 771 break; 772 case NO_IDENT: 773 panic("%s: No IDENTIFY message from reconnecting " 774 "target %d at seqaddr = 0x%x " 775 "SAVED_TCL == 0x%x\n", 776 ahc->sc_dev.dv_xname, 777 (inb(SELID + iobase) >> 4) & 0xf, 778 (inb(SEQADDR1 + iobase) << 8) | 779 (inb(SEQADDR0 + iobase) << 0), 780 inb(SAVED_TCL + iobase)); 781 break; 782 case NO_MATCH: { 783 u_char active; 784 int active_port = HA_ACTIVE0 + iobase; 785 int tcl = inb(SCBARRAY+1 + iobase); 786 int target = (tcl >> 4) & 0x0f; 787 printf("%s: no active SCB for reconnecting " 788 "target %d, channel %c - issuing ABORT\n", 789 ahc->sc_dev.dv_xname, 790 target, tcl & 0x08 ? 'B' : 'A'); 791 printf("SAVED_TCL == 0x%x\n", inb(SAVED_TCL + iobase)); 792 if (tcl & 0x88) { 793 /* Second channel stores its info 794 * in byte two of HA_ACTIVE 795 */ 796 active_port++; 797 } 798 active = inb(active_port); 799 active &= ~(0x01 << (target & 0x07)); 800 outb(SCBARRAY + iobase, SCB_NEEDDMA); 801 outb(active_port, active); 802 outb(CLRSINT1 + iobase, CLRSELTIMEO); 803 RESTART_SEQUENCER(ahc); 804 break; 805 } 806 case MSG_SDTR: { 807 u_char scsi_id = 808 (inb(SCSIID + iobase) >> 0x4) | 809 (inb(SBLKCTL + iobase) & 0x08); 810 u_char scratch, offset; 811 int period; 812 813 /* 814 * Help the sequencer to translate the 815 * negotiated transfer rate. Transfer is 816 * 1/4 the period in ns as is returned by 817 * the sync negotiation message. So, we must 818 * multiply by four 819 */ 820 period = inb(HA_ARG_1 + iobase) << 2; 821 /* The bottom half of SCSIXFER */ 822 offset = inb(ACCUM + iobase); 823 824 printf("%s: SDTR, target %d period %d offset %d\n", 825 ahc->sc_dev.dv_xname, scsi_id, period, offset); 826 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 827 scratch &= 0x80; 828 scratch |= ahc_scsirate(offset, period, ahc, scsi_id); 829 830 if ((scratch & 0x7f) == 0) { 831 /* 832 * The requested rate was so low 833 * that asyncronous transfers are 834 * faster (not to mention the 835 * controller won't support them), 836 * so we issue a message reject to 837 * ensure we go to asyncronous 838 * transfers. 839 */ 840 outb(HA_RETURN_1 + iobase, SEND_REJ); 841 } else if (ahc->sdtrpending & (0x01 << scsi_id)) { 842 /* 843 * Don't send an SDTR back to the 844 * target, since we asked first. 845 */ 846 outb(HA_RETURN_1 + iobase, 0); 847 } else { 848 /* 849 * Send our own SDTR in reply 850 */ 851 #ifdef AHC_DEBUG 852 if (ahc_debug & AHC_SHOWMISC) 853 printf("Sending SDTR!!\n"); 854 #endif 855 outb(HA_RETURN_1 + iobase, SEND_SDTR); 856 } 857 /* 858 * Negate the flags 859 */ 860 ahc->needsdtr &= ~(0x01 << scsi_id); 861 ahc->sdtrpending &= ~(0x01 << scsi_id); 862 863 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 864 outb(SCSIRATE + iobase, scratch); 865 break; 866 } 867 case MSG_WDTR: { 868 u_char scsi_id = 869 (inb(SCSIID + iobase) >> 0x4) | 870 (inb(SBLKCTL + iobase) & 0x08); 871 u_char scratch, width; 872 873 width = inb(ACCUM + iobase); 874 875 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 876 877 if (ahc->wdtrpending & (0x01 << scsi_id)) { 878 /* 879 * Don't send a WDTR back to the 880 * target, since we asked first. 881 */ 882 outb(HA_RETURN_1 + iobase, 0); 883 switch (width) { 884 case BUS_8_BIT: 885 scratch &= 0x7f; 886 break; 887 case BUS_16_BIT: 888 printf("%s: target %d using 16Bit " 889 "transfers\n", 890 ahc->sc_dev.dv_xname, scsi_id); 891 scratch &= 0xf8; 892 scratch |= 0x88; 893 break; 894 case BUS_32_BIT: 895 /* XXXX */ 896 } 897 } else { 898 /* 899 * Send our own WDTR in reply 900 */ 901 switch (width) { 902 case BUS_8_BIT: 903 scratch &= 0x7f; 904 break; 905 case BUS_32_BIT: 906 /* Negotiate 16_BITS */ 907 width = BUS_16_BIT; 908 case BUS_16_BIT: 909 printf("%s: target %d using 16Bit " 910 "transfers\n", 911 ahc->sc_dev.dv_xname, scsi_id); 912 scratch &= 0xf8; 913 scratch |= 0x88; 914 break; 915 } 916 outb(HA_RETURN_1 + iobase, 917 width | SEND_WDTR); 918 } 919 ahc->needwdtr &= ~(0x01 << scsi_id); 920 ahc->wdtrpending &= ~(0x01 << scsi_id); 921 922 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 923 outb(SCSIRATE + iobase, scratch); 924 break; 925 } 926 case MSG_REJECT: { 927 /* 928 * What we care about here is if we had an 929 * outstanding SDTR or WDTR message for this 930 * target. If we did, this is a signal that 931 * the target is refusing negotiation. 932 */ 933 934 u_char scsi_id = 935 (inb(SCSIID + iobase) >> 0x4) | 936 (inb(SBLKCTL + iobase) & 0x08); 937 u_char scratch; 938 u_short mask; 939 940 scratch = inb(HA_TARG_SCRATCH + iobase + scsi_id); 941 942 mask = (0x01 << scsi_id); 943 if (ahc->wdtrpending & mask) { 944 /* note 8bit xfers and clear flag */ 945 scratch &= 0x7f; 946 ahc->needwdtr &= ~mask; 947 ahc->wdtrpending &= ~mask; 948 printf("%s: target %d refusing " 949 "WIDE negotiation. Using " 950 "8bit transfers\n", 951 ahc->sc_dev.dv_xname, scsi_id); 952 } else if (ahc->sdtrpending & mask) { 953 /* note asynch xfers and clear flag */ 954 scratch &= 0xf0; 955 ahc->needsdtr &= ~mask; 956 ahc->sdtrpending &= ~mask; 957 printf("%s: target %d refusing " 958 "syncronous negotiation; using " 959 "asyncronous transfers\n", 960 ahc->sc_dev.dv_xname, scsi_id); 961 } else { 962 /* 963 * Otherwise, we ignore it. 964 */ 965 #ifdef AHC_DEBUG 966 if (ahc_debug & AHC_SHOWMISC) 967 printf("Message reject -- ignored\n"); 968 #endif 969 break; 970 } 971 972 outb(HA_TARG_SCRATCH + iobase + scsi_id, scratch); 973 outb(SCSIRATE + iobase, scratch); 974 break; 975 } 976 case BAD_STATUS: { 977 int scb_index = inb(SCBPTR + iobase); 978 scb = ahc->scbarray[scb_index]; 979 980 /* 981 * The sequencer will notify us when a command 982 * has an error that would be of interest to 983 * the kernel. This allows us to leave the sequencer 984 * running in the common case of command completes 985 * without error. 986 */ 987 988 /* 989 * Set the default return value to 0 (don't 990 * send sense). The sense code with change 991 * this if needed and this reduces code 992 * duplication. 993 */ 994 outb(HA_RETURN_1 + iobase, 0); 995 if (!scb || scb->flags == SCB_FREE) { 996 printf("%s: ahcintr: referenced scb not " 997 "valid during seqint 0x%x scb(%d)\n", 998 ahc->sc_dev.dv_xname, intstat, scb_index); 999 goto clear; 1000 } 1001 1002 xs = scb->xs; 1003 1004 ahc_getscb(iobase, scb); 1005 1006 #ifdef AHC_MORE_DEBUG 1007 if (xs->sc_link->target == DEBUGTARGET) 1008 ahc_print_scb(scb); 1009 #endif 1010 xs->status = scb->target_status; 1011 switch (scb->target_status) { 1012 case SCSI_OK: 1013 printf("%s: Interrupted for status of 0???\n", 1014 ahc->sc_dev.dv_xname); 1015 break; 1016 case SCSI_CHECK: 1017 #ifdef AHC_DEBUG 1018 sc_print_addr(xs->sc_link); 1019 printf("requests Check Status\n"); 1020 #endif 1021 1022 if (xs->error == XS_NOERROR && 1023 scb->flags != SCB_CHKSENSE) { 1024 u_char head; 1025 u_char tail; 1026 struct ahc_dma_seg *sg = scb->ahc_dma; 1027 struct scsi_sense *sc = &(scb->sense_cmd); 1028 u_char control = scb->control; 1029 u_char tcl = scb->target_channel_lun; 1030 #ifdef AHC_DEBUG 1031 sc_print_addr(xs->sc_link); 1032 printf("Sending Sense\n"); 1033 #endif 1034 bzero(scb, SCB_DOWN_SIZE); 1035 scb->flags = SCB_CHKSENSE; 1036 scb->control = (control & SCB_TE); 1037 sc->opcode = REQUEST_SENSE; 1038 sc->byte2 = xs->sc_link->lun << 5; 1039 sc->length = sizeof(struct scsi_sense_data); 1040 sc->control = 0; 1041 1042 sg->seg_addr = vtophys(&xs->sense); 1043 sg->seg_len = sizeof(struct scsi_sense_data); 1044 1045 scb->target_channel_lun = tcl; 1046 scb->SG_segment_count = 1; 1047 scb->SG_list_pointer = vtophys(sg); 1048 scb->cmdpointer = vtophys(sc); 1049 scb->cmdlen = sizeof(*sc); 1050 1051 outb(SCBCNT + iobase, SCBAUTO); 1052 outsb(SCBARRAY + iobase, scb, 1053 SCB_DOWN_SIZE); 1054 outb(SCBCNT + iobase, 0); 1055 outb(SCBARRAY + iobase + 30, 1056 SCB_LIST_NULL); 1057 1058 /* 1059 * Add this SCB to the "waiting for 1060 * selection" list. 1061 */ 1062 head = inb(WAITING_SCBH + iobase); 1063 tail = inb(WAITING_SCBT + iobase); 1064 if (head & SCB_LIST_NULL) { 1065 /* List was empty */ 1066 head = scb->position; 1067 tail = SCB_LIST_NULL; 1068 } else if (tail & SCB_LIST_NULL) { 1069 /* List had one element */ 1070 tail = scb->position; 1071 outb(SCBPTR + iobase, head); 1072 outb(SCBARRAY + iobase + 30, 1073 tail); 1074 } else { 1075 outb(SCBPTR + iobase, tail); 1076 tail = scb->position; 1077 outb(SCBARRAY + iobase + 30, 1078 tail); 1079 } 1080 outb(WAITING_SCBH + iobase, head); 1081 outb(WAITING_SCBT + iobase, tail); 1082 outb(HA_RETURN_1 + iobase, SEND_SENSE); 1083 break; 1084 } 1085 /* 1086 * Have the sequencer do a normal command 1087 * complete with either a "DRIVER_STUFFUP" 1088 * error or whatever other error condition 1089 * we already had. 1090 */ 1091 if (xs->error == XS_NOERROR) 1092 xs->error = XS_DRIVER_STUFFUP; 1093 break; 1094 case SCSI_BUSY: 1095 sc_print_addr(xs->sc_link); 1096 printf("Target Busy\n"); 1097 xs->error = XS_BUSY; 1098 break; 1099 #if 0 1100 case SCSI_QUEUE_FULL: 1101 /* 1102 * The upper level SCSI code will eventually 1103 * handle this properly. 1104 */ 1105 sc_print_addr(xs->sc_link); 1106 printf("Queue Full\n"); 1107 xs->error = XS_BUSY; 1108 break; 1109 #endif 1110 default: 1111 sc_print_addr(xs->sc_link); 1112 printf("unexpected targ_status: %x\n", 1113 scb->target_status); 1114 xs->error = XS_DRIVER_STUFFUP; 1115 break; 1116 } 1117 break; 1118 } 1119 case RESIDUAL: { 1120 int scb_index = inb(SCBPTR + iobase); 1121 scb = ahc->scbarray[scb_index]; 1122 1123 /* 1124 * Don't clobber valid resid info with 1125 * a resid coming from a check sense 1126 * operation. 1127 */ 1128 if (scb->flags != SCB_CHKSENSE) 1129 scb->xs->resid = 1130 (inb(iobase + SCBARRAY + 17) << 16) | 1131 (inb(iobase + SCBARRAY + 16) << 8) | 1132 (inb(iobase + SCBARRAY + 15) << 0); 1133 #ifdef AHC_MORE_DEBUG 1134 printf("ahc: Handled Residual\n"); 1135 #endif 1136 break; 1137 } 1138 case ABORT_TAG: { 1139 int scb_index = inb(SCBPTR + iobase); 1140 scb = ahc->scbarray[scb_index]; 1141 1142 /* 1143 * We didn't recieve a valid tag back from 1144 * the target on a reconnect. 1145 */ 1146 sc_print_addr(xs->sc_link); 1147 printf("invalid tag recieved on channel %c " 1148 "-- sending ABORT_TAG\n", 1149 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1150 scb->xs->error = XS_DRIVER_STUFFUP; 1151 untimeout(ahc_timeout, scb); 1152 ahc_done(ahc, scb); 1153 break; 1154 } 1155 default: 1156 printf("%s: seqint, intstat == 0x%x, scsisigi = 0x%x\n", 1157 ahc->sc_dev.dv_xname, 1158 intstat, inb(SCSISIGI + iobase)); 1159 break; 1160 } 1161 1162 clear: 1163 /* 1164 * Clear the upper byte that holds SEQINT status 1165 * codes and clear the SEQINT bit. 1166 */ 1167 outb(CLRINT + iobase, CLRSEQINT); 1168 1169 /* 1170 * The sequencer is paused immediately on 1171 * a SEQINT, so we should restart it when 1172 * we leave this section. 1173 */ 1174 UNPAUSE_SEQUENCER(ahc); 1175 } 1176 1177 if (intstat & SCSIINT) { 1178 int scb_index = inb(SCBPTR + iobase); 1179 scb = ahc->scbarray[scb_index]; 1180 1181 status = inb(SSTAT1 + iobase); 1182 1183 if (!scb || scb->flags == SCB_FREE) { 1184 printf("%s: ahcintr - referenced scb not " 1185 "valid during scsiint 0x%x scb(%d)\n", 1186 ahc->sc_dev.dv_xname, status, scb_index); 1187 outb(CLRSINT1 + iobase, status); 1188 UNPAUSE_SEQUENCER(ahc); 1189 outb(CLRINT + iobase, CLRSCSIINT); 1190 scb = NULL; 1191 goto cmdcomplete; 1192 } 1193 xs = scb->xs; 1194 1195 #ifdef AHC_MORE_DEBUG 1196 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) 1197 printf("Intr status %x\n", status); 1198 #endif 1199 1200 if (status & SELTO) { 1201 u_char active; 1202 u_char waiting; 1203 u_char flags; 1204 int active_port = HA_ACTIVE0 + iobase; 1205 1206 outb(SCSISEQ + iobase, ENRSELI); 1207 xs->error = XS_SELTIMEOUT; 1208 /* 1209 * Clear any pending messages for the timed out 1210 * target, and mark the target as free 1211 */ 1212 flags = inb(HA_FLAGS + iobase); 1213 outb(HA_FLAGS + iobase, flags & ~ACTIVE_MSG); 1214 1215 if (scb->target_channel_lun & 0x88) 1216 active_port++; 1217 1218 active = inb(active_port) & 1219 ~(0x01 << (xs->sc_link->target & 0x07)); 1220 outb(active_port, active); 1221 1222 outb(SCBARRAY + iobase, SCB_NEEDDMA); 1223 1224 outb(CLRSINT1 + iobase, CLRSELTIMEO); 1225 1226 outb(CLRINT + iobase, CLRSCSIINT); 1227 1228 /* Shift the waiting for selection queue forward */ 1229 waiting = inb(WAITING_SCBH + iobase); 1230 outb(SCBPTR + iobase, waiting); 1231 waiting = inb(SCBARRAY + iobase + 30); 1232 outb(WAITING_SCBH + iobase, waiting); 1233 1234 RESTART_SEQUENCER(ahc); 1235 } 1236 1237 if (status & SCSIPERR) { 1238 sc_print_addr(xs->sc_link); 1239 printf("parity error on channel %c\n", 1240 (xs->sc_link->quirks & 0x08) ? 'B' : 'A'); 1241 xs->error = XS_DRIVER_STUFFUP; 1242 1243 outb(CLRSINT1 + iobase, CLRSCSIPERR); 1244 UNPAUSE_SEQUENCER(ahc); 1245 1246 outb(CLRINT + iobase, CLRSCSIINT); 1247 scb = NULL; 1248 } 1249 if (status & BUSFREE) { 1250 #if 0 1251 /* 1252 * Has seen busfree since selection, i.e. 1253 * a "spurious" selection. Shouldn't happen. 1254 */ 1255 printf("ahc: unexpected busfree\n"); 1256 #if 0 1257 xs->error = XS_DRIVER_STUFFUP; 1258 outb(CLRSINT1 + iobase, BUSFREE); /* CLRBUSFREE */ 1259 #endif 1260 #endif 1261 } else { 1262 printf("%s: Unknown SCSIINT. Status = 0x%x\n", 1263 ahc->sc_dev.dv_xname, status); 1264 outb(CLRSINT1 + iobase, status); 1265 UNPAUSE_SEQUENCER(ahc); 1266 outb(CLRINT + iobase, CLRSCSIINT); 1267 scb = NULL; 1268 } 1269 if (scb != NULL) { 1270 /* We want to process the command */ 1271 untimeout(ahc_timeout, scb); 1272 ahc_done(ahc, scb); 1273 } 1274 } 1275 1276 cmdcomplete: 1277 if (intstat & CMDCMPLT) { 1278 int scb_index; 1279 1280 do { 1281 scb_index = inb(QOUTFIFO + iobase); 1282 scb = ahc->scbarray[scb_index]; 1283 1284 if (!scb || scb->flags == SCB_FREE) { 1285 printf("%s: WARNING " 1286 "no command for scb %d (cmdcmplt)\n" 1287 "QOUTCNT == %d\n", 1288 ahc->sc_dev.dv_xname, 1289 scb_index, inb(QOUTCNT + iobase)); 1290 outb(CLRINT + iobase, CLRCMDINT); 1291 continue; 1292 } 1293 1294 /* XXXX Should do this before reading FIFO? */ 1295 outb(CLRINT + iobase, CLRCMDINT); 1296 untimeout(ahc_timeout, scb); 1297 ahc_done(ahc, scb); 1298 } while (inb(QOUTCNT + iobase)); 1299 } 1300 1301 return 1; 1302 } 1303 1304 /* 1305 * We have a scb which has been processed by the 1306 * adaptor, now we look to see how the operation 1307 * went. 1308 */ 1309 void 1310 ahc_done(ahc, scb) 1311 struct ahc_softc *ahc; 1312 struct ahc_scb *scb; 1313 { 1314 struct scsi_xfer *xs = scb->xs; 1315 1316 #ifdef AHC_MORE_DEBUG 1317 if ((xs->sc_link->target & 0xf) == DEBUGTARGET) { 1318 xs->sc_link->flags |= 0xf0; 1319 SC_DEBUG(xs->sc_link, SDEV_DB2, ("ahc_done\n")); 1320 printf("%x %x %x %x\n", 1321 scb->flags, 1322 scb->target_status, 1323 xs->flags, 1324 xs->error); 1325 } 1326 #endif 1327 1328 /* 1329 * Put the results of the operation 1330 * into the xfer and call whoever started it 1331 */ 1332 if (xs->error == XS_NOERROR) { 1333 if (scb->flags == SCB_ABORTED) 1334 xs->error = XS_DRIVER_STUFFUP; 1335 else if (scb->flags == SCB_CHKSENSE) 1336 xs->error = XS_SENSE; 1337 } 1338 1339 xs->flags |= ITSDONE; 1340 1341 #ifdef AHC_TAGENABLE 1342 if (xs->cmd->opcode == 0x12 && xs->error == XS_NOERROR) { 1343 struct scsi_inquiry_data *inq_data; 1344 u_short mask = 0x01 << (xs->sc_link->target | 1345 (scb->target_channel_lun & 0x08)); 1346 /* 1347 * Sneak a look at the results of the SCSI Inquiry 1348 * command and see if we can do Tagged queing. XXX This 1349 * should really be done by the higher level drivers. 1350 */ 1351 inq_data = (struct scsi_inquiry_data *)xs->data; 1352 if (((inq_data->device & SID_TYPE) == 0) 1353 && (inq_data->flags & SID_CmdQue) 1354 && !(ahc->tagenable & mask)) { 1355 /* 1356 * Disk type device and can tag 1357 */ 1358 sc_print_addr(xs->sc_link); 1359 printf("Tagged Queuing Device\n"); 1360 ahc->tagenable |= mask; 1361 #ifdef QUEUE_FULL_SUPPORTED 1362 xs->sc_link->openings += 2; */ 1363 #endif 1364 } 1365 } 1366 #endif 1367 1368 ahc_free_scb(ahc, scb, xs->flags); 1369 scsi_done(xs); 1370 } 1371 1372 /* 1373 * Start the board, ready for normal operation 1374 */ 1375 /* XXXX clean */ 1376 int 1377 ahc_init(ahc) 1378 struct ahc_softc *ahc; 1379 { 1380 int iobase = ahc->sc_iobase; 1381 u_char scsi_conf, sblkctl, i; 1382 int intdef, max_targ = 16, wait; 1383 1384 /* 1385 * Assume we have a board at this stage 1386 * Find out the configured interupt and the card type. 1387 */ 1388 1389 #ifdef AHC_DEBUG 1390 printf("%s: scb %d bytes; SCB_SIZE %d bytes, ahc_dma %d bytes\n", 1391 ahc->sc_dev.dv_xname, sizeof(struct ahc_scb), SCB_DOWN_SIZE, 1392 sizeof(struct ahc_dma_seg)); 1393 #endif /* AHC_DEBUG */ 1394 1395 /* Save the IRQ type before we do a chip reset */ 1396 1397 ahc->unpause = (inb(HCNTRL + iobase) & IRQMS) | INTEN; 1398 ahc->pause = ahc->unpause | PAUSE; 1399 outb(HCNTRL + iobase, CHIPRST | ahc->pause); 1400 1401 /* 1402 * Ensure that the reset has finished 1403 */ 1404 wait = 1000; 1405 while (wait--) { 1406 delay(1000); 1407 if (!(inb(HCNTRL + iobase) & CHIPRST)) 1408 break; 1409 } 1410 if (wait == 0) { 1411 printf("\n%s: WARNING - Failed chip reset! " 1412 "Trying to initialize anyway.\n", ahc->sc_dev.dv_xname); 1413 /* Forcibly clear CHIPRST */ 1414 outb(HCNTRL + iobase, ahc->pause); 1415 } 1416 1417 switch (ahc->type) { 1418 case AHC_274: 1419 printf("%s: 274x ", ahc->sc_dev.dv_xname); 1420 ahc->maxscbs = 0x4; 1421 break; 1422 case AHC_284: 1423 printf("%s: 284x ", ahc->sc_dev.dv_xname); 1424 ahc->maxscbs = 0x4; 1425 break; 1426 case AHC_AIC7870: 1427 case AHC_294: 1428 if (ahc->type == AHC_AIC7870) 1429 printf("%s: aic7870 ", ahc->sc_dev.dv_xname); 1430 else 1431 printf("%s: 294x ", ahc->sc_dev.dv_xname); 1432 ahc->maxscbs = 0x10; 1433 #define DFTHRESH 3 1434 outb(DSPCISTATUS + iobase, DFTHRESH << 6); 1435 /* 1436 * XXX Hard coded SCSI ID until we can read it from the 1437 * SEEPROM or NVRAM. 1438 */ 1439 outb(HA_SCSICONF + iobase, 0x07 | (DFTHRESH << 6)); 1440 /* In case we are a wide card */ 1441 outb(HA_SCSICONF + 1 + iobase, 0x07); 1442 break; 1443 default: 1444 printf("%s: unknown(0x%x) ", ahc->sc_dev.dv_xname, ahc->type); 1445 break; 1446 } 1447 1448 /* Determine channel configuration and who we are on the scsi bus. */ 1449 switch ((sblkctl = inb(SBLKCTL + iobase) & 0x0f)) { 1450 case 0: 1451 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1452 printf("Single Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1453 outb(HA_FLAGS + iobase, SINGLE_BUS); 1454 break; 1455 case 2: 1456 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + 1 + iobase) & HWSCSIID); 1457 printf("Wide Channel, SCSI Id=%d, ", ahc->ahc_scsi_dev); 1458 ahc->type |= AHC_WIDE; 1459 outb(HA_FLAGS + iobase, WIDE_BUS); 1460 break; 1461 case 8: 1462 ahc->ahc_scsi_dev = (inb(HA_SCSICONF + iobase) & HSCSIID); 1463 ahc->ahc_scsi_dev_b = (inb(HA_SCSICONF + 1 + iobase) & HSCSIID); 1464 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ", 1465 ahc->ahc_scsi_dev, ahc->ahc_scsi_dev_b); 1466 ahc->type |= AHC_TWIN; 1467 outb(HA_FLAGS + iobase, TWIN_BUS); 1468 break; 1469 default: 1470 printf(" Unsupported adapter type. %x Ignoring\n", sblkctl); 1471 return(-1); 1472 } 1473 1474 /* 1475 * Take the bus led out of diagnostic mode 1476 */ 1477 outb(SBLKCTL + iobase, sblkctl); 1478 1479 /* 1480 * Number of SCBs that will be used. Rev E aic7770s and 1481 * aic7870s have 16. The rest have 4. 1482 */ 1483 if (!(ahc->type & AHC_AIC7870)) { 1484 /* 1485 * See if we have a Rev E or higher 1486 * aic7770. Anything below a Rev E will 1487 * have a R/O autoflush disable configuration 1488 * bit. 1489 */ 1490 u_char sblkctl_orig; 1491 sblkctl_orig = inb(SBLKCTL + iobase); 1492 sblkctl = sblkctl_orig ^ AUTOFLUSHDIS; 1493 outb(SBLKCTL + iobase, sblkctl); 1494 sblkctl = inb(SBLKCTL + iobase); 1495 if (sblkctl != sblkctl_orig) { 1496 printf("aic7770 >= Rev E, "); 1497 /* 1498 * Ensure autoflush is enabled 1499 */ 1500 sblkctl &= ~AUTOFLUSHDIS; 1501 outb(SBLKCTL + iobase, sblkctl); 1502 } else 1503 printf("aic7770 <= Rev C, "); 1504 } else 1505 printf("aic7870, "); 1506 printf("%d SCBs\n", ahc->maxscbs); 1507 1508 if (ahc->pause & IRQMS) 1509 printf("%s: Using Level Sensitive Interrupts\n", 1510 ahc->sc_dev.dv_xname); 1511 else 1512 printf("%s: Using Edge Triggered Interrupts\n", 1513 ahc->sc_dev.dv_xname); 1514 1515 if (!(ahc->type & AHC_AIC7870)) { 1516 /* 1517 * The 294x cards are PCI, so we get their interrupt from the 1518 * PCI BIOS. 1519 */ 1520 1521 intdef = inb(INTDEF + iobase); 1522 switch (intdef & 0xf) { 1523 case 9: 1524 ahc->sc_irq = 9; 1525 break; 1526 case 10: 1527 ahc->sc_irq = 10; 1528 break; 1529 case 11: 1530 ahc->sc_irq = 11; 1531 break; 1532 case 12: 1533 ahc->sc_irq = 12; 1534 break; 1535 case 14: 1536 ahc->sc_irq = 14; 1537 break; 1538 case 15: 1539 ahc->sc_irq = 15; 1540 break; 1541 default: 1542 printf("illegal irq setting\n"); 1543 return (EIO); 1544 } 1545 } 1546 1547 /* Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels */ 1548 if (ahc->type & AHC_TWIN) { 1549 /* 1550 * The device is gated to channel B after a chip reset, 1551 * so set those values first 1552 */ 1553 outb(SCSIID + iobase, ahc->ahc_scsi_dev_b); 1554 scsi_conf = inb(HA_SCSICONF + 1 + iobase) & (ENSPCHK|STIMESEL); 1555 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1556 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1557 /* Select Channel A */ 1558 outb(SBLKCTL + iobase, 0); 1559 } 1560 outb(SCSIID + iobase, ahc->ahc_scsi_dev); 1561 scsi_conf = inb(HA_SCSICONF + iobase) & (ENSPCHK|STIMESEL); 1562 outb(SXFRCTL1 + iobase, scsi_conf|ENSTIMER|ACTNEGEN|STPWEN); 1563 outb(SIMODE1 + iobase, ENSELTIMO|ENSCSIPERR); 1564 1565 /* 1566 * Look at the information that board initialization or 1567 * the board bios has left us. In the lower four bits of each 1568 * target's scratch space any value other than 0 indicates 1569 * that we should initiate syncronous transfers. If it's zero, 1570 * the user or the BIOS has decided to disable syncronous 1571 * negotiation to that target so we don't activate the needsdr 1572 * flag. 1573 */ 1574 ahc->needsdtr_orig = 0; 1575 ahc->needwdtr_orig = 0; 1576 if (!(ahc->type & AHC_WIDE)) 1577 max_targ = 8; 1578 1579 for (i = 0; i < max_targ; i++) { 1580 u_char target_settings = inb(HA_TARG_SCRATCH + i + iobase); 1581 #if 0 /* XXXX */ 1582 target_settings |= 0x8f; 1583 #endif 1584 if (target_settings & 0x0f) { 1585 ahc->needsdtr_orig |= (0x01 << i); 1586 /* Default to a asyncronous transfers (0 offset) */ 1587 target_settings &= 0xf0; 1588 } 1589 if (target_settings & 0x80) { 1590 ahc->needwdtr_orig |= (0x01 << i); 1591 /* 1592 * We'll set the Wide flag when we 1593 * are successful with Wide negotiation, 1594 * so turn it off for now so we aren't 1595 * confused. 1596 */ 1597 target_settings &= 0x7f; 1598 } 1599 outb(HA_TARG_SCRATCH + i + iobase, target_settings); 1600 } 1601 /* 1602 * If we are not a WIDE device, forget WDTR. This 1603 * makes the driver work on some cards that don't 1604 * leave these fields cleared when the BIOS is not 1605 * installed. 1606 */ 1607 if (!(ahc->type & AHC_WIDE)) 1608 ahc->needwdtr_orig = 0; 1609 ahc->needsdtr = ahc->needsdtr_orig; 1610 ahc->needwdtr = ahc->needwdtr_orig; 1611 ahc->sdtrpending = 0; 1612 ahc->wdtrpending = 0; 1613 ahc->tagenable = 0; 1614 1615 /* 1616 * Clear the control byte for every SCB so that the sequencer 1617 * doesn't get confused and think that one of them is valid 1618 */ 1619 for (i = 0; i < ahc->maxscbs; i++) { 1620 outb(SCBPTR + iobase, i); 1621 outb(SCBARRAY + iobase, 0); 1622 } 1623 1624 #ifdef AHC_DEBUG 1625 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n", ahc->needsdtr, 1626 ahc->needwdtr); 1627 #endif 1628 1629 /* 1630 * Set the number of availible SCBs 1631 */ 1632 outb(HA_SCBCOUNT + iobase, ahc->maxscbs); 1633 1634 /* We don't have any busy targets right now */ 1635 outb(HA_ACTIVE0 + iobase, 0); 1636 outb(HA_ACTIVE1 + iobase, 0); 1637 1638 /* We don't have any waiting selections */ 1639 outb(WAITING_SCBH + iobase, SCB_LIST_NULL); 1640 outb(WAITING_SCBT + iobase, SCB_LIST_NULL); 1641 /* 1642 * Load the Sequencer program and Enable the adapter. 1643 * Place the aic7770 in fastmode which makes a big 1644 * difference when doing many small block transfers. 1645 */ 1646 1647 printf("%s: Downloading Sequencer Program...", ahc->sc_dev.dv_xname); 1648 ahc_loadseq(iobase); 1649 printf("Done\n"); 1650 1651 if (!(ahc->type & AHC_AIC7870)) 1652 outb(BCTL + iobase, ENABLE); 1653 1654 /* Reset the bus */ 1655 outb(SCSISEQ + iobase, SCSIRSTO); 1656 delay(1000); 1657 outb(SCSISEQ + iobase, 0); 1658 1659 RESTART_SEQUENCER(ahc); 1660 1661 return (0); 1662 } 1663 1664 void 1665 ahcminphys(bp) 1666 struct buf *bp; 1667 { 1668 1669 if (bp->b_bcount > ((AHC_NSEG - 1) << PGSHIFT)) 1670 bp->b_bcount = ((AHC_NSEG - 1) << PGSHIFT); 1671 minphys(bp); 1672 } 1673 1674 /* 1675 * start a scsi operation given the command and 1676 * the data address, target, and lun all of which 1677 * are stored in the scsi_xfer struct 1678 */ 1679 int 1680 ahc_scsi_cmd(xs) 1681 struct scsi_xfer *xs; 1682 { 1683 struct scsi_link *sc_link = xs->sc_link; 1684 struct ahc_softc *ahc = sc_link->adapter_softc; 1685 struct ahc_scb *scb; 1686 struct ahc_dma_seg *sg; 1687 int seg; /* scatter gather seg being worked on */ 1688 u_long thiskv, thisphys, nextphys; 1689 int bytes_this_seg, bytes_this_page, datalen, flags; 1690 int s; 1691 u_short mask = (0x01 << (sc_link->target | (sc_link->quirks & 0x08))); 1692 1693 #ifdef AHC_MORE_DEBUG 1694 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1695 printf("ahc ahc_scsi_cmd for %x\n", sc_link->target); 1696 sc_link->flags = 0xf0; 1697 SC_DEBUG(sc_link, SDEV_DB2, ("ahc_scsi_cmd\n")); 1698 } 1699 #endif 1700 1701 /* 1702 * get a scb to use. If the transfer 1703 * is from a buf (possibly from interrupt time) 1704 * then we can't allow it to sleep 1705 */ 1706 flags = xs->flags; 1707 if ((flags & (ITSDONE|INUSE)) != INUSE) { 1708 printf("%s: done or not in use?\n", ahc->sc_dev.dv_xname); 1709 xs->flags &= ~ITSDONE; 1710 xs->flags |= INUSE; 1711 } 1712 if ((scb = ahc_get_scb(ahc, flags)) == NULL) { 1713 xs->error = XS_DRIVER_STUFFUP; 1714 return (TRY_AGAIN_LATER); 1715 } 1716 scb->xs = xs; 1717 1718 #ifdef AHC_MORE_DEBUG 1719 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1720 sc_link->flags = 0xf0; 1721 SC_DEBUG(sc_link, SDEV_DB3, ("start scb(%x)\n", scb)); 1722 } 1723 #endif 1724 1725 if (flags & SCSI_RESET) { 1726 /* XXX: Needs Implementation */ 1727 printf("ahc: SCSI_RESET called.\n"); 1728 } 1729 1730 /* 1731 * Put all the arguments for the xfer in the scb 1732 */ 1733 scb->control = 0; 1734 if (ahc->tagenable & mask) 1735 scb->control |= SCB_TE; 1736 if ((ahc->needwdtr & mask) && !(ahc->wdtrpending & mask)) { 1737 scb->control |= SCB_NEEDWDTR; 1738 ahc->wdtrpending |= mask; 1739 } 1740 if ((ahc->needsdtr & mask) && !(ahc->sdtrpending & mask)) { 1741 scb->control |= SCB_NEEDSDTR; 1742 ahc->sdtrpending |= mask; 1743 } 1744 scb->target_channel_lun = ((sc_link->target << 4) & 0xF0) | 1745 (sc_link->quirks & 0x08) | (sc_link->lun & 0x07); 1746 scb->cmdlen = xs->cmdlen; 1747 scb->cmdpointer = vtophys(xs->cmd); 1748 1749 xs->resid = 0; 1750 if (xs->datalen) { 1751 scb->SG_list_pointer = vtophys(scb->ahc_dma); 1752 sg = scb->ahc_dma; 1753 seg = 0; 1754 { 1755 /* 1756 * Set up the scatter gather block 1757 */ 1758 #ifdef AHC_MORE_DEBUG 1759 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1760 sc_link->flags = 0xf0; 1761 SC_DEBUG(sc_link, SDEV_DB4, 1762 ("%ld @%x:- ", xs->datalen, xs->data)); 1763 } 1764 #endif 1765 datalen = xs->datalen; 1766 thiskv = (long) xs->data; 1767 thisphys = vtophys(thiskv); 1768 1769 while (datalen && seg < AHC_NSEG) { 1770 bytes_this_seg = 0; 1771 1772 /* put in the base address */ 1773 sg->seg_addr = thisphys; 1774 1775 #ifdef AHC_MORE_DEBUG 1776 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1777 sc_link->flags = 0xf0; 1778 SC_DEBUGN(sc_link, SDEV_DB4, ("0x%lx", 1779 thisphys)); 1780 } 1781 #endif 1782 1783 /* do it at least once */ 1784 nextphys = thisphys; 1785 while (datalen && thisphys == nextphys) { 1786 /* 1787 * This page is contiguous (physically) 1788 * with the the last, just extend the 1789 * length 1790 */ 1791 /* how far to the end of the page */ 1792 nextphys = (thisphys & ~PGOFSET) + NBPG; 1793 bytes_this_page = nextphys - thisphys; 1794 /**** or the data ****/ 1795 bytes_this_page = min(bytes_this_page, 1796 datalen); 1797 bytes_this_seg += bytes_this_page; 1798 datalen -= bytes_this_page; 1799 1800 /* get more ready for the next page */ 1801 thiskv = (thiskv & ~PGOFSET) + NBPG; 1802 if (datalen) 1803 thisphys = vtophys(thiskv); 1804 } 1805 /* 1806 * next page isn't contiguous, finish the seg 1807 */ 1808 #ifdef AHC_MORE_DEBUG 1809 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1810 sc_link->flags = 0xf0; 1811 SC_DEBUGN(sc_link, SDEV_DB4, ("(0x%x)", 1812 bytes_this_seg)); 1813 } 1814 #endif 1815 sg->seg_len = bytes_this_seg; 1816 sg++; 1817 seg++; 1818 } 1819 } 1820 /*end of iov/kv decision */ 1821 scb->SG_segment_count = seg; 1822 #ifdef AHC_MORE_DEBUG 1823 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1824 sc_link->flags = 0xf0; 1825 SC_DEBUGN(sc_link, SDEV_DB4, ("\n")); 1826 } 1827 #endif 1828 if (datalen) { 1829 /* 1830 * there's still data, must have run out of segs! 1831 */ 1832 printf("%s: ahc_scsi_cmd: more than %d dma segs\n", 1833 ahc->sc_dev.dv_xname, AHC_NSEG); 1834 xs->error = XS_DRIVER_STUFFUP; 1835 ahc_free_scb(ahc, scb, flags); 1836 return (COMPLETE); 1837 } 1838 } else { 1839 scb->SG_list_pointer = (physaddr)0; 1840 scb->SG_segment_count = 0; 1841 } 1842 1843 #ifdef AHC_MORE_DEBUG 1844 if (sc_link->target == DEBUGTARGET) 1845 ahc_print_scb(scb); 1846 #endif 1847 1848 s = splbio(); 1849 1850 ahc_send_scb(ahc, scb); 1851 1852 /* 1853 * Usually return SUCCESSFULLY QUEUED 1854 */ 1855 if ((flags & SCSI_POLL) == 0) { 1856 timeout(ahc_timeout, scb, (xs->timeout * hz) / 1000); 1857 splx(s); 1858 #ifdef AHC_MORE_DEBUG 1859 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1860 sc_link->flags = 0xf0; 1861 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_sent\n")); 1862 } 1863 #endif 1864 return (SUCCESSFULLY_QUEUED); 1865 } 1866 1867 splx(s); 1868 1869 /* 1870 * If we can't use interrupts, poll on completion 1871 */ 1872 #ifdef AHC_MORE_DEBUG 1873 if ((sc_link->target & 0xf) == DEBUGTARGET) { 1874 sc_link->flags = 0xf0; 1875 SC_DEBUG(sc_link, SDEV_DB3, ("cmd_wait\n")); 1876 } 1877 #endif 1878 if (ahc_poll(ahc, xs, xs->timeout)) { 1879 ahc_timeout(scb); 1880 if (ahc_poll(ahc, xs, 2000)) 1881 ahc_timeout(scb); 1882 } 1883 return (COMPLETE); 1884 } 1885 1886 1887 /* 1888 * A scb (and hence an scb entry on the board is put onto the 1889 * free list. 1890 */ 1891 void 1892 ahc_free_scb(ahc, scb, flags) 1893 struct ahc_softc *ahc; 1894 struct ahc_scb *scb; 1895 int flags; 1896 { 1897 int s; 1898 1899 s = splbio(); 1900 1901 scb->flags = SCB_FREE; 1902 TAILQ_INSERT_TAIL(&ahc->free_scb, scb, chain); 1903 #ifdef AHC_DEBUG 1904 ahc->activescbs--; 1905 #endif 1906 1907 /* 1908 * If there were none, wake anybody waiting for one to come free, 1909 * starting with queued entries. 1910 */ 1911 if (scb->chain.tqe_next == 0) 1912 wakeup(&ahc->free_scb); 1913 1914 splx(s); 1915 } 1916 1917 /* XXXX check */ 1918 static inline void 1919 ahc_init_scb(ahc, scb) 1920 struct ahc_softc *ahc; 1921 struct ahc_scb *scb; 1922 { 1923 int iobase = ahc->sc_iobase; 1924 u_char scb_index; 1925 1926 bzero(scb, sizeof(struct ahc_scb)); 1927 scb->position = ahc->numscbs; 1928 /* 1929 * Place in the scbarray 1930 * Never is removed. Position 1931 * in ahc->scbarray is the scbarray 1932 * position on the board we will 1933 * load it into. 1934 */ 1935 ahc->scbarray[scb->position] = scb; 1936 1937 /* 1938 * Initialize the host memory location 1939 * of this SCB down on the board and 1940 * flag that it should be DMA's before 1941 * reference. Also set its psuedo 1942 * next pointer (for use in the psuedo 1943 * list of SCBs waiting for selection) 1944 * to SCB_LIST_NULL. 1945 */ 1946 scb->control = SCB_NEEDDMA; 1947 scb->host_scb = vtophys(scb); 1948 scb->next_waiting = SCB_LIST_NULL; 1949 PAUSE_SEQUENCER(ahc); 1950 scb_index = inb(SCBPTR + iobase); 1951 outb(SCBPTR + iobase, scb->position); 1952 outb(SCBCNT + iobase, SCBAUTO); 1953 outsb(SCBARRAY + iobase, scb, 31); 1954 outb(SCBCNT + iobase, 0); 1955 outb(SCBPTR + iobase, scb_index); 1956 UNPAUSE_SEQUENCER(ahc); 1957 scb->control = 0; 1958 } 1959 1960 static inline void 1961 ahc_reset_scb(ahc, scb) 1962 struct ahc_softc *ahc; 1963 struct ahc_scb *scb; 1964 { 1965 1966 bzero(scb, SCB_BZERO_SIZE); 1967 } 1968 1969 /* 1970 * Get a free scb 1971 * 1972 * If there are none, see if we can allocate a new one. 1973 */ 1974 struct ahc_scb * 1975 ahc_get_scb(ahc, flags) 1976 struct ahc_softc *ahc; 1977 int flags; 1978 { 1979 struct ahc_scb *scb; 1980 int s; 1981 1982 s = splbio(); 1983 1984 /* 1985 * If we can and have to, sleep waiting for one to come free 1986 * but only if we can't allocate a new one. 1987 */ 1988 for (;;) { 1989 scb = ahc->free_scb.tqh_first; 1990 if (scb) { 1991 TAILQ_REMOVE(&ahc->free_scb, scb, chain); 1992 break; 1993 } 1994 if (ahc->numscbs < ahc->maxscbs) { 1995 if (scb = (struct ahc_scb *) malloc(sizeof(struct ahc_scb), 1996 M_TEMP, M_NOWAIT)) { 1997 ahc_init_scb(ahc, scb); 1998 ahc->numscbs++; 1999 } else { 2000 printf("%s: can't malloc scb\n", 2001 ahc->sc_dev.dv_xname); 2002 goto out; 2003 } 2004 break; 2005 } 2006 if ((flags & SCSI_NOSLEEP) != 0) 2007 goto out; 2008 tsleep(&ahc->free_scb, PRIBIO, "ahcscb", 0); 2009 } 2010 2011 ahc_reset_scb(ahc, scb); 2012 scb->flags = SCB_ACTIVE; 2013 #ifdef AHC_DEBUG 2014 ahc->activescbs++; 2015 if (ahc->activescbs == ahc->maxscbs) 2016 printf("%s: Max SCBs active\n", ahc->sc_dev.dv_xname); 2017 #endif 2018 2019 out: 2020 splx(s); 2021 return (scb); 2022 } 2023 2024 /* XXXX check */ 2025 void 2026 ahc_loadseq(iobase) 2027 int iobase; 2028 { 2029 static u_char seqprog[] = { 2030 # include "aic7xxx_seq.h" 2031 }; 2032 2033 outb(SEQCTL + iobase, PERRORDIS|SEQRESET|LOADRAM); 2034 outsb(SEQRAM + iobase, seqprog, sizeof(seqprog)); 2035 outb(SEQCTL + iobase, FASTMODE|SEQRESET); 2036 } 2037 2038 /* 2039 * Function to poll for command completion when in poll mode 2040 */ 2041 int 2042 ahc_poll(ahc, xs, count) 2043 struct ahc_softc *ahc; 2044 struct scsi_xfer *xs; 2045 int count; 2046 { /* in msec */ 2047 int iobase = ahc->sc_iobase; 2048 int stport = INTSTAT + iobase; 2049 2050 while (count) { 2051 /* 2052 * If we had interrupts enabled, would we 2053 * have got an interrupt? 2054 */ 2055 if (inb(stport) & INT_PEND) 2056 ahcintr(ahc); 2057 if (xs->flags & ITSDONE) 2058 return 0; 2059 delay(1000); 2060 count--; 2061 } 2062 return 1; 2063 } 2064 2065 /* XXXX check */ 2066 void 2067 ahc_abort_scb(ahc, scb) 2068 struct ahc_softc *ahc; 2069 struct ahc_scb *scb; 2070 { 2071 int iobase = ahc->sc_iobase; 2072 int found = 0; 2073 int scb_index; 2074 u_char flags; 2075 u_char scb_control; 2076 2077 PAUSE_SEQUENCER(ahc); 2078 /* 2079 * Case 1: In the QINFIFO 2080 */ 2081 { 2082 int saved_queue[AHC_SCB_MAX]; 2083 int i; 2084 int queued = inb(QINCNT + iobase); 2085 2086 for (i = 0; i < (queued - found); i++) { 2087 saved_queue[i] = inb(QINFIFO + iobase); 2088 if (saved_queue[i] == scb->position) { 2089 i--; 2090 found = 1; 2091 } 2092 } 2093 /* Re-insert entries back into the queue */ 2094 for (queued = 0; queued < i; queued++) 2095 outb(QINFIFO + iobase, saved_queue[queued]); 2096 2097 if (found) 2098 goto done; 2099 } 2100 2101 scb_index = inb(SCBPTR + iobase); 2102 /* 2103 * Case 2: Not the active command 2104 */ 2105 if (scb_index != scb->position) { 2106 /* 2107 * Select the SCB we want to abort 2108 * and turn off the disconnected bit. 2109 * the driver will then abort the command 2110 * and notify us of the abort. 2111 */ 2112 outb(SCBPTR + iobase, scb->position); 2113 scb_control = inb(SCBARRAY + iobase); 2114 scb_control &= ~SCB_DIS; 2115 outb(SCBARRAY + iobase, scb_control); 2116 outb(SCBPTR + iobase, scb_index); 2117 goto done; 2118 } 2119 scb_control = inb(SCBARRAY + iobase); 2120 if (scb_control & SCB_DIS) { 2121 scb_control &= ~SCB_DIS; 2122 outb(SCBARRAY + iobase, scb_control); 2123 goto done; 2124 } 2125 /* 2126 * Case 3: Currently active command 2127 */ 2128 if ((flags = inb(HA_FLAGS + iobase)) & ACTIVE_MSG) { 2129 /* 2130 * If there's a message in progress, 2131 * reset the bus and have all devices renegotiate. 2132 */ 2133 if (scb->target_channel_lun & 0x08) { 2134 ahc->needsdtr |= (ahc->needsdtr_orig & 0xff00); 2135 ahc->sdtrpending &= 0x00ff; 2136 outb(HA_ACTIVE1, 0); 2137 } else if (ahc->type & AHC_WIDE) { 2138 ahc->needsdtr = ahc->needsdtr_orig; 2139 ahc->needwdtr = ahc->needwdtr_orig; 2140 ahc->sdtrpending = 0; 2141 ahc->wdtrpending = 0; 2142 outb(HA_ACTIVE0, 0); 2143 outb(HA_ACTIVE1, 0); 2144 } else { 2145 ahc->needsdtr |= (ahc->needsdtr_orig & 0x00ff); 2146 ahc->sdtrpending &= 0xff00; 2147 outb(HA_ACTIVE0, 0); 2148 } 2149 2150 /* Reset the bus */ 2151 outb(SCSISEQ + iobase, SCSIRSTO); 2152 delay(1000); 2153 outb(SCSISEQ + iobase, 0); 2154 goto done; 2155 } 2156 2157 /* 2158 * Otherwise, set up an abort message and have the sequencer 2159 * clean up 2160 */ 2161 outb(HA_FLAGS + iobase, flags | ACTIVE_MSG); 2162 outb(HA_MSG_LEN + iobase, 1); 2163 outb(HA_MSG_START + iobase, MSG_ABORT); 2164 2165 outb(SCSISIGO + iobase, inb(HA_SIGSTATE + iobase) | 0x10); 2166 2167 done: 2168 scb->flags = SCB_ABORTED; 2169 UNPAUSE_SEQUENCER(ahc); 2170 ahc_done(ahc, scb); 2171 return; 2172 } 2173 2174 void 2175 ahc_timeout(arg) 2176 void *arg; 2177 { 2178 struct ahc_scb *scb = arg; 2179 struct scsi_xfer *xs = scb->xs; 2180 struct scsi_link *sc_link = xs->sc_link; 2181 struct ahc_softc *ahc = sc_link->adapter_softc; 2182 int s; 2183 2184 sc_print_addr(sc_link); 2185 printf("timed out"); 2186 2187 s = splbio(); 2188 2189 #ifdef SCSIDEBUG 2190 show_scsi_cmd(scb->xs); 2191 #endif 2192 #ifdef AHC_DEBUG 2193 if (ahc_debug & AHC_SHOWSCBS) 2194 ahc_print_active_scb(ahc); 2195 #endif /*AHC_DEBUG */ 2196 2197 if (scb->flags & SCB_IMMED) { 2198 printf("\n"); 2199 scb->xs->retries = 0; /* I MEAN IT ! */ 2200 scb->flags |= SCB_IMMED_FAIL; 2201 ahc_done(ahc, scb); 2202 splx(s); 2203 return; 2204 } 2205 2206 /* 2207 * If it has been through before, then 2208 * a previous abort has failed, don't 2209 * try abort again 2210 */ 2211 if (scb->flags == SCB_ABORTED) { 2212 /* abort timed out */ 2213 printf(" AGAIN\n"); 2214 scb->xs->retries = 0; /* I MEAN IT ! */ 2215 ahc_done(ahc, scb); 2216 } else { 2217 /* abort the operation that has timed out */ 2218 printf("\n"); 2219 scb->xs->error = XS_TIMEOUT; 2220 scb->flags = SCB_ABORTED; 2221 ahc_abort_scb(ahc, scb); 2222 /* 2 secs for the abort */ 2223 if ((xs->flags & SCSI_POLL) == 0) 2224 timeout(ahc_timeout, scb, 2 * hz); 2225 } 2226 2227 splx(s); 2228 } 2229
Indexes created Tue Sep 30 11:09:46 GMT 2025