aic7xxx.c revision 1.51
1 /* $NetBSD: aic7xxx.c,v 1.51 2000/05/25 11:41:05 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 99 #include <machine/bus.h> 100 #include <machine/intr.h> 101 102 #include <dev/scsipi/scsi_all.h> 103 #include <dev/scsipi/scsipi_all.h> 104 #include <dev/scsipi/scsi_message.h> 105 #include <dev/scsipi/scsipi_debug.h> 106 #include <dev/scsipi/scsiconf.h> 107 108 #include <vm/vm.h> 109 #include <vm/vm_param.h> 110 #include <vm/pmap.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 118 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 119 #define ALL_CHANNELS '\0' 120 #define ALL_TARGETS_MASK 0xFFFF 121 #define INITIATOR_WILDCARD (~0) 122 123 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 124 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 125 #define SIM_CHANNEL(ahc, sc_link) \ 126 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 127 #define SIM_SCSI_ID(ahc, sc_link) \ 128 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 129 #define SCB_IS_SCSIBUS_B(scb) \ 130 (((scb)->hscb->tcl & SELBUSB) != 0) 131 #define SCB_TARGET(scb) \ 132 (((scb)->hscb->tcl & TID) >> 4) 133 #define SCB_CHANNEL(scb) \ 134 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 135 #define SCB_LUN(scb) \ 136 ((scb)->hscb->tcl & LID) 137 #define SCB_TARGET_OFFSET(scb) \ 138 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 139 #define SCB_TARGET_MASK(scb) \ 140 (0x01 << (SCB_TARGET_OFFSET(scb))) 141 #define TCL_CHANNEL(ahc, tcl) \ 142 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 143 #define TCL_SCSI_ID(ahc, tcl) \ 144 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 145 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 146 #define TCL_LUN(tcl) ((tcl) & LID) 147 148 #define XS_TCL(ahc, xs) \ 149 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 150 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 151 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 152 153 char *ahc_chip_names[] = 154 { 155 "NONE", 156 "aic7770", 157 "aic7850", 158 "aic7855", 159 "aic7859", 160 "aic7860", 161 "aic7870", 162 "aic7880", 163 "aic7890/91", 164 "aic7892", 165 "aic7895", 166 "aic7896/97", 167 "aic7899" 168 }; 169 170 typedef enum { 171 ROLE_UNKNOWN, 172 ROLE_INITIATOR, 173 ROLE_TARGET 174 } role_t; 175 176 struct ahc_devinfo { 177 int our_scsiid; 178 int target_offset; 179 u_int16_t target_mask; 180 u_int8_t target; 181 u_int8_t lun; 182 char channel; 183 role_t role; /* 184 * Only guaranteed to be correct if not 185 * in the busfree state. 186 */ 187 }; 188 189 typedef enum { 190 SEARCH_COMPLETE, 191 SEARCH_COUNT, 192 SEARCH_REMOVE 193 } ahc_search_action; 194 195 #ifdef AHC_DEBUG 196 static int ahc_debug = AHC_DEBUG; 197 #endif 198 199 static int ahcinitscbdata(struct ahc_softc *); 200 static void ahcfiniscbdata(struct ahc_softc *); 201 202 #if UNUSED 203 static void ahc_dump_targcmd(struct target_cmd *); 204 #endif 205 static void ahc_shutdown(void *arg); 206 static int32_t ahc_action(struct scsipi_xfer *); 207 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 208 static int ahc_poll(struct ahc_softc *, int); 209 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 210 struct scb *); 211 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 212 static void ahcallocscbs(struct ahc_softc *); 213 #if UNUSED 214 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 215 struct scb *); 216 #endif 217 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 218 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 219 char, role_t); 220 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 221 static void ahc_done(struct ahc_softc *, struct scb *); 222 static struct tmode_tstate * 223 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 224 #if UNUSED 225 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 226 #endif 227 static void ahc_handle_seqint(struct ahc_softc *, u_int); 228 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 229 static void ahc_build_transfer_msg(struct ahc_softc *, 230 struct ahc_devinfo *); 231 static void ahc_setup_initiator_msgout(struct ahc_softc *, 232 struct ahc_devinfo *, 233 struct scb *); 234 static void ahc_setup_target_msgin(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_clear_msg_state(struct ahc_softc *); 237 static void ahc_handle_message_phase(struct ahc_softc *, 238 struct scsipi_link *); 239 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 240 241 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 242 struct ahc_devinfo *); 243 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 244 struct ahc_devinfo *); 245 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 246 int, char *, int); 247 #ifdef AHC_DUMP_SEQ 248 static void ahc_dumpseq(struct ahc_softc *); 249 #endif 250 static void ahc_loadseq(struct ahc_softc *); 251 static int ahc_check_patch(struct ahc_softc *, struct patch **, 252 int, int *); 253 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 254 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 255 #if defined(AHC_DEBUG) 256 static void ahc_print_scb(struct scb *); 257 #endif 258 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 259 role_t, scb_flag, ahc_search_action); 260 static int ahc_reset_channel(struct ahc_softc *, char, int); 261 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 262 role_t, int); 263 static int ahc_search_disc_list(struct ahc_softc *, int, 264 char, int, u_int, int, int, int); 265 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 266 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 267 static void ahc_clear_intstat(struct ahc_softc *); 268 static void ahc_reset_current_bus(struct ahc_softc *); 269 static struct ahc_syncrate * 270 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 271 static struct ahc_syncrate * 272 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 273 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 274 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 275 u_int *, int); 276 static void ahc_update_target_msg_request(struct ahc_softc *, 277 struct ahc_devinfo *, 278 struct ahc_initiator_tinfo *, 279 int, int); 280 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 281 struct ahc_syncrate *, u_int, u_int, u_int, 282 int, int); 283 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 284 u_int, u_int, int, int); 285 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 286 int); 287 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 288 289 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 290 291 static void ahc_calc_residual(struct scb *); 292 293 static void ahc_update_pending_syncrates(struct ahc_softc *); 294 295 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 296 297 static void ahc_timeout (void *); 298 static __inline int sequencer_paused(struct ahc_softc *); 299 static __inline void pause_sequencer(struct ahc_softc *); 300 static __inline void unpause_sequencer(struct ahc_softc *); 301 static void restart_sequencer(struct ahc_softc *); 302 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 303 304 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 305 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 306 307 static __inline void ahc_freeze_ccb(struct scb *); 308 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 309 static void ahc_run_qoutfifo(struct ahc_softc *); 310 311 static __inline struct ahc_initiator_tinfo * 312 ahc_fetch_transinfo(struct ahc_softc *, 313 char, u_int, u_int, 314 struct tmode_tstate **); 315 static void ahcfreescb(struct ahc_softc *, struct scb *); 316 static __inline struct scb *ahcgetscb(struct ahc_softc *); 317 318 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 319 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 320 int *, const char *, const char *); 321 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 322 caddr_t, bus_dma_segment_t *, int); 323 static void ahcminphys(struct buf *); 324 325 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 329 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 330 331 #if defined(AHC_DEBUG) && 0 332 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 333 #endif 334 335 static struct scsipi_device ahc_dev = 336 { 337 NULL, /* Use default error handler */ 338 NULL, /* have a queue, served by this */ 339 NULL, /* have no async handler */ 340 NULL, /* Use default 'done' routine */ 341 }; 342 343 /* 344 * Pick the first xs for a non-blocked target. 345 */ 346 static __inline struct scsipi_xfer * 347 ahc_first_xs(struct ahc_softc *ahc) 348 { 349 int target; 350 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 351 352 if (ahc->queue_blocked) 353 return NULL; 354 355 while (xs != NULL) { 356 target = xs->sc_link->scsipi_scsi.target; 357 if (ahc->devqueue_blocked[target] == 0 && 358 (!ahc_istagged_device(ahc, xs, 0) && 359 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 360 SCB_LIST_NULL)) 361 break; 362 xs = TAILQ_NEXT(xs, adapter_q); 363 } 364 365 return xs; 366 } 367 368 static __inline void 369 ahc_swap_hscb(struct hardware_scb *hscb) 370 { 371 hscb->SG_pointer = htole32(hscb->SG_pointer); 372 hscb->data = htole32(hscb->data); 373 hscb->datalen = htole32(hscb->datalen); 374 /* 375 * No need to swap cmdpointer; it's either 0 or set to 376 * cmdstore_busaddr, which is already swapped. 377 */ 378 } 379 380 static __inline void 381 ahc_swap_sg(struct ahc_dma_seg *sg) 382 { 383 sg->addr = htole32(sg->addr); 384 sg->len = htole32(sg->len); 385 } 386 387 static void 388 ahcminphys(bp) 389 struct buf *bp; 390 { 391 /* 392 * Even though the card can transfer up to 16megs per command 393 * we are limited by the number of segments in the dma segment 394 * list that we can hold. The worst case is that all pages are 395 * discontinuous physically, hense the "page per segment" limit 396 * enforced here. 397 */ 398 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 399 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 400 } 401 minphys(bp); 402 } 403 404 405 static __inline u_int32_t 406 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 407 { 408 return (ahc->scb_data->hscb_busaddr 409 + (sizeof(struct hardware_scb) * index)); 410 } 411 412 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 413 414 static __inline int 415 sequencer_paused(struct ahc_softc *ahc) 416 { 417 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 418 } 419 420 static __inline void 421 pause_sequencer(struct ahc_softc *ahc) 422 { 423 ahc_outb(ahc, HCNTRL, ahc->pause); 424 425 /* 426 * Since the sequencer can disable pausing in a critical section, we 427 * must loop until it actually stops. 428 */ 429 while (sequencer_paused(ahc) == 0) 430 ; 431 } 432 433 static __inline void 434 unpause_sequencer(struct ahc_softc *ahc) 435 { 436 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 437 ahc_outb(ahc, HCNTRL, ahc->unpause); 438 } 439 440 /* 441 * Restart the sequencer program from address zero 442 */ 443 static void 444 restart_sequencer(struct ahc_softc *ahc) 445 { 446 u_int i; 447 448 pause_sequencer(ahc); 449 450 /* 451 * Everytime we restart the sequencer, there 452 * is the possiblitity that we have restarted 453 * within a three instruction window where an 454 * SCB has been marked free but has not made it 455 * onto the free list. Since SCSI events(bus reset, 456 * unexpected bus free) will always freeze the 457 * sequencer, we cannot close this window. To 458 * avoid losing an SCB, we reconsitute the free 459 * list every time we restart the sequencer. 460 */ 461 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 462 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 463 464 ahc_outb(ahc, SCBPTR, i); 465 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 466 ahc_add_curscb_to_free_list(ahc); 467 } 468 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 469 unpause_sequencer(ahc); 470 } 471 472 static __inline u_int 473 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 474 { 475 u_int scbid; 476 477 scbid = ahc->untagged_scbs[tcl]; 478 if (unbusy) { 479 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 480 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 481 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 482 } 483 484 return (scbid); 485 } 486 487 static __inline void 488 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 489 { 490 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 491 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 492 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 493 } 494 495 static __inline int 496 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 497 { 498 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 499 } 500 501 static __inline void 502 ahc_freeze_ccb(struct scb *scb) 503 { 504 struct scsipi_xfer *xs = scb->xs; 505 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 506 int target; 507 508 target = xs->sc_link->scsipi_scsi.target; 509 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 510 ahc->devqueue_blocked[target]++; 511 scb->flags |= SCB_FREEZE_QUEUE; 512 } 513 } 514 515 static __inline void 516 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 517 { 518 xs->error = status; 519 } 520 521 static __inline struct ahc_initiator_tinfo * 522 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 523 u_int remote_id, struct tmode_tstate **tstate) 524 { 525 /* 526 * Transfer data structures are stored from the perspective 527 * of the target role. Since the parameters for a connection 528 * in the initiator role to a given target are the same as 529 * when the roles are reversed, we pretend we are the target. 530 */ 531 if (channel == 'B') 532 our_id += 8; 533 *tstate = ahc->enabled_targets[our_id]; 534 return (&(*tstate)->transinfo[remote_id]); 535 } 536 537 static void 538 ahc_run_qoutfifo(struct ahc_softc *ahc) 539 { 540 struct scb *scb; 541 u_int scb_index; 542 543 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 544 256, BUS_DMASYNC_POSTREAD); 545 546 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 547 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 548 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 549 550 scb = &ahc->scb_data->scbarray[scb_index]; 551 if (scb_index >= ahc->scb_data->numscbs 552 || (scb->flags & SCB_ACTIVE) == 0) { 553 printf("%s: WARNING no command for scb %d " 554 "(cmdcmplt)\nQOUTPOS = %d\n", 555 ahc_name(ahc), scb_index, 556 ahc->qoutfifonext - 1); 557 continue; 558 } 559 560 /* 561 * Save off the residual 562 * if there is one. 563 */ 564 if (scb->hscb->residual_SG_count != 0) 565 ahc_calc_residual(scb); 566 else 567 scb->xs->resid = 0; 568 #ifdef AHC_DEBUG 569 if (ahc_debug & AHC_SHOWSCBS) { 570 scsi_print_addr(scb->xs->sc_link); 571 printf("run_qoutfifo: SCB %x complete\n", 572 scb->hscb->tag); 573 } 574 #endif 575 ahc_done(ahc, scb); 576 } 577 } 578 579 580 /* 581 * An scb (and hence an scb entry on the board) is put onto the 582 * free list. 583 */ 584 static void 585 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 586 { 587 struct hardware_scb *hscb; 588 int opri; 589 590 hscb = scb->hscb; 591 592 #ifdef AHC_DEBUG 593 if (ahc_debug & AHC_SHOWSCBALLOC) 594 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 595 #endif 596 597 opri = splbio(); 598 599 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 600 (scb->flags & SCB_RECOVERY_SCB) != 0) { 601 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 602 ahc->queue_blocked = 0; 603 } 604 605 /* Clean up for the next user */ 606 scb->flags = SCB_FREE; 607 hscb->control = 0; 608 hscb->status = 0; 609 610 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 611 612 splx(opri); 613 } 614 615 /* 616 * Get a free scb, either one already assigned to a hardware slot 617 * on the adapter or one that will require an SCB to be paged out before 618 * use. If there are none, see if we can allocate a new SCB. Otherwise 619 * either return an error or sleep. 620 */ 621 static __inline struct scb * 622 ahcgetscb(struct ahc_softc *ahc) 623 { 624 struct scb *scbp; 625 int opri;; 626 627 opri = splbio(); 628 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 629 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 630 } else { 631 ahcallocscbs(ahc); 632 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 633 if (scbp != NULL) 634 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 635 } 636 637 splx(opri); 638 639 #ifdef AHC_DEBUG 640 if (ahc_debug & AHC_SHOWSCBALLOC) { 641 if (scbp != NULL) 642 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 643 scbp->hscb->tag); 644 else 645 printf("%s: failed to allocate new SCB\n", 646 ahc_name(ahc)); 647 } 648 #endif 649 650 return (scbp); 651 } 652 653 static int 654 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 655 bus_dma_tag_t tag; 656 int size; 657 int flags; 658 bus_dmamap_t *mapp; 659 caddr_t *vaddr; 660 bus_addr_t *baddr; 661 bus_dma_segment_t *seg; 662 int *nseg; 663 const char *myname, *what; 664 { 665 int error, level = 0; 666 667 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 668 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 669 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 670 myname, what, error); 671 goto out; 672 } 673 level++; 674 675 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 676 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 677 printf("%s: failed to map DMA mem for %s, error = %d\n", 678 myname, what, error); 679 goto out; 680 } 681 level++; 682 683 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 684 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 685 printf("%s: failed to create DMA map for %s, error = %d\n", 686 myname, what, error); 687 goto out; 688 } 689 level++; 690 691 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 692 BUS_DMA_NOWAIT)) != 0) { 693 printf("%s: failed to load DMA map for %s, error = %d\n", 694 myname, what, error); 695 goto out; 696 } 697 698 *baddr = (*mapp)->dm_segs[0].ds_addr; 699 700 #ifdef AHC_DEBUG 701 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 702 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 703 *nseg, size); 704 #endif 705 706 return 0; 707 out: 708 switch (level) { 709 case 3: 710 bus_dmamap_destroy(tag, *mapp); 711 /* FALLTHROUGH */ 712 case 2: 713 bus_dmamem_unmap(tag, *vaddr, size); 714 /* FALLTHROUGH */ 715 case 1: 716 bus_dmamem_free(tag, seg, *nseg); 717 break; 718 default: 719 break; 720 } 721 722 return error; 723 } 724 725 static void 726 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 727 bus_dma_tag_t tag; 728 int size; 729 bus_dmamap_t map; 730 caddr_t vaddr; 731 bus_dma_segment_t *seg; 732 int nseg; 733 { 734 735 bus_dmamap_unload(tag, map); 736 bus_dmamap_destroy(tag, map); 737 bus_dmamem_unmap(tag, vaddr, size); 738 bus_dmamem_free(tag, seg, nseg); 739 } 740 741 char * 742 ahc_name(struct ahc_softc *ahc) 743 { 744 return (ahc->sc_dev.dv_xname); 745 } 746 747 #ifdef AHC_DEBUG 748 static void 749 ahc_print_scb(struct scb *scb) 750 { 751 struct hardware_scb *hscb = scb->hscb; 752 753 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 754 scb, 755 hscb->tag, 756 hscb->control, 757 hscb->tcl, 758 hscb->cmdlen, 759 (unsigned long)le32toh(hscb->cmdpointer)); 760 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 761 le32toh(hscb->datalen), 762 (unsigned long)(le32toh(hscb->data)), 763 hscb->SG_count, 764 (unsigned long)(le32toh(hscb->SG_pointer))); 765 printf(" sg_addr:%lx sg_len:%lu\n", 766 (unsigned long)(le32toh(scb->sg_list[0].addr)), 767 (unsigned long)(le32toh(scb->sg_list[0].len))); 768 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 769 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 770 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 771 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 772 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 773 } 774 #endif 775 776 static struct { 777 u_int8_t errno; 778 char *errmesg; 779 } hard_error[] = { 780 { ILLHADDR, "Illegal Host Access" }, 781 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 782 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 783 { SQPARERR, "Sequencer Parity Error" }, 784 { DPARERR, "Data-path Parity Error" }, 785 { MPARERR, "Scratch or SCB Memory Parity Error" }, 786 { PCIERRSTAT, "PCI Error detected" }, 787 { CIOPARERR, "CIOBUS Parity Error" }, 788 }; 789 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 790 791 static struct { 792 u_int8_t phase; 793 u_int8_t mesg_out; /* Message response to parity errors */ 794 char *phasemsg; 795 } phase_table[] = { 796 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 797 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 798 { P_COMMAND, MSG_NOOP, "in Command phase" }, 799 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 800 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 801 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 802 { P_BUSFREE, MSG_NOOP, "while idle" }, 803 { 0, MSG_NOOP, "in unknown phase" } 804 }; 805 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 806 807 /* 808 * Valid SCSIRATE values. (p. 3-17) 809 * Provides a mapping of tranfer periods in ns to the proper value to 810 * stick in the scsiscfr reg to use that transfer rate. 811 */ 812 #define AHC_SYNCRATE_DT 0 813 #define AHC_SYNCRATE_ULTRA2 1 814 #define AHC_SYNCRATE_ULTRA 3 815 #define AHC_SYNCRATE_FAST 6 816 static struct ahc_syncrate ahc_syncrates[] = { 817 /* ultra2 fast/ultra period rate */ 818 { 0x42, 0x000, 9, "80.0" }, 819 { 0x03, 0x000, 10, "40.0" }, 820 { 0x04, 0x000, 11, "33.0" }, 821 { 0x05, 0x100, 12, "20.0" }, 822 { 0x06, 0x110, 15, "16.0" }, 823 { 0x07, 0x120, 18, "13.4" }, 824 { 0x08, 0x000, 25, "10.0" }, 825 { 0x19, 0x010, 31, "8.0" }, 826 { 0x1a, 0x020, 37, "6.67" }, 827 { 0x1b, 0x030, 43, "5.7" }, 828 { 0x1c, 0x040, 50, "5.0" }, 829 { 0x00, 0x050, 56, "4.4" }, 830 { 0x00, 0x060, 62, "4.0" }, 831 { 0x00, 0x070, 68, "3.6" }, 832 { 0x00, 0x000, 0, NULL } 833 }; 834 835 /* 836 * Allocate a controller structure for a new device and initialize it. 837 */ 838 int 839 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 840 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 841 ahc_flag flags) 842 { 843 struct scb_data *scb_data; 844 845 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 846 if (scb_data == NULL) { 847 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 848 return -1; 849 } 850 bzero(scb_data, sizeof (struct scb_data)); 851 LIST_INIT(&ahc->pending_ccbs); 852 ahc->tag = st; 853 ahc->bsh = sh; 854 ahc->parent_dmat = parent_dmat; 855 ahc->chip = chip; 856 ahc->features = features; 857 ahc->flags = flags; 858 ahc->scb_data = scb_data; 859 860 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 861 /* The IRQMS bit is only valid on VL and EISA chips */ 862 if ((ahc->chip & AHC_PCI) != 0) 863 ahc->unpause &= ~IRQMS; 864 ahc->pause = ahc->unpause | PAUSE; 865 return (0); 866 } 867 868 void 869 ahc_free(ahc) 870 struct ahc_softc *ahc; 871 { 872 ahcfiniscbdata(ahc); 873 if (ahc->init_level != 0) 874 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 875 ahc->shared_data_dmamap, ahc->qoutfifo, 876 &ahc->shared_data_seg, ahc->shared_data_nseg); 877 878 if (ahc->scb_data != NULL) 879 free(ahc->scb_data, M_DEVBUF); 880 if (ahc->bus_data != NULL) 881 free(ahc->bus_data, M_DEVBUF); 882 return; 883 } 884 885 static int 886 ahcinitscbdata(struct ahc_softc *ahc) 887 { 888 struct scb_data *scb_data; 889 int i; 890 891 scb_data = ahc->scb_data; 892 SLIST_INIT(&scb_data->free_scbs); 893 SLIST_INIT(&scb_data->sg_maps); 894 895 /* Allocate SCB resources */ 896 scb_data->scbarray = 897 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 898 M_DEVBUF, M_NOWAIT); 899 if (scb_data->scbarray == NULL) 900 return (ENOMEM); 901 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 902 903 /* Determine the number of hardware SCBs and initialize them */ 904 905 scb_data->maxhscbs = ahc_probe_scbs(ahc); 906 /* SCB 0 heads the free list */ 907 ahc_outb(ahc, FREE_SCBH, 0); 908 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 909 ahc_outb(ahc, SCBPTR, i); 910 911 /* Clear the control byte. */ 912 ahc_outb(ahc, SCB_CONTROL, 0); 913 914 /* Set the next pointer */ 915 ahc_outb(ahc, SCB_NEXT, i+1); 916 917 /* Make the tag number invalid */ 918 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 919 } 920 921 /* Make sure that the last SCB terminates the free list */ 922 ahc_outb(ahc, SCBPTR, i-1); 923 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 924 925 /* Ensure we clear the 0 SCB's control byte. */ 926 ahc_outb(ahc, SCBPTR, 0); 927 ahc_outb(ahc, SCB_CONTROL, 0); 928 929 scb_data->maxhscbs = i; 930 931 if (ahc->scb_data->maxhscbs == 0) 932 panic("%s: No SCB space found", ahc_name(ahc)); 933 934 /* 935 * Create our DMA tags. These tags define the kinds of device 936 * accessable memory allocations and memory mappings we will 937 * need to perform during normal operation. 938 * 939 * Unless we need to further restrict the allocation, we rely 940 * on the restrictions of the parent dmat, hence the common 941 * use of MAXADDR and MAXSIZE. 942 */ 943 944 if (ahc_createdmamem(ahc->parent_dmat, 945 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 946 &scb_data->hscb_dmamap, 947 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 948 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 949 "hardware SCB structures") < 0) 950 goto error_exit; 951 952 scb_data->init_level++; 953 954 if (ahc_createdmamem(ahc->parent_dmat, 955 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 956 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 957 &scb_data->sense_busaddr, &scb_data->sense_seg, 958 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 959 goto error_exit; 960 961 scb_data->init_level++; 962 963 /* Perform initial CCB allocation */ 964 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 965 ahcallocscbs(ahc); 966 967 if (scb_data->numscbs == 0) { 968 printf("%s: ahc_init_scb_data - " 969 "Unable to allocate initial scbs\n", 970 ahc_name(ahc)); 971 goto error_exit; 972 } 973 974 scb_data->init_level++; 975 976 /* 977 * Note that we were successfull 978 */ 979 return 0; 980 981 error_exit: 982 983 return ENOMEM; 984 } 985 986 static void 987 ahcfiniscbdata(struct ahc_softc *ahc) 988 { 989 struct scb_data *scb_data; 990 991 scb_data = ahc->scb_data; 992 993 switch (scb_data->init_level) { 994 default: 995 case 3: 996 { 997 struct sg_map_node *sg_map; 998 999 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1000 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1001 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1002 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1003 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1004 free(sg_map, M_DEVBUF); 1005 } 1006 } 1007 /*FALLTHROUGH*/ 1008 case 2: 1009 ahc_freedmamem(ahc->parent_dmat, 1010 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1011 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1012 &scb_data->sense_seg, scb_data->sense_nseg); 1013 /*FALLTHROUGH*/ 1014 case 1: 1015 ahc_freedmamem(ahc->parent_dmat, 1016 AHC_SCB_MAX * sizeof(struct hardware_scb), 1017 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1018 &scb_data->hscb_seg, scb_data->hscb_nseg); 1019 /*FALLTHROUGH*/ 1020 } 1021 if (scb_data->scbarray != NULL) 1022 free(scb_data->scbarray, M_DEVBUF); 1023 } 1024 1025 int 1026 ahc_reset(struct ahc_softc *ahc) 1027 { 1028 u_int sblkctl; 1029 int wait; 1030 1031 #ifdef AHC_DUMP_SEQ 1032 if (ahc->init_level == 0) 1033 ahc_dumpseq(ahc); 1034 #endif 1035 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1036 /* 1037 * Ensure that the reset has finished 1038 */ 1039 wait = 1000; 1040 do { 1041 DELAY(1000); 1042 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1043 1044 if (wait == 0) { 1045 printf("%s: WARNING - Failed chip reset! " 1046 "Trying to initialize anyway.\n", ahc_name(ahc)); 1047 } 1048 ahc_outb(ahc, HCNTRL, ahc->pause); 1049 1050 /* Determine channel configuration */ 1051 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1052 /* No Twin Channel PCI cards */ 1053 if ((ahc->chip & AHC_PCI) != 0) 1054 sblkctl &= ~SELBUSB; 1055 switch (sblkctl) { 1056 case 0: 1057 /* Single Narrow Channel */ 1058 break; 1059 case 2: 1060 /* Wide Channel */ 1061 ahc->features |= AHC_WIDE; 1062 break; 1063 case 8: 1064 /* Twin Channel */ 1065 ahc->features |= AHC_TWIN; 1066 break; 1067 default: 1068 printf(" Unsupported adapter type. Ignoring\n"); 1069 return(-1); 1070 } 1071 1072 return (0); 1073 } 1074 1075 /* 1076 * Called when we have an active connection to a target on the bus, 1077 * this function finds the nearest syncrate to the input period limited 1078 * by the capabilities of the bus connectivity of the target. 1079 */ 1080 static struct ahc_syncrate * 1081 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1082 u_int maxsync; 1083 1084 if ((ahc->features & AHC_ULTRA2) != 0) { 1085 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1086 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1087 maxsync = AHC_SYNCRATE_ULTRA2; 1088 } else { 1089 maxsync = AHC_SYNCRATE_ULTRA; 1090 } 1091 } else if ((ahc->features & AHC_ULTRA) != 0) { 1092 maxsync = AHC_SYNCRATE_ULTRA; 1093 } else { 1094 maxsync = AHC_SYNCRATE_FAST; 1095 } 1096 return (ahc_find_syncrate(ahc, period, maxsync)); 1097 } 1098 1099 /* 1100 * Look up the valid period to SCSIRATE conversion in our table. 1101 * Return the period and offset that should be sent to the target 1102 * if this was the beginning of an SDTR. 1103 */ 1104 static struct ahc_syncrate * 1105 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1106 { 1107 struct ahc_syncrate *syncrate; 1108 1109 syncrate = &ahc_syncrates[maxsync]; 1110 while ((syncrate->rate != NULL) 1111 && ((ahc->features & AHC_ULTRA2) == 0 1112 || (syncrate->sxfr_u2 != 0))) { 1113 1114 if (*period <= syncrate->period) { 1115 /* 1116 * When responding to a target that requests 1117 * sync, the requested rate may fall between 1118 * two rates that we can output, but still be 1119 * a rate that we can receive. Because of this, 1120 * we want to respond to the target with 1121 * the same rate that it sent to us even 1122 * if the period we use to send data to it 1123 * is lower. Only lower the response period 1124 * if we must. 1125 */ 1126 if (syncrate == &ahc_syncrates[maxsync]) 1127 *period = syncrate->period; 1128 break; 1129 } 1130 syncrate++; 1131 } 1132 1133 if ((*period == 0) 1134 || (syncrate->rate == NULL) 1135 || ((ahc->features & AHC_ULTRA2) != 0 1136 && (syncrate->sxfr_u2 == 0))) { 1137 /* Use asynchronous transfers. */ 1138 *period = 0; 1139 syncrate = NULL; 1140 } 1141 return (syncrate); 1142 } 1143 1144 static u_int 1145 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1146 { 1147 struct ahc_syncrate *syncrate; 1148 1149 if ((ahc->features & AHC_ULTRA2) != 0) 1150 scsirate &= SXFR_ULTRA2; 1151 else 1152 scsirate &= SXFR; 1153 1154 syncrate = &ahc_syncrates[maxsync]; 1155 while (syncrate->rate != NULL) { 1156 1157 if ((ahc->features & AHC_ULTRA2) != 0) { 1158 if (syncrate->sxfr_u2 == 0) 1159 break; 1160 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1161 return (syncrate->period); 1162 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1163 return (syncrate->period); 1164 } 1165 syncrate++; 1166 } 1167 return (0); /* async */ 1168 } 1169 1170 static void 1171 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1172 u_int *offset, int wide) 1173 { 1174 u_int maxoffset; 1175 1176 /* Limit offset to what we can do */ 1177 if (syncrate == NULL) { 1178 maxoffset = 0; 1179 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1180 maxoffset = MAX_OFFSET_ULTRA2; 1181 } else { 1182 if (wide) 1183 maxoffset = MAX_OFFSET_16BIT; 1184 else 1185 maxoffset = MAX_OFFSET_8BIT; 1186 } 1187 *offset = MIN(*offset, maxoffset); 1188 } 1189 1190 static void 1191 ahc_update_target_msg_request(struct ahc_softc *ahc, 1192 struct ahc_devinfo *devinfo, 1193 struct ahc_initiator_tinfo *tinfo, 1194 int force, int paused) 1195 { 1196 u_int targ_msg_req_orig; 1197 1198 targ_msg_req_orig = ahc->targ_msg_req; 1199 if (tinfo->current.period != tinfo->goal.period 1200 || tinfo->current.width != tinfo->goal.width 1201 || tinfo->current.offset != tinfo->goal.offset 1202 || (force 1203 && (tinfo->goal.period != 0 1204 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1205 ahc->targ_msg_req |= devinfo->target_mask; 1206 } else { 1207 ahc->targ_msg_req &= ~devinfo->target_mask; 1208 } 1209 1210 if (ahc->targ_msg_req != targ_msg_req_orig) { 1211 /* Update the message request bit for this target */ 1212 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1213 if (paused) { 1214 ahc_outb(ahc, TARGET_MSG_REQUEST, 1215 ahc->targ_msg_req & 0xFF); 1216 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1217 (ahc->targ_msg_req >> 8) & 0xFF); 1218 } else { 1219 ahc_outb(ahc, HS_MAILBOX, 1220 0x01 << HOST_MAILBOX_SHIFT); 1221 } 1222 } else { 1223 if (!paused) 1224 pause_sequencer(ahc); 1225 1226 ahc_outb(ahc, TARGET_MSG_REQUEST, 1227 ahc->targ_msg_req & 0xFF); 1228 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1229 (ahc->targ_msg_req >> 8) & 0xFF); 1230 1231 if (!paused) 1232 unpause_sequencer(ahc); 1233 } 1234 } 1235 } 1236 1237 static void 1238 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1239 struct ahc_syncrate *syncrate, 1240 u_int period, u_int offset, u_int type, int paused, int done) 1241 { 1242 struct ahc_initiator_tinfo *tinfo; 1243 struct tmode_tstate *tstate; 1244 u_int old_period; 1245 u_int old_offset; 1246 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1247 1248 if (syncrate == NULL) { 1249 period = 0; 1250 offset = 0; 1251 } 1252 1253 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1254 devinfo->target, &tstate); 1255 old_period = tinfo->current.period; 1256 old_offset = tinfo->current.offset; 1257 1258 if ((type & AHC_TRANS_CUR) != 0 1259 && (old_period != period || old_offset != offset)) { 1260 u_int scsirate; 1261 1262 scsirate = tinfo->scsirate; 1263 if ((ahc->features & AHC_ULTRA2) != 0) { 1264 1265 /* XXX */ 1266 /* Force single edge until DT is fully implemented */ 1267 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1268 if (syncrate != NULL) 1269 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1270 1271 if (active) 1272 ahc_outb(ahc, SCSIOFFSET, offset); 1273 } else { 1274 1275 scsirate &= ~(SXFR|SOFS); 1276 /* 1277 * Ensure Ultra mode is set properly for 1278 * this target. 1279 */ 1280 tstate->ultraenb &= ~devinfo->target_mask; 1281 if (syncrate != NULL) { 1282 if (syncrate->sxfr & ULTRA_SXFR) { 1283 tstate->ultraenb |= 1284 devinfo->target_mask; 1285 } 1286 scsirate |= syncrate->sxfr & SXFR; 1287 scsirate |= offset & SOFS; 1288 } 1289 if (active) { 1290 u_int sxfrctl0; 1291 1292 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1293 sxfrctl0 &= ~FAST20; 1294 if (tstate->ultraenb & devinfo->target_mask) 1295 sxfrctl0 |= FAST20; 1296 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1297 } 1298 } 1299 if (active) 1300 ahc_outb(ahc, SCSIRATE, scsirate); 1301 1302 tinfo->scsirate = scsirate; 1303 tinfo->current.period = period; 1304 tinfo->current.offset = offset; 1305 1306 /* Update the syncrates in any pending scbs */ 1307 ahc_update_pending_syncrates(ahc); 1308 } 1309 1310 /* 1311 * Print messages if we're verbose and at the end of a negotiation 1312 * cycle. 1313 */ 1314 if (done) { 1315 if (offset != 0) { 1316 printf("%s: target %d synchronous at %sMHz, " 1317 "offset = 0x%x\n", ahc_name(ahc), 1318 devinfo->target, syncrate->rate, offset); 1319 } else { 1320 printf("%s: target %d using " 1321 "asynchronous transfers\n", 1322 ahc_name(ahc), devinfo->target); 1323 } 1324 } 1325 1326 if ((type & AHC_TRANS_GOAL) != 0) { 1327 tinfo->goal.period = period; 1328 tinfo->goal.offset = offset; 1329 } 1330 1331 if ((type & AHC_TRANS_USER) != 0) { 1332 tinfo->user.period = period; 1333 tinfo->user.offset = offset; 1334 } 1335 1336 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1337 /*force*/FALSE, 1338 paused); 1339 } 1340 1341 static void 1342 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1343 u_int width, u_int type, int paused, int done) 1344 { 1345 struct ahc_initiator_tinfo *tinfo; 1346 struct tmode_tstate *tstate; 1347 u_int oldwidth; 1348 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1349 1350 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1351 devinfo->target, &tstate); 1352 oldwidth = tinfo->current.width; 1353 1354 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1355 u_int scsirate; 1356 1357 scsirate = tinfo->scsirate; 1358 scsirate &= ~WIDEXFER; 1359 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1360 scsirate |= WIDEXFER; 1361 1362 tinfo->scsirate = scsirate; 1363 1364 if (active) 1365 ahc_outb(ahc, SCSIRATE, scsirate); 1366 1367 tinfo->current.width = width; 1368 } 1369 1370 if (done) { 1371 printf("%s: target %d using %dbit transfers\n", 1372 ahc_name(ahc), devinfo->target, 1373 8 * (0x01 << width)); 1374 } 1375 1376 if ((type & AHC_TRANS_GOAL) != 0) 1377 tinfo->goal.width = width; 1378 if ((type & AHC_TRANS_USER) != 0) 1379 tinfo->user.width = width; 1380 1381 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1382 /*force*/FALSE, paused); 1383 } 1384 1385 static void 1386 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1387 { 1388 struct ahc_initiator_tinfo *tinfo; 1389 struct tmode_tstate *tstate; 1390 1391 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1392 devinfo->target, &tstate); 1393 1394 if (enable) 1395 tstate->tagenable |= devinfo->target_mask; 1396 else { 1397 tstate->tagenable &= ~devinfo->target_mask; 1398 tstate->tagdisable |= devinfo->target_mask; 1399 } 1400 } 1401 1402 /* 1403 * Attach all the sub-devices we can find 1404 */ 1405 int 1406 ahc_attach(struct ahc_softc *ahc) 1407 { 1408 TAILQ_INIT(&ahc->sc_q); 1409 1410 ahc->sc_adapter.scsipi_cmd = ahc_action; 1411 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1412 ahc->sc_link.type = BUS_SCSI; 1413 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1414 ahc->sc_link.scsipi_scsi.channel = 0; 1415 ahc->sc_link.scsipi_scsi.max_target = 1416 (ahc->features & AHC_WIDE) ? 15 : 7; 1417 ahc->sc_link.scsipi_scsi.max_lun = 7; 1418 ahc->sc_link.adapter_softc = ahc; 1419 ahc->sc_link.adapter = &ahc->sc_adapter; 1420 ahc->sc_link.openings = 2; 1421 ahc->sc_link.device = &ahc_dev; 1422 1423 if (ahc->features & AHC_TWIN) { 1424 ahc->sc_link_b = ahc->sc_link; 1425 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1426 ahc->sc_link_b.scsipi_scsi.channel = 1; 1427 } 1428 1429 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1430 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1431 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1432 if (ahc->features & AHC_TWIN) 1433 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1434 } else { 1435 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1436 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1437 } 1438 return 1; 1439 } 1440 1441 static void 1442 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1443 { 1444 u_int saved_tcl; 1445 role_t role; 1446 int our_id; 1447 1448 if (ahc_inb(ahc, SSTAT0) & TARGET) 1449 role = ROLE_TARGET; 1450 else 1451 role = ROLE_INITIATOR; 1452 1453 if (role == ROLE_TARGET 1454 && (ahc->features & AHC_MULTI_TID) != 0 1455 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1456 /* We were selected, so pull our id from TARGIDIN */ 1457 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1458 } else if ((ahc->features & AHC_ULTRA2) != 0) 1459 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1460 else 1461 our_id = ahc_inb(ahc, SCSIID) & OID; 1462 1463 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1464 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1465 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1466 role); 1467 } 1468 1469 static void 1470 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1471 u_int lun, char channel, role_t role) 1472 { 1473 devinfo->our_scsiid = our_id; 1474 devinfo->target = target; 1475 devinfo->lun = lun; 1476 devinfo->target_offset = target; 1477 devinfo->channel = channel; 1478 devinfo->role = role; 1479 if (channel == 'B') 1480 devinfo->target_offset += 8; 1481 devinfo->target_mask = (0x01 << devinfo->target_offset); 1482 } 1483 1484 /* 1485 * Catch an interrupt from the adapter 1486 */ 1487 int 1488 ahc_intr(void *arg) 1489 { 1490 struct ahc_softc *ahc; 1491 u_int intstat; 1492 1493 ahc = (struct ahc_softc *)arg; 1494 1495 intstat = ahc_inb(ahc, INTSTAT); 1496 1497 /* 1498 * Any interrupts to process? 1499 */ 1500 if ((intstat & INT_PEND) == 0) { 1501 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1502 #ifdef AHC_DEBUG 1503 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1504 ahc_name(ahc), 1505 ahc_inb(ahc, CCHADDR) | 1506 (ahc_inb(ahc, CCHADDR+1) << 8) 1507 | (ahc_inb(ahc, CCHADDR+2) << 16) 1508 | (ahc_inb(ahc, CCHADDR+3) << 24), 1509 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1510 | (ahc_inb(ahc, HADDR+2) << 16) 1511 | (ahc_inb(ahc, HADDR+3) << 24), 1512 ahc_inb(ahc, SEQADDR0) | 1513 (ahc_inb(ahc, SEQADDR1) << 8)); 1514 #endif 1515 return 1; 1516 } 1517 return 0; 1518 } 1519 1520 #ifdef AHC_DEBUG 1521 if (ahc_debug & AHC_SHOWINTR) { 1522 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1523 } 1524 #endif 1525 1526 if (intstat & CMDCMPLT) { 1527 ahc_outb(ahc, CLRINT, CLRCMDINT); 1528 ahc_run_qoutfifo(ahc); 1529 } 1530 if (intstat & BRKADRINT) { 1531 /* 1532 * We upset the sequencer :-( 1533 * Lookup the error message 1534 */ 1535 int i, error, num_errors; 1536 1537 error = ahc_inb(ahc, ERROR); 1538 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1539 for (i = 0; error != 1 && i < num_errors; i++) 1540 error >>= 1; 1541 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1542 ahc_name(ahc), hard_error[i].errmesg, 1543 ahc_inb(ahc, SEQADDR0) | 1544 (ahc_inb(ahc, SEQADDR1) << 8)); 1545 1546 /* Tell everyone that this HBA is no longer availible */ 1547 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1548 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1549 XS_DRIVER_STUFFUP); 1550 } 1551 if (intstat & SEQINT) 1552 ahc_handle_seqint(ahc, intstat); 1553 1554 if (intstat & SCSIINT) 1555 ahc_handle_scsiint(ahc, intstat); 1556 1557 return 1; 1558 } 1559 1560 static struct tmode_tstate * 1561 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1562 { 1563 struct tmode_tstate *master_tstate; 1564 struct tmode_tstate *tstate; 1565 int i, s; 1566 1567 master_tstate = ahc->enabled_targets[ahc->our_id]; 1568 if (channel == 'B') { 1569 scsi_id += 8; 1570 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1571 } 1572 if (ahc->enabled_targets[scsi_id] != NULL 1573 && ahc->enabled_targets[scsi_id] != master_tstate) 1574 panic("%s: ahc_alloc_tstate - Target already allocated", 1575 ahc_name(ahc)); 1576 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1577 if (tstate == NULL) 1578 return (NULL); 1579 1580 /* 1581 * If we have allocated a master tstate, copy user settings from 1582 * the master tstate (taken from SRAM or the EEPROM) for this 1583 * channel, but reset our current and goal settings to async/narrow 1584 * until an initiator talks to us. 1585 */ 1586 if (master_tstate != NULL) { 1587 bcopy(master_tstate, tstate, sizeof(*tstate)); 1588 tstate->ultraenb = 0; 1589 for (i = 0; i < 16; i++) { 1590 bzero(&tstate->transinfo[i].current, 1591 sizeof(tstate->transinfo[i].current)); 1592 bzero(&tstate->transinfo[i].goal, 1593 sizeof(tstate->transinfo[i].goal)); 1594 } 1595 } else 1596 bzero(tstate, sizeof(*tstate)); 1597 s = splbio(); 1598 ahc->enabled_targets[scsi_id] = tstate; 1599 splx(s); 1600 return (tstate); 1601 } 1602 1603 #if UNUSED 1604 static void 1605 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1606 { 1607 struct tmode_tstate *tstate; 1608 1609 /* Don't clean up the entry for our initiator role */ 1610 if ((ahc->flags & AHC_INITIATORMODE) != 0 1611 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1612 || (channel == 'A' && scsi_id == ahc->our_id)) 1613 && force == FALSE) 1614 return; 1615 1616 if (channel == 'B') 1617 scsi_id += 8; 1618 tstate = ahc->enabled_targets[scsi_id]; 1619 if (tstate != NULL) 1620 free(tstate, M_DEVBUF); 1621 ahc->enabled_targets[scsi_id] = NULL; 1622 } 1623 #endif 1624 1625 static void 1626 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1627 { 1628 struct scb *scb; 1629 struct ahc_devinfo devinfo; 1630 1631 ahc_fetch_devinfo(ahc, &devinfo); 1632 1633 /* 1634 * Clear the upper byte that holds SEQINT status 1635 * codes and clear the SEQINT bit. We will unpause 1636 * the sequencer, if appropriate, after servicing 1637 * the request. 1638 */ 1639 ahc_outb(ahc, CLRINT, CLRSEQINT); 1640 switch (intstat & SEQINT_MASK) { 1641 case NO_MATCH: 1642 { 1643 /* Ensure we don't leave the selection hardware on */ 1644 ahc_outb(ahc, SCSISEQ, 1645 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1646 1647 printf("%s:%c:%d: no active SCB for reconnecting " 1648 "target - issuing BUS DEVICE RESET\n", 1649 ahc_name(ahc), devinfo.channel, devinfo.target); 1650 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1651 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1652 ahc_inb(ahc, SEQ_FLAGS)); 1653 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1654 ahc->msgout_len = 1; 1655 ahc->msgout_index = 0; 1656 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1657 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1658 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1659 break; 1660 } 1661 case UPDATE_TMSG_REQ: 1662 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1663 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1664 (ahc->targ_msg_req >> 8) & 0xFF); 1665 ahc_outb(ahc, HS_MAILBOX, 0); 1666 break; 1667 case SEND_REJECT: 1668 { 1669 u_int rejbyte = ahc_inb(ahc, ACCUM); 1670 printf("%s:%c:%d: Warning - unknown message received from " 1671 "target (0x%x). Rejecting\n", 1672 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1673 break; 1674 } 1675 case NO_IDENT: 1676 { 1677 /* 1678 * The reconnecting target either did not send an identify 1679 * message, or did, but we didn't find and SCB to match and 1680 * before it could respond to our ATN/abort, it hit a dataphase. 1681 * The only safe thing to do is to blow it away with a bus 1682 * reset. 1683 */ 1684 int found; 1685 1686 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1687 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1688 ahc_name(ahc), devinfo.channel, devinfo.target, 1689 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1690 found = ahc_reset_channel(ahc, devinfo.channel, 1691 /*initiate reset*/TRUE); 1692 printf("%s: Issued Channel %c Bus Reset. " 1693 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1694 found); 1695 return; 1696 } 1697 case BAD_PHASE: 1698 { 1699 u_int lastphase; 1700 1701 lastphase = ahc_inb(ahc, LASTPHASE); 1702 if (lastphase == P_BUSFREE) { 1703 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1704 ahc_name(ahc), devinfo.channel, devinfo.target, 1705 ahc_inb(ahc, SCSISIGI)); 1706 restart_sequencer(ahc); 1707 return; 1708 } else { 1709 printf("%s:%c:%d: unknown scsi bus phase %x. " 1710 "Attempting to continue\n", 1711 ahc_name(ahc), devinfo.channel, devinfo.target, 1712 ahc_inb(ahc, SCSISIGI)); 1713 } 1714 break; 1715 } 1716 case BAD_STATUS: 1717 { 1718 u_int scb_index; 1719 struct hardware_scb *hscb; 1720 struct scsipi_xfer *xs; 1721 /* 1722 * The sequencer will notify us when a command 1723 * has an error that would be of interest to 1724 * the kernel. This allows us to leave the sequencer 1725 * running in the common case of command completes 1726 * without error. The sequencer will already have 1727 * dma'd the SCB back up to us, so we can reference 1728 * the in kernel copy directly. 1729 */ 1730 scb_index = ahc_inb(ahc, SCB_TAG); 1731 scb = &ahc->scb_data->scbarray[scb_index]; 1732 1733 /* ahc_print_scb(scb); */ 1734 1735 /* 1736 * Set the default return value to 0 (don't 1737 * send sense). The sense code will change 1738 * this if needed. 1739 */ 1740 ahc_outb(ahc, RETURN_1, 0); 1741 if (!(scb_index < ahc->scb_data->numscbs 1742 && (scb->flags & SCB_ACTIVE) != 0)) { 1743 printf("%s:%c:%d: ahc_intr - referenced scb " 1744 "not valid during seqint 0x%x scb(%d)\n", 1745 ahc_name(ahc), devinfo.channel, 1746 devinfo.target, intstat, scb_index); 1747 goto unpause; 1748 } 1749 1750 hscb = scb->hscb; 1751 xs = scb->xs; 1752 1753 /* Don't want to clobber the original sense code */ 1754 if ((scb->flags & SCB_SENSE) != 0) { 1755 /* 1756 * Clear the SCB_SENSE Flag and have 1757 * the sequencer do a normal command 1758 * complete. 1759 */ 1760 scb->flags &= ~SCB_SENSE; 1761 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1762 break; 1763 } 1764 /* Freeze the queue unit the client sees the error. */ 1765 ahc_freeze_devq(ahc, xs->sc_link); 1766 ahc_freeze_ccb(scb); 1767 xs->status = hscb->status; 1768 switch (hscb->status) { 1769 case SCSI_STATUS_OK: 1770 printf("%s: Interrupted for status of 0???\n", 1771 ahc_name(ahc)); 1772 break; 1773 case SCSI_STATUS_CMD_TERMINATED: 1774 case SCSI_STATUS_CHECK_COND: 1775 #if defined(AHC_DEBUG) 1776 if (ahc_debug & AHC_SHOWSENSE) { 1777 scsi_print_addr(xs->sc_link); 1778 printf("Check Status, resid %d datalen %d\n", 1779 xs->resid, xs->datalen); 1780 } 1781 #endif 1782 1783 if (xs->error == XS_NOERROR && 1784 !(scb->flags & SCB_SENSE)) { 1785 struct ahc_dma_seg *sg; 1786 struct scsipi_sense *sc; 1787 struct ahc_initiator_tinfo *tinfo; 1788 struct tmode_tstate *tstate; 1789 1790 sg = scb->sg_list; 1791 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1792 /* 1793 * Save off the residual if there is one. 1794 */ 1795 if (hscb->residual_SG_count != 0) 1796 ahc_calc_residual(scb); 1797 else 1798 xs->resid = 0; 1799 1800 #ifdef AHC_DEBUG 1801 if (ahc_debug & AHC_SHOWSENSE) { 1802 scsi_print_addr(xs->sc_link); 1803 printf("Sending Sense\n"); 1804 } 1805 #endif 1806 sg->addr = ahc->scb_data->sense_busaddr + 1807 (hscb->tag*sizeof(struct scsipi_sense_data)); 1808 sg->len = sizeof (struct scsipi_sense_data); 1809 1810 sc->opcode = REQUEST_SENSE; 1811 sc->byte2 = SCB_LUN(scb) << 5; 1812 sc->unused[0] = 0; 1813 sc->unused[1] = 0; 1814 sc->length = sg->len; 1815 sc->control = 0; 1816 1817 /* 1818 * Would be nice to preserve DISCENB here, 1819 * but due to the way we page SCBs, we can't. 1820 */ 1821 hscb->control = 0; 1822 1823 /* 1824 * This request sense could be because the 1825 * the device lost power or in some other 1826 * way has lost our transfer negotiations. 1827 * Renegotiate if appropriate. Unit attention 1828 * errors will be reported before any data 1829 * phases occur. 1830 */ 1831 ahc_calc_residual(scb); 1832 #if defined(AHC_DEBUG) 1833 if (ahc_debug & AHC_SHOWSENSE) { 1834 scsi_print_addr(xs->sc_link); 1835 printf("Sense: datalen %d resid %d" 1836 "chan %d id %d targ %d\n", 1837 xs->datalen, xs->resid, 1838 devinfo.channel, devinfo.our_scsiid, 1839 devinfo.target); 1840 } 1841 #endif 1842 if (xs->datalen > 0 && 1843 xs->resid == xs->datalen) { 1844 tinfo = ahc_fetch_transinfo(ahc, 1845 devinfo.channel, 1846 devinfo.our_scsiid, 1847 devinfo.target, 1848 &tstate); 1849 ahc_update_target_msg_request(ahc, 1850 &devinfo, 1851 tinfo, 1852 /*force*/TRUE, 1853 /*paused*/TRUE); 1854 } 1855 hscb->status = 0; 1856 hscb->SG_count = 1; 1857 hscb->SG_pointer = scb->sg_list_phys; 1858 hscb->data = sg->addr; 1859 hscb->datalen = sg->len; 1860 hscb->cmdpointer = hscb->cmdstore_busaddr; 1861 hscb->cmdlen = sizeof(*sc); 1862 scb->sg_count = hscb->SG_count; 1863 ahc_swap_hscb(hscb); 1864 ahc_swap_sg(scb->sg_list); 1865 scb->flags |= SCB_SENSE; 1866 /* 1867 * Ensure the target is busy since this 1868 * will be an untagged request. 1869 */ 1870 ahc_busy_tcl(ahc, scb); 1871 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1872 1873 /* 1874 * Ensure we have enough time to actually 1875 * retrieve the sense. 1876 */ 1877 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1878 callout_reset(&scb->xs->xs_callout, 1879 5 * hz, ahc_timeout, scb); 1880 } 1881 } 1882 break; 1883 case SCSI_STATUS_QUEUE_FULL: 1884 scsi_print_addr(xs->sc_link); 1885 printf("queue full\n"); 1886 case SCSI_STATUS_BUSY: 1887 /* 1888 * Requeue any transactions that haven't been 1889 * sent yet. 1890 */ 1891 ahc_freeze_devq(ahc, xs->sc_link); 1892 ahc_freeze_ccb(scb); 1893 break; 1894 } 1895 break; 1896 } 1897 case TRACE_POINT: 1898 { 1899 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1900 ahc_inb(ahc, DFCNTRL)); 1901 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1902 ahc_inb(ahc, DFSTATUS)); 1903 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1904 ahc_inb(ahc, SSTAT0), 1905 ahc_inb(ahc, SCB_DATACNT)); 1906 break; 1907 } 1908 case HOST_MSG_LOOP: 1909 { 1910 /* 1911 * The sequencer has encountered a message phase 1912 * that requires host assistance for completion. 1913 * While handling the message phase(s), we will be 1914 * notified by the sequencer after each byte is 1915 * transfered so we can track bus phases. 1916 * 1917 * If this is the first time we've seen a HOST_MSG_LOOP, 1918 * initialize the state of the host message loop. 1919 */ 1920 if (ahc->msg_type == MSG_TYPE_NONE) { 1921 u_int bus_phase; 1922 1923 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1924 if (bus_phase != P_MESGIN 1925 && bus_phase != P_MESGOUT) { 1926 printf("ahc_intr: HOST_MSG_LOOP bad " 1927 "phase 0x%x\n", 1928 bus_phase); 1929 /* 1930 * Probably transitioned to bus free before 1931 * we got here. Just punt the message. 1932 */ 1933 ahc_clear_intstat(ahc); 1934 restart_sequencer(ahc); 1935 } 1936 1937 if (devinfo.role == ROLE_INITIATOR) { 1938 struct scb *scb; 1939 u_int scb_index; 1940 1941 scb_index = ahc_inb(ahc, SCB_TAG); 1942 scb = &ahc->scb_data->scbarray[scb_index]; 1943 1944 if (bus_phase == P_MESGOUT) 1945 ahc_setup_initiator_msgout(ahc, 1946 &devinfo, 1947 scb); 1948 else { 1949 ahc->msg_type = 1950 MSG_TYPE_INITIATOR_MSGIN; 1951 ahc->msgin_index = 0; 1952 } 1953 } else { 1954 if (bus_phase == P_MESGOUT) { 1955 ahc->msg_type = 1956 MSG_TYPE_TARGET_MSGOUT; 1957 ahc->msgin_index = 0; 1958 } else 1959 /* XXX Ever executed??? */ 1960 ahc_setup_target_msgin(ahc, &devinfo); 1961 } 1962 } 1963 1964 /* Pass a NULL path so that handlers generate their own */ 1965 ahc_handle_message_phase(ahc, /*path*/NULL); 1966 break; 1967 } 1968 case PERR_DETECTED: 1969 { 1970 /* 1971 * If we've cleared the parity error interrupt 1972 * but the sequencer still believes that SCSIPERR 1973 * is true, it must be that the parity error is 1974 * for the currently presented byte on the bus, 1975 * and we are not in a phase (data-in) where we will 1976 * eventually ack this byte. Ack the byte and 1977 * throw it away in the hope that the target will 1978 * take us to message out to deliver the appropriate 1979 * error message. 1980 */ 1981 if ((intstat & SCSIINT) == 0 1982 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1983 u_int curphase; 1984 1985 /* 1986 * The hardware will only let you ack bytes 1987 * if the expected phase in SCSISIGO matches 1988 * the current phase. Make sure this is 1989 * currently the case. 1990 */ 1991 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1992 ahc_outb(ahc, LASTPHASE, curphase); 1993 ahc_outb(ahc, SCSISIGO, curphase); 1994 ahc_inb(ahc, SCSIDATL); 1995 } 1996 break; 1997 } 1998 case DATA_OVERRUN: 1999 { 2000 /* 2001 * When the sequencer detects an overrun, it 2002 * places the controller in "BITBUCKET" mode 2003 * and allows the target to complete its transfer. 2004 * Unfortunately, none of the counters get updated 2005 * when the controller is in this mode, so we have 2006 * no way of knowing how large the overrun was. 2007 */ 2008 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2009 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2010 int i; 2011 2012 scb = &ahc->scb_data->scbarray[scbindex]; 2013 for (i = 0; i < num_phases; i++) { 2014 if (lastphase == phase_table[i].phase) 2015 break; 2016 } 2017 scsi_print_addr(scb->xs->sc_link); 2018 printf("data overrun detected %s." 2019 " Tag == 0x%x.\n", 2020 phase_table[i].phasemsg, 2021 scb->hscb->tag); 2022 scsi_print_addr(scb->xs->sc_link); 2023 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2024 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2025 scb->xs->datalen, scb->sg_count); 2026 if (scb->sg_count > 0) { 2027 for (i = 0; i < scb->sg_count; i++) { 2028 printf("sg[%d] - Addr 0x%x : Length %d\n", 2029 i, 2030 le32toh(scb->sg_list[i].addr), 2031 le32toh(scb->sg_list[i].len)); 2032 } 2033 } 2034 /* 2035 * Set this and it will take affect when the 2036 * target does a command complete. 2037 */ 2038 ahc_freeze_devq(ahc, scb->xs->sc_link); 2039 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2040 ahc_freeze_ccb(scb); 2041 break; 2042 } 2043 case TRACEPOINT: 2044 { 2045 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2046 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2047 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2048 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2049 printf("TRACEPOINT: CCHADDR = %x\n", 2050 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2051 | (ahc_inb(ahc, CCHADDR+2) << 16) 2052 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2053 #if 0 2054 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2055 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2056 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2057 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2058 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2059 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2060 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2061 ahc_inb(ahc, CCHADDR) 2062 | (ahc_inb(ahc, CCHADDR+1) << 8) 2063 | (ahc_inb(ahc, CCHADDR+2) << 16) 2064 | (ahc_inb(ahc, CCHADDR+3) << 24), 2065 ahc_inb(ahc, CCHCNT) 2066 | (ahc_inb(ahc, CCHCNT+1) << 8) 2067 | (ahc_inb(ahc, CCHCNT+2) << 16), 2068 ahc_inb(ahc, SCBPTR)); 2069 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2070 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2071 #if DDB > 0 2072 cpu_Debugger(); 2073 #endif 2074 #endif 2075 break; 2076 } 2077 #if NOT_YET 2078 /* XXX Fill these in later */ 2079 case MESG_BUFFER_BUSY: 2080 break; 2081 case MSGIN_PHASEMIS: 2082 break; 2083 #endif 2084 default: 2085 printf("ahc_intr: seqint, " 2086 "intstat == 0x%x, scsisigi = 0x%x\n", 2087 intstat, ahc_inb(ahc, SCSISIGI)); 2088 break; 2089 } 2090 2091 unpause: 2092 /* 2093 * The sequencer is paused immediately on 2094 * a SEQINT, so we should restart it when 2095 * we're done. 2096 */ 2097 unpause_sequencer(ahc); 2098 } 2099 2100 static void 2101 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2102 { 2103 u_int scb_index; 2104 u_int status; 2105 struct scb *scb; 2106 char cur_channel; 2107 char intr_channel; 2108 2109 if ((ahc->features & AHC_TWIN) != 0 2110 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2111 cur_channel = 'B'; 2112 else 2113 cur_channel = 'A'; 2114 intr_channel = cur_channel; 2115 2116 status = ahc_inb(ahc, SSTAT1); 2117 if (status == 0) { 2118 if ((ahc->features & AHC_TWIN) != 0) { 2119 /* Try the other channel */ 2120 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2121 status = ahc_inb(ahc, SSTAT1); 2122 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2123 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2124 } 2125 if (status == 0) { 2126 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2127 return; 2128 } 2129 } 2130 2131 scb_index = ahc_inb(ahc, SCB_TAG); 2132 if (scb_index < ahc->scb_data->numscbs) { 2133 scb = &ahc->scb_data->scbarray[scb_index]; 2134 if ((scb->flags & SCB_ACTIVE) == 0 2135 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2136 scb = NULL; 2137 } else 2138 scb = NULL; 2139 2140 if ((status & SCSIRSTI) != 0) { 2141 printf("%s: Someone reset channel %c\n", 2142 ahc_name(ahc), intr_channel); 2143 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2144 } else if ((status & SCSIPERR) != 0) { 2145 /* 2146 * Determine the bus phase and queue an appropriate message. 2147 * SCSIPERR is latched true as soon as a parity error 2148 * occurs. If the sequencer acked the transfer that 2149 * caused the parity error and the currently presented 2150 * transfer on the bus has correct parity, SCSIPERR will 2151 * be cleared by CLRSCSIPERR. Use this to determine if 2152 * we should look at the last phase the sequencer recorded, 2153 * or the current phase presented on the bus. 2154 */ 2155 u_int mesg_out; 2156 u_int curphase; 2157 u_int errorphase; 2158 u_int lastphase; 2159 int i; 2160 2161 lastphase = ahc_inb(ahc, LASTPHASE); 2162 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2163 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2164 /* 2165 * For all phases save DATA, the sequencer won't 2166 * automatically ack a byte that has a parity error 2167 * in it. So the only way that the current phase 2168 * could be 'data-in' is if the parity error is for 2169 * an already acked byte in the data phase. During 2170 * synchronous data-in transfers, we may actually 2171 * ack bytes before latching the current phase in 2172 * LASTPHASE, leading to the discrepancy between 2173 * curphase and lastphase. 2174 */ 2175 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2176 || curphase == P_DATAIN) 2177 errorphase = curphase; 2178 else 2179 errorphase = lastphase; 2180 2181 for (i = 0; i < num_phases; i++) { 2182 if (errorphase == phase_table[i].phase) 2183 break; 2184 } 2185 mesg_out = phase_table[i].mesg_out; 2186 if (scb != NULL) 2187 scsi_print_addr(scb->xs->sc_link); 2188 else 2189 printf("%s:%c:%d: ", ahc_name(ahc), 2190 intr_channel, 2191 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2192 2193 printf("parity error detected %s. " 2194 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2195 phase_table[i].phasemsg, 2196 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2197 ahc_inb(ahc, SCSIRATE)); 2198 2199 /* 2200 * We've set the hardware to assert ATN if we 2201 * get a parity error on "in" phases, so all we 2202 * need to do is stuff the message buffer with 2203 * the appropriate message. "In" phases have set 2204 * mesg_out to something other than MSG_NOP. 2205 */ 2206 if (mesg_out != MSG_NOOP) { 2207 if (ahc->msg_type != MSG_TYPE_NONE) 2208 ahc->send_msg_perror = TRUE; 2209 else 2210 ahc_outb(ahc, MSG_OUT, mesg_out); 2211 } 2212 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2213 unpause_sequencer(ahc); 2214 } else if ((status & BUSFREE) != 0 2215 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2216 /* 2217 * First look at what phase we were last in. 2218 * If its message out, chances are pretty good 2219 * that the busfree was in response to one of 2220 * our abort requests. 2221 */ 2222 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2223 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2224 u_int target = TCL_TARGET(saved_tcl); 2225 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2226 char channel = TCL_CHANNEL(ahc, saved_tcl); 2227 int printerror = 1; 2228 2229 ahc_outb(ahc, SCSISEQ, 2230 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2231 if (lastphase == P_MESGOUT) { 2232 u_int message; 2233 u_int tag; 2234 2235 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2236 tag = SCB_LIST_NULL; 2237 switch (message) { 2238 case MSG_ABORT_TAG: 2239 tag = scb->hscb->tag; 2240 /* FALLTRHOUGH */ 2241 case MSG_ABORT: 2242 scsi_print_addr(scb->xs->sc_link); 2243 printf("SCB %x - Abort %s Completed.\n", 2244 scb->hscb->tag, tag == SCB_LIST_NULL ? 2245 "" : "Tag"); 2246 ahc_abort_scbs(ahc, target, channel, 2247 TCL_LUN(saved_tcl), tag, 2248 ROLE_INITIATOR, 2249 XS_DRIVER_STUFFUP); 2250 printerror = 0; 2251 break; 2252 case MSG_BUS_DEV_RESET: 2253 { 2254 struct ahc_devinfo devinfo; 2255 2256 if (scb != NULL && 2257 (scb->xs->xs_control & XS_CTL_RESET) 2258 && ahc_match_scb(scb, target, channel, 2259 TCL_LUN(saved_tcl), 2260 SCB_LIST_NULL, 2261 ROLE_INITIATOR)) { 2262 ahcsetccbstatus(scb->xs, XS_NOERROR); 2263 } 2264 ahc_compile_devinfo(&devinfo, 2265 initiator_role_id, 2266 target, 2267 TCL_LUN(saved_tcl), 2268 channel, 2269 ROLE_INITIATOR); 2270 ahc_handle_devreset(ahc, &devinfo, 2271 XS_RESET, 2272 "Bus Device Reset", 2273 /*verbose_level*/0); 2274 printerror = 0; 2275 break; 2276 } 2277 default: 2278 break; 2279 } 2280 } 2281 if (printerror != 0) { 2282 int i; 2283 2284 if (scb != NULL) { 2285 u_int tag; 2286 2287 if ((scb->hscb->control & TAG_ENB) != 0) 2288 tag = scb->hscb->tag; 2289 else 2290 tag = SCB_LIST_NULL; 2291 ahc_abort_scbs(ahc, target, channel, 2292 SCB_LUN(scb), tag, 2293 ROLE_INITIATOR, 2294 XS_DRIVER_STUFFUP); 2295 scsi_print_addr(scb->xs->sc_link); 2296 } else { 2297 /* 2298 * We had not fully identified this connection, 2299 * so we cannot abort anything. 2300 */ 2301 printf("%s: ", ahc_name(ahc)); 2302 } 2303 for (i = 0; i < num_phases; i++) { 2304 if (lastphase == phase_table[i].phase) 2305 break; 2306 } 2307 printf("Unexpected busfree %s\n" 2308 "SEQADDR == 0x%x\n", 2309 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2310 | (ahc_inb(ahc, SEQADDR1) << 8)); 2311 } 2312 ahc_clear_msg_state(ahc); 2313 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2314 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2315 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2316 restart_sequencer(ahc); 2317 } else if ((status & SELTO) != 0) { 2318 u_int scbptr; 2319 2320 scbptr = ahc_inb(ahc, WAITING_SCBH); 2321 ahc_outb(ahc, SCBPTR, scbptr); 2322 scb_index = ahc_inb(ahc, SCB_TAG); 2323 2324 if (scb_index < ahc->scb_data->numscbs) { 2325 scb = &ahc->scb_data->scbarray[scb_index]; 2326 if ((scb->flags & SCB_ACTIVE) == 0) 2327 scb = NULL; 2328 } else 2329 scb = NULL; 2330 2331 if (scb == NULL) { 2332 printf("%s: ahc_intr - referenced scb not " 2333 "valid during SELTO scb(%d, %d)\n", 2334 ahc_name(ahc), scbptr, scb_index); 2335 } else { 2336 u_int tag; 2337 2338 tag = SCB_LIST_NULL; 2339 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2340 tag = scb->hscb->tag; 2341 2342 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2343 SCB_LUN(scb), tag, 2344 ROLE_INITIATOR, XS_SELTIMEOUT); 2345 } 2346 /* Stop the selection */ 2347 ahc_outb(ahc, SCSISEQ, 0); 2348 2349 /* No more pending messages */ 2350 ahc_clear_msg_state(ahc); 2351 2352 /* 2353 * Although the driver does not care about the 2354 * 'Selection in Progress' status bit, the busy 2355 * LED does. SELINGO is only cleared by a sucessful 2356 * selection, so we must manually clear it to ensure 2357 * the LED turns off just incase no future successful 2358 * selections occur (e.g. no devices on the bus). 2359 */ 2360 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2361 2362 /* Clear interrupt state */ 2363 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2364 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2365 restart_sequencer(ahc); 2366 } else { 2367 scsi_print_addr(scb->xs->sc_link); 2368 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2369 ahc_outb(ahc, CLRSINT1, status); 2370 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2371 unpause_sequencer(ahc); 2372 } 2373 } 2374 2375 static void 2376 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2377 { 2378 /* 2379 * We need to initiate transfer negotiations. 2380 * If our current and goal settings are identical, 2381 * we want to renegotiate due to a check condition. 2382 */ 2383 struct ahc_initiator_tinfo *tinfo; 2384 struct tmode_tstate *tstate; 2385 int dowide; 2386 int dosync; 2387 2388 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2389 devinfo->target, &tstate); 2390 dowide = tinfo->current.width != tinfo->goal.width; 2391 dosync = tinfo->current.period != tinfo->goal.period; 2392 2393 if (!dowide && !dosync) { 2394 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2395 dosync = tinfo->goal.period != 0; 2396 } 2397 2398 if (dowide) { 2399 ahc_construct_wdtr(ahc, tinfo->goal.width); 2400 } else if (dosync) { 2401 struct ahc_syncrate *rate; 2402 u_int period; 2403 u_int offset; 2404 2405 period = tinfo->goal.period; 2406 rate = ahc_devlimited_syncrate(ahc, &period); 2407 offset = tinfo->goal.offset; 2408 ahc_validate_offset(ahc, rate, &offset, 2409 tinfo->current.width); 2410 ahc_construct_sdtr(ahc, period, offset); 2411 } else { 2412 panic("ahc_intr: AWAITING_MSG for negotiation, " 2413 "but no negotiation needed\n"); 2414 } 2415 } 2416 2417 static void 2418 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2419 struct scb *scb) 2420 { 2421 /* 2422 * To facilitate adding multiple messages together, 2423 * each routine should increment the index and len 2424 * variables instead of setting them explicitly. 2425 */ 2426 ahc->msgout_index = 0; 2427 ahc->msgout_len = 0; 2428 2429 if ((scb->flags & SCB_DEVICE_RESET) == 0 2430 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2431 u_int identify_msg; 2432 2433 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2434 if ((scb->hscb->control & DISCENB) != 0) 2435 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2436 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2437 ahc->msgout_len++; 2438 2439 if ((scb->hscb->control & TAG_ENB) != 0) { 2440 /* XXX fvdl FreeBSD has tag action passed down */ 2441 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2442 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2443 ahc->msgout_len += 2; 2444 } 2445 } 2446 2447 if (scb->flags & SCB_DEVICE_RESET) { 2448 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2449 ahc->msgout_len++; 2450 scsi_print_addr(scb->xs->sc_link); 2451 printf("Bus Device Reset Message Sent\n"); 2452 } else if (scb->flags & SCB_ABORT) { 2453 if ((scb->hscb->control & TAG_ENB) != 0) 2454 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2455 else 2456 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2457 ahc->msgout_len++; 2458 scsi_print_addr(scb->xs->sc_link); 2459 printf("Abort Message Sent\n"); 2460 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2461 ahc_build_transfer_msg(ahc, devinfo); 2462 } else { 2463 printf("ahc_intr: AWAITING_MSG for an SCB that " 2464 "does not have a waiting message"); 2465 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2466 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2467 ahc_inb(ahc, MSG_OUT), scb->flags); 2468 } 2469 2470 /* 2471 * Clear the MK_MESSAGE flag from the SCB so we aren't 2472 * asked to send this message again. 2473 */ 2474 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2475 ahc->msgout_index = 0; 2476 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2477 } 2478 2479 static void 2480 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2481 { 2482 /* 2483 * To facilitate adding multiple messages together, 2484 * each routine should increment the index and len 2485 * variables instead of setting them explicitly. 2486 */ 2487 ahc->msgout_index = 0; 2488 ahc->msgout_len = 0; 2489 2490 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2491 ahc_build_transfer_msg(ahc, devinfo); 2492 else 2493 panic("ahc_intr: AWAITING target message with no message"); 2494 2495 ahc->msgout_index = 0; 2496 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2497 } 2498 2499 static int 2500 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2501 { 2502 /* 2503 * What we care about here is if we had an 2504 * outstanding SDTR or WDTR message for this 2505 * target. If we did, this is a signal that 2506 * the target is refusing negotiation. 2507 */ 2508 struct scb *scb; 2509 u_int scb_index; 2510 u_int last_msg; 2511 int response = 0; 2512 2513 scb_index = ahc_inb(ahc, SCB_TAG); 2514 scb = &ahc->scb_data->scbarray[scb_index]; 2515 2516 /* Might be necessary */ 2517 last_msg = ahc_inb(ahc, LAST_MSG); 2518 2519 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2520 struct ahc_initiator_tinfo *tinfo; 2521 struct tmode_tstate *tstate; 2522 2523 #ifdef AHC_DEBUG_NEG 2524 /* note 8bit xfers */ 2525 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2526 "8bit transfers\n", ahc_name(ahc), 2527 devinfo->channel, devinfo->target); 2528 #endif 2529 ahc_set_width(ahc, devinfo, 2530 MSG_EXT_WDTR_BUS_8_BIT, 2531 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2532 /*paused*/TRUE, /*done*/TRUE); 2533 /* 2534 * No need to clear the sync rate. If the target 2535 * did not accept the command, our syncrate is 2536 * unaffected. If the target started the negotiation, 2537 * but rejected our response, we already cleared the 2538 * sync rate before sending our WDTR. 2539 */ 2540 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2541 devinfo->our_scsiid, 2542 devinfo->target, &tstate); 2543 if (tinfo->goal.period) { 2544 u_int period; 2545 2546 /* Start the sync negotiation */ 2547 period = tinfo->goal.period; 2548 ahc_devlimited_syncrate(ahc, &period); 2549 ahc->msgout_index = 0; 2550 ahc->msgout_len = 0; 2551 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2552 ahc->msgout_index = 0; 2553 response = 1; 2554 } 2555 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2556 /* note asynch xfers and clear flag */ 2557 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2558 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2559 /*paused*/TRUE, /*done*/TRUE); 2560 #ifdef AHC_DEBUG_NEG 2561 printf("%s:%c:%d: refuses synchronous negotiation. " 2562 "Using asynchronous transfers\n", 2563 ahc_name(ahc), 2564 devinfo->channel, devinfo->target); 2565 #endif 2566 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2567 printf("%s:%c:%d: refuses tagged commands. Performing " 2568 "non-tagged I/O\n", ahc_name(ahc), 2569 devinfo->channel, devinfo->target); 2570 2571 ahc_set_tags(ahc, devinfo, FALSE); 2572 2573 /* 2574 * Resend the identify for this CCB as the target 2575 * may believe that the selection is invalid otherwise. 2576 */ 2577 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2578 & ~MSG_SIMPLE_Q_TAG); 2579 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2580 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2581 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2582 2583 /* 2584 * Requeue all tagged commands for this target 2585 * currently in our posession so they can be 2586 * converted to untagged commands. 2587 */ 2588 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2589 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2590 ROLE_INITIATOR, SCB_REQUEUE, 2591 SEARCH_COMPLETE); 2592 } else { 2593 /* 2594 * Otherwise, we ignore it. 2595 */ 2596 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2597 ahc_name(ahc), devinfo->channel, devinfo->target, 2598 last_msg); 2599 } 2600 return (response); 2601 } 2602 2603 static void 2604 ahc_clear_msg_state(struct ahc_softc *ahc) 2605 { 2606 ahc->msgout_len = 0; 2607 ahc->msgin_index = 0; 2608 ahc->msg_type = MSG_TYPE_NONE; 2609 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2610 } 2611 2612 static void 2613 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2614 { 2615 struct ahc_devinfo devinfo; 2616 u_int bus_phase; 2617 int end_session; 2618 2619 ahc_fetch_devinfo(ahc, &devinfo); 2620 end_session = FALSE; 2621 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2622 2623 reswitch: 2624 switch (ahc->msg_type) { 2625 case MSG_TYPE_INITIATOR_MSGOUT: 2626 { 2627 int lastbyte; 2628 int phasemis; 2629 int msgdone; 2630 2631 if (ahc->msgout_len == 0) 2632 panic("REQINIT interrupt with no active message"); 2633 2634 phasemis = bus_phase != P_MESGOUT; 2635 if (phasemis) { 2636 if (bus_phase == P_MESGIN) { 2637 /* 2638 * Change gears and see if 2639 * this messages is of interest to 2640 * us or should be passed back to 2641 * the sequencer. 2642 */ 2643 ahc_outb(ahc, CLRSINT1, CLRATNO); 2644 ahc->send_msg_perror = FALSE; 2645 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2646 ahc->msgin_index = 0; 2647 goto reswitch; 2648 } 2649 end_session = TRUE; 2650 break; 2651 } 2652 2653 if (ahc->send_msg_perror) { 2654 ahc_outb(ahc, CLRSINT1, CLRATNO); 2655 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2656 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2657 break; 2658 } 2659 2660 msgdone = ahc->msgout_index == ahc->msgout_len; 2661 if (msgdone) { 2662 /* 2663 * The target has requested a retry. 2664 * Re-assert ATN, reset our message index to 2665 * 0, and try again. 2666 */ 2667 ahc->msgout_index = 0; 2668 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2669 } 2670 2671 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2672 if (lastbyte) { 2673 /* Last byte is signified by dropping ATN */ 2674 ahc_outb(ahc, CLRSINT1, CLRATNO); 2675 } 2676 2677 /* 2678 * Clear our interrupt status and present 2679 * the next byte on the bus. 2680 */ 2681 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2682 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2683 break; 2684 } 2685 case MSG_TYPE_INITIATOR_MSGIN: 2686 { 2687 int phasemis; 2688 int message_done; 2689 2690 phasemis = bus_phase != P_MESGIN; 2691 2692 if (phasemis) { 2693 ahc->msgin_index = 0; 2694 if (bus_phase == P_MESGOUT 2695 && (ahc->send_msg_perror == TRUE 2696 || (ahc->msgout_len != 0 2697 && ahc->msgout_index == 0))) { 2698 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2699 goto reswitch; 2700 } 2701 end_session = TRUE; 2702 break; 2703 } 2704 2705 /* Pull the byte in without acking it */ 2706 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2707 2708 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2709 2710 if (message_done) { 2711 /* 2712 * Clear our incoming message buffer in case there 2713 * is another message following this one. 2714 */ 2715 ahc->msgin_index = 0; 2716 2717 /* 2718 * If this message illicited a response, 2719 * assert ATN so the target takes us to the 2720 * message out phase. 2721 */ 2722 if (ahc->msgout_len != 0) 2723 ahc_outb(ahc, SCSISIGO, 2724 ahc_inb(ahc, SCSISIGO) | ATNO); 2725 } else 2726 ahc->msgin_index++; 2727 2728 /* Ack the byte */ 2729 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2730 ahc_inb(ahc, SCSIDATL); 2731 break; 2732 } 2733 case MSG_TYPE_TARGET_MSGIN: 2734 { 2735 int msgdone; 2736 int msgout_request; 2737 2738 if (ahc->msgout_len == 0) 2739 panic("Target MSGIN with no active message"); 2740 2741 /* 2742 * If we interrupted a mesgout session, the initiator 2743 * will not know this until our first REQ. So, we 2744 * only honor mesgout requests after we've sent our 2745 * first byte. 2746 */ 2747 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2748 && ahc->msgout_index > 0) 2749 msgout_request = TRUE; 2750 else 2751 msgout_request = FALSE; 2752 2753 if (msgout_request) { 2754 2755 /* 2756 * Change gears and see if 2757 * this messages is of interest to 2758 * us or should be passed back to 2759 * the sequencer. 2760 */ 2761 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2762 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2763 ahc->msgin_index = 0; 2764 /* Dummy read to REQ for first byte */ 2765 ahc_inb(ahc, SCSIDATL); 2766 ahc_outb(ahc, SXFRCTL0, 2767 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2768 break; 2769 } 2770 2771 msgdone = ahc->msgout_index == ahc->msgout_len; 2772 if (msgdone) { 2773 ahc_outb(ahc, SXFRCTL0, 2774 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2775 end_session = TRUE; 2776 break; 2777 } 2778 2779 /* 2780 * Present the next byte on the bus. 2781 */ 2782 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2783 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2784 break; 2785 } 2786 case MSG_TYPE_TARGET_MSGOUT: 2787 { 2788 int lastbyte; 2789 int msgdone; 2790 2791 /* 2792 * The initiator signals that this is 2793 * the last byte by dropping ATN. 2794 */ 2795 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2796 2797 /* 2798 * Read the latched byte, but turn off SPIOEN first 2799 * so that we don't inadvertantly cause a REQ for the 2800 * next byte. 2801 */ 2802 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2803 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2804 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2805 if (msgdone == MSGLOOP_TERMINATED) { 2806 /* 2807 * The message is *really* done in that it caused 2808 * us to go to bus free. The sequencer has already 2809 * been reset at this point, so pull the ejection 2810 * handle. 2811 */ 2812 return; 2813 } 2814 2815 ahc->msgin_index++; 2816 2817 /* 2818 * XXX Read spec about initiator dropping ATN too soon 2819 * and use msgdone to detect it. 2820 */ 2821 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2822 ahc->msgin_index = 0; 2823 2824 /* 2825 * If this message illicited a response, transition 2826 * to the Message in phase and send it. 2827 */ 2828 if (ahc->msgout_len != 0) { 2829 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2830 ahc_outb(ahc, SXFRCTL0, 2831 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2832 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2833 ahc->msgin_index = 0; 2834 break; 2835 } 2836 } 2837 2838 if (lastbyte) 2839 end_session = TRUE; 2840 else { 2841 /* Ask for the next byte. */ 2842 ahc_outb(ahc, SXFRCTL0, 2843 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2844 } 2845 2846 break; 2847 } 2848 default: 2849 panic("Unknown REQINIT message type"); 2850 } 2851 2852 if (end_session) { 2853 ahc_clear_msg_state(ahc); 2854 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2855 } else 2856 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2857 } 2858 2859 /* 2860 * See if we sent a particular extended message to the target. 2861 * If "full" is true, the target saw the full message. 2862 * If "full" is false, the target saw at least the first 2863 * byte of the message. 2864 */ 2865 static int 2866 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2867 { 2868 int found; 2869 int index; 2870 2871 found = FALSE; 2872 index = 0; 2873 2874 while (index < ahc->msgout_len) { 2875 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2876 2877 /* Found a candidate */ 2878 if (ahc->msgout_buf[index+2] == msgtype) { 2879 u_int end_index; 2880 2881 end_index = index + 1 2882 + ahc->msgout_buf[index + 1]; 2883 if (full) { 2884 if (ahc->msgout_index > end_index) 2885 found = TRUE; 2886 } else if (ahc->msgout_index > index) 2887 found = TRUE; 2888 } 2889 break; 2890 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2891 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2892 2893 /* Skip tag type and tag id or residue param*/ 2894 index += 2; 2895 } else { 2896 /* Single byte message */ 2897 index++; 2898 } 2899 } 2900 return (found); 2901 } 2902 2903 static int 2904 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2905 struct ahc_devinfo *devinfo) 2906 { 2907 struct ahc_initiator_tinfo *tinfo; 2908 struct tmode_tstate *tstate; 2909 int reject; 2910 int done; 2911 int response; 2912 u_int targ_scsirate; 2913 2914 done = MSGLOOP_IN_PROG; 2915 response = FALSE; 2916 reject = FALSE; 2917 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2918 devinfo->target, &tstate); 2919 targ_scsirate = tinfo->scsirate; 2920 2921 /* 2922 * Parse as much of the message as is availible, 2923 * rejecting it if we don't support it. When 2924 * the entire message is availible and has been 2925 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2926 * that we have parsed an entire message. 2927 * 2928 * In the case of extended messages, we accept the length 2929 * byte outright and perform more checking once we know the 2930 * extended message type. 2931 */ 2932 switch (ahc->msgin_buf[0]) { 2933 case MSG_MESSAGE_REJECT: 2934 response = ahc_handle_msg_reject(ahc, devinfo); 2935 /* FALLTHROUGH */ 2936 case MSG_NOOP: 2937 done = MSGLOOP_MSGCOMPLETE; 2938 break; 2939 case MSG_IGN_WIDE_RESIDUE: 2940 { 2941 /* Wait for the whole message */ 2942 if (ahc->msgin_index >= 1) { 2943 if (ahc->msgin_buf[1] != 1 2944 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2945 reject = TRUE; 2946 done = MSGLOOP_MSGCOMPLETE; 2947 } else 2948 ahc_handle_ign_wide_residue(ahc, devinfo); 2949 } 2950 break; 2951 } 2952 case MSG_EXTENDED: 2953 { 2954 /* Wait for enough of the message to begin validation */ 2955 if (ahc->msgin_index < 2) 2956 break; 2957 switch (ahc->msgin_buf[2]) { 2958 case MSG_EXT_SDTR: 2959 { 2960 struct ahc_syncrate *syncrate; 2961 u_int period; 2962 u_int offset; 2963 u_int saved_offset; 2964 2965 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2966 reject = TRUE; 2967 break; 2968 } 2969 2970 /* 2971 * Wait until we have both args before validating 2972 * and acting on this message. 2973 * 2974 * Add one to MSG_EXT_SDTR_LEN to account for 2975 * the extended message preamble. 2976 */ 2977 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2978 break; 2979 2980 period = ahc->msgin_buf[3]; 2981 saved_offset = offset = ahc->msgin_buf[4]; 2982 syncrate = ahc_devlimited_syncrate(ahc, &period); 2983 ahc_validate_offset(ahc, syncrate, &offset, 2984 targ_scsirate & WIDEXFER); 2985 ahc_set_syncrate(ahc, devinfo, 2986 syncrate, period, offset, 2987 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2988 /*paused*/TRUE, /*done*/TRUE); 2989 2990 /* 2991 * See if we initiated Sync Negotiation 2992 * and didn't have to fall down to async 2993 * transfers. 2994 */ 2995 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2996 /* We started it */ 2997 if (saved_offset != offset) { 2998 /* Went too low - force async */ 2999 reject = TRUE; 3000 } 3001 } else { 3002 /* 3003 * Send our own SDTR in reply 3004 */ 3005 ahc->msgout_index = 0; 3006 ahc->msgout_len = 0; 3007 ahc_construct_sdtr(ahc, period, offset); 3008 ahc->msgout_index = 0; 3009 response = TRUE; 3010 } 3011 done = MSGLOOP_MSGCOMPLETE; 3012 break; 3013 } 3014 case MSG_EXT_WDTR: 3015 { 3016 u_int bus_width; 3017 u_int sending_reply; 3018 3019 sending_reply = FALSE; 3020 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3021 reject = TRUE; 3022 break; 3023 } 3024 3025 /* 3026 * Wait until we have our arg before validating 3027 * and acting on this message. 3028 * 3029 * Add one to MSG_EXT_WDTR_LEN to account for 3030 * the extended message preamble. 3031 */ 3032 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3033 break; 3034 3035 bus_width = ahc->msgin_buf[3]; 3036 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3037 /* 3038 * Don't send a WDTR back to the 3039 * target, since we asked first. 3040 */ 3041 switch (bus_width){ 3042 default: 3043 /* 3044 * How can we do anything greater 3045 * than 16bit transfers on a 16bit 3046 * bus? 3047 */ 3048 reject = TRUE; 3049 printf("%s: target %d requested %dBit " 3050 "transfers. Rejecting...\n", 3051 ahc_name(ahc), devinfo->target, 3052 8 * (0x01 << bus_width)); 3053 /* FALLTHROUGH */ 3054 case MSG_EXT_WDTR_BUS_8_BIT: 3055 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3056 break; 3057 case MSG_EXT_WDTR_BUS_16_BIT: 3058 break; 3059 } 3060 } else { 3061 /* 3062 * Send our own WDTR in reply 3063 */ 3064 switch (bus_width) { 3065 default: 3066 if (ahc->features & AHC_WIDE) { 3067 /* Respond Wide */ 3068 bus_width = 3069 MSG_EXT_WDTR_BUS_16_BIT; 3070 break; 3071 } 3072 /* FALLTHROUGH */ 3073 case MSG_EXT_WDTR_BUS_8_BIT: 3074 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3075 break; 3076 } 3077 ahc->msgout_index = 0; 3078 ahc->msgout_len = 0; 3079 ahc_construct_wdtr(ahc, bus_width); 3080 ahc->msgout_index = 0; 3081 response = TRUE; 3082 sending_reply = TRUE; 3083 } 3084 ahc_set_width(ahc, devinfo, bus_width, 3085 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3086 /*paused*/TRUE, /*done*/TRUE); 3087 3088 /* After a wide message, we are async */ 3089 ahc_set_syncrate(ahc, devinfo, 3090 /*syncrate*/NULL, /*period*/0, 3091 /*offset*/0, AHC_TRANS_ACTIVE, 3092 /*paused*/TRUE, /*done*/FALSE); 3093 if (sending_reply == FALSE && reject == FALSE) { 3094 3095 if (tinfo->goal.period) { 3096 struct ahc_syncrate *rate; 3097 u_int period; 3098 u_int offset; 3099 3100 /* Start the sync negotiation */ 3101 period = tinfo->goal.period; 3102 rate = ahc_devlimited_syncrate(ahc, 3103 &period); 3104 offset = tinfo->goal.offset; 3105 ahc_validate_offset(ahc, rate, &offset, 3106 tinfo->current.width); 3107 ahc->msgout_index = 0; 3108 ahc->msgout_len = 0; 3109 ahc_construct_sdtr(ahc, period, offset); 3110 ahc->msgout_index = 0; 3111 response = TRUE; 3112 } 3113 } 3114 done = MSGLOOP_MSGCOMPLETE; 3115 break; 3116 } 3117 default: 3118 /* Unknown extended message. Reject it. */ 3119 reject = TRUE; 3120 break; 3121 } 3122 break; 3123 } 3124 case MSG_BUS_DEV_RESET: 3125 ahc_handle_devreset(ahc, devinfo, 3126 XS_RESET, "Bus Device Reset Received", 3127 /*verbose_level*/0); 3128 restart_sequencer(ahc); 3129 done = MSGLOOP_TERMINATED; 3130 break; 3131 case MSG_ABORT_TAG: 3132 case MSG_ABORT: 3133 case MSG_CLEAR_QUEUE: 3134 /* Target mode messages */ 3135 if (devinfo->role != ROLE_TARGET) { 3136 reject = TRUE; 3137 break; 3138 } 3139 #if AHC_TARGET_MODE 3140 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3141 devinfo->lun, 3142 ahc->msgin_buf[0] == MSG_ABORT_TAG 3143 ? SCB_LIST_NULL 3144 : ahc_inb(ahc, INITIATOR_TAG), 3145 ROLE_TARGET, XS_DRIVER_STUFFUP); 3146 3147 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3148 if (tstate != NULL) { 3149 struct tmode_lstate* lstate; 3150 3151 lstate = tstate->enabled_luns[devinfo->lun]; 3152 if (lstate != NULL) { 3153 ahc_queue_lstate_event(ahc, lstate, 3154 devinfo->our_scsiid, 3155 ahc->msgin_buf[0], 3156 /*arg*/0); 3157 ahc_send_lstate_events(ahc, lstate); 3158 } 3159 } 3160 done = MSGLOOP_MSGCOMPLETE; 3161 #else 3162 panic("ahc: got target mode message"); 3163 #endif 3164 break; 3165 case MSG_TERM_IO_PROC: 3166 default: 3167 reject = TRUE; 3168 break; 3169 } 3170 3171 if (reject) { 3172 /* 3173 * Setup to reject the message. 3174 */ 3175 ahc->msgout_index = 0; 3176 ahc->msgout_len = 1; 3177 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3178 done = MSGLOOP_MSGCOMPLETE; 3179 response = TRUE; 3180 } 3181 3182 if (done != MSGLOOP_IN_PROG && !response) 3183 /* Clear the outgoing message buffer */ 3184 ahc->msgout_len = 0; 3185 3186 return (done); 3187 } 3188 3189 static void 3190 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3191 { 3192 u_int scb_index; 3193 struct scb *scb; 3194 3195 scb_index = ahc_inb(ahc, SCB_TAG); 3196 scb = &ahc->scb_data->scbarray[scb_index]; 3197 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3198 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3199 /* 3200 * Ignore the message if we haven't 3201 * seen an appropriate data phase yet. 3202 */ 3203 } else { 3204 /* 3205 * If the residual occurred on the last 3206 * transfer and the transfer request was 3207 * expected to end on an odd count, do 3208 * nothing. Otherwise, subtract a byte 3209 * and update the residual count accordingly. 3210 */ 3211 u_int resid_sgcnt; 3212 3213 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3214 if (resid_sgcnt == 0 3215 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3216 /* 3217 * If the residual occurred on the last 3218 * transfer and the transfer request was 3219 * expected to end on an odd count, do 3220 * nothing. 3221 */ 3222 } else { 3223 u_int data_cnt; 3224 u_int32_t data_addr; 3225 u_int sg_index; 3226 3227 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3228 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3229 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3230 3231 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3232 | (ahc_inb(ahc, SHADDR + 2) << 16) 3233 | (ahc_inb(ahc, SHADDR + 1) << 8) 3234 | (ahc_inb(ahc, SHADDR)); 3235 3236 data_cnt += 1; 3237 data_addr -= 1; 3238 3239 sg_index = scb->sg_count - resid_sgcnt; 3240 3241 if (sg_index != 0 3242 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3243 u_int32_t sg_addr; 3244 3245 sg_index--; 3246 data_cnt = 1; 3247 data_addr = le32toh(scb->sg_list[sg_index].addr) 3248 + le32toh(scb->sg_list[sg_index].len) 3249 - 1; 3250 3251 /* 3252 * The physical address base points to the 3253 * second entry as it is always used for 3254 * calculating the "next S/G pointer". 3255 */ 3256 sg_addr = scb->sg_list_phys 3257 + (sg_index* sizeof(*scb->sg_list)); 3258 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3259 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3260 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3261 ahc_outb(ahc, SG_NEXT, sg_addr); 3262 } 3263 3264 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3265 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3266 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3267 3268 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3269 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3270 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3271 ahc_outb(ahc, SHADDR, data_addr); 3272 } 3273 } 3274 } 3275 3276 static void 3277 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3278 int status, char *message, 3279 int verbose_level) 3280 { 3281 int found; 3282 3283 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3284 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3285 status); 3286 3287 /* 3288 * Go back to async/narrow transfers and renegotiate. 3289 * ahc_set_width and ahc_set_syncrate can cope with NULL 3290 * paths. 3291 */ 3292 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3293 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3294 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3295 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3296 /*paused*/TRUE, /*done*/FALSE); 3297 3298 if (message != NULL && (verbose_level <= 0)) 3299 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3300 message, devinfo->channel, devinfo->target, found); 3301 } 3302 3303 /* 3304 * We have an scb which has been processed by the 3305 * adaptor, now we look to see how the operation 3306 * went. 3307 */ 3308 static void 3309 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3310 { 3311 struct scsipi_xfer *xs; 3312 struct scsipi_link *sc_link; 3313 int requeue = 0; 3314 int target; 3315 3316 3317 xs = scb->xs; 3318 sc_link = xs->sc_link; 3319 LIST_REMOVE(scb, plinks); 3320 3321 callout_stop(&scb->xs->xs_callout); 3322 3323 #ifdef AHC_DEBUG 3324 if (ahc_debug & AHC_SHOWCMDS) { 3325 scsi_print_addr(sc_link); 3326 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3327 scb->hscb->tag); 3328 } 3329 #endif 3330 3331 target = sc_link->scsipi_scsi.target; 3332 3333 if (xs->datalen) { 3334 int op; 3335 3336 if (xs->xs_control & XS_CTL_DATA_IN) 3337 op = BUS_DMASYNC_POSTREAD; 3338 else 3339 op = BUS_DMASYNC_POSTWRITE; 3340 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3341 scb->dmamap->dm_mapsize, op); 3342 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3343 } 3344 3345 /* 3346 * Unbusy this target/channel/lun. 3347 * XXX if we are holding two commands per lun, 3348 * send the next command. 3349 */ 3350 if (!(scb->hscb->control & TAG_ENB)) 3351 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3352 3353 /* 3354 * If the recovery SCB completes, we have to be 3355 * out of our timeout. 3356 */ 3357 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3358 3359 struct scb *scbp; 3360 3361 /* 3362 * We were able to complete the command successfully, 3363 * so reinstate the timeouts for all other pending 3364 * commands. 3365 */ 3366 scbp = ahc->pending_ccbs.lh_first; 3367 while (scbp != NULL) { 3368 struct scsipi_xfer *txs = scbp->xs; 3369 3370 if (!(txs->xs_control & XS_CTL_POLL)) { 3371 callout_reset(&scbp->xs->xs_callout, 3372 (scbp->xs->timeout * hz) / 1000, 3373 ahc_timeout, scbp); 3374 } 3375 scbp = LIST_NEXT(scbp, plinks); 3376 } 3377 3378 /* 3379 * Ensure that we didn't put a second instance of this 3380 * SCB into the QINFIFO. 3381 */ 3382 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3383 SCB_LUN(scb), scb->hscb->tag, 3384 ROLE_INITIATOR, /*status*/0, 3385 SEARCH_REMOVE); 3386 if (xs->error != XS_NOERROR) 3387 ahcsetccbstatus(xs, XS_TIMEOUT); 3388 scsi_print_addr(xs->sc_link); 3389 printf("no longer in timeout, status = %x\n", xs->status); 3390 } 3391 3392 if (xs->error != XS_NOERROR) { 3393 /* Don't clobber any existing error state */ 3394 } else if ((scb->flags & SCB_SENSE) != 0) { 3395 /* 3396 * We performed autosense retrieval. 3397 * 3398 * bzero the sense data before having 3399 * the drive fill it. The SCSI spec mandates 3400 * that any untransfered data should be 3401 * assumed to be zero. Complete the 'bounce' 3402 * of sense information through buffers accessible 3403 * via bus-space by copying it into the clients 3404 * csio. 3405 */ 3406 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3407 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3408 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3409 xs->error = XS_SENSE; 3410 } 3411 if (scb->flags & SCB_FREEZE_QUEUE) { 3412 ahc->devqueue_blocked[target]--; 3413 scb->flags &= ~SCB_FREEZE_QUEUE; 3414 } 3415 3416 requeue = scb->flags & SCB_REQUEUE; 3417 ahcfreescb(ahc, scb); 3418 3419 if (requeue) { 3420 /* 3421 * Re-insert at the front of the private queue to 3422 * preserve order. 3423 */ 3424 int s; 3425 3426 s = splbio(); 3427 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3428 splx(s); 3429 } else { 3430 xs->xs_status |= XS_STS_DONE; 3431 ahc_check_tags(ahc, xs); 3432 scsipi_done(xs); 3433 } 3434 3435 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3436 ahc_action(xs); 3437 } 3438 3439 /* 3440 * Determine the number of SCBs available on the controller 3441 */ 3442 int 3443 ahc_probe_scbs(struct ahc_softc *ahc) { 3444 int i; 3445 3446 for (i = 0; i < AHC_SCB_MAX; i++) { 3447 ahc_outb(ahc, SCBPTR, i); 3448 ahc_outb(ahc, SCB_CONTROL, i); 3449 if (ahc_inb(ahc, SCB_CONTROL) != i) 3450 break; 3451 ahc_outb(ahc, SCBPTR, 0); 3452 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3453 break; 3454 } 3455 return (i); 3456 } 3457 3458 /* 3459 * Start the board, ready for normal operation 3460 */ 3461 int 3462 ahc_init(struct ahc_softc *ahc) 3463 { 3464 int max_targ = 15; 3465 int i; 3466 int term; 3467 u_int scsi_conf; 3468 u_int scsiseq_template; 3469 u_int ultraenb; 3470 u_int discenable; 3471 u_int tagenable; 3472 size_t driver_data_size; 3473 u_int32_t physaddr; 3474 3475 #ifdef AHC_PRINT_SRAM 3476 printf("Scratch Ram:"); 3477 for (i = 0x20; i < 0x5f; i++) { 3478 if (((i % 8) == 0) && (i != 0)) { 3479 printf ("\n "); 3480 } 3481 printf (" 0x%x", ahc_inb(ahc, i)); 3482 } 3483 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3484 for (i = 0x70; i < 0x7f; i++) { 3485 if (((i % 8) == 0) && (i != 0)) { 3486 printf ("\n "); 3487 } 3488 printf (" 0x%x", ahc_inb(ahc, i)); 3489 } 3490 } 3491 printf ("\n"); 3492 #endif 3493 3494 /* 3495 * Assume we have a board at this stage and it has been reset. 3496 */ 3497 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3498 ahc->our_id = ahc->our_id_b = 7; 3499 3500 /* 3501 * Default to allowing initiator operations. 3502 */ 3503 ahc->flags |= AHC_INITIATORMODE; 3504 3505 /* 3506 * DMA tag for our command fifos and other data in system memory 3507 * the card's sequencer must be able to access. For initiator 3508 * roles, we need to allocate space for the qinfifo, qoutfifo, 3509 * and untagged_scb arrays each of which are composed of 256 3510 * 1 byte elements. When providing for the target mode role, 3511 * we additionally must provide space for the incoming target 3512 * command fifo. 3513 */ 3514 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3515 3516 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3517 ahc->sc_dmaflags, 3518 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3519 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3520 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3521 return (ENOMEM); 3522 3523 ahc->init_level++; 3524 3525 /* Allocate SCB data now that parent_dmat is initialized */ 3526 if (ahc->scb_data->maxhscbs == 0) 3527 if (ahcinitscbdata(ahc) != 0) 3528 return (ENOMEM); 3529 3530 ahc->qinfifo = &ahc->qoutfifo[256]; 3531 ahc->untagged_scbs = &ahc->qinfifo[256]; 3532 /* There are no untagged SCBs active yet. */ 3533 for (i = 0; i < 256; i++) 3534 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3535 3536 /* All of our queues are empty */ 3537 for (i = 0; i < 256; i++) 3538 ahc->qoutfifo[i] = SCB_LIST_NULL; 3539 3540 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3541 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3542 3543 /* 3544 * Allocate a tstate to house information for our 3545 * initiator presence on the bus as well as the user 3546 * data for any target mode initiator. 3547 */ 3548 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3549 printf("%s: unable to allocate tmode_tstate. " 3550 "Failing attach\n", ahc_name(ahc)); 3551 return (-1); 3552 } 3553 3554 if ((ahc->features & AHC_TWIN) != 0) { 3555 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3556 printf("%s: unable to allocate tmode_tstate. " 3557 "Failing attach\n", ahc_name(ahc)); 3558 return (-1); 3559 } 3560 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3561 ahc->our_id, ahc->our_id_b, 3562 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3563 } else { 3564 if ((ahc->features & AHC_WIDE) != 0) { 3565 printf("Wide "); 3566 } else { 3567 printf("Single "); 3568 } 3569 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3570 } 3571 3572 ahc_outb(ahc, SEQ_FLAGS, 0); 3573 3574 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3575 ahc->flags |= AHC_PAGESCBS; 3576 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3577 } else { 3578 ahc->flags &= ~AHC_PAGESCBS; 3579 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3580 } 3581 3582 #ifdef AHC_DEBUG 3583 if (ahc_debug & AHC_SHOWMISC) { 3584 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3585 "ahc_dma %d bytes\n", 3586 ahc_name(ahc), 3587 sizeof(struct hardware_scb), 3588 sizeof(struct scb), 3589 sizeof(struct ahc_dma_seg)); 3590 } 3591 #endif /* AHC_DEBUG */ 3592 3593 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3594 if (ahc->features & AHC_TWIN) { 3595 3596 /* 3597 * The device is gated to channel B after a chip reset, 3598 * so set those values first 3599 */ 3600 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3601 if ((ahc->features & AHC_ULTRA2) != 0) 3602 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3603 else 3604 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3605 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3606 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3607 |term|ENSTIMER|ACTNEGEN); 3608 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3609 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3610 3611 if ((scsi_conf & RESET_SCSI) != 0 3612 && (ahc->flags & AHC_INITIATORMODE) != 0) 3613 ahc->flags |= AHC_RESET_BUS_B; 3614 3615 /* Select Channel A */ 3616 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3617 } 3618 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3619 if ((ahc->features & AHC_ULTRA2) != 0) 3620 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3621 else 3622 ahc_outb(ahc, SCSIID, ahc->our_id); 3623 scsi_conf = ahc_inb(ahc, SCSICONF); 3624 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3625 |term 3626 |ENSTIMER|ACTNEGEN); 3627 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3628 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3629 3630 if ((scsi_conf & RESET_SCSI) != 0 3631 && (ahc->flags & AHC_INITIATORMODE) != 0) 3632 ahc->flags |= AHC_RESET_BUS_A; 3633 3634 /* 3635 * Look at the information that board initialization or 3636 * the board bios has left us. 3637 */ 3638 ultraenb = 0; 3639 tagenable = ALL_TARGETS_MASK; 3640 3641 /* Grab the disconnection disable table and invert it for our needs */ 3642 if (ahc->flags & AHC_USEDEFAULTS) { 3643 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3644 "device parameters\n", ahc_name(ahc)); 3645 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3646 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3647 discenable = ALL_TARGETS_MASK; 3648 if ((ahc->features & AHC_ULTRA) != 0) 3649 ultraenb = ALL_TARGETS_MASK; 3650 } else { 3651 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3652 | ahc_inb(ahc, DISC_DSB)); 3653 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3654 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3655 | ahc_inb(ahc, ULTRA_ENB); 3656 } 3657 3658 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3659 max_targ = 7; 3660 3661 for (i = 0; i <= max_targ; i++) { 3662 struct ahc_initiator_tinfo *tinfo; 3663 struct tmode_tstate *tstate; 3664 u_int our_id; 3665 u_int target_id; 3666 char channel; 3667 3668 channel = 'A'; 3669 our_id = ahc->our_id; 3670 target_id = i; 3671 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3672 channel = 'B'; 3673 our_id = ahc->our_id_b; 3674 target_id = i % 8; 3675 } 3676 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3677 target_id, &tstate); 3678 /* Default to async narrow across the board */ 3679 bzero(tinfo, sizeof(*tinfo)); 3680 if (ahc->flags & AHC_USEDEFAULTS) { 3681 if ((ahc->features & AHC_WIDE) != 0) 3682 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3683 3684 /* 3685 * These will be truncated when we determine the 3686 * connection type we have with the target. 3687 */ 3688 tinfo->user.period = ahc_syncrates->period; 3689 tinfo->user.offset = ~0; 3690 } else { 3691 u_int scsirate; 3692 u_int16_t mask; 3693 3694 /* Take the settings leftover in scratch RAM. */ 3695 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3696 mask = (0x01 << i); 3697 if ((ahc->features & AHC_ULTRA2) != 0) { 3698 u_int offset; 3699 u_int maxsync; 3700 3701 if ((scsirate & SOFS) == 0x0F) { 3702 /* 3703 * Haven't negotiated yet, 3704 * so the format is different. 3705 */ 3706 scsirate = (scsirate & SXFR) >> 4 3707 | (ultraenb & mask) 3708 ? 0x08 : 0x0 3709 | (scsirate & WIDEXFER); 3710 offset = MAX_OFFSET_ULTRA2; 3711 } else 3712 offset = ahc_inb(ahc, TARG_OFFSET + i); 3713 maxsync = AHC_SYNCRATE_ULTRA2; 3714 if ((ahc->features & AHC_DT) != 0) 3715 maxsync = AHC_SYNCRATE_DT; 3716 tinfo->user.period = 3717 ahc_find_period(ahc, scsirate, maxsync); 3718 if (offset == 0) 3719 tinfo->user.period = 0; 3720 else 3721 tinfo->user.offset = ~0; 3722 } else if ((scsirate & SOFS) != 0) { 3723 tinfo->user.period = 3724 ahc_find_period(ahc, scsirate, 3725 (ultraenb & mask) 3726 ? AHC_SYNCRATE_ULTRA 3727 : AHC_SYNCRATE_FAST); 3728 if (tinfo->user.period != 0) 3729 tinfo->user.offset = ~0; 3730 } 3731 if ((scsirate & WIDEXFER) != 0 3732 && (ahc->features & AHC_WIDE) != 0) 3733 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3734 } 3735 tinfo->goal = tinfo->user; /* force negotiation */ 3736 tstate->ultraenb = ultraenb; 3737 tstate->discenable = discenable; 3738 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3739 tstate->tagdisable = 0; 3740 } 3741 ahc->user_discenable = discenable; 3742 ahc->user_tagenable = tagenable; 3743 3744 /* 3745 * Tell the sequencer where it can find our arrays in memory. 3746 */ 3747 physaddr = ahc->scb_data->hscb_busaddr; 3748 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3749 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3750 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3751 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3752 3753 physaddr = ahc->shared_data_busaddr; 3754 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3755 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3756 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3757 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3758 3759 /* Target mode incomding command fifo */ 3760 physaddr += 3 * 256 * sizeof(u_int8_t); 3761 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3762 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3763 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3764 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3765 3766 /* 3767 * Initialize the group code to command length table. 3768 * This overrides the values in TARG_SCSIRATE, so only 3769 * setup the table after we have processed that information. 3770 */ 3771 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3772 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3773 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3774 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3775 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3779 3780 /* Tell the sequencer of our initial queue positions */ 3781 ahc_outb(ahc, KERNEL_QINPOS, 0); 3782 ahc_outb(ahc, QINPOS, 0); 3783 ahc_outb(ahc, QOUTPOS, 0); 3784 3785 #ifdef AHC_DEBUG 3786 if (ahc_debug & AHC_SHOWMISC) 3787 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3788 discenable, ultraenb); 3789 #endif 3790 3791 /* Don't have any special messages to send to targets */ 3792 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3793 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3794 3795 /* 3796 * Use the built in queue management registers 3797 * if they are available. 3798 */ 3799 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3800 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3801 ahc_outb(ahc, SDSCB_QOFF, 0); 3802 ahc_outb(ahc, SNSCB_QOFF, 0); 3803 ahc_outb(ahc, HNSCB_QOFF, 0); 3804 } 3805 3806 3807 /* We don't have any waiting selections */ 3808 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3809 3810 /* Our disconnection list is empty too */ 3811 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3812 3813 /* Message out buffer starts empty */ 3814 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3815 3816 /* 3817 * Setup the allowed SCSI Sequences based on operational mode. 3818 * If we are a target, we'll enalbe select in operations once 3819 * we've had a lun enabled. 3820 */ 3821 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3822 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3823 scsiseq_template |= ENRSELI; 3824 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3825 3826 /* 3827 * Load the Sequencer program and Enable the adapter 3828 * in "fast" mode. 3829 */ 3830 #ifdef AHC_DEBUG 3831 printf("%s: Downloading Sequencer Program...", 3832 ahc_name(ahc)); 3833 #endif 3834 3835 ahc_loadseq(ahc); 3836 3837 /* We have to wait until after any system dumps... */ 3838 shutdownhook_establish(ahc_shutdown, ahc); 3839 3840 return (0); 3841 } 3842 3843 /* 3844 * XXX fvdl the busy_tcl checks and settings should only be done 3845 * for the non-tagged queueing case, but we don't do tagged queueing 3846 * yet, so.. 3847 */ 3848 static int32_t 3849 ahc_action(struct scsipi_xfer *xs) 3850 { 3851 struct scsipi_xfer *first_xs, *next_xs = NULL; 3852 struct ahc_softc *ahc; 3853 struct scb *scb; 3854 struct hardware_scb *hscb; 3855 struct ahc_initiator_tinfo *tinfo; 3856 struct tmode_tstate *tstate; 3857 u_int target_id; 3858 u_int our_id; 3859 int s, tcl; 3860 u_int16_t mask; 3861 int dontqueue = 0, fromqueue = 0; 3862 3863 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3864 3865 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3866 3867 /* must protect the queue */ 3868 s = splbio(); 3869 3870 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3871 /* 3872 * Called from ahc_done. Calling with the first entry in 3873 * the queue is really just a way of seeing where we're 3874 * called from. Now, find the first eligible SCB to send, 3875 * e.g. one which will be accepted immediately. 3876 */ 3877 3878 if (ahc->queue_blocked) { 3879 splx(s); 3880 return (TRY_AGAIN_LATER); 3881 } 3882 3883 xs = ahc_first_xs(ahc); 3884 if (xs == NULL) { 3885 splx(s); 3886 return (TRY_AGAIN_LATER); 3887 } 3888 3889 next_xs = TAILQ_NEXT(xs, adapter_q); 3890 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3891 fromqueue = 1; 3892 goto get_scb; 3893 } 3894 3895 /* 3896 * If no new requests are accepted, just insert into the 3897 * private queue to wait for our turn. 3898 */ 3899 tcl = XS_TCL(ahc, xs); 3900 3901 if (ahc->queue_blocked || 3902 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3903 (!ahc_istagged_device(ahc, xs, 0) && 3904 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3905 if (dontqueue) { 3906 splx(s); 3907 xs->error = XS_DRIVER_STUFFUP; 3908 return TRY_AGAIN_LATER; 3909 } 3910 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3911 splx(s); 3912 return SUCCESSFULLY_QUEUED; 3913 } 3914 3915 first_xs = ahc_first_xs(ahc); 3916 3917 /* determine safety of software queueing */ 3918 dontqueue = xs->xs_control & XS_CTL_POLL; 3919 3920 /* 3921 * Handle situations where there's already entries in the 3922 * queue. 3923 */ 3924 if (first_xs != NULL) { 3925 /* 3926 * If we can't queue, we have to abort, since 3927 * we have to preserve order. 3928 */ 3929 if (dontqueue) { 3930 splx(s); 3931 xs->error = XS_DRIVER_STUFFUP; 3932 return (TRY_AGAIN_LATER); 3933 } 3934 3935 /* 3936 * Swap with the first queue entry. 3937 */ 3938 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3939 xs = first_xs; 3940 next_xs = TAILQ_NEXT(xs, adapter_q); 3941 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3942 fromqueue = 1; 3943 3944 } 3945 3946 get_scb: 3947 3948 target_id = xs->sc_link->scsipi_scsi.target; 3949 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3950 3951 /* 3952 * get an scb to use. 3953 */ 3954 if ((scb = ahcgetscb(ahc)) == NULL) { 3955 3956 if (dontqueue) { 3957 splx(s); 3958 xs->error = XS_DRIVER_STUFFUP; 3959 return (TRY_AGAIN_LATER); 3960 } 3961 3962 /* 3963 * If we were pulled off the queue, put ourselves 3964 * back to where we came from, otherwise tack ourselves 3965 * onto the end. 3966 */ 3967 if (fromqueue && next_xs != NULL) 3968 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3969 else 3970 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3971 3972 splx(s); 3973 return (SUCCESSFULLY_QUEUED); 3974 } 3975 3976 tcl = XS_TCL(ahc, xs); 3977 3978 #ifdef DIAGNOSTIC 3979 if (!ahc_istagged_device(ahc, xs, 0) && 3980 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3981 panic("ahc: queuing for busy target"); 3982 #endif 3983 3984 scb->xs = xs; 3985 hscb = scb->hscb; 3986 hscb->tcl = tcl; 3987 3988 if (ahc_istagged_device(ahc, xs, 0)) 3989 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 3990 else 3991 ahc_busy_tcl(ahc, scb); 3992 3993 splx(s); 3994 3995 /* 3996 * Put all the arguments for the xfer in the scb 3997 */ 3998 3999 mask = SCB_TARGET_MASK(scb); 4000 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4001 target_id, &tstate); 4002 if (ahc->inited_targets[target_id] == 0) { 4003 struct ahc_devinfo devinfo; 4004 4005 s = splbio(); 4006 ahc_compile_devinfo(&devinfo, our_id, target_id, 4007 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4008 ROLE_INITIATOR); 4009 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4010 FALSE); 4011 ahc->inited_targets[target_id] = 1; 4012 splx(s); 4013 } 4014 4015 hscb->scsirate = tinfo->scsirate; 4016 hscb->scsioffset = tinfo->current.offset; 4017 if ((tstate->ultraenb & mask) != 0) 4018 hscb->control |= ULTRAENB; 4019 4020 if ((tstate->discenable & mask) != 0) 4021 hscb->control |= DISCENB; 4022 4023 if (xs->xs_control & XS_CTL_RESET) { 4024 hscb->cmdpointer = 0; 4025 scb->flags |= SCB_DEVICE_RESET; 4026 hscb->control |= MK_MESSAGE; 4027 return ahc_execute_scb(scb, NULL, 0); 4028 } 4029 4030 return ahc_setup_data(ahc, xs, scb); 4031 } 4032 4033 static int 4034 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4035 { 4036 struct scb *scb; 4037 struct scsipi_xfer *xs; 4038 struct ahc_softc *ahc; 4039 int s; 4040 4041 scb = (struct scb *)arg; 4042 xs = scb->xs; 4043 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4044 4045 4046 if (nsegments != 0) { 4047 struct ahc_dma_seg *sg; 4048 bus_dma_segment_t *end_seg; 4049 int op; 4050 4051 end_seg = dm_segs + nsegments; 4052 4053 /* Copy the first SG into the data pointer area */ 4054 scb->hscb->data = dm_segs->ds_addr; 4055 scb->hscb->datalen = dm_segs->ds_len; 4056 4057 /* Copy the segments into our SG list */ 4058 sg = scb->sg_list; 4059 while (dm_segs < end_seg) { 4060 sg->addr = dm_segs->ds_addr; 4061 sg->len = dm_segs->ds_len; 4062 ahc_swap_sg(sg); 4063 sg++; 4064 dm_segs++; 4065 } 4066 4067 /* Note where to find the SG entries in bus space */ 4068 scb->hscb->SG_pointer = scb->sg_list_phys; 4069 4070 if (xs->xs_control & XS_CTL_DATA_IN) 4071 op = BUS_DMASYNC_PREREAD; 4072 else 4073 op = BUS_DMASYNC_PREWRITE; 4074 4075 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4076 scb->dmamap->dm_mapsize, op); 4077 4078 } else { 4079 scb->hscb->SG_pointer = 0; 4080 scb->hscb->data = 0; 4081 scb->hscb->datalen = 0; 4082 } 4083 4084 scb->sg_count = scb->hscb->SG_count = nsegments; 4085 4086 s = splbio(); 4087 4088 /* 4089 * Last time we need to check if this SCB needs to 4090 * be aborted. 4091 */ 4092 if (xs->xs_status & XS_STS_DONE) { 4093 if (!ahc_istagged_device(ahc, xs, 0)) 4094 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4095 if (nsegments != 0) 4096 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4097 ahcfreescb(ahc, scb); 4098 splx(s); 4099 return (COMPLETE); 4100 } 4101 4102 #ifdef DIAGNOSTIC 4103 if (scb->sg_count > 255) 4104 panic("ahc bad sg_count"); 4105 #endif 4106 4107 ahc_swap_hscb(scb->hscb); 4108 4109 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4110 4111 scb->flags |= SCB_ACTIVE; 4112 4113 if (!(xs->xs_control & XS_CTL_POLL)) 4114 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4115 ahc_timeout, scb); 4116 4117 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4118 #if 0 4119 printf("Continueing Immediate Command %d:%d\n", 4120 xs->sc_link->scsipi_scsi.target, 4121 xs->sc_link->scsipi_scsi.lun); 4122 #endif 4123 pause_sequencer(ahc); 4124 if ((ahc->flags & AHC_PAGESCBS) == 0) 4125 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4126 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4127 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4128 unpause_sequencer(ahc); 4129 } else { 4130 4131 #if 0 4132 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4133 scb->hscb->tag, ahc->qinfifonext, 4134 &ahc->qinfifo[ahc->qinfifonext], 4135 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4136 #endif 4137 4138 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4139 4140 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4141 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4142 4143 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4144 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4145 } else { 4146 pause_sequencer(ahc); 4147 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4148 unpause_sequencer(ahc); 4149 } 4150 } 4151 4152 #ifdef AHC_DEBUG 4153 if (ahc_debug & AHC_SHOWCMDS) { 4154 scsi_print_addr(xs->sc_link); 4155 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4156 " rate %x\n", 4157 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4158 scb->flags, scb->hscb->control, ahc->qinfifonext, 4159 scb->hscb->scsirate); 4160 } 4161 #endif 4162 4163 if (!(xs->xs_control & XS_CTL_POLL)) { 4164 splx(s); 4165 return (SUCCESSFULLY_QUEUED); 4166 } 4167 /* 4168 * If we can't use interrupts, poll for completion 4169 */ 4170 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4171 do { 4172 if (ahc_poll(ahc, xs->timeout)) { 4173 if (!(xs->xs_control & XS_CTL_SILENT)) 4174 printf("cmd fail\n"); 4175 ahc_timeout(scb); 4176 break; 4177 } 4178 } while (!(xs->xs_status & XS_STS_DONE)); 4179 splx(s); 4180 return (COMPLETE); 4181 } 4182 4183 static int 4184 ahc_poll(struct ahc_softc *ahc, int wait) 4185 { 4186 while (--wait) { 4187 DELAY(1000); 4188 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4189 break; 4190 } 4191 4192 if (wait == 0) { 4193 printf("%s: board is not responding\n", ahc_name(ahc)); 4194 return (EIO); 4195 } 4196 4197 ahc_intr((void *)ahc); 4198 return (0); 4199 } 4200 4201 static int 4202 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4203 struct scb *scb) 4204 { 4205 struct hardware_scb *hscb; 4206 4207 hscb = scb->hscb; 4208 xs->resid = xs->status = 0; 4209 4210 hscb->cmdlen = xs->cmdlen; 4211 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4212 hscb->cmdpointer = hscb->cmdstore_busaddr; 4213 4214 /* Only use S/G if there is a transfer */ 4215 if (xs->datalen) { 4216 int error; 4217 4218 error = bus_dmamap_load(ahc->parent_dmat, 4219 scb->dmamap, xs->data, 4220 xs->datalen, NULL, 4221 (xs->xs_control & XS_CTL_NOSLEEP) ? 4222 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4223 if (error) { 4224 if (!ahc_istagged_device(ahc, xs, 0)) 4225 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4226 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4227 } 4228 error = ahc_execute_scb(scb, 4229 scb->dmamap->dm_segs, 4230 scb->dmamap->dm_nsegs); 4231 return error; 4232 } else { 4233 return ahc_execute_scb(scb, NULL, 0); 4234 } 4235 } 4236 4237 static void 4238 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4239 { 4240 int target; 4241 char channel; 4242 int lun; 4243 4244 target = sc_link->scsipi_scsi.target; 4245 lun = sc_link->scsipi_scsi.lun; 4246 channel = sc_link->scsipi_scsi.channel; 4247 4248 ahc_search_qinfifo(ahc, target, channel, lun, 4249 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4250 SCB_REQUEUE, SEARCH_COMPLETE); 4251 } 4252 4253 static void 4254 ahcallocscbs(struct ahc_softc *ahc) 4255 { 4256 struct scb_data *scb_data; 4257 struct scb *next_scb; 4258 struct sg_map_node *sg_map; 4259 bus_addr_t physaddr; 4260 struct ahc_dma_seg *segs; 4261 int newcount; 4262 int i; 4263 4264 scb_data = ahc->scb_data; 4265 if (scb_data->numscbs >= AHC_SCB_MAX) 4266 /* Can't allocate any more */ 4267 return; 4268 4269 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4270 4271 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4272 4273 if (sg_map == NULL) 4274 return; 4275 4276 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4277 &sg_map->sg_dmamap, 4278 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4279 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4280 "SG space") < 0) { 4281 free(sg_map, M_DEVBUF); 4282 return; 4283 } 4284 4285 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4286 4287 segs = sg_map->sg_vaddr; 4288 physaddr = sg_map->sg_physaddr; 4289 4290 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4291 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4292 int error; 4293 4294 next_scb->sg_list = segs; 4295 /* 4296 * The sequencer always starts with the second entry. 4297 * The first entry is embedded in the scb. 4298 */ 4299 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4300 next_scb->flags = SCB_FREE; 4301 error = bus_dmamap_create(ahc->parent_dmat, 4302 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4303 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4304 &next_scb->dmamap); 4305 if (error != 0) 4306 break; 4307 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4308 next_scb->hscb->tag = ahc->scb_data->numscbs; 4309 next_scb->hscb->cmdstore_busaddr = 4310 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4311 + offsetof(struct hardware_scb, cmdstore); 4312 next_scb->hscb->cmdstore_busaddr = 4313 htole32(next_scb->hscb->cmdstore_busaddr); 4314 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4315 segs += AHC_NSEG; 4316 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4317 next_scb++; 4318 ahc->scb_data->numscbs++; 4319 } 4320 #ifdef AHC_DEBUG 4321 if (ahc_debug & AHC_SHOWSCBALLOC) 4322 printf("%s: allocated %d new SCBs count now %d\n", 4323 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4324 #endif 4325 } 4326 4327 #ifdef AHC_DUMP_SEQ 4328 static void 4329 ahc_dumpseq(struct ahc_softc* ahc) 4330 { 4331 int i; 4332 int max_prog; 4333 4334 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4335 max_prog = 448; 4336 else if ((ahc->features & AHC_ULTRA2) != 0) 4337 max_prog = 768; 4338 else 4339 max_prog = 512; 4340 4341 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4342 ahc_outb(ahc, SEQADDR0, 0); 4343 ahc_outb(ahc, SEQADDR1, 0); 4344 for (i = 0; i < max_prog; i++) { 4345 u_int8_t ins_bytes[4]; 4346 4347 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4348 printf("0x%08x\n", ins_bytes[0] << 24 4349 | ins_bytes[1] << 16 4350 | ins_bytes[2] << 8 4351 | ins_bytes[3]); 4352 } 4353 } 4354 #endif 4355 4356 static void 4357 ahc_loadseq(struct ahc_softc *ahc) 4358 { 4359 struct patch *cur_patch; 4360 int i; 4361 int downloaded; 4362 int skip_addr; 4363 u_int8_t download_consts[4]; 4364 4365 /* Setup downloadable constant table */ 4366 #if 0 4367 /* No downloaded constants are currently defined. */ 4368 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4369 #endif 4370 4371 cur_patch = patches; 4372 downloaded = 0; 4373 skip_addr = 0; 4374 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4375 ahc_outb(ahc, SEQADDR0, 0); 4376 ahc_outb(ahc, SEQADDR1, 0); 4377 4378 for (i = 0; i < sizeof(seqprog)/4; i++) { 4379 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4380 /* 4381 * Don't download this instruction as it 4382 * is in a patch that was removed. 4383 */ 4384 continue; 4385 } 4386 ahc_download_instr(ahc, i, download_consts); 4387 downloaded++; 4388 } 4389 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4390 restart_sequencer(ahc); 4391 4392 #ifdef AHC_DEBUG 4393 printf(" %d instructions downloaded\n", downloaded); 4394 #endif 4395 } 4396 4397 static int 4398 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4399 int start_instr, int *skip_addr) 4400 { 4401 struct patch *cur_patch; 4402 struct patch *last_patch; 4403 int num_patches; 4404 4405 num_patches = sizeof(patches)/sizeof(struct patch); 4406 last_patch = &patches[num_patches]; 4407 cur_patch = *start_patch; 4408 4409 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4410 4411 if (cur_patch->patch_func(ahc) == 0) { 4412 4413 /* Start rejecting code */ 4414 *skip_addr = start_instr + cur_patch->skip_instr; 4415 cur_patch += cur_patch->skip_patch; 4416 } else { 4417 /* Accepted this patch. Advance to the next 4418 * one and wait for our intruction pointer to 4419 * hit this point. 4420 */ 4421 cur_patch++; 4422 } 4423 } 4424 4425 *start_patch = cur_patch; 4426 if (start_instr < *skip_addr) 4427 /* Still skipping */ 4428 return (0); 4429 4430 return (1); 4431 } 4432 4433 static void 4434 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4435 { 4436 union ins_formats instr; 4437 struct ins_format1 *fmt1_ins; 4438 struct ins_format3 *fmt3_ins; 4439 u_int opcode; 4440 4441 /* Structure copy */ 4442 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4443 4444 instr.integer = le32toh(instr.integer); 4445 4446 fmt1_ins = &instr.format1; 4447 fmt3_ins = NULL; 4448 4449 /* Pull the opcode */ 4450 opcode = instr.format1.opcode; 4451 switch (opcode) { 4452 case AIC_OP_JMP: 4453 case AIC_OP_JC: 4454 case AIC_OP_JNC: 4455 case AIC_OP_CALL: 4456 case AIC_OP_JNE: 4457 case AIC_OP_JNZ: 4458 case AIC_OP_JE: 4459 case AIC_OP_JZ: 4460 { 4461 struct patch *cur_patch; 4462 int address_offset; 4463 u_int address; 4464 int skip_addr; 4465 int i; 4466 4467 fmt3_ins = &instr.format3; 4468 address_offset = 0; 4469 address = fmt3_ins->address; 4470 cur_patch = patches; 4471 skip_addr = 0; 4472 4473 for (i = 0; i < address;) { 4474 4475 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4476 4477 if (skip_addr > i) { 4478 int end_addr; 4479 4480 end_addr = MIN(address, skip_addr); 4481 address_offset += end_addr - i; 4482 i = skip_addr; 4483 } else { 4484 i++; 4485 } 4486 } 4487 address -= address_offset; 4488 fmt3_ins->address = address; 4489 /* FALLTHROUGH */ 4490 } 4491 case AIC_OP_OR: 4492 case AIC_OP_AND: 4493 case AIC_OP_XOR: 4494 case AIC_OP_ADD: 4495 case AIC_OP_ADC: 4496 case AIC_OP_BMOV: 4497 if (fmt1_ins->parity != 0) { 4498 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4499 } 4500 fmt1_ins->parity = 0; 4501 /* FALLTHROUGH */ 4502 case AIC_OP_ROL: 4503 if ((ahc->features & AHC_ULTRA2) != 0) { 4504 int i, count; 4505 4506 /* Calculate odd parity for the instruction */ 4507 for (i = 0, count = 0; i < 31; i++) { 4508 u_int32_t mask; 4509 4510 mask = 0x01 << i; 4511 if ((instr.integer & mask) != 0) 4512 count++; 4513 } 4514 if ((count & 0x01) == 0) 4515 instr.format1.parity = 1; 4516 } else { 4517 /* Compress the instruction for older sequencers */ 4518 if (fmt3_ins != NULL) { 4519 instr.integer = 4520 fmt3_ins->immediate 4521 | (fmt3_ins->source << 8) 4522 | (fmt3_ins->address << 16) 4523 | (fmt3_ins->opcode << 25); 4524 } else { 4525 instr.integer = 4526 fmt1_ins->immediate 4527 | (fmt1_ins->source << 8) 4528 | (fmt1_ins->destination << 16) 4529 | (fmt1_ins->ret << 24) 4530 | (fmt1_ins->opcode << 25); 4531 } 4532 } 4533 instr.integer = htole32(instr.integer); 4534 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4535 break; 4536 default: 4537 panic("Unknown opcode encountered in seq program"); 4538 break; 4539 } 4540 } 4541 4542 static void 4543 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4544 { 4545 4546 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4547 struct scb *scbp; 4548 4549 scb->flags |= SCB_RECOVERY_SCB; 4550 4551 /* 4552 * Take all queued, but not sent SCBs out of the equation. 4553 * Also ensure that no new CCBs are queued to us while we 4554 * try to fix this problem. 4555 */ 4556 ahc->queue_blocked = 1; 4557 4558 /* 4559 * Go through all of our pending SCBs and remove 4560 * any scheduled timeouts for them. We will reschedule 4561 * them after we've successfully fixed this problem. 4562 */ 4563 scbp = ahc->pending_ccbs.lh_first; 4564 while (scbp != NULL) { 4565 callout_stop(&scbp->xs->xs_callout); 4566 scbp = scbp->plinks.le_next; 4567 } 4568 } 4569 } 4570 4571 static void 4572 ahc_timeout(void *arg) 4573 { 4574 struct scb *scb; 4575 struct ahc_softc *ahc; 4576 int s, found; 4577 u_int last_phase; 4578 int target; 4579 int lun; 4580 int i; 4581 char channel; 4582 4583 scb = (struct scb *)arg; 4584 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4585 4586 s = splbio(); 4587 4588 /* 4589 * Ensure that the card doesn't do anything 4590 * behind our back. Also make sure that we 4591 * didn't "just" miss an interrupt that would 4592 * affect this timeout. 4593 */ 4594 do { 4595 ahc_intr(ahc); 4596 pause_sequencer(ahc); 4597 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4598 4599 if ((scb->flags & SCB_ACTIVE) == 0) { 4600 /* Previous timeout took care of me already */ 4601 printf("Timedout SCB handled by another timeout\n"); 4602 unpause_sequencer(ahc); 4603 splx(s); 4604 return; 4605 } 4606 4607 target = SCB_TARGET(scb); 4608 channel = SCB_CHANNEL(scb); 4609 lun = SCB_LUN(scb); 4610 4611 scsi_print_addr(scb->xs->sc_link); 4612 printf("SCB %x - timed out ", scb->hscb->tag); 4613 /* 4614 * Take a snapshot of the bus state and print out 4615 * some information so we can track down driver bugs. 4616 */ 4617 last_phase = ahc_inb(ahc, LASTPHASE); 4618 4619 for (i = 0; i < num_phases; i++) { 4620 if (last_phase == phase_table[i].phase) 4621 break; 4622 } 4623 printf("%s", phase_table[i].phasemsg); 4624 4625 printf(", SEQADDR == 0x%x\n", 4626 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4627 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4628 4629 #ifdef AHC_DEBUG 4630 ahc_print_scb(scb); 4631 #endif 4632 4633 #if 0 4634 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4635 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4636 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4637 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4638 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4639 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4640 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4641 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4642 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4643 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4644 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4645 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4646 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4647 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4648 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4649 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4650 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4651 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4652 if (scb->sg_count > 0) { 4653 for (i = 0; i < scb->sg_count; i++) { 4654 printf("sg[%d] - Addr 0x%x : Length %d\n", 4655 i, 4656 le32toh(scb->sg_list[i].addr), 4657 le32toh(scb->sg_list[i].len)); 4658 } 4659 } 4660 #endif 4661 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4662 /* 4663 * Been down this road before. 4664 * Do a full bus reset. 4665 */ 4666 bus_reset: 4667 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4668 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4669 printf("%s: Issued Channel %c Bus Reset. " 4670 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4671 } else { 4672 /* 4673 * If we are a target, transition to bus free and report 4674 * the timeout. 4675 * 4676 * The target/initiator that is holding up the bus may not 4677 * be the same as the one that triggered this timeout 4678 * (different commands have different timeout lengths). 4679 * If the bus is idle and we are actiing as the initiator 4680 * for this request, queue a BDR message to the timed out 4681 * target. Otherwise, if the timed out transaction is 4682 * active: 4683 * Initiator transaction: 4684 * Stuff the message buffer with a BDR message and assert 4685 * ATN in the hopes that the target will let go of the bus 4686 * and go to the mesgout phase. If this fails, we'll 4687 * get another timeout 2 seconds later which will attempt 4688 * a bus reset. 4689 * 4690 * Target transaction: 4691 * Transition to BUS FREE and report the error. 4692 * It's good to be the target! 4693 */ 4694 u_int active_scb_index; 4695 4696 active_scb_index = ahc_inb(ahc, SCB_TAG); 4697 4698 if (last_phase != P_BUSFREE 4699 && (active_scb_index < ahc->scb_data->numscbs)) { 4700 struct scb *active_scb; 4701 4702 /* 4703 * If the active SCB is not from our device, 4704 * assume that another device is hogging the bus 4705 * and wait for it's timeout to expire before 4706 * taking additional action. 4707 */ 4708 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4709 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4710 u_int newtimeout; 4711 4712 scsi_print_addr(scb->xs->sc_link); 4713 printf("Other SCB Timeout%s", 4714 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4715 ? " again\n" : "\n"); 4716 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4717 newtimeout = MAX(active_scb->xs->timeout, 4718 scb->xs->timeout); 4719 callout_reset(&scb->xs->xs_callout, 4720 (newtimeout * hz) / 1000, 4721 ahc_timeout, scb); 4722 splx(s); 4723 return; 4724 } 4725 4726 /* It's us */ 4727 if ((scb->hscb->control & TARGET_SCB) != 0) { 4728 4729 /* 4730 * Send back any queued up transactions 4731 * and properly record the error condition. 4732 */ 4733 ahc_freeze_devq(ahc, scb->xs->sc_link); 4734 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4735 ahc_freeze_ccb(scb); 4736 ahc_done(ahc, scb); 4737 4738 /* Will clear us from the bus */ 4739 restart_sequencer(ahc); 4740 return; 4741 } 4742 4743 ahc_set_recoveryscb(ahc, active_scb); 4744 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4745 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4746 scsi_print_addr(active_scb->xs->sc_link); 4747 printf("BDR message in message buffer\n"); 4748 active_scb->flags |= SCB_DEVICE_RESET; 4749 callout_reset(&active_scb->xs->xs_callout, 4750 2 * hz, ahc_timeout, active_scb); 4751 unpause_sequencer(ahc); 4752 } else { 4753 int disconnected; 4754 4755 /* XXX Shouldn't panic. Just punt instead */ 4756 if ((scb->hscb->control & TARGET_SCB) != 0) 4757 panic("Timed-out target SCB but bus idle"); 4758 4759 if (last_phase != P_BUSFREE 4760 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4761 /* XXX What happened to the SCB? */ 4762 /* Hung target selection. Goto busfree */ 4763 printf("%s: Hung target selection\n", 4764 ahc_name(ahc)); 4765 restart_sequencer(ahc); 4766 return; 4767 } 4768 4769 if (ahc_search_qinfifo(ahc, target, channel, lun, 4770 scb->hscb->tag, ROLE_INITIATOR, 4771 /*status*/0, SEARCH_COUNT) > 0) { 4772 disconnected = FALSE; 4773 } else { 4774 disconnected = TRUE; 4775 } 4776 4777 if (disconnected) { 4778 u_int active_scb; 4779 4780 ahc_set_recoveryscb(ahc, scb); 4781 /* 4782 * Simply set the MK_MESSAGE control bit. 4783 */ 4784 scb->hscb->control |= MK_MESSAGE; 4785 scb->flags |= SCB_QUEUED_MSG 4786 | SCB_DEVICE_RESET; 4787 4788 /* 4789 * Mark the cached copy of this SCB in the 4790 * disconnected list too, so that a reconnect 4791 * at this point causes a BDR or abort. 4792 */ 4793 active_scb = ahc_inb(ahc, SCBPTR); 4794 if (ahc_search_disc_list(ahc, target, 4795 channel, lun, 4796 scb->hscb->tag, 4797 /*stop_on_first*/TRUE, 4798 /*remove*/FALSE, 4799 /*save_state*/FALSE)) { 4800 u_int scb_control; 4801 4802 scb_control = ahc_inb(ahc, SCB_CONTROL); 4803 scb_control |= MK_MESSAGE; 4804 ahc_outb(ahc, SCB_CONTROL, scb_control); 4805 } 4806 ahc_outb(ahc, SCBPTR, active_scb); 4807 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4808 /*unbusy*/TRUE); 4809 4810 /* 4811 * Actually re-queue this SCB in case we can 4812 * select the device before it reconnects. 4813 * Clear out any entries in the QINFIFO first 4814 * so we are the next SCB for this target 4815 * to run. 4816 */ 4817 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4818 channel, SCB_LUN(scb), 4819 SCB_LIST_NULL, 4820 ROLE_INITIATOR, 4821 SCB_REQUEUE, 4822 SEARCH_COMPLETE); 4823 scsi_print_addr(scb->xs->sc_link); 4824 printf("Queuing a BDR SCB\n"); 4825 ahc->qinfifo[ahc->qinfifonext++] = 4826 scb->hscb->tag; 4827 4828 bus_dmamap_sync(ahc->parent_dmat, 4829 ahc->shared_data_dmamap, 4830 QINFIFO_OFFSET * 256, 256, 4831 BUS_DMASYNC_PREWRITE); 4832 4833 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4834 ahc_outb(ahc, HNSCB_QOFF, 4835 ahc->qinfifonext); 4836 } else { 4837 ahc_outb(ahc, KERNEL_QINPOS, 4838 ahc->qinfifonext); 4839 } 4840 callout_reset(&scb->xs->xs_callout, 2 * hz, 4841 ahc_timeout, scb); 4842 unpause_sequencer(ahc); 4843 } else { 4844 /* Go "immediatly" to the bus reset */ 4845 /* This shouldn't happen */ 4846 ahc_set_recoveryscb(ahc, scb); 4847 scsi_print_addr(scb->xs->sc_link); 4848 printf("SCB %x: Immediate reset. " 4849 "Flags = 0x%x\n", scb->hscb->tag, 4850 scb->flags); 4851 goto bus_reset; 4852 } 4853 } 4854 } 4855 splx(s); 4856 } 4857 4858 static int 4859 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4860 int lun, u_int tag, role_t role, scb_flag status, 4861 ahc_search_action action) 4862 { 4863 struct scb *scbp; 4864 u_int8_t qinpos; 4865 u_int8_t qintail; 4866 int found; 4867 4868 qinpos = ahc_inb(ahc, QINPOS); 4869 qintail = ahc->qinfifonext; 4870 found = 0; 4871 4872 /* 4873 * Start with an empty queue. Entries that are not chosen 4874 * for removal will be re-added to the queue as we go. 4875 */ 4876 ahc->qinfifonext = qinpos; 4877 4878 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4879 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4880 4881 while (qinpos != qintail) { 4882 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4883 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4884 /* 4885 * We found an scb that needs to be removed. 4886 */ 4887 switch (action) { 4888 case SEARCH_COMPLETE: 4889 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4890 scbp->flags |= status; 4891 scbp->xs->error = XS_NOERROR; 4892 } 4893 ahc_freeze_ccb(scbp); 4894 ahc_done(ahc, scbp); 4895 break; 4896 case SEARCH_COUNT: 4897 ahc->qinfifo[ahc->qinfifonext++] = 4898 scbp->hscb->tag; 4899 break; 4900 case SEARCH_REMOVE: 4901 break; 4902 } 4903 found++; 4904 } else { 4905 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4906 } 4907 qinpos++; 4908 } 4909 4910 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4911 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4912 4913 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4914 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4915 } else { 4916 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4917 } 4918 4919 return (found); 4920 } 4921 4922 /* 4923 * Abort all SCBs that match the given description (target/channel/lun/tag), 4924 * setting their status to the passed in status if the status has not already 4925 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4926 * is paused before it is called. 4927 */ 4928 static int 4929 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4930 int lun, u_int tag, role_t role, int status) 4931 { 4932 struct scb *scbp; 4933 u_int active_scb; 4934 int i; 4935 int found; 4936 4937 /* restore this when we're done */ 4938 active_scb = ahc_inb(ahc, SCBPTR); 4939 4940 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4941 role, SCB_REQUEUE, SEARCH_COMPLETE); 4942 4943 /* 4944 * Search waiting for selection list. 4945 */ 4946 { 4947 u_int8_t next, prev; 4948 4949 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4950 prev = SCB_LIST_NULL; 4951 4952 while (next != SCB_LIST_NULL) { 4953 u_int8_t scb_index; 4954 4955 ahc_outb(ahc, SCBPTR, next); 4956 scb_index = ahc_inb(ahc, SCB_TAG); 4957 if (scb_index >= ahc->scb_data->numscbs) { 4958 panic("Waiting List inconsistency. " 4959 "SCB index == %d, yet numscbs == %d.", 4960 scb_index, ahc->scb_data->numscbs); 4961 } 4962 scbp = &ahc->scb_data->scbarray[scb_index]; 4963 if (ahc_match_scb(scbp, target, channel, 4964 lun, SCB_LIST_NULL, role)) { 4965 4966 next = ahc_abort_wscb(ahc, next, prev); 4967 } else { 4968 4969 prev = next; 4970 next = ahc_inb(ahc, SCB_NEXT); 4971 } 4972 } 4973 } 4974 /* 4975 * Go through the disconnected list and remove any entries we 4976 * have queued for completion, 0'ing their control byte too. 4977 * We save the active SCB and restore it ourselves, so there 4978 * is no reason for this search to restore it too. 4979 */ 4980 ahc_search_disc_list(ahc, target, channel, lun, tag, 4981 /*stop_on_first*/FALSE, /*remove*/TRUE, 4982 /*save_state*/FALSE); 4983 4984 /* 4985 * Go through the hardware SCB array looking for commands that 4986 * were active but not on any list. 4987 */ 4988 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4989 u_int scbid; 4990 4991 ahc_outb(ahc, SCBPTR, i); 4992 scbid = ahc_inb(ahc, SCB_TAG); 4993 scbp = &ahc->scb_data->scbarray[scbid]; 4994 if (scbid < ahc->scb_data->numscbs 4995 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4996 ahc_add_curscb_to_free_list(ahc); 4997 } 4998 4999 /* 5000 * Go through the pending CCB list and look for 5001 * commands for this target that are still active. 5002 * These are other tagged commands that were 5003 * disconnected when the reset occured. 5004 */ 5005 { 5006 struct scb *scb; 5007 5008 scb = ahc->pending_ccbs.lh_first; 5009 while (scb != NULL) { 5010 scbp = scb; 5011 scb = scb->plinks.le_next; 5012 if (ahc_match_scb(scbp, target, channel, 5013 lun, tag, role)) { 5014 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5015 ahcsetccbstatus(scbp->xs, status); 5016 ahc_freeze_ccb(scbp); 5017 ahc_done(ahc, scbp); 5018 found++; 5019 } 5020 } 5021 } 5022 ahc_outb(ahc, SCBPTR, active_scb); 5023 return found; 5024 } 5025 5026 static int 5027 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5028 int lun, u_int tag, int stop_on_first, int remove, 5029 int save_state) 5030 { 5031 struct scb *scbp; 5032 u_int next; 5033 u_int prev; 5034 u_int count; 5035 u_int active_scb; 5036 5037 count = 0; 5038 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5039 prev = SCB_LIST_NULL; 5040 5041 if (save_state) { 5042 /* restore this when we're done */ 5043 active_scb = ahc_inb(ahc, SCBPTR); 5044 } else 5045 /* Silence compiler */ 5046 active_scb = SCB_LIST_NULL; 5047 5048 while (next != SCB_LIST_NULL) { 5049 u_int scb_index; 5050 5051 ahc_outb(ahc, SCBPTR, next); 5052 scb_index = ahc_inb(ahc, SCB_TAG); 5053 if (scb_index >= ahc->scb_data->numscbs) { 5054 panic("Disconnected List inconsistency. " 5055 "SCB index == %d, yet numscbs == %d.", 5056 scb_index, ahc->scb_data->numscbs); 5057 } 5058 scbp = &ahc->scb_data->scbarray[scb_index]; 5059 if (ahc_match_scb(scbp, target, channel, lun, 5060 tag, ROLE_INITIATOR)) { 5061 count++; 5062 if (remove) { 5063 next = 5064 ahc_rem_scb_from_disc_list(ahc, prev, next); 5065 } else { 5066 prev = next; 5067 next = ahc_inb(ahc, SCB_NEXT); 5068 } 5069 if (stop_on_first) 5070 break; 5071 } else { 5072 prev = next; 5073 next = ahc_inb(ahc, SCB_NEXT); 5074 } 5075 } 5076 if (save_state) 5077 ahc_outb(ahc, SCBPTR, active_scb); 5078 return (count); 5079 } 5080 5081 static u_int 5082 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5083 { 5084 u_int next; 5085 5086 ahc_outb(ahc, SCBPTR, scbptr); 5087 next = ahc_inb(ahc, SCB_NEXT); 5088 5089 ahc_outb(ahc, SCB_CONTROL, 0); 5090 5091 ahc_add_curscb_to_free_list(ahc); 5092 5093 if (prev != SCB_LIST_NULL) { 5094 ahc_outb(ahc, SCBPTR, prev); 5095 ahc_outb(ahc, SCB_NEXT, next); 5096 } else 5097 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5098 5099 return (next); 5100 } 5101 5102 static void 5103 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5104 { 5105 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5106 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5107 5108 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5109 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5110 } 5111 5112 /* 5113 * Manipulate the waiting for selection list and return the 5114 * scb that follows the one that we remove. 5115 */ 5116 static u_int 5117 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5118 { 5119 u_int curscb, next; 5120 5121 /* 5122 * Select the SCB we want to abort and 5123 * pull the next pointer out of it. 5124 */ 5125 curscb = ahc_inb(ahc, SCBPTR); 5126 ahc_outb(ahc, SCBPTR, scbpos); 5127 next = ahc_inb(ahc, SCB_NEXT); 5128 5129 /* Clear the necessary fields */ 5130 ahc_outb(ahc, SCB_CONTROL, 0); 5131 5132 ahc_add_curscb_to_free_list(ahc); 5133 5134 /* update the waiting list */ 5135 if (prev == SCB_LIST_NULL) { 5136 /* First in the list */ 5137 ahc_outb(ahc, WAITING_SCBH, next); 5138 5139 /* 5140 * Ensure we aren't attempting to perform 5141 * selection for this entry. 5142 */ 5143 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5144 } else { 5145 /* 5146 * Select the scb that pointed to us 5147 * and update its next pointer. 5148 */ 5149 ahc_outb(ahc, SCBPTR, prev); 5150 ahc_outb(ahc, SCB_NEXT, next); 5151 } 5152 5153 /* 5154 * Point us back at the original scb position. 5155 */ 5156 ahc_outb(ahc, SCBPTR, curscb); 5157 return next; 5158 } 5159 5160 static void 5161 ahc_clear_intstat(struct ahc_softc *ahc) 5162 { 5163 /* Clear any interrupt conditions this may have caused */ 5164 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5165 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5166 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5167 CLRREQINIT); 5168 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5169 } 5170 5171 static void 5172 ahc_reset_current_bus(struct ahc_softc *ahc) 5173 { 5174 u_int8_t scsiseq; 5175 5176 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5177 scsiseq = ahc_inb(ahc, SCSISEQ); 5178 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5179 DELAY(AHC_BUSRESET_DELAY); 5180 /* Turn off the bus reset */ 5181 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5182 5183 ahc_clear_intstat(ahc); 5184 5185 /* Re-enable reset interrupts */ 5186 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5187 } 5188 5189 static int 5190 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5191 { 5192 u_int initiator, target, max_scsiid; 5193 u_int sblkctl; 5194 u_int our_id; 5195 int found; 5196 int restart_needed; 5197 char cur_channel; 5198 5199 ahc->pending_device = NULL; 5200 5201 pause_sequencer(ahc); 5202 5203 /* 5204 * Run our command complete fifos to ensure that we perform 5205 * completion processing on any commands that 'completed' 5206 * before the reset occurred. 5207 */ 5208 ahc_run_qoutfifo(ahc); 5209 5210 /* 5211 * Reset the bus if we are initiating this reset 5212 */ 5213 sblkctl = ahc_inb(ahc, SBLKCTL); 5214 cur_channel = 'A'; 5215 if ((ahc->features & AHC_TWIN) != 0 5216 && ((sblkctl & SELBUSB) != 0)) 5217 cur_channel = 'B'; 5218 if (cur_channel != channel) { 5219 /* Case 1: Command for another bus is active 5220 * Stealthily reset the other bus without 5221 * upsetting the current bus. 5222 */ 5223 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5224 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5225 ahc_outb(ahc, SCSISEQ, 5226 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5227 if (initiate_reset) 5228 ahc_reset_current_bus(ahc); 5229 ahc_clear_intstat(ahc); 5230 ahc_outb(ahc, SBLKCTL, sblkctl); 5231 restart_needed = FALSE; 5232 } else { 5233 /* Case 2: A command from this bus is active or we're idle */ 5234 ahc_clear_msg_state(ahc); 5235 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5236 ahc_outb(ahc, SCSISEQ, 5237 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5238 if (initiate_reset) 5239 ahc_reset_current_bus(ahc); 5240 ahc_clear_intstat(ahc); 5241 5242 /* 5243 * Since we are going to restart the sequencer, avoid 5244 * a race in the sequencer that could cause corruption 5245 * of our Q pointers by starting over from index 0. 5246 */ 5247 ahc->qoutfifonext = 0; 5248 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5249 ahc_outb(ahc, SDSCB_QOFF, 0); 5250 else 5251 ahc_outb(ahc, QOUTPOS, 0); 5252 restart_needed = TRUE; 5253 } 5254 5255 /* 5256 * Clean up all the state information for the 5257 * pending transactions on this bus. 5258 */ 5259 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5260 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5261 ROLE_UNKNOWN, XS_RESET); 5262 if (channel == 'B') { 5263 our_id = ahc->our_id_b; 5264 } else { 5265 our_id = ahc->our_id; 5266 } 5267 5268 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5269 5270 /* 5271 * Revert to async/narrow transfers until we renegotiate. 5272 */ 5273 for (target = 0; target <= max_scsiid; target++) { 5274 5275 if (ahc->enabled_targets[target] == NULL) 5276 continue; 5277 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5278 struct ahc_devinfo devinfo; 5279 5280 ahc_compile_devinfo(&devinfo, target, initiator, 5281 AHC_LUN_WILDCARD, 5282 channel, ROLE_UNKNOWN); 5283 ahc_set_width(ahc, &devinfo, 5284 MSG_EXT_WDTR_BUS_8_BIT, 5285 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5286 ahc_set_syncrate(ahc, &devinfo, 5287 /*syncrate*/NULL, /*period*/0, 5288 /*offset*/0, AHC_TRANS_CUR, 5289 /*paused*/TRUE, FALSE); 5290 } 5291 } 5292 5293 if (restart_needed) 5294 restart_sequencer(ahc); 5295 else 5296 unpause_sequencer(ahc); 5297 return found; 5298 } 5299 5300 static int 5301 ahc_match_scb(struct scb *scb, int target, char channel, 5302 int lun, u_int tag, role_t role) 5303 { 5304 int targ = SCB_TARGET(scb); 5305 char chan = SCB_CHANNEL(scb); 5306 int slun = SCB_LUN(scb); 5307 int match; 5308 5309 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5310 if (match != 0) 5311 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5312 if (match != 0) 5313 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5314 5315 return match; 5316 } 5317 5318 static void 5319 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5320 { 5321 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5322 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5323 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5324 ahc->msgout_buf[ahc->msgout_index++] = period; 5325 ahc->msgout_buf[ahc->msgout_index++] = offset; 5326 ahc->msgout_len += 5; 5327 } 5328 5329 static void 5330 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5331 { 5332 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5333 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5334 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5335 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5336 ahc->msgout_len += 4; 5337 } 5338 5339 static void 5340 ahc_calc_residual(struct scb *scb) 5341 { 5342 struct hardware_scb *hscb; 5343 5344 hscb = scb->hscb; 5345 5346 /* 5347 * If the disconnected flag is still set, this is bogus 5348 * residual information left over from a sequencer 5349 * pagin/pageout, so ignore this case. 5350 */ 5351 if ((scb->hscb->control & DISCONNECTED) == 0) { 5352 u_int32_t resid; 5353 int resid_sgs; 5354 int sg; 5355 5356 /* 5357 * Remainder of the SG where the transfer 5358 * stopped. 5359 */ 5360 resid = (hscb->residual_data_count[2] << 16) 5361 | (hscb->residual_data_count[1] <<8) 5362 | (hscb->residual_data_count[0]); 5363 5364 /* 5365 * Add up the contents of all residual 5366 * SG segments that are after the SG where 5367 * the transfer stopped. 5368 */ 5369 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5370 sg = scb->sg_count - resid_sgs; 5371 while (resid_sgs > 0) { 5372 5373 resid += le32toh(scb->sg_list[sg].len); 5374 sg++; 5375 resid_sgs--; 5376 } 5377 scb->xs->resid = resid; 5378 } 5379 5380 /* 5381 * Clean out the residual information in this SCB for its 5382 * next consumer. 5383 */ 5384 hscb->residual_SG_count = 0; 5385 5386 #ifdef AHC_DEBUG 5387 if (ahc_debug & AHC_SHOWMISC) { 5388 scsi_print_addr(scb->xs->sc_link); 5389 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5390 } 5391 #endif 5392 } 5393 5394 static void 5395 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5396 { 5397 struct scb *scb; 5398 int pending_ccb_count; 5399 int i; 5400 u_int saved_scbptr; 5401 5402 /* 5403 * Traverse the pending SCB list and ensure that all of the 5404 * SCBs there have the proper settings. 5405 */ 5406 scb = LIST_FIRST(&ahc->pending_ccbs); 5407 pending_ccb_count = 0; 5408 while (scb != NULL) { 5409 struct ahc_devinfo devinfo; 5410 struct scsipi_xfer *xs; 5411 struct scb *pending_scb; 5412 struct hardware_scb *pending_hscb; 5413 struct ahc_initiator_tinfo *tinfo; 5414 struct tmode_tstate *tstate; 5415 u_int our_id, remote_id; 5416 5417 xs = scb->xs; 5418 pending_scb = scb; 5419 pending_hscb = pending_scb->hscb; 5420 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5421 ? ahc->our_id_b : ahc->our_id; 5422 remote_id = xs->sc_link->scsipi_scsi.target; 5423 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5424 SCB_LUN(pending_scb), 5425 SCB_CHANNEL(pending_scb), 5426 ROLE_UNKNOWN); 5427 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5428 our_id, remote_id, &tstate); 5429 pending_hscb->control &= ~ULTRAENB; 5430 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5431 pending_hscb->control |= ULTRAENB; 5432 pending_hscb->scsirate = tinfo->scsirate; 5433 pending_hscb->scsioffset = tinfo->current.offset; 5434 pending_ccb_count++; 5435 scb = LIST_NEXT(scb, plinks); 5436 } 5437 5438 if (pending_ccb_count == 0) 5439 return; 5440 5441 saved_scbptr = ahc_inb(ahc, SCBPTR); 5442 /* Ensure that the hscbs down on the card match the new information */ 5443 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5444 u_int scb_tag; 5445 5446 ahc_outb(ahc, SCBPTR, i); 5447 scb_tag = ahc_inb(ahc, SCB_TAG); 5448 if (scb_tag != SCB_LIST_NULL) { 5449 struct ahc_devinfo devinfo; 5450 struct scb *pending_scb; 5451 struct scsipi_xfer *xs; 5452 struct hardware_scb *pending_hscb; 5453 struct ahc_initiator_tinfo *tinfo; 5454 struct tmode_tstate *tstate; 5455 u_int our_id, remote_id; 5456 u_int control; 5457 5458 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5459 if (pending_scb->flags == SCB_FREE) 5460 continue; 5461 pending_hscb = pending_scb->hscb; 5462 xs = pending_scb->xs; 5463 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5464 ? ahc->our_id_b : ahc->our_id; 5465 remote_id = xs->sc_link->scsipi_scsi.target; 5466 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5467 SCB_LUN(pending_scb), 5468 SCB_CHANNEL(pending_scb), 5469 ROLE_UNKNOWN); 5470 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5471 our_id, remote_id, &tstate); 5472 control = ahc_inb(ahc, SCB_CONTROL); 5473 control &= ~ULTRAENB; 5474 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5475 control |= ULTRAENB; 5476 ahc_outb(ahc, SCB_CONTROL, control); 5477 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5478 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5479 } 5480 } 5481 ahc_outb(ahc, SCBPTR, saved_scbptr); 5482 } 5483 5484 #if UNUSED 5485 static void 5486 ahc_dump_targcmd(struct target_cmd *cmd) 5487 { 5488 u_int8_t *byte; 5489 u_int8_t *last_byte; 5490 int i; 5491 5492 byte = &cmd->initiator_channel; 5493 /* Debugging info for received commands */ 5494 last_byte = &cmd[1].initiator_channel; 5495 5496 i = 0; 5497 while (byte < last_byte) { 5498 if (i == 0) 5499 printf("\t"); 5500 printf("%#x", *byte++); 5501 i++; 5502 if (i == 8) { 5503 printf("\n"); 5504 i = 0; 5505 } else { 5506 printf(", "); 5507 } 5508 } 5509 } 5510 #endif 5511 5512 static void 5513 ahc_shutdown(void *arg) 5514 { 5515 struct ahc_softc *ahc; 5516 int i; 5517 u_int sxfrctl1_a, sxfrctl1_b; 5518 5519 ahc = (struct ahc_softc *)arg; 5520 5521 pause_sequencer(ahc); 5522 5523 /* 5524 * Preserve the value of the SXFRCTL1 register for all channels. 5525 * It contains settings that affect termination and we don't want 5526 * to disturb the integrity of the bus during shutdown in case 5527 * we are in a multi-initiator setup. 5528 */ 5529 sxfrctl1_b = 0; 5530 if ((ahc->features & AHC_TWIN) != 0) { 5531 u_int sblkctl; 5532 5533 sblkctl = ahc_inb(ahc, SBLKCTL); 5534 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5535 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5536 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5537 } 5538 5539 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5540 5541 /* This will reset most registers to 0, but not all */ 5542 ahc_reset(ahc); 5543 5544 if ((ahc->features & AHC_TWIN) != 0) { 5545 u_int sblkctl; 5546 5547 sblkctl = ahc_inb(ahc, SBLKCTL); 5548 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5549 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5550 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5551 } 5552 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5553 5554 ahc_outb(ahc, SCSISEQ, 0); 5555 ahc_outb(ahc, SXFRCTL0, 0); 5556 ahc_outb(ahc, DSPCISTATUS, 0); 5557 5558 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5559 ahc_outb(ahc, i, 0); 5560 } 5561 5562 #if defined(AHC_DEBUG) && 0 5563 static void 5564 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5565 { 5566 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5567 5568 printf("\tcurrent:\n"); 5569 printf("\t\twidth %u period %u offset %u flags %x\n", 5570 tinfo->current.width, tinfo->current.period, 5571 tinfo->current.offset, tinfo->current.ppr_flags); 5572 5573 printf("\tgoal:\n"); 5574 printf("\t\twidth %u period %u offset %u flags %x\n", 5575 tinfo->goal.width, tinfo->goal.period, 5576 tinfo->goal.offset, tinfo->goal.ppr_flags); 5577 5578 printf("\tuser:\n"); 5579 printf("\t\twidth %u period %u offset %u flags %x\n", 5580 tinfo->user.width, tinfo->user.period, 5581 tinfo->user.offset, tinfo->user.ppr_flags); 5582 } 5583 #endif 5584 5585 static void 5586 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5587 { 5588 struct scsipi_inquiry_data *inq; 5589 struct ahc_devinfo devinfo; 5590 struct tmode_tstate *tstate; 5591 int target_id, our_id; 5592 char channel; 5593 5594 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5595 return; 5596 5597 if (xs->sc_link->quirks & SDEV_NOTAG) 5598 return; 5599 5600 target_id = xs->sc_link->scsipi_scsi.target; 5601 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5602 channel = SIM_CHANNEL(ahc, xs->sc_link); 5603 5604 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5605 ahc_compile_devinfo(&devinfo, our_id, target_id, 5606 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5607 5608 if (tstate->tagdisable & devinfo.target_mask) 5609 return; 5610 5611 /* 5612 * Sneak a look at the results of the SCSI Inquiry 5613 * command and see if we can do Tagged queing. This 5614 * should really be done by the higher level drivers. 5615 */ 5616 inq = (struct scsipi_inquiry_data *)xs->data; 5617 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5618 printf("%s: target %d using tagged queuing\n", 5619 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5620 5621 ahc_set_tags(ahc, &devinfo, TRUE); 5622 5623 if (ahc->scb_data->maxhscbs >= 16 || 5624 (ahc->flags & AHC_PAGESCBS)) { 5625 /* Default to 16 tags */ 5626 xs->sc_link->openings = 16; 5627 } else { 5628 /* 5629 * Default to 4 tags on whimpy 5630 * cards that don't have much SCB 5631 * space and can't page. This prevents 5632 * a single device from hogging all 5633 * slots. We should really have a better 5634 * way of providing fairness. 5635 */ 5636 xs->sc_link->openings = 4; 5637 } 5638 } 5639 } 5640 5641 static int 5642 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5643 int nocmdcheck) 5644 { 5645 char channel; 5646 u_int our_id, target; 5647 struct tmode_tstate *tstate; 5648 struct ahc_devinfo devinfo; 5649 5650 if (xs->sc_link->quirks & SDEV_NOTAG) 5651 return 0; 5652 5653 /* 5654 * XXX never do these commands with tags. Should really be 5655 * in a higher layer. 5656 */ 5657 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5658 xs->cmd->opcode == TEST_UNIT_READY || 5659 xs->cmd->opcode == REQUEST_SENSE)) 5660 return 0; 5661 5662 channel = SIM_CHANNEL(ahc, xs->sc_link); 5663 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5664 target = xs->sc_link->scsipi_scsi.target; 5665 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5666 5667 ahc_compile_devinfo(&devinfo, our_id, target, 5668 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5669 5670 return (tstate->tagenable & devinfo.target_mask); 5671 } 5672
Indexes created Tue Sep 30 17:09:57 GMT 2025