aic7xxx.c revision 1.54
1 /* $NetBSD: aic7xxx.c,v 1.54 2000/05/29 20:13:53 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 #include <sys/scsiio.h> 99 100 #include <machine/bus.h> 101 #include <machine/intr.h> 102 103 #include <dev/scsipi/scsi_all.h> 104 #include <dev/scsipi/scsipi_all.h> 105 #include <dev/scsipi/scsi_message.h> 106 #include <dev/scsipi/scsipi_debug.h> 107 #include <dev/scsipi/scsiconf.h> 108 109 #include <vm/vm.h> 110 #include <vm/vm_param.h> 111 #include <vm/pmap.h> 112 113 #include <dev/ic/aic7xxxvar.h> 114 #include <dev/microcode/aic7xxx/sequencer.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 116 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 117 118 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 119 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 120 #define ALL_CHANNELS '\0' 121 #define ALL_TARGETS_MASK 0xFFFF 122 #define INITIATOR_WILDCARD (~0) 123 124 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 125 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 126 #define SIM_CHANNEL(ahc, sc_link) \ 127 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 128 #define SIM_SCSI_ID(ahc, sc_link) \ 129 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 130 #define SCB_IS_SCSIBUS_B(scb) \ 131 (((scb)->hscb->tcl & SELBUSB) != 0) 132 #define SCB_TARGET(scb) \ 133 (((scb)->hscb->tcl & TID) >> 4) 134 #define SCB_CHANNEL(scb) \ 135 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 136 #define SCB_LUN(scb) \ 137 ((scb)->hscb->tcl & LID) 138 #define SCB_TARGET_OFFSET(scb) \ 139 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 140 #define SCB_TARGET_MASK(scb) \ 141 (0x01 << (SCB_TARGET_OFFSET(scb))) 142 #define TCL_CHANNEL(ahc, tcl) \ 143 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 144 #define TCL_SCSI_ID(ahc, tcl) \ 145 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 146 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 147 #define TCL_LUN(tcl) ((tcl) & LID) 148 149 #define XS_TCL(ahc, xs) \ 150 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 151 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 152 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 153 154 char *ahc_chip_names[] = 155 { 156 "NONE", 157 "aic7770", 158 "aic7850", 159 "aic7855", 160 "aic7859", 161 "aic7860", 162 "aic7870", 163 "aic7880", 164 "aic7890/91", 165 "aic7892", 166 "aic7895", 167 "aic7896/97", 168 "aic7899" 169 }; 170 171 typedef enum { 172 ROLE_UNKNOWN, 173 ROLE_INITIATOR, 174 ROLE_TARGET 175 } role_t; 176 177 struct ahc_devinfo { 178 int our_scsiid; 179 int target_offset; 180 u_int16_t target_mask; 181 u_int8_t target; 182 u_int8_t lun; 183 char channel; 184 role_t role; /* 185 * Only guaranteed to be correct if not 186 * in the busfree state. 187 */ 188 }; 189 190 typedef enum { 191 SEARCH_COMPLETE, 192 SEARCH_COUNT, 193 SEARCH_REMOVE 194 } ahc_search_action; 195 196 #ifdef AHC_DEBUG 197 static int ahc_debug = AHC_DEBUG; 198 #endif 199 200 static int ahcinitscbdata(struct ahc_softc *); 201 static void ahcfiniscbdata(struct ahc_softc *); 202 203 #if UNUSED 204 static void ahc_dump_targcmd(struct target_cmd *); 205 #endif 206 static void ahc_shutdown(void *arg); 207 static int32_t ahc_action(struct scsipi_xfer *); 208 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 209 struct proc *); 210 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 211 static int ahc_poll(struct ahc_softc *, int); 212 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 213 struct scb *); 214 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 215 static void ahcallocscbs(struct ahc_softc *); 216 #if UNUSED 217 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 218 struct scb *); 219 #endif 220 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 221 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 222 char, role_t); 223 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 224 static void ahc_done(struct ahc_softc *, struct scb *); 225 static struct tmode_tstate * 226 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 227 #if UNUSED 228 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 229 #endif 230 static void ahc_handle_seqint(struct ahc_softc *, u_int); 231 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 232 static void ahc_build_transfer_msg(struct ahc_softc *, 233 struct ahc_devinfo *); 234 static void ahc_setup_initiator_msgout(struct ahc_softc *, 235 struct ahc_devinfo *, 236 struct scb *); 237 static void ahc_setup_target_msgin(struct ahc_softc *, 238 struct ahc_devinfo *); 239 static void ahc_clear_msg_state(struct ahc_softc *); 240 static void ahc_handle_message_phase(struct ahc_softc *, 241 struct scsipi_link *); 242 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 243 244 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 245 struct ahc_devinfo *); 246 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 247 struct ahc_devinfo *); 248 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 249 int, char *, int); 250 #ifdef AHC_DUMP_SEQ 251 static void ahc_dumpseq(struct ahc_softc *); 252 #endif 253 static void ahc_loadseq(struct ahc_softc *); 254 static int ahc_check_patch(struct ahc_softc *, struct patch **, 255 int, int *); 256 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 257 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 258 #if defined(AHC_DEBUG) 259 static void ahc_print_scb(struct scb *); 260 #endif 261 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 262 role_t, scb_flag, ahc_search_action); 263 static int ahc_reset_channel(struct ahc_softc *, char, int); 264 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 265 role_t, int); 266 static int ahc_search_disc_list(struct ahc_softc *, int, 267 char, int, u_int, int, int, int); 268 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 269 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 270 static void ahc_clear_intstat(struct ahc_softc *); 271 static void ahc_reset_current_bus(struct ahc_softc *); 272 static struct ahc_syncrate * 273 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 274 static struct ahc_syncrate * 275 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 276 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 277 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 278 u_int *, int); 279 static void ahc_update_target_msg_request(struct ahc_softc *, 280 struct ahc_devinfo *, 281 struct ahc_initiator_tinfo *, 282 int, int); 283 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 284 struct ahc_syncrate *, u_int, u_int, u_int, 285 int, int); 286 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 287 u_int, u_int, int, int); 288 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 289 int); 290 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 291 292 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 293 294 static void ahc_calc_residual(struct scb *); 295 296 static void ahc_update_pending_syncrates(struct ahc_softc *); 297 298 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 299 300 static void ahc_timeout (void *); 301 static __inline int sequencer_paused(struct ahc_softc *); 302 static __inline void pause_sequencer(struct ahc_softc *); 303 static __inline void unpause_sequencer(struct ahc_softc *); 304 static void restart_sequencer(struct ahc_softc *); 305 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 306 307 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 308 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 309 310 static __inline void ahc_freeze_ccb(struct scb *); 311 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 312 static void ahc_run_qoutfifo(struct ahc_softc *); 313 314 static __inline struct ahc_initiator_tinfo * 315 ahc_fetch_transinfo(struct ahc_softc *, 316 char, u_int, u_int, 317 struct tmode_tstate **); 318 static void ahcfreescb(struct ahc_softc *, struct scb *); 319 static __inline struct scb *ahcgetscb(struct ahc_softc *); 320 321 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 322 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 323 int *, const char *, const char *); 324 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 325 caddr_t, bus_dma_segment_t *, int); 326 static void ahcminphys(struct buf *); 327 328 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 329 static __inline void ahc_swap_hscb(struct hardware_scb *); 330 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 331 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 332 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 333 334 #if defined(AHC_DEBUG) && 0 335 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 336 #endif 337 338 static struct scsipi_device ahc_dev = 339 { 340 NULL, /* Use default error handler */ 341 NULL, /* have a queue, served by this */ 342 NULL, /* have no async handler */ 343 NULL, /* Use default 'done' routine */ 344 }; 345 346 /* 347 * Pick the first xs for a non-blocked target. 348 */ 349 static __inline struct scsipi_xfer * 350 ahc_first_xs(struct ahc_softc *ahc) 351 { 352 int target; 353 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 354 355 if (ahc->queue_blocked) 356 return NULL; 357 358 while (xs != NULL) { 359 target = xs->sc_link->scsipi_scsi.target; 360 if (ahc->devqueue_blocked[target] == 0 && 361 (!ahc_istagged_device(ahc, xs, 0) && 362 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 363 SCB_LIST_NULL)) 364 break; 365 xs = TAILQ_NEXT(xs, adapter_q); 366 } 367 368 return xs; 369 } 370 371 static __inline void 372 ahc_swap_hscb(struct hardware_scb *hscb) 373 { 374 hscb->SG_pointer = htole32(hscb->SG_pointer); 375 hscb->data = htole32(hscb->data); 376 hscb->datalen = htole32(hscb->datalen); 377 /* 378 * No need to swap cmdpointer; it's either 0 or set to 379 * cmdstore_busaddr, which is already swapped. 380 */ 381 } 382 383 static __inline void 384 ahc_swap_sg(struct ahc_dma_seg *sg) 385 { 386 sg->addr = htole32(sg->addr); 387 sg->len = htole32(sg->len); 388 } 389 390 static void 391 ahcminphys(bp) 392 struct buf *bp; 393 { 394 /* 395 * Even though the card can transfer up to 16megs per command 396 * we are limited by the number of segments in the dma segment 397 * list that we can hold. The worst case is that all pages are 398 * discontinuous physically, hense the "page per segment" limit 399 * enforced here. 400 */ 401 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 402 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 403 } 404 minphys(bp); 405 } 406 407 408 static __inline u_int32_t 409 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 410 { 411 return (ahc->scb_data->hscb_busaddr 412 + (sizeof(struct hardware_scb) * index)); 413 } 414 415 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 416 417 static __inline int 418 sequencer_paused(struct ahc_softc *ahc) 419 { 420 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 421 } 422 423 static __inline void 424 pause_sequencer(struct ahc_softc *ahc) 425 { 426 ahc_outb(ahc, HCNTRL, ahc->pause); 427 428 /* 429 * Since the sequencer can disable pausing in a critical section, we 430 * must loop until it actually stops. 431 */ 432 while (sequencer_paused(ahc) == 0) 433 ; 434 } 435 436 static __inline void 437 unpause_sequencer(struct ahc_softc *ahc) 438 { 439 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 440 ahc_outb(ahc, HCNTRL, ahc->unpause); 441 } 442 443 /* 444 * Restart the sequencer program from address zero 445 */ 446 static void 447 restart_sequencer(struct ahc_softc *ahc) 448 { 449 u_int i; 450 451 pause_sequencer(ahc); 452 453 /* 454 * Everytime we restart the sequencer, there 455 * is the possiblitity that we have restarted 456 * within a three instruction window where an 457 * SCB has been marked free but has not made it 458 * onto the free list. Since SCSI events(bus reset, 459 * unexpected bus free) will always freeze the 460 * sequencer, we cannot close this window. To 461 * avoid losing an SCB, we reconsitute the free 462 * list every time we restart the sequencer. 463 */ 464 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 465 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 466 467 ahc_outb(ahc, SCBPTR, i); 468 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 469 ahc_add_curscb_to_free_list(ahc); 470 } 471 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 472 unpause_sequencer(ahc); 473 } 474 475 static __inline u_int 476 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 477 { 478 u_int scbid; 479 480 scbid = ahc->untagged_scbs[tcl]; 481 if (unbusy) { 482 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 483 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 484 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 485 } 486 487 return (scbid); 488 } 489 490 static __inline void 491 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 492 { 493 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 494 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 495 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 496 } 497 498 static __inline int 499 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 500 { 501 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 502 } 503 504 static __inline void 505 ahc_freeze_ccb(struct scb *scb) 506 { 507 struct scsipi_xfer *xs = scb->xs; 508 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 509 int target; 510 511 target = xs->sc_link->scsipi_scsi.target; 512 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 513 ahc->devqueue_blocked[target]++; 514 scb->flags |= SCB_FREEZE_QUEUE; 515 } 516 } 517 518 static __inline void 519 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 520 { 521 xs->error = status; 522 } 523 524 static __inline struct ahc_initiator_tinfo * 525 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 526 u_int remote_id, struct tmode_tstate **tstate) 527 { 528 /* 529 * Transfer data structures are stored from the perspective 530 * of the target role. Since the parameters for a connection 531 * in the initiator role to a given target are the same as 532 * when the roles are reversed, we pretend we are the target. 533 */ 534 if (channel == 'B') 535 our_id += 8; 536 *tstate = ahc->enabled_targets[our_id]; 537 return (&(*tstate)->transinfo[remote_id]); 538 } 539 540 static void 541 ahc_run_qoutfifo(struct ahc_softc *ahc) 542 { 543 struct scb *scb; 544 u_int scb_index; 545 546 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 547 256, BUS_DMASYNC_POSTREAD); 548 549 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 550 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 551 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 552 553 scb = &ahc->scb_data->scbarray[scb_index]; 554 if (scb_index >= ahc->scb_data->numscbs 555 || (scb->flags & SCB_ACTIVE) == 0) { 556 printf("%s: WARNING no command for scb %d " 557 "(cmdcmplt)\nQOUTPOS = %d\n", 558 ahc_name(ahc), scb_index, 559 ahc->qoutfifonext - 1); 560 continue; 561 } 562 563 /* 564 * Save off the residual 565 * if there is one. 566 */ 567 if (scb->hscb->residual_SG_count != 0) 568 ahc_calc_residual(scb); 569 else 570 scb->xs->resid = 0; 571 #ifdef AHC_DEBUG 572 if (ahc_debug & AHC_SHOWSCBS) { 573 scsi_print_addr(scb->xs->sc_link); 574 printf("run_qoutfifo: SCB %x complete\n", 575 scb->hscb->tag); 576 } 577 #endif 578 ahc_done(ahc, scb); 579 } 580 } 581 582 583 /* 584 * An scb (and hence an scb entry on the board) is put onto the 585 * free list. 586 */ 587 static void 588 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 589 { 590 struct hardware_scb *hscb; 591 int opri; 592 593 hscb = scb->hscb; 594 595 #ifdef AHC_DEBUG 596 if (ahc_debug & AHC_SHOWSCBALLOC) 597 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 598 #endif 599 600 opri = splbio(); 601 602 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 603 (scb->flags & SCB_RECOVERY_SCB) != 0) { 604 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 605 ahc->queue_blocked = 0; 606 } 607 608 /* Clean up for the next user */ 609 scb->flags = SCB_FREE; 610 hscb->control = 0; 611 hscb->status = 0; 612 613 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 614 615 splx(opri); 616 } 617 618 /* 619 * Get a free scb, either one already assigned to a hardware slot 620 * on the adapter or one that will require an SCB to be paged out before 621 * use. If there are none, see if we can allocate a new SCB. Otherwise 622 * either return an error or sleep. 623 */ 624 static __inline struct scb * 625 ahcgetscb(struct ahc_softc *ahc) 626 { 627 struct scb *scbp; 628 int opri;; 629 630 opri = splbio(); 631 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 632 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 633 } else { 634 ahcallocscbs(ahc); 635 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 636 if (scbp != NULL) 637 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 638 } 639 640 splx(opri); 641 642 #ifdef AHC_DEBUG 643 if (ahc_debug & AHC_SHOWSCBALLOC) { 644 if (scbp != NULL) 645 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 646 scbp->hscb->tag); 647 else 648 printf("%s: failed to allocate new SCB\n", 649 ahc_name(ahc)); 650 } 651 #endif 652 653 return (scbp); 654 } 655 656 static int 657 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 658 bus_dma_tag_t tag; 659 int size; 660 int flags; 661 bus_dmamap_t *mapp; 662 caddr_t *vaddr; 663 bus_addr_t *baddr; 664 bus_dma_segment_t *seg; 665 int *nseg; 666 const char *myname, *what; 667 { 668 int error, level = 0; 669 670 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 671 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 672 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 673 myname, what, error); 674 goto out; 675 } 676 level++; 677 678 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 679 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 680 printf("%s: failed to map DMA mem for %s, error = %d\n", 681 myname, what, error); 682 goto out; 683 } 684 level++; 685 686 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 687 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 688 printf("%s: failed to create DMA map for %s, error = %d\n", 689 myname, what, error); 690 goto out; 691 } 692 level++; 693 694 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 695 BUS_DMA_NOWAIT)) != 0) { 696 printf("%s: failed to load DMA map for %s, error = %d\n", 697 myname, what, error); 698 goto out; 699 } 700 701 *baddr = (*mapp)->dm_segs[0].ds_addr; 702 703 #ifdef AHC_DEBUG 704 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 705 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 706 *nseg, size); 707 #endif 708 709 return 0; 710 out: 711 switch (level) { 712 case 3: 713 bus_dmamap_destroy(tag, *mapp); 714 /* FALLTHROUGH */ 715 case 2: 716 bus_dmamem_unmap(tag, *vaddr, size); 717 /* FALLTHROUGH */ 718 case 1: 719 bus_dmamem_free(tag, seg, *nseg); 720 break; 721 default: 722 break; 723 } 724 725 return error; 726 } 727 728 static void 729 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 730 bus_dma_tag_t tag; 731 int size; 732 bus_dmamap_t map; 733 caddr_t vaddr; 734 bus_dma_segment_t *seg; 735 int nseg; 736 { 737 738 bus_dmamap_unload(tag, map); 739 bus_dmamap_destroy(tag, map); 740 bus_dmamem_unmap(tag, vaddr, size); 741 bus_dmamem_free(tag, seg, nseg); 742 } 743 744 char * 745 ahc_name(struct ahc_softc *ahc) 746 { 747 return (ahc->sc_dev.dv_xname); 748 } 749 750 #ifdef AHC_DEBUG 751 static void 752 ahc_print_scb(struct scb *scb) 753 { 754 struct hardware_scb *hscb = scb->hscb; 755 756 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 757 scb, 758 hscb->tag, 759 hscb->control, 760 hscb->tcl, 761 hscb->cmdlen, 762 (unsigned long)le32toh(hscb->cmdpointer)); 763 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 764 le32toh(hscb->datalen), 765 (unsigned long)(le32toh(hscb->data)), 766 hscb->SG_count, 767 (unsigned long)(le32toh(hscb->SG_pointer))); 768 printf(" sg_addr:%lx sg_len:%lu\n", 769 (unsigned long)(le32toh(scb->sg_list[0].addr)), 770 (unsigned long)(le32toh(scb->sg_list[0].len))); 771 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 772 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 773 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 774 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 775 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 776 } 777 #endif 778 779 static struct { 780 u_int8_t errno; 781 char *errmesg; 782 } hard_error[] = { 783 { ILLHADDR, "Illegal Host Access" }, 784 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 785 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 786 { SQPARERR, "Sequencer Parity Error" }, 787 { DPARERR, "Data-path Parity Error" }, 788 { MPARERR, "Scratch or SCB Memory Parity Error" }, 789 { PCIERRSTAT, "PCI Error detected" }, 790 { CIOPARERR, "CIOBUS Parity Error" }, 791 }; 792 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 793 794 static struct { 795 u_int8_t phase; 796 u_int8_t mesg_out; /* Message response to parity errors */ 797 char *phasemsg; 798 } phase_table[] = { 799 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 800 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 801 { P_COMMAND, MSG_NOOP, "in Command phase" }, 802 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 803 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 804 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 805 { P_BUSFREE, MSG_NOOP, "while idle" }, 806 { 0, MSG_NOOP, "in unknown phase" } 807 }; 808 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 809 810 /* 811 * Valid SCSIRATE values. (p. 3-17) 812 * Provides a mapping of tranfer periods in ns to the proper value to 813 * stick in the scsiscfr reg to use that transfer rate. 814 */ 815 #define AHC_SYNCRATE_DT 0 816 #define AHC_SYNCRATE_ULTRA2 1 817 #define AHC_SYNCRATE_ULTRA 3 818 #define AHC_SYNCRATE_FAST 6 819 static struct ahc_syncrate ahc_syncrates[] = { 820 /* ultra2 fast/ultra period rate */ 821 { 0x42, 0x000, 9, "80.0" }, 822 { 0x03, 0x000, 10, "40.0" }, 823 { 0x04, 0x000, 11, "33.0" }, 824 { 0x05, 0x100, 12, "20.0" }, 825 { 0x06, 0x110, 15, "16.0" }, 826 { 0x07, 0x120, 18, "13.4" }, 827 { 0x08, 0x000, 25, "10.0" }, 828 { 0x19, 0x010, 31, "8.0" }, 829 { 0x1a, 0x020, 37, "6.67" }, 830 { 0x1b, 0x030, 43, "5.7" }, 831 { 0x1c, 0x040, 50, "5.0" }, 832 { 0x00, 0x050, 56, "4.4" }, 833 { 0x00, 0x060, 62, "4.0" }, 834 { 0x00, 0x070, 68, "3.6" }, 835 { 0x00, 0x000, 0, NULL } 836 }; 837 838 /* 839 * Allocate a controller structure for a new device and initialize it. 840 */ 841 int 842 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 843 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 844 ahc_flag flags) 845 { 846 struct scb_data *scb_data; 847 848 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 849 if (scb_data == NULL) { 850 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 851 return -1; 852 } 853 bzero(scb_data, sizeof (struct scb_data)); 854 LIST_INIT(&ahc->pending_ccbs); 855 ahc->tag = st; 856 ahc->bsh = sh; 857 ahc->parent_dmat = parent_dmat; 858 ahc->chip = chip; 859 ahc->features = features; 860 ahc->flags = flags; 861 ahc->scb_data = scb_data; 862 863 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 864 /* The IRQMS bit is only valid on VL and EISA chips */ 865 if ((ahc->chip & AHC_PCI) != 0) 866 ahc->unpause &= ~IRQMS; 867 ahc->pause = ahc->unpause | PAUSE; 868 return (0); 869 } 870 871 void 872 ahc_free(ahc) 873 struct ahc_softc *ahc; 874 { 875 ahcfiniscbdata(ahc); 876 if (ahc->init_level != 0) 877 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 878 ahc->shared_data_dmamap, ahc->qoutfifo, 879 &ahc->shared_data_seg, ahc->shared_data_nseg); 880 881 if (ahc->scb_data != NULL) 882 free(ahc->scb_data, M_DEVBUF); 883 if (ahc->bus_data != NULL) 884 free(ahc->bus_data, M_DEVBUF); 885 return; 886 } 887 888 static int 889 ahcinitscbdata(struct ahc_softc *ahc) 890 { 891 struct scb_data *scb_data; 892 int i; 893 894 scb_data = ahc->scb_data; 895 SLIST_INIT(&scb_data->free_scbs); 896 SLIST_INIT(&scb_data->sg_maps); 897 898 /* Allocate SCB resources */ 899 scb_data->scbarray = 900 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 901 M_DEVBUF, M_NOWAIT); 902 if (scb_data->scbarray == NULL) 903 return (ENOMEM); 904 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 905 906 /* Determine the number of hardware SCBs and initialize them */ 907 908 scb_data->maxhscbs = ahc_probe_scbs(ahc); 909 /* SCB 0 heads the free list */ 910 ahc_outb(ahc, FREE_SCBH, 0); 911 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 912 ahc_outb(ahc, SCBPTR, i); 913 914 /* Clear the control byte. */ 915 ahc_outb(ahc, SCB_CONTROL, 0); 916 917 /* Set the next pointer */ 918 ahc_outb(ahc, SCB_NEXT, i+1); 919 920 /* Make the tag number invalid */ 921 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 922 } 923 924 /* Make sure that the last SCB terminates the free list */ 925 ahc_outb(ahc, SCBPTR, i-1); 926 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 927 928 /* Ensure we clear the 0 SCB's control byte. */ 929 ahc_outb(ahc, SCBPTR, 0); 930 ahc_outb(ahc, SCB_CONTROL, 0); 931 932 scb_data->maxhscbs = i; 933 934 if (ahc->scb_data->maxhscbs == 0) 935 panic("%s: No SCB space found", ahc_name(ahc)); 936 937 /* 938 * Create our DMA tags. These tags define the kinds of device 939 * accessable memory allocations and memory mappings we will 940 * need to perform during normal operation. 941 * 942 * Unless we need to further restrict the allocation, we rely 943 * on the restrictions of the parent dmat, hence the common 944 * use of MAXADDR and MAXSIZE. 945 */ 946 947 if (ahc_createdmamem(ahc->parent_dmat, 948 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 949 &scb_data->hscb_dmamap, 950 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 951 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 952 "hardware SCB structures") < 0) 953 goto error_exit; 954 955 scb_data->init_level++; 956 957 if (ahc_createdmamem(ahc->parent_dmat, 958 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 959 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 960 &scb_data->sense_busaddr, &scb_data->sense_seg, 961 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 962 goto error_exit; 963 964 scb_data->init_level++; 965 966 /* Perform initial CCB allocation */ 967 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 968 ahcallocscbs(ahc); 969 970 if (scb_data->numscbs == 0) { 971 printf("%s: ahc_init_scb_data - " 972 "Unable to allocate initial scbs\n", 973 ahc_name(ahc)); 974 goto error_exit; 975 } 976 977 scb_data->init_level++; 978 979 /* 980 * Note that we were successfull 981 */ 982 return 0; 983 984 error_exit: 985 986 return ENOMEM; 987 } 988 989 static void 990 ahcfiniscbdata(struct ahc_softc *ahc) 991 { 992 struct scb_data *scb_data; 993 994 scb_data = ahc->scb_data; 995 996 switch (scb_data->init_level) { 997 default: 998 case 3: 999 { 1000 struct sg_map_node *sg_map; 1001 1002 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1003 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1004 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1005 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1006 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1007 free(sg_map, M_DEVBUF); 1008 } 1009 } 1010 /*FALLTHROUGH*/ 1011 case 2: 1012 ahc_freedmamem(ahc->parent_dmat, 1013 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1014 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1015 &scb_data->sense_seg, scb_data->sense_nseg); 1016 /*FALLTHROUGH*/ 1017 case 1: 1018 ahc_freedmamem(ahc->parent_dmat, 1019 AHC_SCB_MAX * sizeof(struct hardware_scb), 1020 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1021 &scb_data->hscb_seg, scb_data->hscb_nseg); 1022 /*FALLTHROUGH*/ 1023 } 1024 if (scb_data->scbarray != NULL) 1025 free(scb_data->scbarray, M_DEVBUF); 1026 } 1027 1028 int 1029 ahc_reset(struct ahc_softc *ahc) 1030 { 1031 u_int sblkctl; 1032 int wait; 1033 1034 #ifdef AHC_DUMP_SEQ 1035 if (ahc->init_level == 0) 1036 ahc_dumpseq(ahc); 1037 #endif 1038 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1039 /* 1040 * Ensure that the reset has finished 1041 */ 1042 wait = 1000; 1043 do { 1044 DELAY(1000); 1045 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1046 1047 if (wait == 0) { 1048 printf("%s: WARNING - Failed chip reset! " 1049 "Trying to initialize anyway.\n", ahc_name(ahc)); 1050 } 1051 ahc_outb(ahc, HCNTRL, ahc->pause); 1052 1053 /* Determine channel configuration */ 1054 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1055 /* No Twin Channel PCI cards */ 1056 if ((ahc->chip & AHC_PCI) != 0) 1057 sblkctl &= ~SELBUSB; 1058 switch (sblkctl) { 1059 case 0: 1060 /* Single Narrow Channel */ 1061 break; 1062 case 2: 1063 /* Wide Channel */ 1064 ahc->features |= AHC_WIDE; 1065 break; 1066 case 8: 1067 /* Twin Channel */ 1068 ahc->features |= AHC_TWIN; 1069 break; 1070 default: 1071 printf(" Unsupported adapter type. Ignoring\n"); 1072 return(-1); 1073 } 1074 1075 return (0); 1076 } 1077 1078 /* 1079 * Called when we have an active connection to a target on the bus, 1080 * this function finds the nearest syncrate to the input period limited 1081 * by the capabilities of the bus connectivity of the target. 1082 */ 1083 static struct ahc_syncrate * 1084 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1085 u_int maxsync; 1086 1087 if ((ahc->features & AHC_ULTRA2) != 0) { 1088 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1089 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1090 maxsync = AHC_SYNCRATE_ULTRA2; 1091 } else { 1092 maxsync = AHC_SYNCRATE_ULTRA; 1093 } 1094 } else if ((ahc->features & AHC_ULTRA) != 0) { 1095 maxsync = AHC_SYNCRATE_ULTRA; 1096 } else { 1097 maxsync = AHC_SYNCRATE_FAST; 1098 } 1099 return (ahc_find_syncrate(ahc, period, maxsync)); 1100 } 1101 1102 /* 1103 * Look up the valid period to SCSIRATE conversion in our table. 1104 * Return the period and offset that should be sent to the target 1105 * if this was the beginning of an SDTR. 1106 */ 1107 static struct ahc_syncrate * 1108 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1109 { 1110 struct ahc_syncrate *syncrate; 1111 1112 syncrate = &ahc_syncrates[maxsync]; 1113 while ((syncrate->rate != NULL) 1114 && ((ahc->features & AHC_ULTRA2) == 0 1115 || (syncrate->sxfr_u2 != 0))) { 1116 1117 if (*period <= syncrate->period) { 1118 /* 1119 * When responding to a target that requests 1120 * sync, the requested rate may fall between 1121 * two rates that we can output, but still be 1122 * a rate that we can receive. Because of this, 1123 * we want to respond to the target with 1124 * the same rate that it sent to us even 1125 * if the period we use to send data to it 1126 * is lower. Only lower the response period 1127 * if we must. 1128 */ 1129 if (syncrate == &ahc_syncrates[maxsync]) 1130 *period = syncrate->period; 1131 break; 1132 } 1133 syncrate++; 1134 } 1135 1136 if ((*period == 0) 1137 || (syncrate->rate == NULL) 1138 || ((ahc->features & AHC_ULTRA2) != 0 1139 && (syncrate->sxfr_u2 == 0))) { 1140 /* Use asynchronous transfers. */ 1141 *period = 0; 1142 syncrate = NULL; 1143 } 1144 return (syncrate); 1145 } 1146 1147 static u_int 1148 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1149 { 1150 struct ahc_syncrate *syncrate; 1151 1152 if ((ahc->features & AHC_ULTRA2) != 0) 1153 scsirate &= SXFR_ULTRA2; 1154 else 1155 scsirate &= SXFR; 1156 1157 syncrate = &ahc_syncrates[maxsync]; 1158 while (syncrate->rate != NULL) { 1159 1160 if ((ahc->features & AHC_ULTRA2) != 0) { 1161 if (syncrate->sxfr_u2 == 0) 1162 break; 1163 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1164 return (syncrate->period); 1165 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1166 return (syncrate->period); 1167 } 1168 syncrate++; 1169 } 1170 return (0); /* async */ 1171 } 1172 1173 static void 1174 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1175 u_int *offset, int wide) 1176 { 1177 u_int maxoffset; 1178 1179 /* Limit offset to what we can do */ 1180 if (syncrate == NULL) { 1181 maxoffset = 0; 1182 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1183 maxoffset = MAX_OFFSET_ULTRA2; 1184 } else { 1185 if (wide) 1186 maxoffset = MAX_OFFSET_16BIT; 1187 else 1188 maxoffset = MAX_OFFSET_8BIT; 1189 } 1190 *offset = MIN(*offset, maxoffset); 1191 } 1192 1193 static void 1194 ahc_update_target_msg_request(struct ahc_softc *ahc, 1195 struct ahc_devinfo *devinfo, 1196 struct ahc_initiator_tinfo *tinfo, 1197 int force, int paused) 1198 { 1199 u_int targ_msg_req_orig; 1200 1201 targ_msg_req_orig = ahc->targ_msg_req; 1202 if (tinfo->current.period != tinfo->goal.period 1203 || tinfo->current.width != tinfo->goal.width 1204 || tinfo->current.offset != tinfo->goal.offset 1205 || (force 1206 && (tinfo->goal.period != 0 1207 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1208 ahc->targ_msg_req |= devinfo->target_mask; 1209 } else { 1210 ahc->targ_msg_req &= ~devinfo->target_mask; 1211 } 1212 1213 if (ahc->targ_msg_req != targ_msg_req_orig) { 1214 /* Update the message request bit for this target */ 1215 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1216 if (paused) { 1217 ahc_outb(ahc, TARGET_MSG_REQUEST, 1218 ahc->targ_msg_req & 0xFF); 1219 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1220 (ahc->targ_msg_req >> 8) & 0xFF); 1221 } else { 1222 ahc_outb(ahc, HS_MAILBOX, 1223 0x01 << HOST_MAILBOX_SHIFT); 1224 } 1225 } else { 1226 if (!paused) 1227 pause_sequencer(ahc); 1228 1229 ahc_outb(ahc, TARGET_MSG_REQUEST, 1230 ahc->targ_msg_req & 0xFF); 1231 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1232 (ahc->targ_msg_req >> 8) & 0xFF); 1233 1234 if (!paused) 1235 unpause_sequencer(ahc); 1236 } 1237 } 1238 } 1239 1240 static void 1241 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1242 struct ahc_syncrate *syncrate, 1243 u_int period, u_int offset, u_int type, int paused, int done) 1244 { 1245 struct ahc_initiator_tinfo *tinfo; 1246 struct tmode_tstate *tstate; 1247 u_int old_period; 1248 u_int old_offset; 1249 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1250 1251 if (syncrate == NULL) { 1252 period = 0; 1253 offset = 0; 1254 } 1255 1256 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1257 devinfo->target, &tstate); 1258 old_period = tinfo->current.period; 1259 old_offset = tinfo->current.offset; 1260 1261 if ((type & AHC_TRANS_CUR) != 0 1262 && (old_period != period || old_offset != offset)) { 1263 u_int scsirate; 1264 1265 scsirate = tinfo->scsirate; 1266 if ((ahc->features & AHC_ULTRA2) != 0) { 1267 1268 /* XXX */ 1269 /* Force single edge until DT is fully implemented */ 1270 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1271 if (syncrate != NULL) 1272 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1273 1274 if (active) 1275 ahc_outb(ahc, SCSIOFFSET, offset); 1276 } else { 1277 1278 scsirate &= ~(SXFR|SOFS); 1279 /* 1280 * Ensure Ultra mode is set properly for 1281 * this target. 1282 */ 1283 tstate->ultraenb &= ~devinfo->target_mask; 1284 if (syncrate != NULL) { 1285 if (syncrate->sxfr & ULTRA_SXFR) { 1286 tstate->ultraenb |= 1287 devinfo->target_mask; 1288 } 1289 scsirate |= syncrate->sxfr & SXFR; 1290 scsirate |= offset & SOFS; 1291 } 1292 if (active) { 1293 u_int sxfrctl0; 1294 1295 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1296 sxfrctl0 &= ~FAST20; 1297 if (tstate->ultraenb & devinfo->target_mask) 1298 sxfrctl0 |= FAST20; 1299 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1300 } 1301 } 1302 if (active) 1303 ahc_outb(ahc, SCSIRATE, scsirate); 1304 1305 tinfo->scsirate = scsirate; 1306 tinfo->current.period = period; 1307 tinfo->current.offset = offset; 1308 1309 /* Update the syncrates in any pending scbs */ 1310 ahc_update_pending_syncrates(ahc); 1311 } 1312 1313 /* 1314 * Print messages if we're verbose and at the end of a negotiation 1315 * cycle. 1316 */ 1317 if (done) { 1318 if (offset != 0) { 1319 printf("%s: target %d synchronous at %sMHz, " 1320 "offset = 0x%x\n", ahc_name(ahc), 1321 devinfo->target, syncrate->rate, offset); 1322 } else { 1323 printf("%s: target %d using " 1324 "asynchronous transfers\n", 1325 ahc_name(ahc), devinfo->target); 1326 } 1327 } 1328 1329 if ((type & AHC_TRANS_GOAL) != 0) { 1330 tinfo->goal.period = period; 1331 tinfo->goal.offset = offset; 1332 } 1333 1334 if ((type & AHC_TRANS_USER) != 0) { 1335 tinfo->user.period = period; 1336 tinfo->user.offset = offset; 1337 } 1338 1339 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1340 /*force*/FALSE, 1341 paused); 1342 } 1343 1344 static void 1345 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1346 u_int width, u_int type, int paused, int done) 1347 { 1348 struct ahc_initiator_tinfo *tinfo; 1349 struct tmode_tstate *tstate; 1350 u_int oldwidth; 1351 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1352 1353 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1354 devinfo->target, &tstate); 1355 oldwidth = tinfo->current.width; 1356 1357 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1358 u_int scsirate; 1359 1360 scsirate = tinfo->scsirate; 1361 scsirate &= ~WIDEXFER; 1362 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1363 scsirate |= WIDEXFER; 1364 1365 tinfo->scsirate = scsirate; 1366 1367 if (active) 1368 ahc_outb(ahc, SCSIRATE, scsirate); 1369 1370 tinfo->current.width = width; 1371 } 1372 1373 if (done) { 1374 printf("%s: target %d using %dbit transfers\n", 1375 ahc_name(ahc), devinfo->target, 1376 8 * (0x01 << width)); 1377 } 1378 1379 if ((type & AHC_TRANS_GOAL) != 0) 1380 tinfo->goal.width = width; 1381 if ((type & AHC_TRANS_USER) != 0) 1382 tinfo->user.width = width; 1383 1384 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1385 /*force*/FALSE, paused); 1386 } 1387 1388 static void 1389 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1390 { 1391 struct ahc_initiator_tinfo *tinfo; 1392 struct tmode_tstate *tstate; 1393 1394 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1395 devinfo->target, &tstate); 1396 1397 if (enable) 1398 tstate->tagenable |= devinfo->target_mask; 1399 else { 1400 tstate->tagenable &= ~devinfo->target_mask; 1401 tstate->tagdisable |= devinfo->target_mask; 1402 } 1403 } 1404 1405 /* 1406 * Attach all the sub-devices we can find 1407 */ 1408 int 1409 ahc_attach(struct ahc_softc *ahc) 1410 { 1411 TAILQ_INIT(&ahc->sc_q); 1412 1413 ahc->sc_adapter.scsipi_cmd = ahc_action; 1414 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1415 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1416 ahc->sc_link.type = BUS_SCSI; 1417 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1418 ahc->sc_link.scsipi_scsi.channel = 0; 1419 ahc->sc_link.scsipi_scsi.max_target = 1420 (ahc->features & AHC_WIDE) ? 15 : 7; 1421 ahc->sc_link.scsipi_scsi.max_lun = 7; 1422 ahc->sc_link.adapter_softc = ahc; 1423 ahc->sc_link.adapter = &ahc->sc_adapter; 1424 ahc->sc_link.openings = 2; 1425 ahc->sc_link.device = &ahc_dev; 1426 1427 if (ahc->features & AHC_TWIN) { 1428 ahc->sc_link_b = ahc->sc_link; 1429 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1430 ahc->sc_link_b.scsipi_scsi.channel = 1; 1431 } 1432 1433 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1434 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1435 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1436 if (ahc->features & AHC_TWIN) 1437 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1438 } else { 1439 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1440 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1441 } 1442 return 1; 1443 } 1444 1445 static void 1446 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1447 { 1448 u_int saved_tcl; 1449 role_t role; 1450 int our_id; 1451 1452 if (ahc_inb(ahc, SSTAT0) & TARGET) 1453 role = ROLE_TARGET; 1454 else 1455 role = ROLE_INITIATOR; 1456 1457 if (role == ROLE_TARGET 1458 && (ahc->features & AHC_MULTI_TID) != 0 1459 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1460 /* We were selected, so pull our id from TARGIDIN */ 1461 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1462 } else if ((ahc->features & AHC_ULTRA2) != 0) 1463 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1464 else 1465 our_id = ahc_inb(ahc, SCSIID) & OID; 1466 1467 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1468 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1469 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1470 role); 1471 } 1472 1473 static void 1474 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1475 u_int lun, char channel, role_t role) 1476 { 1477 devinfo->our_scsiid = our_id; 1478 devinfo->target = target; 1479 devinfo->lun = lun; 1480 devinfo->target_offset = target; 1481 devinfo->channel = channel; 1482 devinfo->role = role; 1483 if (channel == 'B') 1484 devinfo->target_offset += 8; 1485 devinfo->target_mask = (0x01 << devinfo->target_offset); 1486 } 1487 1488 /* 1489 * Catch an interrupt from the adapter 1490 */ 1491 int 1492 ahc_intr(void *arg) 1493 { 1494 struct ahc_softc *ahc; 1495 u_int intstat; 1496 1497 ahc = (struct ahc_softc *)arg; 1498 1499 intstat = ahc_inb(ahc, INTSTAT); 1500 1501 /* 1502 * Any interrupts to process? 1503 */ 1504 if ((intstat & INT_PEND) == 0) { 1505 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1506 #ifdef AHC_DEBUG 1507 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1508 ahc_name(ahc), 1509 ahc_inb(ahc, CCHADDR) | 1510 (ahc_inb(ahc, CCHADDR+1) << 8) 1511 | (ahc_inb(ahc, CCHADDR+2) << 16) 1512 | (ahc_inb(ahc, CCHADDR+3) << 24), 1513 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1514 | (ahc_inb(ahc, HADDR+2) << 16) 1515 | (ahc_inb(ahc, HADDR+3) << 24), 1516 ahc_inb(ahc, SEQADDR0) | 1517 (ahc_inb(ahc, SEQADDR1) << 8)); 1518 #endif 1519 return 1; 1520 } 1521 return 0; 1522 } 1523 1524 #ifdef AHC_DEBUG 1525 if (ahc_debug & AHC_SHOWINTR) { 1526 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1527 } 1528 #endif 1529 1530 if (intstat & CMDCMPLT) { 1531 ahc_outb(ahc, CLRINT, CLRCMDINT); 1532 ahc_run_qoutfifo(ahc); 1533 } 1534 if (intstat & BRKADRINT) { 1535 /* 1536 * We upset the sequencer :-( 1537 * Lookup the error message 1538 */ 1539 int i, error, num_errors; 1540 1541 error = ahc_inb(ahc, ERROR); 1542 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1543 for (i = 0; error != 1 && i < num_errors; i++) 1544 error >>= 1; 1545 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1546 ahc_name(ahc), hard_error[i].errmesg, 1547 ahc_inb(ahc, SEQADDR0) | 1548 (ahc_inb(ahc, SEQADDR1) << 8)); 1549 1550 /* Tell everyone that this HBA is no longer availible */ 1551 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1552 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1553 XS_DRIVER_STUFFUP); 1554 } 1555 if (intstat & SEQINT) 1556 ahc_handle_seqint(ahc, intstat); 1557 1558 if (intstat & SCSIINT) 1559 ahc_handle_scsiint(ahc, intstat); 1560 1561 return 1; 1562 } 1563 1564 static struct tmode_tstate * 1565 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1566 { 1567 struct tmode_tstate *master_tstate; 1568 struct tmode_tstate *tstate; 1569 int i, s; 1570 1571 master_tstate = ahc->enabled_targets[ahc->our_id]; 1572 if (channel == 'B') { 1573 scsi_id += 8; 1574 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1575 } 1576 if (ahc->enabled_targets[scsi_id] != NULL 1577 && ahc->enabled_targets[scsi_id] != master_tstate) 1578 panic("%s: ahc_alloc_tstate - Target already allocated", 1579 ahc_name(ahc)); 1580 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1581 if (tstate == NULL) 1582 return (NULL); 1583 1584 /* 1585 * If we have allocated a master tstate, copy user settings from 1586 * the master tstate (taken from SRAM or the EEPROM) for this 1587 * channel, but reset our current and goal settings to async/narrow 1588 * until an initiator talks to us. 1589 */ 1590 if (master_tstate != NULL) { 1591 bcopy(master_tstate, tstate, sizeof(*tstate)); 1592 tstate->ultraenb = 0; 1593 for (i = 0; i < 16; i++) { 1594 bzero(&tstate->transinfo[i].current, 1595 sizeof(tstate->transinfo[i].current)); 1596 bzero(&tstate->transinfo[i].goal, 1597 sizeof(tstate->transinfo[i].goal)); 1598 } 1599 } else 1600 bzero(tstate, sizeof(*tstate)); 1601 s = splbio(); 1602 ahc->enabled_targets[scsi_id] = tstate; 1603 splx(s); 1604 return (tstate); 1605 } 1606 1607 #if UNUSED 1608 static void 1609 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1610 { 1611 struct tmode_tstate *tstate; 1612 1613 /* Don't clean up the entry for our initiator role */ 1614 if ((ahc->flags & AHC_INITIATORMODE) != 0 1615 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1616 || (channel == 'A' && scsi_id == ahc->our_id)) 1617 && force == FALSE) 1618 return; 1619 1620 if (channel == 'B') 1621 scsi_id += 8; 1622 tstate = ahc->enabled_targets[scsi_id]; 1623 if (tstate != NULL) 1624 free(tstate, M_DEVBUF); 1625 ahc->enabled_targets[scsi_id] = NULL; 1626 } 1627 #endif 1628 1629 static void 1630 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1631 { 1632 struct scb *scb; 1633 struct ahc_devinfo devinfo; 1634 1635 ahc_fetch_devinfo(ahc, &devinfo); 1636 1637 /* 1638 * Clear the upper byte that holds SEQINT status 1639 * codes and clear the SEQINT bit. We will unpause 1640 * the sequencer, if appropriate, after servicing 1641 * the request. 1642 */ 1643 ahc_outb(ahc, CLRINT, CLRSEQINT); 1644 switch (intstat & SEQINT_MASK) { 1645 case NO_MATCH: 1646 { 1647 /* Ensure we don't leave the selection hardware on */ 1648 ahc_outb(ahc, SCSISEQ, 1649 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1650 1651 printf("%s:%c:%d: no active SCB for reconnecting " 1652 "target - issuing BUS DEVICE RESET\n", 1653 ahc_name(ahc), devinfo.channel, devinfo.target); 1654 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1655 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1656 ahc_inb(ahc, SEQ_FLAGS)); 1657 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1658 ahc->msgout_len = 1; 1659 ahc->msgout_index = 0; 1660 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1661 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1662 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1663 break; 1664 } 1665 case UPDATE_TMSG_REQ: 1666 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1667 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1668 (ahc->targ_msg_req >> 8) & 0xFF); 1669 ahc_outb(ahc, HS_MAILBOX, 0); 1670 break; 1671 case SEND_REJECT: 1672 { 1673 u_int rejbyte = ahc_inb(ahc, ACCUM); 1674 printf("%s:%c:%d: Warning - unknown message received from " 1675 "target (0x%x). Rejecting\n", 1676 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1677 break; 1678 } 1679 case NO_IDENT: 1680 { 1681 /* 1682 * The reconnecting target either did not send an identify 1683 * message, or did, but we didn't find and SCB to match and 1684 * before it could respond to our ATN/abort, it hit a dataphase. 1685 * The only safe thing to do is to blow it away with a bus 1686 * reset. 1687 */ 1688 int found; 1689 1690 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1691 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1692 ahc_name(ahc), devinfo.channel, devinfo.target, 1693 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1694 found = ahc_reset_channel(ahc, devinfo.channel, 1695 /*initiate reset*/TRUE); 1696 printf("%s: Issued Channel %c Bus Reset. " 1697 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1698 found); 1699 return; 1700 } 1701 case BAD_PHASE: 1702 { 1703 u_int lastphase; 1704 1705 lastphase = ahc_inb(ahc, LASTPHASE); 1706 if (lastphase == P_BUSFREE) { 1707 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1708 ahc_name(ahc), devinfo.channel, devinfo.target, 1709 ahc_inb(ahc, SCSISIGI)); 1710 restart_sequencer(ahc); 1711 return; 1712 } else { 1713 printf("%s:%c:%d: unknown scsi bus phase %x. " 1714 "Attempting to continue\n", 1715 ahc_name(ahc), devinfo.channel, devinfo.target, 1716 ahc_inb(ahc, SCSISIGI)); 1717 } 1718 break; 1719 } 1720 case BAD_STATUS: 1721 { 1722 u_int scb_index; 1723 struct hardware_scb *hscb; 1724 struct scsipi_xfer *xs; 1725 /* 1726 * The sequencer will notify us when a command 1727 * has an error that would be of interest to 1728 * the kernel. This allows us to leave the sequencer 1729 * running in the common case of command completes 1730 * without error. The sequencer will already have 1731 * dma'd the SCB back up to us, so we can reference 1732 * the in kernel copy directly. 1733 */ 1734 scb_index = ahc_inb(ahc, SCB_TAG); 1735 scb = &ahc->scb_data->scbarray[scb_index]; 1736 1737 /* ahc_print_scb(scb); */ 1738 1739 /* 1740 * Set the default return value to 0 (don't 1741 * send sense). The sense code will change 1742 * this if needed. 1743 */ 1744 ahc_outb(ahc, RETURN_1, 0); 1745 if (!(scb_index < ahc->scb_data->numscbs 1746 && (scb->flags & SCB_ACTIVE) != 0)) { 1747 printf("%s:%c:%d: ahc_intr - referenced scb " 1748 "not valid during seqint 0x%x scb(%d)\n", 1749 ahc_name(ahc), devinfo.channel, 1750 devinfo.target, intstat, scb_index); 1751 goto unpause; 1752 } 1753 1754 hscb = scb->hscb; 1755 xs = scb->xs; 1756 1757 /* Don't want to clobber the original sense code */ 1758 if ((scb->flags & SCB_SENSE) != 0) { 1759 /* 1760 * Clear the SCB_SENSE Flag and have 1761 * the sequencer do a normal command 1762 * complete. 1763 */ 1764 scb->flags &= ~SCB_SENSE; 1765 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1766 break; 1767 } 1768 /* Freeze the queue unit the client sees the error. */ 1769 ahc_freeze_devq(ahc, xs->sc_link); 1770 ahc_freeze_ccb(scb); 1771 xs->status = hscb->status; 1772 switch (hscb->status) { 1773 case SCSI_STATUS_OK: 1774 printf("%s: Interrupted for status of 0???\n", 1775 ahc_name(ahc)); 1776 break; 1777 case SCSI_STATUS_CMD_TERMINATED: 1778 case SCSI_STATUS_CHECK_COND: 1779 #if defined(AHC_DEBUG) 1780 if (ahc_debug & AHC_SHOWSENSE) { 1781 scsi_print_addr(xs->sc_link); 1782 printf("Check Status, resid %d datalen %d\n", 1783 xs->resid, xs->datalen); 1784 } 1785 #endif 1786 1787 if (xs->error == XS_NOERROR && 1788 !(scb->flags & SCB_SENSE)) { 1789 struct ahc_dma_seg *sg; 1790 struct scsipi_sense *sc; 1791 struct ahc_initiator_tinfo *tinfo; 1792 struct tmode_tstate *tstate; 1793 1794 sg = scb->sg_list; 1795 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1796 /* 1797 * Save off the residual if there is one. 1798 */ 1799 if (hscb->residual_SG_count != 0) 1800 ahc_calc_residual(scb); 1801 else 1802 xs->resid = 0; 1803 1804 #ifdef AHC_DEBUG 1805 if (ahc_debug & AHC_SHOWSENSE) { 1806 scsi_print_addr(xs->sc_link); 1807 printf("Sending Sense\n"); 1808 } 1809 #endif 1810 sg->addr = ahc->scb_data->sense_busaddr + 1811 (hscb->tag*sizeof(struct scsipi_sense_data)); 1812 sg->len = sizeof (struct scsipi_sense_data); 1813 1814 sc->opcode = REQUEST_SENSE; 1815 sc->byte2 = SCB_LUN(scb) << 5; 1816 sc->unused[0] = 0; 1817 sc->unused[1] = 0; 1818 sc->length = sg->len; 1819 sc->control = 0; 1820 1821 /* 1822 * Would be nice to preserve DISCENB here, 1823 * but due to the way we page SCBs, we can't. 1824 */ 1825 hscb->control = 0; 1826 1827 /* 1828 * This request sense could be because the 1829 * the device lost power or in some other 1830 * way has lost our transfer negotiations. 1831 * Renegotiate if appropriate. Unit attention 1832 * errors will be reported before any data 1833 * phases occur. 1834 */ 1835 ahc_calc_residual(scb); 1836 #if defined(AHC_DEBUG) 1837 if (ahc_debug & AHC_SHOWSENSE) { 1838 scsi_print_addr(xs->sc_link); 1839 printf("Sense: datalen %d resid %d" 1840 "chan %d id %d targ %d\n", 1841 xs->datalen, xs->resid, 1842 devinfo.channel, devinfo.our_scsiid, 1843 devinfo.target); 1844 } 1845 #endif 1846 if (xs->datalen > 0 && 1847 xs->resid == xs->datalen) { 1848 tinfo = ahc_fetch_transinfo(ahc, 1849 devinfo.channel, 1850 devinfo.our_scsiid, 1851 devinfo.target, 1852 &tstate); 1853 ahc_update_target_msg_request(ahc, 1854 &devinfo, 1855 tinfo, 1856 /*force*/TRUE, 1857 /*paused*/TRUE); 1858 } 1859 hscb->status = 0; 1860 hscb->SG_count = 1; 1861 hscb->SG_pointer = scb->sg_list_phys; 1862 hscb->data = sg->addr; 1863 hscb->datalen = sg->len; 1864 hscb->cmdpointer = hscb->cmdstore_busaddr; 1865 hscb->cmdlen = sizeof(*sc); 1866 scb->sg_count = hscb->SG_count; 1867 ahc_swap_hscb(hscb); 1868 ahc_swap_sg(scb->sg_list); 1869 scb->flags |= SCB_SENSE; 1870 /* 1871 * Ensure the target is busy since this 1872 * will be an untagged request. 1873 */ 1874 ahc_busy_tcl(ahc, scb); 1875 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1876 1877 /* 1878 * Ensure we have enough time to actually 1879 * retrieve the sense. 1880 */ 1881 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1882 callout_reset(&scb->xs->xs_callout, 1883 5 * hz, ahc_timeout, scb); 1884 } 1885 } 1886 break; 1887 case SCSI_STATUS_QUEUE_FULL: 1888 scsi_print_addr(xs->sc_link); 1889 printf("queue full\n"); 1890 case SCSI_STATUS_BUSY: 1891 /* 1892 * XXX middle layer doesn't handle XS_BUSY well. 1893 * So, requeue this ourselves internally. 1894 */ 1895 xs->error = XS_BUSY; 1896 scb->flags |= SCB_REQUEUE; 1897 break; 1898 } 1899 break; 1900 } 1901 case TRACE_POINT: 1902 { 1903 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1904 ahc_inb(ahc, DFCNTRL)); 1905 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1906 ahc_inb(ahc, DFSTATUS)); 1907 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1908 ahc_inb(ahc, SSTAT0), 1909 ahc_inb(ahc, SCB_DATACNT)); 1910 break; 1911 } 1912 case HOST_MSG_LOOP: 1913 { 1914 /* 1915 * The sequencer has encountered a message phase 1916 * that requires host assistance for completion. 1917 * While handling the message phase(s), we will be 1918 * notified by the sequencer after each byte is 1919 * transfered so we can track bus phases. 1920 * 1921 * If this is the first time we've seen a HOST_MSG_LOOP, 1922 * initialize the state of the host message loop. 1923 */ 1924 if (ahc->msg_type == MSG_TYPE_NONE) { 1925 u_int bus_phase; 1926 1927 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1928 if (bus_phase != P_MESGIN 1929 && bus_phase != P_MESGOUT) { 1930 printf("ahc_intr: HOST_MSG_LOOP bad " 1931 "phase 0x%x\n", 1932 bus_phase); 1933 /* 1934 * Probably transitioned to bus free before 1935 * we got here. Just punt the message. 1936 */ 1937 ahc_clear_intstat(ahc); 1938 restart_sequencer(ahc); 1939 } 1940 1941 if (devinfo.role == ROLE_INITIATOR) { 1942 struct scb *scb; 1943 u_int scb_index; 1944 1945 scb_index = ahc_inb(ahc, SCB_TAG); 1946 scb = &ahc->scb_data->scbarray[scb_index]; 1947 1948 if (bus_phase == P_MESGOUT) 1949 ahc_setup_initiator_msgout(ahc, 1950 &devinfo, 1951 scb); 1952 else { 1953 ahc->msg_type = 1954 MSG_TYPE_INITIATOR_MSGIN; 1955 ahc->msgin_index = 0; 1956 } 1957 } else { 1958 if (bus_phase == P_MESGOUT) { 1959 ahc->msg_type = 1960 MSG_TYPE_TARGET_MSGOUT; 1961 ahc->msgin_index = 0; 1962 } else 1963 /* XXX Ever executed??? */ 1964 ahc_setup_target_msgin(ahc, &devinfo); 1965 } 1966 } 1967 1968 /* Pass a NULL path so that handlers generate their own */ 1969 ahc_handle_message_phase(ahc, /*path*/NULL); 1970 break; 1971 } 1972 case PERR_DETECTED: 1973 { 1974 /* 1975 * If we've cleared the parity error interrupt 1976 * but the sequencer still believes that SCSIPERR 1977 * is true, it must be that the parity error is 1978 * for the currently presented byte on the bus, 1979 * and we are not in a phase (data-in) where we will 1980 * eventually ack this byte. Ack the byte and 1981 * throw it away in the hope that the target will 1982 * take us to message out to deliver the appropriate 1983 * error message. 1984 */ 1985 if ((intstat & SCSIINT) == 0 1986 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1987 u_int curphase; 1988 1989 /* 1990 * The hardware will only let you ack bytes 1991 * if the expected phase in SCSISIGO matches 1992 * the current phase. Make sure this is 1993 * currently the case. 1994 */ 1995 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1996 ahc_outb(ahc, LASTPHASE, curphase); 1997 ahc_outb(ahc, SCSISIGO, curphase); 1998 ahc_inb(ahc, SCSIDATL); 1999 } 2000 break; 2001 } 2002 case DATA_OVERRUN: 2003 { 2004 /* 2005 * When the sequencer detects an overrun, it 2006 * places the controller in "BITBUCKET" mode 2007 * and allows the target to complete its transfer. 2008 * Unfortunately, none of the counters get updated 2009 * when the controller is in this mode, so we have 2010 * no way of knowing how large the overrun was. 2011 */ 2012 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2013 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2014 int i; 2015 2016 scb = &ahc->scb_data->scbarray[scbindex]; 2017 for (i = 0; i < num_phases; i++) { 2018 if (lastphase == phase_table[i].phase) 2019 break; 2020 } 2021 scsi_print_addr(scb->xs->sc_link); 2022 printf("data overrun detected %s." 2023 " Tag == 0x%x.\n", 2024 phase_table[i].phasemsg, 2025 scb->hscb->tag); 2026 scsi_print_addr(scb->xs->sc_link); 2027 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2028 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2029 scb->xs->datalen, scb->sg_count); 2030 if (scb->sg_count > 0) { 2031 for (i = 0; i < scb->sg_count; i++) { 2032 printf("sg[%d] - Addr 0x%x : Length %d\n", 2033 i, 2034 le32toh(scb->sg_list[i].addr), 2035 le32toh(scb->sg_list[i].len)); 2036 } 2037 } 2038 /* 2039 * Set this and it will take affect when the 2040 * target does a command complete. 2041 */ 2042 ahc_freeze_devq(ahc, scb->xs->sc_link); 2043 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2044 ahc_freeze_ccb(scb); 2045 break; 2046 } 2047 case TRACEPOINT: 2048 { 2049 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2050 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2051 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2052 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2053 printf("TRACEPOINT: CCHADDR = %x\n", 2054 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2055 | (ahc_inb(ahc, CCHADDR+2) << 16) 2056 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2057 #if 0 2058 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2059 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2060 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2061 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2062 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2063 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2064 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2065 ahc_inb(ahc, CCHADDR) 2066 | (ahc_inb(ahc, CCHADDR+1) << 8) 2067 | (ahc_inb(ahc, CCHADDR+2) << 16) 2068 | (ahc_inb(ahc, CCHADDR+3) << 24), 2069 ahc_inb(ahc, CCHCNT) 2070 | (ahc_inb(ahc, CCHCNT+1) << 8) 2071 | (ahc_inb(ahc, CCHCNT+2) << 16), 2072 ahc_inb(ahc, SCBPTR)); 2073 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2074 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2075 #if DDB > 0 2076 cpu_Debugger(); 2077 #endif 2078 #endif 2079 break; 2080 } 2081 #if NOT_YET 2082 /* XXX Fill these in later */ 2083 case MESG_BUFFER_BUSY: 2084 break; 2085 case MSGIN_PHASEMIS: 2086 break; 2087 #endif 2088 default: 2089 printf("ahc_intr: seqint, " 2090 "intstat == 0x%x, scsisigi = 0x%x\n", 2091 intstat, ahc_inb(ahc, SCSISIGI)); 2092 break; 2093 } 2094 2095 unpause: 2096 /* 2097 * The sequencer is paused immediately on 2098 * a SEQINT, so we should restart it when 2099 * we're done. 2100 */ 2101 unpause_sequencer(ahc); 2102 } 2103 2104 static void 2105 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2106 { 2107 u_int scb_index; 2108 u_int status; 2109 struct scb *scb; 2110 char cur_channel; 2111 char intr_channel; 2112 2113 if ((ahc->features & AHC_TWIN) != 0 2114 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2115 cur_channel = 'B'; 2116 else 2117 cur_channel = 'A'; 2118 intr_channel = cur_channel; 2119 2120 status = ahc_inb(ahc, SSTAT1); 2121 if (status == 0) { 2122 if ((ahc->features & AHC_TWIN) != 0) { 2123 /* Try the other channel */ 2124 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2125 status = ahc_inb(ahc, SSTAT1); 2126 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2127 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2128 } 2129 if (status == 0) { 2130 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2131 return; 2132 } 2133 } 2134 2135 scb_index = ahc_inb(ahc, SCB_TAG); 2136 if (scb_index < ahc->scb_data->numscbs) { 2137 scb = &ahc->scb_data->scbarray[scb_index]; 2138 if ((scb->flags & SCB_ACTIVE) == 0 2139 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2140 scb = NULL; 2141 } else 2142 scb = NULL; 2143 2144 if ((status & SCSIRSTI) != 0) { 2145 printf("%s: Someone reset channel %c\n", 2146 ahc_name(ahc), intr_channel); 2147 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2148 } else if ((status & SCSIPERR) != 0) { 2149 /* 2150 * Determine the bus phase and queue an appropriate message. 2151 * SCSIPERR is latched true as soon as a parity error 2152 * occurs. If the sequencer acked the transfer that 2153 * caused the parity error and the currently presented 2154 * transfer on the bus has correct parity, SCSIPERR will 2155 * be cleared by CLRSCSIPERR. Use this to determine if 2156 * we should look at the last phase the sequencer recorded, 2157 * or the current phase presented on the bus. 2158 */ 2159 u_int mesg_out; 2160 u_int curphase; 2161 u_int errorphase; 2162 u_int lastphase; 2163 int i; 2164 2165 lastphase = ahc_inb(ahc, LASTPHASE); 2166 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2167 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2168 /* 2169 * For all phases save DATA, the sequencer won't 2170 * automatically ack a byte that has a parity error 2171 * in it. So the only way that the current phase 2172 * could be 'data-in' is if the parity error is for 2173 * an already acked byte in the data phase. During 2174 * synchronous data-in transfers, we may actually 2175 * ack bytes before latching the current phase in 2176 * LASTPHASE, leading to the discrepancy between 2177 * curphase and lastphase. 2178 */ 2179 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2180 || curphase == P_DATAIN) 2181 errorphase = curphase; 2182 else 2183 errorphase = lastphase; 2184 2185 for (i = 0; i < num_phases; i++) { 2186 if (errorphase == phase_table[i].phase) 2187 break; 2188 } 2189 mesg_out = phase_table[i].mesg_out; 2190 if (scb != NULL) 2191 scsi_print_addr(scb->xs->sc_link); 2192 else 2193 printf("%s:%c:%d: ", ahc_name(ahc), 2194 intr_channel, 2195 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2196 2197 printf("parity error detected %s. " 2198 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2199 phase_table[i].phasemsg, 2200 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2201 ahc_inb(ahc, SCSIRATE)); 2202 2203 /* 2204 * We've set the hardware to assert ATN if we 2205 * get a parity error on "in" phases, so all we 2206 * need to do is stuff the message buffer with 2207 * the appropriate message. "In" phases have set 2208 * mesg_out to something other than MSG_NOP. 2209 */ 2210 if (mesg_out != MSG_NOOP) { 2211 if (ahc->msg_type != MSG_TYPE_NONE) 2212 ahc->send_msg_perror = TRUE; 2213 else 2214 ahc_outb(ahc, MSG_OUT, mesg_out); 2215 } 2216 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2217 unpause_sequencer(ahc); 2218 } else if ((status & BUSFREE) != 0 2219 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2220 /* 2221 * First look at what phase we were last in. 2222 * If its message out, chances are pretty good 2223 * that the busfree was in response to one of 2224 * our abort requests. 2225 */ 2226 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2227 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2228 u_int target = TCL_TARGET(saved_tcl); 2229 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2230 char channel = TCL_CHANNEL(ahc, saved_tcl); 2231 int printerror = 1; 2232 2233 ahc_outb(ahc, SCSISEQ, 2234 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2235 if (lastphase == P_MESGOUT) { 2236 u_int message; 2237 u_int tag; 2238 2239 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2240 tag = SCB_LIST_NULL; 2241 switch (message) { 2242 case MSG_ABORT_TAG: 2243 tag = scb->hscb->tag; 2244 /* FALLTRHOUGH */ 2245 case MSG_ABORT: 2246 scsi_print_addr(scb->xs->sc_link); 2247 printf("SCB %x - Abort %s Completed.\n", 2248 scb->hscb->tag, tag == SCB_LIST_NULL ? 2249 "" : "Tag"); 2250 ahc_abort_scbs(ahc, target, channel, 2251 TCL_LUN(saved_tcl), tag, 2252 ROLE_INITIATOR, 2253 XS_DRIVER_STUFFUP); 2254 printerror = 0; 2255 break; 2256 case MSG_BUS_DEV_RESET: 2257 { 2258 struct ahc_devinfo devinfo; 2259 2260 if (scb != NULL && 2261 (scb->xs->xs_control & XS_CTL_RESET) 2262 && ahc_match_scb(scb, target, channel, 2263 TCL_LUN(saved_tcl), 2264 SCB_LIST_NULL, 2265 ROLE_INITIATOR)) { 2266 ahcsetccbstatus(scb->xs, XS_NOERROR); 2267 } 2268 ahc_compile_devinfo(&devinfo, 2269 initiator_role_id, 2270 target, 2271 TCL_LUN(saved_tcl), 2272 channel, 2273 ROLE_INITIATOR); 2274 ahc_handle_devreset(ahc, &devinfo, 2275 XS_RESET, 2276 "Bus Device Reset", 2277 /*verbose_level*/0); 2278 printerror = 0; 2279 break; 2280 } 2281 default: 2282 break; 2283 } 2284 } 2285 if (printerror != 0) { 2286 int i; 2287 2288 if (scb != NULL) { 2289 u_int tag; 2290 2291 if ((scb->hscb->control & TAG_ENB) != 0) 2292 tag = scb->hscb->tag; 2293 else 2294 tag = SCB_LIST_NULL; 2295 ahc_abort_scbs(ahc, target, channel, 2296 SCB_LUN(scb), tag, 2297 ROLE_INITIATOR, 2298 XS_DRIVER_STUFFUP); 2299 scsi_print_addr(scb->xs->sc_link); 2300 } else { 2301 /* 2302 * We had not fully identified this connection, 2303 * so we cannot abort anything. 2304 */ 2305 printf("%s: ", ahc_name(ahc)); 2306 } 2307 for (i = 0; i < num_phases; i++) { 2308 if (lastphase == phase_table[i].phase) 2309 break; 2310 } 2311 printf("Unexpected busfree %s\n" 2312 "SEQADDR == 0x%x\n", 2313 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2314 | (ahc_inb(ahc, SEQADDR1) << 8)); 2315 } 2316 ahc_clear_msg_state(ahc); 2317 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2318 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2319 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2320 restart_sequencer(ahc); 2321 } else if ((status & SELTO) != 0) { 2322 u_int scbptr; 2323 2324 scbptr = ahc_inb(ahc, WAITING_SCBH); 2325 ahc_outb(ahc, SCBPTR, scbptr); 2326 scb_index = ahc_inb(ahc, SCB_TAG); 2327 2328 if (scb_index < ahc->scb_data->numscbs) { 2329 scb = &ahc->scb_data->scbarray[scb_index]; 2330 if ((scb->flags & SCB_ACTIVE) == 0) 2331 scb = NULL; 2332 } else 2333 scb = NULL; 2334 2335 if (scb == NULL) { 2336 printf("%s: ahc_intr - referenced scb not " 2337 "valid during SELTO scb(%d, %d)\n", 2338 ahc_name(ahc), scbptr, scb_index); 2339 } else { 2340 u_int tag; 2341 2342 tag = SCB_LIST_NULL; 2343 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2344 tag = scb->hscb->tag; 2345 2346 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2347 SCB_LUN(scb), tag, 2348 ROLE_INITIATOR, XS_SELTIMEOUT); 2349 } 2350 /* Stop the selection */ 2351 ahc_outb(ahc, SCSISEQ, 0); 2352 2353 /* No more pending messages */ 2354 ahc_clear_msg_state(ahc); 2355 2356 /* 2357 * Although the driver does not care about the 2358 * 'Selection in Progress' status bit, the busy 2359 * LED does. SELINGO is only cleared by a sucessful 2360 * selection, so we must manually clear it to ensure 2361 * the LED turns off just incase no future successful 2362 * selections occur (e.g. no devices on the bus). 2363 */ 2364 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2365 2366 /* Clear interrupt state */ 2367 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2368 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2369 restart_sequencer(ahc); 2370 } else { 2371 scsi_print_addr(scb->xs->sc_link); 2372 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2373 ahc_outb(ahc, CLRSINT1, status); 2374 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2375 unpause_sequencer(ahc); 2376 } 2377 } 2378 2379 static void 2380 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2381 { 2382 /* 2383 * We need to initiate transfer negotiations. 2384 * If our current and goal settings are identical, 2385 * we want to renegotiate due to a check condition. 2386 */ 2387 struct ahc_initiator_tinfo *tinfo; 2388 struct tmode_tstate *tstate; 2389 int dowide; 2390 int dosync; 2391 2392 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2393 devinfo->target, &tstate); 2394 dowide = tinfo->current.width != tinfo->goal.width; 2395 dosync = tinfo->current.period != tinfo->goal.period; 2396 2397 if (!dowide && !dosync) { 2398 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2399 dosync = tinfo->goal.period != 0; 2400 } 2401 2402 if (dowide) { 2403 ahc_construct_wdtr(ahc, tinfo->goal.width); 2404 } else if (dosync) { 2405 struct ahc_syncrate *rate; 2406 u_int period; 2407 u_int offset; 2408 2409 period = tinfo->goal.period; 2410 rate = ahc_devlimited_syncrate(ahc, &period); 2411 offset = tinfo->goal.offset; 2412 ahc_validate_offset(ahc, rate, &offset, 2413 tinfo->current.width); 2414 ahc_construct_sdtr(ahc, period, offset); 2415 } else { 2416 panic("ahc_intr: AWAITING_MSG for negotiation, " 2417 "but no negotiation needed\n"); 2418 } 2419 } 2420 2421 static void 2422 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2423 struct scb *scb) 2424 { 2425 /* 2426 * To facilitate adding multiple messages together, 2427 * each routine should increment the index and len 2428 * variables instead of setting them explicitly. 2429 */ 2430 ahc->msgout_index = 0; 2431 ahc->msgout_len = 0; 2432 2433 if ((scb->flags & SCB_DEVICE_RESET) == 0 2434 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2435 u_int identify_msg; 2436 2437 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2438 if ((scb->hscb->control & DISCENB) != 0) 2439 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2440 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2441 ahc->msgout_len++; 2442 2443 if ((scb->hscb->control & TAG_ENB) != 0) { 2444 /* XXX fvdl FreeBSD has tag action passed down */ 2445 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2446 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2447 ahc->msgout_len += 2; 2448 } 2449 } 2450 2451 if (scb->flags & SCB_DEVICE_RESET) { 2452 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2453 ahc->msgout_len++; 2454 scsi_print_addr(scb->xs->sc_link); 2455 printf("Bus Device Reset Message Sent\n"); 2456 } else if (scb->flags & SCB_ABORT) { 2457 if ((scb->hscb->control & TAG_ENB) != 0) 2458 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2459 else 2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2461 ahc->msgout_len++; 2462 scsi_print_addr(scb->xs->sc_link); 2463 printf("Abort Message Sent\n"); 2464 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2465 ahc_build_transfer_msg(ahc, devinfo); 2466 } else { 2467 printf("ahc_intr: AWAITING_MSG for an SCB that " 2468 "does not have a waiting message"); 2469 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2470 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2471 ahc_inb(ahc, MSG_OUT), scb->flags); 2472 } 2473 2474 /* 2475 * Clear the MK_MESSAGE flag from the SCB so we aren't 2476 * asked to send this message again. 2477 */ 2478 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2479 ahc->msgout_index = 0; 2480 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2481 } 2482 2483 static void 2484 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2485 { 2486 /* 2487 * To facilitate adding multiple messages together, 2488 * each routine should increment the index and len 2489 * variables instead of setting them explicitly. 2490 */ 2491 ahc->msgout_index = 0; 2492 ahc->msgout_len = 0; 2493 2494 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2495 ahc_build_transfer_msg(ahc, devinfo); 2496 else 2497 panic("ahc_intr: AWAITING target message with no message"); 2498 2499 ahc->msgout_index = 0; 2500 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2501 } 2502 2503 static int 2504 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2505 { 2506 /* 2507 * What we care about here is if we had an 2508 * outstanding SDTR or WDTR message for this 2509 * target. If we did, this is a signal that 2510 * the target is refusing negotiation. 2511 */ 2512 struct scb *scb; 2513 u_int scb_index; 2514 u_int last_msg; 2515 int response = 0; 2516 2517 scb_index = ahc_inb(ahc, SCB_TAG); 2518 scb = &ahc->scb_data->scbarray[scb_index]; 2519 2520 /* Might be necessary */ 2521 last_msg = ahc_inb(ahc, LAST_MSG); 2522 2523 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2524 struct ahc_initiator_tinfo *tinfo; 2525 struct tmode_tstate *tstate; 2526 2527 #ifdef AHC_DEBUG_NEG 2528 /* note 8bit xfers */ 2529 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2530 "8bit transfers\n", ahc_name(ahc), 2531 devinfo->channel, devinfo->target); 2532 #endif 2533 ahc_set_width(ahc, devinfo, 2534 MSG_EXT_WDTR_BUS_8_BIT, 2535 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2536 /*paused*/TRUE, /*done*/TRUE); 2537 /* 2538 * No need to clear the sync rate. If the target 2539 * did not accept the command, our syncrate is 2540 * unaffected. If the target started the negotiation, 2541 * but rejected our response, we already cleared the 2542 * sync rate before sending our WDTR. 2543 */ 2544 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2545 devinfo->our_scsiid, 2546 devinfo->target, &tstate); 2547 if (tinfo->goal.period) { 2548 u_int period; 2549 2550 /* Start the sync negotiation */ 2551 period = tinfo->goal.period; 2552 ahc_devlimited_syncrate(ahc, &period); 2553 ahc->msgout_index = 0; 2554 ahc->msgout_len = 0; 2555 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2556 ahc->msgout_index = 0; 2557 response = 1; 2558 } 2559 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2560 /* note asynch xfers and clear flag */ 2561 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2562 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2563 /*paused*/TRUE, /*done*/TRUE); 2564 #ifdef AHC_DEBUG_NEG 2565 printf("%s:%c:%d: refuses synchronous negotiation. " 2566 "Using asynchronous transfers\n", 2567 ahc_name(ahc), 2568 devinfo->channel, devinfo->target); 2569 #endif 2570 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2571 printf("%s:%c:%d: refuses tagged commands. Performing " 2572 "non-tagged I/O\n", ahc_name(ahc), 2573 devinfo->channel, devinfo->target); 2574 2575 ahc_set_tags(ahc, devinfo, FALSE); 2576 2577 /* 2578 * Resend the identify for this CCB as the target 2579 * may believe that the selection is invalid otherwise. 2580 */ 2581 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2582 & ~MSG_SIMPLE_Q_TAG); 2583 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2584 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2585 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2586 2587 /* 2588 * Requeue all tagged commands for this target 2589 * currently in our posession so they can be 2590 * converted to untagged commands. 2591 */ 2592 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2593 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2594 ROLE_INITIATOR, SCB_REQUEUE, 2595 SEARCH_COMPLETE); 2596 } else { 2597 /* 2598 * Otherwise, we ignore it. 2599 */ 2600 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2601 ahc_name(ahc), devinfo->channel, devinfo->target, 2602 last_msg); 2603 } 2604 return (response); 2605 } 2606 2607 static void 2608 ahc_clear_msg_state(struct ahc_softc *ahc) 2609 { 2610 ahc->msgout_len = 0; 2611 ahc->msgin_index = 0; 2612 ahc->msg_type = MSG_TYPE_NONE; 2613 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2614 } 2615 2616 static void 2617 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2618 { 2619 struct ahc_devinfo devinfo; 2620 u_int bus_phase; 2621 int end_session; 2622 2623 ahc_fetch_devinfo(ahc, &devinfo); 2624 end_session = FALSE; 2625 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2626 2627 reswitch: 2628 switch (ahc->msg_type) { 2629 case MSG_TYPE_INITIATOR_MSGOUT: 2630 { 2631 int lastbyte; 2632 int phasemis; 2633 int msgdone; 2634 2635 if (ahc->msgout_len == 0) 2636 panic("REQINIT interrupt with no active message"); 2637 2638 phasemis = bus_phase != P_MESGOUT; 2639 if (phasemis) { 2640 if (bus_phase == P_MESGIN) { 2641 /* 2642 * Change gears and see if 2643 * this messages is of interest to 2644 * us or should be passed back to 2645 * the sequencer. 2646 */ 2647 ahc_outb(ahc, CLRSINT1, CLRATNO); 2648 ahc->send_msg_perror = FALSE; 2649 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2650 ahc->msgin_index = 0; 2651 goto reswitch; 2652 } 2653 end_session = TRUE; 2654 break; 2655 } 2656 2657 if (ahc->send_msg_perror) { 2658 ahc_outb(ahc, CLRSINT1, CLRATNO); 2659 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2660 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2661 break; 2662 } 2663 2664 msgdone = ahc->msgout_index == ahc->msgout_len; 2665 if (msgdone) { 2666 /* 2667 * The target has requested a retry. 2668 * Re-assert ATN, reset our message index to 2669 * 0, and try again. 2670 */ 2671 ahc->msgout_index = 0; 2672 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2673 } 2674 2675 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2676 if (lastbyte) { 2677 /* Last byte is signified by dropping ATN */ 2678 ahc_outb(ahc, CLRSINT1, CLRATNO); 2679 } 2680 2681 /* 2682 * Clear our interrupt status and present 2683 * the next byte on the bus. 2684 */ 2685 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2686 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2687 break; 2688 } 2689 case MSG_TYPE_INITIATOR_MSGIN: 2690 { 2691 int phasemis; 2692 int message_done; 2693 2694 phasemis = bus_phase != P_MESGIN; 2695 2696 if (phasemis) { 2697 ahc->msgin_index = 0; 2698 if (bus_phase == P_MESGOUT 2699 && (ahc->send_msg_perror == TRUE 2700 || (ahc->msgout_len != 0 2701 && ahc->msgout_index == 0))) { 2702 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2703 goto reswitch; 2704 } 2705 end_session = TRUE; 2706 break; 2707 } 2708 2709 /* Pull the byte in without acking it */ 2710 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2711 2712 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2713 2714 if (message_done) { 2715 /* 2716 * Clear our incoming message buffer in case there 2717 * is another message following this one. 2718 */ 2719 ahc->msgin_index = 0; 2720 2721 /* 2722 * If this message illicited a response, 2723 * assert ATN so the target takes us to the 2724 * message out phase. 2725 */ 2726 if (ahc->msgout_len != 0) 2727 ahc_outb(ahc, SCSISIGO, 2728 ahc_inb(ahc, SCSISIGO) | ATNO); 2729 } else 2730 ahc->msgin_index++; 2731 2732 /* Ack the byte */ 2733 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2734 ahc_inb(ahc, SCSIDATL); 2735 break; 2736 } 2737 case MSG_TYPE_TARGET_MSGIN: 2738 { 2739 int msgdone; 2740 int msgout_request; 2741 2742 if (ahc->msgout_len == 0) 2743 panic("Target MSGIN with no active message"); 2744 2745 /* 2746 * If we interrupted a mesgout session, the initiator 2747 * will not know this until our first REQ. So, we 2748 * only honor mesgout requests after we've sent our 2749 * first byte. 2750 */ 2751 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2752 && ahc->msgout_index > 0) 2753 msgout_request = TRUE; 2754 else 2755 msgout_request = FALSE; 2756 2757 if (msgout_request) { 2758 2759 /* 2760 * Change gears and see if 2761 * this messages is of interest to 2762 * us or should be passed back to 2763 * the sequencer. 2764 */ 2765 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2766 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2767 ahc->msgin_index = 0; 2768 /* Dummy read to REQ for first byte */ 2769 ahc_inb(ahc, SCSIDATL); 2770 ahc_outb(ahc, SXFRCTL0, 2771 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2772 break; 2773 } 2774 2775 msgdone = ahc->msgout_index == ahc->msgout_len; 2776 if (msgdone) { 2777 ahc_outb(ahc, SXFRCTL0, 2778 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2779 end_session = TRUE; 2780 break; 2781 } 2782 2783 /* 2784 * Present the next byte on the bus. 2785 */ 2786 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2787 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2788 break; 2789 } 2790 case MSG_TYPE_TARGET_MSGOUT: 2791 { 2792 int lastbyte; 2793 int msgdone; 2794 2795 /* 2796 * The initiator signals that this is 2797 * the last byte by dropping ATN. 2798 */ 2799 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2800 2801 /* 2802 * Read the latched byte, but turn off SPIOEN first 2803 * so that we don't inadvertantly cause a REQ for the 2804 * next byte. 2805 */ 2806 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2807 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2808 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2809 if (msgdone == MSGLOOP_TERMINATED) { 2810 /* 2811 * The message is *really* done in that it caused 2812 * us to go to bus free. The sequencer has already 2813 * been reset at this point, so pull the ejection 2814 * handle. 2815 */ 2816 return; 2817 } 2818 2819 ahc->msgin_index++; 2820 2821 /* 2822 * XXX Read spec about initiator dropping ATN too soon 2823 * and use msgdone to detect it. 2824 */ 2825 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2826 ahc->msgin_index = 0; 2827 2828 /* 2829 * If this message illicited a response, transition 2830 * to the Message in phase and send it. 2831 */ 2832 if (ahc->msgout_len != 0) { 2833 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2834 ahc_outb(ahc, SXFRCTL0, 2835 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2836 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2837 ahc->msgin_index = 0; 2838 break; 2839 } 2840 } 2841 2842 if (lastbyte) 2843 end_session = TRUE; 2844 else { 2845 /* Ask for the next byte. */ 2846 ahc_outb(ahc, SXFRCTL0, 2847 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2848 } 2849 2850 break; 2851 } 2852 default: 2853 panic("Unknown REQINIT message type"); 2854 } 2855 2856 if (end_session) { 2857 ahc_clear_msg_state(ahc); 2858 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2859 } else 2860 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2861 } 2862 2863 /* 2864 * See if we sent a particular extended message to the target. 2865 * If "full" is true, the target saw the full message. 2866 * If "full" is false, the target saw at least the first 2867 * byte of the message. 2868 */ 2869 static int 2870 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2871 { 2872 int found; 2873 int index; 2874 2875 found = FALSE; 2876 index = 0; 2877 2878 while (index < ahc->msgout_len) { 2879 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2880 2881 /* Found a candidate */ 2882 if (ahc->msgout_buf[index+2] == msgtype) { 2883 u_int end_index; 2884 2885 end_index = index + 1 2886 + ahc->msgout_buf[index + 1]; 2887 if (full) { 2888 if (ahc->msgout_index > end_index) 2889 found = TRUE; 2890 } else if (ahc->msgout_index > index) 2891 found = TRUE; 2892 } 2893 break; 2894 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2895 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2896 2897 /* Skip tag type and tag id or residue param*/ 2898 index += 2; 2899 } else { 2900 /* Single byte message */ 2901 index++; 2902 } 2903 } 2904 return (found); 2905 } 2906 2907 static int 2908 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2909 struct ahc_devinfo *devinfo) 2910 { 2911 struct ahc_initiator_tinfo *tinfo; 2912 struct tmode_tstate *tstate; 2913 int reject; 2914 int done; 2915 int response; 2916 u_int targ_scsirate; 2917 2918 done = MSGLOOP_IN_PROG; 2919 response = FALSE; 2920 reject = FALSE; 2921 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2922 devinfo->target, &tstate); 2923 targ_scsirate = tinfo->scsirate; 2924 2925 /* 2926 * Parse as much of the message as is availible, 2927 * rejecting it if we don't support it. When 2928 * the entire message is availible and has been 2929 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2930 * that we have parsed an entire message. 2931 * 2932 * In the case of extended messages, we accept the length 2933 * byte outright and perform more checking once we know the 2934 * extended message type. 2935 */ 2936 switch (ahc->msgin_buf[0]) { 2937 case MSG_MESSAGE_REJECT: 2938 response = ahc_handle_msg_reject(ahc, devinfo); 2939 /* FALLTHROUGH */ 2940 case MSG_NOOP: 2941 done = MSGLOOP_MSGCOMPLETE; 2942 break; 2943 case MSG_IGN_WIDE_RESIDUE: 2944 { 2945 /* Wait for the whole message */ 2946 if (ahc->msgin_index >= 1) { 2947 if (ahc->msgin_buf[1] != 1 2948 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2949 reject = TRUE; 2950 done = MSGLOOP_MSGCOMPLETE; 2951 } else 2952 ahc_handle_ign_wide_residue(ahc, devinfo); 2953 } 2954 break; 2955 } 2956 case MSG_EXTENDED: 2957 { 2958 /* Wait for enough of the message to begin validation */ 2959 if (ahc->msgin_index < 2) 2960 break; 2961 switch (ahc->msgin_buf[2]) { 2962 case MSG_EXT_SDTR: 2963 { 2964 struct ahc_syncrate *syncrate; 2965 u_int period; 2966 u_int offset; 2967 u_int saved_offset; 2968 2969 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2970 reject = TRUE; 2971 break; 2972 } 2973 2974 /* 2975 * Wait until we have both args before validating 2976 * and acting on this message. 2977 * 2978 * Add one to MSG_EXT_SDTR_LEN to account for 2979 * the extended message preamble. 2980 */ 2981 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2982 break; 2983 2984 period = ahc->msgin_buf[3]; 2985 saved_offset = offset = ahc->msgin_buf[4]; 2986 syncrate = ahc_devlimited_syncrate(ahc, &period); 2987 ahc_validate_offset(ahc, syncrate, &offset, 2988 targ_scsirate & WIDEXFER); 2989 ahc_set_syncrate(ahc, devinfo, 2990 syncrate, period, offset, 2991 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2992 /*paused*/TRUE, /*done*/TRUE); 2993 2994 /* 2995 * See if we initiated Sync Negotiation 2996 * and didn't have to fall down to async 2997 * transfers. 2998 */ 2999 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3000 /* We started it */ 3001 if (saved_offset != offset) { 3002 /* Went too low - force async */ 3003 reject = TRUE; 3004 } 3005 } else { 3006 /* 3007 * Send our own SDTR in reply 3008 */ 3009 ahc->msgout_index = 0; 3010 ahc->msgout_len = 0; 3011 ahc_construct_sdtr(ahc, period, offset); 3012 ahc->msgout_index = 0; 3013 response = TRUE; 3014 } 3015 done = MSGLOOP_MSGCOMPLETE; 3016 break; 3017 } 3018 case MSG_EXT_WDTR: 3019 { 3020 u_int bus_width; 3021 u_int sending_reply; 3022 3023 sending_reply = FALSE; 3024 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3025 reject = TRUE; 3026 break; 3027 } 3028 3029 /* 3030 * Wait until we have our arg before validating 3031 * and acting on this message. 3032 * 3033 * Add one to MSG_EXT_WDTR_LEN to account for 3034 * the extended message preamble. 3035 */ 3036 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3037 break; 3038 3039 bus_width = ahc->msgin_buf[3]; 3040 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3041 /* 3042 * Don't send a WDTR back to the 3043 * target, since we asked first. 3044 */ 3045 switch (bus_width){ 3046 default: 3047 /* 3048 * How can we do anything greater 3049 * than 16bit transfers on a 16bit 3050 * bus? 3051 */ 3052 reject = TRUE; 3053 printf("%s: target %d requested %dBit " 3054 "transfers. Rejecting...\n", 3055 ahc_name(ahc), devinfo->target, 3056 8 * (0x01 << bus_width)); 3057 /* FALLTHROUGH */ 3058 case MSG_EXT_WDTR_BUS_8_BIT: 3059 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3060 break; 3061 case MSG_EXT_WDTR_BUS_16_BIT: 3062 break; 3063 } 3064 } else { 3065 /* 3066 * Send our own WDTR in reply 3067 */ 3068 switch (bus_width) { 3069 default: 3070 if (ahc->features & AHC_WIDE) { 3071 /* Respond Wide */ 3072 bus_width = 3073 MSG_EXT_WDTR_BUS_16_BIT; 3074 break; 3075 } 3076 /* FALLTHROUGH */ 3077 case MSG_EXT_WDTR_BUS_8_BIT: 3078 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3079 break; 3080 } 3081 ahc->msgout_index = 0; 3082 ahc->msgout_len = 0; 3083 ahc_construct_wdtr(ahc, bus_width); 3084 ahc->msgout_index = 0; 3085 response = TRUE; 3086 sending_reply = TRUE; 3087 } 3088 ahc_set_width(ahc, devinfo, bus_width, 3089 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3090 /*paused*/TRUE, /*done*/TRUE); 3091 3092 /* After a wide message, we are async */ 3093 ahc_set_syncrate(ahc, devinfo, 3094 /*syncrate*/NULL, /*period*/0, 3095 /*offset*/0, AHC_TRANS_ACTIVE, 3096 /*paused*/TRUE, /*done*/FALSE); 3097 if (sending_reply == FALSE && reject == FALSE) { 3098 3099 if (tinfo->goal.period) { 3100 struct ahc_syncrate *rate; 3101 u_int period; 3102 u_int offset; 3103 3104 /* Start the sync negotiation */ 3105 period = tinfo->goal.period; 3106 rate = ahc_devlimited_syncrate(ahc, 3107 &period); 3108 offset = tinfo->goal.offset; 3109 ahc_validate_offset(ahc, rate, &offset, 3110 tinfo->current.width); 3111 ahc->msgout_index = 0; 3112 ahc->msgout_len = 0; 3113 ahc_construct_sdtr(ahc, period, offset); 3114 ahc->msgout_index = 0; 3115 response = TRUE; 3116 } 3117 } 3118 done = MSGLOOP_MSGCOMPLETE; 3119 break; 3120 } 3121 default: 3122 /* Unknown extended message. Reject it. */ 3123 reject = TRUE; 3124 break; 3125 } 3126 break; 3127 } 3128 case MSG_BUS_DEV_RESET: 3129 ahc_handle_devreset(ahc, devinfo, 3130 XS_RESET, "Bus Device Reset Received", 3131 /*verbose_level*/0); 3132 restart_sequencer(ahc); 3133 done = MSGLOOP_TERMINATED; 3134 break; 3135 case MSG_ABORT_TAG: 3136 case MSG_ABORT: 3137 case MSG_CLEAR_QUEUE: 3138 /* Target mode messages */ 3139 if (devinfo->role != ROLE_TARGET) { 3140 reject = TRUE; 3141 break; 3142 } 3143 #if AHC_TARGET_MODE 3144 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3145 devinfo->lun, 3146 ahc->msgin_buf[0] == MSG_ABORT_TAG 3147 ? SCB_LIST_NULL 3148 : ahc_inb(ahc, INITIATOR_TAG), 3149 ROLE_TARGET, XS_DRIVER_STUFFUP); 3150 3151 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3152 if (tstate != NULL) { 3153 struct tmode_lstate* lstate; 3154 3155 lstate = tstate->enabled_luns[devinfo->lun]; 3156 if (lstate != NULL) { 3157 ahc_queue_lstate_event(ahc, lstate, 3158 devinfo->our_scsiid, 3159 ahc->msgin_buf[0], 3160 /*arg*/0); 3161 ahc_send_lstate_events(ahc, lstate); 3162 } 3163 } 3164 done = MSGLOOP_MSGCOMPLETE; 3165 #else 3166 panic("ahc: got target mode message"); 3167 #endif 3168 break; 3169 case MSG_TERM_IO_PROC: 3170 default: 3171 reject = TRUE; 3172 break; 3173 } 3174 3175 if (reject) { 3176 /* 3177 * Setup to reject the message. 3178 */ 3179 ahc->msgout_index = 0; 3180 ahc->msgout_len = 1; 3181 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3182 done = MSGLOOP_MSGCOMPLETE; 3183 response = TRUE; 3184 } 3185 3186 if (done != MSGLOOP_IN_PROG && !response) 3187 /* Clear the outgoing message buffer */ 3188 ahc->msgout_len = 0; 3189 3190 return (done); 3191 } 3192 3193 static void 3194 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3195 { 3196 u_int scb_index; 3197 struct scb *scb; 3198 3199 scb_index = ahc_inb(ahc, SCB_TAG); 3200 scb = &ahc->scb_data->scbarray[scb_index]; 3201 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3202 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3203 /* 3204 * Ignore the message if we haven't 3205 * seen an appropriate data phase yet. 3206 */ 3207 } else { 3208 /* 3209 * If the residual occurred on the last 3210 * transfer and the transfer request was 3211 * expected to end on an odd count, do 3212 * nothing. Otherwise, subtract a byte 3213 * and update the residual count accordingly. 3214 */ 3215 u_int resid_sgcnt; 3216 3217 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3218 if (resid_sgcnt == 0 3219 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3220 /* 3221 * If the residual occurred on the last 3222 * transfer and the transfer request was 3223 * expected to end on an odd count, do 3224 * nothing. 3225 */ 3226 } else { 3227 u_int data_cnt; 3228 u_int32_t data_addr; 3229 u_int sg_index; 3230 3231 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3232 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3233 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3234 3235 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3236 | (ahc_inb(ahc, SHADDR + 2) << 16) 3237 | (ahc_inb(ahc, SHADDR + 1) << 8) 3238 | (ahc_inb(ahc, SHADDR)); 3239 3240 data_cnt += 1; 3241 data_addr -= 1; 3242 3243 sg_index = scb->sg_count - resid_sgcnt; 3244 3245 if (sg_index != 0 3246 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3247 u_int32_t sg_addr; 3248 3249 sg_index--; 3250 data_cnt = 1; 3251 data_addr = le32toh(scb->sg_list[sg_index].addr) 3252 + le32toh(scb->sg_list[sg_index].len) 3253 - 1; 3254 3255 /* 3256 * The physical address base points to the 3257 * second entry as it is always used for 3258 * calculating the "next S/G pointer". 3259 */ 3260 sg_addr = scb->sg_list_phys 3261 + (sg_index* sizeof(*scb->sg_list)); 3262 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3263 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3264 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3265 ahc_outb(ahc, SG_NEXT, sg_addr); 3266 } 3267 3268 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3269 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3270 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3271 3272 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3273 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3274 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3275 ahc_outb(ahc, SHADDR, data_addr); 3276 } 3277 } 3278 } 3279 3280 static void 3281 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3282 int status, char *message, 3283 int verbose_level) 3284 { 3285 int found; 3286 3287 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3288 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3289 status); 3290 3291 /* 3292 * Go back to async/narrow transfers and renegotiate. 3293 * ahc_set_width and ahc_set_syncrate can cope with NULL 3294 * paths. 3295 */ 3296 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3297 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3298 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3299 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3300 /*paused*/TRUE, /*done*/FALSE); 3301 3302 if (message != NULL && (verbose_level <= 0)) 3303 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3304 message, devinfo->channel, devinfo->target, found); 3305 } 3306 3307 /* 3308 * We have an scb which has been processed by the 3309 * adaptor, now we look to see how the operation 3310 * went. 3311 */ 3312 static void 3313 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3314 { 3315 struct scsipi_xfer *xs; 3316 struct scsipi_link *sc_link; 3317 int requeue = 0; 3318 int target; 3319 3320 3321 xs = scb->xs; 3322 sc_link = xs->sc_link; 3323 LIST_REMOVE(scb, plinks); 3324 3325 callout_stop(&scb->xs->xs_callout); 3326 3327 #ifdef AHC_DEBUG 3328 if (ahc_debug & AHC_SHOWCMDS) { 3329 scsi_print_addr(sc_link); 3330 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3331 scb->hscb->tag); 3332 } 3333 #endif 3334 3335 target = sc_link->scsipi_scsi.target; 3336 3337 if (xs->datalen) { 3338 int op; 3339 3340 if (xs->xs_control & XS_CTL_DATA_IN) 3341 op = BUS_DMASYNC_POSTREAD; 3342 else 3343 op = BUS_DMASYNC_POSTWRITE; 3344 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3345 scb->dmamap->dm_mapsize, op); 3346 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3347 } 3348 3349 /* 3350 * Unbusy this target/channel/lun. 3351 * XXX if we are holding two commands per lun, 3352 * send the next command. 3353 */ 3354 if (!(scb->hscb->control & TAG_ENB)) 3355 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3356 3357 /* 3358 * If the recovery SCB completes, we have to be 3359 * out of our timeout. 3360 */ 3361 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3362 3363 struct scb *scbp; 3364 3365 /* 3366 * We were able to complete the command successfully, 3367 * so reinstate the timeouts for all other pending 3368 * commands. 3369 */ 3370 scbp = ahc->pending_ccbs.lh_first; 3371 while (scbp != NULL) { 3372 struct scsipi_xfer *txs = scbp->xs; 3373 3374 if (!(txs->xs_control & XS_CTL_POLL)) { 3375 callout_reset(&scbp->xs->xs_callout, 3376 (scbp->xs->timeout * hz) / 1000, 3377 ahc_timeout, scbp); 3378 } 3379 scbp = LIST_NEXT(scbp, plinks); 3380 } 3381 3382 /* 3383 * Ensure that we didn't put a second instance of this 3384 * SCB into the QINFIFO. 3385 */ 3386 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3387 SCB_LUN(scb), scb->hscb->tag, 3388 ROLE_INITIATOR, /*status*/0, 3389 SEARCH_REMOVE); 3390 if (xs->error != XS_NOERROR) 3391 ahcsetccbstatus(xs, XS_TIMEOUT); 3392 scsi_print_addr(xs->sc_link); 3393 printf("no longer in timeout, status = %x\n", xs->status); 3394 } 3395 3396 if (xs->error != XS_NOERROR) { 3397 /* Don't clobber any existing error state */ 3398 } else if ((scb->flags & SCB_SENSE) != 0) { 3399 /* 3400 * We performed autosense retrieval. 3401 * 3402 * bzero the sense data before having 3403 * the drive fill it. The SCSI spec mandates 3404 * that any untransfered data should be 3405 * assumed to be zero. Complete the 'bounce' 3406 * of sense information through buffers accessible 3407 * via bus-space by copying it into the clients 3408 * csio. 3409 */ 3410 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3411 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3412 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3413 xs->error = XS_SENSE; 3414 } 3415 if (scb->flags & SCB_FREEZE_QUEUE) { 3416 ahc->devqueue_blocked[target]--; 3417 scb->flags &= ~SCB_FREEZE_QUEUE; 3418 } 3419 3420 requeue = scb->flags & SCB_REQUEUE; 3421 ahcfreescb(ahc, scb); 3422 3423 if (requeue) { 3424 /* 3425 * Re-insert at the front of the private queue to 3426 * preserve order. 3427 */ 3428 int s; 3429 3430 s = splbio(); 3431 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3432 splx(s); 3433 } else { 3434 xs->xs_status |= XS_STS_DONE; 3435 ahc_check_tags(ahc, xs); 3436 scsipi_done(xs); 3437 } 3438 3439 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3440 ahc_action(xs); 3441 } 3442 3443 /* 3444 * Determine the number of SCBs available on the controller 3445 */ 3446 int 3447 ahc_probe_scbs(struct ahc_softc *ahc) { 3448 int i; 3449 3450 for (i = 0; i < AHC_SCB_MAX; i++) { 3451 ahc_outb(ahc, SCBPTR, i); 3452 ahc_outb(ahc, SCB_CONTROL, i); 3453 if (ahc_inb(ahc, SCB_CONTROL) != i) 3454 break; 3455 ahc_outb(ahc, SCBPTR, 0); 3456 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3457 break; 3458 } 3459 return (i); 3460 } 3461 3462 /* 3463 * Start the board, ready for normal operation 3464 */ 3465 int 3466 ahc_init(struct ahc_softc *ahc) 3467 { 3468 int max_targ = 15; 3469 int i; 3470 int term; 3471 u_int scsi_conf; 3472 u_int scsiseq_template; 3473 u_int ultraenb; 3474 u_int discenable; 3475 u_int tagenable; 3476 size_t driver_data_size; 3477 u_int32_t physaddr; 3478 3479 #ifdef AHC_PRINT_SRAM 3480 printf("Scratch Ram:"); 3481 for (i = 0x20; i < 0x5f; i++) { 3482 if (((i % 8) == 0) && (i != 0)) { 3483 printf ("\n "); 3484 } 3485 printf (" 0x%x", ahc_inb(ahc, i)); 3486 } 3487 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3488 for (i = 0x70; i < 0x7f; i++) { 3489 if (((i % 8) == 0) && (i != 0)) { 3490 printf ("\n "); 3491 } 3492 printf (" 0x%x", ahc_inb(ahc, i)); 3493 } 3494 } 3495 printf ("\n"); 3496 #endif 3497 3498 /* 3499 * Assume we have a board at this stage and it has been reset. 3500 */ 3501 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3502 ahc->our_id = ahc->our_id_b = 7; 3503 3504 /* 3505 * Default to allowing initiator operations. 3506 */ 3507 ahc->flags |= AHC_INITIATORMODE; 3508 3509 /* 3510 * DMA tag for our command fifos and other data in system memory 3511 * the card's sequencer must be able to access. For initiator 3512 * roles, we need to allocate space for the qinfifo, qoutfifo, 3513 * and untagged_scb arrays each of which are composed of 256 3514 * 1 byte elements. When providing for the target mode role, 3515 * we additionally must provide space for the incoming target 3516 * command fifo. 3517 */ 3518 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3519 3520 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3521 ahc->sc_dmaflags, 3522 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3523 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3524 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3525 return (ENOMEM); 3526 3527 ahc->init_level++; 3528 3529 /* Allocate SCB data now that parent_dmat is initialized */ 3530 if (ahc->scb_data->maxhscbs == 0) 3531 if (ahcinitscbdata(ahc) != 0) 3532 return (ENOMEM); 3533 3534 ahc->qinfifo = &ahc->qoutfifo[256]; 3535 ahc->untagged_scbs = &ahc->qinfifo[256]; 3536 /* There are no untagged SCBs active yet. */ 3537 for (i = 0; i < 256; i++) 3538 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3539 3540 /* All of our queues are empty */ 3541 for (i = 0; i < 256; i++) 3542 ahc->qoutfifo[i] = SCB_LIST_NULL; 3543 3544 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3545 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3546 3547 /* 3548 * Allocate a tstate to house information for our 3549 * initiator presence on the bus as well as the user 3550 * data for any target mode initiator. 3551 */ 3552 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3553 printf("%s: unable to allocate tmode_tstate. " 3554 "Failing attach\n", ahc_name(ahc)); 3555 return (-1); 3556 } 3557 3558 if ((ahc->features & AHC_TWIN) != 0) { 3559 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3560 printf("%s: unable to allocate tmode_tstate. " 3561 "Failing attach\n", ahc_name(ahc)); 3562 return (-1); 3563 } 3564 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3565 ahc->our_id, ahc->our_id_b, 3566 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3567 } else { 3568 if ((ahc->features & AHC_WIDE) != 0) { 3569 printf("Wide "); 3570 } else { 3571 printf("Single "); 3572 } 3573 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3574 } 3575 3576 ahc_outb(ahc, SEQ_FLAGS, 0); 3577 3578 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3579 ahc->flags |= AHC_PAGESCBS; 3580 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3581 } else { 3582 ahc->flags &= ~AHC_PAGESCBS; 3583 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3584 } 3585 3586 #ifdef AHC_DEBUG 3587 if (ahc_debug & AHC_SHOWMISC) { 3588 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3589 "ahc_dma %d bytes\n", 3590 ahc_name(ahc), 3591 sizeof(struct hardware_scb), 3592 sizeof(struct scb), 3593 sizeof(struct ahc_dma_seg)); 3594 } 3595 #endif /* AHC_DEBUG */ 3596 3597 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3598 if (ahc->features & AHC_TWIN) { 3599 3600 /* 3601 * The device is gated to channel B after a chip reset, 3602 * so set those values first 3603 */ 3604 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3605 if ((ahc->features & AHC_ULTRA2) != 0) 3606 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3607 else 3608 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3609 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3610 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3611 |term|ENSTIMER|ACTNEGEN); 3612 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3613 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3614 3615 if ((scsi_conf & RESET_SCSI) != 0 3616 && (ahc->flags & AHC_INITIATORMODE) != 0) 3617 ahc->flags |= AHC_RESET_BUS_B; 3618 3619 /* Select Channel A */ 3620 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3621 } 3622 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3623 if ((ahc->features & AHC_ULTRA2) != 0) 3624 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3625 else 3626 ahc_outb(ahc, SCSIID, ahc->our_id); 3627 scsi_conf = ahc_inb(ahc, SCSICONF); 3628 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3629 |term 3630 |ENSTIMER|ACTNEGEN); 3631 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3632 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3633 3634 if ((scsi_conf & RESET_SCSI) != 0 3635 && (ahc->flags & AHC_INITIATORMODE) != 0) 3636 ahc->flags |= AHC_RESET_BUS_A; 3637 3638 /* 3639 * Look at the information that board initialization or 3640 * the board bios has left us. 3641 */ 3642 ultraenb = 0; 3643 tagenable = ALL_TARGETS_MASK; 3644 3645 /* Grab the disconnection disable table and invert it for our needs */ 3646 if (ahc->flags & AHC_USEDEFAULTS) { 3647 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3648 "device parameters\n", ahc_name(ahc)); 3649 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3650 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3651 discenable = ALL_TARGETS_MASK; 3652 if ((ahc->features & AHC_ULTRA) != 0) 3653 ultraenb = ALL_TARGETS_MASK; 3654 } else { 3655 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3656 | ahc_inb(ahc, DISC_DSB)); 3657 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3658 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3659 | ahc_inb(ahc, ULTRA_ENB); 3660 } 3661 3662 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3663 max_targ = 7; 3664 3665 for (i = 0; i <= max_targ; i++) { 3666 struct ahc_initiator_tinfo *tinfo; 3667 struct tmode_tstate *tstate; 3668 u_int our_id; 3669 u_int target_id; 3670 char channel; 3671 3672 channel = 'A'; 3673 our_id = ahc->our_id; 3674 target_id = i; 3675 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3676 channel = 'B'; 3677 our_id = ahc->our_id_b; 3678 target_id = i % 8; 3679 } 3680 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3681 target_id, &tstate); 3682 /* Default to async narrow across the board */ 3683 bzero(tinfo, sizeof(*tinfo)); 3684 if (ahc->flags & AHC_USEDEFAULTS) { 3685 if ((ahc->features & AHC_WIDE) != 0) 3686 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3687 3688 /* 3689 * These will be truncated when we determine the 3690 * connection type we have with the target. 3691 */ 3692 tinfo->user.period = ahc_syncrates->period; 3693 tinfo->user.offset = ~0; 3694 } else { 3695 u_int scsirate; 3696 u_int16_t mask; 3697 3698 /* Take the settings leftover in scratch RAM. */ 3699 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3700 mask = (0x01 << i); 3701 if ((ahc->features & AHC_ULTRA2) != 0) { 3702 u_int offset; 3703 u_int maxsync; 3704 3705 if ((scsirate & SOFS) == 0x0F) { 3706 /* 3707 * Haven't negotiated yet, 3708 * so the format is different. 3709 */ 3710 scsirate = (scsirate & SXFR) >> 4 3711 | (ultraenb & mask) 3712 ? 0x08 : 0x0 3713 | (scsirate & WIDEXFER); 3714 offset = MAX_OFFSET_ULTRA2; 3715 } else 3716 offset = ahc_inb(ahc, TARG_OFFSET + i); 3717 maxsync = AHC_SYNCRATE_ULTRA2; 3718 if ((ahc->features & AHC_DT) != 0) 3719 maxsync = AHC_SYNCRATE_DT; 3720 tinfo->user.period = 3721 ahc_find_period(ahc, scsirate, maxsync); 3722 if (offset == 0) 3723 tinfo->user.period = 0; 3724 else 3725 tinfo->user.offset = ~0; 3726 } else if ((scsirate & SOFS) != 0) { 3727 tinfo->user.period = 3728 ahc_find_period(ahc, scsirate, 3729 (ultraenb & mask) 3730 ? AHC_SYNCRATE_ULTRA 3731 : AHC_SYNCRATE_FAST); 3732 if (tinfo->user.period != 0) 3733 tinfo->user.offset = ~0; 3734 } 3735 if ((scsirate & WIDEXFER) != 0 3736 && (ahc->features & AHC_WIDE) != 0) 3737 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3738 } 3739 tinfo->goal = tinfo->user; /* force negotiation */ 3740 tstate->ultraenb = ultraenb; 3741 tstate->discenable = discenable; 3742 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3743 tstate->tagdisable = 0; 3744 } 3745 ahc->user_discenable = discenable; 3746 ahc->user_tagenable = tagenable; 3747 3748 /* 3749 * Tell the sequencer where it can find our arrays in memory. 3750 */ 3751 physaddr = ahc->scb_data->hscb_busaddr; 3752 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3753 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3754 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3755 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3756 3757 physaddr = ahc->shared_data_busaddr; 3758 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3759 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3760 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3761 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3762 3763 /* Target mode incomding command fifo */ 3764 physaddr += 3 * 256 * sizeof(u_int8_t); 3765 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3766 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3767 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3768 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3769 3770 /* 3771 * Initialize the group code to command length table. 3772 * This overrides the values in TARG_SCSIRATE, so only 3773 * setup the table after we have processed that information. 3774 */ 3775 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3781 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3782 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3783 3784 /* Tell the sequencer of our initial queue positions */ 3785 ahc_outb(ahc, KERNEL_QINPOS, 0); 3786 ahc_outb(ahc, QINPOS, 0); 3787 ahc_outb(ahc, QOUTPOS, 0); 3788 3789 #ifdef AHC_DEBUG 3790 if (ahc_debug & AHC_SHOWMISC) 3791 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3792 discenable, ultraenb); 3793 #endif 3794 3795 /* Don't have any special messages to send to targets */ 3796 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3797 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3798 3799 /* 3800 * Use the built in queue management registers 3801 * if they are available. 3802 */ 3803 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3804 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3805 ahc_outb(ahc, SDSCB_QOFF, 0); 3806 ahc_outb(ahc, SNSCB_QOFF, 0); 3807 ahc_outb(ahc, HNSCB_QOFF, 0); 3808 } 3809 3810 3811 /* We don't have any waiting selections */ 3812 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3813 3814 /* Our disconnection list is empty too */ 3815 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3816 3817 /* Message out buffer starts empty */ 3818 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3819 3820 /* 3821 * Setup the allowed SCSI Sequences based on operational mode. 3822 * If we are a target, we'll enalbe select in operations once 3823 * we've had a lun enabled. 3824 */ 3825 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3826 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3827 scsiseq_template |= ENRSELI; 3828 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3829 3830 /* 3831 * Load the Sequencer program and Enable the adapter 3832 * in "fast" mode. 3833 */ 3834 #ifdef AHC_DEBUG 3835 printf("%s: Downloading Sequencer Program...", 3836 ahc_name(ahc)); 3837 #endif 3838 3839 ahc_loadseq(ahc); 3840 3841 /* We have to wait until after any system dumps... */ 3842 shutdownhook_establish(ahc_shutdown, ahc); 3843 3844 return (0); 3845 } 3846 3847 static int 3848 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3849 struct proc *p) 3850 { 3851 struct ahc_softc *ahc = sc_link->adapter_softc; 3852 char channel; 3853 int s, ret = ENOTTY; 3854 3855 switch (cmd) { 3856 case SCBUSIORESET: 3857 channel = SIM_CHANNEL(ahc, sc_link); 3858 s = splbio(); 3859 ahc_reset_channel(ahc, channel, TRUE); 3860 splx(s); 3861 ret = 0; 3862 break; 3863 default: 3864 } 3865 3866 return ret; 3867 } 3868 3869 3870 /* 3871 * XXX fvdl the busy_tcl checks and settings should only be done 3872 * for the non-tagged queueing case, but we don't do tagged queueing 3873 * yet, so.. 3874 */ 3875 static int32_t 3876 ahc_action(struct scsipi_xfer *xs) 3877 { 3878 struct scsipi_xfer *first_xs, *next_xs = NULL; 3879 struct ahc_softc *ahc; 3880 struct scb *scb; 3881 struct hardware_scb *hscb; 3882 struct ahc_initiator_tinfo *tinfo; 3883 struct tmode_tstate *tstate; 3884 u_int target_id; 3885 u_int our_id; 3886 int s, tcl; 3887 u_int16_t mask; 3888 char channel; 3889 int dontqueue = 0, fromqueue = 0; 3890 3891 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3892 3893 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3894 3895 /* must protect the queue */ 3896 s = splbio(); 3897 3898 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3899 /* 3900 * Called from ahc_done. Calling with the first entry in 3901 * the queue is really just a way of seeing where we're 3902 * called from. Now, find the first eligible SCB to send, 3903 * e.g. one which will be accepted immediately. 3904 */ 3905 3906 if (ahc->queue_blocked) { 3907 splx(s); 3908 return (TRY_AGAIN_LATER); 3909 } 3910 3911 xs = ahc_first_xs(ahc); 3912 if (xs == NULL) { 3913 splx(s); 3914 return (TRY_AGAIN_LATER); 3915 } 3916 3917 next_xs = TAILQ_NEXT(xs, adapter_q); 3918 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3919 fromqueue = 1; 3920 goto get_scb; 3921 } 3922 3923 /* 3924 * If no new requests are accepted, just insert into the 3925 * private queue to wait for our turn. 3926 */ 3927 tcl = XS_TCL(ahc, xs); 3928 3929 if (ahc->queue_blocked || 3930 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3931 (!ahc_istagged_device(ahc, xs, 0) && 3932 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3933 if (dontqueue) { 3934 splx(s); 3935 xs->error = XS_DRIVER_STUFFUP; 3936 return TRY_AGAIN_LATER; 3937 } 3938 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3939 splx(s); 3940 return SUCCESSFULLY_QUEUED; 3941 } 3942 3943 first_xs = ahc_first_xs(ahc); 3944 3945 /* determine safety of software queueing */ 3946 dontqueue = xs->xs_control & XS_CTL_POLL; 3947 3948 /* 3949 * Handle situations where there's already entries in the 3950 * queue. 3951 */ 3952 if (first_xs != NULL) { 3953 /* 3954 * If we can't queue, we have to abort, since 3955 * we have to preserve order. 3956 */ 3957 if (dontqueue) { 3958 splx(s); 3959 xs->error = XS_DRIVER_STUFFUP; 3960 return (TRY_AGAIN_LATER); 3961 } 3962 3963 /* 3964 * Swap with the first queue entry. 3965 */ 3966 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3967 xs = first_xs; 3968 next_xs = TAILQ_NEXT(xs, adapter_q); 3969 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3970 fromqueue = 1; 3971 3972 } 3973 3974 get_scb: 3975 3976 target_id = xs->sc_link->scsipi_scsi.target; 3977 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3978 3979 /* 3980 * get an scb to use. 3981 */ 3982 if ((scb = ahcgetscb(ahc)) == NULL) { 3983 3984 if (dontqueue) { 3985 splx(s); 3986 xs->error = XS_DRIVER_STUFFUP; 3987 return (TRY_AGAIN_LATER); 3988 } 3989 3990 /* 3991 * If we were pulled off the queue, put ourselves 3992 * back to where we came from, otherwise tack ourselves 3993 * onto the end. 3994 */ 3995 if (fromqueue && next_xs != NULL) 3996 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3997 else 3998 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3999 4000 splx(s); 4001 return (SUCCESSFULLY_QUEUED); 4002 } 4003 4004 tcl = XS_TCL(ahc, xs); 4005 4006 #ifdef DIAGNOSTIC 4007 if (!ahc_istagged_device(ahc, xs, 0) && 4008 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4009 panic("ahc: queuing for busy target"); 4010 #endif 4011 4012 scb->xs = xs; 4013 hscb = scb->hscb; 4014 hscb->tcl = tcl; 4015 4016 if (ahc_istagged_device(ahc, xs, 0)) 4017 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4018 else 4019 ahc_busy_tcl(ahc, scb); 4020 4021 splx(s); 4022 4023 channel = SIM_CHANNEL(ahc, xs->sc_link); 4024 if (ahc->inited_channels[channel - 'A'] == 0) { 4025 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4026 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4027 s = splbio(); 4028 ahc_reset_channel(ahc, channel, TRUE); 4029 splx(s); 4030 } 4031 ahc->inited_channels[channel - 'A'] = 1; 4032 } 4033 4034 /* 4035 * Put all the arguments for the xfer in the scb 4036 */ 4037 4038 mask = SCB_TARGET_MASK(scb); 4039 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4040 target_id, &tstate); 4041 if (ahc->inited_targets[target_id] == 0) { 4042 struct ahc_devinfo devinfo; 4043 4044 s = splbio(); 4045 ahc_compile_devinfo(&devinfo, our_id, target_id, 4046 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4047 ROLE_INITIATOR); 4048 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4049 FALSE); 4050 ahc->inited_targets[target_id] = 1; 4051 splx(s); 4052 } 4053 4054 hscb->scsirate = tinfo->scsirate; 4055 hscb->scsioffset = tinfo->current.offset; 4056 if ((tstate->ultraenb & mask) != 0) 4057 hscb->control |= ULTRAENB; 4058 4059 if ((tstate->discenable & mask) != 0) 4060 hscb->control |= DISCENB; 4061 4062 if (xs->xs_control & XS_CTL_RESET) { 4063 hscb->cmdpointer = 0; 4064 scb->flags |= SCB_DEVICE_RESET; 4065 hscb->control |= MK_MESSAGE; 4066 return ahc_execute_scb(scb, NULL, 0); 4067 } 4068 4069 return ahc_setup_data(ahc, xs, scb); 4070 } 4071 4072 static int 4073 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4074 { 4075 struct scb *scb; 4076 struct scsipi_xfer *xs; 4077 struct ahc_softc *ahc; 4078 int s; 4079 4080 scb = (struct scb *)arg; 4081 xs = scb->xs; 4082 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4083 4084 4085 if (nsegments != 0) { 4086 struct ahc_dma_seg *sg; 4087 bus_dma_segment_t *end_seg; 4088 int op; 4089 4090 end_seg = dm_segs + nsegments; 4091 4092 /* Copy the first SG into the data pointer area */ 4093 scb->hscb->data = dm_segs->ds_addr; 4094 scb->hscb->datalen = dm_segs->ds_len; 4095 4096 /* Copy the segments into our SG list */ 4097 sg = scb->sg_list; 4098 while (dm_segs < end_seg) { 4099 sg->addr = dm_segs->ds_addr; 4100 sg->len = dm_segs->ds_len; 4101 ahc_swap_sg(sg); 4102 sg++; 4103 dm_segs++; 4104 } 4105 4106 /* Note where to find the SG entries in bus space */ 4107 scb->hscb->SG_pointer = scb->sg_list_phys; 4108 4109 if (xs->xs_control & XS_CTL_DATA_IN) 4110 op = BUS_DMASYNC_PREREAD; 4111 else 4112 op = BUS_DMASYNC_PREWRITE; 4113 4114 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4115 scb->dmamap->dm_mapsize, op); 4116 4117 } else { 4118 scb->hscb->SG_pointer = 0; 4119 scb->hscb->data = 0; 4120 scb->hscb->datalen = 0; 4121 } 4122 4123 scb->sg_count = scb->hscb->SG_count = nsegments; 4124 4125 s = splbio(); 4126 4127 /* 4128 * Last time we need to check if this SCB needs to 4129 * be aborted. 4130 */ 4131 if (xs->xs_status & XS_STS_DONE) { 4132 if (!ahc_istagged_device(ahc, xs, 0)) 4133 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4134 if (nsegments != 0) 4135 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4136 ahcfreescb(ahc, scb); 4137 splx(s); 4138 return (COMPLETE); 4139 } 4140 4141 #ifdef DIAGNOSTIC 4142 if (scb->sg_count > 255) 4143 panic("ahc bad sg_count"); 4144 #endif 4145 4146 ahc_swap_hscb(scb->hscb); 4147 4148 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4149 4150 scb->flags |= SCB_ACTIVE; 4151 4152 if (!(xs->xs_control & XS_CTL_POLL)) 4153 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4154 ahc_timeout, scb); 4155 4156 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4157 #if 0 4158 printf("Continueing Immediate Command %d:%d\n", 4159 xs->sc_link->scsipi_scsi.target, 4160 xs->sc_link->scsipi_scsi.lun); 4161 #endif 4162 pause_sequencer(ahc); 4163 if ((ahc->flags & AHC_PAGESCBS) == 0) 4164 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4165 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4166 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4167 unpause_sequencer(ahc); 4168 } else { 4169 4170 #if 0 4171 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4172 scb->hscb->tag, ahc->qinfifonext, 4173 &ahc->qinfifo[ahc->qinfifonext], 4174 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4175 #endif 4176 4177 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4178 4179 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4180 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4181 4182 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4183 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4184 } else { 4185 pause_sequencer(ahc); 4186 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4187 unpause_sequencer(ahc); 4188 } 4189 } 4190 4191 #ifdef AHC_DEBUG 4192 if (ahc_debug & AHC_SHOWCMDS) { 4193 scsi_print_addr(xs->sc_link); 4194 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4195 " rate %x\n", 4196 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4197 scb->flags, scb->hscb->control, ahc->qinfifonext, 4198 scb->hscb->scsirate); 4199 } 4200 #endif 4201 4202 if (!(xs->xs_control & XS_CTL_POLL)) { 4203 splx(s); 4204 return (SUCCESSFULLY_QUEUED); 4205 } 4206 /* 4207 * If we can't use interrupts, poll for completion 4208 */ 4209 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4210 do { 4211 if (ahc_poll(ahc, xs->timeout)) { 4212 if (!(xs->xs_control & XS_CTL_SILENT)) 4213 printf("cmd fail\n"); 4214 ahc_timeout(scb); 4215 break; 4216 } 4217 } while (!(xs->xs_status & XS_STS_DONE)); 4218 splx(s); 4219 return (COMPLETE); 4220 } 4221 4222 static int 4223 ahc_poll(struct ahc_softc *ahc, int wait) 4224 { 4225 while (--wait) { 4226 DELAY(1000); 4227 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4228 break; 4229 } 4230 4231 if (wait == 0) { 4232 printf("%s: board is not responding\n", ahc_name(ahc)); 4233 return (EIO); 4234 } 4235 4236 ahc_intr((void *)ahc); 4237 return (0); 4238 } 4239 4240 static int 4241 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4242 struct scb *scb) 4243 { 4244 struct hardware_scb *hscb; 4245 4246 hscb = scb->hscb; 4247 xs->resid = xs->status = 0; 4248 4249 hscb->cmdlen = xs->cmdlen; 4250 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4251 hscb->cmdpointer = hscb->cmdstore_busaddr; 4252 4253 /* Only use S/G if there is a transfer */ 4254 if (xs->datalen) { 4255 int error; 4256 4257 error = bus_dmamap_load(ahc->parent_dmat, 4258 scb->dmamap, xs->data, 4259 xs->datalen, NULL, 4260 (xs->xs_control & XS_CTL_NOSLEEP) ? 4261 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4262 if (error) { 4263 if (!ahc_istagged_device(ahc, xs, 0)) 4264 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4265 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4266 } 4267 error = ahc_execute_scb(scb, 4268 scb->dmamap->dm_segs, 4269 scb->dmamap->dm_nsegs); 4270 return error; 4271 } else { 4272 return ahc_execute_scb(scb, NULL, 0); 4273 } 4274 } 4275 4276 static void 4277 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4278 { 4279 int target; 4280 char channel; 4281 int lun; 4282 4283 target = sc_link->scsipi_scsi.target; 4284 lun = sc_link->scsipi_scsi.lun; 4285 channel = sc_link->scsipi_scsi.channel; 4286 4287 ahc_search_qinfifo(ahc, target, channel, lun, 4288 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4289 SCB_REQUEUE, SEARCH_COMPLETE); 4290 } 4291 4292 static void 4293 ahcallocscbs(struct ahc_softc *ahc) 4294 { 4295 struct scb_data *scb_data; 4296 struct scb *next_scb; 4297 struct sg_map_node *sg_map; 4298 bus_addr_t physaddr; 4299 struct ahc_dma_seg *segs; 4300 int newcount; 4301 int i; 4302 4303 scb_data = ahc->scb_data; 4304 if (scb_data->numscbs >= AHC_SCB_MAX) 4305 /* Can't allocate any more */ 4306 return; 4307 4308 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4309 4310 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4311 4312 if (sg_map == NULL) 4313 return; 4314 4315 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4316 &sg_map->sg_dmamap, 4317 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4318 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4319 "SG space") < 0) { 4320 free(sg_map, M_DEVBUF); 4321 return; 4322 } 4323 4324 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4325 4326 segs = sg_map->sg_vaddr; 4327 physaddr = sg_map->sg_physaddr; 4328 4329 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4330 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4331 int error; 4332 4333 next_scb->sg_list = segs; 4334 /* 4335 * The sequencer always starts with the second entry. 4336 * The first entry is embedded in the scb. 4337 */ 4338 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4339 next_scb->flags = SCB_FREE; 4340 error = bus_dmamap_create(ahc->parent_dmat, 4341 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4342 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4343 &next_scb->dmamap); 4344 if (error != 0) 4345 break; 4346 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4347 next_scb->hscb->tag = ahc->scb_data->numscbs; 4348 next_scb->hscb->cmdstore_busaddr = 4349 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4350 + offsetof(struct hardware_scb, cmdstore); 4351 next_scb->hscb->cmdstore_busaddr = 4352 htole32(next_scb->hscb->cmdstore_busaddr); 4353 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4354 segs += AHC_NSEG; 4355 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4356 next_scb++; 4357 ahc->scb_data->numscbs++; 4358 } 4359 #ifdef AHC_DEBUG 4360 if (ahc_debug & AHC_SHOWSCBALLOC) 4361 printf("%s: allocated %d new SCBs count now %d\n", 4362 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4363 #endif 4364 } 4365 4366 #ifdef AHC_DUMP_SEQ 4367 static void 4368 ahc_dumpseq(struct ahc_softc* ahc) 4369 { 4370 int i; 4371 int max_prog; 4372 4373 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4374 max_prog = 448; 4375 else if ((ahc->features & AHC_ULTRA2) != 0) 4376 max_prog = 768; 4377 else 4378 max_prog = 512; 4379 4380 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4381 ahc_outb(ahc, SEQADDR0, 0); 4382 ahc_outb(ahc, SEQADDR1, 0); 4383 for (i = 0; i < max_prog; i++) { 4384 u_int8_t ins_bytes[4]; 4385 4386 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4387 printf("0x%08x\n", ins_bytes[0] << 24 4388 | ins_bytes[1] << 16 4389 | ins_bytes[2] << 8 4390 | ins_bytes[3]); 4391 } 4392 } 4393 #endif 4394 4395 static void 4396 ahc_loadseq(struct ahc_softc *ahc) 4397 { 4398 struct patch *cur_patch; 4399 int i; 4400 int downloaded; 4401 int skip_addr; 4402 u_int8_t download_consts[4]; 4403 4404 /* Setup downloadable constant table */ 4405 #if 0 4406 /* No downloaded constants are currently defined. */ 4407 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4408 #endif 4409 4410 cur_patch = patches; 4411 downloaded = 0; 4412 skip_addr = 0; 4413 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4414 ahc_outb(ahc, SEQADDR0, 0); 4415 ahc_outb(ahc, SEQADDR1, 0); 4416 4417 for (i = 0; i < sizeof(seqprog)/4; i++) { 4418 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4419 /* 4420 * Don't download this instruction as it 4421 * is in a patch that was removed. 4422 */ 4423 continue; 4424 } 4425 ahc_download_instr(ahc, i, download_consts); 4426 downloaded++; 4427 } 4428 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4429 restart_sequencer(ahc); 4430 4431 #ifdef AHC_DEBUG 4432 printf(" %d instructions downloaded\n", downloaded); 4433 #endif 4434 } 4435 4436 static int 4437 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4438 int start_instr, int *skip_addr) 4439 { 4440 struct patch *cur_patch; 4441 struct patch *last_patch; 4442 int num_patches; 4443 4444 num_patches = sizeof(patches)/sizeof(struct patch); 4445 last_patch = &patches[num_patches]; 4446 cur_patch = *start_patch; 4447 4448 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4449 4450 if (cur_patch->patch_func(ahc) == 0) { 4451 4452 /* Start rejecting code */ 4453 *skip_addr = start_instr + cur_patch->skip_instr; 4454 cur_patch += cur_patch->skip_patch; 4455 } else { 4456 /* Accepted this patch. Advance to the next 4457 * one and wait for our intruction pointer to 4458 * hit this point. 4459 */ 4460 cur_patch++; 4461 } 4462 } 4463 4464 *start_patch = cur_patch; 4465 if (start_instr < *skip_addr) 4466 /* Still skipping */ 4467 return (0); 4468 4469 return (1); 4470 } 4471 4472 static void 4473 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4474 { 4475 union ins_formats instr; 4476 struct ins_format1 *fmt1_ins; 4477 struct ins_format3 *fmt3_ins; 4478 u_int opcode; 4479 4480 /* Structure copy */ 4481 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4482 4483 instr.integer = le32toh(instr.integer); 4484 4485 fmt1_ins = &instr.format1; 4486 fmt3_ins = NULL; 4487 4488 /* Pull the opcode */ 4489 opcode = instr.format1.opcode; 4490 switch (opcode) { 4491 case AIC_OP_JMP: 4492 case AIC_OP_JC: 4493 case AIC_OP_JNC: 4494 case AIC_OP_CALL: 4495 case AIC_OP_JNE: 4496 case AIC_OP_JNZ: 4497 case AIC_OP_JE: 4498 case AIC_OP_JZ: 4499 { 4500 struct patch *cur_patch; 4501 int address_offset; 4502 u_int address; 4503 int skip_addr; 4504 int i; 4505 4506 fmt3_ins = &instr.format3; 4507 address_offset = 0; 4508 address = fmt3_ins->address; 4509 cur_patch = patches; 4510 skip_addr = 0; 4511 4512 for (i = 0; i < address;) { 4513 4514 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4515 4516 if (skip_addr > i) { 4517 int end_addr; 4518 4519 end_addr = MIN(address, skip_addr); 4520 address_offset += end_addr - i; 4521 i = skip_addr; 4522 } else { 4523 i++; 4524 } 4525 } 4526 address -= address_offset; 4527 fmt3_ins->address = address; 4528 /* FALLTHROUGH */ 4529 } 4530 case AIC_OP_OR: 4531 case AIC_OP_AND: 4532 case AIC_OP_XOR: 4533 case AIC_OP_ADD: 4534 case AIC_OP_ADC: 4535 case AIC_OP_BMOV: 4536 if (fmt1_ins->parity != 0) { 4537 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4538 } 4539 fmt1_ins->parity = 0; 4540 /* FALLTHROUGH */ 4541 case AIC_OP_ROL: 4542 if ((ahc->features & AHC_ULTRA2) != 0) { 4543 int i, count; 4544 4545 /* Calculate odd parity for the instruction */ 4546 for (i = 0, count = 0; i < 31; i++) { 4547 u_int32_t mask; 4548 4549 mask = 0x01 << i; 4550 if ((instr.integer & mask) != 0) 4551 count++; 4552 } 4553 if ((count & 0x01) == 0) 4554 instr.format1.parity = 1; 4555 } else { 4556 /* Compress the instruction for older sequencers */ 4557 if (fmt3_ins != NULL) { 4558 instr.integer = 4559 fmt3_ins->immediate 4560 | (fmt3_ins->source << 8) 4561 | (fmt3_ins->address << 16) 4562 | (fmt3_ins->opcode << 25); 4563 } else { 4564 instr.integer = 4565 fmt1_ins->immediate 4566 | (fmt1_ins->source << 8) 4567 | (fmt1_ins->destination << 16) 4568 | (fmt1_ins->ret << 24) 4569 | (fmt1_ins->opcode << 25); 4570 } 4571 } 4572 instr.integer = htole32(instr.integer); 4573 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4574 break; 4575 default: 4576 panic("Unknown opcode encountered in seq program"); 4577 break; 4578 } 4579 } 4580 4581 static void 4582 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4583 { 4584 4585 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4586 struct scb *scbp; 4587 4588 scb->flags |= SCB_RECOVERY_SCB; 4589 4590 /* 4591 * Take all queued, but not sent SCBs out of the equation. 4592 * Also ensure that no new CCBs are queued to us while we 4593 * try to fix this problem. 4594 */ 4595 ahc->queue_blocked = 1; 4596 4597 /* 4598 * Go through all of our pending SCBs and remove 4599 * any scheduled timeouts for them. We will reschedule 4600 * them after we've successfully fixed this problem. 4601 */ 4602 scbp = ahc->pending_ccbs.lh_first; 4603 while (scbp != NULL) { 4604 callout_stop(&scbp->xs->xs_callout); 4605 scbp = scbp->plinks.le_next; 4606 } 4607 } 4608 } 4609 4610 static void 4611 ahc_timeout(void *arg) 4612 { 4613 struct scb *scb; 4614 struct ahc_softc *ahc; 4615 int s, found; 4616 u_int last_phase; 4617 int target; 4618 int lun; 4619 int i; 4620 char channel; 4621 4622 scb = (struct scb *)arg; 4623 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4624 4625 s = splbio(); 4626 4627 /* 4628 * Ensure that the card doesn't do anything 4629 * behind our back. Also make sure that we 4630 * didn't "just" miss an interrupt that would 4631 * affect this timeout. 4632 */ 4633 do { 4634 ahc_intr(ahc); 4635 pause_sequencer(ahc); 4636 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4637 4638 if ((scb->flags & SCB_ACTIVE) == 0) { 4639 /* Previous timeout took care of me already */ 4640 printf("Timedout SCB handled by another timeout\n"); 4641 unpause_sequencer(ahc); 4642 splx(s); 4643 return; 4644 } 4645 4646 target = SCB_TARGET(scb); 4647 channel = SCB_CHANNEL(scb); 4648 lun = SCB_LUN(scb); 4649 4650 scsi_print_addr(scb->xs->sc_link); 4651 printf("SCB %x - timed out ", scb->hscb->tag); 4652 /* 4653 * Take a snapshot of the bus state and print out 4654 * some information so we can track down driver bugs. 4655 */ 4656 last_phase = ahc_inb(ahc, LASTPHASE); 4657 4658 for (i = 0; i < num_phases; i++) { 4659 if (last_phase == phase_table[i].phase) 4660 break; 4661 } 4662 printf("%s", phase_table[i].phasemsg); 4663 4664 printf(", SEQADDR == 0x%x\n", 4665 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4666 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4667 4668 #ifdef AHC_DEBUG 4669 ahc_print_scb(scb); 4670 #endif 4671 4672 #if 0 4673 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4674 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4675 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4676 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4677 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4678 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4679 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4680 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4681 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4682 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4683 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4684 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4685 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4686 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4687 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4688 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4689 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4690 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4691 if (scb->sg_count > 0) { 4692 for (i = 0; i < scb->sg_count; i++) { 4693 printf("sg[%d] - Addr 0x%x : Length %d\n", 4694 i, 4695 le32toh(scb->sg_list[i].addr), 4696 le32toh(scb->sg_list[i].len)); 4697 } 4698 } 4699 #endif 4700 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4701 /* 4702 * Been down this road before. 4703 * Do a full bus reset. 4704 */ 4705 bus_reset: 4706 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4707 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4708 printf("%s: Issued Channel %c Bus Reset. " 4709 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4710 } else { 4711 /* 4712 * If we are a target, transition to bus free and report 4713 * the timeout. 4714 * 4715 * The target/initiator that is holding up the bus may not 4716 * be the same as the one that triggered this timeout 4717 * (different commands have different timeout lengths). 4718 * If the bus is idle and we are actiing as the initiator 4719 * for this request, queue a BDR message to the timed out 4720 * target. Otherwise, if the timed out transaction is 4721 * active: 4722 * Initiator transaction: 4723 * Stuff the message buffer with a BDR message and assert 4724 * ATN in the hopes that the target will let go of the bus 4725 * and go to the mesgout phase. If this fails, we'll 4726 * get another timeout 2 seconds later which will attempt 4727 * a bus reset. 4728 * 4729 * Target transaction: 4730 * Transition to BUS FREE and report the error. 4731 * It's good to be the target! 4732 */ 4733 u_int active_scb_index; 4734 4735 active_scb_index = ahc_inb(ahc, SCB_TAG); 4736 4737 if (last_phase != P_BUSFREE 4738 && (active_scb_index < ahc->scb_data->numscbs)) { 4739 struct scb *active_scb; 4740 4741 /* 4742 * If the active SCB is not from our device, 4743 * assume that another device is hogging the bus 4744 * and wait for it's timeout to expire before 4745 * taking additional action. 4746 */ 4747 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4748 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4749 u_int newtimeout; 4750 4751 scsi_print_addr(scb->xs->sc_link); 4752 printf("Other SCB Timeout%s", 4753 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4754 ? " again\n" : "\n"); 4755 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4756 newtimeout = MAX(active_scb->xs->timeout, 4757 scb->xs->timeout); 4758 callout_reset(&scb->xs->xs_callout, 4759 (newtimeout * hz) / 1000, 4760 ahc_timeout, scb); 4761 splx(s); 4762 return; 4763 } 4764 4765 /* It's us */ 4766 if ((scb->hscb->control & TARGET_SCB) != 0) { 4767 4768 /* 4769 * Send back any queued up transactions 4770 * and properly record the error condition. 4771 */ 4772 ahc_freeze_devq(ahc, scb->xs->sc_link); 4773 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4774 ahc_freeze_ccb(scb); 4775 ahc_done(ahc, scb); 4776 4777 /* Will clear us from the bus */ 4778 restart_sequencer(ahc); 4779 return; 4780 } 4781 4782 ahc_set_recoveryscb(ahc, active_scb); 4783 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4784 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4785 scsi_print_addr(active_scb->xs->sc_link); 4786 printf("BDR message in message buffer\n"); 4787 active_scb->flags |= SCB_DEVICE_RESET; 4788 callout_reset(&active_scb->xs->xs_callout, 4789 2 * hz, ahc_timeout, active_scb); 4790 unpause_sequencer(ahc); 4791 } else { 4792 int disconnected; 4793 4794 /* XXX Shouldn't panic. Just punt instead */ 4795 if ((scb->hscb->control & TARGET_SCB) != 0) 4796 panic("Timed-out target SCB but bus idle"); 4797 4798 if (last_phase != P_BUSFREE 4799 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4800 /* XXX What happened to the SCB? */ 4801 /* Hung target selection. Goto busfree */ 4802 printf("%s: Hung target selection\n", 4803 ahc_name(ahc)); 4804 restart_sequencer(ahc); 4805 return; 4806 } 4807 4808 if (ahc_search_qinfifo(ahc, target, channel, lun, 4809 scb->hscb->tag, ROLE_INITIATOR, 4810 /*status*/0, SEARCH_COUNT) > 0) { 4811 disconnected = FALSE; 4812 } else { 4813 disconnected = TRUE; 4814 } 4815 4816 if (disconnected) { 4817 u_int active_scb; 4818 4819 ahc_set_recoveryscb(ahc, scb); 4820 /* 4821 * Simply set the MK_MESSAGE control bit. 4822 */ 4823 scb->hscb->control |= MK_MESSAGE; 4824 scb->flags |= SCB_QUEUED_MSG 4825 | SCB_DEVICE_RESET; 4826 4827 /* 4828 * Mark the cached copy of this SCB in the 4829 * disconnected list too, so that a reconnect 4830 * at this point causes a BDR or abort. 4831 */ 4832 active_scb = ahc_inb(ahc, SCBPTR); 4833 if (ahc_search_disc_list(ahc, target, 4834 channel, lun, 4835 scb->hscb->tag, 4836 /*stop_on_first*/TRUE, 4837 /*remove*/FALSE, 4838 /*save_state*/FALSE)) { 4839 u_int scb_control; 4840 4841 scb_control = ahc_inb(ahc, SCB_CONTROL); 4842 scb_control |= MK_MESSAGE; 4843 ahc_outb(ahc, SCB_CONTROL, scb_control); 4844 } 4845 ahc_outb(ahc, SCBPTR, active_scb); 4846 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4847 /*unbusy*/TRUE); 4848 4849 /* 4850 * Actually re-queue this SCB in case we can 4851 * select the device before it reconnects. 4852 * Clear out any entries in the QINFIFO first 4853 * so we are the next SCB for this target 4854 * to run. 4855 */ 4856 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4857 channel, SCB_LUN(scb), 4858 SCB_LIST_NULL, 4859 ROLE_INITIATOR, 4860 SCB_REQUEUE, 4861 SEARCH_COMPLETE); 4862 scsi_print_addr(scb->xs->sc_link); 4863 printf("Queuing a BDR SCB\n"); 4864 ahc->qinfifo[ahc->qinfifonext++] = 4865 scb->hscb->tag; 4866 4867 bus_dmamap_sync(ahc->parent_dmat, 4868 ahc->shared_data_dmamap, 4869 QINFIFO_OFFSET * 256, 256, 4870 BUS_DMASYNC_PREWRITE); 4871 4872 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4873 ahc_outb(ahc, HNSCB_QOFF, 4874 ahc->qinfifonext); 4875 } else { 4876 ahc_outb(ahc, KERNEL_QINPOS, 4877 ahc->qinfifonext); 4878 } 4879 callout_reset(&scb->xs->xs_callout, 2 * hz, 4880 ahc_timeout, scb); 4881 unpause_sequencer(ahc); 4882 } else { 4883 /* Go "immediatly" to the bus reset */ 4884 /* This shouldn't happen */ 4885 ahc_set_recoveryscb(ahc, scb); 4886 scsi_print_addr(scb->xs->sc_link); 4887 printf("SCB %x: Immediate reset. " 4888 "Flags = 0x%x\n", scb->hscb->tag, 4889 scb->flags); 4890 goto bus_reset; 4891 } 4892 } 4893 } 4894 splx(s); 4895 } 4896 4897 static int 4898 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4899 int lun, u_int tag, role_t role, scb_flag status, 4900 ahc_search_action action) 4901 { 4902 struct scb *scbp; 4903 u_int8_t qinpos; 4904 u_int8_t qintail; 4905 int found; 4906 4907 qinpos = ahc_inb(ahc, QINPOS); 4908 qintail = ahc->qinfifonext; 4909 found = 0; 4910 4911 /* 4912 * Start with an empty queue. Entries that are not chosen 4913 * for removal will be re-added to the queue as we go. 4914 */ 4915 ahc->qinfifonext = qinpos; 4916 4917 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4918 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4919 4920 while (qinpos != qintail) { 4921 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4922 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4923 /* 4924 * We found an scb that needs to be removed. 4925 */ 4926 switch (action) { 4927 case SEARCH_COMPLETE: 4928 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4929 scbp->flags |= status; 4930 scbp->xs->error = XS_NOERROR; 4931 } 4932 ahc_freeze_ccb(scbp); 4933 ahc_done(ahc, scbp); 4934 break; 4935 case SEARCH_COUNT: 4936 ahc->qinfifo[ahc->qinfifonext++] = 4937 scbp->hscb->tag; 4938 break; 4939 case SEARCH_REMOVE: 4940 break; 4941 } 4942 found++; 4943 } else { 4944 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4945 } 4946 qinpos++; 4947 } 4948 4949 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4950 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4951 4952 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4953 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4954 } else { 4955 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4956 } 4957 4958 return (found); 4959 } 4960 4961 /* 4962 * Abort all SCBs that match the given description (target/channel/lun/tag), 4963 * setting their status to the passed in status if the status has not already 4964 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4965 * is paused before it is called. 4966 */ 4967 static int 4968 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4969 int lun, u_int tag, role_t role, int status) 4970 { 4971 struct scb *scbp; 4972 u_int active_scb; 4973 int i; 4974 int found; 4975 4976 /* restore this when we're done */ 4977 active_scb = ahc_inb(ahc, SCBPTR); 4978 4979 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4980 role, SCB_REQUEUE, SEARCH_COMPLETE); 4981 4982 /* 4983 * Search waiting for selection list. 4984 */ 4985 { 4986 u_int8_t next, prev; 4987 4988 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4989 prev = SCB_LIST_NULL; 4990 4991 while (next != SCB_LIST_NULL) { 4992 u_int8_t scb_index; 4993 4994 ahc_outb(ahc, SCBPTR, next); 4995 scb_index = ahc_inb(ahc, SCB_TAG); 4996 if (scb_index >= ahc->scb_data->numscbs) { 4997 panic("Waiting List inconsistency. " 4998 "SCB index == %d, yet numscbs == %d.", 4999 scb_index, ahc->scb_data->numscbs); 5000 } 5001 scbp = &ahc->scb_data->scbarray[scb_index]; 5002 if (ahc_match_scb(scbp, target, channel, 5003 lun, SCB_LIST_NULL, role)) { 5004 5005 next = ahc_abort_wscb(ahc, next, prev); 5006 } else { 5007 5008 prev = next; 5009 next = ahc_inb(ahc, SCB_NEXT); 5010 } 5011 } 5012 } 5013 /* 5014 * Go through the disconnected list and remove any entries we 5015 * have queued for completion, 0'ing their control byte too. 5016 * We save the active SCB and restore it ourselves, so there 5017 * is no reason for this search to restore it too. 5018 */ 5019 ahc_search_disc_list(ahc, target, channel, lun, tag, 5020 /*stop_on_first*/FALSE, /*remove*/TRUE, 5021 /*save_state*/FALSE); 5022 5023 /* 5024 * Go through the hardware SCB array looking for commands that 5025 * were active but not on any list. 5026 */ 5027 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5028 u_int scbid; 5029 5030 ahc_outb(ahc, SCBPTR, i); 5031 scbid = ahc_inb(ahc, SCB_TAG); 5032 scbp = &ahc->scb_data->scbarray[scbid]; 5033 if (scbid < ahc->scb_data->numscbs 5034 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5035 ahc_add_curscb_to_free_list(ahc); 5036 } 5037 5038 /* 5039 * Go through the pending CCB list and look for 5040 * commands for this target that are still active. 5041 * These are other tagged commands that were 5042 * disconnected when the reset occured. 5043 */ 5044 { 5045 struct scb *scb; 5046 5047 scb = ahc->pending_ccbs.lh_first; 5048 while (scb != NULL) { 5049 scbp = scb; 5050 scb = scb->plinks.le_next; 5051 if (ahc_match_scb(scbp, target, channel, 5052 lun, tag, role)) { 5053 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5054 ahcsetccbstatus(scbp->xs, status); 5055 ahc_freeze_ccb(scbp); 5056 ahc_done(ahc, scbp); 5057 found++; 5058 } 5059 } 5060 } 5061 ahc_outb(ahc, SCBPTR, active_scb); 5062 return found; 5063 } 5064 5065 static int 5066 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5067 int lun, u_int tag, int stop_on_first, int remove, 5068 int save_state) 5069 { 5070 struct scb *scbp; 5071 u_int next; 5072 u_int prev; 5073 u_int count; 5074 u_int active_scb; 5075 5076 count = 0; 5077 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5078 prev = SCB_LIST_NULL; 5079 5080 if (save_state) { 5081 /* restore this when we're done */ 5082 active_scb = ahc_inb(ahc, SCBPTR); 5083 } else 5084 /* Silence compiler */ 5085 active_scb = SCB_LIST_NULL; 5086 5087 while (next != SCB_LIST_NULL) { 5088 u_int scb_index; 5089 5090 ahc_outb(ahc, SCBPTR, next); 5091 scb_index = ahc_inb(ahc, SCB_TAG); 5092 if (scb_index >= ahc->scb_data->numscbs) { 5093 panic("Disconnected List inconsistency. " 5094 "SCB index == %d, yet numscbs == %d.", 5095 scb_index, ahc->scb_data->numscbs); 5096 } 5097 scbp = &ahc->scb_data->scbarray[scb_index]; 5098 if (ahc_match_scb(scbp, target, channel, lun, 5099 tag, ROLE_INITIATOR)) { 5100 count++; 5101 if (remove) { 5102 next = 5103 ahc_rem_scb_from_disc_list(ahc, prev, next); 5104 } else { 5105 prev = next; 5106 next = ahc_inb(ahc, SCB_NEXT); 5107 } 5108 if (stop_on_first) 5109 break; 5110 } else { 5111 prev = next; 5112 next = ahc_inb(ahc, SCB_NEXT); 5113 } 5114 } 5115 if (save_state) 5116 ahc_outb(ahc, SCBPTR, active_scb); 5117 return (count); 5118 } 5119 5120 static u_int 5121 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5122 { 5123 u_int next; 5124 5125 ahc_outb(ahc, SCBPTR, scbptr); 5126 next = ahc_inb(ahc, SCB_NEXT); 5127 5128 ahc_outb(ahc, SCB_CONTROL, 0); 5129 5130 ahc_add_curscb_to_free_list(ahc); 5131 5132 if (prev != SCB_LIST_NULL) { 5133 ahc_outb(ahc, SCBPTR, prev); 5134 ahc_outb(ahc, SCB_NEXT, next); 5135 } else 5136 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5137 5138 return (next); 5139 } 5140 5141 static void 5142 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5143 { 5144 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5145 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5146 5147 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5148 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5149 } 5150 5151 /* 5152 * Manipulate the waiting for selection list and return the 5153 * scb that follows the one that we remove. 5154 */ 5155 static u_int 5156 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5157 { 5158 u_int curscb, next; 5159 5160 /* 5161 * Select the SCB we want to abort and 5162 * pull the next pointer out of it. 5163 */ 5164 curscb = ahc_inb(ahc, SCBPTR); 5165 ahc_outb(ahc, SCBPTR, scbpos); 5166 next = ahc_inb(ahc, SCB_NEXT); 5167 5168 /* Clear the necessary fields */ 5169 ahc_outb(ahc, SCB_CONTROL, 0); 5170 5171 ahc_add_curscb_to_free_list(ahc); 5172 5173 /* update the waiting list */ 5174 if (prev == SCB_LIST_NULL) { 5175 /* First in the list */ 5176 ahc_outb(ahc, WAITING_SCBH, next); 5177 5178 /* 5179 * Ensure we aren't attempting to perform 5180 * selection for this entry. 5181 */ 5182 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5183 } else { 5184 /* 5185 * Select the scb that pointed to us 5186 * and update its next pointer. 5187 */ 5188 ahc_outb(ahc, SCBPTR, prev); 5189 ahc_outb(ahc, SCB_NEXT, next); 5190 } 5191 5192 /* 5193 * Point us back at the original scb position. 5194 */ 5195 ahc_outb(ahc, SCBPTR, curscb); 5196 return next; 5197 } 5198 5199 static void 5200 ahc_clear_intstat(struct ahc_softc *ahc) 5201 { 5202 /* Clear any interrupt conditions this may have caused */ 5203 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5204 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5205 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5206 CLRREQINIT); 5207 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5208 } 5209 5210 static void 5211 ahc_reset_current_bus(struct ahc_softc *ahc) 5212 { 5213 u_int8_t scsiseq; 5214 5215 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5216 scsiseq = ahc_inb(ahc, SCSISEQ); 5217 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5218 DELAY(AHC_BUSRESET_DELAY); 5219 /* Turn off the bus reset */ 5220 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5221 5222 ahc_clear_intstat(ahc); 5223 5224 /* Re-enable reset interrupts */ 5225 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5226 } 5227 5228 static int 5229 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5230 { 5231 u_int initiator, target, max_scsiid; 5232 u_int sblkctl; 5233 u_int our_id; 5234 int found; 5235 int restart_needed; 5236 char cur_channel; 5237 5238 ahc->pending_device = NULL; 5239 5240 pause_sequencer(ahc); 5241 5242 /* 5243 * Run our command complete fifos to ensure that we perform 5244 * completion processing on any commands that 'completed' 5245 * before the reset occurred. 5246 */ 5247 ahc_run_qoutfifo(ahc); 5248 5249 /* 5250 * Reset the bus if we are initiating this reset 5251 */ 5252 sblkctl = ahc_inb(ahc, SBLKCTL); 5253 cur_channel = 'A'; 5254 if ((ahc->features & AHC_TWIN) != 0 5255 && ((sblkctl & SELBUSB) != 0)) 5256 cur_channel = 'B'; 5257 if (cur_channel != channel) { 5258 /* Case 1: Command for another bus is active 5259 * Stealthily reset the other bus without 5260 * upsetting the current bus. 5261 */ 5262 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5263 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5264 ahc_outb(ahc, SCSISEQ, 5265 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5266 if (initiate_reset) 5267 ahc_reset_current_bus(ahc); 5268 ahc_clear_intstat(ahc); 5269 ahc_outb(ahc, SBLKCTL, sblkctl); 5270 restart_needed = FALSE; 5271 } else { 5272 /* Case 2: A command from this bus is active or we're idle */ 5273 ahc_clear_msg_state(ahc); 5274 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5275 ahc_outb(ahc, SCSISEQ, 5276 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5277 if (initiate_reset) 5278 ahc_reset_current_bus(ahc); 5279 ahc_clear_intstat(ahc); 5280 5281 /* 5282 * Since we are going to restart the sequencer, avoid 5283 * a race in the sequencer that could cause corruption 5284 * of our Q pointers by starting over from index 0. 5285 */ 5286 ahc->qoutfifonext = 0; 5287 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5288 ahc_outb(ahc, SDSCB_QOFF, 0); 5289 else 5290 ahc_outb(ahc, QOUTPOS, 0); 5291 restart_needed = TRUE; 5292 } 5293 5294 /* 5295 * Clean up all the state information for the 5296 * pending transactions on this bus. 5297 */ 5298 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5299 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5300 ROLE_UNKNOWN, XS_RESET); 5301 if (channel == 'B') { 5302 our_id = ahc->our_id_b; 5303 } else { 5304 our_id = ahc->our_id; 5305 } 5306 5307 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5308 5309 /* 5310 * Revert to async/narrow transfers until we renegotiate. 5311 */ 5312 for (target = 0; target <= max_scsiid; target++) { 5313 5314 if (ahc->enabled_targets[target] == NULL) 5315 continue; 5316 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5317 struct ahc_devinfo devinfo; 5318 5319 ahc_compile_devinfo(&devinfo, target, initiator, 5320 AHC_LUN_WILDCARD, 5321 channel, ROLE_UNKNOWN); 5322 ahc_set_width(ahc, &devinfo, 5323 MSG_EXT_WDTR_BUS_8_BIT, 5324 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5325 ahc_set_syncrate(ahc, &devinfo, 5326 /*syncrate*/NULL, /*period*/0, 5327 /*offset*/0, AHC_TRANS_CUR, 5328 /*paused*/TRUE, FALSE); 5329 } 5330 } 5331 5332 if (restart_needed) 5333 restart_sequencer(ahc); 5334 else 5335 unpause_sequencer(ahc); 5336 return found; 5337 } 5338 5339 static int 5340 ahc_match_scb(struct scb *scb, int target, char channel, 5341 int lun, u_int tag, role_t role) 5342 { 5343 int targ = SCB_TARGET(scb); 5344 char chan = SCB_CHANNEL(scb); 5345 int slun = SCB_LUN(scb); 5346 int match; 5347 5348 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5349 if (match != 0) 5350 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5351 if (match != 0) 5352 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5353 5354 return match; 5355 } 5356 5357 static void 5358 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5359 { 5360 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5361 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5362 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5363 ahc->msgout_buf[ahc->msgout_index++] = period; 5364 ahc->msgout_buf[ahc->msgout_index++] = offset; 5365 ahc->msgout_len += 5; 5366 } 5367 5368 static void 5369 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5370 { 5371 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5372 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5373 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5374 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5375 ahc->msgout_len += 4; 5376 } 5377 5378 static void 5379 ahc_calc_residual(struct scb *scb) 5380 { 5381 struct hardware_scb *hscb; 5382 5383 hscb = scb->hscb; 5384 5385 /* 5386 * If the disconnected flag is still set, this is bogus 5387 * residual information left over from a sequencer 5388 * pagin/pageout, so ignore this case. 5389 */ 5390 if ((scb->hscb->control & DISCONNECTED) == 0) { 5391 u_int32_t resid; 5392 int resid_sgs; 5393 int sg; 5394 5395 /* 5396 * Remainder of the SG where the transfer 5397 * stopped. 5398 */ 5399 resid = (hscb->residual_data_count[2] << 16) 5400 | (hscb->residual_data_count[1] <<8) 5401 | (hscb->residual_data_count[0]); 5402 5403 /* 5404 * Add up the contents of all residual 5405 * SG segments that are after the SG where 5406 * the transfer stopped. 5407 */ 5408 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5409 sg = scb->sg_count - resid_sgs; 5410 while (resid_sgs > 0) { 5411 5412 resid += le32toh(scb->sg_list[sg].len); 5413 sg++; 5414 resid_sgs--; 5415 } 5416 scb->xs->resid = resid; 5417 } 5418 5419 /* 5420 * Clean out the residual information in this SCB for its 5421 * next consumer. 5422 */ 5423 hscb->residual_SG_count = 0; 5424 5425 #ifdef AHC_DEBUG 5426 if (ahc_debug & AHC_SHOWMISC) { 5427 scsi_print_addr(scb->xs->sc_link); 5428 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5429 } 5430 #endif 5431 } 5432 5433 static void 5434 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5435 { 5436 struct scb *scb; 5437 int pending_ccb_count; 5438 int i; 5439 u_int saved_scbptr; 5440 5441 /* 5442 * Traverse the pending SCB list and ensure that all of the 5443 * SCBs there have the proper settings. 5444 */ 5445 scb = LIST_FIRST(&ahc->pending_ccbs); 5446 pending_ccb_count = 0; 5447 while (scb != NULL) { 5448 struct ahc_devinfo devinfo; 5449 struct scsipi_xfer *xs; 5450 struct scb *pending_scb; 5451 struct hardware_scb *pending_hscb; 5452 struct ahc_initiator_tinfo *tinfo; 5453 struct tmode_tstate *tstate; 5454 u_int our_id, remote_id; 5455 5456 xs = scb->xs; 5457 pending_scb = scb; 5458 pending_hscb = pending_scb->hscb; 5459 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5460 ? ahc->our_id_b : ahc->our_id; 5461 remote_id = xs->sc_link->scsipi_scsi.target; 5462 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5463 SCB_LUN(pending_scb), 5464 SCB_CHANNEL(pending_scb), 5465 ROLE_UNKNOWN); 5466 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5467 our_id, remote_id, &tstate); 5468 pending_hscb->control &= ~ULTRAENB; 5469 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5470 pending_hscb->control |= ULTRAENB; 5471 pending_hscb->scsirate = tinfo->scsirate; 5472 pending_hscb->scsioffset = tinfo->current.offset; 5473 pending_ccb_count++; 5474 scb = LIST_NEXT(scb, plinks); 5475 } 5476 5477 if (pending_ccb_count == 0) 5478 return; 5479 5480 saved_scbptr = ahc_inb(ahc, SCBPTR); 5481 /* Ensure that the hscbs down on the card match the new information */ 5482 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5483 u_int scb_tag; 5484 5485 ahc_outb(ahc, SCBPTR, i); 5486 scb_tag = ahc_inb(ahc, SCB_TAG); 5487 if (scb_tag != SCB_LIST_NULL) { 5488 struct ahc_devinfo devinfo; 5489 struct scb *pending_scb; 5490 struct scsipi_xfer *xs; 5491 struct hardware_scb *pending_hscb; 5492 struct ahc_initiator_tinfo *tinfo; 5493 struct tmode_tstate *tstate; 5494 u_int our_id, remote_id; 5495 u_int control; 5496 5497 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5498 if (pending_scb->flags == SCB_FREE) 5499 continue; 5500 pending_hscb = pending_scb->hscb; 5501 xs = pending_scb->xs; 5502 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5503 ? ahc->our_id_b : ahc->our_id; 5504 remote_id = xs->sc_link->scsipi_scsi.target; 5505 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5506 SCB_LUN(pending_scb), 5507 SCB_CHANNEL(pending_scb), 5508 ROLE_UNKNOWN); 5509 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5510 our_id, remote_id, &tstate); 5511 control = ahc_inb(ahc, SCB_CONTROL); 5512 control &= ~ULTRAENB; 5513 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5514 control |= ULTRAENB; 5515 ahc_outb(ahc, SCB_CONTROL, control); 5516 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5517 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5518 } 5519 } 5520 ahc_outb(ahc, SCBPTR, saved_scbptr); 5521 } 5522 5523 #if UNUSED 5524 static void 5525 ahc_dump_targcmd(struct target_cmd *cmd) 5526 { 5527 u_int8_t *byte; 5528 u_int8_t *last_byte; 5529 int i; 5530 5531 byte = &cmd->initiator_channel; 5532 /* Debugging info for received commands */ 5533 last_byte = &cmd[1].initiator_channel; 5534 5535 i = 0; 5536 while (byte < last_byte) { 5537 if (i == 0) 5538 printf("\t"); 5539 printf("%#x", *byte++); 5540 i++; 5541 if (i == 8) { 5542 printf("\n"); 5543 i = 0; 5544 } else { 5545 printf(", "); 5546 } 5547 } 5548 } 5549 #endif 5550 5551 static void 5552 ahc_shutdown(void *arg) 5553 { 5554 struct ahc_softc *ahc; 5555 int i; 5556 u_int sxfrctl1_a, sxfrctl1_b; 5557 5558 ahc = (struct ahc_softc *)arg; 5559 5560 pause_sequencer(ahc); 5561 5562 /* 5563 * Preserve the value of the SXFRCTL1 register for all channels. 5564 * It contains settings that affect termination and we don't want 5565 * to disturb the integrity of the bus during shutdown in case 5566 * we are in a multi-initiator setup. 5567 */ 5568 sxfrctl1_b = 0; 5569 if ((ahc->features & AHC_TWIN) != 0) { 5570 u_int sblkctl; 5571 5572 sblkctl = ahc_inb(ahc, SBLKCTL); 5573 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5574 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5575 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5576 } 5577 5578 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5579 5580 /* This will reset most registers to 0, but not all */ 5581 ahc_reset(ahc); 5582 5583 if ((ahc->features & AHC_TWIN) != 0) { 5584 u_int sblkctl; 5585 5586 sblkctl = ahc_inb(ahc, SBLKCTL); 5587 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5588 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5589 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5590 } 5591 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5592 5593 ahc_outb(ahc, SCSISEQ, 0); 5594 ahc_outb(ahc, SXFRCTL0, 0); 5595 ahc_outb(ahc, DSPCISTATUS, 0); 5596 5597 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5598 ahc_outb(ahc, i, 0); 5599 } 5600 5601 #if defined(AHC_DEBUG) && 0 5602 static void 5603 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5604 { 5605 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5606 5607 printf("\tcurrent:\n"); 5608 printf("\t\twidth %u period %u offset %u flags %x\n", 5609 tinfo->current.width, tinfo->current.period, 5610 tinfo->current.offset, tinfo->current.ppr_flags); 5611 5612 printf("\tgoal:\n"); 5613 printf("\t\twidth %u period %u offset %u flags %x\n", 5614 tinfo->goal.width, tinfo->goal.period, 5615 tinfo->goal.offset, tinfo->goal.ppr_flags); 5616 5617 printf("\tuser:\n"); 5618 printf("\t\twidth %u period %u offset %u flags %x\n", 5619 tinfo->user.width, tinfo->user.period, 5620 tinfo->user.offset, tinfo->user.ppr_flags); 5621 } 5622 #endif 5623 5624 static void 5625 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5626 { 5627 struct scsipi_inquiry_data *inq; 5628 struct ahc_devinfo devinfo; 5629 struct tmode_tstate *tstate; 5630 int target_id, our_id; 5631 char channel; 5632 5633 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5634 return; 5635 5636 if (xs->sc_link->quirks & SDEV_NOTAG) 5637 return; 5638 5639 target_id = xs->sc_link->scsipi_scsi.target; 5640 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5641 channel = SIM_CHANNEL(ahc, xs->sc_link); 5642 5643 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5644 ahc_compile_devinfo(&devinfo, our_id, target_id, 5645 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5646 5647 if (tstate->tagdisable & devinfo.target_mask) 5648 return; 5649 5650 /* 5651 * Sneak a look at the results of the SCSI Inquiry 5652 * command and see if we can do Tagged queing. This 5653 * should really be done by the higher level drivers. 5654 */ 5655 inq = (struct scsipi_inquiry_data *)xs->data; 5656 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5657 printf("%s: target %d using tagged queuing\n", 5658 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5659 5660 ahc_set_tags(ahc, &devinfo, TRUE); 5661 5662 if (ahc->scb_data->maxhscbs >= 16 || 5663 (ahc->flags & AHC_PAGESCBS)) { 5664 /* Default to 16 tags */ 5665 xs->sc_link->openings = 16; 5666 } else { 5667 /* 5668 * Default to 4 tags on whimpy 5669 * cards that don't have much SCB 5670 * space and can't page. This prevents 5671 * a single device from hogging all 5672 * slots. We should really have a better 5673 * way of providing fairness. 5674 */ 5675 xs->sc_link->openings = 4; 5676 } 5677 } 5678 } 5679 5680 static int 5681 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5682 int nocmdcheck) 5683 { 5684 char channel; 5685 u_int our_id, target; 5686 struct tmode_tstate *tstate; 5687 struct ahc_devinfo devinfo; 5688 5689 if (xs->sc_link->quirks & SDEV_NOTAG) 5690 return 0; 5691 5692 /* 5693 * XXX never do these commands with tags. Should really be 5694 * in a higher layer. 5695 */ 5696 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5697 xs->cmd->opcode == TEST_UNIT_READY || 5698 xs->cmd->opcode == REQUEST_SENSE)) 5699 return 0; 5700 5701 channel = SIM_CHANNEL(ahc, xs->sc_link); 5702 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5703 target = xs->sc_link->scsipi_scsi.target; 5704 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5705 5706 ahc_compile_devinfo(&devinfo, our_id, target, 5707 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5708 5709 return (tstate->tagenable & devinfo.target_mask); 5710 } 5711
Indexes created Wed Oct 01 15:09:59 GMT 2025