aic7xxx.c revision 1.55
1 /* $NetBSD: aic7xxx.c,v 1.55 2000/06/04 11:42:55 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 #include <sys/scsiio.h> 99 100 #include <machine/bus.h> 101 #include <machine/intr.h> 102 103 #include <dev/scsipi/scsi_all.h> 104 #include <dev/scsipi/scsipi_all.h> 105 #include <dev/scsipi/scsi_message.h> 106 #include <dev/scsipi/scsipi_debug.h> 107 #include <dev/scsipi/scsiconf.h> 108 109 #include <vm/vm.h> 110 #include <vm/vm_param.h> 111 #include <vm/pmap.h> 112 113 #include <dev/ic/aic7xxxvar.h> 114 #include <dev/microcode/aic7xxx/sequencer.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 116 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 117 118 #define XS_STS_DEBUG 0x00000002 119 120 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 121 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 122 #define ALL_CHANNELS '\0' 123 #define ALL_TARGETS_MASK 0xFFFF 124 #define INITIATOR_WILDCARD (~0) 125 126 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 127 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 128 #define SIM_CHANNEL(ahc, sc_link) \ 129 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 130 #define SIM_SCSI_ID(ahc, sc_link) \ 131 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 132 #define SCB_IS_SCSIBUS_B(scb) \ 133 (((scb)->hscb->tcl & SELBUSB) != 0) 134 #define SCB_TARGET(scb) \ 135 (((scb)->hscb->tcl & TID) >> 4) 136 #define SCB_CHANNEL(scb) \ 137 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 138 #define SCB_LUN(scb) \ 139 ((scb)->hscb->tcl & LID) 140 #define SCB_TARGET_OFFSET(scb) \ 141 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 142 #define SCB_TARGET_MASK(scb) \ 143 (0x01 << (SCB_TARGET_OFFSET(scb))) 144 #define TCL_CHANNEL(ahc, tcl) \ 145 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 146 #define TCL_SCSI_ID(ahc, tcl) \ 147 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 148 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 149 #define TCL_LUN(tcl) ((tcl) & LID) 150 151 #define XS_TCL(ahc, xs) \ 152 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 153 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 154 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 155 156 char *ahc_chip_names[] = 157 { 158 "NONE", 159 "aic7770", 160 "aic7850", 161 "aic7855", 162 "aic7859", 163 "aic7860", 164 "aic7870", 165 "aic7880", 166 "aic7890/91", 167 "aic7892", 168 "aic7895", 169 "aic7896/97", 170 "aic7899" 171 }; 172 173 typedef enum { 174 ROLE_UNKNOWN, 175 ROLE_INITIATOR, 176 ROLE_TARGET 177 } role_t; 178 179 struct ahc_devinfo { 180 int our_scsiid; 181 int target_offset; 182 u_int16_t target_mask; 183 u_int8_t target; 184 u_int8_t lun; 185 char channel; 186 role_t role; /* 187 * Only guaranteed to be correct if not 188 * in the busfree state. 189 */ 190 }; 191 192 typedef enum { 193 SEARCH_COMPLETE, 194 SEARCH_COUNT, 195 SEARCH_REMOVE 196 } ahc_search_action; 197 198 #ifdef AHC_DEBUG 199 static int ahc_debug = AHC_DEBUG; 200 #endif 201 202 static int ahcinitscbdata(struct ahc_softc *); 203 static void ahcfiniscbdata(struct ahc_softc *); 204 205 #if UNUSED 206 static void ahc_dump_targcmd(struct target_cmd *); 207 #endif 208 static void ahc_shutdown(void *arg); 209 static int32_t ahc_action(struct scsipi_xfer *); 210 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 211 struct proc *); 212 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 213 static int ahc_poll(struct ahc_softc *, int); 214 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 215 struct scb *); 216 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 217 static void ahcallocscbs(struct ahc_softc *); 218 #if UNUSED 219 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 220 struct scb *); 221 #endif 222 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 223 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 224 char, role_t); 225 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 226 static void ahc_done(struct ahc_softc *, struct scb *); 227 static struct tmode_tstate * 228 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 229 #if UNUSED 230 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 231 #endif 232 static void ahc_handle_seqint(struct ahc_softc *, u_int); 233 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 234 static void ahc_build_transfer_msg(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_setup_initiator_msgout(struct ahc_softc *, 237 struct ahc_devinfo *, 238 struct scb *); 239 static void ahc_setup_target_msgin(struct ahc_softc *, 240 struct ahc_devinfo *); 241 static void ahc_clear_msg_state(struct ahc_softc *); 242 static void ahc_handle_message_phase(struct ahc_softc *, 243 struct scsipi_link *); 244 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 245 246 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 247 struct ahc_devinfo *); 248 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 249 struct ahc_devinfo *); 250 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 251 int, char *, int); 252 #ifdef AHC_DUMP_SEQ 253 static void ahc_dumpseq(struct ahc_softc *); 254 #endif 255 static void ahc_loadseq(struct ahc_softc *); 256 static int ahc_check_patch(struct ahc_softc *, struct patch **, 257 int, int *); 258 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 259 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 260 #if defined(AHC_DEBUG) 261 static void ahc_print_scb(struct scb *); 262 #endif 263 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 264 role_t, scb_flag, ahc_search_action); 265 static int ahc_reset_channel(struct ahc_softc *, char, int); 266 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 267 role_t, int); 268 static int ahc_search_disc_list(struct ahc_softc *, int, 269 char, int, u_int, int, int, int); 270 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 271 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 272 static void ahc_clear_intstat(struct ahc_softc *); 273 static void ahc_reset_current_bus(struct ahc_softc *); 274 static struct ahc_syncrate * 275 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 276 static struct ahc_syncrate * 277 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 278 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 279 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 280 u_int *, int); 281 static void ahc_update_target_msg_request(struct ahc_softc *, 282 struct ahc_devinfo *, 283 struct ahc_initiator_tinfo *, 284 int, int); 285 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 286 struct ahc_syncrate *, u_int, u_int, u_int, 287 int, int); 288 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 289 u_int, u_int, int, int); 290 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 291 int); 292 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 293 294 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 295 296 static void ahc_calc_residual(struct scb *); 297 298 static void ahc_update_pending_syncrates(struct ahc_softc *); 299 300 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 301 302 static void ahc_timeout (void *); 303 static __inline int sequencer_paused(struct ahc_softc *); 304 static __inline void pause_sequencer(struct ahc_softc *); 305 static __inline void unpause_sequencer(struct ahc_softc *); 306 static void restart_sequencer(struct ahc_softc *); 307 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 308 309 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 310 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 311 312 static __inline void ahc_freeze_ccb(struct scb *); 313 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 314 static void ahc_run_qoutfifo(struct ahc_softc *); 315 316 static __inline struct ahc_initiator_tinfo * 317 ahc_fetch_transinfo(struct ahc_softc *, 318 char, u_int, u_int, 319 struct tmode_tstate **); 320 static void ahcfreescb(struct ahc_softc *, struct scb *); 321 static __inline struct scb *ahcgetscb(struct ahc_softc *); 322 323 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 324 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 325 int *, const char *, const char *); 326 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 327 caddr_t, bus_dma_segment_t *, int); 328 static void ahcminphys(struct buf *); 329 330 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 331 static __inline void ahc_swap_hscb(struct hardware_scb *); 332 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 333 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 334 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 335 336 #if defined(AHC_DEBUG) && 0 337 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 338 #endif 339 340 static struct scsipi_device ahc_dev = 341 { 342 NULL, /* Use default error handler */ 343 NULL, /* have a queue, served by this */ 344 NULL, /* have no async handler */ 345 NULL, /* Use default 'done' routine */ 346 }; 347 348 /* 349 * Pick the first xs for a non-blocked target. 350 */ 351 static __inline struct scsipi_xfer * 352 ahc_first_xs(struct ahc_softc *ahc) 353 { 354 int target; 355 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 356 357 if (ahc->queue_blocked) 358 return NULL; 359 360 while (xs != NULL) { 361 target = xs->sc_link->scsipi_scsi.target; 362 if (ahc->devqueue_blocked[target] == 0 && 363 (ahc_istagged_device(ahc, xs, 0) || 364 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 365 SCB_LIST_NULL)) 366 break; 367 xs = TAILQ_NEXT(xs, adapter_q); 368 } 369 370 return xs; 371 } 372 373 static __inline void 374 ahc_swap_hscb(struct hardware_scb *hscb) 375 { 376 hscb->SG_pointer = htole32(hscb->SG_pointer); 377 hscb->data = htole32(hscb->data); 378 hscb->datalen = htole32(hscb->datalen); 379 /* 380 * No need to swap cmdpointer; it's either 0 or set to 381 * cmdstore_busaddr, which is already swapped. 382 */ 383 } 384 385 static __inline void 386 ahc_swap_sg(struct ahc_dma_seg *sg) 387 { 388 sg->addr = htole32(sg->addr); 389 sg->len = htole32(sg->len); 390 } 391 392 static void 393 ahcminphys(bp) 394 struct buf *bp; 395 { 396 /* 397 * Even though the card can transfer up to 16megs per command 398 * we are limited by the number of segments in the dma segment 399 * list that we can hold. The worst case is that all pages are 400 * discontinuous physically, hense the "page per segment" limit 401 * enforced here. 402 */ 403 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 404 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 405 } 406 minphys(bp); 407 } 408 409 410 static __inline u_int32_t 411 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 412 { 413 return (ahc->scb_data->hscb_busaddr 414 + (sizeof(struct hardware_scb) * index)); 415 } 416 417 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 418 419 static __inline int 420 sequencer_paused(struct ahc_softc *ahc) 421 { 422 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 423 } 424 425 static __inline void 426 pause_sequencer(struct ahc_softc *ahc) 427 { 428 ahc_outb(ahc, HCNTRL, ahc->pause); 429 430 /* 431 * Since the sequencer can disable pausing in a critical section, we 432 * must loop until it actually stops. 433 */ 434 while (sequencer_paused(ahc) == 0) 435 ; 436 } 437 438 static __inline void 439 unpause_sequencer(struct ahc_softc *ahc) 440 { 441 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 442 ahc_outb(ahc, HCNTRL, ahc->unpause); 443 } 444 445 /* 446 * Restart the sequencer program from address zero 447 */ 448 static void 449 restart_sequencer(struct ahc_softc *ahc) 450 { 451 u_int i; 452 453 pause_sequencer(ahc); 454 455 /* 456 * Everytime we restart the sequencer, there 457 * is the possiblitity that we have restarted 458 * within a three instruction window where an 459 * SCB has been marked free but has not made it 460 * onto the free list. Since SCSI events(bus reset, 461 * unexpected bus free) will always freeze the 462 * sequencer, we cannot close this window. To 463 * avoid losing an SCB, we reconsitute the free 464 * list every time we restart the sequencer. 465 */ 466 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 467 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 468 469 ahc_outb(ahc, SCBPTR, i); 470 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 471 ahc_add_curscb_to_free_list(ahc); 472 } 473 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 474 unpause_sequencer(ahc); 475 } 476 477 static __inline u_int 478 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 479 { 480 u_int scbid; 481 482 scbid = ahc->untagged_scbs[tcl]; 483 if (unbusy) { 484 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 485 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 486 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 487 } 488 489 return (scbid); 490 } 491 492 static __inline void 493 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 494 { 495 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 496 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 497 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 498 } 499 500 static __inline int 501 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 502 { 503 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 504 } 505 506 static __inline void 507 ahc_freeze_ccb(struct scb *scb) 508 { 509 struct scsipi_xfer *xs = scb->xs; 510 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 511 int target; 512 513 target = xs->sc_link->scsipi_scsi.target; 514 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 515 ahc->devqueue_blocked[target]++; 516 scb->flags |= SCB_FREEZE_QUEUE; 517 } 518 } 519 520 static __inline void 521 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 522 { 523 xs->error = status; 524 } 525 526 static __inline struct ahc_initiator_tinfo * 527 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 528 u_int remote_id, struct tmode_tstate **tstate) 529 { 530 /* 531 * Transfer data structures are stored from the perspective 532 * of the target role. Since the parameters for a connection 533 * in the initiator role to a given target are the same as 534 * when the roles are reversed, we pretend we are the target. 535 */ 536 if (channel == 'B') 537 our_id += 8; 538 *tstate = ahc->enabled_targets[our_id]; 539 return (&(*tstate)->transinfo[remote_id]); 540 } 541 542 static void 543 ahc_run_qoutfifo(struct ahc_softc *ahc) 544 { 545 struct scb *scb; 546 u_int scb_index; 547 548 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 549 256, BUS_DMASYNC_POSTREAD); 550 551 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 552 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 553 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 554 555 scb = &ahc->scb_data->scbarray[scb_index]; 556 if (scb_index >= ahc->scb_data->numscbs 557 || (scb->flags & SCB_ACTIVE) == 0) { 558 printf("%s: WARNING no command for scb %d " 559 "(cmdcmplt)\nQOUTPOS = %d\n", 560 ahc_name(ahc), scb_index, 561 ahc->qoutfifonext - 1); 562 continue; 563 } 564 565 /* 566 * Save off the residual 567 * if there is one. 568 */ 569 if (scb->hscb->residual_SG_count != 0) 570 ahc_calc_residual(scb); 571 else 572 scb->xs->resid = 0; 573 #ifdef AHC_DEBUG 574 if (ahc_debug & AHC_SHOWSCBS) { 575 scsi_print_addr(scb->xs->sc_link); 576 printf("run_qoutfifo: SCB %x complete\n", 577 scb->hscb->tag); 578 } 579 #endif 580 ahc_done(ahc, scb); 581 } 582 } 583 584 585 /* 586 * An scb (and hence an scb entry on the board) is put onto the 587 * free list. 588 */ 589 static void 590 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 591 { 592 struct hardware_scb *hscb; 593 int opri; 594 595 hscb = scb->hscb; 596 597 #ifdef AHC_DEBUG 598 if (ahc_debug & AHC_SHOWSCBALLOC) 599 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 600 #endif 601 602 opri = splbio(); 603 604 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 605 (scb->flags & SCB_RECOVERY_SCB) != 0) { 606 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 607 ahc->queue_blocked = 0; 608 } 609 610 /* Clean up for the next user */ 611 scb->flags = SCB_FREE; 612 hscb->control = 0; 613 hscb->status = 0; 614 615 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 616 617 splx(opri); 618 } 619 620 /* 621 * Get a free scb, either one already assigned to a hardware slot 622 * on the adapter or one that will require an SCB to be paged out before 623 * use. If there are none, see if we can allocate a new SCB. Otherwise 624 * either return an error or sleep. 625 */ 626 static __inline struct scb * 627 ahcgetscb(struct ahc_softc *ahc) 628 { 629 struct scb *scbp; 630 int opri;; 631 632 opri = splbio(); 633 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 634 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 635 } else { 636 ahcallocscbs(ahc); 637 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 638 if (scbp != NULL) 639 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 640 } 641 642 splx(opri); 643 644 #ifdef AHC_DEBUG 645 if (ahc_debug & AHC_SHOWSCBALLOC) { 646 if (scbp != NULL) 647 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 648 scbp->hscb->tag); 649 else 650 printf("%s: failed to allocate new SCB\n", 651 ahc_name(ahc)); 652 } 653 #endif 654 655 return (scbp); 656 } 657 658 static int 659 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 660 bus_dma_tag_t tag; 661 int size; 662 int flags; 663 bus_dmamap_t *mapp; 664 caddr_t *vaddr; 665 bus_addr_t *baddr; 666 bus_dma_segment_t *seg; 667 int *nseg; 668 const char *myname, *what; 669 { 670 int error, level = 0; 671 672 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 673 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 674 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 675 myname, what, error); 676 goto out; 677 } 678 level++; 679 680 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 681 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 682 printf("%s: failed to map DMA mem for %s, error = %d\n", 683 myname, what, error); 684 goto out; 685 } 686 level++; 687 688 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 689 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 690 printf("%s: failed to create DMA map for %s, error = %d\n", 691 myname, what, error); 692 goto out; 693 } 694 level++; 695 696 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 697 BUS_DMA_NOWAIT)) != 0) { 698 printf("%s: failed to load DMA map for %s, error = %d\n", 699 myname, what, error); 700 goto out; 701 } 702 703 *baddr = (*mapp)->dm_segs[0].ds_addr; 704 705 #ifdef AHC_DEBUG 706 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 707 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 708 *nseg, size); 709 #endif 710 711 return 0; 712 out: 713 switch (level) { 714 case 3: 715 bus_dmamap_destroy(tag, *mapp); 716 /* FALLTHROUGH */ 717 case 2: 718 bus_dmamem_unmap(tag, *vaddr, size); 719 /* FALLTHROUGH */ 720 case 1: 721 bus_dmamem_free(tag, seg, *nseg); 722 break; 723 default: 724 break; 725 } 726 727 return error; 728 } 729 730 static void 731 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 732 bus_dma_tag_t tag; 733 int size; 734 bus_dmamap_t map; 735 caddr_t vaddr; 736 bus_dma_segment_t *seg; 737 int nseg; 738 { 739 740 bus_dmamap_unload(tag, map); 741 bus_dmamap_destroy(tag, map); 742 bus_dmamem_unmap(tag, vaddr, size); 743 bus_dmamem_free(tag, seg, nseg); 744 } 745 746 char * 747 ahc_name(struct ahc_softc *ahc) 748 { 749 return (ahc->sc_dev.dv_xname); 750 } 751 752 #ifdef AHC_DEBUG 753 static void 754 ahc_print_scb(struct scb *scb) 755 { 756 struct hardware_scb *hscb = scb->hscb; 757 758 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 759 scb, 760 hscb->tag, 761 hscb->control, 762 hscb->tcl, 763 hscb->cmdlen, 764 (unsigned long)le32toh(hscb->cmdpointer)); 765 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 766 le32toh(hscb->datalen), 767 (unsigned long)(le32toh(hscb->data)), 768 hscb->SG_count, 769 (unsigned long)(le32toh(hscb->SG_pointer))); 770 printf(" sg_addr:%lx sg_len:%lu\n", 771 (unsigned long)(le32toh(scb->sg_list[0].addr)), 772 (unsigned long)(le32toh(scb->sg_list[0].len))); 773 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 774 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 775 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 776 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 777 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 778 } 779 #endif 780 781 static struct { 782 u_int8_t errno; 783 char *errmesg; 784 } hard_error[] = { 785 { ILLHADDR, "Illegal Host Access" }, 786 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 787 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 788 { SQPARERR, "Sequencer Parity Error" }, 789 { DPARERR, "Data-path Parity Error" }, 790 { MPARERR, "Scratch or SCB Memory Parity Error" }, 791 { PCIERRSTAT, "PCI Error detected" }, 792 { CIOPARERR, "CIOBUS Parity Error" }, 793 }; 794 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 795 796 static struct { 797 u_int8_t phase; 798 u_int8_t mesg_out; /* Message response to parity errors */ 799 char *phasemsg; 800 } phase_table[] = { 801 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 802 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 803 { P_COMMAND, MSG_NOOP, "in Command phase" }, 804 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 805 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 806 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 807 { P_BUSFREE, MSG_NOOP, "while idle" }, 808 { 0, MSG_NOOP, "in unknown phase" } 809 }; 810 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 811 812 /* 813 * Valid SCSIRATE values. (p. 3-17) 814 * Provides a mapping of tranfer periods in ns to the proper value to 815 * stick in the scsiscfr reg to use that transfer rate. 816 */ 817 #define AHC_SYNCRATE_DT 0 818 #define AHC_SYNCRATE_ULTRA2 1 819 #define AHC_SYNCRATE_ULTRA 3 820 #define AHC_SYNCRATE_FAST 6 821 static struct ahc_syncrate ahc_syncrates[] = { 822 /* ultra2 fast/ultra period rate */ 823 { 0x42, 0x000, 9, "80.0" }, 824 { 0x03, 0x000, 10, "40.0" }, 825 { 0x04, 0x000, 11, "33.0" }, 826 { 0x05, 0x100, 12, "20.0" }, 827 { 0x06, 0x110, 15, "16.0" }, 828 { 0x07, 0x120, 18, "13.4" }, 829 { 0x08, 0x000, 25, "10.0" }, 830 { 0x19, 0x010, 31, "8.0" }, 831 { 0x1a, 0x020, 37, "6.67" }, 832 { 0x1b, 0x030, 43, "5.7" }, 833 { 0x1c, 0x040, 50, "5.0" }, 834 { 0x00, 0x050, 56, "4.4" }, 835 { 0x00, 0x060, 62, "4.0" }, 836 { 0x00, 0x070, 68, "3.6" }, 837 { 0x00, 0x000, 0, NULL } 838 }; 839 840 /* 841 * Allocate a controller structure for a new device and initialize it. 842 */ 843 int 844 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 845 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 846 ahc_flag flags) 847 { 848 struct scb_data *scb_data; 849 850 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 851 if (scb_data == NULL) { 852 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 853 return -1; 854 } 855 bzero(scb_data, sizeof (struct scb_data)); 856 LIST_INIT(&ahc->pending_ccbs); 857 ahc->tag = st; 858 ahc->bsh = sh; 859 ahc->parent_dmat = parent_dmat; 860 ahc->chip = chip; 861 ahc->features = features; 862 ahc->flags = flags; 863 ahc->scb_data = scb_data; 864 865 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 866 /* The IRQMS bit is only valid on VL and EISA chips */ 867 if ((ahc->chip & AHC_PCI) != 0) 868 ahc->unpause &= ~IRQMS; 869 ahc->pause = ahc->unpause | PAUSE; 870 return (0); 871 } 872 873 void 874 ahc_free(ahc) 875 struct ahc_softc *ahc; 876 { 877 ahcfiniscbdata(ahc); 878 if (ahc->init_level != 0) 879 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 880 ahc->shared_data_dmamap, ahc->qoutfifo, 881 &ahc->shared_data_seg, ahc->shared_data_nseg); 882 883 if (ahc->scb_data != NULL) 884 free(ahc->scb_data, M_DEVBUF); 885 if (ahc->bus_data != NULL) 886 free(ahc->bus_data, M_DEVBUF); 887 return; 888 } 889 890 static int 891 ahcinitscbdata(struct ahc_softc *ahc) 892 { 893 struct scb_data *scb_data; 894 int i; 895 896 scb_data = ahc->scb_data; 897 SLIST_INIT(&scb_data->free_scbs); 898 SLIST_INIT(&scb_data->sg_maps); 899 900 /* Allocate SCB resources */ 901 scb_data->scbarray = 902 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 903 M_DEVBUF, M_NOWAIT); 904 if (scb_data->scbarray == NULL) 905 return (ENOMEM); 906 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 907 908 /* Determine the number of hardware SCBs and initialize them */ 909 910 scb_data->maxhscbs = ahc_probe_scbs(ahc); 911 /* SCB 0 heads the free list */ 912 ahc_outb(ahc, FREE_SCBH, 0); 913 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 914 ahc_outb(ahc, SCBPTR, i); 915 916 /* Clear the control byte. */ 917 ahc_outb(ahc, SCB_CONTROL, 0); 918 919 /* Set the next pointer */ 920 ahc_outb(ahc, SCB_NEXT, i+1); 921 922 /* Make the tag number invalid */ 923 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 924 } 925 926 /* Make sure that the last SCB terminates the free list */ 927 ahc_outb(ahc, SCBPTR, i-1); 928 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 929 930 /* Ensure we clear the 0 SCB's control byte. */ 931 ahc_outb(ahc, SCBPTR, 0); 932 ahc_outb(ahc, SCB_CONTROL, 0); 933 934 scb_data->maxhscbs = i; 935 936 if (ahc->scb_data->maxhscbs == 0) 937 panic("%s: No SCB space found", ahc_name(ahc)); 938 939 /* 940 * Create our DMA tags. These tags define the kinds of device 941 * accessable memory allocations and memory mappings we will 942 * need to perform during normal operation. 943 * 944 * Unless we need to further restrict the allocation, we rely 945 * on the restrictions of the parent dmat, hence the common 946 * use of MAXADDR and MAXSIZE. 947 */ 948 949 if (ahc_createdmamem(ahc->parent_dmat, 950 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 951 &scb_data->hscb_dmamap, 952 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 953 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 954 "hardware SCB structures") < 0) 955 goto error_exit; 956 957 scb_data->init_level++; 958 959 if (ahc_createdmamem(ahc->parent_dmat, 960 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 961 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 962 &scb_data->sense_busaddr, &scb_data->sense_seg, 963 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 964 goto error_exit; 965 966 scb_data->init_level++; 967 968 /* Perform initial CCB allocation */ 969 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 970 ahcallocscbs(ahc); 971 972 if (scb_data->numscbs == 0) { 973 printf("%s: ahc_init_scb_data - " 974 "Unable to allocate initial scbs\n", 975 ahc_name(ahc)); 976 goto error_exit; 977 } 978 979 scb_data->init_level++; 980 981 /* 982 * Note that we were successfull 983 */ 984 return 0; 985 986 error_exit: 987 988 return ENOMEM; 989 } 990 991 static void 992 ahcfiniscbdata(struct ahc_softc *ahc) 993 { 994 struct scb_data *scb_data; 995 996 scb_data = ahc->scb_data; 997 998 switch (scb_data->init_level) { 999 default: 1000 case 3: 1001 { 1002 struct sg_map_node *sg_map; 1003 1004 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1005 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1006 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1007 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1008 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1009 free(sg_map, M_DEVBUF); 1010 } 1011 } 1012 /*FALLTHROUGH*/ 1013 case 2: 1014 ahc_freedmamem(ahc->parent_dmat, 1015 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1016 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1017 &scb_data->sense_seg, scb_data->sense_nseg); 1018 /*FALLTHROUGH*/ 1019 case 1: 1020 ahc_freedmamem(ahc->parent_dmat, 1021 AHC_SCB_MAX * sizeof(struct hardware_scb), 1022 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1023 &scb_data->hscb_seg, scb_data->hscb_nseg); 1024 /*FALLTHROUGH*/ 1025 } 1026 if (scb_data->scbarray != NULL) 1027 free(scb_data->scbarray, M_DEVBUF); 1028 } 1029 1030 int 1031 ahc_reset(struct ahc_softc *ahc) 1032 { 1033 u_int sblkctl; 1034 int wait; 1035 1036 #ifdef AHC_DUMP_SEQ 1037 if (ahc->init_level == 0) 1038 ahc_dumpseq(ahc); 1039 #endif 1040 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1041 /* 1042 * Ensure that the reset has finished 1043 */ 1044 wait = 1000; 1045 do { 1046 DELAY(1000); 1047 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1048 1049 if (wait == 0) { 1050 printf("%s: WARNING - Failed chip reset! " 1051 "Trying to initialize anyway.\n", ahc_name(ahc)); 1052 } 1053 ahc_outb(ahc, HCNTRL, ahc->pause); 1054 1055 /* Determine channel configuration */ 1056 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1057 /* No Twin Channel PCI cards */ 1058 if ((ahc->chip & AHC_PCI) != 0) 1059 sblkctl &= ~SELBUSB; 1060 switch (sblkctl) { 1061 case 0: 1062 /* Single Narrow Channel */ 1063 break; 1064 case 2: 1065 /* Wide Channel */ 1066 ahc->features |= AHC_WIDE; 1067 break; 1068 case 8: 1069 /* Twin Channel */ 1070 ahc->features |= AHC_TWIN; 1071 break; 1072 default: 1073 printf(" Unsupported adapter type. Ignoring\n"); 1074 return(-1); 1075 } 1076 1077 return (0); 1078 } 1079 1080 /* 1081 * Called when we have an active connection to a target on the bus, 1082 * this function finds the nearest syncrate to the input period limited 1083 * by the capabilities of the bus connectivity of the target. 1084 */ 1085 static struct ahc_syncrate * 1086 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1087 u_int maxsync; 1088 1089 if ((ahc->features & AHC_ULTRA2) != 0) { 1090 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1091 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1092 maxsync = AHC_SYNCRATE_ULTRA2; 1093 } else { 1094 maxsync = AHC_SYNCRATE_ULTRA; 1095 } 1096 } else if ((ahc->features & AHC_ULTRA) != 0) { 1097 maxsync = AHC_SYNCRATE_ULTRA; 1098 } else { 1099 maxsync = AHC_SYNCRATE_FAST; 1100 } 1101 return (ahc_find_syncrate(ahc, period, maxsync)); 1102 } 1103 1104 /* 1105 * Look up the valid period to SCSIRATE conversion in our table. 1106 * Return the period and offset that should be sent to the target 1107 * if this was the beginning of an SDTR. 1108 */ 1109 static struct ahc_syncrate * 1110 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1111 { 1112 struct ahc_syncrate *syncrate; 1113 1114 syncrate = &ahc_syncrates[maxsync]; 1115 while ((syncrate->rate != NULL) 1116 && ((ahc->features & AHC_ULTRA2) == 0 1117 || (syncrate->sxfr_u2 != 0))) { 1118 1119 if (*period <= syncrate->period) { 1120 /* 1121 * When responding to a target that requests 1122 * sync, the requested rate may fall between 1123 * two rates that we can output, but still be 1124 * a rate that we can receive. Because of this, 1125 * we want to respond to the target with 1126 * the same rate that it sent to us even 1127 * if the period we use to send data to it 1128 * is lower. Only lower the response period 1129 * if we must. 1130 */ 1131 if (syncrate == &ahc_syncrates[maxsync]) 1132 *period = syncrate->period; 1133 break; 1134 } 1135 syncrate++; 1136 } 1137 1138 if ((*period == 0) 1139 || (syncrate->rate == NULL) 1140 || ((ahc->features & AHC_ULTRA2) != 0 1141 && (syncrate->sxfr_u2 == 0))) { 1142 /* Use asynchronous transfers. */ 1143 *period = 0; 1144 syncrate = NULL; 1145 } 1146 return (syncrate); 1147 } 1148 1149 static u_int 1150 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1151 { 1152 struct ahc_syncrate *syncrate; 1153 1154 if ((ahc->features & AHC_ULTRA2) != 0) 1155 scsirate &= SXFR_ULTRA2; 1156 else 1157 scsirate &= SXFR; 1158 1159 syncrate = &ahc_syncrates[maxsync]; 1160 while (syncrate->rate != NULL) { 1161 1162 if ((ahc->features & AHC_ULTRA2) != 0) { 1163 if (syncrate->sxfr_u2 == 0) 1164 break; 1165 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1166 return (syncrate->period); 1167 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1168 return (syncrate->period); 1169 } 1170 syncrate++; 1171 } 1172 return (0); /* async */ 1173 } 1174 1175 static void 1176 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1177 u_int *offset, int wide) 1178 { 1179 u_int maxoffset; 1180 1181 /* Limit offset to what we can do */ 1182 if (syncrate == NULL) { 1183 maxoffset = 0; 1184 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1185 maxoffset = MAX_OFFSET_ULTRA2; 1186 } else { 1187 if (wide) 1188 maxoffset = MAX_OFFSET_16BIT; 1189 else 1190 maxoffset = MAX_OFFSET_8BIT; 1191 } 1192 *offset = MIN(*offset, maxoffset); 1193 } 1194 1195 static void 1196 ahc_update_target_msg_request(struct ahc_softc *ahc, 1197 struct ahc_devinfo *devinfo, 1198 struct ahc_initiator_tinfo *tinfo, 1199 int force, int paused) 1200 { 1201 u_int targ_msg_req_orig; 1202 1203 targ_msg_req_orig = ahc->targ_msg_req; 1204 if (tinfo->current.period != tinfo->goal.period 1205 || tinfo->current.width != tinfo->goal.width 1206 || tinfo->current.offset != tinfo->goal.offset 1207 || (force 1208 && (tinfo->goal.period != 0 1209 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1210 ahc->targ_msg_req |= devinfo->target_mask; 1211 } else { 1212 ahc->targ_msg_req &= ~devinfo->target_mask; 1213 } 1214 1215 if (ahc->targ_msg_req != targ_msg_req_orig) { 1216 /* Update the message request bit for this target */ 1217 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1218 if (paused) { 1219 ahc_outb(ahc, TARGET_MSG_REQUEST, 1220 ahc->targ_msg_req & 0xFF); 1221 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1222 (ahc->targ_msg_req >> 8) & 0xFF); 1223 } else { 1224 ahc_outb(ahc, HS_MAILBOX, 1225 0x01 << HOST_MAILBOX_SHIFT); 1226 } 1227 } else { 1228 if (!paused) 1229 pause_sequencer(ahc); 1230 1231 ahc_outb(ahc, TARGET_MSG_REQUEST, 1232 ahc->targ_msg_req & 0xFF); 1233 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1234 (ahc->targ_msg_req >> 8) & 0xFF); 1235 1236 if (!paused) 1237 unpause_sequencer(ahc); 1238 } 1239 } 1240 } 1241 1242 static void 1243 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1244 struct ahc_syncrate *syncrate, 1245 u_int period, u_int offset, u_int type, int paused, int done) 1246 { 1247 struct ahc_initiator_tinfo *tinfo; 1248 struct tmode_tstate *tstate; 1249 u_int old_period; 1250 u_int old_offset; 1251 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1252 1253 if (syncrate == NULL) { 1254 period = 0; 1255 offset = 0; 1256 } 1257 1258 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1259 devinfo->target, &tstate); 1260 old_period = tinfo->current.period; 1261 old_offset = tinfo->current.offset; 1262 1263 if ((type & AHC_TRANS_CUR) != 0 1264 && (old_period != period || old_offset != offset)) { 1265 u_int scsirate; 1266 1267 scsirate = tinfo->scsirate; 1268 if ((ahc->features & AHC_ULTRA2) != 0) { 1269 1270 /* XXX */ 1271 /* Force single edge until DT is fully implemented */ 1272 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1273 if (syncrate != NULL) 1274 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1275 1276 if (active) 1277 ahc_outb(ahc, SCSIOFFSET, offset); 1278 } else { 1279 1280 scsirate &= ~(SXFR|SOFS); 1281 /* 1282 * Ensure Ultra mode is set properly for 1283 * this target. 1284 */ 1285 tstate->ultraenb &= ~devinfo->target_mask; 1286 if (syncrate != NULL) { 1287 if (syncrate->sxfr & ULTRA_SXFR) { 1288 tstate->ultraenb |= 1289 devinfo->target_mask; 1290 } 1291 scsirate |= syncrate->sxfr & SXFR; 1292 scsirate |= offset & SOFS; 1293 } 1294 if (active) { 1295 u_int sxfrctl0; 1296 1297 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1298 sxfrctl0 &= ~FAST20; 1299 if (tstate->ultraenb & devinfo->target_mask) 1300 sxfrctl0 |= FAST20; 1301 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1302 } 1303 } 1304 if (active) 1305 ahc_outb(ahc, SCSIRATE, scsirate); 1306 1307 tinfo->scsirate = scsirate; 1308 tinfo->current.period = period; 1309 tinfo->current.offset = offset; 1310 1311 /* Update the syncrates in any pending scbs */ 1312 ahc_update_pending_syncrates(ahc); 1313 } 1314 1315 /* 1316 * Print messages if we're verbose and at the end of a negotiation 1317 * cycle. 1318 */ 1319 if (done) { 1320 if (offset != 0) { 1321 printf("%s: target %d synchronous at %sMHz, " 1322 "offset = 0x%x\n", ahc_name(ahc), 1323 devinfo->target, syncrate->rate, offset); 1324 } else { 1325 printf("%s: target %d using " 1326 "asynchronous transfers\n", 1327 ahc_name(ahc), devinfo->target); 1328 } 1329 } 1330 1331 if ((type & AHC_TRANS_GOAL) != 0) { 1332 tinfo->goal.period = period; 1333 tinfo->goal.offset = offset; 1334 } 1335 1336 if ((type & AHC_TRANS_USER) != 0) { 1337 tinfo->user.period = period; 1338 tinfo->user.offset = offset; 1339 } 1340 1341 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1342 /*force*/FALSE, 1343 paused); 1344 } 1345 1346 static void 1347 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1348 u_int width, u_int type, int paused, int done) 1349 { 1350 struct ahc_initiator_tinfo *tinfo; 1351 struct tmode_tstate *tstate; 1352 u_int oldwidth; 1353 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1354 1355 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1356 devinfo->target, &tstate); 1357 oldwidth = tinfo->current.width; 1358 1359 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1360 u_int scsirate; 1361 1362 scsirate = tinfo->scsirate; 1363 scsirate &= ~WIDEXFER; 1364 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1365 scsirate |= WIDEXFER; 1366 1367 tinfo->scsirate = scsirate; 1368 1369 if (active) 1370 ahc_outb(ahc, SCSIRATE, scsirate); 1371 1372 tinfo->current.width = width; 1373 } 1374 1375 if (done) { 1376 printf("%s: target %d using %dbit transfers\n", 1377 ahc_name(ahc), devinfo->target, 1378 8 * (0x01 << width)); 1379 } 1380 1381 if ((type & AHC_TRANS_GOAL) != 0) 1382 tinfo->goal.width = width; 1383 if ((type & AHC_TRANS_USER) != 0) 1384 tinfo->user.width = width; 1385 1386 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1387 /*force*/FALSE, paused); 1388 } 1389 1390 static void 1391 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1392 { 1393 struct ahc_initiator_tinfo *tinfo; 1394 struct tmode_tstate *tstate; 1395 1396 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1397 devinfo->target, &tstate); 1398 1399 if (enable) 1400 tstate->tagenable |= devinfo->target_mask; 1401 else { 1402 tstate->tagenable &= ~devinfo->target_mask; 1403 tstate->tagdisable |= devinfo->target_mask; 1404 } 1405 } 1406 1407 /* 1408 * Attach all the sub-devices we can find 1409 */ 1410 int 1411 ahc_attach(struct ahc_softc *ahc) 1412 { 1413 TAILQ_INIT(&ahc->sc_q); 1414 1415 ahc->sc_adapter.scsipi_cmd = ahc_action; 1416 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1417 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1418 ahc->sc_link.type = BUS_SCSI; 1419 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1420 ahc->sc_link.scsipi_scsi.channel = 0; 1421 ahc->sc_link.scsipi_scsi.max_target = 1422 (ahc->features & AHC_WIDE) ? 15 : 7; 1423 ahc->sc_link.scsipi_scsi.max_lun = 7; 1424 ahc->sc_link.adapter_softc = ahc; 1425 ahc->sc_link.adapter = &ahc->sc_adapter; 1426 ahc->sc_link.openings = 2; 1427 ahc->sc_link.device = &ahc_dev; 1428 1429 if (ahc->features & AHC_TWIN) { 1430 ahc->sc_link_b = ahc->sc_link; 1431 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1432 ahc->sc_link_b.scsipi_scsi.channel = 1; 1433 } 1434 1435 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1436 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1437 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1438 if (ahc->features & AHC_TWIN) 1439 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1440 } else { 1441 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1442 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1443 } 1444 return 1; 1445 } 1446 1447 static void 1448 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1449 { 1450 u_int saved_tcl; 1451 role_t role; 1452 int our_id; 1453 1454 if (ahc_inb(ahc, SSTAT0) & TARGET) 1455 role = ROLE_TARGET; 1456 else 1457 role = ROLE_INITIATOR; 1458 1459 if (role == ROLE_TARGET 1460 && (ahc->features & AHC_MULTI_TID) != 0 1461 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1462 /* We were selected, so pull our id from TARGIDIN */ 1463 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1464 } else if ((ahc->features & AHC_ULTRA2) != 0) 1465 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1466 else 1467 our_id = ahc_inb(ahc, SCSIID) & OID; 1468 1469 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1470 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1471 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1472 role); 1473 } 1474 1475 static void 1476 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1477 u_int lun, char channel, role_t role) 1478 { 1479 devinfo->our_scsiid = our_id; 1480 devinfo->target = target; 1481 devinfo->lun = lun; 1482 devinfo->target_offset = target; 1483 devinfo->channel = channel; 1484 devinfo->role = role; 1485 if (channel == 'B') 1486 devinfo->target_offset += 8; 1487 devinfo->target_mask = (0x01 << devinfo->target_offset); 1488 } 1489 1490 /* 1491 * Catch an interrupt from the adapter 1492 */ 1493 int 1494 ahc_intr(void *arg) 1495 { 1496 struct ahc_softc *ahc; 1497 u_int intstat; 1498 1499 ahc = (struct ahc_softc *)arg; 1500 1501 intstat = ahc_inb(ahc, INTSTAT); 1502 1503 /* 1504 * Any interrupts to process? 1505 */ 1506 if ((intstat & INT_PEND) == 0) { 1507 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1508 #ifdef AHC_DEBUG 1509 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1510 ahc_name(ahc), 1511 ahc_inb(ahc, CCHADDR) | 1512 (ahc_inb(ahc, CCHADDR+1) << 8) 1513 | (ahc_inb(ahc, CCHADDR+2) << 16) 1514 | (ahc_inb(ahc, CCHADDR+3) << 24), 1515 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1516 | (ahc_inb(ahc, HADDR+2) << 16) 1517 | (ahc_inb(ahc, HADDR+3) << 24), 1518 ahc_inb(ahc, SEQADDR0) | 1519 (ahc_inb(ahc, SEQADDR1) << 8)); 1520 #endif 1521 return 1; 1522 } 1523 return 0; 1524 } 1525 1526 #ifdef AHC_DEBUG 1527 if (ahc_debug & AHC_SHOWINTR) { 1528 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1529 } 1530 #endif 1531 1532 if (intstat & CMDCMPLT) { 1533 ahc_outb(ahc, CLRINT, CLRCMDINT); 1534 ahc_run_qoutfifo(ahc); 1535 } 1536 if (intstat & BRKADRINT) { 1537 /* 1538 * We upset the sequencer :-( 1539 * Lookup the error message 1540 */ 1541 int i, error, num_errors; 1542 1543 error = ahc_inb(ahc, ERROR); 1544 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1545 for (i = 0; error != 1 && i < num_errors; i++) 1546 error >>= 1; 1547 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1548 ahc_name(ahc), hard_error[i].errmesg, 1549 ahc_inb(ahc, SEQADDR0) | 1550 (ahc_inb(ahc, SEQADDR1) << 8)); 1551 1552 /* Tell everyone that this HBA is no longer availible */ 1553 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1554 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1555 XS_DRIVER_STUFFUP); 1556 } 1557 if (intstat & SEQINT) 1558 ahc_handle_seqint(ahc, intstat); 1559 1560 if (intstat & SCSIINT) 1561 ahc_handle_scsiint(ahc, intstat); 1562 1563 return 1; 1564 } 1565 1566 static struct tmode_tstate * 1567 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1568 { 1569 struct tmode_tstate *master_tstate; 1570 struct tmode_tstate *tstate; 1571 int i, s; 1572 1573 master_tstate = ahc->enabled_targets[ahc->our_id]; 1574 if (channel == 'B') { 1575 scsi_id += 8; 1576 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1577 } 1578 if (ahc->enabled_targets[scsi_id] != NULL 1579 && ahc->enabled_targets[scsi_id] != master_tstate) 1580 panic("%s: ahc_alloc_tstate - Target already allocated", 1581 ahc_name(ahc)); 1582 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1583 if (tstate == NULL) 1584 return (NULL); 1585 1586 /* 1587 * If we have allocated a master tstate, copy user settings from 1588 * the master tstate (taken from SRAM or the EEPROM) for this 1589 * channel, but reset our current and goal settings to async/narrow 1590 * until an initiator talks to us. 1591 */ 1592 if (master_tstate != NULL) { 1593 bcopy(master_tstate, tstate, sizeof(*tstate)); 1594 tstate->ultraenb = 0; 1595 for (i = 0; i < 16; i++) { 1596 bzero(&tstate->transinfo[i].current, 1597 sizeof(tstate->transinfo[i].current)); 1598 bzero(&tstate->transinfo[i].goal, 1599 sizeof(tstate->transinfo[i].goal)); 1600 } 1601 } else 1602 bzero(tstate, sizeof(*tstate)); 1603 s = splbio(); 1604 ahc->enabled_targets[scsi_id] = tstate; 1605 splx(s); 1606 return (tstate); 1607 } 1608 1609 #if UNUSED 1610 static void 1611 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1612 { 1613 struct tmode_tstate *tstate; 1614 1615 /* Don't clean up the entry for our initiator role */ 1616 if ((ahc->flags & AHC_INITIATORMODE) != 0 1617 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1618 || (channel == 'A' && scsi_id == ahc->our_id)) 1619 && force == FALSE) 1620 return; 1621 1622 if (channel == 'B') 1623 scsi_id += 8; 1624 tstate = ahc->enabled_targets[scsi_id]; 1625 if (tstate != NULL) 1626 free(tstate, M_DEVBUF); 1627 ahc->enabled_targets[scsi_id] = NULL; 1628 } 1629 #endif 1630 1631 static void 1632 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1633 { 1634 struct scb *scb; 1635 struct ahc_devinfo devinfo; 1636 1637 ahc_fetch_devinfo(ahc, &devinfo); 1638 1639 /* 1640 * Clear the upper byte that holds SEQINT status 1641 * codes and clear the SEQINT bit. We will unpause 1642 * the sequencer, if appropriate, after servicing 1643 * the request. 1644 */ 1645 ahc_outb(ahc, CLRINT, CLRSEQINT); 1646 switch (intstat & SEQINT_MASK) { 1647 case NO_MATCH: 1648 { 1649 /* Ensure we don't leave the selection hardware on */ 1650 ahc_outb(ahc, SCSISEQ, 1651 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1652 1653 printf("%s:%c:%d: no active SCB for reconnecting " 1654 "target - issuing BUS DEVICE RESET\n", 1655 ahc_name(ahc), devinfo.channel, devinfo.target); 1656 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1657 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1658 ahc_inb(ahc, SEQ_FLAGS)); 1659 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1660 ahc->msgout_len = 1; 1661 ahc->msgout_index = 0; 1662 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1663 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1664 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1665 break; 1666 } 1667 case UPDATE_TMSG_REQ: 1668 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1669 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1670 (ahc->targ_msg_req >> 8) & 0xFF); 1671 ahc_outb(ahc, HS_MAILBOX, 0); 1672 break; 1673 case SEND_REJECT: 1674 { 1675 u_int rejbyte = ahc_inb(ahc, ACCUM); 1676 printf("%s:%c:%d: Warning - unknown message received from " 1677 "target (0x%x). Rejecting\n", 1678 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1679 break; 1680 } 1681 case NO_IDENT: 1682 { 1683 /* 1684 * The reconnecting target either did not send an identify 1685 * message, or did, but we didn't find and SCB to match and 1686 * before it could respond to our ATN/abort, it hit a dataphase. 1687 * The only safe thing to do is to blow it away with a bus 1688 * reset. 1689 */ 1690 int found; 1691 1692 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1693 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1694 ahc_name(ahc), devinfo.channel, devinfo.target, 1695 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1696 found = ahc_reset_channel(ahc, devinfo.channel, 1697 /*initiate reset*/TRUE); 1698 printf("%s: Issued Channel %c Bus Reset. " 1699 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1700 found); 1701 return; 1702 } 1703 case BAD_PHASE: 1704 { 1705 u_int lastphase; 1706 1707 lastphase = ahc_inb(ahc, LASTPHASE); 1708 if (lastphase == P_BUSFREE) { 1709 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1710 ahc_name(ahc), devinfo.channel, devinfo.target, 1711 ahc_inb(ahc, SCSISIGI)); 1712 restart_sequencer(ahc); 1713 return; 1714 } else { 1715 printf("%s:%c:%d: unknown scsi bus phase %x. " 1716 "Attempting to continue\n", 1717 ahc_name(ahc), devinfo.channel, devinfo.target, 1718 ahc_inb(ahc, SCSISIGI)); 1719 } 1720 break; 1721 } 1722 case BAD_STATUS: 1723 { 1724 u_int scb_index; 1725 struct hardware_scb *hscb; 1726 struct scsipi_xfer *xs; 1727 struct scb *scbp; 1728 int todo, inqueue; 1729 /* 1730 * The sequencer will notify us when a command 1731 * has an error that would be of interest to 1732 * the kernel. This allows us to leave the sequencer 1733 * running in the common case of command completes 1734 * without error. The sequencer will already have 1735 * dma'd the SCB back up to us, so we can reference 1736 * the in kernel copy directly. 1737 */ 1738 scb_index = ahc_inb(ahc, SCB_TAG); 1739 scb = &ahc->scb_data->scbarray[scb_index]; 1740 1741 /* ahc_print_scb(scb); */ 1742 1743 /* 1744 * Set the default return value to 0 (don't 1745 * send sense). The sense code will change 1746 * this if needed. 1747 */ 1748 ahc_outb(ahc, RETURN_1, 0); 1749 if (!(scb_index < ahc->scb_data->numscbs 1750 && (scb->flags & SCB_ACTIVE) != 0)) { 1751 printf("%s:%c:%d: ahc_intr - referenced scb " 1752 "not valid during seqint 0x%x scb(%d)\n", 1753 ahc_name(ahc), devinfo.channel, 1754 devinfo.target, intstat, scb_index); 1755 goto unpause; 1756 } 1757 1758 hscb = scb->hscb; 1759 xs = scb->xs; 1760 1761 /* Don't want to clobber the original sense code */ 1762 if ((scb->flags & SCB_SENSE) != 0) { 1763 /* 1764 * Clear the SCB_SENSE Flag and have 1765 * the sequencer do a normal command 1766 * complete. 1767 */ 1768 scb->flags &= ~SCB_SENSE; 1769 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1770 break; 1771 } 1772 /* Freeze the queue unit the client sees the error. */ 1773 ahc_freeze_devq(ahc, xs->sc_link); 1774 ahc_freeze_ccb(scb); 1775 xs->status = hscb->status; 1776 switch (hscb->status) { 1777 case SCSI_STATUS_OK: 1778 printf("%s: Interrupted for status of 0???\n", 1779 ahc_name(ahc)); 1780 break; 1781 case SCSI_STATUS_CMD_TERMINATED: 1782 case SCSI_STATUS_CHECK_COND: 1783 #if defined(AHC_DEBUG) 1784 if (ahc_debug & AHC_SHOWSENSE) { 1785 scsi_print_addr(xs->sc_link); 1786 printf("Check Status, resid %d datalen %d\n", 1787 xs->resid, xs->datalen); 1788 } 1789 #endif 1790 1791 if (xs->error == XS_NOERROR && 1792 !(scb->flags & SCB_SENSE)) { 1793 struct ahc_dma_seg *sg; 1794 struct scsipi_sense *sc; 1795 struct ahc_initiator_tinfo *tinfo; 1796 struct tmode_tstate *tstate; 1797 1798 sg = scb->sg_list; 1799 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1800 /* 1801 * Save off the residual if there is one. 1802 */ 1803 if (hscb->residual_SG_count != 0) 1804 ahc_calc_residual(scb); 1805 else 1806 xs->resid = 0; 1807 1808 #ifdef AHC_DEBUG 1809 if (ahc_debug & AHC_SHOWSENSE) { 1810 scsi_print_addr(xs->sc_link); 1811 printf("Sending Sense\n"); 1812 } 1813 #endif 1814 sg->addr = ahc->scb_data->sense_busaddr + 1815 (hscb->tag*sizeof(struct scsipi_sense_data)); 1816 sg->len = sizeof (struct scsipi_sense_data); 1817 1818 sc->opcode = REQUEST_SENSE; 1819 sc->byte2 = SCB_LUN(scb) << 5; 1820 sc->unused[0] = 0; 1821 sc->unused[1] = 0; 1822 sc->length = sg->len; 1823 sc->control = 0; 1824 1825 /* 1826 * Would be nice to preserve DISCENB here, 1827 * but due to the way we page SCBs, we can't. 1828 */ 1829 hscb->control = 0; 1830 1831 /* 1832 * This request sense could be because the 1833 * the device lost power or in some other 1834 * way has lost our transfer negotiations. 1835 * Renegotiate if appropriate. Unit attention 1836 * errors will be reported before any data 1837 * phases occur. 1838 */ 1839 ahc_calc_residual(scb); 1840 #if defined(AHC_DEBUG) 1841 if (ahc_debug & AHC_SHOWSENSE) { 1842 scsi_print_addr(xs->sc_link); 1843 printf("Sense: datalen %d resid %d" 1844 "chan %d id %d targ %d\n", 1845 xs->datalen, xs->resid, 1846 devinfo.channel, devinfo.our_scsiid, 1847 devinfo.target); 1848 } 1849 #endif 1850 if (xs->datalen > 0 && 1851 xs->resid == xs->datalen) { 1852 tinfo = ahc_fetch_transinfo(ahc, 1853 devinfo.channel, 1854 devinfo.our_scsiid, 1855 devinfo.target, 1856 &tstate); 1857 ahc_update_target_msg_request(ahc, 1858 &devinfo, 1859 tinfo, 1860 /*force*/TRUE, 1861 /*paused*/TRUE); 1862 } 1863 hscb->status = 0; 1864 hscb->SG_count = 1; 1865 hscb->SG_pointer = scb->sg_list_phys; 1866 hscb->data = sg->addr; 1867 hscb->datalen = sg->len; 1868 hscb->cmdpointer = hscb->cmdstore_busaddr; 1869 hscb->cmdlen = sizeof(*sc); 1870 scb->sg_count = hscb->SG_count; 1871 ahc_swap_hscb(hscb); 1872 ahc_swap_sg(scb->sg_list); 1873 scb->flags |= SCB_SENSE; 1874 /* 1875 * Ensure the target is busy since this 1876 * will be an untagged request. 1877 */ 1878 ahc_busy_tcl(ahc, scb); 1879 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1880 1881 /* 1882 * Ensure we have enough time to actually 1883 * retrieve the sense. 1884 */ 1885 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1886 callout_reset(&scb->xs->xs_callout, 1887 5 * hz, ahc_timeout, scb); 1888 } 1889 } 1890 break; 1891 case SCSI_STATUS_QUEUE_FULL: 1892 scsi_print_addr(xs->sc_link); 1893 printf("queue full\n"); 1894 case SCSI_STATUS_BUSY: 1895 /* 1896 * XXX middle layer doesn't handle XS_BUSY well. 1897 * So, requeue this ourselves internally. It will 1898 * get its turn once all outstanding (tagged) 1899 * commands have finished. 1900 */ 1901 xs->error = XS_BUSY; 1902 xs->xs_status |= XS_STS_DEBUG; 1903 scb->flags |= SCB_REQUEUE; 1904 1905 /* 1906 * Walk through all pending SCBs for this target, 1907 * incrementing the freeze count for the queue. 1908 * When all of these have been completed, the 1909 * queue will be available again. 1910 */ 1911 inqueue = todo = 0; 1912 scbp = ahc->pending_ccbs.lh_first; 1913 while (scbp != NULL) { 1914 inqueue++; 1915 if (ahc_match_scb(scbp, SCB_TARGET(scb), 1916 SCB_CHANNEL(scb), SCB_LUN(scb), 1917 SCB_LIST_NULL, ROLE_INITIATOR)) { 1918 ahc_freeze_ccb(scbp); 1919 todo++; 1920 } 1921 scbp = scbp->plinks.le_next; 1922 } 1923 scsi_print_addr(xs->sc_link); 1924 printf("%d SCBs pending, %d to drain\n", inqueue, todo); 1925 break; 1926 } 1927 break; 1928 } 1929 case TRACE_POINT: 1930 { 1931 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1932 ahc_inb(ahc, DFCNTRL)); 1933 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1934 ahc_inb(ahc, DFSTATUS)); 1935 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1936 ahc_inb(ahc, SSTAT0), 1937 ahc_inb(ahc, SCB_DATACNT)); 1938 break; 1939 } 1940 case HOST_MSG_LOOP: 1941 { 1942 /* 1943 * The sequencer has encountered a message phase 1944 * that requires host assistance for completion. 1945 * While handling the message phase(s), we will be 1946 * notified by the sequencer after each byte is 1947 * transfered so we can track bus phases. 1948 * 1949 * If this is the first time we've seen a HOST_MSG_LOOP, 1950 * initialize the state of the host message loop. 1951 */ 1952 if (ahc->msg_type == MSG_TYPE_NONE) { 1953 u_int bus_phase; 1954 1955 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1956 if (bus_phase != P_MESGIN 1957 && bus_phase != P_MESGOUT) { 1958 printf("ahc_intr: HOST_MSG_LOOP bad " 1959 "phase 0x%x\n", 1960 bus_phase); 1961 /* 1962 * Probably transitioned to bus free before 1963 * we got here. Just punt the message. 1964 */ 1965 ahc_clear_intstat(ahc); 1966 restart_sequencer(ahc); 1967 } 1968 1969 if (devinfo.role == ROLE_INITIATOR) { 1970 struct scb *scb; 1971 u_int scb_index; 1972 1973 scb_index = ahc_inb(ahc, SCB_TAG); 1974 scb = &ahc->scb_data->scbarray[scb_index]; 1975 1976 if (bus_phase == P_MESGOUT) 1977 ahc_setup_initiator_msgout(ahc, 1978 &devinfo, 1979 scb); 1980 else { 1981 ahc->msg_type = 1982 MSG_TYPE_INITIATOR_MSGIN; 1983 ahc->msgin_index = 0; 1984 } 1985 } else { 1986 if (bus_phase == P_MESGOUT) { 1987 ahc->msg_type = 1988 MSG_TYPE_TARGET_MSGOUT; 1989 ahc->msgin_index = 0; 1990 } else 1991 /* XXX Ever executed??? */ 1992 ahc_setup_target_msgin(ahc, &devinfo); 1993 } 1994 } 1995 1996 /* Pass a NULL path so that handlers generate their own */ 1997 ahc_handle_message_phase(ahc, /*path*/NULL); 1998 break; 1999 } 2000 case PERR_DETECTED: 2001 { 2002 /* 2003 * If we've cleared the parity error interrupt 2004 * but the sequencer still believes that SCSIPERR 2005 * is true, it must be that the parity error is 2006 * for the currently presented byte on the bus, 2007 * and we are not in a phase (data-in) where we will 2008 * eventually ack this byte. Ack the byte and 2009 * throw it away in the hope that the target will 2010 * take us to message out to deliver the appropriate 2011 * error message. 2012 */ 2013 if ((intstat & SCSIINT) == 0 2014 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 2015 u_int curphase; 2016 2017 /* 2018 * The hardware will only let you ack bytes 2019 * if the expected phase in SCSISIGO matches 2020 * the current phase. Make sure this is 2021 * currently the case. 2022 */ 2023 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2024 ahc_outb(ahc, LASTPHASE, curphase); 2025 ahc_outb(ahc, SCSISIGO, curphase); 2026 ahc_inb(ahc, SCSIDATL); 2027 } 2028 break; 2029 } 2030 case DATA_OVERRUN: 2031 { 2032 /* 2033 * When the sequencer detects an overrun, it 2034 * places the controller in "BITBUCKET" mode 2035 * and allows the target to complete its transfer. 2036 * Unfortunately, none of the counters get updated 2037 * when the controller is in this mode, so we have 2038 * no way of knowing how large the overrun was. 2039 */ 2040 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2041 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2042 int i; 2043 2044 scb = &ahc->scb_data->scbarray[scbindex]; 2045 for (i = 0; i < num_phases; i++) { 2046 if (lastphase == phase_table[i].phase) 2047 break; 2048 } 2049 scsi_print_addr(scb->xs->sc_link); 2050 printf("data overrun detected %s." 2051 " Tag == 0x%x.\n", 2052 phase_table[i].phasemsg, 2053 scb->hscb->tag); 2054 scsi_print_addr(scb->xs->sc_link); 2055 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2056 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2057 scb->xs->datalen, scb->sg_count); 2058 if (scb->sg_count > 0) { 2059 for (i = 0; i < scb->sg_count; i++) { 2060 printf("sg[%d] - Addr 0x%x : Length %d\n", 2061 i, 2062 le32toh(scb->sg_list[i].addr), 2063 le32toh(scb->sg_list[i].len)); 2064 } 2065 } 2066 /* 2067 * Set this and it will take affect when the 2068 * target does a command complete. 2069 */ 2070 ahc_freeze_devq(ahc, scb->xs->sc_link); 2071 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2072 ahc_freeze_ccb(scb); 2073 break; 2074 } 2075 case TRACEPOINT: 2076 { 2077 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2078 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2079 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2080 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2081 printf("TRACEPOINT: CCHADDR = %x\n", 2082 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2083 | (ahc_inb(ahc, CCHADDR+2) << 16) 2084 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2085 #if 0 2086 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2087 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2088 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2089 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2090 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2091 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2092 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2093 ahc_inb(ahc, CCHADDR) 2094 | (ahc_inb(ahc, CCHADDR+1) << 8) 2095 | (ahc_inb(ahc, CCHADDR+2) << 16) 2096 | (ahc_inb(ahc, CCHADDR+3) << 24), 2097 ahc_inb(ahc, CCHCNT) 2098 | (ahc_inb(ahc, CCHCNT+1) << 8) 2099 | (ahc_inb(ahc, CCHCNT+2) << 16), 2100 ahc_inb(ahc, SCBPTR)); 2101 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2102 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2103 #if DDB > 0 2104 cpu_Debugger(); 2105 #endif 2106 #endif 2107 break; 2108 } 2109 #if NOT_YET 2110 /* XXX Fill these in later */ 2111 case MESG_BUFFER_BUSY: 2112 break; 2113 case MSGIN_PHASEMIS: 2114 break; 2115 #endif 2116 default: 2117 printf("ahc_intr: seqint, " 2118 "intstat == 0x%x, scsisigi = 0x%x\n", 2119 intstat, ahc_inb(ahc, SCSISIGI)); 2120 break; 2121 } 2122 2123 unpause: 2124 /* 2125 * The sequencer is paused immediately on 2126 * a SEQINT, so we should restart it when 2127 * we're done. 2128 */ 2129 unpause_sequencer(ahc); 2130 } 2131 2132 static void 2133 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2134 { 2135 u_int scb_index; 2136 u_int status; 2137 struct scb *scb; 2138 char cur_channel; 2139 char intr_channel; 2140 2141 if ((ahc->features & AHC_TWIN) != 0 2142 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2143 cur_channel = 'B'; 2144 else 2145 cur_channel = 'A'; 2146 intr_channel = cur_channel; 2147 2148 status = ahc_inb(ahc, SSTAT1); 2149 if (status == 0) { 2150 if ((ahc->features & AHC_TWIN) != 0) { 2151 /* Try the other channel */ 2152 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2153 status = ahc_inb(ahc, SSTAT1); 2154 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2155 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2156 } 2157 if (status == 0) { 2158 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2159 return; 2160 } 2161 } 2162 2163 scb_index = ahc_inb(ahc, SCB_TAG); 2164 if (scb_index < ahc->scb_data->numscbs) { 2165 scb = &ahc->scb_data->scbarray[scb_index]; 2166 if ((scb->flags & SCB_ACTIVE) == 0 2167 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2168 scb = NULL; 2169 } else 2170 scb = NULL; 2171 2172 if ((status & SCSIRSTI) != 0) { 2173 printf("%s: Someone reset channel %c\n", 2174 ahc_name(ahc), intr_channel); 2175 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2176 } else if ((status & SCSIPERR) != 0) { 2177 /* 2178 * Determine the bus phase and queue an appropriate message. 2179 * SCSIPERR is latched true as soon as a parity error 2180 * occurs. If the sequencer acked the transfer that 2181 * caused the parity error and the currently presented 2182 * transfer on the bus has correct parity, SCSIPERR will 2183 * be cleared by CLRSCSIPERR. Use this to determine if 2184 * we should look at the last phase the sequencer recorded, 2185 * or the current phase presented on the bus. 2186 */ 2187 u_int mesg_out; 2188 u_int curphase; 2189 u_int errorphase; 2190 u_int lastphase; 2191 int i; 2192 2193 lastphase = ahc_inb(ahc, LASTPHASE); 2194 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2195 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2196 /* 2197 * For all phases save DATA, the sequencer won't 2198 * automatically ack a byte that has a parity error 2199 * in it. So the only way that the current phase 2200 * could be 'data-in' is if the parity error is for 2201 * an already acked byte in the data phase. During 2202 * synchronous data-in transfers, we may actually 2203 * ack bytes before latching the current phase in 2204 * LASTPHASE, leading to the discrepancy between 2205 * curphase and lastphase. 2206 */ 2207 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2208 || curphase == P_DATAIN) 2209 errorphase = curphase; 2210 else 2211 errorphase = lastphase; 2212 2213 for (i = 0; i < num_phases; i++) { 2214 if (errorphase == phase_table[i].phase) 2215 break; 2216 } 2217 mesg_out = phase_table[i].mesg_out; 2218 if (scb != NULL) 2219 scsi_print_addr(scb->xs->sc_link); 2220 else 2221 printf("%s:%c:%d: ", ahc_name(ahc), 2222 intr_channel, 2223 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2224 2225 printf("parity error detected %s. " 2226 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2227 phase_table[i].phasemsg, 2228 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2229 ahc_inb(ahc, SCSIRATE)); 2230 2231 /* 2232 * We've set the hardware to assert ATN if we 2233 * get a parity error on "in" phases, so all we 2234 * need to do is stuff the message buffer with 2235 * the appropriate message. "In" phases have set 2236 * mesg_out to something other than MSG_NOP. 2237 */ 2238 if (mesg_out != MSG_NOOP) { 2239 if (ahc->msg_type != MSG_TYPE_NONE) 2240 ahc->send_msg_perror = TRUE; 2241 else 2242 ahc_outb(ahc, MSG_OUT, mesg_out); 2243 } 2244 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2245 unpause_sequencer(ahc); 2246 } else if ((status & BUSFREE) != 0 2247 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2248 /* 2249 * First look at what phase we were last in. 2250 * If its message out, chances are pretty good 2251 * that the busfree was in response to one of 2252 * our abort requests. 2253 */ 2254 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2255 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2256 u_int target = TCL_TARGET(saved_tcl); 2257 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2258 char channel = TCL_CHANNEL(ahc, saved_tcl); 2259 int printerror = 1; 2260 2261 ahc_outb(ahc, SCSISEQ, 2262 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2263 if (lastphase == P_MESGOUT) { 2264 u_int message; 2265 u_int tag; 2266 2267 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2268 tag = SCB_LIST_NULL; 2269 switch (message) { 2270 case MSG_ABORT_TAG: 2271 tag = scb->hscb->tag; 2272 /* FALLTRHOUGH */ 2273 case MSG_ABORT: 2274 scsi_print_addr(scb->xs->sc_link); 2275 printf("SCB %x - Abort %s Completed.\n", 2276 scb->hscb->tag, tag == SCB_LIST_NULL ? 2277 "" : "Tag"); 2278 ahc_abort_scbs(ahc, target, channel, 2279 TCL_LUN(saved_tcl), tag, 2280 ROLE_INITIATOR, 2281 XS_DRIVER_STUFFUP); 2282 printerror = 0; 2283 break; 2284 case MSG_BUS_DEV_RESET: 2285 { 2286 struct ahc_devinfo devinfo; 2287 2288 if (scb != NULL && 2289 (scb->xs->xs_control & XS_CTL_RESET) 2290 && ahc_match_scb(scb, target, channel, 2291 TCL_LUN(saved_tcl), 2292 SCB_LIST_NULL, 2293 ROLE_INITIATOR)) { 2294 ahcsetccbstatus(scb->xs, XS_NOERROR); 2295 } 2296 ahc_compile_devinfo(&devinfo, 2297 initiator_role_id, 2298 target, 2299 TCL_LUN(saved_tcl), 2300 channel, 2301 ROLE_INITIATOR); 2302 ahc_handle_devreset(ahc, &devinfo, 2303 XS_RESET, 2304 "Bus Device Reset", 2305 /*verbose_level*/0); 2306 printerror = 0; 2307 break; 2308 } 2309 default: 2310 break; 2311 } 2312 } 2313 if (printerror != 0) { 2314 int i; 2315 2316 if (scb != NULL) { 2317 u_int tag; 2318 2319 if ((scb->hscb->control & TAG_ENB) != 0) 2320 tag = scb->hscb->tag; 2321 else 2322 tag = SCB_LIST_NULL; 2323 ahc_abort_scbs(ahc, target, channel, 2324 SCB_LUN(scb), tag, 2325 ROLE_INITIATOR, 2326 XS_DRIVER_STUFFUP); 2327 scsi_print_addr(scb->xs->sc_link); 2328 } else { 2329 /* 2330 * We had not fully identified this connection, 2331 * so we cannot abort anything. 2332 */ 2333 printf("%s: ", ahc_name(ahc)); 2334 } 2335 for (i = 0; i < num_phases; i++) { 2336 if (lastphase == phase_table[i].phase) 2337 break; 2338 } 2339 printf("Unexpected busfree %s\n" 2340 "SEQADDR == 0x%x\n", 2341 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2342 | (ahc_inb(ahc, SEQADDR1) << 8)); 2343 } 2344 ahc_clear_msg_state(ahc); 2345 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2346 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2347 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2348 restart_sequencer(ahc); 2349 } else if ((status & SELTO) != 0) { 2350 u_int scbptr; 2351 2352 scbptr = ahc_inb(ahc, WAITING_SCBH); 2353 ahc_outb(ahc, SCBPTR, scbptr); 2354 scb_index = ahc_inb(ahc, SCB_TAG); 2355 2356 if (scb_index < ahc->scb_data->numscbs) { 2357 scb = &ahc->scb_data->scbarray[scb_index]; 2358 if ((scb->flags & SCB_ACTIVE) == 0) 2359 scb = NULL; 2360 } else 2361 scb = NULL; 2362 2363 if (scb == NULL) { 2364 printf("%s: ahc_intr - referenced scb not " 2365 "valid during SELTO scb(%d, %d)\n", 2366 ahc_name(ahc), scbptr, scb_index); 2367 } else { 2368 u_int tag; 2369 2370 tag = SCB_LIST_NULL; 2371 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2372 tag = scb->hscb->tag; 2373 2374 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2375 SCB_LUN(scb), tag, 2376 ROLE_INITIATOR, XS_SELTIMEOUT); 2377 } 2378 /* Stop the selection */ 2379 ahc_outb(ahc, SCSISEQ, 0); 2380 2381 /* No more pending messages */ 2382 ahc_clear_msg_state(ahc); 2383 2384 /* 2385 * Although the driver does not care about the 2386 * 'Selection in Progress' status bit, the busy 2387 * LED does. SELINGO is only cleared by a sucessful 2388 * selection, so we must manually clear it to ensure 2389 * the LED turns off just incase no future successful 2390 * selections occur (e.g. no devices on the bus). 2391 */ 2392 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2393 2394 /* Clear interrupt state */ 2395 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2396 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2397 restart_sequencer(ahc); 2398 } else { 2399 scsi_print_addr(scb->xs->sc_link); 2400 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2401 ahc_outb(ahc, CLRSINT1, status); 2402 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2403 unpause_sequencer(ahc); 2404 } 2405 } 2406 2407 static void 2408 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2409 { 2410 /* 2411 * We need to initiate transfer negotiations. 2412 * If our current and goal settings are identical, 2413 * we want to renegotiate due to a check condition. 2414 */ 2415 struct ahc_initiator_tinfo *tinfo; 2416 struct tmode_tstate *tstate; 2417 int dowide; 2418 int dosync; 2419 2420 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2421 devinfo->target, &tstate); 2422 dowide = tinfo->current.width != tinfo->goal.width; 2423 dosync = tinfo->current.period != tinfo->goal.period; 2424 2425 if (!dowide && !dosync) { 2426 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2427 dosync = tinfo->goal.period != 0; 2428 } 2429 2430 if (dowide) { 2431 ahc_construct_wdtr(ahc, tinfo->goal.width); 2432 } else if (dosync) { 2433 struct ahc_syncrate *rate; 2434 u_int period; 2435 u_int offset; 2436 2437 period = tinfo->goal.period; 2438 rate = ahc_devlimited_syncrate(ahc, &period); 2439 offset = tinfo->goal.offset; 2440 ahc_validate_offset(ahc, rate, &offset, 2441 tinfo->current.width); 2442 ahc_construct_sdtr(ahc, period, offset); 2443 } else { 2444 panic("ahc_intr: AWAITING_MSG for negotiation, " 2445 "but no negotiation needed\n"); 2446 } 2447 } 2448 2449 static void 2450 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2451 struct scb *scb) 2452 { 2453 /* 2454 * To facilitate adding multiple messages together, 2455 * each routine should increment the index and len 2456 * variables instead of setting them explicitly. 2457 */ 2458 ahc->msgout_index = 0; 2459 ahc->msgout_len = 0; 2460 2461 if ((scb->flags & SCB_DEVICE_RESET) == 0 2462 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2463 u_int identify_msg; 2464 2465 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2466 if ((scb->hscb->control & DISCENB) != 0) 2467 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2468 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2469 ahc->msgout_len++; 2470 2471 if ((scb->hscb->control & TAG_ENB) != 0) { 2472 /* XXX fvdl FreeBSD has tag action passed down */ 2473 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2474 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2475 ahc->msgout_len += 2; 2476 } 2477 } 2478 2479 if (scb->flags & SCB_DEVICE_RESET) { 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2481 ahc->msgout_len++; 2482 scsi_print_addr(scb->xs->sc_link); 2483 printf("Bus Device Reset Message Sent\n"); 2484 } else if (scb->flags & SCB_ABORT) { 2485 if ((scb->hscb->control & TAG_ENB) != 0) 2486 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2487 else 2488 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2489 ahc->msgout_len++; 2490 scsi_print_addr(scb->xs->sc_link); 2491 printf("Abort Message Sent\n"); 2492 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2493 ahc_build_transfer_msg(ahc, devinfo); 2494 } else { 2495 printf("ahc_intr: AWAITING_MSG for an SCB that " 2496 "does not have a waiting message"); 2497 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2498 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2499 ahc_inb(ahc, MSG_OUT), scb->flags); 2500 } 2501 2502 /* 2503 * Clear the MK_MESSAGE flag from the SCB so we aren't 2504 * asked to send this message again. 2505 */ 2506 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2507 ahc->msgout_index = 0; 2508 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2509 } 2510 2511 static void 2512 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2513 { 2514 /* 2515 * To facilitate adding multiple messages together, 2516 * each routine should increment the index and len 2517 * variables instead of setting them explicitly. 2518 */ 2519 ahc->msgout_index = 0; 2520 ahc->msgout_len = 0; 2521 2522 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2523 ahc_build_transfer_msg(ahc, devinfo); 2524 else 2525 panic("ahc_intr: AWAITING target message with no message"); 2526 2527 ahc->msgout_index = 0; 2528 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2529 } 2530 2531 static int 2532 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2533 { 2534 /* 2535 * What we care about here is if we had an 2536 * outstanding SDTR or WDTR message for this 2537 * target. If we did, this is a signal that 2538 * the target is refusing negotiation. 2539 */ 2540 struct scb *scb; 2541 u_int scb_index; 2542 u_int last_msg; 2543 int response = 0; 2544 2545 scb_index = ahc_inb(ahc, SCB_TAG); 2546 scb = &ahc->scb_data->scbarray[scb_index]; 2547 2548 /* Might be necessary */ 2549 last_msg = ahc_inb(ahc, LAST_MSG); 2550 2551 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2552 struct ahc_initiator_tinfo *tinfo; 2553 struct tmode_tstate *tstate; 2554 2555 #ifdef AHC_DEBUG_NEG 2556 /* note 8bit xfers */ 2557 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2558 "8bit transfers\n", ahc_name(ahc), 2559 devinfo->channel, devinfo->target); 2560 #endif 2561 ahc_set_width(ahc, devinfo, 2562 MSG_EXT_WDTR_BUS_8_BIT, 2563 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2564 /*paused*/TRUE, /*done*/TRUE); 2565 /* 2566 * No need to clear the sync rate. If the target 2567 * did not accept the command, our syncrate is 2568 * unaffected. If the target started the negotiation, 2569 * but rejected our response, we already cleared the 2570 * sync rate before sending our WDTR. 2571 */ 2572 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2573 devinfo->our_scsiid, 2574 devinfo->target, &tstate); 2575 if (tinfo->goal.period) { 2576 u_int period; 2577 2578 /* Start the sync negotiation */ 2579 period = tinfo->goal.period; 2580 ahc_devlimited_syncrate(ahc, &period); 2581 ahc->msgout_index = 0; 2582 ahc->msgout_len = 0; 2583 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2584 ahc->msgout_index = 0; 2585 response = 1; 2586 } 2587 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2588 /* note asynch xfers and clear flag */ 2589 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2590 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2591 /*paused*/TRUE, /*done*/TRUE); 2592 #ifdef AHC_DEBUG_NEG 2593 printf("%s:%c:%d: refuses synchronous negotiation. " 2594 "Using asynchronous transfers\n", 2595 ahc_name(ahc), 2596 devinfo->channel, devinfo->target); 2597 #endif 2598 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2599 printf("%s:%c:%d: refuses tagged commands. Performing " 2600 "non-tagged I/O\n", ahc_name(ahc), 2601 devinfo->channel, devinfo->target); 2602 2603 ahc_set_tags(ahc, devinfo, FALSE); 2604 2605 /* 2606 * Resend the identify for this CCB as the target 2607 * may believe that the selection is invalid otherwise. 2608 */ 2609 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2610 & ~MSG_SIMPLE_Q_TAG); 2611 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2612 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2613 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2614 2615 /* 2616 * Requeue all tagged commands for this target 2617 * currently in our posession so they can be 2618 * converted to untagged commands. 2619 */ 2620 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2621 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2622 ROLE_INITIATOR, SCB_REQUEUE, 2623 SEARCH_COMPLETE); 2624 } else { 2625 /* 2626 * Otherwise, we ignore it. 2627 */ 2628 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2629 ahc_name(ahc), devinfo->channel, devinfo->target, 2630 last_msg); 2631 } 2632 return (response); 2633 } 2634 2635 static void 2636 ahc_clear_msg_state(struct ahc_softc *ahc) 2637 { 2638 ahc->msgout_len = 0; 2639 ahc->msgin_index = 0; 2640 ahc->msg_type = MSG_TYPE_NONE; 2641 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2642 } 2643 2644 static void 2645 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2646 { 2647 struct ahc_devinfo devinfo; 2648 u_int bus_phase; 2649 int end_session; 2650 2651 ahc_fetch_devinfo(ahc, &devinfo); 2652 end_session = FALSE; 2653 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2654 2655 reswitch: 2656 switch (ahc->msg_type) { 2657 case MSG_TYPE_INITIATOR_MSGOUT: 2658 { 2659 int lastbyte; 2660 int phasemis; 2661 int msgdone; 2662 2663 if (ahc->msgout_len == 0) 2664 panic("REQINIT interrupt with no active message"); 2665 2666 phasemis = bus_phase != P_MESGOUT; 2667 if (phasemis) { 2668 if (bus_phase == P_MESGIN) { 2669 /* 2670 * Change gears and see if 2671 * this messages is of interest to 2672 * us or should be passed back to 2673 * the sequencer. 2674 */ 2675 ahc_outb(ahc, CLRSINT1, CLRATNO); 2676 ahc->send_msg_perror = FALSE; 2677 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2678 ahc->msgin_index = 0; 2679 goto reswitch; 2680 } 2681 end_session = TRUE; 2682 break; 2683 } 2684 2685 if (ahc->send_msg_perror) { 2686 ahc_outb(ahc, CLRSINT1, CLRATNO); 2687 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2688 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2689 break; 2690 } 2691 2692 msgdone = ahc->msgout_index == ahc->msgout_len; 2693 if (msgdone) { 2694 /* 2695 * The target has requested a retry. 2696 * Re-assert ATN, reset our message index to 2697 * 0, and try again. 2698 */ 2699 ahc->msgout_index = 0; 2700 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2701 } 2702 2703 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2704 if (lastbyte) { 2705 /* Last byte is signified by dropping ATN */ 2706 ahc_outb(ahc, CLRSINT1, CLRATNO); 2707 } 2708 2709 /* 2710 * Clear our interrupt status and present 2711 * the next byte on the bus. 2712 */ 2713 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2714 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2715 break; 2716 } 2717 case MSG_TYPE_INITIATOR_MSGIN: 2718 { 2719 int phasemis; 2720 int message_done; 2721 2722 phasemis = bus_phase != P_MESGIN; 2723 2724 if (phasemis) { 2725 ahc->msgin_index = 0; 2726 if (bus_phase == P_MESGOUT 2727 && (ahc->send_msg_perror == TRUE 2728 || (ahc->msgout_len != 0 2729 && ahc->msgout_index == 0))) { 2730 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2731 goto reswitch; 2732 } 2733 end_session = TRUE; 2734 break; 2735 } 2736 2737 /* Pull the byte in without acking it */ 2738 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2739 2740 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2741 2742 if (message_done) { 2743 /* 2744 * Clear our incoming message buffer in case there 2745 * is another message following this one. 2746 */ 2747 ahc->msgin_index = 0; 2748 2749 /* 2750 * If this message illicited a response, 2751 * assert ATN so the target takes us to the 2752 * message out phase. 2753 */ 2754 if (ahc->msgout_len != 0) 2755 ahc_outb(ahc, SCSISIGO, 2756 ahc_inb(ahc, SCSISIGO) | ATNO); 2757 } else 2758 ahc->msgin_index++; 2759 2760 /* Ack the byte */ 2761 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2762 ahc_inb(ahc, SCSIDATL); 2763 break; 2764 } 2765 case MSG_TYPE_TARGET_MSGIN: 2766 { 2767 int msgdone; 2768 int msgout_request; 2769 2770 if (ahc->msgout_len == 0) 2771 panic("Target MSGIN with no active message"); 2772 2773 /* 2774 * If we interrupted a mesgout session, the initiator 2775 * will not know this until our first REQ. So, we 2776 * only honor mesgout requests after we've sent our 2777 * first byte. 2778 */ 2779 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2780 && ahc->msgout_index > 0) 2781 msgout_request = TRUE; 2782 else 2783 msgout_request = FALSE; 2784 2785 if (msgout_request) { 2786 2787 /* 2788 * Change gears and see if 2789 * this messages is of interest to 2790 * us or should be passed back to 2791 * the sequencer. 2792 */ 2793 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2794 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2795 ahc->msgin_index = 0; 2796 /* Dummy read to REQ for first byte */ 2797 ahc_inb(ahc, SCSIDATL); 2798 ahc_outb(ahc, SXFRCTL0, 2799 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2800 break; 2801 } 2802 2803 msgdone = ahc->msgout_index == ahc->msgout_len; 2804 if (msgdone) { 2805 ahc_outb(ahc, SXFRCTL0, 2806 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2807 end_session = TRUE; 2808 break; 2809 } 2810 2811 /* 2812 * Present the next byte on the bus. 2813 */ 2814 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2815 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2816 break; 2817 } 2818 case MSG_TYPE_TARGET_MSGOUT: 2819 { 2820 int lastbyte; 2821 int msgdone; 2822 2823 /* 2824 * The initiator signals that this is 2825 * the last byte by dropping ATN. 2826 */ 2827 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2828 2829 /* 2830 * Read the latched byte, but turn off SPIOEN first 2831 * so that we don't inadvertantly cause a REQ for the 2832 * next byte. 2833 */ 2834 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2835 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2836 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2837 if (msgdone == MSGLOOP_TERMINATED) { 2838 /* 2839 * The message is *really* done in that it caused 2840 * us to go to bus free. The sequencer has already 2841 * been reset at this point, so pull the ejection 2842 * handle. 2843 */ 2844 return; 2845 } 2846 2847 ahc->msgin_index++; 2848 2849 /* 2850 * XXX Read spec about initiator dropping ATN too soon 2851 * and use msgdone to detect it. 2852 */ 2853 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2854 ahc->msgin_index = 0; 2855 2856 /* 2857 * If this message illicited a response, transition 2858 * to the Message in phase and send it. 2859 */ 2860 if (ahc->msgout_len != 0) { 2861 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2862 ahc_outb(ahc, SXFRCTL0, 2863 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2864 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2865 ahc->msgin_index = 0; 2866 break; 2867 } 2868 } 2869 2870 if (lastbyte) 2871 end_session = TRUE; 2872 else { 2873 /* Ask for the next byte. */ 2874 ahc_outb(ahc, SXFRCTL0, 2875 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2876 } 2877 2878 break; 2879 } 2880 default: 2881 panic("Unknown REQINIT message type"); 2882 } 2883 2884 if (end_session) { 2885 ahc_clear_msg_state(ahc); 2886 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2887 } else 2888 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2889 } 2890 2891 /* 2892 * See if we sent a particular extended message to the target. 2893 * If "full" is true, the target saw the full message. 2894 * If "full" is false, the target saw at least the first 2895 * byte of the message. 2896 */ 2897 static int 2898 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2899 { 2900 int found; 2901 int index; 2902 2903 found = FALSE; 2904 index = 0; 2905 2906 while (index < ahc->msgout_len) { 2907 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2908 2909 /* Found a candidate */ 2910 if (ahc->msgout_buf[index+2] == msgtype) { 2911 u_int end_index; 2912 2913 end_index = index + 1 2914 + ahc->msgout_buf[index + 1]; 2915 if (full) { 2916 if (ahc->msgout_index > end_index) 2917 found = TRUE; 2918 } else if (ahc->msgout_index > index) 2919 found = TRUE; 2920 } 2921 break; 2922 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2923 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2924 2925 /* Skip tag type and tag id or residue param*/ 2926 index += 2; 2927 } else { 2928 /* Single byte message */ 2929 index++; 2930 } 2931 } 2932 return (found); 2933 } 2934 2935 static int 2936 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2937 struct ahc_devinfo *devinfo) 2938 { 2939 struct ahc_initiator_tinfo *tinfo; 2940 struct tmode_tstate *tstate; 2941 int reject; 2942 int done; 2943 int response; 2944 u_int targ_scsirate; 2945 2946 done = MSGLOOP_IN_PROG; 2947 response = FALSE; 2948 reject = FALSE; 2949 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2950 devinfo->target, &tstate); 2951 targ_scsirate = tinfo->scsirate; 2952 2953 /* 2954 * Parse as much of the message as is availible, 2955 * rejecting it if we don't support it. When 2956 * the entire message is availible and has been 2957 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2958 * that we have parsed an entire message. 2959 * 2960 * In the case of extended messages, we accept the length 2961 * byte outright and perform more checking once we know the 2962 * extended message type. 2963 */ 2964 switch (ahc->msgin_buf[0]) { 2965 case MSG_MESSAGE_REJECT: 2966 response = ahc_handle_msg_reject(ahc, devinfo); 2967 /* FALLTHROUGH */ 2968 case MSG_NOOP: 2969 done = MSGLOOP_MSGCOMPLETE; 2970 break; 2971 case MSG_IGN_WIDE_RESIDUE: 2972 { 2973 /* Wait for the whole message */ 2974 if (ahc->msgin_index >= 1) { 2975 if (ahc->msgin_buf[1] != 1 2976 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2977 reject = TRUE; 2978 done = MSGLOOP_MSGCOMPLETE; 2979 } else 2980 ahc_handle_ign_wide_residue(ahc, devinfo); 2981 } 2982 break; 2983 } 2984 case MSG_EXTENDED: 2985 { 2986 /* Wait for enough of the message to begin validation */ 2987 if (ahc->msgin_index < 2) 2988 break; 2989 switch (ahc->msgin_buf[2]) { 2990 case MSG_EXT_SDTR: 2991 { 2992 struct ahc_syncrate *syncrate; 2993 u_int period; 2994 u_int offset; 2995 u_int saved_offset; 2996 2997 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2998 reject = TRUE; 2999 break; 3000 } 3001 3002 /* 3003 * Wait until we have both args before validating 3004 * and acting on this message. 3005 * 3006 * Add one to MSG_EXT_SDTR_LEN to account for 3007 * the extended message preamble. 3008 */ 3009 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3010 break; 3011 3012 period = ahc->msgin_buf[3]; 3013 saved_offset = offset = ahc->msgin_buf[4]; 3014 syncrate = ahc_devlimited_syncrate(ahc, &period); 3015 ahc_validate_offset(ahc, syncrate, &offset, 3016 targ_scsirate & WIDEXFER); 3017 ahc_set_syncrate(ahc, devinfo, 3018 syncrate, period, offset, 3019 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3020 /*paused*/TRUE, /*done*/TRUE); 3021 3022 /* 3023 * See if we initiated Sync Negotiation 3024 * and didn't have to fall down to async 3025 * transfers. 3026 */ 3027 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3028 /* We started it */ 3029 if (saved_offset != offset) { 3030 /* Went too low - force async */ 3031 reject = TRUE; 3032 } 3033 } else { 3034 /* 3035 * Send our own SDTR in reply 3036 */ 3037 ahc->msgout_index = 0; 3038 ahc->msgout_len = 0; 3039 ahc_construct_sdtr(ahc, period, offset); 3040 ahc->msgout_index = 0; 3041 response = TRUE; 3042 } 3043 done = MSGLOOP_MSGCOMPLETE; 3044 break; 3045 } 3046 case MSG_EXT_WDTR: 3047 { 3048 u_int bus_width; 3049 u_int sending_reply; 3050 3051 sending_reply = FALSE; 3052 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3053 reject = TRUE; 3054 break; 3055 } 3056 3057 /* 3058 * Wait until we have our arg before validating 3059 * and acting on this message. 3060 * 3061 * Add one to MSG_EXT_WDTR_LEN to account for 3062 * the extended message preamble. 3063 */ 3064 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3065 break; 3066 3067 bus_width = ahc->msgin_buf[3]; 3068 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3069 /* 3070 * Don't send a WDTR back to the 3071 * target, since we asked first. 3072 */ 3073 switch (bus_width){ 3074 default: 3075 /* 3076 * How can we do anything greater 3077 * than 16bit transfers on a 16bit 3078 * bus? 3079 */ 3080 reject = TRUE; 3081 printf("%s: target %d requested %dBit " 3082 "transfers. Rejecting...\n", 3083 ahc_name(ahc), devinfo->target, 3084 8 * (0x01 << bus_width)); 3085 /* FALLTHROUGH */ 3086 case MSG_EXT_WDTR_BUS_8_BIT: 3087 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3088 break; 3089 case MSG_EXT_WDTR_BUS_16_BIT: 3090 break; 3091 } 3092 } else { 3093 /* 3094 * Send our own WDTR in reply 3095 */ 3096 switch (bus_width) { 3097 default: 3098 if (ahc->features & AHC_WIDE) { 3099 /* Respond Wide */ 3100 bus_width = 3101 MSG_EXT_WDTR_BUS_16_BIT; 3102 break; 3103 } 3104 /* FALLTHROUGH */ 3105 case MSG_EXT_WDTR_BUS_8_BIT: 3106 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3107 break; 3108 } 3109 ahc->msgout_index = 0; 3110 ahc->msgout_len = 0; 3111 ahc_construct_wdtr(ahc, bus_width); 3112 ahc->msgout_index = 0; 3113 response = TRUE; 3114 sending_reply = TRUE; 3115 } 3116 ahc_set_width(ahc, devinfo, bus_width, 3117 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3118 /*paused*/TRUE, /*done*/TRUE); 3119 3120 /* After a wide message, we are async */ 3121 ahc_set_syncrate(ahc, devinfo, 3122 /*syncrate*/NULL, /*period*/0, 3123 /*offset*/0, AHC_TRANS_ACTIVE, 3124 /*paused*/TRUE, /*done*/FALSE); 3125 if (sending_reply == FALSE && reject == FALSE) { 3126 3127 if (tinfo->goal.period) { 3128 struct ahc_syncrate *rate; 3129 u_int period; 3130 u_int offset; 3131 3132 /* Start the sync negotiation */ 3133 period = tinfo->goal.period; 3134 rate = ahc_devlimited_syncrate(ahc, 3135 &period); 3136 offset = tinfo->goal.offset; 3137 ahc_validate_offset(ahc, rate, &offset, 3138 tinfo->current.width); 3139 ahc->msgout_index = 0; 3140 ahc->msgout_len = 0; 3141 ahc_construct_sdtr(ahc, period, offset); 3142 ahc->msgout_index = 0; 3143 response = TRUE; 3144 } 3145 } 3146 done = MSGLOOP_MSGCOMPLETE; 3147 break; 3148 } 3149 default: 3150 /* Unknown extended message. Reject it. */ 3151 reject = TRUE; 3152 break; 3153 } 3154 break; 3155 } 3156 case MSG_BUS_DEV_RESET: 3157 ahc_handle_devreset(ahc, devinfo, 3158 XS_RESET, "Bus Device Reset Received", 3159 /*verbose_level*/0); 3160 restart_sequencer(ahc); 3161 done = MSGLOOP_TERMINATED; 3162 break; 3163 case MSG_ABORT_TAG: 3164 case MSG_ABORT: 3165 case MSG_CLEAR_QUEUE: 3166 /* Target mode messages */ 3167 if (devinfo->role != ROLE_TARGET) { 3168 reject = TRUE; 3169 break; 3170 } 3171 #if AHC_TARGET_MODE 3172 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3173 devinfo->lun, 3174 ahc->msgin_buf[0] == MSG_ABORT_TAG 3175 ? SCB_LIST_NULL 3176 : ahc_inb(ahc, INITIATOR_TAG), 3177 ROLE_TARGET, XS_DRIVER_STUFFUP); 3178 3179 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3180 if (tstate != NULL) { 3181 struct tmode_lstate* lstate; 3182 3183 lstate = tstate->enabled_luns[devinfo->lun]; 3184 if (lstate != NULL) { 3185 ahc_queue_lstate_event(ahc, lstate, 3186 devinfo->our_scsiid, 3187 ahc->msgin_buf[0], 3188 /*arg*/0); 3189 ahc_send_lstate_events(ahc, lstate); 3190 } 3191 } 3192 done = MSGLOOP_MSGCOMPLETE; 3193 #else 3194 panic("ahc: got target mode message"); 3195 #endif 3196 break; 3197 case MSG_TERM_IO_PROC: 3198 default: 3199 reject = TRUE; 3200 break; 3201 } 3202 3203 if (reject) { 3204 /* 3205 * Setup to reject the message. 3206 */ 3207 ahc->msgout_index = 0; 3208 ahc->msgout_len = 1; 3209 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3210 done = MSGLOOP_MSGCOMPLETE; 3211 response = TRUE; 3212 } 3213 3214 if (done != MSGLOOP_IN_PROG && !response) 3215 /* Clear the outgoing message buffer */ 3216 ahc->msgout_len = 0; 3217 3218 return (done); 3219 } 3220 3221 static void 3222 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3223 { 3224 u_int scb_index; 3225 struct scb *scb; 3226 3227 scb_index = ahc_inb(ahc, SCB_TAG); 3228 scb = &ahc->scb_data->scbarray[scb_index]; 3229 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3230 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3231 /* 3232 * Ignore the message if we haven't 3233 * seen an appropriate data phase yet. 3234 */ 3235 } else { 3236 /* 3237 * If the residual occurred on the last 3238 * transfer and the transfer request was 3239 * expected to end on an odd count, do 3240 * nothing. Otherwise, subtract a byte 3241 * and update the residual count accordingly. 3242 */ 3243 u_int resid_sgcnt; 3244 3245 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3246 if (resid_sgcnt == 0 3247 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3248 /* 3249 * If the residual occurred on the last 3250 * transfer and the transfer request was 3251 * expected to end on an odd count, do 3252 * nothing. 3253 */ 3254 } else { 3255 u_int data_cnt; 3256 u_int32_t data_addr; 3257 u_int sg_index; 3258 3259 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3260 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3261 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3262 3263 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3264 | (ahc_inb(ahc, SHADDR + 2) << 16) 3265 | (ahc_inb(ahc, SHADDR + 1) << 8) 3266 | (ahc_inb(ahc, SHADDR)); 3267 3268 data_cnt += 1; 3269 data_addr -= 1; 3270 3271 sg_index = scb->sg_count - resid_sgcnt; 3272 3273 if (sg_index != 0 3274 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3275 u_int32_t sg_addr; 3276 3277 sg_index--; 3278 data_cnt = 1; 3279 data_addr = le32toh(scb->sg_list[sg_index].addr) 3280 + le32toh(scb->sg_list[sg_index].len) 3281 - 1; 3282 3283 /* 3284 * The physical address base points to the 3285 * second entry as it is always used for 3286 * calculating the "next S/G pointer". 3287 */ 3288 sg_addr = scb->sg_list_phys 3289 + (sg_index* sizeof(*scb->sg_list)); 3290 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3291 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3292 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3293 ahc_outb(ahc, SG_NEXT, sg_addr); 3294 } 3295 3296 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3297 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3298 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3299 3300 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3301 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3302 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3303 ahc_outb(ahc, SHADDR, data_addr); 3304 } 3305 } 3306 } 3307 3308 static void 3309 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3310 int status, char *message, 3311 int verbose_level) 3312 { 3313 int found; 3314 3315 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3316 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3317 status); 3318 3319 /* 3320 * Go back to async/narrow transfers and renegotiate. 3321 * ahc_set_width and ahc_set_syncrate can cope with NULL 3322 * paths. 3323 */ 3324 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3325 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3326 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3327 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3328 /*paused*/TRUE, /*done*/FALSE); 3329 3330 if (message != NULL && (verbose_level <= 0)) 3331 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3332 message, devinfo->channel, devinfo->target, found); 3333 } 3334 3335 /* 3336 * We have an scb which has been processed by the 3337 * adaptor, now we look to see how the operation 3338 * went. 3339 */ 3340 static void 3341 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3342 { 3343 struct scsipi_xfer *xs; 3344 struct scsipi_link *sc_link; 3345 int requeue = 0; 3346 int target; 3347 3348 3349 xs = scb->xs; 3350 sc_link = xs->sc_link; 3351 LIST_REMOVE(scb, plinks); 3352 3353 callout_stop(&scb->xs->xs_callout); 3354 3355 #ifdef AHC_DEBUG 3356 if (ahc_debug & AHC_SHOWCMDS) { 3357 scsi_print_addr(sc_link); 3358 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3359 scb->hscb->tag); 3360 } 3361 #endif 3362 3363 target = sc_link->scsipi_scsi.target; 3364 3365 if (xs->datalen) { 3366 int op; 3367 3368 if (xs->xs_control & XS_CTL_DATA_IN) 3369 op = BUS_DMASYNC_POSTREAD; 3370 else 3371 op = BUS_DMASYNC_POSTWRITE; 3372 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3373 scb->dmamap->dm_mapsize, op); 3374 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3375 } 3376 3377 /* 3378 * Unbusy this target/channel/lun. 3379 * XXX if we are holding two commands per lun, 3380 * send the next command. 3381 */ 3382 if (!(scb->hscb->control & TAG_ENB)) 3383 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3384 3385 /* 3386 * If the recovery SCB completes, we have to be 3387 * out of our timeout. 3388 */ 3389 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3390 3391 struct scb *scbp; 3392 3393 /* 3394 * We were able to complete the command successfully, 3395 * so reinstate the timeouts for all other pending 3396 * commands. 3397 */ 3398 scbp = ahc->pending_ccbs.lh_first; 3399 while (scbp != NULL) { 3400 struct scsipi_xfer *txs = scbp->xs; 3401 3402 if (!(txs->xs_control & XS_CTL_POLL)) { 3403 callout_reset(&scbp->xs->xs_callout, 3404 (scbp->xs->timeout * hz) / 1000, 3405 ahc_timeout, scbp); 3406 } 3407 scbp = LIST_NEXT(scbp, plinks); 3408 } 3409 3410 /* 3411 * Ensure that we didn't put a second instance of this 3412 * SCB into the QINFIFO. 3413 */ 3414 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3415 SCB_LUN(scb), scb->hscb->tag, 3416 ROLE_INITIATOR, /*status*/0, 3417 SEARCH_REMOVE); 3418 if (xs->error != XS_NOERROR) 3419 ahcsetccbstatus(xs, XS_TIMEOUT); 3420 scsi_print_addr(xs->sc_link); 3421 printf("no longer in timeout, status = %x\n", xs->status); 3422 } 3423 3424 if (xs->error != XS_NOERROR) { 3425 /* Don't clobber any existing error state */ 3426 } else if ((scb->flags & SCB_SENSE) != 0) { 3427 /* 3428 * We performed autosense retrieval. 3429 * 3430 * bzero the sense data before having 3431 * the drive fill it. The SCSI spec mandates 3432 * that any untransfered data should be 3433 * assumed to be zero. Complete the 'bounce' 3434 * of sense information through buffers accessible 3435 * via bus-space by copying it into the clients 3436 * csio. 3437 */ 3438 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3439 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3440 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3441 xs->error = XS_SENSE; 3442 } 3443 if (scb->flags & SCB_FREEZE_QUEUE) { 3444 ahc->devqueue_blocked[target]--; 3445 scb->flags &= ~SCB_FREEZE_QUEUE; 3446 } 3447 3448 requeue = scb->flags & SCB_REQUEUE; 3449 ahcfreescb(ahc, scb); 3450 3451 if (requeue) { 3452 /* 3453 * Re-insert at the front of the private queue to 3454 * preserve order. 3455 */ 3456 int s; 3457 3458 if (xs->xs_status & XS_STS_DEBUG) { 3459 scsi_print_addr(xs->sc_link); 3460 printf("putting SCB that caused queue full back" 3461 " in queue\n"); 3462 } 3463 3464 s = splbio(); 3465 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3466 splx(s); 3467 } else { 3468 if (xs->xs_status & XS_STS_DEBUG) { 3469 xs->xs_status &= ~XS_STS_DEBUG; 3470 scsi_print_addr(xs->sc_link); 3471 printf("completed SCB that caused queue full\n"); 3472 } 3473 xs->xs_status |= XS_STS_DONE; 3474 ahc_check_tags(ahc, xs); 3475 scsipi_done(xs); 3476 } 3477 3478 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3479 ahc_action(xs); 3480 } 3481 3482 /* 3483 * Determine the number of SCBs available on the controller 3484 */ 3485 int 3486 ahc_probe_scbs(struct ahc_softc *ahc) { 3487 int i; 3488 3489 for (i = 0; i < AHC_SCB_MAX; i++) { 3490 ahc_outb(ahc, SCBPTR, i); 3491 ahc_outb(ahc, SCB_CONTROL, i); 3492 if (ahc_inb(ahc, SCB_CONTROL) != i) 3493 break; 3494 ahc_outb(ahc, SCBPTR, 0); 3495 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3496 break; 3497 } 3498 return (i); 3499 } 3500 3501 /* 3502 * Start the board, ready for normal operation 3503 */ 3504 int 3505 ahc_init(struct ahc_softc *ahc) 3506 { 3507 int max_targ = 15; 3508 int i; 3509 int term; 3510 u_int scsi_conf; 3511 u_int scsiseq_template; 3512 u_int ultraenb; 3513 u_int discenable; 3514 u_int tagenable; 3515 size_t driver_data_size; 3516 u_int32_t physaddr; 3517 3518 #ifdef AHC_PRINT_SRAM 3519 printf("Scratch Ram:"); 3520 for (i = 0x20; i < 0x5f; i++) { 3521 if (((i % 8) == 0) && (i != 0)) { 3522 printf ("\n "); 3523 } 3524 printf (" 0x%x", ahc_inb(ahc, i)); 3525 } 3526 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3527 for (i = 0x70; i < 0x7f; i++) { 3528 if (((i % 8) == 0) && (i != 0)) { 3529 printf ("\n "); 3530 } 3531 printf (" 0x%x", ahc_inb(ahc, i)); 3532 } 3533 } 3534 printf ("\n"); 3535 #endif 3536 3537 /* 3538 * Assume we have a board at this stage and it has been reset. 3539 */ 3540 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3541 ahc->our_id = ahc->our_id_b = 7; 3542 3543 /* 3544 * Default to allowing initiator operations. 3545 */ 3546 ahc->flags |= AHC_INITIATORMODE; 3547 3548 /* 3549 * DMA tag for our command fifos and other data in system memory 3550 * the card's sequencer must be able to access. For initiator 3551 * roles, we need to allocate space for the qinfifo, qoutfifo, 3552 * and untagged_scb arrays each of which are composed of 256 3553 * 1 byte elements. When providing for the target mode role, 3554 * we additionally must provide space for the incoming target 3555 * command fifo. 3556 */ 3557 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3558 3559 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3560 ahc->sc_dmaflags, 3561 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3562 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3563 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3564 return (ENOMEM); 3565 3566 ahc->init_level++; 3567 3568 /* Allocate SCB data now that parent_dmat is initialized */ 3569 if (ahc->scb_data->maxhscbs == 0) 3570 if (ahcinitscbdata(ahc) != 0) 3571 return (ENOMEM); 3572 3573 ahc->qinfifo = &ahc->qoutfifo[256]; 3574 ahc->untagged_scbs = &ahc->qinfifo[256]; 3575 /* There are no untagged SCBs active yet. */ 3576 for (i = 0; i < 256; i++) 3577 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3578 3579 /* All of our queues are empty */ 3580 for (i = 0; i < 256; i++) 3581 ahc->qoutfifo[i] = SCB_LIST_NULL; 3582 3583 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3584 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3585 3586 /* 3587 * Allocate a tstate to house information for our 3588 * initiator presence on the bus as well as the user 3589 * data for any target mode initiator. 3590 */ 3591 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3592 printf("%s: unable to allocate tmode_tstate. " 3593 "Failing attach\n", ahc_name(ahc)); 3594 return (-1); 3595 } 3596 3597 if ((ahc->features & AHC_TWIN) != 0) { 3598 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3599 printf("%s: unable to allocate tmode_tstate. " 3600 "Failing attach\n", ahc_name(ahc)); 3601 return (-1); 3602 } 3603 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3604 ahc->our_id, ahc->our_id_b, 3605 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3606 } else { 3607 if ((ahc->features & AHC_WIDE) != 0) { 3608 printf("Wide "); 3609 } else { 3610 printf("Single "); 3611 } 3612 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3613 } 3614 3615 ahc_outb(ahc, SEQ_FLAGS, 0); 3616 3617 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3618 ahc->flags |= AHC_PAGESCBS; 3619 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3620 } else { 3621 ahc->flags &= ~AHC_PAGESCBS; 3622 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3623 } 3624 3625 #ifdef AHC_DEBUG 3626 if (ahc_debug & AHC_SHOWMISC) { 3627 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3628 "ahc_dma %d bytes\n", 3629 ahc_name(ahc), 3630 sizeof(struct hardware_scb), 3631 sizeof(struct scb), 3632 sizeof(struct ahc_dma_seg)); 3633 } 3634 #endif /* AHC_DEBUG */ 3635 3636 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3637 if (ahc->features & AHC_TWIN) { 3638 3639 /* 3640 * The device is gated to channel B after a chip reset, 3641 * so set those values first 3642 */ 3643 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3644 if ((ahc->features & AHC_ULTRA2) != 0) 3645 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3646 else 3647 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3648 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3649 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3650 |term|ENSTIMER|ACTNEGEN); 3651 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3652 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3653 3654 if ((scsi_conf & RESET_SCSI) != 0 3655 && (ahc->flags & AHC_INITIATORMODE) != 0) 3656 ahc->flags |= AHC_RESET_BUS_B; 3657 3658 /* Select Channel A */ 3659 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3660 } 3661 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3662 if ((ahc->features & AHC_ULTRA2) != 0) 3663 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3664 else 3665 ahc_outb(ahc, SCSIID, ahc->our_id); 3666 scsi_conf = ahc_inb(ahc, SCSICONF); 3667 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3668 |term 3669 |ENSTIMER|ACTNEGEN); 3670 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3671 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3672 3673 if ((scsi_conf & RESET_SCSI) != 0 3674 && (ahc->flags & AHC_INITIATORMODE) != 0) 3675 ahc->flags |= AHC_RESET_BUS_A; 3676 3677 /* 3678 * Look at the information that board initialization or 3679 * the board bios has left us. 3680 */ 3681 ultraenb = 0; 3682 tagenable = ALL_TARGETS_MASK; 3683 3684 /* Grab the disconnection disable table and invert it for our needs */ 3685 if (ahc->flags & AHC_USEDEFAULTS) { 3686 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3687 "device parameters\n", ahc_name(ahc)); 3688 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3689 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3690 discenable = ALL_TARGETS_MASK; 3691 if ((ahc->features & AHC_ULTRA) != 0) 3692 ultraenb = ALL_TARGETS_MASK; 3693 } else { 3694 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3695 | ahc_inb(ahc, DISC_DSB)); 3696 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3697 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3698 | ahc_inb(ahc, ULTRA_ENB); 3699 } 3700 3701 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3702 max_targ = 7; 3703 3704 for (i = 0; i <= max_targ; i++) { 3705 struct ahc_initiator_tinfo *tinfo; 3706 struct tmode_tstate *tstate; 3707 u_int our_id; 3708 u_int target_id; 3709 char channel; 3710 3711 channel = 'A'; 3712 our_id = ahc->our_id; 3713 target_id = i; 3714 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3715 channel = 'B'; 3716 our_id = ahc->our_id_b; 3717 target_id = i % 8; 3718 } 3719 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3720 target_id, &tstate); 3721 /* Default to async narrow across the board */ 3722 bzero(tinfo, sizeof(*tinfo)); 3723 if (ahc->flags & AHC_USEDEFAULTS) { 3724 if ((ahc->features & AHC_WIDE) != 0) 3725 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3726 3727 /* 3728 * These will be truncated when we determine the 3729 * connection type we have with the target. 3730 */ 3731 tinfo->user.period = ahc_syncrates->period; 3732 tinfo->user.offset = ~0; 3733 } else { 3734 u_int scsirate; 3735 u_int16_t mask; 3736 3737 /* Take the settings leftover in scratch RAM. */ 3738 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3739 mask = (0x01 << i); 3740 if ((ahc->features & AHC_ULTRA2) != 0) { 3741 u_int offset; 3742 u_int maxsync; 3743 3744 if ((scsirate & SOFS) == 0x0F) { 3745 /* 3746 * Haven't negotiated yet, 3747 * so the format is different. 3748 */ 3749 scsirate = (scsirate & SXFR) >> 4 3750 | (ultraenb & mask) 3751 ? 0x08 : 0x0 3752 | (scsirate & WIDEXFER); 3753 offset = MAX_OFFSET_ULTRA2; 3754 } else 3755 offset = ahc_inb(ahc, TARG_OFFSET + i); 3756 maxsync = AHC_SYNCRATE_ULTRA2; 3757 if ((ahc->features & AHC_DT) != 0) 3758 maxsync = AHC_SYNCRATE_DT; 3759 tinfo->user.period = 3760 ahc_find_period(ahc, scsirate, maxsync); 3761 if (offset == 0) 3762 tinfo->user.period = 0; 3763 else 3764 tinfo->user.offset = ~0; 3765 } else if ((scsirate & SOFS) != 0) { 3766 tinfo->user.period = 3767 ahc_find_period(ahc, scsirate, 3768 (ultraenb & mask) 3769 ? AHC_SYNCRATE_ULTRA 3770 : AHC_SYNCRATE_FAST); 3771 if (tinfo->user.period != 0) 3772 tinfo->user.offset = ~0; 3773 } 3774 if ((scsirate & WIDEXFER) != 0 3775 && (ahc->features & AHC_WIDE) != 0) 3776 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3777 } 3778 tinfo->goal = tinfo->user; /* force negotiation */ 3779 tstate->ultraenb = ultraenb; 3780 tstate->discenable = discenable; 3781 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3782 tstate->tagdisable = 0; 3783 } 3784 ahc->user_discenable = discenable; 3785 ahc->user_tagenable = tagenable; 3786 3787 /* 3788 * Tell the sequencer where it can find our arrays in memory. 3789 */ 3790 physaddr = ahc->scb_data->hscb_busaddr; 3791 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3792 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3793 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3794 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3795 3796 physaddr = ahc->shared_data_busaddr; 3797 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3798 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3799 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3800 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3801 3802 /* Target mode incomding command fifo */ 3803 physaddr += 3 * 256 * sizeof(u_int8_t); 3804 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3805 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3806 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3807 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3808 3809 /* 3810 * Initialize the group code to command length table. 3811 * This overrides the values in TARG_SCSIRATE, so only 3812 * setup the table after we have processed that information. 3813 */ 3814 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3815 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3816 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3817 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3818 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3819 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3820 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3821 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3822 3823 /* Tell the sequencer of our initial queue positions */ 3824 ahc_outb(ahc, KERNEL_QINPOS, 0); 3825 ahc_outb(ahc, QINPOS, 0); 3826 ahc_outb(ahc, QOUTPOS, 0); 3827 3828 #ifdef AHC_DEBUG 3829 if (ahc_debug & AHC_SHOWMISC) 3830 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3831 discenable, ultraenb); 3832 #endif 3833 3834 /* Don't have any special messages to send to targets */ 3835 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3836 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3837 3838 /* 3839 * Use the built in queue management registers 3840 * if they are available. 3841 */ 3842 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3843 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3844 ahc_outb(ahc, SDSCB_QOFF, 0); 3845 ahc_outb(ahc, SNSCB_QOFF, 0); 3846 ahc_outb(ahc, HNSCB_QOFF, 0); 3847 } 3848 3849 3850 /* We don't have any waiting selections */ 3851 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3852 3853 /* Our disconnection list is empty too */ 3854 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3855 3856 /* Message out buffer starts empty */ 3857 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3858 3859 /* 3860 * Setup the allowed SCSI Sequences based on operational mode. 3861 * If we are a target, we'll enalbe select in operations once 3862 * we've had a lun enabled. 3863 */ 3864 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3865 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3866 scsiseq_template |= ENRSELI; 3867 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3868 3869 /* 3870 * Load the Sequencer program and Enable the adapter 3871 * in "fast" mode. 3872 */ 3873 #ifdef AHC_DEBUG 3874 printf("%s: Downloading Sequencer Program...", 3875 ahc_name(ahc)); 3876 #endif 3877 3878 ahc_loadseq(ahc); 3879 3880 /* We have to wait until after any system dumps... */ 3881 shutdownhook_establish(ahc_shutdown, ahc); 3882 3883 return (0); 3884 } 3885 3886 static int 3887 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3888 struct proc *p) 3889 { 3890 struct ahc_softc *ahc = sc_link->adapter_softc; 3891 char channel; 3892 int s, ret = ENOTTY; 3893 3894 switch (cmd) { 3895 case SCBUSIORESET: 3896 channel = SIM_CHANNEL(ahc, sc_link); 3897 s = splbio(); 3898 ahc_reset_channel(ahc, channel, TRUE); 3899 splx(s); 3900 ret = 0; 3901 break; 3902 default: 3903 } 3904 3905 return ret; 3906 } 3907 3908 3909 /* 3910 * XXX fvdl the busy_tcl checks and settings should only be done 3911 * for the non-tagged queueing case, but we don't do tagged queueing 3912 * yet, so.. 3913 */ 3914 static int32_t 3915 ahc_action(struct scsipi_xfer *xs) 3916 { 3917 struct scsipi_xfer *first_xs, *next_xs = NULL; 3918 struct ahc_softc *ahc; 3919 struct scb *scb; 3920 struct hardware_scb *hscb; 3921 struct ahc_initiator_tinfo *tinfo; 3922 struct tmode_tstate *tstate; 3923 u_int target_id; 3924 u_int our_id; 3925 int s, tcl; 3926 u_int16_t mask; 3927 char channel; 3928 int dontqueue = 0, fromqueue = 0; 3929 3930 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3931 3932 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3933 3934 /* must protect the queue */ 3935 s = splbio(); 3936 3937 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3938 /* 3939 * Called from ahc_done. Calling with the first entry in 3940 * the queue is really just a way of seeing where we're 3941 * called from. Now, find the first eligible SCB to send, 3942 * e.g. one which will be accepted immediately. 3943 */ 3944 3945 if (ahc->queue_blocked) { 3946 splx(s); 3947 return (TRY_AGAIN_LATER); 3948 } 3949 3950 xs = ahc_first_xs(ahc); 3951 if (xs == NULL) { 3952 splx(s); 3953 return (TRY_AGAIN_LATER); 3954 } 3955 3956 next_xs = TAILQ_NEXT(xs, adapter_q); 3957 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3958 fromqueue = 1; 3959 goto get_scb; 3960 } 3961 3962 /* 3963 * If no new requests are accepted, just insert into the 3964 * private queue to wait for our turn. 3965 */ 3966 tcl = XS_TCL(ahc, xs); 3967 3968 if (ahc->queue_blocked || 3969 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3970 (!ahc_istagged_device(ahc, xs, 0) && 3971 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3972 if (dontqueue) { 3973 splx(s); 3974 xs->error = XS_DRIVER_STUFFUP; 3975 return TRY_AGAIN_LATER; 3976 } 3977 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3978 splx(s); 3979 return SUCCESSFULLY_QUEUED; 3980 } 3981 3982 first_xs = ahc_first_xs(ahc); 3983 3984 /* determine safety of software queueing */ 3985 dontqueue = xs->xs_control & XS_CTL_POLL; 3986 3987 /* 3988 * Handle situations where there's already entries in the 3989 * queue. 3990 */ 3991 if (first_xs != NULL) { 3992 /* 3993 * If we can't queue, we have to abort, since 3994 * we have to preserve order. 3995 */ 3996 if (dontqueue) { 3997 splx(s); 3998 xs->error = XS_DRIVER_STUFFUP; 3999 return (TRY_AGAIN_LATER); 4000 } 4001 4002 /* 4003 * Swap with the first queue entry. 4004 */ 4005 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4006 xs = first_xs; 4007 next_xs = TAILQ_NEXT(xs, adapter_q); 4008 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 4009 fromqueue = 1; 4010 4011 } 4012 4013 get_scb: 4014 4015 target_id = xs->sc_link->scsipi_scsi.target; 4016 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 4017 4018 /* 4019 * get an scb to use. 4020 */ 4021 if ((scb = ahcgetscb(ahc)) == NULL) { 4022 4023 if (dontqueue) { 4024 splx(s); 4025 xs->error = XS_DRIVER_STUFFUP; 4026 return (TRY_AGAIN_LATER); 4027 } 4028 4029 /* 4030 * If we were pulled off the queue, put ourselves 4031 * back to where we came from, otherwise tack ourselves 4032 * onto the end. 4033 */ 4034 if (fromqueue && next_xs != NULL) 4035 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 4036 else 4037 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4038 4039 splx(s); 4040 return (SUCCESSFULLY_QUEUED); 4041 } 4042 4043 tcl = XS_TCL(ahc, xs); 4044 4045 #ifdef DIAGNOSTIC 4046 if (!ahc_istagged_device(ahc, xs, 0) && 4047 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4048 panic("ahc: queuing for busy target"); 4049 #endif 4050 4051 scb->xs = xs; 4052 hscb = scb->hscb; 4053 hscb->tcl = tcl; 4054 4055 if (ahc_istagged_device(ahc, xs, 0)) 4056 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4057 else 4058 ahc_busy_tcl(ahc, scb); 4059 4060 splx(s); 4061 4062 channel = SIM_CHANNEL(ahc, xs->sc_link); 4063 if (ahc->inited_channels[channel - 'A'] == 0) { 4064 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4065 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4066 s = splbio(); 4067 ahc_reset_channel(ahc, channel, TRUE); 4068 splx(s); 4069 } 4070 ahc->inited_channels[channel - 'A'] = 1; 4071 } 4072 4073 /* 4074 * Put all the arguments for the xfer in the scb 4075 */ 4076 4077 mask = SCB_TARGET_MASK(scb); 4078 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4079 target_id, &tstate); 4080 if (ahc->inited_targets[target_id] == 0) { 4081 struct ahc_devinfo devinfo; 4082 4083 s = splbio(); 4084 ahc_compile_devinfo(&devinfo, our_id, target_id, 4085 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4086 ROLE_INITIATOR); 4087 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4088 FALSE); 4089 ahc->inited_targets[target_id] = 1; 4090 splx(s); 4091 } 4092 4093 hscb->scsirate = tinfo->scsirate; 4094 hscb->scsioffset = tinfo->current.offset; 4095 if ((tstate->ultraenb & mask) != 0) 4096 hscb->control |= ULTRAENB; 4097 4098 if ((tstate->discenable & mask) != 0) 4099 hscb->control |= DISCENB; 4100 4101 if (xs->xs_status & XS_STS_DEBUG) { 4102 scsi_print_addr(xs->sc_link); 4103 printf("redoing command that caused queue full\n"); 4104 } 4105 4106 if (xs->xs_control & XS_CTL_RESET) { 4107 hscb->cmdpointer = 0; 4108 scb->flags |= SCB_DEVICE_RESET; 4109 hscb->control |= MK_MESSAGE; 4110 return ahc_execute_scb(scb, NULL, 0); 4111 } 4112 4113 return ahc_setup_data(ahc, xs, scb); 4114 } 4115 4116 static int 4117 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4118 { 4119 struct scb *scb; 4120 struct scsipi_xfer *xs; 4121 struct ahc_softc *ahc; 4122 int s; 4123 4124 scb = (struct scb *)arg; 4125 xs = scb->xs; 4126 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4127 4128 4129 if (nsegments != 0) { 4130 struct ahc_dma_seg *sg; 4131 bus_dma_segment_t *end_seg; 4132 int op; 4133 4134 end_seg = dm_segs + nsegments; 4135 4136 /* Copy the first SG into the data pointer area */ 4137 scb->hscb->data = dm_segs->ds_addr; 4138 scb->hscb->datalen = dm_segs->ds_len; 4139 4140 /* Copy the segments into our SG list */ 4141 sg = scb->sg_list; 4142 while (dm_segs < end_seg) { 4143 sg->addr = dm_segs->ds_addr; 4144 sg->len = dm_segs->ds_len; 4145 ahc_swap_sg(sg); 4146 sg++; 4147 dm_segs++; 4148 } 4149 4150 /* Note where to find the SG entries in bus space */ 4151 scb->hscb->SG_pointer = scb->sg_list_phys; 4152 4153 if (xs->xs_control & XS_CTL_DATA_IN) 4154 op = BUS_DMASYNC_PREREAD; 4155 else 4156 op = BUS_DMASYNC_PREWRITE; 4157 4158 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4159 scb->dmamap->dm_mapsize, op); 4160 4161 } else { 4162 scb->hscb->SG_pointer = 0; 4163 scb->hscb->data = 0; 4164 scb->hscb->datalen = 0; 4165 } 4166 4167 scb->sg_count = scb->hscb->SG_count = nsegments; 4168 4169 s = splbio(); 4170 4171 /* 4172 * Last time we need to check if this SCB needs to 4173 * be aborted. 4174 */ 4175 if (xs->xs_status & XS_STS_DONE) { 4176 if (!ahc_istagged_device(ahc, xs, 0)) 4177 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4178 if (nsegments != 0) 4179 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4180 ahcfreescb(ahc, scb); 4181 splx(s); 4182 return (COMPLETE); 4183 } 4184 4185 #ifdef DIAGNOSTIC 4186 if (scb->sg_count > 255) 4187 panic("ahc bad sg_count"); 4188 #endif 4189 4190 ahc_swap_hscb(scb->hscb); 4191 4192 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4193 4194 scb->flags |= SCB_ACTIVE; 4195 4196 if (!(xs->xs_control & XS_CTL_POLL)) 4197 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4198 ahc_timeout, scb); 4199 4200 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4201 #if 0 4202 printf("Continueing Immediate Command %d:%d\n", 4203 xs->sc_link->scsipi_scsi.target, 4204 xs->sc_link->scsipi_scsi.lun); 4205 #endif 4206 pause_sequencer(ahc); 4207 if ((ahc->flags & AHC_PAGESCBS) == 0) 4208 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4209 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4210 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4211 unpause_sequencer(ahc); 4212 } else { 4213 4214 #if 0 4215 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4216 scb->hscb->tag, ahc->qinfifonext, 4217 &ahc->qinfifo[ahc->qinfifonext], 4218 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4219 #endif 4220 4221 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4222 4223 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4224 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4225 4226 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4227 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4228 } else { 4229 pause_sequencer(ahc); 4230 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4231 unpause_sequencer(ahc); 4232 } 4233 } 4234 4235 #ifdef AHC_DEBUG 4236 if (ahc_debug & AHC_SHOWCMDS) { 4237 scsi_print_addr(xs->sc_link); 4238 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4239 " rate %x\n", 4240 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4241 scb->flags, scb->hscb->control, ahc->qinfifonext, 4242 scb->hscb->scsirate); 4243 } 4244 #endif 4245 4246 if (!(xs->xs_control & XS_CTL_POLL)) { 4247 splx(s); 4248 return (SUCCESSFULLY_QUEUED); 4249 } 4250 /* 4251 * If we can't use interrupts, poll for completion 4252 */ 4253 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4254 do { 4255 if (ahc_poll(ahc, xs->timeout)) { 4256 if (!(xs->xs_control & XS_CTL_SILENT)) 4257 printf("cmd fail\n"); 4258 ahc_timeout(scb); 4259 break; 4260 } 4261 } while (!(xs->xs_status & XS_STS_DONE)); 4262 splx(s); 4263 return (COMPLETE); 4264 } 4265 4266 static int 4267 ahc_poll(struct ahc_softc *ahc, int wait) 4268 { 4269 while (--wait) { 4270 DELAY(1000); 4271 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4272 break; 4273 } 4274 4275 if (wait == 0) { 4276 printf("%s: board is not responding\n", ahc_name(ahc)); 4277 return (EIO); 4278 } 4279 4280 ahc_intr((void *)ahc); 4281 return (0); 4282 } 4283 4284 static int 4285 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4286 struct scb *scb) 4287 { 4288 struct hardware_scb *hscb; 4289 4290 hscb = scb->hscb; 4291 xs->resid = xs->status = 0; 4292 4293 hscb->cmdlen = xs->cmdlen; 4294 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4295 hscb->cmdpointer = hscb->cmdstore_busaddr; 4296 4297 /* Only use S/G if there is a transfer */ 4298 if (xs->datalen) { 4299 int error; 4300 4301 error = bus_dmamap_load(ahc->parent_dmat, 4302 scb->dmamap, xs->data, 4303 xs->datalen, NULL, 4304 (xs->xs_control & XS_CTL_NOSLEEP) ? 4305 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4306 if (error) { 4307 if (!ahc_istagged_device(ahc, xs, 0)) 4308 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4309 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4310 } 4311 error = ahc_execute_scb(scb, 4312 scb->dmamap->dm_segs, 4313 scb->dmamap->dm_nsegs); 4314 return error; 4315 } else { 4316 return ahc_execute_scb(scb, NULL, 0); 4317 } 4318 } 4319 4320 static void 4321 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4322 { 4323 int target; 4324 char channel; 4325 int lun; 4326 4327 target = sc_link->scsipi_scsi.target; 4328 lun = sc_link->scsipi_scsi.lun; 4329 channel = sc_link->scsipi_scsi.channel; 4330 4331 ahc_search_qinfifo(ahc, target, channel, lun, 4332 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4333 SCB_REQUEUE, SEARCH_COMPLETE); 4334 } 4335 4336 static void 4337 ahcallocscbs(struct ahc_softc *ahc) 4338 { 4339 struct scb_data *scb_data; 4340 struct scb *next_scb; 4341 struct sg_map_node *sg_map; 4342 bus_addr_t physaddr; 4343 struct ahc_dma_seg *segs; 4344 int newcount; 4345 int i; 4346 4347 scb_data = ahc->scb_data; 4348 if (scb_data->numscbs >= AHC_SCB_MAX) 4349 /* Can't allocate any more */ 4350 return; 4351 4352 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4353 4354 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4355 4356 if (sg_map == NULL) 4357 return; 4358 4359 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4360 &sg_map->sg_dmamap, 4361 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4362 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4363 "SG space") < 0) { 4364 free(sg_map, M_DEVBUF); 4365 return; 4366 } 4367 4368 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4369 4370 segs = sg_map->sg_vaddr; 4371 physaddr = sg_map->sg_physaddr; 4372 4373 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4374 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4375 int error; 4376 4377 next_scb->sg_list = segs; 4378 /* 4379 * The sequencer always starts with the second entry. 4380 * The first entry is embedded in the scb. 4381 */ 4382 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4383 next_scb->flags = SCB_FREE; 4384 error = bus_dmamap_create(ahc->parent_dmat, 4385 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4386 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4387 &next_scb->dmamap); 4388 if (error != 0) 4389 break; 4390 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4391 next_scb->hscb->tag = ahc->scb_data->numscbs; 4392 next_scb->hscb->cmdstore_busaddr = 4393 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4394 + offsetof(struct hardware_scb, cmdstore); 4395 next_scb->hscb->cmdstore_busaddr = 4396 htole32(next_scb->hscb->cmdstore_busaddr); 4397 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4398 segs += AHC_NSEG; 4399 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4400 next_scb++; 4401 ahc->scb_data->numscbs++; 4402 } 4403 #ifdef AHC_DEBUG 4404 if (ahc_debug & AHC_SHOWSCBALLOC) 4405 printf("%s: allocated %d new SCBs count now %d\n", 4406 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4407 #endif 4408 } 4409 4410 #ifdef AHC_DUMP_SEQ 4411 static void 4412 ahc_dumpseq(struct ahc_softc* ahc) 4413 { 4414 int i; 4415 int max_prog; 4416 4417 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4418 max_prog = 448; 4419 else if ((ahc->features & AHC_ULTRA2) != 0) 4420 max_prog = 768; 4421 else 4422 max_prog = 512; 4423 4424 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4425 ahc_outb(ahc, SEQADDR0, 0); 4426 ahc_outb(ahc, SEQADDR1, 0); 4427 for (i = 0; i < max_prog; i++) { 4428 u_int8_t ins_bytes[4]; 4429 4430 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4431 printf("0x%08x\n", ins_bytes[0] << 24 4432 | ins_bytes[1] << 16 4433 | ins_bytes[2] << 8 4434 | ins_bytes[3]); 4435 } 4436 } 4437 #endif 4438 4439 static void 4440 ahc_loadseq(struct ahc_softc *ahc) 4441 { 4442 struct patch *cur_patch; 4443 int i; 4444 int downloaded; 4445 int skip_addr; 4446 u_int8_t download_consts[4]; 4447 4448 /* Setup downloadable constant table */ 4449 #if 0 4450 /* No downloaded constants are currently defined. */ 4451 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4452 #endif 4453 4454 cur_patch = patches; 4455 downloaded = 0; 4456 skip_addr = 0; 4457 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4458 ahc_outb(ahc, SEQADDR0, 0); 4459 ahc_outb(ahc, SEQADDR1, 0); 4460 4461 for (i = 0; i < sizeof(seqprog)/4; i++) { 4462 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4463 /* 4464 * Don't download this instruction as it 4465 * is in a patch that was removed. 4466 */ 4467 continue; 4468 } 4469 ahc_download_instr(ahc, i, download_consts); 4470 downloaded++; 4471 } 4472 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4473 restart_sequencer(ahc); 4474 4475 #ifdef AHC_DEBUG 4476 printf(" %d instructions downloaded\n", downloaded); 4477 #endif 4478 } 4479 4480 static int 4481 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4482 int start_instr, int *skip_addr) 4483 { 4484 struct patch *cur_patch; 4485 struct patch *last_patch; 4486 int num_patches; 4487 4488 num_patches = sizeof(patches)/sizeof(struct patch); 4489 last_patch = &patches[num_patches]; 4490 cur_patch = *start_patch; 4491 4492 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4493 4494 if (cur_patch->patch_func(ahc) == 0) { 4495 4496 /* Start rejecting code */ 4497 *skip_addr = start_instr + cur_patch->skip_instr; 4498 cur_patch += cur_patch->skip_patch; 4499 } else { 4500 /* Accepted this patch. Advance to the next 4501 * one and wait for our intruction pointer to 4502 * hit this point. 4503 */ 4504 cur_patch++; 4505 } 4506 } 4507 4508 *start_patch = cur_patch; 4509 if (start_instr < *skip_addr) 4510 /* Still skipping */ 4511 return (0); 4512 4513 return (1); 4514 } 4515 4516 static void 4517 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4518 { 4519 union ins_formats instr; 4520 struct ins_format1 *fmt1_ins; 4521 struct ins_format3 *fmt3_ins; 4522 u_int opcode; 4523 4524 /* Structure copy */ 4525 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4526 4527 instr.integer = le32toh(instr.integer); 4528 4529 fmt1_ins = &instr.format1; 4530 fmt3_ins = NULL; 4531 4532 /* Pull the opcode */ 4533 opcode = instr.format1.opcode; 4534 switch (opcode) { 4535 case AIC_OP_JMP: 4536 case AIC_OP_JC: 4537 case AIC_OP_JNC: 4538 case AIC_OP_CALL: 4539 case AIC_OP_JNE: 4540 case AIC_OP_JNZ: 4541 case AIC_OP_JE: 4542 case AIC_OP_JZ: 4543 { 4544 struct patch *cur_patch; 4545 int address_offset; 4546 u_int address; 4547 int skip_addr; 4548 int i; 4549 4550 fmt3_ins = &instr.format3; 4551 address_offset = 0; 4552 address = fmt3_ins->address; 4553 cur_patch = patches; 4554 skip_addr = 0; 4555 4556 for (i = 0; i < address;) { 4557 4558 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4559 4560 if (skip_addr > i) { 4561 int end_addr; 4562 4563 end_addr = MIN(address, skip_addr); 4564 address_offset += end_addr - i; 4565 i = skip_addr; 4566 } else { 4567 i++; 4568 } 4569 } 4570 address -= address_offset; 4571 fmt3_ins->address = address; 4572 /* FALLTHROUGH */ 4573 } 4574 case AIC_OP_OR: 4575 case AIC_OP_AND: 4576 case AIC_OP_XOR: 4577 case AIC_OP_ADD: 4578 case AIC_OP_ADC: 4579 case AIC_OP_BMOV: 4580 if (fmt1_ins->parity != 0) { 4581 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4582 } 4583 fmt1_ins->parity = 0; 4584 /* FALLTHROUGH */ 4585 case AIC_OP_ROL: 4586 if ((ahc->features & AHC_ULTRA2) != 0) { 4587 int i, count; 4588 4589 /* Calculate odd parity for the instruction */ 4590 for (i = 0, count = 0; i < 31; i++) { 4591 u_int32_t mask; 4592 4593 mask = 0x01 << i; 4594 if ((instr.integer & mask) != 0) 4595 count++; 4596 } 4597 if ((count & 0x01) == 0) 4598 instr.format1.parity = 1; 4599 } else { 4600 /* Compress the instruction for older sequencers */ 4601 if (fmt3_ins != NULL) { 4602 instr.integer = 4603 fmt3_ins->immediate 4604 | (fmt3_ins->source << 8) 4605 | (fmt3_ins->address << 16) 4606 | (fmt3_ins->opcode << 25); 4607 } else { 4608 instr.integer = 4609 fmt1_ins->immediate 4610 | (fmt1_ins->source << 8) 4611 | (fmt1_ins->destination << 16) 4612 | (fmt1_ins->ret << 24) 4613 | (fmt1_ins->opcode << 25); 4614 } 4615 } 4616 instr.integer = htole32(instr.integer); 4617 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4618 break; 4619 default: 4620 panic("Unknown opcode encountered in seq program"); 4621 break; 4622 } 4623 } 4624 4625 static void 4626 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4627 { 4628 4629 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4630 struct scb *scbp; 4631 4632 scb->flags |= SCB_RECOVERY_SCB; 4633 4634 /* 4635 * Take all queued, but not sent SCBs out of the equation. 4636 * Also ensure that no new CCBs are queued to us while we 4637 * try to fix this problem. 4638 */ 4639 ahc->queue_blocked = 1; 4640 4641 /* 4642 * Go through all of our pending SCBs and remove 4643 * any scheduled timeouts for them. We will reschedule 4644 * them after we've successfully fixed this problem. 4645 */ 4646 scbp = ahc->pending_ccbs.lh_first; 4647 while (scbp != NULL) { 4648 callout_stop(&scbp->xs->xs_callout); 4649 scbp = scbp->plinks.le_next; 4650 } 4651 } 4652 } 4653 4654 static void 4655 ahc_timeout(void *arg) 4656 { 4657 struct scb *scb; 4658 struct ahc_softc *ahc; 4659 int s, found; 4660 u_int last_phase; 4661 int target; 4662 int lun; 4663 int i; 4664 char channel; 4665 4666 scb = (struct scb *)arg; 4667 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4668 4669 s = splbio(); 4670 4671 /* 4672 * Ensure that the card doesn't do anything 4673 * behind our back. Also make sure that we 4674 * didn't "just" miss an interrupt that would 4675 * affect this timeout. 4676 */ 4677 do { 4678 ahc_intr(ahc); 4679 pause_sequencer(ahc); 4680 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4681 4682 if ((scb->flags & SCB_ACTIVE) == 0) { 4683 /* Previous timeout took care of me already */ 4684 printf("Timedout SCB handled by another timeout\n"); 4685 unpause_sequencer(ahc); 4686 splx(s); 4687 return; 4688 } 4689 4690 target = SCB_TARGET(scb); 4691 channel = SCB_CHANNEL(scb); 4692 lun = SCB_LUN(scb); 4693 4694 scsi_print_addr(scb->xs->sc_link); 4695 printf("SCB %x - timed out ", scb->hscb->tag); 4696 /* 4697 * Take a snapshot of the bus state and print out 4698 * some information so we can track down driver bugs. 4699 */ 4700 last_phase = ahc_inb(ahc, LASTPHASE); 4701 4702 for (i = 0; i < num_phases; i++) { 4703 if (last_phase == phase_table[i].phase) 4704 break; 4705 } 4706 printf("%s", phase_table[i].phasemsg); 4707 4708 printf(", SEQADDR == 0x%x\n", 4709 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4710 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4711 4712 #ifdef AHC_DEBUG 4713 ahc_print_scb(scb); 4714 #endif 4715 4716 #if 0 4717 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4718 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4719 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4720 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4721 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4722 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4723 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4724 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4725 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4726 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4727 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4728 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4729 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4730 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4731 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4732 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4733 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4734 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4735 if (scb->sg_count > 0) { 4736 for (i = 0; i < scb->sg_count; i++) { 4737 printf("sg[%d] - Addr 0x%x : Length %d\n", 4738 i, 4739 le32toh(scb->sg_list[i].addr), 4740 le32toh(scb->sg_list[i].len)); 4741 } 4742 } 4743 #endif 4744 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4745 /* 4746 * Been down this road before. 4747 * Do a full bus reset. 4748 */ 4749 bus_reset: 4750 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4751 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4752 printf("%s: Issued Channel %c Bus Reset. " 4753 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4754 } else { 4755 /* 4756 * If we are a target, transition to bus free and report 4757 * the timeout. 4758 * 4759 * The target/initiator that is holding up the bus may not 4760 * be the same as the one that triggered this timeout 4761 * (different commands have different timeout lengths). 4762 * If the bus is idle and we are actiing as the initiator 4763 * for this request, queue a BDR message to the timed out 4764 * target. Otherwise, if the timed out transaction is 4765 * active: 4766 * Initiator transaction: 4767 * Stuff the message buffer with a BDR message and assert 4768 * ATN in the hopes that the target will let go of the bus 4769 * and go to the mesgout phase. If this fails, we'll 4770 * get another timeout 2 seconds later which will attempt 4771 * a bus reset. 4772 * 4773 * Target transaction: 4774 * Transition to BUS FREE and report the error. 4775 * It's good to be the target! 4776 */ 4777 u_int active_scb_index; 4778 4779 active_scb_index = ahc_inb(ahc, SCB_TAG); 4780 4781 if (last_phase != P_BUSFREE 4782 && (active_scb_index < ahc->scb_data->numscbs)) { 4783 struct scb *active_scb; 4784 4785 /* 4786 * If the active SCB is not from our device, 4787 * assume that another device is hogging the bus 4788 * and wait for it's timeout to expire before 4789 * taking additional action. 4790 */ 4791 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4792 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4793 u_int newtimeout; 4794 4795 scsi_print_addr(scb->xs->sc_link); 4796 printf("Other SCB Timeout%s", 4797 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4798 ? " again\n" : "\n"); 4799 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4800 newtimeout = MAX(active_scb->xs->timeout, 4801 scb->xs->timeout); 4802 callout_reset(&scb->xs->xs_callout, 4803 (newtimeout * hz) / 1000, 4804 ahc_timeout, scb); 4805 splx(s); 4806 return; 4807 } 4808 4809 /* It's us */ 4810 if ((scb->hscb->control & TARGET_SCB) != 0) { 4811 4812 /* 4813 * Send back any queued up transactions 4814 * and properly record the error condition. 4815 */ 4816 ahc_freeze_devq(ahc, scb->xs->sc_link); 4817 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4818 ahc_freeze_ccb(scb); 4819 ahc_done(ahc, scb); 4820 4821 /* Will clear us from the bus */ 4822 restart_sequencer(ahc); 4823 return; 4824 } 4825 4826 ahc_set_recoveryscb(ahc, active_scb); 4827 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4828 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4829 scsi_print_addr(active_scb->xs->sc_link); 4830 printf("BDR message in message buffer\n"); 4831 active_scb->flags |= SCB_DEVICE_RESET; 4832 callout_reset(&active_scb->xs->xs_callout, 4833 2 * hz, ahc_timeout, active_scb); 4834 unpause_sequencer(ahc); 4835 } else { 4836 int disconnected; 4837 4838 /* XXX Shouldn't panic. Just punt instead */ 4839 if ((scb->hscb->control & TARGET_SCB) != 0) 4840 panic("Timed-out target SCB but bus idle"); 4841 4842 if (last_phase != P_BUSFREE 4843 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4844 /* XXX What happened to the SCB? */ 4845 /* Hung target selection. Goto busfree */ 4846 printf("%s: Hung target selection\n", 4847 ahc_name(ahc)); 4848 restart_sequencer(ahc); 4849 return; 4850 } 4851 4852 if (ahc_search_qinfifo(ahc, target, channel, lun, 4853 scb->hscb->tag, ROLE_INITIATOR, 4854 /*status*/0, SEARCH_COUNT) > 0) { 4855 disconnected = FALSE; 4856 } else { 4857 disconnected = TRUE; 4858 } 4859 4860 if (disconnected) { 4861 u_int active_scb; 4862 4863 ahc_set_recoveryscb(ahc, scb); 4864 /* 4865 * Simply set the MK_MESSAGE control bit. 4866 */ 4867 scb->hscb->control |= MK_MESSAGE; 4868 scb->flags |= SCB_QUEUED_MSG 4869 | SCB_DEVICE_RESET; 4870 4871 /* 4872 * Mark the cached copy of this SCB in the 4873 * disconnected list too, so that a reconnect 4874 * at this point causes a BDR or abort. 4875 */ 4876 active_scb = ahc_inb(ahc, SCBPTR); 4877 if (ahc_search_disc_list(ahc, target, 4878 channel, lun, 4879 scb->hscb->tag, 4880 /*stop_on_first*/TRUE, 4881 /*remove*/FALSE, 4882 /*save_state*/FALSE)) { 4883 u_int scb_control; 4884 4885 scb_control = ahc_inb(ahc, SCB_CONTROL); 4886 scb_control |= MK_MESSAGE; 4887 ahc_outb(ahc, SCB_CONTROL, scb_control); 4888 } 4889 ahc_outb(ahc, SCBPTR, active_scb); 4890 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4891 /*unbusy*/TRUE); 4892 4893 /* 4894 * Actually re-queue this SCB in case we can 4895 * select the device before it reconnects. 4896 * Clear out any entries in the QINFIFO first 4897 * so we are the next SCB for this target 4898 * to run. 4899 */ 4900 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4901 channel, SCB_LUN(scb), 4902 SCB_LIST_NULL, 4903 ROLE_INITIATOR, 4904 SCB_REQUEUE, 4905 SEARCH_COMPLETE); 4906 scsi_print_addr(scb->xs->sc_link); 4907 printf("Queuing a BDR SCB\n"); 4908 ahc->qinfifo[ahc->qinfifonext++] = 4909 scb->hscb->tag; 4910 4911 bus_dmamap_sync(ahc->parent_dmat, 4912 ahc->shared_data_dmamap, 4913 QINFIFO_OFFSET * 256, 256, 4914 BUS_DMASYNC_PREWRITE); 4915 4916 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4917 ahc_outb(ahc, HNSCB_QOFF, 4918 ahc->qinfifonext); 4919 } else { 4920 ahc_outb(ahc, KERNEL_QINPOS, 4921 ahc->qinfifonext); 4922 } 4923 callout_reset(&scb->xs->xs_callout, 2 * hz, 4924 ahc_timeout, scb); 4925 unpause_sequencer(ahc); 4926 } else { 4927 /* Go "immediatly" to the bus reset */ 4928 /* This shouldn't happen */ 4929 ahc_set_recoveryscb(ahc, scb); 4930 scsi_print_addr(scb->xs->sc_link); 4931 printf("SCB %x: Immediate reset. " 4932 "Flags = 0x%x\n", scb->hscb->tag, 4933 scb->flags); 4934 goto bus_reset; 4935 } 4936 } 4937 } 4938 splx(s); 4939 } 4940 4941 static int 4942 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4943 int lun, u_int tag, role_t role, scb_flag status, 4944 ahc_search_action action) 4945 { 4946 struct scb *scbp; 4947 u_int8_t qinpos; 4948 u_int8_t qintail; 4949 int found; 4950 4951 qinpos = ahc_inb(ahc, QINPOS); 4952 qintail = ahc->qinfifonext; 4953 found = 0; 4954 4955 /* 4956 * Start with an empty queue. Entries that are not chosen 4957 * for removal will be re-added to the queue as we go. 4958 */ 4959 ahc->qinfifonext = qinpos; 4960 4961 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4962 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4963 4964 while (qinpos != qintail) { 4965 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4966 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4967 /* 4968 * We found an scb that needs to be removed. 4969 */ 4970 switch (action) { 4971 case SEARCH_COMPLETE: 4972 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4973 scbp->flags |= status; 4974 scbp->xs->error = XS_NOERROR; 4975 } 4976 ahc_freeze_ccb(scbp); 4977 ahc_done(ahc, scbp); 4978 break; 4979 case SEARCH_COUNT: 4980 ahc->qinfifo[ahc->qinfifonext++] = 4981 scbp->hscb->tag; 4982 break; 4983 case SEARCH_REMOVE: 4984 break; 4985 } 4986 found++; 4987 } else { 4988 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4989 } 4990 qinpos++; 4991 } 4992 4993 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4994 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4995 4996 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4997 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4998 } else { 4999 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5000 } 5001 5002 return (found); 5003 } 5004 5005 /* 5006 * Abort all SCBs that match the given description (target/channel/lun/tag), 5007 * setting their status to the passed in status if the status has not already 5008 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5009 * is paused before it is called. 5010 */ 5011 static int 5012 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5013 int lun, u_int tag, role_t role, int status) 5014 { 5015 struct scb *scbp; 5016 u_int active_scb; 5017 int i; 5018 int found; 5019 5020 /* restore this when we're done */ 5021 active_scb = ahc_inb(ahc, SCBPTR); 5022 5023 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5024 role, SCB_REQUEUE, SEARCH_COMPLETE); 5025 5026 /* 5027 * Search waiting for selection list. 5028 */ 5029 { 5030 u_int8_t next, prev; 5031 5032 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5033 prev = SCB_LIST_NULL; 5034 5035 while (next != SCB_LIST_NULL) { 5036 u_int8_t scb_index; 5037 5038 ahc_outb(ahc, SCBPTR, next); 5039 scb_index = ahc_inb(ahc, SCB_TAG); 5040 if (scb_index >= ahc->scb_data->numscbs) { 5041 panic("Waiting List inconsistency. " 5042 "SCB index == %d, yet numscbs == %d.", 5043 scb_index, ahc->scb_data->numscbs); 5044 } 5045 scbp = &ahc->scb_data->scbarray[scb_index]; 5046 if (ahc_match_scb(scbp, target, channel, 5047 lun, SCB_LIST_NULL, role)) { 5048 5049 next = ahc_abort_wscb(ahc, next, prev); 5050 } else { 5051 5052 prev = next; 5053 next = ahc_inb(ahc, SCB_NEXT); 5054 } 5055 } 5056 } 5057 /* 5058 * Go through the disconnected list and remove any entries we 5059 * have queued for completion, 0'ing their control byte too. 5060 * We save the active SCB and restore it ourselves, so there 5061 * is no reason for this search to restore it too. 5062 */ 5063 ahc_search_disc_list(ahc, target, channel, lun, tag, 5064 /*stop_on_first*/FALSE, /*remove*/TRUE, 5065 /*save_state*/FALSE); 5066 5067 /* 5068 * Go through the hardware SCB array looking for commands that 5069 * were active but not on any list. 5070 */ 5071 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5072 u_int scbid; 5073 5074 ahc_outb(ahc, SCBPTR, i); 5075 scbid = ahc_inb(ahc, SCB_TAG); 5076 scbp = &ahc->scb_data->scbarray[scbid]; 5077 if (scbid < ahc->scb_data->numscbs 5078 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5079 ahc_add_curscb_to_free_list(ahc); 5080 } 5081 5082 /* 5083 * Go through the pending CCB list and look for 5084 * commands for this target that are still active. 5085 * These are other tagged commands that were 5086 * disconnected when the reset occured. 5087 */ 5088 { 5089 struct scb *scb; 5090 5091 scb = ahc->pending_ccbs.lh_first; 5092 while (scb != NULL) { 5093 scbp = scb; 5094 scb = scb->plinks.le_next; 5095 if (ahc_match_scb(scbp, target, channel, 5096 lun, tag, role)) { 5097 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5098 ahcsetccbstatus(scbp->xs, status); 5099 ahc_freeze_ccb(scbp); 5100 ahc_done(ahc, scbp); 5101 found++; 5102 } 5103 } 5104 } 5105 ahc_outb(ahc, SCBPTR, active_scb); 5106 return found; 5107 } 5108 5109 static int 5110 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5111 int lun, u_int tag, int stop_on_first, int remove, 5112 int save_state) 5113 { 5114 struct scb *scbp; 5115 u_int next; 5116 u_int prev; 5117 u_int count; 5118 u_int active_scb; 5119 5120 count = 0; 5121 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5122 prev = SCB_LIST_NULL; 5123 5124 if (save_state) { 5125 /* restore this when we're done */ 5126 active_scb = ahc_inb(ahc, SCBPTR); 5127 } else 5128 /* Silence compiler */ 5129 active_scb = SCB_LIST_NULL; 5130 5131 while (next != SCB_LIST_NULL) { 5132 u_int scb_index; 5133 5134 ahc_outb(ahc, SCBPTR, next); 5135 scb_index = ahc_inb(ahc, SCB_TAG); 5136 if (scb_index >= ahc->scb_data->numscbs) { 5137 panic("Disconnected List inconsistency. " 5138 "SCB index == %d, yet numscbs == %d.", 5139 scb_index, ahc->scb_data->numscbs); 5140 } 5141 scbp = &ahc->scb_data->scbarray[scb_index]; 5142 if (ahc_match_scb(scbp, target, channel, lun, 5143 tag, ROLE_INITIATOR)) { 5144 count++; 5145 if (remove) { 5146 next = 5147 ahc_rem_scb_from_disc_list(ahc, prev, next); 5148 } else { 5149 prev = next; 5150 next = ahc_inb(ahc, SCB_NEXT); 5151 } 5152 if (stop_on_first) 5153 break; 5154 } else { 5155 prev = next; 5156 next = ahc_inb(ahc, SCB_NEXT); 5157 } 5158 } 5159 if (save_state) 5160 ahc_outb(ahc, SCBPTR, active_scb); 5161 return (count); 5162 } 5163 5164 static u_int 5165 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5166 { 5167 u_int next; 5168 5169 ahc_outb(ahc, SCBPTR, scbptr); 5170 next = ahc_inb(ahc, SCB_NEXT); 5171 5172 ahc_outb(ahc, SCB_CONTROL, 0); 5173 5174 ahc_add_curscb_to_free_list(ahc); 5175 5176 if (prev != SCB_LIST_NULL) { 5177 ahc_outb(ahc, SCBPTR, prev); 5178 ahc_outb(ahc, SCB_NEXT, next); 5179 } else 5180 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5181 5182 return (next); 5183 } 5184 5185 static void 5186 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5187 { 5188 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5189 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5190 5191 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5192 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5193 } 5194 5195 /* 5196 * Manipulate the waiting for selection list and return the 5197 * scb that follows the one that we remove. 5198 */ 5199 static u_int 5200 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5201 { 5202 u_int curscb, next; 5203 5204 /* 5205 * Select the SCB we want to abort and 5206 * pull the next pointer out of it. 5207 */ 5208 curscb = ahc_inb(ahc, SCBPTR); 5209 ahc_outb(ahc, SCBPTR, scbpos); 5210 next = ahc_inb(ahc, SCB_NEXT); 5211 5212 /* Clear the necessary fields */ 5213 ahc_outb(ahc, SCB_CONTROL, 0); 5214 5215 ahc_add_curscb_to_free_list(ahc); 5216 5217 /* update the waiting list */ 5218 if (prev == SCB_LIST_NULL) { 5219 /* First in the list */ 5220 ahc_outb(ahc, WAITING_SCBH, next); 5221 5222 /* 5223 * Ensure we aren't attempting to perform 5224 * selection for this entry. 5225 */ 5226 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5227 } else { 5228 /* 5229 * Select the scb that pointed to us 5230 * and update its next pointer. 5231 */ 5232 ahc_outb(ahc, SCBPTR, prev); 5233 ahc_outb(ahc, SCB_NEXT, next); 5234 } 5235 5236 /* 5237 * Point us back at the original scb position. 5238 */ 5239 ahc_outb(ahc, SCBPTR, curscb); 5240 return next; 5241 } 5242 5243 static void 5244 ahc_clear_intstat(struct ahc_softc *ahc) 5245 { 5246 /* Clear any interrupt conditions this may have caused */ 5247 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5248 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5249 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5250 CLRREQINIT); 5251 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5252 } 5253 5254 static void 5255 ahc_reset_current_bus(struct ahc_softc *ahc) 5256 { 5257 u_int8_t scsiseq; 5258 5259 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5260 scsiseq = ahc_inb(ahc, SCSISEQ); 5261 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5262 DELAY(AHC_BUSRESET_DELAY); 5263 /* Turn off the bus reset */ 5264 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5265 5266 ahc_clear_intstat(ahc); 5267 5268 /* Re-enable reset interrupts */ 5269 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5270 } 5271 5272 static int 5273 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5274 { 5275 u_int initiator, target, max_scsiid; 5276 u_int sblkctl; 5277 u_int our_id; 5278 int found; 5279 int restart_needed; 5280 char cur_channel; 5281 5282 ahc->pending_device = NULL; 5283 5284 pause_sequencer(ahc); 5285 5286 /* 5287 * Run our command complete fifos to ensure that we perform 5288 * completion processing on any commands that 'completed' 5289 * before the reset occurred. 5290 */ 5291 ahc_run_qoutfifo(ahc); 5292 5293 /* 5294 * Reset the bus if we are initiating this reset 5295 */ 5296 sblkctl = ahc_inb(ahc, SBLKCTL); 5297 cur_channel = 'A'; 5298 if ((ahc->features & AHC_TWIN) != 0 5299 && ((sblkctl & SELBUSB) != 0)) 5300 cur_channel = 'B'; 5301 if (cur_channel != channel) { 5302 /* Case 1: Command for another bus is active 5303 * Stealthily reset the other bus without 5304 * upsetting the current bus. 5305 */ 5306 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5307 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5308 ahc_outb(ahc, SCSISEQ, 5309 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5310 if (initiate_reset) 5311 ahc_reset_current_bus(ahc); 5312 ahc_clear_intstat(ahc); 5313 ahc_outb(ahc, SBLKCTL, sblkctl); 5314 restart_needed = FALSE; 5315 } else { 5316 /* Case 2: A command from this bus is active or we're idle */ 5317 ahc_clear_msg_state(ahc); 5318 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5319 ahc_outb(ahc, SCSISEQ, 5320 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5321 if (initiate_reset) 5322 ahc_reset_current_bus(ahc); 5323 ahc_clear_intstat(ahc); 5324 5325 /* 5326 * Since we are going to restart the sequencer, avoid 5327 * a race in the sequencer that could cause corruption 5328 * of our Q pointers by starting over from index 0. 5329 */ 5330 ahc->qoutfifonext = 0; 5331 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5332 ahc_outb(ahc, SDSCB_QOFF, 0); 5333 else 5334 ahc_outb(ahc, QOUTPOS, 0); 5335 restart_needed = TRUE; 5336 } 5337 5338 /* 5339 * Clean up all the state information for the 5340 * pending transactions on this bus. 5341 */ 5342 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5343 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5344 ROLE_UNKNOWN, XS_RESET); 5345 if (channel == 'B') { 5346 our_id = ahc->our_id_b; 5347 } else { 5348 our_id = ahc->our_id; 5349 } 5350 5351 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5352 5353 /* 5354 * Revert to async/narrow transfers until we renegotiate. 5355 */ 5356 for (target = 0; target <= max_scsiid; target++) { 5357 5358 if (ahc->enabled_targets[target] == NULL) 5359 continue; 5360 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5361 struct ahc_devinfo devinfo; 5362 5363 ahc_compile_devinfo(&devinfo, target, initiator, 5364 AHC_LUN_WILDCARD, 5365 channel, ROLE_UNKNOWN); 5366 ahc_set_width(ahc, &devinfo, 5367 MSG_EXT_WDTR_BUS_8_BIT, 5368 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5369 ahc_set_syncrate(ahc, &devinfo, 5370 /*syncrate*/NULL, /*period*/0, 5371 /*offset*/0, AHC_TRANS_CUR, 5372 /*paused*/TRUE, FALSE); 5373 } 5374 } 5375 5376 if (restart_needed) 5377 restart_sequencer(ahc); 5378 else 5379 unpause_sequencer(ahc); 5380 return found; 5381 } 5382 5383 static int 5384 ahc_match_scb(struct scb *scb, int target, char channel, 5385 int lun, u_int tag, role_t role) 5386 { 5387 int targ = SCB_TARGET(scb); 5388 char chan = SCB_CHANNEL(scb); 5389 int slun = SCB_LUN(scb); 5390 int match; 5391 5392 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5393 if (match != 0) 5394 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5395 if (match != 0) 5396 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5397 5398 return match; 5399 } 5400 5401 static void 5402 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5403 { 5404 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5405 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5406 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5407 ahc->msgout_buf[ahc->msgout_index++] = period; 5408 ahc->msgout_buf[ahc->msgout_index++] = offset; 5409 ahc->msgout_len += 5; 5410 } 5411 5412 static void 5413 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5414 { 5415 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5416 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5417 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5418 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5419 ahc->msgout_len += 4; 5420 } 5421 5422 static void 5423 ahc_calc_residual(struct scb *scb) 5424 { 5425 struct hardware_scb *hscb; 5426 5427 hscb = scb->hscb; 5428 5429 /* 5430 * If the disconnected flag is still set, this is bogus 5431 * residual information left over from a sequencer 5432 * pagin/pageout, so ignore this case. 5433 */ 5434 if ((scb->hscb->control & DISCONNECTED) == 0) { 5435 u_int32_t resid; 5436 int resid_sgs; 5437 int sg; 5438 5439 /* 5440 * Remainder of the SG where the transfer 5441 * stopped. 5442 */ 5443 resid = (hscb->residual_data_count[2] << 16) 5444 | (hscb->residual_data_count[1] <<8) 5445 | (hscb->residual_data_count[0]); 5446 5447 /* 5448 * Add up the contents of all residual 5449 * SG segments that are after the SG where 5450 * the transfer stopped. 5451 */ 5452 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5453 sg = scb->sg_count - resid_sgs; 5454 while (resid_sgs > 0) { 5455 5456 resid += le32toh(scb->sg_list[sg].len); 5457 sg++; 5458 resid_sgs--; 5459 } 5460 scb->xs->resid = resid; 5461 } 5462 5463 /* 5464 * Clean out the residual information in this SCB for its 5465 * next consumer. 5466 */ 5467 hscb->residual_SG_count = 0; 5468 5469 #ifdef AHC_DEBUG 5470 if (ahc_debug & AHC_SHOWMISC) { 5471 scsi_print_addr(scb->xs->sc_link); 5472 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5473 } 5474 #endif 5475 } 5476 5477 static void 5478 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5479 { 5480 struct scb *scb; 5481 int pending_ccb_count; 5482 int i; 5483 u_int saved_scbptr; 5484 5485 /* 5486 * Traverse the pending SCB list and ensure that all of the 5487 * SCBs there have the proper settings. 5488 */ 5489 scb = LIST_FIRST(&ahc->pending_ccbs); 5490 pending_ccb_count = 0; 5491 while (scb != NULL) { 5492 struct ahc_devinfo devinfo; 5493 struct scsipi_xfer *xs; 5494 struct scb *pending_scb; 5495 struct hardware_scb *pending_hscb; 5496 struct ahc_initiator_tinfo *tinfo; 5497 struct tmode_tstate *tstate; 5498 u_int our_id, remote_id; 5499 5500 xs = scb->xs; 5501 pending_scb = scb; 5502 pending_hscb = pending_scb->hscb; 5503 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5504 ? ahc->our_id_b : ahc->our_id; 5505 remote_id = xs->sc_link->scsipi_scsi.target; 5506 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5507 SCB_LUN(pending_scb), 5508 SCB_CHANNEL(pending_scb), 5509 ROLE_UNKNOWN); 5510 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5511 our_id, remote_id, &tstate); 5512 pending_hscb->control &= ~ULTRAENB; 5513 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5514 pending_hscb->control |= ULTRAENB; 5515 pending_hscb->scsirate = tinfo->scsirate; 5516 pending_hscb->scsioffset = tinfo->current.offset; 5517 pending_ccb_count++; 5518 scb = LIST_NEXT(scb, plinks); 5519 } 5520 5521 if (pending_ccb_count == 0) 5522 return; 5523 5524 saved_scbptr = ahc_inb(ahc, SCBPTR); 5525 /* Ensure that the hscbs down on the card match the new information */ 5526 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5527 u_int scb_tag; 5528 5529 ahc_outb(ahc, SCBPTR, i); 5530 scb_tag = ahc_inb(ahc, SCB_TAG); 5531 if (scb_tag != SCB_LIST_NULL) { 5532 struct ahc_devinfo devinfo; 5533 struct scb *pending_scb; 5534 struct scsipi_xfer *xs; 5535 struct hardware_scb *pending_hscb; 5536 struct ahc_initiator_tinfo *tinfo; 5537 struct tmode_tstate *tstate; 5538 u_int our_id, remote_id; 5539 u_int control; 5540 5541 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5542 if (pending_scb->flags == SCB_FREE) 5543 continue; 5544 pending_hscb = pending_scb->hscb; 5545 xs = pending_scb->xs; 5546 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5547 ? ahc->our_id_b : ahc->our_id; 5548 remote_id = xs->sc_link->scsipi_scsi.target; 5549 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5550 SCB_LUN(pending_scb), 5551 SCB_CHANNEL(pending_scb), 5552 ROLE_UNKNOWN); 5553 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5554 our_id, remote_id, &tstate); 5555 control = ahc_inb(ahc, SCB_CONTROL); 5556 control &= ~ULTRAENB; 5557 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5558 control |= ULTRAENB; 5559 ahc_outb(ahc, SCB_CONTROL, control); 5560 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5561 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5562 } 5563 } 5564 ahc_outb(ahc, SCBPTR, saved_scbptr); 5565 } 5566 5567 #if UNUSED 5568 static void 5569 ahc_dump_targcmd(struct target_cmd *cmd) 5570 { 5571 u_int8_t *byte; 5572 u_int8_t *last_byte; 5573 int i; 5574 5575 byte = &cmd->initiator_channel; 5576 /* Debugging info for received commands */ 5577 last_byte = &cmd[1].initiator_channel; 5578 5579 i = 0; 5580 while (byte < last_byte) { 5581 if (i == 0) 5582 printf("\t"); 5583 printf("%#x", *byte++); 5584 i++; 5585 if (i == 8) { 5586 printf("\n"); 5587 i = 0; 5588 } else { 5589 printf(", "); 5590 } 5591 } 5592 } 5593 #endif 5594 5595 static void 5596 ahc_shutdown(void *arg) 5597 { 5598 struct ahc_softc *ahc; 5599 int i; 5600 u_int sxfrctl1_a, sxfrctl1_b; 5601 5602 ahc = (struct ahc_softc *)arg; 5603 5604 pause_sequencer(ahc); 5605 5606 /* 5607 * Preserve the value of the SXFRCTL1 register for all channels. 5608 * It contains settings that affect termination and we don't want 5609 * to disturb the integrity of the bus during shutdown in case 5610 * we are in a multi-initiator setup. 5611 */ 5612 sxfrctl1_b = 0; 5613 if ((ahc->features & AHC_TWIN) != 0) { 5614 u_int sblkctl; 5615 5616 sblkctl = ahc_inb(ahc, SBLKCTL); 5617 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5618 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5619 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5620 } 5621 5622 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5623 5624 /* This will reset most registers to 0, but not all */ 5625 ahc_reset(ahc); 5626 5627 if ((ahc->features & AHC_TWIN) != 0) { 5628 u_int sblkctl; 5629 5630 sblkctl = ahc_inb(ahc, SBLKCTL); 5631 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5632 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5633 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5634 } 5635 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5636 5637 ahc_outb(ahc, SCSISEQ, 0); 5638 ahc_outb(ahc, SXFRCTL0, 0); 5639 ahc_outb(ahc, DSPCISTATUS, 0); 5640 5641 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5642 ahc_outb(ahc, i, 0); 5643 } 5644 5645 #if defined(AHC_DEBUG) && 0 5646 static void 5647 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5648 { 5649 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5650 5651 printf("\tcurrent:\n"); 5652 printf("\t\twidth %u period %u offset %u flags %x\n", 5653 tinfo->current.width, tinfo->current.period, 5654 tinfo->current.offset, tinfo->current.ppr_flags); 5655 5656 printf("\tgoal:\n"); 5657 printf("\t\twidth %u period %u offset %u flags %x\n", 5658 tinfo->goal.width, tinfo->goal.period, 5659 tinfo->goal.offset, tinfo->goal.ppr_flags); 5660 5661 printf("\tuser:\n"); 5662 printf("\t\twidth %u period %u offset %u flags %x\n", 5663 tinfo->user.width, tinfo->user.period, 5664 tinfo->user.offset, tinfo->user.ppr_flags); 5665 } 5666 #endif 5667 5668 static void 5669 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5670 { 5671 struct scsipi_inquiry_data *inq; 5672 struct ahc_devinfo devinfo; 5673 struct tmode_tstate *tstate; 5674 int target_id, our_id; 5675 char channel; 5676 5677 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5678 return; 5679 5680 if (xs->sc_link->quirks & SDEV_NOTAG) 5681 return; 5682 5683 target_id = xs->sc_link->scsipi_scsi.target; 5684 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5685 channel = SIM_CHANNEL(ahc, xs->sc_link); 5686 5687 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5688 ahc_compile_devinfo(&devinfo, our_id, target_id, 5689 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5690 5691 if (tstate->tagdisable & devinfo.target_mask) 5692 return; 5693 5694 /* 5695 * Sneak a look at the results of the SCSI Inquiry 5696 * command and see if we can do Tagged queing. This 5697 * should really be done by the higher level drivers. 5698 */ 5699 inq = (struct scsipi_inquiry_data *)xs->data; 5700 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5701 printf("%s: target %d using tagged queuing\n", 5702 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5703 5704 ahc_set_tags(ahc, &devinfo, TRUE); 5705 5706 if (ahc->scb_data->maxhscbs >= 16 || 5707 (ahc->flags & AHC_PAGESCBS)) { 5708 /* Default to 16 tags */ 5709 xs->sc_link->openings = 16; 5710 } else { 5711 /* 5712 * Default to 4 tags on whimpy 5713 * cards that don't have much SCB 5714 * space and can't page. This prevents 5715 * a single device from hogging all 5716 * slots. We should really have a better 5717 * way of providing fairness. 5718 */ 5719 xs->sc_link->openings = 4; 5720 } 5721 } 5722 } 5723 5724 static int 5725 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5726 int nocmdcheck) 5727 { 5728 char channel; 5729 u_int our_id, target; 5730 struct tmode_tstate *tstate; 5731 struct ahc_devinfo devinfo; 5732 5733 if (xs->sc_link->quirks & SDEV_NOTAG) 5734 return 0; 5735 5736 /* 5737 * XXX never do these commands with tags. Should really be 5738 * in a higher layer. 5739 */ 5740 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5741 xs->cmd->opcode == TEST_UNIT_READY || 5742 xs->cmd->opcode == REQUEST_SENSE)) 5743 return 0; 5744 5745 channel = SIM_CHANNEL(ahc, xs->sc_link); 5746 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5747 target = xs->sc_link->scsipi_scsi.target; 5748 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5749 5750 ahc_compile_devinfo(&devinfo, our_id, target, 5751 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5752 5753 return (tstate->tagenable & devinfo.target_mask); 5754 } 5755
Indexes created Wed Oct 01 07:09:59 GMT 2025