aic7xxx.c revision 1.56
1 /* $NetBSD: aic7xxx.c,v 1.56 2000/06/26 14:38:52 mrg Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 #include <sys/scsiio.h> 99 100 #include <machine/bus.h> 101 #include <machine/intr.h> 102 103 #include <dev/scsipi/scsi_all.h> 104 #include <dev/scsipi/scsipi_all.h> 105 #include <dev/scsipi/scsi_message.h> 106 #include <dev/scsipi/scsipi_debug.h> 107 #include <dev/scsipi/scsiconf.h> 108 109 #include <vm/vm.h> 110 111 #include <dev/ic/aic7xxxvar.h> 112 #include <dev/microcode/aic7xxx/sequencer.h> 113 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 115 116 #define XS_STS_DEBUG 0x00000002 117 118 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 119 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 120 #define ALL_CHANNELS '\0' 121 #define ALL_TARGETS_MASK 0xFFFF 122 #define INITIATOR_WILDCARD (~0) 123 124 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 125 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 126 #define SIM_CHANNEL(ahc, sc_link) \ 127 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 128 #define SIM_SCSI_ID(ahc, sc_link) \ 129 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 130 #define SCB_IS_SCSIBUS_B(scb) \ 131 (((scb)->hscb->tcl & SELBUSB) != 0) 132 #define SCB_TARGET(scb) \ 133 (((scb)->hscb->tcl & TID) >> 4) 134 #define SCB_CHANNEL(scb) \ 135 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 136 #define SCB_LUN(scb) \ 137 ((scb)->hscb->tcl & LID) 138 #define SCB_TARGET_OFFSET(scb) \ 139 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 140 #define SCB_TARGET_MASK(scb) \ 141 (0x01 << (SCB_TARGET_OFFSET(scb))) 142 #define TCL_CHANNEL(ahc, tcl) \ 143 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 144 #define TCL_SCSI_ID(ahc, tcl) \ 145 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 146 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 147 #define TCL_LUN(tcl) ((tcl) & LID) 148 149 #define XS_TCL(ahc, xs) \ 150 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 151 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 152 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 153 154 char *ahc_chip_names[] = 155 { 156 "NONE", 157 "aic7770", 158 "aic7850", 159 "aic7855", 160 "aic7859", 161 "aic7860", 162 "aic7870", 163 "aic7880", 164 "aic7890/91", 165 "aic7892", 166 "aic7895", 167 "aic7896/97", 168 "aic7899" 169 }; 170 171 typedef enum { 172 ROLE_UNKNOWN, 173 ROLE_INITIATOR, 174 ROLE_TARGET 175 } role_t; 176 177 struct ahc_devinfo { 178 int our_scsiid; 179 int target_offset; 180 u_int16_t target_mask; 181 u_int8_t target; 182 u_int8_t lun; 183 char channel; 184 role_t role; /* 185 * Only guaranteed to be correct if not 186 * in the busfree state. 187 */ 188 }; 189 190 typedef enum { 191 SEARCH_COMPLETE, 192 SEARCH_COUNT, 193 SEARCH_REMOVE 194 } ahc_search_action; 195 196 #ifdef AHC_DEBUG 197 static int ahc_debug = AHC_DEBUG; 198 #endif 199 200 static int ahcinitscbdata(struct ahc_softc *); 201 static void ahcfiniscbdata(struct ahc_softc *); 202 203 #if UNUSED 204 static void ahc_dump_targcmd(struct target_cmd *); 205 #endif 206 static void ahc_shutdown(void *arg); 207 static int32_t ahc_action(struct scsipi_xfer *); 208 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 209 struct proc *); 210 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 211 static int ahc_poll(struct ahc_softc *, int); 212 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 213 struct scb *); 214 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 215 static void ahcallocscbs(struct ahc_softc *); 216 #if UNUSED 217 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 218 struct scb *); 219 #endif 220 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 221 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 222 char, role_t); 223 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 224 static void ahc_done(struct ahc_softc *, struct scb *); 225 static struct tmode_tstate * 226 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 227 #if UNUSED 228 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 229 #endif 230 static void ahc_handle_seqint(struct ahc_softc *, u_int); 231 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 232 static void ahc_build_transfer_msg(struct ahc_softc *, 233 struct ahc_devinfo *); 234 static void ahc_setup_initiator_msgout(struct ahc_softc *, 235 struct ahc_devinfo *, 236 struct scb *); 237 static void ahc_setup_target_msgin(struct ahc_softc *, 238 struct ahc_devinfo *); 239 static void ahc_clear_msg_state(struct ahc_softc *); 240 static void ahc_handle_message_phase(struct ahc_softc *, 241 struct scsipi_link *); 242 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 243 244 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 245 struct ahc_devinfo *); 246 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 247 struct ahc_devinfo *); 248 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 249 int, char *, int); 250 #ifdef AHC_DUMP_SEQ 251 static void ahc_dumpseq(struct ahc_softc *); 252 #endif 253 static void ahc_loadseq(struct ahc_softc *); 254 static int ahc_check_patch(struct ahc_softc *, struct patch **, 255 int, int *); 256 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 257 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 258 #if defined(AHC_DEBUG) 259 static void ahc_print_scb(struct scb *); 260 #endif 261 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 262 role_t, scb_flag, ahc_search_action); 263 static int ahc_reset_channel(struct ahc_softc *, char, int); 264 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 265 role_t, int); 266 static int ahc_search_disc_list(struct ahc_softc *, int, 267 char, int, u_int, int, int, int); 268 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 269 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 270 static void ahc_clear_intstat(struct ahc_softc *); 271 static void ahc_reset_current_bus(struct ahc_softc *); 272 static struct ahc_syncrate * 273 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 274 static struct ahc_syncrate * 275 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 276 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 277 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 278 u_int *, int); 279 static void ahc_update_target_msg_request(struct ahc_softc *, 280 struct ahc_devinfo *, 281 struct ahc_initiator_tinfo *, 282 int, int); 283 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 284 struct ahc_syncrate *, u_int, u_int, u_int, 285 int, int); 286 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 287 u_int, u_int, int, int); 288 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 289 int); 290 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 291 292 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 293 294 static void ahc_calc_residual(struct scb *); 295 296 static void ahc_update_pending_syncrates(struct ahc_softc *); 297 298 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 299 300 static void ahc_timeout (void *); 301 static __inline int sequencer_paused(struct ahc_softc *); 302 static __inline void pause_sequencer(struct ahc_softc *); 303 static __inline void unpause_sequencer(struct ahc_softc *); 304 static void restart_sequencer(struct ahc_softc *); 305 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 306 307 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 308 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 309 310 static __inline void ahc_freeze_ccb(struct scb *); 311 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 312 static void ahc_run_qoutfifo(struct ahc_softc *); 313 314 static __inline struct ahc_initiator_tinfo * 315 ahc_fetch_transinfo(struct ahc_softc *, 316 char, u_int, u_int, 317 struct tmode_tstate **); 318 static void ahcfreescb(struct ahc_softc *, struct scb *); 319 static __inline struct scb *ahcgetscb(struct ahc_softc *); 320 321 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 322 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 323 int *, const char *, const char *); 324 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 325 caddr_t, bus_dma_segment_t *, int); 326 static void ahcminphys(struct buf *); 327 328 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 329 static __inline void ahc_swap_hscb(struct hardware_scb *); 330 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 331 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 332 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 333 334 #if defined(AHC_DEBUG) && 0 335 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 336 #endif 337 338 static struct scsipi_device ahc_dev = 339 { 340 NULL, /* Use default error handler */ 341 NULL, /* have a queue, served by this */ 342 NULL, /* have no async handler */ 343 NULL, /* Use default 'done' routine */ 344 }; 345 346 /* 347 * Pick the first xs for a non-blocked target. 348 */ 349 static __inline struct scsipi_xfer * 350 ahc_first_xs(struct ahc_softc *ahc) 351 { 352 int target; 353 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 354 355 if (ahc->queue_blocked) 356 return NULL; 357 358 while (xs != NULL) { 359 target = xs->sc_link->scsipi_scsi.target; 360 if (ahc->devqueue_blocked[target] == 0 && 361 (ahc_istagged_device(ahc, xs, 0) || 362 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 363 SCB_LIST_NULL)) 364 break; 365 xs = TAILQ_NEXT(xs, adapter_q); 366 } 367 368 return xs; 369 } 370 371 static __inline void 372 ahc_swap_hscb(struct hardware_scb *hscb) 373 { 374 hscb->SG_pointer = htole32(hscb->SG_pointer); 375 hscb->data = htole32(hscb->data); 376 hscb->datalen = htole32(hscb->datalen); 377 /* 378 * No need to swap cmdpointer; it's either 0 or set to 379 * cmdstore_busaddr, which is already swapped. 380 */ 381 } 382 383 static __inline void 384 ahc_swap_sg(struct ahc_dma_seg *sg) 385 { 386 sg->addr = htole32(sg->addr); 387 sg->len = htole32(sg->len); 388 } 389 390 static void 391 ahcminphys(bp) 392 struct buf *bp; 393 { 394 /* 395 * Even though the card can transfer up to 16megs per command 396 * we are limited by the number of segments in the dma segment 397 * list that we can hold. The worst case is that all pages are 398 * discontinuous physically, hense the "page per segment" limit 399 * enforced here. 400 */ 401 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 402 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 403 } 404 minphys(bp); 405 } 406 407 408 static __inline u_int32_t 409 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 410 { 411 return (ahc->scb_data->hscb_busaddr 412 + (sizeof(struct hardware_scb) * index)); 413 } 414 415 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 416 417 static __inline int 418 sequencer_paused(struct ahc_softc *ahc) 419 { 420 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 421 } 422 423 static __inline void 424 pause_sequencer(struct ahc_softc *ahc) 425 { 426 ahc_outb(ahc, HCNTRL, ahc->pause); 427 428 /* 429 * Since the sequencer can disable pausing in a critical section, we 430 * must loop until it actually stops. 431 */ 432 while (sequencer_paused(ahc) == 0) 433 ; 434 } 435 436 static __inline void 437 unpause_sequencer(struct ahc_softc *ahc) 438 { 439 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 440 ahc_outb(ahc, HCNTRL, ahc->unpause); 441 } 442 443 /* 444 * Restart the sequencer program from address zero 445 */ 446 static void 447 restart_sequencer(struct ahc_softc *ahc) 448 { 449 u_int i; 450 451 pause_sequencer(ahc); 452 453 /* 454 * Everytime we restart the sequencer, there 455 * is the possiblitity that we have restarted 456 * within a three instruction window where an 457 * SCB has been marked free but has not made it 458 * onto the free list. Since SCSI events(bus reset, 459 * unexpected bus free) will always freeze the 460 * sequencer, we cannot close this window. To 461 * avoid losing an SCB, we reconsitute the free 462 * list every time we restart the sequencer. 463 */ 464 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 465 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 466 467 ahc_outb(ahc, SCBPTR, i); 468 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 469 ahc_add_curscb_to_free_list(ahc); 470 } 471 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 472 unpause_sequencer(ahc); 473 } 474 475 static __inline u_int 476 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 477 { 478 u_int scbid; 479 480 scbid = ahc->untagged_scbs[tcl]; 481 if (unbusy) { 482 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 483 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 484 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 485 } 486 487 return (scbid); 488 } 489 490 static __inline void 491 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 492 { 493 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 494 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 495 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 496 } 497 498 static __inline int 499 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 500 { 501 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 502 } 503 504 static __inline void 505 ahc_freeze_ccb(struct scb *scb) 506 { 507 struct scsipi_xfer *xs = scb->xs; 508 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 509 int target; 510 511 target = xs->sc_link->scsipi_scsi.target; 512 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 513 ahc->devqueue_blocked[target]++; 514 scb->flags |= SCB_FREEZE_QUEUE; 515 } 516 } 517 518 static __inline void 519 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 520 { 521 xs->error = status; 522 } 523 524 static __inline struct ahc_initiator_tinfo * 525 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 526 u_int remote_id, struct tmode_tstate **tstate) 527 { 528 /* 529 * Transfer data structures are stored from the perspective 530 * of the target role. Since the parameters for a connection 531 * in the initiator role to a given target are the same as 532 * when the roles are reversed, we pretend we are the target. 533 */ 534 if (channel == 'B') 535 our_id += 8; 536 *tstate = ahc->enabled_targets[our_id]; 537 return (&(*tstate)->transinfo[remote_id]); 538 } 539 540 static void 541 ahc_run_qoutfifo(struct ahc_softc *ahc) 542 { 543 struct scb *scb; 544 u_int scb_index; 545 546 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 547 256, BUS_DMASYNC_POSTREAD); 548 549 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 550 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 551 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 552 553 scb = &ahc->scb_data->scbarray[scb_index]; 554 if (scb_index >= ahc->scb_data->numscbs 555 || (scb->flags & SCB_ACTIVE) == 0) { 556 printf("%s: WARNING no command for scb %d " 557 "(cmdcmplt)\nQOUTPOS = %d\n", 558 ahc_name(ahc), scb_index, 559 ahc->qoutfifonext - 1); 560 continue; 561 } 562 563 /* 564 * Save off the residual 565 * if there is one. 566 */ 567 if (scb->hscb->residual_SG_count != 0) 568 ahc_calc_residual(scb); 569 else 570 scb->xs->resid = 0; 571 #ifdef AHC_DEBUG 572 if (ahc_debug & AHC_SHOWSCBS) { 573 scsi_print_addr(scb->xs->sc_link); 574 printf("run_qoutfifo: SCB %x complete\n", 575 scb->hscb->tag); 576 } 577 #endif 578 ahc_done(ahc, scb); 579 } 580 } 581 582 583 /* 584 * An scb (and hence an scb entry on the board) is put onto the 585 * free list. 586 */ 587 static void 588 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 589 { 590 struct hardware_scb *hscb; 591 int opri; 592 593 hscb = scb->hscb; 594 595 #ifdef AHC_DEBUG 596 if (ahc_debug & AHC_SHOWSCBALLOC) 597 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 598 #endif 599 600 opri = splbio(); 601 602 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 603 (scb->flags & SCB_RECOVERY_SCB) != 0) { 604 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 605 ahc->queue_blocked = 0; 606 } 607 608 /* Clean up for the next user */ 609 scb->flags = SCB_FREE; 610 hscb->control = 0; 611 hscb->status = 0; 612 613 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 614 615 splx(opri); 616 } 617 618 /* 619 * Get a free scb, either one already assigned to a hardware slot 620 * on the adapter or one that will require an SCB to be paged out before 621 * use. If there are none, see if we can allocate a new SCB. Otherwise 622 * either return an error or sleep. 623 */ 624 static __inline struct scb * 625 ahcgetscb(struct ahc_softc *ahc) 626 { 627 struct scb *scbp; 628 int opri;; 629 630 opri = splbio(); 631 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 632 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 633 } else { 634 ahcallocscbs(ahc); 635 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 636 if (scbp != NULL) 637 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 638 } 639 640 splx(opri); 641 642 #ifdef AHC_DEBUG 643 if (ahc_debug & AHC_SHOWSCBALLOC) { 644 if (scbp != NULL) 645 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 646 scbp->hscb->tag); 647 else 648 printf("%s: failed to allocate new SCB\n", 649 ahc_name(ahc)); 650 } 651 #endif 652 653 return (scbp); 654 } 655 656 static int 657 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 658 bus_dma_tag_t tag; 659 int size; 660 int flags; 661 bus_dmamap_t *mapp; 662 caddr_t *vaddr; 663 bus_addr_t *baddr; 664 bus_dma_segment_t *seg; 665 int *nseg; 666 const char *myname, *what; 667 { 668 int error, level = 0; 669 670 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 671 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 672 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 673 myname, what, error); 674 goto out; 675 } 676 level++; 677 678 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 679 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 680 printf("%s: failed to map DMA mem for %s, error = %d\n", 681 myname, what, error); 682 goto out; 683 } 684 level++; 685 686 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 687 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 688 printf("%s: failed to create DMA map for %s, error = %d\n", 689 myname, what, error); 690 goto out; 691 } 692 level++; 693 694 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 695 BUS_DMA_NOWAIT)) != 0) { 696 printf("%s: failed to load DMA map for %s, error = %d\n", 697 myname, what, error); 698 goto out; 699 } 700 701 *baddr = (*mapp)->dm_segs[0].ds_addr; 702 703 #ifdef AHC_DEBUG 704 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 705 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 706 *nseg, size); 707 #endif 708 709 return 0; 710 out: 711 switch (level) { 712 case 3: 713 bus_dmamap_destroy(tag, *mapp); 714 /* FALLTHROUGH */ 715 case 2: 716 bus_dmamem_unmap(tag, *vaddr, size); 717 /* FALLTHROUGH */ 718 case 1: 719 bus_dmamem_free(tag, seg, *nseg); 720 break; 721 default: 722 break; 723 } 724 725 return error; 726 } 727 728 static void 729 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 730 bus_dma_tag_t tag; 731 int size; 732 bus_dmamap_t map; 733 caddr_t vaddr; 734 bus_dma_segment_t *seg; 735 int nseg; 736 { 737 738 bus_dmamap_unload(tag, map); 739 bus_dmamap_destroy(tag, map); 740 bus_dmamem_unmap(tag, vaddr, size); 741 bus_dmamem_free(tag, seg, nseg); 742 } 743 744 char * 745 ahc_name(struct ahc_softc *ahc) 746 { 747 return (ahc->sc_dev.dv_xname); 748 } 749 750 #ifdef AHC_DEBUG 751 static void 752 ahc_print_scb(struct scb *scb) 753 { 754 struct hardware_scb *hscb = scb->hscb; 755 756 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 757 scb, 758 hscb->tag, 759 hscb->control, 760 hscb->tcl, 761 hscb->cmdlen, 762 (unsigned long)le32toh(hscb->cmdpointer)); 763 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 764 le32toh(hscb->datalen), 765 (unsigned long)(le32toh(hscb->data)), 766 hscb->SG_count, 767 (unsigned long)(le32toh(hscb->SG_pointer))); 768 printf(" sg_addr:%lx sg_len:%lu\n", 769 (unsigned long)(le32toh(scb->sg_list[0].addr)), 770 (unsigned long)(le32toh(scb->sg_list[0].len))); 771 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 772 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 773 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 774 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 775 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 776 } 777 #endif 778 779 static struct { 780 u_int8_t errno; 781 char *errmesg; 782 } hard_error[] = { 783 { ILLHADDR, "Illegal Host Access" }, 784 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 785 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 786 { SQPARERR, "Sequencer Parity Error" }, 787 { DPARERR, "Data-path Parity Error" }, 788 { MPARERR, "Scratch or SCB Memory Parity Error" }, 789 { PCIERRSTAT, "PCI Error detected" }, 790 { CIOPARERR, "CIOBUS Parity Error" }, 791 }; 792 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 793 794 static struct { 795 u_int8_t phase; 796 u_int8_t mesg_out; /* Message response to parity errors */ 797 char *phasemsg; 798 } phase_table[] = { 799 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 800 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 801 { P_COMMAND, MSG_NOOP, "in Command phase" }, 802 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 803 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 804 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 805 { P_BUSFREE, MSG_NOOP, "while idle" }, 806 { 0, MSG_NOOP, "in unknown phase" } 807 }; 808 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 809 810 /* 811 * Valid SCSIRATE values. (p. 3-17) 812 * Provides a mapping of tranfer periods in ns to the proper value to 813 * stick in the scsiscfr reg to use that transfer rate. 814 */ 815 #define AHC_SYNCRATE_DT 0 816 #define AHC_SYNCRATE_ULTRA2 1 817 #define AHC_SYNCRATE_ULTRA 3 818 #define AHC_SYNCRATE_FAST 6 819 static struct ahc_syncrate ahc_syncrates[] = { 820 /* ultra2 fast/ultra period rate */ 821 { 0x42, 0x000, 9, "80.0" }, 822 { 0x03, 0x000, 10, "40.0" }, 823 { 0x04, 0x000, 11, "33.0" }, 824 { 0x05, 0x100, 12, "20.0" }, 825 { 0x06, 0x110, 15, "16.0" }, 826 { 0x07, 0x120, 18, "13.4" }, 827 { 0x08, 0x000, 25, "10.0" }, 828 { 0x19, 0x010, 31, "8.0" }, 829 { 0x1a, 0x020, 37, "6.67" }, 830 { 0x1b, 0x030, 43, "5.7" }, 831 { 0x1c, 0x040, 50, "5.0" }, 832 { 0x00, 0x050, 56, "4.4" }, 833 { 0x00, 0x060, 62, "4.0" }, 834 { 0x00, 0x070, 68, "3.6" }, 835 { 0x00, 0x000, 0, NULL } 836 }; 837 838 /* 839 * Allocate a controller structure for a new device and initialize it. 840 */ 841 int 842 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 843 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 844 ahc_flag flags) 845 { 846 struct scb_data *scb_data; 847 848 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 849 if (scb_data == NULL) { 850 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 851 return -1; 852 } 853 bzero(scb_data, sizeof (struct scb_data)); 854 LIST_INIT(&ahc->pending_ccbs); 855 ahc->tag = st; 856 ahc->bsh = sh; 857 ahc->parent_dmat = parent_dmat; 858 ahc->chip = chip; 859 ahc->features = features; 860 ahc->flags = flags; 861 ahc->scb_data = scb_data; 862 863 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 864 /* The IRQMS bit is only valid on VL and EISA chips */ 865 if ((ahc->chip & AHC_PCI) != 0) 866 ahc->unpause &= ~IRQMS; 867 ahc->pause = ahc->unpause | PAUSE; 868 return (0); 869 } 870 871 void 872 ahc_free(ahc) 873 struct ahc_softc *ahc; 874 { 875 ahcfiniscbdata(ahc); 876 if (ahc->init_level != 0) 877 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 878 ahc->shared_data_dmamap, ahc->qoutfifo, 879 &ahc->shared_data_seg, ahc->shared_data_nseg); 880 881 if (ahc->scb_data != NULL) 882 free(ahc->scb_data, M_DEVBUF); 883 if (ahc->bus_data != NULL) 884 free(ahc->bus_data, M_DEVBUF); 885 return; 886 } 887 888 static int 889 ahcinitscbdata(struct ahc_softc *ahc) 890 { 891 struct scb_data *scb_data; 892 int i; 893 894 scb_data = ahc->scb_data; 895 SLIST_INIT(&scb_data->free_scbs); 896 SLIST_INIT(&scb_data->sg_maps); 897 898 /* Allocate SCB resources */ 899 scb_data->scbarray = 900 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 901 M_DEVBUF, M_NOWAIT); 902 if (scb_data->scbarray == NULL) 903 return (ENOMEM); 904 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 905 906 /* Determine the number of hardware SCBs and initialize them */ 907 908 scb_data->maxhscbs = ahc_probe_scbs(ahc); 909 /* SCB 0 heads the free list */ 910 ahc_outb(ahc, FREE_SCBH, 0); 911 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 912 ahc_outb(ahc, SCBPTR, i); 913 914 /* Clear the control byte. */ 915 ahc_outb(ahc, SCB_CONTROL, 0); 916 917 /* Set the next pointer */ 918 ahc_outb(ahc, SCB_NEXT, i+1); 919 920 /* Make the tag number invalid */ 921 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 922 } 923 924 /* Make sure that the last SCB terminates the free list */ 925 ahc_outb(ahc, SCBPTR, i-1); 926 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 927 928 /* Ensure we clear the 0 SCB's control byte. */ 929 ahc_outb(ahc, SCBPTR, 0); 930 ahc_outb(ahc, SCB_CONTROL, 0); 931 932 scb_data->maxhscbs = i; 933 934 if (ahc->scb_data->maxhscbs == 0) 935 panic("%s: No SCB space found", ahc_name(ahc)); 936 937 /* 938 * Create our DMA tags. These tags define the kinds of device 939 * accessable memory allocations and memory mappings we will 940 * need to perform during normal operation. 941 * 942 * Unless we need to further restrict the allocation, we rely 943 * on the restrictions of the parent dmat, hence the common 944 * use of MAXADDR and MAXSIZE. 945 */ 946 947 if (ahc_createdmamem(ahc->parent_dmat, 948 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 949 &scb_data->hscb_dmamap, 950 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 951 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 952 "hardware SCB structures") < 0) 953 goto error_exit; 954 955 scb_data->init_level++; 956 957 if (ahc_createdmamem(ahc->parent_dmat, 958 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 959 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 960 &scb_data->sense_busaddr, &scb_data->sense_seg, 961 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 962 goto error_exit; 963 964 scb_data->init_level++; 965 966 /* Perform initial CCB allocation */ 967 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 968 ahcallocscbs(ahc); 969 970 if (scb_data->numscbs == 0) { 971 printf("%s: ahc_init_scb_data - " 972 "Unable to allocate initial scbs\n", 973 ahc_name(ahc)); 974 goto error_exit; 975 } 976 977 scb_data->init_level++; 978 979 /* 980 * Note that we were successfull 981 */ 982 return 0; 983 984 error_exit: 985 986 return ENOMEM; 987 } 988 989 static void 990 ahcfiniscbdata(struct ahc_softc *ahc) 991 { 992 struct scb_data *scb_data; 993 994 scb_data = ahc->scb_data; 995 996 switch (scb_data->init_level) { 997 default: 998 case 3: 999 { 1000 struct sg_map_node *sg_map; 1001 1002 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1003 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1004 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1005 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1006 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1007 free(sg_map, M_DEVBUF); 1008 } 1009 } 1010 /*FALLTHROUGH*/ 1011 case 2: 1012 ahc_freedmamem(ahc->parent_dmat, 1013 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1014 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1015 &scb_data->sense_seg, scb_data->sense_nseg); 1016 /*FALLTHROUGH*/ 1017 case 1: 1018 ahc_freedmamem(ahc->parent_dmat, 1019 AHC_SCB_MAX * sizeof(struct hardware_scb), 1020 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1021 &scb_data->hscb_seg, scb_data->hscb_nseg); 1022 /*FALLTHROUGH*/ 1023 } 1024 if (scb_data->scbarray != NULL) 1025 free(scb_data->scbarray, M_DEVBUF); 1026 } 1027 1028 int 1029 ahc_reset(struct ahc_softc *ahc) 1030 { 1031 u_int sblkctl; 1032 int wait; 1033 1034 #ifdef AHC_DUMP_SEQ 1035 if (ahc->init_level == 0) 1036 ahc_dumpseq(ahc); 1037 #endif 1038 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1039 /* 1040 * Ensure that the reset has finished 1041 */ 1042 wait = 1000; 1043 do { 1044 DELAY(1000); 1045 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1046 1047 if (wait == 0) { 1048 printf("%s: WARNING - Failed chip reset! " 1049 "Trying to initialize anyway.\n", ahc_name(ahc)); 1050 } 1051 ahc_outb(ahc, HCNTRL, ahc->pause); 1052 1053 /* Determine channel configuration */ 1054 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1055 /* No Twin Channel PCI cards */ 1056 if ((ahc->chip & AHC_PCI) != 0) 1057 sblkctl &= ~SELBUSB; 1058 switch (sblkctl) { 1059 case 0: 1060 /* Single Narrow Channel */ 1061 break; 1062 case 2: 1063 /* Wide Channel */ 1064 ahc->features |= AHC_WIDE; 1065 break; 1066 case 8: 1067 /* Twin Channel */ 1068 ahc->features |= AHC_TWIN; 1069 break; 1070 default: 1071 printf(" Unsupported adapter type. Ignoring\n"); 1072 return(-1); 1073 } 1074 1075 return (0); 1076 } 1077 1078 /* 1079 * Called when we have an active connection to a target on the bus, 1080 * this function finds the nearest syncrate to the input period limited 1081 * by the capabilities of the bus connectivity of the target. 1082 */ 1083 static struct ahc_syncrate * 1084 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1085 u_int maxsync; 1086 1087 if ((ahc->features & AHC_ULTRA2) != 0) { 1088 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1089 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1090 maxsync = AHC_SYNCRATE_ULTRA2; 1091 } else { 1092 maxsync = AHC_SYNCRATE_ULTRA; 1093 } 1094 } else if ((ahc->features & AHC_ULTRA) != 0) { 1095 maxsync = AHC_SYNCRATE_ULTRA; 1096 } else { 1097 maxsync = AHC_SYNCRATE_FAST; 1098 } 1099 return (ahc_find_syncrate(ahc, period, maxsync)); 1100 } 1101 1102 /* 1103 * Look up the valid period to SCSIRATE conversion in our table. 1104 * Return the period and offset that should be sent to the target 1105 * if this was the beginning of an SDTR. 1106 */ 1107 static struct ahc_syncrate * 1108 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1109 { 1110 struct ahc_syncrate *syncrate; 1111 1112 syncrate = &ahc_syncrates[maxsync]; 1113 while ((syncrate->rate != NULL) 1114 && ((ahc->features & AHC_ULTRA2) == 0 1115 || (syncrate->sxfr_u2 != 0))) { 1116 1117 if (*period <= syncrate->period) { 1118 /* 1119 * When responding to a target that requests 1120 * sync, the requested rate may fall between 1121 * two rates that we can output, but still be 1122 * a rate that we can receive. Because of this, 1123 * we want to respond to the target with 1124 * the same rate that it sent to us even 1125 * if the period we use to send data to it 1126 * is lower. Only lower the response period 1127 * if we must. 1128 */ 1129 if (syncrate == &ahc_syncrates[maxsync]) 1130 *period = syncrate->period; 1131 break; 1132 } 1133 syncrate++; 1134 } 1135 1136 if ((*period == 0) 1137 || (syncrate->rate == NULL) 1138 || ((ahc->features & AHC_ULTRA2) != 0 1139 && (syncrate->sxfr_u2 == 0))) { 1140 /* Use asynchronous transfers. */ 1141 *period = 0; 1142 syncrate = NULL; 1143 } 1144 return (syncrate); 1145 } 1146 1147 static u_int 1148 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1149 { 1150 struct ahc_syncrate *syncrate; 1151 1152 if ((ahc->features & AHC_ULTRA2) != 0) 1153 scsirate &= SXFR_ULTRA2; 1154 else 1155 scsirate &= SXFR; 1156 1157 syncrate = &ahc_syncrates[maxsync]; 1158 while (syncrate->rate != NULL) { 1159 1160 if ((ahc->features & AHC_ULTRA2) != 0) { 1161 if (syncrate->sxfr_u2 == 0) 1162 break; 1163 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1164 return (syncrate->period); 1165 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1166 return (syncrate->period); 1167 } 1168 syncrate++; 1169 } 1170 return (0); /* async */ 1171 } 1172 1173 static void 1174 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1175 u_int *offset, int wide) 1176 { 1177 u_int maxoffset; 1178 1179 /* Limit offset to what we can do */ 1180 if (syncrate == NULL) { 1181 maxoffset = 0; 1182 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1183 maxoffset = MAX_OFFSET_ULTRA2; 1184 } else { 1185 if (wide) 1186 maxoffset = MAX_OFFSET_16BIT; 1187 else 1188 maxoffset = MAX_OFFSET_8BIT; 1189 } 1190 *offset = MIN(*offset, maxoffset); 1191 } 1192 1193 static void 1194 ahc_update_target_msg_request(struct ahc_softc *ahc, 1195 struct ahc_devinfo *devinfo, 1196 struct ahc_initiator_tinfo *tinfo, 1197 int force, int paused) 1198 { 1199 u_int targ_msg_req_orig; 1200 1201 targ_msg_req_orig = ahc->targ_msg_req; 1202 if (tinfo->current.period != tinfo->goal.period 1203 || tinfo->current.width != tinfo->goal.width 1204 || tinfo->current.offset != tinfo->goal.offset 1205 || (force 1206 && (tinfo->goal.period != 0 1207 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1208 ahc->targ_msg_req |= devinfo->target_mask; 1209 } else { 1210 ahc->targ_msg_req &= ~devinfo->target_mask; 1211 } 1212 1213 if (ahc->targ_msg_req != targ_msg_req_orig) { 1214 /* Update the message request bit for this target */ 1215 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1216 if (paused) { 1217 ahc_outb(ahc, TARGET_MSG_REQUEST, 1218 ahc->targ_msg_req & 0xFF); 1219 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1220 (ahc->targ_msg_req >> 8) & 0xFF); 1221 } else { 1222 ahc_outb(ahc, HS_MAILBOX, 1223 0x01 << HOST_MAILBOX_SHIFT); 1224 } 1225 } else { 1226 if (!paused) 1227 pause_sequencer(ahc); 1228 1229 ahc_outb(ahc, TARGET_MSG_REQUEST, 1230 ahc->targ_msg_req & 0xFF); 1231 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1232 (ahc->targ_msg_req >> 8) & 0xFF); 1233 1234 if (!paused) 1235 unpause_sequencer(ahc); 1236 } 1237 } 1238 } 1239 1240 static void 1241 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1242 struct ahc_syncrate *syncrate, 1243 u_int period, u_int offset, u_int type, int paused, int done) 1244 { 1245 struct ahc_initiator_tinfo *tinfo; 1246 struct tmode_tstate *tstate; 1247 u_int old_period; 1248 u_int old_offset; 1249 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1250 1251 if (syncrate == NULL) { 1252 period = 0; 1253 offset = 0; 1254 } 1255 1256 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1257 devinfo->target, &tstate); 1258 old_period = tinfo->current.period; 1259 old_offset = tinfo->current.offset; 1260 1261 if ((type & AHC_TRANS_CUR) != 0 1262 && (old_period != period || old_offset != offset)) { 1263 u_int scsirate; 1264 1265 scsirate = tinfo->scsirate; 1266 if ((ahc->features & AHC_ULTRA2) != 0) { 1267 1268 /* XXX */ 1269 /* Force single edge until DT is fully implemented */ 1270 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1271 if (syncrate != NULL) 1272 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1273 1274 if (active) 1275 ahc_outb(ahc, SCSIOFFSET, offset); 1276 } else { 1277 1278 scsirate &= ~(SXFR|SOFS); 1279 /* 1280 * Ensure Ultra mode is set properly for 1281 * this target. 1282 */ 1283 tstate->ultraenb &= ~devinfo->target_mask; 1284 if (syncrate != NULL) { 1285 if (syncrate->sxfr & ULTRA_SXFR) { 1286 tstate->ultraenb |= 1287 devinfo->target_mask; 1288 } 1289 scsirate |= syncrate->sxfr & SXFR; 1290 scsirate |= offset & SOFS; 1291 } 1292 if (active) { 1293 u_int sxfrctl0; 1294 1295 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1296 sxfrctl0 &= ~FAST20; 1297 if (tstate->ultraenb & devinfo->target_mask) 1298 sxfrctl0 |= FAST20; 1299 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1300 } 1301 } 1302 if (active) 1303 ahc_outb(ahc, SCSIRATE, scsirate); 1304 1305 tinfo->scsirate = scsirate; 1306 tinfo->current.period = period; 1307 tinfo->current.offset = offset; 1308 1309 /* Update the syncrates in any pending scbs */ 1310 ahc_update_pending_syncrates(ahc); 1311 } 1312 1313 /* 1314 * Print messages if we're verbose and at the end of a negotiation 1315 * cycle. 1316 */ 1317 if (done) { 1318 if (offset != 0) { 1319 printf("%s: target %d synchronous at %sMHz, " 1320 "offset = 0x%x\n", ahc_name(ahc), 1321 devinfo->target, syncrate->rate, offset); 1322 } else { 1323 printf("%s: target %d using " 1324 "asynchronous transfers\n", 1325 ahc_name(ahc), devinfo->target); 1326 } 1327 } 1328 1329 if ((type & AHC_TRANS_GOAL) != 0) { 1330 tinfo->goal.period = period; 1331 tinfo->goal.offset = offset; 1332 } 1333 1334 if ((type & AHC_TRANS_USER) != 0) { 1335 tinfo->user.period = period; 1336 tinfo->user.offset = offset; 1337 } 1338 1339 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1340 /*force*/FALSE, 1341 paused); 1342 } 1343 1344 static void 1345 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1346 u_int width, u_int type, int paused, int done) 1347 { 1348 struct ahc_initiator_tinfo *tinfo; 1349 struct tmode_tstate *tstate; 1350 u_int oldwidth; 1351 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1352 1353 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1354 devinfo->target, &tstate); 1355 oldwidth = tinfo->current.width; 1356 1357 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1358 u_int scsirate; 1359 1360 scsirate = tinfo->scsirate; 1361 scsirate &= ~WIDEXFER; 1362 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1363 scsirate |= WIDEXFER; 1364 1365 tinfo->scsirate = scsirate; 1366 1367 if (active) 1368 ahc_outb(ahc, SCSIRATE, scsirate); 1369 1370 tinfo->current.width = width; 1371 } 1372 1373 if (done) { 1374 printf("%s: target %d using %dbit transfers\n", 1375 ahc_name(ahc), devinfo->target, 1376 8 * (0x01 << width)); 1377 } 1378 1379 if ((type & AHC_TRANS_GOAL) != 0) 1380 tinfo->goal.width = width; 1381 if ((type & AHC_TRANS_USER) != 0) 1382 tinfo->user.width = width; 1383 1384 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1385 /*force*/FALSE, paused); 1386 } 1387 1388 static void 1389 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1390 { 1391 struct ahc_initiator_tinfo *tinfo; 1392 struct tmode_tstate *tstate; 1393 1394 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1395 devinfo->target, &tstate); 1396 1397 if (enable) 1398 tstate->tagenable |= devinfo->target_mask; 1399 else { 1400 tstate->tagenable &= ~devinfo->target_mask; 1401 tstate->tagdisable |= devinfo->target_mask; 1402 } 1403 } 1404 1405 /* 1406 * Attach all the sub-devices we can find 1407 */ 1408 int 1409 ahc_attach(struct ahc_softc *ahc) 1410 { 1411 TAILQ_INIT(&ahc->sc_q); 1412 1413 ahc->sc_adapter.scsipi_cmd = ahc_action; 1414 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1415 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1416 ahc->sc_link.type = BUS_SCSI; 1417 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1418 ahc->sc_link.scsipi_scsi.channel = 0; 1419 ahc->sc_link.scsipi_scsi.max_target = 1420 (ahc->features & AHC_WIDE) ? 15 : 7; 1421 ahc->sc_link.scsipi_scsi.max_lun = 7; 1422 ahc->sc_link.adapter_softc = ahc; 1423 ahc->sc_link.adapter = &ahc->sc_adapter; 1424 ahc->sc_link.openings = 2; 1425 ahc->sc_link.device = &ahc_dev; 1426 1427 if (ahc->features & AHC_TWIN) { 1428 ahc->sc_link_b = ahc->sc_link; 1429 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1430 ahc->sc_link_b.scsipi_scsi.channel = 1; 1431 } 1432 1433 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1434 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1435 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1436 if (ahc->features & AHC_TWIN) 1437 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1438 } else { 1439 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1440 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1441 } 1442 return 1; 1443 } 1444 1445 static void 1446 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1447 { 1448 u_int saved_tcl; 1449 role_t role; 1450 int our_id; 1451 1452 if (ahc_inb(ahc, SSTAT0) & TARGET) 1453 role = ROLE_TARGET; 1454 else 1455 role = ROLE_INITIATOR; 1456 1457 if (role == ROLE_TARGET 1458 && (ahc->features & AHC_MULTI_TID) != 0 1459 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1460 /* We were selected, so pull our id from TARGIDIN */ 1461 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1462 } else if ((ahc->features & AHC_ULTRA2) != 0) 1463 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1464 else 1465 our_id = ahc_inb(ahc, SCSIID) & OID; 1466 1467 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1468 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1469 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1470 role); 1471 } 1472 1473 static void 1474 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1475 u_int lun, char channel, role_t role) 1476 { 1477 devinfo->our_scsiid = our_id; 1478 devinfo->target = target; 1479 devinfo->lun = lun; 1480 devinfo->target_offset = target; 1481 devinfo->channel = channel; 1482 devinfo->role = role; 1483 if (channel == 'B') 1484 devinfo->target_offset += 8; 1485 devinfo->target_mask = (0x01 << devinfo->target_offset); 1486 } 1487 1488 /* 1489 * Catch an interrupt from the adapter 1490 */ 1491 int 1492 ahc_intr(void *arg) 1493 { 1494 struct ahc_softc *ahc; 1495 u_int intstat; 1496 1497 ahc = (struct ahc_softc *)arg; 1498 1499 intstat = ahc_inb(ahc, INTSTAT); 1500 1501 /* 1502 * Any interrupts to process? 1503 */ 1504 if ((intstat & INT_PEND) == 0) { 1505 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1506 #ifdef AHC_DEBUG 1507 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1508 ahc_name(ahc), 1509 ahc_inb(ahc, CCHADDR) | 1510 (ahc_inb(ahc, CCHADDR+1) << 8) 1511 | (ahc_inb(ahc, CCHADDR+2) << 16) 1512 | (ahc_inb(ahc, CCHADDR+3) << 24), 1513 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1514 | (ahc_inb(ahc, HADDR+2) << 16) 1515 | (ahc_inb(ahc, HADDR+3) << 24), 1516 ahc_inb(ahc, SEQADDR0) | 1517 (ahc_inb(ahc, SEQADDR1) << 8)); 1518 #endif 1519 return 1; 1520 } 1521 return 0; 1522 } 1523 1524 #ifdef AHC_DEBUG 1525 if (ahc_debug & AHC_SHOWINTR) { 1526 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1527 } 1528 #endif 1529 1530 if (intstat & CMDCMPLT) { 1531 ahc_outb(ahc, CLRINT, CLRCMDINT); 1532 ahc_run_qoutfifo(ahc); 1533 } 1534 if (intstat & BRKADRINT) { 1535 /* 1536 * We upset the sequencer :-( 1537 * Lookup the error message 1538 */ 1539 int i, error, num_errors; 1540 1541 error = ahc_inb(ahc, ERROR); 1542 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1543 for (i = 0; error != 1 && i < num_errors; i++) 1544 error >>= 1; 1545 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1546 ahc_name(ahc), hard_error[i].errmesg, 1547 ahc_inb(ahc, SEQADDR0) | 1548 (ahc_inb(ahc, SEQADDR1) << 8)); 1549 1550 /* Tell everyone that this HBA is no longer availible */ 1551 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1552 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1553 XS_DRIVER_STUFFUP); 1554 } 1555 if (intstat & SEQINT) 1556 ahc_handle_seqint(ahc, intstat); 1557 1558 if (intstat & SCSIINT) 1559 ahc_handle_scsiint(ahc, intstat); 1560 1561 return 1; 1562 } 1563 1564 static struct tmode_tstate * 1565 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1566 { 1567 struct tmode_tstate *master_tstate; 1568 struct tmode_tstate *tstate; 1569 int i, s; 1570 1571 master_tstate = ahc->enabled_targets[ahc->our_id]; 1572 if (channel == 'B') { 1573 scsi_id += 8; 1574 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1575 } 1576 if (ahc->enabled_targets[scsi_id] != NULL 1577 && ahc->enabled_targets[scsi_id] != master_tstate) 1578 panic("%s: ahc_alloc_tstate - Target already allocated", 1579 ahc_name(ahc)); 1580 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1581 if (tstate == NULL) 1582 return (NULL); 1583 1584 /* 1585 * If we have allocated a master tstate, copy user settings from 1586 * the master tstate (taken from SRAM or the EEPROM) for this 1587 * channel, but reset our current and goal settings to async/narrow 1588 * until an initiator talks to us. 1589 */ 1590 if (master_tstate != NULL) { 1591 bcopy(master_tstate, tstate, sizeof(*tstate)); 1592 tstate->ultraenb = 0; 1593 for (i = 0; i < 16; i++) { 1594 bzero(&tstate->transinfo[i].current, 1595 sizeof(tstate->transinfo[i].current)); 1596 bzero(&tstate->transinfo[i].goal, 1597 sizeof(tstate->transinfo[i].goal)); 1598 } 1599 } else 1600 bzero(tstate, sizeof(*tstate)); 1601 s = splbio(); 1602 ahc->enabled_targets[scsi_id] = tstate; 1603 splx(s); 1604 return (tstate); 1605 } 1606 1607 #if UNUSED 1608 static void 1609 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1610 { 1611 struct tmode_tstate *tstate; 1612 1613 /* Don't clean up the entry for our initiator role */ 1614 if ((ahc->flags & AHC_INITIATORMODE) != 0 1615 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1616 || (channel == 'A' && scsi_id == ahc->our_id)) 1617 && force == FALSE) 1618 return; 1619 1620 if (channel == 'B') 1621 scsi_id += 8; 1622 tstate = ahc->enabled_targets[scsi_id]; 1623 if (tstate != NULL) 1624 free(tstate, M_DEVBUF); 1625 ahc->enabled_targets[scsi_id] = NULL; 1626 } 1627 #endif 1628 1629 static void 1630 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1631 { 1632 struct scb *scb; 1633 struct ahc_devinfo devinfo; 1634 1635 ahc_fetch_devinfo(ahc, &devinfo); 1636 1637 /* 1638 * Clear the upper byte that holds SEQINT status 1639 * codes and clear the SEQINT bit. We will unpause 1640 * the sequencer, if appropriate, after servicing 1641 * the request. 1642 */ 1643 ahc_outb(ahc, CLRINT, CLRSEQINT); 1644 switch (intstat & SEQINT_MASK) { 1645 case NO_MATCH: 1646 { 1647 /* Ensure we don't leave the selection hardware on */ 1648 ahc_outb(ahc, SCSISEQ, 1649 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1650 1651 printf("%s:%c:%d: no active SCB for reconnecting " 1652 "target - issuing BUS DEVICE RESET\n", 1653 ahc_name(ahc), devinfo.channel, devinfo.target); 1654 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1655 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1656 ahc_inb(ahc, SEQ_FLAGS)); 1657 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1658 ahc->msgout_len = 1; 1659 ahc->msgout_index = 0; 1660 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1661 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1662 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1663 break; 1664 } 1665 case UPDATE_TMSG_REQ: 1666 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1667 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1668 (ahc->targ_msg_req >> 8) & 0xFF); 1669 ahc_outb(ahc, HS_MAILBOX, 0); 1670 break; 1671 case SEND_REJECT: 1672 { 1673 u_int rejbyte = ahc_inb(ahc, ACCUM); 1674 printf("%s:%c:%d: Warning - unknown message received from " 1675 "target (0x%x). Rejecting\n", 1676 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1677 break; 1678 } 1679 case NO_IDENT: 1680 { 1681 /* 1682 * The reconnecting target either did not send an identify 1683 * message, or did, but we didn't find and SCB to match and 1684 * before it could respond to our ATN/abort, it hit a dataphase. 1685 * The only safe thing to do is to blow it away with a bus 1686 * reset. 1687 */ 1688 int found; 1689 1690 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1691 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1692 ahc_name(ahc), devinfo.channel, devinfo.target, 1693 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1694 found = ahc_reset_channel(ahc, devinfo.channel, 1695 /*initiate reset*/TRUE); 1696 printf("%s: Issued Channel %c Bus Reset. " 1697 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1698 found); 1699 return; 1700 } 1701 case BAD_PHASE: 1702 { 1703 u_int lastphase; 1704 1705 lastphase = ahc_inb(ahc, LASTPHASE); 1706 if (lastphase == P_BUSFREE) { 1707 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1708 ahc_name(ahc), devinfo.channel, devinfo.target, 1709 ahc_inb(ahc, SCSISIGI)); 1710 restart_sequencer(ahc); 1711 return; 1712 } else { 1713 printf("%s:%c:%d: unknown scsi bus phase %x. " 1714 "Attempting to continue\n", 1715 ahc_name(ahc), devinfo.channel, devinfo.target, 1716 ahc_inb(ahc, SCSISIGI)); 1717 } 1718 break; 1719 } 1720 case BAD_STATUS: 1721 { 1722 u_int scb_index; 1723 struct hardware_scb *hscb; 1724 struct scsipi_xfer *xs; 1725 struct scb *scbp; 1726 int todo, inqueue; 1727 /* 1728 * The sequencer will notify us when a command 1729 * has an error that would be of interest to 1730 * the kernel. This allows us to leave the sequencer 1731 * running in the common case of command completes 1732 * without error. The sequencer will already have 1733 * dma'd the SCB back up to us, so we can reference 1734 * the in kernel copy directly. 1735 */ 1736 scb_index = ahc_inb(ahc, SCB_TAG); 1737 scb = &ahc->scb_data->scbarray[scb_index]; 1738 1739 /* ahc_print_scb(scb); */ 1740 1741 /* 1742 * Set the default return value to 0 (don't 1743 * send sense). The sense code will change 1744 * this if needed. 1745 */ 1746 ahc_outb(ahc, RETURN_1, 0); 1747 if (!(scb_index < ahc->scb_data->numscbs 1748 && (scb->flags & SCB_ACTIVE) != 0)) { 1749 printf("%s:%c:%d: ahc_intr - referenced scb " 1750 "not valid during seqint 0x%x scb(%d)\n", 1751 ahc_name(ahc), devinfo.channel, 1752 devinfo.target, intstat, scb_index); 1753 goto unpause; 1754 } 1755 1756 hscb = scb->hscb; 1757 xs = scb->xs; 1758 1759 /* Don't want to clobber the original sense code */ 1760 if ((scb->flags & SCB_SENSE) != 0) { 1761 /* 1762 * Clear the SCB_SENSE Flag and have 1763 * the sequencer do a normal command 1764 * complete. 1765 */ 1766 scb->flags &= ~SCB_SENSE; 1767 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1768 break; 1769 } 1770 /* Freeze the queue unit the client sees the error. */ 1771 ahc_freeze_devq(ahc, xs->sc_link); 1772 ahc_freeze_ccb(scb); 1773 xs->status = hscb->status; 1774 switch (hscb->status) { 1775 case SCSI_STATUS_OK: 1776 printf("%s: Interrupted for status of 0???\n", 1777 ahc_name(ahc)); 1778 break; 1779 case SCSI_STATUS_CMD_TERMINATED: 1780 case SCSI_STATUS_CHECK_COND: 1781 #if defined(AHC_DEBUG) 1782 if (ahc_debug & AHC_SHOWSENSE) { 1783 scsi_print_addr(xs->sc_link); 1784 printf("Check Status, resid %d datalen %d\n", 1785 xs->resid, xs->datalen); 1786 } 1787 #endif 1788 1789 if (xs->error == XS_NOERROR && 1790 !(scb->flags & SCB_SENSE)) { 1791 struct ahc_dma_seg *sg; 1792 struct scsipi_sense *sc; 1793 struct ahc_initiator_tinfo *tinfo; 1794 struct tmode_tstate *tstate; 1795 1796 sg = scb->sg_list; 1797 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1798 /* 1799 * Save off the residual if there is one. 1800 */ 1801 if (hscb->residual_SG_count != 0) 1802 ahc_calc_residual(scb); 1803 else 1804 xs->resid = 0; 1805 1806 #ifdef AHC_DEBUG 1807 if (ahc_debug & AHC_SHOWSENSE) { 1808 scsi_print_addr(xs->sc_link); 1809 printf("Sending Sense\n"); 1810 } 1811 #endif 1812 sg->addr = ahc->scb_data->sense_busaddr + 1813 (hscb->tag*sizeof(struct scsipi_sense_data)); 1814 sg->len = sizeof (struct scsipi_sense_data); 1815 1816 sc->opcode = REQUEST_SENSE; 1817 sc->byte2 = SCB_LUN(scb) << 5; 1818 sc->unused[0] = 0; 1819 sc->unused[1] = 0; 1820 sc->length = sg->len; 1821 sc->control = 0; 1822 1823 /* 1824 * Would be nice to preserve DISCENB here, 1825 * but due to the way we page SCBs, we can't. 1826 */ 1827 hscb->control = 0; 1828 1829 /* 1830 * This request sense could be because the 1831 * the device lost power or in some other 1832 * way has lost our transfer negotiations. 1833 * Renegotiate if appropriate. Unit attention 1834 * errors will be reported before any data 1835 * phases occur. 1836 */ 1837 ahc_calc_residual(scb); 1838 #if defined(AHC_DEBUG) 1839 if (ahc_debug & AHC_SHOWSENSE) { 1840 scsi_print_addr(xs->sc_link); 1841 printf("Sense: datalen %d resid %d" 1842 "chan %d id %d targ %d\n", 1843 xs->datalen, xs->resid, 1844 devinfo.channel, devinfo.our_scsiid, 1845 devinfo.target); 1846 } 1847 #endif 1848 if (xs->datalen > 0 && 1849 xs->resid == xs->datalen) { 1850 tinfo = ahc_fetch_transinfo(ahc, 1851 devinfo.channel, 1852 devinfo.our_scsiid, 1853 devinfo.target, 1854 &tstate); 1855 ahc_update_target_msg_request(ahc, 1856 &devinfo, 1857 tinfo, 1858 /*force*/TRUE, 1859 /*paused*/TRUE); 1860 } 1861 hscb->status = 0; 1862 hscb->SG_count = 1; 1863 hscb->SG_pointer = scb->sg_list_phys; 1864 hscb->data = sg->addr; 1865 hscb->datalen = sg->len; 1866 hscb->cmdpointer = hscb->cmdstore_busaddr; 1867 hscb->cmdlen = sizeof(*sc); 1868 scb->sg_count = hscb->SG_count; 1869 ahc_swap_hscb(hscb); 1870 ahc_swap_sg(scb->sg_list); 1871 scb->flags |= SCB_SENSE; 1872 /* 1873 * Ensure the target is busy since this 1874 * will be an untagged request. 1875 */ 1876 ahc_busy_tcl(ahc, scb); 1877 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1878 1879 /* 1880 * Ensure we have enough time to actually 1881 * retrieve the sense. 1882 */ 1883 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1884 callout_reset(&scb->xs->xs_callout, 1885 5 * hz, ahc_timeout, scb); 1886 } 1887 } 1888 break; 1889 case SCSI_STATUS_QUEUE_FULL: 1890 scsi_print_addr(xs->sc_link); 1891 printf("queue full\n"); 1892 case SCSI_STATUS_BUSY: 1893 /* 1894 * XXX middle layer doesn't handle XS_BUSY well. 1895 * So, requeue this ourselves internally. It will 1896 * get its turn once all outstanding (tagged) 1897 * commands have finished. 1898 */ 1899 xs->error = XS_BUSY; 1900 xs->xs_status |= XS_STS_DEBUG; 1901 scb->flags |= SCB_REQUEUE; 1902 1903 /* 1904 * Walk through all pending SCBs for this target, 1905 * incrementing the freeze count for the queue. 1906 * When all of these have been completed, the 1907 * queue will be available again. 1908 */ 1909 inqueue = todo = 0; 1910 scbp = ahc->pending_ccbs.lh_first; 1911 while (scbp != NULL) { 1912 inqueue++; 1913 if (ahc_match_scb(scbp, SCB_TARGET(scb), 1914 SCB_CHANNEL(scb), SCB_LUN(scb), 1915 SCB_LIST_NULL, ROLE_INITIATOR)) { 1916 ahc_freeze_ccb(scbp); 1917 todo++; 1918 } 1919 scbp = scbp->plinks.le_next; 1920 } 1921 scsi_print_addr(xs->sc_link); 1922 printf("%d SCBs pending, %d to drain\n", inqueue, todo); 1923 break; 1924 } 1925 break; 1926 } 1927 case TRACE_POINT: 1928 { 1929 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1930 ahc_inb(ahc, DFCNTRL)); 1931 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1932 ahc_inb(ahc, DFSTATUS)); 1933 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1934 ahc_inb(ahc, SSTAT0), 1935 ahc_inb(ahc, SCB_DATACNT)); 1936 break; 1937 } 1938 case HOST_MSG_LOOP: 1939 { 1940 /* 1941 * The sequencer has encountered a message phase 1942 * that requires host assistance for completion. 1943 * While handling the message phase(s), we will be 1944 * notified by the sequencer after each byte is 1945 * transfered so we can track bus phases. 1946 * 1947 * If this is the first time we've seen a HOST_MSG_LOOP, 1948 * initialize the state of the host message loop. 1949 */ 1950 if (ahc->msg_type == MSG_TYPE_NONE) { 1951 u_int bus_phase; 1952 1953 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1954 if (bus_phase != P_MESGIN 1955 && bus_phase != P_MESGOUT) { 1956 printf("ahc_intr: HOST_MSG_LOOP bad " 1957 "phase 0x%x\n", 1958 bus_phase); 1959 /* 1960 * Probably transitioned to bus free before 1961 * we got here. Just punt the message. 1962 */ 1963 ahc_clear_intstat(ahc); 1964 restart_sequencer(ahc); 1965 } 1966 1967 if (devinfo.role == ROLE_INITIATOR) { 1968 struct scb *scb; 1969 u_int scb_index; 1970 1971 scb_index = ahc_inb(ahc, SCB_TAG); 1972 scb = &ahc->scb_data->scbarray[scb_index]; 1973 1974 if (bus_phase == P_MESGOUT) 1975 ahc_setup_initiator_msgout(ahc, 1976 &devinfo, 1977 scb); 1978 else { 1979 ahc->msg_type = 1980 MSG_TYPE_INITIATOR_MSGIN; 1981 ahc->msgin_index = 0; 1982 } 1983 } else { 1984 if (bus_phase == P_MESGOUT) { 1985 ahc->msg_type = 1986 MSG_TYPE_TARGET_MSGOUT; 1987 ahc->msgin_index = 0; 1988 } else 1989 /* XXX Ever executed??? */ 1990 ahc_setup_target_msgin(ahc, &devinfo); 1991 } 1992 } 1993 1994 /* Pass a NULL path so that handlers generate their own */ 1995 ahc_handle_message_phase(ahc, /*path*/NULL); 1996 break; 1997 } 1998 case PERR_DETECTED: 1999 { 2000 /* 2001 * If we've cleared the parity error interrupt 2002 * but the sequencer still believes that SCSIPERR 2003 * is true, it must be that the parity error is 2004 * for the currently presented byte on the bus, 2005 * and we are not in a phase (data-in) where we will 2006 * eventually ack this byte. Ack the byte and 2007 * throw it away in the hope that the target will 2008 * take us to message out to deliver the appropriate 2009 * error message. 2010 */ 2011 if ((intstat & SCSIINT) == 0 2012 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 2013 u_int curphase; 2014 2015 /* 2016 * The hardware will only let you ack bytes 2017 * if the expected phase in SCSISIGO matches 2018 * the current phase. Make sure this is 2019 * currently the case. 2020 */ 2021 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2022 ahc_outb(ahc, LASTPHASE, curphase); 2023 ahc_outb(ahc, SCSISIGO, curphase); 2024 ahc_inb(ahc, SCSIDATL); 2025 } 2026 break; 2027 } 2028 case DATA_OVERRUN: 2029 { 2030 /* 2031 * When the sequencer detects an overrun, it 2032 * places the controller in "BITBUCKET" mode 2033 * and allows the target to complete its transfer. 2034 * Unfortunately, none of the counters get updated 2035 * when the controller is in this mode, so we have 2036 * no way of knowing how large the overrun was. 2037 */ 2038 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2039 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2040 int i; 2041 2042 scb = &ahc->scb_data->scbarray[scbindex]; 2043 for (i = 0; i < num_phases; i++) { 2044 if (lastphase == phase_table[i].phase) 2045 break; 2046 } 2047 scsi_print_addr(scb->xs->sc_link); 2048 printf("data overrun detected %s." 2049 " Tag == 0x%x.\n", 2050 phase_table[i].phasemsg, 2051 scb->hscb->tag); 2052 scsi_print_addr(scb->xs->sc_link); 2053 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2054 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2055 scb->xs->datalen, scb->sg_count); 2056 if (scb->sg_count > 0) { 2057 for (i = 0; i < scb->sg_count; i++) { 2058 printf("sg[%d] - Addr 0x%x : Length %d\n", 2059 i, 2060 le32toh(scb->sg_list[i].addr), 2061 le32toh(scb->sg_list[i].len)); 2062 } 2063 } 2064 /* 2065 * Set this and it will take affect when the 2066 * target does a command complete. 2067 */ 2068 ahc_freeze_devq(ahc, scb->xs->sc_link); 2069 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2070 ahc_freeze_ccb(scb); 2071 break; 2072 } 2073 case TRACEPOINT: 2074 { 2075 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2076 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2077 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2078 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2079 printf("TRACEPOINT: CCHADDR = %x\n", 2080 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2081 | (ahc_inb(ahc, CCHADDR+2) << 16) 2082 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2083 #if 0 2084 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2085 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2086 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2087 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2088 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2089 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2090 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2091 ahc_inb(ahc, CCHADDR) 2092 | (ahc_inb(ahc, CCHADDR+1) << 8) 2093 | (ahc_inb(ahc, CCHADDR+2) << 16) 2094 | (ahc_inb(ahc, CCHADDR+3) << 24), 2095 ahc_inb(ahc, CCHCNT) 2096 | (ahc_inb(ahc, CCHCNT+1) << 8) 2097 | (ahc_inb(ahc, CCHCNT+2) << 16), 2098 ahc_inb(ahc, SCBPTR)); 2099 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2100 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2101 #if DDB > 0 2102 cpu_Debugger(); 2103 #endif 2104 #endif 2105 break; 2106 } 2107 #if NOT_YET 2108 /* XXX Fill these in later */ 2109 case MESG_BUFFER_BUSY: 2110 break; 2111 case MSGIN_PHASEMIS: 2112 break; 2113 #endif 2114 default: 2115 printf("ahc_intr: seqint, " 2116 "intstat == 0x%x, scsisigi = 0x%x\n", 2117 intstat, ahc_inb(ahc, SCSISIGI)); 2118 break; 2119 } 2120 2121 unpause: 2122 /* 2123 * The sequencer is paused immediately on 2124 * a SEQINT, so we should restart it when 2125 * we're done. 2126 */ 2127 unpause_sequencer(ahc); 2128 } 2129 2130 static void 2131 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2132 { 2133 u_int scb_index; 2134 u_int status; 2135 struct scb *scb; 2136 char cur_channel; 2137 char intr_channel; 2138 2139 if ((ahc->features & AHC_TWIN) != 0 2140 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2141 cur_channel = 'B'; 2142 else 2143 cur_channel = 'A'; 2144 intr_channel = cur_channel; 2145 2146 status = ahc_inb(ahc, SSTAT1); 2147 if (status == 0) { 2148 if ((ahc->features & AHC_TWIN) != 0) { 2149 /* Try the other channel */ 2150 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2151 status = ahc_inb(ahc, SSTAT1); 2152 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2153 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2154 } 2155 if (status == 0) { 2156 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2157 return; 2158 } 2159 } 2160 2161 scb_index = ahc_inb(ahc, SCB_TAG); 2162 if (scb_index < ahc->scb_data->numscbs) { 2163 scb = &ahc->scb_data->scbarray[scb_index]; 2164 if ((scb->flags & SCB_ACTIVE) == 0 2165 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2166 scb = NULL; 2167 } else 2168 scb = NULL; 2169 2170 if ((status & SCSIRSTI) != 0) { 2171 printf("%s: Someone reset channel %c\n", 2172 ahc_name(ahc), intr_channel); 2173 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2174 } else if ((status & SCSIPERR) != 0) { 2175 /* 2176 * Determine the bus phase and queue an appropriate message. 2177 * SCSIPERR is latched true as soon as a parity error 2178 * occurs. If the sequencer acked the transfer that 2179 * caused the parity error and the currently presented 2180 * transfer on the bus has correct parity, SCSIPERR will 2181 * be cleared by CLRSCSIPERR. Use this to determine if 2182 * we should look at the last phase the sequencer recorded, 2183 * or the current phase presented on the bus. 2184 */ 2185 u_int mesg_out; 2186 u_int curphase; 2187 u_int errorphase; 2188 u_int lastphase; 2189 int i; 2190 2191 lastphase = ahc_inb(ahc, LASTPHASE); 2192 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2193 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2194 /* 2195 * For all phases save DATA, the sequencer won't 2196 * automatically ack a byte that has a parity error 2197 * in it. So the only way that the current phase 2198 * could be 'data-in' is if the parity error is for 2199 * an already acked byte in the data phase. During 2200 * synchronous data-in transfers, we may actually 2201 * ack bytes before latching the current phase in 2202 * LASTPHASE, leading to the discrepancy between 2203 * curphase and lastphase. 2204 */ 2205 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2206 || curphase == P_DATAIN) 2207 errorphase = curphase; 2208 else 2209 errorphase = lastphase; 2210 2211 for (i = 0; i < num_phases; i++) { 2212 if (errorphase == phase_table[i].phase) 2213 break; 2214 } 2215 mesg_out = phase_table[i].mesg_out; 2216 if (scb != NULL) 2217 scsi_print_addr(scb->xs->sc_link); 2218 else 2219 printf("%s:%c:%d: ", ahc_name(ahc), 2220 intr_channel, 2221 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2222 2223 printf("parity error detected %s. " 2224 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2225 phase_table[i].phasemsg, 2226 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2227 ahc_inb(ahc, SCSIRATE)); 2228 2229 /* 2230 * We've set the hardware to assert ATN if we 2231 * get a parity error on "in" phases, so all we 2232 * need to do is stuff the message buffer with 2233 * the appropriate message. "In" phases have set 2234 * mesg_out to something other than MSG_NOP. 2235 */ 2236 if (mesg_out != MSG_NOOP) { 2237 if (ahc->msg_type != MSG_TYPE_NONE) 2238 ahc->send_msg_perror = TRUE; 2239 else 2240 ahc_outb(ahc, MSG_OUT, mesg_out); 2241 } 2242 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2243 unpause_sequencer(ahc); 2244 } else if ((status & BUSFREE) != 0 2245 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2246 /* 2247 * First look at what phase we were last in. 2248 * If its message out, chances are pretty good 2249 * that the busfree was in response to one of 2250 * our abort requests. 2251 */ 2252 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2253 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2254 u_int target = TCL_TARGET(saved_tcl); 2255 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2256 char channel = TCL_CHANNEL(ahc, saved_tcl); 2257 int printerror = 1; 2258 2259 ahc_outb(ahc, SCSISEQ, 2260 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2261 if (lastphase == P_MESGOUT) { 2262 u_int message; 2263 u_int tag; 2264 2265 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2266 tag = SCB_LIST_NULL; 2267 switch (message) { 2268 case MSG_ABORT_TAG: 2269 tag = scb->hscb->tag; 2270 /* FALLTRHOUGH */ 2271 case MSG_ABORT: 2272 scsi_print_addr(scb->xs->sc_link); 2273 printf("SCB %x - Abort %s Completed.\n", 2274 scb->hscb->tag, tag == SCB_LIST_NULL ? 2275 "" : "Tag"); 2276 ahc_abort_scbs(ahc, target, channel, 2277 TCL_LUN(saved_tcl), tag, 2278 ROLE_INITIATOR, 2279 XS_DRIVER_STUFFUP); 2280 printerror = 0; 2281 break; 2282 case MSG_BUS_DEV_RESET: 2283 { 2284 struct ahc_devinfo devinfo; 2285 2286 if (scb != NULL && 2287 (scb->xs->xs_control & XS_CTL_RESET) 2288 && ahc_match_scb(scb, target, channel, 2289 TCL_LUN(saved_tcl), 2290 SCB_LIST_NULL, 2291 ROLE_INITIATOR)) { 2292 ahcsetccbstatus(scb->xs, XS_NOERROR); 2293 } 2294 ahc_compile_devinfo(&devinfo, 2295 initiator_role_id, 2296 target, 2297 TCL_LUN(saved_tcl), 2298 channel, 2299 ROLE_INITIATOR); 2300 ahc_handle_devreset(ahc, &devinfo, 2301 XS_RESET, 2302 "Bus Device Reset", 2303 /*verbose_level*/0); 2304 printerror = 0; 2305 break; 2306 } 2307 default: 2308 break; 2309 } 2310 } 2311 if (printerror != 0) { 2312 int i; 2313 2314 if (scb != NULL) { 2315 u_int tag; 2316 2317 if ((scb->hscb->control & TAG_ENB) != 0) 2318 tag = scb->hscb->tag; 2319 else 2320 tag = SCB_LIST_NULL; 2321 ahc_abort_scbs(ahc, target, channel, 2322 SCB_LUN(scb), tag, 2323 ROLE_INITIATOR, 2324 XS_DRIVER_STUFFUP); 2325 scsi_print_addr(scb->xs->sc_link); 2326 } else { 2327 /* 2328 * We had not fully identified this connection, 2329 * so we cannot abort anything. 2330 */ 2331 printf("%s: ", ahc_name(ahc)); 2332 } 2333 for (i = 0; i < num_phases; i++) { 2334 if (lastphase == phase_table[i].phase) 2335 break; 2336 } 2337 printf("Unexpected busfree %s\n" 2338 "SEQADDR == 0x%x\n", 2339 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2340 | (ahc_inb(ahc, SEQADDR1) << 8)); 2341 } 2342 ahc_clear_msg_state(ahc); 2343 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2344 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2345 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2346 restart_sequencer(ahc); 2347 } else if ((status & SELTO) != 0) { 2348 u_int scbptr; 2349 2350 scbptr = ahc_inb(ahc, WAITING_SCBH); 2351 ahc_outb(ahc, SCBPTR, scbptr); 2352 scb_index = ahc_inb(ahc, SCB_TAG); 2353 2354 if (scb_index < ahc->scb_data->numscbs) { 2355 scb = &ahc->scb_data->scbarray[scb_index]; 2356 if ((scb->flags & SCB_ACTIVE) == 0) 2357 scb = NULL; 2358 } else 2359 scb = NULL; 2360 2361 if (scb == NULL) { 2362 printf("%s: ahc_intr - referenced scb not " 2363 "valid during SELTO scb(%d, %d)\n", 2364 ahc_name(ahc), scbptr, scb_index); 2365 } else { 2366 u_int tag; 2367 2368 tag = SCB_LIST_NULL; 2369 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2370 tag = scb->hscb->tag; 2371 2372 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2373 SCB_LUN(scb), tag, 2374 ROLE_INITIATOR, XS_SELTIMEOUT); 2375 } 2376 /* Stop the selection */ 2377 ahc_outb(ahc, SCSISEQ, 0); 2378 2379 /* No more pending messages */ 2380 ahc_clear_msg_state(ahc); 2381 2382 /* 2383 * Although the driver does not care about the 2384 * 'Selection in Progress' status bit, the busy 2385 * LED does. SELINGO is only cleared by a sucessful 2386 * selection, so we must manually clear it to ensure 2387 * the LED turns off just incase no future successful 2388 * selections occur (e.g. no devices on the bus). 2389 */ 2390 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2391 2392 /* Clear interrupt state */ 2393 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2394 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2395 restart_sequencer(ahc); 2396 } else { 2397 scsi_print_addr(scb->xs->sc_link); 2398 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2399 ahc_outb(ahc, CLRSINT1, status); 2400 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2401 unpause_sequencer(ahc); 2402 } 2403 } 2404 2405 static void 2406 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2407 { 2408 /* 2409 * We need to initiate transfer negotiations. 2410 * If our current and goal settings are identical, 2411 * we want to renegotiate due to a check condition. 2412 */ 2413 struct ahc_initiator_tinfo *tinfo; 2414 struct tmode_tstate *tstate; 2415 int dowide; 2416 int dosync; 2417 2418 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2419 devinfo->target, &tstate); 2420 dowide = tinfo->current.width != tinfo->goal.width; 2421 dosync = tinfo->current.period != tinfo->goal.period; 2422 2423 if (!dowide && !dosync) { 2424 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2425 dosync = tinfo->goal.period != 0; 2426 } 2427 2428 if (dowide) { 2429 ahc_construct_wdtr(ahc, tinfo->goal.width); 2430 } else if (dosync) { 2431 struct ahc_syncrate *rate; 2432 u_int period; 2433 u_int offset; 2434 2435 period = tinfo->goal.period; 2436 rate = ahc_devlimited_syncrate(ahc, &period); 2437 offset = tinfo->goal.offset; 2438 ahc_validate_offset(ahc, rate, &offset, 2439 tinfo->current.width); 2440 ahc_construct_sdtr(ahc, period, offset); 2441 } else { 2442 panic("ahc_intr: AWAITING_MSG for negotiation, " 2443 "but no negotiation needed\n"); 2444 } 2445 } 2446 2447 static void 2448 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2449 struct scb *scb) 2450 { 2451 /* 2452 * To facilitate adding multiple messages together, 2453 * each routine should increment the index and len 2454 * variables instead of setting them explicitly. 2455 */ 2456 ahc->msgout_index = 0; 2457 ahc->msgout_len = 0; 2458 2459 if ((scb->flags & SCB_DEVICE_RESET) == 0 2460 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2461 u_int identify_msg; 2462 2463 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2464 if ((scb->hscb->control & DISCENB) != 0) 2465 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2466 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2467 ahc->msgout_len++; 2468 2469 if ((scb->hscb->control & TAG_ENB) != 0) { 2470 /* XXX fvdl FreeBSD has tag action passed down */ 2471 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2472 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2473 ahc->msgout_len += 2; 2474 } 2475 } 2476 2477 if (scb->flags & SCB_DEVICE_RESET) { 2478 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2479 ahc->msgout_len++; 2480 scsi_print_addr(scb->xs->sc_link); 2481 printf("Bus Device Reset Message Sent\n"); 2482 } else if (scb->flags & SCB_ABORT) { 2483 if ((scb->hscb->control & TAG_ENB) != 0) 2484 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2485 else 2486 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2487 ahc->msgout_len++; 2488 scsi_print_addr(scb->xs->sc_link); 2489 printf("Abort Message Sent\n"); 2490 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2491 ahc_build_transfer_msg(ahc, devinfo); 2492 } else { 2493 printf("ahc_intr: AWAITING_MSG for an SCB that " 2494 "does not have a waiting message"); 2495 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2496 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2497 ahc_inb(ahc, MSG_OUT), scb->flags); 2498 } 2499 2500 /* 2501 * Clear the MK_MESSAGE flag from the SCB so we aren't 2502 * asked to send this message again. 2503 */ 2504 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2505 ahc->msgout_index = 0; 2506 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2507 } 2508 2509 static void 2510 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2511 { 2512 /* 2513 * To facilitate adding multiple messages together, 2514 * each routine should increment the index and len 2515 * variables instead of setting them explicitly. 2516 */ 2517 ahc->msgout_index = 0; 2518 ahc->msgout_len = 0; 2519 2520 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2521 ahc_build_transfer_msg(ahc, devinfo); 2522 else 2523 panic("ahc_intr: AWAITING target message with no message"); 2524 2525 ahc->msgout_index = 0; 2526 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2527 } 2528 2529 static int 2530 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2531 { 2532 /* 2533 * What we care about here is if we had an 2534 * outstanding SDTR or WDTR message for this 2535 * target. If we did, this is a signal that 2536 * the target is refusing negotiation. 2537 */ 2538 struct scb *scb; 2539 u_int scb_index; 2540 u_int last_msg; 2541 int response = 0; 2542 2543 scb_index = ahc_inb(ahc, SCB_TAG); 2544 scb = &ahc->scb_data->scbarray[scb_index]; 2545 2546 /* Might be necessary */ 2547 last_msg = ahc_inb(ahc, LAST_MSG); 2548 2549 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2550 struct ahc_initiator_tinfo *tinfo; 2551 struct tmode_tstate *tstate; 2552 2553 #ifdef AHC_DEBUG_NEG 2554 /* note 8bit xfers */ 2555 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2556 "8bit transfers\n", ahc_name(ahc), 2557 devinfo->channel, devinfo->target); 2558 #endif 2559 ahc_set_width(ahc, devinfo, 2560 MSG_EXT_WDTR_BUS_8_BIT, 2561 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2562 /*paused*/TRUE, /*done*/TRUE); 2563 /* 2564 * No need to clear the sync rate. If the target 2565 * did not accept the command, our syncrate is 2566 * unaffected. If the target started the negotiation, 2567 * but rejected our response, we already cleared the 2568 * sync rate before sending our WDTR. 2569 */ 2570 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2571 devinfo->our_scsiid, 2572 devinfo->target, &tstate); 2573 if (tinfo->goal.period) { 2574 u_int period; 2575 2576 /* Start the sync negotiation */ 2577 period = tinfo->goal.period; 2578 ahc_devlimited_syncrate(ahc, &period); 2579 ahc->msgout_index = 0; 2580 ahc->msgout_len = 0; 2581 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2582 ahc->msgout_index = 0; 2583 response = 1; 2584 } 2585 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2586 /* note asynch xfers and clear flag */ 2587 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2588 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2589 /*paused*/TRUE, /*done*/TRUE); 2590 #ifdef AHC_DEBUG_NEG 2591 printf("%s:%c:%d: refuses synchronous negotiation. " 2592 "Using asynchronous transfers\n", 2593 ahc_name(ahc), 2594 devinfo->channel, devinfo->target); 2595 #endif 2596 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2597 printf("%s:%c:%d: refuses tagged commands. Performing " 2598 "non-tagged I/O\n", ahc_name(ahc), 2599 devinfo->channel, devinfo->target); 2600 2601 ahc_set_tags(ahc, devinfo, FALSE); 2602 2603 /* 2604 * Resend the identify for this CCB as the target 2605 * may believe that the selection is invalid otherwise. 2606 */ 2607 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2608 & ~MSG_SIMPLE_Q_TAG); 2609 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2610 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2611 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2612 2613 /* 2614 * Requeue all tagged commands for this target 2615 * currently in our posession so they can be 2616 * converted to untagged commands. 2617 */ 2618 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2619 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2620 ROLE_INITIATOR, SCB_REQUEUE, 2621 SEARCH_COMPLETE); 2622 } else { 2623 /* 2624 * Otherwise, we ignore it. 2625 */ 2626 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2627 ahc_name(ahc), devinfo->channel, devinfo->target, 2628 last_msg); 2629 } 2630 return (response); 2631 } 2632 2633 static void 2634 ahc_clear_msg_state(struct ahc_softc *ahc) 2635 { 2636 ahc->msgout_len = 0; 2637 ahc->msgin_index = 0; 2638 ahc->msg_type = MSG_TYPE_NONE; 2639 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2640 } 2641 2642 static void 2643 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2644 { 2645 struct ahc_devinfo devinfo; 2646 u_int bus_phase; 2647 int end_session; 2648 2649 ahc_fetch_devinfo(ahc, &devinfo); 2650 end_session = FALSE; 2651 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2652 2653 reswitch: 2654 switch (ahc->msg_type) { 2655 case MSG_TYPE_INITIATOR_MSGOUT: 2656 { 2657 int lastbyte; 2658 int phasemis; 2659 int msgdone; 2660 2661 if (ahc->msgout_len == 0) 2662 panic("REQINIT interrupt with no active message"); 2663 2664 phasemis = bus_phase != P_MESGOUT; 2665 if (phasemis) { 2666 if (bus_phase == P_MESGIN) { 2667 /* 2668 * Change gears and see if 2669 * this messages is of interest to 2670 * us or should be passed back to 2671 * the sequencer. 2672 */ 2673 ahc_outb(ahc, CLRSINT1, CLRATNO); 2674 ahc->send_msg_perror = FALSE; 2675 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2676 ahc->msgin_index = 0; 2677 goto reswitch; 2678 } 2679 end_session = TRUE; 2680 break; 2681 } 2682 2683 if (ahc->send_msg_perror) { 2684 ahc_outb(ahc, CLRSINT1, CLRATNO); 2685 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2686 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2687 break; 2688 } 2689 2690 msgdone = ahc->msgout_index == ahc->msgout_len; 2691 if (msgdone) { 2692 /* 2693 * The target has requested a retry. 2694 * Re-assert ATN, reset our message index to 2695 * 0, and try again. 2696 */ 2697 ahc->msgout_index = 0; 2698 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2699 } 2700 2701 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2702 if (lastbyte) { 2703 /* Last byte is signified by dropping ATN */ 2704 ahc_outb(ahc, CLRSINT1, CLRATNO); 2705 } 2706 2707 /* 2708 * Clear our interrupt status and present 2709 * the next byte on the bus. 2710 */ 2711 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2712 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2713 break; 2714 } 2715 case MSG_TYPE_INITIATOR_MSGIN: 2716 { 2717 int phasemis; 2718 int message_done; 2719 2720 phasemis = bus_phase != P_MESGIN; 2721 2722 if (phasemis) { 2723 ahc->msgin_index = 0; 2724 if (bus_phase == P_MESGOUT 2725 && (ahc->send_msg_perror == TRUE 2726 || (ahc->msgout_len != 0 2727 && ahc->msgout_index == 0))) { 2728 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2729 goto reswitch; 2730 } 2731 end_session = TRUE; 2732 break; 2733 } 2734 2735 /* Pull the byte in without acking it */ 2736 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2737 2738 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2739 2740 if (message_done) { 2741 /* 2742 * Clear our incoming message buffer in case there 2743 * is another message following this one. 2744 */ 2745 ahc->msgin_index = 0; 2746 2747 /* 2748 * If this message illicited a response, 2749 * assert ATN so the target takes us to the 2750 * message out phase. 2751 */ 2752 if (ahc->msgout_len != 0) 2753 ahc_outb(ahc, SCSISIGO, 2754 ahc_inb(ahc, SCSISIGO) | ATNO); 2755 } else 2756 ahc->msgin_index++; 2757 2758 /* Ack the byte */ 2759 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2760 ahc_inb(ahc, SCSIDATL); 2761 break; 2762 } 2763 case MSG_TYPE_TARGET_MSGIN: 2764 { 2765 int msgdone; 2766 int msgout_request; 2767 2768 if (ahc->msgout_len == 0) 2769 panic("Target MSGIN with no active message"); 2770 2771 /* 2772 * If we interrupted a mesgout session, the initiator 2773 * will not know this until our first REQ. So, we 2774 * only honor mesgout requests after we've sent our 2775 * first byte. 2776 */ 2777 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2778 && ahc->msgout_index > 0) 2779 msgout_request = TRUE; 2780 else 2781 msgout_request = FALSE; 2782 2783 if (msgout_request) { 2784 2785 /* 2786 * Change gears and see if 2787 * this messages is of interest to 2788 * us or should be passed back to 2789 * the sequencer. 2790 */ 2791 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2792 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2793 ahc->msgin_index = 0; 2794 /* Dummy read to REQ for first byte */ 2795 ahc_inb(ahc, SCSIDATL); 2796 ahc_outb(ahc, SXFRCTL0, 2797 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2798 break; 2799 } 2800 2801 msgdone = ahc->msgout_index == ahc->msgout_len; 2802 if (msgdone) { 2803 ahc_outb(ahc, SXFRCTL0, 2804 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2805 end_session = TRUE; 2806 break; 2807 } 2808 2809 /* 2810 * Present the next byte on the bus. 2811 */ 2812 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2813 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2814 break; 2815 } 2816 case MSG_TYPE_TARGET_MSGOUT: 2817 { 2818 int lastbyte; 2819 int msgdone; 2820 2821 /* 2822 * The initiator signals that this is 2823 * the last byte by dropping ATN. 2824 */ 2825 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2826 2827 /* 2828 * Read the latched byte, but turn off SPIOEN first 2829 * so that we don't inadvertantly cause a REQ for the 2830 * next byte. 2831 */ 2832 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2833 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2834 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2835 if (msgdone == MSGLOOP_TERMINATED) { 2836 /* 2837 * The message is *really* done in that it caused 2838 * us to go to bus free. The sequencer has already 2839 * been reset at this point, so pull the ejection 2840 * handle. 2841 */ 2842 return; 2843 } 2844 2845 ahc->msgin_index++; 2846 2847 /* 2848 * XXX Read spec about initiator dropping ATN too soon 2849 * and use msgdone to detect it. 2850 */ 2851 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2852 ahc->msgin_index = 0; 2853 2854 /* 2855 * If this message illicited a response, transition 2856 * to the Message in phase and send it. 2857 */ 2858 if (ahc->msgout_len != 0) { 2859 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2860 ahc_outb(ahc, SXFRCTL0, 2861 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2862 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2863 ahc->msgin_index = 0; 2864 break; 2865 } 2866 } 2867 2868 if (lastbyte) 2869 end_session = TRUE; 2870 else { 2871 /* Ask for the next byte. */ 2872 ahc_outb(ahc, SXFRCTL0, 2873 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2874 } 2875 2876 break; 2877 } 2878 default: 2879 panic("Unknown REQINIT message type"); 2880 } 2881 2882 if (end_session) { 2883 ahc_clear_msg_state(ahc); 2884 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2885 } else 2886 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2887 } 2888 2889 /* 2890 * See if we sent a particular extended message to the target. 2891 * If "full" is true, the target saw the full message. 2892 * If "full" is false, the target saw at least the first 2893 * byte of the message. 2894 */ 2895 static int 2896 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2897 { 2898 int found; 2899 int index; 2900 2901 found = FALSE; 2902 index = 0; 2903 2904 while (index < ahc->msgout_len) { 2905 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2906 2907 /* Found a candidate */ 2908 if (ahc->msgout_buf[index+2] == msgtype) { 2909 u_int end_index; 2910 2911 end_index = index + 1 2912 + ahc->msgout_buf[index + 1]; 2913 if (full) { 2914 if (ahc->msgout_index > end_index) 2915 found = TRUE; 2916 } else if (ahc->msgout_index > index) 2917 found = TRUE; 2918 } 2919 break; 2920 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2921 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2922 2923 /* Skip tag type and tag id or residue param*/ 2924 index += 2; 2925 } else { 2926 /* Single byte message */ 2927 index++; 2928 } 2929 } 2930 return (found); 2931 } 2932 2933 static int 2934 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2935 struct ahc_devinfo *devinfo) 2936 { 2937 struct ahc_initiator_tinfo *tinfo; 2938 struct tmode_tstate *tstate; 2939 int reject; 2940 int done; 2941 int response; 2942 u_int targ_scsirate; 2943 2944 done = MSGLOOP_IN_PROG; 2945 response = FALSE; 2946 reject = FALSE; 2947 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2948 devinfo->target, &tstate); 2949 targ_scsirate = tinfo->scsirate; 2950 2951 /* 2952 * Parse as much of the message as is availible, 2953 * rejecting it if we don't support it. When 2954 * the entire message is availible and has been 2955 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2956 * that we have parsed an entire message. 2957 * 2958 * In the case of extended messages, we accept the length 2959 * byte outright and perform more checking once we know the 2960 * extended message type. 2961 */ 2962 switch (ahc->msgin_buf[0]) { 2963 case MSG_MESSAGE_REJECT: 2964 response = ahc_handle_msg_reject(ahc, devinfo); 2965 /* FALLTHROUGH */ 2966 case MSG_NOOP: 2967 done = MSGLOOP_MSGCOMPLETE; 2968 break; 2969 case MSG_IGN_WIDE_RESIDUE: 2970 { 2971 /* Wait for the whole message */ 2972 if (ahc->msgin_index >= 1) { 2973 if (ahc->msgin_buf[1] != 1 2974 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2975 reject = TRUE; 2976 done = MSGLOOP_MSGCOMPLETE; 2977 } else 2978 ahc_handle_ign_wide_residue(ahc, devinfo); 2979 } 2980 break; 2981 } 2982 case MSG_EXTENDED: 2983 { 2984 /* Wait for enough of the message to begin validation */ 2985 if (ahc->msgin_index < 2) 2986 break; 2987 switch (ahc->msgin_buf[2]) { 2988 case MSG_EXT_SDTR: 2989 { 2990 struct ahc_syncrate *syncrate; 2991 u_int period; 2992 u_int offset; 2993 u_int saved_offset; 2994 2995 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2996 reject = TRUE; 2997 break; 2998 } 2999 3000 /* 3001 * Wait until we have both args before validating 3002 * and acting on this message. 3003 * 3004 * Add one to MSG_EXT_SDTR_LEN to account for 3005 * the extended message preamble. 3006 */ 3007 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3008 break; 3009 3010 period = ahc->msgin_buf[3]; 3011 saved_offset = offset = ahc->msgin_buf[4]; 3012 syncrate = ahc_devlimited_syncrate(ahc, &period); 3013 ahc_validate_offset(ahc, syncrate, &offset, 3014 targ_scsirate & WIDEXFER); 3015 ahc_set_syncrate(ahc, devinfo, 3016 syncrate, period, offset, 3017 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3018 /*paused*/TRUE, /*done*/TRUE); 3019 3020 /* 3021 * See if we initiated Sync Negotiation 3022 * and didn't have to fall down to async 3023 * transfers. 3024 */ 3025 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3026 /* We started it */ 3027 if (saved_offset != offset) { 3028 /* Went too low - force async */ 3029 reject = TRUE; 3030 } 3031 } else { 3032 /* 3033 * Send our own SDTR in reply 3034 */ 3035 ahc->msgout_index = 0; 3036 ahc->msgout_len = 0; 3037 ahc_construct_sdtr(ahc, period, offset); 3038 ahc->msgout_index = 0; 3039 response = TRUE; 3040 } 3041 done = MSGLOOP_MSGCOMPLETE; 3042 break; 3043 } 3044 case MSG_EXT_WDTR: 3045 { 3046 u_int bus_width; 3047 u_int sending_reply; 3048 3049 sending_reply = FALSE; 3050 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3051 reject = TRUE; 3052 break; 3053 } 3054 3055 /* 3056 * Wait until we have our arg before validating 3057 * and acting on this message. 3058 * 3059 * Add one to MSG_EXT_WDTR_LEN to account for 3060 * the extended message preamble. 3061 */ 3062 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3063 break; 3064 3065 bus_width = ahc->msgin_buf[3]; 3066 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3067 /* 3068 * Don't send a WDTR back to the 3069 * target, since we asked first. 3070 */ 3071 switch (bus_width){ 3072 default: 3073 /* 3074 * How can we do anything greater 3075 * than 16bit transfers on a 16bit 3076 * bus? 3077 */ 3078 reject = TRUE; 3079 printf("%s: target %d requested %dBit " 3080 "transfers. Rejecting...\n", 3081 ahc_name(ahc), devinfo->target, 3082 8 * (0x01 << bus_width)); 3083 /* FALLTHROUGH */ 3084 case MSG_EXT_WDTR_BUS_8_BIT: 3085 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3086 break; 3087 case MSG_EXT_WDTR_BUS_16_BIT: 3088 break; 3089 } 3090 } else { 3091 /* 3092 * Send our own WDTR in reply 3093 */ 3094 switch (bus_width) { 3095 default: 3096 if (ahc->features & AHC_WIDE) { 3097 /* Respond Wide */ 3098 bus_width = 3099 MSG_EXT_WDTR_BUS_16_BIT; 3100 break; 3101 } 3102 /* FALLTHROUGH */ 3103 case MSG_EXT_WDTR_BUS_8_BIT: 3104 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3105 break; 3106 } 3107 ahc->msgout_index = 0; 3108 ahc->msgout_len = 0; 3109 ahc_construct_wdtr(ahc, bus_width); 3110 ahc->msgout_index = 0; 3111 response = TRUE; 3112 sending_reply = TRUE; 3113 } 3114 ahc_set_width(ahc, devinfo, bus_width, 3115 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3116 /*paused*/TRUE, /*done*/TRUE); 3117 3118 /* After a wide message, we are async */ 3119 ahc_set_syncrate(ahc, devinfo, 3120 /*syncrate*/NULL, /*period*/0, 3121 /*offset*/0, AHC_TRANS_ACTIVE, 3122 /*paused*/TRUE, /*done*/FALSE); 3123 if (sending_reply == FALSE && reject == FALSE) { 3124 3125 if (tinfo->goal.period) { 3126 struct ahc_syncrate *rate; 3127 u_int period; 3128 u_int offset; 3129 3130 /* Start the sync negotiation */ 3131 period = tinfo->goal.period; 3132 rate = ahc_devlimited_syncrate(ahc, 3133 &period); 3134 offset = tinfo->goal.offset; 3135 ahc_validate_offset(ahc, rate, &offset, 3136 tinfo->current.width); 3137 ahc->msgout_index = 0; 3138 ahc->msgout_len = 0; 3139 ahc_construct_sdtr(ahc, period, offset); 3140 ahc->msgout_index = 0; 3141 response = TRUE; 3142 } 3143 } 3144 done = MSGLOOP_MSGCOMPLETE; 3145 break; 3146 } 3147 default: 3148 /* Unknown extended message. Reject it. */ 3149 reject = TRUE; 3150 break; 3151 } 3152 break; 3153 } 3154 case MSG_BUS_DEV_RESET: 3155 ahc_handle_devreset(ahc, devinfo, 3156 XS_RESET, "Bus Device Reset Received", 3157 /*verbose_level*/0); 3158 restart_sequencer(ahc); 3159 done = MSGLOOP_TERMINATED; 3160 break; 3161 case MSG_ABORT_TAG: 3162 case MSG_ABORT: 3163 case MSG_CLEAR_QUEUE: 3164 /* Target mode messages */ 3165 if (devinfo->role != ROLE_TARGET) { 3166 reject = TRUE; 3167 break; 3168 } 3169 #if AHC_TARGET_MODE 3170 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3171 devinfo->lun, 3172 ahc->msgin_buf[0] == MSG_ABORT_TAG 3173 ? SCB_LIST_NULL 3174 : ahc_inb(ahc, INITIATOR_TAG), 3175 ROLE_TARGET, XS_DRIVER_STUFFUP); 3176 3177 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3178 if (tstate != NULL) { 3179 struct tmode_lstate* lstate; 3180 3181 lstate = tstate->enabled_luns[devinfo->lun]; 3182 if (lstate != NULL) { 3183 ahc_queue_lstate_event(ahc, lstate, 3184 devinfo->our_scsiid, 3185 ahc->msgin_buf[0], 3186 /*arg*/0); 3187 ahc_send_lstate_events(ahc, lstate); 3188 } 3189 } 3190 done = MSGLOOP_MSGCOMPLETE; 3191 #else 3192 panic("ahc: got target mode message"); 3193 #endif 3194 break; 3195 case MSG_TERM_IO_PROC: 3196 default: 3197 reject = TRUE; 3198 break; 3199 } 3200 3201 if (reject) { 3202 /* 3203 * Setup to reject the message. 3204 */ 3205 ahc->msgout_index = 0; 3206 ahc->msgout_len = 1; 3207 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3208 done = MSGLOOP_MSGCOMPLETE; 3209 response = TRUE; 3210 } 3211 3212 if (done != MSGLOOP_IN_PROG && !response) 3213 /* Clear the outgoing message buffer */ 3214 ahc->msgout_len = 0; 3215 3216 return (done); 3217 } 3218 3219 static void 3220 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3221 { 3222 u_int scb_index; 3223 struct scb *scb; 3224 3225 scb_index = ahc_inb(ahc, SCB_TAG); 3226 scb = &ahc->scb_data->scbarray[scb_index]; 3227 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3228 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3229 /* 3230 * Ignore the message if we haven't 3231 * seen an appropriate data phase yet. 3232 */ 3233 } else { 3234 /* 3235 * If the residual occurred on the last 3236 * transfer and the transfer request was 3237 * expected to end on an odd count, do 3238 * nothing. Otherwise, subtract a byte 3239 * and update the residual count accordingly. 3240 */ 3241 u_int resid_sgcnt; 3242 3243 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3244 if (resid_sgcnt == 0 3245 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3246 /* 3247 * If the residual occurred on the last 3248 * transfer and the transfer request was 3249 * expected to end on an odd count, do 3250 * nothing. 3251 */ 3252 } else { 3253 u_int data_cnt; 3254 u_int32_t data_addr; 3255 u_int sg_index; 3256 3257 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3258 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3259 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3260 3261 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3262 | (ahc_inb(ahc, SHADDR + 2) << 16) 3263 | (ahc_inb(ahc, SHADDR + 1) << 8) 3264 | (ahc_inb(ahc, SHADDR)); 3265 3266 data_cnt += 1; 3267 data_addr -= 1; 3268 3269 sg_index = scb->sg_count - resid_sgcnt; 3270 3271 if (sg_index != 0 3272 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3273 u_int32_t sg_addr; 3274 3275 sg_index--; 3276 data_cnt = 1; 3277 data_addr = le32toh(scb->sg_list[sg_index].addr) 3278 + le32toh(scb->sg_list[sg_index].len) 3279 - 1; 3280 3281 /* 3282 * The physical address base points to the 3283 * second entry as it is always used for 3284 * calculating the "next S/G pointer". 3285 */ 3286 sg_addr = scb->sg_list_phys 3287 + (sg_index* sizeof(*scb->sg_list)); 3288 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3289 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3290 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3291 ahc_outb(ahc, SG_NEXT, sg_addr); 3292 } 3293 3294 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3295 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3296 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3297 3298 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3299 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3300 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3301 ahc_outb(ahc, SHADDR, data_addr); 3302 } 3303 } 3304 } 3305 3306 static void 3307 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3308 int status, char *message, 3309 int verbose_level) 3310 { 3311 int found; 3312 3313 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3314 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3315 status); 3316 3317 /* 3318 * Go back to async/narrow transfers and renegotiate. 3319 * ahc_set_width and ahc_set_syncrate can cope with NULL 3320 * paths. 3321 */ 3322 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3323 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3324 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3325 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3326 /*paused*/TRUE, /*done*/FALSE); 3327 3328 if (message != NULL && (verbose_level <= 0)) 3329 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3330 message, devinfo->channel, devinfo->target, found); 3331 } 3332 3333 /* 3334 * We have an scb which has been processed by the 3335 * adaptor, now we look to see how the operation 3336 * went. 3337 */ 3338 static void 3339 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3340 { 3341 struct scsipi_xfer *xs; 3342 struct scsipi_link *sc_link; 3343 int requeue = 0; 3344 int target; 3345 3346 3347 xs = scb->xs; 3348 sc_link = xs->sc_link; 3349 LIST_REMOVE(scb, plinks); 3350 3351 callout_stop(&scb->xs->xs_callout); 3352 3353 #ifdef AHC_DEBUG 3354 if (ahc_debug & AHC_SHOWCMDS) { 3355 scsi_print_addr(sc_link); 3356 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3357 scb->hscb->tag); 3358 } 3359 #endif 3360 3361 target = sc_link->scsipi_scsi.target; 3362 3363 if (xs->datalen) { 3364 int op; 3365 3366 if (xs->xs_control & XS_CTL_DATA_IN) 3367 op = BUS_DMASYNC_POSTREAD; 3368 else 3369 op = BUS_DMASYNC_POSTWRITE; 3370 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3371 scb->dmamap->dm_mapsize, op); 3372 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3373 } 3374 3375 /* 3376 * Unbusy this target/channel/lun. 3377 * XXX if we are holding two commands per lun, 3378 * send the next command. 3379 */ 3380 if (!(scb->hscb->control & TAG_ENB)) 3381 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3382 3383 /* 3384 * If the recovery SCB completes, we have to be 3385 * out of our timeout. 3386 */ 3387 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3388 3389 struct scb *scbp; 3390 3391 /* 3392 * We were able to complete the command successfully, 3393 * so reinstate the timeouts for all other pending 3394 * commands. 3395 */ 3396 scbp = ahc->pending_ccbs.lh_first; 3397 while (scbp != NULL) { 3398 struct scsipi_xfer *txs = scbp->xs; 3399 3400 if (!(txs->xs_control & XS_CTL_POLL)) { 3401 callout_reset(&scbp->xs->xs_callout, 3402 (scbp->xs->timeout * hz) / 1000, 3403 ahc_timeout, scbp); 3404 } 3405 scbp = LIST_NEXT(scbp, plinks); 3406 } 3407 3408 /* 3409 * Ensure that we didn't put a second instance of this 3410 * SCB into the QINFIFO. 3411 */ 3412 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3413 SCB_LUN(scb), scb->hscb->tag, 3414 ROLE_INITIATOR, /*status*/0, 3415 SEARCH_REMOVE); 3416 if (xs->error != XS_NOERROR) 3417 ahcsetccbstatus(xs, XS_TIMEOUT); 3418 scsi_print_addr(xs->sc_link); 3419 printf("no longer in timeout, status = %x\n", xs->status); 3420 } 3421 3422 if (xs->error != XS_NOERROR) { 3423 /* Don't clobber any existing error state */ 3424 } else if ((scb->flags & SCB_SENSE) != 0) { 3425 /* 3426 * We performed autosense retrieval. 3427 * 3428 * bzero the sense data before having 3429 * the drive fill it. The SCSI spec mandates 3430 * that any untransfered data should be 3431 * assumed to be zero. Complete the 'bounce' 3432 * of sense information through buffers accessible 3433 * via bus-space by copying it into the clients 3434 * csio. 3435 */ 3436 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3437 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3438 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3439 xs->error = XS_SENSE; 3440 } 3441 if (scb->flags & SCB_FREEZE_QUEUE) { 3442 ahc->devqueue_blocked[target]--; 3443 scb->flags &= ~SCB_FREEZE_QUEUE; 3444 } 3445 3446 requeue = scb->flags & SCB_REQUEUE; 3447 ahcfreescb(ahc, scb); 3448 3449 if (requeue) { 3450 /* 3451 * Re-insert at the front of the private queue to 3452 * preserve order. 3453 */ 3454 int s; 3455 3456 if (xs->xs_status & XS_STS_DEBUG) { 3457 scsi_print_addr(xs->sc_link); 3458 printf("putting SCB that caused queue full back" 3459 " in queue\n"); 3460 } 3461 3462 s = splbio(); 3463 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3464 splx(s); 3465 } else { 3466 if (xs->xs_status & XS_STS_DEBUG) { 3467 xs->xs_status &= ~XS_STS_DEBUG; 3468 scsi_print_addr(xs->sc_link); 3469 printf("completed SCB that caused queue full\n"); 3470 } 3471 xs->xs_status |= XS_STS_DONE; 3472 ahc_check_tags(ahc, xs); 3473 scsipi_done(xs); 3474 } 3475 3476 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3477 ahc_action(xs); 3478 } 3479 3480 /* 3481 * Determine the number of SCBs available on the controller 3482 */ 3483 int 3484 ahc_probe_scbs(struct ahc_softc *ahc) { 3485 int i; 3486 3487 for (i = 0; i < AHC_SCB_MAX; i++) { 3488 ahc_outb(ahc, SCBPTR, i); 3489 ahc_outb(ahc, SCB_CONTROL, i); 3490 if (ahc_inb(ahc, SCB_CONTROL) != i) 3491 break; 3492 ahc_outb(ahc, SCBPTR, 0); 3493 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3494 break; 3495 } 3496 return (i); 3497 } 3498 3499 /* 3500 * Start the board, ready for normal operation 3501 */ 3502 int 3503 ahc_init(struct ahc_softc *ahc) 3504 { 3505 int max_targ = 15; 3506 int i; 3507 int term; 3508 u_int scsi_conf; 3509 u_int scsiseq_template; 3510 u_int ultraenb; 3511 u_int discenable; 3512 u_int tagenable; 3513 size_t driver_data_size; 3514 u_int32_t physaddr; 3515 3516 #ifdef AHC_PRINT_SRAM 3517 printf("Scratch Ram:"); 3518 for (i = 0x20; i < 0x5f; i++) { 3519 if (((i % 8) == 0) && (i != 0)) { 3520 printf ("\n "); 3521 } 3522 printf (" 0x%x", ahc_inb(ahc, i)); 3523 } 3524 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3525 for (i = 0x70; i < 0x7f; i++) { 3526 if (((i % 8) == 0) && (i != 0)) { 3527 printf ("\n "); 3528 } 3529 printf (" 0x%x", ahc_inb(ahc, i)); 3530 } 3531 } 3532 printf ("\n"); 3533 #endif 3534 3535 /* 3536 * Assume we have a board at this stage and it has been reset. 3537 */ 3538 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3539 ahc->our_id = ahc->our_id_b = 7; 3540 3541 /* 3542 * Default to allowing initiator operations. 3543 */ 3544 ahc->flags |= AHC_INITIATORMODE; 3545 3546 /* 3547 * DMA tag for our command fifos and other data in system memory 3548 * the card's sequencer must be able to access. For initiator 3549 * roles, we need to allocate space for the qinfifo, qoutfifo, 3550 * and untagged_scb arrays each of which are composed of 256 3551 * 1 byte elements. When providing for the target mode role, 3552 * we additionally must provide space for the incoming target 3553 * command fifo. 3554 */ 3555 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3556 3557 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3558 ahc->sc_dmaflags, 3559 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3560 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3561 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3562 return (ENOMEM); 3563 3564 ahc->init_level++; 3565 3566 /* Allocate SCB data now that parent_dmat is initialized */ 3567 if (ahc->scb_data->maxhscbs == 0) 3568 if (ahcinitscbdata(ahc) != 0) 3569 return (ENOMEM); 3570 3571 ahc->qinfifo = &ahc->qoutfifo[256]; 3572 ahc->untagged_scbs = &ahc->qinfifo[256]; 3573 /* There are no untagged SCBs active yet. */ 3574 for (i = 0; i < 256; i++) 3575 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3576 3577 /* All of our queues are empty */ 3578 for (i = 0; i < 256; i++) 3579 ahc->qoutfifo[i] = SCB_LIST_NULL; 3580 3581 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3582 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3583 3584 /* 3585 * Allocate a tstate to house information for our 3586 * initiator presence on the bus as well as the user 3587 * data for any target mode initiator. 3588 */ 3589 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3590 printf("%s: unable to allocate tmode_tstate. " 3591 "Failing attach\n", ahc_name(ahc)); 3592 return (-1); 3593 } 3594 3595 if ((ahc->features & AHC_TWIN) != 0) { 3596 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3597 printf("%s: unable to allocate tmode_tstate. " 3598 "Failing attach\n", ahc_name(ahc)); 3599 return (-1); 3600 } 3601 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3602 ahc->our_id, ahc->our_id_b, 3603 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3604 } else { 3605 if ((ahc->features & AHC_WIDE) != 0) { 3606 printf("Wide "); 3607 } else { 3608 printf("Single "); 3609 } 3610 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3611 } 3612 3613 ahc_outb(ahc, SEQ_FLAGS, 0); 3614 3615 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3616 ahc->flags |= AHC_PAGESCBS; 3617 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3618 } else { 3619 ahc->flags &= ~AHC_PAGESCBS; 3620 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3621 } 3622 3623 #ifdef AHC_DEBUG 3624 if (ahc_debug & AHC_SHOWMISC) { 3625 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3626 "ahc_dma %d bytes\n", 3627 ahc_name(ahc), 3628 sizeof(struct hardware_scb), 3629 sizeof(struct scb), 3630 sizeof(struct ahc_dma_seg)); 3631 } 3632 #endif /* AHC_DEBUG */ 3633 3634 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3635 if (ahc->features & AHC_TWIN) { 3636 3637 /* 3638 * The device is gated to channel B after a chip reset, 3639 * so set those values first 3640 */ 3641 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3642 if ((ahc->features & AHC_ULTRA2) != 0) 3643 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3644 else 3645 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3646 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3647 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3648 |term|ENSTIMER|ACTNEGEN); 3649 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3650 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3651 3652 if ((scsi_conf & RESET_SCSI) != 0 3653 && (ahc->flags & AHC_INITIATORMODE) != 0) 3654 ahc->flags |= AHC_RESET_BUS_B; 3655 3656 /* Select Channel A */ 3657 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3658 } 3659 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3660 if ((ahc->features & AHC_ULTRA2) != 0) 3661 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3662 else 3663 ahc_outb(ahc, SCSIID, ahc->our_id); 3664 scsi_conf = ahc_inb(ahc, SCSICONF); 3665 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3666 |term 3667 |ENSTIMER|ACTNEGEN); 3668 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3669 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3670 3671 if ((scsi_conf & RESET_SCSI) != 0 3672 && (ahc->flags & AHC_INITIATORMODE) != 0) 3673 ahc->flags |= AHC_RESET_BUS_A; 3674 3675 /* 3676 * Look at the information that board initialization or 3677 * the board bios has left us. 3678 */ 3679 ultraenb = 0; 3680 tagenable = ALL_TARGETS_MASK; 3681 3682 /* Grab the disconnection disable table and invert it for our needs */ 3683 if (ahc->flags & AHC_USEDEFAULTS) { 3684 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3685 "device parameters\n", ahc_name(ahc)); 3686 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3687 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3688 discenable = ALL_TARGETS_MASK; 3689 if ((ahc->features & AHC_ULTRA) != 0) 3690 ultraenb = ALL_TARGETS_MASK; 3691 } else { 3692 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3693 | ahc_inb(ahc, DISC_DSB)); 3694 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3695 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3696 | ahc_inb(ahc, ULTRA_ENB); 3697 } 3698 3699 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3700 max_targ = 7; 3701 3702 for (i = 0; i <= max_targ; i++) { 3703 struct ahc_initiator_tinfo *tinfo; 3704 struct tmode_tstate *tstate; 3705 u_int our_id; 3706 u_int target_id; 3707 char channel; 3708 3709 channel = 'A'; 3710 our_id = ahc->our_id; 3711 target_id = i; 3712 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3713 channel = 'B'; 3714 our_id = ahc->our_id_b; 3715 target_id = i % 8; 3716 } 3717 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3718 target_id, &tstate); 3719 /* Default to async narrow across the board */ 3720 bzero(tinfo, sizeof(*tinfo)); 3721 if (ahc->flags & AHC_USEDEFAULTS) { 3722 if ((ahc->features & AHC_WIDE) != 0) 3723 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3724 3725 /* 3726 * These will be truncated when we determine the 3727 * connection type we have with the target. 3728 */ 3729 tinfo->user.period = ahc_syncrates->period; 3730 tinfo->user.offset = ~0; 3731 } else { 3732 u_int scsirate; 3733 u_int16_t mask; 3734 3735 /* Take the settings leftover in scratch RAM. */ 3736 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3737 mask = (0x01 << i); 3738 if ((ahc->features & AHC_ULTRA2) != 0) { 3739 u_int offset; 3740 u_int maxsync; 3741 3742 if ((scsirate & SOFS) == 0x0F) { 3743 /* 3744 * Haven't negotiated yet, 3745 * so the format is different. 3746 */ 3747 scsirate = (scsirate & SXFR) >> 4 3748 | (ultraenb & mask) 3749 ? 0x08 : 0x0 3750 | (scsirate & WIDEXFER); 3751 offset = MAX_OFFSET_ULTRA2; 3752 } else 3753 offset = ahc_inb(ahc, TARG_OFFSET + i); 3754 maxsync = AHC_SYNCRATE_ULTRA2; 3755 if ((ahc->features & AHC_DT) != 0) 3756 maxsync = AHC_SYNCRATE_DT; 3757 tinfo->user.period = 3758 ahc_find_period(ahc, scsirate, maxsync); 3759 if (offset == 0) 3760 tinfo->user.period = 0; 3761 else 3762 tinfo->user.offset = ~0; 3763 } else if ((scsirate & SOFS) != 0) { 3764 tinfo->user.period = 3765 ahc_find_period(ahc, scsirate, 3766 (ultraenb & mask) 3767 ? AHC_SYNCRATE_ULTRA 3768 : AHC_SYNCRATE_FAST); 3769 if (tinfo->user.period != 0) 3770 tinfo->user.offset = ~0; 3771 } 3772 if ((scsirate & WIDEXFER) != 0 3773 && (ahc->features & AHC_WIDE) != 0) 3774 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3775 } 3776 tinfo->goal = tinfo->user; /* force negotiation */ 3777 tstate->ultraenb = ultraenb; 3778 tstate->discenable = discenable; 3779 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3780 tstate->tagdisable = 0; 3781 } 3782 ahc->user_discenable = discenable; 3783 ahc->user_tagenable = tagenable; 3784 3785 /* 3786 * Tell the sequencer where it can find our arrays in memory. 3787 */ 3788 physaddr = ahc->scb_data->hscb_busaddr; 3789 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3790 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3791 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3792 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3793 3794 physaddr = ahc->shared_data_busaddr; 3795 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3796 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3797 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3798 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3799 3800 /* Target mode incomding command fifo */ 3801 physaddr += 3 * 256 * sizeof(u_int8_t); 3802 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3803 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3804 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3805 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3806 3807 /* 3808 * Initialize the group code to command length table. 3809 * This overrides the values in TARG_SCSIRATE, so only 3810 * setup the table after we have processed that information. 3811 */ 3812 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3813 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3814 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3815 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3816 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3817 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3818 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3819 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3820 3821 /* Tell the sequencer of our initial queue positions */ 3822 ahc_outb(ahc, KERNEL_QINPOS, 0); 3823 ahc_outb(ahc, QINPOS, 0); 3824 ahc_outb(ahc, QOUTPOS, 0); 3825 3826 #ifdef AHC_DEBUG 3827 if (ahc_debug & AHC_SHOWMISC) 3828 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3829 discenable, ultraenb); 3830 #endif 3831 3832 /* Don't have any special messages to send to targets */ 3833 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3834 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3835 3836 /* 3837 * Use the built in queue management registers 3838 * if they are available. 3839 */ 3840 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3841 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3842 ahc_outb(ahc, SDSCB_QOFF, 0); 3843 ahc_outb(ahc, SNSCB_QOFF, 0); 3844 ahc_outb(ahc, HNSCB_QOFF, 0); 3845 } 3846 3847 3848 /* We don't have any waiting selections */ 3849 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3850 3851 /* Our disconnection list is empty too */ 3852 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3853 3854 /* Message out buffer starts empty */ 3855 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3856 3857 /* 3858 * Setup the allowed SCSI Sequences based on operational mode. 3859 * If we are a target, we'll enalbe select in operations once 3860 * we've had a lun enabled. 3861 */ 3862 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3863 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3864 scsiseq_template |= ENRSELI; 3865 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3866 3867 /* 3868 * Load the Sequencer program and Enable the adapter 3869 * in "fast" mode. 3870 */ 3871 #ifdef AHC_DEBUG 3872 printf("%s: Downloading Sequencer Program...", 3873 ahc_name(ahc)); 3874 #endif 3875 3876 ahc_loadseq(ahc); 3877 3878 /* We have to wait until after any system dumps... */ 3879 shutdownhook_establish(ahc_shutdown, ahc); 3880 3881 return (0); 3882 } 3883 3884 static int 3885 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3886 struct proc *p) 3887 { 3888 struct ahc_softc *ahc = sc_link->adapter_softc; 3889 char channel; 3890 int s, ret = ENOTTY; 3891 3892 switch (cmd) { 3893 case SCBUSIORESET: 3894 channel = SIM_CHANNEL(ahc, sc_link); 3895 s = splbio(); 3896 ahc_reset_channel(ahc, channel, TRUE); 3897 splx(s); 3898 ret = 0; 3899 break; 3900 default: 3901 } 3902 3903 return ret; 3904 } 3905 3906 3907 /* 3908 * XXX fvdl the busy_tcl checks and settings should only be done 3909 * for the non-tagged queueing case, but we don't do tagged queueing 3910 * yet, so.. 3911 */ 3912 static int32_t 3913 ahc_action(struct scsipi_xfer *xs) 3914 { 3915 struct scsipi_xfer *first_xs, *next_xs = NULL; 3916 struct ahc_softc *ahc; 3917 struct scb *scb; 3918 struct hardware_scb *hscb; 3919 struct ahc_initiator_tinfo *tinfo; 3920 struct tmode_tstate *tstate; 3921 u_int target_id; 3922 u_int our_id; 3923 int s, tcl; 3924 u_int16_t mask; 3925 char channel; 3926 int dontqueue = 0, fromqueue = 0; 3927 3928 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3929 3930 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3931 3932 /* must protect the queue */ 3933 s = splbio(); 3934 3935 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3936 /* 3937 * Called from ahc_done. Calling with the first entry in 3938 * the queue is really just a way of seeing where we're 3939 * called from. Now, find the first eligible SCB to send, 3940 * e.g. one which will be accepted immediately. 3941 */ 3942 3943 if (ahc->queue_blocked) { 3944 splx(s); 3945 return (TRY_AGAIN_LATER); 3946 } 3947 3948 xs = ahc_first_xs(ahc); 3949 if (xs == NULL) { 3950 splx(s); 3951 return (TRY_AGAIN_LATER); 3952 } 3953 3954 next_xs = TAILQ_NEXT(xs, adapter_q); 3955 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3956 fromqueue = 1; 3957 goto get_scb; 3958 } 3959 3960 /* 3961 * If no new requests are accepted, just insert into the 3962 * private queue to wait for our turn. 3963 */ 3964 tcl = XS_TCL(ahc, xs); 3965 3966 if (ahc->queue_blocked || 3967 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3968 (!ahc_istagged_device(ahc, xs, 0) && 3969 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3970 if (dontqueue) { 3971 splx(s); 3972 xs->error = XS_DRIVER_STUFFUP; 3973 return TRY_AGAIN_LATER; 3974 } 3975 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3976 splx(s); 3977 return SUCCESSFULLY_QUEUED; 3978 } 3979 3980 first_xs = ahc_first_xs(ahc); 3981 3982 /* determine safety of software queueing */ 3983 dontqueue = xs->xs_control & XS_CTL_POLL; 3984 3985 /* 3986 * Handle situations where there's already entries in the 3987 * queue. 3988 */ 3989 if (first_xs != NULL) { 3990 /* 3991 * If we can't queue, we have to abort, since 3992 * we have to preserve order. 3993 */ 3994 if (dontqueue) { 3995 splx(s); 3996 xs->error = XS_DRIVER_STUFFUP; 3997 return (TRY_AGAIN_LATER); 3998 } 3999 4000 /* 4001 * Swap with the first queue entry. 4002 */ 4003 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4004 xs = first_xs; 4005 next_xs = TAILQ_NEXT(xs, adapter_q); 4006 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 4007 fromqueue = 1; 4008 4009 } 4010 4011 get_scb: 4012 4013 target_id = xs->sc_link->scsipi_scsi.target; 4014 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 4015 4016 /* 4017 * get an scb to use. 4018 */ 4019 if ((scb = ahcgetscb(ahc)) == NULL) { 4020 4021 if (dontqueue) { 4022 splx(s); 4023 xs->error = XS_DRIVER_STUFFUP; 4024 return (TRY_AGAIN_LATER); 4025 } 4026 4027 /* 4028 * If we were pulled off the queue, put ourselves 4029 * back to where we came from, otherwise tack ourselves 4030 * onto the end. 4031 */ 4032 if (fromqueue && next_xs != NULL) 4033 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 4034 else 4035 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4036 4037 splx(s); 4038 return (SUCCESSFULLY_QUEUED); 4039 } 4040 4041 tcl = XS_TCL(ahc, xs); 4042 4043 #ifdef DIAGNOSTIC 4044 if (!ahc_istagged_device(ahc, xs, 0) && 4045 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4046 panic("ahc: queuing for busy target"); 4047 #endif 4048 4049 scb->xs = xs; 4050 hscb = scb->hscb; 4051 hscb->tcl = tcl; 4052 4053 if (ahc_istagged_device(ahc, xs, 0)) 4054 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4055 else 4056 ahc_busy_tcl(ahc, scb); 4057 4058 splx(s); 4059 4060 channel = SIM_CHANNEL(ahc, xs->sc_link); 4061 if (ahc->inited_channels[channel - 'A'] == 0) { 4062 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4063 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4064 s = splbio(); 4065 ahc_reset_channel(ahc, channel, TRUE); 4066 splx(s); 4067 } 4068 ahc->inited_channels[channel - 'A'] = 1; 4069 } 4070 4071 /* 4072 * Put all the arguments for the xfer in the scb 4073 */ 4074 4075 mask = SCB_TARGET_MASK(scb); 4076 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4077 target_id, &tstate); 4078 if (ahc->inited_targets[target_id] == 0) { 4079 struct ahc_devinfo devinfo; 4080 4081 s = splbio(); 4082 ahc_compile_devinfo(&devinfo, our_id, target_id, 4083 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4084 ROLE_INITIATOR); 4085 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4086 FALSE); 4087 ahc->inited_targets[target_id] = 1; 4088 splx(s); 4089 } 4090 4091 hscb->scsirate = tinfo->scsirate; 4092 hscb->scsioffset = tinfo->current.offset; 4093 if ((tstate->ultraenb & mask) != 0) 4094 hscb->control |= ULTRAENB; 4095 4096 if ((tstate->discenable & mask) != 0) 4097 hscb->control |= DISCENB; 4098 4099 if (xs->xs_status & XS_STS_DEBUG) { 4100 scsi_print_addr(xs->sc_link); 4101 printf("redoing command that caused queue full\n"); 4102 } 4103 4104 if (xs->xs_control & XS_CTL_RESET) { 4105 hscb->cmdpointer = 0; 4106 scb->flags |= SCB_DEVICE_RESET; 4107 hscb->control |= MK_MESSAGE; 4108 return ahc_execute_scb(scb, NULL, 0); 4109 } 4110 4111 return ahc_setup_data(ahc, xs, scb); 4112 } 4113 4114 static int 4115 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4116 { 4117 struct scb *scb; 4118 struct scsipi_xfer *xs; 4119 struct ahc_softc *ahc; 4120 int s; 4121 4122 scb = (struct scb *)arg; 4123 xs = scb->xs; 4124 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4125 4126 4127 if (nsegments != 0) { 4128 struct ahc_dma_seg *sg; 4129 bus_dma_segment_t *end_seg; 4130 int op; 4131 4132 end_seg = dm_segs + nsegments; 4133 4134 /* Copy the first SG into the data pointer area */ 4135 scb->hscb->data = dm_segs->ds_addr; 4136 scb->hscb->datalen = dm_segs->ds_len; 4137 4138 /* Copy the segments into our SG list */ 4139 sg = scb->sg_list; 4140 while (dm_segs < end_seg) { 4141 sg->addr = dm_segs->ds_addr; 4142 sg->len = dm_segs->ds_len; 4143 ahc_swap_sg(sg); 4144 sg++; 4145 dm_segs++; 4146 } 4147 4148 /* Note where to find the SG entries in bus space */ 4149 scb->hscb->SG_pointer = scb->sg_list_phys; 4150 4151 if (xs->xs_control & XS_CTL_DATA_IN) 4152 op = BUS_DMASYNC_PREREAD; 4153 else 4154 op = BUS_DMASYNC_PREWRITE; 4155 4156 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4157 scb->dmamap->dm_mapsize, op); 4158 4159 } else { 4160 scb->hscb->SG_pointer = 0; 4161 scb->hscb->data = 0; 4162 scb->hscb->datalen = 0; 4163 } 4164 4165 scb->sg_count = scb->hscb->SG_count = nsegments; 4166 4167 s = splbio(); 4168 4169 /* 4170 * Last time we need to check if this SCB needs to 4171 * be aborted. 4172 */ 4173 if (xs->xs_status & XS_STS_DONE) { 4174 if (!ahc_istagged_device(ahc, xs, 0)) 4175 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4176 if (nsegments != 0) 4177 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4178 ahcfreescb(ahc, scb); 4179 splx(s); 4180 return (COMPLETE); 4181 } 4182 4183 #ifdef DIAGNOSTIC 4184 if (scb->sg_count > 255) 4185 panic("ahc bad sg_count"); 4186 #endif 4187 4188 ahc_swap_hscb(scb->hscb); 4189 4190 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4191 4192 scb->flags |= SCB_ACTIVE; 4193 4194 if (!(xs->xs_control & XS_CTL_POLL)) 4195 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4196 ahc_timeout, scb); 4197 4198 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4199 #if 0 4200 printf("Continueing Immediate Command %d:%d\n", 4201 xs->sc_link->scsipi_scsi.target, 4202 xs->sc_link->scsipi_scsi.lun); 4203 #endif 4204 pause_sequencer(ahc); 4205 if ((ahc->flags & AHC_PAGESCBS) == 0) 4206 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4207 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4208 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4209 unpause_sequencer(ahc); 4210 } else { 4211 4212 #if 0 4213 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4214 scb->hscb->tag, ahc->qinfifonext, 4215 &ahc->qinfifo[ahc->qinfifonext], 4216 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4217 #endif 4218 4219 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4220 4221 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4222 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4223 4224 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4225 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4226 } else { 4227 pause_sequencer(ahc); 4228 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4229 unpause_sequencer(ahc); 4230 } 4231 } 4232 4233 #ifdef AHC_DEBUG 4234 if (ahc_debug & AHC_SHOWCMDS) { 4235 scsi_print_addr(xs->sc_link); 4236 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4237 " rate %x\n", 4238 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4239 scb->flags, scb->hscb->control, ahc->qinfifonext, 4240 scb->hscb->scsirate); 4241 } 4242 #endif 4243 4244 if (!(xs->xs_control & XS_CTL_POLL)) { 4245 splx(s); 4246 return (SUCCESSFULLY_QUEUED); 4247 } 4248 /* 4249 * If we can't use interrupts, poll for completion 4250 */ 4251 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4252 do { 4253 if (ahc_poll(ahc, xs->timeout)) { 4254 if (!(xs->xs_control & XS_CTL_SILENT)) 4255 printf("cmd fail\n"); 4256 ahc_timeout(scb); 4257 break; 4258 } 4259 } while (!(xs->xs_status & XS_STS_DONE)); 4260 splx(s); 4261 return (COMPLETE); 4262 } 4263 4264 static int 4265 ahc_poll(struct ahc_softc *ahc, int wait) 4266 { 4267 while (--wait) { 4268 DELAY(1000); 4269 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4270 break; 4271 } 4272 4273 if (wait == 0) { 4274 printf("%s: board is not responding\n", ahc_name(ahc)); 4275 return (EIO); 4276 } 4277 4278 ahc_intr((void *)ahc); 4279 return (0); 4280 } 4281 4282 static int 4283 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4284 struct scb *scb) 4285 { 4286 struct hardware_scb *hscb; 4287 4288 hscb = scb->hscb; 4289 xs->resid = xs->status = 0; 4290 4291 hscb->cmdlen = xs->cmdlen; 4292 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4293 hscb->cmdpointer = hscb->cmdstore_busaddr; 4294 4295 /* Only use S/G if there is a transfer */ 4296 if (xs->datalen) { 4297 int error; 4298 4299 error = bus_dmamap_load(ahc->parent_dmat, 4300 scb->dmamap, xs->data, 4301 xs->datalen, NULL, 4302 (xs->xs_control & XS_CTL_NOSLEEP) ? 4303 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4304 if (error) { 4305 if (!ahc_istagged_device(ahc, xs, 0)) 4306 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4307 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4308 } 4309 error = ahc_execute_scb(scb, 4310 scb->dmamap->dm_segs, 4311 scb->dmamap->dm_nsegs); 4312 return error; 4313 } else { 4314 return ahc_execute_scb(scb, NULL, 0); 4315 } 4316 } 4317 4318 static void 4319 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4320 { 4321 int target; 4322 char channel; 4323 int lun; 4324 4325 target = sc_link->scsipi_scsi.target; 4326 lun = sc_link->scsipi_scsi.lun; 4327 channel = sc_link->scsipi_scsi.channel; 4328 4329 ahc_search_qinfifo(ahc, target, channel, lun, 4330 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4331 SCB_REQUEUE, SEARCH_COMPLETE); 4332 } 4333 4334 static void 4335 ahcallocscbs(struct ahc_softc *ahc) 4336 { 4337 struct scb_data *scb_data; 4338 struct scb *next_scb; 4339 struct sg_map_node *sg_map; 4340 bus_addr_t physaddr; 4341 struct ahc_dma_seg *segs; 4342 int newcount; 4343 int i; 4344 4345 scb_data = ahc->scb_data; 4346 if (scb_data->numscbs >= AHC_SCB_MAX) 4347 /* Can't allocate any more */ 4348 return; 4349 4350 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4351 4352 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4353 4354 if (sg_map == NULL) 4355 return; 4356 4357 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4358 &sg_map->sg_dmamap, 4359 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4360 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4361 "SG space") < 0) { 4362 free(sg_map, M_DEVBUF); 4363 return; 4364 } 4365 4366 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4367 4368 segs = sg_map->sg_vaddr; 4369 physaddr = sg_map->sg_physaddr; 4370 4371 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4372 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4373 int error; 4374 4375 next_scb->sg_list = segs; 4376 /* 4377 * The sequencer always starts with the second entry. 4378 * The first entry is embedded in the scb. 4379 */ 4380 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4381 next_scb->flags = SCB_FREE; 4382 error = bus_dmamap_create(ahc->parent_dmat, 4383 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4384 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4385 &next_scb->dmamap); 4386 if (error != 0) 4387 break; 4388 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4389 next_scb->hscb->tag = ahc->scb_data->numscbs; 4390 next_scb->hscb->cmdstore_busaddr = 4391 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4392 + offsetof(struct hardware_scb, cmdstore); 4393 next_scb->hscb->cmdstore_busaddr = 4394 htole32(next_scb->hscb->cmdstore_busaddr); 4395 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4396 segs += AHC_NSEG; 4397 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4398 next_scb++; 4399 ahc->scb_data->numscbs++; 4400 } 4401 #ifdef AHC_DEBUG 4402 if (ahc_debug & AHC_SHOWSCBALLOC) 4403 printf("%s: allocated %d new SCBs count now %d\n", 4404 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4405 #endif 4406 } 4407 4408 #ifdef AHC_DUMP_SEQ 4409 static void 4410 ahc_dumpseq(struct ahc_softc* ahc) 4411 { 4412 int i; 4413 int max_prog; 4414 4415 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4416 max_prog = 448; 4417 else if ((ahc->features & AHC_ULTRA2) != 0) 4418 max_prog = 768; 4419 else 4420 max_prog = 512; 4421 4422 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4423 ahc_outb(ahc, SEQADDR0, 0); 4424 ahc_outb(ahc, SEQADDR1, 0); 4425 for (i = 0; i < max_prog; i++) { 4426 u_int8_t ins_bytes[4]; 4427 4428 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4429 printf("0x%08x\n", ins_bytes[0] << 24 4430 | ins_bytes[1] << 16 4431 | ins_bytes[2] << 8 4432 | ins_bytes[3]); 4433 } 4434 } 4435 #endif 4436 4437 static void 4438 ahc_loadseq(struct ahc_softc *ahc) 4439 { 4440 struct patch *cur_patch; 4441 int i; 4442 int downloaded; 4443 int skip_addr; 4444 u_int8_t download_consts[4]; 4445 4446 /* Setup downloadable constant table */ 4447 #if 0 4448 /* No downloaded constants are currently defined. */ 4449 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4450 #endif 4451 4452 cur_patch = patches; 4453 downloaded = 0; 4454 skip_addr = 0; 4455 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4456 ahc_outb(ahc, SEQADDR0, 0); 4457 ahc_outb(ahc, SEQADDR1, 0); 4458 4459 for (i = 0; i < sizeof(seqprog)/4; i++) { 4460 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4461 /* 4462 * Don't download this instruction as it 4463 * is in a patch that was removed. 4464 */ 4465 continue; 4466 } 4467 ahc_download_instr(ahc, i, download_consts); 4468 downloaded++; 4469 } 4470 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4471 restart_sequencer(ahc); 4472 4473 #ifdef AHC_DEBUG 4474 printf(" %d instructions downloaded\n", downloaded); 4475 #endif 4476 } 4477 4478 static int 4479 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4480 int start_instr, int *skip_addr) 4481 { 4482 struct patch *cur_patch; 4483 struct patch *last_patch; 4484 int num_patches; 4485 4486 num_patches = sizeof(patches)/sizeof(struct patch); 4487 last_patch = &patches[num_patches]; 4488 cur_patch = *start_patch; 4489 4490 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4491 4492 if (cur_patch->patch_func(ahc) == 0) { 4493 4494 /* Start rejecting code */ 4495 *skip_addr = start_instr + cur_patch->skip_instr; 4496 cur_patch += cur_patch->skip_patch; 4497 } else { 4498 /* Accepted this patch. Advance to the next 4499 * one and wait for our intruction pointer to 4500 * hit this point. 4501 */ 4502 cur_patch++; 4503 } 4504 } 4505 4506 *start_patch = cur_patch; 4507 if (start_instr < *skip_addr) 4508 /* Still skipping */ 4509 return (0); 4510 4511 return (1); 4512 } 4513 4514 static void 4515 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4516 { 4517 union ins_formats instr; 4518 struct ins_format1 *fmt1_ins; 4519 struct ins_format3 *fmt3_ins; 4520 u_int opcode; 4521 4522 /* Structure copy */ 4523 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4524 4525 instr.integer = le32toh(instr.integer); 4526 4527 fmt1_ins = &instr.format1; 4528 fmt3_ins = NULL; 4529 4530 /* Pull the opcode */ 4531 opcode = instr.format1.opcode; 4532 switch (opcode) { 4533 case AIC_OP_JMP: 4534 case AIC_OP_JC: 4535 case AIC_OP_JNC: 4536 case AIC_OP_CALL: 4537 case AIC_OP_JNE: 4538 case AIC_OP_JNZ: 4539 case AIC_OP_JE: 4540 case AIC_OP_JZ: 4541 { 4542 struct patch *cur_patch; 4543 int address_offset; 4544 u_int address; 4545 int skip_addr; 4546 int i; 4547 4548 fmt3_ins = &instr.format3; 4549 address_offset = 0; 4550 address = fmt3_ins->address; 4551 cur_patch = patches; 4552 skip_addr = 0; 4553 4554 for (i = 0; i < address;) { 4555 4556 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4557 4558 if (skip_addr > i) { 4559 int end_addr; 4560 4561 end_addr = MIN(address, skip_addr); 4562 address_offset += end_addr - i; 4563 i = skip_addr; 4564 } else { 4565 i++; 4566 } 4567 } 4568 address -= address_offset; 4569 fmt3_ins->address = address; 4570 /* FALLTHROUGH */ 4571 } 4572 case AIC_OP_OR: 4573 case AIC_OP_AND: 4574 case AIC_OP_XOR: 4575 case AIC_OP_ADD: 4576 case AIC_OP_ADC: 4577 case AIC_OP_BMOV: 4578 if (fmt1_ins->parity != 0) { 4579 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4580 } 4581 fmt1_ins->parity = 0; 4582 /* FALLTHROUGH */ 4583 case AIC_OP_ROL: 4584 if ((ahc->features & AHC_ULTRA2) != 0) { 4585 int i, count; 4586 4587 /* Calculate odd parity for the instruction */ 4588 for (i = 0, count = 0; i < 31; i++) { 4589 u_int32_t mask; 4590 4591 mask = 0x01 << i; 4592 if ((instr.integer & mask) != 0) 4593 count++; 4594 } 4595 if ((count & 0x01) == 0) 4596 instr.format1.parity = 1; 4597 } else { 4598 /* Compress the instruction for older sequencers */ 4599 if (fmt3_ins != NULL) { 4600 instr.integer = 4601 fmt3_ins->immediate 4602 | (fmt3_ins->source << 8) 4603 | (fmt3_ins->address << 16) 4604 | (fmt3_ins->opcode << 25); 4605 } else { 4606 instr.integer = 4607 fmt1_ins->immediate 4608 | (fmt1_ins->source << 8) 4609 | (fmt1_ins->destination << 16) 4610 | (fmt1_ins->ret << 24) 4611 | (fmt1_ins->opcode << 25); 4612 } 4613 } 4614 instr.integer = htole32(instr.integer); 4615 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4616 break; 4617 default: 4618 panic("Unknown opcode encountered in seq program"); 4619 break; 4620 } 4621 } 4622 4623 static void 4624 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4625 { 4626 4627 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4628 struct scb *scbp; 4629 4630 scb->flags |= SCB_RECOVERY_SCB; 4631 4632 /* 4633 * Take all queued, but not sent SCBs out of the equation. 4634 * Also ensure that no new CCBs are queued to us while we 4635 * try to fix this problem. 4636 */ 4637 ahc->queue_blocked = 1; 4638 4639 /* 4640 * Go through all of our pending SCBs and remove 4641 * any scheduled timeouts for them. We will reschedule 4642 * them after we've successfully fixed this problem. 4643 */ 4644 scbp = ahc->pending_ccbs.lh_first; 4645 while (scbp != NULL) { 4646 callout_stop(&scbp->xs->xs_callout); 4647 scbp = scbp->plinks.le_next; 4648 } 4649 } 4650 } 4651 4652 static void 4653 ahc_timeout(void *arg) 4654 { 4655 struct scb *scb; 4656 struct ahc_softc *ahc; 4657 int s, found; 4658 u_int last_phase; 4659 int target; 4660 int lun; 4661 int i; 4662 char channel; 4663 4664 scb = (struct scb *)arg; 4665 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4666 4667 s = splbio(); 4668 4669 /* 4670 * Ensure that the card doesn't do anything 4671 * behind our back. Also make sure that we 4672 * didn't "just" miss an interrupt that would 4673 * affect this timeout. 4674 */ 4675 do { 4676 ahc_intr(ahc); 4677 pause_sequencer(ahc); 4678 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4679 4680 if ((scb->flags & SCB_ACTIVE) == 0) { 4681 /* Previous timeout took care of me already */ 4682 printf("Timedout SCB handled by another timeout\n"); 4683 unpause_sequencer(ahc); 4684 splx(s); 4685 return; 4686 } 4687 4688 target = SCB_TARGET(scb); 4689 channel = SCB_CHANNEL(scb); 4690 lun = SCB_LUN(scb); 4691 4692 scsi_print_addr(scb->xs->sc_link); 4693 printf("SCB %x - timed out ", scb->hscb->tag); 4694 /* 4695 * Take a snapshot of the bus state and print out 4696 * some information so we can track down driver bugs. 4697 */ 4698 last_phase = ahc_inb(ahc, LASTPHASE); 4699 4700 for (i = 0; i < num_phases; i++) { 4701 if (last_phase == phase_table[i].phase) 4702 break; 4703 } 4704 printf("%s", phase_table[i].phasemsg); 4705 4706 printf(", SEQADDR == 0x%x\n", 4707 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4708 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4709 4710 #ifdef AHC_DEBUG 4711 ahc_print_scb(scb); 4712 #endif 4713 4714 #if 0 4715 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4716 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4717 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4718 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4719 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4720 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4721 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4722 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4723 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4724 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4725 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4726 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4727 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4728 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4729 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4730 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4731 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4732 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4733 if (scb->sg_count > 0) { 4734 for (i = 0; i < scb->sg_count; i++) { 4735 printf("sg[%d] - Addr 0x%x : Length %d\n", 4736 i, 4737 le32toh(scb->sg_list[i].addr), 4738 le32toh(scb->sg_list[i].len)); 4739 } 4740 } 4741 #endif 4742 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4743 /* 4744 * Been down this road before. 4745 * Do a full bus reset. 4746 */ 4747 bus_reset: 4748 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4749 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4750 printf("%s: Issued Channel %c Bus Reset. " 4751 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4752 } else { 4753 /* 4754 * If we are a target, transition to bus free and report 4755 * the timeout. 4756 * 4757 * The target/initiator that is holding up the bus may not 4758 * be the same as the one that triggered this timeout 4759 * (different commands have different timeout lengths). 4760 * If the bus is idle and we are actiing as the initiator 4761 * for this request, queue a BDR message to the timed out 4762 * target. Otherwise, if the timed out transaction is 4763 * active: 4764 * Initiator transaction: 4765 * Stuff the message buffer with a BDR message and assert 4766 * ATN in the hopes that the target will let go of the bus 4767 * and go to the mesgout phase. If this fails, we'll 4768 * get another timeout 2 seconds later which will attempt 4769 * a bus reset. 4770 * 4771 * Target transaction: 4772 * Transition to BUS FREE and report the error. 4773 * It's good to be the target! 4774 */ 4775 u_int active_scb_index; 4776 4777 active_scb_index = ahc_inb(ahc, SCB_TAG); 4778 4779 if (last_phase != P_BUSFREE 4780 && (active_scb_index < ahc->scb_data->numscbs)) { 4781 struct scb *active_scb; 4782 4783 /* 4784 * If the active SCB is not from our device, 4785 * assume that another device is hogging the bus 4786 * and wait for it's timeout to expire before 4787 * taking additional action. 4788 */ 4789 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4790 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4791 u_int newtimeout; 4792 4793 scsi_print_addr(scb->xs->sc_link); 4794 printf("Other SCB Timeout%s", 4795 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4796 ? " again\n" : "\n"); 4797 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4798 newtimeout = MAX(active_scb->xs->timeout, 4799 scb->xs->timeout); 4800 callout_reset(&scb->xs->xs_callout, 4801 (newtimeout * hz) / 1000, 4802 ahc_timeout, scb); 4803 splx(s); 4804 return; 4805 } 4806 4807 /* It's us */ 4808 if ((scb->hscb->control & TARGET_SCB) != 0) { 4809 4810 /* 4811 * Send back any queued up transactions 4812 * and properly record the error condition. 4813 */ 4814 ahc_freeze_devq(ahc, scb->xs->sc_link); 4815 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4816 ahc_freeze_ccb(scb); 4817 ahc_done(ahc, scb); 4818 4819 /* Will clear us from the bus */ 4820 restart_sequencer(ahc); 4821 return; 4822 } 4823 4824 ahc_set_recoveryscb(ahc, active_scb); 4825 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4826 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4827 scsi_print_addr(active_scb->xs->sc_link); 4828 printf("BDR message in message buffer\n"); 4829 active_scb->flags |= SCB_DEVICE_RESET; 4830 callout_reset(&active_scb->xs->xs_callout, 4831 2 * hz, ahc_timeout, active_scb); 4832 unpause_sequencer(ahc); 4833 } else { 4834 int disconnected; 4835 4836 /* XXX Shouldn't panic. Just punt instead */ 4837 if ((scb->hscb->control & TARGET_SCB) != 0) 4838 panic("Timed-out target SCB but bus idle"); 4839 4840 if (last_phase != P_BUSFREE 4841 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4842 /* XXX What happened to the SCB? */ 4843 /* Hung target selection. Goto busfree */ 4844 printf("%s: Hung target selection\n", 4845 ahc_name(ahc)); 4846 restart_sequencer(ahc); 4847 return; 4848 } 4849 4850 if (ahc_search_qinfifo(ahc, target, channel, lun, 4851 scb->hscb->tag, ROLE_INITIATOR, 4852 /*status*/0, SEARCH_COUNT) > 0) { 4853 disconnected = FALSE; 4854 } else { 4855 disconnected = TRUE; 4856 } 4857 4858 if (disconnected) { 4859 u_int active_scb; 4860 4861 ahc_set_recoveryscb(ahc, scb); 4862 /* 4863 * Simply set the MK_MESSAGE control bit. 4864 */ 4865 scb->hscb->control |= MK_MESSAGE; 4866 scb->flags |= SCB_QUEUED_MSG 4867 | SCB_DEVICE_RESET; 4868 4869 /* 4870 * Mark the cached copy of this SCB in the 4871 * disconnected list too, so that a reconnect 4872 * at this point causes a BDR or abort. 4873 */ 4874 active_scb = ahc_inb(ahc, SCBPTR); 4875 if (ahc_search_disc_list(ahc, target, 4876 channel, lun, 4877 scb->hscb->tag, 4878 /*stop_on_first*/TRUE, 4879 /*remove*/FALSE, 4880 /*save_state*/FALSE)) { 4881 u_int scb_control; 4882 4883 scb_control = ahc_inb(ahc, SCB_CONTROL); 4884 scb_control |= MK_MESSAGE; 4885 ahc_outb(ahc, SCB_CONTROL, scb_control); 4886 } 4887 ahc_outb(ahc, SCBPTR, active_scb); 4888 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4889 /*unbusy*/TRUE); 4890 4891 /* 4892 * Actually re-queue this SCB in case we can 4893 * select the device before it reconnects. 4894 * Clear out any entries in the QINFIFO first 4895 * so we are the next SCB for this target 4896 * to run. 4897 */ 4898 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4899 channel, SCB_LUN(scb), 4900 SCB_LIST_NULL, 4901 ROLE_INITIATOR, 4902 SCB_REQUEUE, 4903 SEARCH_COMPLETE); 4904 scsi_print_addr(scb->xs->sc_link); 4905 printf("Queuing a BDR SCB\n"); 4906 ahc->qinfifo[ahc->qinfifonext++] = 4907 scb->hscb->tag; 4908 4909 bus_dmamap_sync(ahc->parent_dmat, 4910 ahc->shared_data_dmamap, 4911 QINFIFO_OFFSET * 256, 256, 4912 BUS_DMASYNC_PREWRITE); 4913 4914 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4915 ahc_outb(ahc, HNSCB_QOFF, 4916 ahc->qinfifonext); 4917 } else { 4918 ahc_outb(ahc, KERNEL_QINPOS, 4919 ahc->qinfifonext); 4920 } 4921 callout_reset(&scb->xs->xs_callout, 2 * hz, 4922 ahc_timeout, scb); 4923 unpause_sequencer(ahc); 4924 } else { 4925 /* Go "immediatly" to the bus reset */ 4926 /* This shouldn't happen */ 4927 ahc_set_recoveryscb(ahc, scb); 4928 scsi_print_addr(scb->xs->sc_link); 4929 printf("SCB %x: Immediate reset. " 4930 "Flags = 0x%x\n", scb->hscb->tag, 4931 scb->flags); 4932 goto bus_reset; 4933 } 4934 } 4935 } 4936 splx(s); 4937 } 4938 4939 static int 4940 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4941 int lun, u_int tag, role_t role, scb_flag status, 4942 ahc_search_action action) 4943 { 4944 struct scb *scbp; 4945 u_int8_t qinpos; 4946 u_int8_t qintail; 4947 int found; 4948 4949 qinpos = ahc_inb(ahc, QINPOS); 4950 qintail = ahc->qinfifonext; 4951 found = 0; 4952 4953 /* 4954 * Start with an empty queue. Entries that are not chosen 4955 * for removal will be re-added to the queue as we go. 4956 */ 4957 ahc->qinfifonext = qinpos; 4958 4959 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4960 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4961 4962 while (qinpos != qintail) { 4963 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4964 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4965 /* 4966 * We found an scb that needs to be removed. 4967 */ 4968 switch (action) { 4969 case SEARCH_COMPLETE: 4970 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4971 scbp->flags |= status; 4972 scbp->xs->error = XS_NOERROR; 4973 } 4974 ahc_freeze_ccb(scbp); 4975 ahc_done(ahc, scbp); 4976 break; 4977 case SEARCH_COUNT: 4978 ahc->qinfifo[ahc->qinfifonext++] = 4979 scbp->hscb->tag; 4980 break; 4981 case SEARCH_REMOVE: 4982 break; 4983 } 4984 found++; 4985 } else { 4986 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4987 } 4988 qinpos++; 4989 } 4990 4991 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4992 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4993 4994 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4995 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4996 } else { 4997 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4998 } 4999 5000 return (found); 5001 } 5002 5003 /* 5004 * Abort all SCBs that match the given description (target/channel/lun/tag), 5005 * setting their status to the passed in status if the status has not already 5006 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5007 * is paused before it is called. 5008 */ 5009 static int 5010 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5011 int lun, u_int tag, role_t role, int status) 5012 { 5013 struct scb *scbp; 5014 u_int active_scb; 5015 int i; 5016 int found; 5017 5018 /* restore this when we're done */ 5019 active_scb = ahc_inb(ahc, SCBPTR); 5020 5021 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5022 role, SCB_REQUEUE, SEARCH_COMPLETE); 5023 5024 /* 5025 * Search waiting for selection list. 5026 */ 5027 { 5028 u_int8_t next, prev; 5029 5030 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5031 prev = SCB_LIST_NULL; 5032 5033 while (next != SCB_LIST_NULL) { 5034 u_int8_t scb_index; 5035 5036 ahc_outb(ahc, SCBPTR, next); 5037 scb_index = ahc_inb(ahc, SCB_TAG); 5038 if (scb_index >= ahc->scb_data->numscbs) { 5039 panic("Waiting List inconsistency. " 5040 "SCB index == %d, yet numscbs == %d.", 5041 scb_index, ahc->scb_data->numscbs); 5042 } 5043 scbp = &ahc->scb_data->scbarray[scb_index]; 5044 if (ahc_match_scb(scbp, target, channel, 5045 lun, SCB_LIST_NULL, role)) { 5046 5047 next = ahc_abort_wscb(ahc, next, prev); 5048 } else { 5049 5050 prev = next; 5051 next = ahc_inb(ahc, SCB_NEXT); 5052 } 5053 } 5054 } 5055 /* 5056 * Go through the disconnected list and remove any entries we 5057 * have queued for completion, 0'ing their control byte too. 5058 * We save the active SCB and restore it ourselves, so there 5059 * is no reason for this search to restore it too. 5060 */ 5061 ahc_search_disc_list(ahc, target, channel, lun, tag, 5062 /*stop_on_first*/FALSE, /*remove*/TRUE, 5063 /*save_state*/FALSE); 5064 5065 /* 5066 * Go through the hardware SCB array looking for commands that 5067 * were active but not on any list. 5068 */ 5069 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5070 u_int scbid; 5071 5072 ahc_outb(ahc, SCBPTR, i); 5073 scbid = ahc_inb(ahc, SCB_TAG); 5074 scbp = &ahc->scb_data->scbarray[scbid]; 5075 if (scbid < ahc->scb_data->numscbs 5076 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5077 ahc_add_curscb_to_free_list(ahc); 5078 } 5079 5080 /* 5081 * Go through the pending CCB list and look for 5082 * commands for this target that are still active. 5083 * These are other tagged commands that were 5084 * disconnected when the reset occured. 5085 */ 5086 { 5087 struct scb *scb; 5088 5089 scb = ahc->pending_ccbs.lh_first; 5090 while (scb != NULL) { 5091 scbp = scb; 5092 scb = scb->plinks.le_next; 5093 if (ahc_match_scb(scbp, target, channel, 5094 lun, tag, role)) { 5095 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5096 ahcsetccbstatus(scbp->xs, status); 5097 ahc_freeze_ccb(scbp); 5098 ahc_done(ahc, scbp); 5099 found++; 5100 } 5101 } 5102 } 5103 ahc_outb(ahc, SCBPTR, active_scb); 5104 return found; 5105 } 5106 5107 static int 5108 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5109 int lun, u_int tag, int stop_on_first, int remove, 5110 int save_state) 5111 { 5112 struct scb *scbp; 5113 u_int next; 5114 u_int prev; 5115 u_int count; 5116 u_int active_scb; 5117 5118 count = 0; 5119 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5120 prev = SCB_LIST_NULL; 5121 5122 if (save_state) { 5123 /* restore this when we're done */ 5124 active_scb = ahc_inb(ahc, SCBPTR); 5125 } else 5126 /* Silence compiler */ 5127 active_scb = SCB_LIST_NULL; 5128 5129 while (next != SCB_LIST_NULL) { 5130 u_int scb_index; 5131 5132 ahc_outb(ahc, SCBPTR, next); 5133 scb_index = ahc_inb(ahc, SCB_TAG); 5134 if (scb_index >= ahc->scb_data->numscbs) { 5135 panic("Disconnected List inconsistency. " 5136 "SCB index == %d, yet numscbs == %d.", 5137 scb_index, ahc->scb_data->numscbs); 5138 } 5139 scbp = &ahc->scb_data->scbarray[scb_index]; 5140 if (ahc_match_scb(scbp, target, channel, lun, 5141 tag, ROLE_INITIATOR)) { 5142 count++; 5143 if (remove) { 5144 next = 5145 ahc_rem_scb_from_disc_list(ahc, prev, next); 5146 } else { 5147 prev = next; 5148 next = ahc_inb(ahc, SCB_NEXT); 5149 } 5150 if (stop_on_first) 5151 break; 5152 } else { 5153 prev = next; 5154 next = ahc_inb(ahc, SCB_NEXT); 5155 } 5156 } 5157 if (save_state) 5158 ahc_outb(ahc, SCBPTR, active_scb); 5159 return (count); 5160 } 5161 5162 static u_int 5163 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5164 { 5165 u_int next; 5166 5167 ahc_outb(ahc, SCBPTR, scbptr); 5168 next = ahc_inb(ahc, SCB_NEXT); 5169 5170 ahc_outb(ahc, SCB_CONTROL, 0); 5171 5172 ahc_add_curscb_to_free_list(ahc); 5173 5174 if (prev != SCB_LIST_NULL) { 5175 ahc_outb(ahc, SCBPTR, prev); 5176 ahc_outb(ahc, SCB_NEXT, next); 5177 } else 5178 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5179 5180 return (next); 5181 } 5182 5183 static void 5184 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5185 { 5186 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5187 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5188 5189 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5190 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5191 } 5192 5193 /* 5194 * Manipulate the waiting for selection list and return the 5195 * scb that follows the one that we remove. 5196 */ 5197 static u_int 5198 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5199 { 5200 u_int curscb, next; 5201 5202 /* 5203 * Select the SCB we want to abort and 5204 * pull the next pointer out of it. 5205 */ 5206 curscb = ahc_inb(ahc, SCBPTR); 5207 ahc_outb(ahc, SCBPTR, scbpos); 5208 next = ahc_inb(ahc, SCB_NEXT); 5209 5210 /* Clear the necessary fields */ 5211 ahc_outb(ahc, SCB_CONTROL, 0); 5212 5213 ahc_add_curscb_to_free_list(ahc); 5214 5215 /* update the waiting list */ 5216 if (prev == SCB_LIST_NULL) { 5217 /* First in the list */ 5218 ahc_outb(ahc, WAITING_SCBH, next); 5219 5220 /* 5221 * Ensure we aren't attempting to perform 5222 * selection for this entry. 5223 */ 5224 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5225 } else { 5226 /* 5227 * Select the scb that pointed to us 5228 * and update its next pointer. 5229 */ 5230 ahc_outb(ahc, SCBPTR, prev); 5231 ahc_outb(ahc, SCB_NEXT, next); 5232 } 5233 5234 /* 5235 * Point us back at the original scb position. 5236 */ 5237 ahc_outb(ahc, SCBPTR, curscb); 5238 return next; 5239 } 5240 5241 static void 5242 ahc_clear_intstat(struct ahc_softc *ahc) 5243 { 5244 /* Clear any interrupt conditions this may have caused */ 5245 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5246 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5247 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5248 CLRREQINIT); 5249 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5250 } 5251 5252 static void 5253 ahc_reset_current_bus(struct ahc_softc *ahc) 5254 { 5255 u_int8_t scsiseq; 5256 5257 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5258 scsiseq = ahc_inb(ahc, SCSISEQ); 5259 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5260 DELAY(AHC_BUSRESET_DELAY); 5261 /* Turn off the bus reset */ 5262 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5263 5264 ahc_clear_intstat(ahc); 5265 5266 /* Re-enable reset interrupts */ 5267 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5268 } 5269 5270 static int 5271 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5272 { 5273 u_int initiator, target, max_scsiid; 5274 u_int sblkctl; 5275 u_int our_id; 5276 int found; 5277 int restart_needed; 5278 char cur_channel; 5279 5280 ahc->pending_device = NULL; 5281 5282 pause_sequencer(ahc); 5283 5284 /* 5285 * Run our command complete fifos to ensure that we perform 5286 * completion processing on any commands that 'completed' 5287 * before the reset occurred. 5288 */ 5289 ahc_run_qoutfifo(ahc); 5290 5291 /* 5292 * Reset the bus if we are initiating this reset 5293 */ 5294 sblkctl = ahc_inb(ahc, SBLKCTL); 5295 cur_channel = 'A'; 5296 if ((ahc->features & AHC_TWIN) != 0 5297 && ((sblkctl & SELBUSB) != 0)) 5298 cur_channel = 'B'; 5299 if (cur_channel != channel) { 5300 /* Case 1: Command for another bus is active 5301 * Stealthily reset the other bus without 5302 * upsetting the current bus. 5303 */ 5304 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5305 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5306 ahc_outb(ahc, SCSISEQ, 5307 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5308 if (initiate_reset) 5309 ahc_reset_current_bus(ahc); 5310 ahc_clear_intstat(ahc); 5311 ahc_outb(ahc, SBLKCTL, sblkctl); 5312 restart_needed = FALSE; 5313 } else { 5314 /* Case 2: A command from this bus is active or we're idle */ 5315 ahc_clear_msg_state(ahc); 5316 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5317 ahc_outb(ahc, SCSISEQ, 5318 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5319 if (initiate_reset) 5320 ahc_reset_current_bus(ahc); 5321 ahc_clear_intstat(ahc); 5322 5323 /* 5324 * Since we are going to restart the sequencer, avoid 5325 * a race in the sequencer that could cause corruption 5326 * of our Q pointers by starting over from index 0. 5327 */ 5328 ahc->qoutfifonext = 0; 5329 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5330 ahc_outb(ahc, SDSCB_QOFF, 0); 5331 else 5332 ahc_outb(ahc, QOUTPOS, 0); 5333 restart_needed = TRUE; 5334 } 5335 5336 /* 5337 * Clean up all the state information for the 5338 * pending transactions on this bus. 5339 */ 5340 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5341 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5342 ROLE_UNKNOWN, XS_RESET); 5343 if (channel == 'B') { 5344 our_id = ahc->our_id_b; 5345 } else { 5346 our_id = ahc->our_id; 5347 } 5348 5349 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5350 5351 /* 5352 * Revert to async/narrow transfers until we renegotiate. 5353 */ 5354 for (target = 0; target <= max_scsiid; target++) { 5355 5356 if (ahc->enabled_targets[target] == NULL) 5357 continue; 5358 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5359 struct ahc_devinfo devinfo; 5360 5361 ahc_compile_devinfo(&devinfo, target, initiator, 5362 AHC_LUN_WILDCARD, 5363 channel, ROLE_UNKNOWN); 5364 ahc_set_width(ahc, &devinfo, 5365 MSG_EXT_WDTR_BUS_8_BIT, 5366 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5367 ahc_set_syncrate(ahc, &devinfo, 5368 /*syncrate*/NULL, /*period*/0, 5369 /*offset*/0, AHC_TRANS_CUR, 5370 /*paused*/TRUE, FALSE); 5371 } 5372 } 5373 5374 if (restart_needed) 5375 restart_sequencer(ahc); 5376 else 5377 unpause_sequencer(ahc); 5378 return found; 5379 } 5380 5381 static int 5382 ahc_match_scb(struct scb *scb, int target, char channel, 5383 int lun, u_int tag, role_t role) 5384 { 5385 int targ = SCB_TARGET(scb); 5386 char chan = SCB_CHANNEL(scb); 5387 int slun = SCB_LUN(scb); 5388 int match; 5389 5390 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5391 if (match != 0) 5392 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5393 if (match != 0) 5394 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5395 5396 return match; 5397 } 5398 5399 static void 5400 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5401 { 5402 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5403 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5404 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5405 ahc->msgout_buf[ahc->msgout_index++] = period; 5406 ahc->msgout_buf[ahc->msgout_index++] = offset; 5407 ahc->msgout_len += 5; 5408 } 5409 5410 static void 5411 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5412 { 5413 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5414 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5415 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5416 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5417 ahc->msgout_len += 4; 5418 } 5419 5420 static void 5421 ahc_calc_residual(struct scb *scb) 5422 { 5423 struct hardware_scb *hscb; 5424 5425 hscb = scb->hscb; 5426 5427 /* 5428 * If the disconnected flag is still set, this is bogus 5429 * residual information left over from a sequencer 5430 * pagin/pageout, so ignore this case. 5431 */ 5432 if ((scb->hscb->control & DISCONNECTED) == 0) { 5433 u_int32_t resid; 5434 int resid_sgs; 5435 int sg; 5436 5437 /* 5438 * Remainder of the SG where the transfer 5439 * stopped. 5440 */ 5441 resid = (hscb->residual_data_count[2] << 16) 5442 | (hscb->residual_data_count[1] <<8) 5443 | (hscb->residual_data_count[0]); 5444 5445 /* 5446 * Add up the contents of all residual 5447 * SG segments that are after the SG where 5448 * the transfer stopped. 5449 */ 5450 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5451 sg = scb->sg_count - resid_sgs; 5452 while (resid_sgs > 0) { 5453 5454 resid += le32toh(scb->sg_list[sg].len); 5455 sg++; 5456 resid_sgs--; 5457 } 5458 scb->xs->resid = resid; 5459 } 5460 5461 /* 5462 * Clean out the residual information in this SCB for its 5463 * next consumer. 5464 */ 5465 hscb->residual_SG_count = 0; 5466 5467 #ifdef AHC_DEBUG 5468 if (ahc_debug & AHC_SHOWMISC) { 5469 scsi_print_addr(scb->xs->sc_link); 5470 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5471 } 5472 #endif 5473 } 5474 5475 static void 5476 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5477 { 5478 struct scb *scb; 5479 int pending_ccb_count; 5480 int i; 5481 u_int saved_scbptr; 5482 5483 /* 5484 * Traverse the pending SCB list and ensure that all of the 5485 * SCBs there have the proper settings. 5486 */ 5487 scb = LIST_FIRST(&ahc->pending_ccbs); 5488 pending_ccb_count = 0; 5489 while (scb != NULL) { 5490 struct ahc_devinfo devinfo; 5491 struct scsipi_xfer *xs; 5492 struct scb *pending_scb; 5493 struct hardware_scb *pending_hscb; 5494 struct ahc_initiator_tinfo *tinfo; 5495 struct tmode_tstate *tstate; 5496 u_int our_id, remote_id; 5497 5498 xs = scb->xs; 5499 pending_scb = scb; 5500 pending_hscb = pending_scb->hscb; 5501 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5502 ? ahc->our_id_b : ahc->our_id; 5503 remote_id = xs->sc_link->scsipi_scsi.target; 5504 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5505 SCB_LUN(pending_scb), 5506 SCB_CHANNEL(pending_scb), 5507 ROLE_UNKNOWN); 5508 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5509 our_id, remote_id, &tstate); 5510 pending_hscb->control &= ~ULTRAENB; 5511 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5512 pending_hscb->control |= ULTRAENB; 5513 pending_hscb->scsirate = tinfo->scsirate; 5514 pending_hscb->scsioffset = tinfo->current.offset; 5515 pending_ccb_count++; 5516 scb = LIST_NEXT(scb, plinks); 5517 } 5518 5519 if (pending_ccb_count == 0) 5520 return; 5521 5522 saved_scbptr = ahc_inb(ahc, SCBPTR); 5523 /* Ensure that the hscbs down on the card match the new information */ 5524 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5525 u_int scb_tag; 5526 5527 ahc_outb(ahc, SCBPTR, i); 5528 scb_tag = ahc_inb(ahc, SCB_TAG); 5529 if (scb_tag != SCB_LIST_NULL) { 5530 struct ahc_devinfo devinfo; 5531 struct scb *pending_scb; 5532 struct scsipi_xfer *xs; 5533 struct hardware_scb *pending_hscb; 5534 struct ahc_initiator_tinfo *tinfo; 5535 struct tmode_tstate *tstate; 5536 u_int our_id, remote_id; 5537 u_int control; 5538 5539 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5540 if (pending_scb->flags == SCB_FREE) 5541 continue; 5542 pending_hscb = pending_scb->hscb; 5543 xs = pending_scb->xs; 5544 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5545 ? ahc->our_id_b : ahc->our_id; 5546 remote_id = xs->sc_link->scsipi_scsi.target; 5547 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5548 SCB_LUN(pending_scb), 5549 SCB_CHANNEL(pending_scb), 5550 ROLE_UNKNOWN); 5551 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5552 our_id, remote_id, &tstate); 5553 control = ahc_inb(ahc, SCB_CONTROL); 5554 control &= ~ULTRAENB; 5555 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5556 control |= ULTRAENB; 5557 ahc_outb(ahc, SCB_CONTROL, control); 5558 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5559 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5560 } 5561 } 5562 ahc_outb(ahc, SCBPTR, saved_scbptr); 5563 } 5564 5565 #if UNUSED 5566 static void 5567 ahc_dump_targcmd(struct target_cmd *cmd) 5568 { 5569 u_int8_t *byte; 5570 u_int8_t *last_byte; 5571 int i; 5572 5573 byte = &cmd->initiator_channel; 5574 /* Debugging info for received commands */ 5575 last_byte = &cmd[1].initiator_channel; 5576 5577 i = 0; 5578 while (byte < last_byte) { 5579 if (i == 0) 5580 printf("\t"); 5581 printf("%#x", *byte++); 5582 i++; 5583 if (i == 8) { 5584 printf("\n"); 5585 i = 0; 5586 } else { 5587 printf(", "); 5588 } 5589 } 5590 } 5591 #endif 5592 5593 static void 5594 ahc_shutdown(void *arg) 5595 { 5596 struct ahc_softc *ahc; 5597 int i; 5598 u_int sxfrctl1_a, sxfrctl1_b; 5599 5600 ahc = (struct ahc_softc *)arg; 5601 5602 pause_sequencer(ahc); 5603 5604 /* 5605 * Preserve the value of the SXFRCTL1 register for all channels. 5606 * It contains settings that affect termination and we don't want 5607 * to disturb the integrity of the bus during shutdown in case 5608 * we are in a multi-initiator setup. 5609 */ 5610 sxfrctl1_b = 0; 5611 if ((ahc->features & AHC_TWIN) != 0) { 5612 u_int sblkctl; 5613 5614 sblkctl = ahc_inb(ahc, SBLKCTL); 5615 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5616 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5617 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5618 } 5619 5620 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5621 5622 /* This will reset most registers to 0, but not all */ 5623 ahc_reset(ahc); 5624 5625 if ((ahc->features & AHC_TWIN) != 0) { 5626 u_int sblkctl; 5627 5628 sblkctl = ahc_inb(ahc, SBLKCTL); 5629 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5630 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5631 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5632 } 5633 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5634 5635 ahc_outb(ahc, SCSISEQ, 0); 5636 ahc_outb(ahc, SXFRCTL0, 0); 5637 ahc_outb(ahc, DSPCISTATUS, 0); 5638 5639 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5640 ahc_outb(ahc, i, 0); 5641 } 5642 5643 #if defined(AHC_DEBUG) && 0 5644 static void 5645 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5646 { 5647 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5648 5649 printf("\tcurrent:\n"); 5650 printf("\t\twidth %u period %u offset %u flags %x\n", 5651 tinfo->current.width, tinfo->current.period, 5652 tinfo->current.offset, tinfo->current.ppr_flags); 5653 5654 printf("\tgoal:\n"); 5655 printf("\t\twidth %u period %u offset %u flags %x\n", 5656 tinfo->goal.width, tinfo->goal.period, 5657 tinfo->goal.offset, tinfo->goal.ppr_flags); 5658 5659 printf("\tuser:\n"); 5660 printf("\t\twidth %u period %u offset %u flags %x\n", 5661 tinfo->user.width, tinfo->user.period, 5662 tinfo->user.offset, tinfo->user.ppr_flags); 5663 } 5664 #endif 5665 5666 static void 5667 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5668 { 5669 struct scsipi_inquiry_data *inq; 5670 struct ahc_devinfo devinfo; 5671 struct tmode_tstate *tstate; 5672 int target_id, our_id; 5673 char channel; 5674 5675 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5676 return; 5677 5678 if (xs->sc_link->quirks & SDEV_NOTAG) 5679 return; 5680 5681 target_id = xs->sc_link->scsipi_scsi.target; 5682 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5683 channel = SIM_CHANNEL(ahc, xs->sc_link); 5684 5685 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5686 ahc_compile_devinfo(&devinfo, our_id, target_id, 5687 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5688 5689 if (tstate->tagdisable & devinfo.target_mask) 5690 return; 5691 5692 /* 5693 * Sneak a look at the results of the SCSI Inquiry 5694 * command and see if we can do Tagged queing. This 5695 * should really be done by the higher level drivers. 5696 */ 5697 inq = (struct scsipi_inquiry_data *)xs->data; 5698 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5699 printf("%s: target %d using tagged queuing\n", 5700 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5701 5702 ahc_set_tags(ahc, &devinfo, TRUE); 5703 5704 if (ahc->scb_data->maxhscbs >= 16 || 5705 (ahc->flags & AHC_PAGESCBS)) { 5706 /* Default to 16 tags */ 5707 xs->sc_link->openings = 16; 5708 } else { 5709 /* 5710 * Default to 4 tags on whimpy 5711 * cards that don't have much SCB 5712 * space and can't page. This prevents 5713 * a single device from hogging all 5714 * slots. We should really have a better 5715 * way of providing fairness. 5716 */ 5717 xs->sc_link->openings = 4; 5718 } 5719 } 5720 } 5721 5722 static int 5723 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5724 int nocmdcheck) 5725 { 5726 char channel; 5727 u_int our_id, target; 5728 struct tmode_tstate *tstate; 5729 struct ahc_devinfo devinfo; 5730 5731 if (xs->sc_link->quirks & SDEV_NOTAG) 5732 return 0; 5733 5734 /* 5735 * XXX never do these commands with tags. Should really be 5736 * in a higher layer. 5737 */ 5738 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5739 xs->cmd->opcode == TEST_UNIT_READY || 5740 xs->cmd->opcode == REQUEST_SENSE)) 5741 return 0; 5742 5743 channel = SIM_CHANNEL(ahc, xs->sc_link); 5744 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5745 target = xs->sc_link->scsipi_scsi.target; 5746 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5747 5748 ahc_compile_devinfo(&devinfo, our_id, target, 5749 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5750 5751 return (tstate->tagenable & devinfo.target_mask); 5752 } 5753
Indexes created Thu Oct 02 01:09:59 GMT 2025