aic7xxx.c revision 1.57
1 /* $NetBSD: aic7xxx.c,v 1.57 2000/06/26 19:38:14 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 91 #include <sys/param.h> 92 #include <sys/kernel.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/malloc.h> 96 #include <sys/buf.h> 97 #include <sys/proc.h> 98 #include <sys/scsiio.h> 99 100 #include <machine/bus.h> 101 #include <machine/intr.h> 102 103 #include <dev/scsipi/scsi_all.h> 104 #include <dev/scsipi/scsipi_all.h> 105 #include <dev/scsipi/scsi_message.h> 106 #include <dev/scsipi/scsipi_debug.h> 107 #include <dev/scsipi/scsiconf.h> 108 109 #include <vm/vm.h> 110 111 #include <dev/ic/aic7xxxvar.h> 112 #include <dev/microcode/aic7xxx/sequencer.h> 113 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 115 116 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 117 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 118 #define ALL_CHANNELS '\0' 119 #define ALL_TARGETS_MASK 0xFFFF 120 #define INITIATOR_WILDCARD (~0) 121 122 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 123 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 124 #define SIM_CHANNEL(ahc, sc_link) \ 125 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 126 #define SIM_SCSI_ID(ahc, sc_link) \ 127 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 128 #define SCB_IS_SCSIBUS_B(scb) \ 129 (((scb)->hscb->tcl & SELBUSB) != 0) 130 #define SCB_TARGET(scb) \ 131 (((scb)->hscb->tcl & TID) >> 4) 132 #define SCB_CHANNEL(scb) \ 133 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 134 #define SCB_LUN(scb) \ 135 ((scb)->hscb->tcl & LID) 136 #define SCB_TARGET_OFFSET(scb) \ 137 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 138 #define SCB_TARGET_MASK(scb) \ 139 (0x01 << (SCB_TARGET_OFFSET(scb))) 140 #define TCL_CHANNEL(ahc, tcl) \ 141 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 142 #define TCL_SCSI_ID(ahc, tcl) \ 143 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 144 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 145 #define TCL_LUN(tcl) ((tcl) & LID) 146 147 #define XS_TCL(ahc, xs) \ 148 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 149 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 150 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 151 152 char *ahc_chip_names[] = 153 { 154 "NONE", 155 "aic7770", 156 "aic7850", 157 "aic7855", 158 "aic7859", 159 "aic7860", 160 "aic7870", 161 "aic7880", 162 "aic7890/91", 163 "aic7892", 164 "aic7895", 165 "aic7896/97", 166 "aic7899" 167 }; 168 169 typedef enum { 170 ROLE_UNKNOWN, 171 ROLE_INITIATOR, 172 ROLE_TARGET 173 } role_t; 174 175 struct ahc_devinfo { 176 int our_scsiid; 177 int target_offset; 178 u_int16_t target_mask; 179 u_int8_t target; 180 u_int8_t lun; 181 char channel; 182 role_t role; /* 183 * Only guaranteed to be correct if not 184 * in the busfree state. 185 */ 186 }; 187 188 typedef enum { 189 SEARCH_COMPLETE, 190 SEARCH_COUNT, 191 SEARCH_REMOVE 192 } ahc_search_action; 193 194 #ifdef AHC_DEBUG 195 static int ahc_debug = AHC_DEBUG; 196 #endif 197 198 static int ahcinitscbdata(struct ahc_softc *); 199 static void ahcfiniscbdata(struct ahc_softc *); 200 201 #if UNUSED 202 static void ahc_dump_targcmd(struct target_cmd *); 203 #endif 204 static void ahc_shutdown(void *arg); 205 static int32_t ahc_action(struct scsipi_xfer *); 206 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 207 struct proc *); 208 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 209 static int ahc_poll(struct ahc_softc *, int); 210 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 211 struct scb *); 212 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 213 static void ahcallocscbs(struct ahc_softc *); 214 #if UNUSED 215 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 216 struct scb *); 217 #endif 218 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 219 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 220 char, role_t); 221 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 222 static void ahc_done(struct ahc_softc *, struct scb *); 223 static struct tmode_tstate * 224 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 225 #if UNUSED 226 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 227 #endif 228 static void ahc_handle_seqint(struct ahc_softc *, u_int); 229 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 230 static void ahc_build_transfer_msg(struct ahc_softc *, 231 struct ahc_devinfo *); 232 static void ahc_setup_initiator_msgout(struct ahc_softc *, 233 struct ahc_devinfo *, 234 struct scb *); 235 static void ahc_setup_target_msgin(struct ahc_softc *, 236 struct ahc_devinfo *); 237 static void ahc_clear_msg_state(struct ahc_softc *); 238 static void ahc_handle_message_phase(struct ahc_softc *, 239 struct scsipi_link *); 240 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 241 242 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 243 struct ahc_devinfo *); 244 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 245 struct ahc_devinfo *); 246 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 247 int, char *, int); 248 #ifdef AHC_DUMP_SEQ 249 static void ahc_dumpseq(struct ahc_softc *); 250 #endif 251 static void ahc_loadseq(struct ahc_softc *); 252 static int ahc_check_patch(struct ahc_softc *, struct patch **, 253 int, int *); 254 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 255 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 256 #if defined(AHC_DEBUG) 257 static void ahc_print_scb(struct scb *); 258 #endif 259 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 260 role_t, scb_flag, ahc_search_action); 261 static int ahc_reset_channel(struct ahc_softc *, char, int); 262 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 263 role_t, int); 264 static int ahc_search_disc_list(struct ahc_softc *, int, 265 char, int, u_int, int, int, int); 266 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 267 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 268 static void ahc_clear_intstat(struct ahc_softc *); 269 static void ahc_reset_current_bus(struct ahc_softc *); 270 static struct ahc_syncrate * 271 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 272 static struct ahc_syncrate * 273 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 274 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 275 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 276 u_int *, int); 277 static void ahc_update_target_msg_request(struct ahc_softc *, 278 struct ahc_devinfo *, 279 struct ahc_initiator_tinfo *, 280 int, int); 281 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 282 struct ahc_syncrate *, u_int, u_int, u_int, 283 int, int); 284 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 285 u_int, u_int, int, int); 286 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 287 int); 288 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 289 290 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 291 292 static void ahc_calc_residual(struct scb *); 293 294 static void ahc_update_pending_syncrates(struct ahc_softc *); 295 296 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 297 298 static void ahc_timeout (void *); 299 static __inline int sequencer_paused(struct ahc_softc *); 300 static __inline void pause_sequencer(struct ahc_softc *); 301 static __inline void unpause_sequencer(struct ahc_softc *); 302 static void restart_sequencer(struct ahc_softc *); 303 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 304 305 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 306 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 307 308 static __inline void ahc_freeze_ccb(struct scb *); 309 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 310 static void ahc_run_qoutfifo(struct ahc_softc *); 311 312 static __inline struct ahc_initiator_tinfo * 313 ahc_fetch_transinfo(struct ahc_softc *, 314 char, u_int, u_int, 315 struct tmode_tstate **); 316 static void ahcfreescb(struct ahc_softc *, struct scb *); 317 static __inline struct scb *ahcgetscb(struct ahc_softc *); 318 319 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 320 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 321 int *, const char *, const char *); 322 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 323 caddr_t, bus_dma_segment_t *, int); 324 static void ahcminphys(struct buf *); 325 326 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 327 static __inline void ahc_swap_hscb(struct hardware_scb *); 328 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 329 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 330 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 331 332 #if defined(AHC_DEBUG) && 0 333 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 334 #endif 335 336 static struct scsipi_device ahc_dev = 337 { 338 NULL, /* Use default error handler */ 339 NULL, /* have a queue, served by this */ 340 NULL, /* have no async handler */ 341 NULL, /* Use default 'done' routine */ 342 }; 343 344 /* 345 * Pick the first xs for a non-blocked target. 346 */ 347 static __inline struct scsipi_xfer * 348 ahc_first_xs(struct ahc_softc *ahc) 349 { 350 int target; 351 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 352 353 if (ahc->queue_blocked) 354 return NULL; 355 356 while (xs != NULL) { 357 target = xs->sc_link->scsipi_scsi.target; 358 if (ahc->devqueue_blocked[target] == 0 && 359 (ahc_istagged_device(ahc, xs, 0) || 360 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 361 SCB_LIST_NULL)) 362 break; 363 xs = TAILQ_NEXT(xs, adapter_q); 364 } 365 366 return xs; 367 } 368 369 static __inline void 370 ahc_swap_hscb(struct hardware_scb *hscb) 371 { 372 hscb->SG_pointer = htole32(hscb->SG_pointer); 373 hscb->data = htole32(hscb->data); 374 hscb->datalen = htole32(hscb->datalen); 375 /* 376 * No need to swap cmdpointer; it's either 0 or set to 377 * cmdstore_busaddr, which is already swapped. 378 */ 379 } 380 381 static __inline void 382 ahc_swap_sg(struct ahc_dma_seg *sg) 383 { 384 sg->addr = htole32(sg->addr); 385 sg->len = htole32(sg->len); 386 } 387 388 static void 389 ahcminphys(bp) 390 struct buf *bp; 391 { 392 /* 393 * Even though the card can transfer up to 16megs per command 394 * we are limited by the number of segments in the dma segment 395 * list that we can hold. The worst case is that all pages are 396 * discontinuous physically, hense the "page per segment" limit 397 * enforced here. 398 */ 399 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 400 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 401 } 402 minphys(bp); 403 } 404 405 406 static __inline u_int32_t 407 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 408 { 409 return (ahc->scb_data->hscb_busaddr 410 + (sizeof(struct hardware_scb) * index)); 411 } 412 413 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 414 415 static __inline int 416 sequencer_paused(struct ahc_softc *ahc) 417 { 418 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 419 } 420 421 static __inline void 422 pause_sequencer(struct ahc_softc *ahc) 423 { 424 ahc_outb(ahc, HCNTRL, ahc->pause); 425 426 /* 427 * Since the sequencer can disable pausing in a critical section, we 428 * must loop until it actually stops. 429 */ 430 while (sequencer_paused(ahc) == 0) 431 ; 432 } 433 434 static __inline void 435 unpause_sequencer(struct ahc_softc *ahc) 436 { 437 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 438 ahc_outb(ahc, HCNTRL, ahc->unpause); 439 } 440 441 /* 442 * Restart the sequencer program from address zero 443 */ 444 static void 445 restart_sequencer(struct ahc_softc *ahc) 446 { 447 u_int i; 448 449 pause_sequencer(ahc); 450 451 /* 452 * Everytime we restart the sequencer, there 453 * is the possiblitity that we have restarted 454 * within a three instruction window where an 455 * SCB has been marked free but has not made it 456 * onto the free list. Since SCSI events(bus reset, 457 * unexpected bus free) will always freeze the 458 * sequencer, we cannot close this window. To 459 * avoid losing an SCB, we reconsitute the free 460 * list every time we restart the sequencer. 461 */ 462 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 463 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 464 465 ahc_outb(ahc, SCBPTR, i); 466 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 467 ahc_add_curscb_to_free_list(ahc); 468 } 469 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 470 unpause_sequencer(ahc); 471 } 472 473 static __inline u_int 474 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 475 { 476 u_int scbid; 477 478 scbid = ahc->untagged_scbs[tcl]; 479 if (unbusy) { 480 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 481 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 482 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 483 } 484 485 return (scbid); 486 } 487 488 static __inline void 489 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 490 { 491 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 492 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 493 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 494 } 495 496 static __inline int 497 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 498 { 499 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 500 } 501 502 static __inline void 503 ahc_freeze_ccb(struct scb *scb) 504 { 505 struct scsipi_xfer *xs = scb->xs; 506 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 507 int target; 508 509 target = xs->sc_link->scsipi_scsi.target; 510 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 511 ahc->devqueue_blocked[target]++; 512 scb->flags |= SCB_FREEZE_QUEUE; 513 } 514 } 515 516 static __inline void 517 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 518 { 519 xs->error = status; 520 } 521 522 static __inline struct ahc_initiator_tinfo * 523 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 524 u_int remote_id, struct tmode_tstate **tstate) 525 { 526 /* 527 * Transfer data structures are stored from the perspective 528 * of the target role. Since the parameters for a connection 529 * in the initiator role to a given target are the same as 530 * when the roles are reversed, we pretend we are the target. 531 */ 532 if (channel == 'B') 533 our_id += 8; 534 *tstate = ahc->enabled_targets[our_id]; 535 return (&(*tstate)->transinfo[remote_id]); 536 } 537 538 static void 539 ahc_run_qoutfifo(struct ahc_softc *ahc) 540 { 541 struct scb *scb; 542 u_int scb_index; 543 544 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 545 256, BUS_DMASYNC_POSTREAD); 546 547 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 548 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 549 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 550 551 scb = &ahc->scb_data->scbarray[scb_index]; 552 if (scb_index >= ahc->scb_data->numscbs 553 || (scb->flags & SCB_ACTIVE) == 0) { 554 printf("%s: WARNING no command for scb %d " 555 "(cmdcmplt)\nQOUTPOS = %d\n", 556 ahc_name(ahc), scb_index, 557 ahc->qoutfifonext - 1); 558 continue; 559 } 560 561 /* 562 * Save off the residual 563 * if there is one. 564 */ 565 if (scb->hscb->residual_SG_count != 0) 566 ahc_calc_residual(scb); 567 else 568 scb->xs->resid = 0; 569 #ifdef AHC_DEBUG 570 if (ahc_debug & AHC_SHOWSCBS) { 571 scsi_print_addr(scb->xs->sc_link); 572 printf("run_qoutfifo: SCB %x complete\n", 573 scb->hscb->tag); 574 } 575 #endif 576 ahc_done(ahc, scb); 577 } 578 } 579 580 581 /* 582 * An scb (and hence an scb entry on the board) is put onto the 583 * free list. 584 */ 585 static void 586 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 587 { 588 struct hardware_scb *hscb; 589 int opri; 590 591 hscb = scb->hscb; 592 593 #ifdef AHC_DEBUG 594 if (ahc_debug & AHC_SHOWSCBALLOC) 595 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 596 #endif 597 598 opri = splbio(); 599 600 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 601 (scb->flags & SCB_RECOVERY_SCB) != 0) { 602 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 603 ahc->queue_blocked = 0; 604 } 605 606 /* Clean up for the next user */ 607 scb->flags = SCB_FREE; 608 hscb->control = 0; 609 hscb->status = 0; 610 611 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 612 613 splx(opri); 614 } 615 616 /* 617 * Get a free scb, either one already assigned to a hardware slot 618 * on the adapter or one that will require an SCB to be paged out before 619 * use. If there are none, see if we can allocate a new SCB. Otherwise 620 * either return an error or sleep. 621 */ 622 static __inline struct scb * 623 ahcgetscb(struct ahc_softc *ahc) 624 { 625 struct scb *scbp; 626 int opri;; 627 628 opri = splbio(); 629 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 630 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 631 } else { 632 ahcallocscbs(ahc); 633 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 634 if (scbp != NULL) 635 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 636 } 637 638 splx(opri); 639 640 #ifdef AHC_DEBUG 641 if (ahc_debug & AHC_SHOWSCBALLOC) { 642 if (scbp != NULL) 643 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 644 scbp->hscb->tag); 645 else 646 printf("%s: failed to allocate new SCB\n", 647 ahc_name(ahc)); 648 } 649 #endif 650 651 return (scbp); 652 } 653 654 static int 655 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 656 bus_dma_tag_t tag; 657 int size; 658 int flags; 659 bus_dmamap_t *mapp; 660 caddr_t *vaddr; 661 bus_addr_t *baddr; 662 bus_dma_segment_t *seg; 663 int *nseg; 664 const char *myname, *what; 665 { 666 int error, level = 0; 667 668 if ((error = bus_dmamem_alloc(tag, size, NBPG, 0, 669 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 670 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 671 myname, what, error); 672 goto out; 673 } 674 level++; 675 676 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 677 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 678 printf("%s: failed to map DMA mem for %s, error = %d\n", 679 myname, what, error); 680 goto out; 681 } 682 level++; 683 684 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 685 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 686 printf("%s: failed to create DMA map for %s, error = %d\n", 687 myname, what, error); 688 goto out; 689 } 690 level++; 691 692 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 693 BUS_DMA_NOWAIT)) != 0) { 694 printf("%s: failed to load DMA map for %s, error = %d\n", 695 myname, what, error); 696 goto out; 697 } 698 699 *baddr = (*mapp)->dm_segs[0].ds_addr; 700 701 #ifdef AHC_DEBUG 702 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 703 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 704 *nseg, size); 705 #endif 706 707 return 0; 708 out: 709 switch (level) { 710 case 3: 711 bus_dmamap_destroy(tag, *mapp); 712 /* FALLTHROUGH */ 713 case 2: 714 bus_dmamem_unmap(tag, *vaddr, size); 715 /* FALLTHROUGH */ 716 case 1: 717 bus_dmamem_free(tag, seg, *nseg); 718 break; 719 default: 720 break; 721 } 722 723 return error; 724 } 725 726 static void 727 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 728 bus_dma_tag_t tag; 729 int size; 730 bus_dmamap_t map; 731 caddr_t vaddr; 732 bus_dma_segment_t *seg; 733 int nseg; 734 { 735 736 bus_dmamap_unload(tag, map); 737 bus_dmamap_destroy(tag, map); 738 bus_dmamem_unmap(tag, vaddr, size); 739 bus_dmamem_free(tag, seg, nseg); 740 } 741 742 char * 743 ahc_name(struct ahc_softc *ahc) 744 { 745 return (ahc->sc_dev.dv_xname); 746 } 747 748 #ifdef AHC_DEBUG 749 static void 750 ahc_print_scb(struct scb *scb) 751 { 752 struct hardware_scb *hscb = scb->hscb; 753 754 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 755 scb, 756 hscb->tag, 757 hscb->control, 758 hscb->tcl, 759 hscb->cmdlen, 760 (unsigned long)le32toh(hscb->cmdpointer)); 761 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 762 le32toh(hscb->datalen), 763 (unsigned long)(le32toh(hscb->data)), 764 hscb->SG_count, 765 (unsigned long)(le32toh(hscb->SG_pointer))); 766 printf(" sg_addr:%lx sg_len:%lu\n", 767 (unsigned long)(le32toh(scb->sg_list[0].addr)), 768 (unsigned long)(le32toh(scb->sg_list[0].len))); 769 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 770 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 771 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 772 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 773 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 774 } 775 #endif 776 777 static struct { 778 u_int8_t errno; 779 char *errmesg; 780 } hard_error[] = { 781 { ILLHADDR, "Illegal Host Access" }, 782 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 783 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 784 { SQPARERR, "Sequencer Parity Error" }, 785 { DPARERR, "Data-path Parity Error" }, 786 { MPARERR, "Scratch or SCB Memory Parity Error" }, 787 { PCIERRSTAT, "PCI Error detected" }, 788 { CIOPARERR, "CIOBUS Parity Error" }, 789 }; 790 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 791 792 static struct { 793 u_int8_t phase; 794 u_int8_t mesg_out; /* Message response to parity errors */ 795 char *phasemsg; 796 } phase_table[] = { 797 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 798 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 799 { P_COMMAND, MSG_NOOP, "in Command phase" }, 800 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 801 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 802 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 803 { P_BUSFREE, MSG_NOOP, "while idle" }, 804 { 0, MSG_NOOP, "in unknown phase" } 805 }; 806 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 807 808 /* 809 * Valid SCSIRATE values. (p. 3-17) 810 * Provides a mapping of tranfer periods in ns to the proper value to 811 * stick in the scsiscfr reg to use that transfer rate. 812 */ 813 #define AHC_SYNCRATE_DT 0 814 #define AHC_SYNCRATE_ULTRA2 1 815 #define AHC_SYNCRATE_ULTRA 3 816 #define AHC_SYNCRATE_FAST 6 817 static struct ahc_syncrate ahc_syncrates[] = { 818 /* ultra2 fast/ultra period rate */ 819 { 0x42, 0x000, 9, "80.0" }, 820 { 0x03, 0x000, 10, "40.0" }, 821 { 0x04, 0x000, 11, "33.0" }, 822 { 0x05, 0x100, 12, "20.0" }, 823 { 0x06, 0x110, 15, "16.0" }, 824 { 0x07, 0x120, 18, "13.4" }, 825 { 0x08, 0x000, 25, "10.0" }, 826 { 0x19, 0x010, 31, "8.0" }, 827 { 0x1a, 0x020, 37, "6.67" }, 828 { 0x1b, 0x030, 43, "5.7" }, 829 { 0x1c, 0x040, 50, "5.0" }, 830 { 0x00, 0x050, 56, "4.4" }, 831 { 0x00, 0x060, 62, "4.0" }, 832 { 0x00, 0x070, 68, "3.6" }, 833 { 0x00, 0x000, 0, NULL } 834 }; 835 836 /* 837 * Allocate a controller structure for a new device and initialize it. 838 */ 839 int 840 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 841 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 842 ahc_flag flags) 843 { 844 struct scb_data *scb_data; 845 846 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 847 if (scb_data == NULL) { 848 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 849 return -1; 850 } 851 bzero(scb_data, sizeof (struct scb_data)); 852 LIST_INIT(&ahc->pending_ccbs); 853 ahc->tag = st; 854 ahc->bsh = sh; 855 ahc->parent_dmat = parent_dmat; 856 ahc->chip = chip; 857 ahc->features = features; 858 ahc->flags = flags; 859 ahc->scb_data = scb_data; 860 861 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 862 /* The IRQMS bit is only valid on VL and EISA chips */ 863 if ((ahc->chip & AHC_PCI) != 0) 864 ahc->unpause &= ~IRQMS; 865 ahc->pause = ahc->unpause | PAUSE; 866 return (0); 867 } 868 869 void 870 ahc_free(ahc) 871 struct ahc_softc *ahc; 872 { 873 ahcfiniscbdata(ahc); 874 if (ahc->init_level != 0) 875 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 876 ahc->shared_data_dmamap, ahc->qoutfifo, 877 &ahc->shared_data_seg, ahc->shared_data_nseg); 878 879 if (ahc->scb_data != NULL) 880 free(ahc->scb_data, M_DEVBUF); 881 if (ahc->bus_data != NULL) 882 free(ahc->bus_data, M_DEVBUF); 883 return; 884 } 885 886 static int 887 ahcinitscbdata(struct ahc_softc *ahc) 888 { 889 struct scb_data *scb_data; 890 int i; 891 892 scb_data = ahc->scb_data; 893 SLIST_INIT(&scb_data->free_scbs); 894 SLIST_INIT(&scb_data->sg_maps); 895 896 /* Allocate SCB resources */ 897 scb_data->scbarray = 898 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 899 M_DEVBUF, M_NOWAIT); 900 if (scb_data->scbarray == NULL) 901 return (ENOMEM); 902 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 903 904 /* Determine the number of hardware SCBs and initialize them */ 905 906 scb_data->maxhscbs = ahc_probe_scbs(ahc); 907 /* SCB 0 heads the free list */ 908 ahc_outb(ahc, FREE_SCBH, 0); 909 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 910 ahc_outb(ahc, SCBPTR, i); 911 912 /* Clear the control byte. */ 913 ahc_outb(ahc, SCB_CONTROL, 0); 914 915 /* Set the next pointer */ 916 ahc_outb(ahc, SCB_NEXT, i+1); 917 918 /* Make the tag number invalid */ 919 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 920 } 921 922 /* Make sure that the last SCB terminates the free list */ 923 ahc_outb(ahc, SCBPTR, i-1); 924 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 925 926 /* Ensure we clear the 0 SCB's control byte. */ 927 ahc_outb(ahc, SCBPTR, 0); 928 ahc_outb(ahc, SCB_CONTROL, 0); 929 930 scb_data->maxhscbs = i; 931 932 if (ahc->scb_data->maxhscbs == 0) 933 panic("%s: No SCB space found", ahc_name(ahc)); 934 935 /* 936 * Create our DMA tags. These tags define the kinds of device 937 * accessable memory allocations and memory mappings we will 938 * need to perform during normal operation. 939 * 940 * Unless we need to further restrict the allocation, we rely 941 * on the restrictions of the parent dmat, hence the common 942 * use of MAXADDR and MAXSIZE. 943 */ 944 945 if (ahc_createdmamem(ahc->parent_dmat, 946 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 947 &scb_data->hscb_dmamap, 948 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 949 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 950 "hardware SCB structures") < 0) 951 goto error_exit; 952 953 scb_data->init_level++; 954 955 if (ahc_createdmamem(ahc->parent_dmat, 956 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 957 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 958 &scb_data->sense_busaddr, &scb_data->sense_seg, 959 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 960 goto error_exit; 961 962 scb_data->init_level++; 963 964 /* Perform initial CCB allocation */ 965 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 966 ahcallocscbs(ahc); 967 968 if (scb_data->numscbs == 0) { 969 printf("%s: ahc_init_scb_data - " 970 "Unable to allocate initial scbs\n", 971 ahc_name(ahc)); 972 goto error_exit; 973 } 974 975 scb_data->init_level++; 976 977 /* 978 * Note that we were successfull 979 */ 980 return 0; 981 982 error_exit: 983 984 return ENOMEM; 985 } 986 987 static void 988 ahcfiniscbdata(struct ahc_softc *ahc) 989 { 990 struct scb_data *scb_data; 991 992 scb_data = ahc->scb_data; 993 994 switch (scb_data->init_level) { 995 default: 996 case 3: 997 { 998 struct sg_map_node *sg_map; 999 1000 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1001 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1002 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1003 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1004 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1005 free(sg_map, M_DEVBUF); 1006 } 1007 } 1008 /*FALLTHROUGH*/ 1009 case 2: 1010 ahc_freedmamem(ahc->parent_dmat, 1011 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1012 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1013 &scb_data->sense_seg, scb_data->sense_nseg); 1014 /*FALLTHROUGH*/ 1015 case 1: 1016 ahc_freedmamem(ahc->parent_dmat, 1017 AHC_SCB_MAX * sizeof(struct hardware_scb), 1018 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1019 &scb_data->hscb_seg, scb_data->hscb_nseg); 1020 /*FALLTHROUGH*/ 1021 } 1022 if (scb_data->scbarray != NULL) 1023 free(scb_data->scbarray, M_DEVBUF); 1024 } 1025 1026 int 1027 ahc_reset(struct ahc_softc *ahc) 1028 { 1029 u_int sblkctl; 1030 int wait; 1031 1032 #ifdef AHC_DUMP_SEQ 1033 if (ahc->init_level == 0) 1034 ahc_dumpseq(ahc); 1035 #endif 1036 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1037 /* 1038 * Ensure that the reset has finished 1039 */ 1040 wait = 1000; 1041 do { 1042 DELAY(1000); 1043 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1044 1045 if (wait == 0) { 1046 printf("%s: WARNING - Failed chip reset! " 1047 "Trying to initialize anyway.\n", ahc_name(ahc)); 1048 } 1049 ahc_outb(ahc, HCNTRL, ahc->pause); 1050 1051 /* Determine channel configuration */ 1052 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1053 /* No Twin Channel PCI cards */ 1054 if ((ahc->chip & AHC_PCI) != 0) 1055 sblkctl &= ~SELBUSB; 1056 switch (sblkctl) { 1057 case 0: 1058 /* Single Narrow Channel */ 1059 break; 1060 case 2: 1061 /* Wide Channel */ 1062 ahc->features |= AHC_WIDE; 1063 break; 1064 case 8: 1065 /* Twin Channel */ 1066 ahc->features |= AHC_TWIN; 1067 break; 1068 default: 1069 printf(" Unsupported adapter type. Ignoring\n"); 1070 return(-1); 1071 } 1072 1073 return (0); 1074 } 1075 1076 /* 1077 * Called when we have an active connection to a target on the bus, 1078 * this function finds the nearest syncrate to the input period limited 1079 * by the capabilities of the bus connectivity of the target. 1080 */ 1081 static struct ahc_syncrate * 1082 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1083 u_int maxsync; 1084 1085 if ((ahc->features & AHC_ULTRA2) != 0) { 1086 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1087 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1088 maxsync = AHC_SYNCRATE_ULTRA2; 1089 } else { 1090 maxsync = AHC_SYNCRATE_ULTRA; 1091 } 1092 } else if ((ahc->features & AHC_ULTRA) != 0) { 1093 maxsync = AHC_SYNCRATE_ULTRA; 1094 } else { 1095 maxsync = AHC_SYNCRATE_FAST; 1096 } 1097 return (ahc_find_syncrate(ahc, period, maxsync)); 1098 } 1099 1100 /* 1101 * Look up the valid period to SCSIRATE conversion in our table. 1102 * Return the period and offset that should be sent to the target 1103 * if this was the beginning of an SDTR. 1104 */ 1105 static struct ahc_syncrate * 1106 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1107 { 1108 struct ahc_syncrate *syncrate; 1109 1110 syncrate = &ahc_syncrates[maxsync]; 1111 while ((syncrate->rate != NULL) 1112 && ((ahc->features & AHC_ULTRA2) == 0 1113 || (syncrate->sxfr_u2 != 0))) { 1114 1115 if (*period <= syncrate->period) { 1116 /* 1117 * When responding to a target that requests 1118 * sync, the requested rate may fall between 1119 * two rates that we can output, but still be 1120 * a rate that we can receive. Because of this, 1121 * we want to respond to the target with 1122 * the same rate that it sent to us even 1123 * if the period we use to send data to it 1124 * is lower. Only lower the response period 1125 * if we must. 1126 */ 1127 if (syncrate == &ahc_syncrates[maxsync]) 1128 *period = syncrate->period; 1129 break; 1130 } 1131 syncrate++; 1132 } 1133 1134 if ((*period == 0) 1135 || (syncrate->rate == NULL) 1136 || ((ahc->features & AHC_ULTRA2) != 0 1137 && (syncrate->sxfr_u2 == 0))) { 1138 /* Use asynchronous transfers. */ 1139 *period = 0; 1140 syncrate = NULL; 1141 } 1142 return (syncrate); 1143 } 1144 1145 static u_int 1146 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1147 { 1148 struct ahc_syncrate *syncrate; 1149 1150 if ((ahc->features & AHC_ULTRA2) != 0) 1151 scsirate &= SXFR_ULTRA2; 1152 else 1153 scsirate &= SXFR; 1154 1155 syncrate = &ahc_syncrates[maxsync]; 1156 while (syncrate->rate != NULL) { 1157 1158 if ((ahc->features & AHC_ULTRA2) != 0) { 1159 if (syncrate->sxfr_u2 == 0) 1160 break; 1161 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1162 return (syncrate->period); 1163 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1164 return (syncrate->period); 1165 } 1166 syncrate++; 1167 } 1168 return (0); /* async */ 1169 } 1170 1171 static void 1172 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1173 u_int *offset, int wide) 1174 { 1175 u_int maxoffset; 1176 1177 /* Limit offset to what we can do */ 1178 if (syncrate == NULL) { 1179 maxoffset = 0; 1180 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1181 maxoffset = MAX_OFFSET_ULTRA2; 1182 } else { 1183 if (wide) 1184 maxoffset = MAX_OFFSET_16BIT; 1185 else 1186 maxoffset = MAX_OFFSET_8BIT; 1187 } 1188 *offset = MIN(*offset, maxoffset); 1189 } 1190 1191 static void 1192 ahc_update_target_msg_request(struct ahc_softc *ahc, 1193 struct ahc_devinfo *devinfo, 1194 struct ahc_initiator_tinfo *tinfo, 1195 int force, int paused) 1196 { 1197 u_int targ_msg_req_orig; 1198 1199 targ_msg_req_orig = ahc->targ_msg_req; 1200 if (tinfo->current.period != tinfo->goal.period 1201 || tinfo->current.width != tinfo->goal.width 1202 || tinfo->current.offset != tinfo->goal.offset 1203 || (force 1204 && (tinfo->goal.period != 0 1205 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1206 ahc->targ_msg_req |= devinfo->target_mask; 1207 } else { 1208 ahc->targ_msg_req &= ~devinfo->target_mask; 1209 } 1210 1211 if (ahc->targ_msg_req != targ_msg_req_orig) { 1212 /* Update the message request bit for this target */ 1213 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1214 if (paused) { 1215 ahc_outb(ahc, TARGET_MSG_REQUEST, 1216 ahc->targ_msg_req & 0xFF); 1217 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1218 (ahc->targ_msg_req >> 8) & 0xFF); 1219 } else { 1220 ahc_outb(ahc, HS_MAILBOX, 1221 0x01 << HOST_MAILBOX_SHIFT); 1222 } 1223 } else { 1224 if (!paused) 1225 pause_sequencer(ahc); 1226 1227 ahc_outb(ahc, TARGET_MSG_REQUEST, 1228 ahc->targ_msg_req & 0xFF); 1229 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1230 (ahc->targ_msg_req >> 8) & 0xFF); 1231 1232 if (!paused) 1233 unpause_sequencer(ahc); 1234 } 1235 } 1236 } 1237 1238 static void 1239 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1240 struct ahc_syncrate *syncrate, 1241 u_int period, u_int offset, u_int type, int paused, int done) 1242 { 1243 struct ahc_initiator_tinfo *tinfo; 1244 struct tmode_tstate *tstate; 1245 u_int old_period; 1246 u_int old_offset; 1247 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1248 1249 if (syncrate == NULL) { 1250 period = 0; 1251 offset = 0; 1252 } 1253 1254 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1255 devinfo->target, &tstate); 1256 old_period = tinfo->current.period; 1257 old_offset = tinfo->current.offset; 1258 1259 if ((type & AHC_TRANS_CUR) != 0 1260 && (old_period != period || old_offset != offset)) { 1261 u_int scsirate; 1262 1263 scsirate = tinfo->scsirate; 1264 if ((ahc->features & AHC_ULTRA2) != 0) { 1265 1266 /* XXX */ 1267 /* Force single edge until DT is fully implemented */ 1268 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1269 if (syncrate != NULL) 1270 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1271 1272 if (active) 1273 ahc_outb(ahc, SCSIOFFSET, offset); 1274 } else { 1275 1276 scsirate &= ~(SXFR|SOFS); 1277 /* 1278 * Ensure Ultra mode is set properly for 1279 * this target. 1280 */ 1281 tstate->ultraenb &= ~devinfo->target_mask; 1282 if (syncrate != NULL) { 1283 if (syncrate->sxfr & ULTRA_SXFR) { 1284 tstate->ultraenb |= 1285 devinfo->target_mask; 1286 } 1287 scsirate |= syncrate->sxfr & SXFR; 1288 scsirate |= offset & SOFS; 1289 } 1290 if (active) { 1291 u_int sxfrctl0; 1292 1293 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1294 sxfrctl0 &= ~FAST20; 1295 if (tstate->ultraenb & devinfo->target_mask) 1296 sxfrctl0 |= FAST20; 1297 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1298 } 1299 } 1300 if (active) 1301 ahc_outb(ahc, SCSIRATE, scsirate); 1302 1303 tinfo->scsirate = scsirate; 1304 tinfo->current.period = period; 1305 tinfo->current.offset = offset; 1306 1307 /* Update the syncrates in any pending scbs */ 1308 ahc_update_pending_syncrates(ahc); 1309 } 1310 1311 /* 1312 * Print messages if we're verbose and at the end of a negotiation 1313 * cycle. 1314 */ 1315 if (done) { 1316 if (offset != 0) { 1317 printf("%s: target %d synchronous at %sMHz, " 1318 "offset = 0x%x\n", ahc_name(ahc), 1319 devinfo->target, syncrate->rate, offset); 1320 } else { 1321 printf("%s: target %d using " 1322 "asynchronous transfers\n", 1323 ahc_name(ahc), devinfo->target); 1324 } 1325 } 1326 1327 if ((type & AHC_TRANS_GOAL) != 0) { 1328 tinfo->goal.period = period; 1329 tinfo->goal.offset = offset; 1330 } 1331 1332 if ((type & AHC_TRANS_USER) != 0) { 1333 tinfo->user.period = period; 1334 tinfo->user.offset = offset; 1335 } 1336 1337 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1338 /*force*/FALSE, 1339 paused); 1340 } 1341 1342 static void 1343 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1344 u_int width, u_int type, int paused, int done) 1345 { 1346 struct ahc_initiator_tinfo *tinfo; 1347 struct tmode_tstate *tstate; 1348 u_int oldwidth; 1349 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1350 1351 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1352 devinfo->target, &tstate); 1353 oldwidth = tinfo->current.width; 1354 1355 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1356 u_int scsirate; 1357 1358 scsirate = tinfo->scsirate; 1359 scsirate &= ~WIDEXFER; 1360 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1361 scsirate |= WIDEXFER; 1362 1363 tinfo->scsirate = scsirate; 1364 1365 if (active) 1366 ahc_outb(ahc, SCSIRATE, scsirate); 1367 1368 tinfo->current.width = width; 1369 } 1370 1371 if (done) { 1372 printf("%s: target %d using %dbit transfers\n", 1373 ahc_name(ahc), devinfo->target, 1374 8 * (0x01 << width)); 1375 } 1376 1377 if ((type & AHC_TRANS_GOAL) != 0) 1378 tinfo->goal.width = width; 1379 if ((type & AHC_TRANS_USER) != 0) 1380 tinfo->user.width = width; 1381 1382 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1383 /*force*/FALSE, paused); 1384 } 1385 1386 static void 1387 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1388 { 1389 struct ahc_initiator_tinfo *tinfo; 1390 struct tmode_tstate *tstate; 1391 1392 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1393 devinfo->target, &tstate); 1394 1395 if (enable) 1396 tstate->tagenable |= devinfo->target_mask; 1397 else { 1398 tstate->tagenable &= ~devinfo->target_mask; 1399 tstate->tagdisable |= devinfo->target_mask; 1400 } 1401 } 1402 1403 /* 1404 * Attach all the sub-devices we can find 1405 */ 1406 int 1407 ahc_attach(struct ahc_softc *ahc) 1408 { 1409 TAILQ_INIT(&ahc->sc_q); 1410 1411 ahc->sc_adapter.scsipi_cmd = ahc_action; 1412 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1413 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1414 ahc->sc_link.type = BUS_SCSI; 1415 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1416 ahc->sc_link.scsipi_scsi.channel = 0; 1417 ahc->sc_link.scsipi_scsi.max_target = 1418 (ahc->features & AHC_WIDE) ? 15 : 7; 1419 ahc->sc_link.scsipi_scsi.max_lun = 7; 1420 ahc->sc_link.adapter_softc = ahc; 1421 ahc->sc_link.adapter = &ahc->sc_adapter; 1422 ahc->sc_link.openings = 2; 1423 ahc->sc_link.device = &ahc_dev; 1424 1425 if (ahc->features & AHC_TWIN) { 1426 ahc->sc_link_b = ahc->sc_link; 1427 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1428 ahc->sc_link_b.scsipi_scsi.channel = 1; 1429 } 1430 1431 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1432 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1433 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1434 if (ahc->features & AHC_TWIN) 1435 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1436 } else { 1437 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1438 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1439 } 1440 return 1; 1441 } 1442 1443 static void 1444 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1445 { 1446 u_int saved_tcl; 1447 role_t role; 1448 int our_id; 1449 1450 if (ahc_inb(ahc, SSTAT0) & TARGET) 1451 role = ROLE_TARGET; 1452 else 1453 role = ROLE_INITIATOR; 1454 1455 if (role == ROLE_TARGET 1456 && (ahc->features & AHC_MULTI_TID) != 0 1457 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1458 /* We were selected, so pull our id from TARGIDIN */ 1459 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1460 } else if ((ahc->features & AHC_ULTRA2) != 0) 1461 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1462 else 1463 our_id = ahc_inb(ahc, SCSIID) & OID; 1464 1465 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1466 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1467 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1468 role); 1469 } 1470 1471 static void 1472 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1473 u_int lun, char channel, role_t role) 1474 { 1475 devinfo->our_scsiid = our_id; 1476 devinfo->target = target; 1477 devinfo->lun = lun; 1478 devinfo->target_offset = target; 1479 devinfo->channel = channel; 1480 devinfo->role = role; 1481 if (channel == 'B') 1482 devinfo->target_offset += 8; 1483 devinfo->target_mask = (0x01 << devinfo->target_offset); 1484 } 1485 1486 /* 1487 * Catch an interrupt from the adapter 1488 */ 1489 int 1490 ahc_intr(void *arg) 1491 { 1492 struct ahc_softc *ahc; 1493 u_int intstat; 1494 1495 ahc = (struct ahc_softc *)arg; 1496 1497 intstat = ahc_inb(ahc, INTSTAT); 1498 1499 /* 1500 * Any interrupts to process? 1501 */ 1502 if ((intstat & INT_PEND) == 0) { 1503 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1504 #ifdef AHC_DEBUG 1505 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1506 ahc_name(ahc), 1507 ahc_inb(ahc, CCHADDR) | 1508 (ahc_inb(ahc, CCHADDR+1) << 8) 1509 | (ahc_inb(ahc, CCHADDR+2) << 16) 1510 | (ahc_inb(ahc, CCHADDR+3) << 24), 1511 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1512 | (ahc_inb(ahc, HADDR+2) << 16) 1513 | (ahc_inb(ahc, HADDR+3) << 24), 1514 ahc_inb(ahc, SEQADDR0) | 1515 (ahc_inb(ahc, SEQADDR1) << 8)); 1516 #endif 1517 return 1; 1518 } 1519 return 0; 1520 } 1521 1522 #ifdef AHC_DEBUG 1523 if (ahc_debug & AHC_SHOWINTR) { 1524 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1525 } 1526 #endif 1527 1528 if (intstat & CMDCMPLT) { 1529 ahc_outb(ahc, CLRINT, CLRCMDINT); 1530 ahc_run_qoutfifo(ahc); 1531 } 1532 if (intstat & BRKADRINT) { 1533 /* 1534 * We upset the sequencer :-( 1535 * Lookup the error message 1536 */ 1537 int i, error, num_errors; 1538 1539 error = ahc_inb(ahc, ERROR); 1540 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1541 for (i = 0; error != 1 && i < num_errors; i++) 1542 error >>= 1; 1543 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1544 ahc_name(ahc), hard_error[i].errmesg, 1545 ahc_inb(ahc, SEQADDR0) | 1546 (ahc_inb(ahc, SEQADDR1) << 8)); 1547 1548 /* Tell everyone that this HBA is no longer availible */ 1549 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1550 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1551 XS_DRIVER_STUFFUP); 1552 } 1553 if (intstat & SEQINT) 1554 ahc_handle_seqint(ahc, intstat); 1555 1556 if (intstat & SCSIINT) 1557 ahc_handle_scsiint(ahc, intstat); 1558 1559 return 1; 1560 } 1561 1562 static struct tmode_tstate * 1563 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1564 { 1565 struct tmode_tstate *master_tstate; 1566 struct tmode_tstate *tstate; 1567 int i, s; 1568 1569 master_tstate = ahc->enabled_targets[ahc->our_id]; 1570 if (channel == 'B') { 1571 scsi_id += 8; 1572 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1573 } 1574 if (ahc->enabled_targets[scsi_id] != NULL 1575 && ahc->enabled_targets[scsi_id] != master_tstate) 1576 panic("%s: ahc_alloc_tstate - Target already allocated", 1577 ahc_name(ahc)); 1578 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1579 if (tstate == NULL) 1580 return (NULL); 1581 1582 /* 1583 * If we have allocated a master tstate, copy user settings from 1584 * the master tstate (taken from SRAM or the EEPROM) for this 1585 * channel, but reset our current and goal settings to async/narrow 1586 * until an initiator talks to us. 1587 */ 1588 if (master_tstate != NULL) { 1589 bcopy(master_tstate, tstate, sizeof(*tstate)); 1590 tstate->ultraenb = 0; 1591 for (i = 0; i < 16; i++) { 1592 bzero(&tstate->transinfo[i].current, 1593 sizeof(tstate->transinfo[i].current)); 1594 bzero(&tstate->transinfo[i].goal, 1595 sizeof(tstate->transinfo[i].goal)); 1596 } 1597 } else 1598 bzero(tstate, sizeof(*tstate)); 1599 s = splbio(); 1600 ahc->enabled_targets[scsi_id] = tstate; 1601 splx(s); 1602 return (tstate); 1603 } 1604 1605 #if UNUSED 1606 static void 1607 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1608 { 1609 struct tmode_tstate *tstate; 1610 1611 /* Don't clean up the entry for our initiator role */ 1612 if ((ahc->flags & AHC_INITIATORMODE) != 0 1613 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1614 || (channel == 'A' && scsi_id == ahc->our_id)) 1615 && force == FALSE) 1616 return; 1617 1618 if (channel == 'B') 1619 scsi_id += 8; 1620 tstate = ahc->enabled_targets[scsi_id]; 1621 if (tstate != NULL) 1622 free(tstate, M_DEVBUF); 1623 ahc->enabled_targets[scsi_id] = NULL; 1624 } 1625 #endif 1626 1627 static void 1628 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1629 { 1630 struct scb *scb; 1631 struct ahc_devinfo devinfo; 1632 1633 ahc_fetch_devinfo(ahc, &devinfo); 1634 1635 /* 1636 * Clear the upper byte that holds SEQINT status 1637 * codes and clear the SEQINT bit. We will unpause 1638 * the sequencer, if appropriate, after servicing 1639 * the request. 1640 */ 1641 ahc_outb(ahc, CLRINT, CLRSEQINT); 1642 switch (intstat & SEQINT_MASK) { 1643 case NO_MATCH: 1644 { 1645 /* Ensure we don't leave the selection hardware on */ 1646 ahc_outb(ahc, SCSISEQ, 1647 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1648 1649 printf("%s:%c:%d: no active SCB for reconnecting " 1650 "target - issuing BUS DEVICE RESET\n", 1651 ahc_name(ahc), devinfo.channel, devinfo.target); 1652 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1653 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1654 ahc_inb(ahc, SEQ_FLAGS)); 1655 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1656 ahc->msgout_len = 1; 1657 ahc->msgout_index = 0; 1658 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1659 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1660 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1661 break; 1662 } 1663 case UPDATE_TMSG_REQ: 1664 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1665 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1666 (ahc->targ_msg_req >> 8) & 0xFF); 1667 ahc_outb(ahc, HS_MAILBOX, 0); 1668 break; 1669 case SEND_REJECT: 1670 { 1671 u_int rejbyte = ahc_inb(ahc, ACCUM); 1672 printf("%s:%c:%d: Warning - unknown message received from " 1673 "target (0x%x). Rejecting\n", 1674 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1675 break; 1676 } 1677 case NO_IDENT: 1678 { 1679 /* 1680 * The reconnecting target either did not send an identify 1681 * message, or did, but we didn't find and SCB to match and 1682 * before it could respond to our ATN/abort, it hit a dataphase. 1683 * The only safe thing to do is to blow it away with a bus 1684 * reset. 1685 */ 1686 int found; 1687 1688 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1689 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1690 ahc_name(ahc), devinfo.channel, devinfo.target, 1691 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1692 found = ahc_reset_channel(ahc, devinfo.channel, 1693 /*initiate reset*/TRUE); 1694 printf("%s: Issued Channel %c Bus Reset. " 1695 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1696 found); 1697 return; 1698 } 1699 case BAD_PHASE: 1700 { 1701 u_int lastphase; 1702 1703 lastphase = ahc_inb(ahc, LASTPHASE); 1704 if (lastphase == P_BUSFREE) { 1705 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1706 ahc_name(ahc), devinfo.channel, devinfo.target, 1707 ahc_inb(ahc, SCSISIGI)); 1708 restart_sequencer(ahc); 1709 return; 1710 } else { 1711 printf("%s:%c:%d: unknown scsi bus phase %x. " 1712 "Attempting to continue\n", 1713 ahc_name(ahc), devinfo.channel, devinfo.target, 1714 ahc_inb(ahc, SCSISIGI)); 1715 } 1716 break; 1717 } 1718 case BAD_STATUS: 1719 { 1720 u_int scb_index; 1721 struct hardware_scb *hscb; 1722 struct scsipi_xfer *xs; 1723 /* 1724 * The sequencer will notify us when a command 1725 * has an error that would be of interest to 1726 * the kernel. This allows us to leave the sequencer 1727 * running in the common case of command completes 1728 * without error. The sequencer will already have 1729 * dma'd the SCB back up to us, so we can reference 1730 * the in kernel copy directly. 1731 */ 1732 scb_index = ahc_inb(ahc, SCB_TAG); 1733 scb = &ahc->scb_data->scbarray[scb_index]; 1734 1735 /* ahc_print_scb(scb); */ 1736 1737 /* 1738 * Set the default return value to 0 (don't 1739 * send sense). The sense code will change 1740 * this if needed. 1741 */ 1742 ahc_outb(ahc, RETURN_1, 0); 1743 if (!(scb_index < ahc->scb_data->numscbs 1744 && (scb->flags & SCB_ACTIVE) != 0)) { 1745 printf("%s:%c:%d: ahc_intr - referenced scb " 1746 "not valid during seqint 0x%x scb(%d)\n", 1747 ahc_name(ahc), devinfo.channel, 1748 devinfo.target, intstat, scb_index); 1749 goto unpause; 1750 } 1751 1752 hscb = scb->hscb; 1753 xs = scb->xs; 1754 1755 /* Don't want to clobber the original sense code */ 1756 if ((scb->flags & SCB_SENSE) != 0) { 1757 /* 1758 * Clear the SCB_SENSE Flag and have 1759 * the sequencer do a normal command 1760 * complete. 1761 */ 1762 scb->flags &= ~SCB_SENSE; 1763 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1764 break; 1765 } 1766 /* Freeze the queue unit the client sees the error. */ 1767 ahc_freeze_devq(ahc, xs->sc_link); 1768 ahc_freeze_ccb(scb); 1769 xs->status = hscb->status; 1770 switch (hscb->status) { 1771 case SCSI_STATUS_OK: 1772 printf("%s: Interrupted for status of 0???\n", 1773 ahc_name(ahc)); 1774 break; 1775 case SCSI_STATUS_CMD_TERMINATED: 1776 case SCSI_STATUS_CHECK_COND: 1777 #if defined(AHC_DEBUG) 1778 if (ahc_debug & AHC_SHOWSENSE) { 1779 scsi_print_addr(xs->sc_link); 1780 printf("Check Status, resid %d datalen %d\n", 1781 xs->resid, xs->datalen); 1782 } 1783 #endif 1784 1785 if (xs->error == XS_NOERROR && 1786 !(scb->flags & SCB_SENSE)) { 1787 struct ahc_dma_seg *sg; 1788 struct scsipi_sense *sc; 1789 struct ahc_initiator_tinfo *tinfo; 1790 struct tmode_tstate *tstate; 1791 1792 sg = scb->sg_list; 1793 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1794 /* 1795 * Save off the residual if there is one. 1796 */ 1797 if (hscb->residual_SG_count != 0) 1798 ahc_calc_residual(scb); 1799 else 1800 xs->resid = 0; 1801 1802 #ifdef AHC_DEBUG 1803 if (ahc_debug & AHC_SHOWSENSE) { 1804 scsi_print_addr(xs->sc_link); 1805 printf("Sending Sense\n"); 1806 } 1807 #endif 1808 sg->addr = ahc->scb_data->sense_busaddr + 1809 (hscb->tag*sizeof(struct scsipi_sense_data)); 1810 sg->len = sizeof (struct scsipi_sense_data); 1811 1812 sc->opcode = REQUEST_SENSE; 1813 sc->byte2 = SCB_LUN(scb) << 5; 1814 sc->unused[0] = 0; 1815 sc->unused[1] = 0; 1816 sc->length = sg->len; 1817 sc->control = 0; 1818 1819 /* 1820 * Would be nice to preserve DISCENB here, 1821 * but due to the way we page SCBs, we can't. 1822 */ 1823 hscb->control = 0; 1824 1825 /* 1826 * This request sense could be because the 1827 * the device lost power or in some other 1828 * way has lost our transfer negotiations. 1829 * Renegotiate if appropriate. Unit attention 1830 * errors will be reported before any data 1831 * phases occur. 1832 */ 1833 ahc_calc_residual(scb); 1834 #if defined(AHC_DEBUG) 1835 if (ahc_debug & AHC_SHOWSENSE) { 1836 scsi_print_addr(xs->sc_link); 1837 printf("Sense: datalen %d resid %d" 1838 "chan %d id %d targ %d\n", 1839 xs->datalen, xs->resid, 1840 devinfo.channel, devinfo.our_scsiid, 1841 devinfo.target); 1842 } 1843 #endif 1844 if (xs->datalen > 0 && 1845 xs->resid == xs->datalen) { 1846 tinfo = ahc_fetch_transinfo(ahc, 1847 devinfo.channel, 1848 devinfo.our_scsiid, 1849 devinfo.target, 1850 &tstate); 1851 ahc_update_target_msg_request(ahc, 1852 &devinfo, 1853 tinfo, 1854 /*force*/TRUE, 1855 /*paused*/TRUE); 1856 } 1857 hscb->status = 0; 1858 hscb->SG_count = 1; 1859 hscb->SG_pointer = scb->sg_list_phys; 1860 hscb->data = sg->addr; 1861 hscb->datalen = sg->len; 1862 hscb->cmdpointer = hscb->cmdstore_busaddr; 1863 hscb->cmdlen = sizeof(*sc); 1864 scb->sg_count = hscb->SG_count; 1865 ahc_swap_hscb(hscb); 1866 ahc_swap_sg(scb->sg_list); 1867 scb->flags |= SCB_SENSE; 1868 /* 1869 * Ensure the target is busy since this 1870 * will be an untagged request. 1871 */ 1872 ahc_busy_tcl(ahc, scb); 1873 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1874 1875 /* 1876 * Ensure we have enough time to actually 1877 * retrieve the sense. 1878 */ 1879 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1880 callout_reset(&scb->xs->xs_callout, 1881 5 * hz, ahc_timeout, scb); 1882 } 1883 } 1884 break; 1885 case SCSI_STATUS_QUEUE_FULL: 1886 scsi_print_addr(xs->sc_link); 1887 printf("queue full\n"); 1888 case SCSI_STATUS_BUSY: 1889 /* 1890 * XXX middle layer doesn't handle XS_BUSY well. 1891 * So, requeue this ourselves internally. 1892 */ 1893 xs->error = XS_BUSY; 1894 scb->flags |= SCB_REQUEUE; 1895 break; 1896 } 1897 break; 1898 } 1899 case TRACE_POINT: 1900 { 1901 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1902 ahc_inb(ahc, DFCNTRL)); 1903 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1904 ahc_inb(ahc, DFSTATUS)); 1905 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1906 ahc_inb(ahc, SSTAT0), 1907 ahc_inb(ahc, SCB_DATACNT)); 1908 break; 1909 } 1910 case HOST_MSG_LOOP: 1911 { 1912 /* 1913 * The sequencer has encountered a message phase 1914 * that requires host assistance for completion. 1915 * While handling the message phase(s), we will be 1916 * notified by the sequencer after each byte is 1917 * transfered so we can track bus phases. 1918 * 1919 * If this is the first time we've seen a HOST_MSG_LOOP, 1920 * initialize the state of the host message loop. 1921 */ 1922 if (ahc->msg_type == MSG_TYPE_NONE) { 1923 u_int bus_phase; 1924 1925 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1926 if (bus_phase != P_MESGIN 1927 && bus_phase != P_MESGOUT) { 1928 printf("ahc_intr: HOST_MSG_LOOP bad " 1929 "phase 0x%x\n", 1930 bus_phase); 1931 /* 1932 * Probably transitioned to bus free before 1933 * we got here. Just punt the message. 1934 */ 1935 ahc_clear_intstat(ahc); 1936 restart_sequencer(ahc); 1937 } 1938 1939 if (devinfo.role == ROLE_INITIATOR) { 1940 struct scb *scb; 1941 u_int scb_index; 1942 1943 scb_index = ahc_inb(ahc, SCB_TAG); 1944 scb = &ahc->scb_data->scbarray[scb_index]; 1945 1946 if (bus_phase == P_MESGOUT) 1947 ahc_setup_initiator_msgout(ahc, 1948 &devinfo, 1949 scb); 1950 else { 1951 ahc->msg_type = 1952 MSG_TYPE_INITIATOR_MSGIN; 1953 ahc->msgin_index = 0; 1954 } 1955 } else { 1956 if (bus_phase == P_MESGOUT) { 1957 ahc->msg_type = 1958 MSG_TYPE_TARGET_MSGOUT; 1959 ahc->msgin_index = 0; 1960 } else 1961 /* XXX Ever executed??? */ 1962 ahc_setup_target_msgin(ahc, &devinfo); 1963 } 1964 } 1965 1966 /* Pass a NULL path so that handlers generate their own */ 1967 ahc_handle_message_phase(ahc, /*path*/NULL); 1968 break; 1969 } 1970 case PERR_DETECTED: 1971 { 1972 /* 1973 * If we've cleared the parity error interrupt 1974 * but the sequencer still believes that SCSIPERR 1975 * is true, it must be that the parity error is 1976 * for the currently presented byte on the bus, 1977 * and we are not in a phase (data-in) where we will 1978 * eventually ack this byte. Ack the byte and 1979 * throw it away in the hope that the target will 1980 * take us to message out to deliver the appropriate 1981 * error message. 1982 */ 1983 if ((intstat & SCSIINT) == 0 1984 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1985 u_int curphase; 1986 1987 /* 1988 * The hardware will only let you ack bytes 1989 * if the expected phase in SCSISIGO matches 1990 * the current phase. Make sure this is 1991 * currently the case. 1992 */ 1993 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1994 ahc_outb(ahc, LASTPHASE, curphase); 1995 ahc_outb(ahc, SCSISIGO, curphase); 1996 ahc_inb(ahc, SCSIDATL); 1997 } 1998 break; 1999 } 2000 case DATA_OVERRUN: 2001 { 2002 /* 2003 * When the sequencer detects an overrun, it 2004 * places the controller in "BITBUCKET" mode 2005 * and allows the target to complete its transfer. 2006 * Unfortunately, none of the counters get updated 2007 * when the controller is in this mode, so we have 2008 * no way of knowing how large the overrun was. 2009 */ 2010 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2011 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2012 int i; 2013 2014 scb = &ahc->scb_data->scbarray[scbindex]; 2015 for (i = 0; i < num_phases; i++) { 2016 if (lastphase == phase_table[i].phase) 2017 break; 2018 } 2019 scsi_print_addr(scb->xs->sc_link); 2020 printf("data overrun detected %s." 2021 " Tag == 0x%x.\n", 2022 phase_table[i].phasemsg, 2023 scb->hscb->tag); 2024 scsi_print_addr(scb->xs->sc_link); 2025 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2026 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2027 scb->xs->datalen, scb->sg_count); 2028 if (scb->sg_count > 0) { 2029 for (i = 0; i < scb->sg_count; i++) { 2030 printf("sg[%d] - Addr 0x%x : Length %d\n", 2031 i, 2032 le32toh(scb->sg_list[i].addr), 2033 le32toh(scb->sg_list[i].len)); 2034 } 2035 } 2036 /* 2037 * Set this and it will take affect when the 2038 * target does a command complete. 2039 */ 2040 ahc_freeze_devq(ahc, scb->xs->sc_link); 2041 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2042 ahc_freeze_ccb(scb); 2043 break; 2044 } 2045 case TRACEPOINT: 2046 { 2047 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2048 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2049 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2050 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2051 printf("TRACEPOINT: CCHADDR = %x\n", 2052 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2053 | (ahc_inb(ahc, CCHADDR+2) << 16) 2054 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2055 #if 0 2056 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2057 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2058 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2059 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2060 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2061 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2062 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2063 ahc_inb(ahc, CCHADDR) 2064 | (ahc_inb(ahc, CCHADDR+1) << 8) 2065 | (ahc_inb(ahc, CCHADDR+2) << 16) 2066 | (ahc_inb(ahc, CCHADDR+3) << 24), 2067 ahc_inb(ahc, CCHCNT) 2068 | (ahc_inb(ahc, CCHCNT+1) << 8) 2069 | (ahc_inb(ahc, CCHCNT+2) << 16), 2070 ahc_inb(ahc, SCBPTR)); 2071 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2072 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2073 #if DDB > 0 2074 cpu_Debugger(); 2075 #endif 2076 #endif 2077 break; 2078 } 2079 #if NOT_YET 2080 /* XXX Fill these in later */ 2081 case MESG_BUFFER_BUSY: 2082 break; 2083 case MSGIN_PHASEMIS: 2084 break; 2085 #endif 2086 default: 2087 printf("ahc_intr: seqint, " 2088 "intstat == 0x%x, scsisigi = 0x%x\n", 2089 intstat, ahc_inb(ahc, SCSISIGI)); 2090 break; 2091 } 2092 2093 unpause: 2094 /* 2095 * The sequencer is paused immediately on 2096 * a SEQINT, so we should restart it when 2097 * we're done. 2098 */ 2099 unpause_sequencer(ahc); 2100 } 2101 2102 static void 2103 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2104 { 2105 u_int scb_index; 2106 u_int status; 2107 struct scb *scb; 2108 char cur_channel; 2109 char intr_channel; 2110 2111 if ((ahc->features & AHC_TWIN) != 0 2112 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2113 cur_channel = 'B'; 2114 else 2115 cur_channel = 'A'; 2116 intr_channel = cur_channel; 2117 2118 status = ahc_inb(ahc, SSTAT1); 2119 if (status == 0) { 2120 if ((ahc->features & AHC_TWIN) != 0) { 2121 /* Try the other channel */ 2122 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2123 status = ahc_inb(ahc, SSTAT1); 2124 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2125 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2126 } 2127 if (status == 0) { 2128 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2129 return; 2130 } 2131 } 2132 2133 scb_index = ahc_inb(ahc, SCB_TAG); 2134 if (scb_index < ahc->scb_data->numscbs) { 2135 scb = &ahc->scb_data->scbarray[scb_index]; 2136 if ((scb->flags & SCB_ACTIVE) == 0 2137 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2138 scb = NULL; 2139 } else 2140 scb = NULL; 2141 2142 if ((status & SCSIRSTI) != 0) { 2143 printf("%s: Someone reset channel %c\n", 2144 ahc_name(ahc), intr_channel); 2145 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2146 } else if ((status & SCSIPERR) != 0) { 2147 /* 2148 * Determine the bus phase and queue an appropriate message. 2149 * SCSIPERR is latched true as soon as a parity error 2150 * occurs. If the sequencer acked the transfer that 2151 * caused the parity error and the currently presented 2152 * transfer on the bus has correct parity, SCSIPERR will 2153 * be cleared by CLRSCSIPERR. Use this to determine if 2154 * we should look at the last phase the sequencer recorded, 2155 * or the current phase presented on the bus. 2156 */ 2157 u_int mesg_out; 2158 u_int curphase; 2159 u_int errorphase; 2160 u_int lastphase; 2161 int i; 2162 2163 lastphase = ahc_inb(ahc, LASTPHASE); 2164 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2165 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2166 /* 2167 * For all phases save DATA, the sequencer won't 2168 * automatically ack a byte that has a parity error 2169 * in it. So the only way that the current phase 2170 * could be 'data-in' is if the parity error is for 2171 * an already acked byte in the data phase. During 2172 * synchronous data-in transfers, we may actually 2173 * ack bytes before latching the current phase in 2174 * LASTPHASE, leading to the discrepancy between 2175 * curphase and lastphase. 2176 */ 2177 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2178 || curphase == P_DATAIN) 2179 errorphase = curphase; 2180 else 2181 errorphase = lastphase; 2182 2183 for (i = 0; i < num_phases; i++) { 2184 if (errorphase == phase_table[i].phase) 2185 break; 2186 } 2187 mesg_out = phase_table[i].mesg_out; 2188 if (scb != NULL) 2189 scsi_print_addr(scb->xs->sc_link); 2190 else 2191 printf("%s:%c:%d: ", ahc_name(ahc), 2192 intr_channel, 2193 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2194 2195 printf("parity error detected %s. " 2196 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2197 phase_table[i].phasemsg, 2198 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2199 ahc_inb(ahc, SCSIRATE)); 2200 2201 /* 2202 * We've set the hardware to assert ATN if we 2203 * get a parity error on "in" phases, so all we 2204 * need to do is stuff the message buffer with 2205 * the appropriate message. "In" phases have set 2206 * mesg_out to something other than MSG_NOP. 2207 */ 2208 if (mesg_out != MSG_NOOP) { 2209 if (ahc->msg_type != MSG_TYPE_NONE) 2210 ahc->send_msg_perror = TRUE; 2211 else 2212 ahc_outb(ahc, MSG_OUT, mesg_out); 2213 } 2214 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2215 unpause_sequencer(ahc); 2216 } else if ((status & BUSFREE) != 0 2217 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2218 /* 2219 * First look at what phase we were last in. 2220 * If its message out, chances are pretty good 2221 * that the busfree was in response to one of 2222 * our abort requests. 2223 */ 2224 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2225 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2226 u_int target = TCL_TARGET(saved_tcl); 2227 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2228 char channel = TCL_CHANNEL(ahc, saved_tcl); 2229 int printerror = 1; 2230 2231 ahc_outb(ahc, SCSISEQ, 2232 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2233 if (lastphase == P_MESGOUT) { 2234 u_int message; 2235 u_int tag; 2236 2237 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2238 tag = SCB_LIST_NULL; 2239 switch (message) { 2240 case MSG_ABORT_TAG: 2241 tag = scb->hscb->tag; 2242 /* FALLTRHOUGH */ 2243 case MSG_ABORT: 2244 scsi_print_addr(scb->xs->sc_link); 2245 printf("SCB %x - Abort %s Completed.\n", 2246 scb->hscb->tag, tag == SCB_LIST_NULL ? 2247 "" : "Tag"); 2248 ahc_abort_scbs(ahc, target, channel, 2249 TCL_LUN(saved_tcl), tag, 2250 ROLE_INITIATOR, 2251 XS_DRIVER_STUFFUP); 2252 printerror = 0; 2253 break; 2254 case MSG_BUS_DEV_RESET: 2255 { 2256 struct ahc_devinfo devinfo; 2257 2258 if (scb != NULL && 2259 (scb->xs->xs_control & XS_CTL_RESET) 2260 && ahc_match_scb(scb, target, channel, 2261 TCL_LUN(saved_tcl), 2262 SCB_LIST_NULL, 2263 ROLE_INITIATOR)) { 2264 ahcsetccbstatus(scb->xs, XS_NOERROR); 2265 } 2266 ahc_compile_devinfo(&devinfo, 2267 initiator_role_id, 2268 target, 2269 TCL_LUN(saved_tcl), 2270 channel, 2271 ROLE_INITIATOR); 2272 ahc_handle_devreset(ahc, &devinfo, 2273 XS_RESET, 2274 "Bus Device Reset", 2275 /*verbose_level*/0); 2276 printerror = 0; 2277 break; 2278 } 2279 default: 2280 break; 2281 } 2282 } 2283 if (printerror != 0) { 2284 int i; 2285 2286 if (scb != NULL) { 2287 u_int tag; 2288 2289 if ((scb->hscb->control & TAG_ENB) != 0) 2290 tag = scb->hscb->tag; 2291 else 2292 tag = SCB_LIST_NULL; 2293 ahc_abort_scbs(ahc, target, channel, 2294 SCB_LUN(scb), tag, 2295 ROLE_INITIATOR, 2296 XS_DRIVER_STUFFUP); 2297 scsi_print_addr(scb->xs->sc_link); 2298 } else { 2299 /* 2300 * We had not fully identified this connection, 2301 * so we cannot abort anything. 2302 */ 2303 printf("%s: ", ahc_name(ahc)); 2304 } 2305 for (i = 0; i < num_phases; i++) { 2306 if (lastphase == phase_table[i].phase) 2307 break; 2308 } 2309 printf("Unexpected busfree %s\n" 2310 "SEQADDR == 0x%x\n", 2311 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2312 | (ahc_inb(ahc, SEQADDR1) << 8)); 2313 } 2314 ahc_clear_msg_state(ahc); 2315 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2316 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2317 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2318 restart_sequencer(ahc); 2319 } else if ((status & SELTO) != 0) { 2320 u_int scbptr; 2321 2322 scbptr = ahc_inb(ahc, WAITING_SCBH); 2323 ahc_outb(ahc, SCBPTR, scbptr); 2324 scb_index = ahc_inb(ahc, SCB_TAG); 2325 2326 if (scb_index < ahc->scb_data->numscbs) { 2327 scb = &ahc->scb_data->scbarray[scb_index]; 2328 if ((scb->flags & SCB_ACTIVE) == 0) 2329 scb = NULL; 2330 } else 2331 scb = NULL; 2332 2333 if (scb == NULL) { 2334 printf("%s: ahc_intr - referenced scb not " 2335 "valid during SELTO scb(%d, %d)\n", 2336 ahc_name(ahc), scbptr, scb_index); 2337 } else { 2338 u_int tag; 2339 2340 tag = SCB_LIST_NULL; 2341 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2342 tag = scb->hscb->tag; 2343 2344 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2345 SCB_LUN(scb), tag, 2346 ROLE_INITIATOR, XS_SELTIMEOUT); 2347 } 2348 /* Stop the selection */ 2349 ahc_outb(ahc, SCSISEQ, 0); 2350 2351 /* No more pending messages */ 2352 ahc_clear_msg_state(ahc); 2353 2354 /* 2355 * Although the driver does not care about the 2356 * 'Selection in Progress' status bit, the busy 2357 * LED does. SELINGO is only cleared by a sucessful 2358 * selection, so we must manually clear it to ensure 2359 * the LED turns off just incase no future successful 2360 * selections occur (e.g. no devices on the bus). 2361 */ 2362 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2363 2364 /* Clear interrupt state */ 2365 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2366 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2367 restart_sequencer(ahc); 2368 } else { 2369 scsi_print_addr(scb->xs->sc_link); 2370 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2371 ahc_outb(ahc, CLRSINT1, status); 2372 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2373 unpause_sequencer(ahc); 2374 } 2375 } 2376 2377 static void 2378 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2379 { 2380 /* 2381 * We need to initiate transfer negotiations. 2382 * If our current and goal settings are identical, 2383 * we want to renegotiate due to a check condition. 2384 */ 2385 struct ahc_initiator_tinfo *tinfo; 2386 struct tmode_tstate *tstate; 2387 int dowide; 2388 int dosync; 2389 2390 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2391 devinfo->target, &tstate); 2392 dowide = tinfo->current.width != tinfo->goal.width; 2393 dosync = tinfo->current.period != tinfo->goal.period; 2394 2395 if (!dowide && !dosync) { 2396 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2397 dosync = tinfo->goal.period != 0; 2398 } 2399 2400 if (dowide) { 2401 ahc_construct_wdtr(ahc, tinfo->goal.width); 2402 } else if (dosync) { 2403 struct ahc_syncrate *rate; 2404 u_int period; 2405 u_int offset; 2406 2407 period = tinfo->goal.period; 2408 rate = ahc_devlimited_syncrate(ahc, &period); 2409 offset = tinfo->goal.offset; 2410 ahc_validate_offset(ahc, rate, &offset, 2411 tinfo->current.width); 2412 ahc_construct_sdtr(ahc, period, offset); 2413 } else { 2414 panic("ahc_intr: AWAITING_MSG for negotiation, " 2415 "but no negotiation needed\n"); 2416 } 2417 } 2418 2419 static void 2420 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2421 struct scb *scb) 2422 { 2423 /* 2424 * To facilitate adding multiple messages together, 2425 * each routine should increment the index and len 2426 * variables instead of setting them explicitly. 2427 */ 2428 ahc->msgout_index = 0; 2429 ahc->msgout_len = 0; 2430 2431 if ((scb->flags & SCB_DEVICE_RESET) == 0 2432 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2433 u_int identify_msg; 2434 2435 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2436 if ((scb->hscb->control & DISCENB) != 0) 2437 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2438 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2439 ahc->msgout_len++; 2440 2441 if ((scb->hscb->control & TAG_ENB) != 0) { 2442 /* XXX fvdl FreeBSD has tag action passed down */ 2443 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2444 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2445 ahc->msgout_len += 2; 2446 } 2447 } 2448 2449 if (scb->flags & SCB_DEVICE_RESET) { 2450 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2451 ahc->msgout_len++; 2452 scsi_print_addr(scb->xs->sc_link); 2453 printf("Bus Device Reset Message Sent\n"); 2454 } else if (scb->flags & SCB_ABORT) { 2455 if ((scb->hscb->control & TAG_ENB) != 0) 2456 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2457 else 2458 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2459 ahc->msgout_len++; 2460 scsi_print_addr(scb->xs->sc_link); 2461 printf("Abort Message Sent\n"); 2462 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2463 ahc_build_transfer_msg(ahc, devinfo); 2464 } else { 2465 printf("ahc_intr: AWAITING_MSG for an SCB that " 2466 "does not have a waiting message"); 2467 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2468 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2469 ahc_inb(ahc, MSG_OUT), scb->flags); 2470 } 2471 2472 /* 2473 * Clear the MK_MESSAGE flag from the SCB so we aren't 2474 * asked to send this message again. 2475 */ 2476 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2477 ahc->msgout_index = 0; 2478 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2479 } 2480 2481 static void 2482 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2483 { 2484 /* 2485 * To facilitate adding multiple messages together, 2486 * each routine should increment the index and len 2487 * variables instead of setting them explicitly. 2488 */ 2489 ahc->msgout_index = 0; 2490 ahc->msgout_len = 0; 2491 2492 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2493 ahc_build_transfer_msg(ahc, devinfo); 2494 else 2495 panic("ahc_intr: AWAITING target message with no message"); 2496 2497 ahc->msgout_index = 0; 2498 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2499 } 2500 2501 static int 2502 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2503 { 2504 /* 2505 * What we care about here is if we had an 2506 * outstanding SDTR or WDTR message for this 2507 * target. If we did, this is a signal that 2508 * the target is refusing negotiation. 2509 */ 2510 struct scb *scb; 2511 u_int scb_index; 2512 u_int last_msg; 2513 int response = 0; 2514 2515 scb_index = ahc_inb(ahc, SCB_TAG); 2516 scb = &ahc->scb_data->scbarray[scb_index]; 2517 2518 /* Might be necessary */ 2519 last_msg = ahc_inb(ahc, LAST_MSG); 2520 2521 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2522 struct ahc_initiator_tinfo *tinfo; 2523 struct tmode_tstate *tstate; 2524 2525 #ifdef AHC_DEBUG_NEG 2526 /* note 8bit xfers */ 2527 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2528 "8bit transfers\n", ahc_name(ahc), 2529 devinfo->channel, devinfo->target); 2530 #endif 2531 ahc_set_width(ahc, devinfo, 2532 MSG_EXT_WDTR_BUS_8_BIT, 2533 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2534 /*paused*/TRUE, /*done*/TRUE); 2535 /* 2536 * No need to clear the sync rate. If the target 2537 * did not accept the command, our syncrate is 2538 * unaffected. If the target started the negotiation, 2539 * but rejected our response, we already cleared the 2540 * sync rate before sending our WDTR. 2541 */ 2542 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2543 devinfo->our_scsiid, 2544 devinfo->target, &tstate); 2545 if (tinfo->goal.period) { 2546 u_int period; 2547 2548 /* Start the sync negotiation */ 2549 period = tinfo->goal.period; 2550 ahc_devlimited_syncrate(ahc, &period); 2551 ahc->msgout_index = 0; 2552 ahc->msgout_len = 0; 2553 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2554 ahc->msgout_index = 0; 2555 response = 1; 2556 } 2557 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2558 /* note asynch xfers and clear flag */ 2559 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2560 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2561 /*paused*/TRUE, /*done*/TRUE); 2562 #ifdef AHC_DEBUG_NEG 2563 printf("%s:%c:%d: refuses synchronous negotiation. " 2564 "Using asynchronous transfers\n", 2565 ahc_name(ahc), 2566 devinfo->channel, devinfo->target); 2567 #endif 2568 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2569 printf("%s:%c:%d: refuses tagged commands. Performing " 2570 "non-tagged I/O\n", ahc_name(ahc), 2571 devinfo->channel, devinfo->target); 2572 2573 ahc_set_tags(ahc, devinfo, FALSE); 2574 2575 /* 2576 * Resend the identify for this CCB as the target 2577 * may believe that the selection is invalid otherwise. 2578 */ 2579 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2580 & ~MSG_SIMPLE_Q_TAG); 2581 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2582 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2583 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2584 2585 /* 2586 * Requeue all tagged commands for this target 2587 * currently in our posession so they can be 2588 * converted to untagged commands. 2589 */ 2590 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2591 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2592 ROLE_INITIATOR, SCB_REQUEUE, 2593 SEARCH_COMPLETE); 2594 } else { 2595 /* 2596 * Otherwise, we ignore it. 2597 */ 2598 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2599 ahc_name(ahc), devinfo->channel, devinfo->target, 2600 last_msg); 2601 } 2602 return (response); 2603 } 2604 2605 static void 2606 ahc_clear_msg_state(struct ahc_softc *ahc) 2607 { 2608 ahc->msgout_len = 0; 2609 ahc->msgin_index = 0; 2610 ahc->msg_type = MSG_TYPE_NONE; 2611 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2612 } 2613 2614 static void 2615 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2616 { 2617 struct ahc_devinfo devinfo; 2618 u_int bus_phase; 2619 int end_session; 2620 2621 ahc_fetch_devinfo(ahc, &devinfo); 2622 end_session = FALSE; 2623 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2624 2625 reswitch: 2626 switch (ahc->msg_type) { 2627 case MSG_TYPE_INITIATOR_MSGOUT: 2628 { 2629 int lastbyte; 2630 int phasemis; 2631 int msgdone; 2632 2633 if (ahc->msgout_len == 0) 2634 panic("REQINIT interrupt with no active message"); 2635 2636 phasemis = bus_phase != P_MESGOUT; 2637 if (phasemis) { 2638 if (bus_phase == P_MESGIN) { 2639 /* 2640 * Change gears and see if 2641 * this messages is of interest to 2642 * us or should be passed back to 2643 * the sequencer. 2644 */ 2645 ahc_outb(ahc, CLRSINT1, CLRATNO); 2646 ahc->send_msg_perror = FALSE; 2647 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2648 ahc->msgin_index = 0; 2649 goto reswitch; 2650 } 2651 end_session = TRUE; 2652 break; 2653 } 2654 2655 if (ahc->send_msg_perror) { 2656 ahc_outb(ahc, CLRSINT1, CLRATNO); 2657 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2658 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2659 break; 2660 } 2661 2662 msgdone = ahc->msgout_index == ahc->msgout_len; 2663 if (msgdone) { 2664 /* 2665 * The target has requested a retry. 2666 * Re-assert ATN, reset our message index to 2667 * 0, and try again. 2668 */ 2669 ahc->msgout_index = 0; 2670 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2671 } 2672 2673 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2674 if (lastbyte) { 2675 /* Last byte is signified by dropping ATN */ 2676 ahc_outb(ahc, CLRSINT1, CLRATNO); 2677 } 2678 2679 /* 2680 * Clear our interrupt status and present 2681 * the next byte on the bus. 2682 */ 2683 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2684 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2685 break; 2686 } 2687 case MSG_TYPE_INITIATOR_MSGIN: 2688 { 2689 int phasemis; 2690 int message_done; 2691 2692 phasemis = bus_phase != P_MESGIN; 2693 2694 if (phasemis) { 2695 ahc->msgin_index = 0; 2696 if (bus_phase == P_MESGOUT 2697 && (ahc->send_msg_perror == TRUE 2698 || (ahc->msgout_len != 0 2699 && ahc->msgout_index == 0))) { 2700 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2701 goto reswitch; 2702 } 2703 end_session = TRUE; 2704 break; 2705 } 2706 2707 /* Pull the byte in without acking it */ 2708 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2709 2710 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2711 2712 if (message_done) { 2713 /* 2714 * Clear our incoming message buffer in case there 2715 * is another message following this one. 2716 */ 2717 ahc->msgin_index = 0; 2718 2719 /* 2720 * If this message illicited a response, 2721 * assert ATN so the target takes us to the 2722 * message out phase. 2723 */ 2724 if (ahc->msgout_len != 0) 2725 ahc_outb(ahc, SCSISIGO, 2726 ahc_inb(ahc, SCSISIGO) | ATNO); 2727 } else 2728 ahc->msgin_index++; 2729 2730 /* Ack the byte */ 2731 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2732 ahc_inb(ahc, SCSIDATL); 2733 break; 2734 } 2735 case MSG_TYPE_TARGET_MSGIN: 2736 { 2737 int msgdone; 2738 int msgout_request; 2739 2740 if (ahc->msgout_len == 0) 2741 panic("Target MSGIN with no active message"); 2742 2743 /* 2744 * If we interrupted a mesgout session, the initiator 2745 * will not know this until our first REQ. So, we 2746 * only honor mesgout requests after we've sent our 2747 * first byte. 2748 */ 2749 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2750 && ahc->msgout_index > 0) 2751 msgout_request = TRUE; 2752 else 2753 msgout_request = FALSE; 2754 2755 if (msgout_request) { 2756 2757 /* 2758 * Change gears and see if 2759 * this messages is of interest to 2760 * us or should be passed back to 2761 * the sequencer. 2762 */ 2763 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2764 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2765 ahc->msgin_index = 0; 2766 /* Dummy read to REQ for first byte */ 2767 ahc_inb(ahc, SCSIDATL); 2768 ahc_outb(ahc, SXFRCTL0, 2769 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2770 break; 2771 } 2772 2773 msgdone = ahc->msgout_index == ahc->msgout_len; 2774 if (msgdone) { 2775 ahc_outb(ahc, SXFRCTL0, 2776 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2777 end_session = TRUE; 2778 break; 2779 } 2780 2781 /* 2782 * Present the next byte on the bus. 2783 */ 2784 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2785 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2786 break; 2787 } 2788 case MSG_TYPE_TARGET_MSGOUT: 2789 { 2790 int lastbyte; 2791 int msgdone; 2792 2793 /* 2794 * The initiator signals that this is 2795 * the last byte by dropping ATN. 2796 */ 2797 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2798 2799 /* 2800 * Read the latched byte, but turn off SPIOEN first 2801 * so that we don't inadvertantly cause a REQ for the 2802 * next byte. 2803 */ 2804 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2805 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2806 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2807 if (msgdone == MSGLOOP_TERMINATED) { 2808 /* 2809 * The message is *really* done in that it caused 2810 * us to go to bus free. The sequencer has already 2811 * been reset at this point, so pull the ejection 2812 * handle. 2813 */ 2814 return; 2815 } 2816 2817 ahc->msgin_index++; 2818 2819 /* 2820 * XXX Read spec about initiator dropping ATN too soon 2821 * and use msgdone to detect it. 2822 */ 2823 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2824 ahc->msgin_index = 0; 2825 2826 /* 2827 * If this message illicited a response, transition 2828 * to the Message in phase and send it. 2829 */ 2830 if (ahc->msgout_len != 0) { 2831 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2832 ahc_outb(ahc, SXFRCTL0, 2833 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2834 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2835 ahc->msgin_index = 0; 2836 break; 2837 } 2838 } 2839 2840 if (lastbyte) 2841 end_session = TRUE; 2842 else { 2843 /* Ask for the next byte. */ 2844 ahc_outb(ahc, SXFRCTL0, 2845 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2846 } 2847 2848 break; 2849 } 2850 default: 2851 panic("Unknown REQINIT message type"); 2852 } 2853 2854 if (end_session) { 2855 ahc_clear_msg_state(ahc); 2856 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2857 } else 2858 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2859 } 2860 2861 /* 2862 * See if we sent a particular extended message to the target. 2863 * If "full" is true, the target saw the full message. 2864 * If "full" is false, the target saw at least the first 2865 * byte of the message. 2866 */ 2867 static int 2868 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2869 { 2870 int found; 2871 int index; 2872 2873 found = FALSE; 2874 index = 0; 2875 2876 while (index < ahc->msgout_len) { 2877 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2878 2879 /* Found a candidate */ 2880 if (ahc->msgout_buf[index+2] == msgtype) { 2881 u_int end_index; 2882 2883 end_index = index + 1 2884 + ahc->msgout_buf[index + 1]; 2885 if (full) { 2886 if (ahc->msgout_index > end_index) 2887 found = TRUE; 2888 } else if (ahc->msgout_index > index) 2889 found = TRUE; 2890 } 2891 break; 2892 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2893 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2894 2895 /* Skip tag type and tag id or residue param*/ 2896 index += 2; 2897 } else { 2898 /* Single byte message */ 2899 index++; 2900 } 2901 } 2902 return (found); 2903 } 2904 2905 static int 2906 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2907 struct ahc_devinfo *devinfo) 2908 { 2909 struct ahc_initiator_tinfo *tinfo; 2910 struct tmode_tstate *tstate; 2911 int reject; 2912 int done; 2913 int response; 2914 u_int targ_scsirate; 2915 2916 done = MSGLOOP_IN_PROG; 2917 response = FALSE; 2918 reject = FALSE; 2919 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2920 devinfo->target, &tstate); 2921 targ_scsirate = tinfo->scsirate; 2922 2923 /* 2924 * Parse as much of the message as is availible, 2925 * rejecting it if we don't support it. When 2926 * the entire message is availible and has been 2927 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2928 * that we have parsed an entire message. 2929 * 2930 * In the case of extended messages, we accept the length 2931 * byte outright and perform more checking once we know the 2932 * extended message type. 2933 */ 2934 switch (ahc->msgin_buf[0]) { 2935 case MSG_MESSAGE_REJECT: 2936 response = ahc_handle_msg_reject(ahc, devinfo); 2937 /* FALLTHROUGH */ 2938 case MSG_NOOP: 2939 done = MSGLOOP_MSGCOMPLETE; 2940 break; 2941 case MSG_IGN_WIDE_RESIDUE: 2942 { 2943 /* Wait for the whole message */ 2944 if (ahc->msgin_index >= 1) { 2945 if (ahc->msgin_buf[1] != 1 2946 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2947 reject = TRUE; 2948 done = MSGLOOP_MSGCOMPLETE; 2949 } else 2950 ahc_handle_ign_wide_residue(ahc, devinfo); 2951 } 2952 break; 2953 } 2954 case MSG_EXTENDED: 2955 { 2956 /* Wait for enough of the message to begin validation */ 2957 if (ahc->msgin_index < 2) 2958 break; 2959 switch (ahc->msgin_buf[2]) { 2960 case MSG_EXT_SDTR: 2961 { 2962 struct ahc_syncrate *syncrate; 2963 u_int period; 2964 u_int offset; 2965 u_int saved_offset; 2966 2967 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2968 reject = TRUE; 2969 break; 2970 } 2971 2972 /* 2973 * Wait until we have both args before validating 2974 * and acting on this message. 2975 * 2976 * Add one to MSG_EXT_SDTR_LEN to account for 2977 * the extended message preamble. 2978 */ 2979 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2980 break; 2981 2982 period = ahc->msgin_buf[3]; 2983 saved_offset = offset = ahc->msgin_buf[4]; 2984 syncrate = ahc_devlimited_syncrate(ahc, &period); 2985 ahc_validate_offset(ahc, syncrate, &offset, 2986 targ_scsirate & WIDEXFER); 2987 ahc_set_syncrate(ahc, devinfo, 2988 syncrate, period, offset, 2989 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2990 /*paused*/TRUE, /*done*/TRUE); 2991 2992 /* 2993 * See if we initiated Sync Negotiation 2994 * and didn't have to fall down to async 2995 * transfers. 2996 */ 2997 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2998 /* We started it */ 2999 if (saved_offset != offset) { 3000 /* Went too low - force async */ 3001 reject = TRUE; 3002 } 3003 } else { 3004 /* 3005 * Send our own SDTR in reply 3006 */ 3007 ahc->msgout_index = 0; 3008 ahc->msgout_len = 0; 3009 ahc_construct_sdtr(ahc, period, offset); 3010 ahc->msgout_index = 0; 3011 response = TRUE; 3012 } 3013 done = MSGLOOP_MSGCOMPLETE; 3014 break; 3015 } 3016 case MSG_EXT_WDTR: 3017 { 3018 u_int bus_width; 3019 u_int sending_reply; 3020 3021 sending_reply = FALSE; 3022 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3023 reject = TRUE; 3024 break; 3025 } 3026 3027 /* 3028 * Wait until we have our arg before validating 3029 * and acting on this message. 3030 * 3031 * Add one to MSG_EXT_WDTR_LEN to account for 3032 * the extended message preamble. 3033 */ 3034 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3035 break; 3036 3037 bus_width = ahc->msgin_buf[3]; 3038 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3039 /* 3040 * Don't send a WDTR back to the 3041 * target, since we asked first. 3042 */ 3043 switch (bus_width){ 3044 default: 3045 /* 3046 * How can we do anything greater 3047 * than 16bit transfers on a 16bit 3048 * bus? 3049 */ 3050 reject = TRUE; 3051 printf("%s: target %d requested %dBit " 3052 "transfers. Rejecting...\n", 3053 ahc_name(ahc), devinfo->target, 3054 8 * (0x01 << bus_width)); 3055 /* FALLTHROUGH */ 3056 case MSG_EXT_WDTR_BUS_8_BIT: 3057 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3058 break; 3059 case MSG_EXT_WDTR_BUS_16_BIT: 3060 break; 3061 } 3062 } else { 3063 /* 3064 * Send our own WDTR in reply 3065 */ 3066 switch (bus_width) { 3067 default: 3068 if (ahc->features & AHC_WIDE) { 3069 /* Respond Wide */ 3070 bus_width = 3071 MSG_EXT_WDTR_BUS_16_BIT; 3072 break; 3073 } 3074 /* FALLTHROUGH */ 3075 case MSG_EXT_WDTR_BUS_8_BIT: 3076 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3077 break; 3078 } 3079 ahc->msgout_index = 0; 3080 ahc->msgout_len = 0; 3081 ahc_construct_wdtr(ahc, bus_width); 3082 ahc->msgout_index = 0; 3083 response = TRUE; 3084 sending_reply = TRUE; 3085 } 3086 ahc_set_width(ahc, devinfo, bus_width, 3087 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3088 /*paused*/TRUE, /*done*/TRUE); 3089 3090 /* After a wide message, we are async */ 3091 ahc_set_syncrate(ahc, devinfo, 3092 /*syncrate*/NULL, /*period*/0, 3093 /*offset*/0, AHC_TRANS_ACTIVE, 3094 /*paused*/TRUE, /*done*/FALSE); 3095 if (sending_reply == FALSE && reject == FALSE) { 3096 3097 if (tinfo->goal.period) { 3098 struct ahc_syncrate *rate; 3099 u_int period; 3100 u_int offset; 3101 3102 /* Start the sync negotiation */ 3103 period = tinfo->goal.period; 3104 rate = ahc_devlimited_syncrate(ahc, 3105 &period); 3106 offset = tinfo->goal.offset; 3107 ahc_validate_offset(ahc, rate, &offset, 3108 tinfo->current.width); 3109 ahc->msgout_index = 0; 3110 ahc->msgout_len = 0; 3111 ahc_construct_sdtr(ahc, period, offset); 3112 ahc->msgout_index = 0; 3113 response = TRUE; 3114 } 3115 } 3116 done = MSGLOOP_MSGCOMPLETE; 3117 break; 3118 } 3119 default: 3120 /* Unknown extended message. Reject it. */ 3121 reject = TRUE; 3122 break; 3123 } 3124 break; 3125 } 3126 case MSG_BUS_DEV_RESET: 3127 ahc_handle_devreset(ahc, devinfo, 3128 XS_RESET, "Bus Device Reset Received", 3129 /*verbose_level*/0); 3130 restart_sequencer(ahc); 3131 done = MSGLOOP_TERMINATED; 3132 break; 3133 case MSG_ABORT_TAG: 3134 case MSG_ABORT: 3135 case MSG_CLEAR_QUEUE: 3136 /* Target mode messages */ 3137 if (devinfo->role != ROLE_TARGET) { 3138 reject = TRUE; 3139 break; 3140 } 3141 #if AHC_TARGET_MODE 3142 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3143 devinfo->lun, 3144 ahc->msgin_buf[0] == MSG_ABORT_TAG 3145 ? SCB_LIST_NULL 3146 : ahc_inb(ahc, INITIATOR_TAG), 3147 ROLE_TARGET, XS_DRIVER_STUFFUP); 3148 3149 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3150 if (tstate != NULL) { 3151 struct tmode_lstate* lstate; 3152 3153 lstate = tstate->enabled_luns[devinfo->lun]; 3154 if (lstate != NULL) { 3155 ahc_queue_lstate_event(ahc, lstate, 3156 devinfo->our_scsiid, 3157 ahc->msgin_buf[0], 3158 /*arg*/0); 3159 ahc_send_lstate_events(ahc, lstate); 3160 } 3161 } 3162 done = MSGLOOP_MSGCOMPLETE; 3163 #else 3164 panic("ahc: got target mode message"); 3165 #endif 3166 break; 3167 case MSG_TERM_IO_PROC: 3168 default: 3169 reject = TRUE; 3170 break; 3171 } 3172 3173 if (reject) { 3174 /* 3175 * Setup to reject the message. 3176 */ 3177 ahc->msgout_index = 0; 3178 ahc->msgout_len = 1; 3179 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3180 done = MSGLOOP_MSGCOMPLETE; 3181 response = TRUE; 3182 } 3183 3184 if (done != MSGLOOP_IN_PROG && !response) 3185 /* Clear the outgoing message buffer */ 3186 ahc->msgout_len = 0; 3187 3188 return (done); 3189 } 3190 3191 static void 3192 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3193 { 3194 u_int scb_index; 3195 struct scb *scb; 3196 3197 scb_index = ahc_inb(ahc, SCB_TAG); 3198 scb = &ahc->scb_data->scbarray[scb_index]; 3199 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3200 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3201 /* 3202 * Ignore the message if we haven't 3203 * seen an appropriate data phase yet. 3204 */ 3205 } else { 3206 /* 3207 * If the residual occurred on the last 3208 * transfer and the transfer request was 3209 * expected to end on an odd count, do 3210 * nothing. Otherwise, subtract a byte 3211 * and update the residual count accordingly. 3212 */ 3213 u_int resid_sgcnt; 3214 3215 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3216 if (resid_sgcnt == 0 3217 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3218 /* 3219 * If the residual occurred on the last 3220 * transfer and the transfer request was 3221 * expected to end on an odd count, do 3222 * nothing. 3223 */ 3224 } else { 3225 u_int data_cnt; 3226 u_int32_t data_addr; 3227 u_int sg_index; 3228 3229 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3230 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3231 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3232 3233 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3234 | (ahc_inb(ahc, SHADDR + 2) << 16) 3235 | (ahc_inb(ahc, SHADDR + 1) << 8) 3236 | (ahc_inb(ahc, SHADDR)); 3237 3238 data_cnt += 1; 3239 data_addr -= 1; 3240 3241 sg_index = scb->sg_count - resid_sgcnt; 3242 3243 if (sg_index != 0 3244 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3245 u_int32_t sg_addr; 3246 3247 sg_index--; 3248 data_cnt = 1; 3249 data_addr = le32toh(scb->sg_list[sg_index].addr) 3250 + le32toh(scb->sg_list[sg_index].len) 3251 - 1; 3252 3253 /* 3254 * The physical address base points to the 3255 * second entry as it is always used for 3256 * calculating the "next S/G pointer". 3257 */ 3258 sg_addr = scb->sg_list_phys 3259 + (sg_index* sizeof(*scb->sg_list)); 3260 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3261 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3262 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3263 ahc_outb(ahc, SG_NEXT, sg_addr); 3264 } 3265 3266 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3267 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3268 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3269 3270 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3271 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3272 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3273 ahc_outb(ahc, SHADDR, data_addr); 3274 } 3275 } 3276 } 3277 3278 static void 3279 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3280 int status, char *message, 3281 int verbose_level) 3282 { 3283 int found; 3284 3285 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3286 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3287 status); 3288 3289 /* 3290 * Go back to async/narrow transfers and renegotiate. 3291 * ahc_set_width and ahc_set_syncrate can cope with NULL 3292 * paths. 3293 */ 3294 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3295 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3296 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3297 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3298 /*paused*/TRUE, /*done*/FALSE); 3299 3300 if (message != NULL && (verbose_level <= 0)) 3301 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3302 message, devinfo->channel, devinfo->target, found); 3303 } 3304 3305 /* 3306 * We have an scb which has been processed by the 3307 * adaptor, now we look to see how the operation 3308 * went. 3309 */ 3310 static void 3311 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3312 { 3313 struct scsipi_xfer *xs; 3314 struct scsipi_link *sc_link; 3315 int requeue = 0; 3316 int target; 3317 3318 3319 xs = scb->xs; 3320 sc_link = xs->sc_link; 3321 LIST_REMOVE(scb, plinks); 3322 3323 callout_stop(&scb->xs->xs_callout); 3324 3325 #ifdef AHC_DEBUG 3326 if (ahc_debug & AHC_SHOWCMDS) { 3327 scsi_print_addr(sc_link); 3328 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3329 scb->hscb->tag); 3330 } 3331 #endif 3332 3333 target = sc_link->scsipi_scsi.target; 3334 3335 if (xs->datalen) { 3336 int op; 3337 3338 if (xs->xs_control & XS_CTL_DATA_IN) 3339 op = BUS_DMASYNC_POSTREAD; 3340 else 3341 op = BUS_DMASYNC_POSTWRITE; 3342 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3343 scb->dmamap->dm_mapsize, op); 3344 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3345 } 3346 3347 /* 3348 * Unbusy this target/channel/lun. 3349 * XXX if we are holding two commands per lun, 3350 * send the next command. 3351 */ 3352 if (!(scb->hscb->control & TAG_ENB)) 3353 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3354 3355 /* 3356 * If the recovery SCB completes, we have to be 3357 * out of our timeout. 3358 */ 3359 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3360 3361 struct scb *scbp; 3362 3363 /* 3364 * We were able to complete the command successfully, 3365 * so reinstate the timeouts for all other pending 3366 * commands. 3367 */ 3368 scbp = ahc->pending_ccbs.lh_first; 3369 while (scbp != NULL) { 3370 struct scsipi_xfer *txs = scbp->xs; 3371 3372 if (!(txs->xs_control & XS_CTL_POLL)) { 3373 callout_reset(&scbp->xs->xs_callout, 3374 (scbp->xs->timeout * hz) / 1000, 3375 ahc_timeout, scbp); 3376 } 3377 scbp = LIST_NEXT(scbp, plinks); 3378 } 3379 3380 /* 3381 * Ensure that we didn't put a second instance of this 3382 * SCB into the QINFIFO. 3383 */ 3384 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3385 SCB_LUN(scb), scb->hscb->tag, 3386 ROLE_INITIATOR, /*status*/0, 3387 SEARCH_REMOVE); 3388 if (xs->error != XS_NOERROR) 3389 ahcsetccbstatus(xs, XS_TIMEOUT); 3390 scsi_print_addr(xs->sc_link); 3391 printf("no longer in timeout, status = %x\n", xs->status); 3392 } 3393 3394 if (xs->error != XS_NOERROR) { 3395 /* Don't clobber any existing error state */ 3396 } else if ((scb->flags & SCB_SENSE) != 0) { 3397 /* 3398 * We performed autosense retrieval. 3399 * 3400 * bzero the sense data before having 3401 * the drive fill it. The SCSI spec mandates 3402 * that any untransfered data should be 3403 * assumed to be zero. Complete the 'bounce' 3404 * of sense information through buffers accessible 3405 * via bus-space by copying it into the clients 3406 * csio. 3407 */ 3408 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3409 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3410 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3411 xs->error = XS_SENSE; 3412 } 3413 if (scb->flags & SCB_FREEZE_QUEUE) { 3414 ahc->devqueue_blocked[target]--; 3415 scb->flags &= ~SCB_FREEZE_QUEUE; 3416 } 3417 3418 requeue = scb->flags & SCB_REQUEUE; 3419 ahcfreescb(ahc, scb); 3420 3421 if (requeue) { 3422 /* 3423 * Re-insert at the front of the private queue to 3424 * preserve order. 3425 */ 3426 int s; 3427 3428 s = splbio(); 3429 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3430 splx(s); 3431 } else { 3432 xs->xs_status |= XS_STS_DONE; 3433 ahc_check_tags(ahc, xs); 3434 scsipi_done(xs); 3435 } 3436 3437 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3438 ahc_action(xs); 3439 } 3440 3441 /* 3442 * Determine the number of SCBs available on the controller 3443 */ 3444 int 3445 ahc_probe_scbs(struct ahc_softc *ahc) { 3446 int i; 3447 3448 for (i = 0; i < AHC_SCB_MAX; i++) { 3449 ahc_outb(ahc, SCBPTR, i); 3450 ahc_outb(ahc, SCB_CONTROL, i); 3451 if (ahc_inb(ahc, SCB_CONTROL) != i) 3452 break; 3453 ahc_outb(ahc, SCBPTR, 0); 3454 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3455 break; 3456 } 3457 return (i); 3458 } 3459 3460 /* 3461 * Start the board, ready for normal operation 3462 */ 3463 int 3464 ahc_init(struct ahc_softc *ahc) 3465 { 3466 int max_targ = 15; 3467 int i; 3468 int term; 3469 u_int scsi_conf; 3470 u_int scsiseq_template; 3471 u_int ultraenb; 3472 u_int discenable; 3473 u_int tagenable; 3474 size_t driver_data_size; 3475 u_int32_t physaddr; 3476 3477 #ifdef AHC_PRINT_SRAM 3478 printf("Scratch Ram:"); 3479 for (i = 0x20; i < 0x5f; i++) { 3480 if (((i % 8) == 0) && (i != 0)) { 3481 printf ("\n "); 3482 } 3483 printf (" 0x%x", ahc_inb(ahc, i)); 3484 } 3485 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3486 for (i = 0x70; i < 0x7f; i++) { 3487 if (((i % 8) == 0) && (i != 0)) { 3488 printf ("\n "); 3489 } 3490 printf (" 0x%x", ahc_inb(ahc, i)); 3491 } 3492 } 3493 printf ("\n"); 3494 #endif 3495 3496 /* 3497 * Assume we have a board at this stage and it has been reset. 3498 */ 3499 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3500 ahc->our_id = ahc->our_id_b = 7; 3501 3502 /* 3503 * Default to allowing initiator operations. 3504 */ 3505 ahc->flags |= AHC_INITIATORMODE; 3506 3507 /* 3508 * DMA tag for our command fifos and other data in system memory 3509 * the card's sequencer must be able to access. For initiator 3510 * roles, we need to allocate space for the qinfifo, qoutfifo, 3511 * and untagged_scb arrays each of which are composed of 256 3512 * 1 byte elements. When providing for the target mode role, 3513 * we additionally must provide space for the incoming target 3514 * command fifo. 3515 */ 3516 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3517 3518 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3519 ahc->sc_dmaflags, 3520 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3521 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3522 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3523 return (ENOMEM); 3524 3525 ahc->init_level++; 3526 3527 /* Allocate SCB data now that parent_dmat is initialized */ 3528 if (ahc->scb_data->maxhscbs == 0) 3529 if (ahcinitscbdata(ahc) != 0) 3530 return (ENOMEM); 3531 3532 ahc->qinfifo = &ahc->qoutfifo[256]; 3533 ahc->untagged_scbs = &ahc->qinfifo[256]; 3534 /* There are no untagged SCBs active yet. */ 3535 for (i = 0; i < 256; i++) 3536 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3537 3538 /* All of our queues are empty */ 3539 for (i = 0; i < 256; i++) 3540 ahc->qoutfifo[i] = SCB_LIST_NULL; 3541 3542 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3543 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3544 3545 /* 3546 * Allocate a tstate to house information for our 3547 * initiator presence on the bus as well as the user 3548 * data for any target mode initiator. 3549 */ 3550 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3551 printf("%s: unable to allocate tmode_tstate. " 3552 "Failing attach\n", ahc_name(ahc)); 3553 return (-1); 3554 } 3555 3556 if ((ahc->features & AHC_TWIN) != 0) { 3557 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3558 printf("%s: unable to allocate tmode_tstate. " 3559 "Failing attach\n", ahc_name(ahc)); 3560 return (-1); 3561 } 3562 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3563 ahc->our_id, ahc->our_id_b, 3564 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3565 } else { 3566 if ((ahc->features & AHC_WIDE) != 0) { 3567 printf("Wide "); 3568 } else { 3569 printf("Single "); 3570 } 3571 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3572 } 3573 3574 ahc_outb(ahc, SEQ_FLAGS, 0); 3575 3576 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3577 ahc->flags |= AHC_PAGESCBS; 3578 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3579 } else { 3580 ahc->flags &= ~AHC_PAGESCBS; 3581 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3582 } 3583 3584 #ifdef AHC_DEBUG 3585 if (ahc_debug & AHC_SHOWMISC) { 3586 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3587 "ahc_dma %d bytes\n", 3588 ahc_name(ahc), 3589 sizeof(struct hardware_scb), 3590 sizeof(struct scb), 3591 sizeof(struct ahc_dma_seg)); 3592 } 3593 #endif /* AHC_DEBUG */ 3594 3595 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3596 if (ahc->features & AHC_TWIN) { 3597 3598 /* 3599 * The device is gated to channel B after a chip reset, 3600 * so set those values first 3601 */ 3602 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3603 if ((ahc->features & AHC_ULTRA2) != 0) 3604 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3605 else 3606 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3607 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3608 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3609 |term|ENSTIMER|ACTNEGEN); 3610 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3611 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3612 3613 if ((scsi_conf & RESET_SCSI) != 0 3614 && (ahc->flags & AHC_INITIATORMODE) != 0) 3615 ahc->flags |= AHC_RESET_BUS_B; 3616 3617 /* Select Channel A */ 3618 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3619 } 3620 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3621 if ((ahc->features & AHC_ULTRA2) != 0) 3622 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3623 else 3624 ahc_outb(ahc, SCSIID, ahc->our_id); 3625 scsi_conf = ahc_inb(ahc, SCSICONF); 3626 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3627 |term 3628 |ENSTIMER|ACTNEGEN); 3629 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3630 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3631 3632 if ((scsi_conf & RESET_SCSI) != 0 3633 && (ahc->flags & AHC_INITIATORMODE) != 0) 3634 ahc->flags |= AHC_RESET_BUS_A; 3635 3636 /* 3637 * Look at the information that board initialization or 3638 * the board bios has left us. 3639 */ 3640 ultraenb = 0; 3641 tagenable = ALL_TARGETS_MASK; 3642 3643 /* Grab the disconnection disable table and invert it for our needs */ 3644 if (ahc->flags & AHC_USEDEFAULTS) { 3645 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3646 "device parameters\n", ahc_name(ahc)); 3647 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3648 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3649 discenable = ALL_TARGETS_MASK; 3650 if ((ahc->features & AHC_ULTRA) != 0) 3651 ultraenb = ALL_TARGETS_MASK; 3652 } else { 3653 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3654 | ahc_inb(ahc, DISC_DSB)); 3655 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3656 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3657 | ahc_inb(ahc, ULTRA_ENB); 3658 } 3659 3660 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3661 max_targ = 7; 3662 3663 for (i = 0; i <= max_targ; i++) { 3664 struct ahc_initiator_tinfo *tinfo; 3665 struct tmode_tstate *tstate; 3666 u_int our_id; 3667 u_int target_id; 3668 char channel; 3669 3670 channel = 'A'; 3671 our_id = ahc->our_id; 3672 target_id = i; 3673 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3674 channel = 'B'; 3675 our_id = ahc->our_id_b; 3676 target_id = i % 8; 3677 } 3678 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3679 target_id, &tstate); 3680 /* Default to async narrow across the board */ 3681 bzero(tinfo, sizeof(*tinfo)); 3682 if (ahc->flags & AHC_USEDEFAULTS) { 3683 if ((ahc->features & AHC_WIDE) != 0) 3684 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3685 3686 /* 3687 * These will be truncated when we determine the 3688 * connection type we have with the target. 3689 */ 3690 tinfo->user.period = ahc_syncrates->period; 3691 tinfo->user.offset = ~0; 3692 } else { 3693 u_int scsirate; 3694 u_int16_t mask; 3695 3696 /* Take the settings leftover in scratch RAM. */ 3697 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3698 mask = (0x01 << i); 3699 if ((ahc->features & AHC_ULTRA2) != 0) { 3700 u_int offset; 3701 u_int maxsync; 3702 3703 if ((scsirate & SOFS) == 0x0F) { 3704 /* 3705 * Haven't negotiated yet, 3706 * so the format is different. 3707 */ 3708 scsirate = (scsirate & SXFR) >> 4 3709 | (ultraenb & mask) 3710 ? 0x08 : 0x0 3711 | (scsirate & WIDEXFER); 3712 offset = MAX_OFFSET_ULTRA2; 3713 } else 3714 offset = ahc_inb(ahc, TARG_OFFSET + i); 3715 maxsync = AHC_SYNCRATE_ULTRA2; 3716 if ((ahc->features & AHC_DT) != 0) 3717 maxsync = AHC_SYNCRATE_DT; 3718 tinfo->user.period = 3719 ahc_find_period(ahc, scsirate, maxsync); 3720 if (offset == 0) 3721 tinfo->user.period = 0; 3722 else 3723 tinfo->user.offset = ~0; 3724 } else if ((scsirate & SOFS) != 0) { 3725 tinfo->user.period = 3726 ahc_find_period(ahc, scsirate, 3727 (ultraenb & mask) 3728 ? AHC_SYNCRATE_ULTRA 3729 : AHC_SYNCRATE_FAST); 3730 if (tinfo->user.period != 0) 3731 tinfo->user.offset = ~0; 3732 } 3733 if ((scsirate & WIDEXFER) != 0 3734 && (ahc->features & AHC_WIDE) != 0) 3735 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3736 } 3737 tinfo->goal = tinfo->user; /* force negotiation */ 3738 tstate->ultraenb = ultraenb; 3739 tstate->discenable = discenable; 3740 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3741 tstate->tagdisable = 0; 3742 } 3743 ahc->user_discenable = discenable; 3744 ahc->user_tagenable = tagenable; 3745 3746 /* 3747 * Tell the sequencer where it can find our arrays in memory. 3748 */ 3749 physaddr = ahc->scb_data->hscb_busaddr; 3750 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3751 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3752 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3753 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3754 3755 physaddr = ahc->shared_data_busaddr; 3756 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3757 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3758 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3759 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3760 3761 /* Target mode incomding command fifo */ 3762 physaddr += 3 * 256 * sizeof(u_int8_t); 3763 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3764 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3765 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3766 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3767 3768 /* 3769 * Initialize the group code to command length table. 3770 * This overrides the values in TARG_SCSIRATE, so only 3771 * setup the table after we have processed that information. 3772 */ 3773 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3774 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3775 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3781 3782 /* Tell the sequencer of our initial queue positions */ 3783 ahc_outb(ahc, KERNEL_QINPOS, 0); 3784 ahc_outb(ahc, QINPOS, 0); 3785 ahc_outb(ahc, QOUTPOS, 0); 3786 3787 #ifdef AHC_DEBUG 3788 if (ahc_debug & AHC_SHOWMISC) 3789 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3790 discenable, ultraenb); 3791 #endif 3792 3793 /* Don't have any special messages to send to targets */ 3794 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3795 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3796 3797 /* 3798 * Use the built in queue management registers 3799 * if they are available. 3800 */ 3801 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3802 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3803 ahc_outb(ahc, SDSCB_QOFF, 0); 3804 ahc_outb(ahc, SNSCB_QOFF, 0); 3805 ahc_outb(ahc, HNSCB_QOFF, 0); 3806 } 3807 3808 3809 /* We don't have any waiting selections */ 3810 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3811 3812 /* Our disconnection list is empty too */ 3813 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3814 3815 /* Message out buffer starts empty */ 3816 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3817 3818 /* 3819 * Setup the allowed SCSI Sequences based on operational mode. 3820 * If we are a target, we'll enalbe select in operations once 3821 * we've had a lun enabled. 3822 */ 3823 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3824 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3825 scsiseq_template |= ENRSELI; 3826 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3827 3828 /* 3829 * Load the Sequencer program and Enable the adapter 3830 * in "fast" mode. 3831 */ 3832 #ifdef AHC_DEBUG 3833 printf("%s: Downloading Sequencer Program...", 3834 ahc_name(ahc)); 3835 #endif 3836 3837 ahc_loadseq(ahc); 3838 3839 /* We have to wait until after any system dumps... */ 3840 shutdownhook_establish(ahc_shutdown, ahc); 3841 3842 return (0); 3843 } 3844 3845 static int 3846 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3847 struct proc *p) 3848 { 3849 struct ahc_softc *ahc = sc_link->adapter_softc; 3850 char channel; 3851 int s, ret = ENOTTY; 3852 3853 switch (cmd) { 3854 case SCBUSIORESET: 3855 channel = SIM_CHANNEL(ahc, sc_link); 3856 s = splbio(); 3857 ahc_reset_channel(ahc, channel, TRUE); 3858 splx(s); 3859 ret = 0; 3860 break; 3861 default: 3862 } 3863 3864 return ret; 3865 } 3866 3867 3868 /* 3869 * XXX fvdl the busy_tcl checks and settings should only be done 3870 * for the non-tagged queueing case, but we don't do tagged queueing 3871 * yet, so.. 3872 */ 3873 static int32_t 3874 ahc_action(struct scsipi_xfer *xs) 3875 { 3876 struct scsipi_xfer *first_xs, *next_xs = NULL; 3877 struct ahc_softc *ahc; 3878 struct scb *scb; 3879 struct hardware_scb *hscb; 3880 struct ahc_initiator_tinfo *tinfo; 3881 struct tmode_tstate *tstate; 3882 u_int target_id; 3883 u_int our_id; 3884 int s, tcl; 3885 u_int16_t mask; 3886 char channel; 3887 int dontqueue = 0, fromqueue = 0; 3888 3889 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3890 3891 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3892 3893 /* must protect the queue */ 3894 s = splbio(); 3895 3896 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3897 /* 3898 * Called from ahc_done. Calling with the first entry in 3899 * the queue is really just a way of seeing where we're 3900 * called from. Now, find the first eligible SCB to send, 3901 * e.g. one which will be accepted immediately. 3902 */ 3903 3904 if (ahc->queue_blocked) { 3905 splx(s); 3906 return (TRY_AGAIN_LATER); 3907 } 3908 3909 xs = ahc_first_xs(ahc); 3910 if (xs == NULL) { 3911 splx(s); 3912 return (TRY_AGAIN_LATER); 3913 } 3914 3915 next_xs = TAILQ_NEXT(xs, adapter_q); 3916 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3917 fromqueue = 1; 3918 goto get_scb; 3919 } 3920 3921 /* 3922 * If no new requests are accepted, just insert into the 3923 * private queue to wait for our turn. 3924 */ 3925 tcl = XS_TCL(ahc, xs); 3926 3927 if (ahc->queue_blocked || 3928 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3929 (!ahc_istagged_device(ahc, xs, 0) && 3930 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3931 if (dontqueue) { 3932 splx(s); 3933 xs->error = XS_DRIVER_STUFFUP; 3934 return TRY_AGAIN_LATER; 3935 } 3936 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3937 splx(s); 3938 return SUCCESSFULLY_QUEUED; 3939 } 3940 3941 first_xs = ahc_first_xs(ahc); 3942 3943 /* determine safety of software queueing */ 3944 dontqueue = xs->xs_control & XS_CTL_POLL; 3945 3946 /* 3947 * Handle situations where there's already entries in the 3948 * queue. 3949 */ 3950 if (first_xs != NULL) { 3951 /* 3952 * If we can't queue, we have to abort, since 3953 * we have to preserve order. 3954 */ 3955 if (dontqueue) { 3956 splx(s); 3957 xs->error = XS_DRIVER_STUFFUP; 3958 return (TRY_AGAIN_LATER); 3959 } 3960 3961 /* 3962 * Swap with the first queue entry. 3963 */ 3964 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3965 xs = first_xs; 3966 next_xs = TAILQ_NEXT(xs, adapter_q); 3967 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3968 fromqueue = 1; 3969 3970 } 3971 3972 get_scb: 3973 3974 target_id = xs->sc_link->scsipi_scsi.target; 3975 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3976 3977 /* 3978 * get an scb to use. 3979 */ 3980 if ((scb = ahcgetscb(ahc)) == NULL) { 3981 3982 if (dontqueue) { 3983 splx(s); 3984 xs->error = XS_DRIVER_STUFFUP; 3985 return (TRY_AGAIN_LATER); 3986 } 3987 3988 /* 3989 * If we were pulled off the queue, put ourselves 3990 * back to where we came from, otherwise tack ourselves 3991 * onto the end. 3992 */ 3993 if (fromqueue && next_xs != NULL) 3994 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3995 else 3996 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3997 3998 splx(s); 3999 return (SUCCESSFULLY_QUEUED); 4000 } 4001 4002 tcl = XS_TCL(ahc, xs); 4003 4004 #ifdef DIAGNOSTIC 4005 if (!ahc_istagged_device(ahc, xs, 0) && 4006 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4007 panic("ahc: queuing for busy target"); 4008 #endif 4009 4010 scb->xs = xs; 4011 hscb = scb->hscb; 4012 hscb->tcl = tcl; 4013 4014 if (ahc_istagged_device(ahc, xs, 0)) 4015 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4016 else 4017 ahc_busy_tcl(ahc, scb); 4018 4019 splx(s); 4020 4021 channel = SIM_CHANNEL(ahc, xs->sc_link); 4022 if (ahc->inited_channels[channel - 'A'] == 0) { 4023 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4024 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4025 s = splbio(); 4026 ahc_reset_channel(ahc, channel, TRUE); 4027 splx(s); 4028 } 4029 ahc->inited_channels[channel - 'A'] = 1; 4030 } 4031 4032 /* 4033 * Put all the arguments for the xfer in the scb 4034 */ 4035 4036 mask = SCB_TARGET_MASK(scb); 4037 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4038 target_id, &tstate); 4039 if (ahc->inited_targets[target_id] == 0) { 4040 struct ahc_devinfo devinfo; 4041 4042 s = splbio(); 4043 ahc_compile_devinfo(&devinfo, our_id, target_id, 4044 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4045 ROLE_INITIATOR); 4046 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4047 FALSE); 4048 ahc->inited_targets[target_id] = 1; 4049 splx(s); 4050 } 4051 4052 hscb->scsirate = tinfo->scsirate; 4053 hscb->scsioffset = tinfo->current.offset; 4054 if ((tstate->ultraenb & mask) != 0) 4055 hscb->control |= ULTRAENB; 4056 4057 if ((tstate->discenable & mask) != 0) 4058 hscb->control |= DISCENB; 4059 4060 if (xs->xs_control & XS_CTL_RESET) { 4061 hscb->cmdpointer = 0; 4062 scb->flags |= SCB_DEVICE_RESET; 4063 hscb->control |= MK_MESSAGE; 4064 return ahc_execute_scb(scb, NULL, 0); 4065 } 4066 4067 return ahc_setup_data(ahc, xs, scb); 4068 } 4069 4070 static int 4071 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4072 { 4073 struct scb *scb; 4074 struct scsipi_xfer *xs; 4075 struct ahc_softc *ahc; 4076 int s; 4077 4078 scb = (struct scb *)arg; 4079 xs = scb->xs; 4080 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4081 4082 4083 if (nsegments != 0) { 4084 struct ahc_dma_seg *sg; 4085 bus_dma_segment_t *end_seg; 4086 int op; 4087 4088 end_seg = dm_segs + nsegments; 4089 4090 /* Copy the first SG into the data pointer area */ 4091 scb->hscb->data = dm_segs->ds_addr; 4092 scb->hscb->datalen = dm_segs->ds_len; 4093 4094 /* Copy the segments into our SG list */ 4095 sg = scb->sg_list; 4096 while (dm_segs < end_seg) { 4097 sg->addr = dm_segs->ds_addr; 4098 sg->len = dm_segs->ds_len; 4099 ahc_swap_sg(sg); 4100 sg++; 4101 dm_segs++; 4102 } 4103 4104 /* Note where to find the SG entries in bus space */ 4105 scb->hscb->SG_pointer = scb->sg_list_phys; 4106 4107 if (xs->xs_control & XS_CTL_DATA_IN) 4108 op = BUS_DMASYNC_PREREAD; 4109 else 4110 op = BUS_DMASYNC_PREWRITE; 4111 4112 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4113 scb->dmamap->dm_mapsize, op); 4114 4115 } else { 4116 scb->hscb->SG_pointer = 0; 4117 scb->hscb->data = 0; 4118 scb->hscb->datalen = 0; 4119 } 4120 4121 scb->sg_count = scb->hscb->SG_count = nsegments; 4122 4123 s = splbio(); 4124 4125 /* 4126 * Last time we need to check if this SCB needs to 4127 * be aborted. 4128 */ 4129 if (xs->xs_status & XS_STS_DONE) { 4130 if (!ahc_istagged_device(ahc, xs, 0)) 4131 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4132 if (nsegments != 0) 4133 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4134 ahcfreescb(ahc, scb); 4135 splx(s); 4136 return (COMPLETE); 4137 } 4138 4139 #ifdef DIAGNOSTIC 4140 if (scb->sg_count > 255) 4141 panic("ahc bad sg_count"); 4142 #endif 4143 4144 ahc_swap_hscb(scb->hscb); 4145 4146 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4147 4148 scb->flags |= SCB_ACTIVE; 4149 4150 if (!(xs->xs_control & XS_CTL_POLL)) 4151 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4152 ahc_timeout, scb); 4153 4154 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4155 #if 0 4156 printf("Continueing Immediate Command %d:%d\n", 4157 xs->sc_link->scsipi_scsi.target, 4158 xs->sc_link->scsipi_scsi.lun); 4159 #endif 4160 pause_sequencer(ahc); 4161 if ((ahc->flags & AHC_PAGESCBS) == 0) 4162 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4163 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4164 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4165 unpause_sequencer(ahc); 4166 } else { 4167 4168 #if 0 4169 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4170 scb->hscb->tag, ahc->qinfifonext, 4171 &ahc->qinfifo[ahc->qinfifonext], 4172 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4173 #endif 4174 4175 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4176 4177 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4178 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4179 4180 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4181 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4182 } else { 4183 pause_sequencer(ahc); 4184 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4185 unpause_sequencer(ahc); 4186 } 4187 } 4188 4189 #ifdef AHC_DEBUG 4190 if (ahc_debug & AHC_SHOWCMDS) { 4191 scsi_print_addr(xs->sc_link); 4192 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4193 " rate %x\n", 4194 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4195 scb->flags, scb->hscb->control, ahc->qinfifonext, 4196 scb->hscb->scsirate); 4197 } 4198 #endif 4199 4200 if (!(xs->xs_control & XS_CTL_POLL)) { 4201 splx(s); 4202 return (SUCCESSFULLY_QUEUED); 4203 } 4204 /* 4205 * If we can't use interrupts, poll for completion 4206 */ 4207 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4208 do { 4209 if (ahc_poll(ahc, xs->timeout)) { 4210 if (!(xs->xs_control & XS_CTL_SILENT)) 4211 printf("cmd fail\n"); 4212 ahc_timeout(scb); 4213 break; 4214 } 4215 } while (!(xs->xs_status & XS_STS_DONE)); 4216 splx(s); 4217 return (COMPLETE); 4218 } 4219 4220 static int 4221 ahc_poll(struct ahc_softc *ahc, int wait) 4222 { 4223 while (--wait) { 4224 DELAY(1000); 4225 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4226 break; 4227 } 4228 4229 if (wait == 0) { 4230 printf("%s: board is not responding\n", ahc_name(ahc)); 4231 return (EIO); 4232 } 4233 4234 ahc_intr((void *)ahc); 4235 return (0); 4236 } 4237 4238 static int 4239 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4240 struct scb *scb) 4241 { 4242 struct hardware_scb *hscb; 4243 4244 hscb = scb->hscb; 4245 xs->resid = xs->status = 0; 4246 4247 hscb->cmdlen = xs->cmdlen; 4248 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4249 hscb->cmdpointer = hscb->cmdstore_busaddr; 4250 4251 /* Only use S/G if there is a transfer */ 4252 if (xs->datalen) { 4253 int error; 4254 4255 error = bus_dmamap_load(ahc->parent_dmat, 4256 scb->dmamap, xs->data, 4257 xs->datalen, NULL, 4258 (xs->xs_control & XS_CTL_NOSLEEP) ? 4259 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4260 if (error) { 4261 if (!ahc_istagged_device(ahc, xs, 0)) 4262 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4263 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4264 } 4265 error = ahc_execute_scb(scb, 4266 scb->dmamap->dm_segs, 4267 scb->dmamap->dm_nsegs); 4268 return error; 4269 } else { 4270 return ahc_execute_scb(scb, NULL, 0); 4271 } 4272 } 4273 4274 static void 4275 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4276 { 4277 int target; 4278 char channel; 4279 int lun; 4280 4281 target = sc_link->scsipi_scsi.target; 4282 lun = sc_link->scsipi_scsi.lun; 4283 channel = sc_link->scsipi_scsi.channel; 4284 4285 ahc_search_qinfifo(ahc, target, channel, lun, 4286 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4287 SCB_REQUEUE, SEARCH_COMPLETE); 4288 } 4289 4290 static void 4291 ahcallocscbs(struct ahc_softc *ahc) 4292 { 4293 struct scb_data *scb_data; 4294 struct scb *next_scb; 4295 struct sg_map_node *sg_map; 4296 bus_addr_t physaddr; 4297 struct ahc_dma_seg *segs; 4298 int newcount; 4299 int i; 4300 4301 scb_data = ahc->scb_data; 4302 if (scb_data->numscbs >= AHC_SCB_MAX) 4303 /* Can't allocate any more */ 4304 return; 4305 4306 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4307 4308 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4309 4310 if (sg_map == NULL) 4311 return; 4312 4313 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4314 &sg_map->sg_dmamap, 4315 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4316 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4317 "SG space") < 0) { 4318 free(sg_map, M_DEVBUF); 4319 return; 4320 } 4321 4322 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4323 4324 segs = sg_map->sg_vaddr; 4325 physaddr = sg_map->sg_physaddr; 4326 4327 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4328 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4329 int error; 4330 4331 next_scb->sg_list = segs; 4332 /* 4333 * The sequencer always starts with the second entry. 4334 * The first entry is embedded in the scb. 4335 */ 4336 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4337 next_scb->flags = SCB_FREE; 4338 error = bus_dmamap_create(ahc->parent_dmat, 4339 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4340 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4341 &next_scb->dmamap); 4342 if (error != 0) 4343 break; 4344 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4345 next_scb->hscb->tag = ahc->scb_data->numscbs; 4346 next_scb->hscb->cmdstore_busaddr = 4347 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4348 + offsetof(struct hardware_scb, cmdstore); 4349 next_scb->hscb->cmdstore_busaddr = 4350 htole32(next_scb->hscb->cmdstore_busaddr); 4351 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4352 segs += AHC_NSEG; 4353 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4354 next_scb++; 4355 ahc->scb_data->numscbs++; 4356 } 4357 #ifdef AHC_DEBUG 4358 if (ahc_debug & AHC_SHOWSCBALLOC) 4359 printf("%s: allocated %d new SCBs count now %d\n", 4360 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4361 #endif 4362 } 4363 4364 #ifdef AHC_DUMP_SEQ 4365 static void 4366 ahc_dumpseq(struct ahc_softc* ahc) 4367 { 4368 int i; 4369 int max_prog; 4370 4371 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4372 max_prog = 448; 4373 else if ((ahc->features & AHC_ULTRA2) != 0) 4374 max_prog = 768; 4375 else 4376 max_prog = 512; 4377 4378 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4379 ahc_outb(ahc, SEQADDR0, 0); 4380 ahc_outb(ahc, SEQADDR1, 0); 4381 for (i = 0; i < max_prog; i++) { 4382 u_int8_t ins_bytes[4]; 4383 4384 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4385 printf("0x%08x\n", ins_bytes[0] << 24 4386 | ins_bytes[1] << 16 4387 | ins_bytes[2] << 8 4388 | ins_bytes[3]); 4389 } 4390 } 4391 #endif 4392 4393 static void 4394 ahc_loadseq(struct ahc_softc *ahc) 4395 { 4396 struct patch *cur_patch; 4397 int i; 4398 int downloaded; 4399 int skip_addr; 4400 u_int8_t download_consts[4]; 4401 4402 /* Setup downloadable constant table */ 4403 #if 0 4404 /* No downloaded constants are currently defined. */ 4405 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4406 #endif 4407 4408 cur_patch = patches; 4409 downloaded = 0; 4410 skip_addr = 0; 4411 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4412 ahc_outb(ahc, SEQADDR0, 0); 4413 ahc_outb(ahc, SEQADDR1, 0); 4414 4415 for (i = 0; i < sizeof(seqprog)/4; i++) { 4416 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4417 /* 4418 * Don't download this instruction as it 4419 * is in a patch that was removed. 4420 */ 4421 continue; 4422 } 4423 ahc_download_instr(ahc, i, download_consts); 4424 downloaded++; 4425 } 4426 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4427 restart_sequencer(ahc); 4428 4429 #ifdef AHC_DEBUG 4430 printf(" %d instructions downloaded\n", downloaded); 4431 #endif 4432 } 4433 4434 static int 4435 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4436 int start_instr, int *skip_addr) 4437 { 4438 struct patch *cur_patch; 4439 struct patch *last_patch; 4440 int num_patches; 4441 4442 num_patches = sizeof(patches)/sizeof(struct patch); 4443 last_patch = &patches[num_patches]; 4444 cur_patch = *start_patch; 4445 4446 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4447 4448 if (cur_patch->patch_func(ahc) == 0) { 4449 4450 /* Start rejecting code */ 4451 *skip_addr = start_instr + cur_patch->skip_instr; 4452 cur_patch += cur_patch->skip_patch; 4453 } else { 4454 /* Accepted this patch. Advance to the next 4455 * one and wait for our intruction pointer to 4456 * hit this point. 4457 */ 4458 cur_patch++; 4459 } 4460 } 4461 4462 *start_patch = cur_patch; 4463 if (start_instr < *skip_addr) 4464 /* Still skipping */ 4465 return (0); 4466 4467 return (1); 4468 } 4469 4470 static void 4471 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4472 { 4473 union ins_formats instr; 4474 struct ins_format1 *fmt1_ins; 4475 struct ins_format3 *fmt3_ins; 4476 u_int opcode; 4477 4478 /* Structure copy */ 4479 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4480 4481 instr.integer = le32toh(instr.integer); 4482 4483 fmt1_ins = &instr.format1; 4484 fmt3_ins = NULL; 4485 4486 /* Pull the opcode */ 4487 opcode = instr.format1.opcode; 4488 switch (opcode) { 4489 case AIC_OP_JMP: 4490 case AIC_OP_JC: 4491 case AIC_OP_JNC: 4492 case AIC_OP_CALL: 4493 case AIC_OP_JNE: 4494 case AIC_OP_JNZ: 4495 case AIC_OP_JE: 4496 case AIC_OP_JZ: 4497 { 4498 struct patch *cur_patch; 4499 int address_offset; 4500 u_int address; 4501 int skip_addr; 4502 int i; 4503 4504 fmt3_ins = &instr.format3; 4505 address_offset = 0; 4506 address = fmt3_ins->address; 4507 cur_patch = patches; 4508 skip_addr = 0; 4509 4510 for (i = 0; i < address;) { 4511 4512 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4513 4514 if (skip_addr > i) { 4515 int end_addr; 4516 4517 end_addr = MIN(address, skip_addr); 4518 address_offset += end_addr - i; 4519 i = skip_addr; 4520 } else { 4521 i++; 4522 } 4523 } 4524 address -= address_offset; 4525 fmt3_ins->address = address; 4526 /* FALLTHROUGH */ 4527 } 4528 case AIC_OP_OR: 4529 case AIC_OP_AND: 4530 case AIC_OP_XOR: 4531 case AIC_OP_ADD: 4532 case AIC_OP_ADC: 4533 case AIC_OP_BMOV: 4534 if (fmt1_ins->parity != 0) { 4535 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4536 } 4537 fmt1_ins->parity = 0; 4538 /* FALLTHROUGH */ 4539 case AIC_OP_ROL: 4540 if ((ahc->features & AHC_ULTRA2) != 0) { 4541 int i, count; 4542 4543 /* Calculate odd parity for the instruction */ 4544 for (i = 0, count = 0; i < 31; i++) { 4545 u_int32_t mask; 4546 4547 mask = 0x01 << i; 4548 if ((instr.integer & mask) != 0) 4549 count++; 4550 } 4551 if ((count & 0x01) == 0) 4552 instr.format1.parity = 1; 4553 } else { 4554 /* Compress the instruction for older sequencers */ 4555 if (fmt3_ins != NULL) { 4556 instr.integer = 4557 fmt3_ins->immediate 4558 | (fmt3_ins->source << 8) 4559 | (fmt3_ins->address << 16) 4560 | (fmt3_ins->opcode << 25); 4561 } else { 4562 instr.integer = 4563 fmt1_ins->immediate 4564 | (fmt1_ins->source << 8) 4565 | (fmt1_ins->destination << 16) 4566 | (fmt1_ins->ret << 24) 4567 | (fmt1_ins->opcode << 25); 4568 } 4569 } 4570 instr.integer = htole32(instr.integer); 4571 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4572 break; 4573 default: 4574 panic("Unknown opcode encountered in seq program"); 4575 break; 4576 } 4577 } 4578 4579 static void 4580 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4581 { 4582 4583 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4584 struct scb *scbp; 4585 4586 scb->flags |= SCB_RECOVERY_SCB; 4587 4588 /* 4589 * Take all queued, but not sent SCBs out of the equation. 4590 * Also ensure that no new CCBs are queued to us while we 4591 * try to fix this problem. 4592 */ 4593 ahc->queue_blocked = 1; 4594 4595 /* 4596 * Go through all of our pending SCBs and remove 4597 * any scheduled timeouts for them. We will reschedule 4598 * them after we've successfully fixed this problem. 4599 */ 4600 scbp = ahc->pending_ccbs.lh_first; 4601 while (scbp != NULL) { 4602 callout_stop(&scbp->xs->xs_callout); 4603 scbp = scbp->plinks.le_next; 4604 } 4605 } 4606 } 4607 4608 static void 4609 ahc_timeout(void *arg) 4610 { 4611 struct scb *scb; 4612 struct ahc_softc *ahc; 4613 int s, found; 4614 u_int last_phase; 4615 int target; 4616 int lun; 4617 int i; 4618 char channel; 4619 4620 scb = (struct scb *)arg; 4621 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4622 4623 s = splbio(); 4624 4625 /* 4626 * Ensure that the card doesn't do anything 4627 * behind our back. Also make sure that we 4628 * didn't "just" miss an interrupt that would 4629 * affect this timeout. 4630 */ 4631 do { 4632 ahc_intr(ahc); 4633 pause_sequencer(ahc); 4634 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4635 4636 if ((scb->flags & SCB_ACTIVE) == 0) { 4637 /* Previous timeout took care of me already */ 4638 printf("Timedout SCB handled by another timeout\n"); 4639 unpause_sequencer(ahc); 4640 splx(s); 4641 return; 4642 } 4643 4644 target = SCB_TARGET(scb); 4645 channel = SCB_CHANNEL(scb); 4646 lun = SCB_LUN(scb); 4647 4648 scsi_print_addr(scb->xs->sc_link); 4649 printf("SCB %x - timed out ", scb->hscb->tag); 4650 /* 4651 * Take a snapshot of the bus state and print out 4652 * some information so we can track down driver bugs. 4653 */ 4654 last_phase = ahc_inb(ahc, LASTPHASE); 4655 4656 for (i = 0; i < num_phases; i++) { 4657 if (last_phase == phase_table[i].phase) 4658 break; 4659 } 4660 printf("%s", phase_table[i].phasemsg); 4661 4662 printf(", SEQADDR == 0x%x\n", 4663 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4664 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4665 4666 #ifdef AHC_DEBUG 4667 ahc_print_scb(scb); 4668 #endif 4669 4670 #if 0 4671 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4672 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4673 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4674 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4675 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4676 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4677 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4678 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4679 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4680 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4681 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4682 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4683 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4684 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4685 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4686 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4687 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4688 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4689 if (scb->sg_count > 0) { 4690 for (i = 0; i < scb->sg_count; i++) { 4691 printf("sg[%d] - Addr 0x%x : Length %d\n", 4692 i, 4693 le32toh(scb->sg_list[i].addr), 4694 le32toh(scb->sg_list[i].len)); 4695 } 4696 } 4697 #endif 4698 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4699 /* 4700 * Been down this road before. 4701 * Do a full bus reset. 4702 */ 4703 bus_reset: 4704 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4705 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4706 printf("%s: Issued Channel %c Bus Reset. " 4707 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4708 } else { 4709 /* 4710 * If we are a target, transition to bus free and report 4711 * the timeout. 4712 * 4713 * The target/initiator that is holding up the bus may not 4714 * be the same as the one that triggered this timeout 4715 * (different commands have different timeout lengths). 4716 * If the bus is idle and we are actiing as the initiator 4717 * for this request, queue a BDR message to the timed out 4718 * target. Otherwise, if the timed out transaction is 4719 * active: 4720 * Initiator transaction: 4721 * Stuff the message buffer with a BDR message and assert 4722 * ATN in the hopes that the target will let go of the bus 4723 * and go to the mesgout phase. If this fails, we'll 4724 * get another timeout 2 seconds later which will attempt 4725 * a bus reset. 4726 * 4727 * Target transaction: 4728 * Transition to BUS FREE and report the error. 4729 * It's good to be the target! 4730 */ 4731 u_int active_scb_index; 4732 4733 active_scb_index = ahc_inb(ahc, SCB_TAG); 4734 4735 if (last_phase != P_BUSFREE 4736 && (active_scb_index < ahc->scb_data->numscbs)) { 4737 struct scb *active_scb; 4738 4739 /* 4740 * If the active SCB is not from our device, 4741 * assume that another device is hogging the bus 4742 * and wait for it's timeout to expire before 4743 * taking additional action. 4744 */ 4745 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4746 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4747 u_int newtimeout; 4748 4749 scsi_print_addr(scb->xs->sc_link); 4750 printf("Other SCB Timeout%s", 4751 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4752 ? " again\n" : "\n"); 4753 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4754 newtimeout = MAX(active_scb->xs->timeout, 4755 scb->xs->timeout); 4756 callout_reset(&scb->xs->xs_callout, 4757 (newtimeout * hz) / 1000, 4758 ahc_timeout, scb); 4759 splx(s); 4760 return; 4761 } 4762 4763 /* It's us */ 4764 if ((scb->hscb->control & TARGET_SCB) != 0) { 4765 4766 /* 4767 * Send back any queued up transactions 4768 * and properly record the error condition. 4769 */ 4770 ahc_freeze_devq(ahc, scb->xs->sc_link); 4771 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4772 ahc_freeze_ccb(scb); 4773 ahc_done(ahc, scb); 4774 4775 /* Will clear us from the bus */ 4776 restart_sequencer(ahc); 4777 return; 4778 } 4779 4780 ahc_set_recoveryscb(ahc, active_scb); 4781 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4782 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4783 scsi_print_addr(active_scb->xs->sc_link); 4784 printf("BDR message in message buffer\n"); 4785 active_scb->flags |= SCB_DEVICE_RESET; 4786 callout_reset(&active_scb->xs->xs_callout, 4787 2 * hz, ahc_timeout, active_scb); 4788 unpause_sequencer(ahc); 4789 } else { 4790 int disconnected; 4791 4792 /* XXX Shouldn't panic. Just punt instead */ 4793 if ((scb->hscb->control & TARGET_SCB) != 0) 4794 panic("Timed-out target SCB but bus idle"); 4795 4796 if (last_phase != P_BUSFREE 4797 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4798 /* XXX What happened to the SCB? */ 4799 /* Hung target selection. Goto busfree */ 4800 printf("%s: Hung target selection\n", 4801 ahc_name(ahc)); 4802 restart_sequencer(ahc); 4803 return; 4804 } 4805 4806 if (ahc_search_qinfifo(ahc, target, channel, lun, 4807 scb->hscb->tag, ROLE_INITIATOR, 4808 /*status*/0, SEARCH_COUNT) > 0) { 4809 disconnected = FALSE; 4810 } else { 4811 disconnected = TRUE; 4812 } 4813 4814 if (disconnected) { 4815 u_int active_scb; 4816 4817 ahc_set_recoveryscb(ahc, scb); 4818 /* 4819 * Simply set the MK_MESSAGE control bit. 4820 */ 4821 scb->hscb->control |= MK_MESSAGE; 4822 scb->flags |= SCB_QUEUED_MSG 4823 | SCB_DEVICE_RESET; 4824 4825 /* 4826 * Mark the cached copy of this SCB in the 4827 * disconnected list too, so that a reconnect 4828 * at this point causes a BDR or abort. 4829 */ 4830 active_scb = ahc_inb(ahc, SCBPTR); 4831 if (ahc_search_disc_list(ahc, target, 4832 channel, lun, 4833 scb->hscb->tag, 4834 /*stop_on_first*/TRUE, 4835 /*remove*/FALSE, 4836 /*save_state*/FALSE)) { 4837 u_int scb_control; 4838 4839 scb_control = ahc_inb(ahc, SCB_CONTROL); 4840 scb_control |= MK_MESSAGE; 4841 ahc_outb(ahc, SCB_CONTROL, scb_control); 4842 } 4843 ahc_outb(ahc, SCBPTR, active_scb); 4844 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4845 /*unbusy*/TRUE); 4846 4847 /* 4848 * Actually re-queue this SCB in case we can 4849 * select the device before it reconnects. 4850 * Clear out any entries in the QINFIFO first 4851 * so we are the next SCB for this target 4852 * to run. 4853 */ 4854 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4855 channel, SCB_LUN(scb), 4856 SCB_LIST_NULL, 4857 ROLE_INITIATOR, 4858 SCB_REQUEUE, 4859 SEARCH_COMPLETE); 4860 scsi_print_addr(scb->xs->sc_link); 4861 printf("Queuing a BDR SCB\n"); 4862 ahc->qinfifo[ahc->qinfifonext++] = 4863 scb->hscb->tag; 4864 4865 bus_dmamap_sync(ahc->parent_dmat, 4866 ahc->shared_data_dmamap, 4867 QINFIFO_OFFSET * 256, 256, 4868 BUS_DMASYNC_PREWRITE); 4869 4870 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4871 ahc_outb(ahc, HNSCB_QOFF, 4872 ahc->qinfifonext); 4873 } else { 4874 ahc_outb(ahc, KERNEL_QINPOS, 4875 ahc->qinfifonext); 4876 } 4877 callout_reset(&scb->xs->xs_callout, 2 * hz, 4878 ahc_timeout, scb); 4879 unpause_sequencer(ahc); 4880 } else { 4881 /* Go "immediatly" to the bus reset */ 4882 /* This shouldn't happen */ 4883 ahc_set_recoveryscb(ahc, scb); 4884 scsi_print_addr(scb->xs->sc_link); 4885 printf("SCB %x: Immediate reset. " 4886 "Flags = 0x%x\n", scb->hscb->tag, 4887 scb->flags); 4888 goto bus_reset; 4889 } 4890 } 4891 } 4892 splx(s); 4893 } 4894 4895 static int 4896 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4897 int lun, u_int tag, role_t role, scb_flag status, 4898 ahc_search_action action) 4899 { 4900 struct scb *scbp; 4901 u_int8_t qinpos; 4902 u_int8_t qintail; 4903 int found; 4904 4905 qinpos = ahc_inb(ahc, QINPOS); 4906 qintail = ahc->qinfifonext; 4907 found = 0; 4908 4909 /* 4910 * Start with an empty queue. Entries that are not chosen 4911 * for removal will be re-added to the queue as we go. 4912 */ 4913 ahc->qinfifonext = qinpos; 4914 4915 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4916 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4917 4918 while (qinpos != qintail) { 4919 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4920 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4921 /* 4922 * We found an scb that needs to be removed. 4923 */ 4924 switch (action) { 4925 case SEARCH_COMPLETE: 4926 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4927 scbp->flags |= status; 4928 scbp->xs->error = XS_NOERROR; 4929 } 4930 ahc_freeze_ccb(scbp); 4931 ahc_done(ahc, scbp); 4932 break; 4933 case SEARCH_COUNT: 4934 ahc->qinfifo[ahc->qinfifonext++] = 4935 scbp->hscb->tag; 4936 break; 4937 case SEARCH_REMOVE: 4938 break; 4939 } 4940 found++; 4941 } else { 4942 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4943 } 4944 qinpos++; 4945 } 4946 4947 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4948 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4949 4950 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4951 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4952 } else { 4953 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4954 } 4955 4956 return (found); 4957 } 4958 4959 /* 4960 * Abort all SCBs that match the given description (target/channel/lun/tag), 4961 * setting their status to the passed in status if the status has not already 4962 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4963 * is paused before it is called. 4964 */ 4965 static int 4966 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4967 int lun, u_int tag, role_t role, int status) 4968 { 4969 struct scb *scbp; 4970 u_int active_scb; 4971 int i; 4972 int found; 4973 4974 /* restore this when we're done */ 4975 active_scb = ahc_inb(ahc, SCBPTR); 4976 4977 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4978 role, SCB_REQUEUE, SEARCH_COMPLETE); 4979 4980 /* 4981 * Search waiting for selection list. 4982 */ 4983 { 4984 u_int8_t next, prev; 4985 4986 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4987 prev = SCB_LIST_NULL; 4988 4989 while (next != SCB_LIST_NULL) { 4990 u_int8_t scb_index; 4991 4992 ahc_outb(ahc, SCBPTR, next); 4993 scb_index = ahc_inb(ahc, SCB_TAG); 4994 if (scb_index >= ahc->scb_data->numscbs) { 4995 panic("Waiting List inconsistency. " 4996 "SCB index == %d, yet numscbs == %d.", 4997 scb_index, ahc->scb_data->numscbs); 4998 } 4999 scbp = &ahc->scb_data->scbarray[scb_index]; 5000 if (ahc_match_scb(scbp, target, channel, 5001 lun, SCB_LIST_NULL, role)) { 5002 5003 next = ahc_abort_wscb(ahc, next, prev); 5004 } else { 5005 5006 prev = next; 5007 next = ahc_inb(ahc, SCB_NEXT); 5008 } 5009 } 5010 } 5011 /* 5012 * Go through the disconnected list and remove any entries we 5013 * have queued for completion, 0'ing their control byte too. 5014 * We save the active SCB and restore it ourselves, so there 5015 * is no reason for this search to restore it too. 5016 */ 5017 ahc_search_disc_list(ahc, target, channel, lun, tag, 5018 /*stop_on_first*/FALSE, /*remove*/TRUE, 5019 /*save_state*/FALSE); 5020 5021 /* 5022 * Go through the hardware SCB array looking for commands that 5023 * were active but not on any list. 5024 */ 5025 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5026 u_int scbid; 5027 5028 ahc_outb(ahc, SCBPTR, i); 5029 scbid = ahc_inb(ahc, SCB_TAG); 5030 scbp = &ahc->scb_data->scbarray[scbid]; 5031 if (scbid < ahc->scb_data->numscbs 5032 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5033 ahc_add_curscb_to_free_list(ahc); 5034 } 5035 5036 /* 5037 * Go through the pending CCB list and look for 5038 * commands for this target that are still active. 5039 * These are other tagged commands that were 5040 * disconnected when the reset occured. 5041 */ 5042 { 5043 struct scb *scb; 5044 5045 scb = ahc->pending_ccbs.lh_first; 5046 while (scb != NULL) { 5047 scbp = scb; 5048 scb = scb->plinks.le_next; 5049 if (ahc_match_scb(scbp, target, channel, 5050 lun, tag, role)) { 5051 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5052 ahcsetccbstatus(scbp->xs, status); 5053 ahc_freeze_ccb(scbp); 5054 ahc_done(ahc, scbp); 5055 found++; 5056 } 5057 } 5058 } 5059 ahc_outb(ahc, SCBPTR, active_scb); 5060 return found; 5061 } 5062 5063 static int 5064 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5065 int lun, u_int tag, int stop_on_first, int remove, 5066 int save_state) 5067 { 5068 struct scb *scbp; 5069 u_int next; 5070 u_int prev; 5071 u_int count; 5072 u_int active_scb; 5073 5074 count = 0; 5075 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5076 prev = SCB_LIST_NULL; 5077 5078 if (save_state) { 5079 /* restore this when we're done */ 5080 active_scb = ahc_inb(ahc, SCBPTR); 5081 } else 5082 /* Silence compiler */ 5083 active_scb = SCB_LIST_NULL; 5084 5085 while (next != SCB_LIST_NULL) { 5086 u_int scb_index; 5087 5088 ahc_outb(ahc, SCBPTR, next); 5089 scb_index = ahc_inb(ahc, SCB_TAG); 5090 if (scb_index >= ahc->scb_data->numscbs) { 5091 panic("Disconnected List inconsistency. " 5092 "SCB index == %d, yet numscbs == %d.", 5093 scb_index, ahc->scb_data->numscbs); 5094 } 5095 scbp = &ahc->scb_data->scbarray[scb_index]; 5096 if (ahc_match_scb(scbp, target, channel, lun, 5097 tag, ROLE_INITIATOR)) { 5098 count++; 5099 if (remove) { 5100 next = 5101 ahc_rem_scb_from_disc_list(ahc, prev, next); 5102 } else { 5103 prev = next; 5104 next = ahc_inb(ahc, SCB_NEXT); 5105 } 5106 if (stop_on_first) 5107 break; 5108 } else { 5109 prev = next; 5110 next = ahc_inb(ahc, SCB_NEXT); 5111 } 5112 } 5113 if (save_state) 5114 ahc_outb(ahc, SCBPTR, active_scb); 5115 return (count); 5116 } 5117 5118 static u_int 5119 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5120 { 5121 u_int next; 5122 5123 ahc_outb(ahc, SCBPTR, scbptr); 5124 next = ahc_inb(ahc, SCB_NEXT); 5125 5126 ahc_outb(ahc, SCB_CONTROL, 0); 5127 5128 ahc_add_curscb_to_free_list(ahc); 5129 5130 if (prev != SCB_LIST_NULL) { 5131 ahc_outb(ahc, SCBPTR, prev); 5132 ahc_outb(ahc, SCB_NEXT, next); 5133 } else 5134 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5135 5136 return (next); 5137 } 5138 5139 static void 5140 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5141 { 5142 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5143 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5144 5145 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5146 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5147 } 5148 5149 /* 5150 * Manipulate the waiting for selection list and return the 5151 * scb that follows the one that we remove. 5152 */ 5153 static u_int 5154 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5155 { 5156 u_int curscb, next; 5157 5158 /* 5159 * Select the SCB we want to abort and 5160 * pull the next pointer out of it. 5161 */ 5162 curscb = ahc_inb(ahc, SCBPTR); 5163 ahc_outb(ahc, SCBPTR, scbpos); 5164 next = ahc_inb(ahc, SCB_NEXT); 5165 5166 /* Clear the necessary fields */ 5167 ahc_outb(ahc, SCB_CONTROL, 0); 5168 5169 ahc_add_curscb_to_free_list(ahc); 5170 5171 /* update the waiting list */ 5172 if (prev == SCB_LIST_NULL) { 5173 /* First in the list */ 5174 ahc_outb(ahc, WAITING_SCBH, next); 5175 5176 /* 5177 * Ensure we aren't attempting to perform 5178 * selection for this entry. 5179 */ 5180 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5181 } else { 5182 /* 5183 * Select the scb that pointed to us 5184 * and update its next pointer. 5185 */ 5186 ahc_outb(ahc, SCBPTR, prev); 5187 ahc_outb(ahc, SCB_NEXT, next); 5188 } 5189 5190 /* 5191 * Point us back at the original scb position. 5192 */ 5193 ahc_outb(ahc, SCBPTR, curscb); 5194 return next; 5195 } 5196 5197 static void 5198 ahc_clear_intstat(struct ahc_softc *ahc) 5199 { 5200 /* Clear any interrupt conditions this may have caused */ 5201 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5202 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5203 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5204 CLRREQINIT); 5205 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5206 } 5207 5208 static void 5209 ahc_reset_current_bus(struct ahc_softc *ahc) 5210 { 5211 u_int8_t scsiseq; 5212 5213 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5214 scsiseq = ahc_inb(ahc, SCSISEQ); 5215 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5216 DELAY(AHC_BUSRESET_DELAY); 5217 /* Turn off the bus reset */ 5218 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5219 5220 ahc_clear_intstat(ahc); 5221 5222 /* Re-enable reset interrupts */ 5223 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5224 } 5225 5226 static int 5227 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5228 { 5229 u_int initiator, target, max_scsiid; 5230 u_int sblkctl; 5231 u_int our_id; 5232 int found; 5233 int restart_needed; 5234 char cur_channel; 5235 5236 ahc->pending_device = NULL; 5237 5238 pause_sequencer(ahc); 5239 5240 /* 5241 * Run our command complete fifos to ensure that we perform 5242 * completion processing on any commands that 'completed' 5243 * before the reset occurred. 5244 */ 5245 ahc_run_qoutfifo(ahc); 5246 5247 /* 5248 * Reset the bus if we are initiating this reset 5249 */ 5250 sblkctl = ahc_inb(ahc, SBLKCTL); 5251 cur_channel = 'A'; 5252 if ((ahc->features & AHC_TWIN) != 0 5253 && ((sblkctl & SELBUSB) != 0)) 5254 cur_channel = 'B'; 5255 if (cur_channel != channel) { 5256 /* Case 1: Command for another bus is active 5257 * Stealthily reset the other bus without 5258 * upsetting the current bus. 5259 */ 5260 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5261 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5262 ahc_outb(ahc, SCSISEQ, 5263 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5264 if (initiate_reset) 5265 ahc_reset_current_bus(ahc); 5266 ahc_clear_intstat(ahc); 5267 ahc_outb(ahc, SBLKCTL, sblkctl); 5268 restart_needed = FALSE; 5269 } else { 5270 /* Case 2: A command from this bus is active or we're idle */ 5271 ahc_clear_msg_state(ahc); 5272 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5273 ahc_outb(ahc, SCSISEQ, 5274 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5275 if (initiate_reset) 5276 ahc_reset_current_bus(ahc); 5277 ahc_clear_intstat(ahc); 5278 5279 /* 5280 * Since we are going to restart the sequencer, avoid 5281 * a race in the sequencer that could cause corruption 5282 * of our Q pointers by starting over from index 0. 5283 */ 5284 ahc->qoutfifonext = 0; 5285 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5286 ahc_outb(ahc, SDSCB_QOFF, 0); 5287 else 5288 ahc_outb(ahc, QOUTPOS, 0); 5289 restart_needed = TRUE; 5290 } 5291 5292 /* 5293 * Clean up all the state information for the 5294 * pending transactions on this bus. 5295 */ 5296 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5297 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5298 ROLE_UNKNOWN, XS_RESET); 5299 if (channel == 'B') { 5300 our_id = ahc->our_id_b; 5301 } else { 5302 our_id = ahc->our_id; 5303 } 5304 5305 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5306 5307 /* 5308 * Revert to async/narrow transfers until we renegotiate. 5309 */ 5310 for (target = 0; target <= max_scsiid; target++) { 5311 5312 if (ahc->enabled_targets[target] == NULL) 5313 continue; 5314 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5315 struct ahc_devinfo devinfo; 5316 5317 ahc_compile_devinfo(&devinfo, target, initiator, 5318 AHC_LUN_WILDCARD, 5319 channel, ROLE_UNKNOWN); 5320 ahc_set_width(ahc, &devinfo, 5321 MSG_EXT_WDTR_BUS_8_BIT, 5322 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5323 ahc_set_syncrate(ahc, &devinfo, 5324 /*syncrate*/NULL, /*period*/0, 5325 /*offset*/0, AHC_TRANS_CUR, 5326 /*paused*/TRUE, FALSE); 5327 } 5328 } 5329 5330 if (restart_needed) 5331 restart_sequencer(ahc); 5332 else 5333 unpause_sequencer(ahc); 5334 return found; 5335 } 5336 5337 static int 5338 ahc_match_scb(struct scb *scb, int target, char channel, 5339 int lun, u_int tag, role_t role) 5340 { 5341 int targ = SCB_TARGET(scb); 5342 char chan = SCB_CHANNEL(scb); 5343 int slun = SCB_LUN(scb); 5344 int match; 5345 5346 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5347 if (match != 0) 5348 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5349 if (match != 0) 5350 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5351 5352 return match; 5353 } 5354 5355 static void 5356 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5357 { 5358 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5359 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5360 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5361 ahc->msgout_buf[ahc->msgout_index++] = period; 5362 ahc->msgout_buf[ahc->msgout_index++] = offset; 5363 ahc->msgout_len += 5; 5364 } 5365 5366 static void 5367 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5368 { 5369 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5370 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5371 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5372 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5373 ahc->msgout_len += 4; 5374 } 5375 5376 static void 5377 ahc_calc_residual(struct scb *scb) 5378 { 5379 struct hardware_scb *hscb; 5380 5381 hscb = scb->hscb; 5382 5383 /* 5384 * If the disconnected flag is still set, this is bogus 5385 * residual information left over from a sequencer 5386 * pagin/pageout, so ignore this case. 5387 */ 5388 if ((scb->hscb->control & DISCONNECTED) == 0) { 5389 u_int32_t resid; 5390 int resid_sgs; 5391 int sg; 5392 5393 /* 5394 * Remainder of the SG where the transfer 5395 * stopped. 5396 */ 5397 resid = (hscb->residual_data_count[2] << 16) 5398 | (hscb->residual_data_count[1] <<8) 5399 | (hscb->residual_data_count[0]); 5400 5401 /* 5402 * Add up the contents of all residual 5403 * SG segments that are after the SG where 5404 * the transfer stopped. 5405 */ 5406 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5407 sg = scb->sg_count - resid_sgs; 5408 while (resid_sgs > 0) { 5409 5410 resid += le32toh(scb->sg_list[sg].len); 5411 sg++; 5412 resid_sgs--; 5413 } 5414 scb->xs->resid = resid; 5415 } 5416 5417 /* 5418 * Clean out the residual information in this SCB for its 5419 * next consumer. 5420 */ 5421 hscb->residual_SG_count = 0; 5422 5423 #ifdef AHC_DEBUG 5424 if (ahc_debug & AHC_SHOWMISC) { 5425 scsi_print_addr(scb->xs->sc_link); 5426 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5427 } 5428 #endif 5429 } 5430 5431 static void 5432 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5433 { 5434 struct scb *scb; 5435 int pending_ccb_count; 5436 int i; 5437 u_int saved_scbptr; 5438 5439 /* 5440 * Traverse the pending SCB list and ensure that all of the 5441 * SCBs there have the proper settings. 5442 */ 5443 scb = LIST_FIRST(&ahc->pending_ccbs); 5444 pending_ccb_count = 0; 5445 while (scb != NULL) { 5446 struct ahc_devinfo devinfo; 5447 struct scsipi_xfer *xs; 5448 struct scb *pending_scb; 5449 struct hardware_scb *pending_hscb; 5450 struct ahc_initiator_tinfo *tinfo; 5451 struct tmode_tstate *tstate; 5452 u_int our_id, remote_id; 5453 5454 xs = scb->xs; 5455 pending_scb = scb; 5456 pending_hscb = pending_scb->hscb; 5457 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5458 ? ahc->our_id_b : ahc->our_id; 5459 remote_id = xs->sc_link->scsipi_scsi.target; 5460 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5461 SCB_LUN(pending_scb), 5462 SCB_CHANNEL(pending_scb), 5463 ROLE_UNKNOWN); 5464 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5465 our_id, remote_id, &tstate); 5466 pending_hscb->control &= ~ULTRAENB; 5467 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5468 pending_hscb->control |= ULTRAENB; 5469 pending_hscb->scsirate = tinfo->scsirate; 5470 pending_hscb->scsioffset = tinfo->current.offset; 5471 pending_ccb_count++; 5472 scb = LIST_NEXT(scb, plinks); 5473 } 5474 5475 if (pending_ccb_count == 0) 5476 return; 5477 5478 saved_scbptr = ahc_inb(ahc, SCBPTR); 5479 /* Ensure that the hscbs down on the card match the new information */ 5480 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5481 u_int scb_tag; 5482 5483 ahc_outb(ahc, SCBPTR, i); 5484 scb_tag = ahc_inb(ahc, SCB_TAG); 5485 if (scb_tag != SCB_LIST_NULL) { 5486 struct ahc_devinfo devinfo; 5487 struct scb *pending_scb; 5488 struct scsipi_xfer *xs; 5489 struct hardware_scb *pending_hscb; 5490 struct ahc_initiator_tinfo *tinfo; 5491 struct tmode_tstate *tstate; 5492 u_int our_id, remote_id; 5493 u_int control; 5494 5495 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5496 if (pending_scb->flags == SCB_FREE) 5497 continue; 5498 pending_hscb = pending_scb->hscb; 5499 xs = pending_scb->xs; 5500 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5501 ? ahc->our_id_b : ahc->our_id; 5502 remote_id = xs->sc_link->scsipi_scsi.target; 5503 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5504 SCB_LUN(pending_scb), 5505 SCB_CHANNEL(pending_scb), 5506 ROLE_UNKNOWN); 5507 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5508 our_id, remote_id, &tstate); 5509 control = ahc_inb(ahc, SCB_CONTROL); 5510 control &= ~ULTRAENB; 5511 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5512 control |= ULTRAENB; 5513 ahc_outb(ahc, SCB_CONTROL, control); 5514 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5515 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5516 } 5517 } 5518 ahc_outb(ahc, SCBPTR, saved_scbptr); 5519 } 5520 5521 #if UNUSED 5522 static void 5523 ahc_dump_targcmd(struct target_cmd *cmd) 5524 { 5525 u_int8_t *byte; 5526 u_int8_t *last_byte; 5527 int i; 5528 5529 byte = &cmd->initiator_channel; 5530 /* Debugging info for received commands */ 5531 last_byte = &cmd[1].initiator_channel; 5532 5533 i = 0; 5534 while (byte < last_byte) { 5535 if (i == 0) 5536 printf("\t"); 5537 printf("%#x", *byte++); 5538 i++; 5539 if (i == 8) { 5540 printf("\n"); 5541 i = 0; 5542 } else { 5543 printf(", "); 5544 } 5545 } 5546 } 5547 #endif 5548 5549 static void 5550 ahc_shutdown(void *arg) 5551 { 5552 struct ahc_softc *ahc; 5553 int i; 5554 u_int sxfrctl1_a, sxfrctl1_b; 5555 5556 ahc = (struct ahc_softc *)arg; 5557 5558 pause_sequencer(ahc); 5559 5560 /* 5561 * Preserve the value of the SXFRCTL1 register for all channels. 5562 * It contains settings that affect termination and we don't want 5563 * to disturb the integrity of the bus during shutdown in case 5564 * we are in a multi-initiator setup. 5565 */ 5566 sxfrctl1_b = 0; 5567 if ((ahc->features & AHC_TWIN) != 0) { 5568 u_int sblkctl; 5569 5570 sblkctl = ahc_inb(ahc, SBLKCTL); 5571 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5572 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5573 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5574 } 5575 5576 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5577 5578 /* This will reset most registers to 0, but not all */ 5579 ahc_reset(ahc); 5580 5581 if ((ahc->features & AHC_TWIN) != 0) { 5582 u_int sblkctl; 5583 5584 sblkctl = ahc_inb(ahc, SBLKCTL); 5585 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5586 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5587 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5588 } 5589 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5590 5591 ahc_outb(ahc, SCSISEQ, 0); 5592 ahc_outb(ahc, SXFRCTL0, 0); 5593 ahc_outb(ahc, DSPCISTATUS, 0); 5594 5595 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5596 ahc_outb(ahc, i, 0); 5597 } 5598 5599 #if defined(AHC_DEBUG) && 0 5600 static void 5601 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5602 { 5603 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5604 5605 printf("\tcurrent:\n"); 5606 printf("\t\twidth %u period %u offset %u flags %x\n", 5607 tinfo->current.width, tinfo->current.period, 5608 tinfo->current.offset, tinfo->current.ppr_flags); 5609 5610 printf("\tgoal:\n"); 5611 printf("\t\twidth %u period %u offset %u flags %x\n", 5612 tinfo->goal.width, tinfo->goal.period, 5613 tinfo->goal.offset, tinfo->goal.ppr_flags); 5614 5615 printf("\tuser:\n"); 5616 printf("\t\twidth %u period %u offset %u flags %x\n", 5617 tinfo->user.width, tinfo->user.period, 5618 tinfo->user.offset, tinfo->user.ppr_flags); 5619 } 5620 #endif 5621 5622 static void 5623 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5624 { 5625 struct scsipi_inquiry_data *inq; 5626 struct ahc_devinfo devinfo; 5627 struct tmode_tstate *tstate; 5628 int target_id, our_id; 5629 char channel; 5630 5631 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5632 return; 5633 5634 if (xs->sc_link->quirks & SDEV_NOTAG) 5635 return; 5636 5637 target_id = xs->sc_link->scsipi_scsi.target; 5638 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5639 channel = SIM_CHANNEL(ahc, xs->sc_link); 5640 5641 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5642 ahc_compile_devinfo(&devinfo, our_id, target_id, 5643 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5644 5645 if (tstate->tagdisable & devinfo.target_mask) 5646 return; 5647 5648 /* 5649 * Sneak a look at the results of the SCSI Inquiry 5650 * command and see if we can do Tagged queing. This 5651 * should really be done by the higher level drivers. 5652 */ 5653 inq = (struct scsipi_inquiry_data *)xs->data; 5654 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5655 printf("%s: target %d using tagged queuing\n", 5656 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5657 5658 ahc_set_tags(ahc, &devinfo, TRUE); 5659 5660 if (ahc->scb_data->maxhscbs >= 16 || 5661 (ahc->flags & AHC_PAGESCBS)) { 5662 /* Default to 16 tags */ 5663 xs->sc_link->openings = 16; 5664 } else { 5665 /* 5666 * Default to 4 tags on whimpy 5667 * cards that don't have much SCB 5668 * space and can't page. This prevents 5669 * a single device from hogging all 5670 * slots. We should really have a better 5671 * way of providing fairness. 5672 */ 5673 xs->sc_link->openings = 4; 5674 } 5675 } 5676 } 5677 5678 static int 5679 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5680 int nocmdcheck) 5681 { 5682 char channel; 5683 u_int our_id, target; 5684 struct tmode_tstate *tstate; 5685 struct ahc_devinfo devinfo; 5686 5687 if (xs->sc_link->quirks & SDEV_NOTAG) 5688 return 0; 5689 5690 /* 5691 * XXX never do these commands with tags. Should really be 5692 * in a higher layer. 5693 */ 5694 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5695 xs->cmd->opcode == TEST_UNIT_READY || 5696 xs->cmd->opcode == REQUEST_SENSE)) 5697 return 0; 5698 5699 channel = SIM_CHANNEL(ahc, xs->sc_link); 5700 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5701 target = xs->sc_link->scsipi_scsi.target; 5702 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5703 5704 ahc_compile_devinfo(&devinfo, our_id, target, 5705 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5706 5707 return (tstate->tagenable & devinfo.target_mask); 5708 } 5709
Indexes created Thu Oct 02 01:09:59 GMT 2025