aic7xxx.c revision 1.62
1 /* $NetBSD: aic7xxx.c,v 1.62 2000/12/02 14:53:01 fvdl Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 #include "opt_ahc.h" 91 92 #include <sys/param.h> 93 #include <sys/kernel.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/malloc.h> 97 #include <sys/buf.h> 98 #include <sys/proc.h> 99 #include <sys/scsiio.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <uvm/uvm_extern.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 118 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 119 #define ALL_CHANNELS '\0' 120 #define ALL_TARGETS_MASK 0xFFFF 121 #define INITIATOR_WILDCARD (~0) 122 123 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 124 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 125 #define SIM_CHANNEL(ahc, sc_link) \ 126 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 127 #define SIM_SCSI_ID(ahc, sc_link) \ 128 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 129 #define SCB_IS_SCSIBUS_B(scb) \ 130 (((scb)->hscb->tcl & SELBUSB) != 0) 131 #define SCB_TARGET(scb) \ 132 (((scb)->hscb->tcl & TID) >> 4) 133 #define SCB_CHANNEL(scb) \ 134 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 135 #define SCB_LUN(scb) \ 136 ((scb)->hscb->tcl & LID) 137 #define SCB_TARGET_OFFSET(scb) \ 138 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 139 #define SCB_TARGET_MASK(scb) \ 140 (0x01 << (SCB_TARGET_OFFSET(scb))) 141 #define TCL_CHANNEL(ahc, tcl) \ 142 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 143 #define TCL_SCSI_ID(ahc, tcl) \ 144 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 145 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 146 #define TCL_LUN(tcl) ((tcl) & LID) 147 148 #define XS_TCL(ahc, xs) \ 149 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 150 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 151 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 152 153 char *ahc_chip_names[] = 154 { 155 "NONE", 156 "aic7770", 157 "aic7850", 158 "aic7855", 159 "aic7859", 160 "aic7860", 161 "aic7870", 162 "aic7880", 163 "aic7890/91", 164 "aic7892", 165 "aic7895", 166 "aic7896/97", 167 "aic7899" 168 }; 169 170 typedef enum { 171 ROLE_UNKNOWN, 172 ROLE_INITIATOR, 173 ROLE_TARGET 174 } role_t; 175 176 struct ahc_devinfo { 177 int our_scsiid; 178 int target_offset; 179 u_int16_t target_mask; 180 u_int8_t target; 181 u_int8_t lun; 182 char channel; 183 role_t role; /* 184 * Only guaranteed to be correct if not 185 * in the busfree state. 186 */ 187 }; 188 189 typedef enum { 190 SEARCH_COMPLETE, 191 SEARCH_COUNT, 192 SEARCH_REMOVE 193 } ahc_search_action; 194 195 #ifdef AHC_DEBUG 196 static int ahc_debug = AHC_DEBUG; 197 #endif 198 199 static int ahcinitscbdata(struct ahc_softc *); 200 static void ahcfiniscbdata(struct ahc_softc *); 201 202 #if UNUSED 203 static void ahc_dump_targcmd(struct target_cmd *); 204 #endif 205 static void ahc_shutdown(void *arg); 206 static int32_t ahc_action(struct scsipi_xfer *); 207 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 208 struct proc *); 209 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 210 static int ahc_poll(struct ahc_softc *, int); 211 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 212 struct scb *); 213 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 214 static void ahcallocscbs(struct ahc_softc *); 215 #if UNUSED 216 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 217 struct scb *); 218 #endif 219 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 220 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 221 char, role_t); 222 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 223 static void ahc_done(struct ahc_softc *, struct scb *); 224 static struct tmode_tstate * 225 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 226 #if UNUSED 227 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 228 #endif 229 static void ahc_handle_seqint(struct ahc_softc *, u_int); 230 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 231 static void ahc_build_transfer_msg(struct ahc_softc *, 232 struct ahc_devinfo *); 233 static void ahc_setup_initiator_msgout(struct ahc_softc *, 234 struct ahc_devinfo *, 235 struct scb *); 236 static void ahc_setup_target_msgin(struct ahc_softc *, 237 struct ahc_devinfo *); 238 static void ahc_clear_msg_state(struct ahc_softc *); 239 static void ahc_handle_message_phase(struct ahc_softc *, 240 struct scsipi_link *); 241 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 242 243 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 244 struct ahc_devinfo *); 245 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 246 struct ahc_devinfo *); 247 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 248 int, char *, int); 249 #ifdef AHC_DUMP_SEQ 250 static void ahc_dumpseq(struct ahc_softc *); 251 #endif 252 static void ahc_loadseq(struct ahc_softc *); 253 static int ahc_check_patch(struct ahc_softc *, struct patch **, 254 int, int *); 255 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 256 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 257 #if defined(AHC_DEBUG) 258 static void ahc_print_scb(struct scb *); 259 #endif 260 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 261 role_t, scb_flag, ahc_search_action); 262 static int ahc_reset_channel(struct ahc_softc *, char, int); 263 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 264 role_t, int); 265 static int ahc_search_disc_list(struct ahc_softc *, int, 266 char, int, u_int, int, int, int); 267 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 268 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 269 static void ahc_clear_intstat(struct ahc_softc *); 270 static void ahc_reset_current_bus(struct ahc_softc *); 271 static struct ahc_syncrate * 272 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 273 static struct ahc_syncrate * 274 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 275 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 276 static void ahc_validate_offset(struct ahc_softc *, struct ahc_syncrate *, 277 u_int *, int); 278 static void ahc_update_target_msg_request(struct ahc_softc *, 279 struct ahc_devinfo *, 280 struct ahc_initiator_tinfo *, 281 int, int); 282 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 283 struct ahc_syncrate *, u_int, u_int, u_int, 284 int, int); 285 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 286 u_int, u_int, int, int); 287 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 288 int); 289 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 290 291 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 292 293 static void ahc_calc_residual(struct scb *); 294 295 static void ahc_update_pending_syncrates(struct ahc_softc *); 296 297 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 298 299 static void ahc_timeout (void *); 300 static __inline int sequencer_paused(struct ahc_softc *); 301 static __inline void pause_sequencer(struct ahc_softc *); 302 static __inline void unpause_sequencer(struct ahc_softc *); 303 static void restart_sequencer(struct ahc_softc *); 304 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 305 306 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 307 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 308 309 static __inline void ahc_freeze_ccb(struct scb *); 310 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 311 static void ahc_run_qoutfifo(struct ahc_softc *); 312 313 static __inline struct ahc_initiator_tinfo * 314 ahc_fetch_transinfo(struct ahc_softc *, 315 char, u_int, u_int, 316 struct tmode_tstate **); 317 static void ahcfreescb(struct ahc_softc *, struct scb *); 318 static __inline struct scb *ahcgetscb(struct ahc_softc *); 319 320 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 321 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 322 int *, const char *, const char *); 323 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 324 caddr_t, bus_dma_segment_t *, int); 325 static void ahcminphys(struct buf *); 326 327 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 328 static __inline void ahc_swap_hscb(struct hardware_scb *); 329 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 330 #ifndef AHC_NO_TAGS 331 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 332 #endif 333 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 334 335 #if defined(AHC_DEBUG) && 0 336 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 337 #endif 338 339 static struct scsipi_device ahc_dev = 340 { 341 NULL, /* Use default error handler */ 342 NULL, /* have a queue, served by this */ 343 NULL, /* have no async handler */ 344 NULL, /* Use default 'done' routine */ 345 }; 346 347 /* 348 * Pick the first xs for a non-blocked target. 349 */ 350 static __inline struct scsipi_xfer * 351 ahc_first_xs(struct ahc_softc *ahc) 352 { 353 int target; 354 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 355 356 if (ahc->queue_blocked) 357 return NULL; 358 359 while (xs != NULL) { 360 target = xs->sc_link->scsipi_scsi.target; 361 if (ahc->devqueue_blocked[target] == 0 && 362 (ahc_istagged_device(ahc, xs, 0) || 363 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 364 SCB_LIST_NULL)) 365 break; 366 xs = TAILQ_NEXT(xs, adapter_q); 367 } 368 369 return xs; 370 } 371 372 static __inline void 373 ahc_swap_hscb(struct hardware_scb *hscb) 374 { 375 hscb->SG_pointer = htole32(hscb->SG_pointer); 376 hscb->data = htole32(hscb->data); 377 hscb->datalen = htole32(hscb->datalen); 378 /* 379 * No need to swap cmdpointer; it's either 0 or set to 380 * cmdstore_busaddr, which is already swapped. 381 */ 382 } 383 384 static __inline void 385 ahc_swap_sg(struct ahc_dma_seg *sg) 386 { 387 sg->addr = htole32(sg->addr); 388 sg->len = htole32(sg->len); 389 } 390 391 static void 392 ahcminphys(bp) 393 struct buf *bp; 394 { 395 /* 396 * Even though the card can transfer up to 16megs per command 397 * we are limited by the number of segments in the dma segment 398 * list that we can hold. The worst case is that all pages are 399 * discontinuous physically, hense the "page per segment" limit 400 * enforced here. 401 */ 402 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 403 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 404 } 405 minphys(bp); 406 } 407 408 409 static __inline u_int32_t 410 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 411 { 412 return (ahc->scb_data->hscb_busaddr 413 + (sizeof(struct hardware_scb) * index)); 414 } 415 416 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 417 418 static __inline int 419 sequencer_paused(struct ahc_softc *ahc) 420 { 421 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 422 } 423 424 static __inline void 425 pause_sequencer(struct ahc_softc *ahc) 426 { 427 ahc_outb(ahc, HCNTRL, ahc->pause); 428 429 /* 430 * Since the sequencer can disable pausing in a critical section, we 431 * must loop until it actually stops. 432 */ 433 while (sequencer_paused(ahc) == 0) 434 ; 435 } 436 437 static __inline void 438 unpause_sequencer(struct ahc_softc *ahc) 439 { 440 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 441 ahc_outb(ahc, HCNTRL, ahc->unpause); 442 } 443 444 /* 445 * Restart the sequencer program from address zero 446 */ 447 static void 448 restart_sequencer(struct ahc_softc *ahc) 449 { 450 u_int i; 451 452 pause_sequencer(ahc); 453 454 /* 455 * Everytime we restart the sequencer, there 456 * is the possiblitity that we have restarted 457 * within a three instruction window where an 458 * SCB has been marked free but has not made it 459 * onto the free list. Since SCSI events(bus reset, 460 * unexpected bus free) will always freeze the 461 * sequencer, we cannot close this window. To 462 * avoid losing an SCB, we reconsitute the free 463 * list every time we restart the sequencer. 464 */ 465 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 466 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 467 468 ahc_outb(ahc, SCBPTR, i); 469 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 470 ahc_add_curscb_to_free_list(ahc); 471 } 472 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 473 unpause_sequencer(ahc); 474 } 475 476 static __inline u_int 477 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 478 { 479 u_int scbid; 480 481 scbid = ahc->untagged_scbs[tcl]; 482 if (unbusy) { 483 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 484 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 485 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 486 } 487 488 return (scbid); 489 } 490 491 static __inline void 492 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 493 { 494 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 495 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 496 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 497 } 498 499 static __inline int 500 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 501 { 502 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 503 } 504 505 static __inline void 506 ahc_freeze_ccb(struct scb *scb) 507 { 508 struct scsipi_xfer *xs = scb->xs; 509 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 510 int target; 511 512 target = xs->sc_link->scsipi_scsi.target; 513 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 514 ahc->devqueue_blocked[target]++; 515 scb->flags |= SCB_FREEZE_QUEUE; 516 } 517 } 518 519 static __inline void 520 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 521 { 522 xs->error = status; 523 } 524 525 static __inline struct ahc_initiator_tinfo * 526 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 527 u_int remote_id, struct tmode_tstate **tstate) 528 { 529 /* 530 * Transfer data structures are stored from the perspective 531 * of the target role. Since the parameters for a connection 532 * in the initiator role to a given target are the same as 533 * when the roles are reversed, we pretend we are the target. 534 */ 535 if (channel == 'B') 536 our_id += 8; 537 *tstate = ahc->enabled_targets[our_id]; 538 return (&(*tstate)->transinfo[remote_id]); 539 } 540 541 static void 542 ahc_run_qoutfifo(struct ahc_softc *ahc) 543 { 544 struct scb *scb; 545 u_int scb_index; 546 547 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 548 256, BUS_DMASYNC_POSTREAD); 549 550 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 551 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 552 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 553 554 scb = &ahc->scb_data->scbarray[scb_index]; 555 if (scb_index >= ahc->scb_data->numscbs 556 || (scb->flags & SCB_ACTIVE) == 0) { 557 printf("%s: WARNING no command for scb %d " 558 "(cmdcmplt)\nQOUTPOS = %d\n", 559 ahc_name(ahc), scb_index, 560 ahc->qoutfifonext - 1); 561 continue; 562 } 563 564 /* 565 * Save off the residual 566 * if there is one. 567 */ 568 if (scb->hscb->residual_SG_count != 0) 569 ahc_calc_residual(scb); 570 else 571 scb->xs->resid = 0; 572 #ifdef AHC_DEBUG 573 if (ahc_debug & AHC_SHOWSCBS) { 574 scsi_print_addr(scb->xs->sc_link); 575 printf("run_qoutfifo: SCB %x complete\n", 576 scb->hscb->tag); 577 } 578 #endif 579 ahc_done(ahc, scb); 580 } 581 } 582 583 584 /* 585 * An scb (and hence an scb entry on the board) is put onto the 586 * free list. 587 */ 588 static void 589 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 590 { 591 struct hardware_scb *hscb; 592 int opri; 593 594 hscb = scb->hscb; 595 596 #ifdef AHC_DEBUG 597 if (ahc_debug & AHC_SHOWSCBALLOC) 598 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 599 #endif 600 601 opri = splbio(); 602 603 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 604 (scb->flags & SCB_RECOVERY_SCB) != 0) { 605 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 606 ahc->queue_blocked = 0; 607 } 608 609 /* Clean up for the next user */ 610 scb->flags = SCB_FREE; 611 hscb->control = 0; 612 hscb->status = 0; 613 614 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 615 616 splx(opri); 617 } 618 619 /* 620 * Get a free scb, either one already assigned to a hardware slot 621 * on the adapter or one that will require an SCB to be paged out before 622 * use. If there are none, see if we can allocate a new SCB. Otherwise 623 * either return an error or sleep. 624 */ 625 static __inline struct scb * 626 ahcgetscb(struct ahc_softc *ahc) 627 { 628 struct scb *scbp; 629 int opri;; 630 631 opri = splbio(); 632 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 633 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 634 } else { 635 ahcallocscbs(ahc); 636 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 637 if (scbp != NULL) 638 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 639 } 640 641 splx(opri); 642 643 #ifdef AHC_DEBUG 644 if (ahc_debug & AHC_SHOWSCBALLOC) { 645 if (scbp != NULL) 646 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 647 scbp->hscb->tag); 648 else 649 printf("%s: failed to allocate new SCB\n", 650 ahc_name(ahc)); 651 } 652 #endif 653 654 return (scbp); 655 } 656 657 static int 658 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 659 bus_dma_tag_t tag; 660 int size; 661 int flags; 662 bus_dmamap_t *mapp; 663 caddr_t *vaddr; 664 bus_addr_t *baddr; 665 bus_dma_segment_t *seg; 666 int *nseg; 667 const char *myname, *what; 668 { 669 int error, level = 0; 670 671 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 672 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 673 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 674 myname, what, error); 675 goto out; 676 } 677 level++; 678 679 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 680 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 681 printf("%s: failed to map DMA mem for %s, error = %d\n", 682 myname, what, error); 683 goto out; 684 } 685 level++; 686 687 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 688 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 689 printf("%s: failed to create DMA map for %s, error = %d\n", 690 myname, what, error); 691 goto out; 692 } 693 level++; 694 695 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 696 BUS_DMA_NOWAIT)) != 0) { 697 printf("%s: failed to load DMA map for %s, error = %d\n", 698 myname, what, error); 699 goto out; 700 } 701 702 *baddr = (*mapp)->dm_segs[0].ds_addr; 703 704 #ifdef AHC_DEBUG 705 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 706 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 707 *nseg, size); 708 #endif 709 710 return 0; 711 out: 712 switch (level) { 713 case 3: 714 bus_dmamap_destroy(tag, *mapp); 715 /* FALLTHROUGH */ 716 case 2: 717 bus_dmamem_unmap(tag, *vaddr, size); 718 /* FALLTHROUGH */ 719 case 1: 720 bus_dmamem_free(tag, seg, *nseg); 721 break; 722 default: 723 break; 724 } 725 726 return error; 727 } 728 729 static void 730 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 731 bus_dma_tag_t tag; 732 int size; 733 bus_dmamap_t map; 734 caddr_t vaddr; 735 bus_dma_segment_t *seg; 736 int nseg; 737 { 738 739 bus_dmamap_unload(tag, map); 740 bus_dmamap_destroy(tag, map); 741 bus_dmamem_unmap(tag, vaddr, size); 742 bus_dmamem_free(tag, seg, nseg); 743 } 744 745 char * 746 ahc_name(struct ahc_softc *ahc) 747 { 748 return (ahc->sc_dev.dv_xname); 749 } 750 751 #ifdef AHC_DEBUG 752 static void 753 ahc_print_scb(struct scb *scb) 754 { 755 struct hardware_scb *hscb = scb->hscb; 756 757 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 758 scb, 759 hscb->tag, 760 hscb->control, 761 hscb->tcl, 762 hscb->cmdlen, 763 (unsigned long)le32toh(hscb->cmdpointer)); 764 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 765 le32toh(hscb->datalen), 766 (unsigned long)(le32toh(hscb->data)), 767 hscb->SG_count, 768 (unsigned long)(le32toh(hscb->SG_pointer))); 769 printf(" sg_addr:%lx sg_len:%lu\n", 770 (unsigned long)(le32toh(scb->sg_list[0].addr)), 771 (unsigned long)(le32toh(scb->sg_list[0].len))); 772 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 773 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 774 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 775 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 776 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 777 } 778 #endif 779 780 static struct { 781 u_int8_t errno; 782 char *errmesg; 783 } hard_error[] = { 784 { ILLHADDR, "Illegal Host Access" }, 785 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 786 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 787 { SQPARERR, "Sequencer Parity Error" }, 788 { DPARERR, "Data-path Parity Error" }, 789 { MPARERR, "Scratch or SCB Memory Parity Error" }, 790 { PCIERRSTAT, "PCI Error detected" }, 791 { CIOPARERR, "CIOBUS Parity Error" }, 792 }; 793 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 794 795 static struct { 796 u_int8_t phase; 797 u_int8_t mesg_out; /* Message response to parity errors */ 798 char *phasemsg; 799 } phase_table[] = { 800 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 801 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 802 { P_COMMAND, MSG_NOOP, "in Command phase" }, 803 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 804 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 805 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 806 { P_BUSFREE, MSG_NOOP, "while idle" }, 807 { 0, MSG_NOOP, "in unknown phase" } 808 }; 809 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 810 811 /* 812 * Valid SCSIRATE values. (p. 3-17) 813 * Provides a mapping of tranfer periods in ns to the proper value to 814 * stick in the scsiscfr reg to use that transfer rate. 815 */ 816 #define AHC_SYNCRATE_DT 0 817 #define AHC_SYNCRATE_ULTRA2 1 818 #define AHC_SYNCRATE_ULTRA 3 819 #define AHC_SYNCRATE_FAST 6 820 static struct ahc_syncrate ahc_syncrates[] = { 821 /* ultra2 fast/ultra period rate */ 822 { 0x42, 0x000, 9, "80.0" }, 823 { 0x03, 0x000, 10, "40.0" }, 824 { 0x04, 0x000, 11, "33.0" }, 825 { 0x05, 0x100, 12, "20.0" }, 826 { 0x06, 0x110, 15, "16.0" }, 827 { 0x07, 0x120, 18, "13.4" }, 828 { 0x08, 0x000, 25, "10.0" }, 829 { 0x19, 0x010, 31, "8.0" }, 830 { 0x1a, 0x020, 37, "6.67" }, 831 { 0x1b, 0x030, 43, "5.7" }, 832 { 0x1c, 0x040, 50, "5.0" }, 833 { 0x00, 0x050, 56, "4.4" }, 834 { 0x00, 0x060, 62, "4.0" }, 835 { 0x00, 0x070, 68, "3.6" }, 836 { 0x00, 0x000, 0, NULL } 837 }; 838 839 /* 840 * Allocate a controller structure for a new device and initialize it. 841 */ 842 int 843 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 844 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 845 ahc_flag flags) 846 { 847 struct scb_data *scb_data; 848 849 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 850 if (scb_data == NULL) { 851 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 852 return -1; 853 } 854 bzero(scb_data, sizeof (struct scb_data)); 855 LIST_INIT(&ahc->pending_ccbs); 856 ahc->tag = st; 857 ahc->bsh = sh; 858 ahc->parent_dmat = parent_dmat; 859 ahc->chip = chip; 860 ahc->features = features; 861 ahc->flags = flags; 862 ahc->scb_data = scb_data; 863 864 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 865 /* The IRQMS bit is only valid on VL and EISA chips */ 866 if ((ahc->chip & AHC_PCI) != 0) 867 ahc->unpause &= ~IRQMS; 868 ahc->pause = ahc->unpause | PAUSE; 869 return (0); 870 } 871 872 void 873 ahc_free(ahc) 874 struct ahc_softc *ahc; 875 { 876 ahcfiniscbdata(ahc); 877 if (ahc->init_level != 0) 878 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 879 ahc->shared_data_dmamap, ahc->qoutfifo, 880 &ahc->shared_data_seg, ahc->shared_data_nseg); 881 882 if (ahc->scb_data != NULL) 883 free(ahc->scb_data, M_DEVBUF); 884 if (ahc->bus_data != NULL) 885 free(ahc->bus_data, M_DEVBUF); 886 return; 887 } 888 889 static int 890 ahcinitscbdata(struct ahc_softc *ahc) 891 { 892 struct scb_data *scb_data; 893 int i; 894 895 scb_data = ahc->scb_data; 896 SLIST_INIT(&scb_data->free_scbs); 897 SLIST_INIT(&scb_data->sg_maps); 898 899 /* Allocate SCB resources */ 900 scb_data->scbarray = 901 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 902 M_DEVBUF, M_NOWAIT); 903 if (scb_data->scbarray == NULL) 904 return (ENOMEM); 905 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 906 907 /* Determine the number of hardware SCBs and initialize them */ 908 909 scb_data->maxhscbs = ahc_probe_scbs(ahc); 910 /* SCB 0 heads the free list */ 911 ahc_outb(ahc, FREE_SCBH, 0); 912 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 913 ahc_outb(ahc, SCBPTR, i); 914 915 /* Clear the control byte. */ 916 ahc_outb(ahc, SCB_CONTROL, 0); 917 918 /* Set the next pointer */ 919 ahc_outb(ahc, SCB_NEXT, i+1); 920 921 /* Make the tag number invalid */ 922 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 923 } 924 925 /* Make sure that the last SCB terminates the free list */ 926 ahc_outb(ahc, SCBPTR, i-1); 927 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 928 929 /* Ensure we clear the 0 SCB's control byte. */ 930 ahc_outb(ahc, SCBPTR, 0); 931 ahc_outb(ahc, SCB_CONTROL, 0); 932 933 scb_data->maxhscbs = i; 934 935 if (ahc->scb_data->maxhscbs == 0) 936 panic("%s: No SCB space found", ahc_name(ahc)); 937 938 /* 939 * Create our DMA tags. These tags define the kinds of device 940 * accessable memory allocations and memory mappings we will 941 * need to perform during normal operation. 942 * 943 * Unless we need to further restrict the allocation, we rely 944 * on the restrictions of the parent dmat, hence the common 945 * use of MAXADDR and MAXSIZE. 946 */ 947 948 if (ahc_createdmamem(ahc->parent_dmat, 949 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 950 &scb_data->hscb_dmamap, 951 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 952 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 953 "hardware SCB structures") < 0) 954 goto error_exit; 955 956 scb_data->init_level++; 957 958 if (ahc_createdmamem(ahc->parent_dmat, 959 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 960 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 961 &scb_data->sense_busaddr, &scb_data->sense_seg, 962 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 963 goto error_exit; 964 965 scb_data->init_level++; 966 967 /* Perform initial CCB allocation */ 968 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 969 ahcallocscbs(ahc); 970 971 if (scb_data->numscbs == 0) { 972 printf("%s: ahc_init_scb_data - " 973 "Unable to allocate initial scbs\n", 974 ahc_name(ahc)); 975 goto error_exit; 976 } 977 978 scb_data->init_level++; 979 980 /* 981 * Note that we were successfull 982 */ 983 return 0; 984 985 error_exit: 986 987 return ENOMEM; 988 } 989 990 static void 991 ahcfiniscbdata(struct ahc_softc *ahc) 992 { 993 struct scb_data *scb_data; 994 995 scb_data = ahc->scb_data; 996 997 switch (scb_data->init_level) { 998 default: 999 case 3: 1000 { 1001 struct sg_map_node *sg_map; 1002 1003 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1004 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1005 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1006 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1007 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1008 free(sg_map, M_DEVBUF); 1009 } 1010 } 1011 /*FALLTHROUGH*/ 1012 case 2: 1013 ahc_freedmamem(ahc->parent_dmat, 1014 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1015 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1016 &scb_data->sense_seg, scb_data->sense_nseg); 1017 /*FALLTHROUGH*/ 1018 case 1: 1019 ahc_freedmamem(ahc->parent_dmat, 1020 AHC_SCB_MAX * sizeof(struct hardware_scb), 1021 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1022 &scb_data->hscb_seg, scb_data->hscb_nseg); 1023 /*FALLTHROUGH*/ 1024 } 1025 if (scb_data->scbarray != NULL) 1026 free(scb_data->scbarray, M_DEVBUF); 1027 } 1028 1029 int 1030 ahc_reset(struct ahc_softc *ahc) 1031 { 1032 u_int sblkctl; 1033 int wait; 1034 1035 #ifdef AHC_DUMP_SEQ 1036 if (ahc->init_level == 0) 1037 ahc_dumpseq(ahc); 1038 #endif 1039 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1040 /* 1041 * Ensure that the reset has finished 1042 */ 1043 wait = 1000; 1044 do { 1045 DELAY(1000); 1046 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1047 1048 if (wait == 0) { 1049 printf("%s: WARNING - Failed chip reset! " 1050 "Trying to initialize anyway.\n", ahc_name(ahc)); 1051 } 1052 ahc_outb(ahc, HCNTRL, ahc->pause); 1053 1054 /* Determine channel configuration */ 1055 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1056 /* No Twin Channel PCI cards */ 1057 if ((ahc->chip & AHC_PCI) != 0) 1058 sblkctl &= ~SELBUSB; 1059 switch (sblkctl) { 1060 case 0: 1061 /* Single Narrow Channel */ 1062 break; 1063 case 2: 1064 /* Wide Channel */ 1065 ahc->features |= AHC_WIDE; 1066 break; 1067 case 8: 1068 /* Twin Channel */ 1069 ahc->features |= AHC_TWIN; 1070 break; 1071 default: 1072 printf(" Unsupported adapter type. Ignoring\n"); 1073 return(-1); 1074 } 1075 1076 return (0); 1077 } 1078 1079 /* 1080 * Called when we have an active connection to a target on the bus, 1081 * this function finds the nearest syncrate to the input period limited 1082 * by the capabilities of the bus connectivity of the target. 1083 */ 1084 static struct ahc_syncrate * 1085 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1086 u_int maxsync; 1087 1088 if ((ahc->features & AHC_ULTRA2) != 0) { 1089 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1090 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1091 maxsync = AHC_SYNCRATE_ULTRA2; 1092 } else { 1093 maxsync = AHC_SYNCRATE_ULTRA; 1094 } 1095 } else if ((ahc->features & AHC_ULTRA) != 0) { 1096 maxsync = AHC_SYNCRATE_ULTRA; 1097 } else { 1098 maxsync = AHC_SYNCRATE_FAST; 1099 } 1100 return (ahc_find_syncrate(ahc, period, maxsync)); 1101 } 1102 1103 /* 1104 * Look up the valid period to SCSIRATE conversion in our table. 1105 * Return the period and offset that should be sent to the target 1106 * if this was the beginning of an SDTR. 1107 */ 1108 static struct ahc_syncrate * 1109 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1110 { 1111 struct ahc_syncrate *syncrate; 1112 1113 syncrate = &ahc_syncrates[maxsync]; 1114 while ((syncrate->rate != NULL) 1115 && ((ahc->features & AHC_ULTRA2) == 0 1116 || (syncrate->sxfr_u2 != 0))) { 1117 1118 if (*period <= syncrate->period) { 1119 /* 1120 * When responding to a target that requests 1121 * sync, the requested rate may fall between 1122 * two rates that we can output, but still be 1123 * a rate that we can receive. Because of this, 1124 * we want to respond to the target with 1125 * the same rate that it sent to us even 1126 * if the period we use to send data to it 1127 * is lower. Only lower the response period 1128 * if we must. 1129 */ 1130 if (syncrate == &ahc_syncrates[maxsync]) 1131 *period = syncrate->period; 1132 break; 1133 } 1134 syncrate++; 1135 } 1136 1137 if ((*period == 0) 1138 || (syncrate->rate == NULL) 1139 || ((ahc->features & AHC_ULTRA2) != 0 1140 && (syncrate->sxfr_u2 == 0))) { 1141 /* Use asynchronous transfers. */ 1142 *period = 0; 1143 syncrate = NULL; 1144 } 1145 return (syncrate); 1146 } 1147 1148 static u_int 1149 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1150 { 1151 struct ahc_syncrate *syncrate; 1152 1153 if ((ahc->features & AHC_ULTRA2) != 0) 1154 scsirate &= SXFR_ULTRA2; 1155 else 1156 scsirate &= SXFR; 1157 1158 syncrate = &ahc_syncrates[maxsync]; 1159 while (syncrate->rate != NULL) { 1160 1161 if ((ahc->features & AHC_ULTRA2) != 0) { 1162 if (syncrate->sxfr_u2 == 0) 1163 break; 1164 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1165 return (syncrate->period); 1166 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1167 return (syncrate->period); 1168 } 1169 syncrate++; 1170 } 1171 return (0); /* async */ 1172 } 1173 1174 static void 1175 ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 1176 u_int *offset, int wide) 1177 { 1178 u_int maxoffset; 1179 1180 /* Limit offset to what we can do */ 1181 if (syncrate == NULL) { 1182 maxoffset = 0; 1183 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1184 maxoffset = MAX_OFFSET_ULTRA2; 1185 } else { 1186 if (wide) 1187 maxoffset = MAX_OFFSET_16BIT; 1188 else 1189 maxoffset = MAX_OFFSET_8BIT; 1190 } 1191 *offset = MIN(*offset, maxoffset); 1192 } 1193 1194 static void 1195 ahc_update_target_msg_request(struct ahc_softc *ahc, 1196 struct ahc_devinfo *devinfo, 1197 struct ahc_initiator_tinfo *tinfo, 1198 int force, int paused) 1199 { 1200 u_int targ_msg_req_orig; 1201 1202 targ_msg_req_orig = ahc->targ_msg_req; 1203 if (tinfo->current.period != tinfo->goal.period 1204 || tinfo->current.width != tinfo->goal.width 1205 || tinfo->current.offset != tinfo->goal.offset 1206 || (force 1207 && (tinfo->goal.period != 0 1208 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1209 ahc->targ_msg_req |= devinfo->target_mask; 1210 } else { 1211 ahc->targ_msg_req &= ~devinfo->target_mask; 1212 } 1213 1214 if (ahc->targ_msg_req != targ_msg_req_orig) { 1215 /* Update the message request bit for this target */ 1216 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1217 if (paused) { 1218 ahc_outb(ahc, TARGET_MSG_REQUEST, 1219 ahc->targ_msg_req & 0xFF); 1220 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1221 (ahc->targ_msg_req >> 8) & 0xFF); 1222 } else { 1223 ahc_outb(ahc, HS_MAILBOX, 1224 0x01 << HOST_MAILBOX_SHIFT); 1225 } 1226 } else { 1227 if (!paused) 1228 pause_sequencer(ahc); 1229 1230 ahc_outb(ahc, TARGET_MSG_REQUEST, 1231 ahc->targ_msg_req & 0xFF); 1232 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1233 (ahc->targ_msg_req >> 8) & 0xFF); 1234 1235 if (!paused) 1236 unpause_sequencer(ahc); 1237 } 1238 } 1239 } 1240 1241 static void 1242 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1243 struct ahc_syncrate *syncrate, 1244 u_int period, u_int offset, u_int type, int paused, int done) 1245 { 1246 struct ahc_initiator_tinfo *tinfo; 1247 struct tmode_tstate *tstate; 1248 u_int old_period; 1249 u_int old_offset; 1250 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1251 1252 if (syncrate == NULL) { 1253 period = 0; 1254 offset = 0; 1255 } 1256 1257 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1258 devinfo->target, &tstate); 1259 old_period = tinfo->current.period; 1260 old_offset = tinfo->current.offset; 1261 1262 if ((type & AHC_TRANS_CUR) != 0 1263 && (old_period != period || old_offset != offset)) { 1264 u_int scsirate; 1265 1266 scsirate = tinfo->scsirate; 1267 if ((ahc->features & AHC_ULTRA2) != 0) { 1268 1269 /* XXX */ 1270 /* Force single edge until DT is fully implemented */ 1271 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1272 if (syncrate != NULL) 1273 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1274 1275 if (active) 1276 ahc_outb(ahc, SCSIOFFSET, offset); 1277 } else { 1278 1279 scsirate &= ~(SXFR|SOFS); 1280 /* 1281 * Ensure Ultra mode is set properly for 1282 * this target. 1283 */ 1284 tstate->ultraenb &= ~devinfo->target_mask; 1285 if (syncrate != NULL) { 1286 if (syncrate->sxfr & ULTRA_SXFR) { 1287 tstate->ultraenb |= 1288 devinfo->target_mask; 1289 } 1290 scsirate |= syncrate->sxfr & SXFR; 1291 scsirate |= offset & SOFS; 1292 } 1293 if (active) { 1294 u_int sxfrctl0; 1295 1296 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1297 sxfrctl0 &= ~FAST20; 1298 if (tstate->ultraenb & devinfo->target_mask) 1299 sxfrctl0 |= FAST20; 1300 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1301 } 1302 } 1303 if (active) 1304 ahc_outb(ahc, SCSIRATE, scsirate); 1305 1306 tinfo->scsirate = scsirate; 1307 tinfo->current.period = period; 1308 tinfo->current.offset = offset; 1309 1310 /* Update the syncrates in any pending scbs */ 1311 ahc_update_pending_syncrates(ahc); 1312 } 1313 1314 /* 1315 * Print messages if we're verbose and at the end of a negotiation 1316 * cycle. 1317 */ 1318 if (done) { 1319 if (offset != 0) { 1320 printf("%s: target %d synchronous at %sMHz, " 1321 "offset = 0x%x\n", ahc_name(ahc), 1322 devinfo->target, syncrate->rate, offset); 1323 } else { 1324 printf("%s: target %d using " 1325 "asynchronous transfers\n", 1326 ahc_name(ahc), devinfo->target); 1327 } 1328 } 1329 1330 if ((type & AHC_TRANS_GOAL) != 0) { 1331 tinfo->goal.period = period; 1332 tinfo->goal.offset = offset; 1333 } 1334 1335 if ((type & AHC_TRANS_USER) != 0) { 1336 tinfo->user.period = period; 1337 tinfo->user.offset = offset; 1338 } 1339 1340 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1341 /*force*/FALSE, 1342 paused); 1343 } 1344 1345 static void 1346 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1347 u_int width, u_int type, int paused, int done) 1348 { 1349 struct ahc_initiator_tinfo *tinfo; 1350 struct tmode_tstate *tstate; 1351 u_int oldwidth; 1352 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1353 1354 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1355 devinfo->target, &tstate); 1356 oldwidth = tinfo->current.width; 1357 1358 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1359 u_int scsirate; 1360 1361 scsirate = tinfo->scsirate; 1362 scsirate &= ~WIDEXFER; 1363 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1364 scsirate |= WIDEXFER; 1365 1366 tinfo->scsirate = scsirate; 1367 1368 if (active) 1369 ahc_outb(ahc, SCSIRATE, scsirate); 1370 1371 tinfo->current.width = width; 1372 } 1373 1374 if (done) { 1375 printf("%s: target %d using %dbit transfers\n", 1376 ahc_name(ahc), devinfo->target, 1377 8 * (0x01 << width)); 1378 } 1379 1380 if ((type & AHC_TRANS_GOAL) != 0) 1381 tinfo->goal.width = width; 1382 if ((type & AHC_TRANS_USER) != 0) 1383 tinfo->user.width = width; 1384 1385 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1386 /*force*/FALSE, paused); 1387 } 1388 1389 static void 1390 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1391 { 1392 struct ahc_initiator_tinfo *tinfo; 1393 struct tmode_tstate *tstate; 1394 1395 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1396 devinfo->target, &tstate); 1397 1398 if (enable) 1399 tstate->tagenable |= devinfo->target_mask; 1400 else { 1401 tstate->tagenable &= ~devinfo->target_mask; 1402 tstate->tagdisable |= devinfo->target_mask; 1403 } 1404 } 1405 1406 /* 1407 * Attach all the sub-devices we can find 1408 */ 1409 int 1410 ahc_attach(struct ahc_softc *ahc) 1411 { 1412 TAILQ_INIT(&ahc->sc_q); 1413 1414 ahc->sc_adapter.scsipi_cmd = ahc_action; 1415 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1416 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1417 ahc->sc_link.type = BUS_SCSI; 1418 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1419 ahc->sc_link.scsipi_scsi.channel = 0; 1420 ahc->sc_link.scsipi_scsi.max_target = 1421 (ahc->features & AHC_WIDE) ? 15 : 7; 1422 ahc->sc_link.scsipi_scsi.max_lun = 7; 1423 ahc->sc_link.adapter_softc = ahc; 1424 ahc->sc_link.adapter = &ahc->sc_adapter; 1425 ahc->sc_link.openings = 2; 1426 ahc->sc_link.device = &ahc_dev; 1427 1428 if (ahc->features & AHC_TWIN) { 1429 ahc->sc_link_b = ahc->sc_link; 1430 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1431 ahc->sc_link_b.scsipi_scsi.channel = 1; 1432 } 1433 1434 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1435 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1436 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1437 if (ahc->features & AHC_TWIN) 1438 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1439 } else { 1440 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1441 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1442 } 1443 return 1; 1444 } 1445 1446 static void 1447 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1448 { 1449 u_int saved_tcl; 1450 role_t role; 1451 int our_id; 1452 1453 if (ahc_inb(ahc, SSTAT0) & TARGET) 1454 role = ROLE_TARGET; 1455 else 1456 role = ROLE_INITIATOR; 1457 1458 if (role == ROLE_TARGET 1459 && (ahc->features & AHC_MULTI_TID) != 0 1460 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1461 /* We were selected, so pull our id from TARGIDIN */ 1462 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1463 } else if ((ahc->features & AHC_ULTRA2) != 0) 1464 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1465 else 1466 our_id = ahc_inb(ahc, SCSIID) & OID; 1467 1468 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1469 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1470 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1471 role); 1472 } 1473 1474 static void 1475 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1476 u_int lun, char channel, role_t role) 1477 { 1478 devinfo->our_scsiid = our_id; 1479 devinfo->target = target; 1480 devinfo->lun = lun; 1481 devinfo->target_offset = target; 1482 devinfo->channel = channel; 1483 devinfo->role = role; 1484 if (channel == 'B') 1485 devinfo->target_offset += 8; 1486 devinfo->target_mask = (0x01 << devinfo->target_offset); 1487 } 1488 1489 /* 1490 * Catch an interrupt from the adapter 1491 */ 1492 int 1493 ahc_intr(void *arg) 1494 { 1495 struct ahc_softc *ahc; 1496 u_int intstat; 1497 1498 ahc = (struct ahc_softc *)arg; 1499 1500 intstat = ahc_inb(ahc, INTSTAT); 1501 1502 /* 1503 * Any interrupts to process? 1504 */ 1505 if ((intstat & INT_PEND) == 0) { 1506 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1507 #ifdef AHC_DEBUG 1508 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1509 ahc_name(ahc), 1510 ahc_inb(ahc, CCHADDR) | 1511 (ahc_inb(ahc, CCHADDR+1) << 8) 1512 | (ahc_inb(ahc, CCHADDR+2) << 16) 1513 | (ahc_inb(ahc, CCHADDR+3) << 24), 1514 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1515 | (ahc_inb(ahc, HADDR+2) << 16) 1516 | (ahc_inb(ahc, HADDR+3) << 24), 1517 ahc_inb(ahc, SEQADDR0) | 1518 (ahc_inb(ahc, SEQADDR1) << 8)); 1519 #endif 1520 return 1; 1521 } 1522 return 0; 1523 } 1524 1525 #ifdef AHC_DEBUG 1526 if (ahc_debug & AHC_SHOWINTR) { 1527 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1528 } 1529 #endif 1530 1531 if (intstat & CMDCMPLT) { 1532 ahc_outb(ahc, CLRINT, CLRCMDINT); 1533 ahc_run_qoutfifo(ahc); 1534 } 1535 if (intstat & BRKADRINT) { 1536 /* 1537 * We upset the sequencer :-( 1538 * Lookup the error message 1539 */ 1540 int i, error, num_errors; 1541 1542 error = ahc_inb(ahc, ERROR); 1543 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1544 for (i = 0; error != 1 && i < num_errors; i++) 1545 error >>= 1; 1546 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1547 ahc_name(ahc), hard_error[i].errmesg, 1548 ahc_inb(ahc, SEQADDR0) | 1549 (ahc_inb(ahc, SEQADDR1) << 8)); 1550 1551 /* Tell everyone that this HBA is no longer availible */ 1552 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1553 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1554 XS_DRIVER_STUFFUP); 1555 } 1556 if (intstat & SEQINT) 1557 ahc_handle_seqint(ahc, intstat); 1558 1559 if (intstat & SCSIINT) 1560 ahc_handle_scsiint(ahc, intstat); 1561 1562 return 1; 1563 } 1564 1565 static struct tmode_tstate * 1566 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1567 { 1568 struct tmode_tstate *master_tstate; 1569 struct tmode_tstate *tstate; 1570 int i, s; 1571 1572 master_tstate = ahc->enabled_targets[ahc->our_id]; 1573 if (channel == 'B') { 1574 scsi_id += 8; 1575 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1576 } 1577 if (ahc->enabled_targets[scsi_id] != NULL 1578 && ahc->enabled_targets[scsi_id] != master_tstate) 1579 panic("%s: ahc_alloc_tstate - Target already allocated", 1580 ahc_name(ahc)); 1581 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1582 if (tstate == NULL) 1583 return (NULL); 1584 1585 /* 1586 * If we have allocated a master tstate, copy user settings from 1587 * the master tstate (taken from SRAM or the EEPROM) for this 1588 * channel, but reset our current and goal settings to async/narrow 1589 * until an initiator talks to us. 1590 */ 1591 if (master_tstate != NULL) { 1592 bcopy(master_tstate, tstate, sizeof(*tstate)); 1593 tstate->ultraenb = 0; 1594 for (i = 0; i < 16; i++) { 1595 bzero(&tstate->transinfo[i].current, 1596 sizeof(tstate->transinfo[i].current)); 1597 bzero(&tstate->transinfo[i].goal, 1598 sizeof(tstate->transinfo[i].goal)); 1599 } 1600 } else 1601 bzero(tstate, sizeof(*tstate)); 1602 s = splbio(); 1603 ahc->enabled_targets[scsi_id] = tstate; 1604 splx(s); 1605 return (tstate); 1606 } 1607 1608 #if UNUSED 1609 static void 1610 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1611 { 1612 struct tmode_tstate *tstate; 1613 1614 /* Don't clean up the entry for our initiator role */ 1615 if ((ahc->flags & AHC_INITIATORMODE) != 0 1616 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1617 || (channel == 'A' && scsi_id == ahc->our_id)) 1618 && force == FALSE) 1619 return; 1620 1621 if (channel == 'B') 1622 scsi_id += 8; 1623 tstate = ahc->enabled_targets[scsi_id]; 1624 if (tstate != NULL) 1625 free(tstate, M_DEVBUF); 1626 ahc->enabled_targets[scsi_id] = NULL; 1627 } 1628 #endif 1629 1630 static void 1631 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1632 { 1633 struct scb *scb; 1634 struct ahc_devinfo devinfo; 1635 1636 ahc_fetch_devinfo(ahc, &devinfo); 1637 1638 /* 1639 * Clear the upper byte that holds SEQINT status 1640 * codes and clear the SEQINT bit. We will unpause 1641 * the sequencer, if appropriate, after servicing 1642 * the request. 1643 */ 1644 ahc_outb(ahc, CLRINT, CLRSEQINT); 1645 switch (intstat & SEQINT_MASK) { 1646 case NO_MATCH: 1647 { 1648 /* Ensure we don't leave the selection hardware on */ 1649 ahc_outb(ahc, SCSISEQ, 1650 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1651 1652 printf("%s:%c:%d: no active SCB for reconnecting " 1653 "target - issuing BUS DEVICE RESET\n", 1654 ahc_name(ahc), devinfo.channel, devinfo.target); 1655 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1656 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1657 ahc_inb(ahc, SEQ_FLAGS)); 1658 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1659 ahc->msgout_len = 1; 1660 ahc->msgout_index = 0; 1661 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1662 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1663 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1664 break; 1665 } 1666 case UPDATE_TMSG_REQ: 1667 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1668 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1669 (ahc->targ_msg_req >> 8) & 0xFF); 1670 ahc_outb(ahc, HS_MAILBOX, 0); 1671 break; 1672 case SEND_REJECT: 1673 { 1674 u_int rejbyte = ahc_inb(ahc, ACCUM); 1675 printf("%s:%c:%d: Warning - unknown message received from " 1676 "target (0x%x). Rejecting\n", 1677 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1678 break; 1679 } 1680 case NO_IDENT: 1681 { 1682 /* 1683 * The reconnecting target either did not send an identify 1684 * message, or did, but we didn't find and SCB to match and 1685 * before it could respond to our ATN/abort, it hit a dataphase. 1686 * The only safe thing to do is to blow it away with a bus 1687 * reset. 1688 */ 1689 int found; 1690 1691 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1692 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1693 ahc_name(ahc), devinfo.channel, devinfo.target, 1694 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1695 found = ahc_reset_channel(ahc, devinfo.channel, 1696 /*initiate reset*/TRUE); 1697 printf("%s: Issued Channel %c Bus Reset. " 1698 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1699 found); 1700 return; 1701 } 1702 case BAD_PHASE: 1703 { 1704 u_int lastphase; 1705 1706 lastphase = ahc_inb(ahc, LASTPHASE); 1707 if (lastphase == P_BUSFREE) { 1708 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1709 ahc_name(ahc), devinfo.channel, devinfo.target, 1710 ahc_inb(ahc, SCSISIGI)); 1711 restart_sequencer(ahc); 1712 return; 1713 } else { 1714 printf("%s:%c:%d: unknown scsi bus phase %x. " 1715 "Attempting to continue\n", 1716 ahc_name(ahc), devinfo.channel, devinfo.target, 1717 ahc_inb(ahc, SCSISIGI)); 1718 } 1719 break; 1720 } 1721 case BAD_STATUS: 1722 { 1723 u_int scb_index; 1724 struct hardware_scb *hscb; 1725 struct scsipi_xfer *xs; 1726 /* 1727 * The sequencer will notify us when a command 1728 * has an error that would be of interest to 1729 * the kernel. This allows us to leave the sequencer 1730 * running in the common case of command completes 1731 * without error. The sequencer will already have 1732 * dma'd the SCB back up to us, so we can reference 1733 * the in kernel copy directly. 1734 */ 1735 scb_index = ahc_inb(ahc, SCB_TAG); 1736 scb = &ahc->scb_data->scbarray[scb_index]; 1737 1738 /* ahc_print_scb(scb); */ 1739 1740 /* 1741 * Set the default return value to 0 (don't 1742 * send sense). The sense code will change 1743 * this if needed. 1744 */ 1745 ahc_outb(ahc, RETURN_1, 0); 1746 if (!(scb_index < ahc->scb_data->numscbs 1747 && (scb->flags & SCB_ACTIVE) != 0)) { 1748 printf("%s:%c:%d: ahc_intr - referenced scb " 1749 "not valid during seqint 0x%x scb(%d)\n", 1750 ahc_name(ahc), devinfo.channel, 1751 devinfo.target, intstat, scb_index); 1752 goto unpause; 1753 } 1754 1755 hscb = scb->hscb; 1756 xs = scb->xs; 1757 1758 /* Don't want to clobber the original sense code */ 1759 if ((scb->flags & SCB_SENSE) != 0) { 1760 /* 1761 * Clear the SCB_SENSE Flag and have 1762 * the sequencer do a normal command 1763 * complete. 1764 */ 1765 scb->flags &= ~SCB_SENSE; 1766 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1767 break; 1768 } 1769 /* Freeze the queue unit the client sees the error. */ 1770 ahc_freeze_devq(ahc, xs->sc_link); 1771 ahc_freeze_ccb(scb); 1772 xs->status = hscb->status; 1773 switch (hscb->status) { 1774 case SCSI_STATUS_OK: 1775 printf("%s: Interrupted for status of 0???\n", 1776 ahc_name(ahc)); 1777 break; 1778 case SCSI_STATUS_CMD_TERMINATED: 1779 case SCSI_STATUS_CHECK_COND: 1780 #if defined(AHC_DEBUG) 1781 if (ahc_debug & AHC_SHOWSENSE) { 1782 scsi_print_addr(xs->sc_link); 1783 printf("Check Status, resid %d datalen %d\n", 1784 xs->resid, xs->datalen); 1785 } 1786 #endif 1787 1788 if (xs->error == XS_NOERROR && 1789 !(scb->flags & SCB_SENSE)) { 1790 struct ahc_dma_seg *sg; 1791 struct scsipi_sense *sc; 1792 struct ahc_initiator_tinfo *tinfo; 1793 struct tmode_tstate *tstate; 1794 1795 sg = scb->sg_list; 1796 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1797 /* 1798 * Save off the residual if there is one. 1799 */ 1800 if (hscb->residual_SG_count != 0) 1801 ahc_calc_residual(scb); 1802 else 1803 xs->resid = 0; 1804 1805 #ifdef AHC_DEBUG 1806 if (ahc_debug & AHC_SHOWSENSE) { 1807 scsi_print_addr(xs->sc_link); 1808 printf("Sending Sense\n"); 1809 } 1810 #endif 1811 sg->addr = ahc->scb_data->sense_busaddr + 1812 (hscb->tag*sizeof(struct scsipi_sense_data)); 1813 sg->len = sizeof (struct scsipi_sense_data); 1814 1815 sc->opcode = REQUEST_SENSE; 1816 sc->byte2 = SCB_LUN(scb) << 5; 1817 sc->unused[0] = 0; 1818 sc->unused[1] = 0; 1819 sc->length = sg->len; 1820 sc->control = 0; 1821 1822 /* 1823 * Would be nice to preserve DISCENB here, 1824 * but due to the way we page SCBs, we can't. 1825 */ 1826 hscb->control = 0; 1827 1828 /* 1829 * This request sense could be because the 1830 * the device lost power or in some other 1831 * way has lost our transfer negotiations. 1832 * Renegotiate if appropriate. Unit attention 1833 * errors will be reported before any data 1834 * phases occur. 1835 */ 1836 ahc_calc_residual(scb); 1837 #if defined(AHC_DEBUG) 1838 if (ahc_debug & AHC_SHOWSENSE) { 1839 scsi_print_addr(xs->sc_link); 1840 printf("Sense: datalen %d resid %d" 1841 "chan %d id %d targ %d\n", 1842 xs->datalen, xs->resid, 1843 devinfo.channel, devinfo.our_scsiid, 1844 devinfo.target); 1845 } 1846 #endif 1847 if (xs->datalen > 0 && 1848 xs->resid == xs->datalen) { 1849 tinfo = ahc_fetch_transinfo(ahc, 1850 devinfo.channel, 1851 devinfo.our_scsiid, 1852 devinfo.target, 1853 &tstate); 1854 ahc_update_target_msg_request(ahc, 1855 &devinfo, 1856 tinfo, 1857 /*force*/TRUE, 1858 /*paused*/TRUE); 1859 } 1860 hscb->status = 0; 1861 hscb->SG_count = 1; 1862 hscb->SG_pointer = scb->sg_list_phys; 1863 hscb->data = sg->addr; 1864 hscb->datalen = sg->len; 1865 hscb->cmdpointer = hscb->cmdstore_busaddr; 1866 hscb->cmdlen = sizeof(*sc); 1867 scb->sg_count = hscb->SG_count; 1868 ahc_swap_hscb(hscb); 1869 ahc_swap_sg(scb->sg_list); 1870 scb->flags |= SCB_SENSE; 1871 /* 1872 * Ensure the target is busy since this 1873 * will be an untagged request. 1874 */ 1875 ahc_busy_tcl(ahc, scb); 1876 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1877 1878 /* 1879 * Ensure we have enough time to actually 1880 * retrieve the sense. 1881 */ 1882 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1883 callout_reset(&scb->xs->xs_callout, 1884 5 * hz, ahc_timeout, scb); 1885 } 1886 } 1887 break; 1888 case SCSI_STATUS_QUEUE_FULL: 1889 scsi_print_addr(xs->sc_link); 1890 printf("queue full\n"); 1891 case SCSI_STATUS_BUSY: 1892 /* 1893 * XXX middle layer doesn't handle XS_BUSY well. 1894 * So, requeue this ourselves internally. 1895 */ 1896 xs->error = XS_BUSY; 1897 scb->flags |= SCB_REQUEUE; 1898 break; 1899 } 1900 break; 1901 } 1902 case TRACE_POINT: 1903 { 1904 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1905 ahc_inb(ahc, DFCNTRL)); 1906 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1907 ahc_inb(ahc, DFSTATUS)); 1908 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1909 ahc_inb(ahc, SSTAT0), 1910 ahc_inb(ahc, SCB_DATACNT)); 1911 break; 1912 } 1913 case HOST_MSG_LOOP: 1914 { 1915 /* 1916 * The sequencer has encountered a message phase 1917 * that requires host assistance for completion. 1918 * While handling the message phase(s), we will be 1919 * notified by the sequencer after each byte is 1920 * transfered so we can track bus phases. 1921 * 1922 * If this is the first time we've seen a HOST_MSG_LOOP, 1923 * initialize the state of the host message loop. 1924 */ 1925 if (ahc->msg_type == MSG_TYPE_NONE) { 1926 u_int bus_phase; 1927 1928 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1929 if (bus_phase != P_MESGIN 1930 && bus_phase != P_MESGOUT) { 1931 printf("ahc_intr: HOST_MSG_LOOP bad " 1932 "phase 0x%x\n", 1933 bus_phase); 1934 /* 1935 * Probably transitioned to bus free before 1936 * we got here. Just punt the message. 1937 */ 1938 ahc_clear_intstat(ahc); 1939 restart_sequencer(ahc); 1940 } 1941 1942 if (devinfo.role == ROLE_INITIATOR) { 1943 struct scb *scb; 1944 u_int scb_index; 1945 1946 scb_index = ahc_inb(ahc, SCB_TAG); 1947 scb = &ahc->scb_data->scbarray[scb_index]; 1948 1949 if (bus_phase == P_MESGOUT) 1950 ahc_setup_initiator_msgout(ahc, 1951 &devinfo, 1952 scb); 1953 else { 1954 ahc->msg_type = 1955 MSG_TYPE_INITIATOR_MSGIN; 1956 ahc->msgin_index = 0; 1957 } 1958 } else { 1959 if (bus_phase == P_MESGOUT) { 1960 ahc->msg_type = 1961 MSG_TYPE_TARGET_MSGOUT; 1962 ahc->msgin_index = 0; 1963 } else 1964 /* XXX Ever executed??? */ 1965 ahc_setup_target_msgin(ahc, &devinfo); 1966 } 1967 } 1968 1969 /* Pass a NULL path so that handlers generate their own */ 1970 ahc_handle_message_phase(ahc, /*path*/NULL); 1971 break; 1972 } 1973 case PERR_DETECTED: 1974 { 1975 /* 1976 * If we've cleared the parity error interrupt 1977 * but the sequencer still believes that SCSIPERR 1978 * is true, it must be that the parity error is 1979 * for the currently presented byte on the bus, 1980 * and we are not in a phase (data-in) where we will 1981 * eventually ack this byte. Ack the byte and 1982 * throw it away in the hope that the target will 1983 * take us to message out to deliver the appropriate 1984 * error message. 1985 */ 1986 if ((intstat & SCSIINT) == 0 1987 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1988 u_int curphase; 1989 1990 /* 1991 * The hardware will only let you ack bytes 1992 * if the expected phase in SCSISIGO matches 1993 * the current phase. Make sure this is 1994 * currently the case. 1995 */ 1996 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1997 ahc_outb(ahc, LASTPHASE, curphase); 1998 ahc_outb(ahc, SCSISIGO, curphase); 1999 ahc_inb(ahc, SCSIDATL); 2000 } 2001 break; 2002 } 2003 case DATA_OVERRUN: 2004 { 2005 /* 2006 * When the sequencer detects an overrun, it 2007 * places the controller in "BITBUCKET" mode 2008 * and allows the target to complete its transfer. 2009 * Unfortunately, none of the counters get updated 2010 * when the controller is in this mode, so we have 2011 * no way of knowing how large the overrun was. 2012 */ 2013 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2014 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2015 int i; 2016 2017 scb = &ahc->scb_data->scbarray[scbindex]; 2018 for (i = 0; i < num_phases; i++) { 2019 if (lastphase == phase_table[i].phase) 2020 break; 2021 } 2022 scsi_print_addr(scb->xs->sc_link); 2023 printf("data overrun detected %s." 2024 " Tag == 0x%x.\n", 2025 phase_table[i].phasemsg, 2026 scb->hscb->tag); 2027 scsi_print_addr(scb->xs->sc_link); 2028 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2029 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2030 scb->xs->datalen, scb->sg_count); 2031 if (scb->sg_count > 0) { 2032 for (i = 0; i < scb->sg_count; i++) { 2033 printf("sg[%d] - Addr 0x%x : Length %d\n", 2034 i, 2035 le32toh(scb->sg_list[i].addr), 2036 le32toh(scb->sg_list[i].len)); 2037 } 2038 } 2039 /* 2040 * Set this and it will take affect when the 2041 * target does a command complete. 2042 */ 2043 ahc_freeze_devq(ahc, scb->xs->sc_link); 2044 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2045 ahc_freeze_ccb(scb); 2046 break; 2047 } 2048 case TRACEPOINT: 2049 { 2050 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2051 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2052 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2053 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2054 printf("TRACEPOINT: CCHADDR = %x\n", 2055 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2056 | (ahc_inb(ahc, CCHADDR+2) << 16) 2057 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2058 #if 0 2059 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2060 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2061 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2062 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2063 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2064 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2065 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2066 ahc_inb(ahc, CCHADDR) 2067 | (ahc_inb(ahc, CCHADDR+1) << 8) 2068 | (ahc_inb(ahc, CCHADDR+2) << 16) 2069 | (ahc_inb(ahc, CCHADDR+3) << 24), 2070 ahc_inb(ahc, CCHCNT) 2071 | (ahc_inb(ahc, CCHCNT+1) << 8) 2072 | (ahc_inb(ahc, CCHCNT+2) << 16), 2073 ahc_inb(ahc, SCBPTR)); 2074 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2075 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2076 #if DDB > 0 2077 cpu_Debugger(); 2078 #endif 2079 #endif 2080 break; 2081 } 2082 #if NOT_YET 2083 /* XXX Fill these in later */ 2084 case MESG_BUFFER_BUSY: 2085 break; 2086 case MSGIN_PHASEMIS: 2087 break; 2088 #endif 2089 default: 2090 printf("ahc_intr: seqint, " 2091 "intstat == 0x%x, scsisigi = 0x%x\n", 2092 intstat, ahc_inb(ahc, SCSISIGI)); 2093 break; 2094 } 2095 2096 unpause: 2097 /* 2098 * The sequencer is paused immediately on 2099 * a SEQINT, so we should restart it when 2100 * we're done. 2101 */ 2102 unpause_sequencer(ahc); 2103 } 2104 2105 static void 2106 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2107 { 2108 u_int scb_index; 2109 u_int status; 2110 struct scb *scb; 2111 char cur_channel; 2112 char intr_channel; 2113 2114 if ((ahc->features & AHC_TWIN) != 0 2115 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2116 cur_channel = 'B'; 2117 else 2118 cur_channel = 'A'; 2119 intr_channel = cur_channel; 2120 2121 status = ahc_inb(ahc, SSTAT1); 2122 if (status == 0) { 2123 if ((ahc->features & AHC_TWIN) != 0) { 2124 /* Try the other channel */ 2125 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2126 status = ahc_inb(ahc, SSTAT1); 2127 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2128 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2129 } 2130 if (status == 0) { 2131 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2132 return; 2133 } 2134 } 2135 2136 scb_index = ahc_inb(ahc, SCB_TAG); 2137 if (scb_index < ahc->scb_data->numscbs) { 2138 scb = &ahc->scb_data->scbarray[scb_index]; 2139 if ((scb->flags & SCB_ACTIVE) == 0 2140 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2141 scb = NULL; 2142 } else 2143 scb = NULL; 2144 2145 if ((status & SCSIRSTI) != 0) { 2146 printf("%s: Someone reset channel %c\n", 2147 ahc_name(ahc), intr_channel); 2148 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2149 } else if ((status & SCSIPERR) != 0) { 2150 /* 2151 * Determine the bus phase and queue an appropriate message. 2152 * SCSIPERR is latched true as soon as a parity error 2153 * occurs. If the sequencer acked the transfer that 2154 * caused the parity error and the currently presented 2155 * transfer on the bus has correct parity, SCSIPERR will 2156 * be cleared by CLRSCSIPERR. Use this to determine if 2157 * we should look at the last phase the sequencer recorded, 2158 * or the current phase presented on the bus. 2159 */ 2160 u_int mesg_out; 2161 u_int curphase; 2162 u_int errorphase; 2163 u_int lastphase; 2164 int i; 2165 2166 lastphase = ahc_inb(ahc, LASTPHASE); 2167 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2168 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2169 /* 2170 * For all phases save DATA, the sequencer won't 2171 * automatically ack a byte that has a parity error 2172 * in it. So the only way that the current phase 2173 * could be 'data-in' is if the parity error is for 2174 * an already acked byte in the data phase. During 2175 * synchronous data-in transfers, we may actually 2176 * ack bytes before latching the current phase in 2177 * LASTPHASE, leading to the discrepancy between 2178 * curphase and lastphase. 2179 */ 2180 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2181 || curphase == P_DATAIN) 2182 errorphase = curphase; 2183 else 2184 errorphase = lastphase; 2185 2186 for (i = 0; i < num_phases; i++) { 2187 if (errorphase == phase_table[i].phase) 2188 break; 2189 } 2190 mesg_out = phase_table[i].mesg_out; 2191 if (scb != NULL) 2192 scsi_print_addr(scb->xs->sc_link); 2193 else 2194 printf("%s:%c:%d: ", ahc_name(ahc), 2195 intr_channel, 2196 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2197 2198 printf("parity error detected %s. " 2199 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2200 phase_table[i].phasemsg, 2201 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2202 ahc_inb(ahc, SCSIRATE)); 2203 2204 /* 2205 * We've set the hardware to assert ATN if we 2206 * get a parity error on "in" phases, so all we 2207 * need to do is stuff the message buffer with 2208 * the appropriate message. "In" phases have set 2209 * mesg_out to something other than MSG_NOP. 2210 */ 2211 if (mesg_out != MSG_NOOP) { 2212 if (ahc->msg_type != MSG_TYPE_NONE) 2213 ahc->send_msg_perror = TRUE; 2214 else 2215 ahc_outb(ahc, MSG_OUT, mesg_out); 2216 } 2217 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2218 unpause_sequencer(ahc); 2219 } else if ((status & BUSFREE) != 0 2220 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2221 /* 2222 * First look at what phase we were last in. 2223 * If its message out, chances are pretty good 2224 * that the busfree was in response to one of 2225 * our abort requests. 2226 */ 2227 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2228 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2229 u_int target = TCL_TARGET(saved_tcl); 2230 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2231 char channel = TCL_CHANNEL(ahc, saved_tcl); 2232 int printerror = 1; 2233 2234 ahc_outb(ahc, SCSISEQ, 2235 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2236 if (lastphase == P_MESGOUT) { 2237 u_int message; 2238 u_int tag; 2239 2240 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2241 tag = SCB_LIST_NULL; 2242 switch (message) { 2243 case MSG_ABORT_TAG: 2244 tag = scb->hscb->tag; 2245 /* FALLTRHOUGH */ 2246 case MSG_ABORT: 2247 scsi_print_addr(scb->xs->sc_link); 2248 printf("SCB %x - Abort %s Completed.\n", 2249 scb->hscb->tag, tag == SCB_LIST_NULL ? 2250 "" : "Tag"); 2251 ahc_abort_scbs(ahc, target, channel, 2252 TCL_LUN(saved_tcl), tag, 2253 ROLE_INITIATOR, 2254 XS_DRIVER_STUFFUP); 2255 printerror = 0; 2256 break; 2257 case MSG_BUS_DEV_RESET: 2258 { 2259 struct ahc_devinfo devinfo; 2260 2261 if (scb != NULL && 2262 (scb->xs->xs_control & XS_CTL_RESET) 2263 && ahc_match_scb(scb, target, channel, 2264 TCL_LUN(saved_tcl), 2265 SCB_LIST_NULL, 2266 ROLE_INITIATOR)) { 2267 ahcsetccbstatus(scb->xs, XS_NOERROR); 2268 } 2269 ahc_compile_devinfo(&devinfo, 2270 initiator_role_id, 2271 target, 2272 TCL_LUN(saved_tcl), 2273 channel, 2274 ROLE_INITIATOR); 2275 ahc_handle_devreset(ahc, &devinfo, 2276 XS_RESET, 2277 "Bus Device Reset", 2278 /*verbose_level*/0); 2279 printerror = 0; 2280 break; 2281 } 2282 default: 2283 break; 2284 } 2285 } 2286 if (printerror != 0) { 2287 int i; 2288 2289 if (scb != NULL) { 2290 u_int tag; 2291 2292 if ((scb->hscb->control & TAG_ENB) != 0) 2293 tag = scb->hscb->tag; 2294 else 2295 tag = SCB_LIST_NULL; 2296 ahc_abort_scbs(ahc, target, channel, 2297 SCB_LUN(scb), tag, 2298 ROLE_INITIATOR, 2299 XS_DRIVER_STUFFUP); 2300 scsi_print_addr(scb->xs->sc_link); 2301 } else { 2302 /* 2303 * We had not fully identified this connection, 2304 * so we cannot abort anything. 2305 */ 2306 printf("%s: ", ahc_name(ahc)); 2307 } 2308 for (i = 0; i < num_phases; i++) { 2309 if (lastphase == phase_table[i].phase) 2310 break; 2311 } 2312 printf("Unexpected busfree %s\n" 2313 "SEQADDR == 0x%x\n", 2314 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2315 | (ahc_inb(ahc, SEQADDR1) << 8)); 2316 } 2317 ahc_clear_msg_state(ahc); 2318 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2319 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2320 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2321 restart_sequencer(ahc); 2322 } else if ((status & SELTO) != 0) { 2323 u_int scbptr; 2324 2325 scbptr = ahc_inb(ahc, WAITING_SCBH); 2326 ahc_outb(ahc, SCBPTR, scbptr); 2327 scb_index = ahc_inb(ahc, SCB_TAG); 2328 2329 if (scb_index < ahc->scb_data->numscbs) { 2330 scb = &ahc->scb_data->scbarray[scb_index]; 2331 if ((scb->flags & SCB_ACTIVE) == 0) 2332 scb = NULL; 2333 } else 2334 scb = NULL; 2335 2336 if (scb == NULL) { 2337 printf("%s: ahc_intr - referenced scb not " 2338 "valid during SELTO scb(%d, %d)\n", 2339 ahc_name(ahc), scbptr, scb_index); 2340 } else { 2341 u_int tag; 2342 2343 tag = SCB_LIST_NULL; 2344 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2345 tag = scb->hscb->tag; 2346 2347 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2348 SCB_LUN(scb), tag, 2349 ROLE_INITIATOR, XS_SELTIMEOUT); 2350 } 2351 /* Stop the selection */ 2352 ahc_outb(ahc, SCSISEQ, 0); 2353 2354 /* No more pending messages */ 2355 ahc_clear_msg_state(ahc); 2356 2357 /* 2358 * Although the driver does not care about the 2359 * 'Selection in Progress' status bit, the busy 2360 * LED does. SELINGO is only cleared by a sucessful 2361 * selection, so we must manually clear it to ensure 2362 * the LED turns off just incase no future successful 2363 * selections occur (e.g. no devices on the bus). 2364 */ 2365 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2366 2367 /* Clear interrupt state */ 2368 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2369 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2370 restart_sequencer(ahc); 2371 } else { 2372 scsi_print_addr(scb->xs->sc_link); 2373 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2374 ahc_outb(ahc, CLRSINT1, status); 2375 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2376 unpause_sequencer(ahc); 2377 } 2378 } 2379 2380 static void 2381 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2382 { 2383 /* 2384 * We need to initiate transfer negotiations. 2385 * If our current and goal settings are identical, 2386 * we want to renegotiate due to a check condition. 2387 */ 2388 struct ahc_initiator_tinfo *tinfo; 2389 struct tmode_tstate *tstate; 2390 int dowide; 2391 int dosync; 2392 2393 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2394 devinfo->target, &tstate); 2395 dowide = tinfo->current.width != tinfo->goal.width; 2396 dosync = tinfo->current.period != tinfo->goal.period; 2397 2398 if (!dowide && !dosync) { 2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2400 dosync = tinfo->goal.period != 0; 2401 } 2402 2403 if (dowide) { 2404 ahc_construct_wdtr(ahc, tinfo->goal.width); 2405 } else if (dosync) { 2406 struct ahc_syncrate *rate; 2407 u_int period; 2408 u_int offset; 2409 2410 period = tinfo->goal.period; 2411 rate = ahc_devlimited_syncrate(ahc, &period); 2412 offset = tinfo->goal.offset; 2413 ahc_validate_offset(ahc, rate, &offset, 2414 tinfo->current.width); 2415 ahc_construct_sdtr(ahc, period, offset); 2416 } else { 2417 panic("ahc_intr: AWAITING_MSG for negotiation, " 2418 "but no negotiation needed\n"); 2419 } 2420 } 2421 2422 static void 2423 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2424 struct scb *scb) 2425 { 2426 /* 2427 * To facilitate adding multiple messages together, 2428 * each routine should increment the index and len 2429 * variables instead of setting them explicitly. 2430 */ 2431 ahc->msgout_index = 0; 2432 ahc->msgout_len = 0; 2433 2434 if ((scb->flags & SCB_DEVICE_RESET) == 0 2435 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2436 u_int identify_msg; 2437 2438 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2439 if ((scb->hscb->control & DISCENB) != 0) 2440 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2441 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2442 ahc->msgout_len++; 2443 2444 if ((scb->hscb->control & TAG_ENB) != 0) { 2445 /* XXX fvdl FreeBSD has tag action passed down */ 2446 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2447 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2448 ahc->msgout_len += 2; 2449 } 2450 } 2451 2452 if (scb->flags & SCB_DEVICE_RESET) { 2453 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2454 ahc->msgout_len++; 2455 scsi_print_addr(scb->xs->sc_link); 2456 printf("Bus Device Reset Message Sent\n"); 2457 } else if (scb->flags & SCB_ABORT) { 2458 if ((scb->hscb->control & TAG_ENB) != 0) 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2460 else 2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2462 ahc->msgout_len++; 2463 scsi_print_addr(scb->xs->sc_link); 2464 printf("Abort Message Sent\n"); 2465 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2466 ahc_build_transfer_msg(ahc, devinfo); 2467 } else { 2468 printf("ahc_intr: AWAITING_MSG for an SCB that " 2469 "does not have a waiting message"); 2470 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2471 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2472 ahc_inb(ahc, MSG_OUT), scb->flags); 2473 } 2474 2475 /* 2476 * Clear the MK_MESSAGE flag from the SCB so we aren't 2477 * asked to send this message again. 2478 */ 2479 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2480 ahc->msgout_index = 0; 2481 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2482 } 2483 2484 static void 2485 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2486 { 2487 /* 2488 * To facilitate adding multiple messages together, 2489 * each routine should increment the index and len 2490 * variables instead of setting them explicitly. 2491 */ 2492 ahc->msgout_index = 0; 2493 ahc->msgout_len = 0; 2494 2495 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2496 ahc_build_transfer_msg(ahc, devinfo); 2497 else 2498 panic("ahc_intr: AWAITING target message with no message"); 2499 2500 ahc->msgout_index = 0; 2501 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2502 } 2503 2504 static int 2505 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2506 { 2507 /* 2508 * What we care about here is if we had an 2509 * outstanding SDTR or WDTR message for this 2510 * target. If we did, this is a signal that 2511 * the target is refusing negotiation. 2512 */ 2513 struct scb *scb; 2514 u_int scb_index; 2515 u_int last_msg; 2516 int response = 0; 2517 2518 scb_index = ahc_inb(ahc, SCB_TAG); 2519 scb = &ahc->scb_data->scbarray[scb_index]; 2520 2521 /* Might be necessary */ 2522 last_msg = ahc_inb(ahc, LAST_MSG); 2523 2524 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2525 struct ahc_initiator_tinfo *tinfo; 2526 struct tmode_tstate *tstate; 2527 2528 #ifdef AHC_DEBUG_NEG 2529 /* note 8bit xfers */ 2530 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2531 "8bit transfers\n", ahc_name(ahc), 2532 devinfo->channel, devinfo->target); 2533 #endif 2534 ahc_set_width(ahc, devinfo, 2535 MSG_EXT_WDTR_BUS_8_BIT, 2536 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2537 /*paused*/TRUE, /*done*/TRUE); 2538 /* 2539 * No need to clear the sync rate. If the target 2540 * did not accept the command, our syncrate is 2541 * unaffected. If the target started the negotiation, 2542 * but rejected our response, we already cleared the 2543 * sync rate before sending our WDTR. 2544 */ 2545 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2546 devinfo->our_scsiid, 2547 devinfo->target, &tstate); 2548 if (tinfo->goal.period) { 2549 u_int period; 2550 2551 /* Start the sync negotiation */ 2552 period = tinfo->goal.period; 2553 ahc_devlimited_syncrate(ahc, &period); 2554 ahc->msgout_index = 0; 2555 ahc->msgout_len = 0; 2556 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2557 ahc->msgout_index = 0; 2558 response = 1; 2559 } 2560 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2561 /* note asynch xfers and clear flag */ 2562 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2563 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2564 /*paused*/TRUE, /*done*/TRUE); 2565 #ifdef AHC_DEBUG_NEG 2566 printf("%s:%c:%d: refuses synchronous negotiation. " 2567 "Using asynchronous transfers\n", 2568 ahc_name(ahc), 2569 devinfo->channel, devinfo->target); 2570 #endif 2571 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2572 printf("%s:%c:%d: refuses tagged commands. Performing " 2573 "non-tagged I/O\n", ahc_name(ahc), 2574 devinfo->channel, devinfo->target); 2575 2576 ahc_set_tags(ahc, devinfo, FALSE); 2577 2578 /* 2579 * Resend the identify for this CCB as the target 2580 * may believe that the selection is invalid otherwise. 2581 */ 2582 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2583 & ~MSG_SIMPLE_Q_TAG); 2584 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2585 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2586 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2587 2588 /* 2589 * Requeue all tagged commands for this target 2590 * currently in our posession so they can be 2591 * converted to untagged commands. 2592 */ 2593 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2594 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2595 ROLE_INITIATOR, SCB_REQUEUE, 2596 SEARCH_COMPLETE); 2597 } else { 2598 /* 2599 * Otherwise, we ignore it. 2600 */ 2601 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2602 ahc_name(ahc), devinfo->channel, devinfo->target, 2603 last_msg); 2604 } 2605 return (response); 2606 } 2607 2608 static void 2609 ahc_clear_msg_state(struct ahc_softc *ahc) 2610 { 2611 ahc->msgout_len = 0; 2612 ahc->msgin_index = 0; 2613 ahc->msg_type = MSG_TYPE_NONE; 2614 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2615 } 2616 2617 static void 2618 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2619 { 2620 struct ahc_devinfo devinfo; 2621 u_int bus_phase; 2622 int end_session; 2623 2624 ahc_fetch_devinfo(ahc, &devinfo); 2625 end_session = FALSE; 2626 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2627 2628 reswitch: 2629 switch (ahc->msg_type) { 2630 case MSG_TYPE_INITIATOR_MSGOUT: 2631 { 2632 int lastbyte; 2633 int phasemis; 2634 int msgdone; 2635 2636 if (ahc->msgout_len == 0) 2637 panic("REQINIT interrupt with no active message"); 2638 2639 phasemis = bus_phase != P_MESGOUT; 2640 if (phasemis) { 2641 if (bus_phase == P_MESGIN) { 2642 /* 2643 * Change gears and see if 2644 * this messages is of interest to 2645 * us or should be passed back to 2646 * the sequencer. 2647 */ 2648 ahc_outb(ahc, CLRSINT1, CLRATNO); 2649 ahc->send_msg_perror = FALSE; 2650 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2651 ahc->msgin_index = 0; 2652 goto reswitch; 2653 } 2654 end_session = TRUE; 2655 break; 2656 } 2657 2658 if (ahc->send_msg_perror) { 2659 ahc_outb(ahc, CLRSINT1, CLRATNO); 2660 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2661 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2662 break; 2663 } 2664 2665 msgdone = ahc->msgout_index == ahc->msgout_len; 2666 if (msgdone) { 2667 /* 2668 * The target has requested a retry. 2669 * Re-assert ATN, reset our message index to 2670 * 0, and try again. 2671 */ 2672 ahc->msgout_index = 0; 2673 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2674 } 2675 2676 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2677 if (lastbyte) { 2678 /* Last byte is signified by dropping ATN */ 2679 ahc_outb(ahc, CLRSINT1, CLRATNO); 2680 } 2681 2682 /* 2683 * Clear our interrupt status and present 2684 * the next byte on the bus. 2685 */ 2686 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2687 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2688 break; 2689 } 2690 case MSG_TYPE_INITIATOR_MSGIN: 2691 { 2692 int phasemis; 2693 int message_done; 2694 2695 phasemis = bus_phase != P_MESGIN; 2696 2697 if (phasemis) { 2698 ahc->msgin_index = 0; 2699 if (bus_phase == P_MESGOUT 2700 && (ahc->send_msg_perror == TRUE 2701 || (ahc->msgout_len != 0 2702 && ahc->msgout_index == 0))) { 2703 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2704 goto reswitch; 2705 } 2706 end_session = TRUE; 2707 break; 2708 } 2709 2710 /* Pull the byte in without acking it */ 2711 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2712 2713 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2714 2715 if (message_done) { 2716 /* 2717 * Clear our incoming message buffer in case there 2718 * is another message following this one. 2719 */ 2720 ahc->msgin_index = 0; 2721 2722 /* 2723 * If this message illicited a response, 2724 * assert ATN so the target takes us to the 2725 * message out phase. 2726 */ 2727 if (ahc->msgout_len != 0) 2728 ahc_outb(ahc, SCSISIGO, 2729 ahc_inb(ahc, SCSISIGO) | ATNO); 2730 } else 2731 ahc->msgin_index++; 2732 2733 /* Ack the byte */ 2734 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2735 ahc_inb(ahc, SCSIDATL); 2736 break; 2737 } 2738 case MSG_TYPE_TARGET_MSGIN: 2739 { 2740 int msgdone; 2741 int msgout_request; 2742 2743 if (ahc->msgout_len == 0) 2744 panic("Target MSGIN with no active message"); 2745 2746 /* 2747 * If we interrupted a mesgout session, the initiator 2748 * will not know this until our first REQ. So, we 2749 * only honor mesgout requests after we've sent our 2750 * first byte. 2751 */ 2752 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2753 && ahc->msgout_index > 0) 2754 msgout_request = TRUE; 2755 else 2756 msgout_request = FALSE; 2757 2758 if (msgout_request) { 2759 2760 /* 2761 * Change gears and see if 2762 * this messages is of interest to 2763 * us or should be passed back to 2764 * the sequencer. 2765 */ 2766 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2767 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2768 ahc->msgin_index = 0; 2769 /* Dummy read to REQ for first byte */ 2770 ahc_inb(ahc, SCSIDATL); 2771 ahc_outb(ahc, SXFRCTL0, 2772 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2773 break; 2774 } 2775 2776 msgdone = ahc->msgout_index == ahc->msgout_len; 2777 if (msgdone) { 2778 ahc_outb(ahc, SXFRCTL0, 2779 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2780 end_session = TRUE; 2781 break; 2782 } 2783 2784 /* 2785 * Present the next byte on the bus. 2786 */ 2787 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2788 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2789 break; 2790 } 2791 case MSG_TYPE_TARGET_MSGOUT: 2792 { 2793 int lastbyte; 2794 int msgdone; 2795 2796 /* 2797 * The initiator signals that this is 2798 * the last byte by dropping ATN. 2799 */ 2800 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2801 2802 /* 2803 * Read the latched byte, but turn off SPIOEN first 2804 * so that we don't inadvertantly cause a REQ for the 2805 * next byte. 2806 */ 2807 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2808 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2809 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2810 if (msgdone == MSGLOOP_TERMINATED) { 2811 /* 2812 * The message is *really* done in that it caused 2813 * us to go to bus free. The sequencer has already 2814 * been reset at this point, so pull the ejection 2815 * handle. 2816 */ 2817 return; 2818 } 2819 2820 ahc->msgin_index++; 2821 2822 /* 2823 * XXX Read spec about initiator dropping ATN too soon 2824 * and use msgdone to detect it. 2825 */ 2826 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2827 ahc->msgin_index = 0; 2828 2829 /* 2830 * If this message illicited a response, transition 2831 * to the Message in phase and send it. 2832 */ 2833 if (ahc->msgout_len != 0) { 2834 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2835 ahc_outb(ahc, SXFRCTL0, 2836 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2837 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2838 ahc->msgin_index = 0; 2839 break; 2840 } 2841 } 2842 2843 if (lastbyte) 2844 end_session = TRUE; 2845 else { 2846 /* Ask for the next byte. */ 2847 ahc_outb(ahc, SXFRCTL0, 2848 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2849 } 2850 2851 break; 2852 } 2853 default: 2854 panic("Unknown REQINIT message type"); 2855 } 2856 2857 if (end_session) { 2858 ahc_clear_msg_state(ahc); 2859 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2860 } else 2861 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2862 } 2863 2864 /* 2865 * See if we sent a particular extended message to the target. 2866 * If "full" is true, the target saw the full message. 2867 * If "full" is false, the target saw at least the first 2868 * byte of the message. 2869 */ 2870 static int 2871 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2872 { 2873 int found; 2874 int index; 2875 2876 found = FALSE; 2877 index = 0; 2878 2879 while (index < ahc->msgout_len) { 2880 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2881 2882 /* Found a candidate */ 2883 if (ahc->msgout_buf[index+2] == msgtype) { 2884 u_int end_index; 2885 2886 end_index = index + 1 2887 + ahc->msgout_buf[index + 1]; 2888 if (full) { 2889 if (ahc->msgout_index > end_index) 2890 found = TRUE; 2891 } else if (ahc->msgout_index > index) 2892 found = TRUE; 2893 } 2894 break; 2895 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2896 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2897 2898 /* Skip tag type and tag id or residue param*/ 2899 index += 2; 2900 } else { 2901 /* Single byte message */ 2902 index++; 2903 } 2904 } 2905 return (found); 2906 } 2907 2908 static int 2909 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2910 struct ahc_devinfo *devinfo) 2911 { 2912 struct ahc_initiator_tinfo *tinfo; 2913 struct tmode_tstate *tstate; 2914 int reject; 2915 int done; 2916 int response; 2917 u_int targ_scsirate; 2918 2919 done = MSGLOOP_IN_PROG; 2920 response = FALSE; 2921 reject = FALSE; 2922 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2923 devinfo->target, &tstate); 2924 targ_scsirate = tinfo->scsirate; 2925 2926 /* 2927 * Parse as much of the message as is availible, 2928 * rejecting it if we don't support it. When 2929 * the entire message is availible and has been 2930 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2931 * that we have parsed an entire message. 2932 * 2933 * In the case of extended messages, we accept the length 2934 * byte outright and perform more checking once we know the 2935 * extended message type. 2936 */ 2937 switch (ahc->msgin_buf[0]) { 2938 case MSG_MESSAGE_REJECT: 2939 response = ahc_handle_msg_reject(ahc, devinfo); 2940 /* FALLTHROUGH */ 2941 case MSG_NOOP: 2942 done = MSGLOOP_MSGCOMPLETE; 2943 break; 2944 case MSG_IGN_WIDE_RESIDUE: 2945 { 2946 /* Wait for the whole message */ 2947 if (ahc->msgin_index >= 1) { 2948 if (ahc->msgin_buf[1] != 1 2949 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2950 reject = TRUE; 2951 done = MSGLOOP_MSGCOMPLETE; 2952 } else 2953 ahc_handle_ign_wide_residue(ahc, devinfo); 2954 } 2955 break; 2956 } 2957 case MSG_EXTENDED: 2958 { 2959 /* Wait for enough of the message to begin validation */ 2960 if (ahc->msgin_index < 2) 2961 break; 2962 switch (ahc->msgin_buf[2]) { 2963 case MSG_EXT_SDTR: 2964 { 2965 struct ahc_syncrate *syncrate; 2966 u_int period; 2967 u_int offset; 2968 u_int saved_offset; 2969 2970 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2971 reject = TRUE; 2972 break; 2973 } 2974 2975 /* 2976 * Wait until we have both args before validating 2977 * and acting on this message. 2978 * 2979 * Add one to MSG_EXT_SDTR_LEN to account for 2980 * the extended message preamble. 2981 */ 2982 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2983 break; 2984 2985 period = ahc->msgin_buf[3]; 2986 saved_offset = offset = ahc->msgin_buf[4]; 2987 syncrate = ahc_devlimited_syncrate(ahc, &period); 2988 ahc_validate_offset(ahc, syncrate, &offset, 2989 targ_scsirate & WIDEXFER); 2990 ahc_set_syncrate(ahc, devinfo, 2991 syncrate, period, offset, 2992 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2993 /*paused*/TRUE, /*done*/TRUE); 2994 2995 /* 2996 * See if we initiated Sync Negotiation 2997 * and didn't have to fall down to async 2998 * transfers. 2999 */ 3000 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3001 /* We started it */ 3002 if (saved_offset != offset) { 3003 /* Went too low - force async */ 3004 reject = TRUE; 3005 } 3006 } else { 3007 /* 3008 * Send our own SDTR in reply 3009 */ 3010 ahc->msgout_index = 0; 3011 ahc->msgout_len = 0; 3012 ahc_construct_sdtr(ahc, period, offset); 3013 ahc->msgout_index = 0; 3014 response = TRUE; 3015 } 3016 done = MSGLOOP_MSGCOMPLETE; 3017 break; 3018 } 3019 case MSG_EXT_WDTR: 3020 { 3021 u_int bus_width; 3022 u_int sending_reply; 3023 3024 sending_reply = FALSE; 3025 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3026 reject = TRUE; 3027 break; 3028 } 3029 3030 /* 3031 * Wait until we have our arg before validating 3032 * and acting on this message. 3033 * 3034 * Add one to MSG_EXT_WDTR_LEN to account for 3035 * the extended message preamble. 3036 */ 3037 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3038 break; 3039 3040 bus_width = ahc->msgin_buf[3]; 3041 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3042 /* 3043 * Don't send a WDTR back to the 3044 * target, since we asked first. 3045 */ 3046 switch (bus_width){ 3047 default: 3048 /* 3049 * How can we do anything greater 3050 * than 16bit transfers on a 16bit 3051 * bus? 3052 */ 3053 reject = TRUE; 3054 printf("%s: target %d requested %dBit " 3055 "transfers. Rejecting...\n", 3056 ahc_name(ahc), devinfo->target, 3057 8 * (0x01 << bus_width)); 3058 /* FALLTHROUGH */ 3059 case MSG_EXT_WDTR_BUS_8_BIT: 3060 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3061 break; 3062 case MSG_EXT_WDTR_BUS_16_BIT: 3063 break; 3064 } 3065 } else { 3066 /* 3067 * Send our own WDTR in reply 3068 */ 3069 switch (bus_width) { 3070 default: 3071 if (ahc->features & AHC_WIDE) { 3072 /* Respond Wide */ 3073 bus_width = 3074 MSG_EXT_WDTR_BUS_16_BIT; 3075 break; 3076 } 3077 /* FALLTHROUGH */ 3078 case MSG_EXT_WDTR_BUS_8_BIT: 3079 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3080 break; 3081 } 3082 ahc->msgout_index = 0; 3083 ahc->msgout_len = 0; 3084 ahc_construct_wdtr(ahc, bus_width); 3085 ahc->msgout_index = 0; 3086 response = TRUE; 3087 sending_reply = TRUE; 3088 } 3089 ahc_set_width(ahc, devinfo, bus_width, 3090 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3091 /*paused*/TRUE, /*done*/TRUE); 3092 3093 /* After a wide message, we are async */ 3094 ahc_set_syncrate(ahc, devinfo, 3095 /*syncrate*/NULL, /*period*/0, 3096 /*offset*/0, AHC_TRANS_ACTIVE, 3097 /*paused*/TRUE, /*done*/FALSE); 3098 if (sending_reply == FALSE && reject == FALSE) { 3099 3100 if (tinfo->goal.period) { 3101 struct ahc_syncrate *rate; 3102 u_int period; 3103 u_int offset; 3104 3105 /* Start the sync negotiation */ 3106 period = tinfo->goal.period; 3107 rate = ahc_devlimited_syncrate(ahc, 3108 &period); 3109 offset = tinfo->goal.offset; 3110 ahc_validate_offset(ahc, rate, &offset, 3111 tinfo->current.width); 3112 ahc->msgout_index = 0; 3113 ahc->msgout_len = 0; 3114 ahc_construct_sdtr(ahc, period, offset); 3115 ahc->msgout_index = 0; 3116 response = TRUE; 3117 } 3118 } 3119 done = MSGLOOP_MSGCOMPLETE; 3120 break; 3121 } 3122 default: 3123 /* Unknown extended message. Reject it. */ 3124 reject = TRUE; 3125 break; 3126 } 3127 break; 3128 } 3129 case MSG_BUS_DEV_RESET: 3130 ahc_handle_devreset(ahc, devinfo, 3131 XS_RESET, "Bus Device Reset Received", 3132 /*verbose_level*/0); 3133 restart_sequencer(ahc); 3134 done = MSGLOOP_TERMINATED; 3135 break; 3136 case MSG_ABORT_TAG: 3137 case MSG_ABORT: 3138 case MSG_CLEAR_QUEUE: 3139 /* Target mode messages */ 3140 if (devinfo->role != ROLE_TARGET) { 3141 reject = TRUE; 3142 break; 3143 } 3144 #if AHC_TARGET_MODE 3145 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3146 devinfo->lun, 3147 ahc->msgin_buf[0] == MSG_ABORT_TAG 3148 ? SCB_LIST_NULL 3149 : ahc_inb(ahc, INITIATOR_TAG), 3150 ROLE_TARGET, XS_DRIVER_STUFFUP); 3151 3152 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3153 if (tstate != NULL) { 3154 struct tmode_lstate* lstate; 3155 3156 lstate = tstate->enabled_luns[devinfo->lun]; 3157 if (lstate != NULL) { 3158 ahc_queue_lstate_event(ahc, lstate, 3159 devinfo->our_scsiid, 3160 ahc->msgin_buf[0], 3161 /*arg*/0); 3162 ahc_send_lstate_events(ahc, lstate); 3163 } 3164 } 3165 done = MSGLOOP_MSGCOMPLETE; 3166 #else 3167 panic("ahc: got target mode message"); 3168 #endif 3169 break; 3170 case MSG_TERM_IO_PROC: 3171 default: 3172 reject = TRUE; 3173 break; 3174 } 3175 3176 if (reject) { 3177 /* 3178 * Setup to reject the message. 3179 */ 3180 ahc->msgout_index = 0; 3181 ahc->msgout_len = 1; 3182 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3183 done = MSGLOOP_MSGCOMPLETE; 3184 response = TRUE; 3185 } 3186 3187 if (done != MSGLOOP_IN_PROG && !response) 3188 /* Clear the outgoing message buffer */ 3189 ahc->msgout_len = 0; 3190 3191 return (done); 3192 } 3193 3194 static void 3195 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3196 { 3197 u_int scb_index; 3198 struct scb *scb; 3199 3200 scb_index = ahc_inb(ahc, SCB_TAG); 3201 scb = &ahc->scb_data->scbarray[scb_index]; 3202 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3203 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3204 /* 3205 * Ignore the message if we haven't 3206 * seen an appropriate data phase yet. 3207 */ 3208 } else { 3209 /* 3210 * If the residual occurred on the last 3211 * transfer and the transfer request was 3212 * expected to end on an odd count, do 3213 * nothing. Otherwise, subtract a byte 3214 * and update the residual count accordingly. 3215 */ 3216 u_int resid_sgcnt; 3217 3218 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3219 if (resid_sgcnt == 0 3220 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3221 /* 3222 * If the residual occurred on the last 3223 * transfer and the transfer request was 3224 * expected to end on an odd count, do 3225 * nothing. 3226 */ 3227 } else { 3228 u_int data_cnt; 3229 u_int32_t data_addr; 3230 u_int sg_index; 3231 3232 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3233 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3234 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3235 3236 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3237 | (ahc_inb(ahc, SHADDR + 2) << 16) 3238 | (ahc_inb(ahc, SHADDR + 1) << 8) 3239 | (ahc_inb(ahc, SHADDR)); 3240 3241 data_cnt += 1; 3242 data_addr -= 1; 3243 3244 sg_index = scb->sg_count - resid_sgcnt; 3245 3246 if (sg_index != 0 3247 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3248 u_int32_t sg_addr; 3249 3250 sg_index--; 3251 data_cnt = 1; 3252 data_addr = le32toh(scb->sg_list[sg_index].addr) 3253 + le32toh(scb->sg_list[sg_index].len) 3254 - 1; 3255 3256 /* 3257 * The physical address base points to the 3258 * second entry as it is always used for 3259 * calculating the "next S/G pointer". 3260 */ 3261 sg_addr = scb->sg_list_phys 3262 + (sg_index* sizeof(*scb->sg_list)); 3263 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3264 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3265 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3266 ahc_outb(ahc, SG_NEXT, sg_addr); 3267 } 3268 3269 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3270 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3271 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3272 3273 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3274 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3275 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3276 ahc_outb(ahc, SHADDR, data_addr); 3277 } 3278 } 3279 } 3280 3281 static void 3282 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3283 int status, char *message, 3284 int verbose_level) 3285 { 3286 int found; 3287 3288 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3289 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3290 status); 3291 3292 /* 3293 * Go back to async/narrow transfers and renegotiate. 3294 * ahc_set_width and ahc_set_syncrate can cope with NULL 3295 * paths. 3296 */ 3297 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3298 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3299 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3300 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3301 /*paused*/TRUE, /*done*/FALSE); 3302 3303 if (message != NULL && (verbose_level <= 0)) 3304 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3305 message, devinfo->channel, devinfo->target, found); 3306 } 3307 3308 /* 3309 * We have an scb which has been processed by the 3310 * adaptor, now we look to see how the operation 3311 * went. 3312 */ 3313 static void 3314 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3315 { 3316 struct scsipi_xfer *xs; 3317 struct scsipi_link *sc_link; 3318 int requeue = 0; 3319 int target; 3320 3321 3322 xs = scb->xs; 3323 sc_link = xs->sc_link; 3324 LIST_REMOVE(scb, plinks); 3325 3326 callout_stop(&scb->xs->xs_callout); 3327 3328 #ifdef AHC_DEBUG 3329 if (ahc_debug & AHC_SHOWCMDS) { 3330 scsi_print_addr(sc_link); 3331 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3332 scb->hscb->tag); 3333 } 3334 #endif 3335 3336 target = sc_link->scsipi_scsi.target; 3337 3338 if (xs->datalen) { 3339 int op; 3340 3341 if (xs->xs_control & XS_CTL_DATA_IN) 3342 op = BUS_DMASYNC_POSTREAD; 3343 else 3344 op = BUS_DMASYNC_POSTWRITE; 3345 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3346 scb->dmamap->dm_mapsize, op); 3347 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3348 } 3349 3350 /* 3351 * Unbusy this target/channel/lun. 3352 * XXX if we are holding two commands per lun, 3353 * send the next command. 3354 */ 3355 if (!(scb->hscb->control & TAG_ENB)) 3356 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3357 3358 /* 3359 * If the recovery SCB completes, we have to be 3360 * out of our timeout. 3361 */ 3362 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3363 3364 struct scb *scbp; 3365 3366 /* 3367 * We were able to complete the command successfully, 3368 * so reinstate the timeouts for all other pending 3369 * commands. 3370 */ 3371 scbp = ahc->pending_ccbs.lh_first; 3372 while (scbp != NULL) { 3373 struct scsipi_xfer *txs = scbp->xs; 3374 3375 if (!(txs->xs_control & XS_CTL_POLL)) { 3376 callout_reset(&scbp->xs->xs_callout, 3377 (scbp->xs->timeout * hz) / 1000, 3378 ahc_timeout, scbp); 3379 } 3380 scbp = LIST_NEXT(scbp, plinks); 3381 } 3382 3383 /* 3384 * Ensure that we didn't put a second instance of this 3385 * SCB into the QINFIFO. 3386 */ 3387 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3388 SCB_LUN(scb), scb->hscb->tag, 3389 ROLE_INITIATOR, /*status*/0, 3390 SEARCH_REMOVE); 3391 if (xs->error != XS_NOERROR) 3392 ahcsetccbstatus(xs, XS_TIMEOUT); 3393 scsi_print_addr(xs->sc_link); 3394 printf("no longer in timeout, status = %x\n", xs->status); 3395 } 3396 3397 if (xs->error != XS_NOERROR) { 3398 /* Don't clobber any existing error state */ 3399 } else if ((scb->flags & SCB_SENSE) != 0) { 3400 /* 3401 * We performed autosense retrieval. 3402 * 3403 * bzero the sense data before having 3404 * the drive fill it. The SCSI spec mandates 3405 * that any untransfered data should be 3406 * assumed to be zero. Complete the 'bounce' 3407 * of sense information through buffers accessible 3408 * via bus-space by copying it into the clients 3409 * csio. 3410 */ 3411 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3412 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3413 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3414 xs->error = XS_SENSE; 3415 } 3416 if (scb->flags & SCB_FREEZE_QUEUE) { 3417 ahc->devqueue_blocked[target]--; 3418 scb->flags &= ~SCB_FREEZE_QUEUE; 3419 } 3420 3421 requeue = scb->flags & SCB_REQUEUE; 3422 ahcfreescb(ahc, scb); 3423 3424 if (requeue) { 3425 /* 3426 * Re-insert at the front of the private queue to 3427 * preserve order. 3428 */ 3429 int s; 3430 3431 s = splbio(); 3432 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3433 splx(s); 3434 } else { 3435 xs->xs_status |= XS_STS_DONE; 3436 #ifndef AHC_NO_TAGS 3437 ahc_check_tags(ahc, xs); 3438 #endif 3439 scsipi_done(xs); 3440 } 3441 3442 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3443 ahc_action(xs); 3444 } 3445 3446 /* 3447 * Determine the number of SCBs available on the controller 3448 */ 3449 int 3450 ahc_probe_scbs(struct ahc_softc *ahc) { 3451 int i; 3452 3453 for (i = 0; i < AHC_SCB_MAX; i++) { 3454 ahc_outb(ahc, SCBPTR, i); 3455 ahc_outb(ahc, SCB_CONTROL, i); 3456 if (ahc_inb(ahc, SCB_CONTROL) != i) 3457 break; 3458 ahc_outb(ahc, SCBPTR, 0); 3459 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3460 break; 3461 } 3462 return (i); 3463 } 3464 3465 /* 3466 * Start the board, ready for normal operation 3467 */ 3468 int 3469 ahc_init(struct ahc_softc *ahc) 3470 { 3471 int max_targ = 15; 3472 int i; 3473 int term; 3474 u_int scsi_conf; 3475 u_int scsiseq_template; 3476 u_int ultraenb; 3477 u_int discenable; 3478 u_int tagenable; 3479 size_t driver_data_size; 3480 u_int32_t physaddr; 3481 3482 #ifdef AHC_PRINT_SRAM 3483 printf("Scratch Ram:"); 3484 for (i = 0x20; i < 0x5f; i++) { 3485 if (((i % 8) == 0) && (i != 0)) { 3486 printf ("\n "); 3487 } 3488 printf (" 0x%x", ahc_inb(ahc, i)); 3489 } 3490 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3491 for (i = 0x70; i < 0x7f; i++) { 3492 if (((i % 8) == 0) && (i != 0)) { 3493 printf ("\n "); 3494 } 3495 printf (" 0x%x", ahc_inb(ahc, i)); 3496 } 3497 } 3498 printf ("\n"); 3499 #endif 3500 3501 /* 3502 * Assume we have a board at this stage and it has been reset. 3503 */ 3504 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3505 ahc->our_id = ahc->our_id_b = 7; 3506 3507 /* 3508 * Default to allowing initiator operations. 3509 */ 3510 ahc->flags |= AHC_INITIATORMODE; 3511 3512 /* 3513 * DMA tag for our command fifos and other data in system memory 3514 * the card's sequencer must be able to access. For initiator 3515 * roles, we need to allocate space for the qinfifo, qoutfifo, 3516 * and untagged_scb arrays each of which are composed of 256 3517 * 1 byte elements. When providing for the target mode role, 3518 * we additionally must provide space for the incoming target 3519 * command fifo. 3520 */ 3521 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3522 3523 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3524 ahc->sc_dmaflags, 3525 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3526 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3527 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3528 return (ENOMEM); 3529 3530 ahc->init_level++; 3531 3532 /* Allocate SCB data now that parent_dmat is initialized */ 3533 if (ahc->scb_data->maxhscbs == 0) 3534 if (ahcinitscbdata(ahc) != 0) 3535 return (ENOMEM); 3536 3537 ahc->qinfifo = &ahc->qoutfifo[256]; 3538 ahc->untagged_scbs = &ahc->qinfifo[256]; 3539 /* There are no untagged SCBs active yet. */ 3540 for (i = 0; i < 256; i++) 3541 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3542 3543 /* All of our queues are empty */ 3544 for (i = 0; i < 256; i++) 3545 ahc->qoutfifo[i] = SCB_LIST_NULL; 3546 3547 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3548 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3549 3550 /* 3551 * Allocate a tstate to house information for our 3552 * initiator presence on the bus as well as the user 3553 * data for any target mode initiator. 3554 */ 3555 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3556 printf("%s: unable to allocate tmode_tstate. " 3557 "Failing attach\n", ahc_name(ahc)); 3558 return (-1); 3559 } 3560 3561 if ((ahc->features & AHC_TWIN) != 0) { 3562 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3563 printf("%s: unable to allocate tmode_tstate. " 3564 "Failing attach\n", ahc_name(ahc)); 3565 return (-1); 3566 } 3567 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3568 ahc->our_id, ahc->our_id_b, 3569 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3570 } else { 3571 if ((ahc->features & AHC_WIDE) != 0) { 3572 printf("Wide "); 3573 } else { 3574 printf("Single "); 3575 } 3576 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3577 } 3578 3579 ahc_outb(ahc, SEQ_FLAGS, 0); 3580 3581 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3582 ahc->flags |= AHC_PAGESCBS; 3583 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3584 } else { 3585 ahc->flags &= ~AHC_PAGESCBS; 3586 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3587 } 3588 3589 #ifdef AHC_DEBUG 3590 if (ahc_debug & AHC_SHOWMISC) { 3591 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3592 "ahc_dma %d bytes\n", 3593 ahc_name(ahc), 3594 sizeof(struct hardware_scb), 3595 sizeof(struct scb), 3596 sizeof(struct ahc_dma_seg)); 3597 } 3598 #endif /* AHC_DEBUG */ 3599 3600 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3601 if (ahc->features & AHC_TWIN) { 3602 3603 /* 3604 * The device is gated to channel B after a chip reset, 3605 * so set those values first 3606 */ 3607 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3608 if ((ahc->features & AHC_ULTRA2) != 0) 3609 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3610 else 3611 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3612 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3613 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3614 |term|ENSTIMER|ACTNEGEN); 3615 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3616 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3617 3618 if ((scsi_conf & RESET_SCSI) != 0 3619 && (ahc->flags & AHC_INITIATORMODE) != 0) 3620 ahc->flags |= AHC_RESET_BUS_B; 3621 3622 /* Select Channel A */ 3623 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3624 } 3625 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3626 if ((ahc->features & AHC_ULTRA2) != 0) 3627 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3628 else 3629 ahc_outb(ahc, SCSIID, ahc->our_id); 3630 scsi_conf = ahc_inb(ahc, SCSICONF); 3631 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3632 |term 3633 |ENSTIMER|ACTNEGEN); 3634 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3635 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3636 3637 if ((scsi_conf & RESET_SCSI) != 0 3638 && (ahc->flags & AHC_INITIATORMODE) != 0) 3639 ahc->flags |= AHC_RESET_BUS_A; 3640 3641 /* 3642 * Look at the information that board initialization or 3643 * the board bios has left us. 3644 */ 3645 ultraenb = 0; 3646 tagenable = ALL_TARGETS_MASK; 3647 3648 /* Grab the disconnection disable table and invert it for our needs */ 3649 if (ahc->flags & AHC_USEDEFAULTS) { 3650 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3651 "device parameters\n", ahc_name(ahc)); 3652 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3653 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3654 discenable = ALL_TARGETS_MASK; 3655 if ((ahc->features & AHC_ULTRA) != 0) 3656 ultraenb = ALL_TARGETS_MASK; 3657 } else { 3658 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3659 | ahc_inb(ahc, DISC_DSB)); 3660 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3661 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3662 | ahc_inb(ahc, ULTRA_ENB); 3663 } 3664 3665 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3666 max_targ = 7; 3667 3668 for (i = 0; i <= max_targ; i++) { 3669 struct ahc_initiator_tinfo *tinfo; 3670 struct tmode_tstate *tstate; 3671 u_int our_id; 3672 u_int target_id; 3673 char channel; 3674 3675 channel = 'A'; 3676 our_id = ahc->our_id; 3677 target_id = i; 3678 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3679 channel = 'B'; 3680 our_id = ahc->our_id_b; 3681 target_id = i % 8; 3682 } 3683 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3684 target_id, &tstate); 3685 /* Default to async narrow across the board */ 3686 bzero(tinfo, sizeof(*tinfo)); 3687 if (ahc->flags & AHC_USEDEFAULTS) { 3688 if ((ahc->features & AHC_WIDE) != 0) 3689 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3690 3691 /* 3692 * These will be truncated when we determine the 3693 * connection type we have with the target. 3694 */ 3695 tinfo->user.period = ahc_syncrates->period; 3696 tinfo->user.offset = ~0; 3697 } else { 3698 u_int scsirate; 3699 u_int16_t mask; 3700 3701 /* Take the settings leftover in scratch RAM. */ 3702 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3703 mask = (0x01 << i); 3704 if ((ahc->features & AHC_ULTRA2) != 0) { 3705 u_int offset; 3706 u_int maxsync; 3707 3708 if ((scsirate & SOFS) == 0x0F) { 3709 /* 3710 * Haven't negotiated yet, 3711 * so the format is different. 3712 */ 3713 scsirate = (scsirate & SXFR) >> 4 3714 | (ultraenb & mask) 3715 ? 0x08 : 0x0 3716 | (scsirate & WIDEXFER); 3717 offset = MAX_OFFSET_ULTRA2; 3718 } else 3719 offset = ahc_inb(ahc, TARG_OFFSET + i); 3720 maxsync = AHC_SYNCRATE_ULTRA2; 3721 if ((ahc->features & AHC_DT) != 0) 3722 maxsync = AHC_SYNCRATE_DT; 3723 tinfo->user.period = 3724 ahc_find_period(ahc, scsirate, maxsync); 3725 if (offset == 0) 3726 tinfo->user.period = 0; 3727 else 3728 tinfo->user.offset = ~0; 3729 } else if ((scsirate & SOFS) != 0) { 3730 tinfo->user.period = 3731 ahc_find_period(ahc, scsirate, 3732 (ultraenb & mask) 3733 ? AHC_SYNCRATE_ULTRA 3734 : AHC_SYNCRATE_FAST); 3735 if (tinfo->user.period != 0) 3736 tinfo->user.offset = ~0; 3737 } 3738 if ((scsirate & WIDEXFER) != 0 3739 && (ahc->features & AHC_WIDE) != 0) 3740 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3741 } 3742 tinfo->goal = tinfo->user; /* force negotiation */ 3743 tstate->ultraenb = ultraenb; 3744 tstate->discenable = discenable; 3745 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3746 tstate->tagdisable = 0; 3747 } 3748 ahc->user_discenable = discenable; 3749 ahc->user_tagenable = tagenable; 3750 3751 /* 3752 * Tell the sequencer where it can find our arrays in memory. 3753 */ 3754 physaddr = ahc->scb_data->hscb_busaddr; 3755 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3756 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3757 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3758 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3759 3760 physaddr = ahc->shared_data_busaddr; 3761 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3762 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3763 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3764 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3765 3766 /* Target mode incomding command fifo */ 3767 physaddr += 3 * 256 * sizeof(u_int8_t); 3768 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3769 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3770 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3771 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3772 3773 /* 3774 * Initialize the group code to command length table. 3775 * This overrides the values in TARG_SCSIRATE, so only 3776 * setup the table after we have processed that information. 3777 */ 3778 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3781 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3782 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3783 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3784 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3785 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3786 3787 /* Tell the sequencer of our initial queue positions */ 3788 ahc_outb(ahc, KERNEL_QINPOS, 0); 3789 ahc_outb(ahc, QINPOS, 0); 3790 ahc_outb(ahc, QOUTPOS, 0); 3791 3792 #ifdef AHC_DEBUG 3793 if (ahc_debug & AHC_SHOWMISC) 3794 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3795 discenable, ultraenb); 3796 #endif 3797 3798 /* Don't have any special messages to send to targets */ 3799 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3800 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3801 3802 /* 3803 * Use the built in queue management registers 3804 * if they are available. 3805 */ 3806 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3807 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3808 ahc_outb(ahc, SDSCB_QOFF, 0); 3809 ahc_outb(ahc, SNSCB_QOFF, 0); 3810 ahc_outb(ahc, HNSCB_QOFF, 0); 3811 } 3812 3813 3814 /* We don't have any waiting selections */ 3815 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3816 3817 /* Our disconnection list is empty too */ 3818 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3819 3820 /* Message out buffer starts empty */ 3821 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3822 3823 /* 3824 * Setup the allowed SCSI Sequences based on operational mode. 3825 * If we are a target, we'll enable select in operations once 3826 * we've had a lun enabled. 3827 */ 3828 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3829 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3830 scsiseq_template |= ENRSELI; 3831 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3832 3833 /* 3834 * Load the Sequencer program and Enable the adapter 3835 * in "fast" mode. 3836 */ 3837 #ifdef AHC_DEBUG 3838 printf("%s: Downloading Sequencer Program...", 3839 ahc_name(ahc)); 3840 #endif 3841 3842 ahc_loadseq(ahc); 3843 3844 /* We have to wait until after any system dumps... */ 3845 shutdownhook_establish(ahc_shutdown, ahc); 3846 3847 return (0); 3848 } 3849 3850 static int 3851 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3852 struct proc *p) 3853 { 3854 struct ahc_softc *ahc = sc_link->adapter_softc; 3855 char channel; 3856 int s, ret = ENOTTY; 3857 3858 switch (cmd) { 3859 case SCBUSIORESET: 3860 channel = SIM_CHANNEL(ahc, sc_link); 3861 s = splbio(); 3862 ahc_reset_channel(ahc, channel, TRUE); 3863 splx(s); 3864 ret = 0; 3865 break; 3866 default: 3867 } 3868 3869 return ret; 3870 } 3871 3872 3873 /* 3874 * XXX fvdl the busy_tcl checks and settings should only be done 3875 * for the non-tagged queueing case, but we don't do tagged queueing 3876 * yet, so.. 3877 */ 3878 static int32_t 3879 ahc_action(struct scsipi_xfer *xs) 3880 { 3881 struct scsipi_xfer *first_xs, *next_xs = NULL; 3882 struct ahc_softc *ahc; 3883 struct scb *scb; 3884 struct hardware_scb *hscb; 3885 struct ahc_initiator_tinfo *tinfo; 3886 struct tmode_tstate *tstate; 3887 u_int target_id; 3888 u_int our_id; 3889 int s, tcl; 3890 u_int16_t mask; 3891 char channel; 3892 int dontqueue = 0, fromqueue = 0; 3893 3894 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3895 3896 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3897 3898 /* must protect the queue */ 3899 s = splbio(); 3900 3901 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3902 /* 3903 * Called from ahc_done. Calling with the first entry in 3904 * the queue is really just a way of seeing where we're 3905 * called from. Now, find the first eligible SCB to send, 3906 * e.g. one which will be accepted immediately. 3907 */ 3908 3909 if (ahc->queue_blocked) { 3910 splx(s); 3911 return (TRY_AGAIN_LATER); 3912 } 3913 3914 xs = ahc_first_xs(ahc); 3915 if (xs == NULL) { 3916 splx(s); 3917 return (TRY_AGAIN_LATER); 3918 } 3919 3920 next_xs = TAILQ_NEXT(xs, adapter_q); 3921 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3922 fromqueue = 1; 3923 goto get_scb; 3924 } 3925 3926 /* 3927 * If no new requests are accepted, just insert into the 3928 * private queue to wait for our turn. 3929 */ 3930 tcl = XS_TCL(ahc, xs); 3931 3932 if (ahc->queue_blocked || 3933 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3934 (!ahc_istagged_device(ahc, xs, 0) && 3935 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3936 if (dontqueue) { 3937 splx(s); 3938 xs->error = XS_DRIVER_STUFFUP; 3939 return TRY_AGAIN_LATER; 3940 } 3941 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3942 splx(s); 3943 return SUCCESSFULLY_QUEUED; 3944 } 3945 3946 first_xs = ahc_first_xs(ahc); 3947 3948 /* determine safety of software queueing */ 3949 dontqueue = xs->xs_control & XS_CTL_POLL; 3950 3951 /* 3952 * Handle situations where there's already entries in the 3953 * queue. 3954 */ 3955 if (first_xs != NULL) { 3956 /* 3957 * If we can't queue, we have to abort, since 3958 * we have to preserve order. 3959 */ 3960 if (dontqueue) { 3961 splx(s); 3962 xs->error = XS_DRIVER_STUFFUP; 3963 return (TRY_AGAIN_LATER); 3964 } 3965 3966 /* 3967 * Swap with the first queue entry. 3968 */ 3969 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3970 xs = first_xs; 3971 next_xs = TAILQ_NEXT(xs, adapter_q); 3972 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3973 fromqueue = 1; 3974 3975 } 3976 3977 get_scb: 3978 3979 target_id = xs->sc_link->scsipi_scsi.target; 3980 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3981 3982 /* 3983 * get an scb to use. 3984 */ 3985 if ((scb = ahcgetscb(ahc)) == NULL) { 3986 3987 if (dontqueue) { 3988 splx(s); 3989 xs->error = XS_DRIVER_STUFFUP; 3990 return (TRY_AGAIN_LATER); 3991 } 3992 3993 /* 3994 * If we were pulled off the queue, put ourselves 3995 * back to where we came from, otherwise tack ourselves 3996 * onto the end. 3997 */ 3998 if (fromqueue && next_xs != NULL) 3999 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 4000 else 4001 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4002 4003 splx(s); 4004 return (SUCCESSFULLY_QUEUED); 4005 } 4006 4007 tcl = XS_TCL(ahc, xs); 4008 4009 #ifdef DIAGNOSTIC 4010 if (!ahc_istagged_device(ahc, xs, 0) && 4011 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4012 panic("ahc: queuing for busy target"); 4013 #endif 4014 4015 scb->xs = xs; 4016 hscb = scb->hscb; 4017 hscb->tcl = tcl; 4018 4019 if (ahc_istagged_device(ahc, xs, 0)) 4020 if((xs->bp != NULL) && xs->bp->b_flags & B_ASYNC) 4021 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4022 else 4023 scb->hscb->control |= MSG_ORDERED_Q_TAG; 4024 else 4025 ahc_busy_tcl(ahc, scb); 4026 4027 splx(s); 4028 4029 channel = SIM_CHANNEL(ahc, xs->sc_link); 4030 if (ahc->inited_channels[channel - 'A'] == 0) { 4031 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4032 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4033 s = splbio(); 4034 ahc_reset_channel(ahc, channel, TRUE); 4035 splx(s); 4036 } 4037 ahc->inited_channels[channel - 'A'] = 1; 4038 } 4039 4040 /* 4041 * Put all the arguments for the xfer in the scb 4042 */ 4043 4044 mask = SCB_TARGET_MASK(scb); 4045 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4046 target_id, &tstate); 4047 if (ahc->inited_targets[target_id] == 0) { 4048 struct ahc_devinfo devinfo; 4049 4050 s = splbio(); 4051 ahc_compile_devinfo(&devinfo, our_id, target_id, 4052 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4053 ROLE_INITIATOR); 4054 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4055 FALSE); 4056 ahc->inited_targets[target_id] = 1; 4057 splx(s); 4058 } 4059 4060 hscb->scsirate = tinfo->scsirate; 4061 hscb->scsioffset = tinfo->current.offset; 4062 if ((tstate->ultraenb & mask) != 0) 4063 hscb->control |= ULTRAENB; 4064 4065 if ((tstate->discenable & mask) != 0) 4066 hscb->control |= DISCENB; 4067 4068 if (xs->xs_control & XS_CTL_RESET) { 4069 hscb->cmdpointer = 0; 4070 scb->flags |= SCB_DEVICE_RESET; 4071 hscb->control |= MK_MESSAGE; 4072 return ahc_execute_scb(scb, NULL, 0); 4073 } 4074 4075 return ahc_setup_data(ahc, xs, scb); 4076 } 4077 4078 static int 4079 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4080 { 4081 struct scb *scb; 4082 struct scsipi_xfer *xs; 4083 struct ahc_softc *ahc; 4084 int s; 4085 4086 scb = (struct scb *)arg; 4087 xs = scb->xs; 4088 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4089 4090 4091 if (nsegments != 0) { 4092 struct ahc_dma_seg *sg; 4093 bus_dma_segment_t *end_seg; 4094 int op; 4095 4096 end_seg = dm_segs + nsegments; 4097 4098 /* Copy the first SG into the data pointer area */ 4099 scb->hscb->data = dm_segs->ds_addr; 4100 scb->hscb->datalen = dm_segs->ds_len; 4101 4102 /* Copy the segments into our SG list */ 4103 sg = scb->sg_list; 4104 while (dm_segs < end_seg) { 4105 sg->addr = dm_segs->ds_addr; 4106 sg->len = dm_segs->ds_len; 4107 ahc_swap_sg(sg); 4108 sg++; 4109 dm_segs++; 4110 } 4111 4112 /* Note where to find the SG entries in bus space */ 4113 scb->hscb->SG_pointer = scb->sg_list_phys; 4114 4115 if (xs->xs_control & XS_CTL_DATA_IN) 4116 op = BUS_DMASYNC_PREREAD; 4117 else 4118 op = BUS_DMASYNC_PREWRITE; 4119 4120 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4121 scb->dmamap->dm_mapsize, op); 4122 4123 } else { 4124 scb->hscb->SG_pointer = 0; 4125 scb->hscb->data = 0; 4126 scb->hscb->datalen = 0; 4127 } 4128 4129 scb->sg_count = scb->hscb->SG_count = nsegments; 4130 4131 s = splbio(); 4132 4133 /* 4134 * Last time we need to check if this SCB needs to 4135 * be aborted. 4136 */ 4137 if (xs->xs_status & XS_STS_DONE) { 4138 if (!ahc_istagged_device(ahc, xs, 0)) 4139 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4140 if (nsegments != 0) 4141 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4142 ahcfreescb(ahc, scb); 4143 splx(s); 4144 return (COMPLETE); 4145 } 4146 4147 #ifdef DIAGNOSTIC 4148 if (scb->sg_count > 255) 4149 panic("ahc bad sg_count"); 4150 #endif 4151 4152 ahc_swap_hscb(scb->hscb); 4153 4154 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4155 4156 scb->flags |= SCB_ACTIVE; 4157 4158 if (!(xs->xs_control & XS_CTL_POLL)) 4159 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4160 ahc_timeout, scb); 4161 4162 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4163 #if 0 4164 printf("Continueing Immediate Command %d:%d\n", 4165 xs->sc_link->scsipi_scsi.target, 4166 xs->sc_link->scsipi_scsi.lun); 4167 #endif 4168 pause_sequencer(ahc); 4169 if ((ahc->flags & AHC_PAGESCBS) == 0) 4170 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4171 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4172 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4173 unpause_sequencer(ahc); 4174 } else { 4175 4176 #if 0 4177 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4178 scb->hscb->tag, ahc->qinfifonext, 4179 &ahc->qinfifo[ahc->qinfifonext], 4180 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4181 #endif 4182 4183 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4184 4185 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4186 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4187 4188 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4189 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4190 } else { 4191 pause_sequencer(ahc); 4192 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4193 unpause_sequencer(ahc); 4194 } 4195 } 4196 4197 #ifdef AHC_DEBUG 4198 if (ahc_debug & AHC_SHOWCMDS) { 4199 scsi_print_addr(xs->sc_link); 4200 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4201 " rate %x\n", 4202 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4203 scb->flags, scb->hscb->control, ahc->qinfifonext, 4204 scb->hscb->scsirate); 4205 } 4206 #endif 4207 4208 if (!(xs->xs_control & XS_CTL_POLL)) { 4209 splx(s); 4210 return (SUCCESSFULLY_QUEUED); 4211 } 4212 /* 4213 * If we can't use interrupts, poll for completion 4214 */ 4215 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4216 do { 4217 if (ahc_poll(ahc, xs->timeout)) { 4218 if (!(xs->xs_control & XS_CTL_SILENT)) 4219 printf("cmd fail\n"); 4220 ahc_timeout(scb); 4221 break; 4222 } 4223 } while (!(xs->xs_status & XS_STS_DONE)); 4224 splx(s); 4225 return (COMPLETE); 4226 } 4227 4228 static int 4229 ahc_poll(struct ahc_softc *ahc, int wait) 4230 { 4231 while (--wait) { 4232 DELAY(1000); 4233 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4234 break; 4235 } 4236 4237 if (wait == 0) { 4238 printf("%s: board is not responding\n", ahc_name(ahc)); 4239 return (EIO); 4240 } 4241 4242 ahc_intr((void *)ahc); 4243 return (0); 4244 } 4245 4246 static int 4247 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4248 struct scb *scb) 4249 { 4250 struct hardware_scb *hscb; 4251 4252 hscb = scb->hscb; 4253 xs->resid = xs->status = 0; 4254 4255 hscb->cmdlen = xs->cmdlen; 4256 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4257 hscb->cmdpointer = hscb->cmdstore_busaddr; 4258 4259 /* Only use S/G if there is a transfer */ 4260 if (xs->datalen) { 4261 int error; 4262 4263 error = bus_dmamap_load(ahc->parent_dmat, 4264 scb->dmamap, xs->data, 4265 xs->datalen, NULL, 4266 (xs->xs_control & XS_CTL_NOSLEEP) ? 4267 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 4268 if (error) { 4269 if (!ahc_istagged_device(ahc, xs, 0)) 4270 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4271 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4272 } 4273 error = ahc_execute_scb(scb, 4274 scb->dmamap->dm_segs, 4275 scb->dmamap->dm_nsegs); 4276 return error; 4277 } else { 4278 return ahc_execute_scb(scb, NULL, 0); 4279 } 4280 } 4281 4282 static void 4283 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4284 { 4285 int target; 4286 char channel; 4287 int lun; 4288 4289 target = sc_link->scsipi_scsi.target; 4290 lun = sc_link->scsipi_scsi.lun; 4291 channel = sc_link->scsipi_scsi.channel; 4292 4293 ahc_search_qinfifo(ahc, target, channel, lun, 4294 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4295 SCB_REQUEUE, SEARCH_COMPLETE); 4296 } 4297 4298 static void 4299 ahcallocscbs(struct ahc_softc *ahc) 4300 { 4301 struct scb_data *scb_data; 4302 struct scb *next_scb; 4303 struct sg_map_node *sg_map; 4304 bus_addr_t physaddr; 4305 struct ahc_dma_seg *segs; 4306 int newcount; 4307 int i; 4308 4309 scb_data = ahc->scb_data; 4310 if (scb_data->numscbs >= AHC_SCB_MAX) 4311 /* Can't allocate any more */ 4312 return; 4313 4314 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4315 4316 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4317 4318 if (sg_map == NULL) 4319 return; 4320 4321 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4322 &sg_map->sg_dmamap, 4323 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4324 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4325 "SG space") < 0) { 4326 free(sg_map, M_DEVBUF); 4327 return; 4328 } 4329 4330 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4331 4332 segs = sg_map->sg_vaddr; 4333 physaddr = sg_map->sg_physaddr; 4334 4335 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4336 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4337 int error; 4338 4339 next_scb->sg_list = segs; 4340 /* 4341 * The sequencer always starts with the second entry. 4342 * The first entry is embedded in the scb. 4343 */ 4344 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4345 next_scb->flags = SCB_FREE; 4346 error = bus_dmamap_create(ahc->parent_dmat, 4347 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4348 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4349 &next_scb->dmamap); 4350 if (error != 0) 4351 break; 4352 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4353 next_scb->hscb->tag = ahc->scb_data->numscbs; 4354 next_scb->hscb->cmdstore_busaddr = 4355 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4356 + offsetof(struct hardware_scb, cmdstore); 4357 next_scb->hscb->cmdstore_busaddr = 4358 htole32(next_scb->hscb->cmdstore_busaddr); 4359 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4360 segs += AHC_NSEG; 4361 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4362 next_scb++; 4363 ahc->scb_data->numscbs++; 4364 } 4365 #ifdef AHC_DEBUG 4366 if (ahc_debug & AHC_SHOWSCBALLOC) 4367 printf("%s: allocated %d new SCBs count now %d\n", 4368 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4369 #endif 4370 } 4371 4372 #ifdef AHC_DUMP_SEQ 4373 static void 4374 ahc_dumpseq(struct ahc_softc* ahc) 4375 { 4376 int i; 4377 int max_prog; 4378 4379 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4380 max_prog = 448; 4381 else if ((ahc->features & AHC_ULTRA2) != 0) 4382 max_prog = 768; 4383 else 4384 max_prog = 512; 4385 4386 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4387 ahc_outb(ahc, SEQADDR0, 0); 4388 ahc_outb(ahc, SEQADDR1, 0); 4389 for (i = 0; i < max_prog; i++) { 4390 u_int8_t ins_bytes[4]; 4391 4392 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4393 printf("0x%08x\n", ins_bytes[0] << 24 4394 | ins_bytes[1] << 16 4395 | ins_bytes[2] << 8 4396 | ins_bytes[3]); 4397 } 4398 } 4399 #endif 4400 4401 static void 4402 ahc_loadseq(struct ahc_softc *ahc) 4403 { 4404 struct patch *cur_patch; 4405 int i; 4406 int downloaded; 4407 int skip_addr; 4408 u_int8_t download_consts[4]; 4409 4410 /* Setup downloadable constant table */ 4411 #if 0 4412 /* No downloaded constants are currently defined. */ 4413 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4414 #endif 4415 4416 cur_patch = patches; 4417 downloaded = 0; 4418 skip_addr = 0; 4419 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4420 ahc_outb(ahc, SEQADDR0, 0); 4421 ahc_outb(ahc, SEQADDR1, 0); 4422 4423 for (i = 0; i < sizeof(seqprog)/4; i++) { 4424 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4425 /* 4426 * Don't download this instruction as it 4427 * is in a patch that was removed. 4428 */ 4429 continue; 4430 } 4431 ahc_download_instr(ahc, i, download_consts); 4432 downloaded++; 4433 } 4434 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4435 restart_sequencer(ahc); 4436 4437 #ifdef AHC_DEBUG 4438 printf(" %d instructions downloaded\n", downloaded); 4439 #endif 4440 } 4441 4442 static int 4443 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4444 int start_instr, int *skip_addr) 4445 { 4446 struct patch *cur_patch; 4447 struct patch *last_patch; 4448 int num_patches; 4449 4450 num_patches = sizeof(patches)/sizeof(struct patch); 4451 last_patch = &patches[num_patches]; 4452 cur_patch = *start_patch; 4453 4454 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4455 4456 if (cur_patch->patch_func(ahc) == 0) { 4457 4458 /* Start rejecting code */ 4459 *skip_addr = start_instr + cur_patch->skip_instr; 4460 cur_patch += cur_patch->skip_patch; 4461 } else { 4462 /* Accepted this patch. Advance to the next 4463 * one and wait for our intruction pointer to 4464 * hit this point. 4465 */ 4466 cur_patch++; 4467 } 4468 } 4469 4470 *start_patch = cur_patch; 4471 if (start_instr < *skip_addr) 4472 /* Still skipping */ 4473 return (0); 4474 4475 return (1); 4476 } 4477 4478 static void 4479 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4480 { 4481 union ins_formats instr; 4482 struct ins_format1 *fmt1_ins; 4483 struct ins_format3 *fmt3_ins; 4484 u_int opcode; 4485 4486 /* Structure copy */ 4487 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4488 4489 instr.integer = le32toh(instr.integer); 4490 4491 fmt1_ins = &instr.format1; 4492 fmt3_ins = NULL; 4493 4494 /* Pull the opcode */ 4495 opcode = instr.format1.opcode; 4496 switch (opcode) { 4497 case AIC_OP_JMP: 4498 case AIC_OP_JC: 4499 case AIC_OP_JNC: 4500 case AIC_OP_CALL: 4501 case AIC_OP_JNE: 4502 case AIC_OP_JNZ: 4503 case AIC_OP_JE: 4504 case AIC_OP_JZ: 4505 { 4506 struct patch *cur_patch; 4507 int address_offset; 4508 u_int address; 4509 int skip_addr; 4510 int i; 4511 4512 fmt3_ins = &instr.format3; 4513 address_offset = 0; 4514 address = fmt3_ins->address; 4515 cur_patch = patches; 4516 skip_addr = 0; 4517 4518 for (i = 0; i < address;) { 4519 4520 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4521 4522 if (skip_addr > i) { 4523 int end_addr; 4524 4525 end_addr = MIN(address, skip_addr); 4526 address_offset += end_addr - i; 4527 i = skip_addr; 4528 } else { 4529 i++; 4530 } 4531 } 4532 address -= address_offset; 4533 fmt3_ins->address = address; 4534 /* FALLTHROUGH */ 4535 } 4536 case AIC_OP_OR: 4537 case AIC_OP_AND: 4538 case AIC_OP_XOR: 4539 case AIC_OP_ADD: 4540 case AIC_OP_ADC: 4541 case AIC_OP_BMOV: 4542 if (fmt1_ins->parity != 0) { 4543 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4544 } 4545 fmt1_ins->parity = 0; 4546 /* FALLTHROUGH */ 4547 case AIC_OP_ROL: 4548 if ((ahc->features & AHC_ULTRA2) != 0) { 4549 int i, count; 4550 4551 /* Calculate odd parity for the instruction */ 4552 for (i = 0, count = 0; i < 31; i++) { 4553 u_int32_t mask; 4554 4555 mask = 0x01 << i; 4556 if ((instr.integer & mask) != 0) 4557 count++; 4558 } 4559 if ((count & 0x01) == 0) 4560 instr.format1.parity = 1; 4561 } else { 4562 /* Compress the instruction for older sequencers */ 4563 if (fmt3_ins != NULL) { 4564 instr.integer = 4565 fmt3_ins->immediate 4566 | (fmt3_ins->source << 8) 4567 | (fmt3_ins->address << 16) 4568 | (fmt3_ins->opcode << 25); 4569 } else { 4570 instr.integer = 4571 fmt1_ins->immediate 4572 | (fmt1_ins->source << 8) 4573 | (fmt1_ins->destination << 16) 4574 | (fmt1_ins->ret << 24) 4575 | (fmt1_ins->opcode << 25); 4576 } 4577 } 4578 instr.integer = htole32(instr.integer); 4579 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4580 break; 4581 default: 4582 panic("Unknown opcode encountered in seq program"); 4583 break; 4584 } 4585 } 4586 4587 static void 4588 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4589 { 4590 4591 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4592 struct scb *scbp; 4593 4594 scb->flags |= SCB_RECOVERY_SCB; 4595 4596 /* 4597 * Take all queued, but not sent SCBs out of the equation. 4598 * Also ensure that no new CCBs are queued to us while we 4599 * try to fix this problem. 4600 */ 4601 ahc->queue_blocked = 1; 4602 4603 /* 4604 * Go through all of our pending SCBs and remove 4605 * any scheduled timeouts for them. We will reschedule 4606 * them after we've successfully fixed this problem. 4607 */ 4608 scbp = ahc->pending_ccbs.lh_first; 4609 while (scbp != NULL) { 4610 callout_stop(&scbp->xs->xs_callout); 4611 scbp = scbp->plinks.le_next; 4612 } 4613 } 4614 } 4615 4616 static void 4617 ahc_timeout(void *arg) 4618 { 4619 struct scb *scb; 4620 struct ahc_softc *ahc; 4621 int s, found; 4622 u_int last_phase; 4623 int target; 4624 int lun; 4625 int i; 4626 char channel; 4627 4628 scb = (struct scb *)arg; 4629 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4630 4631 s = splbio(); 4632 4633 /* 4634 * Ensure that the card doesn't do anything 4635 * behind our back. Also make sure that we 4636 * didn't "just" miss an interrupt that would 4637 * affect this timeout. 4638 */ 4639 do { 4640 ahc_intr(ahc); 4641 pause_sequencer(ahc); 4642 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4643 4644 if ((scb->flags & SCB_ACTIVE) == 0) { 4645 /* Previous timeout took care of me already */ 4646 printf("Timedout SCB handled by another timeout\n"); 4647 unpause_sequencer(ahc); 4648 splx(s); 4649 return; 4650 } 4651 4652 target = SCB_TARGET(scb); 4653 channel = SCB_CHANNEL(scb); 4654 lun = SCB_LUN(scb); 4655 4656 scsi_print_addr(scb->xs->sc_link); 4657 printf("SCB %x - timed out ", scb->hscb->tag); 4658 /* 4659 * Take a snapshot of the bus state and print out 4660 * some information so we can track down driver bugs. 4661 */ 4662 last_phase = ahc_inb(ahc, LASTPHASE); 4663 4664 for (i = 0; i < num_phases; i++) { 4665 if (last_phase == phase_table[i].phase) 4666 break; 4667 } 4668 printf("%s", phase_table[i].phasemsg); 4669 4670 printf(", SEQADDR == 0x%x\n", 4671 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4672 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4673 4674 #ifdef AHC_DEBUG 4675 ahc_print_scb(scb); 4676 #endif 4677 4678 #if 0 4679 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4680 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4681 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4682 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4683 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4684 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4685 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4686 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4687 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4688 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4689 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4690 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4691 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4692 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4693 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4694 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4695 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4696 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4697 if (scb->sg_count > 0) { 4698 for (i = 0; i < scb->sg_count; i++) { 4699 printf("sg[%d] - Addr 0x%x : Length %d\n", 4700 i, 4701 le32toh(scb->sg_list[i].addr), 4702 le32toh(scb->sg_list[i].len)); 4703 } 4704 } 4705 #endif 4706 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4707 /* 4708 * Been down this road before. 4709 * Do a full bus reset. 4710 */ 4711 bus_reset: 4712 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4713 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4714 printf("%s: Issued Channel %c Bus Reset. " 4715 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4716 } else { 4717 /* 4718 * If we are a target, transition to bus free and report 4719 * the timeout. 4720 * 4721 * The target/initiator that is holding up the bus may not 4722 * be the same as the one that triggered this timeout 4723 * (different commands have different timeout lengths). 4724 * If the bus is idle and we are actiing as the initiator 4725 * for this request, queue a BDR message to the timed out 4726 * target. Otherwise, if the timed out transaction is 4727 * active: 4728 * Initiator transaction: 4729 * Stuff the message buffer with a BDR message and assert 4730 * ATN in the hopes that the target will let go of the bus 4731 * and go to the mesgout phase. If this fails, we'll 4732 * get another timeout 2 seconds later which will attempt 4733 * a bus reset. 4734 * 4735 * Target transaction: 4736 * Transition to BUS FREE and report the error. 4737 * It's good to be the target! 4738 */ 4739 u_int active_scb_index; 4740 4741 active_scb_index = ahc_inb(ahc, SCB_TAG); 4742 4743 if (last_phase != P_BUSFREE 4744 && (active_scb_index < ahc->scb_data->numscbs)) { 4745 struct scb *active_scb; 4746 4747 /* 4748 * If the active SCB is not from our device, 4749 * assume that another device is hogging the bus 4750 * and wait for it's timeout to expire before 4751 * taking additional action. 4752 */ 4753 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4754 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4755 u_int newtimeout; 4756 4757 scsi_print_addr(scb->xs->sc_link); 4758 printf("Other SCB Timeout%s", 4759 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4760 ? " again\n" : "\n"); 4761 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4762 newtimeout = MAX(active_scb->xs->timeout, 4763 scb->xs->timeout); 4764 callout_reset(&scb->xs->xs_callout, 4765 (newtimeout * hz) / 1000, 4766 ahc_timeout, scb); 4767 splx(s); 4768 return; 4769 } 4770 4771 /* It's us */ 4772 if ((scb->hscb->control & TARGET_SCB) != 0) { 4773 4774 /* 4775 * Send back any queued up transactions 4776 * and properly record the error condition. 4777 */ 4778 ahc_freeze_devq(ahc, scb->xs->sc_link); 4779 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4780 ahc_freeze_ccb(scb); 4781 ahc_done(ahc, scb); 4782 4783 /* Will clear us from the bus */ 4784 restart_sequencer(ahc); 4785 return; 4786 } 4787 4788 ahc_set_recoveryscb(ahc, active_scb); 4789 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4790 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4791 scsi_print_addr(active_scb->xs->sc_link); 4792 printf("BDR message in message buffer\n"); 4793 active_scb->flags |= SCB_DEVICE_RESET; 4794 callout_reset(&active_scb->xs->xs_callout, 4795 2 * hz, ahc_timeout, active_scb); 4796 unpause_sequencer(ahc); 4797 } else { 4798 int disconnected; 4799 4800 /* XXX Shouldn't panic. Just punt instead */ 4801 if ((scb->hscb->control & TARGET_SCB) != 0) 4802 panic("Timed-out target SCB but bus idle"); 4803 4804 if (last_phase != P_BUSFREE 4805 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4806 /* XXX What happened to the SCB? */ 4807 /* Hung target selection. Goto busfree */ 4808 printf("%s: Hung target selection\n", 4809 ahc_name(ahc)); 4810 restart_sequencer(ahc); 4811 return; 4812 } 4813 4814 if (ahc_search_qinfifo(ahc, target, channel, lun, 4815 scb->hscb->tag, ROLE_INITIATOR, 4816 /*status*/0, SEARCH_COUNT) > 0) { 4817 disconnected = FALSE; 4818 } else { 4819 disconnected = TRUE; 4820 } 4821 4822 if (disconnected) { 4823 u_int active_scb; 4824 4825 ahc_set_recoveryscb(ahc, scb); 4826 /* 4827 * Simply set the MK_MESSAGE control bit. 4828 */ 4829 scb->hscb->control |= MK_MESSAGE; 4830 scb->flags |= SCB_QUEUED_MSG 4831 | SCB_DEVICE_RESET; 4832 4833 /* 4834 * Mark the cached copy of this SCB in the 4835 * disconnected list too, so that a reconnect 4836 * at this point causes a BDR or abort. 4837 */ 4838 active_scb = ahc_inb(ahc, SCBPTR); 4839 if (ahc_search_disc_list(ahc, target, 4840 channel, lun, 4841 scb->hscb->tag, 4842 /*stop_on_first*/TRUE, 4843 /*remove*/FALSE, 4844 /*save_state*/FALSE)) { 4845 u_int scb_control; 4846 4847 scb_control = ahc_inb(ahc, SCB_CONTROL); 4848 scb_control |= MK_MESSAGE; 4849 ahc_outb(ahc, SCB_CONTROL, scb_control); 4850 } 4851 ahc_outb(ahc, SCBPTR, active_scb); 4852 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4853 /*unbusy*/TRUE); 4854 4855 /* 4856 * Actually re-queue this SCB in case we can 4857 * select the device before it reconnects. 4858 * Clear out any entries in the QINFIFO first 4859 * so we are the next SCB for this target 4860 * to run. 4861 */ 4862 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4863 channel, SCB_LUN(scb), 4864 SCB_LIST_NULL, 4865 ROLE_INITIATOR, 4866 SCB_REQUEUE, 4867 SEARCH_COMPLETE); 4868 scsi_print_addr(scb->xs->sc_link); 4869 printf("Queuing a BDR SCB\n"); 4870 ahc->qinfifo[ahc->qinfifonext++] = 4871 scb->hscb->tag; 4872 4873 bus_dmamap_sync(ahc->parent_dmat, 4874 ahc->shared_data_dmamap, 4875 QINFIFO_OFFSET * 256, 256, 4876 BUS_DMASYNC_PREWRITE); 4877 4878 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4879 ahc_outb(ahc, HNSCB_QOFF, 4880 ahc->qinfifonext); 4881 } else { 4882 ahc_outb(ahc, KERNEL_QINPOS, 4883 ahc->qinfifonext); 4884 } 4885 callout_reset(&scb->xs->xs_callout, 2 * hz, 4886 ahc_timeout, scb); 4887 unpause_sequencer(ahc); 4888 } else { 4889 /* Go "immediatly" to the bus reset */ 4890 /* This shouldn't happen */ 4891 ahc_set_recoveryscb(ahc, scb); 4892 scsi_print_addr(scb->xs->sc_link); 4893 printf("SCB %x: Immediate reset. " 4894 "Flags = 0x%x\n", scb->hscb->tag, 4895 scb->flags); 4896 goto bus_reset; 4897 } 4898 } 4899 } 4900 splx(s); 4901 } 4902 4903 static int 4904 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4905 int lun, u_int tag, role_t role, scb_flag status, 4906 ahc_search_action action) 4907 { 4908 struct scb *scbp; 4909 u_int8_t qinpos; 4910 u_int8_t qintail; 4911 int found; 4912 4913 qinpos = ahc_inb(ahc, QINPOS); 4914 qintail = ahc->qinfifonext; 4915 found = 0; 4916 4917 /* 4918 * Start with an empty queue. Entries that are not chosen 4919 * for removal will be re-added to the queue as we go. 4920 */ 4921 ahc->qinfifonext = qinpos; 4922 4923 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4924 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4925 4926 while (qinpos != qintail) { 4927 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4928 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4929 /* 4930 * We found an scb that needs to be removed. 4931 */ 4932 switch (action) { 4933 case SEARCH_COMPLETE: 4934 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4935 scbp->flags |= status; 4936 scbp->xs->error = XS_NOERROR; 4937 } 4938 ahc_freeze_ccb(scbp); 4939 ahc_done(ahc, scbp); 4940 break; 4941 case SEARCH_COUNT: 4942 ahc->qinfifo[ahc->qinfifonext++] = 4943 scbp->hscb->tag; 4944 break; 4945 case SEARCH_REMOVE: 4946 break; 4947 } 4948 found++; 4949 } else { 4950 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4951 } 4952 qinpos++; 4953 } 4954 4955 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4956 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4957 4958 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4959 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4960 } else { 4961 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4962 } 4963 4964 return (found); 4965 } 4966 4967 /* 4968 * Abort all SCBs that match the given description (target/channel/lun/tag), 4969 * setting their status to the passed in status if the status has not already 4970 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4971 * is paused before it is called. 4972 */ 4973 static int 4974 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4975 int lun, u_int tag, role_t role, int status) 4976 { 4977 struct scb *scbp; 4978 u_int active_scb; 4979 int i; 4980 int found; 4981 4982 /* restore this when we're done */ 4983 active_scb = ahc_inb(ahc, SCBPTR); 4984 4985 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4986 role, SCB_REQUEUE, SEARCH_COMPLETE); 4987 4988 /* 4989 * Search waiting for selection list. 4990 */ 4991 { 4992 u_int8_t next, prev; 4993 4994 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4995 prev = SCB_LIST_NULL; 4996 4997 while (next != SCB_LIST_NULL) { 4998 u_int8_t scb_index; 4999 5000 ahc_outb(ahc, SCBPTR, next); 5001 scb_index = ahc_inb(ahc, SCB_TAG); 5002 if (scb_index >= ahc->scb_data->numscbs) { 5003 panic("Waiting List inconsistency. " 5004 "SCB index == %d, yet numscbs == %d.", 5005 scb_index, ahc->scb_data->numscbs); 5006 } 5007 scbp = &ahc->scb_data->scbarray[scb_index]; 5008 if (ahc_match_scb(scbp, target, channel, 5009 lun, SCB_LIST_NULL, role)) { 5010 5011 next = ahc_abort_wscb(ahc, next, prev); 5012 } else { 5013 5014 prev = next; 5015 next = ahc_inb(ahc, SCB_NEXT); 5016 } 5017 } 5018 } 5019 /* 5020 * Go through the disconnected list and remove any entries we 5021 * have queued for completion, 0'ing their control byte too. 5022 * We save the active SCB and restore it ourselves, so there 5023 * is no reason for this search to restore it too. 5024 */ 5025 ahc_search_disc_list(ahc, target, channel, lun, tag, 5026 /*stop_on_first*/FALSE, /*remove*/TRUE, 5027 /*save_state*/FALSE); 5028 5029 /* 5030 * Go through the hardware SCB array looking for commands that 5031 * were active but not on any list. 5032 */ 5033 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5034 u_int scbid; 5035 5036 ahc_outb(ahc, SCBPTR, i); 5037 scbid = ahc_inb(ahc, SCB_TAG); 5038 scbp = &ahc->scb_data->scbarray[scbid]; 5039 if (scbid < ahc->scb_data->numscbs 5040 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5041 ahc_add_curscb_to_free_list(ahc); 5042 } 5043 5044 /* 5045 * Go through the pending CCB list and look for 5046 * commands for this target that are still active. 5047 * These are other tagged commands that were 5048 * disconnected when the reset occured. 5049 */ 5050 { 5051 struct scb *scb; 5052 5053 scb = ahc->pending_ccbs.lh_first; 5054 while (scb != NULL) { 5055 scbp = scb; 5056 scb = scb->plinks.le_next; 5057 if (ahc_match_scb(scbp, target, channel, 5058 lun, tag, role)) { 5059 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5060 ahcsetccbstatus(scbp->xs, status); 5061 ahc_freeze_ccb(scbp); 5062 ahc_done(ahc, scbp); 5063 found++; 5064 } 5065 } 5066 } 5067 ahc_outb(ahc, SCBPTR, active_scb); 5068 return found; 5069 } 5070 5071 static int 5072 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5073 int lun, u_int tag, int stop_on_first, int remove, 5074 int save_state) 5075 { 5076 struct scb *scbp; 5077 u_int next; 5078 u_int prev; 5079 u_int count; 5080 u_int active_scb; 5081 5082 count = 0; 5083 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5084 prev = SCB_LIST_NULL; 5085 5086 if (save_state) { 5087 /* restore this when we're done */ 5088 active_scb = ahc_inb(ahc, SCBPTR); 5089 } else 5090 /* Silence compiler */ 5091 active_scb = SCB_LIST_NULL; 5092 5093 while (next != SCB_LIST_NULL) { 5094 u_int scb_index; 5095 5096 ahc_outb(ahc, SCBPTR, next); 5097 scb_index = ahc_inb(ahc, SCB_TAG); 5098 if (scb_index >= ahc->scb_data->numscbs) { 5099 panic("Disconnected List inconsistency. " 5100 "SCB index == %d, yet numscbs == %d.", 5101 scb_index, ahc->scb_data->numscbs); 5102 } 5103 scbp = &ahc->scb_data->scbarray[scb_index]; 5104 if (ahc_match_scb(scbp, target, channel, lun, 5105 tag, ROLE_INITIATOR)) { 5106 count++; 5107 if (remove) { 5108 next = 5109 ahc_rem_scb_from_disc_list(ahc, prev, next); 5110 } else { 5111 prev = next; 5112 next = ahc_inb(ahc, SCB_NEXT); 5113 } 5114 if (stop_on_first) 5115 break; 5116 } else { 5117 prev = next; 5118 next = ahc_inb(ahc, SCB_NEXT); 5119 } 5120 } 5121 if (save_state) 5122 ahc_outb(ahc, SCBPTR, active_scb); 5123 return (count); 5124 } 5125 5126 static u_int 5127 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5128 { 5129 u_int next; 5130 5131 ahc_outb(ahc, SCBPTR, scbptr); 5132 next = ahc_inb(ahc, SCB_NEXT); 5133 5134 ahc_outb(ahc, SCB_CONTROL, 0); 5135 5136 ahc_add_curscb_to_free_list(ahc); 5137 5138 if (prev != SCB_LIST_NULL) { 5139 ahc_outb(ahc, SCBPTR, prev); 5140 ahc_outb(ahc, SCB_NEXT, next); 5141 } else 5142 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5143 5144 return (next); 5145 } 5146 5147 static void 5148 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5149 { 5150 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5151 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5152 5153 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5154 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5155 } 5156 5157 /* 5158 * Manipulate the waiting for selection list and return the 5159 * scb that follows the one that we remove. 5160 */ 5161 static u_int 5162 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5163 { 5164 u_int curscb, next; 5165 5166 /* 5167 * Select the SCB we want to abort and 5168 * pull the next pointer out of it. 5169 */ 5170 curscb = ahc_inb(ahc, SCBPTR); 5171 ahc_outb(ahc, SCBPTR, scbpos); 5172 next = ahc_inb(ahc, SCB_NEXT); 5173 5174 /* Clear the necessary fields */ 5175 ahc_outb(ahc, SCB_CONTROL, 0); 5176 5177 ahc_add_curscb_to_free_list(ahc); 5178 5179 /* update the waiting list */ 5180 if (prev == SCB_LIST_NULL) { 5181 /* First in the list */ 5182 ahc_outb(ahc, WAITING_SCBH, next); 5183 5184 /* 5185 * Ensure we aren't attempting to perform 5186 * selection for this entry. 5187 */ 5188 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5189 } else { 5190 /* 5191 * Select the scb that pointed to us 5192 * and update its next pointer. 5193 */ 5194 ahc_outb(ahc, SCBPTR, prev); 5195 ahc_outb(ahc, SCB_NEXT, next); 5196 } 5197 5198 /* 5199 * Point us back at the original scb position. 5200 */ 5201 ahc_outb(ahc, SCBPTR, curscb); 5202 return next; 5203 } 5204 5205 static void 5206 ahc_clear_intstat(struct ahc_softc *ahc) 5207 { 5208 /* Clear any interrupt conditions this may have caused */ 5209 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5210 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5211 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5212 CLRREQINIT); 5213 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5214 } 5215 5216 static void 5217 ahc_reset_current_bus(struct ahc_softc *ahc) 5218 { 5219 u_int8_t scsiseq; 5220 5221 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5222 scsiseq = ahc_inb(ahc, SCSISEQ); 5223 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5224 DELAY(AHC_BUSRESET_DELAY); 5225 /* Turn off the bus reset */ 5226 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5227 5228 ahc_clear_intstat(ahc); 5229 5230 /* Re-enable reset interrupts */ 5231 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5232 } 5233 5234 static int 5235 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5236 { 5237 u_int initiator, target, max_scsiid; 5238 u_int sblkctl; 5239 u_int our_id; 5240 int found; 5241 int restart_needed; 5242 char cur_channel; 5243 5244 ahc->pending_device = NULL; 5245 5246 pause_sequencer(ahc); 5247 5248 /* 5249 * Run our command complete fifos to ensure that we perform 5250 * completion processing on any commands that 'completed' 5251 * before the reset occurred. 5252 */ 5253 ahc_run_qoutfifo(ahc); 5254 5255 /* 5256 * Reset the bus if we are initiating this reset 5257 */ 5258 sblkctl = ahc_inb(ahc, SBLKCTL); 5259 cur_channel = 'A'; 5260 if ((ahc->features & AHC_TWIN) != 0 5261 && ((sblkctl & SELBUSB) != 0)) 5262 cur_channel = 'B'; 5263 if (cur_channel != channel) { 5264 /* Case 1: Command for another bus is active 5265 * Stealthily reset the other bus without 5266 * upsetting the current bus. 5267 */ 5268 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5269 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5270 ahc_outb(ahc, SCSISEQ, 5271 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5272 if (initiate_reset) 5273 ahc_reset_current_bus(ahc); 5274 ahc_clear_intstat(ahc); 5275 ahc_outb(ahc, SBLKCTL, sblkctl); 5276 restart_needed = FALSE; 5277 } else { 5278 /* Case 2: A command from this bus is active or we're idle */ 5279 ahc_clear_msg_state(ahc); 5280 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5281 ahc_outb(ahc, SCSISEQ, 5282 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5283 if (initiate_reset) 5284 ahc_reset_current_bus(ahc); 5285 ahc_clear_intstat(ahc); 5286 5287 /* 5288 * Since we are going to restart the sequencer, avoid 5289 * a race in the sequencer that could cause corruption 5290 * of our Q pointers by starting over from index 0. 5291 */ 5292 ahc->qoutfifonext = 0; 5293 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5294 ahc_outb(ahc, SDSCB_QOFF, 0); 5295 else 5296 ahc_outb(ahc, QOUTPOS, 0); 5297 restart_needed = TRUE; 5298 } 5299 5300 /* 5301 * Clean up all the state information for the 5302 * pending transactions on this bus. 5303 */ 5304 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5305 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5306 ROLE_UNKNOWN, XS_RESET); 5307 if (channel == 'B') { 5308 our_id = ahc->our_id_b; 5309 } else { 5310 our_id = ahc->our_id; 5311 } 5312 5313 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5314 5315 /* 5316 * Revert to async/narrow transfers until we renegotiate. 5317 */ 5318 for (target = 0; target <= max_scsiid; target++) { 5319 5320 if (ahc->enabled_targets[target] == NULL) 5321 continue; 5322 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5323 struct ahc_devinfo devinfo; 5324 5325 ahc_compile_devinfo(&devinfo, target, initiator, 5326 AHC_LUN_WILDCARD, 5327 channel, ROLE_UNKNOWN); 5328 ahc_set_width(ahc, &devinfo, 5329 MSG_EXT_WDTR_BUS_8_BIT, 5330 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5331 ahc_set_syncrate(ahc, &devinfo, 5332 /*syncrate*/NULL, /*period*/0, 5333 /*offset*/0, AHC_TRANS_CUR, 5334 /*paused*/TRUE, FALSE); 5335 } 5336 } 5337 5338 if (restart_needed) 5339 restart_sequencer(ahc); 5340 else 5341 unpause_sequencer(ahc); 5342 return found; 5343 } 5344 5345 static int 5346 ahc_match_scb(struct scb *scb, int target, char channel, 5347 int lun, u_int tag, role_t role) 5348 { 5349 int targ = SCB_TARGET(scb); 5350 char chan = SCB_CHANNEL(scb); 5351 int slun = SCB_LUN(scb); 5352 int match; 5353 5354 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5355 if (match != 0) 5356 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5357 if (match != 0) 5358 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5359 5360 return match; 5361 } 5362 5363 static void 5364 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5365 { 5366 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5367 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5368 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5369 ahc->msgout_buf[ahc->msgout_index++] = period; 5370 ahc->msgout_buf[ahc->msgout_index++] = offset; 5371 ahc->msgout_len += 5; 5372 } 5373 5374 static void 5375 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5376 { 5377 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5378 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5379 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5380 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5381 ahc->msgout_len += 4; 5382 } 5383 5384 static void 5385 ahc_calc_residual(struct scb *scb) 5386 { 5387 struct hardware_scb *hscb; 5388 5389 hscb = scb->hscb; 5390 5391 /* 5392 * If the disconnected flag is still set, this is bogus 5393 * residual information left over from a sequencer 5394 * pagin/pageout, so ignore this case. 5395 */ 5396 if ((scb->hscb->control & DISCONNECTED) == 0) { 5397 u_int32_t resid; 5398 int resid_sgs; 5399 int sg; 5400 5401 /* 5402 * Remainder of the SG where the transfer 5403 * stopped. 5404 */ 5405 resid = (hscb->residual_data_count[2] << 16) 5406 | (hscb->residual_data_count[1] <<8) 5407 | (hscb->residual_data_count[0]); 5408 5409 /* 5410 * Add up the contents of all residual 5411 * SG segments that are after the SG where 5412 * the transfer stopped. 5413 */ 5414 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5415 sg = scb->sg_count - resid_sgs; 5416 while (resid_sgs > 0) { 5417 5418 resid += le32toh(scb->sg_list[sg].len); 5419 sg++; 5420 resid_sgs--; 5421 } 5422 scb->xs->resid = resid; 5423 } 5424 5425 /* 5426 * Clean out the residual information in this SCB for its 5427 * next consumer. 5428 */ 5429 hscb->residual_SG_count = 0; 5430 5431 #ifdef AHC_DEBUG 5432 if (ahc_debug & AHC_SHOWMISC) { 5433 scsi_print_addr(scb->xs->sc_link); 5434 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5435 } 5436 #endif 5437 } 5438 5439 static void 5440 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5441 { 5442 struct scb *scb; 5443 int pending_ccb_count; 5444 int i; 5445 u_int saved_scbptr; 5446 5447 /* 5448 * Traverse the pending SCB list and ensure that all of the 5449 * SCBs there have the proper settings. 5450 */ 5451 scb = LIST_FIRST(&ahc->pending_ccbs); 5452 pending_ccb_count = 0; 5453 while (scb != NULL) { 5454 struct ahc_devinfo devinfo; 5455 struct scsipi_xfer *xs; 5456 struct scb *pending_scb; 5457 struct hardware_scb *pending_hscb; 5458 struct ahc_initiator_tinfo *tinfo; 5459 struct tmode_tstate *tstate; 5460 u_int our_id, remote_id; 5461 5462 xs = scb->xs; 5463 pending_scb = scb; 5464 pending_hscb = pending_scb->hscb; 5465 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5466 ? ahc->our_id_b : ahc->our_id; 5467 remote_id = xs->sc_link->scsipi_scsi.target; 5468 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5469 SCB_LUN(pending_scb), 5470 SCB_CHANNEL(pending_scb), 5471 ROLE_UNKNOWN); 5472 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5473 our_id, remote_id, &tstate); 5474 pending_hscb->control &= ~ULTRAENB; 5475 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5476 pending_hscb->control |= ULTRAENB; 5477 pending_hscb->scsirate = tinfo->scsirate; 5478 pending_hscb->scsioffset = tinfo->current.offset; 5479 pending_ccb_count++; 5480 scb = LIST_NEXT(scb, plinks); 5481 } 5482 5483 if (pending_ccb_count == 0) 5484 return; 5485 5486 saved_scbptr = ahc_inb(ahc, SCBPTR); 5487 /* Ensure that the hscbs down on the card match the new information */ 5488 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5489 u_int scb_tag; 5490 5491 ahc_outb(ahc, SCBPTR, i); 5492 scb_tag = ahc_inb(ahc, SCB_TAG); 5493 if (scb_tag != SCB_LIST_NULL) { 5494 struct ahc_devinfo devinfo; 5495 struct scb *pending_scb; 5496 struct scsipi_xfer *xs; 5497 struct hardware_scb *pending_hscb; 5498 struct ahc_initiator_tinfo *tinfo; 5499 struct tmode_tstate *tstate; 5500 u_int our_id, remote_id; 5501 u_int control; 5502 5503 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5504 if (pending_scb->flags == SCB_FREE) 5505 continue; 5506 pending_hscb = pending_scb->hscb; 5507 xs = pending_scb->xs; 5508 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5509 ? ahc->our_id_b : ahc->our_id; 5510 remote_id = xs->sc_link->scsipi_scsi.target; 5511 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5512 SCB_LUN(pending_scb), 5513 SCB_CHANNEL(pending_scb), 5514 ROLE_UNKNOWN); 5515 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5516 our_id, remote_id, &tstate); 5517 control = ahc_inb(ahc, SCB_CONTROL); 5518 control &= ~ULTRAENB; 5519 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5520 control |= ULTRAENB; 5521 ahc_outb(ahc, SCB_CONTROL, control); 5522 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5523 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5524 } 5525 } 5526 ahc_outb(ahc, SCBPTR, saved_scbptr); 5527 } 5528 5529 #if UNUSED 5530 static void 5531 ahc_dump_targcmd(struct target_cmd *cmd) 5532 { 5533 u_int8_t *byte; 5534 u_int8_t *last_byte; 5535 int i; 5536 5537 byte = &cmd->initiator_channel; 5538 /* Debugging info for received commands */ 5539 last_byte = &cmd[1].initiator_channel; 5540 5541 i = 0; 5542 while (byte < last_byte) { 5543 if (i == 0) 5544 printf("\t"); 5545 printf("%#x", *byte++); 5546 i++; 5547 if (i == 8) { 5548 printf("\n"); 5549 i = 0; 5550 } else { 5551 printf(", "); 5552 } 5553 } 5554 } 5555 #endif 5556 5557 static void 5558 ahc_shutdown(void *arg) 5559 { 5560 struct ahc_softc *ahc; 5561 int i; 5562 u_int sxfrctl1_a, sxfrctl1_b; 5563 5564 ahc = (struct ahc_softc *)arg; 5565 5566 pause_sequencer(ahc); 5567 5568 /* 5569 * Preserve the value of the SXFRCTL1 register for all channels. 5570 * It contains settings that affect termination and we don't want 5571 * to disturb the integrity of the bus during shutdown in case 5572 * we are in a multi-initiator setup. 5573 */ 5574 sxfrctl1_b = 0; 5575 if ((ahc->features & AHC_TWIN) != 0) { 5576 u_int sblkctl; 5577 5578 sblkctl = ahc_inb(ahc, SBLKCTL); 5579 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5580 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5581 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5582 } 5583 5584 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5585 5586 /* This will reset most registers to 0, but not all */ 5587 ahc_reset(ahc); 5588 5589 if ((ahc->features & AHC_TWIN) != 0) { 5590 u_int sblkctl; 5591 5592 sblkctl = ahc_inb(ahc, SBLKCTL); 5593 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5594 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5595 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5596 } 5597 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5598 5599 ahc_outb(ahc, SCSISEQ, 0); 5600 ahc_outb(ahc, SXFRCTL0, 0); 5601 ahc_outb(ahc, DSPCISTATUS, 0); 5602 5603 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5604 ahc_outb(ahc, i, 0); 5605 } 5606 5607 #if defined(AHC_DEBUG) && 0 5608 static void 5609 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5610 { 5611 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5612 5613 printf("\tcurrent:\n"); 5614 printf("\t\twidth %u period %u offset %u flags %x\n", 5615 tinfo->current.width, tinfo->current.period, 5616 tinfo->current.offset, tinfo->current.ppr_flags); 5617 5618 printf("\tgoal:\n"); 5619 printf("\t\twidth %u period %u offset %u flags %x\n", 5620 tinfo->goal.width, tinfo->goal.period, 5621 tinfo->goal.offset, tinfo->goal.ppr_flags); 5622 5623 printf("\tuser:\n"); 5624 printf("\t\twidth %u period %u offset %u flags %x\n", 5625 tinfo->user.width, tinfo->user.period, 5626 tinfo->user.offset, tinfo->user.ppr_flags); 5627 } 5628 #endif 5629 5630 #ifndef AHC_NO_TAGS 5631 static void 5632 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5633 { 5634 struct scsipi_inquiry_data *inq; 5635 struct ahc_devinfo devinfo; 5636 struct tmode_tstate *tstate; 5637 int target_id, our_id; 5638 char channel; 5639 5640 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5641 return; 5642 5643 if (xs->sc_link->quirks & SDEV_NOTAG) 5644 return; 5645 5646 target_id = xs->sc_link->scsipi_scsi.target; 5647 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5648 channel = SIM_CHANNEL(ahc, xs->sc_link); 5649 5650 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5651 ahc_compile_devinfo(&devinfo, our_id, target_id, 5652 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5653 5654 if (tstate->tagdisable & devinfo.target_mask) 5655 return; 5656 5657 /* 5658 * Sneak a look at the results of the SCSI Inquiry 5659 * command and see if we can do Tagged queing. This 5660 * should really be done by the higher level drivers. 5661 */ 5662 inq = (struct scsipi_inquiry_data *)xs->data; 5663 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5664 printf("%s: target %d using tagged queuing\n", 5665 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5666 5667 ahc_set_tags(ahc, &devinfo, TRUE); 5668 5669 if (ahc->scb_data->maxhscbs >= 16 || 5670 (ahc->flags & AHC_PAGESCBS)) { 5671 /* Default to 16 tags */ 5672 xs->sc_link->openings = 16; 5673 } else { 5674 /* 5675 * Default to 4 tags on whimpy 5676 * cards that don't have much SCB 5677 * space and can't page. This prevents 5678 * a single device from hogging all 5679 * slots. We should really have a better 5680 * way of providing fairness. 5681 */ 5682 xs->sc_link->openings = 4; 5683 } 5684 } 5685 } 5686 #endif 5687 5688 static int 5689 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5690 int nocmdcheck) 5691 { 5692 #ifdef AHC_NO_TAGS 5693 return 0; 5694 #else 5695 char channel; 5696 u_int our_id, target; 5697 struct tmode_tstate *tstate; 5698 struct ahc_devinfo devinfo; 5699 5700 if (xs->sc_link->quirks & SDEV_NOTAG) 5701 return 0; 5702 5703 /* 5704 * XXX never do these commands with tags. Should really be 5705 * in a higher layer. 5706 */ 5707 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5708 xs->cmd->opcode == TEST_UNIT_READY || 5709 xs->cmd->opcode == REQUEST_SENSE)) 5710 return 0; 5711 5712 channel = SIM_CHANNEL(ahc, xs->sc_link); 5713 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5714 target = xs->sc_link->scsipi_scsi.target; 5715 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5716 5717 ahc_compile_devinfo(&devinfo, our_id, target, 5718 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5719 5720 return (tstate->tagenable & devinfo.target_mask); 5721 #endif 5722 } 5723
Indexes created Thu Oct 02 01:09:59 GMT 2025