aic7xxx.c revision 1.67
1 /* $NetBSD: aic7xxx.c,v 1.67 2001/03/07 23:07:13 thorpej Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 #include "opt_ahc.h" 91 92 #include <sys/param.h> 93 #include <sys/kernel.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/malloc.h> 97 #include <sys/buf.h> 98 #include <sys/proc.h> 99 #include <sys/scsiio.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <uvm/uvm_extern.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define ALL_CHANNELS '\0' 118 #define ALL_TARGETS_MASK 0xFFFF 119 #define INITIATOR_WILDCARD (~0) 120 121 #define SIM_IS_SCSIBUS_B(ahc, sc_link) \ 122 ((sc_link)->scsipi_scsi.scsibus == (ahc)->sc_link_b.scsipi_scsi.scsibus) 123 #define SIM_CHANNEL(ahc, sc_link) \ 124 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? 'B' : 'A') 125 #define SIM_SCSI_ID(ahc, sc_link) \ 126 (SIM_IS_SCSIBUS_B(ahc, sc_link) ? ahc->our_id_b : ahc->our_id) 127 #define SCB_IS_SCSIBUS_B(scb) \ 128 (((scb)->hscb->tcl & SELBUSB) != 0) 129 #define SCB_TARGET(scb) \ 130 (((scb)->hscb->tcl & TID) >> 4) 131 #define SCB_CHANNEL(scb) \ 132 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 133 #define SCB_LUN(scb) \ 134 ((scb)->hscb->tcl & LID) 135 #define SCB_TARGET_OFFSET(scb) \ 136 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 137 #define SCB_TARGET_MASK(scb) \ 138 (0x01 << (SCB_TARGET_OFFSET(scb))) 139 #define TCL_CHANNEL(ahc, tcl) \ 140 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 141 #define TCL_SCSI_ID(ahc, tcl) \ 142 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 143 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 144 #define TCL_LUN(tcl) ((tcl) & LID) 145 146 #define XS_TCL(ahc, xs) \ 147 ((((xs)->sc_link->scsipi_scsi.target << 4) & 0xF0) \ 148 | (SIM_IS_SCSIBUS_B((ahc), (xs)->sc_link) ? SELBUSB : 0) \ 149 | ((xs)->sc_link->scsipi_scsi.lun & 0x07)) 150 151 const char * const ahc_chip_names[] = 152 { 153 "NONE", 154 "aic7770", 155 "aic7850", 156 "aic7855", 157 "aic7859", 158 "aic7860", 159 "aic7870", 160 "aic7880", 161 "aic7890/91", 162 "aic7892", 163 "aic7895", 164 "aic7896/97", 165 "aic7899" 166 }; 167 168 typedef enum { 169 ROLE_UNKNOWN, 170 ROLE_INITIATOR, 171 ROLE_TARGET 172 } role_t; 173 174 struct ahc_devinfo { 175 int our_scsiid; 176 int target_offset; 177 u_int16_t target_mask; 178 u_int8_t target; 179 u_int8_t lun; 180 char channel; 181 role_t role; /* 182 * Only guaranteed to be correct if not 183 * in the busfree state. 184 */ 185 }; 186 187 typedef enum { 188 SEARCH_COMPLETE, 189 SEARCH_COUNT, 190 SEARCH_REMOVE 191 } ahc_search_action; 192 193 #ifdef AHC_DEBUG 194 static int ahc_debug = AHC_DEBUG; 195 #endif 196 197 static int ahcinitscbdata(struct ahc_softc *); 198 static void ahcfiniscbdata(struct ahc_softc *); 199 200 #if UNUSED 201 static void ahc_dump_targcmd(struct target_cmd *); 202 #endif 203 static void ahc_shutdown(void *arg); 204 static int32_t ahc_action(struct scsipi_xfer *); 205 static int ahc_ioctl(struct scsipi_link *, u_long, caddr_t, int, 206 struct proc *); 207 static int ahc_execute_scb(void *, bus_dma_segment_t *, int); 208 static int ahc_poll(struct ahc_softc *, int); 209 static int ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 210 struct scb *); 211 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_link *); 212 static void ahcallocscbs(struct ahc_softc *); 213 #if UNUSED 214 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 215 struct scb *); 216 #endif 217 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 218 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 219 char, role_t); 220 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 221 static void ahc_done(struct ahc_softc *, struct scb *); 222 static struct tmode_tstate * 223 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 224 #if UNUSED 225 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 226 #endif 227 static void ahc_handle_seqint(struct ahc_softc *, u_int); 228 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 229 static void ahc_build_transfer_msg(struct ahc_softc *, 230 struct ahc_devinfo *); 231 static void ahc_setup_initiator_msgout(struct ahc_softc *, 232 struct ahc_devinfo *, 233 struct scb *); 234 static void ahc_setup_target_msgin(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_clear_msg_state(struct ahc_softc *); 237 static void ahc_handle_message_phase(struct ahc_softc *, 238 struct scsipi_link *); 239 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 240 241 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_link *, 242 struct ahc_devinfo *); 243 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 244 struct ahc_devinfo *); 245 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 246 int, char *, int); 247 #ifdef AHC_DUMP_SEQ 248 static void ahc_dumpseq(struct ahc_softc *); 249 #endif 250 static void ahc_loadseq(struct ahc_softc *); 251 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 252 int, int *); 253 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 254 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 255 #if defined(AHC_DEBUG) 256 static void ahc_print_scb(struct scb *); 257 #endif 258 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 259 role_t, scb_flag, ahc_search_action); 260 static int ahc_reset_channel(struct ahc_softc *, char, int); 261 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 262 role_t, int); 263 static int ahc_search_disc_list(struct ahc_softc *, int, 264 char, int, u_int, int, int, int); 265 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 266 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 267 static void ahc_clear_intstat(struct ahc_softc *); 268 static void ahc_reset_current_bus(struct ahc_softc *); 269 static const struct ahc_syncrate * 270 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 271 static const struct ahc_syncrate * 272 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 273 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 274 static void ahc_validate_offset(struct ahc_softc *, 275 const struct ahc_syncrate *, u_int *, int); 276 static void ahc_update_target_msg_request(struct ahc_softc *, 277 struct ahc_devinfo *, 278 struct ahc_initiator_tinfo *, 279 int, int); 280 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 281 const struct ahc_syncrate *, u_int, u_int, 282 u_int, int, int); 283 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 284 u_int, u_int, int, int); 285 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, 286 int); 287 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 288 289 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 290 291 static void ahc_calc_residual(struct scb *); 292 293 static void ahc_update_pending_syncrates(struct ahc_softc *); 294 295 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 296 297 static void ahc_timeout (void *); 298 static __inline int sequencer_paused(struct ahc_softc *); 299 static __inline void pause_sequencer(struct ahc_softc *); 300 static __inline void unpause_sequencer(struct ahc_softc *); 301 static void restart_sequencer(struct ahc_softc *); 302 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 303 304 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 305 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 306 307 static __inline void ahc_freeze_ccb(struct scb *); 308 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 309 static void ahc_run_qoutfifo(struct ahc_softc *); 310 311 static __inline struct ahc_initiator_tinfo * 312 ahc_fetch_transinfo(struct ahc_softc *, 313 char, u_int, u_int, 314 struct tmode_tstate **); 315 static void ahcfreescb(struct ahc_softc *, struct scb *); 316 static __inline struct scb *ahcgetscb(struct ahc_softc *); 317 318 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 319 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 320 int *, const char *, const char *); 321 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 322 caddr_t, bus_dma_segment_t *, int); 323 static void ahcminphys(struct buf *); 324 325 static __inline struct scsipi_xfer *ahc_first_xs(struct ahc_softc *); 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 #ifndef AHC_NO_TAGS 329 static void ahc_check_tags(struct ahc_softc *, struct scsipi_xfer *); 330 #endif 331 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 332 333 #if defined(AHC_DEBUG) && 0 334 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 335 #endif 336 337 static struct scsipi_device ahc_dev = 338 { 339 NULL, /* Use default error handler */ 340 NULL, /* have a queue, served by this */ 341 NULL, /* have no async handler */ 342 NULL, /* Use default 'done' routine */ 343 }; 344 345 /* 346 * Pick the first xs for a non-blocked target. 347 */ 348 static __inline struct scsipi_xfer * 349 ahc_first_xs(struct ahc_softc *ahc) 350 { 351 int target; 352 struct scsipi_xfer *xs = TAILQ_FIRST(&ahc->sc_q); 353 354 if (ahc->queue_blocked) 355 return NULL; 356 357 while (xs != NULL) { 358 target = xs->sc_link->scsipi_scsi.target; 359 if (ahc->devqueue_blocked[target] == 0 && 360 (ahc_istagged_device(ahc, xs, 0) || 361 ahc_index_busy_tcl(ahc, XS_TCL(ahc, xs), FALSE) == 362 SCB_LIST_NULL)) 363 break; 364 xs = TAILQ_NEXT(xs, adapter_q); 365 } 366 367 return xs; 368 } 369 370 static __inline void 371 ahc_swap_hscb(struct hardware_scb *hscb) 372 { 373 hscb->SG_pointer = htole32(hscb->SG_pointer); 374 hscb->data = htole32(hscb->data); 375 hscb->datalen = htole32(hscb->datalen); 376 /* 377 * No need to swap cmdpointer; it's either 0 or set to 378 * cmdstore_busaddr, which is already swapped. 379 */ 380 } 381 382 static __inline void 383 ahc_swap_sg(struct ahc_dma_seg *sg) 384 { 385 sg->addr = htole32(sg->addr); 386 sg->len = htole32(sg->len); 387 } 388 389 static void 390 ahcminphys(bp) 391 struct buf *bp; 392 { 393 /* 394 * Even though the card can transfer up to 16megs per command 395 * we are limited by the number of segments in the dma segment 396 * list that we can hold. The worst case is that all pages are 397 * discontinuous physically, hense the "page per segment" limit 398 * enforced here. 399 */ 400 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 401 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 402 } 403 minphys(bp); 404 } 405 406 407 static __inline u_int32_t 408 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 409 { 410 return (ahc->scb_data->hscb_busaddr 411 + (sizeof(struct hardware_scb) * index)); 412 } 413 414 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 415 416 static __inline int 417 sequencer_paused(struct ahc_softc *ahc) 418 { 419 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 420 } 421 422 static __inline void 423 pause_sequencer(struct ahc_softc *ahc) 424 { 425 ahc_outb(ahc, HCNTRL, ahc->pause); 426 427 /* 428 * Since the sequencer can disable pausing in a critical section, we 429 * must loop until it actually stops. 430 */ 431 while (sequencer_paused(ahc) == 0) 432 ; 433 } 434 435 static __inline void 436 unpause_sequencer(struct ahc_softc *ahc) 437 { 438 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 439 ahc_outb(ahc, HCNTRL, ahc->unpause); 440 } 441 442 /* 443 * Restart the sequencer program from address zero 444 */ 445 static void 446 restart_sequencer(struct ahc_softc *ahc) 447 { 448 u_int i; 449 450 pause_sequencer(ahc); 451 452 /* 453 * Everytime we restart the sequencer, there 454 * is the possiblitity that we have restarted 455 * within a three instruction window where an 456 * SCB has been marked free but has not made it 457 * onto the free list. Since SCSI events(bus reset, 458 * unexpected bus free) will always freeze the 459 * sequencer, we cannot close this window. To 460 * avoid losing an SCB, we reconsitute the free 461 * list every time we restart the sequencer. 462 */ 463 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 464 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 465 466 ahc_outb(ahc, SCBPTR, i); 467 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 468 ahc_add_curscb_to_free_list(ahc); 469 } 470 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 471 unpause_sequencer(ahc); 472 } 473 474 static __inline u_int 475 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 476 { 477 u_int scbid; 478 479 scbid = ahc->untagged_scbs[tcl]; 480 if (unbusy) { 481 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 482 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 483 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 484 } 485 486 return (scbid); 487 } 488 489 static __inline void 490 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 491 { 492 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 493 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 494 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 495 } 496 497 static __inline int 498 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 499 { 500 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 501 } 502 503 static __inline void 504 ahc_freeze_ccb(struct scb *scb) 505 { 506 struct scsipi_xfer *xs = scb->xs; 507 struct ahc_softc *ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 508 int target; 509 510 target = xs->sc_link->scsipi_scsi.target; 511 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 512 ahc->devqueue_blocked[target]++; 513 scb->flags |= SCB_FREEZE_QUEUE; 514 } 515 } 516 517 static __inline void 518 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 519 { 520 xs->error = status; 521 } 522 523 static __inline struct ahc_initiator_tinfo * 524 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 525 u_int remote_id, struct tmode_tstate **tstate) 526 { 527 /* 528 * Transfer data structures are stored from the perspective 529 * of the target role. Since the parameters for a connection 530 * in the initiator role to a given target are the same as 531 * when the roles are reversed, we pretend we are the target. 532 */ 533 if (channel == 'B') 534 our_id += 8; 535 *tstate = ahc->enabled_targets[our_id]; 536 return (&(*tstate)->transinfo[remote_id]); 537 } 538 539 static void 540 ahc_run_qoutfifo(struct ahc_softc *ahc) 541 { 542 struct scb *scb; 543 u_int scb_index; 544 545 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 546 256, BUS_DMASYNC_POSTREAD); 547 548 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 549 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 550 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 551 552 scb = &ahc->scb_data->scbarray[scb_index]; 553 if (scb_index >= ahc->scb_data->numscbs 554 || (scb->flags & SCB_ACTIVE) == 0) { 555 printf("%s: WARNING no command for scb %d " 556 "(cmdcmplt)\nQOUTPOS = %d\n", 557 ahc_name(ahc), scb_index, 558 ahc->qoutfifonext - 1); 559 continue; 560 } 561 562 /* 563 * Save off the residual 564 * if there is one. 565 */ 566 if (scb->hscb->residual_SG_count != 0) 567 ahc_calc_residual(scb); 568 else 569 scb->xs->resid = 0; 570 #ifdef AHC_DEBUG 571 if (ahc_debug & AHC_SHOWSCBS) { 572 scsi_print_addr(scb->xs->sc_link); 573 printf("run_qoutfifo: SCB %x complete\n", 574 scb->hscb->tag); 575 } 576 #endif 577 ahc_done(ahc, scb); 578 } 579 } 580 581 582 /* 583 * An scb (and hence an scb entry on the board) is put onto the 584 * free list. 585 */ 586 static void 587 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 588 { 589 struct hardware_scb *hscb; 590 int opri; 591 592 hscb = scb->hscb; 593 594 #ifdef AHC_DEBUG 595 if (ahc_debug & AHC_SHOWSCBALLOC) 596 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 597 #endif 598 599 opri = splbio(); 600 601 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 602 (scb->flags & SCB_RECOVERY_SCB) != 0) { 603 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 604 ahc->queue_blocked = 0; 605 } 606 607 /* Clean up for the next user */ 608 scb->flags = SCB_FREE; 609 hscb->control = 0; 610 hscb->status = 0; 611 612 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 613 614 splx(opri); 615 } 616 617 /* 618 * Get a free scb, either one already assigned to a hardware slot 619 * on the adapter or one that will require an SCB to be paged out before 620 * use. If there are none, see if we can allocate a new SCB. Otherwise 621 * either return an error or sleep. 622 */ 623 static __inline struct scb * 624 ahcgetscb(struct ahc_softc *ahc) 625 { 626 struct scb *scbp; 627 int opri;; 628 629 opri = splbio(); 630 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 631 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 632 } else { 633 ahcallocscbs(ahc); 634 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 635 if (scbp != NULL) 636 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 637 } 638 639 splx(opri); 640 641 #ifdef AHC_DEBUG 642 if (ahc_debug & AHC_SHOWSCBALLOC) { 643 if (scbp != NULL) 644 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 645 scbp->hscb->tag); 646 else 647 printf("%s: failed to allocate new SCB\n", 648 ahc_name(ahc)); 649 } 650 #endif 651 652 return (scbp); 653 } 654 655 static int 656 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 657 bus_dma_tag_t tag; 658 int size; 659 int flags; 660 bus_dmamap_t *mapp; 661 caddr_t *vaddr; 662 bus_addr_t *baddr; 663 bus_dma_segment_t *seg; 664 int *nseg; 665 const char *myname, *what; 666 { 667 int error, level = 0; 668 669 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 670 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 671 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 672 myname, what, error); 673 goto out; 674 } 675 level++; 676 677 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 678 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 679 printf("%s: failed to map DMA mem for %s, error = %d\n", 680 myname, what, error); 681 goto out; 682 } 683 level++; 684 685 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 686 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 687 printf("%s: failed to create DMA map for %s, error = %d\n", 688 myname, what, error); 689 goto out; 690 } 691 level++; 692 693 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 694 BUS_DMA_NOWAIT)) != 0) { 695 printf("%s: failed to load DMA map for %s, error = %d\n", 696 myname, what, error); 697 goto out; 698 } 699 700 *baddr = (*mapp)->dm_segs[0].ds_addr; 701 702 #ifdef AHC_DEBUG 703 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 704 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 705 *nseg, size); 706 #endif 707 708 return 0; 709 out: 710 switch (level) { 711 case 3: 712 bus_dmamap_destroy(tag, *mapp); 713 /* FALLTHROUGH */ 714 case 2: 715 bus_dmamem_unmap(tag, *vaddr, size); 716 /* FALLTHROUGH */ 717 case 1: 718 bus_dmamem_free(tag, seg, *nseg); 719 break; 720 default: 721 break; 722 } 723 724 return error; 725 } 726 727 static void 728 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 729 bus_dma_tag_t tag; 730 int size; 731 bus_dmamap_t map; 732 caddr_t vaddr; 733 bus_dma_segment_t *seg; 734 int nseg; 735 { 736 737 bus_dmamap_unload(tag, map); 738 bus_dmamap_destroy(tag, map); 739 bus_dmamem_unmap(tag, vaddr, size); 740 bus_dmamem_free(tag, seg, nseg); 741 } 742 743 char * 744 ahc_name(struct ahc_softc *ahc) 745 { 746 return (ahc->sc_dev.dv_xname); 747 } 748 749 #ifdef AHC_DEBUG 750 static void 751 ahc_print_scb(struct scb *scb) 752 { 753 struct hardware_scb *hscb = scb->hscb; 754 755 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 756 scb, 757 hscb->tag, 758 hscb->control, 759 hscb->tcl, 760 hscb->cmdlen, 761 (unsigned long)le32toh(hscb->cmdpointer)); 762 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 763 le32toh(hscb->datalen), 764 (unsigned long)(le32toh(hscb->data)), 765 hscb->SG_count, 766 (unsigned long)(le32toh(hscb->SG_pointer))); 767 printf(" sg_addr:%lx sg_len:%lu\n", 768 (unsigned long)(le32toh(scb->sg_list[0].addr)), 769 (unsigned long)(le32toh(scb->sg_list[0].len))); 770 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 771 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 772 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 773 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 774 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 775 } 776 #endif 777 778 static const struct { 779 u_int8_t errno; 780 const char *errmesg; 781 } hard_error[] = { 782 { ILLHADDR, "Illegal Host Access" }, 783 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 784 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 785 { SQPARERR, "Sequencer Parity Error" }, 786 { DPARERR, "Data-path Parity Error" }, 787 { MPARERR, "Scratch or SCB Memory Parity Error" }, 788 { PCIERRSTAT, "PCI Error detected" }, 789 { CIOPARERR, "CIOBUS Parity Error" }, 790 }; 791 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 792 793 static const struct { 794 u_int8_t phase; 795 u_int8_t mesg_out; /* Message response to parity errors */ 796 const char *phasemsg; 797 } phase_table[] = { 798 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 799 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 800 { P_COMMAND, MSG_NOOP, "in Command phase" }, 801 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 802 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 803 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 804 { P_BUSFREE, MSG_NOOP, "while idle" }, 805 { 0, MSG_NOOP, "in unknown phase" } 806 }; 807 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 808 809 /* 810 * Valid SCSIRATE values. (p. 3-17) 811 * Provides a mapping of tranfer periods in ns to the proper value to 812 * stick in the scsiscfr reg to use that transfer rate. 813 */ 814 #define AHC_SYNCRATE_DT 0 815 #define AHC_SYNCRATE_ULTRA2 1 816 #define AHC_SYNCRATE_ULTRA 3 817 #define AHC_SYNCRATE_FAST 6 818 static const struct ahc_syncrate ahc_syncrates[] = { 819 /* ultra2 fast/ultra period rate */ 820 { 0x42, 0x000, 9, "80.0" }, 821 { 0x03, 0x000, 10, "40.0" }, 822 { 0x04, 0x000, 11, "33.0" }, 823 { 0x05, 0x100, 12, "20.0" }, 824 { 0x06, 0x110, 15, "16.0" }, 825 { 0x07, 0x120, 18, "13.4" }, 826 { 0x08, 0x000, 25, "10.0" }, 827 { 0x19, 0x010, 31, "8.0" }, 828 { 0x1a, 0x020, 37, "6.67" }, 829 { 0x1b, 0x030, 43, "5.7" }, 830 { 0x1c, 0x040, 50, "5.0" }, 831 { 0x00, 0x050, 56, "4.4" }, 832 { 0x00, 0x060, 62, "4.0" }, 833 { 0x00, 0x070, 68, "3.6" }, 834 { 0x00, 0x000, 0, NULL } 835 }; 836 837 /* 838 * Allocate a controller structure for a new device and initialize it. 839 */ 840 int 841 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 842 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 843 ahc_flag flags) 844 { 845 struct scb_data *scb_data; 846 847 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 848 if (scb_data == NULL) { 849 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 850 return -1; 851 } 852 bzero(scb_data, sizeof (struct scb_data)); 853 LIST_INIT(&ahc->pending_ccbs); 854 ahc->tag = st; 855 ahc->bsh = sh; 856 ahc->parent_dmat = parent_dmat; 857 ahc->chip = chip; 858 ahc->features = features; 859 ahc->flags = flags; 860 ahc->scb_data = scb_data; 861 862 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 863 /* The IRQMS bit is only valid on VL and EISA chips */ 864 if ((ahc->chip & AHC_PCI) != 0) 865 ahc->unpause &= ~IRQMS; 866 ahc->pause = ahc->unpause | PAUSE; 867 return (0); 868 } 869 870 void 871 ahc_free(ahc) 872 struct ahc_softc *ahc; 873 { 874 ahcfiniscbdata(ahc); 875 if (ahc->init_level != 0) 876 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 877 ahc->shared_data_dmamap, ahc->qoutfifo, 878 &ahc->shared_data_seg, ahc->shared_data_nseg); 879 880 if (ahc->scb_data != NULL) 881 free(ahc->scb_data, M_DEVBUF); 882 if (ahc->bus_data != NULL) 883 free(ahc->bus_data, M_DEVBUF); 884 return; 885 } 886 887 static int 888 ahcinitscbdata(struct ahc_softc *ahc) 889 { 890 struct scb_data *scb_data; 891 int i; 892 893 scb_data = ahc->scb_data; 894 SLIST_INIT(&scb_data->free_scbs); 895 SLIST_INIT(&scb_data->sg_maps); 896 897 /* Allocate SCB resources */ 898 scb_data->scbarray = 899 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 900 M_DEVBUF, M_NOWAIT); 901 if (scb_data->scbarray == NULL) 902 return (ENOMEM); 903 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 904 905 /* Determine the number of hardware SCBs and initialize them */ 906 907 scb_data->maxhscbs = ahc_probe_scbs(ahc); 908 /* SCB 0 heads the free list */ 909 ahc_outb(ahc, FREE_SCBH, 0); 910 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 911 ahc_outb(ahc, SCBPTR, i); 912 913 /* Clear the control byte. */ 914 ahc_outb(ahc, SCB_CONTROL, 0); 915 916 /* Set the next pointer */ 917 ahc_outb(ahc, SCB_NEXT, i+1); 918 919 /* Make the tag number invalid */ 920 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 921 } 922 923 /* Make sure that the last SCB terminates the free list */ 924 ahc_outb(ahc, SCBPTR, i-1); 925 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 926 927 /* Ensure we clear the 0 SCB's control byte. */ 928 ahc_outb(ahc, SCBPTR, 0); 929 ahc_outb(ahc, SCB_CONTROL, 0); 930 931 scb_data->maxhscbs = i; 932 933 if (ahc->scb_data->maxhscbs == 0) 934 panic("%s: No SCB space found", ahc_name(ahc)); 935 936 /* 937 * Create our DMA tags. These tags define the kinds of device 938 * accessable memory allocations and memory mappings we will 939 * need to perform during normal operation. 940 * 941 * Unless we need to further restrict the allocation, we rely 942 * on the restrictions of the parent dmat, hence the common 943 * use of MAXADDR and MAXSIZE. 944 */ 945 946 if (ahc_createdmamem(ahc->parent_dmat, 947 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 948 &scb_data->hscb_dmamap, 949 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 950 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 951 "hardware SCB structures") < 0) 952 goto error_exit; 953 954 scb_data->init_level++; 955 956 if (ahc_createdmamem(ahc->parent_dmat, 957 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 958 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 959 &scb_data->sense_busaddr, &scb_data->sense_seg, 960 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 961 goto error_exit; 962 963 scb_data->init_level++; 964 965 /* Perform initial CCB allocation */ 966 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 967 ahcallocscbs(ahc); 968 969 if (scb_data->numscbs == 0) { 970 printf("%s: ahc_init_scb_data - " 971 "Unable to allocate initial scbs\n", 972 ahc_name(ahc)); 973 goto error_exit; 974 } 975 976 scb_data->init_level++; 977 978 /* 979 * Note that we were successfull 980 */ 981 return 0; 982 983 error_exit: 984 985 return ENOMEM; 986 } 987 988 static void 989 ahcfiniscbdata(struct ahc_softc *ahc) 990 { 991 struct scb_data *scb_data; 992 993 scb_data = ahc->scb_data; 994 995 switch (scb_data->init_level) { 996 default: 997 case 3: 998 { 999 struct sg_map_node *sg_map; 1000 1001 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 1002 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 1003 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 1004 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 1005 &sg_map->sg_dmasegs, sg_map->sg_nseg); 1006 free(sg_map, M_DEVBUF); 1007 } 1008 } 1009 /*FALLTHROUGH*/ 1010 case 2: 1011 ahc_freedmamem(ahc->parent_dmat, 1012 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 1013 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 1014 &scb_data->sense_seg, scb_data->sense_nseg); 1015 /*FALLTHROUGH*/ 1016 case 1: 1017 ahc_freedmamem(ahc->parent_dmat, 1018 AHC_SCB_MAX * sizeof(struct hardware_scb), 1019 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 1020 &scb_data->hscb_seg, scb_data->hscb_nseg); 1021 /*FALLTHROUGH*/ 1022 } 1023 if (scb_data->scbarray != NULL) 1024 free(scb_data->scbarray, M_DEVBUF); 1025 } 1026 1027 int 1028 ahc_reset(struct ahc_softc *ahc) 1029 { 1030 u_int sblkctl; 1031 int wait; 1032 1033 #ifdef AHC_DUMP_SEQ 1034 if (ahc->init_level == 0) 1035 ahc_dumpseq(ahc); 1036 #endif 1037 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1038 /* 1039 * Ensure that the reset has finished 1040 */ 1041 wait = 1000; 1042 do { 1043 DELAY(1000); 1044 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1045 1046 if (wait == 0) { 1047 printf("%s: WARNING - Failed chip reset! " 1048 "Trying to initialize anyway.\n", ahc_name(ahc)); 1049 } 1050 ahc_outb(ahc, HCNTRL, ahc->pause); 1051 1052 /* Determine channel configuration */ 1053 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1054 /* No Twin Channel PCI cards */ 1055 if ((ahc->chip & AHC_PCI) != 0) 1056 sblkctl &= ~SELBUSB; 1057 switch (sblkctl) { 1058 case 0: 1059 /* Single Narrow Channel */ 1060 break; 1061 case 2: 1062 /* Wide Channel */ 1063 ahc->features |= AHC_WIDE; 1064 break; 1065 case 8: 1066 /* Twin Channel */ 1067 ahc->features |= AHC_TWIN; 1068 break; 1069 default: 1070 printf(" Unsupported adapter type. Ignoring\n"); 1071 return(-1); 1072 } 1073 1074 return (0); 1075 } 1076 1077 /* 1078 * Called when we have an active connection to a target on the bus, 1079 * this function finds the nearest syncrate to the input period limited 1080 * by the capabilities of the bus connectivity of the target. 1081 */ 1082 static const struct ahc_syncrate * 1083 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1084 u_int maxsync; 1085 1086 if ((ahc->features & AHC_ULTRA2) != 0) { 1087 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1088 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1089 maxsync = AHC_SYNCRATE_ULTRA2; 1090 } else { 1091 maxsync = AHC_SYNCRATE_ULTRA; 1092 } 1093 } else if ((ahc->features & AHC_ULTRA) != 0) { 1094 maxsync = AHC_SYNCRATE_ULTRA; 1095 } else { 1096 maxsync = AHC_SYNCRATE_FAST; 1097 } 1098 return (ahc_find_syncrate(ahc, period, maxsync)); 1099 } 1100 1101 /* 1102 * Look up the valid period to SCSIRATE conversion in our table. 1103 * Return the period and offset that should be sent to the target 1104 * if this was the beginning of an SDTR. 1105 */ 1106 static const struct ahc_syncrate * 1107 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1108 { 1109 const struct ahc_syncrate *syncrate; 1110 1111 syncrate = &ahc_syncrates[maxsync]; 1112 while ((syncrate->rate != NULL) 1113 && ((ahc->features & AHC_ULTRA2) == 0 1114 || (syncrate->sxfr_u2 != 0))) { 1115 1116 if (*period <= syncrate->period) { 1117 /* 1118 * When responding to a target that requests 1119 * sync, the requested rate may fall between 1120 * two rates that we can output, but still be 1121 * a rate that we can receive. Because of this, 1122 * we want to respond to the target with 1123 * the same rate that it sent to us even 1124 * if the period we use to send data to it 1125 * is lower. Only lower the response period 1126 * if we must. 1127 */ 1128 if (syncrate == &ahc_syncrates[maxsync]) 1129 *period = syncrate->period; 1130 break; 1131 } 1132 syncrate++; 1133 } 1134 1135 if ((*period == 0) 1136 || (syncrate->rate == NULL) 1137 || ((ahc->features & AHC_ULTRA2) != 0 1138 && (syncrate->sxfr_u2 == 0))) { 1139 /* Use asynchronous transfers. */ 1140 *period = 0; 1141 syncrate = NULL; 1142 } 1143 return (syncrate); 1144 } 1145 1146 static u_int 1147 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1148 { 1149 const struct ahc_syncrate *syncrate; 1150 1151 if ((ahc->features & AHC_ULTRA2) != 0) 1152 scsirate &= SXFR_ULTRA2; 1153 else 1154 scsirate &= SXFR; 1155 1156 syncrate = &ahc_syncrates[maxsync]; 1157 while (syncrate->rate != NULL) { 1158 1159 if ((ahc->features & AHC_ULTRA2) != 0) { 1160 if (syncrate->sxfr_u2 == 0) 1161 break; 1162 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1163 return (syncrate->period); 1164 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1165 return (syncrate->period); 1166 } 1167 syncrate++; 1168 } 1169 return (0); /* async */ 1170 } 1171 1172 static void 1173 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1174 u_int *offset, int wide) 1175 { 1176 u_int maxoffset; 1177 1178 /* Limit offset to what we can do */ 1179 if (syncrate == NULL) { 1180 maxoffset = 0; 1181 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1182 maxoffset = MAX_OFFSET_ULTRA2; 1183 } else { 1184 if (wide) 1185 maxoffset = MAX_OFFSET_16BIT; 1186 else 1187 maxoffset = MAX_OFFSET_8BIT; 1188 } 1189 *offset = MIN(*offset, maxoffset); 1190 } 1191 1192 static void 1193 ahc_update_target_msg_request(struct ahc_softc *ahc, 1194 struct ahc_devinfo *devinfo, 1195 struct ahc_initiator_tinfo *tinfo, 1196 int force, int paused) 1197 { 1198 u_int targ_msg_req_orig; 1199 1200 targ_msg_req_orig = ahc->targ_msg_req; 1201 if (tinfo->current.period != tinfo->goal.period 1202 || tinfo->current.width != tinfo->goal.width 1203 || tinfo->current.offset != tinfo->goal.offset 1204 || (force 1205 && (tinfo->goal.period != 0 1206 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1207 ahc->targ_msg_req |= devinfo->target_mask; 1208 } else { 1209 ahc->targ_msg_req &= ~devinfo->target_mask; 1210 } 1211 1212 if (ahc->targ_msg_req != targ_msg_req_orig) { 1213 /* Update the message request bit for this target */ 1214 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1215 if (paused) { 1216 ahc_outb(ahc, TARGET_MSG_REQUEST, 1217 ahc->targ_msg_req & 0xFF); 1218 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1219 (ahc->targ_msg_req >> 8) & 0xFF); 1220 } else { 1221 ahc_outb(ahc, HS_MAILBOX, 1222 0x01 << HOST_MAILBOX_SHIFT); 1223 } 1224 } else { 1225 if (!paused) 1226 pause_sequencer(ahc); 1227 1228 ahc_outb(ahc, TARGET_MSG_REQUEST, 1229 ahc->targ_msg_req & 0xFF); 1230 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1231 (ahc->targ_msg_req >> 8) & 0xFF); 1232 1233 if (!paused) 1234 unpause_sequencer(ahc); 1235 } 1236 } 1237 } 1238 1239 static void 1240 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1241 const struct ahc_syncrate *syncrate, 1242 u_int period, u_int offset, u_int type, int paused, int done) 1243 { 1244 struct ahc_initiator_tinfo *tinfo; 1245 struct tmode_tstate *tstate; 1246 u_int old_period; 1247 u_int old_offset; 1248 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1249 1250 if (syncrate == NULL) { 1251 period = 0; 1252 offset = 0; 1253 } 1254 1255 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1256 devinfo->target, &tstate); 1257 old_period = tinfo->current.period; 1258 old_offset = tinfo->current.offset; 1259 1260 if ((type & AHC_TRANS_CUR) != 0 1261 && (old_period != period || old_offset != offset)) { 1262 u_int scsirate; 1263 1264 scsirate = tinfo->scsirate; 1265 if ((ahc->features & AHC_ULTRA2) != 0) { 1266 1267 /* XXX */ 1268 /* Force single edge until DT is fully implemented */ 1269 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1270 if (syncrate != NULL) 1271 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1272 1273 if (active) 1274 ahc_outb(ahc, SCSIOFFSET, offset); 1275 } else { 1276 1277 scsirate &= ~(SXFR|SOFS); 1278 /* 1279 * Ensure Ultra mode is set properly for 1280 * this target. 1281 */ 1282 tstate->ultraenb &= ~devinfo->target_mask; 1283 if (syncrate != NULL) { 1284 if (syncrate->sxfr & ULTRA_SXFR) { 1285 tstate->ultraenb |= 1286 devinfo->target_mask; 1287 } 1288 scsirate |= syncrate->sxfr & SXFR; 1289 scsirate |= offset & SOFS; 1290 } 1291 if (active) { 1292 u_int sxfrctl0; 1293 1294 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1295 sxfrctl0 &= ~FAST20; 1296 if (tstate->ultraenb & devinfo->target_mask) 1297 sxfrctl0 |= FAST20; 1298 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1299 } 1300 } 1301 if (active) 1302 ahc_outb(ahc, SCSIRATE, scsirate); 1303 1304 tinfo->scsirate = scsirate; 1305 tinfo->current.period = period; 1306 tinfo->current.offset = offset; 1307 1308 /* Update the syncrates in any pending scbs */ 1309 ahc_update_pending_syncrates(ahc); 1310 } 1311 1312 /* 1313 * Print messages if we're verbose and at the end of a negotiation 1314 * cycle. 1315 */ 1316 if (done) { 1317 if (offset != 0) { 1318 printf("%s: target %d synchronous at %sMHz, " 1319 "offset = 0x%x\n", ahc_name(ahc), 1320 devinfo->target, syncrate->rate, offset); 1321 } else { 1322 printf("%s: target %d using " 1323 "asynchronous transfers\n", 1324 ahc_name(ahc), devinfo->target); 1325 } 1326 } 1327 1328 if ((type & AHC_TRANS_GOAL) != 0) { 1329 tinfo->goal.period = period; 1330 tinfo->goal.offset = offset; 1331 } 1332 1333 if ((type & AHC_TRANS_USER) != 0) { 1334 tinfo->user.period = period; 1335 tinfo->user.offset = offset; 1336 } 1337 1338 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1339 /*force*/FALSE, 1340 paused); 1341 } 1342 1343 static void 1344 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1345 u_int width, u_int type, int paused, int done) 1346 { 1347 struct ahc_initiator_tinfo *tinfo; 1348 struct tmode_tstate *tstate; 1349 u_int oldwidth; 1350 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1351 1352 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1353 devinfo->target, &tstate); 1354 oldwidth = tinfo->current.width; 1355 1356 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1357 u_int scsirate; 1358 1359 scsirate = tinfo->scsirate; 1360 scsirate &= ~WIDEXFER; 1361 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1362 scsirate |= WIDEXFER; 1363 1364 tinfo->scsirate = scsirate; 1365 1366 if (active) 1367 ahc_outb(ahc, SCSIRATE, scsirate); 1368 1369 tinfo->current.width = width; 1370 } 1371 1372 if (done) { 1373 printf("%s: target %d using %dbit transfers\n", 1374 ahc_name(ahc), devinfo->target, 1375 8 * (0x01 << width)); 1376 } 1377 1378 if ((type & AHC_TRANS_GOAL) != 0) 1379 tinfo->goal.width = width; 1380 if ((type & AHC_TRANS_USER) != 0) 1381 tinfo->user.width = width; 1382 1383 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1384 /*force*/FALSE, paused); 1385 } 1386 1387 static void 1388 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1389 { 1390 struct ahc_initiator_tinfo *tinfo; 1391 struct tmode_tstate *tstate; 1392 1393 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1394 devinfo->target, &tstate); 1395 1396 if (enable) 1397 tstate->tagenable |= devinfo->target_mask; 1398 else { 1399 tstate->tagenable &= ~devinfo->target_mask; 1400 tstate->tagdisable |= devinfo->target_mask; 1401 } 1402 } 1403 1404 /* 1405 * Attach all the sub-devices we can find 1406 */ 1407 int 1408 ahc_attach(struct ahc_softc *ahc) 1409 { 1410 TAILQ_INIT(&ahc->sc_q); 1411 1412 ahc->sc_adapter.scsipi_cmd = ahc_action; 1413 ahc->sc_adapter.scsipi_minphys = ahcminphys; 1414 ahc->sc_adapter.scsipi_ioctl = ahc_ioctl; 1415 ahc->sc_link.type = BUS_SCSI; 1416 ahc->sc_link.scsipi_scsi.adapter_target = ahc->our_id; 1417 ahc->sc_link.scsipi_scsi.channel = 0; 1418 ahc->sc_link.scsipi_scsi.max_target = 1419 (ahc->features & AHC_WIDE) ? 15 : 7; 1420 ahc->sc_link.scsipi_scsi.max_lun = 7; 1421 ahc->sc_link.adapter_softc = ahc; 1422 ahc->sc_link.adapter = &ahc->sc_adapter; 1423 ahc->sc_link.openings = 2; 1424 ahc->sc_link.device = &ahc_dev; 1425 1426 if (ahc->features & AHC_TWIN) { 1427 ahc->sc_link_b = ahc->sc_link; 1428 ahc->sc_link_b.scsipi_scsi.adapter_target = ahc->our_id_b; 1429 ahc->sc_link_b.scsipi_scsi.channel = 1; 1430 } 1431 1432 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1433 ahc->sc_link_b.scsipi_scsi.scsibus = 0xff; 1434 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1435 if (ahc->features & AHC_TWIN) 1436 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1437 } else { 1438 config_found((void *)ahc, &ahc->sc_link_b, scsiprint); 1439 config_found((void *)ahc, &ahc->sc_link, scsiprint); 1440 } 1441 return 1; 1442 } 1443 1444 static void 1445 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1446 { 1447 u_int saved_tcl; 1448 role_t role; 1449 int our_id; 1450 1451 if (ahc_inb(ahc, SSTAT0) & TARGET) 1452 role = ROLE_TARGET; 1453 else 1454 role = ROLE_INITIATOR; 1455 1456 if (role == ROLE_TARGET 1457 && (ahc->features & AHC_MULTI_TID) != 0 1458 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1459 /* We were selected, so pull our id from TARGIDIN */ 1460 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1461 } else if ((ahc->features & AHC_ULTRA2) != 0) 1462 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1463 else 1464 our_id = ahc_inb(ahc, SCSIID) & OID; 1465 1466 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1467 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1468 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1469 role); 1470 } 1471 1472 static void 1473 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1474 u_int lun, char channel, role_t role) 1475 { 1476 devinfo->our_scsiid = our_id; 1477 devinfo->target = target; 1478 devinfo->lun = lun; 1479 devinfo->target_offset = target; 1480 devinfo->channel = channel; 1481 devinfo->role = role; 1482 if (channel == 'B') 1483 devinfo->target_offset += 8; 1484 devinfo->target_mask = (0x01 << devinfo->target_offset); 1485 } 1486 1487 /* 1488 * Catch an interrupt from the adapter 1489 */ 1490 int 1491 ahc_intr(void *arg) 1492 { 1493 struct ahc_softc *ahc; 1494 u_int intstat; 1495 1496 ahc = (struct ahc_softc *)arg; 1497 1498 intstat = ahc_inb(ahc, INTSTAT); 1499 1500 /* 1501 * Any interrupts to process? 1502 */ 1503 if ((intstat & INT_PEND) == 0) { 1504 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1505 #ifdef AHC_DEBUG 1506 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1507 ahc_name(ahc), 1508 ahc_inb(ahc, CCHADDR) | 1509 (ahc_inb(ahc, CCHADDR+1) << 8) 1510 | (ahc_inb(ahc, CCHADDR+2) << 16) 1511 | (ahc_inb(ahc, CCHADDR+3) << 24), 1512 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1513 | (ahc_inb(ahc, HADDR+2) << 16) 1514 | (ahc_inb(ahc, HADDR+3) << 24), 1515 ahc_inb(ahc, SEQADDR0) | 1516 (ahc_inb(ahc, SEQADDR1) << 8)); 1517 #endif 1518 return 1; 1519 } 1520 return 0; 1521 } 1522 1523 #ifdef AHC_DEBUG 1524 if (ahc_debug & AHC_SHOWINTR) { 1525 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1526 } 1527 #endif 1528 1529 if (intstat & CMDCMPLT) { 1530 ahc_outb(ahc, CLRINT, CLRCMDINT); 1531 ahc_run_qoutfifo(ahc); 1532 } 1533 if (intstat & BRKADRINT) { 1534 /* 1535 * We upset the sequencer :-( 1536 * Lookup the error message 1537 */ 1538 int i, error, num_errors; 1539 1540 error = ahc_inb(ahc, ERROR); 1541 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1542 for (i = 0; error != 1 && i < num_errors; i++) 1543 error >>= 1; 1544 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1545 ahc_name(ahc), hard_error[i].errmesg, 1546 ahc_inb(ahc, SEQADDR0) | 1547 (ahc_inb(ahc, SEQADDR1) << 8)); 1548 1549 /* Tell everyone that this HBA is no longer availible */ 1550 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1551 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1552 XS_DRIVER_STUFFUP); 1553 } 1554 if (intstat & SEQINT) 1555 ahc_handle_seqint(ahc, intstat); 1556 1557 if (intstat & SCSIINT) 1558 ahc_handle_scsiint(ahc, intstat); 1559 1560 return 1; 1561 } 1562 1563 static struct tmode_tstate * 1564 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1565 { 1566 struct tmode_tstate *master_tstate; 1567 struct tmode_tstate *tstate; 1568 int i, s; 1569 1570 master_tstate = ahc->enabled_targets[ahc->our_id]; 1571 if (channel == 'B') { 1572 scsi_id += 8; 1573 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1574 } 1575 if (ahc->enabled_targets[scsi_id] != NULL 1576 && ahc->enabled_targets[scsi_id] != master_tstate) 1577 panic("%s: ahc_alloc_tstate - Target already allocated", 1578 ahc_name(ahc)); 1579 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1580 if (tstate == NULL) 1581 return (NULL); 1582 1583 /* 1584 * If we have allocated a master tstate, copy user settings from 1585 * the master tstate (taken from SRAM or the EEPROM) for this 1586 * channel, but reset our current and goal settings to async/narrow 1587 * until an initiator talks to us. 1588 */ 1589 if (master_tstate != NULL) { 1590 bcopy(master_tstate, tstate, sizeof(*tstate)); 1591 tstate->ultraenb = 0; 1592 for (i = 0; i < 16; i++) { 1593 bzero(&tstate->transinfo[i].current, 1594 sizeof(tstate->transinfo[i].current)); 1595 bzero(&tstate->transinfo[i].goal, 1596 sizeof(tstate->transinfo[i].goal)); 1597 } 1598 } else 1599 bzero(tstate, sizeof(*tstate)); 1600 s = splbio(); 1601 ahc->enabled_targets[scsi_id] = tstate; 1602 splx(s); 1603 return (tstate); 1604 } 1605 1606 #if UNUSED 1607 static void 1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1609 { 1610 struct tmode_tstate *tstate; 1611 1612 /* Don't clean up the entry for our initiator role */ 1613 if ((ahc->flags & AHC_INITIATORMODE) != 0 1614 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1615 || (channel == 'A' && scsi_id == ahc->our_id)) 1616 && force == FALSE) 1617 return; 1618 1619 if (channel == 'B') 1620 scsi_id += 8; 1621 tstate = ahc->enabled_targets[scsi_id]; 1622 if (tstate != NULL) 1623 free(tstate, M_DEVBUF); 1624 ahc->enabled_targets[scsi_id] = NULL; 1625 } 1626 #endif 1627 1628 static void 1629 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1630 { 1631 struct scb *scb; 1632 struct ahc_devinfo devinfo; 1633 1634 ahc_fetch_devinfo(ahc, &devinfo); 1635 1636 /* 1637 * Clear the upper byte that holds SEQINT status 1638 * codes and clear the SEQINT bit. We will unpause 1639 * the sequencer, if appropriate, after servicing 1640 * the request. 1641 */ 1642 ahc_outb(ahc, CLRINT, CLRSEQINT); 1643 switch (intstat & SEQINT_MASK) { 1644 case NO_MATCH: 1645 { 1646 /* Ensure we don't leave the selection hardware on */ 1647 ahc_outb(ahc, SCSISEQ, 1648 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1649 1650 printf("%s:%c:%d: no active SCB for reconnecting " 1651 "target - issuing BUS DEVICE RESET\n", 1652 ahc_name(ahc), devinfo.channel, devinfo.target); 1653 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1654 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1655 ahc_inb(ahc, SEQ_FLAGS)); 1656 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1657 ahc->msgout_len = 1; 1658 ahc->msgout_index = 0; 1659 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1660 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1661 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1662 break; 1663 } 1664 case UPDATE_TMSG_REQ: 1665 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1666 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1667 (ahc->targ_msg_req >> 8) & 0xFF); 1668 ahc_outb(ahc, HS_MAILBOX, 0); 1669 break; 1670 case SEND_REJECT: 1671 { 1672 u_int rejbyte = ahc_inb(ahc, ACCUM); 1673 printf("%s:%c:%d: Warning - unknown message received from " 1674 "target (0x%x). Rejecting\n", 1675 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1676 break; 1677 } 1678 case NO_IDENT: 1679 { 1680 /* 1681 * The reconnecting target either did not send an identify 1682 * message, or did, but we didn't find and SCB to match and 1683 * before it could respond to our ATN/abort, it hit a dataphase. 1684 * The only safe thing to do is to blow it away with a bus 1685 * reset. 1686 */ 1687 int found; 1688 1689 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1690 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1691 ahc_name(ahc), devinfo.channel, devinfo.target, 1692 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1693 found = ahc_reset_channel(ahc, devinfo.channel, 1694 /*initiate reset*/TRUE); 1695 printf("%s: Issued Channel %c Bus Reset. " 1696 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1697 found); 1698 return; 1699 } 1700 case BAD_PHASE: 1701 { 1702 u_int lastphase; 1703 1704 lastphase = ahc_inb(ahc, LASTPHASE); 1705 if (lastphase == P_BUSFREE) { 1706 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1707 ahc_name(ahc), devinfo.channel, devinfo.target, 1708 ahc_inb(ahc, SCSISIGI)); 1709 restart_sequencer(ahc); 1710 return; 1711 } else { 1712 printf("%s:%c:%d: unknown scsi bus phase %x. " 1713 "Attempting to continue\n", 1714 ahc_name(ahc), devinfo.channel, devinfo.target, 1715 ahc_inb(ahc, SCSISIGI)); 1716 } 1717 break; 1718 } 1719 case BAD_STATUS: 1720 { 1721 u_int scb_index; 1722 struct hardware_scb *hscb; 1723 struct scsipi_xfer *xs; 1724 /* 1725 * The sequencer will notify us when a command 1726 * has an error that would be of interest to 1727 * the kernel. This allows us to leave the sequencer 1728 * running in the common case of command completes 1729 * without error. The sequencer will already have 1730 * dma'd the SCB back up to us, so we can reference 1731 * the in kernel copy directly. 1732 */ 1733 scb_index = ahc_inb(ahc, SCB_TAG); 1734 scb = &ahc->scb_data->scbarray[scb_index]; 1735 1736 /* ahc_print_scb(scb); */ 1737 1738 /* 1739 * Set the default return value to 0 (don't 1740 * send sense). The sense code will change 1741 * this if needed. 1742 */ 1743 ahc_outb(ahc, RETURN_1, 0); 1744 if (!(scb_index < ahc->scb_data->numscbs 1745 && (scb->flags & SCB_ACTIVE) != 0)) { 1746 printf("%s:%c:%d: ahc_intr - referenced scb " 1747 "not valid during seqint 0x%x scb(%d)\n", 1748 ahc_name(ahc), devinfo.channel, 1749 devinfo.target, intstat, scb_index); 1750 goto unpause; 1751 } 1752 1753 hscb = scb->hscb; 1754 xs = scb->xs; 1755 1756 /* Don't want to clobber the original sense code */ 1757 if ((scb->flags & SCB_SENSE) != 0) { 1758 /* 1759 * Clear the SCB_SENSE Flag and have 1760 * the sequencer do a normal command 1761 * complete. 1762 */ 1763 scb->flags &= ~SCB_SENSE; 1764 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1765 break; 1766 } 1767 /* Freeze the queue unit the client sees the error. */ 1768 ahc_freeze_devq(ahc, xs->sc_link); 1769 ahc_freeze_ccb(scb); 1770 xs->status = hscb->status; 1771 switch (hscb->status) { 1772 case SCSI_STATUS_OK: 1773 printf("%s: Interrupted for status of 0???\n", 1774 ahc_name(ahc)); 1775 break; 1776 case SCSI_STATUS_CMD_TERMINATED: 1777 case SCSI_STATUS_CHECK_COND: 1778 #if defined(AHC_DEBUG) 1779 if (ahc_debug & AHC_SHOWSENSE) { 1780 scsi_print_addr(xs->sc_link); 1781 printf("Check Status, resid %d datalen %d\n", 1782 xs->resid, xs->datalen); 1783 } 1784 #endif 1785 1786 if (xs->error == XS_NOERROR && 1787 !(scb->flags & SCB_SENSE)) { 1788 struct ahc_dma_seg *sg; 1789 struct scsipi_sense *sc; 1790 struct ahc_initiator_tinfo *tinfo; 1791 struct tmode_tstate *tstate; 1792 1793 sg = scb->sg_list; 1794 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1795 /* 1796 * Save off the residual if there is one. 1797 */ 1798 if (hscb->residual_SG_count != 0) 1799 ahc_calc_residual(scb); 1800 else 1801 xs->resid = 0; 1802 1803 #ifdef AHC_DEBUG 1804 if (ahc_debug & AHC_SHOWSENSE) { 1805 scsi_print_addr(xs->sc_link); 1806 printf("Sending Sense\n"); 1807 } 1808 #endif 1809 sg->addr = ahc->scb_data->sense_busaddr + 1810 (hscb->tag*sizeof(struct scsipi_sense_data)); 1811 sg->len = sizeof (struct scsipi_sense_data); 1812 1813 sc->opcode = REQUEST_SENSE; 1814 sc->byte2 = SCB_LUN(scb) << 5; 1815 sc->unused[0] = 0; 1816 sc->unused[1] = 0; 1817 sc->length = sg->len; 1818 sc->control = 0; 1819 1820 /* 1821 * Would be nice to preserve DISCENB here, 1822 * but due to the way we page SCBs, we can't. 1823 */ 1824 hscb->control = 0; 1825 1826 /* 1827 * This request sense could be because the 1828 * the device lost power or in some other 1829 * way has lost our transfer negotiations. 1830 * Renegotiate if appropriate. Unit attention 1831 * errors will be reported before any data 1832 * phases occur. 1833 */ 1834 ahc_calc_residual(scb); 1835 #if defined(AHC_DEBUG) 1836 if (ahc_debug & AHC_SHOWSENSE) { 1837 scsi_print_addr(xs->sc_link); 1838 printf("Sense: datalen %d resid %d" 1839 "chan %d id %d targ %d\n", 1840 xs->datalen, xs->resid, 1841 devinfo.channel, devinfo.our_scsiid, 1842 devinfo.target); 1843 } 1844 #endif 1845 if (xs->datalen > 0 && 1846 xs->resid == xs->datalen) { 1847 tinfo = ahc_fetch_transinfo(ahc, 1848 devinfo.channel, 1849 devinfo.our_scsiid, 1850 devinfo.target, 1851 &tstate); 1852 ahc_update_target_msg_request(ahc, 1853 &devinfo, 1854 tinfo, 1855 /*force*/TRUE, 1856 /*paused*/TRUE); 1857 } 1858 hscb->status = 0; 1859 hscb->SG_count = 1; 1860 hscb->SG_pointer = scb->sg_list_phys; 1861 hscb->data = sg->addr; 1862 hscb->datalen = sg->len; 1863 hscb->cmdpointer = hscb->cmdstore_busaddr; 1864 hscb->cmdlen = sizeof(*sc); 1865 scb->sg_count = hscb->SG_count; 1866 ahc_swap_hscb(hscb); 1867 ahc_swap_sg(scb->sg_list); 1868 scb->flags |= SCB_SENSE; 1869 /* 1870 * Ensure the target is busy since this 1871 * will be an untagged request. 1872 */ 1873 ahc_busy_tcl(ahc, scb); 1874 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1875 1876 /* 1877 * Ensure we have enough time to actually 1878 * retrieve the sense. 1879 */ 1880 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1881 callout_reset(&scb->xs->xs_callout, 1882 5 * hz, ahc_timeout, scb); 1883 } 1884 } 1885 break; 1886 case SCSI_STATUS_QUEUE_FULL: 1887 scsi_print_addr(xs->sc_link); 1888 printf("queue full\n"); 1889 case SCSI_STATUS_BUSY: 1890 /* 1891 * XXX middle layer doesn't handle XS_BUSY well. 1892 * So, requeue this ourselves internally. 1893 */ 1894 xs->error = XS_BUSY; 1895 scb->flags |= SCB_REQUEUE; 1896 break; 1897 } 1898 break; 1899 } 1900 case TRACE_POINT: 1901 { 1902 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1903 ahc_inb(ahc, DFCNTRL)); 1904 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1905 ahc_inb(ahc, DFSTATUS)); 1906 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1907 ahc_inb(ahc, SSTAT0), 1908 ahc_inb(ahc, SCB_DATACNT)); 1909 break; 1910 } 1911 case HOST_MSG_LOOP: 1912 { 1913 /* 1914 * The sequencer has encountered a message phase 1915 * that requires host assistance for completion. 1916 * While handling the message phase(s), we will be 1917 * notified by the sequencer after each byte is 1918 * transfered so we can track bus phases. 1919 * 1920 * If this is the first time we've seen a HOST_MSG_LOOP, 1921 * initialize the state of the host message loop. 1922 */ 1923 if (ahc->msg_type == MSG_TYPE_NONE) { 1924 u_int bus_phase; 1925 1926 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1927 if (bus_phase != P_MESGIN 1928 && bus_phase != P_MESGOUT) { 1929 printf("ahc_intr: HOST_MSG_LOOP bad " 1930 "phase 0x%x\n", 1931 bus_phase); 1932 /* 1933 * Probably transitioned to bus free before 1934 * we got here. Just punt the message. 1935 */ 1936 ahc_clear_intstat(ahc); 1937 restart_sequencer(ahc); 1938 } 1939 1940 if (devinfo.role == ROLE_INITIATOR) { 1941 struct scb *scb; 1942 u_int scb_index; 1943 1944 scb_index = ahc_inb(ahc, SCB_TAG); 1945 scb = &ahc->scb_data->scbarray[scb_index]; 1946 1947 if (bus_phase == P_MESGOUT) 1948 ahc_setup_initiator_msgout(ahc, 1949 &devinfo, 1950 scb); 1951 else { 1952 ahc->msg_type = 1953 MSG_TYPE_INITIATOR_MSGIN; 1954 ahc->msgin_index = 0; 1955 } 1956 } else { 1957 if (bus_phase == P_MESGOUT) { 1958 ahc->msg_type = 1959 MSG_TYPE_TARGET_MSGOUT; 1960 ahc->msgin_index = 0; 1961 } else 1962 /* XXX Ever executed??? */ 1963 ahc_setup_target_msgin(ahc, &devinfo); 1964 } 1965 } 1966 1967 /* Pass a NULL path so that handlers generate their own */ 1968 ahc_handle_message_phase(ahc, /*path*/NULL); 1969 break; 1970 } 1971 case PERR_DETECTED: 1972 { 1973 /* 1974 * If we've cleared the parity error interrupt 1975 * but the sequencer still believes that SCSIPERR 1976 * is true, it must be that the parity error is 1977 * for the currently presented byte on the bus, 1978 * and we are not in a phase (data-in) where we will 1979 * eventually ack this byte. Ack the byte and 1980 * throw it away in the hope that the target will 1981 * take us to message out to deliver the appropriate 1982 * error message. 1983 */ 1984 if ((intstat & SCSIINT) == 0 1985 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1986 u_int curphase; 1987 1988 /* 1989 * The hardware will only let you ack bytes 1990 * if the expected phase in SCSISIGO matches 1991 * the current phase. Make sure this is 1992 * currently the case. 1993 */ 1994 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1995 ahc_outb(ahc, LASTPHASE, curphase); 1996 ahc_outb(ahc, SCSISIGO, curphase); 1997 ahc_inb(ahc, SCSIDATL); 1998 } 1999 break; 2000 } 2001 case DATA_OVERRUN: 2002 { 2003 /* 2004 * When the sequencer detects an overrun, it 2005 * places the controller in "BITBUCKET" mode 2006 * and allows the target to complete its transfer. 2007 * Unfortunately, none of the counters get updated 2008 * when the controller is in this mode, so we have 2009 * no way of knowing how large the overrun was. 2010 */ 2011 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2012 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2013 int i; 2014 2015 scb = &ahc->scb_data->scbarray[scbindex]; 2016 for (i = 0; i < num_phases; i++) { 2017 if (lastphase == phase_table[i].phase) 2018 break; 2019 } 2020 scsi_print_addr(scb->xs->sc_link); 2021 printf("data overrun detected %s." 2022 " Tag == 0x%x.\n", 2023 phase_table[i].phasemsg, 2024 scb->hscb->tag); 2025 scsi_print_addr(scb->xs->sc_link); 2026 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2027 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2028 scb->xs->datalen, scb->sg_count); 2029 if (scb->sg_count > 0) { 2030 for (i = 0; i < scb->sg_count; i++) { 2031 printf("sg[%d] - Addr 0x%x : Length %d\n", 2032 i, 2033 le32toh(scb->sg_list[i].addr), 2034 le32toh(scb->sg_list[i].len)); 2035 } 2036 } 2037 /* 2038 * Set this and it will take affect when the 2039 * target does a command complete. 2040 */ 2041 ahc_freeze_devq(ahc, scb->xs->sc_link); 2042 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2043 ahc_freeze_ccb(scb); 2044 break; 2045 } 2046 case TRACEPOINT: 2047 { 2048 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2049 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2050 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2051 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2052 printf("TRACEPOINT: CCHADDR = %x\n", 2053 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2054 | (ahc_inb(ahc, CCHADDR+2) << 16) 2055 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2056 #if 0 2057 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2058 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2059 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2060 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2061 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2062 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2063 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2064 ahc_inb(ahc, CCHADDR) 2065 | (ahc_inb(ahc, CCHADDR+1) << 8) 2066 | (ahc_inb(ahc, CCHADDR+2) << 16) 2067 | (ahc_inb(ahc, CCHADDR+3) << 24), 2068 ahc_inb(ahc, CCHCNT) 2069 | (ahc_inb(ahc, CCHCNT+1) << 8) 2070 | (ahc_inb(ahc, CCHCNT+2) << 16), 2071 ahc_inb(ahc, SCBPTR)); 2072 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2073 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2074 #if DDB > 0 2075 cpu_Debugger(); 2076 #endif 2077 #endif 2078 break; 2079 } 2080 #if NOT_YET 2081 /* XXX Fill these in later */ 2082 case MESG_BUFFER_BUSY: 2083 break; 2084 case MSGIN_PHASEMIS: 2085 break; 2086 #endif 2087 default: 2088 printf("ahc_intr: seqint, " 2089 "intstat == 0x%x, scsisigi = 0x%x\n", 2090 intstat, ahc_inb(ahc, SCSISIGI)); 2091 break; 2092 } 2093 2094 unpause: 2095 /* 2096 * The sequencer is paused immediately on 2097 * a SEQINT, so we should restart it when 2098 * we're done. 2099 */ 2100 unpause_sequencer(ahc); 2101 } 2102 2103 static void 2104 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2105 { 2106 u_int scb_index; 2107 u_int status; 2108 struct scb *scb; 2109 char cur_channel; 2110 char intr_channel; 2111 2112 if ((ahc->features & AHC_TWIN) != 0 2113 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2114 cur_channel = 'B'; 2115 else 2116 cur_channel = 'A'; 2117 intr_channel = cur_channel; 2118 2119 status = ahc_inb(ahc, SSTAT1); 2120 if (status == 0) { 2121 if ((ahc->features & AHC_TWIN) != 0) { 2122 /* Try the other channel */ 2123 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2124 status = ahc_inb(ahc, SSTAT1); 2125 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2126 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2127 } 2128 if (status == 0) { 2129 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2130 return; 2131 } 2132 } 2133 2134 scb_index = ahc_inb(ahc, SCB_TAG); 2135 if (scb_index < ahc->scb_data->numscbs) { 2136 scb = &ahc->scb_data->scbarray[scb_index]; 2137 if ((scb->flags & SCB_ACTIVE) == 0 2138 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2139 scb = NULL; 2140 } else 2141 scb = NULL; 2142 2143 if ((status & SCSIRSTI) != 0) { 2144 printf("%s: Someone reset channel %c\n", 2145 ahc_name(ahc), intr_channel); 2146 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2147 } else if ((status & SCSIPERR) != 0) { 2148 /* 2149 * Determine the bus phase and queue an appropriate message. 2150 * SCSIPERR is latched true as soon as a parity error 2151 * occurs. If the sequencer acked the transfer that 2152 * caused the parity error and the currently presented 2153 * transfer on the bus has correct parity, SCSIPERR will 2154 * be cleared by CLRSCSIPERR. Use this to determine if 2155 * we should look at the last phase the sequencer recorded, 2156 * or the current phase presented on the bus. 2157 */ 2158 u_int mesg_out; 2159 u_int curphase; 2160 u_int errorphase; 2161 u_int lastphase; 2162 int i; 2163 2164 lastphase = ahc_inb(ahc, LASTPHASE); 2165 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2166 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2167 /* 2168 * For all phases save DATA, the sequencer won't 2169 * automatically ack a byte that has a parity error 2170 * in it. So the only way that the current phase 2171 * could be 'data-in' is if the parity error is for 2172 * an already acked byte in the data phase. During 2173 * synchronous data-in transfers, we may actually 2174 * ack bytes before latching the current phase in 2175 * LASTPHASE, leading to the discrepancy between 2176 * curphase and lastphase. 2177 */ 2178 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2179 || curphase == P_DATAIN) 2180 errorphase = curphase; 2181 else 2182 errorphase = lastphase; 2183 2184 for (i = 0; i < num_phases; i++) { 2185 if (errorphase == phase_table[i].phase) 2186 break; 2187 } 2188 mesg_out = phase_table[i].mesg_out; 2189 if (scb != NULL) 2190 scsi_print_addr(scb->xs->sc_link); 2191 else 2192 printf("%s:%c:%d: ", ahc_name(ahc), 2193 intr_channel, 2194 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2195 2196 printf("parity error detected %s. " 2197 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2198 phase_table[i].phasemsg, 2199 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2200 ahc_inb(ahc, SCSIRATE)); 2201 2202 /* 2203 * We've set the hardware to assert ATN if we 2204 * get a parity error on "in" phases, so all we 2205 * need to do is stuff the message buffer with 2206 * the appropriate message. "In" phases have set 2207 * mesg_out to something other than MSG_NOP. 2208 */ 2209 if (mesg_out != MSG_NOOP) { 2210 if (ahc->msg_type != MSG_TYPE_NONE) 2211 ahc->send_msg_perror = TRUE; 2212 else 2213 ahc_outb(ahc, MSG_OUT, mesg_out); 2214 } 2215 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2216 unpause_sequencer(ahc); 2217 } else if ((status & BUSFREE) != 0 2218 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2219 /* 2220 * First look at what phase we were last in. 2221 * If its message out, chances are pretty good 2222 * that the busfree was in response to one of 2223 * our abort requests. 2224 */ 2225 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2226 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2227 u_int target = TCL_TARGET(saved_tcl); 2228 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2229 char channel = TCL_CHANNEL(ahc, saved_tcl); 2230 int printerror = 1; 2231 2232 ahc_outb(ahc, SCSISEQ, 2233 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2234 if (lastphase == P_MESGOUT) { 2235 u_int message; 2236 u_int tag; 2237 2238 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2239 tag = SCB_LIST_NULL; 2240 switch (message) { 2241 case MSG_ABORT_TAG: 2242 tag = scb->hscb->tag; 2243 /* FALLTRHOUGH */ 2244 case MSG_ABORT: 2245 scsi_print_addr(scb->xs->sc_link); 2246 printf("SCB %x - Abort %s Completed.\n", 2247 scb->hscb->tag, tag == SCB_LIST_NULL ? 2248 "" : "Tag"); 2249 ahc_abort_scbs(ahc, target, channel, 2250 TCL_LUN(saved_tcl), tag, 2251 ROLE_INITIATOR, 2252 XS_DRIVER_STUFFUP); 2253 printerror = 0; 2254 break; 2255 case MSG_BUS_DEV_RESET: 2256 { 2257 struct ahc_devinfo devinfo; 2258 2259 if (scb != NULL && 2260 (scb->xs->xs_control & XS_CTL_RESET) 2261 && ahc_match_scb(scb, target, channel, 2262 TCL_LUN(saved_tcl), 2263 SCB_LIST_NULL, 2264 ROLE_INITIATOR)) { 2265 ahcsetccbstatus(scb->xs, XS_NOERROR); 2266 } 2267 ahc_compile_devinfo(&devinfo, 2268 initiator_role_id, 2269 target, 2270 TCL_LUN(saved_tcl), 2271 channel, 2272 ROLE_INITIATOR); 2273 ahc_handle_devreset(ahc, &devinfo, 2274 XS_RESET, 2275 "Bus Device Reset", 2276 /*verbose_level*/0); 2277 printerror = 0; 2278 break; 2279 } 2280 default: 2281 break; 2282 } 2283 } 2284 if (printerror != 0) { 2285 int i; 2286 2287 if (scb != NULL) { 2288 u_int tag; 2289 2290 if ((scb->hscb->control & TAG_ENB) != 0) 2291 tag = scb->hscb->tag; 2292 else 2293 tag = SCB_LIST_NULL; 2294 ahc_abort_scbs(ahc, target, channel, 2295 SCB_LUN(scb), tag, 2296 ROLE_INITIATOR, 2297 XS_DRIVER_STUFFUP); 2298 scsi_print_addr(scb->xs->sc_link); 2299 } else { 2300 /* 2301 * We had not fully identified this connection, 2302 * so we cannot abort anything. 2303 */ 2304 printf("%s: ", ahc_name(ahc)); 2305 } 2306 for (i = 0; i < num_phases; i++) { 2307 if (lastphase == phase_table[i].phase) 2308 break; 2309 } 2310 printf("Unexpected busfree %s\n" 2311 "SEQADDR == 0x%x\n", 2312 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2313 | (ahc_inb(ahc, SEQADDR1) << 8)); 2314 } 2315 ahc_clear_msg_state(ahc); 2316 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2317 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2318 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2319 restart_sequencer(ahc); 2320 } else if ((status & SELTO) != 0) { 2321 u_int scbptr; 2322 2323 scbptr = ahc_inb(ahc, WAITING_SCBH); 2324 ahc_outb(ahc, SCBPTR, scbptr); 2325 scb_index = ahc_inb(ahc, SCB_TAG); 2326 2327 if (scb_index < ahc->scb_data->numscbs) { 2328 scb = &ahc->scb_data->scbarray[scb_index]; 2329 if ((scb->flags & SCB_ACTIVE) == 0) 2330 scb = NULL; 2331 } else 2332 scb = NULL; 2333 2334 if (scb == NULL) { 2335 printf("%s: ahc_intr - referenced scb not " 2336 "valid during SELTO scb(%d, %d)\n", 2337 ahc_name(ahc), scbptr, scb_index); 2338 } else { 2339 u_int tag; 2340 2341 tag = SCB_LIST_NULL; 2342 if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) 2343 tag = scb->hscb->tag; 2344 2345 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2346 SCB_LUN(scb), tag, 2347 ROLE_INITIATOR, XS_SELTIMEOUT); 2348 } 2349 /* Stop the selection */ 2350 ahc_outb(ahc, SCSISEQ, 0); 2351 2352 /* No more pending messages */ 2353 ahc_clear_msg_state(ahc); 2354 2355 /* 2356 * Although the driver does not care about the 2357 * 'Selection in Progress' status bit, the busy 2358 * LED does. SELINGO is only cleared by a sucessful 2359 * selection, so we must manually clear it to ensure 2360 * the LED turns off just incase no future successful 2361 * selections occur (e.g. no devices on the bus). 2362 */ 2363 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2364 2365 /* Clear interrupt state */ 2366 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2367 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2368 restart_sequencer(ahc); 2369 } else { 2370 scsi_print_addr(scb->xs->sc_link); 2371 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2372 ahc_outb(ahc, CLRSINT1, status); 2373 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2374 unpause_sequencer(ahc); 2375 } 2376 } 2377 2378 static void 2379 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2380 { 2381 /* 2382 * We need to initiate transfer negotiations. 2383 * If our current and goal settings are identical, 2384 * we want to renegotiate due to a check condition. 2385 */ 2386 struct ahc_initiator_tinfo *tinfo; 2387 struct tmode_tstate *tstate; 2388 int dowide; 2389 int dosync; 2390 2391 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2392 devinfo->target, &tstate); 2393 dowide = tinfo->current.width != tinfo->goal.width; 2394 dosync = tinfo->current.period != tinfo->goal.period; 2395 2396 if (!dowide && !dosync) { 2397 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2398 dosync = tinfo->goal.period != 0; 2399 } 2400 2401 if (dowide) { 2402 ahc_construct_wdtr(ahc, tinfo->goal.width); 2403 } else if (dosync) { 2404 const struct ahc_syncrate *rate; 2405 u_int period; 2406 u_int offset; 2407 2408 period = tinfo->goal.period; 2409 rate = ahc_devlimited_syncrate(ahc, &period); 2410 offset = tinfo->goal.offset; 2411 ahc_validate_offset(ahc, rate, &offset, 2412 tinfo->current.width); 2413 ahc_construct_sdtr(ahc, period, offset); 2414 } else { 2415 panic("ahc_intr: AWAITING_MSG for negotiation, " 2416 "but no negotiation needed\n"); 2417 } 2418 } 2419 2420 static void 2421 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2422 struct scb *scb) 2423 { 2424 /* 2425 * To facilitate adding multiple messages together, 2426 * each routine should increment the index and len 2427 * variables instead of setting them explicitly. 2428 */ 2429 ahc->msgout_index = 0; 2430 ahc->msgout_len = 0; 2431 2432 if ((scb->flags & SCB_DEVICE_RESET) == 0 2433 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2434 u_int identify_msg; 2435 2436 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2437 if ((scb->hscb->control & DISCENB) != 0) 2438 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2439 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2440 ahc->msgout_len++; 2441 2442 if ((scb->hscb->control & TAG_ENB) != 0) { 2443 /* XXX fvdl FreeBSD has tag action passed down */ 2444 ahc->msgout_buf[ahc->msgout_index++] = MSG_SIMPLE_Q_TAG; 2445 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2446 ahc->msgout_len += 2; 2447 } 2448 } 2449 2450 if (scb->flags & SCB_DEVICE_RESET) { 2451 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2452 ahc->msgout_len++; 2453 scsi_print_addr(scb->xs->sc_link); 2454 printf("Bus Device Reset Message Sent\n"); 2455 } else if (scb->flags & SCB_ABORT) { 2456 if ((scb->hscb->control & TAG_ENB) != 0) 2457 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2458 else 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2460 ahc->msgout_len++; 2461 scsi_print_addr(scb->xs->sc_link); 2462 printf("Abort Message Sent\n"); 2463 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2464 ahc_build_transfer_msg(ahc, devinfo); 2465 } else { 2466 printf("ahc_intr: AWAITING_MSG for an SCB that " 2467 "does not have a waiting message"); 2468 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2469 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2470 ahc_inb(ahc, MSG_OUT), scb->flags); 2471 } 2472 2473 /* 2474 * Clear the MK_MESSAGE flag from the SCB so we aren't 2475 * asked to send this message again. 2476 */ 2477 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2478 ahc->msgout_index = 0; 2479 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2480 } 2481 2482 static void 2483 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2484 { 2485 /* 2486 * To facilitate adding multiple messages together, 2487 * each routine should increment the index and len 2488 * variables instead of setting them explicitly. 2489 */ 2490 ahc->msgout_index = 0; 2491 ahc->msgout_len = 0; 2492 2493 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2494 ahc_build_transfer_msg(ahc, devinfo); 2495 else 2496 panic("ahc_intr: AWAITING target message with no message"); 2497 2498 ahc->msgout_index = 0; 2499 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2500 } 2501 2502 static int 2503 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2504 { 2505 /* 2506 * What we care about here is if we had an 2507 * outstanding SDTR or WDTR message for this 2508 * target. If we did, this is a signal that 2509 * the target is refusing negotiation. 2510 */ 2511 struct scb *scb; 2512 u_int scb_index; 2513 u_int last_msg; 2514 int response = 0; 2515 2516 scb_index = ahc_inb(ahc, SCB_TAG); 2517 scb = &ahc->scb_data->scbarray[scb_index]; 2518 2519 /* Might be necessary */ 2520 last_msg = ahc_inb(ahc, LAST_MSG); 2521 2522 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2523 struct ahc_initiator_tinfo *tinfo; 2524 struct tmode_tstate *tstate; 2525 2526 #ifdef AHC_DEBUG_NEG 2527 /* note 8bit xfers */ 2528 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2529 "8bit transfers\n", ahc_name(ahc), 2530 devinfo->channel, devinfo->target); 2531 #endif 2532 ahc_set_width(ahc, devinfo, 2533 MSG_EXT_WDTR_BUS_8_BIT, 2534 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2535 /*paused*/TRUE, /*done*/TRUE); 2536 /* 2537 * No need to clear the sync rate. If the target 2538 * did not accept the command, our syncrate is 2539 * unaffected. If the target started the negotiation, 2540 * but rejected our response, we already cleared the 2541 * sync rate before sending our WDTR. 2542 */ 2543 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2544 devinfo->our_scsiid, 2545 devinfo->target, &tstate); 2546 if (tinfo->goal.period) { 2547 u_int period; 2548 2549 /* Start the sync negotiation */ 2550 period = tinfo->goal.period; 2551 ahc_devlimited_syncrate(ahc, &period); 2552 ahc->msgout_index = 0; 2553 ahc->msgout_len = 0; 2554 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2555 ahc->msgout_index = 0; 2556 response = 1; 2557 } 2558 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2559 /* note asynch xfers and clear flag */ 2560 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2561 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2562 /*paused*/TRUE, /*done*/TRUE); 2563 #ifdef AHC_DEBUG_NEG 2564 printf("%s:%c:%d: refuses synchronous negotiation. " 2565 "Using asynchronous transfers\n", 2566 ahc_name(ahc), 2567 devinfo->channel, devinfo->target); 2568 #endif 2569 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2570 printf("%s:%c:%d: refuses tagged commands. Performing " 2571 "non-tagged I/O\n", ahc_name(ahc), 2572 devinfo->channel, devinfo->target); 2573 2574 ahc_set_tags(ahc, devinfo, FALSE); 2575 2576 /* 2577 * Resend the identify for this CCB as the target 2578 * may believe that the selection is invalid otherwise. 2579 */ 2580 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2581 & ~MSG_SIMPLE_Q_TAG); 2582 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2583 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2584 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2585 2586 /* 2587 * Requeue all tagged commands for this target 2588 * currently in our posession so they can be 2589 * converted to untagged commands. 2590 */ 2591 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2592 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2593 ROLE_INITIATOR, SCB_REQUEUE, 2594 SEARCH_COMPLETE); 2595 } else { 2596 /* 2597 * Otherwise, we ignore it. 2598 */ 2599 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2600 ahc_name(ahc), devinfo->channel, devinfo->target, 2601 last_msg); 2602 } 2603 return (response); 2604 } 2605 2606 static void 2607 ahc_clear_msg_state(struct ahc_softc *ahc) 2608 { 2609 ahc->msgout_len = 0; 2610 ahc->msgin_index = 0; 2611 ahc->msg_type = MSG_TYPE_NONE; 2612 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2613 } 2614 2615 static void 2616 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_link *sc_link) 2617 { 2618 struct ahc_devinfo devinfo; 2619 u_int bus_phase; 2620 int end_session; 2621 2622 ahc_fetch_devinfo(ahc, &devinfo); 2623 end_session = FALSE; 2624 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2625 2626 reswitch: 2627 switch (ahc->msg_type) { 2628 case MSG_TYPE_INITIATOR_MSGOUT: 2629 { 2630 int lastbyte; 2631 int phasemis; 2632 int msgdone; 2633 2634 if (ahc->msgout_len == 0) 2635 panic("REQINIT interrupt with no active message"); 2636 2637 phasemis = bus_phase != P_MESGOUT; 2638 if (phasemis) { 2639 if (bus_phase == P_MESGIN) { 2640 /* 2641 * Change gears and see if 2642 * this messages is of interest to 2643 * us or should be passed back to 2644 * the sequencer. 2645 */ 2646 ahc_outb(ahc, CLRSINT1, CLRATNO); 2647 ahc->send_msg_perror = FALSE; 2648 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2649 ahc->msgin_index = 0; 2650 goto reswitch; 2651 } 2652 end_session = TRUE; 2653 break; 2654 } 2655 2656 if (ahc->send_msg_perror) { 2657 ahc_outb(ahc, CLRSINT1, CLRATNO); 2658 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2659 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2660 break; 2661 } 2662 2663 msgdone = ahc->msgout_index == ahc->msgout_len; 2664 if (msgdone) { 2665 /* 2666 * The target has requested a retry. 2667 * Re-assert ATN, reset our message index to 2668 * 0, and try again. 2669 */ 2670 ahc->msgout_index = 0; 2671 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2672 } 2673 2674 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2675 if (lastbyte) { 2676 /* Last byte is signified by dropping ATN */ 2677 ahc_outb(ahc, CLRSINT1, CLRATNO); 2678 } 2679 2680 /* 2681 * Clear our interrupt status and present 2682 * the next byte on the bus. 2683 */ 2684 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2685 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2686 break; 2687 } 2688 case MSG_TYPE_INITIATOR_MSGIN: 2689 { 2690 int phasemis; 2691 int message_done; 2692 2693 phasemis = bus_phase != P_MESGIN; 2694 2695 if (phasemis) { 2696 ahc->msgin_index = 0; 2697 if (bus_phase == P_MESGOUT 2698 && (ahc->send_msg_perror == TRUE 2699 || (ahc->msgout_len != 0 2700 && ahc->msgout_index == 0))) { 2701 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2702 goto reswitch; 2703 } 2704 end_session = TRUE; 2705 break; 2706 } 2707 2708 /* Pull the byte in without acking it */ 2709 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2710 2711 message_done = ahc_parse_msg(ahc, sc_link, &devinfo); 2712 2713 if (message_done) { 2714 /* 2715 * Clear our incoming message buffer in case there 2716 * is another message following this one. 2717 */ 2718 ahc->msgin_index = 0; 2719 2720 /* 2721 * If this message illicited a response, 2722 * assert ATN so the target takes us to the 2723 * message out phase. 2724 */ 2725 if (ahc->msgout_len != 0) 2726 ahc_outb(ahc, SCSISIGO, 2727 ahc_inb(ahc, SCSISIGO) | ATNO); 2728 } else 2729 ahc->msgin_index++; 2730 2731 /* Ack the byte */ 2732 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2733 ahc_inb(ahc, SCSIDATL); 2734 break; 2735 } 2736 case MSG_TYPE_TARGET_MSGIN: 2737 { 2738 int msgdone; 2739 int msgout_request; 2740 2741 if (ahc->msgout_len == 0) 2742 panic("Target MSGIN with no active message"); 2743 2744 /* 2745 * If we interrupted a mesgout session, the initiator 2746 * will not know this until our first REQ. So, we 2747 * only honor mesgout requests after we've sent our 2748 * first byte. 2749 */ 2750 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2751 && ahc->msgout_index > 0) 2752 msgout_request = TRUE; 2753 else 2754 msgout_request = FALSE; 2755 2756 if (msgout_request) { 2757 2758 /* 2759 * Change gears and see if 2760 * this messages is of interest to 2761 * us or should be passed back to 2762 * the sequencer. 2763 */ 2764 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2765 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2766 ahc->msgin_index = 0; 2767 /* Dummy read to REQ for first byte */ 2768 ahc_inb(ahc, SCSIDATL); 2769 ahc_outb(ahc, SXFRCTL0, 2770 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2771 break; 2772 } 2773 2774 msgdone = ahc->msgout_index == ahc->msgout_len; 2775 if (msgdone) { 2776 ahc_outb(ahc, SXFRCTL0, 2777 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2778 end_session = TRUE; 2779 break; 2780 } 2781 2782 /* 2783 * Present the next byte on the bus. 2784 */ 2785 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2786 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2787 break; 2788 } 2789 case MSG_TYPE_TARGET_MSGOUT: 2790 { 2791 int lastbyte; 2792 int msgdone; 2793 2794 /* 2795 * The initiator signals that this is 2796 * the last byte by dropping ATN. 2797 */ 2798 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2799 2800 /* 2801 * Read the latched byte, but turn off SPIOEN first 2802 * so that we don't inadvertantly cause a REQ for the 2803 * next byte. 2804 */ 2805 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2806 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2807 msgdone = ahc_parse_msg(ahc, sc_link, &devinfo); 2808 if (msgdone == MSGLOOP_TERMINATED) { 2809 /* 2810 * The message is *really* done in that it caused 2811 * us to go to bus free. The sequencer has already 2812 * been reset at this point, so pull the ejection 2813 * handle. 2814 */ 2815 return; 2816 } 2817 2818 ahc->msgin_index++; 2819 2820 /* 2821 * XXX Read spec about initiator dropping ATN too soon 2822 * and use msgdone to detect it. 2823 */ 2824 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2825 ahc->msgin_index = 0; 2826 2827 /* 2828 * If this message illicited a response, transition 2829 * to the Message in phase and send it. 2830 */ 2831 if (ahc->msgout_len != 0) { 2832 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2833 ahc_outb(ahc, SXFRCTL0, 2834 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2835 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2836 ahc->msgin_index = 0; 2837 break; 2838 } 2839 } 2840 2841 if (lastbyte) 2842 end_session = TRUE; 2843 else { 2844 /* Ask for the next byte. */ 2845 ahc_outb(ahc, SXFRCTL0, 2846 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2847 } 2848 2849 break; 2850 } 2851 default: 2852 panic("Unknown REQINIT message type"); 2853 } 2854 2855 if (end_session) { 2856 ahc_clear_msg_state(ahc); 2857 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2858 } else 2859 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2860 } 2861 2862 /* 2863 * See if we sent a particular extended message to the target. 2864 * If "full" is true, the target saw the full message. 2865 * If "full" is false, the target saw at least the first 2866 * byte of the message. 2867 */ 2868 static int 2869 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2870 { 2871 int found; 2872 int index; 2873 2874 found = FALSE; 2875 index = 0; 2876 2877 while (index < ahc->msgout_len) { 2878 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2879 2880 /* Found a candidate */ 2881 if (ahc->msgout_buf[index+2] == msgtype) { 2882 u_int end_index; 2883 2884 end_index = index + 1 2885 + ahc->msgout_buf[index + 1]; 2886 if (full) { 2887 if (ahc->msgout_index > end_index) 2888 found = TRUE; 2889 } else if (ahc->msgout_index > index) 2890 found = TRUE; 2891 } 2892 break; 2893 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2894 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2895 2896 /* Skip tag type and tag id or residue param*/ 2897 index += 2; 2898 } else { 2899 /* Single byte message */ 2900 index++; 2901 } 2902 } 2903 return (found); 2904 } 2905 2906 static int 2907 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_link *sc_link, 2908 struct ahc_devinfo *devinfo) 2909 { 2910 struct ahc_initiator_tinfo *tinfo; 2911 struct tmode_tstate *tstate; 2912 int reject; 2913 int done; 2914 int response; 2915 u_int targ_scsirate; 2916 2917 done = MSGLOOP_IN_PROG; 2918 response = FALSE; 2919 reject = FALSE; 2920 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2921 devinfo->target, &tstate); 2922 targ_scsirate = tinfo->scsirate; 2923 2924 /* 2925 * Parse as much of the message as is availible, 2926 * rejecting it if we don't support it. When 2927 * the entire message is availible and has been 2928 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2929 * that we have parsed an entire message. 2930 * 2931 * In the case of extended messages, we accept the length 2932 * byte outright and perform more checking once we know the 2933 * extended message type. 2934 */ 2935 switch (ahc->msgin_buf[0]) { 2936 case MSG_MESSAGE_REJECT: 2937 response = ahc_handle_msg_reject(ahc, devinfo); 2938 /* FALLTHROUGH */ 2939 case MSG_NOOP: 2940 done = MSGLOOP_MSGCOMPLETE; 2941 break; 2942 case MSG_IGN_WIDE_RESIDUE: 2943 { 2944 /* Wait for the whole message */ 2945 if (ahc->msgin_index >= 1) { 2946 if (ahc->msgin_buf[1] != 1 2947 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2948 reject = TRUE; 2949 done = MSGLOOP_MSGCOMPLETE; 2950 } else 2951 ahc_handle_ign_wide_residue(ahc, devinfo); 2952 } 2953 break; 2954 } 2955 case MSG_EXTENDED: 2956 { 2957 /* Wait for enough of the message to begin validation */ 2958 if (ahc->msgin_index < 2) 2959 break; 2960 switch (ahc->msgin_buf[2]) { 2961 case MSG_EXT_SDTR: 2962 { 2963 const struct ahc_syncrate *syncrate; 2964 u_int period; 2965 u_int offset; 2966 u_int saved_offset; 2967 2968 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2969 reject = TRUE; 2970 break; 2971 } 2972 2973 /* 2974 * Wait until we have both args before validating 2975 * and acting on this message. 2976 * 2977 * Add one to MSG_EXT_SDTR_LEN to account for 2978 * the extended message preamble. 2979 */ 2980 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2981 break; 2982 2983 period = ahc->msgin_buf[3]; 2984 saved_offset = offset = ahc->msgin_buf[4]; 2985 syncrate = ahc_devlimited_syncrate(ahc, &period); 2986 ahc_validate_offset(ahc, syncrate, &offset, 2987 targ_scsirate & WIDEXFER); 2988 ahc_set_syncrate(ahc, devinfo, 2989 syncrate, period, offset, 2990 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2991 /*paused*/TRUE, /*done*/TRUE); 2992 2993 /* 2994 * See if we initiated Sync Negotiation 2995 * and didn't have to fall down to async 2996 * transfers. 2997 */ 2998 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2999 /* We started it */ 3000 if (saved_offset != offset) { 3001 /* Went too low - force async */ 3002 reject = TRUE; 3003 } 3004 } else { 3005 /* 3006 * Send our own SDTR in reply 3007 */ 3008 ahc->msgout_index = 0; 3009 ahc->msgout_len = 0; 3010 ahc_construct_sdtr(ahc, period, offset); 3011 ahc->msgout_index = 0; 3012 response = TRUE; 3013 } 3014 done = MSGLOOP_MSGCOMPLETE; 3015 break; 3016 } 3017 case MSG_EXT_WDTR: 3018 { 3019 u_int bus_width; 3020 u_int sending_reply; 3021 3022 sending_reply = FALSE; 3023 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3024 reject = TRUE; 3025 break; 3026 } 3027 3028 /* 3029 * Wait until we have our arg before validating 3030 * and acting on this message. 3031 * 3032 * Add one to MSG_EXT_WDTR_LEN to account for 3033 * the extended message preamble. 3034 */ 3035 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3036 break; 3037 3038 bus_width = ahc->msgin_buf[3]; 3039 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3040 /* 3041 * Don't send a WDTR back to the 3042 * target, since we asked first. 3043 */ 3044 switch (bus_width){ 3045 default: 3046 /* 3047 * How can we do anything greater 3048 * than 16bit transfers on a 16bit 3049 * bus? 3050 */ 3051 reject = TRUE; 3052 printf("%s: target %d requested %dBit " 3053 "transfers. Rejecting...\n", 3054 ahc_name(ahc), devinfo->target, 3055 8 * (0x01 << bus_width)); 3056 /* FALLTHROUGH */ 3057 case MSG_EXT_WDTR_BUS_8_BIT: 3058 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3059 break; 3060 case MSG_EXT_WDTR_BUS_16_BIT: 3061 break; 3062 } 3063 } else { 3064 /* 3065 * Send our own WDTR in reply 3066 */ 3067 switch (bus_width) { 3068 default: 3069 if (ahc->features & AHC_WIDE) { 3070 /* Respond Wide */ 3071 bus_width = 3072 MSG_EXT_WDTR_BUS_16_BIT; 3073 break; 3074 } 3075 /* FALLTHROUGH */ 3076 case MSG_EXT_WDTR_BUS_8_BIT: 3077 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3078 break; 3079 } 3080 ahc->msgout_index = 0; 3081 ahc->msgout_len = 0; 3082 ahc_construct_wdtr(ahc, bus_width); 3083 ahc->msgout_index = 0; 3084 response = TRUE; 3085 sending_reply = TRUE; 3086 } 3087 ahc_set_width(ahc, devinfo, bus_width, 3088 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3089 /*paused*/TRUE, /*done*/TRUE); 3090 3091 /* After a wide message, we are async */ 3092 ahc_set_syncrate(ahc, devinfo, 3093 /*syncrate*/NULL, /*period*/0, 3094 /*offset*/0, AHC_TRANS_ACTIVE, 3095 /*paused*/TRUE, /*done*/FALSE); 3096 if (sending_reply == FALSE && reject == FALSE) { 3097 3098 if (tinfo->goal.period) { 3099 const struct ahc_syncrate *rate; 3100 u_int period; 3101 u_int offset; 3102 3103 /* Start the sync negotiation */ 3104 period = tinfo->goal.period; 3105 rate = ahc_devlimited_syncrate(ahc, 3106 &period); 3107 offset = tinfo->goal.offset; 3108 ahc_validate_offset(ahc, rate, &offset, 3109 tinfo->current.width); 3110 ahc->msgout_index = 0; 3111 ahc->msgout_len = 0; 3112 ahc_construct_sdtr(ahc, period, offset); 3113 ahc->msgout_index = 0; 3114 response = TRUE; 3115 } 3116 } 3117 done = MSGLOOP_MSGCOMPLETE; 3118 break; 3119 } 3120 default: 3121 /* Unknown extended message. Reject it. */ 3122 reject = TRUE; 3123 break; 3124 } 3125 break; 3126 } 3127 case MSG_BUS_DEV_RESET: 3128 ahc_handle_devreset(ahc, devinfo, 3129 XS_RESET, "Bus Device Reset Received", 3130 /*verbose_level*/0); 3131 restart_sequencer(ahc); 3132 done = MSGLOOP_TERMINATED; 3133 break; 3134 case MSG_ABORT_TAG: 3135 case MSG_ABORT: 3136 case MSG_CLEAR_QUEUE: 3137 /* Target mode messages */ 3138 if (devinfo->role != ROLE_TARGET) { 3139 reject = TRUE; 3140 break; 3141 } 3142 #if AHC_TARGET_MODE 3143 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3144 devinfo->lun, 3145 ahc->msgin_buf[0] == MSG_ABORT_TAG 3146 ? SCB_LIST_NULL 3147 : ahc_inb(ahc, INITIATOR_TAG), 3148 ROLE_TARGET, XS_DRIVER_STUFFUP); 3149 3150 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3151 if (tstate != NULL) { 3152 struct tmode_lstate* lstate; 3153 3154 lstate = tstate->enabled_luns[devinfo->lun]; 3155 if (lstate != NULL) { 3156 ahc_queue_lstate_event(ahc, lstate, 3157 devinfo->our_scsiid, 3158 ahc->msgin_buf[0], 3159 /*arg*/0); 3160 ahc_send_lstate_events(ahc, lstate); 3161 } 3162 } 3163 done = MSGLOOP_MSGCOMPLETE; 3164 #else 3165 panic("ahc: got target mode message"); 3166 #endif 3167 break; 3168 case MSG_TERM_IO_PROC: 3169 default: 3170 reject = TRUE; 3171 break; 3172 } 3173 3174 if (reject) { 3175 /* 3176 * Setup to reject the message. 3177 */ 3178 ahc->msgout_index = 0; 3179 ahc->msgout_len = 1; 3180 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3181 done = MSGLOOP_MSGCOMPLETE; 3182 response = TRUE; 3183 } 3184 3185 if (done != MSGLOOP_IN_PROG && !response) 3186 /* Clear the outgoing message buffer */ 3187 ahc->msgout_len = 0; 3188 3189 return (done); 3190 } 3191 3192 static void 3193 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3194 { 3195 u_int scb_index; 3196 struct scb *scb; 3197 3198 scb_index = ahc_inb(ahc, SCB_TAG); 3199 scb = &ahc->scb_data->scbarray[scb_index]; 3200 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3201 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3202 /* 3203 * Ignore the message if we haven't 3204 * seen an appropriate data phase yet. 3205 */ 3206 } else { 3207 /* 3208 * If the residual occurred on the last 3209 * transfer and the transfer request was 3210 * expected to end on an odd count, do 3211 * nothing. Otherwise, subtract a byte 3212 * and update the residual count accordingly. 3213 */ 3214 u_int resid_sgcnt; 3215 3216 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3217 if (resid_sgcnt == 0 3218 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3219 /* 3220 * If the residual occurred on the last 3221 * transfer and the transfer request was 3222 * expected to end on an odd count, do 3223 * nothing. 3224 */ 3225 } else { 3226 u_int data_cnt; 3227 u_int32_t data_addr; 3228 u_int sg_index; 3229 3230 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3231 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3232 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3233 3234 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3235 | (ahc_inb(ahc, SHADDR + 2) << 16) 3236 | (ahc_inb(ahc, SHADDR + 1) << 8) 3237 | (ahc_inb(ahc, SHADDR)); 3238 3239 data_cnt += 1; 3240 data_addr -= 1; 3241 3242 sg_index = scb->sg_count - resid_sgcnt; 3243 3244 if (sg_index != 0 3245 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3246 u_int32_t sg_addr; 3247 3248 sg_index--; 3249 data_cnt = 1; 3250 data_addr = le32toh(scb->sg_list[sg_index].addr) 3251 + le32toh(scb->sg_list[sg_index].len) 3252 - 1; 3253 3254 /* 3255 * The physical address base points to the 3256 * second entry as it is always used for 3257 * calculating the "next S/G pointer". 3258 */ 3259 sg_addr = scb->sg_list_phys 3260 + (sg_index* sizeof(*scb->sg_list)); 3261 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3262 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3263 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3264 ahc_outb(ahc, SG_NEXT, sg_addr); 3265 } 3266 3267 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3268 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3269 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3270 3271 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3272 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3273 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3274 ahc_outb(ahc, SHADDR, data_addr); 3275 } 3276 } 3277 } 3278 3279 static void 3280 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3281 int status, char *message, 3282 int verbose_level) 3283 { 3284 int found; 3285 3286 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3287 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3288 status); 3289 3290 /* 3291 * Go back to async/narrow transfers and renegotiate. 3292 * ahc_set_width and ahc_set_syncrate can cope with NULL 3293 * paths. 3294 */ 3295 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3296 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3297 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3298 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3299 /*paused*/TRUE, /*done*/FALSE); 3300 3301 if (message != NULL && (verbose_level <= 0)) 3302 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3303 message, devinfo->channel, devinfo->target, found); 3304 } 3305 3306 /* 3307 * We have an scb which has been processed by the 3308 * adaptor, now we look to see how the operation 3309 * went. 3310 */ 3311 static void 3312 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3313 { 3314 struct scsipi_xfer *xs; 3315 struct scsipi_link *sc_link; 3316 int requeue = 0; 3317 int target; 3318 3319 3320 xs = scb->xs; 3321 sc_link = xs->sc_link; 3322 LIST_REMOVE(scb, plinks); 3323 3324 callout_stop(&scb->xs->xs_callout); 3325 3326 #ifdef AHC_DEBUG 3327 if (ahc_debug & AHC_SHOWCMDS) { 3328 scsi_print_addr(sc_link); 3329 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3330 scb->hscb->tag); 3331 } 3332 #endif 3333 3334 target = sc_link->scsipi_scsi.target; 3335 3336 if (xs->datalen) { 3337 int op; 3338 3339 if (xs->xs_control & XS_CTL_DATA_IN) 3340 op = BUS_DMASYNC_POSTREAD; 3341 else 3342 op = BUS_DMASYNC_POSTWRITE; 3343 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3344 scb->dmamap->dm_mapsize, op); 3345 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3346 } 3347 3348 /* 3349 * Unbusy this target/channel/lun. 3350 * XXX if we are holding two commands per lun, 3351 * send the next command. 3352 */ 3353 if (!(scb->hscb->control & TAG_ENB)) 3354 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3355 3356 /* 3357 * If the recovery SCB completes, we have to be 3358 * out of our timeout. 3359 */ 3360 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3361 3362 struct scb *scbp; 3363 3364 /* 3365 * We were able to complete the command successfully, 3366 * so reinstate the timeouts for all other pending 3367 * commands. 3368 */ 3369 scbp = ahc->pending_ccbs.lh_first; 3370 while (scbp != NULL) { 3371 struct scsipi_xfer *txs = scbp->xs; 3372 3373 if (!(txs->xs_control & XS_CTL_POLL)) { 3374 callout_reset(&scbp->xs->xs_callout, 3375 (scbp->xs->timeout * hz) / 1000, 3376 ahc_timeout, scbp); 3377 } 3378 scbp = LIST_NEXT(scbp, plinks); 3379 } 3380 3381 /* 3382 * Ensure that we didn't put a second instance of this 3383 * SCB into the QINFIFO. 3384 */ 3385 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3386 SCB_LUN(scb), scb->hscb->tag, 3387 ROLE_INITIATOR, /*status*/0, 3388 SEARCH_REMOVE); 3389 if (xs->error != XS_NOERROR) 3390 ahcsetccbstatus(xs, XS_TIMEOUT); 3391 scsi_print_addr(xs->sc_link); 3392 printf("no longer in timeout, status = %x\n", xs->status); 3393 } 3394 3395 if (xs->error != XS_NOERROR) { 3396 /* Don't clobber any existing error state */ 3397 } else if ((scb->flags & SCB_SENSE) != 0) { 3398 /* 3399 * We performed autosense retrieval. 3400 * 3401 * bzero the sense data before having 3402 * the drive fill it. The SCSI spec mandates 3403 * that any untransfered data should be 3404 * assumed to be zero. Complete the 'bounce' 3405 * of sense information through buffers accessible 3406 * via bus-space by copying it into the clients 3407 * csio. 3408 */ 3409 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3410 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3411 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3412 xs->error = XS_SENSE; 3413 } 3414 if (scb->flags & SCB_FREEZE_QUEUE) { 3415 ahc->devqueue_blocked[target]--; 3416 scb->flags &= ~SCB_FREEZE_QUEUE; 3417 } 3418 3419 requeue = scb->flags & SCB_REQUEUE; 3420 ahcfreescb(ahc, scb); 3421 3422 if (requeue) { 3423 /* 3424 * Re-insert at the front of the private queue to 3425 * preserve order. 3426 */ 3427 int s; 3428 3429 s = splbio(); 3430 TAILQ_INSERT_HEAD(&ahc->sc_q, xs, adapter_q); 3431 splx(s); 3432 } else { 3433 xs->xs_status |= XS_STS_DONE; 3434 #ifndef AHC_NO_TAGS 3435 ahc_check_tags(ahc, xs); 3436 #endif 3437 scsipi_done(xs); 3438 } 3439 3440 if ((xs = TAILQ_FIRST(&ahc->sc_q)) != NULL) 3441 ahc_action(xs); 3442 } 3443 3444 /* 3445 * Determine the number of SCBs available on the controller 3446 */ 3447 int 3448 ahc_probe_scbs(struct ahc_softc *ahc) { 3449 int i; 3450 3451 for (i = 0; i < AHC_SCB_MAX; i++) { 3452 ahc_outb(ahc, SCBPTR, i); 3453 ahc_outb(ahc, SCB_CONTROL, i); 3454 if (ahc_inb(ahc, SCB_CONTROL) != i) 3455 break; 3456 ahc_outb(ahc, SCBPTR, 0); 3457 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3458 break; 3459 } 3460 return (i); 3461 } 3462 3463 /* 3464 * Start the board, ready for normal operation 3465 */ 3466 int 3467 ahc_init(struct ahc_softc *ahc) 3468 { 3469 int max_targ = 15; 3470 int i; 3471 int term; 3472 u_int scsi_conf; 3473 u_int scsiseq_template; 3474 u_int ultraenb; 3475 u_int discenable; 3476 u_int tagenable; 3477 size_t driver_data_size; 3478 u_int32_t physaddr; 3479 3480 #ifdef AHC_PRINT_SRAM 3481 printf("Scratch Ram:"); 3482 for (i = 0x20; i < 0x5f; i++) { 3483 if (((i % 8) == 0) && (i != 0)) { 3484 printf ("\n "); 3485 } 3486 printf (" 0x%x", ahc_inb(ahc, i)); 3487 } 3488 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3489 for (i = 0x70; i < 0x7f; i++) { 3490 if (((i % 8) == 0) && (i != 0)) { 3491 printf ("\n "); 3492 } 3493 printf (" 0x%x", ahc_inb(ahc, i)); 3494 } 3495 } 3496 printf ("\n"); 3497 #endif 3498 3499 /* 3500 * Assume we have a board at this stage and it has been reset. 3501 */ 3502 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3503 ahc->our_id = ahc->our_id_b = 7; 3504 3505 /* 3506 * Default to allowing initiator operations. 3507 */ 3508 ahc->flags |= AHC_INITIATORMODE; 3509 3510 /* 3511 * DMA tag for our command fifos and other data in system memory 3512 * the card's sequencer must be able to access. For initiator 3513 * roles, we need to allocate space for the qinfifo, qoutfifo, 3514 * and untagged_scb arrays each of which are composed of 256 3515 * 1 byte elements. When providing for the target mode role, 3516 * we additionally must provide space for the incoming target 3517 * command fifo. 3518 */ 3519 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3520 3521 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3522 ahc->sc_dmaflags, 3523 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3524 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3525 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3526 return (ENOMEM); 3527 3528 ahc->init_level++; 3529 3530 /* Allocate SCB data now that parent_dmat is initialized */ 3531 if (ahc->scb_data->maxhscbs == 0) 3532 if (ahcinitscbdata(ahc) != 0) 3533 return (ENOMEM); 3534 3535 ahc->qinfifo = &ahc->qoutfifo[256]; 3536 ahc->untagged_scbs = &ahc->qinfifo[256]; 3537 /* There are no untagged SCBs active yet. */ 3538 for (i = 0; i < 256; i++) 3539 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3540 3541 /* All of our queues are empty */ 3542 for (i = 0; i < 256; i++) 3543 ahc->qoutfifo[i] = SCB_LIST_NULL; 3544 3545 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3546 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3547 3548 /* 3549 * Allocate a tstate to house information for our 3550 * initiator presence on the bus as well as the user 3551 * data for any target mode initiator. 3552 */ 3553 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3554 printf("%s: unable to allocate tmode_tstate. " 3555 "Failing attach\n", ahc_name(ahc)); 3556 return (-1); 3557 } 3558 3559 if ((ahc->features & AHC_TWIN) != 0) { 3560 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3561 printf("%s: unable to allocate tmode_tstate. " 3562 "Failing attach\n", ahc_name(ahc)); 3563 return (-1); 3564 } 3565 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3566 ahc->our_id, ahc->our_id_b, 3567 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3568 } else { 3569 if ((ahc->features & AHC_WIDE) != 0) { 3570 printf("Wide "); 3571 } else { 3572 printf("Single "); 3573 } 3574 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3575 } 3576 3577 ahc_outb(ahc, SEQ_FLAGS, 0); 3578 3579 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3580 ahc->flags |= AHC_PAGESCBS; 3581 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3582 } else { 3583 ahc->flags &= ~AHC_PAGESCBS; 3584 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3585 } 3586 3587 #ifdef AHC_DEBUG 3588 if (ahc_debug & AHC_SHOWMISC) { 3589 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3590 "ahc_dma %d bytes\n", 3591 ahc_name(ahc), 3592 sizeof(struct hardware_scb), 3593 sizeof(struct scb), 3594 sizeof(struct ahc_dma_seg)); 3595 } 3596 #endif /* AHC_DEBUG */ 3597 3598 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3599 if (ahc->features & AHC_TWIN) { 3600 3601 /* 3602 * The device is gated to channel B after a chip reset, 3603 * so set those values first 3604 */ 3605 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3606 if ((ahc->features & AHC_ULTRA2) != 0) 3607 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3608 else 3609 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3610 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3611 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3612 |term|ENSTIMER|ACTNEGEN); 3613 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3614 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3615 3616 if ((scsi_conf & RESET_SCSI) != 0 3617 && (ahc->flags & AHC_INITIATORMODE) != 0) 3618 ahc->flags |= AHC_RESET_BUS_B; 3619 3620 /* Select Channel A */ 3621 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3622 } 3623 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3624 if ((ahc->features & AHC_ULTRA2) != 0) 3625 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3626 else 3627 ahc_outb(ahc, SCSIID, ahc->our_id); 3628 scsi_conf = ahc_inb(ahc, SCSICONF); 3629 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3630 |term 3631 |ENSTIMER|ACTNEGEN); 3632 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3633 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3634 3635 if ((scsi_conf & RESET_SCSI) != 0 3636 && (ahc->flags & AHC_INITIATORMODE) != 0) 3637 ahc->flags |= AHC_RESET_BUS_A; 3638 3639 /* 3640 * Look at the information that board initialization or 3641 * the board bios has left us. 3642 */ 3643 ultraenb = 0; 3644 tagenable = ALL_TARGETS_MASK; 3645 3646 /* Grab the disconnection disable table and invert it for our needs */ 3647 if (ahc->flags & AHC_USEDEFAULTS) { 3648 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3649 "device parameters\n", ahc_name(ahc)); 3650 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3651 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3652 discenable = ALL_TARGETS_MASK; 3653 if ((ahc->features & AHC_ULTRA) != 0) 3654 ultraenb = ALL_TARGETS_MASK; 3655 } else { 3656 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3657 | ahc_inb(ahc, DISC_DSB)); 3658 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3659 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3660 | ahc_inb(ahc, ULTRA_ENB); 3661 } 3662 3663 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3664 max_targ = 7; 3665 3666 for (i = 0; i <= max_targ; i++) { 3667 struct ahc_initiator_tinfo *tinfo; 3668 struct tmode_tstate *tstate; 3669 u_int our_id; 3670 u_int target_id; 3671 char channel; 3672 3673 channel = 'A'; 3674 our_id = ahc->our_id; 3675 target_id = i; 3676 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3677 channel = 'B'; 3678 our_id = ahc->our_id_b; 3679 target_id = i % 8; 3680 } 3681 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3682 target_id, &tstate); 3683 /* Default to async narrow across the board */ 3684 bzero(tinfo, sizeof(*tinfo)); 3685 if (ahc->flags & AHC_USEDEFAULTS) { 3686 if ((ahc->features & AHC_WIDE) != 0) 3687 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3688 3689 /* 3690 * These will be truncated when we determine the 3691 * connection type we have with the target. 3692 */ 3693 tinfo->user.period = ahc_syncrates->period; 3694 tinfo->user.offset = ~0; 3695 } else { 3696 u_int scsirate; 3697 u_int16_t mask; 3698 3699 /* Take the settings leftover in scratch RAM. */ 3700 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3701 mask = (0x01 << i); 3702 if ((ahc->features & AHC_ULTRA2) != 0) { 3703 u_int offset; 3704 u_int maxsync; 3705 3706 if ((scsirate & SOFS) == 0x0F) { 3707 /* 3708 * Haven't negotiated yet, 3709 * so the format is different. 3710 */ 3711 scsirate = (scsirate & SXFR) >> 4 3712 | (ultraenb & mask) 3713 ? 0x08 : 0x0 3714 | (scsirate & WIDEXFER); 3715 offset = MAX_OFFSET_ULTRA2; 3716 } else 3717 offset = ahc_inb(ahc, TARG_OFFSET + i); 3718 maxsync = AHC_SYNCRATE_ULTRA2; 3719 if ((ahc->features & AHC_DT) != 0) 3720 maxsync = AHC_SYNCRATE_DT; 3721 tinfo->user.period = 3722 ahc_find_period(ahc, scsirate, maxsync); 3723 if (offset == 0) 3724 tinfo->user.period = 0; 3725 else 3726 tinfo->user.offset = ~0; 3727 } else if ((scsirate & SOFS) != 0) { 3728 tinfo->user.period = 3729 ahc_find_period(ahc, scsirate, 3730 (ultraenb & mask) 3731 ? AHC_SYNCRATE_ULTRA 3732 : AHC_SYNCRATE_FAST); 3733 if (tinfo->user.period != 0) 3734 tinfo->user.offset = ~0; 3735 } 3736 if ((scsirate & WIDEXFER) != 0 3737 && (ahc->features & AHC_WIDE) != 0) 3738 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3739 } 3740 tinfo->goal = tinfo->user; /* force negotiation */ 3741 tstate->ultraenb = ultraenb; 3742 tstate->discenable = discenable; 3743 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3744 tstate->tagdisable = 0; 3745 } 3746 ahc->user_discenable = discenable; 3747 ahc->user_tagenable = tagenable; 3748 3749 /* 3750 * Tell the sequencer where it can find our arrays in memory. 3751 */ 3752 physaddr = ahc->scb_data->hscb_busaddr; 3753 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3754 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3755 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3756 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3757 3758 physaddr = ahc->shared_data_busaddr; 3759 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3760 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3761 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3762 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3763 3764 /* Target mode incomding command fifo */ 3765 physaddr += 3 * 256 * sizeof(u_int8_t); 3766 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3767 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3768 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3769 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3770 3771 /* 3772 * Initialize the group code to command length table. 3773 * This overrides the values in TARG_SCSIRATE, so only 3774 * setup the table after we have processed that information. 3775 */ 3776 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3781 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3782 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3783 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3784 3785 /* Tell the sequencer of our initial queue positions */ 3786 ahc_outb(ahc, KERNEL_QINPOS, 0); 3787 ahc_outb(ahc, QINPOS, 0); 3788 ahc_outb(ahc, QOUTPOS, 0); 3789 3790 #ifdef AHC_DEBUG 3791 if (ahc_debug & AHC_SHOWMISC) 3792 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3793 discenable, ultraenb); 3794 #endif 3795 3796 /* Don't have any special messages to send to targets */ 3797 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3798 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3799 3800 /* 3801 * Use the built in queue management registers 3802 * if they are available. 3803 */ 3804 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3805 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3806 ahc_outb(ahc, SDSCB_QOFF, 0); 3807 ahc_outb(ahc, SNSCB_QOFF, 0); 3808 ahc_outb(ahc, HNSCB_QOFF, 0); 3809 } 3810 3811 3812 /* We don't have any waiting selections */ 3813 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3814 3815 /* Our disconnection list is empty too */ 3816 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3817 3818 /* Message out buffer starts empty */ 3819 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3820 3821 /* 3822 * Setup the allowed SCSI Sequences based on operational mode. 3823 * If we are a target, we'll enable select in operations once 3824 * we've had a lun enabled. 3825 */ 3826 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3827 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3828 scsiseq_template |= ENRSELI; 3829 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3830 3831 /* 3832 * Load the Sequencer program and Enable the adapter 3833 * in "fast" mode. 3834 */ 3835 #ifdef AHC_DEBUG 3836 printf("%s: Downloading Sequencer Program...", 3837 ahc_name(ahc)); 3838 #endif 3839 3840 ahc_loadseq(ahc); 3841 3842 /* We have to wait until after any system dumps... */ 3843 shutdownhook_establish(ahc_shutdown, ahc); 3844 3845 return (0); 3846 } 3847 3848 static int 3849 ahc_ioctl(struct scsipi_link *sc_link, u_long cmd, caddr_t addr, int flag, 3850 struct proc *p) 3851 { 3852 struct ahc_softc *ahc = sc_link->adapter_softc; 3853 char channel; 3854 int s, ret = ENOTTY; 3855 3856 switch (cmd) { 3857 case SCBUSIORESET: 3858 channel = SIM_CHANNEL(ahc, sc_link); 3859 s = splbio(); 3860 ahc_reset_channel(ahc, channel, TRUE); 3861 splx(s); 3862 ret = 0; 3863 break; 3864 default: 3865 break; 3866 } 3867 3868 return ret; 3869 } 3870 3871 3872 /* 3873 * XXX fvdl the busy_tcl checks and settings should only be done 3874 * for the non-tagged queueing case, but we don't do tagged queueing 3875 * yet, so.. 3876 */ 3877 static int32_t 3878 ahc_action(struct scsipi_xfer *xs) 3879 { 3880 struct scsipi_xfer *first_xs, *next_xs = NULL; 3881 struct ahc_softc *ahc; 3882 struct scb *scb; 3883 struct hardware_scb *hscb; 3884 struct ahc_initiator_tinfo *tinfo; 3885 struct tmode_tstate *tstate; 3886 u_int target_id; 3887 u_int our_id; 3888 int s, tcl; 3889 u_int16_t mask; 3890 char channel; 3891 int dontqueue = 0, fromqueue = 0; 3892 3893 SC_DEBUG(xs->sc_link, SDEV_DB3, ("ahc_action\n")); 3894 3895 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 3896 3897 /* must protect the queue */ 3898 s = splbio(); 3899 3900 if (xs == TAILQ_FIRST(&ahc->sc_q)) { 3901 /* 3902 * Called from ahc_done. Calling with the first entry in 3903 * the queue is really just a way of seeing where we're 3904 * called from. Now, find the first eligible SCB to send, 3905 * e.g. one which will be accepted immediately. 3906 */ 3907 3908 if (ahc->queue_blocked) { 3909 splx(s); 3910 return (TRY_AGAIN_LATER); 3911 } 3912 3913 xs = ahc_first_xs(ahc); 3914 if (xs == NULL) { 3915 splx(s); 3916 return (TRY_AGAIN_LATER); 3917 } 3918 3919 next_xs = TAILQ_NEXT(xs, adapter_q); 3920 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3921 fromqueue = 1; 3922 goto get_scb; 3923 } 3924 3925 /* 3926 * If no new requests are accepted, just insert into the 3927 * private queue to wait for our turn. 3928 */ 3929 tcl = XS_TCL(ahc, xs); 3930 3931 if (ahc->queue_blocked || 3932 ahc->devqueue_blocked[xs->sc_link->scsipi_scsi.target] || 3933 (!ahc_istagged_device(ahc, xs, 0) && 3934 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL)) { 3935 if (dontqueue) { 3936 splx(s); 3937 xs->error = XS_DRIVER_STUFFUP; 3938 return TRY_AGAIN_LATER; 3939 } 3940 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3941 splx(s); 3942 return SUCCESSFULLY_QUEUED; 3943 } 3944 3945 first_xs = ahc_first_xs(ahc); 3946 3947 /* determine safety of software queueing */ 3948 dontqueue = xs->xs_control & XS_CTL_POLL; 3949 3950 /* 3951 * Handle situations where there's already entries in the 3952 * queue. 3953 */ 3954 if (first_xs != NULL) { 3955 /* 3956 * If we can't queue, we have to abort, since 3957 * we have to preserve order. 3958 */ 3959 if (dontqueue) { 3960 splx(s); 3961 xs->error = XS_DRIVER_STUFFUP; 3962 return (TRY_AGAIN_LATER); 3963 } 3964 3965 /* 3966 * Swap with the first queue entry. 3967 */ 3968 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 3969 xs = first_xs; 3970 next_xs = TAILQ_NEXT(xs, adapter_q); 3971 TAILQ_REMOVE(&ahc->sc_q, xs, adapter_q); 3972 fromqueue = 1; 3973 3974 } 3975 3976 get_scb: 3977 3978 target_id = xs->sc_link->scsipi_scsi.target; 3979 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 3980 3981 /* 3982 * get an scb to use. 3983 */ 3984 if ((scb = ahcgetscb(ahc)) == NULL) { 3985 3986 if (dontqueue) { 3987 splx(s); 3988 xs->error = XS_DRIVER_STUFFUP; 3989 return (TRY_AGAIN_LATER); 3990 } 3991 3992 /* 3993 * If we were pulled off the queue, put ourselves 3994 * back to where we came from, otherwise tack ourselves 3995 * onto the end. 3996 */ 3997 if (fromqueue && next_xs != NULL) 3998 TAILQ_INSERT_BEFORE(xs, next_xs, adapter_q); 3999 else 4000 TAILQ_INSERT_TAIL(&ahc->sc_q, xs, adapter_q); 4001 4002 splx(s); 4003 return (SUCCESSFULLY_QUEUED); 4004 } 4005 4006 tcl = XS_TCL(ahc, xs); 4007 4008 #ifdef DIAGNOSTIC 4009 if (!ahc_istagged_device(ahc, xs, 0) && 4010 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 4011 panic("ahc: queuing for busy target"); 4012 #endif 4013 4014 scb->xs = xs; 4015 hscb = scb->hscb; 4016 hscb->tcl = tcl; 4017 4018 if (ahc_istagged_device(ahc, xs, 0)) 4019 if((xs->bp != NULL) && xs->bp->b_flags & B_ASYNC) 4020 scb->hscb->control |= MSG_SIMPLE_Q_TAG; 4021 else 4022 scb->hscb->control |= MSG_ORDERED_Q_TAG; 4023 else 4024 ahc_busy_tcl(ahc, scb); 4025 4026 splx(s); 4027 4028 channel = SIM_CHANNEL(ahc, xs->sc_link); 4029 if (ahc->inited_channels[channel - 'A'] == 0) { 4030 if ((channel == 'A' && (ahc->flags & AHC_RESET_BUS_A)) || 4031 (channel == 'B' && (ahc->flags & AHC_RESET_BUS_B))) { 4032 s = splbio(); 4033 ahc_reset_channel(ahc, channel, TRUE); 4034 splx(s); 4035 } 4036 ahc->inited_channels[channel - 'A'] = 1; 4037 } 4038 4039 /* 4040 * Put all the arguments for the xfer in the scb 4041 */ 4042 4043 mask = SCB_TARGET_MASK(scb); 4044 tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, xs->sc_link), our_id, 4045 target_id, &tstate); 4046 if (ahc->inited_targets[target_id] == 0) { 4047 struct ahc_devinfo devinfo; 4048 4049 s = splbio(); 4050 ahc_compile_devinfo(&devinfo, our_id, target_id, 4051 xs->sc_link->scsipi_scsi.lun, SIM_CHANNEL(ahc, xs->sc_link), 4052 ROLE_INITIATOR); 4053 ahc_update_target_msg_request(ahc, &devinfo, tinfo, TRUE, 4054 FALSE); 4055 ahc->inited_targets[target_id] = 1; 4056 splx(s); 4057 } 4058 4059 hscb->scsirate = tinfo->scsirate; 4060 hscb->scsioffset = tinfo->current.offset; 4061 if ((tstate->ultraenb & mask) != 0) 4062 hscb->control |= ULTRAENB; 4063 4064 if ((tstate->discenable & mask) != 0) 4065 hscb->control |= DISCENB; 4066 4067 if (xs->xs_control & XS_CTL_RESET) { 4068 hscb->cmdpointer = 0; 4069 scb->flags |= SCB_DEVICE_RESET; 4070 hscb->control |= MK_MESSAGE; 4071 return ahc_execute_scb(scb, NULL, 0); 4072 } 4073 4074 return ahc_setup_data(ahc, xs, scb); 4075 } 4076 4077 static int 4078 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4079 { 4080 struct scb *scb; 4081 struct scsipi_xfer *xs; 4082 struct ahc_softc *ahc; 4083 int s; 4084 4085 scb = (struct scb *)arg; 4086 xs = scb->xs; 4087 ahc = (struct ahc_softc *)xs->sc_link->adapter_softc; 4088 4089 4090 if (nsegments != 0) { 4091 struct ahc_dma_seg *sg; 4092 bus_dma_segment_t *end_seg; 4093 int op; 4094 4095 end_seg = dm_segs + nsegments; 4096 4097 /* Copy the first SG into the data pointer area */ 4098 scb->hscb->data = dm_segs->ds_addr; 4099 scb->hscb->datalen = dm_segs->ds_len; 4100 4101 /* Copy the segments into our SG list */ 4102 sg = scb->sg_list; 4103 while (dm_segs < end_seg) { 4104 sg->addr = dm_segs->ds_addr; 4105 sg->len = dm_segs->ds_len; 4106 ahc_swap_sg(sg); 4107 sg++; 4108 dm_segs++; 4109 } 4110 4111 /* Note where to find the SG entries in bus space */ 4112 scb->hscb->SG_pointer = scb->sg_list_phys; 4113 4114 if (xs->xs_control & XS_CTL_DATA_IN) 4115 op = BUS_DMASYNC_PREREAD; 4116 else 4117 op = BUS_DMASYNC_PREWRITE; 4118 4119 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4120 scb->dmamap->dm_mapsize, op); 4121 4122 } else { 4123 scb->hscb->SG_pointer = 0; 4124 scb->hscb->data = 0; 4125 scb->hscb->datalen = 0; 4126 } 4127 4128 scb->sg_count = scb->hscb->SG_count = nsegments; 4129 4130 s = splbio(); 4131 4132 /* 4133 * Last time we need to check if this SCB needs to 4134 * be aborted. 4135 */ 4136 if (xs->xs_status & XS_STS_DONE) { 4137 if (!ahc_istagged_device(ahc, xs, 0)) 4138 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4139 if (nsegments != 0) 4140 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4141 ahcfreescb(ahc, scb); 4142 splx(s); 4143 return (COMPLETE); 4144 } 4145 4146 #ifdef DIAGNOSTIC 4147 if (scb->sg_count > 255) 4148 panic("ahc bad sg_count"); 4149 #endif 4150 4151 ahc_swap_hscb(scb->hscb); 4152 4153 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4154 4155 scb->flags |= SCB_ACTIVE; 4156 4157 if (!(xs->xs_control & XS_CTL_POLL)) 4158 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4159 ahc_timeout, scb); 4160 4161 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4162 #if 0 4163 printf("Continueing Immediate Command %d:%d\n", 4164 xs->sc_link->scsipi_scsi.target, 4165 xs->sc_link->scsipi_scsi.lun); 4166 #endif 4167 pause_sequencer(ahc); 4168 if ((ahc->flags & AHC_PAGESCBS) == 0) 4169 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4170 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4171 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4172 unpause_sequencer(ahc); 4173 } else { 4174 4175 #if 0 4176 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4177 scb->hscb->tag, ahc->qinfifonext, 4178 &ahc->qinfifo[ahc->qinfifonext], 4179 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4180 #endif 4181 4182 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4183 4184 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4185 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4186 4187 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4188 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4189 } else { 4190 pause_sequencer(ahc); 4191 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4192 unpause_sequencer(ahc); 4193 } 4194 } 4195 4196 #ifdef AHC_DEBUG 4197 if (ahc_debug & AHC_SHOWCMDS) { 4198 scsi_print_addr(xs->sc_link); 4199 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4200 " rate %x\n", 4201 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4202 scb->flags, scb->hscb->control, ahc->qinfifonext, 4203 scb->hscb->scsirate); 4204 } 4205 #endif 4206 4207 if (!(xs->xs_control & XS_CTL_POLL)) { 4208 splx(s); 4209 return (SUCCESSFULLY_QUEUED); 4210 } 4211 /* 4212 * If we can't use interrupts, poll for completion 4213 */ 4214 SC_DEBUG(xs->sc_link, SDEV_DB3, ("cmd_poll\n")); 4215 do { 4216 if (ahc_poll(ahc, xs->timeout)) { 4217 if (!(xs->xs_control & XS_CTL_SILENT)) 4218 printf("cmd fail\n"); 4219 ahc_timeout(scb); 4220 break; 4221 } 4222 } while (!(xs->xs_status & XS_STS_DONE)); 4223 splx(s); 4224 return (COMPLETE); 4225 } 4226 4227 static int 4228 ahc_poll(struct ahc_softc *ahc, int wait) 4229 { 4230 while (--wait) { 4231 DELAY(1000); 4232 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4233 break; 4234 } 4235 4236 if (wait == 0) { 4237 printf("%s: board is not responding\n", ahc_name(ahc)); 4238 return (EIO); 4239 } 4240 4241 ahc_intr((void *)ahc); 4242 return (0); 4243 } 4244 4245 static int 4246 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4247 struct scb *scb) 4248 { 4249 struct hardware_scb *hscb; 4250 4251 hscb = scb->hscb; 4252 xs->resid = xs->status = 0; 4253 4254 hscb->cmdlen = xs->cmdlen; 4255 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4256 hscb->cmdpointer = hscb->cmdstore_busaddr; 4257 4258 /* Only use S/G if there is a transfer */ 4259 if (xs->datalen) { 4260 int error; 4261 4262 error = bus_dmamap_load(ahc->parent_dmat, 4263 scb->dmamap, xs->data, 4264 xs->datalen, NULL, 4265 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4266 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4267 BUS_DMA_STREAMING); 4268 if (error) { 4269 if (!ahc_istagged_device(ahc, xs, 0)) 4270 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4271 return (TRY_AGAIN_LATER); /* XXX fvdl */ 4272 } 4273 error = ahc_execute_scb(scb, 4274 scb->dmamap->dm_segs, 4275 scb->dmamap->dm_nsegs); 4276 return error; 4277 } else { 4278 return ahc_execute_scb(scb, NULL, 0); 4279 } 4280 } 4281 4282 static void 4283 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_link *sc_link) 4284 { 4285 int target; 4286 char channel; 4287 int lun; 4288 4289 target = sc_link->scsipi_scsi.target; 4290 lun = sc_link->scsipi_scsi.lun; 4291 channel = sc_link->scsipi_scsi.channel; 4292 4293 ahc_search_qinfifo(ahc, target, channel, lun, 4294 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4295 SCB_REQUEUE, SEARCH_COMPLETE); 4296 } 4297 4298 static void 4299 ahcallocscbs(struct ahc_softc *ahc) 4300 { 4301 struct scb_data *scb_data; 4302 struct scb *next_scb; 4303 struct sg_map_node *sg_map; 4304 bus_addr_t physaddr; 4305 struct ahc_dma_seg *segs; 4306 int newcount; 4307 int i; 4308 4309 scb_data = ahc->scb_data; 4310 if (scb_data->numscbs >= AHC_SCB_MAX) 4311 /* Can't allocate any more */ 4312 return; 4313 4314 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4315 4316 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4317 4318 if (sg_map == NULL) 4319 return; 4320 4321 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4322 &sg_map->sg_dmamap, 4323 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4324 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4325 "SG space") < 0) { 4326 free(sg_map, M_DEVBUF); 4327 return; 4328 } 4329 4330 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4331 4332 segs = sg_map->sg_vaddr; 4333 physaddr = sg_map->sg_physaddr; 4334 4335 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4336 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4337 int error; 4338 4339 next_scb->sg_list = segs; 4340 /* 4341 * The sequencer always starts with the second entry. 4342 * The first entry is embedded in the scb. 4343 */ 4344 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4345 next_scb->flags = SCB_FREE; 4346 error = bus_dmamap_create(ahc->parent_dmat, 4347 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4348 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4349 &next_scb->dmamap); 4350 if (error != 0) 4351 break; 4352 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4353 next_scb->hscb->tag = ahc->scb_data->numscbs; 4354 next_scb->hscb->cmdstore_busaddr = 4355 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4356 + offsetof(struct hardware_scb, cmdstore); 4357 next_scb->hscb->cmdstore_busaddr = 4358 htole32(next_scb->hscb->cmdstore_busaddr); 4359 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4360 segs += AHC_NSEG; 4361 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4362 next_scb++; 4363 ahc->scb_data->numscbs++; 4364 } 4365 #ifdef AHC_DEBUG 4366 if (ahc_debug & AHC_SHOWSCBALLOC) 4367 printf("%s: allocated %d new SCBs count now %d\n", 4368 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4369 #endif 4370 } 4371 4372 #ifdef AHC_DUMP_SEQ 4373 static void 4374 ahc_dumpseq(struct ahc_softc* ahc) 4375 { 4376 int i; 4377 int max_prog; 4378 4379 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4380 max_prog = 448; 4381 else if ((ahc->features & AHC_ULTRA2) != 0) 4382 max_prog = 768; 4383 else 4384 max_prog = 512; 4385 4386 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4387 ahc_outb(ahc, SEQADDR0, 0); 4388 ahc_outb(ahc, SEQADDR1, 0); 4389 for (i = 0; i < max_prog; i++) { 4390 u_int8_t ins_bytes[4]; 4391 4392 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4393 printf("0x%08x\n", ins_bytes[0] << 24 4394 | ins_bytes[1] << 16 4395 | ins_bytes[2] << 8 4396 | ins_bytes[3]); 4397 } 4398 } 4399 #endif 4400 4401 static void 4402 ahc_loadseq(struct ahc_softc *ahc) 4403 { 4404 const struct patch *cur_patch; 4405 int i; 4406 int downloaded; 4407 int skip_addr; 4408 u_int8_t download_consts[4]; 4409 4410 /* Setup downloadable constant table */ 4411 #if 0 4412 /* No downloaded constants are currently defined. */ 4413 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4414 #endif 4415 4416 cur_patch = patches; 4417 downloaded = 0; 4418 skip_addr = 0; 4419 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4420 ahc_outb(ahc, SEQADDR0, 0); 4421 ahc_outb(ahc, SEQADDR1, 0); 4422 4423 for (i = 0; i < sizeof(seqprog)/4; i++) { 4424 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4425 /* 4426 * Don't download this instruction as it 4427 * is in a patch that was removed. 4428 */ 4429 continue; 4430 } 4431 ahc_download_instr(ahc, i, download_consts); 4432 downloaded++; 4433 } 4434 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4435 restart_sequencer(ahc); 4436 4437 #ifdef AHC_DEBUG 4438 printf(" %d instructions downloaded\n", downloaded); 4439 #endif 4440 } 4441 4442 static int 4443 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4444 int start_instr, int *skip_addr) 4445 { 4446 const struct patch *cur_patch; 4447 const struct patch *last_patch; 4448 int num_patches; 4449 4450 num_patches = sizeof(patches)/sizeof(struct patch); 4451 last_patch = &patches[num_patches]; 4452 cur_patch = *start_patch; 4453 4454 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4455 4456 if (cur_patch->patch_func(ahc) == 0) { 4457 4458 /* Start rejecting code */ 4459 *skip_addr = start_instr + cur_patch->skip_instr; 4460 cur_patch += cur_patch->skip_patch; 4461 } else { 4462 /* Accepted this patch. Advance to the next 4463 * one and wait for our intruction pointer to 4464 * hit this point. 4465 */ 4466 cur_patch++; 4467 } 4468 } 4469 4470 *start_patch = cur_patch; 4471 if (start_instr < *skip_addr) 4472 /* Still skipping */ 4473 return (0); 4474 4475 return (1); 4476 } 4477 4478 static void 4479 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4480 { 4481 union ins_formats instr; 4482 struct ins_format1 *fmt1_ins; 4483 struct ins_format3 *fmt3_ins; 4484 u_int opcode; 4485 4486 /* Structure copy */ 4487 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4488 4489 instr.integer = le32toh(instr.integer); 4490 4491 fmt1_ins = &instr.format1; 4492 fmt3_ins = NULL; 4493 4494 /* Pull the opcode */ 4495 opcode = instr.format1.opcode; 4496 switch (opcode) { 4497 case AIC_OP_JMP: 4498 case AIC_OP_JC: 4499 case AIC_OP_JNC: 4500 case AIC_OP_CALL: 4501 case AIC_OP_JNE: 4502 case AIC_OP_JNZ: 4503 case AIC_OP_JE: 4504 case AIC_OP_JZ: 4505 { 4506 const struct patch *cur_patch; 4507 int address_offset; 4508 u_int address; 4509 int skip_addr; 4510 int i; 4511 4512 fmt3_ins = &instr.format3; 4513 address_offset = 0; 4514 address = fmt3_ins->address; 4515 cur_patch = patches; 4516 skip_addr = 0; 4517 4518 for (i = 0; i < address;) { 4519 4520 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4521 4522 if (skip_addr > i) { 4523 int end_addr; 4524 4525 end_addr = MIN(address, skip_addr); 4526 address_offset += end_addr - i; 4527 i = skip_addr; 4528 } else { 4529 i++; 4530 } 4531 } 4532 address -= address_offset; 4533 fmt3_ins->address = address; 4534 /* FALLTHROUGH */ 4535 } 4536 case AIC_OP_OR: 4537 case AIC_OP_AND: 4538 case AIC_OP_XOR: 4539 case AIC_OP_ADD: 4540 case AIC_OP_ADC: 4541 case AIC_OP_BMOV: 4542 if (fmt1_ins->parity != 0) { 4543 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4544 } 4545 fmt1_ins->parity = 0; 4546 /* FALLTHROUGH */ 4547 case AIC_OP_ROL: 4548 if ((ahc->features & AHC_ULTRA2) != 0) { 4549 int i, count; 4550 4551 /* Calculate odd parity for the instruction */ 4552 for (i = 0, count = 0; i < 31; i++) { 4553 u_int32_t mask; 4554 4555 mask = 0x01 << i; 4556 if ((instr.integer & mask) != 0) 4557 count++; 4558 } 4559 if ((count & 0x01) == 0) 4560 instr.format1.parity = 1; 4561 } else { 4562 /* Compress the instruction for older sequencers */ 4563 if (fmt3_ins != NULL) { 4564 instr.integer = 4565 fmt3_ins->immediate 4566 | (fmt3_ins->source << 8) 4567 | (fmt3_ins->address << 16) 4568 | (fmt3_ins->opcode << 25); 4569 } else { 4570 instr.integer = 4571 fmt1_ins->immediate 4572 | (fmt1_ins->source << 8) 4573 | (fmt1_ins->destination << 16) 4574 | (fmt1_ins->ret << 24) 4575 | (fmt1_ins->opcode << 25); 4576 } 4577 } 4578 instr.integer = htole32(instr.integer); 4579 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4580 break; 4581 default: 4582 panic("Unknown opcode encountered in seq program"); 4583 break; 4584 } 4585 } 4586 4587 static void 4588 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4589 { 4590 4591 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4592 struct scb *scbp; 4593 4594 scb->flags |= SCB_RECOVERY_SCB; 4595 4596 /* 4597 * Take all queued, but not sent SCBs out of the equation. 4598 * Also ensure that no new CCBs are queued to us while we 4599 * try to fix this problem. 4600 */ 4601 ahc->queue_blocked = 1; 4602 4603 /* 4604 * Go through all of our pending SCBs and remove 4605 * any scheduled timeouts for them. We will reschedule 4606 * them after we've successfully fixed this problem. 4607 */ 4608 scbp = ahc->pending_ccbs.lh_first; 4609 while (scbp != NULL) { 4610 callout_stop(&scbp->xs->xs_callout); 4611 scbp = scbp->plinks.le_next; 4612 } 4613 } 4614 } 4615 4616 static void 4617 ahc_timeout(void *arg) 4618 { 4619 struct scb *scb; 4620 struct ahc_softc *ahc; 4621 int s, found; 4622 u_int last_phase; 4623 int target; 4624 int lun; 4625 int i; 4626 char channel; 4627 4628 scb = (struct scb *)arg; 4629 ahc = (struct ahc_softc *)scb->xs->sc_link->adapter_softc; 4630 4631 s = splbio(); 4632 4633 /* 4634 * Ensure that the card doesn't do anything 4635 * behind our back. Also make sure that we 4636 * didn't "just" miss an interrupt that would 4637 * affect this timeout. 4638 */ 4639 do { 4640 ahc_intr(ahc); 4641 pause_sequencer(ahc); 4642 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4643 4644 if ((scb->flags & SCB_ACTIVE) == 0) { 4645 /* Previous timeout took care of me already */ 4646 printf("Timedout SCB handled by another timeout\n"); 4647 unpause_sequencer(ahc); 4648 splx(s); 4649 return; 4650 } 4651 4652 target = SCB_TARGET(scb); 4653 channel = SCB_CHANNEL(scb); 4654 lun = SCB_LUN(scb); 4655 4656 scsi_print_addr(scb->xs->sc_link); 4657 printf("SCB %x - timed out ", scb->hscb->tag); 4658 /* 4659 * Take a snapshot of the bus state and print out 4660 * some information so we can track down driver bugs. 4661 */ 4662 last_phase = ahc_inb(ahc, LASTPHASE); 4663 4664 for (i = 0; i < num_phases; i++) { 4665 if (last_phase == phase_table[i].phase) 4666 break; 4667 } 4668 printf("%s", phase_table[i].phasemsg); 4669 4670 printf(", SEQADDR == 0x%x\n", 4671 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4672 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4673 4674 #ifdef AHC_DEBUG 4675 ahc_print_scb(scb); 4676 #endif 4677 4678 #if 0 4679 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4680 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4681 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4682 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4683 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4684 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4685 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4686 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4687 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4688 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4689 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4690 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4691 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4692 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4693 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4694 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4695 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4696 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4697 if (scb->sg_count > 0) { 4698 for (i = 0; i < scb->sg_count; i++) { 4699 printf("sg[%d] - Addr 0x%x : Length %d\n", 4700 i, 4701 le32toh(scb->sg_list[i].addr), 4702 le32toh(scb->sg_list[i].len)); 4703 } 4704 } 4705 #endif 4706 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4707 /* 4708 * Been down this road before. 4709 * Do a full bus reset. 4710 */ 4711 bus_reset: 4712 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4713 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4714 printf("%s: Issued Channel %c Bus Reset. " 4715 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4716 } else { 4717 /* 4718 * If we are a target, transition to bus free and report 4719 * the timeout. 4720 * 4721 * The target/initiator that is holding up the bus may not 4722 * be the same as the one that triggered this timeout 4723 * (different commands have different timeout lengths). 4724 * If the bus is idle and we are actiing as the initiator 4725 * for this request, queue a BDR message to the timed out 4726 * target. Otherwise, if the timed out transaction is 4727 * active: 4728 * Initiator transaction: 4729 * Stuff the message buffer with a BDR message and assert 4730 * ATN in the hopes that the target will let go of the bus 4731 * and go to the mesgout phase. If this fails, we'll 4732 * get another timeout 2 seconds later which will attempt 4733 * a bus reset. 4734 * 4735 * Target transaction: 4736 * Transition to BUS FREE and report the error. 4737 * It's good to be the target! 4738 */ 4739 u_int active_scb_index; 4740 4741 active_scb_index = ahc_inb(ahc, SCB_TAG); 4742 4743 if (last_phase != P_BUSFREE 4744 && (active_scb_index < ahc->scb_data->numscbs)) { 4745 struct scb *active_scb; 4746 4747 /* 4748 * If the active SCB is not from our device, 4749 * assume that another device is hogging the bus 4750 * and wait for it's timeout to expire before 4751 * taking additional action. 4752 */ 4753 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4754 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4755 u_int newtimeout; 4756 4757 scsi_print_addr(scb->xs->sc_link); 4758 printf("Other SCB Timeout%s", 4759 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4760 ? " again\n" : "\n"); 4761 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4762 newtimeout = MAX(active_scb->xs->timeout, 4763 scb->xs->timeout); 4764 callout_reset(&scb->xs->xs_callout, 4765 (newtimeout * hz) / 1000, 4766 ahc_timeout, scb); 4767 splx(s); 4768 return; 4769 } 4770 4771 /* It's us */ 4772 if ((scb->hscb->control & TARGET_SCB) != 0) { 4773 4774 /* 4775 * Send back any queued up transactions 4776 * and properly record the error condition. 4777 */ 4778 ahc_freeze_devq(ahc, scb->xs->sc_link); 4779 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4780 ahc_freeze_ccb(scb); 4781 ahc_done(ahc, scb); 4782 4783 /* Will clear us from the bus */ 4784 restart_sequencer(ahc); 4785 return; 4786 } 4787 4788 ahc_set_recoveryscb(ahc, active_scb); 4789 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4790 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4791 scsi_print_addr(active_scb->xs->sc_link); 4792 printf("BDR message in message buffer\n"); 4793 active_scb->flags |= SCB_DEVICE_RESET; 4794 callout_reset(&active_scb->xs->xs_callout, 4795 2 * hz, ahc_timeout, active_scb); 4796 unpause_sequencer(ahc); 4797 } else { 4798 int disconnected; 4799 4800 /* XXX Shouldn't panic. Just punt instead */ 4801 if ((scb->hscb->control & TARGET_SCB) != 0) 4802 panic("Timed-out target SCB but bus idle"); 4803 4804 if (last_phase != P_BUSFREE 4805 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4806 /* XXX What happened to the SCB? */ 4807 /* Hung target selection. Goto busfree */ 4808 printf("%s: Hung target selection\n", 4809 ahc_name(ahc)); 4810 restart_sequencer(ahc); 4811 return; 4812 } 4813 4814 if (ahc_search_qinfifo(ahc, target, channel, lun, 4815 scb->hscb->tag, ROLE_INITIATOR, 4816 /*status*/0, SEARCH_COUNT) > 0) { 4817 disconnected = FALSE; 4818 } else { 4819 disconnected = TRUE; 4820 } 4821 4822 if (disconnected) { 4823 u_int active_scb; 4824 4825 ahc_set_recoveryscb(ahc, scb); 4826 /* 4827 * Simply set the MK_MESSAGE control bit. 4828 */ 4829 scb->hscb->control |= MK_MESSAGE; 4830 scb->flags |= SCB_QUEUED_MSG 4831 | SCB_DEVICE_RESET; 4832 4833 /* 4834 * Mark the cached copy of this SCB in the 4835 * disconnected list too, so that a reconnect 4836 * at this point causes a BDR or abort. 4837 */ 4838 active_scb = ahc_inb(ahc, SCBPTR); 4839 if (ahc_search_disc_list(ahc, target, 4840 channel, lun, 4841 scb->hscb->tag, 4842 /*stop_on_first*/TRUE, 4843 /*remove*/FALSE, 4844 /*save_state*/FALSE)) { 4845 u_int scb_control; 4846 4847 scb_control = ahc_inb(ahc, SCB_CONTROL); 4848 scb_control |= MK_MESSAGE; 4849 ahc_outb(ahc, SCB_CONTROL, scb_control); 4850 } 4851 ahc_outb(ahc, SCBPTR, active_scb); 4852 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4853 /*unbusy*/TRUE); 4854 4855 /* 4856 * Actually re-queue this SCB in case we can 4857 * select the device before it reconnects. 4858 * Clear out any entries in the QINFIFO first 4859 * so we are the next SCB for this target 4860 * to run. 4861 */ 4862 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4863 channel, SCB_LUN(scb), 4864 SCB_LIST_NULL, 4865 ROLE_INITIATOR, 4866 SCB_REQUEUE, 4867 SEARCH_COMPLETE); 4868 scsi_print_addr(scb->xs->sc_link); 4869 printf("Queuing a BDR SCB\n"); 4870 ahc->qinfifo[ahc->qinfifonext++] = 4871 scb->hscb->tag; 4872 4873 bus_dmamap_sync(ahc->parent_dmat, 4874 ahc->shared_data_dmamap, 4875 QINFIFO_OFFSET * 256, 256, 4876 BUS_DMASYNC_PREWRITE); 4877 4878 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4879 ahc_outb(ahc, HNSCB_QOFF, 4880 ahc->qinfifonext); 4881 } else { 4882 ahc_outb(ahc, KERNEL_QINPOS, 4883 ahc->qinfifonext); 4884 } 4885 callout_reset(&scb->xs->xs_callout, 2 * hz, 4886 ahc_timeout, scb); 4887 unpause_sequencer(ahc); 4888 } else { 4889 /* Go "immediatly" to the bus reset */ 4890 /* This shouldn't happen */ 4891 ahc_set_recoveryscb(ahc, scb); 4892 scsi_print_addr(scb->xs->sc_link); 4893 printf("SCB %x: Immediate reset. " 4894 "Flags = 0x%x\n", scb->hscb->tag, 4895 scb->flags); 4896 goto bus_reset; 4897 } 4898 } 4899 } 4900 splx(s); 4901 } 4902 4903 static int 4904 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4905 int lun, u_int tag, role_t role, scb_flag status, 4906 ahc_search_action action) 4907 { 4908 struct scb *scbp; 4909 u_int8_t qinpos; 4910 u_int8_t qintail; 4911 int found; 4912 4913 qinpos = ahc_inb(ahc, QINPOS); 4914 qintail = ahc->qinfifonext; 4915 found = 0; 4916 4917 /* 4918 * Start with an empty queue. Entries that are not chosen 4919 * for removal will be re-added to the queue as we go. 4920 */ 4921 ahc->qinfifonext = qinpos; 4922 4923 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4924 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4925 4926 while (qinpos != qintail) { 4927 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4928 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4929 /* 4930 * We found an scb that needs to be removed. 4931 */ 4932 switch (action) { 4933 case SEARCH_COMPLETE: 4934 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4935 scbp->flags |= status; 4936 scbp->xs->error = XS_NOERROR; 4937 } 4938 ahc_freeze_ccb(scbp); 4939 ahc_done(ahc, scbp); 4940 break; 4941 case SEARCH_COUNT: 4942 ahc->qinfifo[ahc->qinfifonext++] = 4943 scbp->hscb->tag; 4944 break; 4945 case SEARCH_REMOVE: 4946 break; 4947 } 4948 found++; 4949 } else { 4950 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4951 } 4952 qinpos++; 4953 } 4954 4955 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4956 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4957 4958 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4959 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4960 } else { 4961 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4962 } 4963 4964 return (found); 4965 } 4966 4967 /* 4968 * Abort all SCBs that match the given description (target/channel/lun/tag), 4969 * setting their status to the passed in status if the status has not already 4970 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4971 * is paused before it is called. 4972 */ 4973 static int 4974 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4975 int lun, u_int tag, role_t role, int status) 4976 { 4977 struct scb *scbp; 4978 u_int active_scb; 4979 int i; 4980 int found; 4981 4982 /* restore this when we're done */ 4983 active_scb = ahc_inb(ahc, SCBPTR); 4984 4985 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4986 role, SCB_REQUEUE, SEARCH_COMPLETE); 4987 4988 /* 4989 * Search waiting for selection list. 4990 */ 4991 { 4992 u_int8_t next, prev; 4993 4994 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4995 prev = SCB_LIST_NULL; 4996 4997 while (next != SCB_LIST_NULL) { 4998 u_int8_t scb_index; 4999 5000 ahc_outb(ahc, SCBPTR, next); 5001 scb_index = ahc_inb(ahc, SCB_TAG); 5002 if (scb_index >= ahc->scb_data->numscbs) { 5003 panic("Waiting List inconsistency. " 5004 "SCB index == %d, yet numscbs == %d.", 5005 scb_index, ahc->scb_data->numscbs); 5006 } 5007 scbp = &ahc->scb_data->scbarray[scb_index]; 5008 if (ahc_match_scb(scbp, target, channel, 5009 lun, SCB_LIST_NULL, role)) { 5010 5011 next = ahc_abort_wscb(ahc, next, prev); 5012 } else { 5013 5014 prev = next; 5015 next = ahc_inb(ahc, SCB_NEXT); 5016 } 5017 } 5018 } 5019 /* 5020 * Go through the disconnected list and remove any entries we 5021 * have queued for completion, 0'ing their control byte too. 5022 * We save the active SCB and restore it ourselves, so there 5023 * is no reason for this search to restore it too. 5024 */ 5025 ahc_search_disc_list(ahc, target, channel, lun, tag, 5026 /*stop_on_first*/FALSE, /*remove*/TRUE, 5027 /*save_state*/FALSE); 5028 5029 /* 5030 * Go through the hardware SCB array looking for commands that 5031 * were active but not on any list. 5032 */ 5033 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 5034 u_int scbid; 5035 5036 ahc_outb(ahc, SCBPTR, i); 5037 scbid = ahc_inb(ahc, SCB_TAG); 5038 scbp = &ahc->scb_data->scbarray[scbid]; 5039 if (scbid < ahc->scb_data->numscbs 5040 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5041 ahc_add_curscb_to_free_list(ahc); 5042 } 5043 5044 /* 5045 * Go through the pending CCB list and look for 5046 * commands for this target that are still active. 5047 * These are other tagged commands that were 5048 * disconnected when the reset occured. 5049 */ 5050 { 5051 struct scb *scb; 5052 5053 scb = ahc->pending_ccbs.lh_first; 5054 while (scb != NULL) { 5055 scbp = scb; 5056 scb = scb->plinks.le_next; 5057 if (ahc_match_scb(scbp, target, channel, 5058 lun, tag, role)) { 5059 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5060 ahcsetccbstatus(scbp->xs, status); 5061 ahc_freeze_ccb(scbp); 5062 ahc_done(ahc, scbp); 5063 found++; 5064 } 5065 } 5066 } 5067 ahc_outb(ahc, SCBPTR, active_scb); 5068 return found; 5069 } 5070 5071 static int 5072 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5073 int lun, u_int tag, int stop_on_first, int remove, 5074 int save_state) 5075 { 5076 struct scb *scbp; 5077 u_int next; 5078 u_int prev; 5079 u_int count; 5080 u_int active_scb; 5081 5082 count = 0; 5083 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5084 prev = SCB_LIST_NULL; 5085 5086 if (save_state) { 5087 /* restore this when we're done */ 5088 active_scb = ahc_inb(ahc, SCBPTR); 5089 } else 5090 /* Silence compiler */ 5091 active_scb = SCB_LIST_NULL; 5092 5093 while (next != SCB_LIST_NULL) { 5094 u_int scb_index; 5095 5096 ahc_outb(ahc, SCBPTR, next); 5097 scb_index = ahc_inb(ahc, SCB_TAG); 5098 if (scb_index >= ahc->scb_data->numscbs) { 5099 panic("Disconnected List inconsistency. " 5100 "SCB index == %d, yet numscbs == %d.", 5101 scb_index, ahc->scb_data->numscbs); 5102 } 5103 scbp = &ahc->scb_data->scbarray[scb_index]; 5104 if (ahc_match_scb(scbp, target, channel, lun, 5105 tag, ROLE_INITIATOR)) { 5106 count++; 5107 if (remove) { 5108 next = 5109 ahc_rem_scb_from_disc_list(ahc, prev, next); 5110 } else { 5111 prev = next; 5112 next = ahc_inb(ahc, SCB_NEXT); 5113 } 5114 if (stop_on_first) 5115 break; 5116 } else { 5117 prev = next; 5118 next = ahc_inb(ahc, SCB_NEXT); 5119 } 5120 } 5121 if (save_state) 5122 ahc_outb(ahc, SCBPTR, active_scb); 5123 return (count); 5124 } 5125 5126 static u_int 5127 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5128 { 5129 u_int next; 5130 5131 ahc_outb(ahc, SCBPTR, scbptr); 5132 next = ahc_inb(ahc, SCB_NEXT); 5133 5134 ahc_outb(ahc, SCB_CONTROL, 0); 5135 5136 ahc_add_curscb_to_free_list(ahc); 5137 5138 if (prev != SCB_LIST_NULL) { 5139 ahc_outb(ahc, SCBPTR, prev); 5140 ahc_outb(ahc, SCB_NEXT, next); 5141 } else 5142 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5143 5144 return (next); 5145 } 5146 5147 static void 5148 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5149 { 5150 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5151 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5152 5153 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5154 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5155 } 5156 5157 /* 5158 * Manipulate the waiting for selection list and return the 5159 * scb that follows the one that we remove. 5160 */ 5161 static u_int 5162 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5163 { 5164 u_int curscb, next; 5165 5166 /* 5167 * Select the SCB we want to abort and 5168 * pull the next pointer out of it. 5169 */ 5170 curscb = ahc_inb(ahc, SCBPTR); 5171 ahc_outb(ahc, SCBPTR, scbpos); 5172 next = ahc_inb(ahc, SCB_NEXT); 5173 5174 /* Clear the necessary fields */ 5175 ahc_outb(ahc, SCB_CONTROL, 0); 5176 5177 ahc_add_curscb_to_free_list(ahc); 5178 5179 /* update the waiting list */ 5180 if (prev == SCB_LIST_NULL) { 5181 /* First in the list */ 5182 ahc_outb(ahc, WAITING_SCBH, next); 5183 5184 /* 5185 * Ensure we aren't attempting to perform 5186 * selection for this entry. 5187 */ 5188 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5189 } else { 5190 /* 5191 * Select the scb that pointed to us 5192 * and update its next pointer. 5193 */ 5194 ahc_outb(ahc, SCBPTR, prev); 5195 ahc_outb(ahc, SCB_NEXT, next); 5196 } 5197 5198 /* 5199 * Point us back at the original scb position. 5200 */ 5201 ahc_outb(ahc, SCBPTR, curscb); 5202 return next; 5203 } 5204 5205 static void 5206 ahc_clear_intstat(struct ahc_softc *ahc) 5207 { 5208 /* Clear any interrupt conditions this may have caused */ 5209 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5210 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5211 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5212 CLRREQINIT); 5213 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5214 } 5215 5216 static void 5217 ahc_reset_current_bus(struct ahc_softc *ahc) 5218 { 5219 u_int8_t scsiseq; 5220 5221 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5222 scsiseq = ahc_inb(ahc, SCSISEQ); 5223 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5224 DELAY(AHC_BUSRESET_DELAY); 5225 /* Turn off the bus reset */ 5226 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5227 5228 ahc_clear_intstat(ahc); 5229 5230 /* Re-enable reset interrupts */ 5231 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5232 } 5233 5234 static int 5235 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5236 { 5237 u_int initiator, target, max_scsiid; 5238 u_int sblkctl; 5239 u_int our_id; 5240 int found; 5241 int restart_needed; 5242 char cur_channel; 5243 5244 ahc->pending_device = NULL; 5245 5246 pause_sequencer(ahc); 5247 5248 /* 5249 * Run our command complete fifos to ensure that we perform 5250 * completion processing on any commands that 'completed' 5251 * before the reset occurred. 5252 */ 5253 ahc_run_qoutfifo(ahc); 5254 5255 /* 5256 * Reset the bus if we are initiating this reset 5257 */ 5258 sblkctl = ahc_inb(ahc, SBLKCTL); 5259 cur_channel = 'A'; 5260 if ((ahc->features & AHC_TWIN) != 0 5261 && ((sblkctl & SELBUSB) != 0)) 5262 cur_channel = 'B'; 5263 if (cur_channel != channel) { 5264 /* Case 1: Command for another bus is active 5265 * Stealthily reset the other bus without 5266 * upsetting the current bus. 5267 */ 5268 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5269 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5270 ahc_outb(ahc, SCSISEQ, 5271 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5272 if (initiate_reset) 5273 ahc_reset_current_bus(ahc); 5274 ahc_clear_intstat(ahc); 5275 ahc_outb(ahc, SBLKCTL, sblkctl); 5276 restart_needed = FALSE; 5277 } else { 5278 /* Case 2: A command from this bus is active or we're idle */ 5279 ahc_clear_msg_state(ahc); 5280 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5281 ahc_outb(ahc, SCSISEQ, 5282 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5283 if (initiate_reset) 5284 ahc_reset_current_bus(ahc); 5285 ahc_clear_intstat(ahc); 5286 5287 /* 5288 * Since we are going to restart the sequencer, avoid 5289 * a race in the sequencer that could cause corruption 5290 * of our Q pointers by starting over from index 0. 5291 */ 5292 ahc->qoutfifonext = 0; 5293 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5294 ahc_outb(ahc, SDSCB_QOFF, 0); 5295 else 5296 ahc_outb(ahc, QOUTPOS, 0); 5297 restart_needed = TRUE; 5298 } 5299 5300 /* 5301 * Clean up all the state information for the 5302 * pending transactions on this bus. 5303 */ 5304 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5305 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5306 ROLE_UNKNOWN, XS_RESET); 5307 if (channel == 'B') { 5308 our_id = ahc->our_id_b; 5309 } else { 5310 our_id = ahc->our_id; 5311 } 5312 5313 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5314 5315 /* 5316 * Revert to async/narrow transfers until we renegotiate. 5317 */ 5318 for (target = 0; target <= max_scsiid; target++) { 5319 5320 if (ahc->enabled_targets[target] == NULL) 5321 continue; 5322 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5323 struct ahc_devinfo devinfo; 5324 5325 ahc_compile_devinfo(&devinfo, target, initiator, 5326 AHC_LUN_WILDCARD, 5327 channel, ROLE_UNKNOWN); 5328 ahc_set_width(ahc, &devinfo, 5329 MSG_EXT_WDTR_BUS_8_BIT, 5330 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5331 ahc_set_syncrate(ahc, &devinfo, 5332 /*syncrate*/NULL, /*period*/0, 5333 /*offset*/0, AHC_TRANS_CUR, 5334 /*paused*/TRUE, FALSE); 5335 } 5336 } 5337 5338 if (restart_needed) 5339 restart_sequencer(ahc); 5340 else 5341 unpause_sequencer(ahc); 5342 return found; 5343 } 5344 5345 static int 5346 ahc_match_scb(struct scb *scb, int target, char channel, 5347 int lun, u_int tag, role_t role) 5348 { 5349 int targ = SCB_TARGET(scb); 5350 char chan = SCB_CHANNEL(scb); 5351 int slun = SCB_LUN(scb); 5352 int match; 5353 5354 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5355 if (match != 0) 5356 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5357 if (match != 0) 5358 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5359 5360 return match; 5361 } 5362 5363 static void 5364 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5365 { 5366 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5367 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5368 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5369 ahc->msgout_buf[ahc->msgout_index++] = period; 5370 ahc->msgout_buf[ahc->msgout_index++] = offset; 5371 ahc->msgout_len += 5; 5372 } 5373 5374 static void 5375 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5376 { 5377 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5378 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5379 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5380 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5381 ahc->msgout_len += 4; 5382 } 5383 5384 static void 5385 ahc_calc_residual(struct scb *scb) 5386 { 5387 struct hardware_scb *hscb; 5388 5389 hscb = scb->hscb; 5390 5391 /* 5392 * If the disconnected flag is still set, this is bogus 5393 * residual information left over from a sequencer 5394 * pagin/pageout, so ignore this case. 5395 */ 5396 if ((scb->hscb->control & DISCONNECTED) == 0) { 5397 u_int32_t resid; 5398 int resid_sgs; 5399 int sg; 5400 5401 /* 5402 * Remainder of the SG where the transfer 5403 * stopped. 5404 */ 5405 resid = (hscb->residual_data_count[2] << 16) 5406 | (hscb->residual_data_count[1] <<8) 5407 | (hscb->residual_data_count[0]); 5408 5409 /* 5410 * Add up the contents of all residual 5411 * SG segments that are after the SG where 5412 * the transfer stopped. 5413 */ 5414 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5415 sg = scb->sg_count - resid_sgs; 5416 while (resid_sgs > 0) { 5417 5418 resid += le32toh(scb->sg_list[sg].len); 5419 sg++; 5420 resid_sgs--; 5421 } 5422 scb->xs->resid = resid; 5423 } 5424 5425 /* 5426 * Clean out the residual information in this SCB for its 5427 * next consumer. 5428 */ 5429 hscb->residual_SG_count = 0; 5430 5431 #ifdef AHC_DEBUG 5432 if (ahc_debug & AHC_SHOWMISC) { 5433 scsi_print_addr(scb->xs->sc_link); 5434 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5435 } 5436 #endif 5437 } 5438 5439 static void 5440 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5441 { 5442 struct scb *scb; 5443 int pending_ccb_count; 5444 int i; 5445 u_int saved_scbptr; 5446 5447 /* 5448 * Traverse the pending SCB list and ensure that all of the 5449 * SCBs there have the proper settings. 5450 */ 5451 scb = LIST_FIRST(&ahc->pending_ccbs); 5452 pending_ccb_count = 0; 5453 while (scb != NULL) { 5454 struct ahc_devinfo devinfo; 5455 struct scsipi_xfer *xs; 5456 struct scb *pending_scb; 5457 struct hardware_scb *pending_hscb; 5458 struct ahc_initiator_tinfo *tinfo; 5459 struct tmode_tstate *tstate; 5460 u_int our_id, remote_id; 5461 5462 xs = scb->xs; 5463 pending_scb = scb; 5464 pending_hscb = pending_scb->hscb; 5465 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5466 ? ahc->our_id_b : ahc->our_id; 5467 remote_id = xs->sc_link->scsipi_scsi.target; 5468 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5469 SCB_LUN(pending_scb), 5470 SCB_CHANNEL(pending_scb), 5471 ROLE_UNKNOWN); 5472 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5473 our_id, remote_id, &tstate); 5474 pending_hscb->control &= ~ULTRAENB; 5475 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5476 pending_hscb->control |= ULTRAENB; 5477 pending_hscb->scsirate = tinfo->scsirate; 5478 pending_hscb->scsioffset = tinfo->current.offset; 5479 pending_ccb_count++; 5480 scb = LIST_NEXT(scb, plinks); 5481 } 5482 5483 if (pending_ccb_count == 0) 5484 return; 5485 5486 saved_scbptr = ahc_inb(ahc, SCBPTR); 5487 /* Ensure that the hscbs down on the card match the new information */ 5488 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5489 u_int scb_tag; 5490 5491 ahc_outb(ahc, SCBPTR, i); 5492 scb_tag = ahc_inb(ahc, SCB_TAG); 5493 if (scb_tag != SCB_LIST_NULL) { 5494 struct ahc_devinfo devinfo; 5495 struct scb *pending_scb; 5496 struct scsipi_xfer *xs; 5497 struct hardware_scb *pending_hscb; 5498 struct ahc_initiator_tinfo *tinfo; 5499 struct tmode_tstate *tstate; 5500 u_int our_id, remote_id; 5501 u_int control; 5502 5503 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5504 if (pending_scb->flags == SCB_FREE) 5505 continue; 5506 pending_hscb = pending_scb->hscb; 5507 xs = pending_scb->xs; 5508 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5509 ? ahc->our_id_b : ahc->our_id; 5510 remote_id = xs->sc_link->scsipi_scsi.target; 5511 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5512 SCB_LUN(pending_scb), 5513 SCB_CHANNEL(pending_scb), 5514 ROLE_UNKNOWN); 5515 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5516 our_id, remote_id, &tstate); 5517 control = ahc_inb(ahc, SCB_CONTROL); 5518 control &= ~ULTRAENB; 5519 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5520 control |= ULTRAENB; 5521 ahc_outb(ahc, SCB_CONTROL, control); 5522 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5523 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5524 } 5525 } 5526 ahc_outb(ahc, SCBPTR, saved_scbptr); 5527 } 5528 5529 #if UNUSED 5530 static void 5531 ahc_dump_targcmd(struct target_cmd *cmd) 5532 { 5533 u_int8_t *byte; 5534 u_int8_t *last_byte; 5535 int i; 5536 5537 byte = &cmd->initiator_channel; 5538 /* Debugging info for received commands */ 5539 last_byte = &cmd[1].initiator_channel; 5540 5541 i = 0; 5542 while (byte < last_byte) { 5543 if (i == 0) 5544 printf("\t"); 5545 printf("%#x", *byte++); 5546 i++; 5547 if (i == 8) { 5548 printf("\n"); 5549 i = 0; 5550 } else { 5551 printf(", "); 5552 } 5553 } 5554 } 5555 #endif 5556 5557 static void 5558 ahc_shutdown(void *arg) 5559 { 5560 struct ahc_softc *ahc; 5561 int i; 5562 u_int sxfrctl1_a, sxfrctl1_b; 5563 5564 ahc = (struct ahc_softc *)arg; 5565 5566 pause_sequencer(ahc); 5567 5568 /* 5569 * Preserve the value of the SXFRCTL1 register for all channels. 5570 * It contains settings that affect termination and we don't want 5571 * to disturb the integrity of the bus during shutdown in case 5572 * we are in a multi-initiator setup. 5573 */ 5574 sxfrctl1_b = 0; 5575 if ((ahc->features & AHC_TWIN) != 0) { 5576 u_int sblkctl; 5577 5578 sblkctl = ahc_inb(ahc, SBLKCTL); 5579 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5580 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5581 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5582 } 5583 5584 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5585 5586 /* This will reset most registers to 0, but not all */ 5587 ahc_reset(ahc); 5588 5589 if ((ahc->features & AHC_TWIN) != 0) { 5590 u_int sblkctl; 5591 5592 sblkctl = ahc_inb(ahc, SBLKCTL); 5593 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5594 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5595 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5596 } 5597 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5598 5599 ahc_outb(ahc, SCSISEQ, 0); 5600 ahc_outb(ahc, SXFRCTL0, 0); 5601 ahc_outb(ahc, DSPCISTATUS, 0); 5602 5603 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5604 ahc_outb(ahc, i, 0); 5605 } 5606 5607 #if defined(AHC_DEBUG) && 0 5608 static void 5609 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5610 { 5611 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5612 5613 printf("\tcurrent:\n"); 5614 printf("\t\twidth %u period %u offset %u flags %x\n", 5615 tinfo->current.width, tinfo->current.period, 5616 tinfo->current.offset, tinfo->current.ppr_flags); 5617 5618 printf("\tgoal:\n"); 5619 printf("\t\twidth %u period %u offset %u flags %x\n", 5620 tinfo->goal.width, tinfo->goal.period, 5621 tinfo->goal.offset, tinfo->goal.ppr_flags); 5622 5623 printf("\tuser:\n"); 5624 printf("\t\twidth %u period %u offset %u flags %x\n", 5625 tinfo->user.width, tinfo->user.period, 5626 tinfo->user.offset, tinfo->user.ppr_flags); 5627 } 5628 #endif 5629 5630 #ifndef AHC_NO_TAGS 5631 static void 5632 ahc_check_tags(struct ahc_softc *ahc, struct scsipi_xfer *xs) 5633 { 5634 struct scsipi_inquiry_data *inq; 5635 struct ahc_devinfo devinfo; 5636 struct tmode_tstate *tstate; 5637 int target_id, our_id; 5638 char channel; 5639 5640 if (xs->cmd->opcode != INQUIRY || xs->error != XS_NOERROR) 5641 return; 5642 5643 if (xs->sc_link->quirks & SDEV_NOTAG) 5644 return; 5645 5646 target_id = xs->sc_link->scsipi_scsi.target; 5647 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5648 channel = SIM_CHANNEL(ahc, xs->sc_link); 5649 5650 (void)ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); 5651 ahc_compile_devinfo(&devinfo, our_id, target_id, 5652 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5653 5654 if (tstate->tagdisable & devinfo.target_mask) 5655 return; 5656 5657 /* 5658 * Sneak a look at the results of the SCSI Inquiry 5659 * command and see if we can do Tagged queing. This 5660 * should really be done by the higher level drivers. 5661 */ 5662 inq = (struct scsipi_inquiry_data *)xs->data; 5663 if ((inq->flags3 & SID_CmdQue) && !(ahc_istagged_device(ahc, xs, 1))) { 5664 printf("%s: target %d using tagged queuing\n", 5665 ahc_name(ahc), xs->sc_link->scsipi_scsi.target); 5666 5667 ahc_set_tags(ahc, &devinfo, TRUE); 5668 5669 if (ahc->scb_data->maxhscbs >= 16 || 5670 (ahc->flags & AHC_PAGESCBS)) { 5671 /* Default to 16 tags */ 5672 xs->sc_link->openings = 16; 5673 } else { 5674 /* 5675 * Default to 4 tags on whimpy 5676 * cards that don't have much SCB 5677 * space and can't page. This prevents 5678 * a single device from hogging all 5679 * slots. We should really have a better 5680 * way of providing fairness. 5681 */ 5682 xs->sc_link->openings = 4; 5683 } 5684 } 5685 } 5686 #endif 5687 5688 static int 5689 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5690 int nocmdcheck) 5691 { 5692 #ifdef AHC_NO_TAGS 5693 return 0; 5694 #else 5695 char channel; 5696 u_int our_id, target; 5697 struct tmode_tstate *tstate; 5698 struct ahc_devinfo devinfo; 5699 5700 if (xs->sc_link->quirks & SDEV_NOTAG) 5701 return 0; 5702 5703 /* 5704 * XXX never do these commands with tags. Should really be 5705 * in a higher layer. 5706 */ 5707 if (!nocmdcheck && (xs->cmd->opcode == INQUIRY || 5708 xs->cmd->opcode == TEST_UNIT_READY || 5709 xs->cmd->opcode == REQUEST_SENSE)) 5710 return 0; 5711 5712 channel = SIM_CHANNEL(ahc, xs->sc_link); 5713 our_id = SIM_SCSI_ID(ahc, xs->sc_link); 5714 target = xs->sc_link->scsipi_scsi.target; 5715 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5716 5717 ahc_compile_devinfo(&devinfo, our_id, target, 5718 xs->sc_link->scsipi_scsi.lun, channel, ROLE_INITIATOR); 5719 5720 return (tstate->tagenable & devinfo.target_mask); 5721 #endif 5722 } 5723
Indexes created Wed Oct 01 19:09:53 GMT 2025