aic7xxx.c revision 1.70
1 /* $NetBSD: aic7xxx.c,v 1.70 2001/04/25 17:53:31 bouyer Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 #include "opt_ahc.h" 91 92 #include <sys/param.h> 93 #include <sys/kernel.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/malloc.h> 97 #include <sys/buf.h> 98 #include <sys/proc.h> 99 #include <sys/scsiio.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <uvm/uvm_extern.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define ALL_CHANNELS '\0' 118 #define ALL_TARGETS_MASK 0xFFFF 119 #define INITIATOR_WILDCARD (~0) 120 121 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 122 ((periph)->periph_channel->chan_channel == 1) 123 #define SIM_CHANNEL(ahc, periph) \ 124 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 125 #define SIM_SCSI_ID(ahc, periph) \ 126 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 127 #define SCB_IS_SCSIBUS_B(scb) \ 128 (((scb)->hscb->tcl & SELBUSB) != 0) 129 #define SCB_TARGET(scb) \ 130 (((scb)->hscb->tcl & TID) >> 4) 131 #define SCB_CHANNEL(scb) \ 132 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 133 #define SCB_LUN(scb) \ 134 ((scb)->hscb->tcl & LID) 135 #define SCB_TARGET_OFFSET(scb) \ 136 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 137 #define SCB_TARGET_MASK(scb) \ 138 (0x01 << (SCB_TARGET_OFFSET(scb))) 139 #define TCL_CHANNEL(ahc, tcl) \ 140 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 141 #define TCL_SCSI_ID(ahc, tcl) \ 142 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 143 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 144 #define TCL_LUN(tcl) ((tcl) & LID) 145 146 #define XS_TCL(ahc, xs) \ 147 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 148 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 149 | ((xs)->xs_periph->periph_lun & 0x07)) 150 151 const char * const ahc_chip_names[] = 152 { 153 "NONE", 154 "aic7770", 155 "aic7850", 156 "aic7855", 157 "aic7859", 158 "aic7860", 159 "aic7870", 160 "aic7880", 161 "aic7890/91", 162 "aic7892", 163 "aic7895", 164 "aic7896/97", 165 "aic7899" 166 }; 167 168 typedef enum { 169 ROLE_UNKNOWN, 170 ROLE_INITIATOR, 171 ROLE_TARGET 172 } role_t; 173 174 struct ahc_devinfo { 175 int our_scsiid; 176 int target_offset; 177 u_int16_t target_mask; 178 u_int8_t target; 179 u_int8_t lun; 180 char channel; 181 role_t role; /* 182 * Only guaranteed to be correct if not 183 * in the busfree state. 184 */ 185 }; 186 187 typedef enum { 188 SEARCH_COMPLETE, 189 SEARCH_COUNT, 190 SEARCH_REMOVE 191 } ahc_search_action; 192 193 #ifdef AHC_DEBUG 194 static int ahc_debug = AHC_DEBUG; 195 #endif 196 197 static int ahcinitscbdata(struct ahc_softc *); 198 static void ahcfiniscbdata(struct ahc_softc *); 199 200 #if UNUSED 201 static void ahc_dump_targcmd(struct target_cmd *); 202 #endif 203 static void ahc_shutdown(void *arg); 204 static void ahc_action(struct scsipi_channel *, 205 scsipi_adapter_req_t, void *); 206 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 207 struct proc *); 208 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 209 static int ahc_poll(struct ahc_softc *, int); 210 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 211 struct scb *); 212 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 213 static void ahcallocscbs(struct ahc_softc *); 214 #if UNUSED 215 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 216 struct scb *); 217 #endif 218 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 219 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 220 char, role_t); 221 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 222 static void ahc_done(struct ahc_softc *, struct scb *); 223 static struct tmode_tstate * 224 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 225 #if UNUSED 226 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 227 #endif 228 static void ahc_handle_seqint(struct ahc_softc *, u_int); 229 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 230 static void ahc_build_transfer_msg(struct ahc_softc *, 231 struct ahc_devinfo *); 232 static void ahc_setup_initiator_msgout(struct ahc_softc *, 233 struct ahc_devinfo *, 234 struct scb *); 235 static void ahc_setup_target_msgin(struct ahc_softc *, 236 struct ahc_devinfo *); 237 static void ahc_clear_msg_state(struct ahc_softc *); 238 static void ahc_handle_message_phase(struct ahc_softc *, 239 struct scsipi_periph *); 240 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 241 242 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 243 struct ahc_devinfo *); 244 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 245 struct ahc_devinfo *); 246 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 247 int, char *, int); 248 #ifdef AHC_DUMP_SEQ 249 static void ahc_dumpseq(struct ahc_softc *); 250 #endif 251 static void ahc_loadseq(struct ahc_softc *); 252 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 253 int, int *); 254 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 255 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 256 #if defined(AHC_DEBUG) 257 static void ahc_print_scb(struct scb *); 258 #endif 259 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 260 role_t, scb_flag, ahc_search_action); 261 static int ahc_reset_channel(struct ahc_softc *, char, int); 262 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 263 role_t, int); 264 static int ahc_search_disc_list(struct ahc_softc *, int, 265 char, int, u_int, int, int, int); 266 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 267 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 268 static void ahc_clear_intstat(struct ahc_softc *); 269 static void ahc_reset_current_bus(struct ahc_softc *); 270 static const struct ahc_syncrate * 271 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 272 static const struct ahc_syncrate * 273 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 274 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 275 static void ahc_validate_offset(struct ahc_softc *, 276 const struct ahc_syncrate *, u_int *, int); 277 static void ahc_update_target_msg_request(struct ahc_softc *, 278 struct ahc_devinfo *, 279 struct ahc_initiator_tinfo *, 280 int, int); 281 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 282 const struct ahc_syncrate *, u_int, u_int, 283 u_int, int, int); 284 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 285 u_int, u_int, int, int); 286 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 287 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 288 289 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 290 291 static void ahc_calc_residual(struct scb *); 292 293 static void ahc_update_pending_syncrates(struct ahc_softc *); 294 295 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 296 297 static void ahc_timeout (void *); 298 static __inline int sequencer_paused(struct ahc_softc *); 299 static __inline void pause_sequencer(struct ahc_softc *); 300 static __inline void unpause_sequencer(struct ahc_softc *); 301 static void restart_sequencer(struct ahc_softc *); 302 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 303 304 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 305 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 306 307 static __inline void ahc_freeze_ccb(struct scb *); 308 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 309 static void ahc_run_qoutfifo(struct ahc_softc *); 310 311 static __inline struct ahc_initiator_tinfo * 312 ahc_fetch_transinfo(struct ahc_softc *, 313 char, u_int, u_int, 314 struct tmode_tstate **); 315 static void ahcfreescb(struct ahc_softc *, struct scb *); 316 static __inline struct scb *ahcgetscb(struct ahc_softc *); 317 318 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 319 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 320 int *, const char *, const char *); 321 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 322 caddr_t, bus_dma_segment_t *, int); 323 static void ahcminphys(struct buf *); 324 325 static __inline void ahc_swap_hscb(struct hardware_scb *); 326 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 327 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 328 329 #if defined(AHC_DEBUG) && 0 330 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 331 #endif 332 333 static __inline void 334 ahc_swap_hscb(struct hardware_scb *hscb) 335 { 336 hscb->SG_pointer = htole32(hscb->SG_pointer); 337 hscb->data = htole32(hscb->data); 338 hscb->datalen = htole32(hscb->datalen); 339 /* 340 * No need to swap cmdpointer; it's either 0 or set to 341 * cmdstore_busaddr, which is already swapped. 342 */ 343 } 344 345 static __inline void 346 ahc_swap_sg(struct ahc_dma_seg *sg) 347 { 348 sg->addr = htole32(sg->addr); 349 sg->len = htole32(sg->len); 350 } 351 352 static void 353 ahcminphys(bp) 354 struct buf *bp; 355 { 356 /* 357 * Even though the card can transfer up to 16megs per command 358 * we are limited by the number of segments in the dma segment 359 * list that we can hold. The worst case is that all pages are 360 * discontinuous physically, hense the "page per segment" limit 361 * enforced here. 362 */ 363 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 364 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 365 } 366 minphys(bp); 367 } 368 369 370 static __inline u_int32_t 371 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 372 { 373 return (ahc->scb_data->hscb_busaddr 374 + (sizeof(struct hardware_scb) * index)); 375 } 376 377 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 378 379 static __inline int 380 sequencer_paused(struct ahc_softc *ahc) 381 { 382 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 383 } 384 385 static __inline void 386 pause_sequencer(struct ahc_softc *ahc) 387 { 388 ahc_outb(ahc, HCNTRL, ahc->pause); 389 390 /* 391 * Since the sequencer can disable pausing in a critical section, we 392 * must loop until it actually stops. 393 */ 394 while (sequencer_paused(ahc) == 0) 395 ; 396 } 397 398 static __inline void 399 unpause_sequencer(struct ahc_softc *ahc) 400 { 401 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 402 ahc_outb(ahc, HCNTRL, ahc->unpause); 403 } 404 405 /* 406 * Restart the sequencer program from address zero 407 */ 408 static void 409 restart_sequencer(struct ahc_softc *ahc) 410 { 411 u_int i; 412 413 pause_sequencer(ahc); 414 415 /* 416 * Everytime we restart the sequencer, there 417 * is the possiblitity that we have restarted 418 * within a three instruction window where an 419 * SCB has been marked free but has not made it 420 * onto the free list. Since SCSI events(bus reset, 421 * unexpected bus free) will always freeze the 422 * sequencer, we cannot close this window. To 423 * avoid losing an SCB, we reconsitute the free 424 * list every time we restart the sequencer. 425 */ 426 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 427 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 428 429 ahc_outb(ahc, SCBPTR, i); 430 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 431 ahc_add_curscb_to_free_list(ahc); 432 } 433 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 434 unpause_sequencer(ahc); 435 } 436 437 static __inline u_int 438 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 439 { 440 u_int scbid; 441 442 scbid = ahc->untagged_scbs[tcl]; 443 if (unbusy) { 444 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 445 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 446 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 447 } 448 449 return (scbid); 450 } 451 452 static __inline void 453 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 454 { 455 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 456 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 457 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 458 } 459 460 static __inline int 461 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 462 { 463 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 464 } 465 466 static __inline void 467 ahc_freeze_ccb(struct scb *scb) 468 { 469 struct scsipi_xfer *xs = scb->xs; 470 471 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 472 scsipi_periph_freeze(xs->xs_periph, 1); 473 scb->flags |= SCB_FREEZE_QUEUE; 474 } 475 } 476 477 static __inline void 478 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 479 { 480 xs->error = status; 481 } 482 483 static __inline struct ahc_initiator_tinfo * 484 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 485 u_int remote_id, struct tmode_tstate **tstate) 486 { 487 /* 488 * Transfer data structures are stored from the perspective 489 * of the target role. Since the parameters for a connection 490 * in the initiator role to a given target are the same as 491 * when the roles are reversed, we pretend we are the target. 492 */ 493 if (channel == 'B') 494 our_id += 8; 495 *tstate = ahc->enabled_targets[our_id]; 496 return (&(*tstate)->transinfo[remote_id]); 497 } 498 499 static void 500 ahc_run_qoutfifo(struct ahc_softc *ahc) 501 { 502 struct scb *scb; 503 u_int scb_index; 504 505 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 506 256, BUS_DMASYNC_POSTREAD); 507 508 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 509 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 510 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 511 512 scb = &ahc->scb_data->scbarray[scb_index]; 513 if (scb_index >= ahc->scb_data->numscbs 514 || (scb->flags & SCB_ACTIVE) == 0) { 515 printf("%s: WARNING no command for scb %d " 516 "(cmdcmplt)\nQOUTPOS = %d\n", 517 ahc_name(ahc), scb_index, 518 ahc->qoutfifonext - 1); 519 continue; 520 } 521 522 /* 523 * Save off the residual 524 * if there is one. 525 */ 526 if (scb->hscb->residual_SG_count != 0) 527 ahc_calc_residual(scb); 528 else 529 scb->xs->resid = 0; 530 #ifdef AHC_DEBUG 531 if (ahc_debug & AHC_SHOWSCBS) { 532 scsipi_printaddr(scb->xs->xs_periph); 533 printf("run_qoutfifo: SCB %x complete\n", 534 scb->hscb->tag); 535 } 536 #endif 537 ahc_done(ahc, scb); 538 } 539 } 540 541 542 /* 543 * An scb (and hence an scb entry on the board) is put onto the 544 * free list. 545 */ 546 static void 547 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 548 { 549 struct hardware_scb *hscb; 550 int opri; 551 552 hscb = scb->hscb; 553 554 #ifdef AHC_DEBUG 555 if (ahc_debug & AHC_SHOWSCBALLOC) 556 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 557 #endif 558 559 opri = splbio(); 560 561 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 562 (scb->flags & SCB_RECOVERY_SCB) != 0) { 563 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 564 scsipi_channel_thaw(&ahc->sc_channel, 1); 565 if (ahc->features & AHC_TWIN) 566 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 567 } 568 569 /* Clean up for the next user */ 570 scb->flags = SCB_FREE; 571 hscb->control = 0; 572 hscb->status = 0; 573 574 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 575 576 splx(opri); 577 } 578 579 /* 580 * Get a free scb, either one already assigned to a hardware slot 581 * on the adapter or one that will require an SCB to be paged out before 582 * use. If there are none, see if we can allocate a new SCB. Otherwise 583 * either return an error or sleep. 584 */ 585 static __inline struct scb * 586 ahcgetscb(struct ahc_softc *ahc) 587 { 588 struct scb *scbp; 589 int opri;; 590 591 opri = splbio(); 592 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 593 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 594 } else { 595 ahcallocscbs(ahc); 596 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 597 if (scbp != NULL) 598 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 599 } 600 601 splx(opri); 602 603 #ifdef AHC_DEBUG 604 if (ahc_debug & AHC_SHOWSCBALLOC) { 605 if (scbp != NULL) 606 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 607 scbp->hscb->tag); 608 else 609 printf("%s: failed to allocate new SCB\n", 610 ahc_name(ahc)); 611 } 612 #endif 613 614 return (scbp); 615 } 616 617 static int 618 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 619 bus_dma_tag_t tag; 620 int size; 621 int flags; 622 bus_dmamap_t *mapp; 623 caddr_t *vaddr; 624 bus_addr_t *baddr; 625 bus_dma_segment_t *seg; 626 int *nseg; 627 const char *myname, *what; 628 { 629 int error, level = 0; 630 631 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 632 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 633 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 634 myname, what, error); 635 goto out; 636 } 637 level++; 638 639 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 640 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 641 printf("%s: failed to map DMA mem for %s, error = %d\n", 642 myname, what, error); 643 goto out; 644 } 645 level++; 646 647 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 648 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 649 printf("%s: failed to create DMA map for %s, error = %d\n", 650 myname, what, error); 651 goto out; 652 } 653 level++; 654 655 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 656 BUS_DMA_NOWAIT)) != 0) { 657 printf("%s: failed to load DMA map for %s, error = %d\n", 658 myname, what, error); 659 goto out; 660 } 661 662 *baddr = (*mapp)->dm_segs[0].ds_addr; 663 664 #ifdef AHC_DEBUG 665 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 666 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 667 *nseg, size); 668 #endif 669 670 return 0; 671 out: 672 switch (level) { 673 case 3: 674 bus_dmamap_destroy(tag, *mapp); 675 /* FALLTHROUGH */ 676 case 2: 677 bus_dmamem_unmap(tag, *vaddr, size); 678 /* FALLTHROUGH */ 679 case 1: 680 bus_dmamem_free(tag, seg, *nseg); 681 break; 682 default: 683 break; 684 } 685 686 return error; 687 } 688 689 static void 690 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 691 bus_dma_tag_t tag; 692 int size; 693 bus_dmamap_t map; 694 caddr_t vaddr; 695 bus_dma_segment_t *seg; 696 int nseg; 697 { 698 699 bus_dmamap_unload(tag, map); 700 bus_dmamap_destroy(tag, map); 701 bus_dmamem_unmap(tag, vaddr, size); 702 bus_dmamem_free(tag, seg, nseg); 703 } 704 705 char * 706 ahc_name(struct ahc_softc *ahc) 707 { 708 return (ahc->sc_dev.dv_xname); 709 } 710 711 #ifdef AHC_DEBUG 712 static void 713 ahc_print_scb(struct scb *scb) 714 { 715 struct hardware_scb *hscb = scb->hscb; 716 717 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 718 scb, 719 hscb->tag, 720 hscb->control, 721 hscb->tcl, 722 hscb->cmdlen, 723 (unsigned long)le32toh(hscb->cmdpointer)); 724 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 725 le32toh(hscb->datalen), 726 (unsigned long)(le32toh(hscb->data)), 727 hscb->SG_count, 728 (unsigned long)(le32toh(hscb->SG_pointer))); 729 printf(" sg_addr:%lx sg_len:%lu\n", 730 (unsigned long)(le32toh(scb->sg_list[0].addr)), 731 (unsigned long)(le32toh(scb->sg_list[0].len))); 732 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 733 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 734 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 735 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 736 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 737 } 738 #endif 739 740 static const struct { 741 u_int8_t errno; 742 const char *errmesg; 743 } hard_error[] = { 744 { ILLHADDR, "Illegal Host Access" }, 745 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 746 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 747 { SQPARERR, "Sequencer Parity Error" }, 748 { DPARERR, "Data-path Parity Error" }, 749 { MPARERR, "Scratch or SCB Memory Parity Error" }, 750 { PCIERRSTAT, "PCI Error detected" }, 751 { CIOPARERR, "CIOBUS Parity Error" }, 752 }; 753 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 754 755 static const struct { 756 u_int8_t phase; 757 u_int8_t mesg_out; /* Message response to parity errors */ 758 const char *phasemsg; 759 } phase_table[] = { 760 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 761 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 762 { P_COMMAND, MSG_NOOP, "in Command phase" }, 763 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 764 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 765 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 766 { P_BUSFREE, MSG_NOOP, "while idle" }, 767 { 0, MSG_NOOP, "in unknown phase" } 768 }; 769 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 770 771 /* 772 * Valid SCSIRATE values. (p. 3-17) 773 * Provides a mapping of tranfer periods in ns to the proper value to 774 * stick in the scsiscfr reg to use that transfer rate. 775 */ 776 #define AHC_SYNCRATE_DT 0 777 #define AHC_SYNCRATE_ULTRA2 1 778 #define AHC_SYNCRATE_ULTRA 3 779 #define AHC_SYNCRATE_FAST 6 780 static const struct ahc_syncrate ahc_syncrates[] = { 781 /* ultra2 fast/ultra period rate */ 782 { 0x42, 0x000, 9, "80.0" }, 783 { 0x03, 0x000, 10, "40.0" }, 784 { 0x04, 0x000, 11, "33.0" }, 785 { 0x05, 0x100, 12, "20.0" }, 786 { 0x06, 0x110, 15, "16.0" }, 787 { 0x07, 0x120, 18, "13.4" }, 788 { 0x08, 0x000, 25, "10.0" }, 789 { 0x19, 0x010, 31, "8.0" }, 790 { 0x1a, 0x020, 37, "6.67" }, 791 { 0x1b, 0x030, 43, "5.7" }, 792 { 0x1c, 0x040, 50, "5.0" }, 793 { 0x00, 0x050, 56, "4.4" }, 794 { 0x00, 0x060, 62, "4.0" }, 795 { 0x00, 0x070, 68, "3.6" }, 796 { 0x00, 0x000, 0, NULL } 797 }; 798 799 /* 800 * Allocate a controller structure for a new device and initialize it. 801 */ 802 int 803 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 804 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 805 ahc_flag flags) 806 { 807 struct scb_data *scb_data; 808 809 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 810 if (scb_data == NULL) { 811 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 812 return -1; 813 } 814 bzero(scb_data, sizeof (struct scb_data)); 815 LIST_INIT(&ahc->pending_ccbs); 816 ahc->tag = st; 817 ahc->bsh = sh; 818 ahc->parent_dmat = parent_dmat; 819 ahc->chip = chip; 820 ahc->features = features; 821 ahc->flags = flags; 822 ahc->scb_data = scb_data; 823 824 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 825 /* The IRQMS bit is only valid on VL and EISA chips */ 826 if ((ahc->chip & AHC_PCI) != 0) 827 ahc->unpause &= ~IRQMS; 828 ahc->pause = ahc->unpause | PAUSE; 829 return (0); 830 } 831 832 void 833 ahc_free(ahc) 834 struct ahc_softc *ahc; 835 { 836 ahcfiniscbdata(ahc); 837 if (ahc->init_level != 0) 838 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 839 ahc->shared_data_dmamap, ahc->qoutfifo, 840 &ahc->shared_data_seg, ahc->shared_data_nseg); 841 842 if (ahc->scb_data != NULL) 843 free(ahc->scb_data, M_DEVBUF); 844 if (ahc->bus_data != NULL) 845 free(ahc->bus_data, M_DEVBUF); 846 return; 847 } 848 849 static int 850 ahcinitscbdata(struct ahc_softc *ahc) 851 { 852 struct scb_data *scb_data; 853 int i; 854 855 scb_data = ahc->scb_data; 856 SLIST_INIT(&scb_data->free_scbs); 857 SLIST_INIT(&scb_data->sg_maps); 858 859 /* Allocate SCB resources */ 860 scb_data->scbarray = 861 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 862 M_DEVBUF, M_NOWAIT); 863 if (scb_data->scbarray == NULL) 864 return (ENOMEM); 865 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 866 867 /* Determine the number of hardware SCBs and initialize them */ 868 869 scb_data->maxhscbs = ahc_probe_scbs(ahc); 870 /* SCB 0 heads the free list */ 871 ahc_outb(ahc, FREE_SCBH, 0); 872 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 873 ahc_outb(ahc, SCBPTR, i); 874 875 /* Clear the control byte. */ 876 ahc_outb(ahc, SCB_CONTROL, 0); 877 878 /* Set the next pointer */ 879 ahc_outb(ahc, SCB_NEXT, i+1); 880 881 /* Make the tag number invalid */ 882 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 883 } 884 885 /* Make sure that the last SCB terminates the free list */ 886 ahc_outb(ahc, SCBPTR, i-1); 887 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 888 889 /* Ensure we clear the 0 SCB's control byte. */ 890 ahc_outb(ahc, SCBPTR, 0); 891 ahc_outb(ahc, SCB_CONTROL, 0); 892 893 scb_data->maxhscbs = i; 894 895 if (ahc->scb_data->maxhscbs == 0) 896 panic("%s: No SCB space found", ahc_name(ahc)); 897 898 /* 899 * Create our DMA tags. These tags define the kinds of device 900 * accessable memory allocations and memory mappings we will 901 * need to perform during normal operation. 902 * 903 * Unless we need to further restrict the allocation, we rely 904 * on the restrictions of the parent dmat, hence the common 905 * use of MAXADDR and MAXSIZE. 906 */ 907 908 if (ahc_createdmamem(ahc->parent_dmat, 909 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 910 &scb_data->hscb_dmamap, 911 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 912 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 913 "hardware SCB structures") < 0) 914 goto error_exit; 915 916 scb_data->init_level++; 917 918 if (ahc_createdmamem(ahc->parent_dmat, 919 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 920 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 921 &scb_data->sense_busaddr, &scb_data->sense_seg, 922 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 923 goto error_exit; 924 925 scb_data->init_level++; 926 927 /* Perform initial CCB allocation */ 928 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 929 ahcallocscbs(ahc); 930 931 if (scb_data->numscbs == 0) { 932 printf("%s: ahc_init_scb_data - " 933 "Unable to allocate initial scbs\n", 934 ahc_name(ahc)); 935 goto error_exit; 936 } 937 938 scb_data->init_level++; 939 940 /* 941 * Note that we were successfull 942 */ 943 return 0; 944 945 error_exit: 946 947 return ENOMEM; 948 } 949 950 static void 951 ahcfiniscbdata(struct ahc_softc *ahc) 952 { 953 struct scb_data *scb_data; 954 955 scb_data = ahc->scb_data; 956 957 switch (scb_data->init_level) { 958 default: 959 case 3: 960 { 961 struct sg_map_node *sg_map; 962 963 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 964 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 965 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 966 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 967 &sg_map->sg_dmasegs, sg_map->sg_nseg); 968 free(sg_map, M_DEVBUF); 969 } 970 } 971 /*FALLTHROUGH*/ 972 case 2: 973 ahc_freedmamem(ahc->parent_dmat, 974 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 975 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 976 &scb_data->sense_seg, scb_data->sense_nseg); 977 /*FALLTHROUGH*/ 978 case 1: 979 ahc_freedmamem(ahc->parent_dmat, 980 AHC_SCB_MAX * sizeof(struct hardware_scb), 981 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 982 &scb_data->hscb_seg, scb_data->hscb_nseg); 983 /*FALLTHROUGH*/ 984 } 985 if (scb_data->scbarray != NULL) 986 free(scb_data->scbarray, M_DEVBUF); 987 } 988 989 int 990 ahc_reset(struct ahc_softc *ahc) 991 { 992 u_int sblkctl; 993 int wait; 994 995 #ifdef AHC_DUMP_SEQ 996 if (ahc->init_level == 0) 997 ahc_dumpseq(ahc); 998 #endif 999 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1000 /* 1001 * Ensure that the reset has finished 1002 */ 1003 wait = 1000; 1004 do { 1005 DELAY(1000); 1006 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1007 1008 if (wait == 0) { 1009 printf("%s: WARNING - Failed chip reset! " 1010 "Trying to initialize anyway.\n", ahc_name(ahc)); 1011 } 1012 ahc_outb(ahc, HCNTRL, ahc->pause); 1013 1014 /* Determine channel configuration */ 1015 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1016 /* No Twin Channel PCI cards */ 1017 if ((ahc->chip & AHC_PCI) != 0) 1018 sblkctl &= ~SELBUSB; 1019 switch (sblkctl) { 1020 case 0: 1021 /* Single Narrow Channel */ 1022 break; 1023 case 2: 1024 /* Wide Channel */ 1025 ahc->features |= AHC_WIDE; 1026 break; 1027 case 8: 1028 /* Twin Channel */ 1029 ahc->features |= AHC_TWIN; 1030 break; 1031 default: 1032 printf(" Unsupported adapter type. Ignoring\n"); 1033 return(-1); 1034 } 1035 1036 return (0); 1037 } 1038 1039 /* 1040 * Called when we have an active connection to a target on the bus, 1041 * this function finds the nearest syncrate to the input period limited 1042 * by the capabilities of the bus connectivity of the target. 1043 */ 1044 static const struct ahc_syncrate * 1045 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1046 u_int maxsync; 1047 1048 if ((ahc->features & AHC_ULTRA2) != 0) { 1049 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1050 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1051 maxsync = AHC_SYNCRATE_ULTRA2; 1052 } else { 1053 maxsync = AHC_SYNCRATE_ULTRA; 1054 } 1055 } else if ((ahc->features & AHC_ULTRA) != 0) { 1056 maxsync = AHC_SYNCRATE_ULTRA; 1057 } else { 1058 maxsync = AHC_SYNCRATE_FAST; 1059 } 1060 return (ahc_find_syncrate(ahc, period, maxsync)); 1061 } 1062 1063 /* 1064 * Look up the valid period to SCSIRATE conversion in our table. 1065 * Return the period and offset that should be sent to the target 1066 * if this was the beginning of an SDTR. 1067 */ 1068 static const struct ahc_syncrate * 1069 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1070 { 1071 const struct ahc_syncrate *syncrate; 1072 1073 syncrate = &ahc_syncrates[maxsync]; 1074 while ((syncrate->rate != NULL) 1075 && ((ahc->features & AHC_ULTRA2) == 0 1076 || (syncrate->sxfr_u2 != 0))) { 1077 1078 if (*period <= syncrate->period) { 1079 /* 1080 * When responding to a target that requests 1081 * sync, the requested rate may fall between 1082 * two rates that we can output, but still be 1083 * a rate that we can receive. Because of this, 1084 * we want to respond to the target with 1085 * the same rate that it sent to us even 1086 * if the period we use to send data to it 1087 * is lower. Only lower the response period 1088 * if we must. 1089 */ 1090 if (syncrate == &ahc_syncrates[maxsync]) 1091 *period = syncrate->period; 1092 break; 1093 } 1094 syncrate++; 1095 } 1096 1097 if ((*period == 0) 1098 || (syncrate->rate == NULL) 1099 || ((ahc->features & AHC_ULTRA2) != 0 1100 && (syncrate->sxfr_u2 == 0))) { 1101 /* Use asynchronous transfers. */ 1102 *period = 0; 1103 syncrate = NULL; 1104 } 1105 return (syncrate); 1106 } 1107 1108 static u_int 1109 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1110 { 1111 const struct ahc_syncrate *syncrate; 1112 1113 if ((ahc->features & AHC_ULTRA2) != 0) 1114 scsirate &= SXFR_ULTRA2; 1115 else 1116 scsirate &= SXFR; 1117 1118 syncrate = &ahc_syncrates[maxsync]; 1119 while (syncrate->rate != NULL) { 1120 1121 if ((ahc->features & AHC_ULTRA2) != 0) { 1122 if (syncrate->sxfr_u2 == 0) 1123 break; 1124 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1125 return (syncrate->period); 1126 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1127 return (syncrate->period); 1128 } 1129 syncrate++; 1130 } 1131 return (0); /* async */ 1132 } 1133 1134 static void 1135 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1136 u_int *offset, int wide) 1137 { 1138 u_int maxoffset; 1139 1140 /* Limit offset to what we can do */ 1141 if (syncrate == NULL) { 1142 maxoffset = 0; 1143 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1144 maxoffset = MAX_OFFSET_ULTRA2; 1145 } else { 1146 if (wide) 1147 maxoffset = MAX_OFFSET_16BIT; 1148 else 1149 maxoffset = MAX_OFFSET_8BIT; 1150 } 1151 *offset = MIN(*offset, maxoffset); 1152 } 1153 1154 static void 1155 ahc_update_target_msg_request(struct ahc_softc *ahc, 1156 struct ahc_devinfo *devinfo, 1157 struct ahc_initiator_tinfo *tinfo, 1158 int force, int paused) 1159 { 1160 u_int targ_msg_req_orig; 1161 1162 targ_msg_req_orig = ahc->targ_msg_req; 1163 if (tinfo->current.period != tinfo->goal.period 1164 || tinfo->current.width != tinfo->goal.width 1165 || tinfo->current.offset != tinfo->goal.offset 1166 || (force 1167 && (tinfo->goal.period != 0 1168 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1169 ahc->targ_msg_req |= devinfo->target_mask; 1170 } else { 1171 ahc->targ_msg_req &= ~devinfo->target_mask; 1172 } 1173 1174 if (ahc->targ_msg_req != targ_msg_req_orig) { 1175 /* Update the message request bit for this target */ 1176 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1177 if (paused) { 1178 ahc_outb(ahc, TARGET_MSG_REQUEST, 1179 ahc->targ_msg_req & 0xFF); 1180 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1181 (ahc->targ_msg_req >> 8) & 0xFF); 1182 } else { 1183 ahc_outb(ahc, HS_MAILBOX, 1184 0x01 << HOST_MAILBOX_SHIFT); 1185 } 1186 } else { 1187 if (!paused) 1188 pause_sequencer(ahc); 1189 1190 ahc_outb(ahc, TARGET_MSG_REQUEST, 1191 ahc->targ_msg_req & 0xFF); 1192 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1193 (ahc->targ_msg_req >> 8) & 0xFF); 1194 1195 if (!paused) 1196 unpause_sequencer(ahc); 1197 } 1198 } 1199 } 1200 1201 static void 1202 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1203 const struct ahc_syncrate *syncrate, 1204 u_int period, u_int offset, u_int type, int paused, int done) 1205 { 1206 struct ahc_initiator_tinfo *tinfo; 1207 struct tmode_tstate *tstate; 1208 u_int old_period; 1209 u_int old_offset; 1210 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1211 1212 if (syncrate == NULL) { 1213 period = 0; 1214 offset = 0; 1215 } 1216 1217 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1218 devinfo->target, &tstate); 1219 old_period = tinfo->current.period; 1220 old_offset = tinfo->current.offset; 1221 1222 if ((type & AHC_TRANS_CUR) != 0 1223 && (old_period != period || old_offset != offset)) { 1224 u_int scsirate; 1225 1226 scsirate = tinfo->scsirate; 1227 if ((ahc->features & AHC_ULTRA2) != 0) { 1228 1229 /* XXX */ 1230 /* Force single edge until DT is fully implemented */ 1231 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1232 if (syncrate != NULL) 1233 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1234 1235 if (active) 1236 ahc_outb(ahc, SCSIOFFSET, offset); 1237 } else { 1238 1239 scsirate &= ~(SXFR|SOFS); 1240 /* 1241 * Ensure Ultra mode is set properly for 1242 * this target. 1243 */ 1244 tstate->ultraenb &= ~devinfo->target_mask; 1245 if (syncrate != NULL) { 1246 if (syncrate->sxfr & ULTRA_SXFR) { 1247 tstate->ultraenb |= 1248 devinfo->target_mask; 1249 } 1250 scsirate |= syncrate->sxfr & SXFR; 1251 scsirate |= offset & SOFS; 1252 } 1253 if (active) { 1254 u_int sxfrctl0; 1255 1256 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1257 sxfrctl0 &= ~FAST20; 1258 if (tstate->ultraenb & devinfo->target_mask) 1259 sxfrctl0 |= FAST20; 1260 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1261 } 1262 } 1263 if (active) 1264 ahc_outb(ahc, SCSIRATE, scsirate); 1265 1266 tinfo->scsirate = scsirate; 1267 tinfo->current.period = period; 1268 tinfo->current.offset = offset; 1269 1270 /* Update the syncrates in any pending scbs */ 1271 ahc_update_pending_syncrates(ahc); 1272 } 1273 1274 /* 1275 * Print messages if we're verbose and at the end of a negotiation 1276 * cycle. 1277 */ 1278 if (done) { 1279 if (offset != 0) { 1280 printf("%s: target %d synchronous at %sMHz, " 1281 "offset = 0x%x\n", ahc_name(ahc), 1282 devinfo->target, syncrate->rate, offset); 1283 } else { 1284 printf("%s: target %d using " 1285 "asynchronous transfers\n", 1286 ahc_name(ahc), devinfo->target); 1287 } 1288 } 1289 1290 if ((type & AHC_TRANS_GOAL) != 0) { 1291 tinfo->goal.period = period; 1292 tinfo->goal.offset = offset; 1293 } 1294 1295 if ((type & AHC_TRANS_USER) != 0) { 1296 tinfo->user.period = period; 1297 tinfo->user.offset = offset; 1298 } 1299 1300 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1301 /*force*/FALSE, 1302 paused); 1303 } 1304 1305 static void 1306 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1307 u_int width, u_int type, int paused, int done) 1308 { 1309 struct ahc_initiator_tinfo *tinfo; 1310 struct tmode_tstate *tstate; 1311 u_int oldwidth; 1312 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1313 1314 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1315 devinfo->target, &tstate); 1316 oldwidth = tinfo->current.width; 1317 1318 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1319 u_int scsirate; 1320 1321 scsirate = tinfo->scsirate; 1322 scsirate &= ~WIDEXFER; 1323 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1324 scsirate |= WIDEXFER; 1325 1326 tinfo->scsirate = scsirate; 1327 1328 if (active) 1329 ahc_outb(ahc, SCSIRATE, scsirate); 1330 1331 tinfo->current.width = width; 1332 } 1333 1334 if (done) { 1335 printf("%s: target %d using %dbit transfers\n", 1336 ahc_name(ahc), devinfo->target, 1337 8 * (0x01 << width)); 1338 } 1339 1340 if ((type & AHC_TRANS_GOAL) != 0) 1341 tinfo->goal.width = width; 1342 if ((type & AHC_TRANS_USER) != 0) 1343 tinfo->user.width = width; 1344 1345 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1346 /*force*/FALSE, paused); 1347 } 1348 1349 static void 1350 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1351 { 1352 struct ahc_initiator_tinfo *tinfo; 1353 struct tmode_tstate *tstate; 1354 1355 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1356 devinfo->target, &tstate); 1357 1358 if (enable) { 1359 tstate->tagenable |= devinfo->target_mask; 1360 } else { 1361 tstate->tagenable &= ~devinfo->target_mask; 1362 tstate->tagdisable |= devinfo->target_mask; 1363 } 1364 } 1365 1366 /* 1367 * Attach all the sub-devices we can find 1368 */ 1369 int 1370 ahc_attach(struct ahc_softc *ahc) 1371 { 1372 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1373 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1374 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1375 ahc->sc_adapter.adapt_max_periph = AHC_SCB_MAX; 1376 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1377 ahc->sc_adapter.adapt_minphys = ahcminphys; 1378 ahc->sc_adapter.adapt_request = ahc_action; 1379 1380 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1381 ahc->sc_channel.chan_bustype = &scsi_bustype; 1382 ahc->sc_channel.chan_channel = 0; 1383 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1384 ahc->sc_channel.chan_nluns = 8; 1385 ahc->sc_channel.chan_id = ahc->our_id; 1386 1387 if (ahc->features & AHC_TWIN) { 1388 ahc->sc_channel_b = ahc->sc_channel; 1389 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1390 ahc->sc_channel_b.chan_channel = 1; 1391 } 1392 1393 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1394 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1395 if (ahc->features & AHC_TWIN) 1396 config_found((void *)ahc, &ahc->sc_channel_b, 1397 scsiprint); 1398 } else { 1399 config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1400 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1401 } 1402 return 1; 1403 } 1404 1405 static void 1406 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1407 { 1408 u_int saved_tcl; 1409 role_t role; 1410 int our_id; 1411 1412 if (ahc_inb(ahc, SSTAT0) & TARGET) 1413 role = ROLE_TARGET; 1414 else 1415 role = ROLE_INITIATOR; 1416 1417 if (role == ROLE_TARGET 1418 && (ahc->features & AHC_MULTI_TID) != 0 1419 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1420 /* We were selected, so pull our id from TARGIDIN */ 1421 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1422 } else if ((ahc->features & AHC_ULTRA2) != 0) 1423 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1424 else 1425 our_id = ahc_inb(ahc, SCSIID) & OID; 1426 1427 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1428 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1429 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1430 role); 1431 } 1432 1433 static void 1434 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1435 u_int lun, char channel, role_t role) 1436 { 1437 devinfo->our_scsiid = our_id; 1438 devinfo->target = target; 1439 devinfo->lun = lun; 1440 devinfo->target_offset = target; 1441 devinfo->channel = channel; 1442 devinfo->role = role; 1443 if (channel == 'B') 1444 devinfo->target_offset += 8; 1445 devinfo->target_mask = (0x01 << devinfo->target_offset); 1446 } 1447 1448 /* 1449 * Catch an interrupt from the adapter 1450 */ 1451 int 1452 ahc_intr(void *arg) 1453 { 1454 struct ahc_softc *ahc; 1455 u_int intstat; 1456 1457 ahc = (struct ahc_softc *)arg; 1458 1459 intstat = ahc_inb(ahc, INTSTAT); 1460 1461 /* 1462 * Any interrupts to process? 1463 */ 1464 if ((intstat & INT_PEND) == 0) { 1465 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1466 #ifdef AHC_DEBUG 1467 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1468 ahc_name(ahc), 1469 ahc_inb(ahc, CCHADDR) | 1470 (ahc_inb(ahc, CCHADDR+1) << 8) 1471 | (ahc_inb(ahc, CCHADDR+2) << 16) 1472 | (ahc_inb(ahc, CCHADDR+3) << 24), 1473 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1474 | (ahc_inb(ahc, HADDR+2) << 16) 1475 | (ahc_inb(ahc, HADDR+3) << 24), 1476 ahc_inb(ahc, SEQADDR0) | 1477 (ahc_inb(ahc, SEQADDR1) << 8)); 1478 #endif 1479 return 1; 1480 } 1481 return 0; 1482 } 1483 1484 #ifdef AHC_DEBUG 1485 if (ahc_debug & AHC_SHOWINTR) { 1486 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1487 } 1488 #endif 1489 1490 if (intstat & CMDCMPLT) { 1491 ahc_outb(ahc, CLRINT, CLRCMDINT); 1492 ahc_run_qoutfifo(ahc); 1493 } 1494 if (intstat & BRKADRINT) { 1495 /* 1496 * We upset the sequencer :-( 1497 * Lookup the error message 1498 */ 1499 int i, error, num_errors; 1500 1501 error = ahc_inb(ahc, ERROR); 1502 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1503 for (i = 0; error != 1 && i < num_errors; i++) 1504 error >>= 1; 1505 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1506 ahc_name(ahc), hard_error[i].errmesg, 1507 ahc_inb(ahc, SEQADDR0) | 1508 (ahc_inb(ahc, SEQADDR1) << 8)); 1509 1510 /* Tell everyone that this HBA is no longer availible */ 1511 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1512 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1513 XS_DRIVER_STUFFUP); 1514 } 1515 if (intstat & SEQINT) 1516 ahc_handle_seqint(ahc, intstat); 1517 1518 if (intstat & SCSIINT) 1519 ahc_handle_scsiint(ahc, intstat); 1520 1521 return 1; 1522 } 1523 1524 static struct tmode_tstate * 1525 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1526 { 1527 struct tmode_tstate *master_tstate; 1528 struct tmode_tstate *tstate; 1529 int i, s; 1530 1531 master_tstate = ahc->enabled_targets[ahc->our_id]; 1532 if (channel == 'B') { 1533 scsi_id += 8; 1534 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1535 } 1536 if (ahc->enabled_targets[scsi_id] != NULL 1537 && ahc->enabled_targets[scsi_id] != master_tstate) 1538 panic("%s: ahc_alloc_tstate - Target already allocated", 1539 ahc_name(ahc)); 1540 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1541 if (tstate == NULL) 1542 return (NULL); 1543 1544 /* 1545 * If we have allocated a master tstate, copy user settings from 1546 * the master tstate (taken from SRAM or the EEPROM) for this 1547 * channel, but reset our current and goal settings to async/narrow 1548 * until an initiator talks to us. 1549 */ 1550 if (master_tstate != NULL) { 1551 bcopy(master_tstate, tstate, sizeof(*tstate)); 1552 tstate->ultraenb = 0; 1553 for (i = 0; i < 16; i++) { 1554 bzero(&tstate->transinfo[i].current, 1555 sizeof(tstate->transinfo[i].current)); 1556 bzero(&tstate->transinfo[i].goal, 1557 sizeof(tstate->transinfo[i].goal)); 1558 } 1559 } else 1560 bzero(tstate, sizeof(*tstate)); 1561 s = splbio(); 1562 ahc->enabled_targets[scsi_id] = tstate; 1563 splx(s); 1564 return (tstate); 1565 } 1566 1567 #if UNUSED 1568 static void 1569 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1570 { 1571 struct tmode_tstate *tstate; 1572 1573 /* Don't clean up the entry for our initiator role */ 1574 if ((ahc->flags & AHC_INITIATORMODE) != 0 1575 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1576 || (channel == 'A' && scsi_id == ahc->our_id)) 1577 && force == FALSE) 1578 return; 1579 1580 if (channel == 'B') 1581 scsi_id += 8; 1582 tstate = ahc->enabled_targets[scsi_id]; 1583 if (tstate != NULL) 1584 free(tstate, M_DEVBUF); 1585 ahc->enabled_targets[scsi_id] = NULL; 1586 } 1587 #endif 1588 1589 static void 1590 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1591 { 1592 struct scb *scb; 1593 struct ahc_devinfo devinfo; 1594 1595 ahc_fetch_devinfo(ahc, &devinfo); 1596 1597 /* 1598 * Clear the upper byte that holds SEQINT status 1599 * codes and clear the SEQINT bit. We will unpause 1600 * the sequencer, if appropriate, after servicing 1601 * the request. 1602 */ 1603 ahc_outb(ahc, CLRINT, CLRSEQINT); 1604 switch (intstat & SEQINT_MASK) { 1605 case NO_MATCH: 1606 { 1607 /* Ensure we don't leave the selection hardware on */ 1608 ahc_outb(ahc, SCSISEQ, 1609 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1610 1611 printf("%s:%c:%d: no active SCB for reconnecting " 1612 "target - issuing BUS DEVICE RESET\n", 1613 ahc_name(ahc), devinfo.channel, devinfo.target); 1614 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1615 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1616 ahc_inb(ahc, SEQ_FLAGS)); 1617 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1618 ahc->msgout_len = 1; 1619 ahc->msgout_index = 0; 1620 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1621 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1622 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1623 break; 1624 } 1625 case UPDATE_TMSG_REQ: 1626 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1627 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1628 (ahc->targ_msg_req >> 8) & 0xFF); 1629 ahc_outb(ahc, HS_MAILBOX, 0); 1630 break; 1631 case SEND_REJECT: 1632 { 1633 u_int rejbyte = ahc_inb(ahc, ACCUM); 1634 printf("%s:%c:%d: Warning - unknown message received from " 1635 "target (0x%x). Rejecting\n", 1636 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1637 break; 1638 } 1639 case NO_IDENT: 1640 { 1641 /* 1642 * The reconnecting target either did not send an identify 1643 * message, or did, but we didn't find and SCB to match and 1644 * before it could respond to our ATN/abort, it hit a dataphase. 1645 * The only safe thing to do is to blow it away with a bus 1646 * reset. 1647 */ 1648 int found; 1649 1650 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1651 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1652 ahc_name(ahc), devinfo.channel, devinfo.target, 1653 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1654 found = ahc_reset_channel(ahc, devinfo.channel, 1655 /*initiate reset*/TRUE); 1656 printf("%s: Issued Channel %c Bus Reset. " 1657 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1658 found); 1659 return; 1660 } 1661 case BAD_PHASE: 1662 { 1663 u_int lastphase; 1664 1665 lastphase = ahc_inb(ahc, LASTPHASE); 1666 if (lastphase == P_BUSFREE) { 1667 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1668 ahc_name(ahc), devinfo.channel, devinfo.target, 1669 ahc_inb(ahc, SCSISIGI)); 1670 restart_sequencer(ahc); 1671 return; 1672 } else { 1673 printf("%s:%c:%d: unknown scsi bus phase %x. " 1674 "Attempting to continue\n", 1675 ahc_name(ahc), devinfo.channel, devinfo.target, 1676 ahc_inb(ahc, SCSISIGI)); 1677 } 1678 break; 1679 } 1680 case BAD_STATUS: 1681 { 1682 u_int scb_index; 1683 struct hardware_scb *hscb; 1684 struct scsipi_xfer *xs; 1685 /* 1686 * The sequencer will notify us when a command 1687 * has an error that would be of interest to 1688 * the kernel. This allows us to leave the sequencer 1689 * running in the common case of command completes 1690 * without error. The sequencer will already have 1691 * dma'd the SCB back up to us, so we can reference 1692 * the in kernel copy directly. 1693 */ 1694 scb_index = ahc_inb(ahc, SCB_TAG); 1695 scb = &ahc->scb_data->scbarray[scb_index]; 1696 1697 /* ahc_print_scb(scb); */ 1698 1699 /* 1700 * Set the default return value to 0 (don't 1701 * send sense). The sense code will change 1702 * this if needed. 1703 */ 1704 ahc_outb(ahc, RETURN_1, 0); 1705 if (!(scb_index < ahc->scb_data->numscbs 1706 && (scb->flags & SCB_ACTIVE) != 0)) { 1707 printf("%s:%c:%d: ahc_intr - referenced scb " 1708 "not valid during seqint 0x%x scb(%d)\n", 1709 ahc_name(ahc), devinfo.channel, 1710 devinfo.target, intstat, scb_index); 1711 goto unpause; 1712 } 1713 1714 hscb = scb->hscb; 1715 xs = scb->xs; 1716 1717 /* Don't want to clobber the original sense code */ 1718 if ((scb->flags & SCB_SENSE) != 0) { 1719 /* 1720 * Clear the SCB_SENSE Flag and have 1721 * the sequencer do a normal command 1722 * complete. 1723 */ 1724 scb->flags &= ~SCB_SENSE; 1725 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1726 break; 1727 } 1728 /* Freeze the queue unit the client sees the error. */ 1729 ahc_freeze_devq(ahc, xs->xs_periph); 1730 ahc_freeze_ccb(scb); 1731 xs->status = hscb->status; 1732 switch (hscb->status) { 1733 case SCSI_STATUS_OK: 1734 printf("%s: Interrupted for status of 0???\n", 1735 ahc_name(ahc)); 1736 break; 1737 case SCSI_STATUS_CMD_TERMINATED: 1738 case SCSI_STATUS_CHECK_COND: 1739 #if defined(AHC_DEBUG) 1740 if (ahc_debug & AHC_SHOWSENSE) { 1741 scsipi_printaddr(xs->xs_periph); 1742 printf("Check Status, resid %d datalen %d\n", 1743 xs->resid, xs->datalen); 1744 } 1745 #endif 1746 1747 if (xs->error == XS_NOERROR && 1748 !(scb->flags & SCB_SENSE)) { 1749 struct ahc_dma_seg *sg; 1750 struct scsipi_sense *sc; 1751 struct ahc_initiator_tinfo *tinfo; 1752 struct tmode_tstate *tstate; 1753 1754 sg = scb->sg_list; 1755 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1756 /* 1757 * Save off the residual if there is one. 1758 */ 1759 if (hscb->residual_SG_count != 0) 1760 ahc_calc_residual(scb); 1761 else 1762 xs->resid = 0; 1763 1764 #ifdef AHC_DEBUG 1765 if (ahc_debug & AHC_SHOWSENSE) { 1766 scsipi_printaddr(xs->xs_periph); 1767 printf("Sending Sense\n"); 1768 } 1769 #endif 1770 sg->addr = ahc->scb_data->sense_busaddr + 1771 (hscb->tag*sizeof(struct scsipi_sense_data)); 1772 sg->len = sizeof (struct scsipi_sense_data); 1773 1774 sc->opcode = REQUEST_SENSE; 1775 sc->byte2 = SCB_LUN(scb) << 5; 1776 sc->unused[0] = 0; 1777 sc->unused[1] = 0; 1778 sc->length = sg->len; 1779 sc->control = 0; 1780 1781 /* 1782 * Would be nice to preserve DISCENB here, 1783 * but due to the way we page SCBs, we can't. 1784 */ 1785 hscb->control = 0; 1786 1787 /* 1788 * This request sense could be because the 1789 * the device lost power or in some other 1790 * way has lost our transfer negotiations. 1791 * Renegotiate if appropriate. Unit attention 1792 * errors will be reported before any data 1793 * phases occur. 1794 */ 1795 ahc_calc_residual(scb); 1796 #if defined(AHC_DEBUG) 1797 if (ahc_debug & AHC_SHOWSENSE) { 1798 scsipi_printaddr(xs->xs_periph); 1799 printf("Sense: datalen %d resid %d" 1800 "chan %d id %d targ %d\n", 1801 xs->datalen, xs->resid, 1802 devinfo.channel, devinfo.our_scsiid, 1803 devinfo.target); 1804 } 1805 #endif 1806 if (xs->datalen > 0 && 1807 xs->resid == xs->datalen) { 1808 tinfo = ahc_fetch_transinfo(ahc, 1809 devinfo.channel, 1810 devinfo.our_scsiid, 1811 devinfo.target, 1812 &tstate); 1813 ahc_update_target_msg_request(ahc, 1814 &devinfo, 1815 tinfo, 1816 /*force*/TRUE, 1817 /*paused*/TRUE); 1818 } 1819 hscb->status = 0; 1820 hscb->SG_count = 1; 1821 hscb->SG_pointer = scb->sg_list_phys; 1822 hscb->data = sg->addr; 1823 hscb->datalen = sg->len; 1824 hscb->cmdpointer = hscb->cmdstore_busaddr; 1825 hscb->cmdlen = sizeof(*sc); 1826 scb->sg_count = hscb->SG_count; 1827 ahc_swap_hscb(hscb); 1828 ahc_swap_sg(scb->sg_list); 1829 scb->flags |= SCB_SENSE; 1830 /* 1831 * Ensure the target is busy since this 1832 * will be an untagged request. 1833 */ 1834 ahc_busy_tcl(ahc, scb); 1835 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1836 1837 /* 1838 * Ensure we have enough time to actually 1839 * retrieve the sense. 1840 */ 1841 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1842 callout_reset(&scb->xs->xs_callout, 1843 5 * hz, ahc_timeout, scb); 1844 } 1845 } 1846 break; 1847 case SCSI_STATUS_QUEUE_FULL: 1848 case SCSI_STATUS_BUSY: 1849 xs->error = XS_BUSY; 1850 break; 1851 } 1852 break; 1853 } 1854 case TRACE_POINT: 1855 { 1856 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1857 ahc_inb(ahc, DFCNTRL)); 1858 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1859 ahc_inb(ahc, DFSTATUS)); 1860 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1861 ahc_inb(ahc, SSTAT0), 1862 ahc_inb(ahc, SCB_DATACNT)); 1863 break; 1864 } 1865 case HOST_MSG_LOOP: 1866 { 1867 /* 1868 * The sequencer has encountered a message phase 1869 * that requires host assistance for completion. 1870 * While handling the message phase(s), we will be 1871 * notified by the sequencer after each byte is 1872 * transfered so we can track bus phases. 1873 * 1874 * If this is the first time we've seen a HOST_MSG_LOOP, 1875 * initialize the state of the host message loop. 1876 */ 1877 if (ahc->msg_type == MSG_TYPE_NONE) { 1878 u_int bus_phase; 1879 1880 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1881 if (bus_phase != P_MESGIN 1882 && bus_phase != P_MESGOUT) { 1883 printf("ahc_intr: HOST_MSG_LOOP bad " 1884 "phase 0x%x\n", 1885 bus_phase); 1886 /* 1887 * Probably transitioned to bus free before 1888 * we got here. Just punt the message. 1889 */ 1890 ahc_clear_intstat(ahc); 1891 restart_sequencer(ahc); 1892 } 1893 1894 if (devinfo.role == ROLE_INITIATOR) { 1895 struct scb *scb; 1896 u_int scb_index; 1897 1898 scb_index = ahc_inb(ahc, SCB_TAG); 1899 scb = &ahc->scb_data->scbarray[scb_index]; 1900 1901 if (bus_phase == P_MESGOUT) 1902 ahc_setup_initiator_msgout(ahc, 1903 &devinfo, 1904 scb); 1905 else { 1906 ahc->msg_type = 1907 MSG_TYPE_INITIATOR_MSGIN; 1908 ahc->msgin_index = 0; 1909 } 1910 } else { 1911 if (bus_phase == P_MESGOUT) { 1912 ahc->msg_type = 1913 MSG_TYPE_TARGET_MSGOUT; 1914 ahc->msgin_index = 0; 1915 } else 1916 /* XXX Ever executed??? */ 1917 ahc_setup_target_msgin(ahc, &devinfo); 1918 } 1919 } 1920 1921 /* Pass a NULL path so that handlers generate their own */ 1922 ahc_handle_message_phase(ahc, /*path*/NULL); 1923 break; 1924 } 1925 case PERR_DETECTED: 1926 { 1927 /* 1928 * If we've cleared the parity error interrupt 1929 * but the sequencer still believes that SCSIPERR 1930 * is true, it must be that the parity error is 1931 * for the currently presented byte on the bus, 1932 * and we are not in a phase (data-in) where we will 1933 * eventually ack this byte. Ack the byte and 1934 * throw it away in the hope that the target will 1935 * take us to message out to deliver the appropriate 1936 * error message. 1937 */ 1938 if ((intstat & SCSIINT) == 0 1939 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1940 u_int curphase; 1941 1942 /* 1943 * The hardware will only let you ack bytes 1944 * if the expected phase in SCSISIGO matches 1945 * the current phase. Make sure this is 1946 * currently the case. 1947 */ 1948 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1949 ahc_outb(ahc, LASTPHASE, curphase); 1950 ahc_outb(ahc, SCSISIGO, curphase); 1951 ahc_inb(ahc, SCSIDATL); 1952 } 1953 break; 1954 } 1955 case DATA_OVERRUN: 1956 { 1957 /* 1958 * When the sequencer detects an overrun, it 1959 * places the controller in "BITBUCKET" mode 1960 * and allows the target to complete its transfer. 1961 * Unfortunately, none of the counters get updated 1962 * when the controller is in this mode, so we have 1963 * no way of knowing how large the overrun was. 1964 */ 1965 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1966 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1967 int i; 1968 1969 scb = &ahc->scb_data->scbarray[scbindex]; 1970 for (i = 0; i < num_phases; i++) { 1971 if (lastphase == phase_table[i].phase) 1972 break; 1973 } 1974 scsipi_printaddr(scb->xs->xs_periph); 1975 printf("data overrun detected %s." 1976 " Tag == 0x%x.\n", 1977 phase_table[i].phasemsg, 1978 scb->hscb->tag); 1979 scsipi_printaddr(scb->xs->xs_periph); 1980 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1981 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1982 scb->xs->datalen, scb->sg_count); 1983 if (scb->sg_count > 0) { 1984 for (i = 0; i < scb->sg_count; i++) { 1985 printf("sg[%d] - Addr 0x%x : Length %d\n", 1986 i, 1987 le32toh(scb->sg_list[i].addr), 1988 le32toh(scb->sg_list[i].len)); 1989 } 1990 } 1991 /* 1992 * Set this and it will take affect when the 1993 * target does a command complete. 1994 */ 1995 ahc_freeze_devq(ahc, scb->xs->xs_periph); 1996 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 1997 ahc_freeze_ccb(scb); 1998 break; 1999 } 2000 case TRACEPOINT: 2001 { 2002 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2003 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2004 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2005 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2006 printf("TRACEPOINT: CCHADDR = %x\n", 2007 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2008 | (ahc_inb(ahc, CCHADDR+2) << 16) 2009 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2010 #if 0 2011 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2012 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2013 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2014 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2015 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2016 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2017 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2018 ahc_inb(ahc, CCHADDR) 2019 | (ahc_inb(ahc, CCHADDR+1) << 8) 2020 | (ahc_inb(ahc, CCHADDR+2) << 16) 2021 | (ahc_inb(ahc, CCHADDR+3) << 24), 2022 ahc_inb(ahc, CCHCNT) 2023 | (ahc_inb(ahc, CCHCNT+1) << 8) 2024 | (ahc_inb(ahc, CCHCNT+2) << 16), 2025 ahc_inb(ahc, SCBPTR)); 2026 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2027 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2028 #if DDB > 0 2029 cpu_Debugger(); 2030 #endif 2031 #endif 2032 break; 2033 } 2034 #if NOT_YET 2035 /* XXX Fill these in later */ 2036 case MESG_BUFFER_BUSY: 2037 break; 2038 case MSGIN_PHASEMIS: 2039 break; 2040 #endif 2041 default: 2042 printf("ahc_intr: seqint, " 2043 "intstat == 0x%x, scsisigi = 0x%x\n", 2044 intstat, ahc_inb(ahc, SCSISIGI)); 2045 break; 2046 } 2047 2048 unpause: 2049 /* 2050 * The sequencer is paused immediately on 2051 * a SEQINT, so we should restart it when 2052 * we're done. 2053 */ 2054 unpause_sequencer(ahc); 2055 } 2056 2057 static void 2058 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2059 { 2060 u_int scb_index; 2061 u_int status; 2062 struct scb *scb; 2063 char cur_channel; 2064 char intr_channel; 2065 2066 if ((ahc->features & AHC_TWIN) != 0 2067 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2068 cur_channel = 'B'; 2069 else 2070 cur_channel = 'A'; 2071 intr_channel = cur_channel; 2072 2073 status = ahc_inb(ahc, SSTAT1); 2074 if (status == 0) { 2075 if ((ahc->features & AHC_TWIN) != 0) { 2076 /* Try the other channel */ 2077 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2078 status = ahc_inb(ahc, SSTAT1); 2079 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2080 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2081 } 2082 if (status == 0) { 2083 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2084 return; 2085 } 2086 } 2087 2088 scb_index = ahc_inb(ahc, SCB_TAG); 2089 if (scb_index < ahc->scb_data->numscbs) { 2090 scb = &ahc->scb_data->scbarray[scb_index]; 2091 if ((scb->flags & SCB_ACTIVE) == 0 2092 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2093 scb = NULL; 2094 } else 2095 scb = NULL; 2096 2097 if ((status & SCSIRSTI) != 0) { 2098 printf("%s: Someone reset channel %c\n", 2099 ahc_name(ahc), intr_channel); 2100 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2101 } else if ((status & SCSIPERR) != 0) { 2102 /* 2103 * Determine the bus phase and queue an appropriate message. 2104 * SCSIPERR is latched true as soon as a parity error 2105 * occurs. If the sequencer acked the transfer that 2106 * caused the parity error and the currently presented 2107 * transfer on the bus has correct parity, SCSIPERR will 2108 * be cleared by CLRSCSIPERR. Use this to determine if 2109 * we should look at the last phase the sequencer recorded, 2110 * or the current phase presented on the bus. 2111 */ 2112 u_int mesg_out; 2113 u_int curphase; 2114 u_int errorphase; 2115 u_int lastphase; 2116 int i; 2117 2118 lastphase = ahc_inb(ahc, LASTPHASE); 2119 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2120 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2121 /* 2122 * For all phases save DATA, the sequencer won't 2123 * automatically ack a byte that has a parity error 2124 * in it. So the only way that the current phase 2125 * could be 'data-in' is if the parity error is for 2126 * an already acked byte in the data phase. During 2127 * synchronous data-in transfers, we may actually 2128 * ack bytes before latching the current phase in 2129 * LASTPHASE, leading to the discrepancy between 2130 * curphase and lastphase. 2131 */ 2132 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2133 || curphase == P_DATAIN) 2134 errorphase = curphase; 2135 else 2136 errorphase = lastphase; 2137 2138 for (i = 0; i < num_phases; i++) { 2139 if (errorphase == phase_table[i].phase) 2140 break; 2141 } 2142 mesg_out = phase_table[i].mesg_out; 2143 if (scb != NULL) 2144 scsipi_printaddr(scb->xs->xs_periph); 2145 else 2146 printf("%s:%c:%d: ", ahc_name(ahc), 2147 intr_channel, 2148 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2149 2150 printf("parity error detected %s. " 2151 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2152 phase_table[i].phasemsg, 2153 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2154 ahc_inb(ahc, SCSIRATE)); 2155 2156 /* 2157 * We've set the hardware to assert ATN if we 2158 * get a parity error on "in" phases, so all we 2159 * need to do is stuff the message buffer with 2160 * the appropriate message. "In" phases have set 2161 * mesg_out to something other than MSG_NOP. 2162 */ 2163 if (mesg_out != MSG_NOOP) { 2164 if (ahc->msg_type != MSG_TYPE_NONE) 2165 ahc->send_msg_perror = TRUE; 2166 else 2167 ahc_outb(ahc, MSG_OUT, mesg_out); 2168 } 2169 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2170 unpause_sequencer(ahc); 2171 } else if ((status & BUSFREE) != 0 2172 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2173 /* 2174 * First look at what phase we were last in. 2175 * If its message out, chances are pretty good 2176 * that the busfree was in response to one of 2177 * our abort requests. 2178 */ 2179 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2180 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2181 u_int target = TCL_TARGET(saved_tcl); 2182 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2183 char channel = TCL_CHANNEL(ahc, saved_tcl); 2184 int printerror = 1; 2185 2186 ahc_outb(ahc, SCSISEQ, 2187 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2188 if (lastphase == P_MESGOUT) { 2189 u_int message; 2190 u_int tag; 2191 2192 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2193 tag = SCB_LIST_NULL; 2194 switch (message) { 2195 case MSG_ABORT_TAG: 2196 tag = scb->hscb->tag; 2197 /* FALLTRHOUGH */ 2198 case MSG_ABORT: 2199 scsipi_printaddr(scb->xs->xs_periph); 2200 printf("SCB %x - Abort %s Completed.\n", 2201 scb->hscb->tag, tag == SCB_LIST_NULL ? 2202 "" : "Tag"); 2203 ahc_abort_scbs(ahc, target, channel, 2204 TCL_LUN(saved_tcl), tag, 2205 ROLE_INITIATOR, 2206 XS_DRIVER_STUFFUP); 2207 printerror = 0; 2208 break; 2209 case MSG_BUS_DEV_RESET: 2210 { 2211 struct ahc_devinfo devinfo; 2212 2213 if (scb != NULL && 2214 (scb->xs->xs_control & XS_CTL_RESET) 2215 && ahc_match_scb(scb, target, channel, 2216 TCL_LUN(saved_tcl), 2217 SCB_LIST_NULL, 2218 ROLE_INITIATOR)) { 2219 ahcsetccbstatus(scb->xs, XS_NOERROR); 2220 } 2221 ahc_compile_devinfo(&devinfo, 2222 initiator_role_id, 2223 target, 2224 TCL_LUN(saved_tcl), 2225 channel, 2226 ROLE_INITIATOR); 2227 ahc_handle_devreset(ahc, &devinfo, 2228 XS_RESET, 2229 "Bus Device Reset", 2230 /*verbose_level*/0); 2231 printerror = 0; 2232 break; 2233 } 2234 default: 2235 break; 2236 } 2237 } 2238 if (printerror != 0) { 2239 int i; 2240 2241 if (scb != NULL) { 2242 u_int tag; 2243 2244 if ((scb->hscb->control & TAG_ENB) != 0) 2245 tag = scb->hscb->tag; 2246 else 2247 tag = SCB_LIST_NULL; 2248 ahc_abort_scbs(ahc, target, channel, 2249 SCB_LUN(scb), tag, 2250 ROLE_INITIATOR, 2251 XS_DRIVER_STUFFUP); 2252 scsipi_printaddr(scb->xs->xs_periph); 2253 } else { 2254 /* 2255 * We had not fully identified this connection, 2256 * so we cannot abort anything. 2257 */ 2258 printf("%s: ", ahc_name(ahc)); 2259 } 2260 for (i = 0; i < num_phases; i++) { 2261 if (lastphase == phase_table[i].phase) 2262 break; 2263 } 2264 printf("Unexpected busfree %s\n" 2265 "SEQADDR == 0x%x\n", 2266 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2267 | (ahc_inb(ahc, SEQADDR1) << 8)); 2268 } 2269 ahc_clear_msg_state(ahc); 2270 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2271 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2272 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2273 restart_sequencer(ahc); 2274 } else if ((status & SELTO) != 0) { 2275 u_int scbptr; 2276 2277 scbptr = ahc_inb(ahc, WAITING_SCBH); 2278 ahc_outb(ahc, SCBPTR, scbptr); 2279 scb_index = ahc_inb(ahc, SCB_TAG); 2280 2281 if (scb_index < ahc->scb_data->numscbs) { 2282 scb = &ahc->scb_data->scbarray[scb_index]; 2283 if ((scb->flags & SCB_ACTIVE) == 0) 2284 scb = NULL; 2285 } else 2286 scb = NULL; 2287 2288 if (scb == NULL) { 2289 printf("%s: ahc_intr - referenced scb not " 2290 "valid during SELTO scb(%d, %d)\n", 2291 ahc_name(ahc), scbptr, scb_index); 2292 } else { 2293 u_int tag; 2294 2295 tag = SCB_LIST_NULL; 2296 if ((scb->hscb->control & TAG_ENB) != 0) 2297 tag = scb->hscb->tag; 2298 2299 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2300 SCB_LUN(scb), tag, 2301 ROLE_INITIATOR, XS_SELTIMEOUT); 2302 } 2303 /* Stop the selection */ 2304 ahc_outb(ahc, SCSISEQ, 0); 2305 2306 /* No more pending messages */ 2307 ahc_clear_msg_state(ahc); 2308 2309 /* 2310 * Although the driver does not care about the 2311 * 'Selection in Progress' status bit, the busy 2312 * LED does. SELINGO is only cleared by a sucessful 2313 * selection, so we must manually clear it to ensure 2314 * the LED turns off just incase no future successful 2315 * selections occur (e.g. no devices on the bus). 2316 */ 2317 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2318 2319 /* Clear interrupt state */ 2320 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2321 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2322 restart_sequencer(ahc); 2323 } else { 2324 scsipi_printaddr(scb->xs->xs_periph); 2325 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2326 ahc_outb(ahc, CLRSINT1, status); 2327 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2328 unpause_sequencer(ahc); 2329 } 2330 } 2331 2332 static void 2333 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2334 { 2335 /* 2336 * We need to initiate transfer negotiations. 2337 * If our current and goal settings are identical, 2338 * we want to renegotiate due to a check condition. 2339 */ 2340 struct ahc_initiator_tinfo *tinfo; 2341 struct tmode_tstate *tstate; 2342 int dowide; 2343 int dosync; 2344 2345 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2346 devinfo->target, &tstate); 2347 dowide = tinfo->current.width != tinfo->goal.width; 2348 dosync = tinfo->current.period != tinfo->goal.period; 2349 2350 if (!dowide && !dosync) { 2351 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2352 dosync = tinfo->goal.period != 0; 2353 } 2354 2355 if (dowide) { 2356 ahc_construct_wdtr(ahc, tinfo->goal.width); 2357 } else if (dosync) { 2358 const struct ahc_syncrate *rate; 2359 u_int period; 2360 u_int offset; 2361 2362 period = tinfo->goal.period; 2363 rate = ahc_devlimited_syncrate(ahc, &period); 2364 offset = tinfo->goal.offset; 2365 ahc_validate_offset(ahc, rate, &offset, 2366 tinfo->current.width); 2367 ahc_construct_sdtr(ahc, period, offset); 2368 } else { 2369 panic("ahc_intr: AWAITING_MSG for negotiation, " 2370 "but no negotiation needed\n"); 2371 } 2372 } 2373 2374 static void 2375 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2376 struct scb *scb) 2377 { 2378 /* 2379 * To facilitate adding multiple messages together, 2380 * each routine should increment the index and len 2381 * variables instead of setting them explicitly. 2382 */ 2383 ahc->msgout_index = 0; 2384 ahc->msgout_len = 0; 2385 2386 if ((scb->flags & SCB_DEVICE_RESET) == 0 2387 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2388 u_int identify_msg; 2389 2390 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2391 if ((scb->hscb->control & DISCENB) != 0) 2392 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2393 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2394 ahc->msgout_len++; 2395 2396 if ((scb->hscb->control & TAG_ENB) != 0) { 2397 ahc->msgout_buf[ahc->msgout_index++] = 2398 scb->xs->xs_tag_type; 2399 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2400 ahc->msgout_len += 2; 2401 } 2402 } 2403 2404 if (scb->flags & SCB_DEVICE_RESET) { 2405 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2406 ahc->msgout_len++; 2407 scsipi_printaddr(scb->xs->xs_periph); 2408 printf("Bus Device Reset Message Sent\n"); 2409 } else if (scb->flags & SCB_ABORT) { 2410 if ((scb->hscb->control & TAG_ENB) != 0) 2411 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2412 else 2413 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2414 ahc->msgout_len++; 2415 scsipi_printaddr(scb->xs->xs_periph); 2416 printf("Abort Message Sent\n"); 2417 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2418 ahc_build_transfer_msg(ahc, devinfo); 2419 } else { 2420 printf("ahc_intr: AWAITING_MSG for an SCB that " 2421 "does not have a waiting message"); 2422 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2423 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2424 ahc_inb(ahc, MSG_OUT), scb->flags); 2425 } 2426 2427 /* 2428 * Clear the MK_MESSAGE flag from the SCB so we aren't 2429 * asked to send this message again. 2430 */ 2431 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2432 ahc->msgout_index = 0; 2433 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2434 } 2435 2436 static void 2437 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2438 { 2439 /* 2440 * To facilitate adding multiple messages together, 2441 * each routine should increment the index and len 2442 * variables instead of setting them explicitly. 2443 */ 2444 ahc->msgout_index = 0; 2445 ahc->msgout_len = 0; 2446 2447 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2448 ahc_build_transfer_msg(ahc, devinfo); 2449 else 2450 panic("ahc_intr: AWAITING target message with no message"); 2451 2452 ahc->msgout_index = 0; 2453 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2454 } 2455 2456 static int 2457 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2458 { 2459 /* 2460 * What we care about here is if we had an 2461 * outstanding SDTR or WDTR message for this 2462 * target. If we did, this is a signal that 2463 * the target is refusing negotiation. 2464 */ 2465 struct scb *scb; 2466 u_int scb_index; 2467 u_int last_msg; 2468 int response = 0; 2469 2470 scb_index = ahc_inb(ahc, SCB_TAG); 2471 scb = &ahc->scb_data->scbarray[scb_index]; 2472 2473 /* Might be necessary */ 2474 last_msg = ahc_inb(ahc, LAST_MSG); 2475 2476 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2477 struct ahc_initiator_tinfo *tinfo; 2478 struct tmode_tstate *tstate; 2479 2480 #ifdef AHC_DEBUG_NEG 2481 /* note 8bit xfers */ 2482 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2483 "8bit transfers\n", ahc_name(ahc), 2484 devinfo->channel, devinfo->target); 2485 #endif 2486 ahc_set_width(ahc, devinfo, 2487 MSG_EXT_WDTR_BUS_8_BIT, 2488 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2489 /*paused*/TRUE, /*done*/TRUE); 2490 /* 2491 * No need to clear the sync rate. If the target 2492 * did not accept the command, our syncrate is 2493 * unaffected. If the target started the negotiation, 2494 * but rejected our response, we already cleared the 2495 * sync rate before sending our WDTR. 2496 */ 2497 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2498 devinfo->our_scsiid, 2499 devinfo->target, &tstate); 2500 if (tinfo->goal.period) { 2501 u_int period; 2502 2503 /* Start the sync negotiation */ 2504 period = tinfo->goal.period; 2505 ahc_devlimited_syncrate(ahc, &period); 2506 ahc->msgout_index = 0; 2507 ahc->msgout_len = 0; 2508 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2509 ahc->msgout_index = 0; 2510 response = 1; 2511 } 2512 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2513 /* note asynch xfers and clear flag */ 2514 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2515 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2516 /*paused*/TRUE, /*done*/TRUE); 2517 #ifdef AHC_DEBUG_NEG 2518 printf("%s:%c:%d: refuses synchronous negotiation. " 2519 "Using asynchronous transfers\n", 2520 ahc_name(ahc), 2521 devinfo->channel, devinfo->target); 2522 #endif 2523 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2524 printf("%s:%c:%d: refuses tagged commands. Performing " 2525 "non-tagged I/O\n", ahc_name(ahc), 2526 devinfo->channel, devinfo->target); 2527 2528 ahc_set_tags(ahc, devinfo, FALSE); 2529 2530 /* 2531 * Resend the identify for this CCB as the target 2532 * may believe that the selection is invalid otherwise. 2533 */ 2534 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2535 & ~MSG_SIMPLE_Q_TAG); 2536 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2537 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2538 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2539 2540 /* 2541 * Requeue all tagged commands for this target 2542 * currently in our posession so they can be 2543 * converted to untagged commands. 2544 */ 2545 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2546 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2547 ROLE_INITIATOR, SCB_REQUEUE, 2548 SEARCH_COMPLETE); 2549 } else { 2550 /* 2551 * Otherwise, we ignore it. 2552 */ 2553 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2554 ahc_name(ahc), devinfo->channel, devinfo->target, 2555 last_msg); 2556 } 2557 return (response); 2558 } 2559 2560 static void 2561 ahc_clear_msg_state(struct ahc_softc *ahc) 2562 { 2563 ahc->msgout_len = 0; 2564 ahc->msgin_index = 0; 2565 ahc->msg_type = MSG_TYPE_NONE; 2566 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2567 } 2568 2569 static void 2570 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2571 { 2572 struct ahc_devinfo devinfo; 2573 u_int bus_phase; 2574 int end_session; 2575 2576 ahc_fetch_devinfo(ahc, &devinfo); 2577 end_session = FALSE; 2578 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2579 2580 reswitch: 2581 switch (ahc->msg_type) { 2582 case MSG_TYPE_INITIATOR_MSGOUT: 2583 { 2584 int lastbyte; 2585 int phasemis; 2586 int msgdone; 2587 2588 if (ahc->msgout_len == 0) 2589 panic("REQINIT interrupt with no active message"); 2590 2591 phasemis = bus_phase != P_MESGOUT; 2592 if (phasemis) { 2593 if (bus_phase == P_MESGIN) { 2594 /* 2595 * Change gears and see if 2596 * this messages is of interest to 2597 * us or should be passed back to 2598 * the sequencer. 2599 */ 2600 ahc_outb(ahc, CLRSINT1, CLRATNO); 2601 ahc->send_msg_perror = FALSE; 2602 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2603 ahc->msgin_index = 0; 2604 goto reswitch; 2605 } 2606 end_session = TRUE; 2607 break; 2608 } 2609 2610 if (ahc->send_msg_perror) { 2611 ahc_outb(ahc, CLRSINT1, CLRATNO); 2612 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2613 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2614 break; 2615 } 2616 2617 msgdone = ahc->msgout_index == ahc->msgout_len; 2618 if (msgdone) { 2619 /* 2620 * The target has requested a retry. 2621 * Re-assert ATN, reset our message index to 2622 * 0, and try again. 2623 */ 2624 ahc->msgout_index = 0; 2625 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2626 } 2627 2628 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2629 if (lastbyte) { 2630 /* Last byte is signified by dropping ATN */ 2631 ahc_outb(ahc, CLRSINT1, CLRATNO); 2632 } 2633 2634 /* 2635 * Clear our interrupt status and present 2636 * the next byte on the bus. 2637 */ 2638 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2639 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2640 break; 2641 } 2642 case MSG_TYPE_INITIATOR_MSGIN: 2643 { 2644 int phasemis; 2645 int message_done; 2646 2647 phasemis = bus_phase != P_MESGIN; 2648 2649 if (phasemis) { 2650 ahc->msgin_index = 0; 2651 if (bus_phase == P_MESGOUT 2652 && (ahc->send_msg_perror == TRUE 2653 || (ahc->msgout_len != 0 2654 && ahc->msgout_index == 0))) { 2655 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2656 goto reswitch; 2657 } 2658 end_session = TRUE; 2659 break; 2660 } 2661 2662 /* Pull the byte in without acking it */ 2663 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2664 2665 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2666 2667 if (message_done) { 2668 /* 2669 * Clear our incoming message buffer in case there 2670 * is another message following this one. 2671 */ 2672 ahc->msgin_index = 0; 2673 2674 /* 2675 * If this message illicited a response, 2676 * assert ATN so the target takes us to the 2677 * message out phase. 2678 */ 2679 if (ahc->msgout_len != 0) 2680 ahc_outb(ahc, SCSISIGO, 2681 ahc_inb(ahc, SCSISIGO) | ATNO); 2682 } else 2683 ahc->msgin_index++; 2684 2685 /* Ack the byte */ 2686 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2687 ahc_inb(ahc, SCSIDATL); 2688 break; 2689 } 2690 case MSG_TYPE_TARGET_MSGIN: 2691 { 2692 int msgdone; 2693 int msgout_request; 2694 2695 if (ahc->msgout_len == 0) 2696 panic("Target MSGIN with no active message"); 2697 2698 /* 2699 * If we interrupted a mesgout session, the initiator 2700 * will not know this until our first REQ. So, we 2701 * only honor mesgout requests after we've sent our 2702 * first byte. 2703 */ 2704 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2705 && ahc->msgout_index > 0) 2706 msgout_request = TRUE; 2707 else 2708 msgout_request = FALSE; 2709 2710 if (msgout_request) { 2711 2712 /* 2713 * Change gears and see if 2714 * this messages is of interest to 2715 * us or should be passed back to 2716 * the sequencer. 2717 */ 2718 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2719 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2720 ahc->msgin_index = 0; 2721 /* Dummy read to REQ for first byte */ 2722 ahc_inb(ahc, SCSIDATL); 2723 ahc_outb(ahc, SXFRCTL0, 2724 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2725 break; 2726 } 2727 2728 msgdone = ahc->msgout_index == ahc->msgout_len; 2729 if (msgdone) { 2730 ahc_outb(ahc, SXFRCTL0, 2731 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2732 end_session = TRUE; 2733 break; 2734 } 2735 2736 /* 2737 * Present the next byte on the bus. 2738 */ 2739 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2740 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2741 break; 2742 } 2743 case MSG_TYPE_TARGET_MSGOUT: 2744 { 2745 int lastbyte; 2746 int msgdone; 2747 2748 /* 2749 * The initiator signals that this is 2750 * the last byte by dropping ATN. 2751 */ 2752 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2753 2754 /* 2755 * Read the latched byte, but turn off SPIOEN first 2756 * so that we don't inadvertantly cause a REQ for the 2757 * next byte. 2758 */ 2759 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2760 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2761 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2762 if (msgdone == MSGLOOP_TERMINATED) { 2763 /* 2764 * The message is *really* done in that it caused 2765 * us to go to bus free. The sequencer has already 2766 * been reset at this point, so pull the ejection 2767 * handle. 2768 */ 2769 return; 2770 } 2771 2772 ahc->msgin_index++; 2773 2774 /* 2775 * XXX Read spec about initiator dropping ATN too soon 2776 * and use msgdone to detect it. 2777 */ 2778 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2779 ahc->msgin_index = 0; 2780 2781 /* 2782 * If this message illicited a response, transition 2783 * to the Message in phase and send it. 2784 */ 2785 if (ahc->msgout_len != 0) { 2786 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2787 ahc_outb(ahc, SXFRCTL0, 2788 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2789 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2790 ahc->msgin_index = 0; 2791 break; 2792 } 2793 } 2794 2795 if (lastbyte) 2796 end_session = TRUE; 2797 else { 2798 /* Ask for the next byte. */ 2799 ahc_outb(ahc, SXFRCTL0, 2800 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2801 } 2802 2803 break; 2804 } 2805 default: 2806 panic("Unknown REQINIT message type"); 2807 } 2808 2809 if (end_session) { 2810 ahc_clear_msg_state(ahc); 2811 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2812 } else 2813 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2814 } 2815 2816 /* 2817 * See if we sent a particular extended message to the target. 2818 * If "full" is true, the target saw the full message. 2819 * If "full" is false, the target saw at least the first 2820 * byte of the message. 2821 */ 2822 static int 2823 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2824 { 2825 int found; 2826 int index; 2827 2828 found = FALSE; 2829 index = 0; 2830 2831 while (index < ahc->msgout_len) { 2832 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2833 2834 /* Found a candidate */ 2835 if (ahc->msgout_buf[index+2] == msgtype) { 2836 u_int end_index; 2837 2838 end_index = index + 1 2839 + ahc->msgout_buf[index + 1]; 2840 if (full) { 2841 if (ahc->msgout_index > end_index) 2842 found = TRUE; 2843 } else if (ahc->msgout_index > index) 2844 found = TRUE; 2845 } 2846 break; 2847 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2848 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2849 2850 /* Skip tag type and tag id or residue param*/ 2851 index += 2; 2852 } else { 2853 /* Single byte message */ 2854 index++; 2855 } 2856 } 2857 return (found); 2858 } 2859 2860 static int 2861 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2862 struct ahc_devinfo *devinfo) 2863 { 2864 struct ahc_initiator_tinfo *tinfo; 2865 struct tmode_tstate *tstate; 2866 int reject; 2867 int done; 2868 int response; 2869 u_int targ_scsirate; 2870 2871 done = MSGLOOP_IN_PROG; 2872 response = FALSE; 2873 reject = FALSE; 2874 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2875 devinfo->target, &tstate); 2876 targ_scsirate = tinfo->scsirate; 2877 2878 /* 2879 * Parse as much of the message as is availible, 2880 * rejecting it if we don't support it. When 2881 * the entire message is availible and has been 2882 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2883 * that we have parsed an entire message. 2884 * 2885 * In the case of extended messages, we accept the length 2886 * byte outright and perform more checking once we know the 2887 * extended message type. 2888 */ 2889 switch (ahc->msgin_buf[0]) { 2890 case MSG_MESSAGE_REJECT: 2891 response = ahc_handle_msg_reject(ahc, devinfo); 2892 /* FALLTHROUGH */ 2893 case MSG_NOOP: 2894 done = MSGLOOP_MSGCOMPLETE; 2895 break; 2896 case MSG_IGN_WIDE_RESIDUE: 2897 { 2898 /* Wait for the whole message */ 2899 if (ahc->msgin_index >= 1) { 2900 if (ahc->msgin_buf[1] != 1 2901 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2902 reject = TRUE; 2903 done = MSGLOOP_MSGCOMPLETE; 2904 } else 2905 ahc_handle_ign_wide_residue(ahc, devinfo); 2906 } 2907 break; 2908 } 2909 case MSG_EXTENDED: 2910 { 2911 /* Wait for enough of the message to begin validation */ 2912 if (ahc->msgin_index < 2) 2913 break; 2914 switch (ahc->msgin_buf[2]) { 2915 case MSG_EXT_SDTR: 2916 { 2917 const struct ahc_syncrate *syncrate; 2918 u_int period; 2919 u_int offset; 2920 u_int saved_offset; 2921 2922 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2923 reject = TRUE; 2924 break; 2925 } 2926 2927 /* 2928 * Wait until we have both args before validating 2929 * and acting on this message. 2930 * 2931 * Add one to MSG_EXT_SDTR_LEN to account for 2932 * the extended message preamble. 2933 */ 2934 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2935 break; 2936 2937 period = ahc->msgin_buf[3]; 2938 saved_offset = offset = ahc->msgin_buf[4]; 2939 syncrate = ahc_devlimited_syncrate(ahc, &period); 2940 ahc_validate_offset(ahc, syncrate, &offset, 2941 targ_scsirate & WIDEXFER); 2942 ahc_set_syncrate(ahc, devinfo, 2943 syncrate, period, offset, 2944 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2945 /*paused*/TRUE, /*done*/TRUE); 2946 2947 /* 2948 * See if we initiated Sync Negotiation 2949 * and didn't have to fall down to async 2950 * transfers. 2951 */ 2952 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2953 /* We started it */ 2954 if (saved_offset != offset) { 2955 /* Went too low - force async */ 2956 reject = TRUE; 2957 } 2958 } else { 2959 /* 2960 * Send our own SDTR in reply 2961 */ 2962 ahc->msgout_index = 0; 2963 ahc->msgout_len = 0; 2964 ahc_construct_sdtr(ahc, period, offset); 2965 ahc->msgout_index = 0; 2966 response = TRUE; 2967 } 2968 done = MSGLOOP_MSGCOMPLETE; 2969 break; 2970 } 2971 case MSG_EXT_WDTR: 2972 { 2973 u_int bus_width; 2974 u_int sending_reply; 2975 2976 sending_reply = FALSE; 2977 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2978 reject = TRUE; 2979 break; 2980 } 2981 2982 /* 2983 * Wait until we have our arg before validating 2984 * and acting on this message. 2985 * 2986 * Add one to MSG_EXT_WDTR_LEN to account for 2987 * the extended message preamble. 2988 */ 2989 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 2990 break; 2991 2992 bus_width = ahc->msgin_buf[3]; 2993 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 2994 /* 2995 * Don't send a WDTR back to the 2996 * target, since we asked first. 2997 */ 2998 switch (bus_width){ 2999 default: 3000 /* 3001 * How can we do anything greater 3002 * than 16bit transfers on a 16bit 3003 * bus? 3004 */ 3005 reject = TRUE; 3006 printf("%s: target %d requested %dBit " 3007 "transfers. Rejecting...\n", 3008 ahc_name(ahc), devinfo->target, 3009 8 * (0x01 << bus_width)); 3010 /* FALLTHROUGH */ 3011 case MSG_EXT_WDTR_BUS_8_BIT: 3012 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3013 break; 3014 case MSG_EXT_WDTR_BUS_16_BIT: 3015 break; 3016 } 3017 } else { 3018 /* 3019 * Send our own WDTR in reply 3020 */ 3021 switch (bus_width) { 3022 default: 3023 if (ahc->features & AHC_WIDE) { 3024 /* Respond Wide */ 3025 bus_width = 3026 MSG_EXT_WDTR_BUS_16_BIT; 3027 break; 3028 } 3029 /* FALLTHROUGH */ 3030 case MSG_EXT_WDTR_BUS_8_BIT: 3031 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3032 break; 3033 } 3034 ahc->msgout_index = 0; 3035 ahc->msgout_len = 0; 3036 ahc_construct_wdtr(ahc, bus_width); 3037 ahc->msgout_index = 0; 3038 response = TRUE; 3039 sending_reply = TRUE; 3040 } 3041 ahc_set_width(ahc, devinfo, bus_width, 3042 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3043 /*paused*/TRUE, /*done*/TRUE); 3044 3045 /* After a wide message, we are async */ 3046 ahc_set_syncrate(ahc, devinfo, 3047 /*syncrate*/NULL, /*period*/0, 3048 /*offset*/0, AHC_TRANS_ACTIVE, 3049 /*paused*/TRUE, /*done*/FALSE); 3050 if (sending_reply == FALSE && reject == FALSE) { 3051 3052 if (tinfo->goal.period) { 3053 const struct ahc_syncrate *rate; 3054 u_int period; 3055 u_int offset; 3056 3057 /* Start the sync negotiation */ 3058 period = tinfo->goal.period; 3059 rate = ahc_devlimited_syncrate(ahc, 3060 &period); 3061 offset = tinfo->goal.offset; 3062 ahc_validate_offset(ahc, rate, &offset, 3063 tinfo->current.width); 3064 ahc->msgout_index = 0; 3065 ahc->msgout_len = 0; 3066 ahc_construct_sdtr(ahc, period, offset); 3067 ahc->msgout_index = 0; 3068 response = TRUE; 3069 } 3070 } 3071 done = MSGLOOP_MSGCOMPLETE; 3072 break; 3073 } 3074 default: 3075 /* Unknown extended message. Reject it. */ 3076 reject = TRUE; 3077 break; 3078 } 3079 break; 3080 } 3081 case MSG_BUS_DEV_RESET: 3082 ahc_handle_devreset(ahc, devinfo, 3083 XS_RESET, "Bus Device Reset Received", 3084 /*verbose_level*/0); 3085 restart_sequencer(ahc); 3086 done = MSGLOOP_TERMINATED; 3087 break; 3088 case MSG_ABORT_TAG: 3089 case MSG_ABORT: 3090 case MSG_CLEAR_QUEUE: 3091 /* Target mode messages */ 3092 if (devinfo->role != ROLE_TARGET) { 3093 reject = TRUE; 3094 break; 3095 } 3096 #if AHC_TARGET_MODE 3097 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3098 devinfo->lun, 3099 ahc->msgin_buf[0] == MSG_ABORT_TAG 3100 ? SCB_LIST_NULL 3101 : ahc_inb(ahc, INITIATOR_TAG), 3102 ROLE_TARGET, XS_DRIVER_STUFFUP); 3103 3104 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3105 if (tstate != NULL) { 3106 struct tmode_lstate* lstate; 3107 3108 lstate = tstate->enabled_luns[devinfo->lun]; 3109 if (lstate != NULL) { 3110 ahc_queue_lstate_event(ahc, lstate, 3111 devinfo->our_scsiid, 3112 ahc->msgin_buf[0], 3113 /*arg*/0); 3114 ahc_send_lstate_events(ahc, lstate); 3115 } 3116 } 3117 done = MSGLOOP_MSGCOMPLETE; 3118 #else 3119 panic("ahc: got target mode message"); 3120 #endif 3121 break; 3122 case MSG_TERM_IO_PROC: 3123 default: 3124 reject = TRUE; 3125 break; 3126 } 3127 3128 if (reject) { 3129 /* 3130 * Setup to reject the message. 3131 */ 3132 ahc->msgout_index = 0; 3133 ahc->msgout_len = 1; 3134 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3135 done = MSGLOOP_MSGCOMPLETE; 3136 response = TRUE; 3137 } 3138 3139 if (done != MSGLOOP_IN_PROG && !response) 3140 /* Clear the outgoing message buffer */ 3141 ahc->msgout_len = 0; 3142 3143 return (done); 3144 } 3145 3146 static void 3147 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3148 { 3149 u_int scb_index; 3150 struct scb *scb; 3151 3152 scb_index = ahc_inb(ahc, SCB_TAG); 3153 scb = &ahc->scb_data->scbarray[scb_index]; 3154 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3155 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3156 /* 3157 * Ignore the message if we haven't 3158 * seen an appropriate data phase yet. 3159 */ 3160 } else { 3161 /* 3162 * If the residual occurred on the last 3163 * transfer and the transfer request was 3164 * expected to end on an odd count, do 3165 * nothing. Otherwise, subtract a byte 3166 * and update the residual count accordingly. 3167 */ 3168 u_int resid_sgcnt; 3169 3170 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3171 if (resid_sgcnt == 0 3172 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3173 /* 3174 * If the residual occurred on the last 3175 * transfer and the transfer request was 3176 * expected to end on an odd count, do 3177 * nothing. 3178 */ 3179 } else { 3180 u_int data_cnt; 3181 u_int32_t data_addr; 3182 u_int sg_index; 3183 3184 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3185 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3186 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3187 3188 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3189 | (ahc_inb(ahc, SHADDR + 2) << 16) 3190 | (ahc_inb(ahc, SHADDR + 1) << 8) 3191 | (ahc_inb(ahc, SHADDR)); 3192 3193 data_cnt += 1; 3194 data_addr -= 1; 3195 3196 sg_index = scb->sg_count - resid_sgcnt; 3197 3198 if (sg_index != 0 3199 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3200 u_int32_t sg_addr; 3201 3202 sg_index--; 3203 data_cnt = 1; 3204 data_addr = le32toh(scb->sg_list[sg_index].addr) 3205 + le32toh(scb->sg_list[sg_index].len) 3206 - 1; 3207 3208 /* 3209 * The physical address base points to the 3210 * second entry as it is always used for 3211 * calculating the "next S/G pointer". 3212 */ 3213 sg_addr = scb->sg_list_phys 3214 + (sg_index* sizeof(*scb->sg_list)); 3215 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3216 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3217 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3218 ahc_outb(ahc, SG_NEXT, sg_addr); 3219 } 3220 3221 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3222 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3223 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3224 3225 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3226 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3227 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3228 ahc_outb(ahc, SHADDR, data_addr); 3229 } 3230 } 3231 } 3232 3233 static void 3234 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3235 int status, char *message, 3236 int verbose_level) 3237 { 3238 int found; 3239 3240 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3241 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3242 status); 3243 3244 /* 3245 * Go back to async/narrow transfers and renegotiate. 3246 * ahc_set_width and ahc_set_syncrate can cope with NULL 3247 * paths. 3248 */ 3249 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3250 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3251 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3252 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3253 /*paused*/TRUE, /*done*/FALSE); 3254 3255 if (message != NULL && (verbose_level <= 0)) 3256 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3257 message, devinfo->channel, devinfo->target, found); 3258 } 3259 3260 /* 3261 * We have an scb which has been processed by the 3262 * adaptor, now we look to see how the operation 3263 * went. 3264 */ 3265 static void 3266 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3267 { 3268 struct scsipi_xfer *xs; 3269 struct scsipi_periph *periph; 3270 int requeue = 0; 3271 int target; 3272 3273 3274 xs = scb->xs; 3275 periph = xs->xs_periph; 3276 LIST_REMOVE(scb, plinks); 3277 3278 callout_stop(&scb->xs->xs_callout); 3279 3280 #ifdef AHC_DEBUG 3281 if (ahc_debug & AHC_SHOWCMDS) { 3282 scsipi_printaddr(periph); 3283 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3284 scb->hscb->tag); 3285 } 3286 #endif 3287 3288 target = periph->periph_target; 3289 3290 if (xs->datalen) { 3291 int op; 3292 3293 if (xs->xs_control & XS_CTL_DATA_IN) 3294 op = BUS_DMASYNC_POSTREAD; 3295 else 3296 op = BUS_DMASYNC_POSTWRITE; 3297 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3298 scb->dmamap->dm_mapsize, op); 3299 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3300 } 3301 3302 /* 3303 * Unbusy this target/channel/lun. 3304 * XXX if we are holding two commands per lun, 3305 * send the next command. 3306 */ 3307 if (!(scb->hscb->control & TAG_ENB)) 3308 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3309 3310 /* 3311 * If the recovery SCB completes, we have to be 3312 * out of our timeout. 3313 */ 3314 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3315 3316 struct scb *scbp; 3317 3318 /* 3319 * We were able to complete the command successfully, 3320 * so reinstate the timeouts for all other pending 3321 * commands. 3322 */ 3323 scbp = ahc->pending_ccbs.lh_first; 3324 while (scbp != NULL) { 3325 struct scsipi_xfer *txs = scbp->xs; 3326 3327 if (!(txs->xs_control & XS_CTL_POLL)) { 3328 callout_reset(&scbp->xs->xs_callout, 3329 (scbp->xs->timeout * hz) / 1000, 3330 ahc_timeout, scbp); 3331 } 3332 scbp = LIST_NEXT(scbp, plinks); 3333 } 3334 3335 /* 3336 * Ensure that we didn't put a second instance of this 3337 * SCB into the QINFIFO. 3338 */ 3339 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3340 SCB_LUN(scb), scb->hscb->tag, 3341 ROLE_INITIATOR, /*status*/0, 3342 SEARCH_REMOVE); 3343 if (xs->error != XS_NOERROR) 3344 ahcsetccbstatus(xs, XS_TIMEOUT); 3345 scsipi_printaddr(xs->xs_periph); 3346 printf("no longer in timeout, status = %x\n", xs->status); 3347 } 3348 3349 if (xs->error != XS_NOERROR) { 3350 /* Don't clobber any existing error state */ 3351 } else if ((scb->flags & SCB_SENSE) != 0) { 3352 /* 3353 * We performed autosense retrieval. 3354 * 3355 * bzero the sense data before having 3356 * the drive fill it. The SCSI spec mandates 3357 * that any untransfered data should be 3358 * assumed to be zero. Complete the 'bounce' 3359 * of sense information through buffers accessible 3360 * via bus-space by copying it into the clients 3361 * csio. 3362 */ 3363 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3364 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3365 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3366 xs->error = XS_SENSE; 3367 } 3368 if (scb->flags & SCB_FREEZE_QUEUE) { 3369 scsipi_periph_thaw(periph, 1); 3370 scb->flags &= ~SCB_FREEZE_QUEUE; 3371 } 3372 3373 requeue = scb->flags & SCB_REQUEUE; 3374 ahcfreescb(ahc, scb); 3375 3376 if (requeue) { 3377 xs->error = XS_REQUEUE; 3378 } 3379 scsipi_done(xs); 3380 } 3381 3382 /* 3383 * Determine the number of SCBs available on the controller 3384 */ 3385 int 3386 ahc_probe_scbs(struct ahc_softc *ahc) { 3387 int i; 3388 3389 for (i = 0; i < AHC_SCB_MAX; i++) { 3390 ahc_outb(ahc, SCBPTR, i); 3391 ahc_outb(ahc, SCB_CONTROL, i); 3392 if (ahc_inb(ahc, SCB_CONTROL) != i) 3393 break; 3394 ahc_outb(ahc, SCBPTR, 0); 3395 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3396 break; 3397 } 3398 return (i); 3399 } 3400 3401 /* 3402 * Start the board, ready for normal operation 3403 */ 3404 int 3405 ahc_init(struct ahc_softc *ahc) 3406 { 3407 int max_targ = 15; 3408 int i; 3409 int term; 3410 u_int scsi_conf; 3411 u_int scsiseq_template; 3412 u_int ultraenb; 3413 u_int discenable; 3414 u_int tagenable; 3415 size_t driver_data_size; 3416 u_int32_t physaddr; 3417 3418 #ifdef AHC_PRINT_SRAM 3419 printf("Scratch Ram:"); 3420 for (i = 0x20; i < 0x5f; i++) { 3421 if (((i % 8) == 0) && (i != 0)) { 3422 printf ("\n "); 3423 } 3424 printf (" 0x%x", ahc_inb(ahc, i)); 3425 } 3426 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3427 for (i = 0x70; i < 0x7f; i++) { 3428 if (((i % 8) == 0) && (i != 0)) { 3429 printf ("\n "); 3430 } 3431 printf (" 0x%x", ahc_inb(ahc, i)); 3432 } 3433 } 3434 printf ("\n"); 3435 #endif 3436 3437 /* 3438 * Assume we have a board at this stage and it has been reset. 3439 */ 3440 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3441 ahc->our_id = ahc->our_id_b = 7; 3442 3443 /* 3444 * Default to allowing initiator operations. 3445 */ 3446 ahc->flags |= AHC_INITIATORMODE; 3447 3448 /* 3449 * DMA tag for our command fifos and other data in system memory 3450 * the card's sequencer must be able to access. For initiator 3451 * roles, we need to allocate space for the qinfifo, qoutfifo, 3452 * and untagged_scb arrays each of which are composed of 256 3453 * 1 byte elements. When providing for the target mode role, 3454 * we additionally must provide space for the incoming target 3455 * command fifo. 3456 */ 3457 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3458 3459 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3460 ahc->sc_dmaflags, 3461 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3462 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3463 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3464 return (ENOMEM); 3465 3466 ahc->init_level++; 3467 3468 /* Allocate SCB data now that parent_dmat is initialized */ 3469 if (ahc->scb_data->maxhscbs == 0) 3470 if (ahcinitscbdata(ahc) != 0) 3471 return (ENOMEM); 3472 3473 ahc->qinfifo = &ahc->qoutfifo[256]; 3474 ahc->untagged_scbs = &ahc->qinfifo[256]; 3475 /* There are no untagged SCBs active yet. */ 3476 for (i = 0; i < 256; i++) 3477 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3478 3479 /* All of our queues are empty */ 3480 for (i = 0; i < 256; i++) 3481 ahc->qoutfifo[i] = SCB_LIST_NULL; 3482 3483 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3484 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3485 3486 /* 3487 * Allocate a tstate to house information for our 3488 * initiator presence on the bus as well as the user 3489 * data for any target mode initiator. 3490 */ 3491 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3492 printf("%s: unable to allocate tmode_tstate. " 3493 "Failing attach\n", ahc_name(ahc)); 3494 return (-1); 3495 } 3496 3497 if ((ahc->features & AHC_TWIN) != 0) { 3498 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3499 printf("%s: unable to allocate tmode_tstate. " 3500 "Failing attach\n", ahc_name(ahc)); 3501 return (-1); 3502 } 3503 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3504 ahc->our_id, ahc->our_id_b, 3505 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3506 } else { 3507 if ((ahc->features & AHC_WIDE) != 0) { 3508 printf("Wide "); 3509 } else { 3510 printf("Single "); 3511 } 3512 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3513 } 3514 3515 ahc_outb(ahc, SEQ_FLAGS, 0); 3516 3517 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3518 ahc->flags |= AHC_PAGESCBS; 3519 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3520 } else { 3521 ahc->flags &= ~AHC_PAGESCBS; 3522 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3523 } 3524 3525 #ifdef AHC_DEBUG 3526 if (ahc_debug & AHC_SHOWMISC) { 3527 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3528 "ahc_dma %d bytes\n", 3529 ahc_name(ahc), 3530 sizeof(struct hardware_scb), 3531 sizeof(struct scb), 3532 sizeof(struct ahc_dma_seg)); 3533 } 3534 #endif /* AHC_DEBUG */ 3535 3536 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3537 if (ahc->features & AHC_TWIN) { 3538 3539 /* 3540 * The device is gated to channel B after a chip reset, 3541 * so set those values first 3542 */ 3543 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3544 if ((ahc->features & AHC_ULTRA2) != 0) 3545 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3546 else 3547 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3548 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3549 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3550 |term|ENSTIMER|ACTNEGEN); 3551 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3552 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3553 3554 if ((scsi_conf & RESET_SCSI) != 0 3555 && (ahc->flags & AHC_INITIATORMODE) != 0) 3556 ahc->flags |= AHC_RESET_BUS_B; 3557 3558 /* Select Channel A */ 3559 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3560 } 3561 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3562 if ((ahc->features & AHC_ULTRA2) != 0) 3563 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3564 else 3565 ahc_outb(ahc, SCSIID, ahc->our_id); 3566 scsi_conf = ahc_inb(ahc, SCSICONF); 3567 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3568 |term 3569 |ENSTIMER|ACTNEGEN); 3570 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3571 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3572 3573 if ((scsi_conf & RESET_SCSI) != 0 3574 && (ahc->flags & AHC_INITIATORMODE) != 0) 3575 ahc->flags |= AHC_RESET_BUS_A; 3576 3577 /* 3578 * Look at the information that board initialization or 3579 * the board bios has left us. 3580 */ 3581 ultraenb = 0; 3582 tagenable = ALL_TARGETS_MASK; 3583 3584 /* Grab the disconnection disable table and invert it for our needs */ 3585 if (ahc->flags & AHC_USEDEFAULTS) { 3586 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3587 "device parameters\n", ahc_name(ahc)); 3588 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3589 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3590 discenable = ALL_TARGETS_MASK; 3591 if ((ahc->features & AHC_ULTRA) != 0) 3592 ultraenb = ALL_TARGETS_MASK; 3593 } else { 3594 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3595 | ahc_inb(ahc, DISC_DSB)); 3596 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3597 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3598 | ahc_inb(ahc, ULTRA_ENB); 3599 } 3600 3601 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3602 max_targ = 7; 3603 3604 for (i = 0; i <= max_targ; i++) { 3605 struct ahc_initiator_tinfo *tinfo; 3606 struct tmode_tstate *tstate; 3607 u_int our_id; 3608 u_int target_id; 3609 char channel; 3610 3611 channel = 'A'; 3612 our_id = ahc->our_id; 3613 target_id = i; 3614 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3615 channel = 'B'; 3616 our_id = ahc->our_id_b; 3617 target_id = i % 8; 3618 } 3619 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3620 target_id, &tstate); 3621 /* Default to async narrow across the board */ 3622 bzero(tinfo, sizeof(*tinfo)); 3623 if (ahc->flags & AHC_USEDEFAULTS) { 3624 if ((ahc->features & AHC_WIDE) != 0) 3625 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3626 3627 /* 3628 * These will be truncated when we determine the 3629 * connection type we have with the target. 3630 */ 3631 tinfo->user.period = ahc_syncrates->period; 3632 tinfo->user.offset = ~0; 3633 } else { 3634 u_int scsirate; 3635 u_int16_t mask; 3636 3637 /* Take the settings leftover in scratch RAM. */ 3638 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3639 mask = (0x01 << i); 3640 if ((ahc->features & AHC_ULTRA2) != 0) { 3641 u_int offset; 3642 u_int maxsync; 3643 3644 if ((scsirate & SOFS) == 0x0F) { 3645 /* 3646 * Haven't negotiated yet, 3647 * so the format is different. 3648 */ 3649 scsirate = (scsirate & SXFR) >> 4 3650 | (ultraenb & mask) 3651 ? 0x08 : 0x0 3652 | (scsirate & WIDEXFER); 3653 offset = MAX_OFFSET_ULTRA2; 3654 } else 3655 offset = ahc_inb(ahc, TARG_OFFSET + i); 3656 maxsync = AHC_SYNCRATE_ULTRA2; 3657 if ((ahc->features & AHC_DT) != 0) 3658 maxsync = AHC_SYNCRATE_DT; 3659 tinfo->user.period = 3660 ahc_find_period(ahc, scsirate, maxsync); 3661 if (offset == 0) 3662 tinfo->user.period = 0; 3663 else 3664 tinfo->user.offset = ~0; 3665 } else if ((scsirate & SOFS) != 0) { 3666 tinfo->user.period = 3667 ahc_find_period(ahc, scsirate, 3668 (ultraenb & mask) 3669 ? AHC_SYNCRATE_ULTRA 3670 : AHC_SYNCRATE_FAST); 3671 if (tinfo->user.period != 0) 3672 tinfo->user.offset = ~0; 3673 } 3674 if ((scsirate & WIDEXFER) != 0 3675 && (ahc->features & AHC_WIDE) != 0) 3676 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3677 } 3678 tinfo->goal = tinfo->user; /* force negotiation */ 3679 tstate->ultraenb = ultraenb; 3680 tstate->discenable = discenable; 3681 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3682 tstate->tagdisable = 0; 3683 } 3684 ahc->user_discenable = discenable; 3685 ahc->user_tagenable = tagenable; 3686 3687 /* 3688 * Tell the sequencer where it can find our arrays in memory. 3689 */ 3690 physaddr = ahc->scb_data->hscb_busaddr; 3691 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3692 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3693 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3694 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3695 3696 physaddr = ahc->shared_data_busaddr; 3697 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3698 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3699 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3700 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3701 3702 /* Target mode incomding command fifo */ 3703 physaddr += 3 * 256 * sizeof(u_int8_t); 3704 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3705 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3706 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3707 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3708 3709 /* 3710 * Initialize the group code to command length table. 3711 * This overrides the values in TARG_SCSIRATE, so only 3712 * setup the table after we have processed that information. 3713 */ 3714 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3715 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3716 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3717 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3718 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3719 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3720 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3721 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3722 3723 /* Tell the sequencer of our initial queue positions */ 3724 ahc_outb(ahc, KERNEL_QINPOS, 0); 3725 ahc_outb(ahc, QINPOS, 0); 3726 ahc_outb(ahc, QOUTPOS, 0); 3727 3728 #ifdef AHC_DEBUG 3729 if (ahc_debug & AHC_SHOWMISC) 3730 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3731 discenable, ultraenb); 3732 #endif 3733 3734 /* Don't have any special messages to send to targets */ 3735 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3736 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3737 3738 /* 3739 * Use the built in queue management registers 3740 * if they are available. 3741 */ 3742 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3743 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3744 ahc_outb(ahc, SDSCB_QOFF, 0); 3745 ahc_outb(ahc, SNSCB_QOFF, 0); 3746 ahc_outb(ahc, HNSCB_QOFF, 0); 3747 } 3748 3749 3750 /* We don't have any waiting selections */ 3751 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3752 3753 /* Our disconnection list is empty too */ 3754 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3755 3756 /* Message out buffer starts empty */ 3757 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3758 3759 /* 3760 * Setup the allowed SCSI Sequences based on operational mode. 3761 * If we are a target, we'll enable select in operations once 3762 * we've had a lun enabled. 3763 */ 3764 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3765 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3766 scsiseq_template |= ENRSELI; 3767 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3768 3769 /* 3770 * Load the Sequencer program and Enable the adapter 3771 * in "fast" mode. 3772 */ 3773 #ifdef AHC_DEBUG 3774 printf("%s: Downloading Sequencer Program...", 3775 ahc_name(ahc)); 3776 #endif 3777 3778 ahc_loadseq(ahc); 3779 3780 /* We have to wait until after any system dumps... */ 3781 shutdownhook_establish(ahc_shutdown, ahc); 3782 3783 return (0); 3784 } 3785 3786 static int 3787 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3788 struct proc *p) 3789 { 3790 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3791 int s, ret = ENOTTY; 3792 3793 switch (cmd) { 3794 case SCBUSIORESET: 3795 s = splbio(); 3796 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3797 TRUE); 3798 splx(s); 3799 ret = 0; 3800 break; 3801 default: 3802 break; 3803 } 3804 3805 return ret; 3806 } 3807 3808 3809 /* 3810 * XXX fvdl the busy_tcl checks and settings should only be done 3811 * for the non-tagged queueing case, but we don't do tagged queueing 3812 * yet, so.. 3813 */ 3814 static void 3815 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3816 { 3817 struct scsipi_xfer *xs; 3818 struct scsipi_periph *periph; 3819 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3820 struct scb *scb; 3821 struct hardware_scb *hscb; 3822 struct ahc_initiator_tinfo *tinfo; 3823 struct tmode_tstate *tstate; 3824 u_int target_id; 3825 u_int our_id; 3826 int s, tcl; 3827 u_int16_t mask; 3828 char channel; 3829 3830 switch (req) { 3831 case ADAPTER_REQ_RUN_XFER: 3832 xs = arg; 3833 periph = xs->xs_periph; 3834 3835 SC_DEBUG(periph, SDEV_DB3, ("ahc_action\n")); 3836 3837 /* must protect the queue */ 3838 s = splbio(); 3839 3840 tcl = XS_TCL(ahc, xs); 3841 3842 if (!ahc_istagged_device(ahc, xs, 0) && 3843 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3844 panic("ahc_action: not tagged and device busy"); 3845 } 3846 3847 3848 target_id = periph->periph_target; 3849 our_id = SIM_SCSI_ID(ahc, periph); 3850 3851 /* 3852 * get an scb to use. 3853 */ 3854 if ((scb = ahcgetscb(ahc)) == NULL) { 3855 xs->error = XS_RESOURCE_SHORTAGE; 3856 scsipi_done(xs); 3857 splx(s); 3858 return; 3859 } 3860 3861 tcl = XS_TCL(ahc, xs); 3862 3863 #ifdef DIAGNOSTIC 3864 if (!ahc_istagged_device(ahc, xs, 0) && 3865 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3866 panic("ahc: queuing for busy target"); 3867 #endif 3868 3869 scb->xs = xs; 3870 hscb = scb->hscb; 3871 hscb->tcl = tcl; 3872 3873 if (xs->xs_tag_type) { 3874 #ifdef DIAGNOSTIC 3875 if (ahc_istagged_device(ahc, xs, 0) == 0) 3876 panic("ahc_action: taggged command for untagged device"); 3877 #endif 3878 scb->hscb->control |= TAG_ENB; 3879 } else 3880 ahc_busy_tcl(ahc, scb); 3881 3882 splx(s); 3883 3884 channel = SIM_CHANNEL(ahc, periph); 3885 if (ahc->inited_channels[channel - 'A'] == 0) { 3886 if ((channel == 'A' && 3887 (ahc->flags & AHC_RESET_BUS_A)) || 3888 (channel == 'B' && 3889 (ahc->flags & AHC_RESET_BUS_B))) { 3890 s = splbio(); 3891 ahc_reset_channel(ahc, channel, TRUE); 3892 splx(s); 3893 } 3894 ahc->inited_channels[channel - 'A'] = 1; 3895 } 3896 3897 /* 3898 * Put all the arguments for the xfer in the scb 3899 */ 3900 3901 mask = SCB_TARGET_MASK(scb); 3902 tinfo = ahc_fetch_transinfo(ahc, 3903 SIM_CHANNEL(ahc, periph), 3904 our_id, target_id, &tstate); 3905 if (ahc->inited_targets[target_id] == 0) { 3906 struct ahc_devinfo devinfo; 3907 3908 s = splbio(); 3909 ahc_compile_devinfo(&devinfo, our_id, target_id, 3910 periph->periph_lun, 3911 SIM_CHANNEL(ahc, periph), 3912 ROLE_INITIATOR); 3913 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3914 TRUE, FALSE); 3915 ahc->inited_targets[target_id] = 1; 3916 splx(s); 3917 } 3918 3919 hscb->scsirate = tinfo->scsirate; 3920 hscb->scsioffset = tinfo->current.offset; 3921 if ((tstate->ultraenb & mask) != 0) 3922 hscb->control |= ULTRAENB; 3923 3924 if ((tstate->discenable & mask) != 0) 3925 hscb->control |= DISCENB; 3926 3927 if (xs->xs_control & XS_CTL_RESET) { 3928 hscb->cmdpointer = 0; 3929 scb->flags |= SCB_DEVICE_RESET; 3930 hscb->control |= MK_MESSAGE; 3931 ahc_execute_scb(scb, NULL, 0); 3932 } 3933 3934 ahc_setup_data(ahc, xs, scb); 3935 return; 3936 case ADAPTER_REQ_GROW_RESOURCES: 3937 /* XXX not supported */ 3938 return; 3939 case ADAPTER_REQ_SET_XFER_MODE: 3940 { 3941 struct scsipi_xfer_mode *xm = arg; 3942 struct ahc_devinfo devinfo; 3943 int target_id, our_id; 3944 char channel; 3945 3946 target_id = xm->xm_target; 3947 our_id = chan->chan_id; 3948 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 3949 s = splbio(); 3950 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 3951 &tstate); 3952 ahc_compile_devinfo(&devinfo, our_id, target_id, 3953 0, channel, ROLE_INITIATOR); 3954 if (xm->xm_mode & PERIPH_CAP_TQING && 3955 (tstate->tagdisable & devinfo.target_mask) == 0) { 3956 ahc_set_tags(ahc, &devinfo, TRUE); 3957 printf("%s: target %d using tagged queuing\n", 3958 ahc_name(ahc), target_id); 3959 } 3960 splx(s); 3961 } 3962 } 3963 } 3964 3965 static void 3966 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 3967 { 3968 struct scb *scb; 3969 struct scsipi_xfer *xs; 3970 struct ahc_softc *ahc; 3971 int s; 3972 3973 scb = (struct scb *)arg; 3974 xs = scb->xs; 3975 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 3976 3977 3978 if (nsegments != 0) { 3979 struct ahc_dma_seg *sg; 3980 bus_dma_segment_t *end_seg; 3981 int op; 3982 3983 end_seg = dm_segs + nsegments; 3984 3985 /* Copy the first SG into the data pointer area */ 3986 scb->hscb->data = dm_segs->ds_addr; 3987 scb->hscb->datalen = dm_segs->ds_len; 3988 3989 /* Copy the segments into our SG list */ 3990 sg = scb->sg_list; 3991 while (dm_segs < end_seg) { 3992 sg->addr = dm_segs->ds_addr; 3993 sg->len = dm_segs->ds_len; 3994 ahc_swap_sg(sg); 3995 sg++; 3996 dm_segs++; 3997 } 3998 3999 /* Note where to find the SG entries in bus space */ 4000 scb->hscb->SG_pointer = scb->sg_list_phys; 4001 4002 if (xs->xs_control & XS_CTL_DATA_IN) 4003 op = BUS_DMASYNC_PREREAD; 4004 else 4005 op = BUS_DMASYNC_PREWRITE; 4006 4007 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4008 scb->dmamap->dm_mapsize, op); 4009 4010 } else { 4011 scb->hscb->SG_pointer = 0; 4012 scb->hscb->data = 0; 4013 scb->hscb->datalen = 0; 4014 } 4015 4016 scb->sg_count = scb->hscb->SG_count = nsegments; 4017 4018 s = splbio(); 4019 4020 /* 4021 * Last time we need to check if this SCB needs to 4022 * be aborted. 4023 */ 4024 if (xs->xs_status & XS_STS_DONE) { 4025 if (!ahc_istagged_device(ahc, xs, 0)) 4026 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4027 if (nsegments != 0) 4028 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4029 ahcfreescb(ahc, scb); 4030 splx(s); 4031 return; 4032 } 4033 4034 #ifdef DIAGNOSTIC 4035 if (scb->sg_count > 255) 4036 panic("ahc bad sg_count"); 4037 #endif 4038 4039 ahc_swap_hscb(scb->hscb); 4040 4041 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4042 4043 scb->flags |= SCB_ACTIVE; 4044 4045 if (!(xs->xs_control & XS_CTL_POLL)) 4046 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4047 ahc_timeout, scb); 4048 4049 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4050 #if 0 4051 printf("Continueing Immediate Command %d:%d\n", 4052 xs->xs_periph->periph_target, 4053 xs->xs_periph->periph_lun); 4054 #endif 4055 pause_sequencer(ahc); 4056 if ((ahc->flags & AHC_PAGESCBS) == 0) 4057 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4058 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4059 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4060 unpause_sequencer(ahc); 4061 } else { 4062 4063 #if 0 4064 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4065 scb->hscb->tag, ahc->qinfifonext, 4066 &ahc->qinfifo[ahc->qinfifonext], 4067 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4068 #endif 4069 4070 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4071 4072 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4073 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4074 4075 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4076 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4077 } else { 4078 pause_sequencer(ahc); 4079 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4080 unpause_sequencer(ahc); 4081 } 4082 } 4083 4084 #ifdef AHC_DEBUG 4085 if (ahc_debug & AHC_SHOWCMDS) { 4086 scsi_print_addr(xs->xs_periph); 4087 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4088 " rate %x\n", 4089 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4090 scb->flags, scb->hscb->control, ahc->qinfifonext, 4091 scb->hscb->scsirate); 4092 } 4093 #endif 4094 4095 if (!(xs->xs_control & XS_CTL_POLL)) { 4096 splx(s); 4097 return; 4098 } 4099 /* 4100 * If we can't use interrupts, poll for completion 4101 */ 4102 SC_DEBUG(xs->xs_periph, SDEV_DB3, ("cmd_poll\n")); 4103 do { 4104 if (ahc_poll(ahc, xs->timeout)) { 4105 if (!(xs->xs_control & XS_CTL_SILENT)) 4106 printf("cmd fail\n"); 4107 ahc_timeout(scb); 4108 break; 4109 } 4110 } while (!(xs->xs_status & XS_STS_DONE)); 4111 splx(s); 4112 return; 4113 } 4114 4115 static int 4116 ahc_poll(struct ahc_softc *ahc, int wait) 4117 { 4118 while (--wait) { 4119 DELAY(1000); 4120 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4121 break; 4122 } 4123 4124 if (wait == 0) { 4125 printf("%s: board is not responding\n", ahc_name(ahc)); 4126 return (EIO); 4127 } 4128 4129 ahc_intr((void *)ahc); 4130 return (0); 4131 } 4132 4133 static void 4134 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4135 struct scb *scb) 4136 { 4137 struct hardware_scb *hscb; 4138 4139 hscb = scb->hscb; 4140 xs->resid = xs->status = 0; 4141 4142 hscb->cmdlen = xs->cmdlen; 4143 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4144 hscb->cmdpointer = hscb->cmdstore_busaddr; 4145 4146 /* Only use S/G if there is a transfer */ 4147 if (xs->datalen) { 4148 int error; 4149 4150 error = bus_dmamap_load(ahc->parent_dmat, 4151 scb->dmamap, xs->data, 4152 xs->datalen, NULL, 4153 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4154 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4155 BUS_DMA_STREAMING); 4156 if (error) { 4157 if (!ahc_istagged_device(ahc, xs, 0)) 4158 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4159 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4160 scsipi_done(xs); 4161 return; 4162 } 4163 ahc_execute_scb(scb, 4164 scb->dmamap->dm_segs, 4165 scb->dmamap->dm_nsegs); 4166 } else { 4167 ahc_execute_scb(scb, NULL, 0); 4168 } 4169 } 4170 4171 static void 4172 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4173 { 4174 int target; 4175 char channel; 4176 int lun; 4177 4178 target = periph->periph_target; 4179 lun = periph->periph_lun; 4180 channel = periph->periph_channel->chan_channel; 4181 4182 ahc_search_qinfifo(ahc, target, channel, lun, 4183 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4184 SCB_REQUEUE, SEARCH_COMPLETE); 4185 } 4186 4187 static void 4188 ahcallocscbs(struct ahc_softc *ahc) 4189 { 4190 struct scb_data *scb_data; 4191 struct scb *next_scb; 4192 struct sg_map_node *sg_map; 4193 bus_addr_t physaddr; 4194 struct ahc_dma_seg *segs; 4195 int newcount; 4196 int i; 4197 4198 scb_data = ahc->scb_data; 4199 if (scb_data->numscbs >= AHC_SCB_MAX) 4200 /* Can't allocate any more */ 4201 return; 4202 4203 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4204 4205 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4206 4207 if (sg_map == NULL) 4208 return; 4209 4210 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4211 &sg_map->sg_dmamap, 4212 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4213 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4214 "SG space") < 0) { 4215 free(sg_map, M_DEVBUF); 4216 return; 4217 } 4218 4219 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4220 4221 segs = sg_map->sg_vaddr; 4222 physaddr = sg_map->sg_physaddr; 4223 4224 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4225 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4226 int error; 4227 4228 next_scb->sg_list = segs; 4229 /* 4230 * The sequencer always starts with the second entry. 4231 * The first entry is embedded in the scb. 4232 */ 4233 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4234 next_scb->flags = SCB_FREE; 4235 error = bus_dmamap_create(ahc->parent_dmat, 4236 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4237 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4238 &next_scb->dmamap); 4239 if (error != 0) 4240 break; 4241 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4242 next_scb->hscb->tag = ahc->scb_data->numscbs; 4243 next_scb->hscb->cmdstore_busaddr = 4244 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4245 + offsetof(struct hardware_scb, cmdstore); 4246 next_scb->hscb->cmdstore_busaddr = 4247 htole32(next_scb->hscb->cmdstore_busaddr); 4248 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4249 segs += AHC_NSEG; 4250 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4251 next_scb++; 4252 ahc->scb_data->numscbs++; 4253 } 4254 #ifdef AHC_DEBUG 4255 if (ahc_debug & AHC_SHOWSCBALLOC) 4256 printf("%s: allocated %d new SCBs count now %d\n", 4257 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4258 #endif 4259 } 4260 4261 #ifdef AHC_DUMP_SEQ 4262 static void 4263 ahc_dumpseq(struct ahc_softc* ahc) 4264 { 4265 int i; 4266 int max_prog; 4267 4268 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4269 max_prog = 448; 4270 else if ((ahc->features & AHC_ULTRA2) != 0) 4271 max_prog = 768; 4272 else 4273 max_prog = 512; 4274 4275 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4276 ahc_outb(ahc, SEQADDR0, 0); 4277 ahc_outb(ahc, SEQADDR1, 0); 4278 for (i = 0; i < max_prog; i++) { 4279 u_int8_t ins_bytes[4]; 4280 4281 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4282 printf("0x%08x\n", ins_bytes[0] << 24 4283 | ins_bytes[1] << 16 4284 | ins_bytes[2] << 8 4285 | ins_bytes[3]); 4286 } 4287 } 4288 #endif 4289 4290 static void 4291 ahc_loadseq(struct ahc_softc *ahc) 4292 { 4293 const struct patch *cur_patch; 4294 int i; 4295 int downloaded; 4296 int skip_addr; 4297 u_int8_t download_consts[4]; 4298 4299 /* Setup downloadable constant table */ 4300 #if 0 4301 /* No downloaded constants are currently defined. */ 4302 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4303 #endif 4304 4305 cur_patch = patches; 4306 downloaded = 0; 4307 skip_addr = 0; 4308 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4309 ahc_outb(ahc, SEQADDR0, 0); 4310 ahc_outb(ahc, SEQADDR1, 0); 4311 4312 for (i = 0; i < sizeof(seqprog)/4; i++) { 4313 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4314 /* 4315 * Don't download this instruction as it 4316 * is in a patch that was removed. 4317 */ 4318 continue; 4319 } 4320 ahc_download_instr(ahc, i, download_consts); 4321 downloaded++; 4322 } 4323 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4324 restart_sequencer(ahc); 4325 4326 #ifdef AHC_DEBUG 4327 printf(" %d instructions downloaded\n", downloaded); 4328 #endif 4329 } 4330 4331 static int 4332 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4333 int start_instr, int *skip_addr) 4334 { 4335 const struct patch *cur_patch; 4336 const struct patch *last_patch; 4337 int num_patches; 4338 4339 num_patches = sizeof(patches)/sizeof(struct patch); 4340 last_patch = &patches[num_patches]; 4341 cur_patch = *start_patch; 4342 4343 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4344 4345 if (cur_patch->patch_func(ahc) == 0) { 4346 4347 /* Start rejecting code */ 4348 *skip_addr = start_instr + cur_patch->skip_instr; 4349 cur_patch += cur_patch->skip_patch; 4350 } else { 4351 /* Accepted this patch. Advance to the next 4352 * one and wait for our intruction pointer to 4353 * hit this point. 4354 */ 4355 cur_patch++; 4356 } 4357 } 4358 4359 *start_patch = cur_patch; 4360 if (start_instr < *skip_addr) 4361 /* Still skipping */ 4362 return (0); 4363 4364 return (1); 4365 } 4366 4367 static void 4368 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4369 { 4370 union ins_formats instr; 4371 struct ins_format1 *fmt1_ins; 4372 struct ins_format3 *fmt3_ins; 4373 u_int opcode; 4374 4375 /* Structure copy */ 4376 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4377 4378 instr.integer = le32toh(instr.integer); 4379 4380 fmt1_ins = &instr.format1; 4381 fmt3_ins = NULL; 4382 4383 /* Pull the opcode */ 4384 opcode = instr.format1.opcode; 4385 switch (opcode) { 4386 case AIC_OP_JMP: 4387 case AIC_OP_JC: 4388 case AIC_OP_JNC: 4389 case AIC_OP_CALL: 4390 case AIC_OP_JNE: 4391 case AIC_OP_JNZ: 4392 case AIC_OP_JE: 4393 case AIC_OP_JZ: 4394 { 4395 const struct patch *cur_patch; 4396 int address_offset; 4397 u_int address; 4398 int skip_addr; 4399 int i; 4400 4401 fmt3_ins = &instr.format3; 4402 address_offset = 0; 4403 address = fmt3_ins->address; 4404 cur_patch = patches; 4405 skip_addr = 0; 4406 4407 for (i = 0; i < address;) { 4408 4409 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4410 4411 if (skip_addr > i) { 4412 int end_addr; 4413 4414 end_addr = MIN(address, skip_addr); 4415 address_offset += end_addr - i; 4416 i = skip_addr; 4417 } else { 4418 i++; 4419 } 4420 } 4421 address -= address_offset; 4422 fmt3_ins->address = address; 4423 /* FALLTHROUGH */ 4424 } 4425 case AIC_OP_OR: 4426 case AIC_OP_AND: 4427 case AIC_OP_XOR: 4428 case AIC_OP_ADD: 4429 case AIC_OP_ADC: 4430 case AIC_OP_BMOV: 4431 if (fmt1_ins->parity != 0) { 4432 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4433 } 4434 fmt1_ins->parity = 0; 4435 /* FALLTHROUGH */ 4436 case AIC_OP_ROL: 4437 if ((ahc->features & AHC_ULTRA2) != 0) { 4438 int i, count; 4439 4440 /* Calculate odd parity for the instruction */ 4441 for (i = 0, count = 0; i < 31; i++) { 4442 u_int32_t mask; 4443 4444 mask = 0x01 << i; 4445 if ((instr.integer & mask) != 0) 4446 count++; 4447 } 4448 if ((count & 0x01) == 0) 4449 instr.format1.parity = 1; 4450 } else { 4451 /* Compress the instruction for older sequencers */ 4452 if (fmt3_ins != NULL) { 4453 instr.integer = 4454 fmt3_ins->immediate 4455 | (fmt3_ins->source << 8) 4456 | (fmt3_ins->address << 16) 4457 | (fmt3_ins->opcode << 25); 4458 } else { 4459 instr.integer = 4460 fmt1_ins->immediate 4461 | (fmt1_ins->source << 8) 4462 | (fmt1_ins->destination << 16) 4463 | (fmt1_ins->ret << 24) 4464 | (fmt1_ins->opcode << 25); 4465 } 4466 } 4467 instr.integer = htole32(instr.integer); 4468 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4469 break; 4470 default: 4471 panic("Unknown opcode encountered in seq program"); 4472 break; 4473 } 4474 } 4475 4476 static void 4477 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4478 { 4479 4480 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4481 struct scb *scbp; 4482 4483 scb->flags |= SCB_RECOVERY_SCB; 4484 4485 /* 4486 * Take all queued, but not sent SCBs out of the equation. 4487 * Also ensure that no new CCBs are queued to us while we 4488 * try to fix this problem. 4489 */ 4490 scsipi_channel_freeze(&ahc->sc_channel, 1); 4491 if (ahc->features & AHC_TWIN) 4492 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4493 4494 /* 4495 * Go through all of our pending SCBs and remove 4496 * any scheduled timeouts for them. We will reschedule 4497 * them after we've successfully fixed this problem. 4498 */ 4499 scbp = ahc->pending_ccbs.lh_first; 4500 while (scbp != NULL) { 4501 callout_stop(&scbp->xs->xs_callout); 4502 scbp = scbp->plinks.le_next; 4503 } 4504 } 4505 } 4506 4507 static void 4508 ahc_timeout(void *arg) 4509 { 4510 struct scb *scb; 4511 struct ahc_softc *ahc; 4512 int s, found; 4513 u_int last_phase; 4514 int target; 4515 int lun; 4516 int i; 4517 char channel; 4518 4519 scb = (struct scb *)arg; 4520 ahc = 4521 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4522 4523 s = splbio(); 4524 4525 /* 4526 * Ensure that the card doesn't do anything 4527 * behind our back. Also make sure that we 4528 * didn't "just" miss an interrupt that would 4529 * affect this timeout. 4530 */ 4531 do { 4532 ahc_intr(ahc); 4533 pause_sequencer(ahc); 4534 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4535 4536 if ((scb->flags & SCB_ACTIVE) == 0) { 4537 /* Previous timeout took care of me already */ 4538 printf("Timedout SCB handled by another timeout\n"); 4539 unpause_sequencer(ahc); 4540 splx(s); 4541 return; 4542 } 4543 4544 target = SCB_TARGET(scb); 4545 channel = SCB_CHANNEL(scb); 4546 lun = SCB_LUN(scb); 4547 4548 scsipi_printaddr(scb->xs->xs_periph); 4549 printf("SCB %x - timed out ", scb->hscb->tag); 4550 /* 4551 * Take a snapshot of the bus state and print out 4552 * some information so we can track down driver bugs. 4553 */ 4554 last_phase = ahc_inb(ahc, LASTPHASE); 4555 4556 for (i = 0; i < num_phases; i++) { 4557 if (last_phase == phase_table[i].phase) 4558 break; 4559 } 4560 printf("%s", phase_table[i].phasemsg); 4561 4562 printf(", SEQADDR == 0x%x\n", 4563 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4564 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4565 4566 #ifdef AHC_DEBUG 4567 ahc_print_scb(scb); 4568 #endif 4569 4570 #if 0 4571 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4572 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4573 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4574 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4575 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4576 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4577 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4578 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4579 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4580 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4581 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4582 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4583 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4584 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4585 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4586 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4587 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4588 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4589 if (scb->sg_count > 0) { 4590 for (i = 0; i < scb->sg_count; i++) { 4591 printf("sg[%d] - Addr 0x%x : Length %d\n", 4592 i, 4593 le32toh(scb->sg_list[i].addr), 4594 le32toh(scb->sg_list[i].len)); 4595 } 4596 } 4597 #endif 4598 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4599 /* 4600 * Been down this road before. 4601 * Do a full bus reset. 4602 */ 4603 bus_reset: 4604 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4605 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4606 printf("%s: Issued Channel %c Bus Reset. " 4607 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4608 } else { 4609 /* 4610 * If we are a target, transition to bus free and report 4611 * the timeout. 4612 * 4613 * The target/initiator that is holding up the bus may not 4614 * be the same as the one that triggered this timeout 4615 * (different commands have different timeout lengths). 4616 * If the bus is idle and we are actiing as the initiator 4617 * for this request, queue a BDR message to the timed out 4618 * target. Otherwise, if the timed out transaction is 4619 * active: 4620 * Initiator transaction: 4621 * Stuff the message buffer with a BDR message and assert 4622 * ATN in the hopes that the target will let go of the bus 4623 * and go to the mesgout phase. If this fails, we'll 4624 * get another timeout 2 seconds later which will attempt 4625 * a bus reset. 4626 * 4627 * Target transaction: 4628 * Transition to BUS FREE and report the error. 4629 * It's good to be the target! 4630 */ 4631 u_int active_scb_index; 4632 4633 active_scb_index = ahc_inb(ahc, SCB_TAG); 4634 4635 if (last_phase != P_BUSFREE 4636 && (active_scb_index < ahc->scb_data->numscbs)) { 4637 struct scb *active_scb; 4638 4639 /* 4640 * If the active SCB is not from our device, 4641 * assume that another device is hogging the bus 4642 * and wait for it's timeout to expire before 4643 * taking additional action. 4644 */ 4645 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4646 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4647 u_int newtimeout; 4648 4649 scsipi_printaddr(scb->xs->xs_periph); 4650 printf("Other SCB Timeout%s", 4651 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4652 ? " again\n" : "\n"); 4653 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4654 newtimeout = MAX(active_scb->xs->timeout, 4655 scb->xs->timeout); 4656 callout_reset(&scb->xs->xs_callout, 4657 (newtimeout * hz) / 1000, 4658 ahc_timeout, scb); 4659 splx(s); 4660 return; 4661 } 4662 4663 /* It's us */ 4664 if ((scb->hscb->control & TARGET_SCB) != 0) { 4665 4666 /* 4667 * Send back any queued up transactions 4668 * and properly record the error condition. 4669 */ 4670 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4671 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4672 ahc_freeze_ccb(scb); 4673 ahc_done(ahc, scb); 4674 4675 /* Will clear us from the bus */ 4676 restart_sequencer(ahc); 4677 splx(s); 4678 return; 4679 } 4680 4681 ahc_set_recoveryscb(ahc, active_scb); 4682 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4683 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4684 scsipi_printaddr(active_scb->xs->xs_periph); 4685 printf("BDR message in message buffer\n"); 4686 active_scb->flags |= SCB_DEVICE_RESET; 4687 callout_reset(&active_scb->xs->xs_callout, 4688 2 * hz, ahc_timeout, active_scb); 4689 unpause_sequencer(ahc); 4690 } else { 4691 int disconnected; 4692 4693 /* XXX Shouldn't panic. Just punt instead */ 4694 if ((scb->hscb->control & TARGET_SCB) != 0) 4695 panic("Timed-out target SCB but bus idle"); 4696 4697 if (last_phase != P_BUSFREE 4698 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4699 /* XXX What happened to the SCB? */ 4700 /* Hung target selection. Goto busfree */ 4701 printf("%s: Hung target selection\n", 4702 ahc_name(ahc)); 4703 restart_sequencer(ahc); 4704 splx(s); 4705 return; 4706 } 4707 4708 if (ahc_search_qinfifo(ahc, target, channel, lun, 4709 scb->hscb->tag, ROLE_INITIATOR, 4710 /*status*/0, SEARCH_COUNT) > 0) { 4711 disconnected = FALSE; 4712 } else { 4713 disconnected = TRUE; 4714 } 4715 4716 if (disconnected) { 4717 u_int active_scb; 4718 4719 ahc_set_recoveryscb(ahc, scb); 4720 /* 4721 * Simply set the MK_MESSAGE control bit. 4722 */ 4723 scb->hscb->control |= MK_MESSAGE; 4724 scb->flags |= SCB_QUEUED_MSG 4725 | SCB_DEVICE_RESET; 4726 4727 /* 4728 * Mark the cached copy of this SCB in the 4729 * disconnected list too, so that a reconnect 4730 * at this point causes a BDR or abort. 4731 */ 4732 active_scb = ahc_inb(ahc, SCBPTR); 4733 if (ahc_search_disc_list(ahc, target, 4734 channel, lun, 4735 scb->hscb->tag, 4736 /*stop_on_first*/TRUE, 4737 /*remove*/FALSE, 4738 /*save_state*/FALSE)) { 4739 u_int scb_control; 4740 4741 scb_control = ahc_inb(ahc, SCB_CONTROL); 4742 scb_control |= MK_MESSAGE; 4743 ahc_outb(ahc, SCB_CONTROL, scb_control); 4744 } 4745 ahc_outb(ahc, SCBPTR, active_scb); 4746 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4747 /*unbusy*/TRUE); 4748 4749 /* 4750 * Actually re-queue this SCB in case we can 4751 * select the device before it reconnects. 4752 * Clear out any entries in the QINFIFO first 4753 * so we are the next SCB for this target 4754 * to run. 4755 */ 4756 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4757 channel, SCB_LUN(scb), 4758 SCB_LIST_NULL, 4759 ROLE_INITIATOR, 4760 SCB_REQUEUE, 4761 SEARCH_COMPLETE); 4762 scsipi_printaddr(scb->xs->xs_periph); 4763 printf("Queuing a BDR SCB\n"); 4764 ahc->qinfifo[ahc->qinfifonext++] = 4765 scb->hscb->tag; 4766 4767 bus_dmamap_sync(ahc->parent_dmat, 4768 ahc->shared_data_dmamap, 4769 QINFIFO_OFFSET * 256, 256, 4770 BUS_DMASYNC_PREWRITE); 4771 4772 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4773 ahc_outb(ahc, HNSCB_QOFF, 4774 ahc->qinfifonext); 4775 } else { 4776 ahc_outb(ahc, KERNEL_QINPOS, 4777 ahc->qinfifonext); 4778 } 4779 callout_reset(&scb->xs->xs_callout, 2 * hz, 4780 ahc_timeout, scb); 4781 unpause_sequencer(ahc); 4782 } else { 4783 /* Go "immediatly" to the bus reset */ 4784 /* This shouldn't happen */ 4785 ahc_set_recoveryscb(ahc, scb); 4786 scsipi_printaddr(scb->xs->xs_periph); 4787 printf("SCB %x: Immediate reset. " 4788 "Flags = 0x%x\n", scb->hscb->tag, 4789 scb->flags); 4790 goto bus_reset; 4791 } 4792 } 4793 } 4794 splx(s); 4795 } 4796 4797 static int 4798 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4799 int lun, u_int tag, role_t role, scb_flag status, 4800 ahc_search_action action) 4801 { 4802 struct scb *scbp; 4803 u_int8_t qinpos; 4804 u_int8_t qintail; 4805 int found; 4806 4807 qinpos = ahc_inb(ahc, QINPOS); 4808 qintail = ahc->qinfifonext; 4809 found = 0; 4810 4811 /* 4812 * Start with an empty queue. Entries that are not chosen 4813 * for removal will be re-added to the queue as we go. 4814 */ 4815 ahc->qinfifonext = qinpos; 4816 4817 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4818 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4819 4820 while (qinpos != qintail) { 4821 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4822 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4823 /* 4824 * We found an scb that needs to be removed. 4825 */ 4826 switch (action) { 4827 case SEARCH_COMPLETE: 4828 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4829 scbp->flags |= status; 4830 scbp->xs->error = XS_NOERROR; 4831 } 4832 ahc_freeze_ccb(scbp); 4833 ahc_done(ahc, scbp); 4834 break; 4835 case SEARCH_COUNT: 4836 ahc->qinfifo[ahc->qinfifonext++] = 4837 scbp->hscb->tag; 4838 break; 4839 case SEARCH_REMOVE: 4840 break; 4841 } 4842 found++; 4843 } else { 4844 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4845 } 4846 qinpos++; 4847 } 4848 4849 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4850 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4851 4852 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4853 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4854 } else { 4855 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4856 } 4857 4858 return (found); 4859 } 4860 4861 /* 4862 * Abort all SCBs that match the given description (target/channel/lun/tag), 4863 * setting their status to the passed in status if the status has not already 4864 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4865 * is paused before it is called. 4866 */ 4867 static int 4868 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4869 int lun, u_int tag, role_t role, int status) 4870 { 4871 struct scb *scbp; 4872 u_int active_scb; 4873 int i; 4874 int found; 4875 4876 /* restore this when we're done */ 4877 active_scb = ahc_inb(ahc, SCBPTR); 4878 4879 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4880 role, SCB_REQUEUE, SEARCH_COMPLETE); 4881 4882 /* 4883 * Search waiting for selection list. 4884 */ 4885 { 4886 u_int8_t next, prev; 4887 4888 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4889 prev = SCB_LIST_NULL; 4890 4891 while (next != SCB_LIST_NULL) { 4892 u_int8_t scb_index; 4893 4894 ahc_outb(ahc, SCBPTR, next); 4895 scb_index = ahc_inb(ahc, SCB_TAG); 4896 if (scb_index >= ahc->scb_data->numscbs) { 4897 panic("Waiting List inconsistency. " 4898 "SCB index == %d, yet numscbs == %d.", 4899 scb_index, ahc->scb_data->numscbs); 4900 } 4901 scbp = &ahc->scb_data->scbarray[scb_index]; 4902 if (ahc_match_scb(scbp, target, channel, 4903 lun, SCB_LIST_NULL, role)) { 4904 4905 next = ahc_abort_wscb(ahc, next, prev); 4906 } else { 4907 4908 prev = next; 4909 next = ahc_inb(ahc, SCB_NEXT); 4910 } 4911 } 4912 } 4913 /* 4914 * Go through the disconnected list and remove any entries we 4915 * have queued for completion, 0'ing their control byte too. 4916 * We save the active SCB and restore it ourselves, so there 4917 * is no reason for this search to restore it too. 4918 */ 4919 ahc_search_disc_list(ahc, target, channel, lun, tag, 4920 /*stop_on_first*/FALSE, /*remove*/TRUE, 4921 /*save_state*/FALSE); 4922 4923 /* 4924 * Go through the hardware SCB array looking for commands that 4925 * were active but not on any list. 4926 */ 4927 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4928 u_int scbid; 4929 4930 ahc_outb(ahc, SCBPTR, i); 4931 scbid = ahc_inb(ahc, SCB_TAG); 4932 scbp = &ahc->scb_data->scbarray[scbid]; 4933 if (scbid < ahc->scb_data->numscbs 4934 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4935 ahc_add_curscb_to_free_list(ahc); 4936 } 4937 4938 /* 4939 * Go through the pending CCB list and look for 4940 * commands for this target that are still active. 4941 * These are other tagged commands that were 4942 * disconnected when the reset occured. 4943 */ 4944 { 4945 struct scb *scb; 4946 4947 scb = ahc->pending_ccbs.lh_first; 4948 while (scb != NULL) { 4949 scbp = scb; 4950 scb = scb->plinks.le_next; 4951 if (ahc_match_scb(scbp, target, channel, 4952 lun, tag, role)) { 4953 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4954 ahcsetccbstatus(scbp->xs, status); 4955 ahc_freeze_ccb(scbp); 4956 ahc_done(ahc, scbp); 4957 found++; 4958 } 4959 } 4960 } 4961 ahc_outb(ahc, SCBPTR, active_scb); 4962 return found; 4963 } 4964 4965 static int 4966 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 4967 int lun, u_int tag, int stop_on_first, int remove, 4968 int save_state) 4969 { 4970 struct scb *scbp; 4971 u_int next; 4972 u_int prev; 4973 u_int count; 4974 u_int active_scb; 4975 4976 count = 0; 4977 next = ahc_inb(ahc, DISCONNECTED_SCBH); 4978 prev = SCB_LIST_NULL; 4979 4980 if (save_state) { 4981 /* restore this when we're done */ 4982 active_scb = ahc_inb(ahc, SCBPTR); 4983 } else 4984 /* Silence compiler */ 4985 active_scb = SCB_LIST_NULL; 4986 4987 while (next != SCB_LIST_NULL) { 4988 u_int scb_index; 4989 4990 ahc_outb(ahc, SCBPTR, next); 4991 scb_index = ahc_inb(ahc, SCB_TAG); 4992 if (scb_index >= ahc->scb_data->numscbs) { 4993 panic("Disconnected List inconsistency. " 4994 "SCB index == %d, yet numscbs == %d.", 4995 scb_index, ahc->scb_data->numscbs); 4996 } 4997 scbp = &ahc->scb_data->scbarray[scb_index]; 4998 if (ahc_match_scb(scbp, target, channel, lun, 4999 tag, ROLE_INITIATOR)) { 5000 count++; 5001 if (remove) { 5002 next = 5003 ahc_rem_scb_from_disc_list(ahc, prev, next); 5004 } else { 5005 prev = next; 5006 next = ahc_inb(ahc, SCB_NEXT); 5007 } 5008 if (stop_on_first) 5009 break; 5010 } else { 5011 prev = next; 5012 next = ahc_inb(ahc, SCB_NEXT); 5013 } 5014 } 5015 if (save_state) 5016 ahc_outb(ahc, SCBPTR, active_scb); 5017 return (count); 5018 } 5019 5020 static u_int 5021 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5022 { 5023 u_int next; 5024 5025 ahc_outb(ahc, SCBPTR, scbptr); 5026 next = ahc_inb(ahc, SCB_NEXT); 5027 5028 ahc_outb(ahc, SCB_CONTROL, 0); 5029 5030 ahc_add_curscb_to_free_list(ahc); 5031 5032 if (prev != SCB_LIST_NULL) { 5033 ahc_outb(ahc, SCBPTR, prev); 5034 ahc_outb(ahc, SCB_NEXT, next); 5035 } else 5036 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5037 5038 return (next); 5039 } 5040 5041 static void 5042 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5043 { 5044 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5045 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5046 5047 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5048 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5049 } 5050 5051 /* 5052 * Manipulate the waiting for selection list and return the 5053 * scb that follows the one that we remove. 5054 */ 5055 static u_int 5056 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5057 { 5058 u_int curscb, next; 5059 5060 /* 5061 * Select the SCB we want to abort and 5062 * pull the next pointer out of it. 5063 */ 5064 curscb = ahc_inb(ahc, SCBPTR); 5065 ahc_outb(ahc, SCBPTR, scbpos); 5066 next = ahc_inb(ahc, SCB_NEXT); 5067 5068 /* Clear the necessary fields */ 5069 ahc_outb(ahc, SCB_CONTROL, 0); 5070 5071 ahc_add_curscb_to_free_list(ahc); 5072 5073 /* update the waiting list */ 5074 if (prev == SCB_LIST_NULL) { 5075 /* First in the list */ 5076 ahc_outb(ahc, WAITING_SCBH, next); 5077 5078 /* 5079 * Ensure we aren't attempting to perform 5080 * selection for this entry. 5081 */ 5082 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5083 } else { 5084 /* 5085 * Select the scb that pointed to us 5086 * and update its next pointer. 5087 */ 5088 ahc_outb(ahc, SCBPTR, prev); 5089 ahc_outb(ahc, SCB_NEXT, next); 5090 } 5091 5092 /* 5093 * Point us back at the original scb position. 5094 */ 5095 ahc_outb(ahc, SCBPTR, curscb); 5096 return next; 5097 } 5098 5099 static void 5100 ahc_clear_intstat(struct ahc_softc *ahc) 5101 { 5102 /* Clear any interrupt conditions this may have caused */ 5103 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5104 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5105 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5106 CLRREQINIT); 5107 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5108 } 5109 5110 static void 5111 ahc_reset_current_bus(struct ahc_softc *ahc) 5112 { 5113 u_int8_t scsiseq; 5114 5115 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5116 scsiseq = ahc_inb(ahc, SCSISEQ); 5117 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5118 DELAY(AHC_BUSRESET_DELAY); 5119 /* Turn off the bus reset */ 5120 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5121 5122 ahc_clear_intstat(ahc); 5123 5124 /* Re-enable reset interrupts */ 5125 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5126 } 5127 5128 static int 5129 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5130 { 5131 u_int initiator, target, max_scsiid; 5132 u_int sblkctl; 5133 u_int our_id; 5134 int found; 5135 int restart_needed; 5136 char cur_channel; 5137 5138 ahc->pending_device = NULL; 5139 5140 pause_sequencer(ahc); 5141 5142 /* 5143 * Run our command complete fifos to ensure that we perform 5144 * completion processing on any commands that 'completed' 5145 * before the reset occurred. 5146 */ 5147 ahc_run_qoutfifo(ahc); 5148 5149 /* 5150 * Reset the bus if we are initiating this reset 5151 */ 5152 sblkctl = ahc_inb(ahc, SBLKCTL); 5153 cur_channel = 'A'; 5154 if ((ahc->features & AHC_TWIN) != 0 5155 && ((sblkctl & SELBUSB) != 0)) 5156 cur_channel = 'B'; 5157 if (cur_channel != channel) { 5158 /* Case 1: Command for another bus is active 5159 * Stealthily reset the other bus without 5160 * upsetting the current bus. 5161 */ 5162 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5163 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5164 ahc_outb(ahc, SCSISEQ, 5165 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5166 if (initiate_reset) 5167 ahc_reset_current_bus(ahc); 5168 ahc_clear_intstat(ahc); 5169 ahc_outb(ahc, SBLKCTL, sblkctl); 5170 restart_needed = FALSE; 5171 } else { 5172 /* Case 2: A command from this bus is active or we're idle */ 5173 ahc_clear_msg_state(ahc); 5174 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5175 ahc_outb(ahc, SCSISEQ, 5176 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5177 if (initiate_reset) 5178 ahc_reset_current_bus(ahc); 5179 ahc_clear_intstat(ahc); 5180 5181 /* 5182 * Since we are going to restart the sequencer, avoid 5183 * a race in the sequencer that could cause corruption 5184 * of our Q pointers by starting over from index 0. 5185 */ 5186 ahc->qoutfifonext = 0; 5187 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5188 ahc_outb(ahc, SDSCB_QOFF, 0); 5189 else 5190 ahc_outb(ahc, QOUTPOS, 0); 5191 restart_needed = TRUE; 5192 } 5193 5194 /* 5195 * Clean up all the state information for the 5196 * pending transactions on this bus. 5197 */ 5198 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5199 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5200 ROLE_UNKNOWN, XS_RESET); 5201 if (channel == 'B') { 5202 our_id = ahc->our_id_b; 5203 } else { 5204 our_id = ahc->our_id; 5205 } 5206 5207 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5208 5209 /* 5210 * Revert to async/narrow transfers until we renegotiate. 5211 */ 5212 for (target = 0; target <= max_scsiid; target++) { 5213 5214 if (ahc->enabled_targets[target] == NULL) 5215 continue; 5216 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5217 struct ahc_devinfo devinfo; 5218 5219 ahc_compile_devinfo(&devinfo, target, initiator, 5220 AHC_LUN_WILDCARD, 5221 channel, ROLE_UNKNOWN); 5222 ahc_set_width(ahc, &devinfo, 5223 MSG_EXT_WDTR_BUS_8_BIT, 5224 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5225 ahc_set_syncrate(ahc, &devinfo, 5226 /*syncrate*/NULL, /*period*/0, 5227 /*offset*/0, AHC_TRANS_CUR, 5228 /*paused*/TRUE, FALSE); 5229 } 5230 } 5231 5232 if (restart_needed) 5233 restart_sequencer(ahc); 5234 else 5235 unpause_sequencer(ahc); 5236 return found; 5237 } 5238 5239 static int 5240 ahc_match_scb(struct scb *scb, int target, char channel, 5241 int lun, u_int tag, role_t role) 5242 { 5243 int targ = SCB_TARGET(scb); 5244 char chan = SCB_CHANNEL(scb); 5245 int slun = SCB_LUN(scb); 5246 int match; 5247 5248 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5249 if (match != 0) 5250 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5251 if (match != 0) 5252 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5253 5254 return match; 5255 } 5256 5257 static void 5258 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5259 { 5260 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5261 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5262 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5263 ahc->msgout_buf[ahc->msgout_index++] = period; 5264 ahc->msgout_buf[ahc->msgout_index++] = offset; 5265 ahc->msgout_len += 5; 5266 } 5267 5268 static void 5269 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5270 { 5271 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5272 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5273 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5274 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5275 ahc->msgout_len += 4; 5276 } 5277 5278 static void 5279 ahc_calc_residual(struct scb *scb) 5280 { 5281 struct hardware_scb *hscb; 5282 5283 hscb = scb->hscb; 5284 5285 /* 5286 * If the disconnected flag is still set, this is bogus 5287 * residual information left over from a sequencer 5288 * pagin/pageout, so ignore this case. 5289 */ 5290 if ((scb->hscb->control & DISCONNECTED) == 0) { 5291 u_int32_t resid; 5292 int resid_sgs; 5293 int sg; 5294 5295 /* 5296 * Remainder of the SG where the transfer 5297 * stopped. 5298 */ 5299 resid = (hscb->residual_data_count[2] << 16) 5300 | (hscb->residual_data_count[1] <<8) 5301 | (hscb->residual_data_count[0]); 5302 5303 /* 5304 * Add up the contents of all residual 5305 * SG segments that are after the SG where 5306 * the transfer stopped. 5307 */ 5308 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5309 sg = scb->sg_count - resid_sgs; 5310 while (resid_sgs > 0) { 5311 5312 resid += le32toh(scb->sg_list[sg].len); 5313 sg++; 5314 resid_sgs--; 5315 } 5316 scb->xs->resid = resid; 5317 } 5318 5319 /* 5320 * Clean out the residual information in this SCB for its 5321 * next consumer. 5322 */ 5323 hscb->residual_SG_count = 0; 5324 5325 #ifdef AHC_DEBUG 5326 if (ahc_debug & AHC_SHOWMISC) { 5327 scsipi_printaddr(scb->xs->xs_periph); 5328 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5329 } 5330 #endif 5331 } 5332 5333 static void 5334 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5335 { 5336 struct scb *scb; 5337 int pending_ccb_count; 5338 int i; 5339 u_int saved_scbptr; 5340 5341 /* 5342 * Traverse the pending SCB list and ensure that all of the 5343 * SCBs there have the proper settings. 5344 */ 5345 scb = LIST_FIRST(&ahc->pending_ccbs); 5346 pending_ccb_count = 0; 5347 while (scb != NULL) { 5348 struct ahc_devinfo devinfo; 5349 struct scsipi_xfer *xs; 5350 struct scb *pending_scb; 5351 struct hardware_scb *pending_hscb; 5352 struct ahc_initiator_tinfo *tinfo; 5353 struct tmode_tstate *tstate; 5354 u_int our_id, remote_id; 5355 5356 xs = scb->xs; 5357 pending_scb = scb; 5358 pending_hscb = pending_scb->hscb; 5359 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5360 ? ahc->our_id_b : ahc->our_id; 5361 remote_id = xs->xs_periph->periph_target; 5362 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5363 SCB_LUN(pending_scb), 5364 SCB_CHANNEL(pending_scb), 5365 ROLE_UNKNOWN); 5366 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5367 our_id, remote_id, &tstate); 5368 pending_hscb->control &= ~ULTRAENB; 5369 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5370 pending_hscb->control |= ULTRAENB; 5371 pending_hscb->scsirate = tinfo->scsirate; 5372 pending_hscb->scsioffset = tinfo->current.offset; 5373 pending_ccb_count++; 5374 scb = LIST_NEXT(scb, plinks); 5375 } 5376 5377 if (pending_ccb_count == 0) 5378 return; 5379 5380 saved_scbptr = ahc_inb(ahc, SCBPTR); 5381 /* Ensure that the hscbs down on the card match the new information */ 5382 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5383 u_int scb_tag; 5384 5385 ahc_outb(ahc, SCBPTR, i); 5386 scb_tag = ahc_inb(ahc, SCB_TAG); 5387 if (scb_tag != SCB_LIST_NULL) { 5388 struct ahc_devinfo devinfo; 5389 struct scb *pending_scb; 5390 struct scsipi_xfer *xs; 5391 struct hardware_scb *pending_hscb; 5392 struct ahc_initiator_tinfo *tinfo; 5393 struct tmode_tstate *tstate; 5394 u_int our_id, remote_id; 5395 u_int control; 5396 5397 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5398 if (pending_scb->flags == SCB_FREE) 5399 continue; 5400 pending_hscb = pending_scb->hscb; 5401 xs = pending_scb->xs; 5402 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5403 ? ahc->our_id_b : ahc->our_id; 5404 remote_id = xs->xs_periph->periph_target; 5405 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5406 SCB_LUN(pending_scb), 5407 SCB_CHANNEL(pending_scb), 5408 ROLE_UNKNOWN); 5409 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5410 our_id, remote_id, &tstate); 5411 control = ahc_inb(ahc, SCB_CONTROL); 5412 control &= ~ULTRAENB; 5413 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5414 control |= ULTRAENB; 5415 ahc_outb(ahc, SCB_CONTROL, control); 5416 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5417 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5418 } 5419 } 5420 ahc_outb(ahc, SCBPTR, saved_scbptr); 5421 } 5422 5423 #if UNUSED 5424 static void 5425 ahc_dump_targcmd(struct target_cmd *cmd) 5426 { 5427 u_int8_t *byte; 5428 u_int8_t *last_byte; 5429 int i; 5430 5431 byte = &cmd->initiator_channel; 5432 /* Debugging info for received commands */ 5433 last_byte = &cmd[1].initiator_channel; 5434 5435 i = 0; 5436 while (byte < last_byte) { 5437 if (i == 0) 5438 printf("\t"); 5439 printf("%#x", *byte++); 5440 i++; 5441 if (i == 8) { 5442 printf("\n"); 5443 i = 0; 5444 } else { 5445 printf(", "); 5446 } 5447 } 5448 } 5449 #endif 5450 5451 static void 5452 ahc_shutdown(void *arg) 5453 { 5454 struct ahc_softc *ahc; 5455 int i; 5456 u_int sxfrctl1_a, sxfrctl1_b; 5457 5458 ahc = (struct ahc_softc *)arg; 5459 5460 pause_sequencer(ahc); 5461 5462 /* 5463 * Preserve the value of the SXFRCTL1 register for all channels. 5464 * It contains settings that affect termination and we don't want 5465 * to disturb the integrity of the bus during shutdown in case 5466 * we are in a multi-initiator setup. 5467 */ 5468 sxfrctl1_b = 0; 5469 if ((ahc->features & AHC_TWIN) != 0) { 5470 u_int sblkctl; 5471 5472 sblkctl = ahc_inb(ahc, SBLKCTL); 5473 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5474 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5475 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5476 } 5477 5478 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5479 5480 /* This will reset most registers to 0, but not all */ 5481 ahc_reset(ahc); 5482 5483 if ((ahc->features & AHC_TWIN) != 0) { 5484 u_int sblkctl; 5485 5486 sblkctl = ahc_inb(ahc, SBLKCTL); 5487 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5488 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5489 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5490 } 5491 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5492 5493 ahc_outb(ahc, SCSISEQ, 0); 5494 ahc_outb(ahc, SXFRCTL0, 0); 5495 ahc_outb(ahc, DSPCISTATUS, 0); 5496 5497 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5498 ahc_outb(ahc, i, 0); 5499 } 5500 5501 #if defined(AHC_DEBUG) && 0 5502 static void 5503 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5504 { 5505 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5506 5507 printf("\tcurrent:\n"); 5508 printf("\t\twidth %u period %u offset %u flags %x\n", 5509 tinfo->current.width, tinfo->current.period, 5510 tinfo->current.offset, tinfo->current.ppr_flags); 5511 5512 printf("\tgoal:\n"); 5513 printf("\t\twidth %u period %u offset %u flags %x\n", 5514 tinfo->goal.width, tinfo->goal.period, 5515 tinfo->goal.offset, tinfo->goal.ppr_flags); 5516 5517 printf("\tuser:\n"); 5518 printf("\t\twidth %u period %u offset %u flags %x\n", 5519 tinfo->user.width, tinfo->user.period, 5520 tinfo->user.offset, tinfo->user.ppr_flags); 5521 } 5522 #endif 5523 5524 static int 5525 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5526 int nocmdcheck) 5527 { 5528 #ifdef AHC_NO_TAGS 5529 return 0; 5530 #else 5531 char channel; 5532 u_int our_id, target; 5533 struct tmode_tstate *tstate; 5534 struct ahc_devinfo devinfo; 5535 5536 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5537 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5538 target = xs->xs_periph->periph_target; 5539 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5540 5541 ahc_compile_devinfo(&devinfo, our_id, target, 5542 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5543 5544 return (tstate->tagenable & devinfo.target_mask); 5545 #endif 5546 } 5547
Indexes created Wed Oct 01 07:09:59 GMT 2025