aic7xxx.c revision 1.71
1 /* $NetBSD: aic7xxx.c,v 1.71 2001/04/26 16:56:53 bouyer Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 #include "opt_ahc.h" 91 92 #include <sys/param.h> 93 #include <sys/kernel.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/malloc.h> 97 #include <sys/buf.h> 98 #include <sys/proc.h> 99 #include <sys/scsiio.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <uvm/uvm_extern.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define ALL_CHANNELS '\0' 118 #define ALL_TARGETS_MASK 0xFFFF 119 #define INITIATOR_WILDCARD (~0) 120 121 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 122 ((periph)->periph_channel->chan_channel == 1) 123 #define SIM_CHANNEL(ahc, periph) \ 124 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 125 #define SIM_SCSI_ID(ahc, periph) \ 126 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 127 #define SCB_IS_SCSIBUS_B(scb) \ 128 (((scb)->hscb->tcl & SELBUSB) != 0) 129 #define SCB_TARGET(scb) \ 130 (((scb)->hscb->tcl & TID) >> 4) 131 #define SCB_CHANNEL(scb) \ 132 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 133 #define SCB_LUN(scb) \ 134 ((scb)->hscb->tcl & LID) 135 #define SCB_TARGET_OFFSET(scb) \ 136 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 137 #define SCB_TARGET_MASK(scb) \ 138 (0x01 << (SCB_TARGET_OFFSET(scb))) 139 #define TCL_CHANNEL(ahc, tcl) \ 140 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 141 #define TCL_SCSI_ID(ahc, tcl) \ 142 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 143 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 144 #define TCL_LUN(tcl) ((tcl) & LID) 145 146 #define XS_TCL(ahc, xs) \ 147 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 148 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 149 | ((xs)->xs_periph->periph_lun & 0x07)) 150 151 const char * const ahc_chip_names[] = 152 { 153 "NONE", 154 "aic7770", 155 "aic7850", 156 "aic7855", 157 "aic7859", 158 "aic7860", 159 "aic7870", 160 "aic7880", 161 "aic7890/91", 162 "aic7892", 163 "aic7895", 164 "aic7896/97", 165 "aic7899" 166 }; 167 168 typedef enum { 169 ROLE_UNKNOWN, 170 ROLE_INITIATOR, 171 ROLE_TARGET 172 } role_t; 173 174 struct ahc_devinfo { 175 int our_scsiid; 176 int target_offset; 177 u_int16_t target_mask; 178 u_int8_t target; 179 u_int8_t lun; 180 char channel; 181 role_t role; /* 182 * Only guaranteed to be correct if not 183 * in the busfree state. 184 */ 185 }; 186 187 typedef enum { 188 SEARCH_COMPLETE, 189 SEARCH_COUNT, 190 SEARCH_REMOVE 191 } ahc_search_action; 192 193 #ifdef AHC_DEBUG 194 static int ahc_debug = AHC_DEBUG; 195 #endif 196 197 static int ahcinitscbdata(struct ahc_softc *); 198 static void ahcfiniscbdata(struct ahc_softc *); 199 200 #if UNUSED 201 static void ahc_dump_targcmd(struct target_cmd *); 202 #endif 203 static void ahc_shutdown(void *arg); 204 static void ahc_action(struct scsipi_channel *, 205 scsipi_adapter_req_t, void *); 206 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 207 struct proc *); 208 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 209 static int ahc_poll(struct ahc_softc *, int); 210 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 211 struct scb *); 212 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 213 static void ahcallocscbs(struct ahc_softc *); 214 #if UNUSED 215 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 216 struct scb *); 217 #endif 218 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 219 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 220 char, role_t); 221 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 222 static void ahc_done(struct ahc_softc *, struct scb *); 223 static struct tmode_tstate * 224 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 225 #if UNUSED 226 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 227 #endif 228 static void ahc_handle_seqint(struct ahc_softc *, u_int); 229 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 230 static void ahc_build_transfer_msg(struct ahc_softc *, 231 struct ahc_devinfo *); 232 static void ahc_setup_initiator_msgout(struct ahc_softc *, 233 struct ahc_devinfo *, 234 struct scb *); 235 static void ahc_setup_target_msgin(struct ahc_softc *, 236 struct ahc_devinfo *); 237 static void ahc_clear_msg_state(struct ahc_softc *); 238 static void ahc_handle_message_phase(struct ahc_softc *, 239 struct scsipi_periph *); 240 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 241 242 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 243 struct ahc_devinfo *); 244 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 245 struct ahc_devinfo *); 246 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 247 int, char *, int); 248 #ifdef AHC_DUMP_SEQ 249 static void ahc_dumpseq(struct ahc_softc *); 250 #endif 251 static void ahc_loadseq(struct ahc_softc *); 252 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 253 int, int *); 254 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 255 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 256 #if defined(AHC_DEBUG) 257 static void ahc_print_scb(struct scb *); 258 #endif 259 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 260 role_t, scb_flag, ahc_search_action); 261 static int ahc_reset_channel(struct ahc_softc *, char, int); 262 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 263 role_t, int); 264 static int ahc_search_disc_list(struct ahc_softc *, int, 265 char, int, u_int, int, int, int); 266 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 267 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 268 static void ahc_clear_intstat(struct ahc_softc *); 269 static void ahc_reset_current_bus(struct ahc_softc *); 270 static const struct ahc_syncrate * 271 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 272 static const struct ahc_syncrate * 273 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 274 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 275 static void ahc_validate_offset(struct ahc_softc *, 276 const struct ahc_syncrate *, u_int *, int); 277 static void ahc_update_target_msg_request(struct ahc_softc *, 278 struct ahc_devinfo *, 279 struct ahc_initiator_tinfo *, 280 int, int); 281 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 282 const struct ahc_syncrate *, u_int, u_int, 283 u_int, int, int); 284 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 285 u_int, u_int, int, int); 286 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 287 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 288 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 289 290 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 291 292 static void ahc_calc_residual(struct scb *); 293 294 static void ahc_update_pending_syncrates(struct ahc_softc *); 295 296 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 297 298 static void ahc_timeout (void *); 299 static __inline int sequencer_paused(struct ahc_softc *); 300 static __inline void pause_sequencer(struct ahc_softc *); 301 static __inline void unpause_sequencer(struct ahc_softc *); 302 static void restart_sequencer(struct ahc_softc *); 303 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 304 305 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 306 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 307 308 static __inline void ahc_freeze_ccb(struct scb *); 309 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 310 static void ahc_run_qoutfifo(struct ahc_softc *); 311 312 static __inline struct ahc_initiator_tinfo * 313 ahc_fetch_transinfo(struct ahc_softc *, 314 char, u_int, u_int, 315 struct tmode_tstate **); 316 static void ahcfreescb(struct ahc_softc *, struct scb *); 317 static __inline struct scb *ahcgetscb(struct ahc_softc *); 318 319 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 320 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 321 int *, const char *, const char *); 322 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 323 caddr_t, bus_dma_segment_t *, int); 324 static void ahcminphys(struct buf *); 325 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 329 330 #if defined(AHC_DEBUG) && 0 331 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 332 #endif 333 334 static __inline void 335 ahc_swap_hscb(struct hardware_scb *hscb) 336 { 337 hscb->SG_pointer = htole32(hscb->SG_pointer); 338 hscb->data = htole32(hscb->data); 339 hscb->datalen = htole32(hscb->datalen); 340 /* 341 * No need to swap cmdpointer; it's either 0 or set to 342 * cmdstore_busaddr, which is already swapped. 343 */ 344 } 345 346 static __inline void 347 ahc_swap_sg(struct ahc_dma_seg *sg) 348 { 349 sg->addr = htole32(sg->addr); 350 sg->len = htole32(sg->len); 351 } 352 353 static void 354 ahcminphys(bp) 355 struct buf *bp; 356 { 357 /* 358 * Even though the card can transfer up to 16megs per command 359 * we are limited by the number of segments in the dma segment 360 * list that we can hold. The worst case is that all pages are 361 * discontinuous physically, hense the "page per segment" limit 362 * enforced here. 363 */ 364 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 365 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 366 } 367 minphys(bp); 368 } 369 370 371 static __inline u_int32_t 372 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 373 { 374 return (ahc->scb_data->hscb_busaddr 375 + (sizeof(struct hardware_scb) * index)); 376 } 377 378 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 379 380 static __inline int 381 sequencer_paused(struct ahc_softc *ahc) 382 { 383 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 384 } 385 386 static __inline void 387 pause_sequencer(struct ahc_softc *ahc) 388 { 389 ahc_outb(ahc, HCNTRL, ahc->pause); 390 391 /* 392 * Since the sequencer can disable pausing in a critical section, we 393 * must loop until it actually stops. 394 */ 395 while (sequencer_paused(ahc) == 0) 396 ; 397 } 398 399 static __inline void 400 unpause_sequencer(struct ahc_softc *ahc) 401 { 402 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 403 ahc_outb(ahc, HCNTRL, ahc->unpause); 404 } 405 406 /* 407 * Restart the sequencer program from address zero 408 */ 409 static void 410 restart_sequencer(struct ahc_softc *ahc) 411 { 412 u_int i; 413 414 pause_sequencer(ahc); 415 416 /* 417 * Everytime we restart the sequencer, there 418 * is the possiblitity that we have restarted 419 * within a three instruction window where an 420 * SCB has been marked free but has not made it 421 * onto the free list. Since SCSI events(bus reset, 422 * unexpected bus free) will always freeze the 423 * sequencer, we cannot close this window. To 424 * avoid losing an SCB, we reconsitute the free 425 * list every time we restart the sequencer. 426 */ 427 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 428 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 429 430 ahc_outb(ahc, SCBPTR, i); 431 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 432 ahc_add_curscb_to_free_list(ahc); 433 } 434 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 435 unpause_sequencer(ahc); 436 } 437 438 static __inline u_int 439 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 440 { 441 u_int scbid; 442 443 scbid = ahc->untagged_scbs[tcl]; 444 if (unbusy) { 445 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 446 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 447 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 448 } 449 450 return (scbid); 451 } 452 453 static __inline void 454 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 455 { 456 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 457 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 458 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 459 } 460 461 static __inline int 462 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 463 { 464 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 465 } 466 467 static __inline void 468 ahc_freeze_ccb(struct scb *scb) 469 { 470 struct scsipi_xfer *xs = scb->xs; 471 472 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 473 scsipi_periph_freeze(xs->xs_periph, 1); 474 scb->flags |= SCB_FREEZE_QUEUE; 475 } 476 } 477 478 static __inline void 479 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 480 { 481 xs->error = status; 482 } 483 484 static __inline struct ahc_initiator_tinfo * 485 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 486 u_int remote_id, struct tmode_tstate **tstate) 487 { 488 /* 489 * Transfer data structures are stored from the perspective 490 * of the target role. Since the parameters for a connection 491 * in the initiator role to a given target are the same as 492 * when the roles are reversed, we pretend we are the target. 493 */ 494 if (channel == 'B') 495 our_id += 8; 496 *tstate = ahc->enabled_targets[our_id]; 497 return (&(*tstate)->transinfo[remote_id]); 498 } 499 500 static void 501 ahc_run_qoutfifo(struct ahc_softc *ahc) 502 { 503 struct scb *scb; 504 u_int scb_index; 505 506 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 507 256, BUS_DMASYNC_POSTREAD); 508 509 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 510 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 511 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 512 513 scb = &ahc->scb_data->scbarray[scb_index]; 514 if (scb_index >= ahc->scb_data->numscbs 515 || (scb->flags & SCB_ACTIVE) == 0) { 516 printf("%s: WARNING no command for scb %d " 517 "(cmdcmplt)\nQOUTPOS = %d\n", 518 ahc_name(ahc), scb_index, 519 ahc->qoutfifonext - 1); 520 continue; 521 } 522 523 /* 524 * Save off the residual 525 * if there is one. 526 */ 527 if (scb->hscb->residual_SG_count != 0) 528 ahc_calc_residual(scb); 529 else 530 scb->xs->resid = 0; 531 #ifdef AHC_DEBUG 532 if (ahc_debug & AHC_SHOWSCBS) { 533 scsipi_printaddr(scb->xs->xs_periph); 534 printf("run_qoutfifo: SCB %x complete\n", 535 scb->hscb->tag); 536 } 537 #endif 538 ahc_done(ahc, scb); 539 } 540 } 541 542 543 /* 544 * An scb (and hence an scb entry on the board) is put onto the 545 * free list. 546 */ 547 static void 548 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 549 { 550 struct hardware_scb *hscb; 551 int opri; 552 553 hscb = scb->hscb; 554 555 #ifdef AHC_DEBUG 556 if (ahc_debug & AHC_SHOWSCBALLOC) 557 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 558 #endif 559 560 opri = splbio(); 561 562 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 563 (scb->flags & SCB_RECOVERY_SCB) != 0) { 564 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 565 scsipi_channel_thaw(&ahc->sc_channel, 1); 566 if (ahc->features & AHC_TWIN) 567 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 568 } 569 570 /* Clean up for the next user */ 571 scb->flags = SCB_FREE; 572 hscb->control = 0; 573 hscb->status = 0; 574 575 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 576 577 splx(opri); 578 } 579 580 /* 581 * Get a free scb, either one already assigned to a hardware slot 582 * on the adapter or one that will require an SCB to be paged out before 583 * use. If there are none, see if we can allocate a new SCB. Otherwise 584 * either return an error or sleep. 585 */ 586 static __inline struct scb * 587 ahcgetscb(struct ahc_softc *ahc) 588 { 589 struct scb *scbp; 590 int opri;; 591 592 opri = splbio(); 593 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 594 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 595 } else { 596 ahcallocscbs(ahc); 597 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 598 if (scbp != NULL) 599 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 600 } 601 602 splx(opri); 603 604 #ifdef AHC_DEBUG 605 if (ahc_debug & AHC_SHOWSCBALLOC) { 606 if (scbp != NULL) 607 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 608 scbp->hscb->tag); 609 else 610 printf("%s: failed to allocate new SCB\n", 611 ahc_name(ahc)); 612 } 613 #endif 614 615 return (scbp); 616 } 617 618 static int 619 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 620 bus_dma_tag_t tag; 621 int size; 622 int flags; 623 bus_dmamap_t *mapp; 624 caddr_t *vaddr; 625 bus_addr_t *baddr; 626 bus_dma_segment_t *seg; 627 int *nseg; 628 const char *myname, *what; 629 { 630 int error, level = 0; 631 632 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 633 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 634 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 635 myname, what, error); 636 goto out; 637 } 638 level++; 639 640 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 641 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 642 printf("%s: failed to map DMA mem for %s, error = %d\n", 643 myname, what, error); 644 goto out; 645 } 646 level++; 647 648 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 649 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 650 printf("%s: failed to create DMA map for %s, error = %d\n", 651 myname, what, error); 652 goto out; 653 } 654 level++; 655 656 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 657 BUS_DMA_NOWAIT)) != 0) { 658 printf("%s: failed to load DMA map for %s, error = %d\n", 659 myname, what, error); 660 goto out; 661 } 662 663 *baddr = (*mapp)->dm_segs[0].ds_addr; 664 665 #ifdef AHC_DEBUG 666 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 667 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 668 *nseg, size); 669 #endif 670 671 return 0; 672 out: 673 switch (level) { 674 case 3: 675 bus_dmamap_destroy(tag, *mapp); 676 /* FALLTHROUGH */ 677 case 2: 678 bus_dmamem_unmap(tag, *vaddr, size); 679 /* FALLTHROUGH */ 680 case 1: 681 bus_dmamem_free(tag, seg, *nseg); 682 break; 683 default: 684 break; 685 } 686 687 return error; 688 } 689 690 static void 691 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 692 bus_dma_tag_t tag; 693 int size; 694 bus_dmamap_t map; 695 caddr_t vaddr; 696 bus_dma_segment_t *seg; 697 int nseg; 698 { 699 700 bus_dmamap_unload(tag, map); 701 bus_dmamap_destroy(tag, map); 702 bus_dmamem_unmap(tag, vaddr, size); 703 bus_dmamem_free(tag, seg, nseg); 704 } 705 706 char * 707 ahc_name(struct ahc_softc *ahc) 708 { 709 return (ahc->sc_dev.dv_xname); 710 } 711 712 #ifdef AHC_DEBUG 713 static void 714 ahc_print_scb(struct scb *scb) 715 { 716 struct hardware_scb *hscb = scb->hscb; 717 718 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 719 scb, 720 hscb->tag, 721 hscb->control, 722 hscb->tcl, 723 hscb->cmdlen, 724 (unsigned long)le32toh(hscb->cmdpointer)); 725 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 726 le32toh(hscb->datalen), 727 (unsigned long)(le32toh(hscb->data)), 728 hscb->SG_count, 729 (unsigned long)(le32toh(hscb->SG_pointer))); 730 printf(" sg_addr:%lx sg_len:%lu\n", 731 (unsigned long)(le32toh(scb->sg_list[0].addr)), 732 (unsigned long)(le32toh(scb->sg_list[0].len))); 733 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 734 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 735 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 736 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 737 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 738 } 739 #endif 740 741 static const struct { 742 u_int8_t errno; 743 const char *errmesg; 744 } hard_error[] = { 745 { ILLHADDR, "Illegal Host Access" }, 746 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 747 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 748 { SQPARERR, "Sequencer Parity Error" }, 749 { DPARERR, "Data-path Parity Error" }, 750 { MPARERR, "Scratch or SCB Memory Parity Error" }, 751 { PCIERRSTAT, "PCI Error detected" }, 752 { CIOPARERR, "CIOBUS Parity Error" }, 753 }; 754 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 755 756 static const struct { 757 u_int8_t phase; 758 u_int8_t mesg_out; /* Message response to parity errors */ 759 const char *phasemsg; 760 } phase_table[] = { 761 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 762 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 763 { P_COMMAND, MSG_NOOP, "in Command phase" }, 764 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 765 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 766 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 767 { P_BUSFREE, MSG_NOOP, "while idle" }, 768 { 0, MSG_NOOP, "in unknown phase" } 769 }; 770 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 771 772 /* 773 * Valid SCSIRATE values. (p. 3-17) 774 * Provides a mapping of tranfer periods in ns to the proper value to 775 * stick in the scsiscfr reg to use that transfer rate. 776 */ 777 #define AHC_SYNCRATE_DT 0 778 #define AHC_SYNCRATE_ULTRA2 1 779 #define AHC_SYNCRATE_ULTRA 3 780 #define AHC_SYNCRATE_FAST 6 781 static const struct ahc_syncrate ahc_syncrates[] = { 782 /* ultra2 fast/ultra period rate */ 783 { 0x42, 0x000, 9, "80.0" }, 784 { 0x03, 0x000, 10, "40.0" }, 785 { 0x04, 0x000, 11, "33.0" }, 786 { 0x05, 0x100, 12, "20.0" }, 787 { 0x06, 0x110, 15, "16.0" }, 788 { 0x07, 0x120, 18, "13.4" }, 789 { 0x08, 0x000, 25, "10.0" }, 790 { 0x19, 0x010, 31, "8.0" }, 791 { 0x1a, 0x020, 37, "6.67" }, 792 { 0x1b, 0x030, 43, "5.7" }, 793 { 0x1c, 0x040, 50, "5.0" }, 794 { 0x00, 0x050, 56, "4.4" }, 795 { 0x00, 0x060, 62, "4.0" }, 796 { 0x00, 0x070, 68, "3.6" }, 797 { 0x00, 0x000, 0, NULL } 798 }; 799 800 /* 801 * Allocate a controller structure for a new device and initialize it. 802 */ 803 int 804 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 805 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 806 ahc_flag flags) 807 { 808 struct scb_data *scb_data; 809 810 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 811 if (scb_data == NULL) { 812 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 813 return -1; 814 } 815 bzero(scb_data, sizeof (struct scb_data)); 816 LIST_INIT(&ahc->pending_ccbs); 817 ahc->tag = st; 818 ahc->bsh = sh; 819 ahc->parent_dmat = parent_dmat; 820 ahc->chip = chip; 821 ahc->features = features; 822 ahc->flags = flags; 823 ahc->scb_data = scb_data; 824 825 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 826 /* The IRQMS bit is only valid on VL and EISA chips */ 827 if ((ahc->chip & AHC_PCI) != 0) 828 ahc->unpause &= ~IRQMS; 829 ahc->pause = ahc->unpause | PAUSE; 830 return (0); 831 } 832 833 void 834 ahc_free(ahc) 835 struct ahc_softc *ahc; 836 { 837 ahcfiniscbdata(ahc); 838 if (ahc->init_level != 0) 839 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 840 ahc->shared_data_dmamap, ahc->qoutfifo, 841 &ahc->shared_data_seg, ahc->shared_data_nseg); 842 843 if (ahc->scb_data != NULL) 844 free(ahc->scb_data, M_DEVBUF); 845 if (ahc->bus_data != NULL) 846 free(ahc->bus_data, M_DEVBUF); 847 return; 848 } 849 850 static int 851 ahcinitscbdata(struct ahc_softc *ahc) 852 { 853 struct scb_data *scb_data; 854 int i; 855 856 scb_data = ahc->scb_data; 857 SLIST_INIT(&scb_data->free_scbs); 858 SLIST_INIT(&scb_data->sg_maps); 859 860 /* Allocate SCB resources */ 861 scb_data->scbarray = 862 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 863 M_DEVBUF, M_NOWAIT); 864 if (scb_data->scbarray == NULL) 865 return (ENOMEM); 866 bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); 867 868 /* Determine the number of hardware SCBs and initialize them */ 869 870 scb_data->maxhscbs = ahc_probe_scbs(ahc); 871 /* SCB 0 heads the free list */ 872 ahc_outb(ahc, FREE_SCBH, 0); 873 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 874 ahc_outb(ahc, SCBPTR, i); 875 876 /* Clear the control byte. */ 877 ahc_outb(ahc, SCB_CONTROL, 0); 878 879 /* Set the next pointer */ 880 ahc_outb(ahc, SCB_NEXT, i+1); 881 882 /* Make the tag number invalid */ 883 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 884 } 885 886 /* Make sure that the last SCB terminates the free list */ 887 ahc_outb(ahc, SCBPTR, i-1); 888 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 889 890 /* Ensure we clear the 0 SCB's control byte. */ 891 ahc_outb(ahc, SCBPTR, 0); 892 ahc_outb(ahc, SCB_CONTROL, 0); 893 894 scb_data->maxhscbs = i; 895 896 if (ahc->scb_data->maxhscbs == 0) 897 panic("%s: No SCB space found", ahc_name(ahc)); 898 899 /* 900 * Create our DMA tags. These tags define the kinds of device 901 * accessable memory allocations and memory mappings we will 902 * need to perform during normal operation. 903 * 904 * Unless we need to further restrict the allocation, we rely 905 * on the restrictions of the parent dmat, hence the common 906 * use of MAXADDR and MAXSIZE. 907 */ 908 909 if (ahc_createdmamem(ahc->parent_dmat, 910 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 911 &scb_data->hscb_dmamap, 912 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 913 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 914 "hardware SCB structures") < 0) 915 goto error_exit; 916 917 scb_data->init_level++; 918 919 if (ahc_createdmamem(ahc->parent_dmat, 920 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 921 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 922 &scb_data->sense_busaddr, &scb_data->sense_seg, 923 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 924 goto error_exit; 925 926 scb_data->init_level++; 927 928 /* Perform initial CCB allocation */ 929 bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); 930 ahcallocscbs(ahc); 931 932 if (scb_data->numscbs == 0) { 933 printf("%s: ahc_init_scb_data - " 934 "Unable to allocate initial scbs\n", 935 ahc_name(ahc)); 936 goto error_exit; 937 } 938 939 scb_data->init_level++; 940 941 /* 942 * Note that we were successfull 943 */ 944 return 0; 945 946 error_exit: 947 948 return ENOMEM; 949 } 950 951 static void 952 ahcfiniscbdata(struct ahc_softc *ahc) 953 { 954 struct scb_data *scb_data; 955 956 scb_data = ahc->scb_data; 957 958 switch (scb_data->init_level) { 959 default: 960 case 3: 961 { 962 struct sg_map_node *sg_map; 963 964 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 965 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 966 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 967 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 968 &sg_map->sg_dmasegs, sg_map->sg_nseg); 969 free(sg_map, M_DEVBUF); 970 } 971 } 972 /*FALLTHROUGH*/ 973 case 2: 974 ahc_freedmamem(ahc->parent_dmat, 975 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 976 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 977 &scb_data->sense_seg, scb_data->sense_nseg); 978 /*FALLTHROUGH*/ 979 case 1: 980 ahc_freedmamem(ahc->parent_dmat, 981 AHC_SCB_MAX * sizeof(struct hardware_scb), 982 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 983 &scb_data->hscb_seg, scb_data->hscb_nseg); 984 /*FALLTHROUGH*/ 985 } 986 if (scb_data->scbarray != NULL) 987 free(scb_data->scbarray, M_DEVBUF); 988 } 989 990 int 991 ahc_reset(struct ahc_softc *ahc) 992 { 993 u_int sblkctl; 994 int wait; 995 996 #ifdef AHC_DUMP_SEQ 997 if (ahc->init_level == 0) 998 ahc_dumpseq(ahc); 999 #endif 1000 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1001 /* 1002 * Ensure that the reset has finished 1003 */ 1004 wait = 1000; 1005 do { 1006 DELAY(1000); 1007 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1008 1009 if (wait == 0) { 1010 printf("%s: WARNING - Failed chip reset! " 1011 "Trying to initialize anyway.\n", ahc_name(ahc)); 1012 } 1013 ahc_outb(ahc, HCNTRL, ahc->pause); 1014 1015 /* Determine channel configuration */ 1016 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1017 /* No Twin Channel PCI cards */ 1018 if ((ahc->chip & AHC_PCI) != 0) 1019 sblkctl &= ~SELBUSB; 1020 switch (sblkctl) { 1021 case 0: 1022 /* Single Narrow Channel */ 1023 break; 1024 case 2: 1025 /* Wide Channel */ 1026 ahc->features |= AHC_WIDE; 1027 break; 1028 case 8: 1029 /* Twin Channel */ 1030 ahc->features |= AHC_TWIN; 1031 break; 1032 default: 1033 printf(" Unsupported adapter type. Ignoring\n"); 1034 return(-1); 1035 } 1036 1037 return (0); 1038 } 1039 1040 /* 1041 * Called when we have an active connection to a target on the bus, 1042 * this function finds the nearest syncrate to the input period limited 1043 * by the capabilities of the bus connectivity of the target. 1044 */ 1045 static const struct ahc_syncrate * 1046 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1047 u_int maxsync; 1048 1049 if ((ahc->features & AHC_ULTRA2) != 0) { 1050 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1051 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1052 maxsync = AHC_SYNCRATE_ULTRA2; 1053 } else { 1054 maxsync = AHC_SYNCRATE_ULTRA; 1055 } 1056 } else if ((ahc->features & AHC_ULTRA) != 0) { 1057 maxsync = AHC_SYNCRATE_ULTRA; 1058 } else { 1059 maxsync = AHC_SYNCRATE_FAST; 1060 } 1061 return (ahc_find_syncrate(ahc, period, maxsync)); 1062 } 1063 1064 /* 1065 * Look up the valid period to SCSIRATE conversion in our table. 1066 * Return the period and offset that should be sent to the target 1067 * if this was the beginning of an SDTR. 1068 */ 1069 static const struct ahc_syncrate * 1070 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1071 { 1072 const struct ahc_syncrate *syncrate; 1073 1074 syncrate = &ahc_syncrates[maxsync]; 1075 while ((syncrate->rate != NULL) 1076 && ((ahc->features & AHC_ULTRA2) == 0 1077 || (syncrate->sxfr_u2 != 0))) { 1078 1079 if (*period <= syncrate->period) { 1080 /* 1081 * When responding to a target that requests 1082 * sync, the requested rate may fall between 1083 * two rates that we can output, but still be 1084 * a rate that we can receive. Because of this, 1085 * we want to respond to the target with 1086 * the same rate that it sent to us even 1087 * if the period we use to send data to it 1088 * is lower. Only lower the response period 1089 * if we must. 1090 */ 1091 if (syncrate == &ahc_syncrates[maxsync]) 1092 *period = syncrate->period; 1093 break; 1094 } 1095 syncrate++; 1096 } 1097 1098 if ((*period == 0) 1099 || (syncrate->rate == NULL) 1100 || ((ahc->features & AHC_ULTRA2) != 0 1101 && (syncrate->sxfr_u2 == 0))) { 1102 /* Use asynchronous transfers. */ 1103 *period = 0; 1104 syncrate = NULL; 1105 } 1106 return (syncrate); 1107 } 1108 1109 static u_int 1110 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1111 { 1112 const struct ahc_syncrate *syncrate; 1113 1114 if ((ahc->features & AHC_ULTRA2) != 0) 1115 scsirate &= SXFR_ULTRA2; 1116 else 1117 scsirate &= SXFR; 1118 1119 syncrate = &ahc_syncrates[maxsync]; 1120 while (syncrate->rate != NULL) { 1121 1122 if ((ahc->features & AHC_ULTRA2) != 0) { 1123 if (syncrate->sxfr_u2 == 0) 1124 break; 1125 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1126 return (syncrate->period); 1127 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1128 return (syncrate->period); 1129 } 1130 syncrate++; 1131 } 1132 return (0); /* async */ 1133 } 1134 1135 static void 1136 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1137 u_int *offset, int wide) 1138 { 1139 u_int maxoffset; 1140 1141 /* Limit offset to what we can do */ 1142 if (syncrate == NULL) { 1143 maxoffset = 0; 1144 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1145 maxoffset = MAX_OFFSET_ULTRA2; 1146 } else { 1147 if (wide) 1148 maxoffset = MAX_OFFSET_16BIT; 1149 else 1150 maxoffset = MAX_OFFSET_8BIT; 1151 } 1152 *offset = MIN(*offset, maxoffset); 1153 } 1154 1155 static void 1156 ahc_update_target_msg_request(struct ahc_softc *ahc, 1157 struct ahc_devinfo *devinfo, 1158 struct ahc_initiator_tinfo *tinfo, 1159 int force, int paused) 1160 { 1161 u_int targ_msg_req_orig; 1162 1163 targ_msg_req_orig = ahc->targ_msg_req; 1164 if (tinfo->current.period != tinfo->goal.period 1165 || tinfo->current.width != tinfo->goal.width 1166 || tinfo->current.offset != tinfo->goal.offset 1167 || (force 1168 && (tinfo->goal.period != 0 1169 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1170 ahc->targ_msg_req |= devinfo->target_mask; 1171 } else { 1172 ahc->targ_msg_req &= ~devinfo->target_mask; 1173 } 1174 1175 if (ahc->targ_msg_req != targ_msg_req_orig) { 1176 /* Update the message request bit for this target */ 1177 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1178 if (paused) { 1179 ahc_outb(ahc, TARGET_MSG_REQUEST, 1180 ahc->targ_msg_req & 0xFF); 1181 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1182 (ahc->targ_msg_req >> 8) & 0xFF); 1183 } else { 1184 ahc_outb(ahc, HS_MAILBOX, 1185 0x01 << HOST_MAILBOX_SHIFT); 1186 } 1187 } else { 1188 if (!paused) 1189 pause_sequencer(ahc); 1190 1191 ahc_outb(ahc, TARGET_MSG_REQUEST, 1192 ahc->targ_msg_req & 0xFF); 1193 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1194 (ahc->targ_msg_req >> 8) & 0xFF); 1195 1196 if (!paused) 1197 unpause_sequencer(ahc); 1198 } 1199 } 1200 } 1201 1202 static void 1203 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1204 const struct ahc_syncrate *syncrate, 1205 u_int period, u_int offset, u_int type, int paused, int done) 1206 { 1207 struct ahc_initiator_tinfo *tinfo; 1208 struct tmode_tstate *tstate; 1209 u_int old_period; 1210 u_int old_offset; 1211 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1212 1213 if (syncrate == NULL) { 1214 period = 0; 1215 offset = 0; 1216 } 1217 1218 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1219 devinfo->target, &tstate); 1220 old_period = tinfo->current.period; 1221 old_offset = tinfo->current.offset; 1222 1223 if ((type & AHC_TRANS_CUR) != 0 1224 && (old_period != period || old_offset != offset)) { 1225 u_int scsirate; 1226 1227 scsirate = tinfo->scsirate; 1228 if ((ahc->features & AHC_ULTRA2) != 0) { 1229 1230 /* XXX */ 1231 /* Force single edge until DT is fully implemented */ 1232 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1233 if (syncrate != NULL) 1234 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1235 1236 if (active) 1237 ahc_outb(ahc, SCSIOFFSET, offset); 1238 } else { 1239 1240 scsirate &= ~(SXFR|SOFS); 1241 /* 1242 * Ensure Ultra mode is set properly for 1243 * this target. 1244 */ 1245 tstate->ultraenb &= ~devinfo->target_mask; 1246 if (syncrate != NULL) { 1247 if (syncrate->sxfr & ULTRA_SXFR) { 1248 tstate->ultraenb |= 1249 devinfo->target_mask; 1250 } 1251 scsirate |= syncrate->sxfr & SXFR; 1252 scsirate |= offset & SOFS; 1253 } 1254 if (active) { 1255 u_int sxfrctl0; 1256 1257 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1258 sxfrctl0 &= ~FAST20; 1259 if (tstate->ultraenb & devinfo->target_mask) 1260 sxfrctl0 |= FAST20; 1261 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1262 } 1263 } 1264 if (active) 1265 ahc_outb(ahc, SCSIRATE, scsirate); 1266 1267 tinfo->scsirate = scsirate; 1268 tinfo->current.period = period; 1269 tinfo->current.offset = offset; 1270 1271 /* Update the syncrates in any pending scbs */ 1272 ahc_update_pending_syncrates(ahc); 1273 } 1274 1275 if ((type & AHC_TRANS_GOAL) != 0) { 1276 tinfo->goal.period = period; 1277 tinfo->goal.offset = offset; 1278 } 1279 1280 if ((type & AHC_TRANS_USER) != 0) { 1281 tinfo->user.period = period; 1282 tinfo->user.offset = offset; 1283 } 1284 1285 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1286 /*force*/FALSE, 1287 paused); 1288 } 1289 1290 static void 1291 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1292 u_int width, u_int type, int paused, int done) 1293 { 1294 struct ahc_initiator_tinfo *tinfo; 1295 struct tmode_tstate *tstate; 1296 u_int oldwidth; 1297 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1298 1299 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1300 devinfo->target, &tstate); 1301 oldwidth = tinfo->current.width; 1302 1303 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1304 u_int scsirate; 1305 1306 scsirate = tinfo->scsirate; 1307 scsirate &= ~WIDEXFER; 1308 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1309 scsirate |= WIDEXFER; 1310 1311 tinfo->scsirate = scsirate; 1312 1313 if (active) 1314 ahc_outb(ahc, SCSIRATE, scsirate); 1315 1316 tinfo->current.width = width; 1317 } 1318 1319 if ((type & AHC_TRANS_GOAL) != 0) 1320 tinfo->goal.width = width; 1321 if ((type & AHC_TRANS_USER) != 0) 1322 tinfo->user.width = width; 1323 1324 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1325 /*force*/FALSE, paused); 1326 } 1327 1328 static void 1329 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1330 { 1331 struct ahc_initiator_tinfo *tinfo; 1332 struct tmode_tstate *tstate; 1333 1334 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1335 devinfo->target, &tstate); 1336 1337 if (enable) { 1338 tstate->tagenable |= devinfo->target_mask; 1339 } else { 1340 tstate->tagenable &= ~devinfo->target_mask; 1341 tstate->tagdisable |= devinfo->target_mask; 1342 } 1343 } 1344 1345 static void 1346 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1347 { 1348 struct scsipi_xfer_mode xm; 1349 struct ahc_initiator_tinfo *tinfo; 1350 struct tmode_tstate *tstate; 1351 1352 if (ahc->inited_targets[devinfo->target] != 2) 1353 return; 1354 1355 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1356 devinfo->target, &tstate); 1357 1358 xm.xm_target = devinfo->target; 1359 xm.xm_mode = 0; 1360 xm.xm_period = tinfo->current.period; 1361 xm.xm_offset = tinfo->current.offset; 1362 if (tinfo->current.width == 1) 1363 xm.xm_mode |= PERIPH_CAP_WIDE16; 1364 if (tinfo->current.period) 1365 xm.xm_mode |= PERIPH_CAP_SYNC; 1366 if (tstate->tagenable & devinfo->target_mask) 1367 xm.xm_mode |= PERIPH_CAP_TQING; 1368 scsipi_async_event( 1369 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1370 ASYNC_EVENT_XFER_MODE, &xm); 1371 } 1372 1373 /* 1374 * Attach all the sub-devices we can find 1375 */ 1376 int 1377 ahc_attach(struct ahc_softc *ahc) 1378 { 1379 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1380 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1381 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1382 ahc->sc_adapter.adapt_max_periph = AHC_SCB_MAX; 1383 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1384 ahc->sc_adapter.adapt_minphys = ahcminphys; 1385 ahc->sc_adapter.adapt_request = ahc_action; 1386 1387 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1388 ahc->sc_channel.chan_bustype = &scsi_bustype; 1389 ahc->sc_channel.chan_channel = 0; 1390 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1391 ahc->sc_channel.chan_nluns = 8; 1392 ahc->sc_channel.chan_id = ahc->our_id; 1393 1394 if (ahc->features & AHC_TWIN) { 1395 ahc->sc_channel_b = ahc->sc_channel; 1396 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1397 ahc->sc_channel_b.chan_channel = 1; 1398 } 1399 1400 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1401 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1402 if (ahc->features & AHC_TWIN) 1403 config_found((void *)ahc, &ahc->sc_channel_b, 1404 scsiprint); 1405 } else { 1406 config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1407 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1408 } 1409 return 1; 1410 } 1411 1412 static void 1413 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1414 { 1415 u_int saved_tcl; 1416 role_t role; 1417 int our_id; 1418 1419 if (ahc_inb(ahc, SSTAT0) & TARGET) 1420 role = ROLE_TARGET; 1421 else 1422 role = ROLE_INITIATOR; 1423 1424 if (role == ROLE_TARGET 1425 && (ahc->features & AHC_MULTI_TID) != 0 1426 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1427 /* We were selected, so pull our id from TARGIDIN */ 1428 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1429 } else if ((ahc->features & AHC_ULTRA2) != 0) 1430 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1431 else 1432 our_id = ahc_inb(ahc, SCSIID) & OID; 1433 1434 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1435 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1436 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1437 role); 1438 } 1439 1440 static void 1441 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1442 u_int lun, char channel, role_t role) 1443 { 1444 devinfo->our_scsiid = our_id; 1445 devinfo->target = target; 1446 devinfo->lun = lun; 1447 devinfo->target_offset = target; 1448 devinfo->channel = channel; 1449 devinfo->role = role; 1450 if (channel == 'B') 1451 devinfo->target_offset += 8; 1452 devinfo->target_mask = (0x01 << devinfo->target_offset); 1453 } 1454 1455 /* 1456 * Catch an interrupt from the adapter 1457 */ 1458 int 1459 ahc_intr(void *arg) 1460 { 1461 struct ahc_softc *ahc; 1462 u_int intstat; 1463 1464 ahc = (struct ahc_softc *)arg; 1465 1466 intstat = ahc_inb(ahc, INTSTAT); 1467 1468 /* 1469 * Any interrupts to process? 1470 */ 1471 if ((intstat & INT_PEND) == 0) { 1472 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1473 #ifdef AHC_DEBUG 1474 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1475 ahc_name(ahc), 1476 ahc_inb(ahc, CCHADDR) | 1477 (ahc_inb(ahc, CCHADDR+1) << 8) 1478 | (ahc_inb(ahc, CCHADDR+2) << 16) 1479 | (ahc_inb(ahc, CCHADDR+3) << 24), 1480 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1481 | (ahc_inb(ahc, HADDR+2) << 16) 1482 | (ahc_inb(ahc, HADDR+3) << 24), 1483 ahc_inb(ahc, SEQADDR0) | 1484 (ahc_inb(ahc, SEQADDR1) << 8)); 1485 #endif 1486 return 1; 1487 } 1488 return 0; 1489 } 1490 1491 #ifdef AHC_DEBUG 1492 if (ahc_debug & AHC_SHOWINTR) { 1493 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1494 } 1495 #endif 1496 1497 if (intstat & CMDCMPLT) { 1498 ahc_outb(ahc, CLRINT, CLRCMDINT); 1499 ahc_run_qoutfifo(ahc); 1500 } 1501 if (intstat & BRKADRINT) { 1502 /* 1503 * We upset the sequencer :-( 1504 * Lookup the error message 1505 */ 1506 int i, error, num_errors; 1507 1508 error = ahc_inb(ahc, ERROR); 1509 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1510 for (i = 0; error != 1 && i < num_errors; i++) 1511 error >>= 1; 1512 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1513 ahc_name(ahc), hard_error[i].errmesg, 1514 ahc_inb(ahc, SEQADDR0) | 1515 (ahc_inb(ahc, SEQADDR1) << 8)); 1516 1517 /* Tell everyone that this HBA is no longer availible */ 1518 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1519 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1520 XS_DRIVER_STUFFUP); 1521 } 1522 if (intstat & SEQINT) 1523 ahc_handle_seqint(ahc, intstat); 1524 1525 if (intstat & SCSIINT) 1526 ahc_handle_scsiint(ahc, intstat); 1527 1528 return 1; 1529 } 1530 1531 static struct tmode_tstate * 1532 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1533 { 1534 struct tmode_tstate *master_tstate; 1535 struct tmode_tstate *tstate; 1536 int i, s; 1537 1538 master_tstate = ahc->enabled_targets[ahc->our_id]; 1539 if (channel == 'B') { 1540 scsi_id += 8; 1541 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1542 } 1543 if (ahc->enabled_targets[scsi_id] != NULL 1544 && ahc->enabled_targets[scsi_id] != master_tstate) 1545 panic("%s: ahc_alloc_tstate - Target already allocated", 1546 ahc_name(ahc)); 1547 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1548 if (tstate == NULL) 1549 return (NULL); 1550 1551 /* 1552 * If we have allocated a master tstate, copy user settings from 1553 * the master tstate (taken from SRAM or the EEPROM) for this 1554 * channel, but reset our current and goal settings to async/narrow 1555 * until an initiator talks to us. 1556 */ 1557 if (master_tstate != NULL) { 1558 bcopy(master_tstate, tstate, sizeof(*tstate)); 1559 tstate->ultraenb = 0; 1560 for (i = 0; i < 16; i++) { 1561 bzero(&tstate->transinfo[i].current, 1562 sizeof(tstate->transinfo[i].current)); 1563 bzero(&tstate->transinfo[i].goal, 1564 sizeof(tstate->transinfo[i].goal)); 1565 } 1566 } else 1567 bzero(tstate, sizeof(*tstate)); 1568 s = splbio(); 1569 ahc->enabled_targets[scsi_id] = tstate; 1570 splx(s); 1571 return (tstate); 1572 } 1573 1574 #if UNUSED 1575 static void 1576 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1577 { 1578 struct tmode_tstate *tstate; 1579 1580 /* Don't clean up the entry for our initiator role */ 1581 if ((ahc->flags & AHC_INITIATORMODE) != 0 1582 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1583 || (channel == 'A' && scsi_id == ahc->our_id)) 1584 && force == FALSE) 1585 return; 1586 1587 if (channel == 'B') 1588 scsi_id += 8; 1589 tstate = ahc->enabled_targets[scsi_id]; 1590 if (tstate != NULL) 1591 free(tstate, M_DEVBUF); 1592 ahc->enabled_targets[scsi_id] = NULL; 1593 } 1594 #endif 1595 1596 static void 1597 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1598 { 1599 struct scb *scb; 1600 struct ahc_devinfo devinfo; 1601 1602 ahc_fetch_devinfo(ahc, &devinfo); 1603 1604 /* 1605 * Clear the upper byte that holds SEQINT status 1606 * codes and clear the SEQINT bit. We will unpause 1607 * the sequencer, if appropriate, after servicing 1608 * the request. 1609 */ 1610 ahc_outb(ahc, CLRINT, CLRSEQINT); 1611 switch (intstat & SEQINT_MASK) { 1612 case NO_MATCH: 1613 { 1614 /* Ensure we don't leave the selection hardware on */ 1615 ahc_outb(ahc, SCSISEQ, 1616 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1617 1618 printf("%s:%c:%d: no active SCB for reconnecting " 1619 "target - issuing BUS DEVICE RESET\n", 1620 ahc_name(ahc), devinfo.channel, devinfo.target); 1621 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1622 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1623 ahc_inb(ahc, SEQ_FLAGS)); 1624 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1625 ahc->msgout_len = 1; 1626 ahc->msgout_index = 0; 1627 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1628 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1629 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1630 break; 1631 } 1632 case UPDATE_TMSG_REQ: 1633 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1634 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1635 (ahc->targ_msg_req >> 8) & 0xFF); 1636 ahc_outb(ahc, HS_MAILBOX, 0); 1637 break; 1638 case SEND_REJECT: 1639 { 1640 u_int rejbyte = ahc_inb(ahc, ACCUM); 1641 printf("%s:%c:%d: Warning - unknown message received from " 1642 "target (0x%x). Rejecting\n", 1643 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1644 break; 1645 } 1646 case NO_IDENT: 1647 { 1648 /* 1649 * The reconnecting target either did not send an identify 1650 * message, or did, but we didn't find and SCB to match and 1651 * before it could respond to our ATN/abort, it hit a dataphase. 1652 * The only safe thing to do is to blow it away with a bus 1653 * reset. 1654 */ 1655 int found; 1656 1657 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1658 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1659 ahc_name(ahc), devinfo.channel, devinfo.target, 1660 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1661 found = ahc_reset_channel(ahc, devinfo.channel, 1662 /*initiate reset*/TRUE); 1663 printf("%s: Issued Channel %c Bus Reset. " 1664 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1665 found); 1666 return; 1667 } 1668 case BAD_PHASE: 1669 { 1670 u_int lastphase; 1671 1672 lastphase = ahc_inb(ahc, LASTPHASE); 1673 if (lastphase == P_BUSFREE) { 1674 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1675 ahc_name(ahc), devinfo.channel, devinfo.target, 1676 ahc_inb(ahc, SCSISIGI)); 1677 restart_sequencer(ahc); 1678 return; 1679 } else { 1680 printf("%s:%c:%d: unknown scsi bus phase %x. " 1681 "Attempting to continue\n", 1682 ahc_name(ahc), devinfo.channel, devinfo.target, 1683 ahc_inb(ahc, SCSISIGI)); 1684 } 1685 break; 1686 } 1687 case BAD_STATUS: 1688 { 1689 u_int scb_index; 1690 struct hardware_scb *hscb; 1691 struct scsipi_xfer *xs; 1692 /* 1693 * The sequencer will notify us when a command 1694 * has an error that would be of interest to 1695 * the kernel. This allows us to leave the sequencer 1696 * running in the common case of command completes 1697 * without error. The sequencer will already have 1698 * dma'd the SCB back up to us, so we can reference 1699 * the in kernel copy directly. 1700 */ 1701 scb_index = ahc_inb(ahc, SCB_TAG); 1702 scb = &ahc->scb_data->scbarray[scb_index]; 1703 1704 /* ahc_print_scb(scb); */ 1705 1706 /* 1707 * Set the default return value to 0 (don't 1708 * send sense). The sense code will change 1709 * this if needed. 1710 */ 1711 ahc_outb(ahc, RETURN_1, 0); 1712 if (!(scb_index < ahc->scb_data->numscbs 1713 && (scb->flags & SCB_ACTIVE) != 0)) { 1714 printf("%s:%c:%d: ahc_intr - referenced scb " 1715 "not valid during seqint 0x%x scb(%d)\n", 1716 ahc_name(ahc), devinfo.channel, 1717 devinfo.target, intstat, scb_index); 1718 goto unpause; 1719 } 1720 1721 hscb = scb->hscb; 1722 xs = scb->xs; 1723 1724 /* Don't want to clobber the original sense code */ 1725 if ((scb->flags & SCB_SENSE) != 0) { 1726 /* 1727 * Clear the SCB_SENSE Flag and have 1728 * the sequencer do a normal command 1729 * complete. 1730 */ 1731 scb->flags &= ~SCB_SENSE; 1732 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1733 break; 1734 } 1735 /* Freeze the queue unit the client sees the error. */ 1736 ahc_freeze_devq(ahc, xs->xs_periph); 1737 ahc_freeze_ccb(scb); 1738 xs->status = hscb->status; 1739 switch (hscb->status) { 1740 case SCSI_STATUS_OK: 1741 printf("%s: Interrupted for status of 0???\n", 1742 ahc_name(ahc)); 1743 break; 1744 case SCSI_STATUS_CMD_TERMINATED: 1745 case SCSI_STATUS_CHECK_COND: 1746 #if defined(AHC_DEBUG) 1747 if (ahc_debug & AHC_SHOWSENSE) { 1748 scsipi_printaddr(xs->xs_periph); 1749 printf("Check Status, resid %d datalen %d\n", 1750 xs->resid, xs->datalen); 1751 } 1752 #endif 1753 1754 if (xs->error == XS_NOERROR && 1755 !(scb->flags & SCB_SENSE)) { 1756 struct ahc_dma_seg *sg; 1757 struct scsipi_sense *sc; 1758 struct ahc_initiator_tinfo *tinfo; 1759 struct tmode_tstate *tstate; 1760 1761 sg = scb->sg_list; 1762 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1763 /* 1764 * Save off the residual if there is one. 1765 */ 1766 if (hscb->residual_SG_count != 0) 1767 ahc_calc_residual(scb); 1768 else 1769 xs->resid = 0; 1770 1771 #ifdef AHC_DEBUG 1772 if (ahc_debug & AHC_SHOWSENSE) { 1773 scsipi_printaddr(xs->xs_periph); 1774 printf("Sending Sense\n"); 1775 } 1776 #endif 1777 sg->addr = ahc->scb_data->sense_busaddr + 1778 (hscb->tag*sizeof(struct scsipi_sense_data)); 1779 sg->len = sizeof (struct scsipi_sense_data); 1780 1781 sc->opcode = REQUEST_SENSE; 1782 sc->byte2 = SCB_LUN(scb) << 5; 1783 sc->unused[0] = 0; 1784 sc->unused[1] = 0; 1785 sc->length = sg->len; 1786 sc->control = 0; 1787 1788 /* 1789 * Would be nice to preserve DISCENB here, 1790 * but due to the way we page SCBs, we can't. 1791 */ 1792 hscb->control = 0; 1793 1794 /* 1795 * This request sense could be because the 1796 * the device lost power or in some other 1797 * way has lost our transfer negotiations. 1798 * Renegotiate if appropriate. Unit attention 1799 * errors will be reported before any data 1800 * phases occur. 1801 */ 1802 ahc_calc_residual(scb); 1803 #if defined(AHC_DEBUG) 1804 if (ahc_debug & AHC_SHOWSENSE) { 1805 scsipi_printaddr(xs->xs_periph); 1806 printf("Sense: datalen %d resid %d" 1807 "chan %d id %d targ %d\n", 1808 xs->datalen, xs->resid, 1809 devinfo.channel, devinfo.our_scsiid, 1810 devinfo.target); 1811 } 1812 #endif 1813 if (xs->datalen > 0 && 1814 xs->resid == xs->datalen) { 1815 tinfo = ahc_fetch_transinfo(ahc, 1816 devinfo.channel, 1817 devinfo.our_scsiid, 1818 devinfo.target, 1819 &tstate); 1820 ahc_update_target_msg_request(ahc, 1821 &devinfo, 1822 tinfo, 1823 /*force*/TRUE, 1824 /*paused*/TRUE); 1825 } 1826 hscb->status = 0; 1827 hscb->SG_count = 1; 1828 hscb->SG_pointer = scb->sg_list_phys; 1829 hscb->data = sg->addr; 1830 hscb->datalen = sg->len; 1831 hscb->cmdpointer = hscb->cmdstore_busaddr; 1832 hscb->cmdlen = sizeof(*sc); 1833 scb->sg_count = hscb->SG_count; 1834 ahc_swap_hscb(hscb); 1835 ahc_swap_sg(scb->sg_list); 1836 scb->flags |= SCB_SENSE; 1837 /* 1838 * Ensure the target is busy since this 1839 * will be an untagged request. 1840 */ 1841 ahc_busy_tcl(ahc, scb); 1842 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1843 1844 /* 1845 * Ensure we have enough time to actually 1846 * retrieve the sense. 1847 */ 1848 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1849 callout_reset(&scb->xs->xs_callout, 1850 5 * hz, ahc_timeout, scb); 1851 } 1852 } 1853 break; 1854 case SCSI_STATUS_QUEUE_FULL: 1855 case SCSI_STATUS_BUSY: 1856 xs->error = XS_BUSY; 1857 break; 1858 } 1859 break; 1860 } 1861 case TRACE_POINT: 1862 { 1863 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1864 ahc_inb(ahc, DFCNTRL)); 1865 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1866 ahc_inb(ahc, DFSTATUS)); 1867 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1868 ahc_inb(ahc, SSTAT0), 1869 ahc_inb(ahc, SCB_DATACNT)); 1870 break; 1871 } 1872 case HOST_MSG_LOOP: 1873 { 1874 /* 1875 * The sequencer has encountered a message phase 1876 * that requires host assistance for completion. 1877 * While handling the message phase(s), we will be 1878 * notified by the sequencer after each byte is 1879 * transfered so we can track bus phases. 1880 * 1881 * If this is the first time we've seen a HOST_MSG_LOOP, 1882 * initialize the state of the host message loop. 1883 */ 1884 if (ahc->msg_type == MSG_TYPE_NONE) { 1885 u_int bus_phase; 1886 1887 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1888 if (bus_phase != P_MESGIN 1889 && bus_phase != P_MESGOUT) { 1890 printf("ahc_intr: HOST_MSG_LOOP bad " 1891 "phase 0x%x\n", 1892 bus_phase); 1893 /* 1894 * Probably transitioned to bus free before 1895 * we got here. Just punt the message. 1896 */ 1897 ahc_clear_intstat(ahc); 1898 restart_sequencer(ahc); 1899 } 1900 1901 if (devinfo.role == ROLE_INITIATOR) { 1902 struct scb *scb; 1903 u_int scb_index; 1904 1905 scb_index = ahc_inb(ahc, SCB_TAG); 1906 scb = &ahc->scb_data->scbarray[scb_index]; 1907 1908 if (bus_phase == P_MESGOUT) 1909 ahc_setup_initiator_msgout(ahc, 1910 &devinfo, 1911 scb); 1912 else { 1913 ahc->msg_type = 1914 MSG_TYPE_INITIATOR_MSGIN; 1915 ahc->msgin_index = 0; 1916 } 1917 } else { 1918 if (bus_phase == P_MESGOUT) { 1919 ahc->msg_type = 1920 MSG_TYPE_TARGET_MSGOUT; 1921 ahc->msgin_index = 0; 1922 } else 1923 /* XXX Ever executed??? */ 1924 ahc_setup_target_msgin(ahc, &devinfo); 1925 } 1926 } 1927 1928 /* Pass a NULL path so that handlers generate their own */ 1929 ahc_handle_message_phase(ahc, /*path*/NULL); 1930 break; 1931 } 1932 case PERR_DETECTED: 1933 { 1934 /* 1935 * If we've cleared the parity error interrupt 1936 * but the sequencer still believes that SCSIPERR 1937 * is true, it must be that the parity error is 1938 * for the currently presented byte on the bus, 1939 * and we are not in a phase (data-in) where we will 1940 * eventually ack this byte. Ack the byte and 1941 * throw it away in the hope that the target will 1942 * take us to message out to deliver the appropriate 1943 * error message. 1944 */ 1945 if ((intstat & SCSIINT) == 0 1946 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1947 u_int curphase; 1948 1949 /* 1950 * The hardware will only let you ack bytes 1951 * if the expected phase in SCSISIGO matches 1952 * the current phase. Make sure this is 1953 * currently the case. 1954 */ 1955 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1956 ahc_outb(ahc, LASTPHASE, curphase); 1957 ahc_outb(ahc, SCSISIGO, curphase); 1958 ahc_inb(ahc, SCSIDATL); 1959 } 1960 break; 1961 } 1962 case DATA_OVERRUN: 1963 { 1964 /* 1965 * When the sequencer detects an overrun, it 1966 * places the controller in "BITBUCKET" mode 1967 * and allows the target to complete its transfer. 1968 * Unfortunately, none of the counters get updated 1969 * when the controller is in this mode, so we have 1970 * no way of knowing how large the overrun was. 1971 */ 1972 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1973 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1974 int i; 1975 1976 scb = &ahc->scb_data->scbarray[scbindex]; 1977 for (i = 0; i < num_phases; i++) { 1978 if (lastphase == phase_table[i].phase) 1979 break; 1980 } 1981 scsipi_printaddr(scb->xs->xs_periph); 1982 printf("data overrun detected %s." 1983 " Tag == 0x%x.\n", 1984 phase_table[i].phasemsg, 1985 scb->hscb->tag); 1986 scsipi_printaddr(scb->xs->xs_periph); 1987 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1988 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1989 scb->xs->datalen, scb->sg_count); 1990 if (scb->sg_count > 0) { 1991 for (i = 0; i < scb->sg_count; i++) { 1992 printf("sg[%d] - Addr 0x%x : Length %d\n", 1993 i, 1994 le32toh(scb->sg_list[i].addr), 1995 le32toh(scb->sg_list[i].len)); 1996 } 1997 } 1998 /* 1999 * Set this and it will take affect when the 2000 * target does a command complete. 2001 */ 2002 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2003 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2004 ahc_freeze_ccb(scb); 2005 break; 2006 } 2007 case TRACEPOINT: 2008 { 2009 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2010 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2011 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2012 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2013 printf("TRACEPOINT: CCHADDR = %x\n", 2014 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2015 | (ahc_inb(ahc, CCHADDR+2) << 16) 2016 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2017 #if 0 2018 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2019 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2020 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2021 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2022 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2023 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2024 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2025 ahc_inb(ahc, CCHADDR) 2026 | (ahc_inb(ahc, CCHADDR+1) << 8) 2027 | (ahc_inb(ahc, CCHADDR+2) << 16) 2028 | (ahc_inb(ahc, CCHADDR+3) << 24), 2029 ahc_inb(ahc, CCHCNT) 2030 | (ahc_inb(ahc, CCHCNT+1) << 8) 2031 | (ahc_inb(ahc, CCHCNT+2) << 16), 2032 ahc_inb(ahc, SCBPTR)); 2033 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2034 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2035 #if DDB > 0 2036 cpu_Debugger(); 2037 #endif 2038 #endif 2039 break; 2040 } 2041 #if NOT_YET 2042 /* XXX Fill these in later */ 2043 case MESG_BUFFER_BUSY: 2044 break; 2045 case MSGIN_PHASEMIS: 2046 break; 2047 #endif 2048 default: 2049 printf("ahc_intr: seqint, " 2050 "intstat == 0x%x, scsisigi = 0x%x\n", 2051 intstat, ahc_inb(ahc, SCSISIGI)); 2052 break; 2053 } 2054 2055 unpause: 2056 /* 2057 * The sequencer is paused immediately on 2058 * a SEQINT, so we should restart it when 2059 * we're done. 2060 */ 2061 unpause_sequencer(ahc); 2062 } 2063 2064 static void 2065 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2066 { 2067 u_int scb_index; 2068 u_int status; 2069 struct scb *scb; 2070 char cur_channel; 2071 char intr_channel; 2072 2073 if ((ahc->features & AHC_TWIN) != 0 2074 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2075 cur_channel = 'B'; 2076 else 2077 cur_channel = 'A'; 2078 intr_channel = cur_channel; 2079 2080 status = ahc_inb(ahc, SSTAT1); 2081 if (status == 0) { 2082 if ((ahc->features & AHC_TWIN) != 0) { 2083 /* Try the other channel */ 2084 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2085 status = ahc_inb(ahc, SSTAT1); 2086 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2087 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2088 } 2089 if (status == 0) { 2090 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2091 return; 2092 } 2093 } 2094 2095 scb_index = ahc_inb(ahc, SCB_TAG); 2096 if (scb_index < ahc->scb_data->numscbs) { 2097 scb = &ahc->scb_data->scbarray[scb_index]; 2098 if ((scb->flags & SCB_ACTIVE) == 0 2099 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2100 scb = NULL; 2101 } else 2102 scb = NULL; 2103 2104 if ((status & SCSIRSTI) != 0) { 2105 printf("%s: Someone reset channel %c\n", 2106 ahc_name(ahc), intr_channel); 2107 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2108 } else if ((status & SCSIPERR) != 0) { 2109 /* 2110 * Determine the bus phase and queue an appropriate message. 2111 * SCSIPERR is latched true as soon as a parity error 2112 * occurs. If the sequencer acked the transfer that 2113 * caused the parity error and the currently presented 2114 * transfer on the bus has correct parity, SCSIPERR will 2115 * be cleared by CLRSCSIPERR. Use this to determine if 2116 * we should look at the last phase the sequencer recorded, 2117 * or the current phase presented on the bus. 2118 */ 2119 u_int mesg_out; 2120 u_int curphase; 2121 u_int errorphase; 2122 u_int lastphase; 2123 int i; 2124 2125 lastphase = ahc_inb(ahc, LASTPHASE); 2126 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2127 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2128 /* 2129 * For all phases save DATA, the sequencer won't 2130 * automatically ack a byte that has a parity error 2131 * in it. So the only way that the current phase 2132 * could be 'data-in' is if the parity error is for 2133 * an already acked byte in the data phase. During 2134 * synchronous data-in transfers, we may actually 2135 * ack bytes before latching the current phase in 2136 * LASTPHASE, leading to the discrepancy between 2137 * curphase and lastphase. 2138 */ 2139 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2140 || curphase == P_DATAIN) 2141 errorphase = curphase; 2142 else 2143 errorphase = lastphase; 2144 2145 for (i = 0; i < num_phases; i++) { 2146 if (errorphase == phase_table[i].phase) 2147 break; 2148 } 2149 mesg_out = phase_table[i].mesg_out; 2150 if (scb != NULL) 2151 scsipi_printaddr(scb->xs->xs_periph); 2152 else 2153 printf("%s:%c:%d: ", ahc_name(ahc), 2154 intr_channel, 2155 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2156 2157 printf("parity error detected %s. " 2158 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2159 phase_table[i].phasemsg, 2160 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2161 ahc_inb(ahc, SCSIRATE)); 2162 2163 /* 2164 * We've set the hardware to assert ATN if we 2165 * get a parity error on "in" phases, so all we 2166 * need to do is stuff the message buffer with 2167 * the appropriate message. "In" phases have set 2168 * mesg_out to something other than MSG_NOP. 2169 */ 2170 if (mesg_out != MSG_NOOP) { 2171 if (ahc->msg_type != MSG_TYPE_NONE) 2172 ahc->send_msg_perror = TRUE; 2173 else 2174 ahc_outb(ahc, MSG_OUT, mesg_out); 2175 } 2176 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2177 unpause_sequencer(ahc); 2178 } else if ((status & BUSFREE) != 0 2179 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2180 /* 2181 * First look at what phase we were last in. 2182 * If its message out, chances are pretty good 2183 * that the busfree was in response to one of 2184 * our abort requests. 2185 */ 2186 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2187 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2188 u_int target = TCL_TARGET(saved_tcl); 2189 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2190 char channel = TCL_CHANNEL(ahc, saved_tcl); 2191 int printerror = 1; 2192 2193 ahc_outb(ahc, SCSISEQ, 2194 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2195 if (lastphase == P_MESGOUT) { 2196 u_int message; 2197 u_int tag; 2198 2199 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2200 tag = SCB_LIST_NULL; 2201 switch (message) { 2202 case MSG_ABORT_TAG: 2203 tag = scb->hscb->tag; 2204 /* FALLTRHOUGH */ 2205 case MSG_ABORT: 2206 scsipi_printaddr(scb->xs->xs_periph); 2207 printf("SCB %x - Abort %s Completed.\n", 2208 scb->hscb->tag, tag == SCB_LIST_NULL ? 2209 "" : "Tag"); 2210 ahc_abort_scbs(ahc, target, channel, 2211 TCL_LUN(saved_tcl), tag, 2212 ROLE_INITIATOR, 2213 XS_DRIVER_STUFFUP); 2214 printerror = 0; 2215 break; 2216 case MSG_BUS_DEV_RESET: 2217 { 2218 struct ahc_devinfo devinfo; 2219 2220 if (scb != NULL && 2221 (scb->xs->xs_control & XS_CTL_RESET) 2222 && ahc_match_scb(scb, target, channel, 2223 TCL_LUN(saved_tcl), 2224 SCB_LIST_NULL, 2225 ROLE_INITIATOR)) { 2226 ahcsetccbstatus(scb->xs, XS_NOERROR); 2227 } 2228 ahc_compile_devinfo(&devinfo, 2229 initiator_role_id, 2230 target, 2231 TCL_LUN(saved_tcl), 2232 channel, 2233 ROLE_INITIATOR); 2234 ahc_handle_devreset(ahc, &devinfo, 2235 XS_RESET, 2236 "Bus Device Reset", 2237 /*verbose_level*/0); 2238 printerror = 0; 2239 break; 2240 } 2241 default: 2242 break; 2243 } 2244 } 2245 if (printerror != 0) { 2246 int i; 2247 2248 if (scb != NULL) { 2249 u_int tag; 2250 2251 if ((scb->hscb->control & TAG_ENB) != 0) 2252 tag = scb->hscb->tag; 2253 else 2254 tag = SCB_LIST_NULL; 2255 ahc_abort_scbs(ahc, target, channel, 2256 SCB_LUN(scb), tag, 2257 ROLE_INITIATOR, 2258 XS_DRIVER_STUFFUP); 2259 scsipi_printaddr(scb->xs->xs_periph); 2260 } else { 2261 /* 2262 * We had not fully identified this connection, 2263 * so we cannot abort anything. 2264 */ 2265 printf("%s: ", ahc_name(ahc)); 2266 } 2267 for (i = 0; i < num_phases; i++) { 2268 if (lastphase == phase_table[i].phase) 2269 break; 2270 } 2271 printf("Unexpected busfree %s\n" 2272 "SEQADDR == 0x%x\n", 2273 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2274 | (ahc_inb(ahc, SEQADDR1) << 8)); 2275 } 2276 ahc_clear_msg_state(ahc); 2277 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2278 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2279 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2280 restart_sequencer(ahc); 2281 } else if ((status & SELTO) != 0) { 2282 u_int scbptr; 2283 2284 scbptr = ahc_inb(ahc, WAITING_SCBH); 2285 ahc_outb(ahc, SCBPTR, scbptr); 2286 scb_index = ahc_inb(ahc, SCB_TAG); 2287 2288 if (scb_index < ahc->scb_data->numscbs) { 2289 scb = &ahc->scb_data->scbarray[scb_index]; 2290 if ((scb->flags & SCB_ACTIVE) == 0) 2291 scb = NULL; 2292 } else 2293 scb = NULL; 2294 2295 if (scb == NULL) { 2296 printf("%s: ahc_intr - referenced scb not " 2297 "valid during SELTO scb(%d, %d)\n", 2298 ahc_name(ahc), scbptr, scb_index); 2299 } else { 2300 u_int tag; 2301 2302 tag = SCB_LIST_NULL; 2303 if ((scb->hscb->control & TAG_ENB) != 0) 2304 tag = scb->hscb->tag; 2305 2306 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2307 SCB_LUN(scb), tag, 2308 ROLE_INITIATOR, XS_SELTIMEOUT); 2309 } 2310 /* Stop the selection */ 2311 ahc_outb(ahc, SCSISEQ, 0); 2312 2313 /* No more pending messages */ 2314 ahc_clear_msg_state(ahc); 2315 2316 /* 2317 * Although the driver does not care about the 2318 * 'Selection in Progress' status bit, the busy 2319 * LED does. SELINGO is only cleared by a sucessful 2320 * selection, so we must manually clear it to ensure 2321 * the LED turns off just incase no future successful 2322 * selections occur (e.g. no devices on the bus). 2323 */ 2324 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2325 2326 /* Clear interrupt state */ 2327 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2328 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2329 restart_sequencer(ahc); 2330 } else { 2331 scsipi_printaddr(scb->xs->xs_periph); 2332 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2333 ahc_outb(ahc, CLRSINT1, status); 2334 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2335 unpause_sequencer(ahc); 2336 } 2337 } 2338 2339 static void 2340 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2341 { 2342 /* 2343 * We need to initiate transfer negotiations. 2344 * If our current and goal settings are identical, 2345 * we want to renegotiate due to a check condition. 2346 */ 2347 struct ahc_initiator_tinfo *tinfo; 2348 struct tmode_tstate *tstate; 2349 int dowide; 2350 int dosync; 2351 2352 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2353 devinfo->target, &tstate); 2354 dowide = tinfo->current.width != tinfo->goal.width; 2355 dosync = tinfo->current.period != tinfo->goal.period; 2356 2357 if (!dowide && !dosync) { 2358 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2359 dosync = tinfo->goal.period != 0; 2360 } 2361 2362 if (dowide) { 2363 ahc_construct_wdtr(ahc, tinfo->goal.width); 2364 } else if (dosync) { 2365 const struct ahc_syncrate *rate; 2366 u_int period; 2367 u_int offset; 2368 2369 period = tinfo->goal.period; 2370 rate = ahc_devlimited_syncrate(ahc, &period); 2371 offset = tinfo->goal.offset; 2372 ahc_validate_offset(ahc, rate, &offset, 2373 tinfo->current.width); 2374 ahc_construct_sdtr(ahc, period, offset); 2375 } else { 2376 panic("ahc_intr: AWAITING_MSG for negotiation, " 2377 "but no negotiation needed\n"); 2378 } 2379 } 2380 2381 static void 2382 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2383 struct scb *scb) 2384 { 2385 /* 2386 * To facilitate adding multiple messages together, 2387 * each routine should increment the index and len 2388 * variables instead of setting them explicitly. 2389 */ 2390 ahc->msgout_index = 0; 2391 ahc->msgout_len = 0; 2392 2393 if ((scb->flags & SCB_DEVICE_RESET) == 0 2394 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2395 u_int identify_msg; 2396 2397 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2398 if ((scb->hscb->control & DISCENB) != 0) 2399 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2400 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2401 ahc->msgout_len++; 2402 2403 if ((scb->hscb->control & TAG_ENB) != 0) { 2404 ahc->msgout_buf[ahc->msgout_index++] = 2405 scb->xs->xs_tag_type; 2406 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2407 ahc->msgout_len += 2; 2408 } 2409 } 2410 2411 if (scb->flags & SCB_DEVICE_RESET) { 2412 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2413 ahc->msgout_len++; 2414 scsipi_printaddr(scb->xs->xs_periph); 2415 printf("Bus Device Reset Message Sent\n"); 2416 } else if (scb->flags & SCB_ABORT) { 2417 if ((scb->hscb->control & TAG_ENB) != 0) 2418 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2419 else 2420 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2421 ahc->msgout_len++; 2422 scsipi_printaddr(scb->xs->xs_periph); 2423 printf("Abort Message Sent\n"); 2424 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2425 ahc_build_transfer_msg(ahc, devinfo); 2426 } else { 2427 printf("ahc_intr: AWAITING_MSG for an SCB that " 2428 "does not have a waiting message"); 2429 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2430 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2431 ahc_inb(ahc, MSG_OUT), scb->flags); 2432 } 2433 2434 /* 2435 * Clear the MK_MESSAGE flag from the SCB so we aren't 2436 * asked to send this message again. 2437 */ 2438 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2439 ahc->msgout_index = 0; 2440 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2441 } 2442 2443 static void 2444 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2445 { 2446 /* 2447 * To facilitate adding multiple messages together, 2448 * each routine should increment the index and len 2449 * variables instead of setting them explicitly. 2450 */ 2451 ahc->msgout_index = 0; 2452 ahc->msgout_len = 0; 2453 2454 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2455 ahc_build_transfer_msg(ahc, devinfo); 2456 else 2457 panic("ahc_intr: AWAITING target message with no message"); 2458 2459 ahc->msgout_index = 0; 2460 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2461 } 2462 2463 static int 2464 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2465 { 2466 /* 2467 * What we care about here is if we had an 2468 * outstanding SDTR or WDTR message for this 2469 * target. If we did, this is a signal that 2470 * the target is refusing negotiation. 2471 */ 2472 struct scb *scb; 2473 u_int scb_index; 2474 u_int last_msg; 2475 int response = 0; 2476 2477 scb_index = ahc_inb(ahc, SCB_TAG); 2478 scb = &ahc->scb_data->scbarray[scb_index]; 2479 2480 /* Might be necessary */ 2481 last_msg = ahc_inb(ahc, LAST_MSG); 2482 2483 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2484 struct ahc_initiator_tinfo *tinfo; 2485 struct tmode_tstate *tstate; 2486 2487 #ifdef AHC_DEBUG_NEG 2488 /* note 8bit xfers */ 2489 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2490 "8bit transfers\n", ahc_name(ahc), 2491 devinfo->channel, devinfo->target); 2492 #endif 2493 ahc_set_width(ahc, devinfo, 2494 MSG_EXT_WDTR_BUS_8_BIT, 2495 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2496 /*paused*/TRUE, /*done*/TRUE); 2497 /* 2498 * No need to clear the sync rate. If the target 2499 * did not accept the command, our syncrate is 2500 * unaffected. If the target started the negotiation, 2501 * but rejected our response, we already cleared the 2502 * sync rate before sending our WDTR. 2503 */ 2504 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2505 devinfo->our_scsiid, 2506 devinfo->target, &tstate); 2507 if (tinfo->goal.period) { 2508 u_int period; 2509 2510 /* Start the sync negotiation */ 2511 period = tinfo->goal.period; 2512 ahc_devlimited_syncrate(ahc, &period); 2513 ahc->msgout_index = 0; 2514 ahc->msgout_len = 0; 2515 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2516 ahc->msgout_index = 0; 2517 response = 1; 2518 } else 2519 ahc_update_xfer_mode(ahc, devinfo); 2520 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2521 /* note asynch xfers and clear flag */ 2522 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2523 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2524 /*paused*/TRUE, /*done*/TRUE); 2525 #ifdef AHC_DEBUG_NEG 2526 printf("%s:%c:%d: refuses synchronous negotiation. " 2527 "Using asynchronous transfers\n", 2528 ahc_name(ahc), 2529 devinfo->channel, devinfo->target); 2530 #endif 2531 ahc_update_xfer_mode(ahc, devinfo); 2532 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2533 printf("%s:%c:%d: refuses tagged commands. Performing " 2534 "non-tagged I/O\n", ahc_name(ahc), 2535 devinfo->channel, devinfo->target); 2536 2537 ahc_set_tags(ahc, devinfo, FALSE); 2538 ahc_update_xfer_mode(ahc, devinfo); 2539 2540 /* 2541 * Resend the identify for this CCB as the target 2542 * may believe that the selection is invalid otherwise. 2543 */ 2544 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2545 & ~MSG_SIMPLE_Q_TAG); 2546 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2547 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2548 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2549 2550 /* 2551 * Requeue all tagged commands for this target 2552 * currently in our posession so they can be 2553 * converted to untagged commands. 2554 */ 2555 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2556 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2557 ROLE_INITIATOR, SCB_REQUEUE, 2558 SEARCH_COMPLETE); 2559 } else { 2560 /* 2561 * Otherwise, we ignore it. 2562 */ 2563 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2564 ahc_name(ahc), devinfo->channel, devinfo->target, 2565 last_msg); 2566 } 2567 return (response); 2568 } 2569 2570 static void 2571 ahc_clear_msg_state(struct ahc_softc *ahc) 2572 { 2573 ahc->msgout_len = 0; 2574 ahc->msgin_index = 0; 2575 ahc->msg_type = MSG_TYPE_NONE; 2576 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2577 } 2578 2579 static void 2580 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2581 { 2582 struct ahc_devinfo devinfo; 2583 u_int bus_phase; 2584 int end_session; 2585 2586 ahc_fetch_devinfo(ahc, &devinfo); 2587 end_session = FALSE; 2588 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2589 2590 reswitch: 2591 switch (ahc->msg_type) { 2592 case MSG_TYPE_INITIATOR_MSGOUT: 2593 { 2594 int lastbyte; 2595 int phasemis; 2596 int msgdone; 2597 2598 if (ahc->msgout_len == 0) 2599 panic("REQINIT interrupt with no active message"); 2600 2601 phasemis = bus_phase != P_MESGOUT; 2602 if (phasemis) { 2603 if (bus_phase == P_MESGIN) { 2604 /* 2605 * Change gears and see if 2606 * this messages is of interest to 2607 * us or should be passed back to 2608 * the sequencer. 2609 */ 2610 ahc_outb(ahc, CLRSINT1, CLRATNO); 2611 ahc->send_msg_perror = FALSE; 2612 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2613 ahc->msgin_index = 0; 2614 goto reswitch; 2615 } 2616 end_session = TRUE; 2617 break; 2618 } 2619 2620 if (ahc->send_msg_perror) { 2621 ahc_outb(ahc, CLRSINT1, CLRATNO); 2622 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2623 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2624 break; 2625 } 2626 2627 msgdone = ahc->msgout_index == ahc->msgout_len; 2628 if (msgdone) { 2629 /* 2630 * The target has requested a retry. 2631 * Re-assert ATN, reset our message index to 2632 * 0, and try again. 2633 */ 2634 ahc->msgout_index = 0; 2635 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2636 } 2637 2638 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2639 if (lastbyte) { 2640 /* Last byte is signified by dropping ATN */ 2641 ahc_outb(ahc, CLRSINT1, CLRATNO); 2642 } 2643 2644 /* 2645 * Clear our interrupt status and present 2646 * the next byte on the bus. 2647 */ 2648 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2649 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2650 break; 2651 } 2652 case MSG_TYPE_INITIATOR_MSGIN: 2653 { 2654 int phasemis; 2655 int message_done; 2656 2657 phasemis = bus_phase != P_MESGIN; 2658 2659 if (phasemis) { 2660 ahc->msgin_index = 0; 2661 if (bus_phase == P_MESGOUT 2662 && (ahc->send_msg_perror == TRUE 2663 || (ahc->msgout_len != 0 2664 && ahc->msgout_index == 0))) { 2665 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2666 goto reswitch; 2667 } 2668 end_session = TRUE; 2669 break; 2670 } 2671 2672 /* Pull the byte in without acking it */ 2673 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2674 2675 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2676 2677 if (message_done) { 2678 /* 2679 * Clear our incoming message buffer in case there 2680 * is another message following this one. 2681 */ 2682 ahc->msgin_index = 0; 2683 2684 /* 2685 * If this message illicited a response, 2686 * assert ATN so the target takes us to the 2687 * message out phase. 2688 */ 2689 if (ahc->msgout_len != 0) 2690 ahc_outb(ahc, SCSISIGO, 2691 ahc_inb(ahc, SCSISIGO) | ATNO); 2692 } else 2693 ahc->msgin_index++; 2694 2695 /* Ack the byte */ 2696 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2697 ahc_inb(ahc, SCSIDATL); 2698 break; 2699 } 2700 case MSG_TYPE_TARGET_MSGIN: 2701 { 2702 int msgdone; 2703 int msgout_request; 2704 2705 if (ahc->msgout_len == 0) 2706 panic("Target MSGIN with no active message"); 2707 2708 /* 2709 * If we interrupted a mesgout session, the initiator 2710 * will not know this until our first REQ. So, we 2711 * only honor mesgout requests after we've sent our 2712 * first byte. 2713 */ 2714 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2715 && ahc->msgout_index > 0) 2716 msgout_request = TRUE; 2717 else 2718 msgout_request = FALSE; 2719 2720 if (msgout_request) { 2721 2722 /* 2723 * Change gears and see if 2724 * this messages is of interest to 2725 * us or should be passed back to 2726 * the sequencer. 2727 */ 2728 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2729 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2730 ahc->msgin_index = 0; 2731 /* Dummy read to REQ for first byte */ 2732 ahc_inb(ahc, SCSIDATL); 2733 ahc_outb(ahc, SXFRCTL0, 2734 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2735 break; 2736 } 2737 2738 msgdone = ahc->msgout_index == ahc->msgout_len; 2739 if (msgdone) { 2740 ahc_outb(ahc, SXFRCTL0, 2741 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2742 end_session = TRUE; 2743 break; 2744 } 2745 2746 /* 2747 * Present the next byte on the bus. 2748 */ 2749 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2750 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2751 break; 2752 } 2753 case MSG_TYPE_TARGET_MSGOUT: 2754 { 2755 int lastbyte; 2756 int msgdone; 2757 2758 /* 2759 * The initiator signals that this is 2760 * the last byte by dropping ATN. 2761 */ 2762 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2763 2764 /* 2765 * Read the latched byte, but turn off SPIOEN first 2766 * so that we don't inadvertantly cause a REQ for the 2767 * next byte. 2768 */ 2769 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2770 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2771 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2772 if (msgdone == MSGLOOP_TERMINATED) { 2773 /* 2774 * The message is *really* done in that it caused 2775 * us to go to bus free. The sequencer has already 2776 * been reset at this point, so pull the ejection 2777 * handle. 2778 */ 2779 return; 2780 } 2781 2782 ahc->msgin_index++; 2783 2784 /* 2785 * XXX Read spec about initiator dropping ATN too soon 2786 * and use msgdone to detect it. 2787 */ 2788 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2789 ahc->msgin_index = 0; 2790 2791 /* 2792 * If this message illicited a response, transition 2793 * to the Message in phase and send it. 2794 */ 2795 if (ahc->msgout_len != 0) { 2796 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2797 ahc_outb(ahc, SXFRCTL0, 2798 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2799 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2800 ahc->msgin_index = 0; 2801 break; 2802 } 2803 } 2804 2805 if (lastbyte) 2806 end_session = TRUE; 2807 else { 2808 /* Ask for the next byte. */ 2809 ahc_outb(ahc, SXFRCTL0, 2810 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2811 } 2812 2813 break; 2814 } 2815 default: 2816 panic("Unknown REQINIT message type"); 2817 } 2818 2819 if (end_session) { 2820 ahc_clear_msg_state(ahc); 2821 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2822 } else 2823 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2824 } 2825 2826 /* 2827 * See if we sent a particular extended message to the target. 2828 * If "full" is true, the target saw the full message. 2829 * If "full" is false, the target saw at least the first 2830 * byte of the message. 2831 */ 2832 static int 2833 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2834 { 2835 int found; 2836 int index; 2837 2838 found = FALSE; 2839 index = 0; 2840 2841 while (index < ahc->msgout_len) { 2842 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2843 2844 /* Found a candidate */ 2845 if (ahc->msgout_buf[index+2] == msgtype) { 2846 u_int end_index; 2847 2848 end_index = index + 1 2849 + ahc->msgout_buf[index + 1]; 2850 if (full) { 2851 if (ahc->msgout_index > end_index) 2852 found = TRUE; 2853 } else if (ahc->msgout_index > index) 2854 found = TRUE; 2855 } 2856 break; 2857 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2858 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2859 2860 /* Skip tag type and tag id or residue param*/ 2861 index += 2; 2862 } else { 2863 /* Single byte message */ 2864 index++; 2865 } 2866 } 2867 return (found); 2868 } 2869 2870 static int 2871 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2872 struct ahc_devinfo *devinfo) 2873 { 2874 struct ahc_initiator_tinfo *tinfo; 2875 struct tmode_tstate *tstate; 2876 int reject; 2877 int done; 2878 int response; 2879 u_int targ_scsirate; 2880 2881 done = MSGLOOP_IN_PROG; 2882 response = FALSE; 2883 reject = FALSE; 2884 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2885 devinfo->target, &tstate); 2886 targ_scsirate = tinfo->scsirate; 2887 2888 /* 2889 * Parse as much of the message as is availible, 2890 * rejecting it if we don't support it. When 2891 * the entire message is availible and has been 2892 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2893 * that we have parsed an entire message. 2894 * 2895 * In the case of extended messages, we accept the length 2896 * byte outright and perform more checking once we know the 2897 * extended message type. 2898 */ 2899 switch (ahc->msgin_buf[0]) { 2900 case MSG_MESSAGE_REJECT: 2901 response = ahc_handle_msg_reject(ahc, devinfo); 2902 /* FALLTHROUGH */ 2903 case MSG_NOOP: 2904 done = MSGLOOP_MSGCOMPLETE; 2905 break; 2906 case MSG_IGN_WIDE_RESIDUE: 2907 { 2908 /* Wait for the whole message */ 2909 if (ahc->msgin_index >= 1) { 2910 if (ahc->msgin_buf[1] != 1 2911 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2912 reject = TRUE; 2913 done = MSGLOOP_MSGCOMPLETE; 2914 } else 2915 ahc_handle_ign_wide_residue(ahc, devinfo); 2916 } 2917 break; 2918 } 2919 case MSG_EXTENDED: 2920 { 2921 /* Wait for enough of the message to begin validation */ 2922 if (ahc->msgin_index < 2) 2923 break; 2924 switch (ahc->msgin_buf[2]) { 2925 case MSG_EXT_SDTR: 2926 { 2927 const struct ahc_syncrate *syncrate; 2928 u_int period; 2929 u_int offset; 2930 u_int saved_offset; 2931 2932 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2933 reject = TRUE; 2934 break; 2935 } 2936 2937 /* 2938 * Wait until we have both args before validating 2939 * and acting on this message. 2940 * 2941 * Add one to MSG_EXT_SDTR_LEN to account for 2942 * the extended message preamble. 2943 */ 2944 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2945 break; 2946 2947 period = ahc->msgin_buf[3]; 2948 saved_offset = offset = ahc->msgin_buf[4]; 2949 syncrate = ahc_devlimited_syncrate(ahc, &period); 2950 ahc_validate_offset(ahc, syncrate, &offset, 2951 targ_scsirate & WIDEXFER); 2952 ahc_set_syncrate(ahc, devinfo, 2953 syncrate, period, offset, 2954 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2955 /*paused*/TRUE, /*done*/TRUE); 2956 ahc_update_xfer_mode(ahc, devinfo); 2957 2958 /* 2959 * See if we initiated Sync Negotiation 2960 * and didn't have to fall down to async 2961 * transfers. 2962 */ 2963 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2964 /* We started it */ 2965 if (saved_offset != offset) { 2966 /* Went too low - force async */ 2967 reject = TRUE; 2968 } 2969 } else { 2970 /* 2971 * Send our own SDTR in reply 2972 */ 2973 ahc->msgout_index = 0; 2974 ahc->msgout_len = 0; 2975 ahc_construct_sdtr(ahc, period, offset); 2976 ahc->msgout_index = 0; 2977 response = TRUE; 2978 } 2979 done = MSGLOOP_MSGCOMPLETE; 2980 break; 2981 } 2982 case MSG_EXT_WDTR: 2983 { 2984 u_int bus_width; 2985 u_int sending_reply; 2986 2987 sending_reply = FALSE; 2988 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2989 reject = TRUE; 2990 break; 2991 } 2992 2993 /* 2994 * Wait until we have our arg before validating 2995 * and acting on this message. 2996 * 2997 * Add one to MSG_EXT_WDTR_LEN to account for 2998 * the extended message preamble. 2999 */ 3000 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3001 break; 3002 3003 bus_width = ahc->msgin_buf[3]; 3004 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3005 /* 3006 * Don't send a WDTR back to the 3007 * target, since we asked first. 3008 */ 3009 switch (bus_width){ 3010 default: 3011 /* 3012 * How can we do anything greater 3013 * than 16bit transfers on a 16bit 3014 * bus? 3015 */ 3016 reject = TRUE; 3017 printf("%s: target %d requested %dBit " 3018 "transfers. Rejecting...\n", 3019 ahc_name(ahc), devinfo->target, 3020 8 * (0x01 << bus_width)); 3021 /* FALLTHROUGH */ 3022 case MSG_EXT_WDTR_BUS_8_BIT: 3023 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3024 break; 3025 case MSG_EXT_WDTR_BUS_16_BIT: 3026 break; 3027 } 3028 } else { 3029 /* 3030 * Send our own WDTR in reply 3031 */ 3032 switch (bus_width) { 3033 default: 3034 if (ahc->features & AHC_WIDE) { 3035 /* Respond Wide */ 3036 bus_width = 3037 MSG_EXT_WDTR_BUS_16_BIT; 3038 break; 3039 } 3040 /* FALLTHROUGH */ 3041 case MSG_EXT_WDTR_BUS_8_BIT: 3042 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3043 break; 3044 } 3045 ahc->msgout_index = 0; 3046 ahc->msgout_len = 0; 3047 ahc_construct_wdtr(ahc, bus_width); 3048 ahc->msgout_index = 0; 3049 response = TRUE; 3050 sending_reply = TRUE; 3051 } 3052 ahc_set_width(ahc, devinfo, bus_width, 3053 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3054 /*paused*/TRUE, /*done*/TRUE); 3055 3056 /* After a wide message, we are async */ 3057 ahc_set_syncrate(ahc, devinfo, 3058 /*syncrate*/NULL, /*period*/0, 3059 /*offset*/0, AHC_TRANS_ACTIVE, 3060 /*paused*/TRUE, /*done*/FALSE); 3061 if (sending_reply == FALSE && reject == FALSE) { 3062 3063 if (tinfo->goal.period) { 3064 const struct ahc_syncrate *rate; 3065 u_int period; 3066 u_int offset; 3067 3068 /* Start the sync negotiation */ 3069 period = tinfo->goal.period; 3070 rate = ahc_devlimited_syncrate(ahc, 3071 &period); 3072 offset = tinfo->goal.offset; 3073 ahc_validate_offset(ahc, rate, &offset, 3074 tinfo->current.width); 3075 ahc->msgout_index = 0; 3076 ahc->msgout_len = 0; 3077 ahc_construct_sdtr(ahc, period, offset); 3078 ahc->msgout_index = 0; 3079 response = TRUE; 3080 } else 3081 ahc_update_xfer_mode(ahc, devinfo); 3082 } 3083 done = MSGLOOP_MSGCOMPLETE; 3084 break; 3085 } 3086 default: 3087 /* Unknown extended message. Reject it. */ 3088 reject = TRUE; 3089 break; 3090 } 3091 break; 3092 } 3093 case MSG_BUS_DEV_RESET: 3094 ahc_handle_devreset(ahc, devinfo, 3095 XS_RESET, "Bus Device Reset Received", 3096 /*verbose_level*/0); 3097 restart_sequencer(ahc); 3098 done = MSGLOOP_TERMINATED; 3099 break; 3100 case MSG_ABORT_TAG: 3101 case MSG_ABORT: 3102 case MSG_CLEAR_QUEUE: 3103 /* Target mode messages */ 3104 if (devinfo->role != ROLE_TARGET) { 3105 reject = TRUE; 3106 break; 3107 } 3108 #if AHC_TARGET_MODE 3109 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3110 devinfo->lun, 3111 ahc->msgin_buf[0] == MSG_ABORT_TAG 3112 ? SCB_LIST_NULL 3113 : ahc_inb(ahc, INITIATOR_TAG), 3114 ROLE_TARGET, XS_DRIVER_STUFFUP); 3115 3116 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3117 if (tstate != NULL) { 3118 struct tmode_lstate* lstate; 3119 3120 lstate = tstate->enabled_luns[devinfo->lun]; 3121 if (lstate != NULL) { 3122 ahc_queue_lstate_event(ahc, lstate, 3123 devinfo->our_scsiid, 3124 ahc->msgin_buf[0], 3125 /*arg*/0); 3126 ahc_send_lstate_events(ahc, lstate); 3127 } 3128 } 3129 done = MSGLOOP_MSGCOMPLETE; 3130 #else 3131 panic("ahc: got target mode message"); 3132 #endif 3133 break; 3134 case MSG_TERM_IO_PROC: 3135 default: 3136 reject = TRUE; 3137 break; 3138 } 3139 3140 if (reject) { 3141 /* 3142 * Setup to reject the message. 3143 */ 3144 ahc->msgout_index = 0; 3145 ahc->msgout_len = 1; 3146 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3147 done = MSGLOOP_MSGCOMPLETE; 3148 response = TRUE; 3149 } 3150 3151 if (done != MSGLOOP_IN_PROG && !response) 3152 /* Clear the outgoing message buffer */ 3153 ahc->msgout_len = 0; 3154 3155 return (done); 3156 } 3157 3158 static void 3159 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3160 { 3161 u_int scb_index; 3162 struct scb *scb; 3163 3164 scb_index = ahc_inb(ahc, SCB_TAG); 3165 scb = &ahc->scb_data->scbarray[scb_index]; 3166 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3167 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3168 /* 3169 * Ignore the message if we haven't 3170 * seen an appropriate data phase yet. 3171 */ 3172 } else { 3173 /* 3174 * If the residual occurred on the last 3175 * transfer and the transfer request was 3176 * expected to end on an odd count, do 3177 * nothing. Otherwise, subtract a byte 3178 * and update the residual count accordingly. 3179 */ 3180 u_int resid_sgcnt; 3181 3182 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3183 if (resid_sgcnt == 0 3184 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3185 /* 3186 * If the residual occurred on the last 3187 * transfer and the transfer request was 3188 * expected to end on an odd count, do 3189 * nothing. 3190 */ 3191 } else { 3192 u_int data_cnt; 3193 u_int32_t data_addr; 3194 u_int sg_index; 3195 3196 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3197 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3198 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3199 3200 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3201 | (ahc_inb(ahc, SHADDR + 2) << 16) 3202 | (ahc_inb(ahc, SHADDR + 1) << 8) 3203 | (ahc_inb(ahc, SHADDR)); 3204 3205 data_cnt += 1; 3206 data_addr -= 1; 3207 3208 sg_index = scb->sg_count - resid_sgcnt; 3209 3210 if (sg_index != 0 3211 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3212 u_int32_t sg_addr; 3213 3214 sg_index--; 3215 data_cnt = 1; 3216 data_addr = le32toh(scb->sg_list[sg_index].addr) 3217 + le32toh(scb->sg_list[sg_index].len) 3218 - 1; 3219 3220 /* 3221 * The physical address base points to the 3222 * second entry as it is always used for 3223 * calculating the "next S/G pointer". 3224 */ 3225 sg_addr = scb->sg_list_phys 3226 + (sg_index* sizeof(*scb->sg_list)); 3227 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3228 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3229 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3230 ahc_outb(ahc, SG_NEXT, sg_addr); 3231 } 3232 3233 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3234 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3235 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3236 3237 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3238 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3239 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3240 ahc_outb(ahc, SHADDR, data_addr); 3241 } 3242 } 3243 } 3244 3245 static void 3246 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3247 int status, char *message, 3248 int verbose_level) 3249 { 3250 int found; 3251 3252 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3253 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3254 status); 3255 3256 /* 3257 * Go back to async/narrow transfers and renegotiate. 3258 * ahc_set_width and ahc_set_syncrate can cope with NULL 3259 * paths. 3260 */ 3261 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3262 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3263 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3264 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3265 /*paused*/TRUE, /*done*/FALSE); 3266 ahc_update_xfer_mode(ahc, devinfo); 3267 3268 if (message != NULL && (verbose_level <= 0)) 3269 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3270 message, devinfo->channel, devinfo->target, found); 3271 } 3272 3273 /* 3274 * We have an scb which has been processed by the 3275 * adaptor, now we look to see how the operation 3276 * went. 3277 */ 3278 static void 3279 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3280 { 3281 struct scsipi_xfer *xs; 3282 struct scsipi_periph *periph; 3283 int requeue = 0; 3284 int target; 3285 3286 3287 xs = scb->xs; 3288 periph = xs->xs_periph; 3289 LIST_REMOVE(scb, plinks); 3290 3291 callout_stop(&scb->xs->xs_callout); 3292 3293 #ifdef AHC_DEBUG 3294 if (ahc_debug & AHC_SHOWCMDS) { 3295 scsipi_printaddr(periph); 3296 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3297 scb->hscb->tag); 3298 } 3299 #endif 3300 3301 target = periph->periph_target; 3302 3303 if (xs->datalen) { 3304 int op; 3305 3306 if (xs->xs_control & XS_CTL_DATA_IN) 3307 op = BUS_DMASYNC_POSTREAD; 3308 else 3309 op = BUS_DMASYNC_POSTWRITE; 3310 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3311 scb->dmamap->dm_mapsize, op); 3312 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3313 } 3314 3315 /* 3316 * Unbusy this target/channel/lun. 3317 * XXX if we are holding two commands per lun, 3318 * send the next command. 3319 */ 3320 if (!(scb->hscb->control & TAG_ENB)) 3321 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3322 3323 /* 3324 * If the recovery SCB completes, we have to be 3325 * out of our timeout. 3326 */ 3327 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3328 3329 struct scb *scbp; 3330 3331 /* 3332 * We were able to complete the command successfully, 3333 * so reinstate the timeouts for all other pending 3334 * commands. 3335 */ 3336 scbp = ahc->pending_ccbs.lh_first; 3337 while (scbp != NULL) { 3338 struct scsipi_xfer *txs = scbp->xs; 3339 3340 if (!(txs->xs_control & XS_CTL_POLL)) { 3341 callout_reset(&scbp->xs->xs_callout, 3342 (scbp->xs->timeout * hz) / 1000, 3343 ahc_timeout, scbp); 3344 } 3345 scbp = LIST_NEXT(scbp, plinks); 3346 } 3347 3348 /* 3349 * Ensure that we didn't put a second instance of this 3350 * SCB into the QINFIFO. 3351 */ 3352 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3353 SCB_LUN(scb), scb->hscb->tag, 3354 ROLE_INITIATOR, /*status*/0, 3355 SEARCH_REMOVE); 3356 if (xs->error != XS_NOERROR) 3357 ahcsetccbstatus(xs, XS_TIMEOUT); 3358 scsipi_printaddr(xs->xs_periph); 3359 printf("no longer in timeout, status = %x\n", xs->status); 3360 } 3361 3362 if (xs->error != XS_NOERROR) { 3363 /* Don't clobber any existing error state */ 3364 } else if ((scb->flags & SCB_SENSE) != 0) { 3365 /* 3366 * We performed autosense retrieval. 3367 * 3368 * bzero the sense data before having 3369 * the drive fill it. The SCSI spec mandates 3370 * that any untransfered data should be 3371 * assumed to be zero. Complete the 'bounce' 3372 * of sense information through buffers accessible 3373 * via bus-space by copying it into the clients 3374 * csio. 3375 */ 3376 bzero(&xs->sense.scsi_sense, sizeof(xs->sense.scsi_sense)); 3377 bcopy(&ahc->scb_data->sense[scb->hscb->tag], 3378 &xs->sense.scsi_sense, le32toh(scb->sg_list->len)); 3379 xs->error = XS_SENSE; 3380 } 3381 if (scb->flags & SCB_FREEZE_QUEUE) { 3382 scsipi_periph_thaw(periph, 1); 3383 scb->flags &= ~SCB_FREEZE_QUEUE; 3384 } 3385 3386 requeue = scb->flags & SCB_REQUEUE; 3387 ahcfreescb(ahc, scb); 3388 3389 if (requeue) { 3390 xs->error = XS_REQUEUE; 3391 } 3392 scsipi_done(xs); 3393 } 3394 3395 /* 3396 * Determine the number of SCBs available on the controller 3397 */ 3398 int 3399 ahc_probe_scbs(struct ahc_softc *ahc) { 3400 int i; 3401 3402 for (i = 0; i < AHC_SCB_MAX; i++) { 3403 ahc_outb(ahc, SCBPTR, i); 3404 ahc_outb(ahc, SCB_CONTROL, i); 3405 if (ahc_inb(ahc, SCB_CONTROL) != i) 3406 break; 3407 ahc_outb(ahc, SCBPTR, 0); 3408 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3409 break; 3410 } 3411 return (i); 3412 } 3413 3414 /* 3415 * Start the board, ready for normal operation 3416 */ 3417 int 3418 ahc_init(struct ahc_softc *ahc) 3419 { 3420 int max_targ = 15; 3421 int i; 3422 int term; 3423 u_int scsi_conf; 3424 u_int scsiseq_template; 3425 u_int ultraenb; 3426 u_int discenable; 3427 u_int tagenable; 3428 size_t driver_data_size; 3429 u_int32_t physaddr; 3430 3431 #ifdef AHC_PRINT_SRAM 3432 printf("Scratch Ram:"); 3433 for (i = 0x20; i < 0x5f; i++) { 3434 if (((i % 8) == 0) && (i != 0)) { 3435 printf ("\n "); 3436 } 3437 printf (" 0x%x", ahc_inb(ahc, i)); 3438 } 3439 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3440 for (i = 0x70; i < 0x7f; i++) { 3441 if (((i % 8) == 0) && (i != 0)) { 3442 printf ("\n "); 3443 } 3444 printf (" 0x%x", ahc_inb(ahc, i)); 3445 } 3446 } 3447 printf ("\n"); 3448 #endif 3449 3450 /* 3451 * Assume we have a board at this stage and it has been reset. 3452 */ 3453 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3454 ahc->our_id = ahc->our_id_b = 7; 3455 3456 /* 3457 * Default to allowing initiator operations. 3458 */ 3459 ahc->flags |= AHC_INITIATORMODE; 3460 3461 /* 3462 * DMA tag for our command fifos and other data in system memory 3463 * the card's sequencer must be able to access. For initiator 3464 * roles, we need to allocate space for the qinfifo, qoutfifo, 3465 * and untagged_scb arrays each of which are composed of 256 3466 * 1 byte elements. When providing for the target mode role, 3467 * we additionally must provide space for the incoming target 3468 * command fifo. 3469 */ 3470 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3471 3472 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3473 ahc->sc_dmaflags, 3474 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3475 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3476 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3477 return (ENOMEM); 3478 3479 ahc->init_level++; 3480 3481 /* Allocate SCB data now that parent_dmat is initialized */ 3482 if (ahc->scb_data->maxhscbs == 0) 3483 if (ahcinitscbdata(ahc) != 0) 3484 return (ENOMEM); 3485 3486 ahc->qinfifo = &ahc->qoutfifo[256]; 3487 ahc->untagged_scbs = &ahc->qinfifo[256]; 3488 /* There are no untagged SCBs active yet. */ 3489 for (i = 0; i < 256; i++) 3490 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3491 3492 /* All of our queues are empty */ 3493 for (i = 0; i < 256; i++) 3494 ahc->qoutfifo[i] = SCB_LIST_NULL; 3495 3496 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3497 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3498 3499 /* 3500 * Allocate a tstate to house information for our 3501 * initiator presence on the bus as well as the user 3502 * data for any target mode initiator. 3503 */ 3504 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3505 printf("%s: unable to allocate tmode_tstate. " 3506 "Failing attach\n", ahc_name(ahc)); 3507 return (-1); 3508 } 3509 3510 if ((ahc->features & AHC_TWIN) != 0) { 3511 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3512 printf("%s: unable to allocate tmode_tstate. " 3513 "Failing attach\n", ahc_name(ahc)); 3514 return (-1); 3515 } 3516 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3517 ahc->our_id, ahc->our_id_b, 3518 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3519 } else { 3520 if ((ahc->features & AHC_WIDE) != 0) { 3521 printf("Wide "); 3522 } else { 3523 printf("Single "); 3524 } 3525 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3526 } 3527 3528 ahc_outb(ahc, SEQ_FLAGS, 0); 3529 3530 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3531 ahc->flags |= AHC_PAGESCBS; 3532 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3533 } else { 3534 ahc->flags &= ~AHC_PAGESCBS; 3535 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3536 } 3537 3538 #ifdef AHC_DEBUG 3539 if (ahc_debug & AHC_SHOWMISC) { 3540 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 3541 "ahc_dma %d bytes\n", 3542 ahc_name(ahc), 3543 sizeof(struct hardware_scb), 3544 sizeof(struct scb), 3545 sizeof(struct ahc_dma_seg)); 3546 } 3547 #endif /* AHC_DEBUG */ 3548 3549 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3550 if (ahc->features & AHC_TWIN) { 3551 3552 /* 3553 * The device is gated to channel B after a chip reset, 3554 * so set those values first 3555 */ 3556 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3557 if ((ahc->features & AHC_ULTRA2) != 0) 3558 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3559 else 3560 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3561 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3562 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3563 |term|ENSTIMER|ACTNEGEN); 3564 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3565 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3566 3567 if ((scsi_conf & RESET_SCSI) != 0 3568 && (ahc->flags & AHC_INITIATORMODE) != 0) 3569 ahc->flags |= AHC_RESET_BUS_B; 3570 3571 /* Select Channel A */ 3572 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3573 } 3574 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3575 if ((ahc->features & AHC_ULTRA2) != 0) 3576 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3577 else 3578 ahc_outb(ahc, SCSIID, ahc->our_id); 3579 scsi_conf = ahc_inb(ahc, SCSICONF); 3580 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3581 |term 3582 |ENSTIMER|ACTNEGEN); 3583 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3584 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3585 3586 if ((scsi_conf & RESET_SCSI) != 0 3587 && (ahc->flags & AHC_INITIATORMODE) != 0) 3588 ahc->flags |= AHC_RESET_BUS_A; 3589 3590 /* 3591 * Look at the information that board initialization or 3592 * the board bios has left us. 3593 */ 3594 ultraenb = 0; 3595 tagenable = ALL_TARGETS_MASK; 3596 3597 /* Grab the disconnection disable table and invert it for our needs */ 3598 if (ahc->flags & AHC_USEDEFAULTS) { 3599 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3600 "device parameters\n", ahc_name(ahc)); 3601 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3602 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3603 discenable = ALL_TARGETS_MASK; 3604 if ((ahc->features & AHC_ULTRA) != 0) 3605 ultraenb = ALL_TARGETS_MASK; 3606 } else { 3607 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3608 | ahc_inb(ahc, DISC_DSB)); 3609 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3610 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3611 | ahc_inb(ahc, ULTRA_ENB); 3612 } 3613 3614 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3615 max_targ = 7; 3616 3617 for (i = 0; i <= max_targ; i++) { 3618 struct ahc_initiator_tinfo *tinfo; 3619 struct tmode_tstate *tstate; 3620 u_int our_id; 3621 u_int target_id; 3622 char channel; 3623 3624 channel = 'A'; 3625 our_id = ahc->our_id; 3626 target_id = i; 3627 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3628 channel = 'B'; 3629 our_id = ahc->our_id_b; 3630 target_id = i % 8; 3631 } 3632 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3633 target_id, &tstate); 3634 /* Default to async narrow across the board */ 3635 bzero(tinfo, sizeof(*tinfo)); 3636 if (ahc->flags & AHC_USEDEFAULTS) { 3637 if ((ahc->features & AHC_WIDE) != 0) 3638 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3639 3640 /* 3641 * These will be truncated when we determine the 3642 * connection type we have with the target. 3643 */ 3644 tinfo->user.period = ahc_syncrates->period; 3645 tinfo->user.offset = ~0; 3646 } else { 3647 u_int scsirate; 3648 u_int16_t mask; 3649 3650 /* Take the settings leftover in scratch RAM. */ 3651 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3652 mask = (0x01 << i); 3653 if ((ahc->features & AHC_ULTRA2) != 0) { 3654 u_int offset; 3655 u_int maxsync; 3656 3657 if ((scsirate & SOFS) == 0x0F) { 3658 /* 3659 * Haven't negotiated yet, 3660 * so the format is different. 3661 */ 3662 scsirate = (scsirate & SXFR) >> 4 3663 | (ultraenb & mask) 3664 ? 0x08 : 0x0 3665 | (scsirate & WIDEXFER); 3666 offset = MAX_OFFSET_ULTRA2; 3667 } else 3668 offset = ahc_inb(ahc, TARG_OFFSET + i); 3669 maxsync = AHC_SYNCRATE_ULTRA2; 3670 if ((ahc->features & AHC_DT) != 0) 3671 maxsync = AHC_SYNCRATE_DT; 3672 tinfo->user.period = 3673 ahc_find_period(ahc, scsirate, maxsync); 3674 if (offset == 0) 3675 tinfo->user.period = 0; 3676 else 3677 tinfo->user.offset = ~0; 3678 } else if ((scsirate & SOFS) != 0) { 3679 tinfo->user.period = 3680 ahc_find_period(ahc, scsirate, 3681 (ultraenb & mask) 3682 ? AHC_SYNCRATE_ULTRA 3683 : AHC_SYNCRATE_FAST); 3684 if (tinfo->user.period != 0) 3685 tinfo->user.offset = ~0; 3686 } 3687 if ((scsirate & WIDEXFER) != 0 3688 && (ahc->features & AHC_WIDE) != 0) 3689 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3690 } 3691 tinfo->goal = tinfo->user; /* force negotiation */ 3692 tstate->ultraenb = ultraenb; 3693 tstate->discenable = discenable; 3694 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3695 tstate->tagdisable = 0; 3696 } 3697 ahc->user_discenable = discenable; 3698 ahc->user_tagenable = tagenable; 3699 3700 /* 3701 * Tell the sequencer where it can find our arrays in memory. 3702 */ 3703 physaddr = ahc->scb_data->hscb_busaddr; 3704 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3705 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3706 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3707 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3708 3709 physaddr = ahc->shared_data_busaddr; 3710 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3711 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3712 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3713 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3714 3715 /* Target mode incomding command fifo */ 3716 physaddr += 3 * 256 * sizeof(u_int8_t); 3717 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3718 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3719 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3720 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3721 3722 /* 3723 * Initialize the group code to command length table. 3724 * This overrides the values in TARG_SCSIRATE, so only 3725 * setup the table after we have processed that information. 3726 */ 3727 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3728 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3729 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3730 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3731 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3732 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3733 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3734 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3735 3736 /* Tell the sequencer of our initial queue positions */ 3737 ahc_outb(ahc, KERNEL_QINPOS, 0); 3738 ahc_outb(ahc, QINPOS, 0); 3739 ahc_outb(ahc, QOUTPOS, 0); 3740 3741 #ifdef AHC_DEBUG 3742 if (ahc_debug & AHC_SHOWMISC) 3743 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3744 discenable, ultraenb); 3745 #endif 3746 3747 /* Don't have any special messages to send to targets */ 3748 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3749 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3750 3751 /* 3752 * Use the built in queue management registers 3753 * if they are available. 3754 */ 3755 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3756 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3757 ahc_outb(ahc, SDSCB_QOFF, 0); 3758 ahc_outb(ahc, SNSCB_QOFF, 0); 3759 ahc_outb(ahc, HNSCB_QOFF, 0); 3760 } 3761 3762 3763 /* We don't have any waiting selections */ 3764 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3765 3766 /* Our disconnection list is empty too */ 3767 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3768 3769 /* Message out buffer starts empty */ 3770 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3771 3772 /* 3773 * Setup the allowed SCSI Sequences based on operational mode. 3774 * If we are a target, we'll enable select in operations once 3775 * we've had a lun enabled. 3776 */ 3777 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3778 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3779 scsiseq_template |= ENRSELI; 3780 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3781 3782 /* 3783 * Load the Sequencer program and Enable the adapter 3784 * in "fast" mode. 3785 */ 3786 #ifdef AHC_DEBUG 3787 printf("%s: Downloading Sequencer Program...", 3788 ahc_name(ahc)); 3789 #endif 3790 3791 ahc_loadseq(ahc); 3792 3793 /* We have to wait until after any system dumps... */ 3794 shutdownhook_establish(ahc_shutdown, ahc); 3795 3796 return (0); 3797 } 3798 3799 static int 3800 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3801 struct proc *p) 3802 { 3803 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3804 int s, ret = ENOTTY; 3805 3806 switch (cmd) { 3807 case SCBUSIORESET: 3808 s = splbio(); 3809 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3810 TRUE); 3811 splx(s); 3812 ret = 0; 3813 break; 3814 default: 3815 break; 3816 } 3817 3818 return ret; 3819 } 3820 3821 3822 /* 3823 * XXX fvdl the busy_tcl checks and settings should only be done 3824 * for the non-tagged queueing case, but we don't do tagged queueing 3825 * yet, so.. 3826 */ 3827 static void 3828 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3829 { 3830 struct scsipi_xfer *xs; 3831 struct scsipi_periph *periph; 3832 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3833 struct scb *scb; 3834 struct hardware_scb *hscb; 3835 struct ahc_initiator_tinfo *tinfo; 3836 struct tmode_tstate *tstate; 3837 u_int target_id; 3838 u_int our_id; 3839 int s, tcl; 3840 u_int16_t mask; 3841 char channel; 3842 3843 switch (req) { 3844 case ADAPTER_REQ_RUN_XFER: 3845 xs = arg; 3846 periph = xs->xs_periph; 3847 3848 SC_DEBUG(xs->xs_periph, SDEV_DB3, ("ahc_action\n")); 3849 3850 /* must protect the queue */ 3851 s = splbio(); 3852 3853 tcl = XS_TCL(ahc, xs); 3854 3855 if (!ahc_istagged_device(ahc, xs, 0) && 3856 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3857 panic("ahc_action: not tagged and device busy"); 3858 } 3859 3860 3861 target_id = periph->periph_target; 3862 our_id = SIM_SCSI_ID(ahc, periph); 3863 3864 /* 3865 * get an scb to use. 3866 */ 3867 if ((scb = ahcgetscb(ahc)) == NULL) { 3868 xs->error = XS_RESOURCE_SHORTAGE; 3869 scsipi_done(xs); 3870 splx(s); 3871 return; 3872 } 3873 3874 tcl = XS_TCL(ahc, xs); 3875 3876 #ifdef DIAGNOSTIC 3877 if (!ahc_istagged_device(ahc, xs, 0) && 3878 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3879 panic("ahc: queuing for busy target"); 3880 #endif 3881 3882 scb->xs = xs; 3883 hscb = scb->hscb; 3884 hscb->tcl = tcl; 3885 3886 if (xs->xs_tag_type) { 3887 #ifdef DIAGNOSTIC 3888 if (ahc_istagged_device(ahc, xs, 0) == 0) 3889 panic("ahc_action: taggged command for untagged device"); 3890 #endif 3891 scb->hscb->control |= TAG_ENB; 3892 } else 3893 ahc_busy_tcl(ahc, scb); 3894 3895 splx(s); 3896 3897 channel = SIM_CHANNEL(ahc, periph); 3898 if (ahc->inited_channels[channel - 'A'] == 0) { 3899 if ((channel == 'A' && 3900 (ahc->flags & AHC_RESET_BUS_A)) || 3901 (channel == 'B' && 3902 (ahc->flags & AHC_RESET_BUS_B))) { 3903 s = splbio(); 3904 ahc_reset_channel(ahc, channel, TRUE); 3905 splx(s); 3906 } 3907 ahc->inited_channels[channel - 'A'] = 1; 3908 } 3909 3910 /* 3911 * Put all the arguments for the xfer in the scb 3912 */ 3913 3914 mask = SCB_TARGET_MASK(scb); 3915 tinfo = ahc_fetch_transinfo(ahc, 3916 SIM_CHANNEL(ahc, periph), 3917 our_id, target_id, &tstate); 3918 if (ahc->inited_targets[target_id] == 0) { 3919 struct ahc_devinfo devinfo; 3920 s = splbio(); 3921 ahc_compile_devinfo(&devinfo, our_id, target_id, 3922 periph->periph_lun, 3923 SIM_CHANNEL(ahc, periph), 3924 ROLE_INITIATOR); 3925 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3926 TRUE, FALSE); 3927 ahc->inited_targets[target_id] = 1; 3928 splx(s); 3929 } 3930 hscb->scsirate = tinfo->scsirate; 3931 hscb->scsioffset = tinfo->current.offset; 3932 if ((tstate->ultraenb & mask) != 0) 3933 hscb->control |= ULTRAENB; 3934 3935 if ((tstate->discenable & mask) != 0) 3936 hscb->control |= DISCENB; 3937 3938 if (xs->xs_control & XS_CTL_RESET) { 3939 hscb->cmdpointer = 0; 3940 scb->flags |= SCB_DEVICE_RESET; 3941 hscb->control |= MK_MESSAGE; 3942 ahc_execute_scb(scb, NULL, 0); 3943 } 3944 3945 ahc_setup_data(ahc, xs, scb); 3946 return; 3947 case ADAPTER_REQ_GROW_RESOURCES: 3948 /* XXX not supported */ 3949 return; 3950 case ADAPTER_REQ_SET_XFER_MODE: 3951 { 3952 struct scsipi_xfer_mode *xm = arg; 3953 struct ahc_devinfo devinfo; 3954 int target_id, our_id; 3955 char channel; 3956 3957 target_id = xm->xm_target; 3958 our_id = chan->chan_id; 3959 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 3960 s = splbio(); 3961 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 3962 &tstate); 3963 ahc_compile_devinfo(&devinfo, our_id, target_id, 3964 0, channel, ROLE_INITIATOR); 3965 ahc->inited_targets[target_id] = 2; 3966 if (xm->xm_mode & PERIPH_CAP_TQING && 3967 (tstate->tagdisable & devinfo.target_mask) == 0) { 3968 ahc_set_tags(ahc, &devinfo, TRUE); 3969 } 3970 splx(s); 3971 ahc_update_xfer_mode(ahc, &devinfo); 3972 } 3973 } 3974 } 3975 3976 static void 3977 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 3978 { 3979 struct scb *scb; 3980 struct scsipi_xfer *xs; 3981 struct ahc_softc *ahc; 3982 int s; 3983 3984 scb = (struct scb *)arg; 3985 xs = scb->xs; 3986 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 3987 3988 3989 if (nsegments != 0) { 3990 struct ahc_dma_seg *sg; 3991 bus_dma_segment_t *end_seg; 3992 int op; 3993 3994 end_seg = dm_segs + nsegments; 3995 3996 /* Copy the first SG into the data pointer area */ 3997 scb->hscb->data = dm_segs->ds_addr; 3998 scb->hscb->datalen = dm_segs->ds_len; 3999 4000 /* Copy the segments into our SG list */ 4001 sg = scb->sg_list; 4002 while (dm_segs < end_seg) { 4003 sg->addr = dm_segs->ds_addr; 4004 sg->len = dm_segs->ds_len; 4005 ahc_swap_sg(sg); 4006 sg++; 4007 dm_segs++; 4008 } 4009 4010 /* Note where to find the SG entries in bus space */ 4011 scb->hscb->SG_pointer = scb->sg_list_phys; 4012 4013 if (xs->xs_control & XS_CTL_DATA_IN) 4014 op = BUS_DMASYNC_PREREAD; 4015 else 4016 op = BUS_DMASYNC_PREWRITE; 4017 4018 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4019 scb->dmamap->dm_mapsize, op); 4020 4021 } else { 4022 scb->hscb->SG_pointer = 0; 4023 scb->hscb->data = 0; 4024 scb->hscb->datalen = 0; 4025 } 4026 4027 scb->sg_count = scb->hscb->SG_count = nsegments; 4028 4029 s = splbio(); 4030 4031 /* 4032 * Last time we need to check if this SCB needs to 4033 * be aborted. 4034 */ 4035 if (xs->xs_status & XS_STS_DONE) { 4036 if (!ahc_istagged_device(ahc, xs, 0)) 4037 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4038 if (nsegments != 0) 4039 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4040 ahcfreescb(ahc, scb); 4041 splx(s); 4042 return; 4043 } 4044 4045 #ifdef DIAGNOSTIC 4046 if (scb->sg_count > 255) 4047 panic("ahc bad sg_count"); 4048 #endif 4049 4050 ahc_swap_hscb(scb->hscb); 4051 4052 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4053 4054 scb->flags |= SCB_ACTIVE; 4055 4056 if (!(xs->xs_control & XS_CTL_POLL)) 4057 callout_reset(&scb->xs->xs_callout, (xs->timeout * hz) / 1000, 4058 ahc_timeout, scb); 4059 4060 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4061 #if 0 4062 printf("Continueing Immediate Command %d:%d\n", 4063 xs->xs_periph->periph_target, 4064 xs->xs_periph->periph_lun); 4065 #endif 4066 pause_sequencer(ahc); 4067 if ((ahc->flags & AHC_PAGESCBS) == 0) 4068 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4069 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4070 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4071 unpause_sequencer(ahc); 4072 } else { 4073 4074 #if 0 4075 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4076 scb->hscb->tag, ahc->qinfifonext, 4077 &ahc->qinfifo[ahc->qinfifonext], 4078 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4079 #endif 4080 4081 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4082 4083 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4084 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4085 4086 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4087 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4088 } else { 4089 pause_sequencer(ahc); 4090 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4091 unpause_sequencer(ahc); 4092 } 4093 } 4094 4095 #ifdef AHC_DEBUG 4096 if (ahc_debug & AHC_SHOWCMDS) { 4097 scsi_print_addr(xs->xs_periph); 4098 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4099 " rate %x\n", 4100 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4101 scb->flags, scb->hscb->control, ahc->qinfifonext, 4102 scb->hscb->scsirate); 4103 } 4104 #endif 4105 4106 if (!(xs->xs_control & XS_CTL_POLL)) { 4107 splx(s); 4108 return; 4109 } 4110 /* 4111 * If we can't use interrupts, poll for completion 4112 */ 4113 SC_DEBUG(xs->xs_periph, SDEV_DB3, ("cmd_poll\n")); 4114 do { 4115 if (ahc_poll(ahc, xs->timeout)) { 4116 if (!(xs->xs_control & XS_CTL_SILENT)) 4117 printf("cmd fail\n"); 4118 ahc_timeout(scb); 4119 break; 4120 } 4121 } while (!(xs->xs_status & XS_STS_DONE)); 4122 splx(s); 4123 return; 4124 } 4125 4126 static int 4127 ahc_poll(struct ahc_softc *ahc, int wait) 4128 { 4129 while (--wait) { 4130 DELAY(1000); 4131 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4132 break; 4133 } 4134 4135 if (wait == 0) { 4136 printf("%s: board is not responding\n", ahc_name(ahc)); 4137 return (EIO); 4138 } 4139 4140 ahc_intr((void *)ahc); 4141 return (0); 4142 } 4143 4144 static void 4145 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4146 struct scb *scb) 4147 { 4148 struct hardware_scb *hscb; 4149 4150 hscb = scb->hscb; 4151 xs->resid = xs->status = 0; 4152 4153 hscb->cmdlen = xs->cmdlen; 4154 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4155 hscb->cmdpointer = hscb->cmdstore_busaddr; 4156 4157 /* Only use S/G if there is a transfer */ 4158 if (xs->datalen) { 4159 int error; 4160 4161 error = bus_dmamap_load(ahc->parent_dmat, 4162 scb->dmamap, xs->data, 4163 xs->datalen, NULL, 4164 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4165 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4166 BUS_DMA_STREAMING); 4167 if (error) { 4168 if (!ahc_istagged_device(ahc, xs, 0)) 4169 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4170 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4171 scsipi_done(xs); 4172 return; 4173 } 4174 ahc_execute_scb(scb, 4175 scb->dmamap->dm_segs, 4176 scb->dmamap->dm_nsegs); 4177 } else { 4178 ahc_execute_scb(scb, NULL, 0); 4179 } 4180 } 4181 4182 static void 4183 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4184 { 4185 int target; 4186 char channel; 4187 int lun; 4188 4189 target = periph->periph_target; 4190 lun = periph->periph_lun; 4191 channel = periph->periph_channel->chan_channel; 4192 4193 ahc_search_qinfifo(ahc, target, channel, lun, 4194 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4195 SCB_REQUEUE, SEARCH_COMPLETE); 4196 } 4197 4198 static void 4199 ahcallocscbs(struct ahc_softc *ahc) 4200 { 4201 struct scb_data *scb_data; 4202 struct scb *next_scb; 4203 struct sg_map_node *sg_map; 4204 bus_addr_t physaddr; 4205 struct ahc_dma_seg *segs; 4206 int newcount; 4207 int i; 4208 4209 scb_data = ahc->scb_data; 4210 if (scb_data->numscbs >= AHC_SCB_MAX) 4211 /* Can't allocate any more */ 4212 return; 4213 4214 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4215 4216 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4217 4218 if (sg_map == NULL) 4219 return; 4220 4221 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4222 &sg_map->sg_dmamap, 4223 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4224 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4225 "SG space") < 0) { 4226 free(sg_map, M_DEVBUF); 4227 return; 4228 } 4229 4230 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4231 4232 segs = sg_map->sg_vaddr; 4233 physaddr = sg_map->sg_physaddr; 4234 4235 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4236 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4237 int error; 4238 4239 next_scb->sg_list = segs; 4240 /* 4241 * The sequencer always starts with the second entry. 4242 * The first entry is embedded in the scb. 4243 */ 4244 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4245 next_scb->flags = SCB_FREE; 4246 error = bus_dmamap_create(ahc->parent_dmat, 4247 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4248 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4249 &next_scb->dmamap); 4250 if (error != 0) 4251 break; 4252 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4253 next_scb->hscb->tag = ahc->scb_data->numscbs; 4254 next_scb->hscb->cmdstore_busaddr = 4255 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4256 + offsetof(struct hardware_scb, cmdstore); 4257 next_scb->hscb->cmdstore_busaddr = 4258 htole32(next_scb->hscb->cmdstore_busaddr); 4259 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4260 segs += AHC_NSEG; 4261 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4262 next_scb++; 4263 ahc->scb_data->numscbs++; 4264 } 4265 #ifdef AHC_DEBUG 4266 if (ahc_debug & AHC_SHOWSCBALLOC) 4267 printf("%s: allocated %d new SCBs count now %d\n", 4268 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4269 #endif 4270 } 4271 4272 #ifdef AHC_DUMP_SEQ 4273 static void 4274 ahc_dumpseq(struct ahc_softc* ahc) 4275 { 4276 int i; 4277 int max_prog; 4278 4279 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4280 max_prog = 448; 4281 else if ((ahc->features & AHC_ULTRA2) != 0) 4282 max_prog = 768; 4283 else 4284 max_prog = 512; 4285 4286 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4287 ahc_outb(ahc, SEQADDR0, 0); 4288 ahc_outb(ahc, SEQADDR1, 0); 4289 for (i = 0; i < max_prog; i++) { 4290 u_int8_t ins_bytes[4]; 4291 4292 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4293 printf("0x%08x\n", ins_bytes[0] << 24 4294 | ins_bytes[1] << 16 4295 | ins_bytes[2] << 8 4296 | ins_bytes[3]); 4297 } 4298 } 4299 #endif 4300 4301 static void 4302 ahc_loadseq(struct ahc_softc *ahc) 4303 { 4304 const struct patch *cur_patch; 4305 int i; 4306 int downloaded; 4307 int skip_addr; 4308 u_int8_t download_consts[4]; 4309 4310 /* Setup downloadable constant table */ 4311 #if 0 4312 /* No downloaded constants are currently defined. */ 4313 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4314 #endif 4315 4316 cur_patch = patches; 4317 downloaded = 0; 4318 skip_addr = 0; 4319 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4320 ahc_outb(ahc, SEQADDR0, 0); 4321 ahc_outb(ahc, SEQADDR1, 0); 4322 4323 for (i = 0; i < sizeof(seqprog)/4; i++) { 4324 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4325 /* 4326 * Don't download this instruction as it 4327 * is in a patch that was removed. 4328 */ 4329 continue; 4330 } 4331 ahc_download_instr(ahc, i, download_consts); 4332 downloaded++; 4333 } 4334 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4335 restart_sequencer(ahc); 4336 4337 #ifdef AHC_DEBUG 4338 printf(" %d instructions downloaded\n", downloaded); 4339 #endif 4340 } 4341 4342 static int 4343 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4344 int start_instr, int *skip_addr) 4345 { 4346 const struct patch *cur_patch; 4347 const struct patch *last_patch; 4348 int num_patches; 4349 4350 num_patches = sizeof(patches)/sizeof(struct patch); 4351 last_patch = &patches[num_patches]; 4352 cur_patch = *start_patch; 4353 4354 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4355 4356 if (cur_patch->patch_func(ahc) == 0) { 4357 4358 /* Start rejecting code */ 4359 *skip_addr = start_instr + cur_patch->skip_instr; 4360 cur_patch += cur_patch->skip_patch; 4361 } else { 4362 /* Accepted this patch. Advance to the next 4363 * one and wait for our intruction pointer to 4364 * hit this point. 4365 */ 4366 cur_patch++; 4367 } 4368 } 4369 4370 *start_patch = cur_patch; 4371 if (start_instr < *skip_addr) 4372 /* Still skipping */ 4373 return (0); 4374 4375 return (1); 4376 } 4377 4378 static void 4379 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4380 { 4381 union ins_formats instr; 4382 struct ins_format1 *fmt1_ins; 4383 struct ins_format3 *fmt3_ins; 4384 u_int opcode; 4385 4386 /* Structure copy */ 4387 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4388 4389 instr.integer = le32toh(instr.integer); 4390 4391 fmt1_ins = &instr.format1; 4392 fmt3_ins = NULL; 4393 4394 /* Pull the opcode */ 4395 opcode = instr.format1.opcode; 4396 switch (opcode) { 4397 case AIC_OP_JMP: 4398 case AIC_OP_JC: 4399 case AIC_OP_JNC: 4400 case AIC_OP_CALL: 4401 case AIC_OP_JNE: 4402 case AIC_OP_JNZ: 4403 case AIC_OP_JE: 4404 case AIC_OP_JZ: 4405 { 4406 const struct patch *cur_patch; 4407 int address_offset; 4408 u_int address; 4409 int skip_addr; 4410 int i; 4411 4412 fmt3_ins = &instr.format3; 4413 address_offset = 0; 4414 address = fmt3_ins->address; 4415 cur_patch = patches; 4416 skip_addr = 0; 4417 4418 for (i = 0; i < address;) { 4419 4420 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4421 4422 if (skip_addr > i) { 4423 int end_addr; 4424 4425 end_addr = MIN(address, skip_addr); 4426 address_offset += end_addr - i; 4427 i = skip_addr; 4428 } else { 4429 i++; 4430 } 4431 } 4432 address -= address_offset; 4433 fmt3_ins->address = address; 4434 /* FALLTHROUGH */ 4435 } 4436 case AIC_OP_OR: 4437 case AIC_OP_AND: 4438 case AIC_OP_XOR: 4439 case AIC_OP_ADD: 4440 case AIC_OP_ADC: 4441 case AIC_OP_BMOV: 4442 if (fmt1_ins->parity != 0) { 4443 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4444 } 4445 fmt1_ins->parity = 0; 4446 /* FALLTHROUGH */ 4447 case AIC_OP_ROL: 4448 if ((ahc->features & AHC_ULTRA2) != 0) { 4449 int i, count; 4450 4451 /* Calculate odd parity for the instruction */ 4452 for (i = 0, count = 0; i < 31; i++) { 4453 u_int32_t mask; 4454 4455 mask = 0x01 << i; 4456 if ((instr.integer & mask) != 0) 4457 count++; 4458 } 4459 if ((count & 0x01) == 0) 4460 instr.format1.parity = 1; 4461 } else { 4462 /* Compress the instruction for older sequencers */ 4463 if (fmt3_ins != NULL) { 4464 instr.integer = 4465 fmt3_ins->immediate 4466 | (fmt3_ins->source << 8) 4467 | (fmt3_ins->address << 16) 4468 | (fmt3_ins->opcode << 25); 4469 } else { 4470 instr.integer = 4471 fmt1_ins->immediate 4472 | (fmt1_ins->source << 8) 4473 | (fmt1_ins->destination << 16) 4474 | (fmt1_ins->ret << 24) 4475 | (fmt1_ins->opcode << 25); 4476 } 4477 } 4478 instr.integer = htole32(instr.integer); 4479 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4480 break; 4481 default: 4482 panic("Unknown opcode encountered in seq program"); 4483 break; 4484 } 4485 } 4486 4487 static void 4488 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4489 { 4490 4491 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4492 struct scb *scbp; 4493 4494 scb->flags |= SCB_RECOVERY_SCB; 4495 4496 /* 4497 * Take all queued, but not sent SCBs out of the equation. 4498 * Also ensure that no new CCBs are queued to us while we 4499 * try to fix this problem. 4500 */ 4501 scsipi_channel_freeze(&ahc->sc_channel, 1); 4502 if (ahc->features & AHC_TWIN) 4503 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4504 4505 /* 4506 * Go through all of our pending SCBs and remove 4507 * any scheduled timeouts for them. We will reschedule 4508 * them after we've successfully fixed this problem. 4509 */ 4510 scbp = ahc->pending_ccbs.lh_first; 4511 while (scbp != NULL) { 4512 callout_stop(&scbp->xs->xs_callout); 4513 scbp = scbp->plinks.le_next; 4514 } 4515 } 4516 } 4517 4518 static void 4519 ahc_timeout(void *arg) 4520 { 4521 struct scb *scb; 4522 struct ahc_softc *ahc; 4523 int s, found; 4524 u_int last_phase; 4525 int target; 4526 int lun; 4527 int i; 4528 char channel; 4529 4530 scb = (struct scb *)arg; 4531 ahc = 4532 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4533 4534 s = splbio(); 4535 4536 /* 4537 * Ensure that the card doesn't do anything 4538 * behind our back. Also make sure that we 4539 * didn't "just" miss an interrupt that would 4540 * affect this timeout. 4541 */ 4542 do { 4543 ahc_intr(ahc); 4544 pause_sequencer(ahc); 4545 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4546 4547 if ((scb->flags & SCB_ACTIVE) == 0) { 4548 /* Previous timeout took care of me already */ 4549 printf("Timedout SCB handled by another timeout\n"); 4550 unpause_sequencer(ahc); 4551 splx(s); 4552 return; 4553 } 4554 4555 target = SCB_TARGET(scb); 4556 channel = SCB_CHANNEL(scb); 4557 lun = SCB_LUN(scb); 4558 4559 scsipi_printaddr(scb->xs->xs_periph); 4560 printf("SCB %x - timed out ", scb->hscb->tag); 4561 /* 4562 * Take a snapshot of the bus state and print out 4563 * some information so we can track down driver bugs. 4564 */ 4565 last_phase = ahc_inb(ahc, LASTPHASE); 4566 4567 for (i = 0; i < num_phases; i++) { 4568 if (last_phase == phase_table[i].phase) 4569 break; 4570 } 4571 printf("%s", phase_table[i].phasemsg); 4572 4573 printf(", SEQADDR == 0x%x\n", 4574 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4575 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4576 4577 #ifdef AHC_DEBUG 4578 ahc_print_scb(scb); 4579 #endif 4580 4581 #if 0 4582 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4583 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4584 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4585 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4586 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4587 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4588 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4589 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4590 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4591 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4592 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4593 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4594 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4595 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4596 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4597 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4598 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4599 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4600 if (scb->sg_count > 0) { 4601 for (i = 0; i < scb->sg_count; i++) { 4602 printf("sg[%d] - Addr 0x%x : Length %d\n", 4603 i, 4604 le32toh(scb->sg_list[i].addr), 4605 le32toh(scb->sg_list[i].len)); 4606 } 4607 } 4608 #endif 4609 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4610 /* 4611 * Been down this road before. 4612 * Do a full bus reset. 4613 */ 4614 bus_reset: 4615 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4616 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4617 printf("%s: Issued Channel %c Bus Reset. " 4618 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4619 } else { 4620 /* 4621 * If we are a target, transition to bus free and report 4622 * the timeout. 4623 * 4624 * The target/initiator that is holding up the bus may not 4625 * be the same as the one that triggered this timeout 4626 * (different commands have different timeout lengths). 4627 * If the bus is idle and we are actiing as the initiator 4628 * for this request, queue a BDR message to the timed out 4629 * target. Otherwise, if the timed out transaction is 4630 * active: 4631 * Initiator transaction: 4632 * Stuff the message buffer with a BDR message and assert 4633 * ATN in the hopes that the target will let go of the bus 4634 * and go to the mesgout phase. If this fails, we'll 4635 * get another timeout 2 seconds later which will attempt 4636 * a bus reset. 4637 * 4638 * Target transaction: 4639 * Transition to BUS FREE and report the error. 4640 * It's good to be the target! 4641 */ 4642 u_int active_scb_index; 4643 4644 active_scb_index = ahc_inb(ahc, SCB_TAG); 4645 4646 if (last_phase != P_BUSFREE 4647 && (active_scb_index < ahc->scb_data->numscbs)) { 4648 struct scb *active_scb; 4649 4650 /* 4651 * If the active SCB is not from our device, 4652 * assume that another device is hogging the bus 4653 * and wait for it's timeout to expire before 4654 * taking additional action. 4655 */ 4656 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4657 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4658 u_int newtimeout; 4659 4660 scsipi_printaddr(scb->xs->xs_periph); 4661 printf("Other SCB Timeout%s", 4662 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4663 ? " again\n" : "\n"); 4664 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4665 newtimeout = MAX(active_scb->xs->timeout, 4666 scb->xs->timeout); 4667 callout_reset(&scb->xs->xs_callout, 4668 (newtimeout * hz) / 1000, 4669 ahc_timeout, scb); 4670 splx(s); 4671 return; 4672 } 4673 4674 /* It's us */ 4675 if ((scb->hscb->control & TARGET_SCB) != 0) { 4676 4677 /* 4678 * Send back any queued up transactions 4679 * and properly record the error condition. 4680 */ 4681 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4682 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4683 ahc_freeze_ccb(scb); 4684 ahc_done(ahc, scb); 4685 4686 /* Will clear us from the bus */ 4687 restart_sequencer(ahc); 4688 splx(s); 4689 return; 4690 } 4691 4692 ahc_set_recoveryscb(ahc, active_scb); 4693 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4694 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4695 scsipi_printaddr(active_scb->xs->xs_periph); 4696 printf("BDR message in message buffer\n"); 4697 active_scb->flags |= SCB_DEVICE_RESET; 4698 callout_reset(&active_scb->xs->xs_callout, 4699 2 * hz, ahc_timeout, active_scb); 4700 unpause_sequencer(ahc); 4701 } else { 4702 int disconnected; 4703 4704 /* XXX Shouldn't panic. Just punt instead */ 4705 if ((scb->hscb->control & TARGET_SCB) != 0) 4706 panic("Timed-out target SCB but bus idle"); 4707 4708 if (last_phase != P_BUSFREE 4709 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4710 /* XXX What happened to the SCB? */ 4711 /* Hung target selection. Goto busfree */ 4712 printf("%s: Hung target selection\n", 4713 ahc_name(ahc)); 4714 restart_sequencer(ahc); 4715 splx(s); 4716 return; 4717 } 4718 4719 if (ahc_search_qinfifo(ahc, target, channel, lun, 4720 scb->hscb->tag, ROLE_INITIATOR, 4721 /*status*/0, SEARCH_COUNT) > 0) { 4722 disconnected = FALSE; 4723 } else { 4724 disconnected = TRUE; 4725 } 4726 4727 if (disconnected) { 4728 u_int active_scb; 4729 4730 ahc_set_recoveryscb(ahc, scb); 4731 /* 4732 * Simply set the MK_MESSAGE control bit. 4733 */ 4734 scb->hscb->control |= MK_MESSAGE; 4735 scb->flags |= SCB_QUEUED_MSG 4736 | SCB_DEVICE_RESET; 4737 4738 /* 4739 * Mark the cached copy of this SCB in the 4740 * disconnected list too, so that a reconnect 4741 * at this point causes a BDR or abort. 4742 */ 4743 active_scb = ahc_inb(ahc, SCBPTR); 4744 if (ahc_search_disc_list(ahc, target, 4745 channel, lun, 4746 scb->hscb->tag, 4747 /*stop_on_first*/TRUE, 4748 /*remove*/FALSE, 4749 /*save_state*/FALSE)) { 4750 u_int scb_control; 4751 4752 scb_control = ahc_inb(ahc, SCB_CONTROL); 4753 scb_control |= MK_MESSAGE; 4754 ahc_outb(ahc, SCB_CONTROL, scb_control); 4755 } 4756 ahc_outb(ahc, SCBPTR, active_scb); 4757 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4758 /*unbusy*/TRUE); 4759 4760 /* 4761 * Actually re-queue this SCB in case we can 4762 * select the device before it reconnects. 4763 * Clear out any entries in the QINFIFO first 4764 * so we are the next SCB for this target 4765 * to run. 4766 */ 4767 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4768 channel, SCB_LUN(scb), 4769 SCB_LIST_NULL, 4770 ROLE_INITIATOR, 4771 SCB_REQUEUE, 4772 SEARCH_COMPLETE); 4773 scsipi_printaddr(scb->xs->xs_periph); 4774 printf("Queuing a BDR SCB\n"); 4775 ahc->qinfifo[ahc->qinfifonext++] = 4776 scb->hscb->tag; 4777 4778 bus_dmamap_sync(ahc->parent_dmat, 4779 ahc->shared_data_dmamap, 4780 QINFIFO_OFFSET * 256, 256, 4781 BUS_DMASYNC_PREWRITE); 4782 4783 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4784 ahc_outb(ahc, HNSCB_QOFF, 4785 ahc->qinfifonext); 4786 } else { 4787 ahc_outb(ahc, KERNEL_QINPOS, 4788 ahc->qinfifonext); 4789 } 4790 callout_reset(&scb->xs->xs_callout, 2 * hz, 4791 ahc_timeout, scb); 4792 unpause_sequencer(ahc); 4793 } else { 4794 /* Go "immediatly" to the bus reset */ 4795 /* This shouldn't happen */ 4796 ahc_set_recoveryscb(ahc, scb); 4797 scsipi_printaddr(scb->xs->xs_periph); 4798 printf("SCB %x: Immediate reset. " 4799 "Flags = 0x%x\n", scb->hscb->tag, 4800 scb->flags); 4801 goto bus_reset; 4802 } 4803 } 4804 } 4805 splx(s); 4806 } 4807 4808 static int 4809 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4810 int lun, u_int tag, role_t role, scb_flag status, 4811 ahc_search_action action) 4812 { 4813 struct scb *scbp; 4814 u_int8_t qinpos; 4815 u_int8_t qintail; 4816 int found; 4817 4818 qinpos = ahc_inb(ahc, QINPOS); 4819 qintail = ahc->qinfifonext; 4820 found = 0; 4821 4822 /* 4823 * Start with an empty queue. Entries that are not chosen 4824 * for removal will be re-added to the queue as we go. 4825 */ 4826 ahc->qinfifonext = qinpos; 4827 4828 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4829 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4830 4831 while (qinpos != qintail) { 4832 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4833 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4834 /* 4835 * We found an scb that needs to be removed. 4836 */ 4837 switch (action) { 4838 case SEARCH_COMPLETE: 4839 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4840 scbp->flags |= status; 4841 scbp->xs->error = XS_NOERROR; 4842 } 4843 ahc_freeze_ccb(scbp); 4844 ahc_done(ahc, scbp); 4845 break; 4846 case SEARCH_COUNT: 4847 ahc->qinfifo[ahc->qinfifonext++] = 4848 scbp->hscb->tag; 4849 break; 4850 case SEARCH_REMOVE: 4851 break; 4852 } 4853 found++; 4854 } else { 4855 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4856 } 4857 qinpos++; 4858 } 4859 4860 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4861 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4862 4863 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4864 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4865 } else { 4866 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4867 } 4868 4869 return (found); 4870 } 4871 4872 /* 4873 * Abort all SCBs that match the given description (target/channel/lun/tag), 4874 * setting their status to the passed in status if the status has not already 4875 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4876 * is paused before it is called. 4877 */ 4878 static int 4879 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4880 int lun, u_int tag, role_t role, int status) 4881 { 4882 struct scb *scbp; 4883 u_int active_scb; 4884 int i; 4885 int found; 4886 4887 /* restore this when we're done */ 4888 active_scb = ahc_inb(ahc, SCBPTR); 4889 4890 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4891 role, SCB_REQUEUE, SEARCH_COMPLETE); 4892 4893 /* 4894 * Search waiting for selection list. 4895 */ 4896 { 4897 u_int8_t next, prev; 4898 4899 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4900 prev = SCB_LIST_NULL; 4901 4902 while (next != SCB_LIST_NULL) { 4903 u_int8_t scb_index; 4904 4905 ahc_outb(ahc, SCBPTR, next); 4906 scb_index = ahc_inb(ahc, SCB_TAG); 4907 if (scb_index >= ahc->scb_data->numscbs) { 4908 panic("Waiting List inconsistency. " 4909 "SCB index == %d, yet numscbs == %d.", 4910 scb_index, ahc->scb_data->numscbs); 4911 } 4912 scbp = &ahc->scb_data->scbarray[scb_index]; 4913 if (ahc_match_scb(scbp, target, channel, 4914 lun, SCB_LIST_NULL, role)) { 4915 4916 next = ahc_abort_wscb(ahc, next, prev); 4917 } else { 4918 4919 prev = next; 4920 next = ahc_inb(ahc, SCB_NEXT); 4921 } 4922 } 4923 } 4924 /* 4925 * Go through the disconnected list and remove any entries we 4926 * have queued for completion, 0'ing their control byte too. 4927 * We save the active SCB and restore it ourselves, so there 4928 * is no reason for this search to restore it too. 4929 */ 4930 ahc_search_disc_list(ahc, target, channel, lun, tag, 4931 /*stop_on_first*/FALSE, /*remove*/TRUE, 4932 /*save_state*/FALSE); 4933 4934 /* 4935 * Go through the hardware SCB array looking for commands that 4936 * were active but not on any list. 4937 */ 4938 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4939 u_int scbid; 4940 4941 ahc_outb(ahc, SCBPTR, i); 4942 scbid = ahc_inb(ahc, SCB_TAG); 4943 scbp = &ahc->scb_data->scbarray[scbid]; 4944 if (scbid < ahc->scb_data->numscbs 4945 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4946 ahc_add_curscb_to_free_list(ahc); 4947 } 4948 4949 /* 4950 * Go through the pending CCB list and look for 4951 * commands for this target that are still active. 4952 * These are other tagged commands that were 4953 * disconnected when the reset occured. 4954 */ 4955 { 4956 struct scb *scb; 4957 4958 scb = ahc->pending_ccbs.lh_first; 4959 while (scb != NULL) { 4960 scbp = scb; 4961 scb = scb->plinks.le_next; 4962 if (ahc_match_scb(scbp, target, channel, 4963 lun, tag, role)) { 4964 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4965 ahcsetccbstatus(scbp->xs, status); 4966 ahc_freeze_ccb(scbp); 4967 ahc_done(ahc, scbp); 4968 found++; 4969 } 4970 } 4971 } 4972 ahc_outb(ahc, SCBPTR, active_scb); 4973 return found; 4974 } 4975 4976 static int 4977 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 4978 int lun, u_int tag, int stop_on_first, int remove, 4979 int save_state) 4980 { 4981 struct scb *scbp; 4982 u_int next; 4983 u_int prev; 4984 u_int count; 4985 u_int active_scb; 4986 4987 count = 0; 4988 next = ahc_inb(ahc, DISCONNECTED_SCBH); 4989 prev = SCB_LIST_NULL; 4990 4991 if (save_state) { 4992 /* restore this when we're done */ 4993 active_scb = ahc_inb(ahc, SCBPTR); 4994 } else 4995 /* Silence compiler */ 4996 active_scb = SCB_LIST_NULL; 4997 4998 while (next != SCB_LIST_NULL) { 4999 u_int scb_index; 5000 5001 ahc_outb(ahc, SCBPTR, next); 5002 scb_index = ahc_inb(ahc, SCB_TAG); 5003 if (scb_index >= ahc->scb_data->numscbs) { 5004 panic("Disconnected List inconsistency. " 5005 "SCB index == %d, yet numscbs == %d.", 5006 scb_index, ahc->scb_data->numscbs); 5007 } 5008 scbp = &ahc->scb_data->scbarray[scb_index]; 5009 if (ahc_match_scb(scbp, target, channel, lun, 5010 tag, ROLE_INITIATOR)) { 5011 count++; 5012 if (remove) { 5013 next = 5014 ahc_rem_scb_from_disc_list(ahc, prev, next); 5015 } else { 5016 prev = next; 5017 next = ahc_inb(ahc, SCB_NEXT); 5018 } 5019 if (stop_on_first) 5020 break; 5021 } else { 5022 prev = next; 5023 next = ahc_inb(ahc, SCB_NEXT); 5024 } 5025 } 5026 if (save_state) 5027 ahc_outb(ahc, SCBPTR, active_scb); 5028 return (count); 5029 } 5030 5031 static u_int 5032 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5033 { 5034 u_int next; 5035 5036 ahc_outb(ahc, SCBPTR, scbptr); 5037 next = ahc_inb(ahc, SCB_NEXT); 5038 5039 ahc_outb(ahc, SCB_CONTROL, 0); 5040 5041 ahc_add_curscb_to_free_list(ahc); 5042 5043 if (prev != SCB_LIST_NULL) { 5044 ahc_outb(ahc, SCBPTR, prev); 5045 ahc_outb(ahc, SCB_NEXT, next); 5046 } else 5047 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5048 5049 return (next); 5050 } 5051 5052 static void 5053 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5054 { 5055 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5056 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5057 5058 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5059 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5060 } 5061 5062 /* 5063 * Manipulate the waiting for selection list and return the 5064 * scb that follows the one that we remove. 5065 */ 5066 static u_int 5067 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5068 { 5069 u_int curscb, next; 5070 5071 /* 5072 * Select the SCB we want to abort and 5073 * pull the next pointer out of it. 5074 */ 5075 curscb = ahc_inb(ahc, SCBPTR); 5076 ahc_outb(ahc, SCBPTR, scbpos); 5077 next = ahc_inb(ahc, SCB_NEXT); 5078 5079 /* Clear the necessary fields */ 5080 ahc_outb(ahc, SCB_CONTROL, 0); 5081 5082 ahc_add_curscb_to_free_list(ahc); 5083 5084 /* update the waiting list */ 5085 if (prev == SCB_LIST_NULL) { 5086 /* First in the list */ 5087 ahc_outb(ahc, WAITING_SCBH, next); 5088 5089 /* 5090 * Ensure we aren't attempting to perform 5091 * selection for this entry. 5092 */ 5093 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5094 } else { 5095 /* 5096 * Select the scb that pointed to us 5097 * and update its next pointer. 5098 */ 5099 ahc_outb(ahc, SCBPTR, prev); 5100 ahc_outb(ahc, SCB_NEXT, next); 5101 } 5102 5103 /* 5104 * Point us back at the original scb position. 5105 */ 5106 ahc_outb(ahc, SCBPTR, curscb); 5107 return next; 5108 } 5109 5110 static void 5111 ahc_clear_intstat(struct ahc_softc *ahc) 5112 { 5113 /* Clear any interrupt conditions this may have caused */ 5114 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5115 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5116 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5117 CLRREQINIT); 5118 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5119 } 5120 5121 static void 5122 ahc_reset_current_bus(struct ahc_softc *ahc) 5123 { 5124 u_int8_t scsiseq; 5125 5126 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5127 scsiseq = ahc_inb(ahc, SCSISEQ); 5128 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5129 DELAY(AHC_BUSRESET_DELAY); 5130 /* Turn off the bus reset */ 5131 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5132 5133 ahc_clear_intstat(ahc); 5134 5135 /* Re-enable reset interrupts */ 5136 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5137 } 5138 5139 static int 5140 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5141 { 5142 u_int initiator, target, max_scsiid; 5143 u_int sblkctl; 5144 u_int our_id; 5145 int found; 5146 int restart_needed; 5147 char cur_channel; 5148 5149 ahc->pending_device = NULL; 5150 5151 pause_sequencer(ahc); 5152 5153 /* 5154 * Run our command complete fifos to ensure that we perform 5155 * completion processing on any commands that 'completed' 5156 * before the reset occurred. 5157 */ 5158 ahc_run_qoutfifo(ahc); 5159 5160 /* 5161 * Reset the bus if we are initiating this reset 5162 */ 5163 sblkctl = ahc_inb(ahc, SBLKCTL); 5164 cur_channel = 'A'; 5165 if ((ahc->features & AHC_TWIN) != 0 5166 && ((sblkctl & SELBUSB) != 0)) 5167 cur_channel = 'B'; 5168 if (cur_channel != channel) { 5169 /* Case 1: Command for another bus is active 5170 * Stealthily reset the other bus without 5171 * upsetting the current bus. 5172 */ 5173 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5174 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5175 ahc_outb(ahc, SCSISEQ, 5176 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5177 if (initiate_reset) 5178 ahc_reset_current_bus(ahc); 5179 ahc_clear_intstat(ahc); 5180 ahc_outb(ahc, SBLKCTL, sblkctl); 5181 restart_needed = FALSE; 5182 } else { 5183 /* Case 2: A command from this bus is active or we're idle */ 5184 ahc_clear_msg_state(ahc); 5185 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5186 ahc_outb(ahc, SCSISEQ, 5187 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5188 if (initiate_reset) 5189 ahc_reset_current_bus(ahc); 5190 ahc_clear_intstat(ahc); 5191 5192 /* 5193 * Since we are going to restart the sequencer, avoid 5194 * a race in the sequencer that could cause corruption 5195 * of our Q pointers by starting over from index 0. 5196 */ 5197 ahc->qoutfifonext = 0; 5198 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5199 ahc_outb(ahc, SDSCB_QOFF, 0); 5200 else 5201 ahc_outb(ahc, QOUTPOS, 0); 5202 restart_needed = TRUE; 5203 } 5204 5205 /* 5206 * Clean up all the state information for the 5207 * pending transactions on this bus. 5208 */ 5209 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5210 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5211 ROLE_UNKNOWN, XS_RESET); 5212 if (channel == 'B') { 5213 our_id = ahc->our_id_b; 5214 } else { 5215 our_id = ahc->our_id; 5216 } 5217 5218 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5219 5220 /* 5221 * Revert to async/narrow transfers until we renegotiate. 5222 */ 5223 for (target = 0; target <= max_scsiid; target++) { 5224 5225 if (ahc->enabled_targets[target] == NULL) 5226 continue; 5227 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5228 struct ahc_devinfo devinfo; 5229 5230 ahc_compile_devinfo(&devinfo, target, initiator, 5231 AHC_LUN_WILDCARD, 5232 channel, ROLE_UNKNOWN); 5233 ahc_set_width(ahc, &devinfo, 5234 MSG_EXT_WDTR_BUS_8_BIT, 5235 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5236 ahc_set_syncrate(ahc, &devinfo, 5237 /*syncrate*/NULL, /*period*/0, 5238 /*offset*/0, AHC_TRANS_CUR, 5239 /*paused*/TRUE, FALSE); 5240 ahc_update_xfer_mode(ahc, &devinfo); 5241 } 5242 } 5243 5244 if (restart_needed) 5245 restart_sequencer(ahc); 5246 else 5247 unpause_sequencer(ahc); 5248 return found; 5249 } 5250 5251 static int 5252 ahc_match_scb(struct scb *scb, int target, char channel, 5253 int lun, u_int tag, role_t role) 5254 { 5255 int targ = SCB_TARGET(scb); 5256 char chan = SCB_CHANNEL(scb); 5257 int slun = SCB_LUN(scb); 5258 int match; 5259 5260 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5261 if (match != 0) 5262 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5263 if (match != 0) 5264 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5265 5266 return match; 5267 } 5268 5269 static void 5270 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5271 { 5272 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5273 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5274 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5275 ahc->msgout_buf[ahc->msgout_index++] = period; 5276 ahc->msgout_buf[ahc->msgout_index++] = offset; 5277 ahc->msgout_len += 5; 5278 } 5279 5280 static void 5281 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5282 { 5283 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5284 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5285 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5286 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5287 ahc->msgout_len += 4; 5288 } 5289 5290 static void 5291 ahc_calc_residual(struct scb *scb) 5292 { 5293 struct hardware_scb *hscb; 5294 5295 hscb = scb->hscb; 5296 5297 /* 5298 * If the disconnected flag is still set, this is bogus 5299 * residual information left over from a sequencer 5300 * pagin/pageout, so ignore this case. 5301 */ 5302 if ((scb->hscb->control & DISCONNECTED) == 0) { 5303 u_int32_t resid; 5304 int resid_sgs; 5305 int sg; 5306 5307 /* 5308 * Remainder of the SG where the transfer 5309 * stopped. 5310 */ 5311 resid = (hscb->residual_data_count[2] << 16) 5312 | (hscb->residual_data_count[1] <<8) 5313 | (hscb->residual_data_count[0]); 5314 5315 /* 5316 * Add up the contents of all residual 5317 * SG segments that are after the SG where 5318 * the transfer stopped. 5319 */ 5320 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5321 sg = scb->sg_count - resid_sgs; 5322 while (resid_sgs > 0) { 5323 5324 resid += le32toh(scb->sg_list[sg].len); 5325 sg++; 5326 resid_sgs--; 5327 } 5328 scb->xs->resid = resid; 5329 } 5330 5331 /* 5332 * Clean out the residual information in this SCB for its 5333 * next consumer. 5334 */ 5335 hscb->residual_SG_count = 0; 5336 5337 #ifdef AHC_DEBUG 5338 if (ahc_debug & AHC_SHOWMISC) { 5339 scsipi_printaddr(scb->xs->xs_periph); 5340 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5341 } 5342 #endif 5343 } 5344 5345 static void 5346 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5347 { 5348 struct scb *scb; 5349 int pending_ccb_count; 5350 int i; 5351 u_int saved_scbptr; 5352 5353 /* 5354 * Traverse the pending SCB list and ensure that all of the 5355 * SCBs there have the proper settings. 5356 */ 5357 scb = LIST_FIRST(&ahc->pending_ccbs); 5358 pending_ccb_count = 0; 5359 while (scb != NULL) { 5360 struct ahc_devinfo devinfo; 5361 struct scsipi_xfer *xs; 5362 struct scb *pending_scb; 5363 struct hardware_scb *pending_hscb; 5364 struct ahc_initiator_tinfo *tinfo; 5365 struct tmode_tstate *tstate; 5366 u_int our_id, remote_id; 5367 5368 xs = scb->xs; 5369 pending_scb = scb; 5370 pending_hscb = pending_scb->hscb; 5371 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5372 ? ahc->our_id_b : ahc->our_id; 5373 remote_id = xs->xs_periph->periph_target; 5374 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5375 SCB_LUN(pending_scb), 5376 SCB_CHANNEL(pending_scb), 5377 ROLE_UNKNOWN); 5378 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5379 our_id, remote_id, &tstate); 5380 pending_hscb->control &= ~ULTRAENB; 5381 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5382 pending_hscb->control |= ULTRAENB; 5383 pending_hscb->scsirate = tinfo->scsirate; 5384 pending_hscb->scsioffset = tinfo->current.offset; 5385 pending_ccb_count++; 5386 scb = LIST_NEXT(scb, plinks); 5387 } 5388 5389 if (pending_ccb_count == 0) 5390 return; 5391 5392 saved_scbptr = ahc_inb(ahc, SCBPTR); 5393 /* Ensure that the hscbs down on the card match the new information */ 5394 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5395 u_int scb_tag; 5396 5397 ahc_outb(ahc, SCBPTR, i); 5398 scb_tag = ahc_inb(ahc, SCB_TAG); 5399 if (scb_tag != SCB_LIST_NULL) { 5400 struct ahc_devinfo devinfo; 5401 struct scb *pending_scb; 5402 struct scsipi_xfer *xs; 5403 struct hardware_scb *pending_hscb; 5404 struct ahc_initiator_tinfo *tinfo; 5405 struct tmode_tstate *tstate; 5406 u_int our_id, remote_id; 5407 u_int control; 5408 5409 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5410 if (pending_scb->flags == SCB_FREE) 5411 continue; 5412 pending_hscb = pending_scb->hscb; 5413 xs = pending_scb->xs; 5414 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5415 ? ahc->our_id_b : ahc->our_id; 5416 remote_id = xs->xs_periph->periph_target; 5417 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5418 SCB_LUN(pending_scb), 5419 SCB_CHANNEL(pending_scb), 5420 ROLE_UNKNOWN); 5421 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5422 our_id, remote_id, &tstate); 5423 control = ahc_inb(ahc, SCB_CONTROL); 5424 control &= ~ULTRAENB; 5425 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5426 control |= ULTRAENB; 5427 ahc_outb(ahc, SCB_CONTROL, control); 5428 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5429 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5430 } 5431 } 5432 ahc_outb(ahc, SCBPTR, saved_scbptr); 5433 } 5434 5435 #if UNUSED 5436 static void 5437 ahc_dump_targcmd(struct target_cmd *cmd) 5438 { 5439 u_int8_t *byte; 5440 u_int8_t *last_byte; 5441 int i; 5442 5443 byte = &cmd->initiator_channel; 5444 /* Debugging info for received commands */ 5445 last_byte = &cmd[1].initiator_channel; 5446 5447 i = 0; 5448 while (byte < last_byte) { 5449 if (i == 0) 5450 printf("\t"); 5451 printf("%#x", *byte++); 5452 i++; 5453 if (i == 8) { 5454 printf("\n"); 5455 i = 0; 5456 } else { 5457 printf(", "); 5458 } 5459 } 5460 } 5461 #endif 5462 5463 static void 5464 ahc_shutdown(void *arg) 5465 { 5466 struct ahc_softc *ahc; 5467 int i; 5468 u_int sxfrctl1_a, sxfrctl1_b; 5469 5470 ahc = (struct ahc_softc *)arg; 5471 5472 pause_sequencer(ahc); 5473 5474 /* 5475 * Preserve the value of the SXFRCTL1 register for all channels. 5476 * It contains settings that affect termination and we don't want 5477 * to disturb the integrity of the bus during shutdown in case 5478 * we are in a multi-initiator setup. 5479 */ 5480 sxfrctl1_b = 0; 5481 if ((ahc->features & AHC_TWIN) != 0) { 5482 u_int sblkctl; 5483 5484 sblkctl = ahc_inb(ahc, SBLKCTL); 5485 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5486 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5487 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5488 } 5489 5490 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5491 5492 /* This will reset most registers to 0, but not all */ 5493 ahc_reset(ahc); 5494 5495 if ((ahc->features & AHC_TWIN) != 0) { 5496 u_int sblkctl; 5497 5498 sblkctl = ahc_inb(ahc, SBLKCTL); 5499 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5500 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5501 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5502 } 5503 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5504 5505 ahc_outb(ahc, SCSISEQ, 0); 5506 ahc_outb(ahc, SXFRCTL0, 0); 5507 ahc_outb(ahc, DSPCISTATUS, 0); 5508 5509 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5510 ahc_outb(ahc, i, 0); 5511 } 5512 5513 #if defined(AHC_DEBUG) && 0 5514 static void 5515 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5516 { 5517 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5518 5519 printf("\tcurrent:\n"); 5520 printf("\t\twidth %u period %u offset %u flags %x\n", 5521 tinfo->current.width, tinfo->current.period, 5522 tinfo->current.offset, tinfo->current.ppr_flags); 5523 5524 printf("\tgoal:\n"); 5525 printf("\t\twidth %u period %u offset %u flags %x\n", 5526 tinfo->goal.width, tinfo->goal.period, 5527 tinfo->goal.offset, tinfo->goal.ppr_flags); 5528 5529 printf("\tuser:\n"); 5530 printf("\t\twidth %u period %u offset %u flags %x\n", 5531 tinfo->user.width, tinfo->user.period, 5532 tinfo->user.offset, tinfo->user.ppr_flags); 5533 } 5534 #endif 5535 5536 static int 5537 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5538 int nocmdcheck) 5539 { 5540 #ifdef AHC_NO_TAGS 5541 return 0; 5542 #else 5543 char channel; 5544 u_int our_id, target; 5545 struct tmode_tstate *tstate; 5546 struct ahc_devinfo devinfo; 5547 5548 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5549 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5550 target = xs->xs_periph->periph_target; 5551 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5552 5553 ahc_compile_devinfo(&devinfo, our_id, target, 5554 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5555 5556 return (tstate->tagenable & devinfo.target_mask); 5557 #endif 5558 } 5559
Indexes created Thu Oct 02 10:09:58 GMT 2025