aic7xxx.c revision 1.82
1 /* $NetBSD: aic7xxx.c,v 1.82 2001/10/14 00:32:33 chs Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include "opt_ddb.h" 90 #include "opt_ahc.h" 91 92 #include <sys/param.h> 93 #include <sys/kernel.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/malloc.h> 97 #include <sys/buf.h> 98 #include <sys/proc.h> 99 #include <sys/scsiio.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/scsipi/scsi_all.h> 105 #include <dev/scsipi/scsipi_all.h> 106 #include <dev/scsipi/scsi_message.h> 107 #include <dev/scsipi/scsipi_debug.h> 108 #include <dev/scsipi/scsiconf.h> 109 110 #include <uvm/uvm_extern.h> 111 112 #include <dev/ic/aic7xxxvar.h> 113 #include <dev/microcode/aic7xxx/sequencer.h> 114 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 115 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 116 117 #define ALL_CHANNELS '\0' 118 #define ALL_TARGETS_MASK 0xFFFF 119 #define INITIATOR_WILDCARD (~0) 120 121 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 122 ((periph)->periph_channel->chan_channel == 1) 123 #define SIM_CHANNEL(ahc, periph) \ 124 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 125 #define SIM_SCSI_ID(ahc, periph) \ 126 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 127 #define SCB_IS_SCSIBUS_B(scb) \ 128 (((scb)->hscb->tcl & SELBUSB) != 0) 129 #define SCB_TARGET(scb) \ 130 (((scb)->hscb->tcl & TID) >> 4) 131 #define SCB_CHANNEL(scb) \ 132 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 133 #define SCB_LUN(scb) \ 134 ((scb)->hscb->tcl & LID) 135 #define SCB_TARGET_OFFSET(scb) \ 136 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 137 #define SCB_TARGET_MASK(scb) \ 138 (0x01 << (SCB_TARGET_OFFSET(scb))) 139 #define TCL_CHANNEL(ahc, tcl) \ 140 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 141 #define TCL_SCSI_ID(ahc, tcl) \ 142 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 143 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 144 #define TCL_LUN(tcl) ((tcl) & LID) 145 146 #define XS_TCL(ahc, xs) \ 147 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 148 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 149 | ((xs)->xs_periph->periph_lun & 0x07)) 150 151 const char * const ahc_chip_names[] = 152 { 153 "NONE", 154 "aic7770", 155 "aic7850", 156 "aic7855", 157 "aic7859", 158 "aic7860", 159 "aic7870", 160 "aic7880", 161 "aic7890/91", 162 "aic7892", 163 "aic7895", 164 "aic7896/97", 165 "aic7899" 166 }; 167 168 typedef enum { 169 ROLE_UNKNOWN, 170 ROLE_INITIATOR, 171 ROLE_TARGET 172 } role_t; 173 174 struct ahc_devinfo { 175 int our_scsiid; 176 int target_offset; 177 u_int16_t target_mask; 178 u_int8_t target; 179 u_int8_t lun; 180 char channel; 181 role_t role; /* 182 * Only guaranteed to be correct if not 183 * in the busfree state. 184 */ 185 }; 186 187 typedef enum { 188 SEARCH_COMPLETE, 189 SEARCH_COUNT, 190 SEARCH_REMOVE 191 } ahc_search_action; 192 193 #ifdef AHC_DEBUG 194 static int ahc_debug = AHC_DEBUG; 195 #endif 196 197 static int ahcinitscbdata(struct ahc_softc *); 198 static void ahcfiniscbdata(struct ahc_softc *); 199 200 #if UNUSED 201 static void ahc_dump_targcmd(struct target_cmd *); 202 #endif 203 static void ahc_shutdown(void *arg); 204 static void ahc_action(struct scsipi_channel *, 205 scsipi_adapter_req_t, void *); 206 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 207 struct proc *); 208 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 209 static int ahc_poll(struct ahc_softc *, int); 210 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 211 struct scb *); 212 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 213 static void ahcallocscbs(struct ahc_softc *); 214 #if UNUSED 215 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 216 struct scb *); 217 #endif 218 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 219 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 220 char, role_t); 221 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 222 static void ahc_done(struct ahc_softc *, struct scb *); 223 static struct tmode_tstate * 224 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 225 #if UNUSED 226 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 227 #endif 228 static void ahc_handle_seqint(struct ahc_softc *, u_int); 229 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 230 static void ahc_build_transfer_msg(struct ahc_softc *, 231 struct ahc_devinfo *); 232 static void ahc_setup_initiator_msgout(struct ahc_softc *, 233 struct ahc_devinfo *, 234 struct scb *); 235 static void ahc_setup_target_msgin(struct ahc_softc *, 236 struct ahc_devinfo *); 237 static void ahc_clear_msg_state(struct ahc_softc *); 238 static void ahc_handle_message_phase(struct ahc_softc *, 239 struct scsipi_periph *); 240 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 241 242 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 243 struct ahc_devinfo *); 244 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 245 struct ahc_devinfo *); 246 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 247 int, char *, int); 248 #ifdef AHC_DUMP_SEQ 249 static void ahc_dumpseq(struct ahc_softc *); 250 #endif 251 static void ahc_loadseq(struct ahc_softc *); 252 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 253 int, int *); 254 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 255 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 256 #if defined(AHC_DEBUG) 257 static void ahc_print_scb(struct scb *); 258 #endif 259 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 260 role_t, scb_flag, ahc_search_action); 261 static int ahc_reset_channel(struct ahc_softc *, char, int); 262 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 263 role_t, int); 264 static int ahc_search_disc_list(struct ahc_softc *, int, 265 char, int, u_int, int, int, int); 266 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 267 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 268 static void ahc_clear_intstat(struct ahc_softc *); 269 static void ahc_reset_current_bus(struct ahc_softc *); 270 static const struct ahc_syncrate * 271 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 272 static const struct ahc_syncrate * 273 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 274 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 275 static void ahc_validate_offset(struct ahc_softc *, 276 const struct ahc_syncrate *, u_int *, int); 277 static void ahc_update_target_msg_request(struct ahc_softc *, 278 struct ahc_devinfo *, 279 struct ahc_initiator_tinfo *, 280 int, int); 281 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 282 const struct ahc_syncrate *, u_int, u_int, 283 u_int, int, int); 284 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 285 u_int, u_int, int, int); 286 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 287 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 288 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 289 290 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 291 292 static void ahc_calc_residual(struct scb *); 293 294 static void ahc_update_pending_syncrates(struct ahc_softc *); 295 296 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 297 298 static void ahc_timeout (void *); 299 static __inline int sequencer_paused(struct ahc_softc *); 300 static __inline void pause_sequencer(struct ahc_softc *); 301 static __inline void unpause_sequencer(struct ahc_softc *); 302 static void restart_sequencer(struct ahc_softc *); 303 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 304 305 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 306 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 307 308 static __inline void ahc_freeze_ccb(struct scb *); 309 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 310 static void ahc_run_qoutfifo(struct ahc_softc *); 311 312 static __inline struct ahc_initiator_tinfo * 313 ahc_fetch_transinfo(struct ahc_softc *, 314 char, u_int, u_int, 315 struct tmode_tstate **); 316 static void ahcfreescb(struct ahc_softc *, struct scb *); 317 static __inline struct scb *ahcgetscb(struct ahc_softc *); 318 319 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 320 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 321 int *, const char *, const char *); 322 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 323 caddr_t, bus_dma_segment_t *, int); 324 static void ahcminphys(struct buf *); 325 326 static __inline void ahc_swap_hscb(struct hardware_scb *); 327 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 328 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 329 330 #if defined(AHC_DEBUG) && 0 331 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 332 #endif 333 334 static __inline void 335 ahc_swap_hscb(struct hardware_scb *hscb) 336 { 337 hscb->SG_pointer = htole32(hscb->SG_pointer); 338 hscb->data = htole32(hscb->data); 339 hscb->datalen = htole32(hscb->datalen); 340 /* 341 * No need to swap cmdpointer; it's either 0 or set to 342 * cmdstore_busaddr, which is already swapped. 343 */ 344 } 345 346 static __inline void 347 ahc_swap_sg(struct ahc_dma_seg *sg) 348 { 349 sg->addr = htole32(sg->addr); 350 sg->len = htole32(sg->len); 351 } 352 353 static void 354 ahcminphys(bp) 355 struct buf *bp; 356 { 357 /* 358 * Even though the card can transfer up to 16megs per command 359 * we are limited by the number of segments in the dma segment 360 * list that we can hold. The worst case is that all pages are 361 * discontinuous physically, hense the "page per segment" limit 362 * enforced here. 363 */ 364 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 365 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 366 } 367 minphys(bp); 368 } 369 370 371 static __inline u_int32_t 372 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 373 { 374 return (ahc->scb_data->hscb_busaddr 375 + (sizeof(struct hardware_scb) * index)); 376 } 377 378 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 379 380 static __inline int 381 sequencer_paused(struct ahc_softc *ahc) 382 { 383 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 384 } 385 386 static __inline void 387 pause_sequencer(struct ahc_softc *ahc) 388 { 389 ahc_outb(ahc, HCNTRL, ahc->pause); 390 391 /* 392 * Since the sequencer can disable pausing in a critical section, we 393 * must loop until it actually stops. 394 */ 395 while (sequencer_paused(ahc) == 0) 396 ; 397 } 398 399 static __inline void 400 unpause_sequencer(struct ahc_softc *ahc) 401 { 402 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 403 ahc_outb(ahc, HCNTRL, ahc->unpause); 404 } 405 406 /* 407 * Restart the sequencer program from address zero 408 */ 409 static void 410 restart_sequencer(struct ahc_softc *ahc) 411 { 412 u_int i; 413 414 pause_sequencer(ahc); 415 416 /* 417 * Everytime we restart the sequencer, there 418 * is the possiblitity that we have restarted 419 * within a three instruction window where an 420 * SCB has been marked free but has not made it 421 * onto the free list. Since SCSI events(bus reset, 422 * unexpected bus free) will always freeze the 423 * sequencer, we cannot close this window. To 424 * avoid losing an SCB, we reconsitute the free 425 * list every time we restart the sequencer. 426 */ 427 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 428 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 429 430 ahc_outb(ahc, SCBPTR, i); 431 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 432 ahc_add_curscb_to_free_list(ahc); 433 } 434 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 435 unpause_sequencer(ahc); 436 } 437 438 static __inline u_int 439 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 440 { 441 u_int scbid; 442 443 scbid = ahc->untagged_scbs[tcl]; 444 if (unbusy) { 445 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 446 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 447 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 448 } 449 450 return (scbid); 451 } 452 453 static __inline void 454 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 455 { 456 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 457 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 458 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 459 } 460 461 static __inline int 462 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 463 { 464 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 465 } 466 467 static __inline void 468 ahc_freeze_ccb(struct scb *scb) 469 { 470 struct scsipi_xfer *xs = scb->xs; 471 472 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 473 scsipi_periph_freeze(xs->xs_periph, 1); 474 scb->flags |= SCB_FREEZE_QUEUE; 475 } 476 } 477 478 static __inline void 479 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 480 { 481 xs->error = status; 482 } 483 484 static __inline struct ahc_initiator_tinfo * 485 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 486 u_int remote_id, struct tmode_tstate **tstate) 487 { 488 /* 489 * Transfer data structures are stored from the perspective 490 * of the target role. Since the parameters for a connection 491 * in the initiator role to a given target are the same as 492 * when the roles are reversed, we pretend we are the target. 493 */ 494 if (channel == 'B') 495 our_id += 8; 496 *tstate = ahc->enabled_targets[our_id]; 497 return (&(*tstate)->transinfo[remote_id]); 498 } 499 500 static void 501 ahc_run_qoutfifo(struct ahc_softc *ahc) 502 { 503 struct scb *scb; 504 u_int scb_index; 505 506 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 507 256, BUS_DMASYNC_POSTREAD); 508 509 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 510 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 511 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 512 513 scb = &ahc->scb_data->scbarray[scb_index]; 514 if (scb_index >= ahc->scb_data->numscbs 515 || (scb->flags & SCB_ACTIVE) == 0) { 516 printf("%s: WARNING no command for scb %d " 517 "(cmdcmplt)\nQOUTPOS = %d\n", 518 ahc_name(ahc), scb_index, 519 ahc->qoutfifonext - 1); 520 continue; 521 } 522 523 /* 524 * Save off the residual 525 * if there is one. 526 */ 527 if (scb->hscb->residual_SG_count != 0) 528 ahc_calc_residual(scb); 529 else 530 scb->xs->resid = 0; 531 #ifdef AHC_DEBUG 532 if (ahc_debug & AHC_SHOWSCBS) { 533 scsipi_printaddr(scb->xs->xs_periph); 534 printf("run_qoutfifo: SCB %x complete\n", 535 scb->hscb->tag); 536 } 537 #endif 538 ahc_done(ahc, scb); 539 } 540 } 541 542 543 /* 544 * An scb (and hence an scb entry on the board) is put onto the 545 * free list. 546 */ 547 static void 548 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 549 { 550 struct hardware_scb *hscb; 551 int opri; 552 553 hscb = scb->hscb; 554 555 #ifdef AHC_DEBUG 556 if (ahc_debug & AHC_SHOWSCBALLOC) 557 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 558 #endif 559 560 opri = splbio(); 561 562 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 563 (scb->flags & SCB_RECOVERY_SCB) != 0) { 564 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 565 scsipi_channel_thaw(&ahc->sc_channel, 1); 566 if (ahc->features & AHC_TWIN) 567 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 568 } 569 570 /* Clean up for the next user */ 571 scb->flags = SCB_FREE; 572 hscb->control = 0; 573 hscb->status = 0; 574 575 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 576 577 splx(opri); 578 } 579 580 /* 581 * Get a free scb, either one already assigned to a hardware slot 582 * on the adapter or one that will require an SCB to be paged out before 583 * use. If there are none, see if we can allocate a new SCB. Otherwise 584 * either return an error or sleep. 585 */ 586 static __inline struct scb * 587 ahcgetscb(struct ahc_softc *ahc) 588 { 589 struct scb *scbp; 590 int opri;; 591 592 opri = splbio(); 593 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 594 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 595 } else { 596 ahcallocscbs(ahc); 597 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 598 if (scbp != NULL) 599 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 600 } 601 602 splx(opri); 603 604 #ifdef AHC_DEBUG 605 if (ahc_debug & AHC_SHOWSCBALLOC) { 606 if (scbp != NULL) 607 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 608 scbp->hscb->tag); 609 else 610 printf("%s: failed to allocate new SCB\n", 611 ahc_name(ahc)); 612 } 613 #endif 614 615 return (scbp); 616 } 617 618 static int 619 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 620 bus_dma_tag_t tag; 621 int size; 622 int flags; 623 bus_dmamap_t *mapp; 624 caddr_t *vaddr; 625 bus_addr_t *baddr; 626 bus_dma_segment_t *seg; 627 int *nseg; 628 const char *myname, *what; 629 { 630 int error, level = 0; 631 632 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 633 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 634 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 635 myname, what, error); 636 goto out; 637 } 638 level++; 639 640 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 641 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 642 printf("%s: failed to map DMA mem for %s, error = %d\n", 643 myname, what, error); 644 goto out; 645 } 646 level++; 647 648 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 649 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 650 printf("%s: failed to create DMA map for %s, error = %d\n", 651 myname, what, error); 652 goto out; 653 } 654 level++; 655 656 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 657 BUS_DMA_NOWAIT)) != 0) { 658 printf("%s: failed to load DMA map for %s, error = %d\n", 659 myname, what, error); 660 goto out; 661 } 662 663 *baddr = (*mapp)->dm_segs[0].ds_addr; 664 665 #ifdef AHC_DEBUG 666 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 667 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 668 *nseg, size); 669 #endif 670 671 return 0; 672 out: 673 switch (level) { 674 case 3: 675 bus_dmamap_destroy(tag, *mapp); 676 /* FALLTHROUGH */ 677 case 2: 678 bus_dmamem_unmap(tag, *vaddr, size); 679 /* FALLTHROUGH */ 680 case 1: 681 bus_dmamem_free(tag, seg, *nseg); 682 break; 683 default: 684 break; 685 } 686 687 return error; 688 } 689 690 static void 691 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 692 bus_dma_tag_t tag; 693 int size; 694 bus_dmamap_t map; 695 caddr_t vaddr; 696 bus_dma_segment_t *seg; 697 int nseg; 698 { 699 700 bus_dmamap_unload(tag, map); 701 bus_dmamap_destroy(tag, map); 702 bus_dmamem_unmap(tag, vaddr, size); 703 bus_dmamem_free(tag, seg, nseg); 704 } 705 706 char * 707 ahc_name(struct ahc_softc *ahc) 708 { 709 return (ahc->sc_dev.dv_xname); 710 } 711 712 #ifdef AHC_DEBUG 713 static void 714 ahc_print_scb(struct scb *scb) 715 { 716 struct hardware_scb *hscb = scb->hscb; 717 718 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 719 scb, 720 hscb->tag, 721 hscb->control, 722 hscb->tcl, 723 hscb->cmdlen, 724 (unsigned long)le32toh(hscb->cmdpointer)); 725 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 726 le32toh(hscb->datalen), 727 (unsigned long)(le32toh(hscb->data)), 728 hscb->SG_count, 729 (unsigned long)(le32toh(hscb->SG_pointer))); 730 printf(" sg_addr:%lx sg_len:%lu\n", 731 (unsigned long)(le32toh(scb->sg_list[0].addr)), 732 (unsigned long)(le32toh(scb->sg_list[0].len))); 733 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 734 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 735 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 736 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 737 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 738 } 739 #endif 740 741 static const struct { 742 u_int8_t errno; 743 const char *errmesg; 744 } hard_error[] = { 745 { ILLHADDR, "Illegal Host Access" }, 746 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 747 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 748 { SQPARERR, "Sequencer Parity Error" }, 749 { DPARERR, "Data-path Parity Error" }, 750 { MPARERR, "Scratch or SCB Memory Parity Error" }, 751 { PCIERRSTAT, "PCI Error detected" }, 752 { CIOPARERR, "CIOBUS Parity Error" }, 753 }; 754 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 755 756 static const struct { 757 u_int8_t phase; 758 u_int8_t mesg_out; /* Message response to parity errors */ 759 const char *phasemsg; 760 } phase_table[] = { 761 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 762 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 763 { P_COMMAND, MSG_NOOP, "in Command phase" }, 764 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 765 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 766 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 767 { P_BUSFREE, MSG_NOOP, "while idle" }, 768 { 0, MSG_NOOP, "in unknown phase" } 769 }; 770 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 771 772 /* 773 * Valid SCSIRATE values. (p. 3-17) 774 * Provides a mapping of transfer periods in ns to the proper value to 775 * stick in the scsiscfr reg to use that transfer rate. 776 */ 777 #define AHC_SYNCRATE_DT 0 778 #define AHC_SYNCRATE_ULTRA2 1 779 #define AHC_SYNCRATE_ULTRA 3 780 #define AHC_SYNCRATE_FAST 6 781 static const struct ahc_syncrate ahc_syncrates[] = { 782 /* ultra2 fast/ultra period rate */ 783 { 0x42, 0x000, 9, "80.0" }, 784 { 0x03, 0x000, 10, "40.0" }, 785 { 0x04, 0x000, 11, "33.0" }, 786 { 0x05, 0x100, 12, "20.0" }, 787 { 0x06, 0x110, 15, "16.0" }, 788 { 0x07, 0x120, 18, "13.4" }, 789 { 0x08, 0x000, 25, "10.0" }, 790 { 0x19, 0x010, 31, "8.0" }, 791 { 0x1a, 0x020, 37, "6.67" }, 792 { 0x1b, 0x030, 43, "5.7" }, 793 { 0x1c, 0x040, 50, "5.0" }, 794 { 0x00, 0x050, 56, "4.4" }, 795 { 0x00, 0x060, 62, "4.0" }, 796 { 0x00, 0x070, 68, "3.6" }, 797 { 0x00, 0x000, 0, NULL } 798 }; 799 800 /* 801 * Allocate a controller structure for a new device and initialize it. 802 */ 803 int 804 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 805 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 806 ahc_flag flags) 807 { 808 struct scb_data *scb_data; 809 810 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 811 if (scb_data == NULL) { 812 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 813 return -1; 814 } 815 memset(scb_data, 0, sizeof (struct scb_data)); 816 LIST_INIT(&ahc->pending_ccbs); 817 ahc->tag = st; 818 ahc->bsh = sh; 819 ahc->parent_dmat = parent_dmat; 820 ahc->chip = chip; 821 ahc->features = features; 822 ahc->flags = flags; 823 ahc->scb_data = scb_data; 824 825 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 826 /* The IRQMS bit is only valid on VL and EISA chips */ 827 if ((ahc->chip & AHC_PCI) != 0) 828 ahc->unpause &= ~IRQMS; 829 ahc->pause = ahc->unpause | PAUSE; 830 return (0); 831 } 832 833 void 834 ahc_free(ahc) 835 struct ahc_softc *ahc; 836 { 837 ahcfiniscbdata(ahc); 838 if (ahc->init_level != 0) 839 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 840 ahc->shared_data_dmamap, ahc->qoutfifo, 841 &ahc->shared_data_seg, ahc->shared_data_nseg); 842 843 if (ahc->scb_data != NULL) 844 free(ahc->scb_data, M_DEVBUF); 845 if (ahc->bus_data != NULL) 846 free(ahc->bus_data, M_DEVBUF); 847 return; 848 } 849 850 static int 851 ahcinitscbdata(struct ahc_softc *ahc) 852 { 853 struct scb_data *scb_data; 854 int i; 855 856 scb_data = ahc->scb_data; 857 SLIST_INIT(&scb_data->free_scbs); 858 SLIST_INIT(&scb_data->sg_maps); 859 860 /* Allocate SCB resources */ 861 scb_data->scbarray = 862 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 863 M_DEVBUF, M_NOWAIT); 864 if (scb_data->scbarray == NULL) 865 return (ENOMEM); 866 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); 867 868 /* Determine the number of hardware SCBs and initialize them */ 869 870 scb_data->maxhscbs = ahc_probe_scbs(ahc); 871 /* SCB 0 heads the free list */ 872 ahc_outb(ahc, FREE_SCBH, 0); 873 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 874 ahc_outb(ahc, SCBPTR, i); 875 876 /* Clear the control byte. */ 877 ahc_outb(ahc, SCB_CONTROL, 0); 878 879 /* Set the next pointer */ 880 ahc_outb(ahc, SCB_NEXT, i+1); 881 882 /* Make the tag number invalid */ 883 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 884 } 885 886 /* Make sure that the last SCB terminates the free list */ 887 ahc_outb(ahc, SCBPTR, i-1); 888 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 889 890 /* Ensure we clear the 0 SCB's control byte. */ 891 ahc_outb(ahc, SCBPTR, 0); 892 ahc_outb(ahc, SCB_CONTROL, 0); 893 894 scb_data->maxhscbs = i; 895 896 if (ahc->scb_data->maxhscbs == 0) 897 panic("%s: No SCB space found", ahc_name(ahc)); 898 899 /* 900 * Create our DMA tags. These tags define the kinds of device 901 * accessible memory allocations and memory mappings we will 902 * need to perform during normal operation. 903 * 904 * Unless we need to further restrict the allocation, we rely 905 * on the restrictions of the parent dmat, hence the common 906 * use of MAXADDR and MAXSIZE. 907 */ 908 909 if (ahc_createdmamem(ahc->parent_dmat, 910 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 911 &scb_data->hscb_dmamap, 912 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 913 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 914 "hardware SCB structures") < 0) 915 goto error_exit; 916 917 scb_data->init_level++; 918 919 if (ahc_createdmamem(ahc->parent_dmat, 920 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 921 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 922 &scb_data->sense_busaddr, &scb_data->sense_seg, 923 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 924 goto error_exit; 925 926 scb_data->init_level++; 927 928 /* Perform initial CCB allocation */ 929 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 930 ahcallocscbs(ahc); 931 932 if (scb_data->numscbs == 0) { 933 printf("%s: ahc_init_scb_data - " 934 "Unable to allocate initial scbs\n", 935 ahc_name(ahc)); 936 goto error_exit; 937 } 938 939 scb_data->init_level++; 940 941 /* 942 * Note that we were successfull 943 */ 944 return 0; 945 946 error_exit: 947 948 return ENOMEM; 949 } 950 951 static void 952 ahcfiniscbdata(struct ahc_softc *ahc) 953 { 954 struct scb_data *scb_data; 955 956 scb_data = ahc->scb_data; 957 958 switch (scb_data->init_level) { 959 default: 960 case 3: 961 { 962 struct sg_map_node *sg_map; 963 964 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 965 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 966 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 967 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 968 &sg_map->sg_dmasegs, sg_map->sg_nseg); 969 free(sg_map, M_DEVBUF); 970 } 971 } 972 /*FALLTHROUGH*/ 973 case 2: 974 ahc_freedmamem(ahc->parent_dmat, 975 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 976 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 977 &scb_data->sense_seg, scb_data->sense_nseg); 978 /*FALLTHROUGH*/ 979 case 1: 980 ahc_freedmamem(ahc->parent_dmat, 981 AHC_SCB_MAX * sizeof(struct hardware_scb), 982 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 983 &scb_data->hscb_seg, scb_data->hscb_nseg); 984 /*FALLTHROUGH*/ 985 } 986 if (scb_data->scbarray != NULL) 987 free(scb_data->scbarray, M_DEVBUF); 988 } 989 990 int 991 ahc_reset(struct ahc_softc *ahc) 992 { 993 u_int sblkctl; 994 int wait; 995 996 #ifdef AHC_DUMP_SEQ 997 if (ahc->init_level == 0) 998 ahc_dumpseq(ahc); 999 #endif 1000 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1001 /* 1002 * Ensure that the reset has finished 1003 */ 1004 wait = 1000; 1005 do { 1006 DELAY(1000); 1007 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1008 1009 if (wait == 0) { 1010 printf("%s: WARNING - Failed chip reset! " 1011 "Trying to initialize anyway.\n", ahc_name(ahc)); 1012 } 1013 ahc_outb(ahc, HCNTRL, ahc->pause); 1014 1015 /* Determine channel configuration */ 1016 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1017 /* No Twin Channel PCI cards */ 1018 if ((ahc->chip & AHC_PCI) != 0) 1019 sblkctl &= ~SELBUSB; 1020 switch (sblkctl) { 1021 case 0: 1022 /* Single Narrow Channel */ 1023 break; 1024 case 2: 1025 /* Wide Channel */ 1026 ahc->features |= AHC_WIDE; 1027 break; 1028 case 8: 1029 /* Twin Channel */ 1030 ahc->features |= AHC_TWIN; 1031 break; 1032 default: 1033 printf(" Unsupported adapter type. Ignoring\n"); 1034 return(-1); 1035 } 1036 1037 return (0); 1038 } 1039 1040 /* 1041 * Called when we have an active connection to a target on the bus, 1042 * this function finds the nearest syncrate to the input period limited 1043 * by the capabilities of the bus connectivity of the target. 1044 */ 1045 static const struct ahc_syncrate * 1046 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1047 u_int maxsync; 1048 1049 if ((ahc->features & AHC_ULTRA2) != 0) { 1050 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1051 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1052 maxsync = AHC_SYNCRATE_ULTRA2; 1053 } else { 1054 maxsync = AHC_SYNCRATE_ULTRA; 1055 } 1056 } else if ((ahc->features & AHC_ULTRA) != 0) { 1057 maxsync = AHC_SYNCRATE_ULTRA; 1058 } else { 1059 maxsync = AHC_SYNCRATE_FAST; 1060 } 1061 return (ahc_find_syncrate(ahc, period, maxsync)); 1062 } 1063 1064 /* 1065 * Look up the valid period to SCSIRATE conversion in our table. 1066 * Return the period and offset that should be sent to the target 1067 * if this was the beginning of an SDTR. 1068 */ 1069 static const struct ahc_syncrate * 1070 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1071 { 1072 const struct ahc_syncrate *syncrate; 1073 1074 syncrate = &ahc_syncrates[maxsync]; 1075 while ((syncrate->rate != NULL) 1076 && ((ahc->features & AHC_ULTRA2) == 0 1077 || (syncrate->sxfr_u2 != 0))) { 1078 1079 if (*period <= syncrate->period) { 1080 /* 1081 * When responding to a target that requests 1082 * sync, the requested rate may fall between 1083 * two rates that we can output, but still be 1084 * a rate that we can receive. Because of this, 1085 * we want to respond to the target with 1086 * the same rate that it sent to us even 1087 * if the period we use to send data to it 1088 * is lower. Only lower the response period 1089 * if we must. 1090 */ 1091 if (syncrate == &ahc_syncrates[maxsync]) 1092 *period = syncrate->period; 1093 break; 1094 } 1095 syncrate++; 1096 } 1097 1098 if ((*period == 0) 1099 || (syncrate->rate == NULL) 1100 || ((ahc->features & AHC_ULTRA2) != 0 1101 && (syncrate->sxfr_u2 == 0))) { 1102 /* Use asynchronous transfers. */ 1103 *period = 0; 1104 syncrate = NULL; 1105 } 1106 return (syncrate); 1107 } 1108 1109 static u_int 1110 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1111 { 1112 const struct ahc_syncrate *syncrate; 1113 1114 if ((ahc->features & AHC_ULTRA2) != 0) 1115 scsirate &= SXFR_ULTRA2; 1116 else 1117 scsirate &= SXFR; 1118 1119 syncrate = &ahc_syncrates[maxsync]; 1120 while (syncrate->rate != NULL) { 1121 1122 if ((ahc->features & AHC_ULTRA2) != 0) { 1123 if (syncrate->sxfr_u2 == 0) 1124 break; 1125 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1126 return (syncrate->period); 1127 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1128 return (syncrate->period); 1129 } 1130 syncrate++; 1131 } 1132 return (0); /* async */ 1133 } 1134 1135 static void 1136 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1137 u_int *offset, int wide) 1138 { 1139 u_int maxoffset; 1140 1141 /* Limit offset to what we can do */ 1142 if (syncrate == NULL) { 1143 maxoffset = 0; 1144 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1145 maxoffset = MAX_OFFSET_ULTRA2; 1146 } else { 1147 if (wide) 1148 maxoffset = MAX_OFFSET_16BIT; 1149 else 1150 maxoffset = MAX_OFFSET_8BIT; 1151 } 1152 *offset = MIN(*offset, maxoffset); 1153 } 1154 1155 static void 1156 ahc_update_target_msg_request(struct ahc_softc *ahc, 1157 struct ahc_devinfo *devinfo, 1158 struct ahc_initiator_tinfo *tinfo, 1159 int force, int paused) 1160 { 1161 u_int targ_msg_req_orig; 1162 1163 targ_msg_req_orig = ahc->targ_msg_req; 1164 if (tinfo->current.period != tinfo->goal.period 1165 || tinfo->current.width != tinfo->goal.width 1166 || tinfo->current.offset != tinfo->goal.offset 1167 || (force 1168 && (tinfo->goal.period != 0 1169 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1170 ahc->targ_msg_req |= devinfo->target_mask; 1171 } else { 1172 ahc->targ_msg_req &= ~devinfo->target_mask; 1173 } 1174 1175 if (ahc->targ_msg_req != targ_msg_req_orig) { 1176 /* Update the message request bit for this target */ 1177 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1178 if (paused) { 1179 ahc_outb(ahc, TARGET_MSG_REQUEST, 1180 ahc->targ_msg_req & 0xFF); 1181 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1182 (ahc->targ_msg_req >> 8) & 0xFF); 1183 } else { 1184 ahc_outb(ahc, HS_MAILBOX, 1185 0x01 << HOST_MAILBOX_SHIFT); 1186 } 1187 } else { 1188 if (!paused) 1189 pause_sequencer(ahc); 1190 1191 ahc_outb(ahc, TARGET_MSG_REQUEST, 1192 ahc->targ_msg_req & 0xFF); 1193 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1194 (ahc->targ_msg_req >> 8) & 0xFF); 1195 1196 if (!paused) 1197 unpause_sequencer(ahc); 1198 } 1199 } 1200 } 1201 1202 static void 1203 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1204 const struct ahc_syncrate *syncrate, 1205 u_int period, u_int offset, u_int type, int paused, int done) 1206 { 1207 struct ahc_initiator_tinfo *tinfo; 1208 struct tmode_tstate *tstate; 1209 u_int old_period; 1210 u_int old_offset; 1211 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1212 1213 if (syncrate == NULL) { 1214 period = 0; 1215 offset = 0; 1216 } 1217 1218 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1219 devinfo->target, &tstate); 1220 old_period = tinfo->current.period; 1221 old_offset = tinfo->current.offset; 1222 1223 if ((type & AHC_TRANS_CUR) != 0 1224 && (old_period != period || old_offset != offset)) { 1225 u_int scsirate; 1226 1227 scsirate = tinfo->scsirate; 1228 if ((ahc->features & AHC_ULTRA2) != 0) { 1229 1230 /* XXX */ 1231 /* Force single edge until DT is fully implemented */ 1232 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1233 if (syncrate != NULL) 1234 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1235 1236 if (active) 1237 ahc_outb(ahc, SCSIOFFSET, offset); 1238 } else { 1239 1240 scsirate &= ~(SXFR|SOFS); 1241 /* 1242 * Ensure Ultra mode is set properly for 1243 * this target. 1244 */ 1245 tstate->ultraenb &= ~devinfo->target_mask; 1246 if (syncrate != NULL) { 1247 if (syncrate->sxfr & ULTRA_SXFR) { 1248 tstate->ultraenb |= 1249 devinfo->target_mask; 1250 } 1251 scsirate |= syncrate->sxfr & SXFR; 1252 scsirate |= offset & SOFS; 1253 } 1254 if (active) { 1255 u_int sxfrctl0; 1256 1257 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1258 sxfrctl0 &= ~FAST20; 1259 if (tstate->ultraenb & devinfo->target_mask) 1260 sxfrctl0 |= FAST20; 1261 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1262 } 1263 } 1264 if (active) 1265 ahc_outb(ahc, SCSIRATE, scsirate); 1266 1267 tinfo->scsirate = scsirate; 1268 tinfo->current.period = period; 1269 tinfo->current.offset = offset; 1270 1271 /* Update the syncrates in any pending scbs */ 1272 ahc_update_pending_syncrates(ahc); 1273 } 1274 1275 if ((type & AHC_TRANS_GOAL) != 0) { 1276 tinfo->goal.period = period; 1277 tinfo->goal.offset = offset; 1278 } 1279 1280 if ((type & AHC_TRANS_USER) != 0) { 1281 tinfo->user.period = period; 1282 tinfo->user.offset = offset; 1283 } 1284 1285 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1286 /*force*/FALSE, 1287 paused); 1288 } 1289 1290 static void 1291 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1292 u_int width, u_int type, int paused, int done) 1293 { 1294 struct ahc_initiator_tinfo *tinfo; 1295 struct tmode_tstate *tstate; 1296 u_int oldwidth; 1297 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1298 1299 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1300 devinfo->target, &tstate); 1301 oldwidth = tinfo->current.width; 1302 1303 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1304 u_int scsirate; 1305 1306 scsirate = tinfo->scsirate; 1307 scsirate &= ~WIDEXFER; 1308 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1309 scsirate |= WIDEXFER; 1310 1311 tinfo->scsirate = scsirate; 1312 1313 if (active) 1314 ahc_outb(ahc, SCSIRATE, scsirate); 1315 1316 tinfo->current.width = width; 1317 } 1318 1319 if ((type & AHC_TRANS_GOAL) != 0) 1320 tinfo->goal.width = width; 1321 if ((type & AHC_TRANS_USER) != 0) 1322 tinfo->user.width = width; 1323 1324 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1325 /*force*/FALSE, paused); 1326 } 1327 1328 static void 1329 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1330 { 1331 struct ahc_initiator_tinfo *tinfo; 1332 struct tmode_tstate *tstate; 1333 1334 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1335 devinfo->target, &tstate); 1336 1337 if (enable) { 1338 tstate->tagenable |= devinfo->target_mask; 1339 } else { 1340 tstate->tagenable &= ~devinfo->target_mask; 1341 tstate->tagdisable |= devinfo->target_mask; 1342 } 1343 } 1344 1345 static void 1346 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1347 { 1348 struct scsipi_xfer_mode xm; 1349 struct ahc_initiator_tinfo *tinfo; 1350 struct tmode_tstate *tstate; 1351 1352 if (ahc->inited_targets[devinfo->target] != 2) 1353 return; 1354 1355 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1356 devinfo->target, &tstate); 1357 1358 xm.xm_target = devinfo->target; 1359 xm.xm_mode = 0; 1360 xm.xm_period = tinfo->current.period; 1361 xm.xm_offset = tinfo->current.offset; 1362 if (tinfo->current.width == 1) 1363 xm.xm_mode |= PERIPH_CAP_WIDE16; 1364 if (tinfo->current.period) 1365 xm.xm_mode |= PERIPH_CAP_SYNC; 1366 if (tstate->tagenable & devinfo->target_mask) 1367 xm.xm_mode |= PERIPH_CAP_TQING; 1368 scsipi_async_event( 1369 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1370 ASYNC_EVENT_XFER_MODE, &xm); 1371 } 1372 1373 /* 1374 * Attach all the sub-devices we can find 1375 */ 1376 int 1377 ahc_attach(struct ahc_softc *ahc) 1378 { 1379 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1380 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1381 if (ahc->flags & AHC_PAGESCBS) { 1382 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1383 ahc->sc_adapter.adapt_max_periph = 16; 1384 } else { 1385 ahc->sc_adapter.adapt_openings = ahc->scb_data->maxhscbs; 1386 if (ahc->scb_data->maxhscbs >= 16) 1387 ahc->sc_adapter.adapt_max_periph = 16; 1388 else 1389 ahc->sc_adapter.adapt_max_periph = 4; 1390 } 1391 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1392 ahc->sc_adapter.adapt_minphys = ahcminphys; 1393 ahc->sc_adapter.adapt_request = ahc_action; 1394 1395 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1396 ahc->sc_channel.chan_bustype = &scsi_bustype; 1397 ahc->sc_channel.chan_channel = 0; 1398 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1399 ahc->sc_channel.chan_nluns = 8; 1400 ahc->sc_channel.chan_id = ahc->our_id; 1401 1402 if (ahc->features & AHC_TWIN) { 1403 ahc->sc_channel_b = ahc->sc_channel; 1404 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1405 ahc->sc_channel_b.chan_channel = 1; 1406 } 1407 1408 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1409 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1410 if (ahc->features & AHC_TWIN) 1411 config_found((void *)ahc, &ahc->sc_channel_b, 1412 scsiprint); 1413 } else { 1414 config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1415 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1416 } 1417 return 1; 1418 } 1419 1420 static void 1421 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1422 { 1423 u_int saved_tcl; 1424 role_t role; 1425 int our_id; 1426 1427 if (ahc_inb(ahc, SSTAT0) & TARGET) 1428 role = ROLE_TARGET; 1429 else 1430 role = ROLE_INITIATOR; 1431 1432 if (role == ROLE_TARGET 1433 && (ahc->features & AHC_MULTI_TID) != 0 1434 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1435 /* We were selected, so pull our id from TARGIDIN */ 1436 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1437 } else if ((ahc->features & AHC_ULTRA2) != 0) 1438 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1439 else 1440 our_id = ahc_inb(ahc, SCSIID) & OID; 1441 1442 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1443 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1444 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1445 role); 1446 } 1447 1448 static void 1449 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1450 u_int lun, char channel, role_t role) 1451 { 1452 devinfo->our_scsiid = our_id; 1453 devinfo->target = target; 1454 devinfo->lun = lun; 1455 devinfo->target_offset = target; 1456 devinfo->channel = channel; 1457 devinfo->role = role; 1458 if (channel == 'B') 1459 devinfo->target_offset += 8; 1460 devinfo->target_mask = (0x01 << devinfo->target_offset); 1461 } 1462 1463 /* 1464 * Catch an interrupt from the adapter 1465 */ 1466 int 1467 ahc_intr(void *arg) 1468 { 1469 struct ahc_softc *ahc; 1470 u_int intstat; 1471 1472 ahc = (struct ahc_softc *)arg; 1473 1474 intstat = ahc_inb(ahc, INTSTAT); 1475 1476 /* 1477 * Any interrupts to process? 1478 */ 1479 if ((intstat & INT_PEND) == 0) { 1480 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1481 #ifdef AHC_DEBUG 1482 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1483 ahc_name(ahc), 1484 ahc_inb(ahc, CCHADDR) | 1485 (ahc_inb(ahc, CCHADDR+1) << 8) 1486 | (ahc_inb(ahc, CCHADDR+2) << 16) 1487 | (ahc_inb(ahc, CCHADDR+3) << 24), 1488 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1489 | (ahc_inb(ahc, HADDR+2) << 16) 1490 | (ahc_inb(ahc, HADDR+3) << 24), 1491 ahc_inb(ahc, SEQADDR0) | 1492 (ahc_inb(ahc, SEQADDR1) << 8)); 1493 #endif 1494 return 1; 1495 } 1496 return 0; 1497 } 1498 1499 #ifdef AHC_DEBUG 1500 if (ahc_debug & AHC_SHOWINTR) { 1501 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1502 } 1503 #endif 1504 1505 if (intstat & CMDCMPLT) { 1506 ahc_outb(ahc, CLRINT, CLRCMDINT); 1507 ahc_run_qoutfifo(ahc); 1508 } 1509 if (intstat & BRKADRINT) { 1510 /* 1511 * We upset the sequencer :-( 1512 * Lookup the error message 1513 */ 1514 int i, error, num_errors; 1515 1516 error = ahc_inb(ahc, ERROR); 1517 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1518 for (i = 0; error != 1 && i < num_errors; i++) 1519 error >>= 1; 1520 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1521 ahc_name(ahc), hard_error[i].errmesg, 1522 ahc_inb(ahc, SEQADDR0) | 1523 (ahc_inb(ahc, SEQADDR1) << 8)); 1524 1525 /* Tell everyone that this HBA is no longer available */ 1526 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1527 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1528 XS_DRIVER_STUFFUP); 1529 } 1530 if (intstat & SEQINT) 1531 ahc_handle_seqint(ahc, intstat); 1532 1533 if (intstat & SCSIINT) 1534 ahc_handle_scsiint(ahc, intstat); 1535 1536 return 1; 1537 } 1538 1539 static struct tmode_tstate * 1540 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1541 { 1542 struct tmode_tstate *master_tstate; 1543 struct tmode_tstate *tstate; 1544 int i, s; 1545 1546 master_tstate = ahc->enabled_targets[ahc->our_id]; 1547 if (channel == 'B') { 1548 scsi_id += 8; 1549 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1550 } 1551 if (ahc->enabled_targets[scsi_id] != NULL 1552 && ahc->enabled_targets[scsi_id] != master_tstate) 1553 panic("%s: ahc_alloc_tstate - Target already allocated", 1554 ahc_name(ahc)); 1555 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1556 if (tstate == NULL) 1557 return (NULL); 1558 1559 /* 1560 * If we have allocated a master tstate, copy user settings from 1561 * the master tstate (taken from SRAM or the EEPROM) for this 1562 * channel, but reset our current and goal settings to async/narrow 1563 * until an initiator talks to us. 1564 */ 1565 if (master_tstate != NULL) { 1566 memcpy(tstate, master_tstate, sizeof(*tstate)); 1567 tstate->ultraenb = 0; 1568 for (i = 0; i < 16; i++) { 1569 memset(&tstate->transinfo[i].current, 0, 1570 sizeof(tstate->transinfo[i].current)); 1571 memset(&tstate->transinfo[i].goal, 0, 1572 sizeof(tstate->transinfo[i].goal)); 1573 } 1574 } else 1575 memset(tstate, 0, sizeof(*tstate)); 1576 s = splbio(); 1577 ahc->enabled_targets[scsi_id] = tstate; 1578 splx(s); 1579 return (tstate); 1580 } 1581 1582 #if UNUSED 1583 static void 1584 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1585 { 1586 struct tmode_tstate *tstate; 1587 1588 /* Don't clean up the entry for our initiator role */ 1589 if ((ahc->flags & AHC_INITIATORMODE) != 0 1590 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1591 || (channel == 'A' && scsi_id == ahc->our_id)) 1592 && force == FALSE) 1593 return; 1594 1595 if (channel == 'B') 1596 scsi_id += 8; 1597 tstate = ahc->enabled_targets[scsi_id]; 1598 if (tstate != NULL) 1599 free(tstate, M_DEVBUF); 1600 ahc->enabled_targets[scsi_id] = NULL; 1601 } 1602 #endif 1603 1604 static void 1605 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1606 { 1607 struct scb *scb; 1608 struct ahc_devinfo devinfo; 1609 1610 ahc_fetch_devinfo(ahc, &devinfo); 1611 1612 /* 1613 * Clear the upper byte that holds SEQINT status 1614 * codes and clear the SEQINT bit. We will unpause 1615 * the sequencer, if appropriate, after servicing 1616 * the request. 1617 */ 1618 ahc_outb(ahc, CLRINT, CLRSEQINT); 1619 switch (intstat & SEQINT_MASK) { 1620 case NO_MATCH: 1621 { 1622 /* Ensure we don't leave the selection hardware on */ 1623 ahc_outb(ahc, SCSISEQ, 1624 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1625 1626 printf("%s:%c:%d: no active SCB for reconnecting " 1627 "target - issuing BUS DEVICE RESET\n", 1628 ahc_name(ahc), devinfo.channel, devinfo.target); 1629 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1630 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1631 ahc_inb(ahc, SEQ_FLAGS)); 1632 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1633 ahc->msgout_len = 1; 1634 ahc->msgout_index = 0; 1635 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1636 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1637 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1638 break; 1639 } 1640 case UPDATE_TMSG_REQ: 1641 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1642 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1643 (ahc->targ_msg_req >> 8) & 0xFF); 1644 ahc_outb(ahc, HS_MAILBOX, 0); 1645 break; 1646 case SEND_REJECT: 1647 { 1648 u_int rejbyte = ahc_inb(ahc, ACCUM); 1649 printf("%s:%c:%d: Warning - unknown message received from " 1650 "target (0x%x). Rejecting\n", 1651 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1652 break; 1653 } 1654 case NO_IDENT: 1655 { 1656 /* 1657 * The reconnecting target either did not send an identify 1658 * message, or did, but we didn't find and SCB to match and 1659 * before it could respond to our ATN/abort, it hit a dataphase. 1660 * The only safe thing to do is to blow it away with a bus 1661 * reset. 1662 */ 1663 int found; 1664 1665 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1666 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1667 ahc_name(ahc), devinfo.channel, devinfo.target, 1668 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1669 found = ahc_reset_channel(ahc, devinfo.channel, 1670 /*initiate reset*/TRUE); 1671 printf("%s: Issued Channel %c Bus Reset. " 1672 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1673 found); 1674 return; 1675 } 1676 case BAD_PHASE: 1677 { 1678 u_int lastphase; 1679 1680 lastphase = ahc_inb(ahc, LASTPHASE); 1681 if (lastphase == P_BUSFREE) { 1682 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1683 ahc_name(ahc), devinfo.channel, devinfo.target, 1684 ahc_inb(ahc, SCSISIGI)); 1685 restart_sequencer(ahc); 1686 return; 1687 } else { 1688 printf("%s:%c:%d: unknown scsi bus phase %x. " 1689 "Attempting to continue\n", 1690 ahc_name(ahc), devinfo.channel, devinfo.target, 1691 ahc_inb(ahc, SCSISIGI)); 1692 } 1693 break; 1694 } 1695 case BAD_STATUS: 1696 { 1697 u_int scb_index; 1698 struct hardware_scb *hscb; 1699 struct scsipi_xfer *xs; 1700 /* 1701 * The sequencer will notify us when a command 1702 * has an error that would be of interest to 1703 * the kernel. This allows us to leave the sequencer 1704 * running in the common case of command completes 1705 * without error. The sequencer will already have 1706 * dma'd the SCB back up to us, so we can reference 1707 * the in kernel copy directly. 1708 */ 1709 scb_index = ahc_inb(ahc, SCB_TAG); 1710 scb = &ahc->scb_data->scbarray[scb_index]; 1711 1712 /* ahc_print_scb(scb); */ 1713 1714 /* 1715 * Set the default return value to 0 (don't 1716 * send sense). The sense code will change 1717 * this if needed. 1718 */ 1719 ahc_outb(ahc, RETURN_1, 0); 1720 if (!(scb_index < ahc->scb_data->numscbs 1721 && (scb->flags & SCB_ACTIVE) != 0)) { 1722 printf("%s:%c:%d: ahc_intr - referenced scb " 1723 "not valid during seqint 0x%x scb(%d)\n", 1724 ahc_name(ahc), devinfo.channel, 1725 devinfo.target, intstat, scb_index); 1726 goto unpause; 1727 } 1728 1729 hscb = scb->hscb; 1730 xs = scb->xs; 1731 1732 /* Don't want to clobber the original sense code */ 1733 if ((scb->flags & SCB_SENSE) != 0) { 1734 /* 1735 * Clear the SCB_SENSE Flag and have 1736 * the sequencer do a normal command 1737 * complete. 1738 */ 1739 scb->flags &= ~SCB_SENSE; 1740 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1741 break; 1742 } 1743 /* Freeze the queue unit the client sees the error. */ 1744 ahc_freeze_devq(ahc, xs->xs_periph); 1745 ahc_freeze_ccb(scb); 1746 xs->status = hscb->status; 1747 switch (hscb->status) { 1748 case SCSI_STATUS_OK: 1749 printf("%s: Interrupted for status of 0???\n", 1750 ahc_name(ahc)); 1751 break; 1752 case SCSI_STATUS_CMD_TERMINATED: 1753 case SCSI_STATUS_CHECK_COND: 1754 #if defined(AHC_DEBUG) 1755 if (ahc_debug & AHC_SHOWSENSE) { 1756 scsipi_printaddr(xs->xs_periph); 1757 printf("Check Status, resid %d datalen %d\n", 1758 xs->resid, xs->datalen); 1759 } 1760 #endif 1761 1762 if (xs->error == XS_NOERROR && 1763 !(scb->flags & SCB_SENSE)) { 1764 struct ahc_dma_seg *sg; 1765 struct scsipi_sense *sc; 1766 struct ahc_initiator_tinfo *tinfo; 1767 struct tmode_tstate *tstate; 1768 1769 sg = scb->sg_list; 1770 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1771 /* 1772 * Save off the residual if there is one. 1773 */ 1774 if (hscb->residual_SG_count != 0) 1775 ahc_calc_residual(scb); 1776 else 1777 xs->resid = 0; 1778 1779 #ifdef AHC_DEBUG 1780 if (ahc_debug & AHC_SHOWSENSE) { 1781 scsipi_printaddr(xs->xs_periph); 1782 printf("Sending Sense\n"); 1783 } 1784 #endif 1785 sg->addr = ahc->scb_data->sense_busaddr + 1786 (hscb->tag*sizeof(struct scsipi_sense_data)); 1787 sg->len = sizeof (struct scsipi_sense_data); 1788 1789 sc->opcode = REQUEST_SENSE; 1790 sc->byte2 = SCB_LUN(scb) << 5; 1791 sc->unused[0] = 0; 1792 sc->unused[1] = 0; 1793 sc->length = sg->len; 1794 sc->control = 0; 1795 1796 /* 1797 * Would be nice to preserve DISCENB here, 1798 * but due to the way we page SCBs, we can't. 1799 */ 1800 hscb->control = 0; 1801 1802 /* 1803 * This request sense could be because the 1804 * the device lost power or in some other 1805 * way has lost our transfer negotiations. 1806 * Renegotiate if appropriate. Unit attention 1807 * errors will be reported before any data 1808 * phases occur. 1809 */ 1810 ahc_calc_residual(scb); 1811 #if defined(AHC_DEBUG) 1812 if (ahc_debug & AHC_SHOWSENSE) { 1813 scsipi_printaddr(xs->xs_periph); 1814 printf("Sense: datalen %d resid %d" 1815 "chan %d id %d targ %d\n", 1816 xs->datalen, xs->resid, 1817 devinfo.channel, devinfo.our_scsiid, 1818 devinfo.target); 1819 } 1820 #endif 1821 if (xs->datalen > 0 && 1822 xs->resid == xs->datalen) { 1823 tinfo = ahc_fetch_transinfo(ahc, 1824 devinfo.channel, 1825 devinfo.our_scsiid, 1826 devinfo.target, 1827 &tstate); 1828 ahc_update_target_msg_request(ahc, 1829 &devinfo, 1830 tinfo, 1831 /*force*/TRUE, 1832 /*paused*/TRUE); 1833 } 1834 hscb->status = 0; 1835 hscb->SG_count = 1; 1836 hscb->SG_pointer = scb->sg_list_phys; 1837 hscb->data = sg->addr; 1838 hscb->datalen = sg->len; 1839 hscb->cmdpointer = hscb->cmdstore_busaddr; 1840 hscb->cmdlen = sizeof(*sc); 1841 scb->sg_count = hscb->SG_count; 1842 ahc_swap_hscb(hscb); 1843 ahc_swap_sg(scb->sg_list); 1844 scb->flags |= SCB_SENSE; 1845 /* 1846 * Ensure the target is busy since this 1847 * will be an untagged request. 1848 */ 1849 ahc_busy_tcl(ahc, scb); 1850 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1851 1852 /* 1853 * Ensure we have enough time to actually 1854 * retrieve the sense. 1855 */ 1856 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1857 callout_reset(&scb->xs->xs_callout, 1858 5 * hz, ahc_timeout, scb); 1859 } 1860 } 1861 break; 1862 case SCSI_STATUS_QUEUE_FULL: 1863 case SCSI_STATUS_BUSY: 1864 xs->error = XS_BUSY; 1865 break; 1866 } 1867 break; 1868 } 1869 case TRACE_POINT: 1870 { 1871 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1872 ahc_inb(ahc, DFCNTRL)); 1873 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1874 ahc_inb(ahc, DFSTATUS)); 1875 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1876 ahc_inb(ahc, SSTAT0), 1877 ahc_inb(ahc, SCB_DATACNT)); 1878 break; 1879 } 1880 case HOST_MSG_LOOP: 1881 { 1882 /* 1883 * The sequencer has encountered a message phase 1884 * that requires host assistance for completion. 1885 * While handling the message phase(s), we will be 1886 * notified by the sequencer after each byte is 1887 * transferred so we can track bus phases. 1888 * 1889 * If this is the first time we've seen a HOST_MSG_LOOP, 1890 * initialize the state of the host message loop. 1891 */ 1892 if (ahc->msg_type == MSG_TYPE_NONE) { 1893 u_int bus_phase; 1894 1895 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1896 if (bus_phase != P_MESGIN 1897 && bus_phase != P_MESGOUT) { 1898 printf("ahc_intr: HOST_MSG_LOOP bad " 1899 "phase 0x%x\n", 1900 bus_phase); 1901 /* 1902 * Probably transitioned to bus free before 1903 * we got here. Just punt the message. 1904 */ 1905 ahc_clear_intstat(ahc); 1906 restart_sequencer(ahc); 1907 } 1908 1909 if (devinfo.role == ROLE_INITIATOR) { 1910 struct scb *scb; 1911 u_int scb_index; 1912 1913 scb_index = ahc_inb(ahc, SCB_TAG); 1914 scb = &ahc->scb_data->scbarray[scb_index]; 1915 1916 if (bus_phase == P_MESGOUT) 1917 ahc_setup_initiator_msgout(ahc, 1918 &devinfo, 1919 scb); 1920 else { 1921 ahc->msg_type = 1922 MSG_TYPE_INITIATOR_MSGIN; 1923 ahc->msgin_index = 0; 1924 } 1925 } else { 1926 if (bus_phase == P_MESGOUT) { 1927 ahc->msg_type = 1928 MSG_TYPE_TARGET_MSGOUT; 1929 ahc->msgin_index = 0; 1930 } else 1931 /* XXX Ever executed??? */ 1932 ahc_setup_target_msgin(ahc, &devinfo); 1933 } 1934 } 1935 1936 /* Pass a NULL path so that handlers generate their own */ 1937 ahc_handle_message_phase(ahc, /*path*/NULL); 1938 break; 1939 } 1940 case PERR_DETECTED: 1941 { 1942 /* 1943 * If we've cleared the parity error interrupt 1944 * but the sequencer still believes that SCSIPERR 1945 * is true, it must be that the parity error is 1946 * for the currently presented byte on the bus, 1947 * and we are not in a phase (data-in) where we will 1948 * eventually ack this byte. Ack the byte and 1949 * throw it away in the hope that the target will 1950 * take us to message out to deliver the appropriate 1951 * error message. 1952 */ 1953 if ((intstat & SCSIINT) == 0 1954 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1955 u_int curphase; 1956 1957 /* 1958 * The hardware will only let you ack bytes 1959 * if the expected phase in SCSISIGO matches 1960 * the current phase. Make sure this is 1961 * currently the case. 1962 */ 1963 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1964 ahc_outb(ahc, LASTPHASE, curphase); 1965 ahc_outb(ahc, SCSISIGO, curphase); 1966 ahc_inb(ahc, SCSIDATL); 1967 } 1968 break; 1969 } 1970 case DATA_OVERRUN: 1971 { 1972 /* 1973 * When the sequencer detects an overrun, it 1974 * places the controller in "BITBUCKET" mode 1975 * and allows the target to complete its transfer. 1976 * Unfortunately, none of the counters get updated 1977 * when the controller is in this mode, so we have 1978 * no way of knowing how large the overrun was. 1979 */ 1980 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1981 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1982 int i; 1983 1984 scb = &ahc->scb_data->scbarray[scbindex]; 1985 for (i = 0; i < num_phases; i++) { 1986 if (lastphase == phase_table[i].phase) 1987 break; 1988 } 1989 scsipi_printaddr(scb->xs->xs_periph); 1990 printf("data overrun detected %s." 1991 " Tag == 0x%x.\n", 1992 phase_table[i].phasemsg, 1993 scb->hscb->tag); 1994 scsipi_printaddr(scb->xs->xs_periph); 1995 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1996 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1997 scb->xs->datalen, scb->sg_count); 1998 if (scb->sg_count > 0) { 1999 for (i = 0; i < scb->sg_count; i++) { 2000 printf("sg[%d] - Addr 0x%x : Length %d\n", 2001 i, 2002 le32toh(scb->sg_list[i].addr), 2003 le32toh(scb->sg_list[i].len)); 2004 } 2005 } 2006 /* 2007 * Set this and it will take affect when the 2008 * target does a command complete. 2009 */ 2010 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2011 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2012 ahc_freeze_ccb(scb); 2013 break; 2014 } 2015 case TRACEPOINT: 2016 { 2017 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2018 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2019 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2020 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2021 printf("TRACEPOINT: CCHADDR = %x\n", 2022 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2023 | (ahc_inb(ahc, CCHADDR+2) << 16) 2024 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2025 #if 0 2026 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2027 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2028 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2029 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2030 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2031 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2032 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2033 ahc_inb(ahc, CCHADDR) 2034 | (ahc_inb(ahc, CCHADDR+1) << 8) 2035 | (ahc_inb(ahc, CCHADDR+2) << 16) 2036 | (ahc_inb(ahc, CCHADDR+3) << 24), 2037 ahc_inb(ahc, CCHCNT) 2038 | (ahc_inb(ahc, CCHCNT+1) << 8) 2039 | (ahc_inb(ahc, CCHCNT+2) << 16), 2040 ahc_inb(ahc, SCBPTR)); 2041 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2042 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2043 #if DDB > 0 2044 cpu_Debugger(); 2045 #endif 2046 #endif 2047 break; 2048 } 2049 #if NOT_YET 2050 /* XXX Fill these in later */ 2051 case MESG_BUFFER_BUSY: 2052 break; 2053 case MSGIN_PHASEMIS: 2054 break; 2055 #endif 2056 default: 2057 printf("ahc_intr: seqint, " 2058 "intstat == 0x%x, scsisigi = 0x%x\n", 2059 intstat, ahc_inb(ahc, SCSISIGI)); 2060 break; 2061 } 2062 2063 unpause: 2064 /* 2065 * The sequencer is paused immediately on 2066 * a SEQINT, so we should restart it when 2067 * we're done. 2068 */ 2069 unpause_sequencer(ahc); 2070 } 2071 2072 static void 2073 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2074 { 2075 u_int scb_index; 2076 u_int status; 2077 struct scb *scb; 2078 char cur_channel; 2079 char intr_channel; 2080 2081 if ((ahc->features & AHC_TWIN) != 0 2082 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2083 cur_channel = 'B'; 2084 else 2085 cur_channel = 'A'; 2086 intr_channel = cur_channel; 2087 2088 status = ahc_inb(ahc, SSTAT1); 2089 if (status == 0) { 2090 if ((ahc->features & AHC_TWIN) != 0) { 2091 /* Try the other channel */ 2092 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2093 status = ahc_inb(ahc, SSTAT1); 2094 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2095 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2096 } 2097 if (status == 0) { 2098 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2099 return; 2100 } 2101 } 2102 2103 scb_index = ahc_inb(ahc, SCB_TAG); 2104 if (scb_index < ahc->scb_data->numscbs) { 2105 scb = &ahc->scb_data->scbarray[scb_index]; 2106 if ((scb->flags & SCB_ACTIVE) == 0 2107 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2108 scb = NULL; 2109 } else 2110 scb = NULL; 2111 2112 if ((status & SCSIRSTI) != 0) { 2113 printf("%s: Someone reset channel %c\n", 2114 ahc_name(ahc), intr_channel); 2115 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2116 } else if ((status & SCSIPERR) != 0) { 2117 /* 2118 * Determine the bus phase and queue an appropriate message. 2119 * SCSIPERR is latched true as soon as a parity error 2120 * occurs. If the sequencer acked the transfer that 2121 * caused the parity error and the currently presented 2122 * transfer on the bus has correct parity, SCSIPERR will 2123 * be cleared by CLRSCSIPERR. Use this to determine if 2124 * we should look at the last phase the sequencer recorded, 2125 * or the current phase presented on the bus. 2126 */ 2127 u_int mesg_out; 2128 u_int curphase; 2129 u_int errorphase; 2130 u_int lastphase; 2131 int i; 2132 2133 lastphase = ahc_inb(ahc, LASTPHASE); 2134 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2135 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2136 /* 2137 * For all phases save DATA, the sequencer won't 2138 * automatically ack a byte that has a parity error 2139 * in it. So the only way that the current phase 2140 * could be 'data-in' is if the parity error is for 2141 * an already acked byte in the data phase. During 2142 * synchronous data-in transfers, we may actually 2143 * ack bytes before latching the current phase in 2144 * LASTPHASE, leading to the discrepancy between 2145 * curphase and lastphase. 2146 */ 2147 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2148 || curphase == P_DATAIN) 2149 errorphase = curphase; 2150 else 2151 errorphase = lastphase; 2152 2153 for (i = 0; i < num_phases; i++) { 2154 if (errorphase == phase_table[i].phase) 2155 break; 2156 } 2157 mesg_out = phase_table[i].mesg_out; 2158 if (scb != NULL) 2159 scsipi_printaddr(scb->xs->xs_periph); 2160 else 2161 printf("%s:%c:%d: ", ahc_name(ahc), 2162 intr_channel, 2163 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2164 2165 printf("parity error detected %s. " 2166 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2167 phase_table[i].phasemsg, 2168 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2169 ahc_inb(ahc, SCSIRATE)); 2170 2171 /* 2172 * We've set the hardware to assert ATN if we 2173 * get a parity error on "in" phases, so all we 2174 * need to do is stuff the message buffer with 2175 * the appropriate message. "In" phases have set 2176 * mesg_out to something other than MSG_NOP. 2177 */ 2178 if (mesg_out != MSG_NOOP) { 2179 if (ahc->msg_type != MSG_TYPE_NONE) 2180 ahc->send_msg_perror = TRUE; 2181 else 2182 ahc_outb(ahc, MSG_OUT, mesg_out); 2183 } 2184 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2185 unpause_sequencer(ahc); 2186 } else if ((status & BUSFREE) != 0 2187 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2188 /* 2189 * First look at what phase we were last in. 2190 * If its message out, chances are pretty good 2191 * that the busfree was in response to one of 2192 * our abort requests. 2193 */ 2194 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2195 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2196 u_int target = TCL_TARGET(saved_tcl); 2197 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2198 char channel = TCL_CHANNEL(ahc, saved_tcl); 2199 int printerror = 1; 2200 2201 ahc_outb(ahc, SCSISEQ, 2202 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2203 if (lastphase == P_MESGOUT) { 2204 u_int message; 2205 u_int tag; 2206 2207 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2208 tag = SCB_LIST_NULL; 2209 switch (message) { 2210 case MSG_ABORT_TAG: 2211 tag = scb->hscb->tag; 2212 /* FALLTRHOUGH */ 2213 case MSG_ABORT: 2214 scsipi_printaddr(scb->xs->xs_periph); 2215 printf("SCB %x - Abort %s Completed.\n", 2216 scb->hscb->tag, tag == SCB_LIST_NULL ? 2217 "" : "Tag"); 2218 ahc_abort_scbs(ahc, target, channel, 2219 TCL_LUN(saved_tcl), tag, 2220 ROLE_INITIATOR, 2221 XS_DRIVER_STUFFUP); 2222 printerror = 0; 2223 break; 2224 case MSG_BUS_DEV_RESET: 2225 { 2226 struct ahc_devinfo devinfo; 2227 2228 if (scb != NULL && 2229 (scb->xs->xs_control & XS_CTL_RESET) 2230 && ahc_match_scb(scb, target, channel, 2231 TCL_LUN(saved_tcl), 2232 SCB_LIST_NULL, 2233 ROLE_INITIATOR)) { 2234 ahcsetccbstatus(scb->xs, XS_NOERROR); 2235 } 2236 ahc_compile_devinfo(&devinfo, 2237 initiator_role_id, 2238 target, 2239 TCL_LUN(saved_tcl), 2240 channel, 2241 ROLE_INITIATOR); 2242 ahc_handle_devreset(ahc, &devinfo, 2243 XS_RESET, 2244 "Bus Device Reset", 2245 /*verbose_level*/0); 2246 printerror = 0; 2247 break; 2248 } 2249 default: 2250 break; 2251 } 2252 } 2253 if (printerror != 0) { 2254 int i; 2255 2256 if (scb != NULL) { 2257 u_int tag; 2258 2259 if ((scb->hscb->control & TAG_ENB) != 0) 2260 tag = scb->hscb->tag; 2261 else 2262 tag = SCB_LIST_NULL; 2263 ahc_abort_scbs(ahc, target, channel, 2264 SCB_LUN(scb), tag, 2265 ROLE_INITIATOR, 2266 XS_DRIVER_STUFFUP); 2267 scsipi_printaddr(scb->xs->xs_periph); 2268 } else { 2269 /* 2270 * We had not fully identified this connection, 2271 * so we cannot abort anything. 2272 */ 2273 printf("%s: ", ahc_name(ahc)); 2274 } 2275 for (i = 0; i < num_phases; i++) { 2276 if (lastphase == phase_table[i].phase) 2277 break; 2278 } 2279 printf("Unexpected busfree %s\n" 2280 "SEQADDR == 0x%x\n", 2281 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2282 | (ahc_inb(ahc, SEQADDR1) << 8)); 2283 } 2284 ahc_clear_msg_state(ahc); 2285 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2286 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2287 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2288 restart_sequencer(ahc); 2289 } else if ((status & SELTO) != 0) { 2290 u_int scbptr; 2291 2292 scbptr = ahc_inb(ahc, WAITING_SCBH); 2293 ahc_outb(ahc, SCBPTR, scbptr); 2294 scb_index = ahc_inb(ahc, SCB_TAG); 2295 2296 if (scb_index < ahc->scb_data->numscbs) { 2297 scb = &ahc->scb_data->scbarray[scb_index]; 2298 if ((scb->flags & SCB_ACTIVE) == 0) 2299 scb = NULL; 2300 } else 2301 scb = NULL; 2302 2303 if (scb == NULL) { 2304 printf("%s: ahc_intr - referenced scb not " 2305 "valid during SELTO scb(%d, %d)\n", 2306 ahc_name(ahc), scbptr, scb_index); 2307 } else { 2308 u_int tag; 2309 2310 tag = SCB_LIST_NULL; 2311 if ((scb->hscb->control & TAG_ENB) != 0) 2312 tag = scb->hscb->tag; 2313 2314 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2315 SCB_LUN(scb), tag, 2316 ROLE_INITIATOR, XS_SELTIMEOUT); 2317 } 2318 /* Stop the selection */ 2319 ahc_outb(ahc, SCSISEQ, 0); 2320 2321 /* No more pending messages */ 2322 ahc_clear_msg_state(ahc); 2323 2324 /* 2325 * Although the driver does not care about the 2326 * 'Selection in Progress' status bit, the busy 2327 * LED does. SELINGO is only cleared by a sucessful 2328 * selection, so we must manually clear it to ensure 2329 * the LED turns off just incase no future successful 2330 * selections occur (e.g. no devices on the bus). 2331 */ 2332 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2333 2334 /* Clear interrupt state */ 2335 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2336 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2337 restart_sequencer(ahc); 2338 } else { 2339 scsipi_printaddr(scb->xs->xs_periph); 2340 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2341 ahc_outb(ahc, CLRSINT1, status); 2342 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2343 unpause_sequencer(ahc); 2344 } 2345 } 2346 2347 static void 2348 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2349 { 2350 /* 2351 * We need to initiate transfer negotiations. 2352 * If our current and goal settings are identical, 2353 * we want to renegotiate due to a check condition. 2354 */ 2355 struct ahc_initiator_tinfo *tinfo; 2356 struct tmode_tstate *tstate; 2357 int dowide; 2358 int dosync; 2359 2360 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2361 devinfo->target, &tstate); 2362 dowide = tinfo->current.width != tinfo->goal.width; 2363 dosync = tinfo->current.period != tinfo->goal.period; 2364 2365 if (!dowide && !dosync) { 2366 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2367 dosync = tinfo->goal.period != 0; 2368 } 2369 2370 if (dowide) { 2371 ahc_construct_wdtr(ahc, tinfo->goal.width); 2372 } else if (dosync) { 2373 const struct ahc_syncrate *rate; 2374 u_int period; 2375 u_int offset; 2376 2377 period = tinfo->goal.period; 2378 rate = ahc_devlimited_syncrate(ahc, &period); 2379 offset = tinfo->goal.offset; 2380 ahc_validate_offset(ahc, rate, &offset, 2381 tinfo->current.width); 2382 ahc_construct_sdtr(ahc, period, offset); 2383 } else { 2384 panic("ahc_intr: AWAITING_MSG for negotiation, " 2385 "but no negotiation needed\n"); 2386 } 2387 } 2388 2389 static void 2390 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2391 struct scb *scb) 2392 { 2393 /* 2394 * To facilitate adding multiple messages together, 2395 * each routine should increment the index and len 2396 * variables instead of setting them explicitly. 2397 */ 2398 ahc->msgout_index = 0; 2399 ahc->msgout_len = 0; 2400 2401 if ((scb->flags & SCB_DEVICE_RESET) == 0 2402 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2403 u_int identify_msg; 2404 2405 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2406 if ((scb->hscb->control & DISCENB) != 0) 2407 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2408 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2409 ahc->msgout_len++; 2410 2411 if ((scb->hscb->control & TAG_ENB) != 0) { 2412 ahc->msgout_buf[ahc->msgout_index++] = 2413 scb->xs->xs_tag_type; 2414 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2415 ahc->msgout_len += 2; 2416 } 2417 } 2418 2419 if (scb->flags & SCB_DEVICE_RESET) { 2420 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2421 ahc->msgout_len++; 2422 scsipi_printaddr(scb->xs->xs_periph); 2423 printf("Bus Device Reset Message Sent\n"); 2424 } else if (scb->flags & SCB_ABORT) { 2425 if ((scb->hscb->control & TAG_ENB) != 0) 2426 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2427 else 2428 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2429 ahc->msgout_len++; 2430 scsipi_printaddr(scb->xs->xs_periph); 2431 printf("Abort Message Sent\n"); 2432 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2433 ahc_build_transfer_msg(ahc, devinfo); 2434 } else { 2435 printf("ahc_intr: AWAITING_MSG for an SCB that " 2436 "does not have a waiting message"); 2437 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2438 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2439 ahc_inb(ahc, MSG_OUT), scb->flags); 2440 } 2441 2442 /* 2443 * Clear the MK_MESSAGE flag from the SCB so we aren't 2444 * asked to send this message again. 2445 */ 2446 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2447 ahc->msgout_index = 0; 2448 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2449 } 2450 2451 static void 2452 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2453 { 2454 /* 2455 * To facilitate adding multiple messages together, 2456 * each routine should increment the index and len 2457 * variables instead of setting them explicitly. 2458 */ 2459 ahc->msgout_index = 0; 2460 ahc->msgout_len = 0; 2461 2462 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2463 ahc_build_transfer_msg(ahc, devinfo); 2464 else 2465 panic("ahc_intr: AWAITING target message with no message"); 2466 2467 ahc->msgout_index = 0; 2468 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2469 } 2470 2471 static int 2472 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2473 { 2474 /* 2475 * What we care about here is if we had an 2476 * outstanding SDTR or WDTR message for this 2477 * target. If we did, this is a signal that 2478 * the target is refusing negotiation. 2479 */ 2480 struct scb *scb; 2481 u_int scb_index; 2482 u_int last_msg; 2483 int response = 0; 2484 2485 scb_index = ahc_inb(ahc, SCB_TAG); 2486 scb = &ahc->scb_data->scbarray[scb_index]; 2487 2488 /* Might be necessary */ 2489 last_msg = ahc_inb(ahc, LAST_MSG); 2490 2491 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2492 struct ahc_initiator_tinfo *tinfo; 2493 struct tmode_tstate *tstate; 2494 2495 #ifdef AHC_DEBUG_NEG 2496 /* note 8bit xfers */ 2497 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2498 "8bit transfers\n", ahc_name(ahc), 2499 devinfo->channel, devinfo->target); 2500 #endif 2501 ahc_set_width(ahc, devinfo, 2502 MSG_EXT_WDTR_BUS_8_BIT, 2503 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2504 /*paused*/TRUE, /*done*/TRUE); 2505 /* 2506 * No need to clear the sync rate. If the target 2507 * did not accept the command, our syncrate is 2508 * unaffected. If the target started the negotiation, 2509 * but rejected our response, we already cleared the 2510 * sync rate before sending our WDTR. 2511 */ 2512 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2513 devinfo->our_scsiid, 2514 devinfo->target, &tstate); 2515 if (tinfo->goal.period) { 2516 u_int period; 2517 2518 /* Start the sync negotiation */ 2519 period = tinfo->goal.period; 2520 ahc_devlimited_syncrate(ahc, &period); 2521 ahc->msgout_index = 0; 2522 ahc->msgout_len = 0; 2523 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2524 ahc->msgout_index = 0; 2525 response = 1; 2526 } else 2527 ahc_update_xfer_mode(ahc, devinfo); 2528 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2529 /* note asynch xfers and clear flag */ 2530 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2531 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2532 /*paused*/TRUE, /*done*/TRUE); 2533 #ifdef AHC_DEBUG_NEG 2534 printf("%s:%c:%d: refuses synchronous negotiation. " 2535 "Using asynchronous transfers\n", 2536 ahc_name(ahc), 2537 devinfo->channel, devinfo->target); 2538 #endif 2539 ahc_update_xfer_mode(ahc, devinfo); 2540 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2541 printf("%s:%c:%d: refuses tagged commands. Performing " 2542 "non-tagged I/O\n", ahc_name(ahc), 2543 devinfo->channel, devinfo->target); 2544 2545 ahc_set_tags(ahc, devinfo, FALSE); 2546 ahc_update_xfer_mode(ahc, devinfo); 2547 2548 /* 2549 * Resend the identify for this CCB as the target 2550 * may believe that the selection is invalid otherwise. 2551 */ 2552 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2553 & ~MSG_SIMPLE_Q_TAG); 2554 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2555 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2556 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2557 2558 /* 2559 * Requeue all tagged commands for this target 2560 * currently in our posession so they can be 2561 * converted to untagged commands. 2562 */ 2563 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2564 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2565 ROLE_INITIATOR, SCB_REQUEUE, 2566 SEARCH_COMPLETE); 2567 } else { 2568 /* 2569 * Otherwise, we ignore it. 2570 */ 2571 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2572 ahc_name(ahc), devinfo->channel, devinfo->target, 2573 last_msg); 2574 } 2575 return (response); 2576 } 2577 2578 static void 2579 ahc_clear_msg_state(struct ahc_softc *ahc) 2580 { 2581 ahc->msgout_len = 0; 2582 ahc->msgin_index = 0; 2583 ahc->msg_type = MSG_TYPE_NONE; 2584 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2585 } 2586 2587 static void 2588 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2589 { 2590 struct ahc_devinfo devinfo; 2591 u_int bus_phase; 2592 int end_session; 2593 2594 ahc_fetch_devinfo(ahc, &devinfo); 2595 end_session = FALSE; 2596 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2597 2598 reswitch: 2599 switch (ahc->msg_type) { 2600 case MSG_TYPE_INITIATOR_MSGOUT: 2601 { 2602 int lastbyte; 2603 int phasemis; 2604 int msgdone; 2605 2606 if (ahc->msgout_len == 0) 2607 panic("REQINIT interrupt with no active message"); 2608 2609 phasemis = bus_phase != P_MESGOUT; 2610 if (phasemis) { 2611 if (bus_phase == P_MESGIN) { 2612 /* 2613 * Change gears and see if 2614 * this messages is of interest to 2615 * us or should be passed back to 2616 * the sequencer. 2617 */ 2618 ahc_outb(ahc, CLRSINT1, CLRATNO); 2619 ahc->send_msg_perror = FALSE; 2620 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2621 ahc->msgin_index = 0; 2622 goto reswitch; 2623 } 2624 end_session = TRUE; 2625 break; 2626 } 2627 2628 if (ahc->send_msg_perror) { 2629 ahc_outb(ahc, CLRSINT1, CLRATNO); 2630 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2631 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2632 break; 2633 } 2634 2635 msgdone = ahc->msgout_index == ahc->msgout_len; 2636 if (msgdone) { 2637 /* 2638 * The target has requested a retry. 2639 * Re-assert ATN, reset our message index to 2640 * 0, and try again. 2641 */ 2642 ahc->msgout_index = 0; 2643 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2644 } 2645 2646 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2647 if (lastbyte) { 2648 /* Last byte is signified by dropping ATN */ 2649 ahc_outb(ahc, CLRSINT1, CLRATNO); 2650 } 2651 2652 /* 2653 * Clear our interrupt status and present 2654 * the next byte on the bus. 2655 */ 2656 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2657 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2658 break; 2659 } 2660 case MSG_TYPE_INITIATOR_MSGIN: 2661 { 2662 int phasemis; 2663 int message_done; 2664 2665 phasemis = bus_phase != P_MESGIN; 2666 2667 if (phasemis) { 2668 ahc->msgin_index = 0; 2669 if (bus_phase == P_MESGOUT 2670 && (ahc->send_msg_perror == TRUE 2671 || (ahc->msgout_len != 0 2672 && ahc->msgout_index == 0))) { 2673 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2674 goto reswitch; 2675 } 2676 end_session = TRUE; 2677 break; 2678 } 2679 2680 /* Pull the byte in without acking it */ 2681 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2682 2683 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2684 2685 if (message_done) { 2686 /* 2687 * Clear our incoming message buffer in case there 2688 * is another message following this one. 2689 */ 2690 ahc->msgin_index = 0; 2691 2692 /* 2693 * If this message illicited a response, 2694 * assert ATN so the target takes us to the 2695 * message out phase. 2696 */ 2697 if (ahc->msgout_len != 0) 2698 ahc_outb(ahc, SCSISIGO, 2699 ahc_inb(ahc, SCSISIGO) | ATNO); 2700 } else 2701 ahc->msgin_index++; 2702 2703 /* Ack the byte */ 2704 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2705 ahc_inb(ahc, SCSIDATL); 2706 break; 2707 } 2708 case MSG_TYPE_TARGET_MSGIN: 2709 { 2710 int msgdone; 2711 int msgout_request; 2712 2713 if (ahc->msgout_len == 0) 2714 panic("Target MSGIN with no active message"); 2715 2716 /* 2717 * If we interrupted a mesgout session, the initiator 2718 * will not know this until our first REQ. So, we 2719 * only honor mesgout requests after we've sent our 2720 * first byte. 2721 */ 2722 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2723 && ahc->msgout_index > 0) 2724 msgout_request = TRUE; 2725 else 2726 msgout_request = FALSE; 2727 2728 if (msgout_request) { 2729 2730 /* 2731 * Change gears and see if 2732 * this messages is of interest to 2733 * us or should be passed back to 2734 * the sequencer. 2735 */ 2736 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2737 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2738 ahc->msgin_index = 0; 2739 /* Dummy read to REQ for first byte */ 2740 ahc_inb(ahc, SCSIDATL); 2741 ahc_outb(ahc, SXFRCTL0, 2742 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2743 break; 2744 } 2745 2746 msgdone = ahc->msgout_index == ahc->msgout_len; 2747 if (msgdone) { 2748 ahc_outb(ahc, SXFRCTL0, 2749 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2750 end_session = TRUE; 2751 break; 2752 } 2753 2754 /* 2755 * Present the next byte on the bus. 2756 */ 2757 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2758 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2759 break; 2760 } 2761 case MSG_TYPE_TARGET_MSGOUT: 2762 { 2763 int lastbyte; 2764 int msgdone; 2765 2766 /* 2767 * The initiator signals that this is 2768 * the last byte by dropping ATN. 2769 */ 2770 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2771 2772 /* 2773 * Read the latched byte, but turn off SPIOEN first 2774 * so that we don't inadvertantly cause a REQ for the 2775 * next byte. 2776 */ 2777 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2778 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2779 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2780 if (msgdone == MSGLOOP_TERMINATED) { 2781 /* 2782 * The message is *really* done in that it caused 2783 * us to go to bus free. The sequencer has already 2784 * been reset at this point, so pull the ejection 2785 * handle. 2786 */ 2787 return; 2788 } 2789 2790 ahc->msgin_index++; 2791 2792 /* 2793 * XXX Read spec about initiator dropping ATN too soon 2794 * and use msgdone to detect it. 2795 */ 2796 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2797 ahc->msgin_index = 0; 2798 2799 /* 2800 * If this message illicited a response, transition 2801 * to the Message in phase and send it. 2802 */ 2803 if (ahc->msgout_len != 0) { 2804 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2805 ahc_outb(ahc, SXFRCTL0, 2806 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2807 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2808 ahc->msgin_index = 0; 2809 break; 2810 } 2811 } 2812 2813 if (lastbyte) 2814 end_session = TRUE; 2815 else { 2816 /* Ask for the next byte. */ 2817 ahc_outb(ahc, SXFRCTL0, 2818 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2819 } 2820 2821 break; 2822 } 2823 default: 2824 panic("Unknown REQINIT message type"); 2825 } 2826 2827 if (end_session) { 2828 ahc_clear_msg_state(ahc); 2829 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2830 } else 2831 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2832 } 2833 2834 /* 2835 * See if we sent a particular extended message to the target. 2836 * If "full" is true, the target saw the full message. 2837 * If "full" is false, the target saw at least the first 2838 * byte of the message. 2839 */ 2840 static int 2841 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2842 { 2843 int found; 2844 int index; 2845 2846 found = FALSE; 2847 index = 0; 2848 2849 while (index < ahc->msgout_len) { 2850 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2851 2852 /* Found a candidate */ 2853 if (ahc->msgout_buf[index+2] == msgtype) { 2854 u_int end_index; 2855 2856 end_index = index + 1 2857 + ahc->msgout_buf[index + 1]; 2858 if (full) { 2859 if (ahc->msgout_index > end_index) 2860 found = TRUE; 2861 } else if (ahc->msgout_index > index) 2862 found = TRUE; 2863 } 2864 break; 2865 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2866 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2867 2868 /* Skip tag type and tag id or residue param*/ 2869 index += 2; 2870 } else { 2871 /* Single byte message */ 2872 index++; 2873 } 2874 } 2875 return (found); 2876 } 2877 2878 static int 2879 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2880 struct ahc_devinfo *devinfo) 2881 { 2882 struct ahc_initiator_tinfo *tinfo; 2883 struct tmode_tstate *tstate; 2884 int reject; 2885 int done; 2886 int response; 2887 u_int targ_scsirate; 2888 2889 done = MSGLOOP_IN_PROG; 2890 response = FALSE; 2891 reject = FALSE; 2892 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2893 devinfo->target, &tstate); 2894 targ_scsirate = tinfo->scsirate; 2895 2896 /* 2897 * Parse as much of the message as is available, 2898 * rejecting it if we don't support it. When 2899 * the entire message is available and has been 2900 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2901 * that we have parsed an entire message. 2902 * 2903 * In the case of extended messages, we accept the length 2904 * byte outright and perform more checking once we know the 2905 * extended message type. 2906 */ 2907 switch (ahc->msgin_buf[0]) { 2908 case MSG_MESSAGE_REJECT: 2909 response = ahc_handle_msg_reject(ahc, devinfo); 2910 /* FALLTHROUGH */ 2911 case MSG_NOOP: 2912 done = MSGLOOP_MSGCOMPLETE; 2913 break; 2914 case MSG_IGN_WIDE_RESIDUE: 2915 { 2916 /* Wait for the whole message */ 2917 if (ahc->msgin_index >= 1) { 2918 if (ahc->msgin_buf[1] != 1 2919 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2920 reject = TRUE; 2921 done = MSGLOOP_MSGCOMPLETE; 2922 } else 2923 ahc_handle_ign_wide_residue(ahc, devinfo); 2924 } 2925 break; 2926 } 2927 case MSG_EXTENDED: 2928 { 2929 /* Wait for enough of the message to begin validation */ 2930 if (ahc->msgin_index < 2) 2931 break; 2932 switch (ahc->msgin_buf[2]) { 2933 case MSG_EXT_SDTR: 2934 { 2935 const struct ahc_syncrate *syncrate; 2936 u_int period; 2937 u_int offset; 2938 u_int saved_offset; 2939 2940 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2941 reject = TRUE; 2942 break; 2943 } 2944 2945 /* 2946 * Wait until we have both args before validating 2947 * and acting on this message. 2948 * 2949 * Add one to MSG_EXT_SDTR_LEN to account for 2950 * the extended message preamble. 2951 */ 2952 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2953 break; 2954 2955 period = ahc->msgin_buf[3]; 2956 saved_offset = offset = ahc->msgin_buf[4]; 2957 syncrate = ahc_devlimited_syncrate(ahc, &period); 2958 ahc_validate_offset(ahc, syncrate, &offset, 2959 targ_scsirate & WIDEXFER); 2960 ahc_set_syncrate(ahc, devinfo, 2961 syncrate, period, offset, 2962 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2963 /*paused*/TRUE, /*done*/TRUE); 2964 ahc_update_xfer_mode(ahc, devinfo); 2965 2966 /* 2967 * See if we initiated Sync Negotiation 2968 * and didn't have to fall down to async 2969 * transfers. 2970 */ 2971 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2972 /* We started it */ 2973 if (saved_offset != offset) { 2974 /* Went too low - force async */ 2975 reject = TRUE; 2976 } 2977 } else { 2978 /* 2979 * Send our own SDTR in reply 2980 */ 2981 ahc->msgout_index = 0; 2982 ahc->msgout_len = 0; 2983 ahc_construct_sdtr(ahc, period, offset); 2984 ahc->msgout_index = 0; 2985 response = TRUE; 2986 } 2987 done = MSGLOOP_MSGCOMPLETE; 2988 break; 2989 } 2990 case MSG_EXT_WDTR: 2991 { 2992 u_int bus_width; 2993 u_int sending_reply; 2994 2995 sending_reply = FALSE; 2996 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2997 reject = TRUE; 2998 break; 2999 } 3000 3001 /* 3002 * Wait until we have our arg before validating 3003 * and acting on this message. 3004 * 3005 * Add one to MSG_EXT_WDTR_LEN to account for 3006 * the extended message preamble. 3007 */ 3008 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3009 break; 3010 3011 bus_width = ahc->msgin_buf[3]; 3012 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3013 /* 3014 * Don't send a WDTR back to the 3015 * target, since we asked first. 3016 */ 3017 switch (bus_width){ 3018 default: 3019 /* 3020 * How can we do anything greater 3021 * than 16bit transfers on a 16bit 3022 * bus? 3023 */ 3024 reject = TRUE; 3025 printf("%s: target %d requested %dBit " 3026 "transfers. Rejecting...\n", 3027 ahc_name(ahc), devinfo->target, 3028 8 * (0x01 << bus_width)); 3029 /* FALLTHROUGH */ 3030 case MSG_EXT_WDTR_BUS_8_BIT: 3031 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3032 break; 3033 case MSG_EXT_WDTR_BUS_16_BIT: 3034 break; 3035 } 3036 } else { 3037 /* 3038 * Send our own WDTR in reply 3039 */ 3040 switch (bus_width) { 3041 default: 3042 if (ahc->features & AHC_WIDE) { 3043 /* Respond Wide */ 3044 bus_width = 3045 MSG_EXT_WDTR_BUS_16_BIT; 3046 break; 3047 } 3048 /* FALLTHROUGH */ 3049 case MSG_EXT_WDTR_BUS_8_BIT: 3050 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3051 break; 3052 } 3053 ahc->msgout_index = 0; 3054 ahc->msgout_len = 0; 3055 ahc_construct_wdtr(ahc, bus_width); 3056 ahc->msgout_index = 0; 3057 response = TRUE; 3058 sending_reply = TRUE; 3059 } 3060 ahc_set_width(ahc, devinfo, bus_width, 3061 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3062 /*paused*/TRUE, /*done*/TRUE); 3063 3064 /* After a wide message, we are async */ 3065 ahc_set_syncrate(ahc, devinfo, 3066 /*syncrate*/NULL, /*period*/0, 3067 /*offset*/0, AHC_TRANS_ACTIVE, 3068 /*paused*/TRUE, /*done*/FALSE); 3069 if (sending_reply == FALSE && reject == FALSE) { 3070 3071 if (tinfo->goal.period) { 3072 const struct ahc_syncrate *rate; 3073 u_int period; 3074 u_int offset; 3075 3076 /* Start the sync negotiation */ 3077 period = tinfo->goal.period; 3078 rate = ahc_devlimited_syncrate(ahc, 3079 &period); 3080 offset = tinfo->goal.offset; 3081 ahc_validate_offset(ahc, rate, &offset, 3082 tinfo->current.width); 3083 ahc->msgout_index = 0; 3084 ahc->msgout_len = 0; 3085 ahc_construct_sdtr(ahc, period, offset); 3086 ahc->msgout_index = 0; 3087 response = TRUE; 3088 } else 3089 ahc_update_xfer_mode(ahc, devinfo); 3090 } 3091 done = MSGLOOP_MSGCOMPLETE; 3092 break; 3093 } 3094 default: 3095 /* Unknown extended message. Reject it. */ 3096 reject = TRUE; 3097 break; 3098 } 3099 break; 3100 } 3101 case MSG_BUS_DEV_RESET: 3102 ahc_handle_devreset(ahc, devinfo, 3103 XS_RESET, "Bus Device Reset Received", 3104 /*verbose_level*/0); 3105 restart_sequencer(ahc); 3106 done = MSGLOOP_TERMINATED; 3107 break; 3108 case MSG_ABORT_TAG: 3109 case MSG_ABORT: 3110 case MSG_CLEAR_QUEUE: 3111 /* Target mode messages */ 3112 if (devinfo->role != ROLE_TARGET) { 3113 reject = TRUE; 3114 break; 3115 } 3116 #if AHC_TARGET_MODE 3117 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3118 devinfo->lun, 3119 ahc->msgin_buf[0] == MSG_ABORT_TAG 3120 ? SCB_LIST_NULL 3121 : ahc_inb(ahc, INITIATOR_TAG), 3122 ROLE_TARGET, XS_DRIVER_STUFFUP); 3123 3124 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3125 if (tstate != NULL) { 3126 struct tmode_lstate* lstate; 3127 3128 lstate = tstate->enabled_luns[devinfo->lun]; 3129 if (lstate != NULL) { 3130 ahc_queue_lstate_event(ahc, lstate, 3131 devinfo->our_scsiid, 3132 ahc->msgin_buf[0], 3133 /*arg*/0); 3134 ahc_send_lstate_events(ahc, lstate); 3135 } 3136 } 3137 done = MSGLOOP_MSGCOMPLETE; 3138 #else 3139 panic("ahc: got target mode message"); 3140 #endif 3141 break; 3142 case MSG_TERM_IO_PROC: 3143 default: 3144 reject = TRUE; 3145 break; 3146 } 3147 3148 if (reject) { 3149 /* 3150 * Setup to reject the message. 3151 */ 3152 ahc->msgout_index = 0; 3153 ahc->msgout_len = 1; 3154 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3155 done = MSGLOOP_MSGCOMPLETE; 3156 response = TRUE; 3157 } 3158 3159 if (done != MSGLOOP_IN_PROG && !response) 3160 /* Clear the outgoing message buffer */ 3161 ahc->msgout_len = 0; 3162 3163 return (done); 3164 } 3165 3166 static void 3167 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3168 { 3169 u_int scb_index; 3170 struct scb *scb; 3171 3172 scb_index = ahc_inb(ahc, SCB_TAG); 3173 scb = &ahc->scb_data->scbarray[scb_index]; 3174 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3175 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3176 /* 3177 * Ignore the message if we haven't 3178 * seen an appropriate data phase yet. 3179 */ 3180 } else { 3181 /* 3182 * If the residual occurred on the last 3183 * transfer and the transfer request was 3184 * expected to end on an odd count, do 3185 * nothing. Otherwise, subtract a byte 3186 * and update the residual count accordingly. 3187 */ 3188 u_int resid_sgcnt; 3189 3190 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3191 if (resid_sgcnt == 0 3192 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3193 /* 3194 * If the residual occurred on the last 3195 * transfer and the transfer request was 3196 * expected to end on an odd count, do 3197 * nothing. 3198 */ 3199 } else { 3200 u_int data_cnt; 3201 u_int32_t data_addr; 3202 u_int sg_index; 3203 3204 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3205 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3206 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3207 3208 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3209 | (ahc_inb(ahc, SHADDR + 2) << 16) 3210 | (ahc_inb(ahc, SHADDR + 1) << 8) 3211 | (ahc_inb(ahc, SHADDR)); 3212 3213 data_cnt += 1; 3214 data_addr -= 1; 3215 3216 sg_index = scb->sg_count - resid_sgcnt; 3217 3218 if (sg_index != 0 3219 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3220 u_int32_t sg_addr; 3221 3222 sg_index--; 3223 data_cnt = 1; 3224 data_addr = le32toh(scb->sg_list[sg_index].addr) 3225 + le32toh(scb->sg_list[sg_index].len) 3226 - 1; 3227 3228 /* 3229 * The physical address base points to the 3230 * second entry as it is always used for 3231 * calculating the "next S/G pointer". 3232 */ 3233 sg_addr = scb->sg_list_phys 3234 + (sg_index* sizeof(*scb->sg_list)); 3235 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3236 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3237 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3238 ahc_outb(ahc, SG_NEXT, sg_addr); 3239 } 3240 3241 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3242 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3243 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3244 3245 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3246 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3247 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3248 ahc_outb(ahc, SHADDR, data_addr); 3249 } 3250 } 3251 } 3252 3253 static void 3254 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3255 int status, char *message, 3256 int verbose_level) 3257 { 3258 int found; 3259 3260 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3261 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3262 status); 3263 3264 /* 3265 * Go back to async/narrow transfers and renegotiate. 3266 * ahc_set_width and ahc_set_syncrate can cope with NULL 3267 * paths. 3268 */ 3269 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3270 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3271 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3272 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3273 /*paused*/TRUE, /*done*/FALSE); 3274 ahc_update_xfer_mode(ahc, devinfo); 3275 3276 if (message != NULL && (verbose_level <= 0)) 3277 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3278 message, devinfo->channel, devinfo->target, found); 3279 } 3280 3281 /* 3282 * We have an scb which has been processed by the 3283 * adaptor, now we look to see how the operation 3284 * went. 3285 */ 3286 static void 3287 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3288 { 3289 struct scsipi_xfer *xs; 3290 struct scsipi_periph *periph; 3291 int requeue = 0; 3292 int target; 3293 3294 3295 xs = scb->xs; 3296 periph = xs->xs_periph; 3297 LIST_REMOVE(scb, plinks); 3298 3299 callout_stop(&scb->xs->xs_callout); 3300 3301 #ifdef AHC_DEBUG 3302 if (ahc_debug & AHC_SHOWCMDS) { 3303 scsipi_printaddr(periph); 3304 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3305 scb->hscb->tag); 3306 } 3307 #endif 3308 3309 target = periph->periph_target; 3310 3311 if (xs->datalen) { 3312 int op; 3313 3314 if (xs->xs_control & XS_CTL_DATA_IN) 3315 op = BUS_DMASYNC_POSTREAD; 3316 else 3317 op = BUS_DMASYNC_POSTWRITE; 3318 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3319 scb->dmamap->dm_mapsize, op); 3320 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3321 } 3322 3323 /* 3324 * Unbusy this target/channel/lun. 3325 * XXX if we are holding two commands per lun, 3326 * send the next command. 3327 */ 3328 if (!(scb->hscb->control & TAG_ENB)) 3329 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3330 3331 /* 3332 * If the recovery SCB completes, we have to be 3333 * out of our timeout. 3334 */ 3335 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3336 3337 struct scb *scbp; 3338 3339 /* 3340 * We were able to complete the command successfully, 3341 * so reinstate the timeouts for all other pending 3342 * commands. 3343 */ 3344 scbp = ahc->pending_ccbs.lh_first; 3345 while (scbp != NULL) { 3346 struct scsipi_xfer *txs = scbp->xs; 3347 3348 if (!(txs->xs_control & XS_CTL_POLL)) { 3349 callout_reset(&scbp->xs->xs_callout, 3350 (scbp->xs->timeout > 1000000) ? 3351 (scbp->xs->timeout / 1000) * hz : 3352 (scbp->xs->timeout * hz) / 1000, 3353 ahc_timeout, scbp); 3354 } 3355 scbp = LIST_NEXT(scbp, plinks); 3356 } 3357 3358 /* 3359 * Ensure that we didn't put a second instance of this 3360 * SCB into the QINFIFO. 3361 */ 3362 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3363 SCB_LUN(scb), scb->hscb->tag, 3364 ROLE_INITIATOR, /*status*/0, 3365 SEARCH_REMOVE); 3366 if (xs->error != XS_NOERROR) 3367 ahcsetccbstatus(xs, XS_TIMEOUT); 3368 scsipi_printaddr(xs->xs_periph); 3369 printf("no longer in timeout, status = %x\n", xs->status); 3370 } 3371 3372 if (xs->error != XS_NOERROR) { 3373 /* Don't clobber any existing error state */ 3374 } else if ((scb->flags & SCB_SENSE) != 0) { 3375 /* 3376 * We performed autosense retrieval. 3377 * 3378 * zero the sense data before having 3379 * the drive fill it. The SCSI spec mandates 3380 * that any untransferred data should be 3381 * assumed to be zero. Complete the 'bounce' 3382 * of sense information through buffers accessible 3383 * via bus-space by copying it into the clients 3384 * csio. 3385 */ 3386 memset(&xs->sense.scsi_sense, 0, sizeof(xs->sense.scsi_sense)); 3387 memcpy(&xs->sense.scsi_sense, 3388 &ahc->scb_data->sense[scb->hscb->tag], 3389 le32toh(scb->sg_list->len)); 3390 xs->error = XS_SENSE; 3391 } 3392 if (scb->flags & SCB_FREEZE_QUEUE) { 3393 scsipi_periph_thaw(periph, 1); 3394 scb->flags &= ~SCB_FREEZE_QUEUE; 3395 } 3396 3397 requeue = scb->flags & SCB_REQUEUE; 3398 ahcfreescb(ahc, scb); 3399 3400 if (requeue) { 3401 xs->error = XS_REQUEUE; 3402 } 3403 scsipi_done(xs); 3404 } 3405 3406 /* 3407 * Determine the number of SCBs available on the controller 3408 */ 3409 int 3410 ahc_probe_scbs(struct ahc_softc *ahc) { 3411 int i; 3412 3413 for (i = 0; i < AHC_SCB_MAX; i++) { 3414 ahc_outb(ahc, SCBPTR, i); 3415 ahc_outb(ahc, SCB_CONTROL, i); 3416 if (ahc_inb(ahc, SCB_CONTROL) != i) 3417 break; 3418 ahc_outb(ahc, SCBPTR, 0); 3419 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3420 break; 3421 } 3422 return (i); 3423 } 3424 3425 /* 3426 * Start the board, ready for normal operation 3427 */ 3428 int 3429 ahc_init(struct ahc_softc *ahc) 3430 { 3431 int max_targ = 15; 3432 int i; 3433 int term; 3434 u_int scsi_conf; 3435 u_int scsiseq_template; 3436 u_int ultraenb; 3437 u_int discenable; 3438 u_int tagenable; 3439 size_t driver_data_size; 3440 u_int32_t physaddr; 3441 3442 #ifdef AHC_PRINT_SRAM 3443 printf("Scratch Ram:"); 3444 for (i = 0x20; i < 0x5f; i++) { 3445 if (((i % 8) == 0) && (i != 0)) { 3446 printf ("\n "); 3447 } 3448 printf (" 0x%x", ahc_inb(ahc, i)); 3449 } 3450 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3451 for (i = 0x70; i < 0x7f; i++) { 3452 if (((i % 8) == 0) && (i != 0)) { 3453 printf ("\n "); 3454 } 3455 printf (" 0x%x", ahc_inb(ahc, i)); 3456 } 3457 } 3458 printf ("\n"); 3459 #endif 3460 3461 /* 3462 * Assume we have a board at this stage and it has been reset. 3463 */ 3464 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3465 ahc->our_id = ahc->our_id_b = 7; 3466 3467 /* 3468 * Default to allowing initiator operations. 3469 */ 3470 ahc->flags |= AHC_INITIATORMODE; 3471 3472 /* 3473 * DMA tag for our command fifos and other data in system memory 3474 * the card's sequencer must be able to access. For initiator 3475 * roles, we need to allocate space for the qinfifo, qoutfifo, 3476 * and untagged_scb arrays each of which are composed of 256 3477 * 1 byte elements. When providing for the target mode role, 3478 * we additionally must provide space for the incoming target 3479 * command fifo. 3480 */ 3481 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3482 3483 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3484 ahc->sc_dmaflags, 3485 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3486 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3487 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3488 return (ENOMEM); 3489 3490 ahc->init_level++; 3491 3492 /* Allocate SCB data now that parent_dmat is initialized */ 3493 if (ahc->scb_data->maxhscbs == 0) 3494 if (ahcinitscbdata(ahc) != 0) 3495 return (ENOMEM); 3496 3497 ahc->qinfifo = &ahc->qoutfifo[256]; 3498 ahc->untagged_scbs = &ahc->qinfifo[256]; 3499 /* There are no untagged SCBs active yet. */ 3500 for (i = 0; i < 256; i++) 3501 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3502 3503 /* All of our queues are empty */ 3504 for (i = 0; i < 256; i++) 3505 ahc->qoutfifo[i] = SCB_LIST_NULL; 3506 3507 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3508 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3509 3510 /* 3511 * Allocate a tstate to house information for our 3512 * initiator presence on the bus as well as the user 3513 * data for any target mode initiator. 3514 */ 3515 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3516 printf("%s: unable to allocate tmode_tstate. " 3517 "Failing attach\n", ahc_name(ahc)); 3518 return (-1); 3519 } 3520 3521 if ((ahc->features & AHC_TWIN) != 0) { 3522 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3523 printf("%s: unable to allocate tmode_tstate. " 3524 "Failing attach\n", ahc_name(ahc)); 3525 return (-1); 3526 } 3527 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3528 ahc->our_id, ahc->our_id_b, 3529 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3530 } else { 3531 if ((ahc->features & AHC_WIDE) != 0) { 3532 printf("Wide "); 3533 } else { 3534 printf("Single "); 3535 } 3536 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3537 } 3538 3539 ahc_outb(ahc, SEQ_FLAGS, 0); 3540 3541 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3542 ahc->flags |= AHC_PAGESCBS; 3543 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3544 } else { 3545 ahc->flags &= ~AHC_PAGESCBS; 3546 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3547 } 3548 3549 #ifdef AHC_DEBUG 3550 if (ahc_debug & AHC_SHOWMISC) { 3551 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 3552 "ahc_dma %lu bytes\n", 3553 ahc_name(ahc), 3554 (unsigned long) sizeof(struct hardware_scb), 3555 (unsigned long) sizeof(struct scb), 3556 (unsigned long) sizeof(struct ahc_dma_seg)); 3557 } 3558 #endif /* AHC_DEBUG */ 3559 3560 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3561 if (ahc->features & AHC_TWIN) { 3562 3563 /* 3564 * The device is gated to channel B after a chip reset, 3565 * so set those values first 3566 */ 3567 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3568 if ((ahc->features & AHC_ULTRA2) != 0) 3569 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3570 else 3571 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3572 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3573 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3574 |term|ENSTIMER|ACTNEGEN); 3575 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3576 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3577 3578 if ((scsi_conf & RESET_SCSI) != 0 3579 && (ahc->flags & AHC_INITIATORMODE) != 0) 3580 ahc->flags |= AHC_RESET_BUS_B; 3581 3582 /* Select Channel A */ 3583 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3584 } 3585 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3586 if ((ahc->features & AHC_ULTRA2) != 0) 3587 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3588 else 3589 ahc_outb(ahc, SCSIID, ahc->our_id); 3590 scsi_conf = ahc_inb(ahc, SCSICONF); 3591 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3592 |term 3593 |ENSTIMER|ACTNEGEN); 3594 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3595 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3596 3597 if ((scsi_conf & RESET_SCSI) != 0 3598 && (ahc->flags & AHC_INITIATORMODE) != 0) 3599 ahc->flags |= AHC_RESET_BUS_A; 3600 3601 /* 3602 * Look at the information that board initialization or 3603 * the board bios has left us. 3604 */ 3605 ultraenb = 0; 3606 tagenable = ALL_TARGETS_MASK; 3607 3608 /* Grab the disconnection disable table and invert it for our needs */ 3609 if (ahc->flags & AHC_USEDEFAULTS) { 3610 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3611 "device parameters\n", ahc_name(ahc)); 3612 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3613 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3614 discenable = ALL_TARGETS_MASK; 3615 if ((ahc->features & AHC_ULTRA) != 0) 3616 ultraenb = ALL_TARGETS_MASK; 3617 } else { 3618 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3619 | ahc_inb(ahc, DISC_DSB)); 3620 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3621 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3622 | ahc_inb(ahc, ULTRA_ENB); 3623 } 3624 3625 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3626 max_targ = 7; 3627 3628 for (i = 0; i <= max_targ; i++) { 3629 struct ahc_initiator_tinfo *tinfo; 3630 struct tmode_tstate *tstate; 3631 u_int our_id; 3632 u_int target_id; 3633 char channel; 3634 3635 channel = 'A'; 3636 our_id = ahc->our_id; 3637 target_id = i; 3638 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3639 channel = 'B'; 3640 our_id = ahc->our_id_b; 3641 target_id = i % 8; 3642 } 3643 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3644 target_id, &tstate); 3645 /* Default to async narrow across the board */ 3646 memset(tinfo, 0, sizeof(*tinfo)); 3647 if (ahc->flags & AHC_USEDEFAULTS) { 3648 if ((ahc->features & AHC_WIDE) != 0) 3649 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3650 3651 /* 3652 * These will be truncated when we determine the 3653 * connection type we have with the target. 3654 */ 3655 tinfo->user.period = ahc_syncrates->period; 3656 tinfo->user.offset = ~0; 3657 } else { 3658 u_int scsirate; 3659 u_int16_t mask; 3660 3661 /* Take the settings leftover in scratch RAM. */ 3662 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3663 mask = (0x01 << i); 3664 if ((ahc->features & AHC_ULTRA2) != 0) { 3665 u_int offset; 3666 u_int maxsync; 3667 3668 if ((scsirate & SOFS) == 0x0F) { 3669 /* 3670 * Haven't negotiated yet, 3671 * so the format is different. 3672 */ 3673 scsirate = (scsirate & SXFR) >> 4 3674 | (ultraenb & mask) 3675 ? 0x08 : 0x0 3676 | (scsirate & WIDEXFER); 3677 offset = MAX_OFFSET_ULTRA2; 3678 } else 3679 offset = ahc_inb(ahc, TARG_OFFSET + i); 3680 maxsync = AHC_SYNCRATE_ULTRA2; 3681 if ((ahc->features & AHC_DT) != 0) 3682 maxsync = AHC_SYNCRATE_DT; 3683 tinfo->user.period = 3684 ahc_find_period(ahc, scsirate, maxsync); 3685 if (offset == 0) 3686 tinfo->user.period = 0; 3687 else 3688 tinfo->user.offset = ~0; 3689 } else if ((scsirate & SOFS) != 0) { 3690 tinfo->user.period = 3691 ahc_find_period(ahc, scsirate, 3692 (ultraenb & mask) 3693 ? AHC_SYNCRATE_ULTRA 3694 : AHC_SYNCRATE_FAST); 3695 if (tinfo->user.period != 0) 3696 tinfo->user.offset = ~0; 3697 } 3698 if ((scsirate & WIDEXFER) != 0 3699 && (ahc->features & AHC_WIDE) != 0) 3700 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3701 } 3702 tinfo->goal = tinfo->user; /* force negotiation */ 3703 tstate->ultraenb = ultraenb; 3704 tstate->discenable = discenable; 3705 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3706 tstate->tagdisable = 0; 3707 } 3708 ahc->user_discenable = discenable; 3709 ahc->user_tagenable = tagenable; 3710 3711 /* 3712 * Tell the sequencer where it can find our arrays in memory. 3713 */ 3714 physaddr = ahc->scb_data->hscb_busaddr; 3715 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3716 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3717 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3718 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3719 3720 physaddr = ahc->shared_data_busaddr; 3721 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3722 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3723 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3724 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3725 3726 /* Target mode incomding command fifo */ 3727 physaddr += 3 * 256 * sizeof(u_int8_t); 3728 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3729 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3730 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3731 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3732 3733 /* 3734 * Initialize the group code to command length table. 3735 * This overrides the values in TARG_SCSIRATE, so only 3736 * setup the table after we have processed that information. 3737 */ 3738 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3739 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3740 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3741 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3742 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3743 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3744 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3745 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3746 3747 /* Tell the sequencer of our initial queue positions */ 3748 ahc_outb(ahc, KERNEL_QINPOS, 0); 3749 ahc_outb(ahc, QINPOS, 0); 3750 ahc_outb(ahc, QOUTPOS, 0); 3751 3752 #ifdef AHC_DEBUG 3753 if (ahc_debug & AHC_SHOWMISC) 3754 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3755 discenable, ultraenb); 3756 #endif 3757 3758 /* Don't have any special messages to send to targets */ 3759 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3760 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3761 3762 /* 3763 * Use the built in queue management registers 3764 * if they are available. 3765 */ 3766 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3767 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3768 ahc_outb(ahc, SDSCB_QOFF, 0); 3769 ahc_outb(ahc, SNSCB_QOFF, 0); 3770 ahc_outb(ahc, HNSCB_QOFF, 0); 3771 } 3772 3773 3774 /* We don't have any waiting selections */ 3775 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3776 3777 /* Our disconnection list is empty too */ 3778 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3779 3780 /* Message out buffer starts empty */ 3781 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3782 3783 /* 3784 * Setup the allowed SCSI Sequences based on operational mode. 3785 * If we are a target, we'll enable select in operations once 3786 * we've had a lun enabled. 3787 */ 3788 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3789 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3790 scsiseq_template |= ENRSELI; 3791 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3792 3793 /* 3794 * Load the Sequencer program and Enable the adapter 3795 * in "fast" mode. 3796 */ 3797 #ifdef AHC_DEBUG 3798 printf("%s: Downloading Sequencer Program...", 3799 ahc_name(ahc)); 3800 #endif 3801 3802 ahc_loadseq(ahc); 3803 3804 /* We have to wait until after any system dumps... */ 3805 shutdownhook_establish(ahc_shutdown, ahc); 3806 3807 return (0); 3808 } 3809 3810 static int 3811 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3812 struct proc *p) 3813 { 3814 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3815 int s, ret = ENOTTY; 3816 3817 switch (cmd) { 3818 case SCBUSIORESET: 3819 s = splbio(); 3820 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3821 TRUE); 3822 splx(s); 3823 ret = 0; 3824 break; 3825 default: 3826 break; 3827 } 3828 3829 return ret; 3830 } 3831 3832 3833 /* 3834 * XXX fvdl the busy_tcl checks and settings should only be done 3835 * for the non-tagged queueing case, but we don't do tagged queueing 3836 * yet, so.. 3837 */ 3838 static void 3839 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3840 { 3841 struct scsipi_xfer *xs; 3842 struct scsipi_periph *periph; 3843 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3844 struct scb *scb; 3845 struct hardware_scb *hscb; 3846 struct ahc_initiator_tinfo *tinfo; 3847 struct tmode_tstate *tstate; 3848 u_int target_id; 3849 u_int our_id; 3850 int s, tcl; 3851 u_int16_t mask; 3852 char channel; 3853 3854 switch (req) { 3855 case ADAPTER_REQ_RUN_XFER: 3856 xs = arg; 3857 periph = xs->xs_periph; 3858 3859 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("ahc_action\n")); 3860 3861 /* must protect the queue */ 3862 s = splbio(); 3863 3864 tcl = XS_TCL(ahc, xs); 3865 3866 if (!ahc_istagged_device(ahc, xs, 0) && 3867 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3868 panic("ahc_action: not tagged and device busy"); 3869 } 3870 3871 3872 target_id = periph->periph_target; 3873 our_id = SIM_SCSI_ID(ahc, periph); 3874 3875 /* 3876 * get an scb to use. 3877 */ 3878 if ((scb = ahcgetscb(ahc)) == NULL) { 3879 xs->error = XS_RESOURCE_SHORTAGE; 3880 scsipi_done(xs); 3881 splx(s); 3882 return; 3883 } 3884 3885 tcl = XS_TCL(ahc, xs); 3886 3887 #ifdef DIAGNOSTIC 3888 if (!ahc_istagged_device(ahc, xs, 0) && 3889 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3890 panic("ahc: queuing for busy target"); 3891 #endif 3892 3893 scb->xs = xs; 3894 hscb = scb->hscb; 3895 hscb->tcl = tcl; 3896 3897 if (xs->xs_tag_type) { 3898 #ifdef DIAGNOSTIC 3899 if (ahc_istagged_device(ahc, xs, 0) == 0) 3900 panic("ahc_action: taggged command for untagged device"); 3901 #endif 3902 scb->hscb->control |= TAG_ENB; 3903 } else 3904 ahc_busy_tcl(ahc, scb); 3905 3906 splx(s); 3907 3908 channel = SIM_CHANNEL(ahc, periph); 3909 if (ahc->inited_channels[channel - 'A'] == 0) { 3910 if ((channel == 'A' && 3911 (ahc->flags & AHC_RESET_BUS_A)) || 3912 (channel == 'B' && 3913 (ahc->flags & AHC_RESET_BUS_B))) { 3914 s = splbio(); 3915 ahc_reset_channel(ahc, channel, TRUE); 3916 splx(s); 3917 } 3918 ahc->inited_channels[channel - 'A'] = 1; 3919 } 3920 3921 /* 3922 * Put all the arguments for the xfer in the scb 3923 */ 3924 3925 mask = SCB_TARGET_MASK(scb); 3926 tinfo = ahc_fetch_transinfo(ahc, 3927 SIM_CHANNEL(ahc, periph), 3928 our_id, target_id, &tstate); 3929 if (ahc->inited_targets[target_id] == 0) { 3930 struct ahc_devinfo devinfo; 3931 s = splbio(); 3932 ahc_compile_devinfo(&devinfo, our_id, target_id, 3933 periph->periph_lun, 3934 SIM_CHANNEL(ahc, periph), 3935 ROLE_INITIATOR); 3936 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3937 TRUE, FALSE); 3938 ahc->inited_targets[target_id] = 1; 3939 splx(s); 3940 } 3941 hscb->scsirate = tinfo->scsirate; 3942 hscb->scsioffset = tinfo->current.offset; 3943 if ((tstate->ultraenb & mask) != 0) 3944 hscb->control |= ULTRAENB; 3945 3946 if ((tstate->discenable & mask) != 0) 3947 hscb->control |= DISCENB; 3948 3949 if (xs->xs_control & XS_CTL_RESET) { 3950 hscb->cmdpointer = 0; 3951 scb->flags |= SCB_DEVICE_RESET; 3952 hscb->control |= MK_MESSAGE; 3953 ahc_execute_scb(scb, NULL, 0); 3954 } 3955 3956 ahc_setup_data(ahc, xs, scb); 3957 return; 3958 case ADAPTER_REQ_GROW_RESOURCES: 3959 /* XXX not supported */ 3960 return; 3961 case ADAPTER_REQ_SET_XFER_MODE: 3962 { 3963 struct scsipi_xfer_mode *xm = arg; 3964 struct ahc_devinfo devinfo; 3965 int target_id, our_id; 3966 char channel; 3967 3968 target_id = xm->xm_target; 3969 our_id = chan->chan_id; 3970 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 3971 s = splbio(); 3972 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 3973 &tstate); 3974 ahc_compile_devinfo(&devinfo, our_id, target_id, 3975 0, channel, ROLE_INITIATOR); 3976 ahc->inited_targets[target_id] = 2; 3977 if (xm->xm_mode & PERIPH_CAP_TQING && 3978 (tstate->tagdisable & devinfo.target_mask) == 0) { 3979 ahc_set_tags(ahc, &devinfo, TRUE); 3980 } 3981 splx(s); 3982 ahc_update_xfer_mode(ahc, &devinfo); 3983 } 3984 } 3985 } 3986 3987 static void 3988 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 3989 { 3990 struct scb *scb; 3991 struct scsipi_xfer *xs; 3992 struct ahc_softc *ahc; 3993 int s; 3994 3995 scb = (struct scb *)arg; 3996 xs = scb->xs; 3997 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 3998 3999 4000 if (nsegments != 0) { 4001 struct ahc_dma_seg *sg; 4002 bus_dma_segment_t *end_seg; 4003 int op; 4004 4005 end_seg = dm_segs + nsegments; 4006 4007 /* Copy the first SG into the data pointer area */ 4008 scb->hscb->data = dm_segs->ds_addr; 4009 scb->hscb->datalen = dm_segs->ds_len; 4010 4011 /* Copy the segments into our SG list */ 4012 sg = scb->sg_list; 4013 while (dm_segs < end_seg) { 4014 sg->addr = dm_segs->ds_addr; 4015 sg->len = dm_segs->ds_len; 4016 ahc_swap_sg(sg); 4017 sg++; 4018 dm_segs++; 4019 } 4020 4021 /* Note where to find the SG entries in bus space */ 4022 scb->hscb->SG_pointer = scb->sg_list_phys; 4023 4024 if (xs->xs_control & XS_CTL_DATA_IN) 4025 op = BUS_DMASYNC_PREREAD; 4026 else 4027 op = BUS_DMASYNC_PREWRITE; 4028 4029 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4030 scb->dmamap->dm_mapsize, op); 4031 4032 } else { 4033 scb->hscb->SG_pointer = 0; 4034 scb->hscb->data = 0; 4035 scb->hscb->datalen = 0; 4036 } 4037 4038 scb->sg_count = scb->hscb->SG_count = nsegments; 4039 4040 s = splbio(); 4041 4042 /* 4043 * Last time we need to check if this SCB needs to 4044 * be aborted. 4045 */ 4046 if (xs->xs_status & XS_STS_DONE) { 4047 if (!ahc_istagged_device(ahc, xs, 0)) 4048 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4049 if (nsegments != 0) 4050 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4051 ahcfreescb(ahc, scb); 4052 splx(s); 4053 return; 4054 } 4055 4056 #ifdef DIAGNOSTIC 4057 if (scb->sg_count > 255) 4058 panic("ahc bad sg_count"); 4059 #endif 4060 4061 ahc_swap_hscb(scb->hscb); 4062 4063 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4064 4065 scb->flags |= SCB_ACTIVE; 4066 4067 if (!(xs->xs_control & XS_CTL_POLL)) 4068 callout_reset(&scb->xs->xs_callout, xs->timeout > 1000000 ? 4069 (xs->timeout / 1000) * hz : (xs->timeout * hz) / 1000, 4070 ahc_timeout, scb); 4071 4072 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4073 #if 0 4074 printf("Continueing Immediate Command %d:%d\n", 4075 xs->xs_periph->periph_target, 4076 xs->xs_periph->periph_lun); 4077 #endif 4078 pause_sequencer(ahc); 4079 if ((ahc->flags & AHC_PAGESCBS) == 0) 4080 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4081 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4082 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4083 unpause_sequencer(ahc); 4084 } else { 4085 4086 #if 0 4087 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4088 scb->hscb->tag, ahc->qinfifonext, 4089 &ahc->qinfifo[ahc->qinfifonext], 4090 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4091 #endif 4092 4093 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4094 4095 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4096 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4097 4098 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4099 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4100 } else { 4101 pause_sequencer(ahc); 4102 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4103 unpause_sequencer(ahc); 4104 } 4105 } 4106 4107 #ifdef AHC_DEBUG 4108 if (ahc_debug & AHC_SHOWCMDS) { 4109 scsi_print_addr(xs->xs_periph); 4110 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4111 " rate %x\n", 4112 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4113 scb->flags, scb->hscb->control, ahc->qinfifonext, 4114 scb->hscb->scsirate); 4115 } 4116 #endif 4117 4118 if (!(xs->xs_control & XS_CTL_POLL)) { 4119 splx(s); 4120 return; 4121 } 4122 /* 4123 * If we can't use interrupts, poll for completion 4124 */ 4125 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("cmd_poll\n")); 4126 do { 4127 if (ahc_poll(ahc, xs->timeout)) { 4128 if (!(xs->xs_control & XS_CTL_SILENT)) 4129 printf("cmd fail\n"); 4130 ahc_timeout(scb); 4131 break; 4132 } 4133 } while (!(xs->xs_status & XS_STS_DONE)); 4134 splx(s); 4135 return; 4136 } 4137 4138 static int 4139 ahc_poll(struct ahc_softc *ahc, int wait) 4140 { 4141 while (--wait) { 4142 DELAY(1000); 4143 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4144 break; 4145 } 4146 4147 if (wait == 0) { 4148 printf("%s: board is not responding\n", ahc_name(ahc)); 4149 return (EIO); 4150 } 4151 4152 ahc_intr((void *)ahc); 4153 return (0); 4154 } 4155 4156 static void 4157 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4158 struct scb *scb) 4159 { 4160 struct hardware_scb *hscb; 4161 4162 hscb = scb->hscb; 4163 xs->resid = xs->status = 0; 4164 4165 hscb->cmdlen = xs->cmdlen; 4166 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4167 hscb->cmdpointer = hscb->cmdstore_busaddr; 4168 4169 /* Only use S/G if there is a transfer */ 4170 if (xs->datalen) { 4171 int error; 4172 4173 error = bus_dmamap_load(ahc->parent_dmat, 4174 scb->dmamap, xs->data, 4175 xs->datalen, NULL, 4176 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4177 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4178 BUS_DMA_STREAMING | 4179 ((xs->xs_control & XS_CTL_DATA_IN) ? 4180 BUS_DMA_READ : BUS_DMA_WRITE)); 4181 if (error) { 4182 #ifdef AHC_DEBUG 4183 printf("%s: in ahc_setup_data(): bus_dmamap_load() " 4184 "= %d\n", 4185 ahc_name(ahc), 4186 error); 4187 #endif 4188 if (!ahc_istagged_device(ahc, xs, 0)) 4189 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4190 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4191 scsipi_done(xs); 4192 return; 4193 } 4194 ahc_execute_scb(scb, 4195 scb->dmamap->dm_segs, 4196 scb->dmamap->dm_nsegs); 4197 } else { 4198 ahc_execute_scb(scb, NULL, 0); 4199 } 4200 } 4201 4202 static void 4203 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4204 { 4205 int target; 4206 char channel; 4207 int lun; 4208 4209 target = periph->periph_target; 4210 lun = periph->periph_lun; 4211 channel = periph->periph_channel->chan_channel; 4212 4213 ahc_search_qinfifo(ahc, target, channel, lun, 4214 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4215 SCB_REQUEUE, SEARCH_COMPLETE); 4216 } 4217 4218 static void 4219 ahcallocscbs(struct ahc_softc *ahc) 4220 { 4221 struct scb_data *scb_data; 4222 struct scb *next_scb; 4223 struct sg_map_node *sg_map; 4224 bus_addr_t physaddr; 4225 struct ahc_dma_seg *segs; 4226 int newcount; 4227 int i; 4228 4229 scb_data = ahc->scb_data; 4230 if (scb_data->numscbs >= AHC_SCB_MAX) 4231 /* Can't allocate any more */ 4232 return; 4233 4234 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4235 4236 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4237 4238 if (sg_map == NULL) 4239 return; 4240 4241 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4242 &sg_map->sg_dmamap, 4243 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4244 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4245 "SG space") < 0) { 4246 free(sg_map, M_DEVBUF); 4247 return; 4248 } 4249 4250 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4251 4252 segs = sg_map->sg_vaddr; 4253 physaddr = sg_map->sg_physaddr; 4254 4255 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4256 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4257 int error; 4258 4259 next_scb->sg_list = segs; 4260 /* 4261 * The sequencer always starts with the second entry. 4262 * The first entry is embedded in the scb. 4263 */ 4264 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4265 next_scb->flags = SCB_FREE; 4266 error = bus_dmamap_create(ahc->parent_dmat, 4267 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4268 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4269 &next_scb->dmamap); 4270 if (error != 0) 4271 break; 4272 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4273 next_scb->hscb->tag = ahc->scb_data->numscbs; 4274 next_scb->hscb->cmdstore_busaddr = 4275 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4276 + offsetof(struct hardware_scb, cmdstore); 4277 next_scb->hscb->cmdstore_busaddr = 4278 htole32(next_scb->hscb->cmdstore_busaddr); 4279 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4280 segs += AHC_NSEG; 4281 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4282 next_scb++; 4283 ahc->scb_data->numscbs++; 4284 } 4285 #ifdef AHC_DEBUG 4286 if (ahc_debug & AHC_SHOWSCBALLOC) 4287 printf("%s: allocated %d new SCBs count now %d\n", 4288 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4289 #endif 4290 } 4291 4292 #ifdef AHC_DUMP_SEQ 4293 static void 4294 ahc_dumpseq(struct ahc_softc* ahc) 4295 { 4296 int i; 4297 int max_prog; 4298 4299 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4300 max_prog = 448; 4301 else if ((ahc->features & AHC_ULTRA2) != 0) 4302 max_prog = 768; 4303 else 4304 max_prog = 512; 4305 4306 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4307 ahc_outb(ahc, SEQADDR0, 0); 4308 ahc_outb(ahc, SEQADDR1, 0); 4309 for (i = 0; i < max_prog; i++) { 4310 u_int8_t ins_bytes[4]; 4311 4312 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4313 printf("0x%08x\n", ins_bytes[0] << 24 4314 | ins_bytes[1] << 16 4315 | ins_bytes[2] << 8 4316 | ins_bytes[3]); 4317 } 4318 } 4319 #endif 4320 4321 static void 4322 ahc_loadseq(struct ahc_softc *ahc) 4323 { 4324 const struct patch *cur_patch; 4325 int i; 4326 int downloaded; 4327 int skip_addr; 4328 u_int8_t download_consts[4]; 4329 4330 /* Setup downloadable constant table */ 4331 #if 0 4332 /* No downloaded constants are currently defined. */ 4333 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4334 #endif 4335 4336 cur_patch = patches; 4337 downloaded = 0; 4338 skip_addr = 0; 4339 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4340 ahc_outb(ahc, SEQADDR0, 0); 4341 ahc_outb(ahc, SEQADDR1, 0); 4342 4343 for (i = 0; i < sizeof(seqprog)/4; i++) { 4344 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4345 /* 4346 * Don't download this instruction as it 4347 * is in a patch that was removed. 4348 */ 4349 continue; 4350 } 4351 ahc_download_instr(ahc, i, download_consts); 4352 downloaded++; 4353 } 4354 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4355 restart_sequencer(ahc); 4356 4357 #ifdef AHC_DEBUG 4358 printf(" %d instructions downloaded\n", downloaded); 4359 #endif 4360 } 4361 4362 static int 4363 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4364 int start_instr, int *skip_addr) 4365 { 4366 const struct patch *cur_patch; 4367 const struct patch *last_patch; 4368 int num_patches; 4369 4370 num_patches = sizeof(patches)/sizeof(struct patch); 4371 last_patch = &patches[num_patches]; 4372 cur_patch = *start_patch; 4373 4374 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4375 4376 if (cur_patch->patch_func(ahc) == 0) { 4377 4378 /* Start rejecting code */ 4379 *skip_addr = start_instr + cur_patch->skip_instr; 4380 cur_patch += cur_patch->skip_patch; 4381 } else { 4382 /* Accepted this patch. Advance to the next 4383 * one and wait for our intruction pointer to 4384 * hit this point. 4385 */ 4386 cur_patch++; 4387 } 4388 } 4389 4390 *start_patch = cur_patch; 4391 if (start_instr < *skip_addr) 4392 /* Still skipping */ 4393 return (0); 4394 4395 return (1); 4396 } 4397 4398 static void 4399 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4400 { 4401 union ins_formats instr; 4402 struct ins_format1 *fmt1_ins; 4403 struct ins_format3 *fmt3_ins; 4404 u_int opcode; 4405 4406 /* Structure copy */ 4407 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4408 4409 instr.integer = le32toh(instr.integer); 4410 4411 fmt1_ins = &instr.format1; 4412 fmt3_ins = NULL; 4413 4414 /* Pull the opcode */ 4415 opcode = instr.format1.opcode; 4416 switch (opcode) { 4417 case AIC_OP_JMP: 4418 case AIC_OP_JC: 4419 case AIC_OP_JNC: 4420 case AIC_OP_CALL: 4421 case AIC_OP_JNE: 4422 case AIC_OP_JNZ: 4423 case AIC_OP_JE: 4424 case AIC_OP_JZ: 4425 { 4426 const struct patch *cur_patch; 4427 int address_offset; 4428 u_int address; 4429 int skip_addr; 4430 int i; 4431 4432 fmt3_ins = &instr.format3; 4433 address_offset = 0; 4434 address = fmt3_ins->address; 4435 cur_patch = patches; 4436 skip_addr = 0; 4437 4438 for (i = 0; i < address;) { 4439 4440 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4441 4442 if (skip_addr > i) { 4443 int end_addr; 4444 4445 end_addr = MIN(address, skip_addr); 4446 address_offset += end_addr - i; 4447 i = skip_addr; 4448 } else { 4449 i++; 4450 } 4451 } 4452 address -= address_offset; 4453 fmt3_ins->address = address; 4454 /* FALLTHROUGH */ 4455 } 4456 case AIC_OP_OR: 4457 case AIC_OP_AND: 4458 case AIC_OP_XOR: 4459 case AIC_OP_ADD: 4460 case AIC_OP_ADC: 4461 case AIC_OP_BMOV: 4462 if (fmt1_ins->parity != 0) { 4463 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4464 } 4465 fmt1_ins->parity = 0; 4466 /* FALLTHROUGH */ 4467 case AIC_OP_ROL: 4468 if ((ahc->features & AHC_ULTRA2) != 0) { 4469 int i, count; 4470 4471 /* Calculate odd parity for the instruction */ 4472 for (i = 0, count = 0; i < 31; i++) { 4473 u_int32_t mask; 4474 4475 mask = 0x01 << i; 4476 if ((instr.integer & mask) != 0) 4477 count++; 4478 } 4479 if ((count & 0x01) == 0) 4480 instr.format1.parity = 1; 4481 } else { 4482 /* Compress the instruction for older sequencers */ 4483 if (fmt3_ins != NULL) { 4484 instr.integer = 4485 fmt3_ins->immediate 4486 | (fmt3_ins->source << 8) 4487 | (fmt3_ins->address << 16) 4488 | (fmt3_ins->opcode << 25); 4489 } else { 4490 instr.integer = 4491 fmt1_ins->immediate 4492 | (fmt1_ins->source << 8) 4493 | (fmt1_ins->destination << 16) 4494 | (fmt1_ins->ret << 24) 4495 | (fmt1_ins->opcode << 25); 4496 } 4497 } 4498 instr.integer = htole32(instr.integer); 4499 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4500 break; 4501 default: 4502 panic("Unknown opcode encountered in seq program"); 4503 break; 4504 } 4505 } 4506 4507 static void 4508 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4509 { 4510 4511 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4512 struct scb *scbp; 4513 4514 scb->flags |= SCB_RECOVERY_SCB; 4515 4516 /* 4517 * Take all queued, but not sent SCBs out of the equation. 4518 * Also ensure that no new CCBs are queued to us while we 4519 * try to fix this problem. 4520 */ 4521 scsipi_channel_freeze(&ahc->sc_channel, 1); 4522 if (ahc->features & AHC_TWIN) 4523 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4524 4525 /* 4526 * Go through all of our pending SCBs and remove 4527 * any scheduled timeouts for them. We will reschedule 4528 * them after we've successfully fixed this problem. 4529 */ 4530 scbp = ahc->pending_ccbs.lh_first; 4531 while (scbp != NULL) { 4532 callout_stop(&scbp->xs->xs_callout); 4533 scbp = scbp->plinks.le_next; 4534 } 4535 } 4536 } 4537 4538 static void 4539 ahc_timeout(void *arg) 4540 { 4541 struct scb *scb; 4542 struct ahc_softc *ahc; 4543 int s, found; 4544 u_int last_phase; 4545 int target; 4546 int lun; 4547 int i; 4548 char channel; 4549 4550 scb = (struct scb *)arg; 4551 ahc = 4552 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4553 4554 s = splbio(); 4555 4556 /* 4557 * Ensure that the card doesn't do anything 4558 * behind our back. Also make sure that we 4559 * didn't "just" miss an interrupt that would 4560 * affect this timeout. 4561 */ 4562 do { 4563 ahc_intr(ahc); 4564 pause_sequencer(ahc); 4565 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4566 4567 if ((scb->flags & SCB_ACTIVE) == 0) { 4568 /* Previous timeout took care of me already */ 4569 printf("Timedout SCB handled by another timeout\n"); 4570 unpause_sequencer(ahc); 4571 splx(s); 4572 return; 4573 } 4574 4575 target = SCB_TARGET(scb); 4576 channel = SCB_CHANNEL(scb); 4577 lun = SCB_LUN(scb); 4578 4579 scsipi_printaddr(scb->xs->xs_periph); 4580 printf("SCB %x - timed out ", scb->hscb->tag); 4581 /* 4582 * Take a snapshot of the bus state and print out 4583 * some information so we can track down driver bugs. 4584 */ 4585 last_phase = ahc_inb(ahc, LASTPHASE); 4586 4587 for (i = 0; i < num_phases; i++) { 4588 if (last_phase == phase_table[i].phase) 4589 break; 4590 } 4591 printf("%s", phase_table[i].phasemsg); 4592 4593 printf(", SEQADDR == 0x%x\n", 4594 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4595 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4596 4597 #ifdef AHC_DEBUG 4598 ahc_print_scb(scb); 4599 #endif 4600 4601 #if 0 4602 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4603 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4604 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4605 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4606 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4607 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4608 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4609 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4610 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4611 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4612 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4613 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4614 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4615 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4616 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4617 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4618 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4619 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4620 if (scb->sg_count > 0) { 4621 for (i = 0; i < scb->sg_count; i++) { 4622 printf("sg[%d] - Addr 0x%x : Length %d\n", 4623 i, 4624 le32toh(scb->sg_list[i].addr), 4625 le32toh(scb->sg_list[i].len)); 4626 } 4627 } 4628 #endif 4629 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4630 /* 4631 * Been down this road before. 4632 * Do a full bus reset. 4633 */ 4634 bus_reset: 4635 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4636 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4637 printf("%s: Issued Channel %c Bus Reset. " 4638 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4639 } else { 4640 /* 4641 * If we are a target, transition to bus free and report 4642 * the timeout. 4643 * 4644 * The target/initiator that is holding up the bus may not 4645 * be the same as the one that triggered this timeout 4646 * (different commands have different timeout lengths). 4647 * If the bus is idle and we are actiing as the initiator 4648 * for this request, queue a BDR message to the timed out 4649 * target. Otherwise, if the timed out transaction is 4650 * active: 4651 * Initiator transaction: 4652 * Stuff the message buffer with a BDR message and assert 4653 * ATN in the hopes that the target will let go of the bus 4654 * and go to the mesgout phase. If this fails, we'll 4655 * get another timeout 2 seconds later which will attempt 4656 * a bus reset. 4657 * 4658 * Target transaction: 4659 * Transition to BUS FREE and report the error. 4660 * It's good to be the target! 4661 */ 4662 u_int active_scb_index; 4663 4664 active_scb_index = ahc_inb(ahc, SCB_TAG); 4665 4666 if (last_phase != P_BUSFREE 4667 && (active_scb_index < ahc->scb_data->numscbs)) { 4668 struct scb *active_scb; 4669 4670 /* 4671 * If the active SCB is not from our device, 4672 * assume that another device is hogging the bus 4673 * and wait for it's timeout to expire before 4674 * taking additional action. 4675 */ 4676 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4677 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4678 u_int newtimeout; 4679 4680 scsipi_printaddr(scb->xs->xs_periph); 4681 printf("Other SCB Timeout%s", 4682 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4683 ? " again\n" : "\n"); 4684 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4685 newtimeout = MAX(active_scb->xs->timeout, 4686 scb->xs->timeout); 4687 callout_reset(&scb->xs->xs_callout, 4688 newtimeout > 1000000 ? 4689 (newtimeout / 1000) * hz : 4690 (newtimeout * hz) / 1000, 4691 ahc_timeout, scb); 4692 splx(s); 4693 return; 4694 } 4695 4696 /* It's us */ 4697 if ((scb->hscb->control & TARGET_SCB) != 0) { 4698 4699 /* 4700 * Send back any queued up transactions 4701 * and properly record the error condition. 4702 */ 4703 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4704 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4705 ahc_freeze_ccb(scb); 4706 ahc_done(ahc, scb); 4707 4708 /* Will clear us from the bus */ 4709 restart_sequencer(ahc); 4710 splx(s); 4711 return; 4712 } 4713 4714 ahc_set_recoveryscb(ahc, active_scb); 4715 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4716 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4717 scsipi_printaddr(active_scb->xs->xs_periph); 4718 printf("BDR message in message buffer\n"); 4719 active_scb->flags |= SCB_DEVICE_RESET; 4720 callout_reset(&active_scb->xs->xs_callout, 4721 2 * hz, ahc_timeout, active_scb); 4722 unpause_sequencer(ahc); 4723 } else { 4724 int disconnected; 4725 4726 /* XXX Shouldn't panic. Just punt instead */ 4727 if ((scb->hscb->control & TARGET_SCB) != 0) 4728 panic("Timed-out target SCB but bus idle"); 4729 4730 if (last_phase != P_BUSFREE 4731 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4732 /* XXX What happened to the SCB? */ 4733 /* Hung target selection. Goto busfree */ 4734 printf("%s: Hung target selection\n", 4735 ahc_name(ahc)); 4736 restart_sequencer(ahc); 4737 splx(s); 4738 return; 4739 } 4740 4741 if (ahc_search_qinfifo(ahc, target, channel, lun, 4742 scb->hscb->tag, ROLE_INITIATOR, 4743 /*status*/0, SEARCH_COUNT) > 0) { 4744 disconnected = FALSE; 4745 } else { 4746 disconnected = TRUE; 4747 } 4748 4749 if (disconnected) { 4750 u_int active_scb; 4751 4752 ahc_set_recoveryscb(ahc, scb); 4753 /* 4754 * Simply set the MK_MESSAGE control bit. 4755 */ 4756 scb->hscb->control |= MK_MESSAGE; 4757 scb->flags |= SCB_QUEUED_MSG 4758 | SCB_DEVICE_RESET; 4759 4760 /* 4761 * Mark the cached copy of this SCB in the 4762 * disconnected list too, so that a reconnect 4763 * at this point causes a BDR or abort. 4764 */ 4765 active_scb = ahc_inb(ahc, SCBPTR); 4766 if (ahc_search_disc_list(ahc, target, 4767 channel, lun, 4768 scb->hscb->tag, 4769 /*stop_on_first*/TRUE, 4770 /*remove*/FALSE, 4771 /*save_state*/FALSE)) { 4772 u_int scb_control; 4773 4774 scb_control = ahc_inb(ahc, SCB_CONTROL); 4775 scb_control |= MK_MESSAGE; 4776 ahc_outb(ahc, SCB_CONTROL, scb_control); 4777 } 4778 ahc_outb(ahc, SCBPTR, active_scb); 4779 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4780 /*unbusy*/TRUE); 4781 4782 /* 4783 * Actually re-queue this SCB in case we can 4784 * select the device before it reconnects. 4785 * Clear out any entries in the QINFIFO first 4786 * so we are the next SCB for this target 4787 * to run. 4788 */ 4789 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4790 channel, SCB_LUN(scb), 4791 SCB_LIST_NULL, 4792 ROLE_INITIATOR, 4793 SCB_REQUEUE, 4794 SEARCH_COMPLETE); 4795 scsipi_printaddr(scb->xs->xs_periph); 4796 printf("Queuing a BDR SCB\n"); 4797 ahc->qinfifo[ahc->qinfifonext++] = 4798 scb->hscb->tag; 4799 4800 bus_dmamap_sync(ahc->parent_dmat, 4801 ahc->shared_data_dmamap, 4802 QINFIFO_OFFSET * 256, 256, 4803 BUS_DMASYNC_PREWRITE); 4804 4805 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4806 ahc_outb(ahc, HNSCB_QOFF, 4807 ahc->qinfifonext); 4808 } else { 4809 ahc_outb(ahc, KERNEL_QINPOS, 4810 ahc->qinfifonext); 4811 } 4812 callout_reset(&scb->xs->xs_callout, 2 * hz, 4813 ahc_timeout, scb); 4814 unpause_sequencer(ahc); 4815 } else { 4816 /* Go "immediatly" to the bus reset */ 4817 /* This shouldn't happen */ 4818 ahc_set_recoveryscb(ahc, scb); 4819 scsipi_printaddr(scb->xs->xs_periph); 4820 printf("SCB %x: Immediate reset. " 4821 "Flags = 0x%x\n", scb->hscb->tag, 4822 scb->flags); 4823 goto bus_reset; 4824 } 4825 } 4826 } 4827 splx(s); 4828 } 4829 4830 static int 4831 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4832 int lun, u_int tag, role_t role, scb_flag status, 4833 ahc_search_action action) 4834 { 4835 struct scb *scbp; 4836 u_int8_t qinpos; 4837 u_int8_t qintail; 4838 int found; 4839 4840 qinpos = ahc_inb(ahc, QINPOS); 4841 qintail = ahc->qinfifonext; 4842 found = 0; 4843 4844 /* 4845 * Start with an empty queue. Entries that are not chosen 4846 * for removal will be re-added to the queue as we go. 4847 */ 4848 ahc->qinfifonext = qinpos; 4849 4850 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4851 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4852 4853 while (qinpos != qintail) { 4854 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4855 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4856 /* 4857 * We found an scb that needs to be removed. 4858 */ 4859 switch (action) { 4860 case SEARCH_COMPLETE: 4861 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4862 scbp->flags |= status; 4863 scbp->xs->error = XS_NOERROR; 4864 } 4865 ahc_freeze_ccb(scbp); 4866 ahc_done(ahc, scbp); 4867 break; 4868 case SEARCH_COUNT: 4869 ahc->qinfifo[ahc->qinfifonext++] = 4870 scbp->hscb->tag; 4871 break; 4872 case SEARCH_REMOVE: 4873 break; 4874 } 4875 found++; 4876 } else { 4877 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4878 } 4879 qinpos++; 4880 } 4881 4882 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4883 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4884 4885 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4886 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4887 } else { 4888 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4889 } 4890 4891 return (found); 4892 } 4893 4894 /* 4895 * Abort all SCBs that match the given description (target/channel/lun/tag), 4896 * setting their status to the passed in status if the status has not already 4897 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4898 * is paused before it is called. 4899 */ 4900 static int 4901 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4902 int lun, u_int tag, role_t role, int status) 4903 { 4904 struct scb *scbp; 4905 u_int active_scb; 4906 int i; 4907 int found; 4908 4909 /* restore this when we're done */ 4910 active_scb = ahc_inb(ahc, SCBPTR); 4911 4912 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4913 role, SCB_REQUEUE, SEARCH_COMPLETE); 4914 4915 /* 4916 * Search waiting for selection list. 4917 */ 4918 { 4919 u_int8_t next, prev; 4920 4921 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4922 prev = SCB_LIST_NULL; 4923 4924 while (next != SCB_LIST_NULL) { 4925 u_int8_t scb_index; 4926 4927 ahc_outb(ahc, SCBPTR, next); 4928 scb_index = ahc_inb(ahc, SCB_TAG); 4929 if (scb_index >= ahc->scb_data->numscbs) { 4930 panic("Waiting List inconsistency. " 4931 "SCB index == %d, yet numscbs == %d.", 4932 scb_index, ahc->scb_data->numscbs); 4933 } 4934 scbp = &ahc->scb_data->scbarray[scb_index]; 4935 if (ahc_match_scb(scbp, target, channel, 4936 lun, SCB_LIST_NULL, role)) { 4937 4938 next = ahc_abort_wscb(ahc, next, prev); 4939 } else { 4940 4941 prev = next; 4942 next = ahc_inb(ahc, SCB_NEXT); 4943 } 4944 } 4945 } 4946 /* 4947 * Go through the disconnected list and remove any entries we 4948 * have queued for completion, 0'ing their control byte too. 4949 * We save the active SCB and restore it ourselves, so there 4950 * is no reason for this search to restore it too. 4951 */ 4952 ahc_search_disc_list(ahc, target, channel, lun, tag, 4953 /*stop_on_first*/FALSE, /*remove*/TRUE, 4954 /*save_state*/FALSE); 4955 4956 /* 4957 * Go through the hardware SCB array looking for commands that 4958 * were active but not on any list. 4959 */ 4960 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4961 u_int scbid; 4962 4963 ahc_outb(ahc, SCBPTR, i); 4964 scbid = ahc_inb(ahc, SCB_TAG); 4965 scbp = &ahc->scb_data->scbarray[scbid]; 4966 if (scbid < ahc->scb_data->numscbs 4967 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4968 ahc_add_curscb_to_free_list(ahc); 4969 } 4970 4971 /* 4972 * Go through the pending CCB list and look for 4973 * commands for this target that are still active. 4974 * These are other tagged commands that were 4975 * disconnected when the reset occurred. 4976 */ 4977 { 4978 struct scb *scb; 4979 4980 scb = ahc->pending_ccbs.lh_first; 4981 while (scb != NULL) { 4982 scbp = scb; 4983 scb = scb->plinks.le_next; 4984 if (ahc_match_scb(scbp, target, channel, 4985 lun, tag, role)) { 4986 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4987 ahcsetccbstatus(scbp->xs, status); 4988 ahc_freeze_ccb(scbp); 4989 ahc_done(ahc, scbp); 4990 found++; 4991 } 4992 } 4993 } 4994 ahc_outb(ahc, SCBPTR, active_scb); 4995 return found; 4996 } 4997 4998 static int 4999 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5000 int lun, u_int tag, int stop_on_first, int remove, 5001 int save_state) 5002 { 5003 struct scb *scbp; 5004 u_int next; 5005 u_int prev; 5006 u_int count; 5007 u_int active_scb; 5008 5009 count = 0; 5010 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5011 prev = SCB_LIST_NULL; 5012 5013 if (save_state) { 5014 /* restore this when we're done */ 5015 active_scb = ahc_inb(ahc, SCBPTR); 5016 } else 5017 /* Silence compiler */ 5018 active_scb = SCB_LIST_NULL; 5019 5020 while (next != SCB_LIST_NULL) { 5021 u_int scb_index; 5022 5023 ahc_outb(ahc, SCBPTR, next); 5024 scb_index = ahc_inb(ahc, SCB_TAG); 5025 if (scb_index >= ahc->scb_data->numscbs) { 5026 panic("Disconnected List inconsistency. " 5027 "SCB index == %d, yet numscbs == %d.", 5028 scb_index, ahc->scb_data->numscbs); 5029 } 5030 scbp = &ahc->scb_data->scbarray[scb_index]; 5031 if (ahc_match_scb(scbp, target, channel, lun, 5032 tag, ROLE_INITIATOR)) { 5033 count++; 5034 if (remove) { 5035 next = 5036 ahc_rem_scb_from_disc_list(ahc, prev, next); 5037 } else { 5038 prev = next; 5039 next = ahc_inb(ahc, SCB_NEXT); 5040 } 5041 if (stop_on_first) 5042 break; 5043 } else { 5044 prev = next; 5045 next = ahc_inb(ahc, SCB_NEXT); 5046 } 5047 } 5048 if (save_state) 5049 ahc_outb(ahc, SCBPTR, active_scb); 5050 return (count); 5051 } 5052 5053 static u_int 5054 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5055 { 5056 u_int next; 5057 5058 ahc_outb(ahc, SCBPTR, scbptr); 5059 next = ahc_inb(ahc, SCB_NEXT); 5060 5061 ahc_outb(ahc, SCB_CONTROL, 0); 5062 5063 ahc_add_curscb_to_free_list(ahc); 5064 5065 if (prev != SCB_LIST_NULL) { 5066 ahc_outb(ahc, SCBPTR, prev); 5067 ahc_outb(ahc, SCB_NEXT, next); 5068 } else 5069 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5070 5071 return (next); 5072 } 5073 5074 static void 5075 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5076 { 5077 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5078 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5079 5080 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5081 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5082 } 5083 5084 /* 5085 * Manipulate the waiting for selection list and return the 5086 * scb that follows the one that we remove. 5087 */ 5088 static u_int 5089 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5090 { 5091 u_int curscb, next; 5092 5093 /* 5094 * Select the SCB we want to abort and 5095 * pull the next pointer out of it. 5096 */ 5097 curscb = ahc_inb(ahc, SCBPTR); 5098 ahc_outb(ahc, SCBPTR, scbpos); 5099 next = ahc_inb(ahc, SCB_NEXT); 5100 5101 /* Clear the necessary fields */ 5102 ahc_outb(ahc, SCB_CONTROL, 0); 5103 5104 ahc_add_curscb_to_free_list(ahc); 5105 5106 /* update the waiting list */ 5107 if (prev == SCB_LIST_NULL) { 5108 /* First in the list */ 5109 ahc_outb(ahc, WAITING_SCBH, next); 5110 5111 /* 5112 * Ensure we aren't attempting to perform 5113 * selection for this entry. 5114 */ 5115 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5116 } else { 5117 /* 5118 * Select the scb that pointed to us 5119 * and update its next pointer. 5120 */ 5121 ahc_outb(ahc, SCBPTR, prev); 5122 ahc_outb(ahc, SCB_NEXT, next); 5123 } 5124 5125 /* 5126 * Point us back at the original scb position. 5127 */ 5128 ahc_outb(ahc, SCBPTR, curscb); 5129 return next; 5130 } 5131 5132 static void 5133 ahc_clear_intstat(struct ahc_softc *ahc) 5134 { 5135 /* Clear any interrupt conditions this may have caused */ 5136 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5137 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5138 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5139 CLRREQINIT); 5140 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5141 } 5142 5143 static void 5144 ahc_reset_current_bus(struct ahc_softc *ahc) 5145 { 5146 u_int8_t scsiseq; 5147 5148 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5149 scsiseq = ahc_inb(ahc, SCSISEQ); 5150 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5151 DELAY(AHC_BUSRESET_DELAY); 5152 /* Turn off the bus reset */ 5153 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5154 5155 ahc_clear_intstat(ahc); 5156 5157 /* Re-enable reset interrupts */ 5158 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5159 } 5160 5161 static int 5162 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5163 { 5164 u_int initiator, target, max_scsiid; 5165 u_int sblkctl; 5166 u_int our_id; 5167 int found; 5168 int restart_needed; 5169 char cur_channel; 5170 5171 ahc->pending_device = NULL; 5172 5173 pause_sequencer(ahc); 5174 5175 /* 5176 * Run our command complete fifos to ensure that we perform 5177 * completion processing on any commands that 'completed' 5178 * before the reset occurred. 5179 */ 5180 ahc_run_qoutfifo(ahc); 5181 5182 /* 5183 * Reset the bus if we are initiating this reset 5184 */ 5185 sblkctl = ahc_inb(ahc, SBLKCTL); 5186 cur_channel = 'A'; 5187 if ((ahc->features & AHC_TWIN) != 0 5188 && ((sblkctl & SELBUSB) != 0)) 5189 cur_channel = 'B'; 5190 if (cur_channel != channel) { 5191 /* Case 1: Command for another bus is active 5192 * Stealthily reset the other bus without 5193 * upsetting the current bus. 5194 */ 5195 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5196 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5197 ahc_outb(ahc, SCSISEQ, 5198 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5199 if (initiate_reset) 5200 ahc_reset_current_bus(ahc); 5201 ahc_clear_intstat(ahc); 5202 ahc_outb(ahc, SBLKCTL, sblkctl); 5203 restart_needed = FALSE; 5204 } else { 5205 /* Case 2: A command from this bus is active or we're idle */ 5206 ahc_clear_msg_state(ahc); 5207 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5208 ahc_outb(ahc, SCSISEQ, 5209 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5210 if (initiate_reset) 5211 ahc_reset_current_bus(ahc); 5212 ahc_clear_intstat(ahc); 5213 5214 /* 5215 * Since we are going to restart the sequencer, avoid 5216 * a race in the sequencer that could cause corruption 5217 * of our Q pointers by starting over from index 0. 5218 */ 5219 ahc->qoutfifonext = 0; 5220 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5221 ahc_outb(ahc, SDSCB_QOFF, 0); 5222 else 5223 ahc_outb(ahc, QOUTPOS, 0); 5224 restart_needed = TRUE; 5225 } 5226 5227 /* 5228 * Clean up all the state information for the 5229 * pending transactions on this bus. 5230 */ 5231 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5232 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5233 ROLE_UNKNOWN, XS_RESET); 5234 if (channel == 'B') { 5235 our_id = ahc->our_id_b; 5236 } else { 5237 our_id = ahc->our_id; 5238 } 5239 5240 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5241 5242 /* 5243 * Revert to async/narrow transfers until we renegotiate. 5244 */ 5245 for (target = 0; target <= max_scsiid; target++) { 5246 5247 if (ahc->enabled_targets[target] == NULL) 5248 continue; 5249 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5250 struct ahc_devinfo devinfo; 5251 5252 ahc_compile_devinfo(&devinfo, target, initiator, 5253 AHC_LUN_WILDCARD, 5254 channel, ROLE_UNKNOWN); 5255 ahc_set_width(ahc, &devinfo, 5256 MSG_EXT_WDTR_BUS_8_BIT, 5257 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5258 ahc_set_syncrate(ahc, &devinfo, 5259 /*syncrate*/NULL, /*period*/0, 5260 /*offset*/0, AHC_TRANS_CUR, 5261 /*paused*/TRUE, FALSE); 5262 ahc_update_xfer_mode(ahc, &devinfo); 5263 } 5264 } 5265 5266 if (restart_needed) 5267 restart_sequencer(ahc); 5268 else 5269 unpause_sequencer(ahc); 5270 return found; 5271 } 5272 5273 static int 5274 ahc_match_scb(struct scb *scb, int target, char channel, 5275 int lun, u_int tag, role_t role) 5276 { 5277 int targ = SCB_TARGET(scb); 5278 char chan = SCB_CHANNEL(scb); 5279 int slun = SCB_LUN(scb); 5280 int match; 5281 5282 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5283 if (match != 0) 5284 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5285 if (match != 0) 5286 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5287 5288 return match; 5289 } 5290 5291 static void 5292 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5293 { 5294 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5295 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5296 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5297 ahc->msgout_buf[ahc->msgout_index++] = period; 5298 ahc->msgout_buf[ahc->msgout_index++] = offset; 5299 ahc->msgout_len += 5; 5300 } 5301 5302 static void 5303 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5304 { 5305 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5306 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5307 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5308 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5309 ahc->msgout_len += 4; 5310 } 5311 5312 static void 5313 ahc_calc_residual(struct scb *scb) 5314 { 5315 struct hardware_scb *hscb; 5316 5317 hscb = scb->hscb; 5318 5319 /* 5320 * If the disconnected flag is still set, this is bogus 5321 * residual information left over from a sequencer 5322 * pagin/pageout, so ignore this case. 5323 */ 5324 if ((scb->hscb->control & DISCONNECTED) == 0) { 5325 u_int32_t resid; 5326 int resid_sgs; 5327 int sg; 5328 5329 /* 5330 * Remainder of the SG where the transfer 5331 * stopped. 5332 */ 5333 resid = (hscb->residual_data_count[2] << 16) 5334 | (hscb->residual_data_count[1] <<8) 5335 | (hscb->residual_data_count[0]); 5336 5337 /* 5338 * Add up the contents of all residual 5339 * SG segments that are after the SG where 5340 * the transfer stopped. 5341 */ 5342 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5343 sg = scb->sg_count - resid_sgs; 5344 while (resid_sgs > 0) { 5345 5346 resid += le32toh(scb->sg_list[sg].len); 5347 sg++; 5348 resid_sgs--; 5349 } 5350 scb->xs->resid = resid; 5351 } 5352 5353 /* 5354 * Clean out the residual information in this SCB for its 5355 * next consumer. 5356 */ 5357 hscb->residual_SG_count = 0; 5358 5359 #ifdef AHC_DEBUG 5360 if (ahc_debug & AHC_SHOWMISC) { 5361 scsipi_printaddr(scb->xs->xs_periph); 5362 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5363 } 5364 #endif 5365 } 5366 5367 static void 5368 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5369 { 5370 struct scb *scb; 5371 int pending_ccb_count; 5372 int i; 5373 u_int saved_scbptr; 5374 5375 /* 5376 * Traverse the pending SCB list and ensure that all of the 5377 * SCBs there have the proper settings. 5378 */ 5379 scb = LIST_FIRST(&ahc->pending_ccbs); 5380 pending_ccb_count = 0; 5381 while (scb != NULL) { 5382 struct ahc_devinfo devinfo; 5383 struct scsipi_xfer *xs; 5384 struct scb *pending_scb; 5385 struct hardware_scb *pending_hscb; 5386 struct ahc_initiator_tinfo *tinfo; 5387 struct tmode_tstate *tstate; 5388 u_int our_id, remote_id; 5389 5390 xs = scb->xs; 5391 pending_scb = scb; 5392 pending_hscb = pending_scb->hscb; 5393 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5394 ? ahc->our_id_b : ahc->our_id; 5395 remote_id = xs->xs_periph->periph_target; 5396 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5397 SCB_LUN(pending_scb), 5398 SCB_CHANNEL(pending_scb), 5399 ROLE_UNKNOWN); 5400 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5401 our_id, remote_id, &tstate); 5402 pending_hscb->control &= ~ULTRAENB; 5403 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5404 pending_hscb->control |= ULTRAENB; 5405 pending_hscb->scsirate = tinfo->scsirate; 5406 pending_hscb->scsioffset = tinfo->current.offset; 5407 pending_ccb_count++; 5408 scb = LIST_NEXT(scb, plinks); 5409 } 5410 5411 if (pending_ccb_count == 0) 5412 return; 5413 5414 saved_scbptr = ahc_inb(ahc, SCBPTR); 5415 /* Ensure that the hscbs down on the card match the new information */ 5416 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5417 u_int scb_tag; 5418 5419 ahc_outb(ahc, SCBPTR, i); 5420 scb_tag = ahc_inb(ahc, SCB_TAG); 5421 if (scb_tag != SCB_LIST_NULL) { 5422 struct ahc_devinfo devinfo; 5423 struct scb *pending_scb; 5424 struct scsipi_xfer *xs; 5425 struct hardware_scb *pending_hscb; 5426 struct ahc_initiator_tinfo *tinfo; 5427 struct tmode_tstate *tstate; 5428 u_int our_id, remote_id; 5429 u_int control; 5430 5431 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5432 if (pending_scb->flags == SCB_FREE) 5433 continue; 5434 pending_hscb = pending_scb->hscb; 5435 xs = pending_scb->xs; 5436 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5437 ? ahc->our_id_b : ahc->our_id; 5438 remote_id = xs->xs_periph->periph_target; 5439 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5440 SCB_LUN(pending_scb), 5441 SCB_CHANNEL(pending_scb), 5442 ROLE_UNKNOWN); 5443 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5444 our_id, remote_id, &tstate); 5445 control = ahc_inb(ahc, SCB_CONTROL); 5446 control &= ~ULTRAENB; 5447 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5448 control |= ULTRAENB; 5449 ahc_outb(ahc, SCB_CONTROL, control); 5450 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5451 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5452 } 5453 } 5454 ahc_outb(ahc, SCBPTR, saved_scbptr); 5455 } 5456 5457 #if UNUSED 5458 static void 5459 ahc_dump_targcmd(struct target_cmd *cmd) 5460 { 5461 u_int8_t *byte; 5462 u_int8_t *last_byte; 5463 int i; 5464 5465 byte = &cmd->initiator_channel; 5466 /* Debugging info for received commands */ 5467 last_byte = &cmd[1].initiator_channel; 5468 5469 i = 0; 5470 while (byte < last_byte) { 5471 if (i == 0) 5472 printf("\t"); 5473 printf("%#x", *byte++); 5474 i++; 5475 if (i == 8) { 5476 printf("\n"); 5477 i = 0; 5478 } else { 5479 printf(", "); 5480 } 5481 } 5482 } 5483 #endif 5484 5485 static void 5486 ahc_shutdown(void *arg) 5487 { 5488 struct ahc_softc *ahc; 5489 int i; 5490 u_int sxfrctl1_a, sxfrctl1_b; 5491 5492 ahc = (struct ahc_softc *)arg; 5493 5494 pause_sequencer(ahc); 5495 5496 /* 5497 * Preserve the value of the SXFRCTL1 register for all channels. 5498 * It contains settings that affect termination and we don't want 5499 * to disturb the integrity of the bus during shutdown in case 5500 * we are in a multi-initiator setup. 5501 */ 5502 sxfrctl1_b = 0; 5503 if ((ahc->features & AHC_TWIN) != 0) { 5504 u_int sblkctl; 5505 5506 sblkctl = ahc_inb(ahc, SBLKCTL); 5507 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5508 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5509 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5510 } 5511 5512 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5513 5514 /* This will reset most registers to 0, but not all */ 5515 ahc_reset(ahc); 5516 5517 if ((ahc->features & AHC_TWIN) != 0) { 5518 u_int sblkctl; 5519 5520 sblkctl = ahc_inb(ahc, SBLKCTL); 5521 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5522 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5523 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5524 } 5525 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5526 5527 ahc_outb(ahc, SCSISEQ, 0); 5528 ahc_outb(ahc, SXFRCTL0, 0); 5529 ahc_outb(ahc, DSPCISTATUS, 0); 5530 5531 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5532 ahc_outb(ahc, i, 0); 5533 } 5534 5535 #if defined(AHC_DEBUG) && 0 5536 static void 5537 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5538 { 5539 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5540 5541 printf("\tcurrent:\n"); 5542 printf("\t\twidth %u period %u offset %u flags %x\n", 5543 tinfo->current.width, tinfo->current.period, 5544 tinfo->current.offset, tinfo->current.ppr_flags); 5545 5546 printf("\tgoal:\n"); 5547 printf("\t\twidth %u period %u offset %u flags %x\n", 5548 tinfo->goal.width, tinfo->goal.period, 5549 tinfo->goal.offset, tinfo->goal.ppr_flags); 5550 5551 printf("\tuser:\n"); 5552 printf("\t\twidth %u period %u offset %u flags %x\n", 5553 tinfo->user.width, tinfo->user.period, 5554 tinfo->user.offset, tinfo->user.ppr_flags); 5555 } 5556 #endif 5557 5558 static int 5559 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5560 int nocmdcheck) 5561 { 5562 #ifdef AHC_NO_TAGS 5563 return 0; 5564 #else 5565 char channel; 5566 u_int our_id, target; 5567 struct tmode_tstate *tstate; 5568 struct ahc_devinfo devinfo; 5569 5570 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5571 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5572 target = xs->xs_periph->periph_target; 5573 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5574 5575 ahc_compile_devinfo(&devinfo, our_id, target, 5576 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5577 5578 return (tstate->tagenable & devinfo.target_mask); 5579 #endif 5580 } 5581
Indexes created Thu Oct 02 10:09:58 GMT 2025