aic7xxx.c revision 1.83
1 /* $NetBSD: aic7xxx.c,v 1.83 2001/11/13 13:14:33 lukem Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.83 2001/11/13 13:14:33 lukem Exp $"); 91 92 #include "opt_ddb.h" 93 #include "opt_ahc.h" 94 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 #include <sys/buf.h> 101 #include <sys/proc.h> 102 #include <sys/scsiio.h> 103 104 #include <machine/bus.h> 105 #include <machine/intr.h> 106 107 #include <dev/scsipi/scsi_all.h> 108 #include <dev/scsipi/scsipi_all.h> 109 #include <dev/scsipi/scsi_message.h> 110 #include <dev/scsipi/scsipi_debug.h> 111 #include <dev/scsipi/scsiconf.h> 112 113 #include <uvm/uvm_extern.h> 114 115 #include <dev/ic/aic7xxxvar.h> 116 #include <dev/microcode/aic7xxx/sequencer.h> 117 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 118 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 119 120 #define ALL_CHANNELS '\0' 121 #define ALL_TARGETS_MASK 0xFFFF 122 #define INITIATOR_WILDCARD (~0) 123 124 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 125 ((periph)->periph_channel->chan_channel == 1) 126 #define SIM_CHANNEL(ahc, periph) \ 127 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 128 #define SIM_SCSI_ID(ahc, periph) \ 129 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 130 #define SCB_IS_SCSIBUS_B(scb) \ 131 (((scb)->hscb->tcl & SELBUSB) != 0) 132 #define SCB_TARGET(scb) \ 133 (((scb)->hscb->tcl & TID) >> 4) 134 #define SCB_CHANNEL(scb) \ 135 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 136 #define SCB_LUN(scb) \ 137 ((scb)->hscb->tcl & LID) 138 #define SCB_TARGET_OFFSET(scb) \ 139 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 140 #define SCB_TARGET_MASK(scb) \ 141 (0x01 << (SCB_TARGET_OFFSET(scb))) 142 #define TCL_CHANNEL(ahc, tcl) \ 143 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 144 #define TCL_SCSI_ID(ahc, tcl) \ 145 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 146 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 147 #define TCL_LUN(tcl) ((tcl) & LID) 148 149 #define XS_TCL(ahc, xs) \ 150 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 151 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 152 | ((xs)->xs_periph->periph_lun & 0x07)) 153 154 const char * const ahc_chip_names[] = 155 { 156 "NONE", 157 "aic7770", 158 "aic7850", 159 "aic7855", 160 "aic7859", 161 "aic7860", 162 "aic7870", 163 "aic7880", 164 "aic7890/91", 165 "aic7892", 166 "aic7895", 167 "aic7896/97", 168 "aic7899" 169 }; 170 171 typedef enum { 172 ROLE_UNKNOWN, 173 ROLE_INITIATOR, 174 ROLE_TARGET 175 } role_t; 176 177 struct ahc_devinfo { 178 int our_scsiid; 179 int target_offset; 180 u_int16_t target_mask; 181 u_int8_t target; 182 u_int8_t lun; 183 char channel; 184 role_t role; /* 185 * Only guaranteed to be correct if not 186 * in the busfree state. 187 */ 188 }; 189 190 typedef enum { 191 SEARCH_COMPLETE, 192 SEARCH_COUNT, 193 SEARCH_REMOVE 194 } ahc_search_action; 195 196 #ifdef AHC_DEBUG 197 static int ahc_debug = AHC_DEBUG; 198 #endif 199 200 static int ahcinitscbdata(struct ahc_softc *); 201 static void ahcfiniscbdata(struct ahc_softc *); 202 203 #if UNUSED 204 static void ahc_dump_targcmd(struct target_cmd *); 205 #endif 206 static void ahc_shutdown(void *arg); 207 static void ahc_action(struct scsipi_channel *, 208 scsipi_adapter_req_t, void *); 209 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 210 struct proc *); 211 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 212 static int ahc_poll(struct ahc_softc *, int); 213 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 214 struct scb *); 215 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 216 static void ahcallocscbs(struct ahc_softc *); 217 #if UNUSED 218 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 219 struct scb *); 220 #endif 221 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 222 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 223 char, role_t); 224 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 225 static void ahc_done(struct ahc_softc *, struct scb *); 226 static struct tmode_tstate * 227 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 228 #if UNUSED 229 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 230 #endif 231 static void ahc_handle_seqint(struct ahc_softc *, u_int); 232 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 233 static void ahc_build_transfer_msg(struct ahc_softc *, 234 struct ahc_devinfo *); 235 static void ahc_setup_initiator_msgout(struct ahc_softc *, 236 struct ahc_devinfo *, 237 struct scb *); 238 static void ahc_setup_target_msgin(struct ahc_softc *, 239 struct ahc_devinfo *); 240 static void ahc_clear_msg_state(struct ahc_softc *); 241 static void ahc_handle_message_phase(struct ahc_softc *, 242 struct scsipi_periph *); 243 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 244 245 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 246 struct ahc_devinfo *); 247 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 248 struct ahc_devinfo *); 249 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 250 int, char *, int); 251 #ifdef AHC_DUMP_SEQ 252 static void ahc_dumpseq(struct ahc_softc *); 253 #endif 254 static void ahc_loadseq(struct ahc_softc *); 255 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 256 int, int *); 257 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 258 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 259 #if defined(AHC_DEBUG) 260 static void ahc_print_scb(struct scb *); 261 #endif 262 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 263 role_t, scb_flag, ahc_search_action); 264 static int ahc_reset_channel(struct ahc_softc *, char, int); 265 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 266 role_t, int); 267 static int ahc_search_disc_list(struct ahc_softc *, int, 268 char, int, u_int, int, int, int); 269 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 270 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 271 static void ahc_clear_intstat(struct ahc_softc *); 272 static void ahc_reset_current_bus(struct ahc_softc *); 273 static const struct ahc_syncrate * 274 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 275 static const struct ahc_syncrate * 276 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 277 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 278 static void ahc_validate_offset(struct ahc_softc *, 279 const struct ahc_syncrate *, u_int *, int); 280 static void ahc_update_target_msg_request(struct ahc_softc *, 281 struct ahc_devinfo *, 282 struct ahc_initiator_tinfo *, 283 int, int); 284 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 285 const struct ahc_syncrate *, u_int, u_int, 286 u_int, int, int); 287 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 288 u_int, u_int, int, int); 289 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 290 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 291 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 292 293 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 294 295 static void ahc_calc_residual(struct scb *); 296 297 static void ahc_update_pending_syncrates(struct ahc_softc *); 298 299 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 300 301 static void ahc_timeout (void *); 302 static __inline int sequencer_paused(struct ahc_softc *); 303 static __inline void pause_sequencer(struct ahc_softc *); 304 static __inline void unpause_sequencer(struct ahc_softc *); 305 static void restart_sequencer(struct ahc_softc *); 306 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 307 308 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 309 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 310 311 static __inline void ahc_freeze_ccb(struct scb *); 312 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 313 static void ahc_run_qoutfifo(struct ahc_softc *); 314 315 static __inline struct ahc_initiator_tinfo * 316 ahc_fetch_transinfo(struct ahc_softc *, 317 char, u_int, u_int, 318 struct tmode_tstate **); 319 static void ahcfreescb(struct ahc_softc *, struct scb *); 320 static __inline struct scb *ahcgetscb(struct ahc_softc *); 321 322 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 323 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 324 int *, const char *, const char *); 325 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 326 caddr_t, bus_dma_segment_t *, int); 327 static void ahcminphys(struct buf *); 328 329 static __inline void ahc_swap_hscb(struct hardware_scb *); 330 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 331 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 332 333 #if defined(AHC_DEBUG) && 0 334 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 335 #endif 336 337 static __inline void 338 ahc_swap_hscb(struct hardware_scb *hscb) 339 { 340 hscb->SG_pointer = htole32(hscb->SG_pointer); 341 hscb->data = htole32(hscb->data); 342 hscb->datalen = htole32(hscb->datalen); 343 /* 344 * No need to swap cmdpointer; it's either 0 or set to 345 * cmdstore_busaddr, which is already swapped. 346 */ 347 } 348 349 static __inline void 350 ahc_swap_sg(struct ahc_dma_seg *sg) 351 { 352 sg->addr = htole32(sg->addr); 353 sg->len = htole32(sg->len); 354 } 355 356 static void 357 ahcminphys(bp) 358 struct buf *bp; 359 { 360 /* 361 * Even though the card can transfer up to 16megs per command 362 * we are limited by the number of segments in the dma segment 363 * list that we can hold. The worst case is that all pages are 364 * discontinuous physically, hense the "page per segment" limit 365 * enforced here. 366 */ 367 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 368 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 369 } 370 minphys(bp); 371 } 372 373 374 static __inline u_int32_t 375 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 376 { 377 return (ahc->scb_data->hscb_busaddr 378 + (sizeof(struct hardware_scb) * index)); 379 } 380 381 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 382 383 static __inline int 384 sequencer_paused(struct ahc_softc *ahc) 385 { 386 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 387 } 388 389 static __inline void 390 pause_sequencer(struct ahc_softc *ahc) 391 { 392 ahc_outb(ahc, HCNTRL, ahc->pause); 393 394 /* 395 * Since the sequencer can disable pausing in a critical section, we 396 * must loop until it actually stops. 397 */ 398 while (sequencer_paused(ahc) == 0) 399 ; 400 } 401 402 static __inline void 403 unpause_sequencer(struct ahc_softc *ahc) 404 { 405 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 406 ahc_outb(ahc, HCNTRL, ahc->unpause); 407 } 408 409 /* 410 * Restart the sequencer program from address zero 411 */ 412 static void 413 restart_sequencer(struct ahc_softc *ahc) 414 { 415 u_int i; 416 417 pause_sequencer(ahc); 418 419 /* 420 * Everytime we restart the sequencer, there 421 * is the possiblitity that we have restarted 422 * within a three instruction window where an 423 * SCB has been marked free but has not made it 424 * onto the free list. Since SCSI events(bus reset, 425 * unexpected bus free) will always freeze the 426 * sequencer, we cannot close this window. To 427 * avoid losing an SCB, we reconsitute the free 428 * list every time we restart the sequencer. 429 */ 430 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 431 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 432 433 ahc_outb(ahc, SCBPTR, i); 434 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 435 ahc_add_curscb_to_free_list(ahc); 436 } 437 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 438 unpause_sequencer(ahc); 439 } 440 441 static __inline u_int 442 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 443 { 444 u_int scbid; 445 446 scbid = ahc->untagged_scbs[tcl]; 447 if (unbusy) { 448 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 449 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 450 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 451 } 452 453 return (scbid); 454 } 455 456 static __inline void 457 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 458 { 459 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 460 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 461 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 462 } 463 464 static __inline int 465 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 466 { 467 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 468 } 469 470 static __inline void 471 ahc_freeze_ccb(struct scb *scb) 472 { 473 struct scsipi_xfer *xs = scb->xs; 474 475 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 476 scsipi_periph_freeze(xs->xs_periph, 1); 477 scb->flags |= SCB_FREEZE_QUEUE; 478 } 479 } 480 481 static __inline void 482 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 483 { 484 xs->error = status; 485 } 486 487 static __inline struct ahc_initiator_tinfo * 488 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 489 u_int remote_id, struct tmode_tstate **tstate) 490 { 491 /* 492 * Transfer data structures are stored from the perspective 493 * of the target role. Since the parameters for a connection 494 * in the initiator role to a given target are the same as 495 * when the roles are reversed, we pretend we are the target. 496 */ 497 if (channel == 'B') 498 our_id += 8; 499 *tstate = ahc->enabled_targets[our_id]; 500 return (&(*tstate)->transinfo[remote_id]); 501 } 502 503 static void 504 ahc_run_qoutfifo(struct ahc_softc *ahc) 505 { 506 struct scb *scb; 507 u_int scb_index; 508 509 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 510 256, BUS_DMASYNC_POSTREAD); 511 512 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 513 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 514 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 515 516 scb = &ahc->scb_data->scbarray[scb_index]; 517 if (scb_index >= ahc->scb_data->numscbs 518 || (scb->flags & SCB_ACTIVE) == 0) { 519 printf("%s: WARNING no command for scb %d " 520 "(cmdcmplt)\nQOUTPOS = %d\n", 521 ahc_name(ahc), scb_index, 522 ahc->qoutfifonext - 1); 523 continue; 524 } 525 526 /* 527 * Save off the residual 528 * if there is one. 529 */ 530 if (scb->hscb->residual_SG_count != 0) 531 ahc_calc_residual(scb); 532 else 533 scb->xs->resid = 0; 534 #ifdef AHC_DEBUG 535 if (ahc_debug & AHC_SHOWSCBS) { 536 scsipi_printaddr(scb->xs->xs_periph); 537 printf("run_qoutfifo: SCB %x complete\n", 538 scb->hscb->tag); 539 } 540 #endif 541 ahc_done(ahc, scb); 542 } 543 } 544 545 546 /* 547 * An scb (and hence an scb entry on the board) is put onto the 548 * free list. 549 */ 550 static void 551 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 552 { 553 struct hardware_scb *hscb; 554 int opri; 555 556 hscb = scb->hscb; 557 558 #ifdef AHC_DEBUG 559 if (ahc_debug & AHC_SHOWSCBALLOC) 560 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 561 #endif 562 563 opri = splbio(); 564 565 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 566 (scb->flags & SCB_RECOVERY_SCB) != 0) { 567 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 568 scsipi_channel_thaw(&ahc->sc_channel, 1); 569 if (ahc->features & AHC_TWIN) 570 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 571 } 572 573 /* Clean up for the next user */ 574 scb->flags = SCB_FREE; 575 hscb->control = 0; 576 hscb->status = 0; 577 578 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 579 580 splx(opri); 581 } 582 583 /* 584 * Get a free scb, either one already assigned to a hardware slot 585 * on the adapter or one that will require an SCB to be paged out before 586 * use. If there are none, see if we can allocate a new SCB. Otherwise 587 * either return an error or sleep. 588 */ 589 static __inline struct scb * 590 ahcgetscb(struct ahc_softc *ahc) 591 { 592 struct scb *scbp; 593 int opri;; 594 595 opri = splbio(); 596 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 597 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 598 } else { 599 ahcallocscbs(ahc); 600 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 601 if (scbp != NULL) 602 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 603 } 604 605 splx(opri); 606 607 #ifdef AHC_DEBUG 608 if (ahc_debug & AHC_SHOWSCBALLOC) { 609 if (scbp != NULL) 610 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 611 scbp->hscb->tag); 612 else 613 printf("%s: failed to allocate new SCB\n", 614 ahc_name(ahc)); 615 } 616 #endif 617 618 return (scbp); 619 } 620 621 static int 622 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 623 bus_dma_tag_t tag; 624 int size; 625 int flags; 626 bus_dmamap_t *mapp; 627 caddr_t *vaddr; 628 bus_addr_t *baddr; 629 bus_dma_segment_t *seg; 630 int *nseg; 631 const char *myname, *what; 632 { 633 int error, level = 0; 634 635 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 636 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 637 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 638 myname, what, error); 639 goto out; 640 } 641 level++; 642 643 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 644 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 645 printf("%s: failed to map DMA mem for %s, error = %d\n", 646 myname, what, error); 647 goto out; 648 } 649 level++; 650 651 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 652 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 653 printf("%s: failed to create DMA map for %s, error = %d\n", 654 myname, what, error); 655 goto out; 656 } 657 level++; 658 659 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 660 BUS_DMA_NOWAIT)) != 0) { 661 printf("%s: failed to load DMA map for %s, error = %d\n", 662 myname, what, error); 663 goto out; 664 } 665 666 *baddr = (*mapp)->dm_segs[0].ds_addr; 667 668 #ifdef AHC_DEBUG 669 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 670 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 671 *nseg, size); 672 #endif 673 674 return 0; 675 out: 676 switch (level) { 677 case 3: 678 bus_dmamap_destroy(tag, *mapp); 679 /* FALLTHROUGH */ 680 case 2: 681 bus_dmamem_unmap(tag, *vaddr, size); 682 /* FALLTHROUGH */ 683 case 1: 684 bus_dmamem_free(tag, seg, *nseg); 685 break; 686 default: 687 break; 688 } 689 690 return error; 691 } 692 693 static void 694 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 695 bus_dma_tag_t tag; 696 int size; 697 bus_dmamap_t map; 698 caddr_t vaddr; 699 bus_dma_segment_t *seg; 700 int nseg; 701 { 702 703 bus_dmamap_unload(tag, map); 704 bus_dmamap_destroy(tag, map); 705 bus_dmamem_unmap(tag, vaddr, size); 706 bus_dmamem_free(tag, seg, nseg); 707 } 708 709 char * 710 ahc_name(struct ahc_softc *ahc) 711 { 712 return (ahc->sc_dev.dv_xname); 713 } 714 715 #ifdef AHC_DEBUG 716 static void 717 ahc_print_scb(struct scb *scb) 718 { 719 struct hardware_scb *hscb = scb->hscb; 720 721 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 722 scb, 723 hscb->tag, 724 hscb->control, 725 hscb->tcl, 726 hscb->cmdlen, 727 (unsigned long)le32toh(hscb->cmdpointer)); 728 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 729 le32toh(hscb->datalen), 730 (unsigned long)(le32toh(hscb->data)), 731 hscb->SG_count, 732 (unsigned long)(le32toh(hscb->SG_pointer))); 733 printf(" sg_addr:%lx sg_len:%lu\n", 734 (unsigned long)(le32toh(scb->sg_list[0].addr)), 735 (unsigned long)(le32toh(scb->sg_list[0].len))); 736 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 737 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 738 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 739 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 740 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 741 } 742 #endif 743 744 static const struct { 745 u_int8_t errno; 746 const char *errmesg; 747 } hard_error[] = { 748 { ILLHADDR, "Illegal Host Access" }, 749 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 750 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 751 { SQPARERR, "Sequencer Parity Error" }, 752 { DPARERR, "Data-path Parity Error" }, 753 { MPARERR, "Scratch or SCB Memory Parity Error" }, 754 { PCIERRSTAT, "PCI Error detected" }, 755 { CIOPARERR, "CIOBUS Parity Error" }, 756 }; 757 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 758 759 static const struct { 760 u_int8_t phase; 761 u_int8_t mesg_out; /* Message response to parity errors */ 762 const char *phasemsg; 763 } phase_table[] = { 764 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 765 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 766 { P_COMMAND, MSG_NOOP, "in Command phase" }, 767 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 768 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 769 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 770 { P_BUSFREE, MSG_NOOP, "while idle" }, 771 { 0, MSG_NOOP, "in unknown phase" } 772 }; 773 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 774 775 /* 776 * Valid SCSIRATE values. (p. 3-17) 777 * Provides a mapping of transfer periods in ns to the proper value to 778 * stick in the scsiscfr reg to use that transfer rate. 779 */ 780 #define AHC_SYNCRATE_DT 0 781 #define AHC_SYNCRATE_ULTRA2 1 782 #define AHC_SYNCRATE_ULTRA 3 783 #define AHC_SYNCRATE_FAST 6 784 static const struct ahc_syncrate ahc_syncrates[] = { 785 /* ultra2 fast/ultra period rate */ 786 { 0x42, 0x000, 9, "80.0" }, 787 { 0x03, 0x000, 10, "40.0" }, 788 { 0x04, 0x000, 11, "33.0" }, 789 { 0x05, 0x100, 12, "20.0" }, 790 { 0x06, 0x110, 15, "16.0" }, 791 { 0x07, 0x120, 18, "13.4" }, 792 { 0x08, 0x000, 25, "10.0" }, 793 { 0x19, 0x010, 31, "8.0" }, 794 { 0x1a, 0x020, 37, "6.67" }, 795 { 0x1b, 0x030, 43, "5.7" }, 796 { 0x1c, 0x040, 50, "5.0" }, 797 { 0x00, 0x050, 56, "4.4" }, 798 { 0x00, 0x060, 62, "4.0" }, 799 { 0x00, 0x070, 68, "3.6" }, 800 { 0x00, 0x000, 0, NULL } 801 }; 802 803 /* 804 * Allocate a controller structure for a new device and initialize it. 805 */ 806 int 807 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 808 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 809 ahc_flag flags) 810 { 811 struct scb_data *scb_data; 812 813 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT); 814 if (scb_data == NULL) { 815 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 816 return -1; 817 } 818 memset(scb_data, 0, sizeof (struct scb_data)); 819 LIST_INIT(&ahc->pending_ccbs); 820 ahc->tag = st; 821 ahc->bsh = sh; 822 ahc->parent_dmat = parent_dmat; 823 ahc->chip = chip; 824 ahc->features = features; 825 ahc->flags = flags; 826 ahc->scb_data = scb_data; 827 828 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 829 /* The IRQMS bit is only valid on VL and EISA chips */ 830 if ((ahc->chip & AHC_PCI) != 0) 831 ahc->unpause &= ~IRQMS; 832 ahc->pause = ahc->unpause | PAUSE; 833 return (0); 834 } 835 836 void 837 ahc_free(ahc) 838 struct ahc_softc *ahc; 839 { 840 ahcfiniscbdata(ahc); 841 if (ahc->init_level != 0) 842 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 843 ahc->shared_data_dmamap, ahc->qoutfifo, 844 &ahc->shared_data_seg, ahc->shared_data_nseg); 845 846 if (ahc->scb_data != NULL) 847 free(ahc->scb_data, M_DEVBUF); 848 if (ahc->bus_data != NULL) 849 free(ahc->bus_data, M_DEVBUF); 850 return; 851 } 852 853 static int 854 ahcinitscbdata(struct ahc_softc *ahc) 855 { 856 struct scb_data *scb_data; 857 int i; 858 859 scb_data = ahc->scb_data; 860 SLIST_INIT(&scb_data->free_scbs); 861 SLIST_INIT(&scb_data->sg_maps); 862 863 /* Allocate SCB resources */ 864 scb_data->scbarray = 865 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 866 M_DEVBUF, M_NOWAIT); 867 if (scb_data->scbarray == NULL) 868 return (ENOMEM); 869 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); 870 871 /* Determine the number of hardware SCBs and initialize them */ 872 873 scb_data->maxhscbs = ahc_probe_scbs(ahc); 874 /* SCB 0 heads the free list */ 875 ahc_outb(ahc, FREE_SCBH, 0); 876 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 877 ahc_outb(ahc, SCBPTR, i); 878 879 /* Clear the control byte. */ 880 ahc_outb(ahc, SCB_CONTROL, 0); 881 882 /* Set the next pointer */ 883 ahc_outb(ahc, SCB_NEXT, i+1); 884 885 /* Make the tag number invalid */ 886 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 887 } 888 889 /* Make sure that the last SCB terminates the free list */ 890 ahc_outb(ahc, SCBPTR, i-1); 891 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 892 893 /* Ensure we clear the 0 SCB's control byte. */ 894 ahc_outb(ahc, SCBPTR, 0); 895 ahc_outb(ahc, SCB_CONTROL, 0); 896 897 scb_data->maxhscbs = i; 898 899 if (ahc->scb_data->maxhscbs == 0) 900 panic("%s: No SCB space found", ahc_name(ahc)); 901 902 /* 903 * Create our DMA tags. These tags define the kinds of device 904 * accessible memory allocations and memory mappings we will 905 * need to perform during normal operation. 906 * 907 * Unless we need to further restrict the allocation, we rely 908 * on the restrictions of the parent dmat, hence the common 909 * use of MAXADDR and MAXSIZE. 910 */ 911 912 if (ahc_createdmamem(ahc->parent_dmat, 913 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 914 &scb_data->hscb_dmamap, 915 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 916 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 917 "hardware SCB structures") < 0) 918 goto error_exit; 919 920 scb_data->init_level++; 921 922 if (ahc_createdmamem(ahc->parent_dmat, 923 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 924 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 925 &scb_data->sense_busaddr, &scb_data->sense_seg, 926 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 927 goto error_exit; 928 929 scb_data->init_level++; 930 931 /* Perform initial CCB allocation */ 932 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 933 ahcallocscbs(ahc); 934 935 if (scb_data->numscbs == 0) { 936 printf("%s: ahc_init_scb_data - " 937 "Unable to allocate initial scbs\n", 938 ahc_name(ahc)); 939 goto error_exit; 940 } 941 942 scb_data->init_level++; 943 944 /* 945 * Note that we were successfull 946 */ 947 return 0; 948 949 error_exit: 950 951 return ENOMEM; 952 } 953 954 static void 955 ahcfiniscbdata(struct ahc_softc *ahc) 956 { 957 struct scb_data *scb_data; 958 959 scb_data = ahc->scb_data; 960 961 switch (scb_data->init_level) { 962 default: 963 case 3: 964 { 965 struct sg_map_node *sg_map; 966 967 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 968 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 969 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 970 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 971 &sg_map->sg_dmasegs, sg_map->sg_nseg); 972 free(sg_map, M_DEVBUF); 973 } 974 } 975 /*FALLTHROUGH*/ 976 case 2: 977 ahc_freedmamem(ahc->parent_dmat, 978 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 979 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 980 &scb_data->sense_seg, scb_data->sense_nseg); 981 /*FALLTHROUGH*/ 982 case 1: 983 ahc_freedmamem(ahc->parent_dmat, 984 AHC_SCB_MAX * sizeof(struct hardware_scb), 985 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 986 &scb_data->hscb_seg, scb_data->hscb_nseg); 987 /*FALLTHROUGH*/ 988 } 989 if (scb_data->scbarray != NULL) 990 free(scb_data->scbarray, M_DEVBUF); 991 } 992 993 int 994 ahc_reset(struct ahc_softc *ahc) 995 { 996 u_int sblkctl; 997 int wait; 998 999 #ifdef AHC_DUMP_SEQ 1000 if (ahc->init_level == 0) 1001 ahc_dumpseq(ahc); 1002 #endif 1003 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1004 /* 1005 * Ensure that the reset has finished 1006 */ 1007 wait = 1000; 1008 do { 1009 DELAY(1000); 1010 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1011 1012 if (wait == 0) { 1013 printf("%s: WARNING - Failed chip reset! " 1014 "Trying to initialize anyway.\n", ahc_name(ahc)); 1015 } 1016 ahc_outb(ahc, HCNTRL, ahc->pause); 1017 1018 /* Determine channel configuration */ 1019 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1020 /* No Twin Channel PCI cards */ 1021 if ((ahc->chip & AHC_PCI) != 0) 1022 sblkctl &= ~SELBUSB; 1023 switch (sblkctl) { 1024 case 0: 1025 /* Single Narrow Channel */ 1026 break; 1027 case 2: 1028 /* Wide Channel */ 1029 ahc->features |= AHC_WIDE; 1030 break; 1031 case 8: 1032 /* Twin Channel */ 1033 ahc->features |= AHC_TWIN; 1034 break; 1035 default: 1036 printf(" Unsupported adapter type. Ignoring\n"); 1037 return(-1); 1038 } 1039 1040 return (0); 1041 } 1042 1043 /* 1044 * Called when we have an active connection to a target on the bus, 1045 * this function finds the nearest syncrate to the input period limited 1046 * by the capabilities of the bus connectivity of the target. 1047 */ 1048 static const struct ahc_syncrate * 1049 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1050 u_int maxsync; 1051 1052 if ((ahc->features & AHC_ULTRA2) != 0) { 1053 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1054 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1055 maxsync = AHC_SYNCRATE_ULTRA2; 1056 } else { 1057 maxsync = AHC_SYNCRATE_ULTRA; 1058 } 1059 } else if ((ahc->features & AHC_ULTRA) != 0) { 1060 maxsync = AHC_SYNCRATE_ULTRA; 1061 } else { 1062 maxsync = AHC_SYNCRATE_FAST; 1063 } 1064 return (ahc_find_syncrate(ahc, period, maxsync)); 1065 } 1066 1067 /* 1068 * Look up the valid period to SCSIRATE conversion in our table. 1069 * Return the period and offset that should be sent to the target 1070 * if this was the beginning of an SDTR. 1071 */ 1072 static const struct ahc_syncrate * 1073 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1074 { 1075 const struct ahc_syncrate *syncrate; 1076 1077 syncrate = &ahc_syncrates[maxsync]; 1078 while ((syncrate->rate != NULL) 1079 && ((ahc->features & AHC_ULTRA2) == 0 1080 || (syncrate->sxfr_u2 != 0))) { 1081 1082 if (*period <= syncrate->period) { 1083 /* 1084 * When responding to a target that requests 1085 * sync, the requested rate may fall between 1086 * two rates that we can output, but still be 1087 * a rate that we can receive. Because of this, 1088 * we want to respond to the target with 1089 * the same rate that it sent to us even 1090 * if the period we use to send data to it 1091 * is lower. Only lower the response period 1092 * if we must. 1093 */ 1094 if (syncrate == &ahc_syncrates[maxsync]) 1095 *period = syncrate->period; 1096 break; 1097 } 1098 syncrate++; 1099 } 1100 1101 if ((*period == 0) 1102 || (syncrate->rate == NULL) 1103 || ((ahc->features & AHC_ULTRA2) != 0 1104 && (syncrate->sxfr_u2 == 0))) { 1105 /* Use asynchronous transfers. */ 1106 *period = 0; 1107 syncrate = NULL; 1108 } 1109 return (syncrate); 1110 } 1111 1112 static u_int 1113 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1114 { 1115 const struct ahc_syncrate *syncrate; 1116 1117 if ((ahc->features & AHC_ULTRA2) != 0) 1118 scsirate &= SXFR_ULTRA2; 1119 else 1120 scsirate &= SXFR; 1121 1122 syncrate = &ahc_syncrates[maxsync]; 1123 while (syncrate->rate != NULL) { 1124 1125 if ((ahc->features & AHC_ULTRA2) != 0) { 1126 if (syncrate->sxfr_u2 == 0) 1127 break; 1128 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1129 return (syncrate->period); 1130 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1131 return (syncrate->period); 1132 } 1133 syncrate++; 1134 } 1135 return (0); /* async */ 1136 } 1137 1138 static void 1139 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1140 u_int *offset, int wide) 1141 { 1142 u_int maxoffset; 1143 1144 /* Limit offset to what we can do */ 1145 if (syncrate == NULL) { 1146 maxoffset = 0; 1147 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1148 maxoffset = MAX_OFFSET_ULTRA2; 1149 } else { 1150 if (wide) 1151 maxoffset = MAX_OFFSET_16BIT; 1152 else 1153 maxoffset = MAX_OFFSET_8BIT; 1154 } 1155 *offset = MIN(*offset, maxoffset); 1156 } 1157 1158 static void 1159 ahc_update_target_msg_request(struct ahc_softc *ahc, 1160 struct ahc_devinfo *devinfo, 1161 struct ahc_initiator_tinfo *tinfo, 1162 int force, int paused) 1163 { 1164 u_int targ_msg_req_orig; 1165 1166 targ_msg_req_orig = ahc->targ_msg_req; 1167 if (tinfo->current.period != tinfo->goal.period 1168 || tinfo->current.width != tinfo->goal.width 1169 || tinfo->current.offset != tinfo->goal.offset 1170 || (force 1171 && (tinfo->goal.period != 0 1172 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1173 ahc->targ_msg_req |= devinfo->target_mask; 1174 } else { 1175 ahc->targ_msg_req &= ~devinfo->target_mask; 1176 } 1177 1178 if (ahc->targ_msg_req != targ_msg_req_orig) { 1179 /* Update the message request bit for this target */ 1180 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1181 if (paused) { 1182 ahc_outb(ahc, TARGET_MSG_REQUEST, 1183 ahc->targ_msg_req & 0xFF); 1184 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1185 (ahc->targ_msg_req >> 8) & 0xFF); 1186 } else { 1187 ahc_outb(ahc, HS_MAILBOX, 1188 0x01 << HOST_MAILBOX_SHIFT); 1189 } 1190 } else { 1191 if (!paused) 1192 pause_sequencer(ahc); 1193 1194 ahc_outb(ahc, TARGET_MSG_REQUEST, 1195 ahc->targ_msg_req & 0xFF); 1196 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1197 (ahc->targ_msg_req >> 8) & 0xFF); 1198 1199 if (!paused) 1200 unpause_sequencer(ahc); 1201 } 1202 } 1203 } 1204 1205 static void 1206 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1207 const struct ahc_syncrate *syncrate, 1208 u_int period, u_int offset, u_int type, int paused, int done) 1209 { 1210 struct ahc_initiator_tinfo *tinfo; 1211 struct tmode_tstate *tstate; 1212 u_int old_period; 1213 u_int old_offset; 1214 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1215 1216 if (syncrate == NULL) { 1217 period = 0; 1218 offset = 0; 1219 } 1220 1221 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1222 devinfo->target, &tstate); 1223 old_period = tinfo->current.period; 1224 old_offset = tinfo->current.offset; 1225 1226 if ((type & AHC_TRANS_CUR) != 0 1227 && (old_period != period || old_offset != offset)) { 1228 u_int scsirate; 1229 1230 scsirate = tinfo->scsirate; 1231 if ((ahc->features & AHC_ULTRA2) != 0) { 1232 1233 /* XXX */ 1234 /* Force single edge until DT is fully implemented */ 1235 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1236 if (syncrate != NULL) 1237 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1238 1239 if (active) 1240 ahc_outb(ahc, SCSIOFFSET, offset); 1241 } else { 1242 1243 scsirate &= ~(SXFR|SOFS); 1244 /* 1245 * Ensure Ultra mode is set properly for 1246 * this target. 1247 */ 1248 tstate->ultraenb &= ~devinfo->target_mask; 1249 if (syncrate != NULL) { 1250 if (syncrate->sxfr & ULTRA_SXFR) { 1251 tstate->ultraenb |= 1252 devinfo->target_mask; 1253 } 1254 scsirate |= syncrate->sxfr & SXFR; 1255 scsirate |= offset & SOFS; 1256 } 1257 if (active) { 1258 u_int sxfrctl0; 1259 1260 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1261 sxfrctl0 &= ~FAST20; 1262 if (tstate->ultraenb & devinfo->target_mask) 1263 sxfrctl0 |= FAST20; 1264 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1265 } 1266 } 1267 if (active) 1268 ahc_outb(ahc, SCSIRATE, scsirate); 1269 1270 tinfo->scsirate = scsirate; 1271 tinfo->current.period = period; 1272 tinfo->current.offset = offset; 1273 1274 /* Update the syncrates in any pending scbs */ 1275 ahc_update_pending_syncrates(ahc); 1276 } 1277 1278 if ((type & AHC_TRANS_GOAL) != 0) { 1279 tinfo->goal.period = period; 1280 tinfo->goal.offset = offset; 1281 } 1282 1283 if ((type & AHC_TRANS_USER) != 0) { 1284 tinfo->user.period = period; 1285 tinfo->user.offset = offset; 1286 } 1287 1288 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1289 /*force*/FALSE, 1290 paused); 1291 } 1292 1293 static void 1294 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1295 u_int width, u_int type, int paused, int done) 1296 { 1297 struct ahc_initiator_tinfo *tinfo; 1298 struct tmode_tstate *tstate; 1299 u_int oldwidth; 1300 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1301 1302 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1303 devinfo->target, &tstate); 1304 oldwidth = tinfo->current.width; 1305 1306 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1307 u_int scsirate; 1308 1309 scsirate = tinfo->scsirate; 1310 scsirate &= ~WIDEXFER; 1311 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1312 scsirate |= WIDEXFER; 1313 1314 tinfo->scsirate = scsirate; 1315 1316 if (active) 1317 ahc_outb(ahc, SCSIRATE, scsirate); 1318 1319 tinfo->current.width = width; 1320 } 1321 1322 if ((type & AHC_TRANS_GOAL) != 0) 1323 tinfo->goal.width = width; 1324 if ((type & AHC_TRANS_USER) != 0) 1325 tinfo->user.width = width; 1326 1327 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1328 /*force*/FALSE, paused); 1329 } 1330 1331 static void 1332 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1333 { 1334 struct ahc_initiator_tinfo *tinfo; 1335 struct tmode_tstate *tstate; 1336 1337 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1338 devinfo->target, &tstate); 1339 1340 if (enable) { 1341 tstate->tagenable |= devinfo->target_mask; 1342 } else { 1343 tstate->tagenable &= ~devinfo->target_mask; 1344 tstate->tagdisable |= devinfo->target_mask; 1345 } 1346 } 1347 1348 static void 1349 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1350 { 1351 struct scsipi_xfer_mode xm; 1352 struct ahc_initiator_tinfo *tinfo; 1353 struct tmode_tstate *tstate; 1354 1355 if (ahc->inited_targets[devinfo->target] != 2) 1356 return; 1357 1358 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1359 devinfo->target, &tstate); 1360 1361 xm.xm_target = devinfo->target; 1362 xm.xm_mode = 0; 1363 xm.xm_period = tinfo->current.period; 1364 xm.xm_offset = tinfo->current.offset; 1365 if (tinfo->current.width == 1) 1366 xm.xm_mode |= PERIPH_CAP_WIDE16; 1367 if (tinfo->current.period) 1368 xm.xm_mode |= PERIPH_CAP_SYNC; 1369 if (tstate->tagenable & devinfo->target_mask) 1370 xm.xm_mode |= PERIPH_CAP_TQING; 1371 scsipi_async_event( 1372 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1373 ASYNC_EVENT_XFER_MODE, &xm); 1374 } 1375 1376 /* 1377 * Attach all the sub-devices we can find 1378 */ 1379 int 1380 ahc_attach(struct ahc_softc *ahc) 1381 { 1382 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1383 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1384 if (ahc->flags & AHC_PAGESCBS) { 1385 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1386 ahc->sc_adapter.adapt_max_periph = 16; 1387 } else { 1388 ahc->sc_adapter.adapt_openings = ahc->scb_data->maxhscbs; 1389 if (ahc->scb_data->maxhscbs >= 16) 1390 ahc->sc_adapter.adapt_max_periph = 16; 1391 else 1392 ahc->sc_adapter.adapt_max_periph = 4; 1393 } 1394 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1395 ahc->sc_adapter.adapt_minphys = ahcminphys; 1396 ahc->sc_adapter.adapt_request = ahc_action; 1397 1398 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1399 ahc->sc_channel.chan_bustype = &scsi_bustype; 1400 ahc->sc_channel.chan_channel = 0; 1401 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1402 ahc->sc_channel.chan_nluns = 8; 1403 ahc->sc_channel.chan_id = ahc->our_id; 1404 1405 if (ahc->features & AHC_TWIN) { 1406 ahc->sc_channel_b = ahc->sc_channel; 1407 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1408 ahc->sc_channel_b.chan_channel = 1; 1409 } 1410 1411 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1412 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1413 if (ahc->features & AHC_TWIN) 1414 config_found((void *)ahc, &ahc->sc_channel_b, 1415 scsiprint); 1416 } else { 1417 config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1418 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1419 } 1420 return 1; 1421 } 1422 1423 static void 1424 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1425 { 1426 u_int saved_tcl; 1427 role_t role; 1428 int our_id; 1429 1430 if (ahc_inb(ahc, SSTAT0) & TARGET) 1431 role = ROLE_TARGET; 1432 else 1433 role = ROLE_INITIATOR; 1434 1435 if (role == ROLE_TARGET 1436 && (ahc->features & AHC_MULTI_TID) != 0 1437 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1438 /* We were selected, so pull our id from TARGIDIN */ 1439 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1440 } else if ((ahc->features & AHC_ULTRA2) != 0) 1441 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1442 else 1443 our_id = ahc_inb(ahc, SCSIID) & OID; 1444 1445 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1446 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1447 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1448 role); 1449 } 1450 1451 static void 1452 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1453 u_int lun, char channel, role_t role) 1454 { 1455 devinfo->our_scsiid = our_id; 1456 devinfo->target = target; 1457 devinfo->lun = lun; 1458 devinfo->target_offset = target; 1459 devinfo->channel = channel; 1460 devinfo->role = role; 1461 if (channel == 'B') 1462 devinfo->target_offset += 8; 1463 devinfo->target_mask = (0x01 << devinfo->target_offset); 1464 } 1465 1466 /* 1467 * Catch an interrupt from the adapter 1468 */ 1469 int 1470 ahc_intr(void *arg) 1471 { 1472 struct ahc_softc *ahc; 1473 u_int intstat; 1474 1475 ahc = (struct ahc_softc *)arg; 1476 1477 intstat = ahc_inb(ahc, INTSTAT); 1478 1479 /* 1480 * Any interrupts to process? 1481 */ 1482 if ((intstat & INT_PEND) == 0) { 1483 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1484 #ifdef AHC_DEBUG 1485 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1486 ahc_name(ahc), 1487 ahc_inb(ahc, CCHADDR) | 1488 (ahc_inb(ahc, CCHADDR+1) << 8) 1489 | (ahc_inb(ahc, CCHADDR+2) << 16) 1490 | (ahc_inb(ahc, CCHADDR+3) << 24), 1491 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1492 | (ahc_inb(ahc, HADDR+2) << 16) 1493 | (ahc_inb(ahc, HADDR+3) << 24), 1494 ahc_inb(ahc, SEQADDR0) | 1495 (ahc_inb(ahc, SEQADDR1) << 8)); 1496 #endif 1497 return 1; 1498 } 1499 return 0; 1500 } 1501 1502 #ifdef AHC_DEBUG 1503 if (ahc_debug & AHC_SHOWINTR) { 1504 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1505 } 1506 #endif 1507 1508 if (intstat & CMDCMPLT) { 1509 ahc_outb(ahc, CLRINT, CLRCMDINT); 1510 ahc_run_qoutfifo(ahc); 1511 } 1512 if (intstat & BRKADRINT) { 1513 /* 1514 * We upset the sequencer :-( 1515 * Lookup the error message 1516 */ 1517 int i, error, num_errors; 1518 1519 error = ahc_inb(ahc, ERROR); 1520 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1521 for (i = 0; error != 1 && i < num_errors; i++) 1522 error >>= 1; 1523 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1524 ahc_name(ahc), hard_error[i].errmesg, 1525 ahc_inb(ahc, SEQADDR0) | 1526 (ahc_inb(ahc, SEQADDR1) << 8)); 1527 1528 /* Tell everyone that this HBA is no longer available */ 1529 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1530 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1531 XS_DRIVER_STUFFUP); 1532 } 1533 if (intstat & SEQINT) 1534 ahc_handle_seqint(ahc, intstat); 1535 1536 if (intstat & SCSIINT) 1537 ahc_handle_scsiint(ahc, intstat); 1538 1539 return 1; 1540 } 1541 1542 static struct tmode_tstate * 1543 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1544 { 1545 struct tmode_tstate *master_tstate; 1546 struct tmode_tstate *tstate; 1547 int i, s; 1548 1549 master_tstate = ahc->enabled_targets[ahc->our_id]; 1550 if (channel == 'B') { 1551 scsi_id += 8; 1552 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1553 } 1554 if (ahc->enabled_targets[scsi_id] != NULL 1555 && ahc->enabled_targets[scsi_id] != master_tstate) 1556 panic("%s: ahc_alloc_tstate - Target already allocated", 1557 ahc_name(ahc)); 1558 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1559 if (tstate == NULL) 1560 return (NULL); 1561 1562 /* 1563 * If we have allocated a master tstate, copy user settings from 1564 * the master tstate (taken from SRAM or the EEPROM) for this 1565 * channel, but reset our current and goal settings to async/narrow 1566 * until an initiator talks to us. 1567 */ 1568 if (master_tstate != NULL) { 1569 memcpy(tstate, master_tstate, sizeof(*tstate)); 1570 tstate->ultraenb = 0; 1571 for (i = 0; i < 16; i++) { 1572 memset(&tstate->transinfo[i].current, 0, 1573 sizeof(tstate->transinfo[i].current)); 1574 memset(&tstate->transinfo[i].goal, 0, 1575 sizeof(tstate->transinfo[i].goal)); 1576 } 1577 } else 1578 memset(tstate, 0, sizeof(*tstate)); 1579 s = splbio(); 1580 ahc->enabled_targets[scsi_id] = tstate; 1581 splx(s); 1582 return (tstate); 1583 } 1584 1585 #if UNUSED 1586 static void 1587 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1588 { 1589 struct tmode_tstate *tstate; 1590 1591 /* Don't clean up the entry for our initiator role */ 1592 if ((ahc->flags & AHC_INITIATORMODE) != 0 1593 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1594 || (channel == 'A' && scsi_id == ahc->our_id)) 1595 && force == FALSE) 1596 return; 1597 1598 if (channel == 'B') 1599 scsi_id += 8; 1600 tstate = ahc->enabled_targets[scsi_id]; 1601 if (tstate != NULL) 1602 free(tstate, M_DEVBUF); 1603 ahc->enabled_targets[scsi_id] = NULL; 1604 } 1605 #endif 1606 1607 static void 1608 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1609 { 1610 struct scb *scb; 1611 struct ahc_devinfo devinfo; 1612 1613 ahc_fetch_devinfo(ahc, &devinfo); 1614 1615 /* 1616 * Clear the upper byte that holds SEQINT status 1617 * codes and clear the SEQINT bit. We will unpause 1618 * the sequencer, if appropriate, after servicing 1619 * the request. 1620 */ 1621 ahc_outb(ahc, CLRINT, CLRSEQINT); 1622 switch (intstat & SEQINT_MASK) { 1623 case NO_MATCH: 1624 { 1625 /* Ensure we don't leave the selection hardware on */ 1626 ahc_outb(ahc, SCSISEQ, 1627 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1628 1629 printf("%s:%c:%d: no active SCB for reconnecting " 1630 "target - issuing BUS DEVICE RESET\n", 1631 ahc_name(ahc), devinfo.channel, devinfo.target); 1632 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1633 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1634 ahc_inb(ahc, SEQ_FLAGS)); 1635 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1636 ahc->msgout_len = 1; 1637 ahc->msgout_index = 0; 1638 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1639 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1640 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1641 break; 1642 } 1643 case UPDATE_TMSG_REQ: 1644 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1645 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1646 (ahc->targ_msg_req >> 8) & 0xFF); 1647 ahc_outb(ahc, HS_MAILBOX, 0); 1648 break; 1649 case SEND_REJECT: 1650 { 1651 u_int rejbyte = ahc_inb(ahc, ACCUM); 1652 printf("%s:%c:%d: Warning - unknown message received from " 1653 "target (0x%x). Rejecting\n", 1654 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1655 break; 1656 } 1657 case NO_IDENT: 1658 { 1659 /* 1660 * The reconnecting target either did not send an identify 1661 * message, or did, but we didn't find and SCB to match and 1662 * before it could respond to our ATN/abort, it hit a dataphase. 1663 * The only safe thing to do is to blow it away with a bus 1664 * reset. 1665 */ 1666 int found; 1667 1668 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1669 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1670 ahc_name(ahc), devinfo.channel, devinfo.target, 1671 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1672 found = ahc_reset_channel(ahc, devinfo.channel, 1673 /*initiate reset*/TRUE); 1674 printf("%s: Issued Channel %c Bus Reset. " 1675 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1676 found); 1677 return; 1678 } 1679 case BAD_PHASE: 1680 { 1681 u_int lastphase; 1682 1683 lastphase = ahc_inb(ahc, LASTPHASE); 1684 if (lastphase == P_BUSFREE) { 1685 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1686 ahc_name(ahc), devinfo.channel, devinfo.target, 1687 ahc_inb(ahc, SCSISIGI)); 1688 restart_sequencer(ahc); 1689 return; 1690 } else { 1691 printf("%s:%c:%d: unknown scsi bus phase %x. " 1692 "Attempting to continue\n", 1693 ahc_name(ahc), devinfo.channel, devinfo.target, 1694 ahc_inb(ahc, SCSISIGI)); 1695 } 1696 break; 1697 } 1698 case BAD_STATUS: 1699 { 1700 u_int scb_index; 1701 struct hardware_scb *hscb; 1702 struct scsipi_xfer *xs; 1703 /* 1704 * The sequencer will notify us when a command 1705 * has an error that would be of interest to 1706 * the kernel. This allows us to leave the sequencer 1707 * running in the common case of command completes 1708 * without error. The sequencer will already have 1709 * dma'd the SCB back up to us, so we can reference 1710 * the in kernel copy directly. 1711 */ 1712 scb_index = ahc_inb(ahc, SCB_TAG); 1713 scb = &ahc->scb_data->scbarray[scb_index]; 1714 1715 /* ahc_print_scb(scb); */ 1716 1717 /* 1718 * Set the default return value to 0 (don't 1719 * send sense). The sense code will change 1720 * this if needed. 1721 */ 1722 ahc_outb(ahc, RETURN_1, 0); 1723 if (!(scb_index < ahc->scb_data->numscbs 1724 && (scb->flags & SCB_ACTIVE) != 0)) { 1725 printf("%s:%c:%d: ahc_intr - referenced scb " 1726 "not valid during seqint 0x%x scb(%d)\n", 1727 ahc_name(ahc), devinfo.channel, 1728 devinfo.target, intstat, scb_index); 1729 goto unpause; 1730 } 1731 1732 hscb = scb->hscb; 1733 xs = scb->xs; 1734 1735 /* Don't want to clobber the original sense code */ 1736 if ((scb->flags & SCB_SENSE) != 0) { 1737 /* 1738 * Clear the SCB_SENSE Flag and have 1739 * the sequencer do a normal command 1740 * complete. 1741 */ 1742 scb->flags &= ~SCB_SENSE; 1743 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1744 break; 1745 } 1746 /* Freeze the queue unit the client sees the error. */ 1747 ahc_freeze_devq(ahc, xs->xs_periph); 1748 ahc_freeze_ccb(scb); 1749 xs->status = hscb->status; 1750 switch (hscb->status) { 1751 case SCSI_STATUS_OK: 1752 printf("%s: Interrupted for status of 0???\n", 1753 ahc_name(ahc)); 1754 break; 1755 case SCSI_STATUS_CMD_TERMINATED: 1756 case SCSI_STATUS_CHECK_COND: 1757 #if defined(AHC_DEBUG) 1758 if (ahc_debug & AHC_SHOWSENSE) { 1759 scsipi_printaddr(xs->xs_periph); 1760 printf("Check Status, resid %d datalen %d\n", 1761 xs->resid, xs->datalen); 1762 } 1763 #endif 1764 1765 if (xs->error == XS_NOERROR && 1766 !(scb->flags & SCB_SENSE)) { 1767 struct ahc_dma_seg *sg; 1768 struct scsipi_sense *sc; 1769 struct ahc_initiator_tinfo *tinfo; 1770 struct tmode_tstate *tstate; 1771 1772 sg = scb->sg_list; 1773 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1774 /* 1775 * Save off the residual if there is one. 1776 */ 1777 if (hscb->residual_SG_count != 0) 1778 ahc_calc_residual(scb); 1779 else 1780 xs->resid = 0; 1781 1782 #ifdef AHC_DEBUG 1783 if (ahc_debug & AHC_SHOWSENSE) { 1784 scsipi_printaddr(xs->xs_periph); 1785 printf("Sending Sense\n"); 1786 } 1787 #endif 1788 sg->addr = ahc->scb_data->sense_busaddr + 1789 (hscb->tag*sizeof(struct scsipi_sense_data)); 1790 sg->len = sizeof (struct scsipi_sense_data); 1791 1792 sc->opcode = REQUEST_SENSE; 1793 sc->byte2 = SCB_LUN(scb) << 5; 1794 sc->unused[0] = 0; 1795 sc->unused[1] = 0; 1796 sc->length = sg->len; 1797 sc->control = 0; 1798 1799 /* 1800 * Would be nice to preserve DISCENB here, 1801 * but due to the way we page SCBs, we can't. 1802 */ 1803 hscb->control = 0; 1804 1805 /* 1806 * This request sense could be because the 1807 * the device lost power or in some other 1808 * way has lost our transfer negotiations. 1809 * Renegotiate if appropriate. Unit attention 1810 * errors will be reported before any data 1811 * phases occur. 1812 */ 1813 ahc_calc_residual(scb); 1814 #if defined(AHC_DEBUG) 1815 if (ahc_debug & AHC_SHOWSENSE) { 1816 scsipi_printaddr(xs->xs_periph); 1817 printf("Sense: datalen %d resid %d" 1818 "chan %d id %d targ %d\n", 1819 xs->datalen, xs->resid, 1820 devinfo.channel, devinfo.our_scsiid, 1821 devinfo.target); 1822 } 1823 #endif 1824 if (xs->datalen > 0 && 1825 xs->resid == xs->datalen) { 1826 tinfo = ahc_fetch_transinfo(ahc, 1827 devinfo.channel, 1828 devinfo.our_scsiid, 1829 devinfo.target, 1830 &tstate); 1831 ahc_update_target_msg_request(ahc, 1832 &devinfo, 1833 tinfo, 1834 /*force*/TRUE, 1835 /*paused*/TRUE); 1836 } 1837 hscb->status = 0; 1838 hscb->SG_count = 1; 1839 hscb->SG_pointer = scb->sg_list_phys; 1840 hscb->data = sg->addr; 1841 hscb->datalen = sg->len; 1842 hscb->cmdpointer = hscb->cmdstore_busaddr; 1843 hscb->cmdlen = sizeof(*sc); 1844 scb->sg_count = hscb->SG_count; 1845 ahc_swap_hscb(hscb); 1846 ahc_swap_sg(scb->sg_list); 1847 scb->flags |= SCB_SENSE; 1848 /* 1849 * Ensure the target is busy since this 1850 * will be an untagged request. 1851 */ 1852 ahc_busy_tcl(ahc, scb); 1853 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1854 1855 /* 1856 * Ensure we have enough time to actually 1857 * retrieve the sense. 1858 */ 1859 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1860 callout_reset(&scb->xs->xs_callout, 1861 5 * hz, ahc_timeout, scb); 1862 } 1863 } 1864 break; 1865 case SCSI_STATUS_QUEUE_FULL: 1866 case SCSI_STATUS_BUSY: 1867 xs->error = XS_BUSY; 1868 break; 1869 } 1870 break; 1871 } 1872 case TRACE_POINT: 1873 { 1874 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1875 ahc_inb(ahc, DFCNTRL)); 1876 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1877 ahc_inb(ahc, DFSTATUS)); 1878 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1879 ahc_inb(ahc, SSTAT0), 1880 ahc_inb(ahc, SCB_DATACNT)); 1881 break; 1882 } 1883 case HOST_MSG_LOOP: 1884 { 1885 /* 1886 * The sequencer has encountered a message phase 1887 * that requires host assistance for completion. 1888 * While handling the message phase(s), we will be 1889 * notified by the sequencer after each byte is 1890 * transferred so we can track bus phases. 1891 * 1892 * If this is the first time we've seen a HOST_MSG_LOOP, 1893 * initialize the state of the host message loop. 1894 */ 1895 if (ahc->msg_type == MSG_TYPE_NONE) { 1896 u_int bus_phase; 1897 1898 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1899 if (bus_phase != P_MESGIN 1900 && bus_phase != P_MESGOUT) { 1901 printf("ahc_intr: HOST_MSG_LOOP bad " 1902 "phase 0x%x\n", 1903 bus_phase); 1904 /* 1905 * Probably transitioned to bus free before 1906 * we got here. Just punt the message. 1907 */ 1908 ahc_clear_intstat(ahc); 1909 restart_sequencer(ahc); 1910 } 1911 1912 if (devinfo.role == ROLE_INITIATOR) { 1913 struct scb *scb; 1914 u_int scb_index; 1915 1916 scb_index = ahc_inb(ahc, SCB_TAG); 1917 scb = &ahc->scb_data->scbarray[scb_index]; 1918 1919 if (bus_phase == P_MESGOUT) 1920 ahc_setup_initiator_msgout(ahc, 1921 &devinfo, 1922 scb); 1923 else { 1924 ahc->msg_type = 1925 MSG_TYPE_INITIATOR_MSGIN; 1926 ahc->msgin_index = 0; 1927 } 1928 } else { 1929 if (bus_phase == P_MESGOUT) { 1930 ahc->msg_type = 1931 MSG_TYPE_TARGET_MSGOUT; 1932 ahc->msgin_index = 0; 1933 } else 1934 /* XXX Ever executed??? */ 1935 ahc_setup_target_msgin(ahc, &devinfo); 1936 } 1937 } 1938 1939 /* Pass a NULL path so that handlers generate their own */ 1940 ahc_handle_message_phase(ahc, /*path*/NULL); 1941 break; 1942 } 1943 case PERR_DETECTED: 1944 { 1945 /* 1946 * If we've cleared the parity error interrupt 1947 * but the sequencer still believes that SCSIPERR 1948 * is true, it must be that the parity error is 1949 * for the currently presented byte on the bus, 1950 * and we are not in a phase (data-in) where we will 1951 * eventually ack this byte. Ack the byte and 1952 * throw it away in the hope that the target will 1953 * take us to message out to deliver the appropriate 1954 * error message. 1955 */ 1956 if ((intstat & SCSIINT) == 0 1957 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1958 u_int curphase; 1959 1960 /* 1961 * The hardware will only let you ack bytes 1962 * if the expected phase in SCSISIGO matches 1963 * the current phase. Make sure this is 1964 * currently the case. 1965 */ 1966 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1967 ahc_outb(ahc, LASTPHASE, curphase); 1968 ahc_outb(ahc, SCSISIGO, curphase); 1969 ahc_inb(ahc, SCSIDATL); 1970 } 1971 break; 1972 } 1973 case DATA_OVERRUN: 1974 { 1975 /* 1976 * When the sequencer detects an overrun, it 1977 * places the controller in "BITBUCKET" mode 1978 * and allows the target to complete its transfer. 1979 * Unfortunately, none of the counters get updated 1980 * when the controller is in this mode, so we have 1981 * no way of knowing how large the overrun was. 1982 */ 1983 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1984 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1985 int i; 1986 1987 scb = &ahc->scb_data->scbarray[scbindex]; 1988 for (i = 0; i < num_phases; i++) { 1989 if (lastphase == phase_table[i].phase) 1990 break; 1991 } 1992 scsipi_printaddr(scb->xs->xs_periph); 1993 printf("data overrun detected %s." 1994 " Tag == 0x%x.\n", 1995 phase_table[i].phasemsg, 1996 scb->hscb->tag); 1997 scsipi_printaddr(scb->xs->xs_periph); 1998 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1999 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2000 scb->xs->datalen, scb->sg_count); 2001 if (scb->sg_count > 0) { 2002 for (i = 0; i < scb->sg_count; i++) { 2003 printf("sg[%d] - Addr 0x%x : Length %d\n", 2004 i, 2005 le32toh(scb->sg_list[i].addr), 2006 le32toh(scb->sg_list[i].len)); 2007 } 2008 } 2009 /* 2010 * Set this and it will take affect when the 2011 * target does a command complete. 2012 */ 2013 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2014 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2015 ahc_freeze_ccb(scb); 2016 break; 2017 } 2018 case TRACEPOINT: 2019 { 2020 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2021 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2022 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2023 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2024 printf("TRACEPOINT: CCHADDR = %x\n", 2025 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2026 | (ahc_inb(ahc, CCHADDR+2) << 16) 2027 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2028 #if 0 2029 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2030 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2031 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2032 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2033 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2034 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2035 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2036 ahc_inb(ahc, CCHADDR) 2037 | (ahc_inb(ahc, CCHADDR+1) << 8) 2038 | (ahc_inb(ahc, CCHADDR+2) << 16) 2039 | (ahc_inb(ahc, CCHADDR+3) << 24), 2040 ahc_inb(ahc, CCHCNT) 2041 | (ahc_inb(ahc, CCHCNT+1) << 8) 2042 | (ahc_inb(ahc, CCHCNT+2) << 16), 2043 ahc_inb(ahc, SCBPTR)); 2044 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2045 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2046 #if DDB > 0 2047 cpu_Debugger(); 2048 #endif 2049 #endif 2050 break; 2051 } 2052 #if NOT_YET 2053 /* XXX Fill these in later */ 2054 case MESG_BUFFER_BUSY: 2055 break; 2056 case MSGIN_PHASEMIS: 2057 break; 2058 #endif 2059 default: 2060 printf("ahc_intr: seqint, " 2061 "intstat == 0x%x, scsisigi = 0x%x\n", 2062 intstat, ahc_inb(ahc, SCSISIGI)); 2063 break; 2064 } 2065 2066 unpause: 2067 /* 2068 * The sequencer is paused immediately on 2069 * a SEQINT, so we should restart it when 2070 * we're done. 2071 */ 2072 unpause_sequencer(ahc); 2073 } 2074 2075 static void 2076 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2077 { 2078 u_int scb_index; 2079 u_int status; 2080 struct scb *scb; 2081 char cur_channel; 2082 char intr_channel; 2083 2084 if ((ahc->features & AHC_TWIN) != 0 2085 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2086 cur_channel = 'B'; 2087 else 2088 cur_channel = 'A'; 2089 intr_channel = cur_channel; 2090 2091 status = ahc_inb(ahc, SSTAT1); 2092 if (status == 0) { 2093 if ((ahc->features & AHC_TWIN) != 0) { 2094 /* Try the other channel */ 2095 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2096 status = ahc_inb(ahc, SSTAT1); 2097 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2098 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2099 } 2100 if (status == 0) { 2101 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2102 return; 2103 } 2104 } 2105 2106 scb_index = ahc_inb(ahc, SCB_TAG); 2107 if (scb_index < ahc->scb_data->numscbs) { 2108 scb = &ahc->scb_data->scbarray[scb_index]; 2109 if ((scb->flags & SCB_ACTIVE) == 0 2110 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2111 scb = NULL; 2112 } else 2113 scb = NULL; 2114 2115 if ((status & SCSIRSTI) != 0) { 2116 printf("%s: Someone reset channel %c\n", 2117 ahc_name(ahc), intr_channel); 2118 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2119 } else if ((status & SCSIPERR) != 0) { 2120 /* 2121 * Determine the bus phase and queue an appropriate message. 2122 * SCSIPERR is latched true as soon as a parity error 2123 * occurs. If the sequencer acked the transfer that 2124 * caused the parity error and the currently presented 2125 * transfer on the bus has correct parity, SCSIPERR will 2126 * be cleared by CLRSCSIPERR. Use this to determine if 2127 * we should look at the last phase the sequencer recorded, 2128 * or the current phase presented on the bus. 2129 */ 2130 u_int mesg_out; 2131 u_int curphase; 2132 u_int errorphase; 2133 u_int lastphase; 2134 int i; 2135 2136 lastphase = ahc_inb(ahc, LASTPHASE); 2137 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2138 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2139 /* 2140 * For all phases save DATA, the sequencer won't 2141 * automatically ack a byte that has a parity error 2142 * in it. So the only way that the current phase 2143 * could be 'data-in' is if the parity error is for 2144 * an already acked byte in the data phase. During 2145 * synchronous data-in transfers, we may actually 2146 * ack bytes before latching the current phase in 2147 * LASTPHASE, leading to the discrepancy between 2148 * curphase and lastphase. 2149 */ 2150 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2151 || curphase == P_DATAIN) 2152 errorphase = curphase; 2153 else 2154 errorphase = lastphase; 2155 2156 for (i = 0; i < num_phases; i++) { 2157 if (errorphase == phase_table[i].phase) 2158 break; 2159 } 2160 mesg_out = phase_table[i].mesg_out; 2161 if (scb != NULL) 2162 scsipi_printaddr(scb->xs->xs_periph); 2163 else 2164 printf("%s:%c:%d: ", ahc_name(ahc), 2165 intr_channel, 2166 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2167 2168 printf("parity error detected %s. " 2169 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2170 phase_table[i].phasemsg, 2171 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2172 ahc_inb(ahc, SCSIRATE)); 2173 2174 /* 2175 * We've set the hardware to assert ATN if we 2176 * get a parity error on "in" phases, so all we 2177 * need to do is stuff the message buffer with 2178 * the appropriate message. "In" phases have set 2179 * mesg_out to something other than MSG_NOP. 2180 */ 2181 if (mesg_out != MSG_NOOP) { 2182 if (ahc->msg_type != MSG_TYPE_NONE) 2183 ahc->send_msg_perror = TRUE; 2184 else 2185 ahc_outb(ahc, MSG_OUT, mesg_out); 2186 } 2187 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2188 unpause_sequencer(ahc); 2189 } else if ((status & BUSFREE) != 0 2190 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2191 /* 2192 * First look at what phase we were last in. 2193 * If its message out, chances are pretty good 2194 * that the busfree was in response to one of 2195 * our abort requests. 2196 */ 2197 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2198 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2199 u_int target = TCL_TARGET(saved_tcl); 2200 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2201 char channel = TCL_CHANNEL(ahc, saved_tcl); 2202 int printerror = 1; 2203 2204 ahc_outb(ahc, SCSISEQ, 2205 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2206 if (lastphase == P_MESGOUT) { 2207 u_int message; 2208 u_int tag; 2209 2210 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2211 tag = SCB_LIST_NULL; 2212 switch (message) { 2213 case MSG_ABORT_TAG: 2214 tag = scb->hscb->tag; 2215 /* FALLTRHOUGH */ 2216 case MSG_ABORT: 2217 scsipi_printaddr(scb->xs->xs_periph); 2218 printf("SCB %x - Abort %s Completed.\n", 2219 scb->hscb->tag, tag == SCB_LIST_NULL ? 2220 "" : "Tag"); 2221 ahc_abort_scbs(ahc, target, channel, 2222 TCL_LUN(saved_tcl), tag, 2223 ROLE_INITIATOR, 2224 XS_DRIVER_STUFFUP); 2225 printerror = 0; 2226 break; 2227 case MSG_BUS_DEV_RESET: 2228 { 2229 struct ahc_devinfo devinfo; 2230 2231 if (scb != NULL && 2232 (scb->xs->xs_control & XS_CTL_RESET) 2233 && ahc_match_scb(scb, target, channel, 2234 TCL_LUN(saved_tcl), 2235 SCB_LIST_NULL, 2236 ROLE_INITIATOR)) { 2237 ahcsetccbstatus(scb->xs, XS_NOERROR); 2238 } 2239 ahc_compile_devinfo(&devinfo, 2240 initiator_role_id, 2241 target, 2242 TCL_LUN(saved_tcl), 2243 channel, 2244 ROLE_INITIATOR); 2245 ahc_handle_devreset(ahc, &devinfo, 2246 XS_RESET, 2247 "Bus Device Reset", 2248 /*verbose_level*/0); 2249 printerror = 0; 2250 break; 2251 } 2252 default: 2253 break; 2254 } 2255 } 2256 if (printerror != 0) { 2257 int i; 2258 2259 if (scb != NULL) { 2260 u_int tag; 2261 2262 if ((scb->hscb->control & TAG_ENB) != 0) 2263 tag = scb->hscb->tag; 2264 else 2265 tag = SCB_LIST_NULL; 2266 ahc_abort_scbs(ahc, target, channel, 2267 SCB_LUN(scb), tag, 2268 ROLE_INITIATOR, 2269 XS_DRIVER_STUFFUP); 2270 scsipi_printaddr(scb->xs->xs_periph); 2271 } else { 2272 /* 2273 * We had not fully identified this connection, 2274 * so we cannot abort anything. 2275 */ 2276 printf("%s: ", ahc_name(ahc)); 2277 } 2278 for (i = 0; i < num_phases; i++) { 2279 if (lastphase == phase_table[i].phase) 2280 break; 2281 } 2282 printf("Unexpected busfree %s\n" 2283 "SEQADDR == 0x%x\n", 2284 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2285 | (ahc_inb(ahc, SEQADDR1) << 8)); 2286 } 2287 ahc_clear_msg_state(ahc); 2288 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2289 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2290 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2291 restart_sequencer(ahc); 2292 } else if ((status & SELTO) != 0) { 2293 u_int scbptr; 2294 2295 scbptr = ahc_inb(ahc, WAITING_SCBH); 2296 ahc_outb(ahc, SCBPTR, scbptr); 2297 scb_index = ahc_inb(ahc, SCB_TAG); 2298 2299 if (scb_index < ahc->scb_data->numscbs) { 2300 scb = &ahc->scb_data->scbarray[scb_index]; 2301 if ((scb->flags & SCB_ACTIVE) == 0) 2302 scb = NULL; 2303 } else 2304 scb = NULL; 2305 2306 if (scb == NULL) { 2307 printf("%s: ahc_intr - referenced scb not " 2308 "valid during SELTO scb(%d, %d)\n", 2309 ahc_name(ahc), scbptr, scb_index); 2310 } else { 2311 u_int tag; 2312 2313 tag = SCB_LIST_NULL; 2314 if ((scb->hscb->control & TAG_ENB) != 0) 2315 tag = scb->hscb->tag; 2316 2317 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2318 SCB_LUN(scb), tag, 2319 ROLE_INITIATOR, XS_SELTIMEOUT); 2320 } 2321 /* Stop the selection */ 2322 ahc_outb(ahc, SCSISEQ, 0); 2323 2324 /* No more pending messages */ 2325 ahc_clear_msg_state(ahc); 2326 2327 /* 2328 * Although the driver does not care about the 2329 * 'Selection in Progress' status bit, the busy 2330 * LED does. SELINGO is only cleared by a sucessful 2331 * selection, so we must manually clear it to ensure 2332 * the LED turns off just incase no future successful 2333 * selections occur (e.g. no devices on the bus). 2334 */ 2335 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2336 2337 /* Clear interrupt state */ 2338 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2339 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2340 restart_sequencer(ahc); 2341 } else { 2342 scsipi_printaddr(scb->xs->xs_periph); 2343 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2344 ahc_outb(ahc, CLRSINT1, status); 2345 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2346 unpause_sequencer(ahc); 2347 } 2348 } 2349 2350 static void 2351 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2352 { 2353 /* 2354 * We need to initiate transfer negotiations. 2355 * If our current and goal settings are identical, 2356 * we want to renegotiate due to a check condition. 2357 */ 2358 struct ahc_initiator_tinfo *tinfo; 2359 struct tmode_tstate *tstate; 2360 int dowide; 2361 int dosync; 2362 2363 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2364 devinfo->target, &tstate); 2365 dowide = tinfo->current.width != tinfo->goal.width; 2366 dosync = tinfo->current.period != tinfo->goal.period; 2367 2368 if (!dowide && !dosync) { 2369 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2370 dosync = tinfo->goal.period != 0; 2371 } 2372 2373 if (dowide) { 2374 ahc_construct_wdtr(ahc, tinfo->goal.width); 2375 } else if (dosync) { 2376 const struct ahc_syncrate *rate; 2377 u_int period; 2378 u_int offset; 2379 2380 period = tinfo->goal.period; 2381 rate = ahc_devlimited_syncrate(ahc, &period); 2382 offset = tinfo->goal.offset; 2383 ahc_validate_offset(ahc, rate, &offset, 2384 tinfo->current.width); 2385 ahc_construct_sdtr(ahc, period, offset); 2386 } else { 2387 panic("ahc_intr: AWAITING_MSG for negotiation, " 2388 "but no negotiation needed\n"); 2389 } 2390 } 2391 2392 static void 2393 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2394 struct scb *scb) 2395 { 2396 /* 2397 * To facilitate adding multiple messages together, 2398 * each routine should increment the index and len 2399 * variables instead of setting them explicitly. 2400 */ 2401 ahc->msgout_index = 0; 2402 ahc->msgout_len = 0; 2403 2404 if ((scb->flags & SCB_DEVICE_RESET) == 0 2405 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2406 u_int identify_msg; 2407 2408 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2409 if ((scb->hscb->control & DISCENB) != 0) 2410 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2411 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2412 ahc->msgout_len++; 2413 2414 if ((scb->hscb->control & TAG_ENB) != 0) { 2415 ahc->msgout_buf[ahc->msgout_index++] = 2416 scb->xs->xs_tag_type; 2417 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2418 ahc->msgout_len += 2; 2419 } 2420 } 2421 2422 if (scb->flags & SCB_DEVICE_RESET) { 2423 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2424 ahc->msgout_len++; 2425 scsipi_printaddr(scb->xs->xs_periph); 2426 printf("Bus Device Reset Message Sent\n"); 2427 } else if (scb->flags & SCB_ABORT) { 2428 if ((scb->hscb->control & TAG_ENB) != 0) 2429 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2430 else 2431 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2432 ahc->msgout_len++; 2433 scsipi_printaddr(scb->xs->xs_periph); 2434 printf("Abort Message Sent\n"); 2435 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2436 ahc_build_transfer_msg(ahc, devinfo); 2437 } else { 2438 printf("ahc_intr: AWAITING_MSG for an SCB that " 2439 "does not have a waiting message"); 2440 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2441 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2442 ahc_inb(ahc, MSG_OUT), scb->flags); 2443 } 2444 2445 /* 2446 * Clear the MK_MESSAGE flag from the SCB so we aren't 2447 * asked to send this message again. 2448 */ 2449 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2450 ahc->msgout_index = 0; 2451 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2452 } 2453 2454 static void 2455 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2456 { 2457 /* 2458 * To facilitate adding multiple messages together, 2459 * each routine should increment the index and len 2460 * variables instead of setting them explicitly. 2461 */ 2462 ahc->msgout_index = 0; 2463 ahc->msgout_len = 0; 2464 2465 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2466 ahc_build_transfer_msg(ahc, devinfo); 2467 else 2468 panic("ahc_intr: AWAITING target message with no message"); 2469 2470 ahc->msgout_index = 0; 2471 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2472 } 2473 2474 static int 2475 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2476 { 2477 /* 2478 * What we care about here is if we had an 2479 * outstanding SDTR or WDTR message for this 2480 * target. If we did, this is a signal that 2481 * the target is refusing negotiation. 2482 */ 2483 struct scb *scb; 2484 u_int scb_index; 2485 u_int last_msg; 2486 int response = 0; 2487 2488 scb_index = ahc_inb(ahc, SCB_TAG); 2489 scb = &ahc->scb_data->scbarray[scb_index]; 2490 2491 /* Might be necessary */ 2492 last_msg = ahc_inb(ahc, LAST_MSG); 2493 2494 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2495 struct ahc_initiator_tinfo *tinfo; 2496 struct tmode_tstate *tstate; 2497 2498 #ifdef AHC_DEBUG_NEG 2499 /* note 8bit xfers */ 2500 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2501 "8bit transfers\n", ahc_name(ahc), 2502 devinfo->channel, devinfo->target); 2503 #endif 2504 ahc_set_width(ahc, devinfo, 2505 MSG_EXT_WDTR_BUS_8_BIT, 2506 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2507 /*paused*/TRUE, /*done*/TRUE); 2508 /* 2509 * No need to clear the sync rate. If the target 2510 * did not accept the command, our syncrate is 2511 * unaffected. If the target started the negotiation, 2512 * but rejected our response, we already cleared the 2513 * sync rate before sending our WDTR. 2514 */ 2515 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2516 devinfo->our_scsiid, 2517 devinfo->target, &tstate); 2518 if (tinfo->goal.period) { 2519 u_int period; 2520 2521 /* Start the sync negotiation */ 2522 period = tinfo->goal.period; 2523 ahc_devlimited_syncrate(ahc, &period); 2524 ahc->msgout_index = 0; 2525 ahc->msgout_len = 0; 2526 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2527 ahc->msgout_index = 0; 2528 response = 1; 2529 } else 2530 ahc_update_xfer_mode(ahc, devinfo); 2531 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2532 /* note asynch xfers and clear flag */ 2533 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2534 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2535 /*paused*/TRUE, /*done*/TRUE); 2536 #ifdef AHC_DEBUG_NEG 2537 printf("%s:%c:%d: refuses synchronous negotiation. " 2538 "Using asynchronous transfers\n", 2539 ahc_name(ahc), 2540 devinfo->channel, devinfo->target); 2541 #endif 2542 ahc_update_xfer_mode(ahc, devinfo); 2543 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2544 printf("%s:%c:%d: refuses tagged commands. Performing " 2545 "non-tagged I/O\n", ahc_name(ahc), 2546 devinfo->channel, devinfo->target); 2547 2548 ahc_set_tags(ahc, devinfo, FALSE); 2549 ahc_update_xfer_mode(ahc, devinfo); 2550 2551 /* 2552 * Resend the identify for this CCB as the target 2553 * may believe that the selection is invalid otherwise. 2554 */ 2555 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2556 & ~MSG_SIMPLE_Q_TAG); 2557 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2558 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2559 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2560 2561 /* 2562 * Requeue all tagged commands for this target 2563 * currently in our posession so they can be 2564 * converted to untagged commands. 2565 */ 2566 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2567 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2568 ROLE_INITIATOR, SCB_REQUEUE, 2569 SEARCH_COMPLETE); 2570 } else { 2571 /* 2572 * Otherwise, we ignore it. 2573 */ 2574 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2575 ahc_name(ahc), devinfo->channel, devinfo->target, 2576 last_msg); 2577 } 2578 return (response); 2579 } 2580 2581 static void 2582 ahc_clear_msg_state(struct ahc_softc *ahc) 2583 { 2584 ahc->msgout_len = 0; 2585 ahc->msgin_index = 0; 2586 ahc->msg_type = MSG_TYPE_NONE; 2587 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2588 } 2589 2590 static void 2591 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2592 { 2593 struct ahc_devinfo devinfo; 2594 u_int bus_phase; 2595 int end_session; 2596 2597 ahc_fetch_devinfo(ahc, &devinfo); 2598 end_session = FALSE; 2599 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2600 2601 reswitch: 2602 switch (ahc->msg_type) { 2603 case MSG_TYPE_INITIATOR_MSGOUT: 2604 { 2605 int lastbyte; 2606 int phasemis; 2607 int msgdone; 2608 2609 if (ahc->msgout_len == 0) 2610 panic("REQINIT interrupt with no active message"); 2611 2612 phasemis = bus_phase != P_MESGOUT; 2613 if (phasemis) { 2614 if (bus_phase == P_MESGIN) { 2615 /* 2616 * Change gears and see if 2617 * this messages is of interest to 2618 * us or should be passed back to 2619 * the sequencer. 2620 */ 2621 ahc_outb(ahc, CLRSINT1, CLRATNO); 2622 ahc->send_msg_perror = FALSE; 2623 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2624 ahc->msgin_index = 0; 2625 goto reswitch; 2626 } 2627 end_session = TRUE; 2628 break; 2629 } 2630 2631 if (ahc->send_msg_perror) { 2632 ahc_outb(ahc, CLRSINT1, CLRATNO); 2633 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2634 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2635 break; 2636 } 2637 2638 msgdone = ahc->msgout_index == ahc->msgout_len; 2639 if (msgdone) { 2640 /* 2641 * The target has requested a retry. 2642 * Re-assert ATN, reset our message index to 2643 * 0, and try again. 2644 */ 2645 ahc->msgout_index = 0; 2646 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2647 } 2648 2649 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2650 if (lastbyte) { 2651 /* Last byte is signified by dropping ATN */ 2652 ahc_outb(ahc, CLRSINT1, CLRATNO); 2653 } 2654 2655 /* 2656 * Clear our interrupt status and present 2657 * the next byte on the bus. 2658 */ 2659 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2660 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2661 break; 2662 } 2663 case MSG_TYPE_INITIATOR_MSGIN: 2664 { 2665 int phasemis; 2666 int message_done; 2667 2668 phasemis = bus_phase != P_MESGIN; 2669 2670 if (phasemis) { 2671 ahc->msgin_index = 0; 2672 if (bus_phase == P_MESGOUT 2673 && (ahc->send_msg_perror == TRUE 2674 || (ahc->msgout_len != 0 2675 && ahc->msgout_index == 0))) { 2676 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2677 goto reswitch; 2678 } 2679 end_session = TRUE; 2680 break; 2681 } 2682 2683 /* Pull the byte in without acking it */ 2684 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2685 2686 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2687 2688 if (message_done) { 2689 /* 2690 * Clear our incoming message buffer in case there 2691 * is another message following this one. 2692 */ 2693 ahc->msgin_index = 0; 2694 2695 /* 2696 * If this message illicited a response, 2697 * assert ATN so the target takes us to the 2698 * message out phase. 2699 */ 2700 if (ahc->msgout_len != 0) 2701 ahc_outb(ahc, SCSISIGO, 2702 ahc_inb(ahc, SCSISIGO) | ATNO); 2703 } else 2704 ahc->msgin_index++; 2705 2706 /* Ack the byte */ 2707 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2708 ahc_inb(ahc, SCSIDATL); 2709 break; 2710 } 2711 case MSG_TYPE_TARGET_MSGIN: 2712 { 2713 int msgdone; 2714 int msgout_request; 2715 2716 if (ahc->msgout_len == 0) 2717 panic("Target MSGIN with no active message"); 2718 2719 /* 2720 * If we interrupted a mesgout session, the initiator 2721 * will not know this until our first REQ. So, we 2722 * only honor mesgout requests after we've sent our 2723 * first byte. 2724 */ 2725 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2726 && ahc->msgout_index > 0) 2727 msgout_request = TRUE; 2728 else 2729 msgout_request = FALSE; 2730 2731 if (msgout_request) { 2732 2733 /* 2734 * Change gears and see if 2735 * this messages is of interest to 2736 * us or should be passed back to 2737 * the sequencer. 2738 */ 2739 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2740 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2741 ahc->msgin_index = 0; 2742 /* Dummy read to REQ for first byte */ 2743 ahc_inb(ahc, SCSIDATL); 2744 ahc_outb(ahc, SXFRCTL0, 2745 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2746 break; 2747 } 2748 2749 msgdone = ahc->msgout_index == ahc->msgout_len; 2750 if (msgdone) { 2751 ahc_outb(ahc, SXFRCTL0, 2752 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2753 end_session = TRUE; 2754 break; 2755 } 2756 2757 /* 2758 * Present the next byte on the bus. 2759 */ 2760 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2761 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2762 break; 2763 } 2764 case MSG_TYPE_TARGET_MSGOUT: 2765 { 2766 int lastbyte; 2767 int msgdone; 2768 2769 /* 2770 * The initiator signals that this is 2771 * the last byte by dropping ATN. 2772 */ 2773 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2774 2775 /* 2776 * Read the latched byte, but turn off SPIOEN first 2777 * so that we don't inadvertantly cause a REQ for the 2778 * next byte. 2779 */ 2780 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2781 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2782 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2783 if (msgdone == MSGLOOP_TERMINATED) { 2784 /* 2785 * The message is *really* done in that it caused 2786 * us to go to bus free. The sequencer has already 2787 * been reset at this point, so pull the ejection 2788 * handle. 2789 */ 2790 return; 2791 } 2792 2793 ahc->msgin_index++; 2794 2795 /* 2796 * XXX Read spec about initiator dropping ATN too soon 2797 * and use msgdone to detect it. 2798 */ 2799 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2800 ahc->msgin_index = 0; 2801 2802 /* 2803 * If this message illicited a response, transition 2804 * to the Message in phase and send it. 2805 */ 2806 if (ahc->msgout_len != 0) { 2807 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2808 ahc_outb(ahc, SXFRCTL0, 2809 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2810 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2811 ahc->msgin_index = 0; 2812 break; 2813 } 2814 } 2815 2816 if (lastbyte) 2817 end_session = TRUE; 2818 else { 2819 /* Ask for the next byte. */ 2820 ahc_outb(ahc, SXFRCTL0, 2821 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2822 } 2823 2824 break; 2825 } 2826 default: 2827 panic("Unknown REQINIT message type"); 2828 } 2829 2830 if (end_session) { 2831 ahc_clear_msg_state(ahc); 2832 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2833 } else 2834 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2835 } 2836 2837 /* 2838 * See if we sent a particular extended message to the target. 2839 * If "full" is true, the target saw the full message. 2840 * If "full" is false, the target saw at least the first 2841 * byte of the message. 2842 */ 2843 static int 2844 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2845 { 2846 int found; 2847 int index; 2848 2849 found = FALSE; 2850 index = 0; 2851 2852 while (index < ahc->msgout_len) { 2853 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2854 2855 /* Found a candidate */ 2856 if (ahc->msgout_buf[index+2] == msgtype) { 2857 u_int end_index; 2858 2859 end_index = index + 1 2860 + ahc->msgout_buf[index + 1]; 2861 if (full) { 2862 if (ahc->msgout_index > end_index) 2863 found = TRUE; 2864 } else if (ahc->msgout_index > index) 2865 found = TRUE; 2866 } 2867 break; 2868 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2869 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2870 2871 /* Skip tag type and tag id or residue param*/ 2872 index += 2; 2873 } else { 2874 /* Single byte message */ 2875 index++; 2876 } 2877 } 2878 return (found); 2879 } 2880 2881 static int 2882 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2883 struct ahc_devinfo *devinfo) 2884 { 2885 struct ahc_initiator_tinfo *tinfo; 2886 struct tmode_tstate *tstate; 2887 int reject; 2888 int done; 2889 int response; 2890 u_int targ_scsirate; 2891 2892 done = MSGLOOP_IN_PROG; 2893 response = FALSE; 2894 reject = FALSE; 2895 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2896 devinfo->target, &tstate); 2897 targ_scsirate = tinfo->scsirate; 2898 2899 /* 2900 * Parse as much of the message as is available, 2901 * rejecting it if we don't support it. When 2902 * the entire message is available and has been 2903 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2904 * that we have parsed an entire message. 2905 * 2906 * In the case of extended messages, we accept the length 2907 * byte outright and perform more checking once we know the 2908 * extended message type. 2909 */ 2910 switch (ahc->msgin_buf[0]) { 2911 case MSG_MESSAGE_REJECT: 2912 response = ahc_handle_msg_reject(ahc, devinfo); 2913 /* FALLTHROUGH */ 2914 case MSG_NOOP: 2915 done = MSGLOOP_MSGCOMPLETE; 2916 break; 2917 case MSG_IGN_WIDE_RESIDUE: 2918 { 2919 /* Wait for the whole message */ 2920 if (ahc->msgin_index >= 1) { 2921 if (ahc->msgin_buf[1] != 1 2922 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2923 reject = TRUE; 2924 done = MSGLOOP_MSGCOMPLETE; 2925 } else 2926 ahc_handle_ign_wide_residue(ahc, devinfo); 2927 } 2928 break; 2929 } 2930 case MSG_EXTENDED: 2931 { 2932 /* Wait for enough of the message to begin validation */ 2933 if (ahc->msgin_index < 2) 2934 break; 2935 switch (ahc->msgin_buf[2]) { 2936 case MSG_EXT_SDTR: 2937 { 2938 const struct ahc_syncrate *syncrate; 2939 u_int period; 2940 u_int offset; 2941 u_int saved_offset; 2942 2943 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2944 reject = TRUE; 2945 break; 2946 } 2947 2948 /* 2949 * Wait until we have both args before validating 2950 * and acting on this message. 2951 * 2952 * Add one to MSG_EXT_SDTR_LEN to account for 2953 * the extended message preamble. 2954 */ 2955 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2956 break; 2957 2958 period = ahc->msgin_buf[3]; 2959 saved_offset = offset = ahc->msgin_buf[4]; 2960 syncrate = ahc_devlimited_syncrate(ahc, &period); 2961 ahc_validate_offset(ahc, syncrate, &offset, 2962 targ_scsirate & WIDEXFER); 2963 ahc_set_syncrate(ahc, devinfo, 2964 syncrate, period, offset, 2965 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2966 /*paused*/TRUE, /*done*/TRUE); 2967 ahc_update_xfer_mode(ahc, devinfo); 2968 2969 /* 2970 * See if we initiated Sync Negotiation 2971 * and didn't have to fall down to async 2972 * transfers. 2973 */ 2974 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2975 /* We started it */ 2976 if (saved_offset != offset) { 2977 /* Went too low - force async */ 2978 reject = TRUE; 2979 } 2980 } else { 2981 /* 2982 * Send our own SDTR in reply 2983 */ 2984 ahc->msgout_index = 0; 2985 ahc->msgout_len = 0; 2986 ahc_construct_sdtr(ahc, period, offset); 2987 ahc->msgout_index = 0; 2988 response = TRUE; 2989 } 2990 done = MSGLOOP_MSGCOMPLETE; 2991 break; 2992 } 2993 case MSG_EXT_WDTR: 2994 { 2995 u_int bus_width; 2996 u_int sending_reply; 2997 2998 sending_reply = FALSE; 2999 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3000 reject = TRUE; 3001 break; 3002 } 3003 3004 /* 3005 * Wait until we have our arg before validating 3006 * and acting on this message. 3007 * 3008 * Add one to MSG_EXT_WDTR_LEN to account for 3009 * the extended message preamble. 3010 */ 3011 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3012 break; 3013 3014 bus_width = ahc->msgin_buf[3]; 3015 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3016 /* 3017 * Don't send a WDTR back to the 3018 * target, since we asked first. 3019 */ 3020 switch (bus_width){ 3021 default: 3022 /* 3023 * How can we do anything greater 3024 * than 16bit transfers on a 16bit 3025 * bus? 3026 */ 3027 reject = TRUE; 3028 printf("%s: target %d requested %dBit " 3029 "transfers. Rejecting...\n", 3030 ahc_name(ahc), devinfo->target, 3031 8 * (0x01 << bus_width)); 3032 /* FALLTHROUGH */ 3033 case MSG_EXT_WDTR_BUS_8_BIT: 3034 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3035 break; 3036 case MSG_EXT_WDTR_BUS_16_BIT: 3037 break; 3038 } 3039 } else { 3040 /* 3041 * Send our own WDTR in reply 3042 */ 3043 switch (bus_width) { 3044 default: 3045 if (ahc->features & AHC_WIDE) { 3046 /* Respond Wide */ 3047 bus_width = 3048 MSG_EXT_WDTR_BUS_16_BIT; 3049 break; 3050 } 3051 /* FALLTHROUGH */ 3052 case MSG_EXT_WDTR_BUS_8_BIT: 3053 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3054 break; 3055 } 3056 ahc->msgout_index = 0; 3057 ahc->msgout_len = 0; 3058 ahc_construct_wdtr(ahc, bus_width); 3059 ahc->msgout_index = 0; 3060 response = TRUE; 3061 sending_reply = TRUE; 3062 } 3063 ahc_set_width(ahc, devinfo, bus_width, 3064 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3065 /*paused*/TRUE, /*done*/TRUE); 3066 3067 /* After a wide message, we are async */ 3068 ahc_set_syncrate(ahc, devinfo, 3069 /*syncrate*/NULL, /*period*/0, 3070 /*offset*/0, AHC_TRANS_ACTIVE, 3071 /*paused*/TRUE, /*done*/FALSE); 3072 if (sending_reply == FALSE && reject == FALSE) { 3073 3074 if (tinfo->goal.period) { 3075 const struct ahc_syncrate *rate; 3076 u_int period; 3077 u_int offset; 3078 3079 /* Start the sync negotiation */ 3080 period = tinfo->goal.period; 3081 rate = ahc_devlimited_syncrate(ahc, 3082 &period); 3083 offset = tinfo->goal.offset; 3084 ahc_validate_offset(ahc, rate, &offset, 3085 tinfo->current.width); 3086 ahc->msgout_index = 0; 3087 ahc->msgout_len = 0; 3088 ahc_construct_sdtr(ahc, period, offset); 3089 ahc->msgout_index = 0; 3090 response = TRUE; 3091 } else 3092 ahc_update_xfer_mode(ahc, devinfo); 3093 } 3094 done = MSGLOOP_MSGCOMPLETE; 3095 break; 3096 } 3097 default: 3098 /* Unknown extended message. Reject it. */ 3099 reject = TRUE; 3100 break; 3101 } 3102 break; 3103 } 3104 case MSG_BUS_DEV_RESET: 3105 ahc_handle_devreset(ahc, devinfo, 3106 XS_RESET, "Bus Device Reset Received", 3107 /*verbose_level*/0); 3108 restart_sequencer(ahc); 3109 done = MSGLOOP_TERMINATED; 3110 break; 3111 case MSG_ABORT_TAG: 3112 case MSG_ABORT: 3113 case MSG_CLEAR_QUEUE: 3114 /* Target mode messages */ 3115 if (devinfo->role != ROLE_TARGET) { 3116 reject = TRUE; 3117 break; 3118 } 3119 #if AHC_TARGET_MODE 3120 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3121 devinfo->lun, 3122 ahc->msgin_buf[0] == MSG_ABORT_TAG 3123 ? SCB_LIST_NULL 3124 : ahc_inb(ahc, INITIATOR_TAG), 3125 ROLE_TARGET, XS_DRIVER_STUFFUP); 3126 3127 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3128 if (tstate != NULL) { 3129 struct tmode_lstate* lstate; 3130 3131 lstate = tstate->enabled_luns[devinfo->lun]; 3132 if (lstate != NULL) { 3133 ahc_queue_lstate_event(ahc, lstate, 3134 devinfo->our_scsiid, 3135 ahc->msgin_buf[0], 3136 /*arg*/0); 3137 ahc_send_lstate_events(ahc, lstate); 3138 } 3139 } 3140 done = MSGLOOP_MSGCOMPLETE; 3141 #else 3142 panic("ahc: got target mode message"); 3143 #endif 3144 break; 3145 case MSG_TERM_IO_PROC: 3146 default: 3147 reject = TRUE; 3148 break; 3149 } 3150 3151 if (reject) { 3152 /* 3153 * Setup to reject the message. 3154 */ 3155 ahc->msgout_index = 0; 3156 ahc->msgout_len = 1; 3157 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3158 done = MSGLOOP_MSGCOMPLETE; 3159 response = TRUE; 3160 } 3161 3162 if (done != MSGLOOP_IN_PROG && !response) 3163 /* Clear the outgoing message buffer */ 3164 ahc->msgout_len = 0; 3165 3166 return (done); 3167 } 3168 3169 static void 3170 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3171 { 3172 u_int scb_index; 3173 struct scb *scb; 3174 3175 scb_index = ahc_inb(ahc, SCB_TAG); 3176 scb = &ahc->scb_data->scbarray[scb_index]; 3177 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3178 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3179 /* 3180 * Ignore the message if we haven't 3181 * seen an appropriate data phase yet. 3182 */ 3183 } else { 3184 /* 3185 * If the residual occurred on the last 3186 * transfer and the transfer request was 3187 * expected to end on an odd count, do 3188 * nothing. Otherwise, subtract a byte 3189 * and update the residual count accordingly. 3190 */ 3191 u_int resid_sgcnt; 3192 3193 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3194 if (resid_sgcnt == 0 3195 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3196 /* 3197 * If the residual occurred on the last 3198 * transfer and the transfer request was 3199 * expected to end on an odd count, do 3200 * nothing. 3201 */ 3202 } else { 3203 u_int data_cnt; 3204 u_int32_t data_addr; 3205 u_int sg_index; 3206 3207 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3208 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3209 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3210 3211 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3212 | (ahc_inb(ahc, SHADDR + 2) << 16) 3213 | (ahc_inb(ahc, SHADDR + 1) << 8) 3214 | (ahc_inb(ahc, SHADDR)); 3215 3216 data_cnt += 1; 3217 data_addr -= 1; 3218 3219 sg_index = scb->sg_count - resid_sgcnt; 3220 3221 if (sg_index != 0 3222 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3223 u_int32_t sg_addr; 3224 3225 sg_index--; 3226 data_cnt = 1; 3227 data_addr = le32toh(scb->sg_list[sg_index].addr) 3228 + le32toh(scb->sg_list[sg_index].len) 3229 - 1; 3230 3231 /* 3232 * The physical address base points to the 3233 * second entry as it is always used for 3234 * calculating the "next S/G pointer". 3235 */ 3236 sg_addr = scb->sg_list_phys 3237 + (sg_index* sizeof(*scb->sg_list)); 3238 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3239 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3240 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3241 ahc_outb(ahc, SG_NEXT, sg_addr); 3242 } 3243 3244 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3245 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3246 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3247 3248 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3249 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3250 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3251 ahc_outb(ahc, SHADDR, data_addr); 3252 } 3253 } 3254 } 3255 3256 static void 3257 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3258 int status, char *message, 3259 int verbose_level) 3260 { 3261 int found; 3262 3263 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3264 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3265 status); 3266 3267 /* 3268 * Go back to async/narrow transfers and renegotiate. 3269 * ahc_set_width and ahc_set_syncrate can cope with NULL 3270 * paths. 3271 */ 3272 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3273 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3274 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3275 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3276 /*paused*/TRUE, /*done*/FALSE); 3277 ahc_update_xfer_mode(ahc, devinfo); 3278 3279 if (message != NULL && (verbose_level <= 0)) 3280 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3281 message, devinfo->channel, devinfo->target, found); 3282 } 3283 3284 /* 3285 * We have an scb which has been processed by the 3286 * adaptor, now we look to see how the operation 3287 * went. 3288 */ 3289 static void 3290 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3291 { 3292 struct scsipi_xfer *xs; 3293 struct scsipi_periph *periph; 3294 int requeue = 0; 3295 int target; 3296 3297 3298 xs = scb->xs; 3299 periph = xs->xs_periph; 3300 LIST_REMOVE(scb, plinks); 3301 3302 callout_stop(&scb->xs->xs_callout); 3303 3304 #ifdef AHC_DEBUG 3305 if (ahc_debug & AHC_SHOWCMDS) { 3306 scsipi_printaddr(periph); 3307 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3308 scb->hscb->tag); 3309 } 3310 #endif 3311 3312 target = periph->periph_target; 3313 3314 if (xs->datalen) { 3315 int op; 3316 3317 if (xs->xs_control & XS_CTL_DATA_IN) 3318 op = BUS_DMASYNC_POSTREAD; 3319 else 3320 op = BUS_DMASYNC_POSTWRITE; 3321 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3322 scb->dmamap->dm_mapsize, op); 3323 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3324 } 3325 3326 /* 3327 * Unbusy this target/channel/lun. 3328 * XXX if we are holding two commands per lun, 3329 * send the next command. 3330 */ 3331 if (!(scb->hscb->control & TAG_ENB)) 3332 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3333 3334 /* 3335 * If the recovery SCB completes, we have to be 3336 * out of our timeout. 3337 */ 3338 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3339 3340 struct scb *scbp; 3341 3342 /* 3343 * We were able to complete the command successfully, 3344 * so reinstate the timeouts for all other pending 3345 * commands. 3346 */ 3347 scbp = ahc->pending_ccbs.lh_first; 3348 while (scbp != NULL) { 3349 struct scsipi_xfer *txs = scbp->xs; 3350 3351 if (!(txs->xs_control & XS_CTL_POLL)) { 3352 callout_reset(&scbp->xs->xs_callout, 3353 (scbp->xs->timeout > 1000000) ? 3354 (scbp->xs->timeout / 1000) * hz : 3355 (scbp->xs->timeout * hz) / 1000, 3356 ahc_timeout, scbp); 3357 } 3358 scbp = LIST_NEXT(scbp, plinks); 3359 } 3360 3361 /* 3362 * Ensure that we didn't put a second instance of this 3363 * SCB into the QINFIFO. 3364 */ 3365 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3366 SCB_LUN(scb), scb->hscb->tag, 3367 ROLE_INITIATOR, /*status*/0, 3368 SEARCH_REMOVE); 3369 if (xs->error != XS_NOERROR) 3370 ahcsetccbstatus(xs, XS_TIMEOUT); 3371 scsipi_printaddr(xs->xs_periph); 3372 printf("no longer in timeout, status = %x\n", xs->status); 3373 } 3374 3375 if (xs->error != XS_NOERROR) { 3376 /* Don't clobber any existing error state */ 3377 } else if ((scb->flags & SCB_SENSE) != 0) { 3378 /* 3379 * We performed autosense retrieval. 3380 * 3381 * zero the sense data before having 3382 * the drive fill it. The SCSI spec mandates 3383 * that any untransferred data should be 3384 * assumed to be zero. Complete the 'bounce' 3385 * of sense information through buffers accessible 3386 * via bus-space by copying it into the clients 3387 * csio. 3388 */ 3389 memset(&xs->sense.scsi_sense, 0, sizeof(xs->sense.scsi_sense)); 3390 memcpy(&xs->sense.scsi_sense, 3391 &ahc->scb_data->sense[scb->hscb->tag], 3392 le32toh(scb->sg_list->len)); 3393 xs->error = XS_SENSE; 3394 } 3395 if (scb->flags & SCB_FREEZE_QUEUE) { 3396 scsipi_periph_thaw(periph, 1); 3397 scb->flags &= ~SCB_FREEZE_QUEUE; 3398 } 3399 3400 requeue = scb->flags & SCB_REQUEUE; 3401 ahcfreescb(ahc, scb); 3402 3403 if (requeue) { 3404 xs->error = XS_REQUEUE; 3405 } 3406 scsipi_done(xs); 3407 } 3408 3409 /* 3410 * Determine the number of SCBs available on the controller 3411 */ 3412 int 3413 ahc_probe_scbs(struct ahc_softc *ahc) { 3414 int i; 3415 3416 for (i = 0; i < AHC_SCB_MAX; i++) { 3417 ahc_outb(ahc, SCBPTR, i); 3418 ahc_outb(ahc, SCB_CONTROL, i); 3419 if (ahc_inb(ahc, SCB_CONTROL) != i) 3420 break; 3421 ahc_outb(ahc, SCBPTR, 0); 3422 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3423 break; 3424 } 3425 return (i); 3426 } 3427 3428 /* 3429 * Start the board, ready for normal operation 3430 */ 3431 int 3432 ahc_init(struct ahc_softc *ahc) 3433 { 3434 int max_targ = 15; 3435 int i; 3436 int term; 3437 u_int scsi_conf; 3438 u_int scsiseq_template; 3439 u_int ultraenb; 3440 u_int discenable; 3441 u_int tagenable; 3442 size_t driver_data_size; 3443 u_int32_t physaddr; 3444 3445 #ifdef AHC_PRINT_SRAM 3446 printf("Scratch Ram:"); 3447 for (i = 0x20; i < 0x5f; i++) { 3448 if (((i % 8) == 0) && (i != 0)) { 3449 printf ("\n "); 3450 } 3451 printf (" 0x%x", ahc_inb(ahc, i)); 3452 } 3453 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3454 for (i = 0x70; i < 0x7f; i++) { 3455 if (((i % 8) == 0) && (i != 0)) { 3456 printf ("\n "); 3457 } 3458 printf (" 0x%x", ahc_inb(ahc, i)); 3459 } 3460 } 3461 printf ("\n"); 3462 #endif 3463 3464 /* 3465 * Assume we have a board at this stage and it has been reset. 3466 */ 3467 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3468 ahc->our_id = ahc->our_id_b = 7; 3469 3470 /* 3471 * Default to allowing initiator operations. 3472 */ 3473 ahc->flags |= AHC_INITIATORMODE; 3474 3475 /* 3476 * DMA tag for our command fifos and other data in system memory 3477 * the card's sequencer must be able to access. For initiator 3478 * roles, we need to allocate space for the qinfifo, qoutfifo, 3479 * and untagged_scb arrays each of which are composed of 256 3480 * 1 byte elements. When providing for the target mode role, 3481 * we additionally must provide space for the incoming target 3482 * command fifo. 3483 */ 3484 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3485 3486 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3487 ahc->sc_dmaflags, 3488 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3489 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3490 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3491 return (ENOMEM); 3492 3493 ahc->init_level++; 3494 3495 /* Allocate SCB data now that parent_dmat is initialized */ 3496 if (ahc->scb_data->maxhscbs == 0) 3497 if (ahcinitscbdata(ahc) != 0) 3498 return (ENOMEM); 3499 3500 ahc->qinfifo = &ahc->qoutfifo[256]; 3501 ahc->untagged_scbs = &ahc->qinfifo[256]; 3502 /* There are no untagged SCBs active yet. */ 3503 for (i = 0; i < 256; i++) 3504 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3505 3506 /* All of our queues are empty */ 3507 for (i = 0; i < 256; i++) 3508 ahc->qoutfifo[i] = SCB_LIST_NULL; 3509 3510 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3511 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3512 3513 /* 3514 * Allocate a tstate to house information for our 3515 * initiator presence on the bus as well as the user 3516 * data for any target mode initiator. 3517 */ 3518 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3519 printf("%s: unable to allocate tmode_tstate. " 3520 "Failing attach\n", ahc_name(ahc)); 3521 return (-1); 3522 } 3523 3524 if ((ahc->features & AHC_TWIN) != 0) { 3525 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3526 printf("%s: unable to allocate tmode_tstate. " 3527 "Failing attach\n", ahc_name(ahc)); 3528 return (-1); 3529 } 3530 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3531 ahc->our_id, ahc->our_id_b, 3532 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3533 } else { 3534 if ((ahc->features & AHC_WIDE) != 0) { 3535 printf("Wide "); 3536 } else { 3537 printf("Single "); 3538 } 3539 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3540 } 3541 3542 ahc_outb(ahc, SEQ_FLAGS, 0); 3543 3544 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3545 ahc->flags |= AHC_PAGESCBS; 3546 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3547 } else { 3548 ahc->flags &= ~AHC_PAGESCBS; 3549 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3550 } 3551 3552 #ifdef AHC_DEBUG 3553 if (ahc_debug & AHC_SHOWMISC) { 3554 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 3555 "ahc_dma %lu bytes\n", 3556 ahc_name(ahc), 3557 (unsigned long) sizeof(struct hardware_scb), 3558 (unsigned long) sizeof(struct scb), 3559 (unsigned long) sizeof(struct ahc_dma_seg)); 3560 } 3561 #endif /* AHC_DEBUG */ 3562 3563 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3564 if (ahc->features & AHC_TWIN) { 3565 3566 /* 3567 * The device is gated to channel B after a chip reset, 3568 * so set those values first 3569 */ 3570 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3571 if ((ahc->features & AHC_ULTRA2) != 0) 3572 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3573 else 3574 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3575 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3576 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3577 |term|ENSTIMER|ACTNEGEN); 3578 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3579 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3580 3581 if ((scsi_conf & RESET_SCSI) != 0 3582 && (ahc->flags & AHC_INITIATORMODE) != 0) 3583 ahc->flags |= AHC_RESET_BUS_B; 3584 3585 /* Select Channel A */ 3586 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3587 } 3588 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3589 if ((ahc->features & AHC_ULTRA2) != 0) 3590 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3591 else 3592 ahc_outb(ahc, SCSIID, ahc->our_id); 3593 scsi_conf = ahc_inb(ahc, SCSICONF); 3594 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3595 |term 3596 |ENSTIMER|ACTNEGEN); 3597 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3598 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3599 3600 if ((scsi_conf & RESET_SCSI) != 0 3601 && (ahc->flags & AHC_INITIATORMODE) != 0) 3602 ahc->flags |= AHC_RESET_BUS_A; 3603 3604 /* 3605 * Look at the information that board initialization or 3606 * the board bios has left us. 3607 */ 3608 ultraenb = 0; 3609 tagenable = ALL_TARGETS_MASK; 3610 3611 /* Grab the disconnection disable table and invert it for our needs */ 3612 if (ahc->flags & AHC_USEDEFAULTS) { 3613 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3614 "device parameters\n", ahc_name(ahc)); 3615 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3616 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3617 discenable = ALL_TARGETS_MASK; 3618 if ((ahc->features & AHC_ULTRA) != 0) 3619 ultraenb = ALL_TARGETS_MASK; 3620 } else { 3621 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3622 | ahc_inb(ahc, DISC_DSB)); 3623 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3624 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3625 | ahc_inb(ahc, ULTRA_ENB); 3626 } 3627 3628 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3629 max_targ = 7; 3630 3631 for (i = 0; i <= max_targ; i++) { 3632 struct ahc_initiator_tinfo *tinfo; 3633 struct tmode_tstate *tstate; 3634 u_int our_id; 3635 u_int target_id; 3636 char channel; 3637 3638 channel = 'A'; 3639 our_id = ahc->our_id; 3640 target_id = i; 3641 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3642 channel = 'B'; 3643 our_id = ahc->our_id_b; 3644 target_id = i % 8; 3645 } 3646 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3647 target_id, &tstate); 3648 /* Default to async narrow across the board */ 3649 memset(tinfo, 0, sizeof(*tinfo)); 3650 if (ahc->flags & AHC_USEDEFAULTS) { 3651 if ((ahc->features & AHC_WIDE) != 0) 3652 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3653 3654 /* 3655 * These will be truncated when we determine the 3656 * connection type we have with the target. 3657 */ 3658 tinfo->user.period = ahc_syncrates->period; 3659 tinfo->user.offset = ~0; 3660 } else { 3661 u_int scsirate; 3662 u_int16_t mask; 3663 3664 /* Take the settings leftover in scratch RAM. */ 3665 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3666 mask = (0x01 << i); 3667 if ((ahc->features & AHC_ULTRA2) != 0) { 3668 u_int offset; 3669 u_int maxsync; 3670 3671 if ((scsirate & SOFS) == 0x0F) { 3672 /* 3673 * Haven't negotiated yet, 3674 * so the format is different. 3675 */ 3676 scsirate = (scsirate & SXFR) >> 4 3677 | (ultraenb & mask) 3678 ? 0x08 : 0x0 3679 | (scsirate & WIDEXFER); 3680 offset = MAX_OFFSET_ULTRA2; 3681 } else 3682 offset = ahc_inb(ahc, TARG_OFFSET + i); 3683 maxsync = AHC_SYNCRATE_ULTRA2; 3684 if ((ahc->features & AHC_DT) != 0) 3685 maxsync = AHC_SYNCRATE_DT; 3686 tinfo->user.period = 3687 ahc_find_period(ahc, scsirate, maxsync); 3688 if (offset == 0) 3689 tinfo->user.period = 0; 3690 else 3691 tinfo->user.offset = ~0; 3692 } else if ((scsirate & SOFS) != 0) { 3693 tinfo->user.period = 3694 ahc_find_period(ahc, scsirate, 3695 (ultraenb & mask) 3696 ? AHC_SYNCRATE_ULTRA 3697 : AHC_SYNCRATE_FAST); 3698 if (tinfo->user.period != 0) 3699 tinfo->user.offset = ~0; 3700 } 3701 if ((scsirate & WIDEXFER) != 0 3702 && (ahc->features & AHC_WIDE) != 0) 3703 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3704 } 3705 tinfo->goal = tinfo->user; /* force negotiation */ 3706 tstate->ultraenb = ultraenb; 3707 tstate->discenable = discenable; 3708 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3709 tstate->tagdisable = 0; 3710 } 3711 ahc->user_discenable = discenable; 3712 ahc->user_tagenable = tagenable; 3713 3714 /* 3715 * Tell the sequencer where it can find our arrays in memory. 3716 */ 3717 physaddr = ahc->scb_data->hscb_busaddr; 3718 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3719 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3720 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3721 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3722 3723 physaddr = ahc->shared_data_busaddr; 3724 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3725 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3726 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3727 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3728 3729 /* Target mode incomding command fifo */ 3730 physaddr += 3 * 256 * sizeof(u_int8_t); 3731 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3732 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3733 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3734 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3735 3736 /* 3737 * Initialize the group code to command length table. 3738 * This overrides the values in TARG_SCSIRATE, so only 3739 * setup the table after we have processed that information. 3740 */ 3741 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3742 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3743 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3744 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3745 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3746 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3747 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3748 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3749 3750 /* Tell the sequencer of our initial queue positions */ 3751 ahc_outb(ahc, KERNEL_QINPOS, 0); 3752 ahc_outb(ahc, QINPOS, 0); 3753 ahc_outb(ahc, QOUTPOS, 0); 3754 3755 #ifdef AHC_DEBUG 3756 if (ahc_debug & AHC_SHOWMISC) 3757 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3758 discenable, ultraenb); 3759 #endif 3760 3761 /* Don't have any special messages to send to targets */ 3762 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3763 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3764 3765 /* 3766 * Use the built in queue management registers 3767 * if they are available. 3768 */ 3769 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3770 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3771 ahc_outb(ahc, SDSCB_QOFF, 0); 3772 ahc_outb(ahc, SNSCB_QOFF, 0); 3773 ahc_outb(ahc, HNSCB_QOFF, 0); 3774 } 3775 3776 3777 /* We don't have any waiting selections */ 3778 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3779 3780 /* Our disconnection list is empty too */ 3781 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3782 3783 /* Message out buffer starts empty */ 3784 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3785 3786 /* 3787 * Setup the allowed SCSI Sequences based on operational mode. 3788 * If we are a target, we'll enable select in operations once 3789 * we've had a lun enabled. 3790 */ 3791 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3792 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3793 scsiseq_template |= ENRSELI; 3794 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3795 3796 /* 3797 * Load the Sequencer program and Enable the adapter 3798 * in "fast" mode. 3799 */ 3800 #ifdef AHC_DEBUG 3801 printf("%s: Downloading Sequencer Program...", 3802 ahc_name(ahc)); 3803 #endif 3804 3805 ahc_loadseq(ahc); 3806 3807 /* We have to wait until after any system dumps... */ 3808 shutdownhook_establish(ahc_shutdown, ahc); 3809 3810 return (0); 3811 } 3812 3813 static int 3814 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3815 struct proc *p) 3816 { 3817 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3818 int s, ret = ENOTTY; 3819 3820 switch (cmd) { 3821 case SCBUSIORESET: 3822 s = splbio(); 3823 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3824 TRUE); 3825 splx(s); 3826 ret = 0; 3827 break; 3828 default: 3829 break; 3830 } 3831 3832 return ret; 3833 } 3834 3835 3836 /* 3837 * XXX fvdl the busy_tcl checks and settings should only be done 3838 * for the non-tagged queueing case, but we don't do tagged queueing 3839 * yet, so.. 3840 */ 3841 static void 3842 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3843 { 3844 struct scsipi_xfer *xs; 3845 struct scsipi_periph *periph; 3846 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3847 struct scb *scb; 3848 struct hardware_scb *hscb; 3849 struct ahc_initiator_tinfo *tinfo; 3850 struct tmode_tstate *tstate; 3851 u_int target_id; 3852 u_int our_id; 3853 int s, tcl; 3854 u_int16_t mask; 3855 char channel; 3856 3857 switch (req) { 3858 case ADAPTER_REQ_RUN_XFER: 3859 xs = arg; 3860 periph = xs->xs_periph; 3861 3862 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("ahc_action\n")); 3863 3864 /* must protect the queue */ 3865 s = splbio(); 3866 3867 tcl = XS_TCL(ahc, xs); 3868 3869 if (!ahc_istagged_device(ahc, xs, 0) && 3870 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3871 panic("ahc_action: not tagged and device busy"); 3872 } 3873 3874 3875 target_id = periph->periph_target; 3876 our_id = SIM_SCSI_ID(ahc, periph); 3877 3878 /* 3879 * get an scb to use. 3880 */ 3881 if ((scb = ahcgetscb(ahc)) == NULL) { 3882 xs->error = XS_RESOURCE_SHORTAGE; 3883 scsipi_done(xs); 3884 splx(s); 3885 return; 3886 } 3887 3888 tcl = XS_TCL(ahc, xs); 3889 3890 #ifdef DIAGNOSTIC 3891 if (!ahc_istagged_device(ahc, xs, 0) && 3892 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3893 panic("ahc: queuing for busy target"); 3894 #endif 3895 3896 scb->xs = xs; 3897 hscb = scb->hscb; 3898 hscb->tcl = tcl; 3899 3900 if (xs->xs_tag_type) { 3901 #ifdef DIAGNOSTIC 3902 if (ahc_istagged_device(ahc, xs, 0) == 0) 3903 panic("ahc_action: taggged command for untagged device"); 3904 #endif 3905 scb->hscb->control |= TAG_ENB; 3906 } else 3907 ahc_busy_tcl(ahc, scb); 3908 3909 splx(s); 3910 3911 channel = SIM_CHANNEL(ahc, periph); 3912 if (ahc->inited_channels[channel - 'A'] == 0) { 3913 if ((channel == 'A' && 3914 (ahc->flags & AHC_RESET_BUS_A)) || 3915 (channel == 'B' && 3916 (ahc->flags & AHC_RESET_BUS_B))) { 3917 s = splbio(); 3918 ahc_reset_channel(ahc, channel, TRUE); 3919 splx(s); 3920 } 3921 ahc->inited_channels[channel - 'A'] = 1; 3922 } 3923 3924 /* 3925 * Put all the arguments for the xfer in the scb 3926 */ 3927 3928 mask = SCB_TARGET_MASK(scb); 3929 tinfo = ahc_fetch_transinfo(ahc, 3930 SIM_CHANNEL(ahc, periph), 3931 our_id, target_id, &tstate); 3932 if (ahc->inited_targets[target_id] == 0) { 3933 struct ahc_devinfo devinfo; 3934 s = splbio(); 3935 ahc_compile_devinfo(&devinfo, our_id, target_id, 3936 periph->periph_lun, 3937 SIM_CHANNEL(ahc, periph), 3938 ROLE_INITIATOR); 3939 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3940 TRUE, FALSE); 3941 ahc->inited_targets[target_id] = 1; 3942 splx(s); 3943 } 3944 hscb->scsirate = tinfo->scsirate; 3945 hscb->scsioffset = tinfo->current.offset; 3946 if ((tstate->ultraenb & mask) != 0) 3947 hscb->control |= ULTRAENB; 3948 3949 if ((tstate->discenable & mask) != 0) 3950 hscb->control |= DISCENB; 3951 3952 if (xs->xs_control & XS_CTL_RESET) { 3953 hscb->cmdpointer = 0; 3954 scb->flags |= SCB_DEVICE_RESET; 3955 hscb->control |= MK_MESSAGE; 3956 ahc_execute_scb(scb, NULL, 0); 3957 } 3958 3959 ahc_setup_data(ahc, xs, scb); 3960 return; 3961 case ADAPTER_REQ_GROW_RESOURCES: 3962 /* XXX not supported */ 3963 return; 3964 case ADAPTER_REQ_SET_XFER_MODE: 3965 { 3966 struct scsipi_xfer_mode *xm = arg; 3967 struct ahc_devinfo devinfo; 3968 int target_id, our_id; 3969 char channel; 3970 3971 target_id = xm->xm_target; 3972 our_id = chan->chan_id; 3973 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 3974 s = splbio(); 3975 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 3976 &tstate); 3977 ahc_compile_devinfo(&devinfo, our_id, target_id, 3978 0, channel, ROLE_INITIATOR); 3979 ahc->inited_targets[target_id] = 2; 3980 if (xm->xm_mode & PERIPH_CAP_TQING && 3981 (tstate->tagdisable & devinfo.target_mask) == 0) { 3982 ahc_set_tags(ahc, &devinfo, TRUE); 3983 } 3984 splx(s); 3985 ahc_update_xfer_mode(ahc, &devinfo); 3986 } 3987 } 3988 } 3989 3990 static void 3991 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 3992 { 3993 struct scb *scb; 3994 struct scsipi_xfer *xs; 3995 struct ahc_softc *ahc; 3996 int s; 3997 3998 scb = (struct scb *)arg; 3999 xs = scb->xs; 4000 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4001 4002 4003 if (nsegments != 0) { 4004 struct ahc_dma_seg *sg; 4005 bus_dma_segment_t *end_seg; 4006 int op; 4007 4008 end_seg = dm_segs + nsegments; 4009 4010 /* Copy the first SG into the data pointer area */ 4011 scb->hscb->data = dm_segs->ds_addr; 4012 scb->hscb->datalen = dm_segs->ds_len; 4013 4014 /* Copy the segments into our SG list */ 4015 sg = scb->sg_list; 4016 while (dm_segs < end_seg) { 4017 sg->addr = dm_segs->ds_addr; 4018 sg->len = dm_segs->ds_len; 4019 ahc_swap_sg(sg); 4020 sg++; 4021 dm_segs++; 4022 } 4023 4024 /* Note where to find the SG entries in bus space */ 4025 scb->hscb->SG_pointer = scb->sg_list_phys; 4026 4027 if (xs->xs_control & XS_CTL_DATA_IN) 4028 op = BUS_DMASYNC_PREREAD; 4029 else 4030 op = BUS_DMASYNC_PREWRITE; 4031 4032 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4033 scb->dmamap->dm_mapsize, op); 4034 4035 } else { 4036 scb->hscb->SG_pointer = 0; 4037 scb->hscb->data = 0; 4038 scb->hscb->datalen = 0; 4039 } 4040 4041 scb->sg_count = scb->hscb->SG_count = nsegments; 4042 4043 s = splbio(); 4044 4045 /* 4046 * Last time we need to check if this SCB needs to 4047 * be aborted. 4048 */ 4049 if (xs->xs_status & XS_STS_DONE) { 4050 if (!ahc_istagged_device(ahc, xs, 0)) 4051 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4052 if (nsegments != 0) 4053 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4054 ahcfreescb(ahc, scb); 4055 splx(s); 4056 return; 4057 } 4058 4059 #ifdef DIAGNOSTIC 4060 if (scb->sg_count > 255) 4061 panic("ahc bad sg_count"); 4062 #endif 4063 4064 ahc_swap_hscb(scb->hscb); 4065 4066 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4067 4068 scb->flags |= SCB_ACTIVE; 4069 4070 if (!(xs->xs_control & XS_CTL_POLL)) 4071 callout_reset(&scb->xs->xs_callout, xs->timeout > 1000000 ? 4072 (xs->timeout / 1000) * hz : (xs->timeout * hz) / 1000, 4073 ahc_timeout, scb); 4074 4075 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4076 #if 0 4077 printf("Continueing Immediate Command %d:%d\n", 4078 xs->xs_periph->periph_target, 4079 xs->xs_periph->periph_lun); 4080 #endif 4081 pause_sequencer(ahc); 4082 if ((ahc->flags & AHC_PAGESCBS) == 0) 4083 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4084 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4085 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4086 unpause_sequencer(ahc); 4087 } else { 4088 4089 #if 0 4090 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4091 scb->hscb->tag, ahc->qinfifonext, 4092 &ahc->qinfifo[ahc->qinfifonext], 4093 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4094 #endif 4095 4096 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4097 4098 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4099 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4100 4101 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4102 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4103 } else { 4104 pause_sequencer(ahc); 4105 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4106 unpause_sequencer(ahc); 4107 } 4108 } 4109 4110 #ifdef AHC_DEBUG 4111 if (ahc_debug & AHC_SHOWCMDS) { 4112 scsi_print_addr(xs->xs_periph); 4113 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4114 " rate %x\n", 4115 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4116 scb->flags, scb->hscb->control, ahc->qinfifonext, 4117 scb->hscb->scsirate); 4118 } 4119 #endif 4120 4121 if (!(xs->xs_control & XS_CTL_POLL)) { 4122 splx(s); 4123 return; 4124 } 4125 /* 4126 * If we can't use interrupts, poll for completion 4127 */ 4128 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("cmd_poll\n")); 4129 do { 4130 if (ahc_poll(ahc, xs->timeout)) { 4131 if (!(xs->xs_control & XS_CTL_SILENT)) 4132 printf("cmd fail\n"); 4133 ahc_timeout(scb); 4134 break; 4135 } 4136 } while (!(xs->xs_status & XS_STS_DONE)); 4137 splx(s); 4138 return; 4139 } 4140 4141 static int 4142 ahc_poll(struct ahc_softc *ahc, int wait) 4143 { 4144 while (--wait) { 4145 DELAY(1000); 4146 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4147 break; 4148 } 4149 4150 if (wait == 0) { 4151 printf("%s: board is not responding\n", ahc_name(ahc)); 4152 return (EIO); 4153 } 4154 4155 ahc_intr((void *)ahc); 4156 return (0); 4157 } 4158 4159 static void 4160 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4161 struct scb *scb) 4162 { 4163 struct hardware_scb *hscb; 4164 4165 hscb = scb->hscb; 4166 xs->resid = xs->status = 0; 4167 4168 hscb->cmdlen = xs->cmdlen; 4169 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4170 hscb->cmdpointer = hscb->cmdstore_busaddr; 4171 4172 /* Only use S/G if there is a transfer */ 4173 if (xs->datalen) { 4174 int error; 4175 4176 error = bus_dmamap_load(ahc->parent_dmat, 4177 scb->dmamap, xs->data, 4178 xs->datalen, NULL, 4179 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4180 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4181 BUS_DMA_STREAMING | 4182 ((xs->xs_control & XS_CTL_DATA_IN) ? 4183 BUS_DMA_READ : BUS_DMA_WRITE)); 4184 if (error) { 4185 #ifdef AHC_DEBUG 4186 printf("%s: in ahc_setup_data(): bus_dmamap_load() " 4187 "= %d\n", 4188 ahc_name(ahc), 4189 error); 4190 #endif 4191 if (!ahc_istagged_device(ahc, xs, 0)) 4192 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4193 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4194 scsipi_done(xs); 4195 return; 4196 } 4197 ahc_execute_scb(scb, 4198 scb->dmamap->dm_segs, 4199 scb->dmamap->dm_nsegs); 4200 } else { 4201 ahc_execute_scb(scb, NULL, 0); 4202 } 4203 } 4204 4205 static void 4206 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4207 { 4208 int target; 4209 char channel; 4210 int lun; 4211 4212 target = periph->periph_target; 4213 lun = periph->periph_lun; 4214 channel = periph->periph_channel->chan_channel; 4215 4216 ahc_search_qinfifo(ahc, target, channel, lun, 4217 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4218 SCB_REQUEUE, SEARCH_COMPLETE); 4219 } 4220 4221 static void 4222 ahcallocscbs(struct ahc_softc *ahc) 4223 { 4224 struct scb_data *scb_data; 4225 struct scb *next_scb; 4226 struct sg_map_node *sg_map; 4227 bus_addr_t physaddr; 4228 struct ahc_dma_seg *segs; 4229 int newcount; 4230 int i; 4231 4232 scb_data = ahc->scb_data; 4233 if (scb_data->numscbs >= AHC_SCB_MAX) 4234 /* Can't allocate any more */ 4235 return; 4236 4237 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4238 4239 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4240 4241 if (sg_map == NULL) 4242 return; 4243 4244 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4245 &sg_map->sg_dmamap, 4246 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4247 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4248 "SG space") < 0) { 4249 free(sg_map, M_DEVBUF); 4250 return; 4251 } 4252 4253 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4254 4255 segs = sg_map->sg_vaddr; 4256 physaddr = sg_map->sg_physaddr; 4257 4258 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4259 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4260 int error; 4261 4262 next_scb->sg_list = segs; 4263 /* 4264 * The sequencer always starts with the second entry. 4265 * The first entry is embedded in the scb. 4266 */ 4267 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4268 next_scb->flags = SCB_FREE; 4269 error = bus_dmamap_create(ahc->parent_dmat, 4270 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4271 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4272 &next_scb->dmamap); 4273 if (error != 0) 4274 break; 4275 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4276 next_scb->hscb->tag = ahc->scb_data->numscbs; 4277 next_scb->hscb->cmdstore_busaddr = 4278 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4279 + offsetof(struct hardware_scb, cmdstore); 4280 next_scb->hscb->cmdstore_busaddr = 4281 htole32(next_scb->hscb->cmdstore_busaddr); 4282 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4283 segs += AHC_NSEG; 4284 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4285 next_scb++; 4286 ahc->scb_data->numscbs++; 4287 } 4288 #ifdef AHC_DEBUG 4289 if (ahc_debug & AHC_SHOWSCBALLOC) 4290 printf("%s: allocated %d new SCBs count now %d\n", 4291 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4292 #endif 4293 } 4294 4295 #ifdef AHC_DUMP_SEQ 4296 static void 4297 ahc_dumpseq(struct ahc_softc* ahc) 4298 { 4299 int i; 4300 int max_prog; 4301 4302 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4303 max_prog = 448; 4304 else if ((ahc->features & AHC_ULTRA2) != 0) 4305 max_prog = 768; 4306 else 4307 max_prog = 512; 4308 4309 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4310 ahc_outb(ahc, SEQADDR0, 0); 4311 ahc_outb(ahc, SEQADDR1, 0); 4312 for (i = 0; i < max_prog; i++) { 4313 u_int8_t ins_bytes[4]; 4314 4315 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4316 printf("0x%08x\n", ins_bytes[0] << 24 4317 | ins_bytes[1] << 16 4318 | ins_bytes[2] << 8 4319 | ins_bytes[3]); 4320 } 4321 } 4322 #endif 4323 4324 static void 4325 ahc_loadseq(struct ahc_softc *ahc) 4326 { 4327 const struct patch *cur_patch; 4328 int i; 4329 int downloaded; 4330 int skip_addr; 4331 u_int8_t download_consts[4]; 4332 4333 /* Setup downloadable constant table */ 4334 #if 0 4335 /* No downloaded constants are currently defined. */ 4336 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4337 #endif 4338 4339 cur_patch = patches; 4340 downloaded = 0; 4341 skip_addr = 0; 4342 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4343 ahc_outb(ahc, SEQADDR0, 0); 4344 ahc_outb(ahc, SEQADDR1, 0); 4345 4346 for (i = 0; i < sizeof(seqprog)/4; i++) { 4347 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4348 /* 4349 * Don't download this instruction as it 4350 * is in a patch that was removed. 4351 */ 4352 continue; 4353 } 4354 ahc_download_instr(ahc, i, download_consts); 4355 downloaded++; 4356 } 4357 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4358 restart_sequencer(ahc); 4359 4360 #ifdef AHC_DEBUG 4361 printf(" %d instructions downloaded\n", downloaded); 4362 #endif 4363 } 4364 4365 static int 4366 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4367 int start_instr, int *skip_addr) 4368 { 4369 const struct patch *cur_patch; 4370 const struct patch *last_patch; 4371 int num_patches; 4372 4373 num_patches = sizeof(patches)/sizeof(struct patch); 4374 last_patch = &patches[num_patches]; 4375 cur_patch = *start_patch; 4376 4377 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4378 4379 if (cur_patch->patch_func(ahc) == 0) { 4380 4381 /* Start rejecting code */ 4382 *skip_addr = start_instr + cur_patch->skip_instr; 4383 cur_patch += cur_patch->skip_patch; 4384 } else { 4385 /* Accepted this patch. Advance to the next 4386 * one and wait for our intruction pointer to 4387 * hit this point. 4388 */ 4389 cur_patch++; 4390 } 4391 } 4392 4393 *start_patch = cur_patch; 4394 if (start_instr < *skip_addr) 4395 /* Still skipping */ 4396 return (0); 4397 4398 return (1); 4399 } 4400 4401 static void 4402 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4403 { 4404 union ins_formats instr; 4405 struct ins_format1 *fmt1_ins; 4406 struct ins_format3 *fmt3_ins; 4407 u_int opcode; 4408 4409 /* Structure copy */ 4410 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4411 4412 instr.integer = le32toh(instr.integer); 4413 4414 fmt1_ins = &instr.format1; 4415 fmt3_ins = NULL; 4416 4417 /* Pull the opcode */ 4418 opcode = instr.format1.opcode; 4419 switch (opcode) { 4420 case AIC_OP_JMP: 4421 case AIC_OP_JC: 4422 case AIC_OP_JNC: 4423 case AIC_OP_CALL: 4424 case AIC_OP_JNE: 4425 case AIC_OP_JNZ: 4426 case AIC_OP_JE: 4427 case AIC_OP_JZ: 4428 { 4429 const struct patch *cur_patch; 4430 int address_offset; 4431 u_int address; 4432 int skip_addr; 4433 int i; 4434 4435 fmt3_ins = &instr.format3; 4436 address_offset = 0; 4437 address = fmt3_ins->address; 4438 cur_patch = patches; 4439 skip_addr = 0; 4440 4441 for (i = 0; i < address;) { 4442 4443 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4444 4445 if (skip_addr > i) { 4446 int end_addr; 4447 4448 end_addr = MIN(address, skip_addr); 4449 address_offset += end_addr - i; 4450 i = skip_addr; 4451 } else { 4452 i++; 4453 } 4454 } 4455 address -= address_offset; 4456 fmt3_ins->address = address; 4457 /* FALLTHROUGH */ 4458 } 4459 case AIC_OP_OR: 4460 case AIC_OP_AND: 4461 case AIC_OP_XOR: 4462 case AIC_OP_ADD: 4463 case AIC_OP_ADC: 4464 case AIC_OP_BMOV: 4465 if (fmt1_ins->parity != 0) { 4466 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4467 } 4468 fmt1_ins->parity = 0; 4469 /* FALLTHROUGH */ 4470 case AIC_OP_ROL: 4471 if ((ahc->features & AHC_ULTRA2) != 0) { 4472 int i, count; 4473 4474 /* Calculate odd parity for the instruction */ 4475 for (i = 0, count = 0; i < 31; i++) { 4476 u_int32_t mask; 4477 4478 mask = 0x01 << i; 4479 if ((instr.integer & mask) != 0) 4480 count++; 4481 } 4482 if ((count & 0x01) == 0) 4483 instr.format1.parity = 1; 4484 } else { 4485 /* Compress the instruction for older sequencers */ 4486 if (fmt3_ins != NULL) { 4487 instr.integer = 4488 fmt3_ins->immediate 4489 | (fmt3_ins->source << 8) 4490 | (fmt3_ins->address << 16) 4491 | (fmt3_ins->opcode << 25); 4492 } else { 4493 instr.integer = 4494 fmt1_ins->immediate 4495 | (fmt1_ins->source << 8) 4496 | (fmt1_ins->destination << 16) 4497 | (fmt1_ins->ret << 24) 4498 | (fmt1_ins->opcode << 25); 4499 } 4500 } 4501 instr.integer = htole32(instr.integer); 4502 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4503 break; 4504 default: 4505 panic("Unknown opcode encountered in seq program"); 4506 break; 4507 } 4508 } 4509 4510 static void 4511 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4512 { 4513 4514 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4515 struct scb *scbp; 4516 4517 scb->flags |= SCB_RECOVERY_SCB; 4518 4519 /* 4520 * Take all queued, but not sent SCBs out of the equation. 4521 * Also ensure that no new CCBs are queued to us while we 4522 * try to fix this problem. 4523 */ 4524 scsipi_channel_freeze(&ahc->sc_channel, 1); 4525 if (ahc->features & AHC_TWIN) 4526 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4527 4528 /* 4529 * Go through all of our pending SCBs and remove 4530 * any scheduled timeouts for them. We will reschedule 4531 * them after we've successfully fixed this problem. 4532 */ 4533 scbp = ahc->pending_ccbs.lh_first; 4534 while (scbp != NULL) { 4535 callout_stop(&scbp->xs->xs_callout); 4536 scbp = scbp->plinks.le_next; 4537 } 4538 } 4539 } 4540 4541 static void 4542 ahc_timeout(void *arg) 4543 { 4544 struct scb *scb; 4545 struct ahc_softc *ahc; 4546 int s, found; 4547 u_int last_phase; 4548 int target; 4549 int lun; 4550 int i; 4551 char channel; 4552 4553 scb = (struct scb *)arg; 4554 ahc = 4555 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4556 4557 s = splbio(); 4558 4559 /* 4560 * Ensure that the card doesn't do anything 4561 * behind our back. Also make sure that we 4562 * didn't "just" miss an interrupt that would 4563 * affect this timeout. 4564 */ 4565 do { 4566 ahc_intr(ahc); 4567 pause_sequencer(ahc); 4568 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4569 4570 if ((scb->flags & SCB_ACTIVE) == 0) { 4571 /* Previous timeout took care of me already */ 4572 printf("Timedout SCB handled by another timeout\n"); 4573 unpause_sequencer(ahc); 4574 splx(s); 4575 return; 4576 } 4577 4578 target = SCB_TARGET(scb); 4579 channel = SCB_CHANNEL(scb); 4580 lun = SCB_LUN(scb); 4581 4582 scsipi_printaddr(scb->xs->xs_periph); 4583 printf("SCB %x - timed out ", scb->hscb->tag); 4584 /* 4585 * Take a snapshot of the bus state and print out 4586 * some information so we can track down driver bugs. 4587 */ 4588 last_phase = ahc_inb(ahc, LASTPHASE); 4589 4590 for (i = 0; i < num_phases; i++) { 4591 if (last_phase == phase_table[i].phase) 4592 break; 4593 } 4594 printf("%s", phase_table[i].phasemsg); 4595 4596 printf(", SEQADDR == 0x%x\n", 4597 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4598 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4599 4600 #ifdef AHC_DEBUG 4601 ahc_print_scb(scb); 4602 #endif 4603 4604 #if 0 4605 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4606 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4607 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4608 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4609 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4610 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4611 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4612 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4613 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4614 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4615 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4616 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4617 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4618 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4619 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4620 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4621 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4622 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4623 if (scb->sg_count > 0) { 4624 for (i = 0; i < scb->sg_count; i++) { 4625 printf("sg[%d] - Addr 0x%x : Length %d\n", 4626 i, 4627 le32toh(scb->sg_list[i].addr), 4628 le32toh(scb->sg_list[i].len)); 4629 } 4630 } 4631 #endif 4632 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4633 /* 4634 * Been down this road before. 4635 * Do a full bus reset. 4636 */ 4637 bus_reset: 4638 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4639 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4640 printf("%s: Issued Channel %c Bus Reset. " 4641 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4642 } else { 4643 /* 4644 * If we are a target, transition to bus free and report 4645 * the timeout. 4646 * 4647 * The target/initiator that is holding up the bus may not 4648 * be the same as the one that triggered this timeout 4649 * (different commands have different timeout lengths). 4650 * If the bus is idle and we are actiing as the initiator 4651 * for this request, queue a BDR message to the timed out 4652 * target. Otherwise, if the timed out transaction is 4653 * active: 4654 * Initiator transaction: 4655 * Stuff the message buffer with a BDR message and assert 4656 * ATN in the hopes that the target will let go of the bus 4657 * and go to the mesgout phase. If this fails, we'll 4658 * get another timeout 2 seconds later which will attempt 4659 * a bus reset. 4660 * 4661 * Target transaction: 4662 * Transition to BUS FREE and report the error. 4663 * It's good to be the target! 4664 */ 4665 u_int active_scb_index; 4666 4667 active_scb_index = ahc_inb(ahc, SCB_TAG); 4668 4669 if (last_phase != P_BUSFREE 4670 && (active_scb_index < ahc->scb_data->numscbs)) { 4671 struct scb *active_scb; 4672 4673 /* 4674 * If the active SCB is not from our device, 4675 * assume that another device is hogging the bus 4676 * and wait for it's timeout to expire before 4677 * taking additional action. 4678 */ 4679 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4680 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4681 u_int newtimeout; 4682 4683 scsipi_printaddr(scb->xs->xs_periph); 4684 printf("Other SCB Timeout%s", 4685 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4686 ? " again\n" : "\n"); 4687 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4688 newtimeout = MAX(active_scb->xs->timeout, 4689 scb->xs->timeout); 4690 callout_reset(&scb->xs->xs_callout, 4691 newtimeout > 1000000 ? 4692 (newtimeout / 1000) * hz : 4693 (newtimeout * hz) / 1000, 4694 ahc_timeout, scb); 4695 splx(s); 4696 return; 4697 } 4698 4699 /* It's us */ 4700 if ((scb->hscb->control & TARGET_SCB) != 0) { 4701 4702 /* 4703 * Send back any queued up transactions 4704 * and properly record the error condition. 4705 */ 4706 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4707 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4708 ahc_freeze_ccb(scb); 4709 ahc_done(ahc, scb); 4710 4711 /* Will clear us from the bus */ 4712 restart_sequencer(ahc); 4713 splx(s); 4714 return; 4715 } 4716 4717 ahc_set_recoveryscb(ahc, active_scb); 4718 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4719 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4720 scsipi_printaddr(active_scb->xs->xs_periph); 4721 printf("BDR message in message buffer\n"); 4722 active_scb->flags |= SCB_DEVICE_RESET; 4723 callout_reset(&active_scb->xs->xs_callout, 4724 2 * hz, ahc_timeout, active_scb); 4725 unpause_sequencer(ahc); 4726 } else { 4727 int disconnected; 4728 4729 /* XXX Shouldn't panic. Just punt instead */ 4730 if ((scb->hscb->control & TARGET_SCB) != 0) 4731 panic("Timed-out target SCB but bus idle"); 4732 4733 if (last_phase != P_BUSFREE 4734 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4735 /* XXX What happened to the SCB? */ 4736 /* Hung target selection. Goto busfree */ 4737 printf("%s: Hung target selection\n", 4738 ahc_name(ahc)); 4739 restart_sequencer(ahc); 4740 splx(s); 4741 return; 4742 } 4743 4744 if (ahc_search_qinfifo(ahc, target, channel, lun, 4745 scb->hscb->tag, ROLE_INITIATOR, 4746 /*status*/0, SEARCH_COUNT) > 0) { 4747 disconnected = FALSE; 4748 } else { 4749 disconnected = TRUE; 4750 } 4751 4752 if (disconnected) { 4753 u_int active_scb; 4754 4755 ahc_set_recoveryscb(ahc, scb); 4756 /* 4757 * Simply set the MK_MESSAGE control bit. 4758 */ 4759 scb->hscb->control |= MK_MESSAGE; 4760 scb->flags |= SCB_QUEUED_MSG 4761 | SCB_DEVICE_RESET; 4762 4763 /* 4764 * Mark the cached copy of this SCB in the 4765 * disconnected list too, so that a reconnect 4766 * at this point causes a BDR or abort. 4767 */ 4768 active_scb = ahc_inb(ahc, SCBPTR); 4769 if (ahc_search_disc_list(ahc, target, 4770 channel, lun, 4771 scb->hscb->tag, 4772 /*stop_on_first*/TRUE, 4773 /*remove*/FALSE, 4774 /*save_state*/FALSE)) { 4775 u_int scb_control; 4776 4777 scb_control = ahc_inb(ahc, SCB_CONTROL); 4778 scb_control |= MK_MESSAGE; 4779 ahc_outb(ahc, SCB_CONTROL, scb_control); 4780 } 4781 ahc_outb(ahc, SCBPTR, active_scb); 4782 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4783 /*unbusy*/TRUE); 4784 4785 /* 4786 * Actually re-queue this SCB in case we can 4787 * select the device before it reconnects. 4788 * Clear out any entries in the QINFIFO first 4789 * so we are the next SCB for this target 4790 * to run. 4791 */ 4792 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4793 channel, SCB_LUN(scb), 4794 SCB_LIST_NULL, 4795 ROLE_INITIATOR, 4796 SCB_REQUEUE, 4797 SEARCH_COMPLETE); 4798 scsipi_printaddr(scb->xs->xs_periph); 4799 printf("Queuing a BDR SCB\n"); 4800 ahc->qinfifo[ahc->qinfifonext++] = 4801 scb->hscb->tag; 4802 4803 bus_dmamap_sync(ahc->parent_dmat, 4804 ahc->shared_data_dmamap, 4805 QINFIFO_OFFSET * 256, 256, 4806 BUS_DMASYNC_PREWRITE); 4807 4808 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4809 ahc_outb(ahc, HNSCB_QOFF, 4810 ahc->qinfifonext); 4811 } else { 4812 ahc_outb(ahc, KERNEL_QINPOS, 4813 ahc->qinfifonext); 4814 } 4815 callout_reset(&scb->xs->xs_callout, 2 * hz, 4816 ahc_timeout, scb); 4817 unpause_sequencer(ahc); 4818 } else { 4819 /* Go "immediatly" to the bus reset */ 4820 /* This shouldn't happen */ 4821 ahc_set_recoveryscb(ahc, scb); 4822 scsipi_printaddr(scb->xs->xs_periph); 4823 printf("SCB %x: Immediate reset. " 4824 "Flags = 0x%x\n", scb->hscb->tag, 4825 scb->flags); 4826 goto bus_reset; 4827 } 4828 } 4829 } 4830 splx(s); 4831 } 4832 4833 static int 4834 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4835 int lun, u_int tag, role_t role, scb_flag status, 4836 ahc_search_action action) 4837 { 4838 struct scb *scbp; 4839 u_int8_t qinpos; 4840 u_int8_t qintail; 4841 int found; 4842 4843 qinpos = ahc_inb(ahc, QINPOS); 4844 qintail = ahc->qinfifonext; 4845 found = 0; 4846 4847 /* 4848 * Start with an empty queue. Entries that are not chosen 4849 * for removal will be re-added to the queue as we go. 4850 */ 4851 ahc->qinfifonext = qinpos; 4852 4853 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4854 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4855 4856 while (qinpos != qintail) { 4857 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4858 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4859 /* 4860 * We found an scb that needs to be removed. 4861 */ 4862 switch (action) { 4863 case SEARCH_COMPLETE: 4864 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4865 scbp->flags |= status; 4866 scbp->xs->error = XS_NOERROR; 4867 } 4868 ahc_freeze_ccb(scbp); 4869 ahc_done(ahc, scbp); 4870 break; 4871 case SEARCH_COUNT: 4872 ahc->qinfifo[ahc->qinfifonext++] = 4873 scbp->hscb->tag; 4874 break; 4875 case SEARCH_REMOVE: 4876 break; 4877 } 4878 found++; 4879 } else { 4880 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4881 } 4882 qinpos++; 4883 } 4884 4885 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4886 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4887 4888 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4889 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4890 } else { 4891 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4892 } 4893 4894 return (found); 4895 } 4896 4897 /* 4898 * Abort all SCBs that match the given description (target/channel/lun/tag), 4899 * setting their status to the passed in status if the status has not already 4900 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4901 * is paused before it is called. 4902 */ 4903 static int 4904 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4905 int lun, u_int tag, role_t role, int status) 4906 { 4907 struct scb *scbp; 4908 u_int active_scb; 4909 int i; 4910 int found; 4911 4912 /* restore this when we're done */ 4913 active_scb = ahc_inb(ahc, SCBPTR); 4914 4915 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4916 role, SCB_REQUEUE, SEARCH_COMPLETE); 4917 4918 /* 4919 * Search waiting for selection list. 4920 */ 4921 { 4922 u_int8_t next, prev; 4923 4924 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4925 prev = SCB_LIST_NULL; 4926 4927 while (next != SCB_LIST_NULL) { 4928 u_int8_t scb_index; 4929 4930 ahc_outb(ahc, SCBPTR, next); 4931 scb_index = ahc_inb(ahc, SCB_TAG); 4932 if (scb_index >= ahc->scb_data->numscbs) { 4933 panic("Waiting List inconsistency. " 4934 "SCB index == %d, yet numscbs == %d.", 4935 scb_index, ahc->scb_data->numscbs); 4936 } 4937 scbp = &ahc->scb_data->scbarray[scb_index]; 4938 if (ahc_match_scb(scbp, target, channel, 4939 lun, SCB_LIST_NULL, role)) { 4940 4941 next = ahc_abort_wscb(ahc, next, prev); 4942 } else { 4943 4944 prev = next; 4945 next = ahc_inb(ahc, SCB_NEXT); 4946 } 4947 } 4948 } 4949 /* 4950 * Go through the disconnected list and remove any entries we 4951 * have queued for completion, 0'ing their control byte too. 4952 * We save the active SCB and restore it ourselves, so there 4953 * is no reason for this search to restore it too. 4954 */ 4955 ahc_search_disc_list(ahc, target, channel, lun, tag, 4956 /*stop_on_first*/FALSE, /*remove*/TRUE, 4957 /*save_state*/FALSE); 4958 4959 /* 4960 * Go through the hardware SCB array looking for commands that 4961 * were active but not on any list. 4962 */ 4963 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4964 u_int scbid; 4965 4966 ahc_outb(ahc, SCBPTR, i); 4967 scbid = ahc_inb(ahc, SCB_TAG); 4968 scbp = &ahc->scb_data->scbarray[scbid]; 4969 if (scbid < ahc->scb_data->numscbs 4970 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4971 ahc_add_curscb_to_free_list(ahc); 4972 } 4973 4974 /* 4975 * Go through the pending CCB list and look for 4976 * commands for this target that are still active. 4977 * These are other tagged commands that were 4978 * disconnected when the reset occurred. 4979 */ 4980 { 4981 struct scb *scb; 4982 4983 scb = ahc->pending_ccbs.lh_first; 4984 while (scb != NULL) { 4985 scbp = scb; 4986 scb = scb->plinks.le_next; 4987 if (ahc_match_scb(scbp, target, channel, 4988 lun, tag, role)) { 4989 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4990 ahcsetccbstatus(scbp->xs, status); 4991 ahc_freeze_ccb(scbp); 4992 ahc_done(ahc, scbp); 4993 found++; 4994 } 4995 } 4996 } 4997 ahc_outb(ahc, SCBPTR, active_scb); 4998 return found; 4999 } 5000 5001 static int 5002 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5003 int lun, u_int tag, int stop_on_first, int remove, 5004 int save_state) 5005 { 5006 struct scb *scbp; 5007 u_int next; 5008 u_int prev; 5009 u_int count; 5010 u_int active_scb; 5011 5012 count = 0; 5013 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5014 prev = SCB_LIST_NULL; 5015 5016 if (save_state) { 5017 /* restore this when we're done */ 5018 active_scb = ahc_inb(ahc, SCBPTR); 5019 } else 5020 /* Silence compiler */ 5021 active_scb = SCB_LIST_NULL; 5022 5023 while (next != SCB_LIST_NULL) { 5024 u_int scb_index; 5025 5026 ahc_outb(ahc, SCBPTR, next); 5027 scb_index = ahc_inb(ahc, SCB_TAG); 5028 if (scb_index >= ahc->scb_data->numscbs) { 5029 panic("Disconnected List inconsistency. " 5030 "SCB index == %d, yet numscbs == %d.", 5031 scb_index, ahc->scb_data->numscbs); 5032 } 5033 scbp = &ahc->scb_data->scbarray[scb_index]; 5034 if (ahc_match_scb(scbp, target, channel, lun, 5035 tag, ROLE_INITIATOR)) { 5036 count++; 5037 if (remove) { 5038 next = 5039 ahc_rem_scb_from_disc_list(ahc, prev, next); 5040 } else { 5041 prev = next; 5042 next = ahc_inb(ahc, SCB_NEXT); 5043 } 5044 if (stop_on_first) 5045 break; 5046 } else { 5047 prev = next; 5048 next = ahc_inb(ahc, SCB_NEXT); 5049 } 5050 } 5051 if (save_state) 5052 ahc_outb(ahc, SCBPTR, active_scb); 5053 return (count); 5054 } 5055 5056 static u_int 5057 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5058 { 5059 u_int next; 5060 5061 ahc_outb(ahc, SCBPTR, scbptr); 5062 next = ahc_inb(ahc, SCB_NEXT); 5063 5064 ahc_outb(ahc, SCB_CONTROL, 0); 5065 5066 ahc_add_curscb_to_free_list(ahc); 5067 5068 if (prev != SCB_LIST_NULL) { 5069 ahc_outb(ahc, SCBPTR, prev); 5070 ahc_outb(ahc, SCB_NEXT, next); 5071 } else 5072 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5073 5074 return (next); 5075 } 5076 5077 static void 5078 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5079 { 5080 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5081 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5082 5083 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5084 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5085 } 5086 5087 /* 5088 * Manipulate the waiting for selection list and return the 5089 * scb that follows the one that we remove. 5090 */ 5091 static u_int 5092 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5093 { 5094 u_int curscb, next; 5095 5096 /* 5097 * Select the SCB we want to abort and 5098 * pull the next pointer out of it. 5099 */ 5100 curscb = ahc_inb(ahc, SCBPTR); 5101 ahc_outb(ahc, SCBPTR, scbpos); 5102 next = ahc_inb(ahc, SCB_NEXT); 5103 5104 /* Clear the necessary fields */ 5105 ahc_outb(ahc, SCB_CONTROL, 0); 5106 5107 ahc_add_curscb_to_free_list(ahc); 5108 5109 /* update the waiting list */ 5110 if (prev == SCB_LIST_NULL) { 5111 /* First in the list */ 5112 ahc_outb(ahc, WAITING_SCBH, next); 5113 5114 /* 5115 * Ensure we aren't attempting to perform 5116 * selection for this entry. 5117 */ 5118 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5119 } else { 5120 /* 5121 * Select the scb that pointed to us 5122 * and update its next pointer. 5123 */ 5124 ahc_outb(ahc, SCBPTR, prev); 5125 ahc_outb(ahc, SCB_NEXT, next); 5126 } 5127 5128 /* 5129 * Point us back at the original scb position. 5130 */ 5131 ahc_outb(ahc, SCBPTR, curscb); 5132 return next; 5133 } 5134 5135 static void 5136 ahc_clear_intstat(struct ahc_softc *ahc) 5137 { 5138 /* Clear any interrupt conditions this may have caused */ 5139 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5140 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5141 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5142 CLRREQINIT); 5143 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5144 } 5145 5146 static void 5147 ahc_reset_current_bus(struct ahc_softc *ahc) 5148 { 5149 u_int8_t scsiseq; 5150 5151 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5152 scsiseq = ahc_inb(ahc, SCSISEQ); 5153 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5154 DELAY(AHC_BUSRESET_DELAY); 5155 /* Turn off the bus reset */ 5156 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5157 5158 ahc_clear_intstat(ahc); 5159 5160 /* Re-enable reset interrupts */ 5161 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5162 } 5163 5164 static int 5165 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5166 { 5167 u_int initiator, target, max_scsiid; 5168 u_int sblkctl; 5169 u_int our_id; 5170 int found; 5171 int restart_needed; 5172 char cur_channel; 5173 5174 ahc->pending_device = NULL; 5175 5176 pause_sequencer(ahc); 5177 5178 /* 5179 * Run our command complete fifos to ensure that we perform 5180 * completion processing on any commands that 'completed' 5181 * before the reset occurred. 5182 */ 5183 ahc_run_qoutfifo(ahc); 5184 5185 /* 5186 * Reset the bus if we are initiating this reset 5187 */ 5188 sblkctl = ahc_inb(ahc, SBLKCTL); 5189 cur_channel = 'A'; 5190 if ((ahc->features & AHC_TWIN) != 0 5191 && ((sblkctl & SELBUSB) != 0)) 5192 cur_channel = 'B'; 5193 if (cur_channel != channel) { 5194 /* Case 1: Command for another bus is active 5195 * Stealthily reset the other bus without 5196 * upsetting the current bus. 5197 */ 5198 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5199 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5200 ahc_outb(ahc, SCSISEQ, 5201 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5202 if (initiate_reset) 5203 ahc_reset_current_bus(ahc); 5204 ahc_clear_intstat(ahc); 5205 ahc_outb(ahc, SBLKCTL, sblkctl); 5206 restart_needed = FALSE; 5207 } else { 5208 /* Case 2: A command from this bus is active or we're idle */ 5209 ahc_clear_msg_state(ahc); 5210 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5211 ahc_outb(ahc, SCSISEQ, 5212 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5213 if (initiate_reset) 5214 ahc_reset_current_bus(ahc); 5215 ahc_clear_intstat(ahc); 5216 5217 /* 5218 * Since we are going to restart the sequencer, avoid 5219 * a race in the sequencer that could cause corruption 5220 * of our Q pointers by starting over from index 0. 5221 */ 5222 ahc->qoutfifonext = 0; 5223 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5224 ahc_outb(ahc, SDSCB_QOFF, 0); 5225 else 5226 ahc_outb(ahc, QOUTPOS, 0); 5227 restart_needed = TRUE; 5228 } 5229 5230 /* 5231 * Clean up all the state information for the 5232 * pending transactions on this bus. 5233 */ 5234 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5235 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5236 ROLE_UNKNOWN, XS_RESET); 5237 if (channel == 'B') { 5238 our_id = ahc->our_id_b; 5239 } else { 5240 our_id = ahc->our_id; 5241 } 5242 5243 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5244 5245 /* 5246 * Revert to async/narrow transfers until we renegotiate. 5247 */ 5248 for (target = 0; target <= max_scsiid; target++) { 5249 5250 if (ahc->enabled_targets[target] == NULL) 5251 continue; 5252 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5253 struct ahc_devinfo devinfo; 5254 5255 ahc_compile_devinfo(&devinfo, target, initiator, 5256 AHC_LUN_WILDCARD, 5257 channel, ROLE_UNKNOWN); 5258 ahc_set_width(ahc, &devinfo, 5259 MSG_EXT_WDTR_BUS_8_BIT, 5260 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5261 ahc_set_syncrate(ahc, &devinfo, 5262 /*syncrate*/NULL, /*period*/0, 5263 /*offset*/0, AHC_TRANS_CUR, 5264 /*paused*/TRUE, FALSE); 5265 ahc_update_xfer_mode(ahc, &devinfo); 5266 } 5267 } 5268 5269 if (restart_needed) 5270 restart_sequencer(ahc); 5271 else 5272 unpause_sequencer(ahc); 5273 return found; 5274 } 5275 5276 static int 5277 ahc_match_scb(struct scb *scb, int target, char channel, 5278 int lun, u_int tag, role_t role) 5279 { 5280 int targ = SCB_TARGET(scb); 5281 char chan = SCB_CHANNEL(scb); 5282 int slun = SCB_LUN(scb); 5283 int match; 5284 5285 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5286 if (match != 0) 5287 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5288 if (match != 0) 5289 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5290 5291 return match; 5292 } 5293 5294 static void 5295 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5296 { 5297 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5298 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5299 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5300 ahc->msgout_buf[ahc->msgout_index++] = period; 5301 ahc->msgout_buf[ahc->msgout_index++] = offset; 5302 ahc->msgout_len += 5; 5303 } 5304 5305 static void 5306 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5307 { 5308 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5309 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5310 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5311 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5312 ahc->msgout_len += 4; 5313 } 5314 5315 static void 5316 ahc_calc_residual(struct scb *scb) 5317 { 5318 struct hardware_scb *hscb; 5319 5320 hscb = scb->hscb; 5321 5322 /* 5323 * If the disconnected flag is still set, this is bogus 5324 * residual information left over from a sequencer 5325 * pagin/pageout, so ignore this case. 5326 */ 5327 if ((scb->hscb->control & DISCONNECTED) == 0) { 5328 u_int32_t resid; 5329 int resid_sgs; 5330 int sg; 5331 5332 /* 5333 * Remainder of the SG where the transfer 5334 * stopped. 5335 */ 5336 resid = (hscb->residual_data_count[2] << 16) 5337 | (hscb->residual_data_count[1] <<8) 5338 | (hscb->residual_data_count[0]); 5339 5340 /* 5341 * Add up the contents of all residual 5342 * SG segments that are after the SG where 5343 * the transfer stopped. 5344 */ 5345 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5346 sg = scb->sg_count - resid_sgs; 5347 while (resid_sgs > 0) { 5348 5349 resid += le32toh(scb->sg_list[sg].len); 5350 sg++; 5351 resid_sgs--; 5352 } 5353 scb->xs->resid = resid; 5354 } 5355 5356 /* 5357 * Clean out the residual information in this SCB for its 5358 * next consumer. 5359 */ 5360 hscb->residual_SG_count = 0; 5361 5362 #ifdef AHC_DEBUG 5363 if (ahc_debug & AHC_SHOWMISC) { 5364 scsipi_printaddr(scb->xs->xs_periph); 5365 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5366 } 5367 #endif 5368 } 5369 5370 static void 5371 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5372 { 5373 struct scb *scb; 5374 int pending_ccb_count; 5375 int i; 5376 u_int saved_scbptr; 5377 5378 /* 5379 * Traverse the pending SCB list and ensure that all of the 5380 * SCBs there have the proper settings. 5381 */ 5382 scb = LIST_FIRST(&ahc->pending_ccbs); 5383 pending_ccb_count = 0; 5384 while (scb != NULL) { 5385 struct ahc_devinfo devinfo; 5386 struct scsipi_xfer *xs; 5387 struct scb *pending_scb; 5388 struct hardware_scb *pending_hscb; 5389 struct ahc_initiator_tinfo *tinfo; 5390 struct tmode_tstate *tstate; 5391 u_int our_id, remote_id; 5392 5393 xs = scb->xs; 5394 pending_scb = scb; 5395 pending_hscb = pending_scb->hscb; 5396 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5397 ? ahc->our_id_b : ahc->our_id; 5398 remote_id = xs->xs_periph->periph_target; 5399 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5400 SCB_LUN(pending_scb), 5401 SCB_CHANNEL(pending_scb), 5402 ROLE_UNKNOWN); 5403 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5404 our_id, remote_id, &tstate); 5405 pending_hscb->control &= ~ULTRAENB; 5406 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5407 pending_hscb->control |= ULTRAENB; 5408 pending_hscb->scsirate = tinfo->scsirate; 5409 pending_hscb->scsioffset = tinfo->current.offset; 5410 pending_ccb_count++; 5411 scb = LIST_NEXT(scb, plinks); 5412 } 5413 5414 if (pending_ccb_count == 0) 5415 return; 5416 5417 saved_scbptr = ahc_inb(ahc, SCBPTR); 5418 /* Ensure that the hscbs down on the card match the new information */ 5419 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5420 u_int scb_tag; 5421 5422 ahc_outb(ahc, SCBPTR, i); 5423 scb_tag = ahc_inb(ahc, SCB_TAG); 5424 if (scb_tag != SCB_LIST_NULL) { 5425 struct ahc_devinfo devinfo; 5426 struct scb *pending_scb; 5427 struct scsipi_xfer *xs; 5428 struct hardware_scb *pending_hscb; 5429 struct ahc_initiator_tinfo *tinfo; 5430 struct tmode_tstate *tstate; 5431 u_int our_id, remote_id; 5432 u_int control; 5433 5434 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5435 if (pending_scb->flags == SCB_FREE) 5436 continue; 5437 pending_hscb = pending_scb->hscb; 5438 xs = pending_scb->xs; 5439 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5440 ? ahc->our_id_b : ahc->our_id; 5441 remote_id = xs->xs_periph->periph_target; 5442 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5443 SCB_LUN(pending_scb), 5444 SCB_CHANNEL(pending_scb), 5445 ROLE_UNKNOWN); 5446 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5447 our_id, remote_id, &tstate); 5448 control = ahc_inb(ahc, SCB_CONTROL); 5449 control &= ~ULTRAENB; 5450 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5451 control |= ULTRAENB; 5452 ahc_outb(ahc, SCB_CONTROL, control); 5453 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5454 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5455 } 5456 } 5457 ahc_outb(ahc, SCBPTR, saved_scbptr); 5458 } 5459 5460 #if UNUSED 5461 static void 5462 ahc_dump_targcmd(struct target_cmd *cmd) 5463 { 5464 u_int8_t *byte; 5465 u_int8_t *last_byte; 5466 int i; 5467 5468 byte = &cmd->initiator_channel; 5469 /* Debugging info for received commands */ 5470 last_byte = &cmd[1].initiator_channel; 5471 5472 i = 0; 5473 while (byte < last_byte) { 5474 if (i == 0) 5475 printf("\t"); 5476 printf("%#x", *byte++); 5477 i++; 5478 if (i == 8) { 5479 printf("\n"); 5480 i = 0; 5481 } else { 5482 printf(", "); 5483 } 5484 } 5485 } 5486 #endif 5487 5488 static void 5489 ahc_shutdown(void *arg) 5490 { 5491 struct ahc_softc *ahc; 5492 int i; 5493 u_int sxfrctl1_a, sxfrctl1_b; 5494 5495 ahc = (struct ahc_softc *)arg; 5496 5497 pause_sequencer(ahc); 5498 5499 /* 5500 * Preserve the value of the SXFRCTL1 register for all channels. 5501 * It contains settings that affect termination and we don't want 5502 * to disturb the integrity of the bus during shutdown in case 5503 * we are in a multi-initiator setup. 5504 */ 5505 sxfrctl1_b = 0; 5506 if ((ahc->features & AHC_TWIN) != 0) { 5507 u_int sblkctl; 5508 5509 sblkctl = ahc_inb(ahc, SBLKCTL); 5510 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5511 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5512 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5513 } 5514 5515 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5516 5517 /* This will reset most registers to 0, but not all */ 5518 ahc_reset(ahc); 5519 5520 if ((ahc->features & AHC_TWIN) != 0) { 5521 u_int sblkctl; 5522 5523 sblkctl = ahc_inb(ahc, SBLKCTL); 5524 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5525 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5526 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5527 } 5528 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5529 5530 ahc_outb(ahc, SCSISEQ, 0); 5531 ahc_outb(ahc, SXFRCTL0, 0); 5532 ahc_outb(ahc, DSPCISTATUS, 0); 5533 5534 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5535 ahc_outb(ahc, i, 0); 5536 } 5537 5538 #if defined(AHC_DEBUG) && 0 5539 static void 5540 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5541 { 5542 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5543 5544 printf("\tcurrent:\n"); 5545 printf("\t\twidth %u period %u offset %u flags %x\n", 5546 tinfo->current.width, tinfo->current.period, 5547 tinfo->current.offset, tinfo->current.ppr_flags); 5548 5549 printf("\tgoal:\n"); 5550 printf("\t\twidth %u period %u offset %u flags %x\n", 5551 tinfo->goal.width, tinfo->goal.period, 5552 tinfo->goal.offset, tinfo->goal.ppr_flags); 5553 5554 printf("\tuser:\n"); 5555 printf("\t\twidth %u period %u offset %u flags %x\n", 5556 tinfo->user.width, tinfo->user.period, 5557 tinfo->user.offset, tinfo->user.ppr_flags); 5558 } 5559 #endif 5560 5561 static int 5562 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5563 int nocmdcheck) 5564 { 5565 #ifdef AHC_NO_TAGS 5566 return 0; 5567 #else 5568 char channel; 5569 u_int our_id, target; 5570 struct tmode_tstate *tstate; 5571 struct ahc_devinfo devinfo; 5572 5573 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5574 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5575 target = xs->xs_periph->periph_target; 5576 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5577 5578 ahc_compile_devinfo(&devinfo, our_id, target, 5579 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5580 5581 return (tstate->tagenable & devinfo.target_mask); 5582 #endif 5583 } 5584
Indexes created Thu Oct 02 01:09:59 GMT 2025