aic7xxx.c revision 1.85
1 /* $NetBSD: aic7xxx.c,v 1.85 2002/01/12 16:03:11 tsutsui Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * 10 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * the GNU Public License ("GPL"). 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 38 */ 39 /* 40 * A few notes on features of the driver. 41 * 42 * SCB paging takes advantage of the fact that devices stay disconnected 43 * from the bus a relatively long time and that while they're disconnected, 44 * having the SCBs for these transactions down on the host adapter is of 45 * little use. Instead of leaving this idle SCB down on the card we copy 46 * it back up into kernel memory and reuse the SCB slot on the card to 47 * schedule another transaction. This can be a real payoff when doing random 48 * I/O to tagged queueing devices since there are more transactions active at 49 * once for the device to sort for optimal seek reduction. The algorithm goes 50 * like this... 51 * 52 * The sequencer maintains two lists of its hardware SCBs. The first is the 53 * singly linked free list which tracks all SCBs that are not currently in 54 * use. The second is the doubly linked disconnected list which holds the 55 * SCBs of transactions that are in the disconnected state sorted most 56 * recently disconnected first. When the kernel queues a transaction to 57 * the card, a hardware SCB to "house" this transaction is retrieved from 58 * either of these two lists. If the SCB came from the disconnected list, 59 * a check is made to see if any data transfer or SCB linking (more on linking 60 * in a bit) information has been changed since it was copied from the host 61 * and if so, DMAs the SCB back up before it can be used. Once a hardware 62 * SCB has been obtained, the SCB is DMAed from the host. Before any work 63 * can begin on this SCB, the sequencer must ensure that either the SCB is 64 * for a tagged transaction or the target is not already working on another 65 * non-tagged transaction. If a conflict arises in the non-tagged case, the 66 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 67 * field in that SCB to this next SCB to execute. To facilitate finding 68 * active non-tagged SCBs, the last four bytes of up to the first four hardware 69 * SCBs serve as a storage area for the currently active SCB ID for each 70 * target. 71 * 72 * When a device reconnects, a search is made of the hardware SCBs to find 73 * the SCB for this transaction. If the search fails, a hardware SCB is 74 * pulled from either the free or disconnected SCB list and the proper 75 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 76 * in the control byte of the SCB while it was disconnected, the sequencer 77 * will assert ATN and attempt to issue a message to the host. 78 * 79 * When a command completes, a check for non-zero status and residuals is 80 * made. If either of these conditions exists, the SCB is DMAed back up to 81 * the host so that it can interpret this information. Additionally, in the 82 * case of bad status, the sequencer generates a special interrupt and pauses 83 * itself. This allows the host to setup a request sense command if it 84 * chooses for this target synchronously with the error so that sense 85 * information isn't lost. 86 * 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.85 2002/01/12 16:03:11 tsutsui Exp $"); 91 92 #include "opt_ddb.h" 93 #include "opt_ahc.h" 94 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 #include <sys/buf.h> 101 #include <sys/proc.h> 102 #include <sys/scsiio.h> 103 104 #include <machine/bus.h> 105 #include <machine/intr.h> 106 107 #include <dev/scsipi/scsi_all.h> 108 #include <dev/scsipi/scsipi_all.h> 109 #include <dev/scsipi/scsi_message.h> 110 #include <dev/scsipi/scsipi_debug.h> 111 #include <dev/scsipi/scsiconf.h> 112 113 #include <uvm/uvm_extern.h> 114 115 #include <dev/ic/aic7xxxvar.h> 116 #include <dev/microcode/aic7xxx/sequencer.h> 117 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 118 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 119 120 #define ALL_CHANNELS '\0' 121 #define ALL_TARGETS_MASK 0xFFFF 122 #define INITIATOR_WILDCARD (~0) 123 124 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 125 ((periph)->periph_channel->chan_channel == 1) 126 #define SIM_CHANNEL(ahc, periph) \ 127 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 128 #define SIM_SCSI_ID(ahc, periph) \ 129 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 130 #define SCB_IS_SCSIBUS_B(scb) \ 131 (((scb)->hscb->tcl & SELBUSB) != 0) 132 #define SCB_TARGET(scb) \ 133 (((scb)->hscb->tcl & TID) >> 4) 134 #define SCB_CHANNEL(scb) \ 135 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 136 #define SCB_LUN(scb) \ 137 ((scb)->hscb->tcl & LID) 138 #define SCB_TARGET_OFFSET(scb) \ 139 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 140 #define SCB_TARGET_MASK(scb) \ 141 (0x01 << (SCB_TARGET_OFFSET(scb))) 142 #define TCL_CHANNEL(ahc, tcl) \ 143 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 144 #define TCL_SCSI_ID(ahc, tcl) \ 145 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 146 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 147 #define TCL_LUN(tcl) ((tcl) & LID) 148 149 #define XS_TCL(ahc, xs) \ 150 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 151 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 152 | ((xs)->xs_periph->periph_lun & 0x07)) 153 154 const char * const ahc_chip_names[] = 155 { 156 "NONE", 157 "aic7770", 158 "aic7850", 159 "aic7855", 160 "aic7859", 161 "aic7860", 162 "aic7870", 163 "aic7880", 164 "aic7890/91", 165 "aic7892", 166 "aic7895", 167 "aic7896/97", 168 "aic7899" 169 }; 170 171 typedef enum { 172 ROLE_UNKNOWN, 173 ROLE_INITIATOR, 174 ROLE_TARGET 175 } role_t; 176 177 struct ahc_devinfo { 178 int our_scsiid; 179 int target_offset; 180 u_int16_t target_mask; 181 u_int8_t target; 182 u_int8_t lun; 183 char channel; 184 role_t role; /* 185 * Only guaranteed to be correct if not 186 * in the busfree state. 187 */ 188 }; 189 190 typedef enum { 191 SEARCH_COMPLETE, 192 SEARCH_COUNT, 193 SEARCH_REMOVE 194 } ahc_search_action; 195 196 #ifdef AHC_DEBUG 197 static int ahc_debug = AHC_DEBUG; 198 #endif 199 200 static int ahcinitscbdata(struct ahc_softc *); 201 static void ahcfiniscbdata(struct ahc_softc *); 202 203 #if UNUSED 204 static void ahc_dump_targcmd(struct target_cmd *); 205 #endif 206 static void ahc_shutdown(void *arg); 207 static void ahc_action(struct scsipi_channel *, 208 scsipi_adapter_req_t, void *); 209 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 210 struct proc *); 211 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 212 static int ahc_poll(struct ahc_softc *, int); 213 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 214 struct scb *); 215 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 216 static void ahcallocscbs(struct ahc_softc *); 217 #if UNUSED 218 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 219 struct scb *); 220 #endif 221 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 222 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 223 char, role_t); 224 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 225 static void ahc_done(struct ahc_softc *, struct scb *); 226 static struct tmode_tstate * 227 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 228 #if UNUSED 229 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 230 #endif 231 static void ahc_handle_seqint(struct ahc_softc *, u_int); 232 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 233 static void ahc_build_transfer_msg(struct ahc_softc *, 234 struct ahc_devinfo *); 235 static void ahc_setup_initiator_msgout(struct ahc_softc *, 236 struct ahc_devinfo *, 237 struct scb *); 238 static void ahc_setup_target_msgin(struct ahc_softc *, 239 struct ahc_devinfo *); 240 static void ahc_clear_msg_state(struct ahc_softc *); 241 static void ahc_handle_message_phase(struct ahc_softc *, 242 struct scsipi_periph *); 243 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 244 245 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 246 struct ahc_devinfo *); 247 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 248 struct ahc_devinfo *); 249 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 250 int, char *, int); 251 #ifdef AHC_DUMP_SEQ 252 static void ahc_dumpseq(struct ahc_softc *); 253 #endif 254 static void ahc_loadseq(struct ahc_softc *); 255 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 256 int, int *); 257 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 258 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 259 #if defined(AHC_DEBUG) 260 static void ahc_print_scb(struct scb *); 261 #endif 262 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 263 role_t, scb_flag, ahc_search_action); 264 static int ahc_reset_channel(struct ahc_softc *, char, int); 265 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 266 role_t, int); 267 static int ahc_search_disc_list(struct ahc_softc *, int, 268 char, int, u_int, int, int, int); 269 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 270 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 271 static void ahc_clear_intstat(struct ahc_softc *); 272 static void ahc_reset_current_bus(struct ahc_softc *); 273 static const struct ahc_syncrate * 274 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 275 static const struct ahc_syncrate * 276 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 277 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 278 static void ahc_validate_offset(struct ahc_softc *, 279 const struct ahc_syncrate *, u_int *, int); 280 static void ahc_update_target_msg_request(struct ahc_softc *, 281 struct ahc_devinfo *, 282 struct ahc_initiator_tinfo *, 283 int, int); 284 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 285 const struct ahc_syncrate *, u_int, u_int, 286 u_int, int, int); 287 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 288 u_int, u_int, int, int); 289 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 290 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 291 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 292 293 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 294 295 static void ahc_calc_residual(struct scb *); 296 297 static void ahc_update_pending_syncrates(struct ahc_softc *); 298 299 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 300 301 static void ahc_timeout (void *); 302 static __inline int sequencer_paused(struct ahc_softc *); 303 static __inline void pause_sequencer(struct ahc_softc *); 304 static __inline void unpause_sequencer(struct ahc_softc *); 305 static void restart_sequencer(struct ahc_softc *); 306 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 307 308 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 309 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 310 311 static __inline void ahc_freeze_ccb(struct scb *); 312 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 313 static void ahc_run_qoutfifo(struct ahc_softc *); 314 315 static __inline struct ahc_initiator_tinfo * 316 ahc_fetch_transinfo(struct ahc_softc *, 317 char, u_int, u_int, 318 struct tmode_tstate **); 319 static void ahcfreescb(struct ahc_softc *, struct scb *); 320 static __inline struct scb *ahcgetscb(struct ahc_softc *); 321 322 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 323 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 324 int *, const char *, const char *); 325 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 326 caddr_t, bus_dma_segment_t *, int); 327 static void ahcminphys(struct buf *); 328 329 static __inline void ahc_swap_hscb(struct hardware_scb *); 330 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 331 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 332 333 #if defined(AHC_DEBUG) && 0 334 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 335 #endif 336 337 static __inline void 338 ahc_swap_hscb(struct hardware_scb *hscb) 339 { 340 hscb->SG_pointer = htole32(hscb->SG_pointer); 341 hscb->data = htole32(hscb->data); 342 hscb->datalen = htole32(hscb->datalen); 343 /* 344 * No need to swap cmdpointer; it's either 0 or set to 345 * cmdstore_busaddr, which is already swapped. 346 */ 347 } 348 349 static __inline void 350 ahc_swap_sg(struct ahc_dma_seg *sg) 351 { 352 sg->addr = htole32(sg->addr); 353 sg->len = htole32(sg->len); 354 } 355 356 static void 357 ahcminphys(bp) 358 struct buf *bp; 359 { 360 /* 361 * Even though the card can transfer up to 16megs per command 362 * we are limited by the number of segments in the dma segment 363 * list that we can hold. The worst case is that all pages are 364 * discontinuous physically, hense the "page per segment" limit 365 * enforced here. 366 */ 367 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 368 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 369 } 370 minphys(bp); 371 } 372 373 374 static __inline u_int32_t 375 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 376 { 377 return (ahc->scb_data->hscb_busaddr 378 + (sizeof(struct hardware_scb) * index)); 379 } 380 381 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 382 383 static __inline int 384 sequencer_paused(struct ahc_softc *ahc) 385 { 386 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 387 } 388 389 static __inline void 390 pause_sequencer(struct ahc_softc *ahc) 391 { 392 ahc_outb(ahc, HCNTRL, ahc->pause); 393 394 /* 395 * Since the sequencer can disable pausing in a critical section, we 396 * must loop until it actually stops. 397 */ 398 while (sequencer_paused(ahc) == 0) 399 ; 400 } 401 402 static __inline void 403 unpause_sequencer(struct ahc_softc *ahc) 404 { 405 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 406 ahc_outb(ahc, HCNTRL, ahc->unpause); 407 } 408 409 /* 410 * Restart the sequencer program from address zero 411 */ 412 static void 413 restart_sequencer(struct ahc_softc *ahc) 414 { 415 u_int i; 416 417 pause_sequencer(ahc); 418 419 /* 420 * Everytime we restart the sequencer, there 421 * is the possiblitity that we have restarted 422 * within a three instruction window where an 423 * SCB has been marked free but has not made it 424 * onto the free list. Since SCSI events(bus reset, 425 * unexpected bus free) will always freeze the 426 * sequencer, we cannot close this window. To 427 * avoid losing an SCB, we reconsitute the free 428 * list every time we restart the sequencer. 429 */ 430 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 431 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 432 433 ahc_outb(ahc, SCBPTR, i); 434 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 435 ahc_add_curscb_to_free_list(ahc); 436 } 437 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 438 unpause_sequencer(ahc); 439 } 440 441 static __inline u_int 442 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 443 { 444 u_int scbid; 445 446 scbid = ahc->untagged_scbs[tcl]; 447 if (unbusy) { 448 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 449 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 450 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 451 } 452 453 return (scbid); 454 } 455 456 static __inline void 457 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 458 { 459 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 460 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 461 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 462 } 463 464 static __inline int 465 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 466 { 467 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 468 } 469 470 static __inline void 471 ahc_freeze_ccb(struct scb *scb) 472 { 473 struct scsipi_xfer *xs = scb->xs; 474 475 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 476 scsipi_periph_freeze(xs->xs_periph, 1); 477 scb->flags |= SCB_FREEZE_QUEUE; 478 } 479 } 480 481 static __inline void 482 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 483 { 484 xs->error = status; 485 } 486 487 static __inline struct ahc_initiator_tinfo * 488 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 489 u_int remote_id, struct tmode_tstate **tstate) 490 { 491 /* 492 * Transfer data structures are stored from the perspective 493 * of the target role. Since the parameters for a connection 494 * in the initiator role to a given target are the same as 495 * when the roles are reversed, we pretend we are the target. 496 */ 497 if (channel == 'B') 498 our_id += 8; 499 *tstate = ahc->enabled_targets[our_id]; 500 return (&(*tstate)->transinfo[remote_id]); 501 } 502 503 static void 504 ahc_run_qoutfifo(struct ahc_softc *ahc) 505 { 506 struct scb *scb; 507 u_int scb_index; 508 509 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 510 256, BUS_DMASYNC_POSTREAD); 511 512 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 513 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 514 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 515 516 scb = &ahc->scb_data->scbarray[scb_index]; 517 if (scb_index >= ahc->scb_data->numscbs 518 || (scb->flags & SCB_ACTIVE) == 0) { 519 printf("%s: WARNING no command for scb %d " 520 "(cmdcmplt)\nQOUTPOS = %d\n", 521 ahc_name(ahc), scb_index, 522 ahc->qoutfifonext - 1); 523 continue; 524 } 525 526 /* 527 * Save off the residual 528 * if there is one. 529 */ 530 if (scb->hscb->residual_SG_count != 0) 531 ahc_calc_residual(scb); 532 else 533 scb->xs->resid = 0; 534 #ifdef AHC_DEBUG 535 if (ahc_debug & AHC_SHOWSCBS) { 536 scsipi_printaddr(scb->xs->xs_periph); 537 printf("run_qoutfifo: SCB %x complete\n", 538 scb->hscb->tag); 539 } 540 #endif 541 ahc_done(ahc, scb); 542 } 543 } 544 545 546 /* 547 * An scb (and hence an scb entry on the board) is put onto the 548 * free list. 549 */ 550 static void 551 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 552 { 553 struct hardware_scb *hscb; 554 int opri; 555 556 hscb = scb->hscb; 557 558 #ifdef AHC_DEBUG 559 if (ahc_debug & AHC_SHOWSCBALLOC) 560 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 561 #endif 562 563 opri = splbio(); 564 565 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 566 (scb->flags & SCB_RECOVERY_SCB) != 0) { 567 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 568 scsipi_channel_thaw(&ahc->sc_channel, 1); 569 if (ahc->features & AHC_TWIN) 570 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 571 } 572 573 /* Clean up for the next user */ 574 scb->flags = SCB_FREE; 575 hscb->control = 0; 576 hscb->status = 0; 577 578 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 579 580 splx(opri); 581 } 582 583 /* 584 * Get a free scb, either one already assigned to a hardware slot 585 * on the adapter or one that will require an SCB to be paged out before 586 * use. If there are none, see if we can allocate a new SCB. Otherwise 587 * either return an error or sleep. 588 */ 589 static __inline struct scb * 590 ahcgetscb(struct ahc_softc *ahc) 591 { 592 struct scb *scbp; 593 int opri;; 594 595 opri = splbio(); 596 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 597 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 598 } else { 599 ahcallocscbs(ahc); 600 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 601 if (scbp != NULL) 602 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 603 } 604 605 splx(opri); 606 607 #ifdef AHC_DEBUG 608 if (ahc_debug & AHC_SHOWSCBALLOC) { 609 if (scbp != NULL) 610 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 611 scbp->hscb->tag); 612 else 613 printf("%s: failed to allocate new SCB\n", 614 ahc_name(ahc)); 615 } 616 #endif 617 618 return (scbp); 619 } 620 621 static int 622 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 623 bus_dma_tag_t tag; 624 int size; 625 int flags; 626 bus_dmamap_t *mapp; 627 caddr_t *vaddr; 628 bus_addr_t *baddr; 629 bus_dma_segment_t *seg; 630 int *nseg; 631 const char *myname, *what; 632 { 633 int error, level = 0; 634 635 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 636 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 637 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 638 myname, what, error); 639 goto out; 640 } 641 level++; 642 643 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 644 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 645 printf("%s: failed to map DMA mem for %s, error = %d\n", 646 myname, what, error); 647 goto out; 648 } 649 level++; 650 651 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 652 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 653 printf("%s: failed to create DMA map for %s, error = %d\n", 654 myname, what, error); 655 goto out; 656 } 657 level++; 658 659 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 660 BUS_DMA_NOWAIT)) != 0) { 661 printf("%s: failed to load DMA map for %s, error = %d\n", 662 myname, what, error); 663 goto out; 664 } 665 666 *baddr = (*mapp)->dm_segs[0].ds_addr; 667 668 #ifdef AHC_DEBUG 669 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 670 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 671 *nseg, size); 672 #endif 673 674 return 0; 675 out: 676 switch (level) { 677 case 3: 678 bus_dmamap_destroy(tag, *mapp); 679 /* FALLTHROUGH */ 680 case 2: 681 bus_dmamem_unmap(tag, *vaddr, size); 682 /* FALLTHROUGH */ 683 case 1: 684 bus_dmamem_free(tag, seg, *nseg); 685 break; 686 default: 687 break; 688 } 689 690 return error; 691 } 692 693 static void 694 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 695 bus_dma_tag_t tag; 696 int size; 697 bus_dmamap_t map; 698 caddr_t vaddr; 699 bus_dma_segment_t *seg; 700 int nseg; 701 { 702 703 bus_dmamap_unload(tag, map); 704 bus_dmamap_destroy(tag, map); 705 bus_dmamem_unmap(tag, vaddr, size); 706 bus_dmamem_free(tag, seg, nseg); 707 } 708 709 char * 710 ahc_name(struct ahc_softc *ahc) 711 { 712 return (ahc->sc_dev.dv_xname); 713 } 714 715 #ifdef AHC_DEBUG 716 static void 717 ahc_print_scb(struct scb *scb) 718 { 719 struct hardware_scb *hscb = scb->hscb; 720 721 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 722 scb, 723 hscb->tag, 724 hscb->control, 725 hscb->tcl, 726 hscb->cmdlen, 727 (unsigned long)le32toh(hscb->cmdpointer)); 728 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 729 le32toh(hscb->datalen), 730 (unsigned long)(le32toh(hscb->data)), 731 hscb->SG_count, 732 (unsigned long)(le32toh(hscb->SG_pointer))); 733 printf(" sg_addr:%lx sg_len:%lu\n", 734 (unsigned long)(le32toh(scb->sg_list[0].addr)), 735 (unsigned long)(le32toh(scb->sg_list[0].len))); 736 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 737 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 738 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 739 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 740 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 741 } 742 #endif 743 744 static const struct { 745 u_int8_t errno; 746 const char *errmesg; 747 } hard_error[] = { 748 { ILLHADDR, "Illegal Host Access" }, 749 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 750 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 751 { SQPARERR, "Sequencer Parity Error" }, 752 { DPARERR, "Data-path Parity Error" }, 753 { MPARERR, "Scratch or SCB Memory Parity Error" }, 754 { PCIERRSTAT, "PCI Error detected" }, 755 { CIOPARERR, "CIOBUS Parity Error" }, 756 }; 757 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 758 759 static const struct { 760 u_int8_t phase; 761 u_int8_t mesg_out; /* Message response to parity errors */ 762 const char *phasemsg; 763 } phase_table[] = { 764 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 765 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 766 { P_COMMAND, MSG_NOOP, "in Command phase" }, 767 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 768 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 769 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 770 { P_BUSFREE, MSG_NOOP, "while idle" }, 771 { 0, MSG_NOOP, "in unknown phase" } 772 }; 773 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 774 775 /* 776 * Valid SCSIRATE values. (p. 3-17) 777 * Provides a mapping of transfer periods in ns to the proper value to 778 * stick in the scsiscfr reg to use that transfer rate. 779 */ 780 #define AHC_SYNCRATE_DT 0 781 #define AHC_SYNCRATE_ULTRA2 1 782 #define AHC_SYNCRATE_ULTRA 3 783 #define AHC_SYNCRATE_FAST 6 784 static const struct ahc_syncrate ahc_syncrates[] = { 785 /* ultra2 fast/ultra period rate */ 786 { 0x42, 0x000, 9, "80.0" }, 787 { 0x03, 0x000, 10, "40.0" }, 788 { 0x04, 0x000, 11, "33.0" }, 789 { 0x05, 0x100, 12, "20.0" }, 790 { 0x06, 0x110, 15, "16.0" }, 791 { 0x07, 0x120, 18, "13.4" }, 792 { 0x08, 0x000, 25, "10.0" }, 793 { 0x19, 0x010, 31, "8.0" }, 794 { 0x1a, 0x020, 37, "6.67" }, 795 { 0x1b, 0x030, 43, "5.7" }, 796 { 0x1c, 0x040, 50, "5.0" }, 797 { 0x00, 0x050, 56, "4.4" }, 798 { 0x00, 0x060, 62, "4.0" }, 799 { 0x00, 0x070, 68, "3.6" }, 800 { 0x00, 0x000, 0, NULL } 801 }; 802 803 /* 804 * Allocate a controller structure for a new device and initialize it. 805 */ 806 int 807 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 808 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 809 ahc_flag flags) 810 { 811 struct scb_data *scb_data; 812 813 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT|M_ZERO); 814 if (scb_data == NULL) { 815 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 816 return -1; 817 } 818 LIST_INIT(&ahc->pending_ccbs); 819 ahc->tag = st; 820 ahc->bsh = sh; 821 ahc->parent_dmat = parent_dmat; 822 ahc->chip = chip; 823 ahc->features = features; 824 ahc->flags = flags; 825 ahc->scb_data = scb_data; 826 827 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 828 /* The IRQMS bit is only valid on VL and EISA chips */ 829 if ((ahc->chip & AHC_PCI) != 0) 830 ahc->unpause &= ~IRQMS; 831 ahc->pause = ahc->unpause | PAUSE; 832 return (0); 833 } 834 835 void 836 ahc_free(ahc) 837 struct ahc_softc *ahc; 838 { 839 ahcfiniscbdata(ahc); 840 if (ahc->init_level != 0) 841 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 842 ahc->shared_data_dmamap, ahc->qoutfifo, 843 &ahc->shared_data_seg, ahc->shared_data_nseg); 844 845 if (ahc->scb_data != NULL) 846 free(ahc->scb_data, M_DEVBUF); 847 if (ahc->bus_data != NULL) 848 free(ahc->bus_data, M_DEVBUF); 849 return; 850 } 851 852 static int 853 ahcinitscbdata(struct ahc_softc *ahc) 854 { 855 struct scb_data *scb_data; 856 int i; 857 858 scb_data = ahc->scb_data; 859 SLIST_INIT(&scb_data->free_scbs); 860 SLIST_INIT(&scb_data->sg_maps); 861 862 /* Allocate SCB resources */ 863 scb_data->scbarray = 864 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 865 M_DEVBUF, M_NOWAIT|M_ZERO); 866 if (scb_data->scbarray == NULL) 867 return (ENOMEM); 868 869 /* Determine the number of hardware SCBs and initialize them */ 870 871 scb_data->maxhscbs = ahc_probe_scbs(ahc); 872 /* SCB 0 heads the free list */ 873 ahc_outb(ahc, FREE_SCBH, 0); 874 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 875 ahc_outb(ahc, SCBPTR, i); 876 877 /* Clear the control byte. */ 878 ahc_outb(ahc, SCB_CONTROL, 0); 879 880 /* Set the next pointer */ 881 ahc_outb(ahc, SCB_NEXT, i+1); 882 883 /* Make the tag number invalid */ 884 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 885 } 886 887 /* Make sure that the last SCB terminates the free list */ 888 ahc_outb(ahc, SCBPTR, i-1); 889 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 890 891 /* Ensure we clear the 0 SCB's control byte. */ 892 ahc_outb(ahc, SCBPTR, 0); 893 ahc_outb(ahc, SCB_CONTROL, 0); 894 895 scb_data->maxhscbs = i; 896 897 if (ahc->scb_data->maxhscbs == 0) 898 panic("%s: No SCB space found", ahc_name(ahc)); 899 900 /* 901 * Create our DMA tags. These tags define the kinds of device 902 * accessible memory allocations and memory mappings we will 903 * need to perform during normal operation. 904 * 905 * Unless we need to further restrict the allocation, we rely 906 * on the restrictions of the parent dmat, hence the common 907 * use of MAXADDR and MAXSIZE. 908 */ 909 910 if (ahc_createdmamem(ahc->parent_dmat, 911 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 912 &scb_data->hscb_dmamap, 913 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 914 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 915 "hardware SCB structures") < 0) 916 goto error_exit; 917 918 scb_data->init_level++; 919 920 if (ahc_createdmamem(ahc->parent_dmat, 921 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 922 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 923 &scb_data->sense_busaddr, &scb_data->sense_seg, 924 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 925 goto error_exit; 926 927 scb_data->init_level++; 928 929 /* Perform initial CCB allocation */ 930 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 931 ahcallocscbs(ahc); 932 933 if (scb_data->numscbs == 0) { 934 printf("%s: ahc_init_scb_data - " 935 "Unable to allocate initial scbs\n", 936 ahc_name(ahc)); 937 goto error_exit; 938 } 939 940 scb_data->init_level++; 941 942 /* 943 * Note that we were successfull 944 */ 945 return 0; 946 947 error_exit: 948 949 return ENOMEM; 950 } 951 952 static void 953 ahcfiniscbdata(struct ahc_softc *ahc) 954 { 955 struct scb_data *scb_data; 956 957 scb_data = ahc->scb_data; 958 959 switch (scb_data->init_level) { 960 default: 961 case 3: 962 { 963 struct sg_map_node *sg_map; 964 965 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 966 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 967 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 968 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 969 &sg_map->sg_dmasegs, sg_map->sg_nseg); 970 free(sg_map, M_DEVBUF); 971 } 972 } 973 /*FALLTHROUGH*/ 974 case 2: 975 ahc_freedmamem(ahc->parent_dmat, 976 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 977 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 978 &scb_data->sense_seg, scb_data->sense_nseg); 979 /*FALLTHROUGH*/ 980 case 1: 981 ahc_freedmamem(ahc->parent_dmat, 982 AHC_SCB_MAX * sizeof(struct hardware_scb), 983 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 984 &scb_data->hscb_seg, scb_data->hscb_nseg); 985 /*FALLTHROUGH*/ 986 } 987 if (scb_data->scbarray != NULL) 988 free(scb_data->scbarray, M_DEVBUF); 989 } 990 991 int 992 ahc_reset(struct ahc_softc *ahc) 993 { 994 u_int sblkctl; 995 int wait; 996 997 #ifdef AHC_DUMP_SEQ 998 if (ahc->init_level == 0) 999 ahc_dumpseq(ahc); 1000 #endif 1001 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1002 /* 1003 * Ensure that the reset has finished 1004 */ 1005 wait = 1000; 1006 do { 1007 DELAY(1000); 1008 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1009 1010 if (wait == 0) { 1011 printf("%s: WARNING - Failed chip reset! " 1012 "Trying to initialize anyway.\n", ahc_name(ahc)); 1013 } 1014 ahc_outb(ahc, HCNTRL, ahc->pause); 1015 1016 /* Determine channel configuration */ 1017 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1018 /* No Twin Channel PCI cards */ 1019 if ((ahc->chip & AHC_PCI) != 0) 1020 sblkctl &= ~SELBUSB; 1021 switch (sblkctl) { 1022 case 0: 1023 /* Single Narrow Channel */ 1024 break; 1025 case 2: 1026 /* Wide Channel */ 1027 ahc->features |= AHC_WIDE; 1028 break; 1029 case 8: 1030 /* Twin Channel */ 1031 ahc->features |= AHC_TWIN; 1032 break; 1033 default: 1034 printf(" Unsupported adapter type. Ignoring\n"); 1035 return(-1); 1036 } 1037 1038 return (0); 1039 } 1040 1041 /* 1042 * Called when we have an active connection to a target on the bus, 1043 * this function finds the nearest syncrate to the input period limited 1044 * by the capabilities of the bus connectivity of the target. 1045 */ 1046 static const struct ahc_syncrate * 1047 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1048 u_int maxsync; 1049 1050 if ((ahc->features & AHC_ULTRA2) != 0) { 1051 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1052 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1053 maxsync = AHC_SYNCRATE_ULTRA2; 1054 } else { 1055 maxsync = AHC_SYNCRATE_ULTRA; 1056 } 1057 } else if ((ahc->features & AHC_ULTRA) != 0) { 1058 maxsync = AHC_SYNCRATE_ULTRA; 1059 } else { 1060 maxsync = AHC_SYNCRATE_FAST; 1061 } 1062 return (ahc_find_syncrate(ahc, period, maxsync)); 1063 } 1064 1065 /* 1066 * Look up the valid period to SCSIRATE conversion in our table. 1067 * Return the period and offset that should be sent to the target 1068 * if this was the beginning of an SDTR. 1069 */ 1070 static const struct ahc_syncrate * 1071 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1072 { 1073 const struct ahc_syncrate *syncrate; 1074 1075 syncrate = &ahc_syncrates[maxsync]; 1076 while ((syncrate->rate != NULL) 1077 && ((ahc->features & AHC_ULTRA2) == 0 1078 || (syncrate->sxfr_u2 != 0))) { 1079 1080 if (*period <= syncrate->period) { 1081 /* 1082 * When responding to a target that requests 1083 * sync, the requested rate may fall between 1084 * two rates that we can output, but still be 1085 * a rate that we can receive. Because of this, 1086 * we want to respond to the target with 1087 * the same rate that it sent to us even 1088 * if the period we use to send data to it 1089 * is lower. Only lower the response period 1090 * if we must. 1091 */ 1092 if (syncrate == &ahc_syncrates[maxsync]) 1093 *period = syncrate->period; 1094 break; 1095 } 1096 syncrate++; 1097 } 1098 1099 if ((*period == 0) 1100 || (syncrate->rate == NULL) 1101 || ((ahc->features & AHC_ULTRA2) != 0 1102 && (syncrate->sxfr_u2 == 0))) { 1103 /* Use asynchronous transfers. */ 1104 *period = 0; 1105 syncrate = NULL; 1106 } 1107 return (syncrate); 1108 } 1109 1110 static u_int 1111 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1112 { 1113 const struct ahc_syncrate *syncrate; 1114 1115 if ((ahc->features & AHC_ULTRA2) != 0) 1116 scsirate &= SXFR_ULTRA2; 1117 else 1118 scsirate &= SXFR; 1119 1120 syncrate = &ahc_syncrates[maxsync]; 1121 while (syncrate->rate != NULL) { 1122 1123 if ((ahc->features & AHC_ULTRA2) != 0) { 1124 if (syncrate->sxfr_u2 == 0) 1125 break; 1126 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1127 return (syncrate->period); 1128 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1129 return (syncrate->period); 1130 } 1131 syncrate++; 1132 } 1133 return (0); /* async */ 1134 } 1135 1136 static void 1137 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1138 u_int *offset, int wide) 1139 { 1140 u_int maxoffset; 1141 1142 /* Limit offset to what we can do */ 1143 if (syncrate == NULL) { 1144 maxoffset = 0; 1145 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1146 maxoffset = MAX_OFFSET_ULTRA2; 1147 } else { 1148 if (wide) 1149 maxoffset = MAX_OFFSET_16BIT; 1150 else 1151 maxoffset = MAX_OFFSET_8BIT; 1152 } 1153 *offset = MIN(*offset, maxoffset); 1154 } 1155 1156 static void 1157 ahc_update_target_msg_request(struct ahc_softc *ahc, 1158 struct ahc_devinfo *devinfo, 1159 struct ahc_initiator_tinfo *tinfo, 1160 int force, int paused) 1161 { 1162 u_int targ_msg_req_orig; 1163 1164 targ_msg_req_orig = ahc->targ_msg_req; 1165 if (tinfo->current.period != tinfo->goal.period 1166 || tinfo->current.width != tinfo->goal.width 1167 || tinfo->current.offset != tinfo->goal.offset 1168 || (force 1169 && (tinfo->goal.period != 0 1170 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1171 ahc->targ_msg_req |= devinfo->target_mask; 1172 } else { 1173 ahc->targ_msg_req &= ~devinfo->target_mask; 1174 } 1175 1176 if (ahc->targ_msg_req != targ_msg_req_orig) { 1177 /* Update the message request bit for this target */ 1178 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1179 if (paused) { 1180 ahc_outb(ahc, TARGET_MSG_REQUEST, 1181 ahc->targ_msg_req & 0xFF); 1182 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1183 (ahc->targ_msg_req >> 8) & 0xFF); 1184 } else { 1185 ahc_outb(ahc, HS_MAILBOX, 1186 0x01 << HOST_MAILBOX_SHIFT); 1187 } 1188 } else { 1189 if (!paused) 1190 pause_sequencer(ahc); 1191 1192 ahc_outb(ahc, TARGET_MSG_REQUEST, 1193 ahc->targ_msg_req & 0xFF); 1194 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1195 (ahc->targ_msg_req >> 8) & 0xFF); 1196 1197 if (!paused) 1198 unpause_sequencer(ahc); 1199 } 1200 } 1201 } 1202 1203 static void 1204 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1205 const struct ahc_syncrate *syncrate, 1206 u_int period, u_int offset, u_int type, int paused, int done) 1207 { 1208 struct ahc_initiator_tinfo *tinfo; 1209 struct tmode_tstate *tstate; 1210 u_int old_period; 1211 u_int old_offset; 1212 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1213 1214 if (syncrate == NULL) { 1215 period = 0; 1216 offset = 0; 1217 } 1218 1219 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1220 devinfo->target, &tstate); 1221 old_period = tinfo->current.period; 1222 old_offset = tinfo->current.offset; 1223 1224 if ((type & AHC_TRANS_CUR) != 0 1225 && (old_period != period || old_offset != offset)) { 1226 u_int scsirate; 1227 1228 scsirate = tinfo->scsirate; 1229 if ((ahc->features & AHC_ULTRA2) != 0) { 1230 1231 /* XXX */ 1232 /* Force single edge until DT is fully implemented */ 1233 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1234 if (syncrate != NULL) 1235 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1236 1237 if (active) 1238 ahc_outb(ahc, SCSIOFFSET, offset); 1239 } else { 1240 1241 scsirate &= ~(SXFR|SOFS); 1242 /* 1243 * Ensure Ultra mode is set properly for 1244 * this target. 1245 */ 1246 tstate->ultraenb &= ~devinfo->target_mask; 1247 if (syncrate != NULL) { 1248 if (syncrate->sxfr & ULTRA_SXFR) { 1249 tstate->ultraenb |= 1250 devinfo->target_mask; 1251 } 1252 scsirate |= syncrate->sxfr & SXFR; 1253 scsirate |= offset & SOFS; 1254 } 1255 if (active) { 1256 u_int sxfrctl0; 1257 1258 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1259 sxfrctl0 &= ~FAST20; 1260 if (tstate->ultraenb & devinfo->target_mask) 1261 sxfrctl0 |= FAST20; 1262 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1263 } 1264 } 1265 if (active) 1266 ahc_outb(ahc, SCSIRATE, scsirate); 1267 1268 tinfo->scsirate = scsirate; 1269 tinfo->current.period = period; 1270 tinfo->current.offset = offset; 1271 1272 /* Update the syncrates in any pending scbs */ 1273 ahc_update_pending_syncrates(ahc); 1274 } 1275 1276 if ((type & AHC_TRANS_GOAL) != 0) { 1277 tinfo->goal.period = period; 1278 tinfo->goal.offset = offset; 1279 } 1280 1281 if ((type & AHC_TRANS_USER) != 0) { 1282 tinfo->user.period = period; 1283 tinfo->user.offset = offset; 1284 } 1285 1286 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1287 /*force*/FALSE, 1288 paused); 1289 } 1290 1291 static void 1292 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1293 u_int width, u_int type, int paused, int done) 1294 { 1295 struct ahc_initiator_tinfo *tinfo; 1296 struct tmode_tstate *tstate; 1297 u_int oldwidth; 1298 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1299 1300 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1301 devinfo->target, &tstate); 1302 oldwidth = tinfo->current.width; 1303 1304 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1305 u_int scsirate; 1306 1307 scsirate = tinfo->scsirate; 1308 scsirate &= ~WIDEXFER; 1309 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1310 scsirate |= WIDEXFER; 1311 1312 tinfo->scsirate = scsirate; 1313 1314 if (active) 1315 ahc_outb(ahc, SCSIRATE, scsirate); 1316 1317 tinfo->current.width = width; 1318 } 1319 1320 if ((type & AHC_TRANS_GOAL) != 0) 1321 tinfo->goal.width = width; 1322 if ((type & AHC_TRANS_USER) != 0) 1323 tinfo->user.width = width; 1324 1325 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1326 /*force*/FALSE, paused); 1327 } 1328 1329 static void 1330 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1331 { 1332 struct ahc_initiator_tinfo *tinfo; 1333 struct tmode_tstate *tstate; 1334 1335 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1336 devinfo->target, &tstate); 1337 1338 if (enable) { 1339 tstate->tagenable |= devinfo->target_mask; 1340 } else { 1341 tstate->tagenable &= ~devinfo->target_mask; 1342 tstate->tagdisable |= devinfo->target_mask; 1343 } 1344 } 1345 1346 static void 1347 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1348 { 1349 struct scsipi_xfer_mode xm; 1350 struct ahc_initiator_tinfo *tinfo; 1351 struct tmode_tstate *tstate; 1352 1353 if (ahc->inited_targets[devinfo->target] != 2) 1354 return; 1355 1356 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1357 devinfo->target, &tstate); 1358 1359 xm.xm_target = devinfo->target; 1360 xm.xm_mode = 0; 1361 xm.xm_period = tinfo->current.period; 1362 xm.xm_offset = tinfo->current.offset; 1363 if (tinfo->current.width == 1) 1364 xm.xm_mode |= PERIPH_CAP_WIDE16; 1365 if (tinfo->current.period) 1366 xm.xm_mode |= PERIPH_CAP_SYNC; 1367 if (tstate->tagenable & devinfo->target_mask) 1368 xm.xm_mode |= PERIPH_CAP_TQING; 1369 scsipi_async_event( 1370 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1371 ASYNC_EVENT_XFER_MODE, &xm); 1372 } 1373 1374 /* 1375 * Attach all the sub-devices we can find 1376 */ 1377 int 1378 ahc_attach(struct ahc_softc *ahc) 1379 { 1380 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1381 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1382 if (ahc->flags & AHC_PAGESCBS) { 1383 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1384 ahc->sc_adapter.adapt_max_periph = 16; 1385 } else { 1386 ahc->sc_adapter.adapt_openings = ahc->scb_data->maxhscbs; 1387 if (ahc->scb_data->maxhscbs >= 16) 1388 ahc->sc_adapter.adapt_max_periph = 16; 1389 else 1390 ahc->sc_adapter.adapt_max_periph = 4; 1391 } 1392 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1393 ahc->sc_adapter.adapt_minphys = ahcminphys; 1394 ahc->sc_adapter.adapt_request = ahc_action; 1395 1396 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1397 ahc->sc_channel.chan_bustype = &scsi_bustype; 1398 ahc->sc_channel.chan_channel = 0; 1399 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1400 ahc->sc_channel.chan_nluns = 8; 1401 ahc->sc_channel.chan_id = ahc->our_id; 1402 1403 if (ahc->features & AHC_TWIN) { 1404 ahc->sc_channel_b = ahc->sc_channel; 1405 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1406 ahc->sc_channel_b.chan_channel = 1; 1407 } 1408 1409 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1410 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1411 if (ahc->features & AHC_TWIN) 1412 config_found((void *)ahc, &ahc->sc_channel_b, 1413 scsiprint); 1414 } else { 1415 config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1416 config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1417 } 1418 return 1; 1419 } 1420 1421 static void 1422 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1423 { 1424 u_int saved_tcl; 1425 role_t role; 1426 int our_id; 1427 1428 if (ahc_inb(ahc, SSTAT0) & TARGET) 1429 role = ROLE_TARGET; 1430 else 1431 role = ROLE_INITIATOR; 1432 1433 if (role == ROLE_TARGET 1434 && (ahc->features & AHC_MULTI_TID) != 0 1435 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1436 /* We were selected, so pull our id from TARGIDIN */ 1437 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1438 } else if ((ahc->features & AHC_ULTRA2) != 0) 1439 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1440 else 1441 our_id = ahc_inb(ahc, SCSIID) & OID; 1442 1443 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1444 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1445 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1446 role); 1447 } 1448 1449 static void 1450 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1451 u_int lun, char channel, role_t role) 1452 { 1453 devinfo->our_scsiid = our_id; 1454 devinfo->target = target; 1455 devinfo->lun = lun; 1456 devinfo->target_offset = target; 1457 devinfo->channel = channel; 1458 devinfo->role = role; 1459 if (channel == 'B') 1460 devinfo->target_offset += 8; 1461 devinfo->target_mask = (0x01 << devinfo->target_offset); 1462 } 1463 1464 /* 1465 * Catch an interrupt from the adapter 1466 */ 1467 int 1468 ahc_intr(void *arg) 1469 { 1470 struct ahc_softc *ahc; 1471 u_int intstat; 1472 1473 ahc = (struct ahc_softc *)arg; 1474 1475 intstat = ahc_inb(ahc, INTSTAT); 1476 1477 /* 1478 * Any interrupts to process? 1479 */ 1480 if ((intstat & INT_PEND) == 0) { 1481 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1482 #ifdef AHC_DEBUG 1483 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1484 ahc_name(ahc), 1485 ahc_inb(ahc, CCHADDR) | 1486 (ahc_inb(ahc, CCHADDR+1) << 8) 1487 | (ahc_inb(ahc, CCHADDR+2) << 16) 1488 | (ahc_inb(ahc, CCHADDR+3) << 24), 1489 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1490 | (ahc_inb(ahc, HADDR+2) << 16) 1491 | (ahc_inb(ahc, HADDR+3) << 24), 1492 ahc_inb(ahc, SEQADDR0) | 1493 (ahc_inb(ahc, SEQADDR1) << 8)); 1494 #endif 1495 return 1; 1496 } 1497 return 0; 1498 } 1499 1500 #ifdef AHC_DEBUG 1501 if (ahc_debug & AHC_SHOWINTR) { 1502 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1503 } 1504 #endif 1505 1506 if (intstat & CMDCMPLT) { 1507 ahc_outb(ahc, CLRINT, CLRCMDINT); 1508 ahc_run_qoutfifo(ahc); 1509 } 1510 if (intstat & BRKADRINT) { 1511 /* 1512 * We upset the sequencer :-( 1513 * Lookup the error message 1514 */ 1515 int i, error, num_errors; 1516 1517 error = ahc_inb(ahc, ERROR); 1518 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1519 for (i = 0; error != 1 && i < num_errors; i++) 1520 error >>= 1; 1521 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1522 ahc_name(ahc), hard_error[i].errmesg, 1523 ahc_inb(ahc, SEQADDR0) | 1524 (ahc_inb(ahc, SEQADDR1) << 8)); 1525 1526 /* Tell everyone that this HBA is no longer available */ 1527 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1528 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1529 XS_DRIVER_STUFFUP); 1530 } 1531 if (intstat & SEQINT) 1532 ahc_handle_seqint(ahc, intstat); 1533 1534 if (intstat & SCSIINT) 1535 ahc_handle_scsiint(ahc, intstat); 1536 1537 return 1; 1538 } 1539 1540 static struct tmode_tstate * 1541 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1542 { 1543 struct tmode_tstate *master_tstate; 1544 struct tmode_tstate *tstate; 1545 int i, s; 1546 1547 master_tstate = ahc->enabled_targets[ahc->our_id]; 1548 if (channel == 'B') { 1549 scsi_id += 8; 1550 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1551 } 1552 if (ahc->enabled_targets[scsi_id] != NULL 1553 && ahc->enabled_targets[scsi_id] != master_tstate) 1554 panic("%s: ahc_alloc_tstate - Target already allocated", 1555 ahc_name(ahc)); 1556 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1557 if (tstate == NULL) 1558 return (NULL); 1559 1560 /* 1561 * If we have allocated a master tstate, copy user settings from 1562 * the master tstate (taken from SRAM or the EEPROM) for this 1563 * channel, but reset our current and goal settings to async/narrow 1564 * until an initiator talks to us. 1565 */ 1566 if (master_tstate != NULL) { 1567 memcpy(tstate, master_tstate, sizeof(*tstate)); 1568 tstate->ultraenb = 0; 1569 for (i = 0; i < 16; i++) { 1570 memset(&tstate->transinfo[i].current, 0, 1571 sizeof(tstate->transinfo[i].current)); 1572 memset(&tstate->transinfo[i].goal, 0, 1573 sizeof(tstate->transinfo[i].goal)); 1574 } 1575 } else 1576 memset(tstate, 0, sizeof(*tstate)); 1577 s = splbio(); 1578 ahc->enabled_targets[scsi_id] = tstate; 1579 splx(s); 1580 return (tstate); 1581 } 1582 1583 #if UNUSED 1584 static void 1585 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1586 { 1587 struct tmode_tstate *tstate; 1588 1589 /* Don't clean up the entry for our initiator role */ 1590 if ((ahc->flags & AHC_INITIATORMODE) != 0 1591 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1592 || (channel == 'A' && scsi_id == ahc->our_id)) 1593 && force == FALSE) 1594 return; 1595 1596 if (channel == 'B') 1597 scsi_id += 8; 1598 tstate = ahc->enabled_targets[scsi_id]; 1599 if (tstate != NULL) 1600 free(tstate, M_DEVBUF); 1601 ahc->enabled_targets[scsi_id] = NULL; 1602 } 1603 #endif 1604 1605 static void 1606 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1607 { 1608 struct scb *scb; 1609 struct ahc_devinfo devinfo; 1610 1611 ahc_fetch_devinfo(ahc, &devinfo); 1612 1613 /* 1614 * Clear the upper byte that holds SEQINT status 1615 * codes and clear the SEQINT bit. We will unpause 1616 * the sequencer, if appropriate, after servicing 1617 * the request. 1618 */ 1619 ahc_outb(ahc, CLRINT, CLRSEQINT); 1620 switch (intstat & SEQINT_MASK) { 1621 case NO_MATCH: 1622 { 1623 /* Ensure we don't leave the selection hardware on */ 1624 ahc_outb(ahc, SCSISEQ, 1625 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1626 1627 printf("%s:%c:%d: no active SCB for reconnecting " 1628 "target - issuing BUS DEVICE RESET\n", 1629 ahc_name(ahc), devinfo.channel, devinfo.target); 1630 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1631 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1632 ahc_inb(ahc, SEQ_FLAGS)); 1633 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1634 ahc->msgout_len = 1; 1635 ahc->msgout_index = 0; 1636 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1637 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1638 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1639 break; 1640 } 1641 case UPDATE_TMSG_REQ: 1642 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1643 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1644 (ahc->targ_msg_req >> 8) & 0xFF); 1645 ahc_outb(ahc, HS_MAILBOX, 0); 1646 break; 1647 case SEND_REJECT: 1648 { 1649 u_int rejbyte = ahc_inb(ahc, ACCUM); 1650 printf("%s:%c:%d: Warning - unknown message received from " 1651 "target (0x%x). Rejecting\n", 1652 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1653 break; 1654 } 1655 case NO_IDENT: 1656 { 1657 /* 1658 * The reconnecting target either did not send an identify 1659 * message, or did, but we didn't find and SCB to match and 1660 * before it could respond to our ATN/abort, it hit a dataphase. 1661 * The only safe thing to do is to blow it away with a bus 1662 * reset. 1663 */ 1664 int found; 1665 1666 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1667 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1668 ahc_name(ahc), devinfo.channel, devinfo.target, 1669 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1670 found = ahc_reset_channel(ahc, devinfo.channel, 1671 /*initiate reset*/TRUE); 1672 printf("%s: Issued Channel %c Bus Reset. " 1673 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1674 found); 1675 return; 1676 } 1677 case BAD_PHASE: 1678 { 1679 u_int lastphase; 1680 1681 lastphase = ahc_inb(ahc, LASTPHASE); 1682 if (lastphase == P_BUSFREE) { 1683 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1684 ahc_name(ahc), devinfo.channel, devinfo.target, 1685 ahc_inb(ahc, SCSISIGI)); 1686 restart_sequencer(ahc); 1687 return; 1688 } else { 1689 printf("%s:%c:%d: unknown scsi bus phase %x. " 1690 "Attempting to continue\n", 1691 ahc_name(ahc), devinfo.channel, devinfo.target, 1692 ahc_inb(ahc, SCSISIGI)); 1693 } 1694 break; 1695 } 1696 case BAD_STATUS: 1697 { 1698 u_int scb_index; 1699 struct hardware_scb *hscb; 1700 struct scsipi_xfer *xs; 1701 /* 1702 * The sequencer will notify us when a command 1703 * has an error that would be of interest to 1704 * the kernel. This allows us to leave the sequencer 1705 * running in the common case of command completes 1706 * without error. The sequencer will already have 1707 * dma'd the SCB back up to us, so we can reference 1708 * the in kernel copy directly. 1709 */ 1710 scb_index = ahc_inb(ahc, SCB_TAG); 1711 scb = &ahc->scb_data->scbarray[scb_index]; 1712 1713 /* ahc_print_scb(scb); */ 1714 1715 /* 1716 * Set the default return value to 0 (don't 1717 * send sense). The sense code will change 1718 * this if needed. 1719 */ 1720 ahc_outb(ahc, RETURN_1, 0); 1721 if (!(scb_index < ahc->scb_data->numscbs 1722 && (scb->flags & SCB_ACTIVE) != 0)) { 1723 printf("%s:%c:%d: ahc_intr - referenced scb " 1724 "not valid during seqint 0x%x scb(%d)\n", 1725 ahc_name(ahc), devinfo.channel, 1726 devinfo.target, intstat, scb_index); 1727 goto unpause; 1728 } 1729 1730 hscb = scb->hscb; 1731 xs = scb->xs; 1732 1733 /* Don't want to clobber the original sense code */ 1734 if ((scb->flags & SCB_SENSE) != 0) { 1735 /* 1736 * Clear the SCB_SENSE Flag and have 1737 * the sequencer do a normal command 1738 * complete. 1739 */ 1740 scb->flags &= ~SCB_SENSE; 1741 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1742 break; 1743 } 1744 /* Freeze the queue unit the client sees the error. */ 1745 ahc_freeze_devq(ahc, xs->xs_periph); 1746 ahc_freeze_ccb(scb); 1747 xs->status = hscb->status; 1748 switch (hscb->status) { 1749 case SCSI_STATUS_OK: 1750 printf("%s: Interrupted for status of 0???\n", 1751 ahc_name(ahc)); 1752 break; 1753 case SCSI_STATUS_CMD_TERMINATED: 1754 case SCSI_STATUS_CHECK_COND: 1755 #if defined(AHC_DEBUG) 1756 if (ahc_debug & AHC_SHOWSENSE) { 1757 scsipi_printaddr(xs->xs_periph); 1758 printf("Check Status, resid %d datalen %d\n", 1759 xs->resid, xs->datalen); 1760 } 1761 #endif 1762 1763 if (xs->error == XS_NOERROR && 1764 !(scb->flags & SCB_SENSE)) { 1765 struct ahc_dma_seg *sg; 1766 struct scsipi_sense *sc; 1767 struct ahc_initiator_tinfo *tinfo; 1768 struct tmode_tstate *tstate; 1769 1770 sg = scb->sg_list; 1771 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1772 /* 1773 * Save off the residual if there is one. 1774 */ 1775 if (hscb->residual_SG_count != 0) 1776 ahc_calc_residual(scb); 1777 else 1778 xs->resid = 0; 1779 1780 #ifdef AHC_DEBUG 1781 if (ahc_debug & AHC_SHOWSENSE) { 1782 scsipi_printaddr(xs->xs_periph); 1783 printf("Sending Sense\n"); 1784 } 1785 #endif 1786 sg->addr = ahc->scb_data->sense_busaddr + 1787 (hscb->tag*sizeof(struct scsipi_sense_data)); 1788 sg->len = sizeof (struct scsipi_sense_data); 1789 1790 sc->opcode = REQUEST_SENSE; 1791 sc->byte2 = SCB_LUN(scb) << 5; 1792 sc->unused[0] = 0; 1793 sc->unused[1] = 0; 1794 sc->length = sg->len; 1795 sc->control = 0; 1796 1797 /* 1798 * Would be nice to preserve DISCENB here, 1799 * but due to the way we page SCBs, we can't. 1800 */ 1801 hscb->control = 0; 1802 1803 /* 1804 * This request sense could be because the 1805 * the device lost power or in some other 1806 * way has lost our transfer negotiations. 1807 * Renegotiate if appropriate. Unit attention 1808 * errors will be reported before any data 1809 * phases occur. 1810 */ 1811 ahc_calc_residual(scb); 1812 #if defined(AHC_DEBUG) 1813 if (ahc_debug & AHC_SHOWSENSE) { 1814 scsipi_printaddr(xs->xs_periph); 1815 printf("Sense: datalen %d resid %d" 1816 "chan %d id %d targ %d\n", 1817 xs->datalen, xs->resid, 1818 devinfo.channel, devinfo.our_scsiid, 1819 devinfo.target); 1820 } 1821 #endif 1822 if (xs->datalen > 0 && 1823 xs->resid == xs->datalen) { 1824 tinfo = ahc_fetch_transinfo(ahc, 1825 devinfo.channel, 1826 devinfo.our_scsiid, 1827 devinfo.target, 1828 &tstate); 1829 ahc_update_target_msg_request(ahc, 1830 &devinfo, 1831 tinfo, 1832 /*force*/TRUE, 1833 /*paused*/TRUE); 1834 } 1835 hscb->status = 0; 1836 hscb->SG_count = 1; 1837 hscb->SG_pointer = scb->sg_list_phys; 1838 hscb->data = sg->addr; 1839 hscb->datalen = sg->len; 1840 hscb->cmdpointer = hscb->cmdstore_busaddr; 1841 hscb->cmdlen = sizeof(*sc); 1842 scb->sg_count = hscb->SG_count; 1843 ahc_swap_hscb(hscb); 1844 ahc_swap_sg(scb->sg_list); 1845 scb->flags |= SCB_SENSE; 1846 /* 1847 * Ensure the target is busy since this 1848 * will be an untagged request. 1849 */ 1850 ahc_busy_tcl(ahc, scb); 1851 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1852 1853 /* 1854 * Ensure we have enough time to actually 1855 * retrieve the sense. 1856 */ 1857 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1858 callout_reset(&scb->xs->xs_callout, 1859 5 * hz, ahc_timeout, scb); 1860 } 1861 } 1862 break; 1863 case SCSI_STATUS_QUEUE_FULL: 1864 case SCSI_STATUS_BUSY: 1865 xs->error = XS_BUSY; 1866 break; 1867 } 1868 break; 1869 } 1870 case TRACE_POINT: 1871 { 1872 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1873 ahc_inb(ahc, DFCNTRL)); 1874 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1875 ahc_inb(ahc, DFSTATUS)); 1876 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1877 ahc_inb(ahc, SSTAT0), 1878 ahc_inb(ahc, SCB_DATACNT)); 1879 break; 1880 } 1881 case HOST_MSG_LOOP: 1882 { 1883 /* 1884 * The sequencer has encountered a message phase 1885 * that requires host assistance for completion. 1886 * While handling the message phase(s), we will be 1887 * notified by the sequencer after each byte is 1888 * transferred so we can track bus phases. 1889 * 1890 * If this is the first time we've seen a HOST_MSG_LOOP, 1891 * initialize the state of the host message loop. 1892 */ 1893 if (ahc->msg_type == MSG_TYPE_NONE) { 1894 u_int bus_phase; 1895 1896 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1897 if (bus_phase != P_MESGIN 1898 && bus_phase != P_MESGOUT) { 1899 printf("ahc_intr: HOST_MSG_LOOP bad " 1900 "phase 0x%x\n", 1901 bus_phase); 1902 /* 1903 * Probably transitioned to bus free before 1904 * we got here. Just punt the message. 1905 */ 1906 ahc_clear_intstat(ahc); 1907 restart_sequencer(ahc); 1908 } 1909 1910 if (devinfo.role == ROLE_INITIATOR) { 1911 struct scb *scb; 1912 u_int scb_index; 1913 1914 scb_index = ahc_inb(ahc, SCB_TAG); 1915 scb = &ahc->scb_data->scbarray[scb_index]; 1916 1917 if (bus_phase == P_MESGOUT) 1918 ahc_setup_initiator_msgout(ahc, 1919 &devinfo, 1920 scb); 1921 else { 1922 ahc->msg_type = 1923 MSG_TYPE_INITIATOR_MSGIN; 1924 ahc->msgin_index = 0; 1925 } 1926 } else { 1927 if (bus_phase == P_MESGOUT) { 1928 ahc->msg_type = 1929 MSG_TYPE_TARGET_MSGOUT; 1930 ahc->msgin_index = 0; 1931 } else 1932 /* XXX Ever executed??? */ 1933 ahc_setup_target_msgin(ahc, &devinfo); 1934 } 1935 } 1936 1937 /* Pass a NULL path so that handlers generate their own */ 1938 ahc_handle_message_phase(ahc, /*path*/NULL); 1939 break; 1940 } 1941 case PERR_DETECTED: 1942 { 1943 /* 1944 * If we've cleared the parity error interrupt 1945 * but the sequencer still believes that SCSIPERR 1946 * is true, it must be that the parity error is 1947 * for the currently presented byte on the bus, 1948 * and we are not in a phase (data-in) where we will 1949 * eventually ack this byte. Ack the byte and 1950 * throw it away in the hope that the target will 1951 * take us to message out to deliver the appropriate 1952 * error message. 1953 */ 1954 if ((intstat & SCSIINT) == 0 1955 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1956 u_int curphase; 1957 1958 /* 1959 * The hardware will only let you ack bytes 1960 * if the expected phase in SCSISIGO matches 1961 * the current phase. Make sure this is 1962 * currently the case. 1963 */ 1964 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1965 ahc_outb(ahc, LASTPHASE, curphase); 1966 ahc_outb(ahc, SCSISIGO, curphase); 1967 ahc_inb(ahc, SCSIDATL); 1968 } 1969 break; 1970 } 1971 case DATA_OVERRUN: 1972 { 1973 /* 1974 * When the sequencer detects an overrun, it 1975 * places the controller in "BITBUCKET" mode 1976 * and allows the target to complete its transfer. 1977 * Unfortunately, none of the counters get updated 1978 * when the controller is in this mode, so we have 1979 * no way of knowing how large the overrun was. 1980 */ 1981 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1982 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1983 int i; 1984 1985 scb = &ahc->scb_data->scbarray[scbindex]; 1986 for (i = 0; i < num_phases; i++) { 1987 if (lastphase == phase_table[i].phase) 1988 break; 1989 } 1990 scsipi_printaddr(scb->xs->xs_periph); 1991 printf("data overrun detected %s." 1992 " Tag == 0x%x.\n", 1993 phase_table[i].phasemsg, 1994 scb->hscb->tag); 1995 scsipi_printaddr(scb->xs->xs_periph); 1996 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1997 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1998 scb->xs->datalen, scb->sg_count); 1999 if (scb->sg_count > 0) { 2000 for (i = 0; i < scb->sg_count; i++) { 2001 printf("sg[%d] - Addr 0x%x : Length %d\n", 2002 i, 2003 le32toh(scb->sg_list[i].addr), 2004 le32toh(scb->sg_list[i].len)); 2005 } 2006 } 2007 /* 2008 * Set this and it will take affect when the 2009 * target does a command complete. 2010 */ 2011 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2012 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2013 ahc_freeze_ccb(scb); 2014 break; 2015 } 2016 case TRACEPOINT: 2017 { 2018 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2019 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2020 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2021 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2022 printf("TRACEPOINT: CCHADDR = %x\n", 2023 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2024 | (ahc_inb(ahc, CCHADDR+2) << 16) 2025 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2026 #if 0 2027 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2028 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2029 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2030 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2031 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2032 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2033 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2034 ahc_inb(ahc, CCHADDR) 2035 | (ahc_inb(ahc, CCHADDR+1) << 8) 2036 | (ahc_inb(ahc, CCHADDR+2) << 16) 2037 | (ahc_inb(ahc, CCHADDR+3) << 24), 2038 ahc_inb(ahc, CCHCNT) 2039 | (ahc_inb(ahc, CCHCNT+1) << 8) 2040 | (ahc_inb(ahc, CCHCNT+2) << 16), 2041 ahc_inb(ahc, SCBPTR)); 2042 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2043 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2044 #ifdef DDB 2045 cpu_Debugger(); 2046 #endif 2047 #endif 2048 break; 2049 } 2050 #if NOT_YET 2051 /* XXX Fill these in later */ 2052 case MESG_BUFFER_BUSY: 2053 break; 2054 case MSGIN_PHASEMIS: 2055 break; 2056 #endif 2057 default: 2058 printf("ahc_intr: seqint, " 2059 "intstat == 0x%x, scsisigi = 0x%x\n", 2060 intstat, ahc_inb(ahc, SCSISIGI)); 2061 break; 2062 } 2063 2064 unpause: 2065 /* 2066 * The sequencer is paused immediately on 2067 * a SEQINT, so we should restart it when 2068 * we're done. 2069 */ 2070 unpause_sequencer(ahc); 2071 } 2072 2073 static void 2074 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2075 { 2076 u_int scb_index; 2077 u_int status; 2078 struct scb *scb; 2079 char cur_channel; 2080 char intr_channel; 2081 2082 if ((ahc->features & AHC_TWIN) != 0 2083 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2084 cur_channel = 'B'; 2085 else 2086 cur_channel = 'A'; 2087 intr_channel = cur_channel; 2088 2089 status = ahc_inb(ahc, SSTAT1); 2090 if (status == 0) { 2091 if ((ahc->features & AHC_TWIN) != 0) { 2092 /* Try the other channel */ 2093 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2094 status = ahc_inb(ahc, SSTAT1); 2095 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2096 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2097 } 2098 if (status == 0) { 2099 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2100 return; 2101 } 2102 } 2103 2104 scb_index = ahc_inb(ahc, SCB_TAG); 2105 if (scb_index < ahc->scb_data->numscbs) { 2106 scb = &ahc->scb_data->scbarray[scb_index]; 2107 if ((scb->flags & SCB_ACTIVE) == 0 2108 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2109 scb = NULL; 2110 } else 2111 scb = NULL; 2112 2113 if ((status & SCSIRSTI) != 0) { 2114 printf("%s: Someone reset channel %c\n", 2115 ahc_name(ahc), intr_channel); 2116 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2117 } else if ((status & SCSIPERR) != 0) { 2118 /* 2119 * Determine the bus phase and queue an appropriate message. 2120 * SCSIPERR is latched true as soon as a parity error 2121 * occurs. If the sequencer acked the transfer that 2122 * caused the parity error and the currently presented 2123 * transfer on the bus has correct parity, SCSIPERR will 2124 * be cleared by CLRSCSIPERR. Use this to determine if 2125 * we should look at the last phase the sequencer recorded, 2126 * or the current phase presented on the bus. 2127 */ 2128 u_int mesg_out; 2129 u_int curphase; 2130 u_int errorphase; 2131 u_int lastphase; 2132 int i; 2133 2134 lastphase = ahc_inb(ahc, LASTPHASE); 2135 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2136 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2137 /* 2138 * For all phases save DATA, the sequencer won't 2139 * automatically ack a byte that has a parity error 2140 * in it. So the only way that the current phase 2141 * could be 'data-in' is if the parity error is for 2142 * an already acked byte in the data phase. During 2143 * synchronous data-in transfers, we may actually 2144 * ack bytes before latching the current phase in 2145 * LASTPHASE, leading to the discrepancy between 2146 * curphase and lastphase. 2147 */ 2148 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2149 || curphase == P_DATAIN) 2150 errorphase = curphase; 2151 else 2152 errorphase = lastphase; 2153 2154 for (i = 0; i < num_phases; i++) { 2155 if (errorphase == phase_table[i].phase) 2156 break; 2157 } 2158 mesg_out = phase_table[i].mesg_out; 2159 if (scb != NULL) 2160 scsipi_printaddr(scb->xs->xs_periph); 2161 else 2162 printf("%s:%c:%d: ", ahc_name(ahc), 2163 intr_channel, 2164 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2165 2166 printf("parity error detected %s. " 2167 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2168 phase_table[i].phasemsg, 2169 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2170 ahc_inb(ahc, SCSIRATE)); 2171 2172 /* 2173 * We've set the hardware to assert ATN if we 2174 * get a parity error on "in" phases, so all we 2175 * need to do is stuff the message buffer with 2176 * the appropriate message. "In" phases have set 2177 * mesg_out to something other than MSG_NOP. 2178 */ 2179 if (mesg_out != MSG_NOOP) { 2180 if (ahc->msg_type != MSG_TYPE_NONE) 2181 ahc->send_msg_perror = TRUE; 2182 else 2183 ahc_outb(ahc, MSG_OUT, mesg_out); 2184 } 2185 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2186 unpause_sequencer(ahc); 2187 } else if ((status & BUSFREE) != 0 2188 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2189 /* 2190 * First look at what phase we were last in. 2191 * If its message out, chances are pretty good 2192 * that the busfree was in response to one of 2193 * our abort requests. 2194 */ 2195 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2196 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2197 u_int target = TCL_TARGET(saved_tcl); 2198 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2199 char channel = TCL_CHANNEL(ahc, saved_tcl); 2200 int printerror = 1; 2201 2202 ahc_outb(ahc, SCSISEQ, 2203 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2204 if (lastphase == P_MESGOUT) { 2205 u_int message; 2206 u_int tag; 2207 2208 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2209 tag = SCB_LIST_NULL; 2210 switch (message) { 2211 case MSG_ABORT_TAG: 2212 tag = scb->hscb->tag; 2213 /* FALLTRHOUGH */ 2214 case MSG_ABORT: 2215 scsipi_printaddr(scb->xs->xs_periph); 2216 printf("SCB %x - Abort %s Completed.\n", 2217 scb->hscb->tag, tag == SCB_LIST_NULL ? 2218 "" : "Tag"); 2219 ahc_abort_scbs(ahc, target, channel, 2220 TCL_LUN(saved_tcl), tag, 2221 ROLE_INITIATOR, 2222 XS_DRIVER_STUFFUP); 2223 printerror = 0; 2224 break; 2225 case MSG_BUS_DEV_RESET: 2226 { 2227 struct ahc_devinfo devinfo; 2228 2229 if (scb != NULL && 2230 (scb->xs->xs_control & XS_CTL_RESET) 2231 && ahc_match_scb(scb, target, channel, 2232 TCL_LUN(saved_tcl), 2233 SCB_LIST_NULL, 2234 ROLE_INITIATOR)) { 2235 ahcsetccbstatus(scb->xs, XS_NOERROR); 2236 } 2237 ahc_compile_devinfo(&devinfo, 2238 initiator_role_id, 2239 target, 2240 TCL_LUN(saved_tcl), 2241 channel, 2242 ROLE_INITIATOR); 2243 ahc_handle_devreset(ahc, &devinfo, 2244 XS_RESET, 2245 "Bus Device Reset", 2246 /*verbose_level*/0); 2247 printerror = 0; 2248 break; 2249 } 2250 default: 2251 break; 2252 } 2253 } 2254 if (printerror != 0) { 2255 int i; 2256 2257 if (scb != NULL) { 2258 u_int tag; 2259 2260 if ((scb->hscb->control & TAG_ENB) != 0) 2261 tag = scb->hscb->tag; 2262 else 2263 tag = SCB_LIST_NULL; 2264 ahc_abort_scbs(ahc, target, channel, 2265 SCB_LUN(scb), tag, 2266 ROLE_INITIATOR, 2267 XS_DRIVER_STUFFUP); 2268 scsipi_printaddr(scb->xs->xs_periph); 2269 } else { 2270 /* 2271 * We had not fully identified this connection, 2272 * so we cannot abort anything. 2273 */ 2274 printf("%s: ", ahc_name(ahc)); 2275 } 2276 for (i = 0; i < num_phases; i++) { 2277 if (lastphase == phase_table[i].phase) 2278 break; 2279 } 2280 printf("Unexpected busfree %s\n" 2281 "SEQADDR == 0x%x\n", 2282 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2283 | (ahc_inb(ahc, SEQADDR1) << 8)); 2284 } 2285 ahc_clear_msg_state(ahc); 2286 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2287 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2288 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2289 restart_sequencer(ahc); 2290 } else if ((status & SELTO) != 0) { 2291 u_int scbptr; 2292 2293 scbptr = ahc_inb(ahc, WAITING_SCBH); 2294 ahc_outb(ahc, SCBPTR, scbptr); 2295 scb_index = ahc_inb(ahc, SCB_TAG); 2296 2297 if (scb_index < ahc->scb_data->numscbs) { 2298 scb = &ahc->scb_data->scbarray[scb_index]; 2299 if ((scb->flags & SCB_ACTIVE) == 0) 2300 scb = NULL; 2301 } else 2302 scb = NULL; 2303 2304 if (scb == NULL) { 2305 printf("%s: ahc_intr - referenced scb not " 2306 "valid during SELTO scb(%d, %d)\n", 2307 ahc_name(ahc), scbptr, scb_index); 2308 } else { 2309 u_int tag; 2310 2311 tag = SCB_LIST_NULL; 2312 if ((scb->hscb->control & TAG_ENB) != 0) 2313 tag = scb->hscb->tag; 2314 2315 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2316 SCB_LUN(scb), tag, 2317 ROLE_INITIATOR, XS_SELTIMEOUT); 2318 } 2319 /* Stop the selection */ 2320 ahc_outb(ahc, SCSISEQ, 0); 2321 2322 /* No more pending messages */ 2323 ahc_clear_msg_state(ahc); 2324 2325 /* 2326 * Although the driver does not care about the 2327 * 'Selection in Progress' status bit, the busy 2328 * LED does. SELINGO is only cleared by a sucessful 2329 * selection, so we must manually clear it to ensure 2330 * the LED turns off just incase no future successful 2331 * selections occur (e.g. no devices on the bus). 2332 */ 2333 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2334 2335 /* Clear interrupt state */ 2336 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2337 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2338 restart_sequencer(ahc); 2339 } else { 2340 scsipi_printaddr(scb->xs->xs_periph); 2341 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2342 ahc_outb(ahc, CLRSINT1, status); 2343 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2344 unpause_sequencer(ahc); 2345 } 2346 } 2347 2348 static void 2349 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2350 { 2351 /* 2352 * We need to initiate transfer negotiations. 2353 * If our current and goal settings are identical, 2354 * we want to renegotiate due to a check condition. 2355 */ 2356 struct ahc_initiator_tinfo *tinfo; 2357 struct tmode_tstate *tstate; 2358 int dowide; 2359 int dosync; 2360 2361 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2362 devinfo->target, &tstate); 2363 dowide = tinfo->current.width != tinfo->goal.width; 2364 dosync = tinfo->current.period != tinfo->goal.period; 2365 2366 if (!dowide && !dosync) { 2367 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2368 dosync = tinfo->goal.period != 0; 2369 } 2370 2371 if (dowide) { 2372 ahc_construct_wdtr(ahc, tinfo->goal.width); 2373 } else if (dosync) { 2374 const struct ahc_syncrate *rate; 2375 u_int period; 2376 u_int offset; 2377 2378 period = tinfo->goal.period; 2379 rate = ahc_devlimited_syncrate(ahc, &period); 2380 offset = tinfo->goal.offset; 2381 ahc_validate_offset(ahc, rate, &offset, 2382 tinfo->current.width); 2383 ahc_construct_sdtr(ahc, period, offset); 2384 } else { 2385 panic("ahc_intr: AWAITING_MSG for negotiation, " 2386 "but no negotiation needed\n"); 2387 } 2388 } 2389 2390 static void 2391 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2392 struct scb *scb) 2393 { 2394 /* 2395 * To facilitate adding multiple messages together, 2396 * each routine should increment the index and len 2397 * variables instead of setting them explicitly. 2398 */ 2399 ahc->msgout_index = 0; 2400 ahc->msgout_len = 0; 2401 2402 if ((scb->flags & SCB_DEVICE_RESET) == 0 2403 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2404 u_int identify_msg; 2405 2406 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2407 if ((scb->hscb->control & DISCENB) != 0) 2408 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2409 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2410 ahc->msgout_len++; 2411 2412 if ((scb->hscb->control & TAG_ENB) != 0) { 2413 ahc->msgout_buf[ahc->msgout_index++] = 2414 scb->xs->xs_tag_type; 2415 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2416 ahc->msgout_len += 2; 2417 } 2418 } 2419 2420 if (scb->flags & SCB_DEVICE_RESET) { 2421 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2422 ahc->msgout_len++; 2423 scsipi_printaddr(scb->xs->xs_periph); 2424 printf("Bus Device Reset Message Sent\n"); 2425 } else if (scb->flags & SCB_ABORT) { 2426 if ((scb->hscb->control & TAG_ENB) != 0) 2427 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2428 else 2429 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2430 ahc->msgout_len++; 2431 scsipi_printaddr(scb->xs->xs_periph); 2432 printf("Abort Message Sent\n"); 2433 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2434 ahc_build_transfer_msg(ahc, devinfo); 2435 } else { 2436 printf("ahc_intr: AWAITING_MSG for an SCB that " 2437 "does not have a waiting message"); 2438 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2439 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2440 ahc_inb(ahc, MSG_OUT), scb->flags); 2441 } 2442 2443 /* 2444 * Clear the MK_MESSAGE flag from the SCB so we aren't 2445 * asked to send this message again. 2446 */ 2447 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2448 ahc->msgout_index = 0; 2449 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2450 } 2451 2452 static void 2453 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2454 { 2455 /* 2456 * To facilitate adding multiple messages together, 2457 * each routine should increment the index and len 2458 * variables instead of setting them explicitly. 2459 */ 2460 ahc->msgout_index = 0; 2461 ahc->msgout_len = 0; 2462 2463 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2464 ahc_build_transfer_msg(ahc, devinfo); 2465 else 2466 panic("ahc_intr: AWAITING target message with no message"); 2467 2468 ahc->msgout_index = 0; 2469 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2470 } 2471 2472 static int 2473 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2474 { 2475 /* 2476 * What we care about here is if we had an 2477 * outstanding SDTR or WDTR message for this 2478 * target. If we did, this is a signal that 2479 * the target is refusing negotiation. 2480 */ 2481 struct scb *scb; 2482 u_int scb_index; 2483 u_int last_msg; 2484 int response = 0; 2485 2486 scb_index = ahc_inb(ahc, SCB_TAG); 2487 scb = &ahc->scb_data->scbarray[scb_index]; 2488 2489 /* Might be necessary */ 2490 last_msg = ahc_inb(ahc, LAST_MSG); 2491 2492 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2493 struct ahc_initiator_tinfo *tinfo; 2494 struct tmode_tstate *tstate; 2495 2496 #ifdef AHC_DEBUG_NEG 2497 /* note 8bit xfers */ 2498 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2499 "8bit transfers\n", ahc_name(ahc), 2500 devinfo->channel, devinfo->target); 2501 #endif 2502 ahc_set_width(ahc, devinfo, 2503 MSG_EXT_WDTR_BUS_8_BIT, 2504 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2505 /*paused*/TRUE, /*done*/TRUE); 2506 /* 2507 * No need to clear the sync rate. If the target 2508 * did not accept the command, our syncrate is 2509 * unaffected. If the target started the negotiation, 2510 * but rejected our response, we already cleared the 2511 * sync rate before sending our WDTR. 2512 */ 2513 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2514 devinfo->our_scsiid, 2515 devinfo->target, &tstate); 2516 if (tinfo->goal.period) { 2517 u_int period; 2518 2519 /* Start the sync negotiation */ 2520 period = tinfo->goal.period; 2521 ahc_devlimited_syncrate(ahc, &period); 2522 ahc->msgout_index = 0; 2523 ahc->msgout_len = 0; 2524 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2525 ahc->msgout_index = 0; 2526 response = 1; 2527 } else 2528 ahc_update_xfer_mode(ahc, devinfo); 2529 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2530 /* note asynch xfers and clear flag */ 2531 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2532 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2533 /*paused*/TRUE, /*done*/TRUE); 2534 #ifdef AHC_DEBUG_NEG 2535 printf("%s:%c:%d: refuses synchronous negotiation. " 2536 "Using asynchronous transfers\n", 2537 ahc_name(ahc), 2538 devinfo->channel, devinfo->target); 2539 #endif 2540 ahc_update_xfer_mode(ahc, devinfo); 2541 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2542 printf("%s:%c:%d: refuses tagged commands. Performing " 2543 "non-tagged I/O\n", ahc_name(ahc), 2544 devinfo->channel, devinfo->target); 2545 2546 ahc_set_tags(ahc, devinfo, FALSE); 2547 ahc_update_xfer_mode(ahc, devinfo); 2548 2549 /* 2550 * Resend the identify for this CCB as the target 2551 * may believe that the selection is invalid otherwise. 2552 */ 2553 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2554 & ~MSG_SIMPLE_Q_TAG); 2555 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2556 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2557 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2558 2559 /* 2560 * Requeue all tagged commands for this target 2561 * currently in our posession so they can be 2562 * converted to untagged commands. 2563 */ 2564 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2565 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2566 ROLE_INITIATOR, SCB_REQUEUE, 2567 SEARCH_COMPLETE); 2568 } else { 2569 /* 2570 * Otherwise, we ignore it. 2571 */ 2572 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2573 ahc_name(ahc), devinfo->channel, devinfo->target, 2574 last_msg); 2575 } 2576 return (response); 2577 } 2578 2579 static void 2580 ahc_clear_msg_state(struct ahc_softc *ahc) 2581 { 2582 ahc->msgout_len = 0; 2583 ahc->msgin_index = 0; 2584 ahc->msg_type = MSG_TYPE_NONE; 2585 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2586 } 2587 2588 static void 2589 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2590 { 2591 struct ahc_devinfo devinfo; 2592 u_int bus_phase; 2593 int end_session; 2594 2595 ahc_fetch_devinfo(ahc, &devinfo); 2596 end_session = FALSE; 2597 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2598 2599 reswitch: 2600 switch (ahc->msg_type) { 2601 case MSG_TYPE_INITIATOR_MSGOUT: 2602 { 2603 int lastbyte; 2604 int phasemis; 2605 int msgdone; 2606 2607 if (ahc->msgout_len == 0) 2608 panic("REQINIT interrupt with no active message"); 2609 2610 phasemis = bus_phase != P_MESGOUT; 2611 if (phasemis) { 2612 if (bus_phase == P_MESGIN) { 2613 /* 2614 * Change gears and see if 2615 * this messages is of interest to 2616 * us or should be passed back to 2617 * the sequencer. 2618 */ 2619 ahc_outb(ahc, CLRSINT1, CLRATNO); 2620 ahc->send_msg_perror = FALSE; 2621 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2622 ahc->msgin_index = 0; 2623 goto reswitch; 2624 } 2625 end_session = TRUE; 2626 break; 2627 } 2628 2629 if (ahc->send_msg_perror) { 2630 ahc_outb(ahc, CLRSINT1, CLRATNO); 2631 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2632 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2633 break; 2634 } 2635 2636 msgdone = ahc->msgout_index == ahc->msgout_len; 2637 if (msgdone) { 2638 /* 2639 * The target has requested a retry. 2640 * Re-assert ATN, reset our message index to 2641 * 0, and try again. 2642 */ 2643 ahc->msgout_index = 0; 2644 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2645 } 2646 2647 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2648 if (lastbyte) { 2649 /* Last byte is signified by dropping ATN */ 2650 ahc_outb(ahc, CLRSINT1, CLRATNO); 2651 } 2652 2653 /* 2654 * Clear our interrupt status and present 2655 * the next byte on the bus. 2656 */ 2657 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2658 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2659 break; 2660 } 2661 case MSG_TYPE_INITIATOR_MSGIN: 2662 { 2663 int phasemis; 2664 int message_done; 2665 2666 phasemis = bus_phase != P_MESGIN; 2667 2668 if (phasemis) { 2669 ahc->msgin_index = 0; 2670 if (bus_phase == P_MESGOUT 2671 && (ahc->send_msg_perror == TRUE 2672 || (ahc->msgout_len != 0 2673 && ahc->msgout_index == 0))) { 2674 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2675 goto reswitch; 2676 } 2677 end_session = TRUE; 2678 break; 2679 } 2680 2681 /* Pull the byte in without acking it */ 2682 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2683 2684 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2685 2686 if (message_done) { 2687 /* 2688 * Clear our incoming message buffer in case there 2689 * is another message following this one. 2690 */ 2691 ahc->msgin_index = 0; 2692 2693 /* 2694 * If this message illicited a response, 2695 * assert ATN so the target takes us to the 2696 * message out phase. 2697 */ 2698 if (ahc->msgout_len != 0) 2699 ahc_outb(ahc, SCSISIGO, 2700 ahc_inb(ahc, SCSISIGO) | ATNO); 2701 } else 2702 ahc->msgin_index++; 2703 2704 /* Ack the byte */ 2705 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2706 ahc_inb(ahc, SCSIDATL); 2707 break; 2708 } 2709 case MSG_TYPE_TARGET_MSGIN: 2710 { 2711 int msgdone; 2712 int msgout_request; 2713 2714 if (ahc->msgout_len == 0) 2715 panic("Target MSGIN with no active message"); 2716 2717 /* 2718 * If we interrupted a mesgout session, the initiator 2719 * will not know this until our first REQ. So, we 2720 * only honor mesgout requests after we've sent our 2721 * first byte. 2722 */ 2723 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2724 && ahc->msgout_index > 0) 2725 msgout_request = TRUE; 2726 else 2727 msgout_request = FALSE; 2728 2729 if (msgout_request) { 2730 2731 /* 2732 * Change gears and see if 2733 * this messages is of interest to 2734 * us or should be passed back to 2735 * the sequencer. 2736 */ 2737 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2738 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2739 ahc->msgin_index = 0; 2740 /* Dummy read to REQ for first byte */ 2741 ahc_inb(ahc, SCSIDATL); 2742 ahc_outb(ahc, SXFRCTL0, 2743 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2744 break; 2745 } 2746 2747 msgdone = ahc->msgout_index == ahc->msgout_len; 2748 if (msgdone) { 2749 ahc_outb(ahc, SXFRCTL0, 2750 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2751 end_session = TRUE; 2752 break; 2753 } 2754 2755 /* 2756 * Present the next byte on the bus. 2757 */ 2758 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2759 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2760 break; 2761 } 2762 case MSG_TYPE_TARGET_MSGOUT: 2763 { 2764 int lastbyte; 2765 int msgdone; 2766 2767 /* 2768 * The initiator signals that this is 2769 * the last byte by dropping ATN. 2770 */ 2771 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2772 2773 /* 2774 * Read the latched byte, but turn off SPIOEN first 2775 * so that we don't inadvertantly cause a REQ for the 2776 * next byte. 2777 */ 2778 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2779 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2780 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2781 if (msgdone == MSGLOOP_TERMINATED) { 2782 /* 2783 * The message is *really* done in that it caused 2784 * us to go to bus free. The sequencer has already 2785 * been reset at this point, so pull the ejection 2786 * handle. 2787 */ 2788 return; 2789 } 2790 2791 ahc->msgin_index++; 2792 2793 /* 2794 * XXX Read spec about initiator dropping ATN too soon 2795 * and use msgdone to detect it. 2796 */ 2797 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2798 ahc->msgin_index = 0; 2799 2800 /* 2801 * If this message illicited a response, transition 2802 * to the Message in phase and send it. 2803 */ 2804 if (ahc->msgout_len != 0) { 2805 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2806 ahc_outb(ahc, SXFRCTL0, 2807 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2808 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2809 ahc->msgin_index = 0; 2810 break; 2811 } 2812 } 2813 2814 if (lastbyte) 2815 end_session = TRUE; 2816 else { 2817 /* Ask for the next byte. */ 2818 ahc_outb(ahc, SXFRCTL0, 2819 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2820 } 2821 2822 break; 2823 } 2824 default: 2825 panic("Unknown REQINIT message type"); 2826 } 2827 2828 if (end_session) { 2829 ahc_clear_msg_state(ahc); 2830 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2831 } else 2832 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2833 } 2834 2835 /* 2836 * See if we sent a particular extended message to the target. 2837 * If "full" is true, the target saw the full message. 2838 * If "full" is false, the target saw at least the first 2839 * byte of the message. 2840 */ 2841 static int 2842 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2843 { 2844 int found; 2845 int index; 2846 2847 found = FALSE; 2848 index = 0; 2849 2850 while (index < ahc->msgout_len) { 2851 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2852 2853 /* Found a candidate */ 2854 if (ahc->msgout_buf[index+2] == msgtype) { 2855 u_int end_index; 2856 2857 end_index = index + 1 2858 + ahc->msgout_buf[index + 1]; 2859 if (full) { 2860 if (ahc->msgout_index > end_index) 2861 found = TRUE; 2862 } else if (ahc->msgout_index > index) 2863 found = TRUE; 2864 } 2865 break; 2866 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2867 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2868 2869 /* Skip tag type and tag id or residue param*/ 2870 index += 2; 2871 } else { 2872 /* Single byte message */ 2873 index++; 2874 } 2875 } 2876 return (found); 2877 } 2878 2879 static int 2880 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2881 struct ahc_devinfo *devinfo) 2882 { 2883 struct ahc_initiator_tinfo *tinfo; 2884 struct tmode_tstate *tstate; 2885 int reject; 2886 int done; 2887 int response; 2888 u_int targ_scsirate; 2889 2890 done = MSGLOOP_IN_PROG; 2891 response = FALSE; 2892 reject = FALSE; 2893 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2894 devinfo->target, &tstate); 2895 targ_scsirate = tinfo->scsirate; 2896 2897 /* 2898 * Parse as much of the message as is available, 2899 * rejecting it if we don't support it. When 2900 * the entire message is available and has been 2901 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2902 * that we have parsed an entire message. 2903 * 2904 * In the case of extended messages, we accept the length 2905 * byte outright and perform more checking once we know the 2906 * extended message type. 2907 */ 2908 switch (ahc->msgin_buf[0]) { 2909 case MSG_MESSAGE_REJECT: 2910 response = ahc_handle_msg_reject(ahc, devinfo); 2911 /* FALLTHROUGH */ 2912 case MSG_NOOP: 2913 done = MSGLOOP_MSGCOMPLETE; 2914 break; 2915 case MSG_IGN_WIDE_RESIDUE: 2916 { 2917 /* Wait for the whole message */ 2918 if (ahc->msgin_index >= 1) { 2919 if (ahc->msgin_buf[1] != 1 2920 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2921 reject = TRUE; 2922 done = MSGLOOP_MSGCOMPLETE; 2923 } else 2924 ahc_handle_ign_wide_residue(ahc, devinfo); 2925 } 2926 break; 2927 } 2928 case MSG_EXTENDED: 2929 { 2930 /* Wait for enough of the message to begin validation */ 2931 if (ahc->msgin_index < 2) 2932 break; 2933 switch (ahc->msgin_buf[2]) { 2934 case MSG_EXT_SDTR: 2935 { 2936 const struct ahc_syncrate *syncrate; 2937 u_int period; 2938 u_int offset; 2939 u_int saved_offset; 2940 2941 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2942 reject = TRUE; 2943 break; 2944 } 2945 2946 /* 2947 * Wait until we have both args before validating 2948 * and acting on this message. 2949 * 2950 * Add one to MSG_EXT_SDTR_LEN to account for 2951 * the extended message preamble. 2952 */ 2953 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2954 break; 2955 2956 period = ahc->msgin_buf[3]; 2957 saved_offset = offset = ahc->msgin_buf[4]; 2958 syncrate = ahc_devlimited_syncrate(ahc, &period); 2959 ahc_validate_offset(ahc, syncrate, &offset, 2960 targ_scsirate & WIDEXFER); 2961 ahc_set_syncrate(ahc, devinfo, 2962 syncrate, period, offset, 2963 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2964 /*paused*/TRUE, /*done*/TRUE); 2965 ahc_update_xfer_mode(ahc, devinfo); 2966 2967 /* 2968 * See if we initiated Sync Negotiation 2969 * and didn't have to fall down to async 2970 * transfers. 2971 */ 2972 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2973 /* We started it */ 2974 if (saved_offset != offset) { 2975 /* Went too low - force async */ 2976 reject = TRUE; 2977 } 2978 } else { 2979 /* 2980 * Send our own SDTR in reply 2981 */ 2982 ahc->msgout_index = 0; 2983 ahc->msgout_len = 0; 2984 ahc_construct_sdtr(ahc, period, offset); 2985 ahc->msgout_index = 0; 2986 response = TRUE; 2987 } 2988 done = MSGLOOP_MSGCOMPLETE; 2989 break; 2990 } 2991 case MSG_EXT_WDTR: 2992 { 2993 u_int bus_width; 2994 u_int sending_reply; 2995 2996 sending_reply = FALSE; 2997 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2998 reject = TRUE; 2999 break; 3000 } 3001 3002 /* 3003 * Wait until we have our arg before validating 3004 * and acting on this message. 3005 * 3006 * Add one to MSG_EXT_WDTR_LEN to account for 3007 * the extended message preamble. 3008 */ 3009 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3010 break; 3011 3012 bus_width = ahc->msgin_buf[3]; 3013 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3014 /* 3015 * Don't send a WDTR back to the 3016 * target, since we asked first. 3017 */ 3018 switch (bus_width){ 3019 default: 3020 /* 3021 * How can we do anything greater 3022 * than 16bit transfers on a 16bit 3023 * bus? 3024 */ 3025 reject = TRUE; 3026 printf("%s: target %d requested %dBit " 3027 "transfers. Rejecting...\n", 3028 ahc_name(ahc), devinfo->target, 3029 8 * (0x01 << bus_width)); 3030 /* FALLTHROUGH */ 3031 case MSG_EXT_WDTR_BUS_8_BIT: 3032 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3033 break; 3034 case MSG_EXT_WDTR_BUS_16_BIT: 3035 break; 3036 } 3037 } else { 3038 /* 3039 * Send our own WDTR in reply 3040 */ 3041 switch (bus_width) { 3042 default: 3043 if (ahc->features & AHC_WIDE) { 3044 /* Respond Wide */ 3045 bus_width = 3046 MSG_EXT_WDTR_BUS_16_BIT; 3047 break; 3048 } 3049 /* FALLTHROUGH */ 3050 case MSG_EXT_WDTR_BUS_8_BIT: 3051 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3052 break; 3053 } 3054 ahc->msgout_index = 0; 3055 ahc->msgout_len = 0; 3056 ahc_construct_wdtr(ahc, bus_width); 3057 ahc->msgout_index = 0; 3058 response = TRUE; 3059 sending_reply = TRUE; 3060 } 3061 ahc_set_width(ahc, devinfo, bus_width, 3062 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3063 /*paused*/TRUE, /*done*/TRUE); 3064 3065 /* After a wide message, we are async */ 3066 ahc_set_syncrate(ahc, devinfo, 3067 /*syncrate*/NULL, /*period*/0, 3068 /*offset*/0, AHC_TRANS_ACTIVE, 3069 /*paused*/TRUE, /*done*/FALSE); 3070 if (sending_reply == FALSE && reject == FALSE) { 3071 3072 if (tinfo->goal.period) { 3073 const struct ahc_syncrate *rate; 3074 u_int period; 3075 u_int offset; 3076 3077 /* Start the sync negotiation */ 3078 period = tinfo->goal.period; 3079 rate = ahc_devlimited_syncrate(ahc, 3080 &period); 3081 offset = tinfo->goal.offset; 3082 ahc_validate_offset(ahc, rate, &offset, 3083 tinfo->current.width); 3084 ahc->msgout_index = 0; 3085 ahc->msgout_len = 0; 3086 ahc_construct_sdtr(ahc, period, offset); 3087 ahc->msgout_index = 0; 3088 response = TRUE; 3089 } else 3090 ahc_update_xfer_mode(ahc, devinfo); 3091 } 3092 done = MSGLOOP_MSGCOMPLETE; 3093 break; 3094 } 3095 default: 3096 /* Unknown extended message. Reject it. */ 3097 reject = TRUE; 3098 break; 3099 } 3100 break; 3101 } 3102 case MSG_BUS_DEV_RESET: 3103 ahc_handle_devreset(ahc, devinfo, 3104 XS_RESET, "Bus Device Reset Received", 3105 /*verbose_level*/0); 3106 restart_sequencer(ahc); 3107 done = MSGLOOP_TERMINATED; 3108 break; 3109 case MSG_ABORT_TAG: 3110 case MSG_ABORT: 3111 case MSG_CLEAR_QUEUE: 3112 /* Target mode messages */ 3113 if (devinfo->role != ROLE_TARGET) { 3114 reject = TRUE; 3115 break; 3116 } 3117 #if AHC_TARGET_MODE 3118 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3119 devinfo->lun, 3120 ahc->msgin_buf[0] == MSG_ABORT_TAG 3121 ? SCB_LIST_NULL 3122 : ahc_inb(ahc, INITIATOR_TAG), 3123 ROLE_TARGET, XS_DRIVER_STUFFUP); 3124 3125 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3126 if (tstate != NULL) { 3127 struct tmode_lstate* lstate; 3128 3129 lstate = tstate->enabled_luns[devinfo->lun]; 3130 if (lstate != NULL) { 3131 ahc_queue_lstate_event(ahc, lstate, 3132 devinfo->our_scsiid, 3133 ahc->msgin_buf[0], 3134 /*arg*/0); 3135 ahc_send_lstate_events(ahc, lstate); 3136 } 3137 } 3138 done = MSGLOOP_MSGCOMPLETE; 3139 #else 3140 panic("ahc: got target mode message"); 3141 #endif 3142 break; 3143 case MSG_TERM_IO_PROC: 3144 default: 3145 reject = TRUE; 3146 break; 3147 } 3148 3149 if (reject) { 3150 /* 3151 * Setup to reject the message. 3152 */ 3153 ahc->msgout_index = 0; 3154 ahc->msgout_len = 1; 3155 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3156 done = MSGLOOP_MSGCOMPLETE; 3157 response = TRUE; 3158 } 3159 3160 if (done != MSGLOOP_IN_PROG && !response) 3161 /* Clear the outgoing message buffer */ 3162 ahc->msgout_len = 0; 3163 3164 return (done); 3165 } 3166 3167 static void 3168 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3169 { 3170 u_int scb_index; 3171 struct scb *scb; 3172 3173 scb_index = ahc_inb(ahc, SCB_TAG); 3174 scb = &ahc->scb_data->scbarray[scb_index]; 3175 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3176 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3177 /* 3178 * Ignore the message if we haven't 3179 * seen an appropriate data phase yet. 3180 */ 3181 } else { 3182 /* 3183 * If the residual occurred on the last 3184 * transfer and the transfer request was 3185 * expected to end on an odd count, do 3186 * nothing. Otherwise, subtract a byte 3187 * and update the residual count accordingly. 3188 */ 3189 u_int resid_sgcnt; 3190 3191 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3192 if (resid_sgcnt == 0 3193 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3194 /* 3195 * If the residual occurred on the last 3196 * transfer and the transfer request was 3197 * expected to end on an odd count, do 3198 * nothing. 3199 */ 3200 } else { 3201 u_int data_cnt; 3202 u_int32_t data_addr; 3203 u_int sg_index; 3204 3205 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3206 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3207 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3208 3209 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3210 | (ahc_inb(ahc, SHADDR + 2) << 16) 3211 | (ahc_inb(ahc, SHADDR + 1) << 8) 3212 | (ahc_inb(ahc, SHADDR)); 3213 3214 data_cnt += 1; 3215 data_addr -= 1; 3216 3217 sg_index = scb->sg_count - resid_sgcnt; 3218 3219 if (sg_index != 0 3220 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3221 u_int32_t sg_addr; 3222 3223 sg_index--; 3224 data_cnt = 1; 3225 data_addr = le32toh(scb->sg_list[sg_index].addr) 3226 + le32toh(scb->sg_list[sg_index].len) 3227 - 1; 3228 3229 /* 3230 * The physical address base points to the 3231 * second entry as it is always used for 3232 * calculating the "next S/G pointer". 3233 */ 3234 sg_addr = scb->sg_list_phys 3235 + (sg_index* sizeof(*scb->sg_list)); 3236 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3237 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3238 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3239 ahc_outb(ahc, SG_NEXT, sg_addr); 3240 } 3241 3242 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3243 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3244 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3245 3246 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3247 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3248 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3249 ahc_outb(ahc, SHADDR, data_addr); 3250 } 3251 } 3252 } 3253 3254 static void 3255 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3256 int status, char *message, 3257 int verbose_level) 3258 { 3259 int found; 3260 3261 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3262 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3263 status); 3264 3265 /* 3266 * Go back to async/narrow transfers and renegotiate. 3267 * ahc_set_width and ahc_set_syncrate can cope with NULL 3268 * paths. 3269 */ 3270 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3271 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3272 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3273 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3274 /*paused*/TRUE, /*done*/FALSE); 3275 ahc_update_xfer_mode(ahc, devinfo); 3276 3277 if (message != NULL && (verbose_level <= 0)) 3278 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3279 message, devinfo->channel, devinfo->target, found); 3280 } 3281 3282 /* 3283 * We have an scb which has been processed by the 3284 * adaptor, now we look to see how the operation 3285 * went. 3286 */ 3287 static void 3288 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3289 { 3290 struct scsipi_xfer *xs; 3291 struct scsipi_periph *periph; 3292 int requeue = 0; 3293 int target; 3294 3295 3296 xs = scb->xs; 3297 periph = xs->xs_periph; 3298 LIST_REMOVE(scb, plinks); 3299 3300 callout_stop(&scb->xs->xs_callout); 3301 3302 #ifdef AHC_DEBUG 3303 if (ahc_debug & AHC_SHOWCMDS) { 3304 scsipi_printaddr(periph); 3305 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3306 scb->hscb->tag); 3307 } 3308 #endif 3309 3310 target = periph->periph_target; 3311 3312 if (xs->datalen) { 3313 int op; 3314 3315 if (xs->xs_control & XS_CTL_DATA_IN) 3316 op = BUS_DMASYNC_POSTREAD; 3317 else 3318 op = BUS_DMASYNC_POSTWRITE; 3319 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3320 scb->dmamap->dm_mapsize, op); 3321 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3322 } 3323 3324 /* 3325 * Unbusy this target/channel/lun. 3326 * XXX if we are holding two commands per lun, 3327 * send the next command. 3328 */ 3329 if (!(scb->hscb->control & TAG_ENB)) 3330 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3331 3332 /* 3333 * If the recovery SCB completes, we have to be 3334 * out of our timeout. 3335 */ 3336 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3337 3338 struct scb *scbp; 3339 3340 /* 3341 * We were able to complete the command successfully, 3342 * so reinstate the timeouts for all other pending 3343 * commands. 3344 */ 3345 scbp = ahc->pending_ccbs.lh_first; 3346 while (scbp != NULL) { 3347 struct scsipi_xfer *txs = scbp->xs; 3348 3349 if (!(txs->xs_control & XS_CTL_POLL)) { 3350 callout_reset(&scbp->xs->xs_callout, 3351 (scbp->xs->timeout > 1000000) ? 3352 (scbp->xs->timeout / 1000) * hz : 3353 (scbp->xs->timeout * hz) / 1000, 3354 ahc_timeout, scbp); 3355 } 3356 scbp = LIST_NEXT(scbp, plinks); 3357 } 3358 3359 /* 3360 * Ensure that we didn't put a second instance of this 3361 * SCB into the QINFIFO. 3362 */ 3363 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3364 SCB_LUN(scb), scb->hscb->tag, 3365 ROLE_INITIATOR, /*status*/0, 3366 SEARCH_REMOVE); 3367 if (xs->error != XS_NOERROR) 3368 ahcsetccbstatus(xs, XS_TIMEOUT); 3369 scsipi_printaddr(xs->xs_periph); 3370 printf("no longer in timeout, status = %x\n", xs->status); 3371 } 3372 3373 if (xs->error != XS_NOERROR) { 3374 /* Don't clobber any existing error state */ 3375 } else if ((scb->flags & SCB_SENSE) != 0) { 3376 /* 3377 * We performed autosense retrieval. 3378 * 3379 * zero the sense data before having 3380 * the drive fill it. The SCSI spec mandates 3381 * that any untransferred data should be 3382 * assumed to be zero. Complete the 'bounce' 3383 * of sense information through buffers accessible 3384 * via bus-space by copying it into the clients 3385 * csio. 3386 */ 3387 memset(&xs->sense.scsi_sense, 0, sizeof(xs->sense.scsi_sense)); 3388 memcpy(&xs->sense.scsi_sense, 3389 &ahc->scb_data->sense[scb->hscb->tag], 3390 le32toh(scb->sg_list->len)); 3391 xs->error = XS_SENSE; 3392 } 3393 if (scb->flags & SCB_FREEZE_QUEUE) { 3394 scsipi_periph_thaw(periph, 1); 3395 scb->flags &= ~SCB_FREEZE_QUEUE; 3396 } 3397 3398 requeue = scb->flags & SCB_REQUEUE; 3399 ahcfreescb(ahc, scb); 3400 3401 if (requeue) { 3402 xs->error = XS_REQUEUE; 3403 } 3404 scsipi_done(xs); 3405 } 3406 3407 /* 3408 * Determine the number of SCBs available on the controller 3409 */ 3410 int 3411 ahc_probe_scbs(struct ahc_softc *ahc) { 3412 int i; 3413 3414 for (i = 0; i < AHC_SCB_MAX; i++) { 3415 ahc_outb(ahc, SCBPTR, i); 3416 ahc_outb(ahc, SCB_CONTROL, i); 3417 if (ahc_inb(ahc, SCB_CONTROL) != i) 3418 break; 3419 ahc_outb(ahc, SCBPTR, 0); 3420 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3421 break; 3422 } 3423 return (i); 3424 } 3425 3426 /* 3427 * Start the board, ready for normal operation 3428 */ 3429 int 3430 ahc_init(struct ahc_softc *ahc) 3431 { 3432 int max_targ = 15; 3433 int i; 3434 int term; 3435 u_int scsi_conf; 3436 u_int scsiseq_template; 3437 u_int ultraenb; 3438 u_int discenable; 3439 u_int tagenable; 3440 size_t driver_data_size; 3441 u_int32_t physaddr; 3442 3443 #ifdef AHC_PRINT_SRAM 3444 printf("Scratch Ram:"); 3445 for (i = 0x20; i < 0x5f; i++) { 3446 if (((i % 8) == 0) && (i != 0)) { 3447 printf ("\n "); 3448 } 3449 printf (" 0x%x", ahc_inb(ahc, i)); 3450 } 3451 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3452 for (i = 0x70; i < 0x7f; i++) { 3453 if (((i % 8) == 0) && (i != 0)) { 3454 printf ("\n "); 3455 } 3456 printf (" 0x%x", ahc_inb(ahc, i)); 3457 } 3458 } 3459 printf ("\n"); 3460 #endif 3461 3462 /* 3463 * Assume we have a board at this stage and it has been reset. 3464 */ 3465 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3466 ahc->our_id = ahc->our_id_b = 7; 3467 3468 /* 3469 * Default to allowing initiator operations. 3470 */ 3471 ahc->flags |= AHC_INITIATORMODE; 3472 3473 /* 3474 * DMA tag for our command fifos and other data in system memory 3475 * the card's sequencer must be able to access. For initiator 3476 * roles, we need to allocate space for the qinfifo, qoutfifo, 3477 * and untagged_scb arrays each of which are composed of 256 3478 * 1 byte elements. When providing for the target mode role, 3479 * we additionally must provide space for the incoming target 3480 * command fifo. 3481 */ 3482 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3483 3484 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3485 ahc->sc_dmaflags, 3486 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3487 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3488 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3489 return (ENOMEM); 3490 3491 ahc->init_level++; 3492 3493 /* Allocate SCB data now that parent_dmat is initialized */ 3494 if (ahc->scb_data->maxhscbs == 0) 3495 if (ahcinitscbdata(ahc) != 0) 3496 return (ENOMEM); 3497 3498 ahc->qinfifo = &ahc->qoutfifo[256]; 3499 ahc->untagged_scbs = &ahc->qinfifo[256]; 3500 /* There are no untagged SCBs active yet. */ 3501 for (i = 0; i < 256; i++) 3502 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3503 3504 /* All of our queues are empty */ 3505 for (i = 0; i < 256; i++) 3506 ahc->qoutfifo[i] = SCB_LIST_NULL; 3507 3508 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3509 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3510 3511 /* 3512 * Allocate a tstate to house information for our 3513 * initiator presence on the bus as well as the user 3514 * data for any target mode initiator. 3515 */ 3516 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3517 printf("%s: unable to allocate tmode_tstate. " 3518 "Failing attach\n", ahc_name(ahc)); 3519 return (-1); 3520 } 3521 3522 if ((ahc->features & AHC_TWIN) != 0) { 3523 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3524 printf("%s: unable to allocate tmode_tstate. " 3525 "Failing attach\n", ahc_name(ahc)); 3526 return (-1); 3527 } 3528 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3529 ahc->our_id, ahc->our_id_b, 3530 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3531 } else { 3532 if ((ahc->features & AHC_WIDE) != 0) { 3533 printf("Wide "); 3534 } else { 3535 printf("Single "); 3536 } 3537 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3538 } 3539 3540 ahc_outb(ahc, SEQ_FLAGS, 0); 3541 3542 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3543 ahc->flags |= AHC_PAGESCBS; 3544 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3545 } else { 3546 ahc->flags &= ~AHC_PAGESCBS; 3547 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3548 } 3549 3550 #ifdef AHC_DEBUG 3551 if (ahc_debug & AHC_SHOWMISC) { 3552 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 3553 "ahc_dma %lu bytes\n", 3554 ahc_name(ahc), 3555 (unsigned long) sizeof(struct hardware_scb), 3556 (unsigned long) sizeof(struct scb), 3557 (unsigned long) sizeof(struct ahc_dma_seg)); 3558 } 3559 #endif /* AHC_DEBUG */ 3560 3561 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3562 if (ahc->features & AHC_TWIN) { 3563 3564 /* 3565 * The device is gated to channel B after a chip reset, 3566 * so set those values first 3567 */ 3568 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3569 if ((ahc->features & AHC_ULTRA2) != 0) 3570 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3571 else 3572 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3573 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3574 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3575 |term|ENSTIMER|ACTNEGEN); 3576 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3577 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3578 3579 if ((scsi_conf & RESET_SCSI) != 0 3580 && (ahc->flags & AHC_INITIATORMODE) != 0) 3581 ahc->flags |= AHC_RESET_BUS_B; 3582 3583 /* Select Channel A */ 3584 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3585 } 3586 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3587 if ((ahc->features & AHC_ULTRA2) != 0) 3588 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3589 else 3590 ahc_outb(ahc, SCSIID, ahc->our_id); 3591 scsi_conf = ahc_inb(ahc, SCSICONF); 3592 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3593 |term 3594 |ENSTIMER|ACTNEGEN); 3595 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3596 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3597 3598 if ((scsi_conf & RESET_SCSI) != 0 3599 && (ahc->flags & AHC_INITIATORMODE) != 0) 3600 ahc->flags |= AHC_RESET_BUS_A; 3601 3602 /* 3603 * Look at the information that board initialization or 3604 * the board bios has left us. 3605 */ 3606 ultraenb = 0; 3607 tagenable = ALL_TARGETS_MASK; 3608 3609 /* Grab the disconnection disable table and invert it for our needs */ 3610 if (ahc->flags & AHC_USEDEFAULTS) { 3611 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3612 "device parameters\n", ahc_name(ahc)); 3613 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3614 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3615 discenable = ALL_TARGETS_MASK; 3616 if ((ahc->features & AHC_ULTRA) != 0) 3617 ultraenb = ALL_TARGETS_MASK; 3618 } else { 3619 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3620 | ahc_inb(ahc, DISC_DSB)); 3621 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3622 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3623 | ahc_inb(ahc, ULTRA_ENB); 3624 } 3625 3626 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3627 max_targ = 7; 3628 3629 for (i = 0; i <= max_targ; i++) { 3630 struct ahc_initiator_tinfo *tinfo; 3631 struct tmode_tstate *tstate; 3632 u_int our_id; 3633 u_int target_id; 3634 char channel; 3635 3636 channel = 'A'; 3637 our_id = ahc->our_id; 3638 target_id = i; 3639 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3640 channel = 'B'; 3641 our_id = ahc->our_id_b; 3642 target_id = i % 8; 3643 } 3644 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3645 target_id, &tstate); 3646 /* Default to async narrow across the board */ 3647 memset(tinfo, 0, sizeof(*tinfo)); 3648 if (ahc->flags & AHC_USEDEFAULTS) { 3649 if ((ahc->features & AHC_WIDE) != 0) 3650 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3651 3652 /* 3653 * These will be truncated when we determine the 3654 * connection type we have with the target. 3655 */ 3656 tinfo->user.period = ahc_syncrates->period; 3657 tinfo->user.offset = ~0; 3658 } else { 3659 u_int scsirate; 3660 u_int16_t mask; 3661 3662 /* Take the settings leftover in scratch RAM. */ 3663 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3664 mask = (0x01 << i); 3665 if ((ahc->features & AHC_ULTRA2) != 0) { 3666 u_int offset; 3667 u_int maxsync; 3668 3669 if ((scsirate & SOFS) == 0x0F) { 3670 /* 3671 * Haven't negotiated yet, 3672 * so the format is different. 3673 */ 3674 scsirate = (scsirate & SXFR) >> 4 3675 | (ultraenb & mask) 3676 ? 0x08 : 0x0 3677 | (scsirate & WIDEXFER); 3678 offset = MAX_OFFSET_ULTRA2; 3679 } else 3680 offset = ahc_inb(ahc, TARG_OFFSET + i); 3681 maxsync = AHC_SYNCRATE_ULTRA2; 3682 if ((ahc->features & AHC_DT) != 0) 3683 maxsync = AHC_SYNCRATE_DT; 3684 tinfo->user.period = 3685 ahc_find_period(ahc, scsirate, maxsync); 3686 if (offset == 0) 3687 tinfo->user.period = 0; 3688 else 3689 tinfo->user.offset = ~0; 3690 } else if ((scsirate & SOFS) != 0) { 3691 tinfo->user.period = 3692 ahc_find_period(ahc, scsirate, 3693 (ultraenb & mask) 3694 ? AHC_SYNCRATE_ULTRA 3695 : AHC_SYNCRATE_FAST); 3696 if (tinfo->user.period != 0) 3697 tinfo->user.offset = ~0; 3698 } 3699 if ((scsirate & WIDEXFER) != 0 3700 && (ahc->features & AHC_WIDE) != 0) 3701 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3702 } 3703 tinfo->goal = tinfo->user; /* force negotiation */ 3704 tstate->ultraenb = ultraenb; 3705 tstate->discenable = discenable; 3706 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3707 tstate->tagdisable = 0; 3708 } 3709 ahc->user_discenable = discenable; 3710 ahc->user_tagenable = tagenable; 3711 3712 /* 3713 * Tell the sequencer where it can find our arrays in memory. 3714 */ 3715 physaddr = ahc->scb_data->hscb_busaddr; 3716 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3717 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3718 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3719 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3720 3721 physaddr = ahc->shared_data_busaddr; 3722 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3723 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3724 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3725 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3726 3727 /* Target mode incomding command fifo */ 3728 physaddr += 3 * 256 * sizeof(u_int8_t); 3729 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3730 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3731 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3732 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3733 3734 /* 3735 * Initialize the group code to command length table. 3736 * This overrides the values in TARG_SCSIRATE, so only 3737 * setup the table after we have processed that information. 3738 */ 3739 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3740 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3741 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3742 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3743 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3744 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3745 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3746 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3747 3748 /* Tell the sequencer of our initial queue positions */ 3749 ahc_outb(ahc, KERNEL_QINPOS, 0); 3750 ahc_outb(ahc, QINPOS, 0); 3751 ahc_outb(ahc, QOUTPOS, 0); 3752 3753 #ifdef AHC_DEBUG 3754 if (ahc_debug & AHC_SHOWMISC) 3755 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3756 discenable, ultraenb); 3757 #endif 3758 3759 /* Don't have any special messages to send to targets */ 3760 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3761 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3762 3763 /* 3764 * Use the built in queue management registers 3765 * if they are available. 3766 */ 3767 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3768 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3769 ahc_outb(ahc, SDSCB_QOFF, 0); 3770 ahc_outb(ahc, SNSCB_QOFF, 0); 3771 ahc_outb(ahc, HNSCB_QOFF, 0); 3772 } 3773 3774 3775 /* We don't have any waiting selections */ 3776 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3777 3778 /* Our disconnection list is empty too */ 3779 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3780 3781 /* Message out buffer starts empty */ 3782 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3783 3784 /* 3785 * Setup the allowed SCSI Sequences based on operational mode. 3786 * If we are a target, we'll enable select in operations once 3787 * we've had a lun enabled. 3788 */ 3789 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3790 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3791 scsiseq_template |= ENRSELI; 3792 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3793 3794 /* 3795 * Load the Sequencer program and Enable the adapter 3796 * in "fast" mode. 3797 */ 3798 #ifdef AHC_DEBUG 3799 printf("%s: Downloading Sequencer Program...", 3800 ahc_name(ahc)); 3801 #endif 3802 3803 ahc_loadseq(ahc); 3804 3805 /* We have to wait until after any system dumps... */ 3806 shutdownhook_establish(ahc_shutdown, ahc); 3807 3808 return (0); 3809 } 3810 3811 static int 3812 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3813 struct proc *p) 3814 { 3815 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3816 int s, ret = ENOTTY; 3817 3818 switch (cmd) { 3819 case SCBUSIORESET: 3820 s = splbio(); 3821 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3822 TRUE); 3823 splx(s); 3824 ret = 0; 3825 break; 3826 default: 3827 break; 3828 } 3829 3830 return ret; 3831 } 3832 3833 3834 /* 3835 * XXX fvdl the busy_tcl checks and settings should only be done 3836 * for the non-tagged queueing case, but we don't do tagged queueing 3837 * yet, so.. 3838 */ 3839 static void 3840 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3841 { 3842 struct scsipi_xfer *xs; 3843 struct scsipi_periph *periph; 3844 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3845 struct scb *scb; 3846 struct hardware_scb *hscb; 3847 struct ahc_initiator_tinfo *tinfo; 3848 struct tmode_tstate *tstate; 3849 u_int target_id; 3850 u_int our_id; 3851 int s, tcl; 3852 u_int16_t mask; 3853 char channel; 3854 3855 switch (req) { 3856 case ADAPTER_REQ_RUN_XFER: 3857 xs = arg; 3858 periph = xs->xs_periph; 3859 3860 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("ahc_action\n")); 3861 3862 /* must protect the queue */ 3863 s = splbio(); 3864 3865 tcl = XS_TCL(ahc, xs); 3866 3867 if (!ahc_istagged_device(ahc, xs, 0) && 3868 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3869 panic("ahc_action: not tagged and device busy"); 3870 } 3871 3872 3873 target_id = periph->periph_target; 3874 our_id = SIM_SCSI_ID(ahc, periph); 3875 3876 /* 3877 * get an scb to use. 3878 */ 3879 if ((scb = ahcgetscb(ahc)) == NULL) { 3880 xs->error = XS_RESOURCE_SHORTAGE; 3881 scsipi_done(xs); 3882 splx(s); 3883 return; 3884 } 3885 3886 tcl = XS_TCL(ahc, xs); 3887 3888 #ifdef DIAGNOSTIC 3889 if (!ahc_istagged_device(ahc, xs, 0) && 3890 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3891 panic("ahc: queuing for busy target"); 3892 #endif 3893 3894 scb->xs = xs; 3895 hscb = scb->hscb; 3896 hscb->tcl = tcl; 3897 3898 if (xs->xs_tag_type) { 3899 #ifdef DIAGNOSTIC 3900 if (ahc_istagged_device(ahc, xs, 0) == 0) 3901 panic("ahc_action: taggged command for untagged device"); 3902 #endif 3903 scb->hscb->control |= TAG_ENB; 3904 } else 3905 ahc_busy_tcl(ahc, scb); 3906 3907 splx(s); 3908 3909 channel = SIM_CHANNEL(ahc, periph); 3910 if (ahc->inited_channels[channel - 'A'] == 0) { 3911 if ((channel == 'A' && 3912 (ahc->flags & AHC_RESET_BUS_A)) || 3913 (channel == 'B' && 3914 (ahc->flags & AHC_RESET_BUS_B))) { 3915 s = splbio(); 3916 ahc_reset_channel(ahc, channel, TRUE); 3917 splx(s); 3918 } 3919 ahc->inited_channels[channel - 'A'] = 1; 3920 } 3921 3922 /* 3923 * Put all the arguments for the xfer in the scb 3924 */ 3925 3926 mask = SCB_TARGET_MASK(scb); 3927 tinfo = ahc_fetch_transinfo(ahc, 3928 SIM_CHANNEL(ahc, periph), 3929 our_id, target_id, &tstate); 3930 if (ahc->inited_targets[target_id] == 0) { 3931 struct ahc_devinfo devinfo; 3932 s = splbio(); 3933 ahc_compile_devinfo(&devinfo, our_id, target_id, 3934 periph->periph_lun, 3935 SIM_CHANNEL(ahc, periph), 3936 ROLE_INITIATOR); 3937 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3938 TRUE, FALSE); 3939 ahc->inited_targets[target_id] = 1; 3940 splx(s); 3941 } 3942 hscb->scsirate = tinfo->scsirate; 3943 hscb->scsioffset = tinfo->current.offset; 3944 if ((tstate->ultraenb & mask) != 0) 3945 hscb->control |= ULTRAENB; 3946 3947 if ((tstate->discenable & mask) != 0) 3948 hscb->control |= DISCENB; 3949 3950 if (xs->xs_control & XS_CTL_RESET) { 3951 hscb->cmdpointer = 0; 3952 scb->flags |= SCB_DEVICE_RESET; 3953 hscb->control |= MK_MESSAGE; 3954 ahc_execute_scb(scb, NULL, 0); 3955 } 3956 3957 ahc_setup_data(ahc, xs, scb); 3958 return; 3959 case ADAPTER_REQ_GROW_RESOURCES: 3960 /* XXX not supported */ 3961 return; 3962 case ADAPTER_REQ_SET_XFER_MODE: 3963 { 3964 struct scsipi_xfer_mode *xm = arg; 3965 struct ahc_devinfo devinfo; 3966 int target_id, our_id; 3967 char channel; 3968 3969 target_id = xm->xm_target; 3970 our_id = chan->chan_id; 3971 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 3972 s = splbio(); 3973 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 3974 &tstate); 3975 ahc_compile_devinfo(&devinfo, our_id, target_id, 3976 0, channel, ROLE_INITIATOR); 3977 ahc->inited_targets[target_id] = 2; 3978 if (xm->xm_mode & PERIPH_CAP_TQING && 3979 (tstate->tagdisable & devinfo.target_mask) == 0) { 3980 ahc_set_tags(ahc, &devinfo, TRUE); 3981 } 3982 splx(s); 3983 ahc_update_xfer_mode(ahc, &devinfo); 3984 } 3985 } 3986 } 3987 3988 static void 3989 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 3990 { 3991 struct scb *scb; 3992 struct scsipi_xfer *xs; 3993 struct ahc_softc *ahc; 3994 int s; 3995 3996 scb = (struct scb *)arg; 3997 xs = scb->xs; 3998 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 3999 4000 4001 if (nsegments != 0) { 4002 struct ahc_dma_seg *sg; 4003 bus_dma_segment_t *end_seg; 4004 int op; 4005 4006 end_seg = dm_segs + nsegments; 4007 4008 /* Copy the first SG into the data pointer area */ 4009 scb->hscb->data = dm_segs->ds_addr; 4010 scb->hscb->datalen = dm_segs->ds_len; 4011 4012 /* Copy the segments into our SG list */ 4013 sg = scb->sg_list; 4014 while (dm_segs < end_seg) { 4015 sg->addr = dm_segs->ds_addr; 4016 sg->len = dm_segs->ds_len; 4017 ahc_swap_sg(sg); 4018 sg++; 4019 dm_segs++; 4020 } 4021 4022 /* Note where to find the SG entries in bus space */ 4023 scb->hscb->SG_pointer = scb->sg_list_phys; 4024 4025 if (xs->xs_control & XS_CTL_DATA_IN) 4026 op = BUS_DMASYNC_PREREAD; 4027 else 4028 op = BUS_DMASYNC_PREWRITE; 4029 4030 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4031 scb->dmamap->dm_mapsize, op); 4032 4033 } else { 4034 scb->hscb->SG_pointer = 0; 4035 scb->hscb->data = 0; 4036 scb->hscb->datalen = 0; 4037 } 4038 4039 scb->sg_count = scb->hscb->SG_count = nsegments; 4040 4041 s = splbio(); 4042 4043 /* 4044 * Last time we need to check if this SCB needs to 4045 * be aborted. 4046 */ 4047 if (xs->xs_status & XS_STS_DONE) { 4048 if (!ahc_istagged_device(ahc, xs, 0)) 4049 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4050 if (nsegments != 0) 4051 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4052 ahcfreescb(ahc, scb); 4053 splx(s); 4054 return; 4055 } 4056 4057 #ifdef DIAGNOSTIC 4058 if (scb->sg_count > 255) 4059 panic("ahc bad sg_count"); 4060 #endif 4061 4062 ahc_swap_hscb(scb->hscb); 4063 4064 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4065 4066 scb->flags |= SCB_ACTIVE; 4067 4068 if (!(xs->xs_control & XS_CTL_POLL)) 4069 callout_reset(&scb->xs->xs_callout, xs->timeout > 1000000 ? 4070 (xs->timeout / 1000) * hz : (xs->timeout * hz) / 1000, 4071 ahc_timeout, scb); 4072 4073 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4074 #if 0 4075 printf("Continueing Immediate Command %d:%d\n", 4076 xs->xs_periph->periph_target, 4077 xs->xs_periph->periph_lun); 4078 #endif 4079 pause_sequencer(ahc); 4080 if ((ahc->flags & AHC_PAGESCBS) == 0) 4081 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4082 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4083 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4084 unpause_sequencer(ahc); 4085 } else { 4086 4087 #if 0 4088 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4089 scb->hscb->tag, ahc->qinfifonext, 4090 &ahc->qinfifo[ahc->qinfifonext], 4091 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4092 #endif 4093 4094 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4095 4096 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4097 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4098 4099 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4100 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4101 } else { 4102 pause_sequencer(ahc); 4103 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4104 unpause_sequencer(ahc); 4105 } 4106 } 4107 4108 #ifdef AHC_DEBUG 4109 if (ahc_debug & AHC_SHOWCMDS) { 4110 scsi_print_addr(xs->xs_periph); 4111 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4112 " rate %x\n", 4113 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4114 scb->flags, scb->hscb->control, ahc->qinfifonext, 4115 scb->hscb->scsirate); 4116 } 4117 #endif 4118 4119 if (!(xs->xs_control & XS_CTL_POLL)) { 4120 splx(s); 4121 return; 4122 } 4123 /* 4124 * If we can't use interrupts, poll for completion 4125 */ 4126 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("cmd_poll\n")); 4127 do { 4128 if (ahc_poll(ahc, xs->timeout)) { 4129 if (!(xs->xs_control & XS_CTL_SILENT)) 4130 printf("cmd fail\n"); 4131 ahc_timeout(scb); 4132 break; 4133 } 4134 } while (!(xs->xs_status & XS_STS_DONE)); 4135 splx(s); 4136 return; 4137 } 4138 4139 static int 4140 ahc_poll(struct ahc_softc *ahc, int wait) 4141 { 4142 while (--wait) { 4143 DELAY(1000); 4144 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4145 break; 4146 } 4147 4148 if (wait == 0) { 4149 printf("%s: board is not responding\n", ahc_name(ahc)); 4150 return (EIO); 4151 } 4152 4153 ahc_intr((void *)ahc); 4154 return (0); 4155 } 4156 4157 static void 4158 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4159 struct scb *scb) 4160 { 4161 struct hardware_scb *hscb; 4162 4163 hscb = scb->hscb; 4164 xs->resid = xs->status = 0; 4165 4166 hscb->cmdlen = xs->cmdlen; 4167 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4168 hscb->cmdpointer = hscb->cmdstore_busaddr; 4169 4170 /* Only use S/G if there is a transfer */ 4171 if (xs->datalen) { 4172 int error; 4173 4174 error = bus_dmamap_load(ahc->parent_dmat, 4175 scb->dmamap, xs->data, 4176 xs->datalen, NULL, 4177 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4178 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4179 BUS_DMA_STREAMING | 4180 ((xs->xs_control & XS_CTL_DATA_IN) ? 4181 BUS_DMA_READ : BUS_DMA_WRITE)); 4182 if (error) { 4183 #ifdef AHC_DEBUG 4184 printf("%s: in ahc_setup_data(): bus_dmamap_load() " 4185 "= %d\n", 4186 ahc_name(ahc), 4187 error); 4188 #endif 4189 if (!ahc_istagged_device(ahc, xs, 0)) 4190 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4191 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4192 scsipi_done(xs); 4193 return; 4194 } 4195 ahc_execute_scb(scb, 4196 scb->dmamap->dm_segs, 4197 scb->dmamap->dm_nsegs); 4198 } else { 4199 ahc_execute_scb(scb, NULL, 0); 4200 } 4201 } 4202 4203 static void 4204 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4205 { 4206 int target; 4207 char channel; 4208 int lun; 4209 4210 target = periph->periph_target; 4211 lun = periph->periph_lun; 4212 channel = periph->periph_channel->chan_channel; 4213 4214 ahc_search_qinfifo(ahc, target, channel, lun, 4215 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4216 SCB_REQUEUE, SEARCH_COMPLETE); 4217 } 4218 4219 static void 4220 ahcallocscbs(struct ahc_softc *ahc) 4221 { 4222 struct scb_data *scb_data; 4223 struct scb *next_scb; 4224 struct sg_map_node *sg_map; 4225 bus_addr_t physaddr; 4226 struct ahc_dma_seg *segs; 4227 int newcount; 4228 int i; 4229 4230 scb_data = ahc->scb_data; 4231 if (scb_data->numscbs >= AHC_SCB_MAX) 4232 /* Can't allocate any more */ 4233 return; 4234 4235 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4236 4237 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4238 4239 if (sg_map == NULL) 4240 return; 4241 4242 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4243 &sg_map->sg_dmamap, 4244 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4245 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4246 "SG space") < 0) { 4247 free(sg_map, M_DEVBUF); 4248 return; 4249 } 4250 4251 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4252 4253 segs = sg_map->sg_vaddr; 4254 physaddr = sg_map->sg_physaddr; 4255 4256 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4257 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4258 int error; 4259 4260 next_scb->sg_list = segs; 4261 /* 4262 * The sequencer always starts with the second entry. 4263 * The first entry is embedded in the scb. 4264 */ 4265 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4266 next_scb->flags = SCB_FREE; 4267 error = bus_dmamap_create(ahc->parent_dmat, 4268 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4269 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4270 &next_scb->dmamap); 4271 if (error != 0) 4272 break; 4273 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4274 next_scb->hscb->tag = ahc->scb_data->numscbs; 4275 next_scb->hscb->cmdstore_busaddr = 4276 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4277 + offsetof(struct hardware_scb, cmdstore); 4278 next_scb->hscb->cmdstore_busaddr = 4279 htole32(next_scb->hscb->cmdstore_busaddr); 4280 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4281 segs += AHC_NSEG; 4282 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4283 next_scb++; 4284 ahc->scb_data->numscbs++; 4285 } 4286 #ifdef AHC_DEBUG 4287 if (ahc_debug & AHC_SHOWSCBALLOC) 4288 printf("%s: allocated %d new SCBs count now %d\n", 4289 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4290 #endif 4291 } 4292 4293 #ifdef AHC_DUMP_SEQ 4294 static void 4295 ahc_dumpseq(struct ahc_softc* ahc) 4296 { 4297 int i; 4298 int max_prog; 4299 4300 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4301 max_prog = 448; 4302 else if ((ahc->features & AHC_ULTRA2) != 0) 4303 max_prog = 768; 4304 else 4305 max_prog = 512; 4306 4307 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4308 ahc_outb(ahc, SEQADDR0, 0); 4309 ahc_outb(ahc, SEQADDR1, 0); 4310 for (i = 0; i < max_prog; i++) { 4311 u_int8_t ins_bytes[4]; 4312 4313 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4314 printf("0x%08x\n", ins_bytes[0] << 24 4315 | ins_bytes[1] << 16 4316 | ins_bytes[2] << 8 4317 | ins_bytes[3]); 4318 } 4319 } 4320 #endif 4321 4322 static void 4323 ahc_loadseq(struct ahc_softc *ahc) 4324 { 4325 const struct patch *cur_patch; 4326 int i; 4327 int downloaded; 4328 int skip_addr; 4329 u_int8_t download_consts[4]; 4330 4331 /* Setup downloadable constant table */ 4332 #if 0 4333 /* No downloaded constants are currently defined. */ 4334 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4335 #endif 4336 4337 cur_patch = patches; 4338 downloaded = 0; 4339 skip_addr = 0; 4340 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4341 ahc_outb(ahc, SEQADDR0, 0); 4342 ahc_outb(ahc, SEQADDR1, 0); 4343 4344 for (i = 0; i < sizeof(seqprog)/4; i++) { 4345 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4346 /* 4347 * Don't download this instruction as it 4348 * is in a patch that was removed. 4349 */ 4350 continue; 4351 } 4352 ahc_download_instr(ahc, i, download_consts); 4353 downloaded++; 4354 } 4355 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4356 restart_sequencer(ahc); 4357 4358 #ifdef AHC_DEBUG 4359 printf(" %d instructions downloaded\n", downloaded); 4360 #endif 4361 } 4362 4363 static int 4364 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4365 int start_instr, int *skip_addr) 4366 { 4367 const struct patch *cur_patch; 4368 const struct patch *last_patch; 4369 int num_patches; 4370 4371 num_patches = sizeof(patches)/sizeof(struct patch); 4372 last_patch = &patches[num_patches]; 4373 cur_patch = *start_patch; 4374 4375 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4376 4377 if (cur_patch->patch_func(ahc) == 0) { 4378 4379 /* Start rejecting code */ 4380 *skip_addr = start_instr + cur_patch->skip_instr; 4381 cur_patch += cur_patch->skip_patch; 4382 } else { 4383 /* Accepted this patch. Advance to the next 4384 * one and wait for our intruction pointer to 4385 * hit this point. 4386 */ 4387 cur_patch++; 4388 } 4389 } 4390 4391 *start_patch = cur_patch; 4392 if (start_instr < *skip_addr) 4393 /* Still skipping */ 4394 return (0); 4395 4396 return (1); 4397 } 4398 4399 static void 4400 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4401 { 4402 union ins_formats instr; 4403 struct ins_format1 *fmt1_ins; 4404 struct ins_format3 *fmt3_ins; 4405 u_int opcode; 4406 4407 /* Structure copy */ 4408 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4409 4410 instr.integer = le32toh(instr.integer); 4411 4412 fmt1_ins = &instr.format1; 4413 fmt3_ins = NULL; 4414 4415 /* Pull the opcode */ 4416 opcode = instr.format1.opcode; 4417 switch (opcode) { 4418 case AIC_OP_JMP: 4419 case AIC_OP_JC: 4420 case AIC_OP_JNC: 4421 case AIC_OP_CALL: 4422 case AIC_OP_JNE: 4423 case AIC_OP_JNZ: 4424 case AIC_OP_JE: 4425 case AIC_OP_JZ: 4426 { 4427 const struct patch *cur_patch; 4428 int address_offset; 4429 u_int address; 4430 int skip_addr; 4431 int i; 4432 4433 fmt3_ins = &instr.format3; 4434 address_offset = 0; 4435 address = fmt3_ins->address; 4436 cur_patch = patches; 4437 skip_addr = 0; 4438 4439 for (i = 0; i < address;) { 4440 4441 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4442 4443 if (skip_addr > i) { 4444 int end_addr; 4445 4446 end_addr = MIN(address, skip_addr); 4447 address_offset += end_addr - i; 4448 i = skip_addr; 4449 } else { 4450 i++; 4451 } 4452 } 4453 address -= address_offset; 4454 fmt3_ins->address = address; 4455 /* FALLTHROUGH */ 4456 } 4457 case AIC_OP_OR: 4458 case AIC_OP_AND: 4459 case AIC_OP_XOR: 4460 case AIC_OP_ADD: 4461 case AIC_OP_ADC: 4462 case AIC_OP_BMOV: 4463 if (fmt1_ins->parity != 0) { 4464 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4465 } 4466 fmt1_ins->parity = 0; 4467 /* FALLTHROUGH */ 4468 case AIC_OP_ROL: 4469 if ((ahc->features & AHC_ULTRA2) != 0) { 4470 int i, count; 4471 4472 /* Calculate odd parity for the instruction */ 4473 for (i = 0, count = 0; i < 31; i++) { 4474 u_int32_t mask; 4475 4476 mask = 0x01 << i; 4477 if ((instr.integer & mask) != 0) 4478 count++; 4479 } 4480 if ((count & 0x01) == 0) 4481 instr.format1.parity = 1; 4482 } else { 4483 /* Compress the instruction for older sequencers */ 4484 if (fmt3_ins != NULL) { 4485 instr.integer = 4486 fmt3_ins->immediate 4487 | (fmt3_ins->source << 8) 4488 | (fmt3_ins->address << 16) 4489 | (fmt3_ins->opcode << 25); 4490 } else { 4491 instr.integer = 4492 fmt1_ins->immediate 4493 | (fmt1_ins->source << 8) 4494 | (fmt1_ins->destination << 16) 4495 | (fmt1_ins->ret << 24) 4496 | (fmt1_ins->opcode << 25); 4497 } 4498 } 4499 instr.integer = htole32(instr.integer); 4500 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4501 break; 4502 default: 4503 panic("Unknown opcode encountered in seq program"); 4504 break; 4505 } 4506 } 4507 4508 static void 4509 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4510 { 4511 4512 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4513 struct scb *scbp; 4514 4515 scb->flags |= SCB_RECOVERY_SCB; 4516 4517 /* 4518 * Take all queued, but not sent SCBs out of the equation. 4519 * Also ensure that no new CCBs are queued to us while we 4520 * try to fix this problem. 4521 */ 4522 scsipi_channel_freeze(&ahc->sc_channel, 1); 4523 if (ahc->features & AHC_TWIN) 4524 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4525 4526 /* 4527 * Go through all of our pending SCBs and remove 4528 * any scheduled timeouts for them. We will reschedule 4529 * them after we've successfully fixed this problem. 4530 */ 4531 scbp = ahc->pending_ccbs.lh_first; 4532 while (scbp != NULL) { 4533 callout_stop(&scbp->xs->xs_callout); 4534 scbp = scbp->plinks.le_next; 4535 } 4536 } 4537 } 4538 4539 static void 4540 ahc_timeout(void *arg) 4541 { 4542 struct scb *scb; 4543 struct ahc_softc *ahc; 4544 int s, found; 4545 u_int last_phase; 4546 int target; 4547 int lun; 4548 int i; 4549 char channel; 4550 4551 scb = (struct scb *)arg; 4552 ahc = 4553 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4554 4555 s = splbio(); 4556 4557 /* 4558 * Ensure that the card doesn't do anything 4559 * behind our back. Also make sure that we 4560 * didn't "just" miss an interrupt that would 4561 * affect this timeout. 4562 */ 4563 do { 4564 ahc_intr(ahc); 4565 pause_sequencer(ahc); 4566 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4567 4568 if ((scb->flags & SCB_ACTIVE) == 0) { 4569 /* Previous timeout took care of me already */ 4570 printf("Timedout SCB handled by another timeout\n"); 4571 unpause_sequencer(ahc); 4572 splx(s); 4573 return; 4574 } 4575 4576 target = SCB_TARGET(scb); 4577 channel = SCB_CHANNEL(scb); 4578 lun = SCB_LUN(scb); 4579 4580 scsipi_printaddr(scb->xs->xs_periph); 4581 printf("SCB %x - timed out ", scb->hscb->tag); 4582 /* 4583 * Take a snapshot of the bus state and print out 4584 * some information so we can track down driver bugs. 4585 */ 4586 last_phase = ahc_inb(ahc, LASTPHASE); 4587 4588 for (i = 0; i < num_phases; i++) { 4589 if (last_phase == phase_table[i].phase) 4590 break; 4591 } 4592 printf("%s", phase_table[i].phasemsg); 4593 4594 printf(", SEQADDR == 0x%x\n", 4595 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4596 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4597 4598 #ifdef AHC_DEBUG 4599 ahc_print_scb(scb); 4600 #endif 4601 4602 #if 0 4603 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4604 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4605 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4606 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4607 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4608 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4609 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4610 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4611 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4612 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4613 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4614 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4615 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4616 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4617 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4618 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4619 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4620 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4621 if (scb->sg_count > 0) { 4622 for (i = 0; i < scb->sg_count; i++) { 4623 printf("sg[%d] - Addr 0x%x : Length %d\n", 4624 i, 4625 le32toh(scb->sg_list[i].addr), 4626 le32toh(scb->sg_list[i].len)); 4627 } 4628 } 4629 #endif 4630 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4631 /* 4632 * Been down this road before. 4633 * Do a full bus reset. 4634 */ 4635 bus_reset: 4636 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4637 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4638 printf("%s: Issued Channel %c Bus Reset. " 4639 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4640 } else { 4641 /* 4642 * If we are a target, transition to bus free and report 4643 * the timeout. 4644 * 4645 * The target/initiator that is holding up the bus may not 4646 * be the same as the one that triggered this timeout 4647 * (different commands have different timeout lengths). 4648 * If the bus is idle and we are actiing as the initiator 4649 * for this request, queue a BDR message to the timed out 4650 * target. Otherwise, if the timed out transaction is 4651 * active: 4652 * Initiator transaction: 4653 * Stuff the message buffer with a BDR message and assert 4654 * ATN in the hopes that the target will let go of the bus 4655 * and go to the mesgout phase. If this fails, we'll 4656 * get another timeout 2 seconds later which will attempt 4657 * a bus reset. 4658 * 4659 * Target transaction: 4660 * Transition to BUS FREE and report the error. 4661 * It's good to be the target! 4662 */ 4663 u_int active_scb_index; 4664 4665 active_scb_index = ahc_inb(ahc, SCB_TAG); 4666 4667 if (last_phase != P_BUSFREE 4668 && (active_scb_index < ahc->scb_data->numscbs)) { 4669 struct scb *active_scb; 4670 4671 /* 4672 * If the active SCB is not from our device, 4673 * assume that another device is hogging the bus 4674 * and wait for it's timeout to expire before 4675 * taking additional action. 4676 */ 4677 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4678 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4679 u_int newtimeout; 4680 4681 scsipi_printaddr(scb->xs->xs_periph); 4682 printf("Other SCB Timeout%s", 4683 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4684 ? " again\n" : "\n"); 4685 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4686 newtimeout = MAX(active_scb->xs->timeout, 4687 scb->xs->timeout); 4688 callout_reset(&scb->xs->xs_callout, 4689 newtimeout > 1000000 ? 4690 (newtimeout / 1000) * hz : 4691 (newtimeout * hz) / 1000, 4692 ahc_timeout, scb); 4693 splx(s); 4694 return; 4695 } 4696 4697 /* It's us */ 4698 if ((scb->hscb->control & TARGET_SCB) != 0) { 4699 4700 /* 4701 * Send back any queued up transactions 4702 * and properly record the error condition. 4703 */ 4704 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4705 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4706 ahc_freeze_ccb(scb); 4707 ahc_done(ahc, scb); 4708 4709 /* Will clear us from the bus */ 4710 restart_sequencer(ahc); 4711 splx(s); 4712 return; 4713 } 4714 4715 ahc_set_recoveryscb(ahc, active_scb); 4716 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4717 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4718 scsipi_printaddr(active_scb->xs->xs_periph); 4719 printf("BDR message in message buffer\n"); 4720 active_scb->flags |= SCB_DEVICE_RESET; 4721 callout_reset(&active_scb->xs->xs_callout, 4722 2 * hz, ahc_timeout, active_scb); 4723 unpause_sequencer(ahc); 4724 } else { 4725 int disconnected; 4726 4727 /* XXX Shouldn't panic. Just punt instead */ 4728 if ((scb->hscb->control & TARGET_SCB) != 0) 4729 panic("Timed-out target SCB but bus idle"); 4730 4731 if (last_phase != P_BUSFREE 4732 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4733 /* XXX What happened to the SCB? */ 4734 /* Hung target selection. Goto busfree */ 4735 printf("%s: Hung target selection\n", 4736 ahc_name(ahc)); 4737 restart_sequencer(ahc); 4738 splx(s); 4739 return; 4740 } 4741 4742 if (ahc_search_qinfifo(ahc, target, channel, lun, 4743 scb->hscb->tag, ROLE_INITIATOR, 4744 /*status*/0, SEARCH_COUNT) > 0) { 4745 disconnected = FALSE; 4746 } else { 4747 disconnected = TRUE; 4748 } 4749 4750 if (disconnected) { 4751 u_int active_scb; 4752 4753 ahc_set_recoveryscb(ahc, scb); 4754 /* 4755 * Simply set the MK_MESSAGE control bit. 4756 */ 4757 scb->hscb->control |= MK_MESSAGE; 4758 scb->flags |= SCB_QUEUED_MSG 4759 | SCB_DEVICE_RESET; 4760 4761 /* 4762 * Mark the cached copy of this SCB in the 4763 * disconnected list too, so that a reconnect 4764 * at this point causes a BDR or abort. 4765 */ 4766 active_scb = ahc_inb(ahc, SCBPTR); 4767 if (ahc_search_disc_list(ahc, target, 4768 channel, lun, 4769 scb->hscb->tag, 4770 /*stop_on_first*/TRUE, 4771 /*remove*/FALSE, 4772 /*save_state*/FALSE)) { 4773 u_int scb_control; 4774 4775 scb_control = ahc_inb(ahc, SCB_CONTROL); 4776 scb_control |= MK_MESSAGE; 4777 ahc_outb(ahc, SCB_CONTROL, scb_control); 4778 } 4779 ahc_outb(ahc, SCBPTR, active_scb); 4780 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4781 /*unbusy*/TRUE); 4782 4783 /* 4784 * Actually re-queue this SCB in case we can 4785 * select the device before it reconnects. 4786 * Clear out any entries in the QINFIFO first 4787 * so we are the next SCB for this target 4788 * to run. 4789 */ 4790 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4791 channel, SCB_LUN(scb), 4792 SCB_LIST_NULL, 4793 ROLE_INITIATOR, 4794 SCB_REQUEUE, 4795 SEARCH_COMPLETE); 4796 scsipi_printaddr(scb->xs->xs_periph); 4797 printf("Queuing a BDR SCB\n"); 4798 ahc->qinfifo[ahc->qinfifonext++] = 4799 scb->hscb->tag; 4800 4801 bus_dmamap_sync(ahc->parent_dmat, 4802 ahc->shared_data_dmamap, 4803 QINFIFO_OFFSET * 256, 256, 4804 BUS_DMASYNC_PREWRITE); 4805 4806 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4807 ahc_outb(ahc, HNSCB_QOFF, 4808 ahc->qinfifonext); 4809 } else { 4810 ahc_outb(ahc, KERNEL_QINPOS, 4811 ahc->qinfifonext); 4812 } 4813 callout_reset(&scb->xs->xs_callout, 2 * hz, 4814 ahc_timeout, scb); 4815 unpause_sequencer(ahc); 4816 } else { 4817 /* Go "immediatly" to the bus reset */ 4818 /* This shouldn't happen */ 4819 ahc_set_recoveryscb(ahc, scb); 4820 scsipi_printaddr(scb->xs->xs_periph); 4821 printf("SCB %x: Immediate reset. " 4822 "Flags = 0x%x\n", scb->hscb->tag, 4823 scb->flags); 4824 goto bus_reset; 4825 } 4826 } 4827 } 4828 splx(s); 4829 } 4830 4831 static int 4832 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4833 int lun, u_int tag, role_t role, scb_flag status, 4834 ahc_search_action action) 4835 { 4836 struct scb *scbp; 4837 u_int8_t qinpos; 4838 u_int8_t qintail; 4839 int found; 4840 4841 qinpos = ahc_inb(ahc, QINPOS); 4842 qintail = ahc->qinfifonext; 4843 found = 0; 4844 4845 /* 4846 * Start with an empty queue. Entries that are not chosen 4847 * for removal will be re-added to the queue as we go. 4848 */ 4849 ahc->qinfifonext = qinpos; 4850 4851 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4852 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4853 4854 while (qinpos != qintail) { 4855 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4856 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4857 /* 4858 * We found an scb that needs to be removed. 4859 */ 4860 switch (action) { 4861 case SEARCH_COMPLETE: 4862 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4863 scbp->flags |= status; 4864 scbp->xs->error = XS_NOERROR; 4865 } 4866 ahc_freeze_ccb(scbp); 4867 ahc_done(ahc, scbp); 4868 break; 4869 case SEARCH_COUNT: 4870 ahc->qinfifo[ahc->qinfifonext++] = 4871 scbp->hscb->tag; 4872 break; 4873 case SEARCH_REMOVE: 4874 break; 4875 } 4876 found++; 4877 } else { 4878 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4879 } 4880 qinpos++; 4881 } 4882 4883 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4884 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4885 4886 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4887 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4888 } else { 4889 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4890 } 4891 4892 return (found); 4893 } 4894 4895 /* 4896 * Abort all SCBs that match the given description (target/channel/lun/tag), 4897 * setting their status to the passed in status if the status has not already 4898 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4899 * is paused before it is called. 4900 */ 4901 static int 4902 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4903 int lun, u_int tag, role_t role, int status) 4904 { 4905 struct scb *scbp; 4906 u_int active_scb; 4907 int i; 4908 int found; 4909 4910 /* restore this when we're done */ 4911 active_scb = ahc_inb(ahc, SCBPTR); 4912 4913 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4914 role, SCB_REQUEUE, SEARCH_COMPLETE); 4915 4916 /* 4917 * Search waiting for selection list. 4918 */ 4919 { 4920 u_int8_t next, prev; 4921 4922 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4923 prev = SCB_LIST_NULL; 4924 4925 while (next != SCB_LIST_NULL) { 4926 u_int8_t scb_index; 4927 4928 ahc_outb(ahc, SCBPTR, next); 4929 scb_index = ahc_inb(ahc, SCB_TAG); 4930 if (scb_index >= ahc->scb_data->numscbs) { 4931 panic("Waiting List inconsistency. " 4932 "SCB index == %d, yet numscbs == %d.", 4933 scb_index, ahc->scb_data->numscbs); 4934 } 4935 scbp = &ahc->scb_data->scbarray[scb_index]; 4936 if (ahc_match_scb(scbp, target, channel, 4937 lun, SCB_LIST_NULL, role)) { 4938 4939 next = ahc_abort_wscb(ahc, next, prev); 4940 } else { 4941 4942 prev = next; 4943 next = ahc_inb(ahc, SCB_NEXT); 4944 } 4945 } 4946 } 4947 /* 4948 * Go through the disconnected list and remove any entries we 4949 * have queued for completion, 0'ing their control byte too. 4950 * We save the active SCB and restore it ourselves, so there 4951 * is no reason for this search to restore it too. 4952 */ 4953 ahc_search_disc_list(ahc, target, channel, lun, tag, 4954 /*stop_on_first*/FALSE, /*remove*/TRUE, 4955 /*save_state*/FALSE); 4956 4957 /* 4958 * Go through the hardware SCB array looking for commands that 4959 * were active but not on any list. 4960 */ 4961 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4962 u_int scbid; 4963 4964 ahc_outb(ahc, SCBPTR, i); 4965 scbid = ahc_inb(ahc, SCB_TAG); 4966 scbp = &ahc->scb_data->scbarray[scbid]; 4967 if (scbid < ahc->scb_data->numscbs 4968 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 4969 ahc_add_curscb_to_free_list(ahc); 4970 } 4971 4972 /* 4973 * Go through the pending CCB list and look for 4974 * commands for this target that are still active. 4975 * These are other tagged commands that were 4976 * disconnected when the reset occurred. 4977 */ 4978 { 4979 struct scb *scb; 4980 4981 scb = ahc->pending_ccbs.lh_first; 4982 while (scb != NULL) { 4983 scbp = scb; 4984 scb = scb->plinks.le_next; 4985 if (ahc_match_scb(scbp, target, channel, 4986 lun, tag, role)) { 4987 if (!(scbp->xs->xs_status & XS_STS_DONE)) 4988 ahcsetccbstatus(scbp->xs, status); 4989 ahc_freeze_ccb(scbp); 4990 ahc_done(ahc, scbp); 4991 found++; 4992 } 4993 } 4994 } 4995 ahc_outb(ahc, SCBPTR, active_scb); 4996 return found; 4997 } 4998 4999 static int 5000 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5001 int lun, u_int tag, int stop_on_first, int remove, 5002 int save_state) 5003 { 5004 struct scb *scbp; 5005 u_int next; 5006 u_int prev; 5007 u_int count; 5008 u_int active_scb; 5009 5010 count = 0; 5011 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5012 prev = SCB_LIST_NULL; 5013 5014 if (save_state) { 5015 /* restore this when we're done */ 5016 active_scb = ahc_inb(ahc, SCBPTR); 5017 } else 5018 /* Silence compiler */ 5019 active_scb = SCB_LIST_NULL; 5020 5021 while (next != SCB_LIST_NULL) { 5022 u_int scb_index; 5023 5024 ahc_outb(ahc, SCBPTR, next); 5025 scb_index = ahc_inb(ahc, SCB_TAG); 5026 if (scb_index >= ahc->scb_data->numscbs) { 5027 panic("Disconnected List inconsistency. " 5028 "SCB index == %d, yet numscbs == %d.", 5029 scb_index, ahc->scb_data->numscbs); 5030 } 5031 scbp = &ahc->scb_data->scbarray[scb_index]; 5032 if (ahc_match_scb(scbp, target, channel, lun, 5033 tag, ROLE_INITIATOR)) { 5034 count++; 5035 if (remove) { 5036 next = 5037 ahc_rem_scb_from_disc_list(ahc, prev, next); 5038 } else { 5039 prev = next; 5040 next = ahc_inb(ahc, SCB_NEXT); 5041 } 5042 if (stop_on_first) 5043 break; 5044 } else { 5045 prev = next; 5046 next = ahc_inb(ahc, SCB_NEXT); 5047 } 5048 } 5049 if (save_state) 5050 ahc_outb(ahc, SCBPTR, active_scb); 5051 return (count); 5052 } 5053 5054 static u_int 5055 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5056 { 5057 u_int next; 5058 5059 ahc_outb(ahc, SCBPTR, scbptr); 5060 next = ahc_inb(ahc, SCB_NEXT); 5061 5062 ahc_outb(ahc, SCB_CONTROL, 0); 5063 5064 ahc_add_curscb_to_free_list(ahc); 5065 5066 if (prev != SCB_LIST_NULL) { 5067 ahc_outb(ahc, SCBPTR, prev); 5068 ahc_outb(ahc, SCB_NEXT, next); 5069 } else 5070 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5071 5072 return (next); 5073 } 5074 5075 static void 5076 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5077 { 5078 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5079 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5080 5081 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5082 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5083 } 5084 5085 /* 5086 * Manipulate the waiting for selection list and return the 5087 * scb that follows the one that we remove. 5088 */ 5089 static u_int 5090 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5091 { 5092 u_int curscb, next; 5093 5094 /* 5095 * Select the SCB we want to abort and 5096 * pull the next pointer out of it. 5097 */ 5098 curscb = ahc_inb(ahc, SCBPTR); 5099 ahc_outb(ahc, SCBPTR, scbpos); 5100 next = ahc_inb(ahc, SCB_NEXT); 5101 5102 /* Clear the necessary fields */ 5103 ahc_outb(ahc, SCB_CONTROL, 0); 5104 5105 ahc_add_curscb_to_free_list(ahc); 5106 5107 /* update the waiting list */ 5108 if (prev == SCB_LIST_NULL) { 5109 /* First in the list */ 5110 ahc_outb(ahc, WAITING_SCBH, next); 5111 5112 /* 5113 * Ensure we aren't attempting to perform 5114 * selection for this entry. 5115 */ 5116 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5117 } else { 5118 /* 5119 * Select the scb that pointed to us 5120 * and update its next pointer. 5121 */ 5122 ahc_outb(ahc, SCBPTR, prev); 5123 ahc_outb(ahc, SCB_NEXT, next); 5124 } 5125 5126 /* 5127 * Point us back at the original scb position. 5128 */ 5129 ahc_outb(ahc, SCBPTR, curscb); 5130 return next; 5131 } 5132 5133 static void 5134 ahc_clear_intstat(struct ahc_softc *ahc) 5135 { 5136 /* Clear any interrupt conditions this may have caused */ 5137 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5138 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5139 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5140 CLRREQINIT); 5141 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5142 } 5143 5144 static void 5145 ahc_reset_current_bus(struct ahc_softc *ahc) 5146 { 5147 u_int8_t scsiseq; 5148 5149 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5150 scsiseq = ahc_inb(ahc, SCSISEQ); 5151 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5152 DELAY(AHC_BUSRESET_DELAY); 5153 /* Turn off the bus reset */ 5154 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5155 5156 ahc_clear_intstat(ahc); 5157 5158 /* Re-enable reset interrupts */ 5159 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5160 } 5161 5162 static int 5163 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5164 { 5165 u_int initiator, target, max_scsiid; 5166 u_int sblkctl; 5167 u_int our_id; 5168 int found; 5169 int restart_needed; 5170 char cur_channel; 5171 5172 ahc->pending_device = NULL; 5173 5174 pause_sequencer(ahc); 5175 5176 /* 5177 * Run our command complete fifos to ensure that we perform 5178 * completion processing on any commands that 'completed' 5179 * before the reset occurred. 5180 */ 5181 ahc_run_qoutfifo(ahc); 5182 5183 /* 5184 * Reset the bus if we are initiating this reset 5185 */ 5186 sblkctl = ahc_inb(ahc, SBLKCTL); 5187 cur_channel = 'A'; 5188 if ((ahc->features & AHC_TWIN) != 0 5189 && ((sblkctl & SELBUSB) != 0)) 5190 cur_channel = 'B'; 5191 if (cur_channel != channel) { 5192 /* Case 1: Command for another bus is active 5193 * Stealthily reset the other bus without 5194 * upsetting the current bus. 5195 */ 5196 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5197 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5198 ahc_outb(ahc, SCSISEQ, 5199 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5200 if (initiate_reset) 5201 ahc_reset_current_bus(ahc); 5202 ahc_clear_intstat(ahc); 5203 ahc_outb(ahc, SBLKCTL, sblkctl); 5204 restart_needed = FALSE; 5205 } else { 5206 /* Case 2: A command from this bus is active or we're idle */ 5207 ahc_clear_msg_state(ahc); 5208 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5209 ahc_outb(ahc, SCSISEQ, 5210 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5211 if (initiate_reset) 5212 ahc_reset_current_bus(ahc); 5213 ahc_clear_intstat(ahc); 5214 5215 /* 5216 * Since we are going to restart the sequencer, avoid 5217 * a race in the sequencer that could cause corruption 5218 * of our Q pointers by starting over from index 0. 5219 */ 5220 ahc->qoutfifonext = 0; 5221 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5222 ahc_outb(ahc, SDSCB_QOFF, 0); 5223 else 5224 ahc_outb(ahc, QOUTPOS, 0); 5225 restart_needed = TRUE; 5226 } 5227 5228 /* 5229 * Clean up all the state information for the 5230 * pending transactions on this bus. 5231 */ 5232 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5233 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5234 ROLE_UNKNOWN, XS_RESET); 5235 if (channel == 'B') { 5236 our_id = ahc->our_id_b; 5237 } else { 5238 our_id = ahc->our_id; 5239 } 5240 5241 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5242 5243 /* 5244 * Revert to async/narrow transfers until we renegotiate. 5245 */ 5246 for (target = 0; target <= max_scsiid; target++) { 5247 5248 if (ahc->enabled_targets[target] == NULL) 5249 continue; 5250 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5251 struct ahc_devinfo devinfo; 5252 5253 ahc_compile_devinfo(&devinfo, target, initiator, 5254 AHC_LUN_WILDCARD, 5255 channel, ROLE_UNKNOWN); 5256 ahc_set_width(ahc, &devinfo, 5257 MSG_EXT_WDTR_BUS_8_BIT, 5258 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5259 ahc_set_syncrate(ahc, &devinfo, 5260 /*syncrate*/NULL, /*period*/0, 5261 /*offset*/0, AHC_TRANS_CUR, 5262 /*paused*/TRUE, FALSE); 5263 ahc_update_xfer_mode(ahc, &devinfo); 5264 } 5265 } 5266 5267 if (restart_needed) 5268 restart_sequencer(ahc); 5269 else 5270 unpause_sequencer(ahc); 5271 return found; 5272 } 5273 5274 static int 5275 ahc_match_scb(struct scb *scb, int target, char channel, 5276 int lun, u_int tag, role_t role) 5277 { 5278 int targ = SCB_TARGET(scb); 5279 char chan = SCB_CHANNEL(scb); 5280 int slun = SCB_LUN(scb); 5281 int match; 5282 5283 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5284 if (match != 0) 5285 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5286 if (match != 0) 5287 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5288 5289 return match; 5290 } 5291 5292 static void 5293 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5294 { 5295 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5296 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5297 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5298 ahc->msgout_buf[ahc->msgout_index++] = period; 5299 ahc->msgout_buf[ahc->msgout_index++] = offset; 5300 ahc->msgout_len += 5; 5301 } 5302 5303 static void 5304 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5305 { 5306 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5307 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5308 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5309 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5310 ahc->msgout_len += 4; 5311 } 5312 5313 static void 5314 ahc_calc_residual(struct scb *scb) 5315 { 5316 struct hardware_scb *hscb; 5317 5318 hscb = scb->hscb; 5319 5320 /* 5321 * If the disconnected flag is still set, this is bogus 5322 * residual information left over from a sequencer 5323 * pagin/pageout, so ignore this case. 5324 */ 5325 if ((scb->hscb->control & DISCONNECTED) == 0) { 5326 u_int32_t resid; 5327 int resid_sgs; 5328 int sg; 5329 5330 /* 5331 * Remainder of the SG where the transfer 5332 * stopped. 5333 */ 5334 resid = (hscb->residual_data_count[2] << 16) 5335 | (hscb->residual_data_count[1] <<8) 5336 | (hscb->residual_data_count[0]); 5337 5338 /* 5339 * Add up the contents of all residual 5340 * SG segments that are after the SG where 5341 * the transfer stopped. 5342 */ 5343 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5344 sg = scb->sg_count - resid_sgs; 5345 while (resid_sgs > 0) { 5346 5347 resid += le32toh(scb->sg_list[sg].len); 5348 sg++; 5349 resid_sgs--; 5350 } 5351 scb->xs->resid = resid; 5352 } 5353 5354 /* 5355 * Clean out the residual information in this SCB for its 5356 * next consumer. 5357 */ 5358 hscb->residual_SG_count = 0; 5359 5360 #ifdef AHC_DEBUG 5361 if (ahc_debug & AHC_SHOWMISC) { 5362 scsipi_printaddr(scb->xs->xs_periph); 5363 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5364 } 5365 #endif 5366 } 5367 5368 static void 5369 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5370 { 5371 struct scb *scb; 5372 int pending_ccb_count; 5373 int i; 5374 u_int saved_scbptr; 5375 5376 /* 5377 * Traverse the pending SCB list and ensure that all of the 5378 * SCBs there have the proper settings. 5379 */ 5380 scb = LIST_FIRST(&ahc->pending_ccbs); 5381 pending_ccb_count = 0; 5382 while (scb != NULL) { 5383 struct ahc_devinfo devinfo; 5384 struct scsipi_xfer *xs; 5385 struct scb *pending_scb; 5386 struct hardware_scb *pending_hscb; 5387 struct ahc_initiator_tinfo *tinfo; 5388 struct tmode_tstate *tstate; 5389 u_int our_id, remote_id; 5390 5391 xs = scb->xs; 5392 pending_scb = scb; 5393 pending_hscb = pending_scb->hscb; 5394 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5395 ? ahc->our_id_b : ahc->our_id; 5396 remote_id = xs->xs_periph->periph_target; 5397 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5398 SCB_LUN(pending_scb), 5399 SCB_CHANNEL(pending_scb), 5400 ROLE_UNKNOWN); 5401 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5402 our_id, remote_id, &tstate); 5403 pending_hscb->control &= ~ULTRAENB; 5404 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5405 pending_hscb->control |= ULTRAENB; 5406 pending_hscb->scsirate = tinfo->scsirate; 5407 pending_hscb->scsioffset = tinfo->current.offset; 5408 pending_ccb_count++; 5409 scb = LIST_NEXT(scb, plinks); 5410 } 5411 5412 if (pending_ccb_count == 0) 5413 return; 5414 5415 saved_scbptr = ahc_inb(ahc, SCBPTR); 5416 /* Ensure that the hscbs down on the card match the new information */ 5417 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5418 u_int scb_tag; 5419 5420 ahc_outb(ahc, SCBPTR, i); 5421 scb_tag = ahc_inb(ahc, SCB_TAG); 5422 if (scb_tag != SCB_LIST_NULL) { 5423 struct ahc_devinfo devinfo; 5424 struct scb *pending_scb; 5425 struct scsipi_xfer *xs; 5426 struct hardware_scb *pending_hscb; 5427 struct ahc_initiator_tinfo *tinfo; 5428 struct tmode_tstate *tstate; 5429 u_int our_id, remote_id; 5430 u_int control; 5431 5432 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5433 if (pending_scb->flags == SCB_FREE) 5434 continue; 5435 pending_hscb = pending_scb->hscb; 5436 xs = pending_scb->xs; 5437 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5438 ? ahc->our_id_b : ahc->our_id; 5439 remote_id = xs->xs_periph->periph_target; 5440 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5441 SCB_LUN(pending_scb), 5442 SCB_CHANNEL(pending_scb), 5443 ROLE_UNKNOWN); 5444 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5445 our_id, remote_id, &tstate); 5446 control = ahc_inb(ahc, SCB_CONTROL); 5447 control &= ~ULTRAENB; 5448 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5449 control |= ULTRAENB; 5450 ahc_outb(ahc, SCB_CONTROL, control); 5451 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5452 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5453 } 5454 } 5455 ahc_outb(ahc, SCBPTR, saved_scbptr); 5456 } 5457 5458 #if UNUSED 5459 static void 5460 ahc_dump_targcmd(struct target_cmd *cmd) 5461 { 5462 u_int8_t *byte; 5463 u_int8_t *last_byte; 5464 int i; 5465 5466 byte = &cmd->initiator_channel; 5467 /* Debugging info for received commands */ 5468 last_byte = &cmd[1].initiator_channel; 5469 5470 i = 0; 5471 while (byte < last_byte) { 5472 if (i == 0) 5473 printf("\t"); 5474 printf("%#x", *byte++); 5475 i++; 5476 if (i == 8) { 5477 printf("\n"); 5478 i = 0; 5479 } else { 5480 printf(", "); 5481 } 5482 } 5483 } 5484 #endif 5485 5486 static void 5487 ahc_shutdown(void *arg) 5488 { 5489 struct ahc_softc *ahc; 5490 int i; 5491 u_int sxfrctl1_a, sxfrctl1_b; 5492 5493 ahc = (struct ahc_softc *)arg; 5494 5495 pause_sequencer(ahc); 5496 5497 /* 5498 * Preserve the value of the SXFRCTL1 register for all channels. 5499 * It contains settings that affect termination and we don't want 5500 * to disturb the integrity of the bus during shutdown in case 5501 * we are in a multi-initiator setup. 5502 */ 5503 sxfrctl1_b = 0; 5504 if ((ahc->features & AHC_TWIN) != 0) { 5505 u_int sblkctl; 5506 5507 sblkctl = ahc_inb(ahc, SBLKCTL); 5508 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5509 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5510 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5511 } 5512 5513 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5514 5515 /* This will reset most registers to 0, but not all */ 5516 ahc_reset(ahc); 5517 5518 if ((ahc->features & AHC_TWIN) != 0) { 5519 u_int sblkctl; 5520 5521 sblkctl = ahc_inb(ahc, SBLKCTL); 5522 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5523 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5524 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5525 } 5526 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5527 5528 ahc_outb(ahc, SCSISEQ, 0); 5529 ahc_outb(ahc, SXFRCTL0, 0); 5530 ahc_outb(ahc, DSPCISTATUS, 0); 5531 5532 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5533 ahc_outb(ahc, i, 0); 5534 } 5535 5536 #if defined(AHC_DEBUG) && 0 5537 static void 5538 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5539 { 5540 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5541 5542 printf("\tcurrent:\n"); 5543 printf("\t\twidth %u period %u offset %u flags %x\n", 5544 tinfo->current.width, tinfo->current.period, 5545 tinfo->current.offset, tinfo->current.ppr_flags); 5546 5547 printf("\tgoal:\n"); 5548 printf("\t\twidth %u period %u offset %u flags %x\n", 5549 tinfo->goal.width, tinfo->goal.period, 5550 tinfo->goal.offset, tinfo->goal.ppr_flags); 5551 5552 printf("\tuser:\n"); 5553 printf("\t\twidth %u period %u offset %u flags %x\n", 5554 tinfo->user.width, tinfo->user.period, 5555 tinfo->user.offset, tinfo->user.ppr_flags); 5556 } 5557 #endif 5558 5559 static int 5560 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5561 int nocmdcheck) 5562 { 5563 #ifdef AHC_NO_TAGS 5564 return 0; 5565 #else 5566 char channel; 5567 u_int our_id, target; 5568 struct tmode_tstate *tstate; 5569 struct ahc_devinfo devinfo; 5570 5571 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5572 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5573 target = xs->xs_periph->periph_target; 5574 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5575 5576 ahc_compile_devinfo(&devinfo, our_id, target, 5577 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5578 5579 return (tstate->tagenable & devinfo.target_mask); 5580 #endif 5581 } 5582
Indexes created Thu Oct 02 01:09:59 GMT 2025