aic7xxx.c revision 1.86
1 /* $NetBSD: aic7xxx.c,v 1.86 2002/01/16 02:11:20 ichiro Exp $ */ 2 3 /* 4 * Generic driver for the aic7xxx based adaptec SCSI controllers 5 * Product specific probe and attach routines can be found in: 6 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 7 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 8 * aic7880, aic7870, aic7860, and aic7850 controllers 9 * cardbus/ahc_cardbus.c aic7860 cardbus controllers 10 * 11 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * the GNU Public License ("GPL"). 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.42 2000/03/18 22:28:18 gibbs Exp $ 39 */ 40 /* 41 * A few notes on features of the driver. 42 * 43 * SCB paging takes advantage of the fact that devices stay disconnected 44 * from the bus a relatively long time and that while they're disconnected, 45 * having the SCBs for these transactions down on the host adapter is of 46 * little use. Instead of leaving this idle SCB down on the card we copy 47 * it back up into kernel memory and reuse the SCB slot on the card to 48 * schedule another transaction. This can be a real payoff when doing random 49 * I/O to tagged queueing devices since there are more transactions active at 50 * once for the device to sort for optimal seek reduction. The algorithm goes 51 * like this... 52 * 53 * The sequencer maintains two lists of its hardware SCBs. The first is the 54 * singly linked free list which tracks all SCBs that are not currently in 55 * use. The second is the doubly linked disconnected list which holds the 56 * SCBs of transactions that are in the disconnected state sorted most 57 * recently disconnected first. When the kernel queues a transaction to 58 * the card, a hardware SCB to "house" this transaction is retrieved from 59 * either of these two lists. If the SCB came from the disconnected list, 60 * a check is made to see if any data transfer or SCB linking (more on linking 61 * in a bit) information has been changed since it was copied from the host 62 * and if so, DMAs the SCB back up before it can be used. Once a hardware 63 * SCB has been obtained, the SCB is DMAed from the host. Before any work 64 * can begin on this SCB, the sequencer must ensure that either the SCB is 65 * for a tagged transaction or the target is not already working on another 66 * non-tagged transaction. If a conflict arises in the non-tagged case, the 67 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 68 * field in that SCB to this next SCB to execute. To facilitate finding 69 * active non-tagged SCBs, the last four bytes of up to the first four hardware 70 * SCBs serve as a storage area for the currently active SCB ID for each 71 * target. 72 * 73 * When a device reconnects, a search is made of the hardware SCBs to find 74 * the SCB for this transaction. If the search fails, a hardware SCB is 75 * pulled from either the free or disconnected SCB list and the proper 76 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 77 * in the control byte of the SCB while it was disconnected, the sequencer 78 * will assert ATN and attempt to issue a message to the host. 79 * 80 * When a command completes, a check for non-zero status and residuals is 81 * made. If either of these conditions exists, the SCB is DMAed back up to 82 * the host so that it can interpret this information. Additionally, in the 83 * case of bad status, the sequencer generates a special interrupt and pauses 84 * itself. This allows the host to setup a request sense command if it 85 * chooses for this target synchronously with the error so that sense 86 * information isn't lost. 87 * 88 */ 89 90 #include <sys/cdefs.h> 91 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.86 2002/01/16 02:11:20 ichiro Exp $"); 92 93 #include "opt_ddb.h" 94 #include "opt_ahc.h" 95 96 #include <sys/param.h> 97 #include <sys/kernel.h> 98 #include <sys/systm.h> 99 #include <sys/device.h> 100 #include <sys/malloc.h> 101 #include <sys/buf.h> 102 #include <sys/proc.h> 103 #include <sys/scsiio.h> 104 105 #include <machine/bus.h> 106 #include <machine/intr.h> 107 108 #include <dev/scsipi/scsi_all.h> 109 #include <dev/scsipi/scsipi_all.h> 110 #include <dev/scsipi/scsi_message.h> 111 #include <dev/scsipi/scsipi_debug.h> 112 #include <dev/scsipi/scsiconf.h> 113 114 #include <uvm/uvm_extern.h> 115 116 #include <dev/ic/aic7xxxvar.h> 117 #include <dev/microcode/aic7xxx/sequencer.h> 118 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 119 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 120 121 #define ALL_CHANNELS '\0' 122 #define ALL_TARGETS_MASK 0xFFFF 123 #define INITIATOR_WILDCARD (~0) 124 125 #define SIM_IS_SCSIBUS_B(ahc, periph) \ 126 ((periph)->periph_channel->chan_channel == 1) 127 #define SIM_CHANNEL(ahc, periph) \ 128 (SIM_IS_SCSIBUS_B(ahc, periph) ? 'B' : 'A') 129 #define SIM_SCSI_ID(ahc, periph) \ 130 (SIM_IS_SCSIBUS_B(ahc, periph) ? ahc->our_id_b : ahc->our_id) 131 #define SCB_IS_SCSIBUS_B(scb) \ 132 (((scb)->hscb->tcl & SELBUSB) != 0) 133 #define SCB_TARGET(scb) \ 134 (((scb)->hscb->tcl & TID) >> 4) 135 #define SCB_CHANNEL(scb) \ 136 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 137 #define SCB_LUN(scb) \ 138 ((scb)->hscb->tcl & LID) 139 #define SCB_TARGET_OFFSET(scb) \ 140 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 141 #define SCB_TARGET_MASK(scb) \ 142 (0x01 << (SCB_TARGET_OFFSET(scb))) 143 #define TCL_CHANNEL(ahc, tcl) \ 144 ((((ahc)->features & AHC_TWIN) && ((tcl) & SELBUSB)) ? 'B' : 'A') 145 #define TCL_SCSI_ID(ahc, tcl) \ 146 (TCL_CHANNEL((ahc), (tcl)) == 'B' ? (ahc)->our_id_b : (ahc)->our_id) 147 #define TCL_TARGET(tcl) (((tcl) & TID) >> TCL_TARGET_SHIFT) 148 #define TCL_LUN(tcl) ((tcl) & LID) 149 150 #define XS_TCL(ahc, xs) \ 151 ((((xs)->xs_periph->periph_target << 4) & 0xF0) \ 152 | (SIM_IS_SCSIBUS_B((ahc), (xs)->xs_periph) ? SELBUSB : 0) \ 153 | ((xs)->xs_periph->periph_lun & 0x07)) 154 155 const char * const ahc_chip_names[] = 156 { 157 "NONE", 158 "aic7770", 159 "aic7850", 160 "aic7855", 161 "aic7859", 162 "aic7860", 163 "aic7870", 164 "aic7880", 165 "aic7890/91", 166 "aic7892", 167 "aic7895", 168 "aic7896/97", 169 "aic7899" 170 }; 171 172 typedef enum { 173 ROLE_UNKNOWN, 174 ROLE_INITIATOR, 175 ROLE_TARGET 176 } role_t; 177 178 struct ahc_devinfo { 179 int our_scsiid; 180 int target_offset; 181 u_int16_t target_mask; 182 u_int8_t target; 183 u_int8_t lun; 184 char channel; 185 role_t role; /* 186 * Only guaranteed to be correct if not 187 * in the busfree state. 188 */ 189 }; 190 191 typedef enum { 192 SEARCH_COMPLETE, 193 SEARCH_COUNT, 194 SEARCH_REMOVE 195 } ahc_search_action; 196 197 #ifdef AHC_DEBUG 198 static int ahc_debug = AHC_DEBUG; 199 #endif 200 201 static int ahcinitscbdata(struct ahc_softc *); 202 static void ahcfiniscbdata(struct ahc_softc *); 203 204 #if UNUSED 205 static void ahc_dump_targcmd(struct target_cmd *); 206 #endif 207 static void ahc_shutdown(void *arg); 208 static void ahc_action(struct scsipi_channel *, 209 scsipi_adapter_req_t, void *); 210 static int ahc_ioctl(struct scsipi_channel *, u_long, caddr_t, int, 211 struct proc *); 212 static void ahc_execute_scb(void *, bus_dma_segment_t *, int); 213 static int ahc_poll(struct ahc_softc *, int); 214 static void ahc_setup_data(struct ahc_softc *, struct scsipi_xfer *, 215 struct scb *); 216 static void ahc_freeze_devq(struct ahc_softc *, struct scsipi_periph *); 217 static void ahcallocscbs(struct ahc_softc *); 218 #if UNUSED 219 static void ahc_scb_devinfo(struct ahc_softc *, struct ahc_devinfo *, 220 struct scb *); 221 #endif 222 static void ahc_fetch_devinfo(struct ahc_softc *, struct ahc_devinfo *); 223 static void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int, u_int, 224 char, role_t); 225 static u_int ahc_abort_wscb(struct ahc_softc *, u_int, u_int); 226 static void ahc_done(struct ahc_softc *, struct scb *); 227 static struct tmode_tstate * 228 ahc_alloc_tstate(struct ahc_softc *, u_int, char); 229 #if UNUSED 230 static void ahc_free_tstate(struct ahc_softc *, u_int, char, int); 231 #endif 232 static void ahc_handle_seqint(struct ahc_softc *, u_int); 233 static void ahc_handle_scsiint(struct ahc_softc *, u_int); 234 static void ahc_build_transfer_msg(struct ahc_softc *, 235 struct ahc_devinfo *); 236 static void ahc_setup_initiator_msgout(struct ahc_softc *, 237 struct ahc_devinfo *, 238 struct scb *); 239 static void ahc_setup_target_msgin(struct ahc_softc *, 240 struct ahc_devinfo *); 241 static void ahc_clear_msg_state(struct ahc_softc *); 242 static void ahc_handle_message_phase(struct ahc_softc *, 243 struct scsipi_periph *); 244 static int ahc_sent_msg(struct ahc_softc *, u_int, int); 245 246 static int ahc_parse_msg(struct ahc_softc *, struct scsipi_periph *, 247 struct ahc_devinfo *); 248 static void ahc_handle_ign_wide_residue(struct ahc_softc *, 249 struct ahc_devinfo *); 250 static void ahc_handle_devreset(struct ahc_softc *, struct ahc_devinfo *, 251 int, char *, int); 252 #ifdef AHC_DUMP_SEQ 253 static void ahc_dumpseq(struct ahc_softc *); 254 #endif 255 static void ahc_loadseq(struct ahc_softc *); 256 static int ahc_check_patch(struct ahc_softc *, const struct patch **, 257 int, int *); 258 static void ahc_download_instr(struct ahc_softc *, int, u_int8_t *); 259 static int ahc_match_scb(struct scb *, int, char, int, u_int, role_t); 260 #if defined(AHC_DEBUG) 261 static void ahc_print_scb(struct scb *); 262 #endif 263 static int ahc_search_qinfifo(struct ahc_softc *, int, char, int, u_int, 264 role_t, scb_flag, ahc_search_action); 265 static int ahc_reset_channel(struct ahc_softc *, char, int); 266 static int ahc_abort_scbs(struct ahc_softc *, int, char, int, u_int, 267 role_t, int); 268 static int ahc_search_disc_list(struct ahc_softc *, int, 269 char, int, u_int, int, int, int); 270 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *, u_int, u_int); 271 static void ahc_add_curscb_to_free_list(struct ahc_softc *); 272 static void ahc_clear_intstat(struct ahc_softc *); 273 static void ahc_reset_current_bus(struct ahc_softc *); 274 static const struct ahc_syncrate * 275 ahc_devlimited_syncrate(struct ahc_softc *, u_int *); 276 static const struct ahc_syncrate * 277 ahc_find_syncrate(struct ahc_softc *, u_int *, u_int); 278 static u_int ahc_find_period(struct ahc_softc *, u_int, u_int); 279 static void ahc_validate_offset(struct ahc_softc *, 280 const struct ahc_syncrate *, u_int *, int); 281 static void ahc_update_target_msg_request(struct ahc_softc *, 282 struct ahc_devinfo *, 283 struct ahc_initiator_tinfo *, 284 int, int); 285 static void ahc_set_syncrate(struct ahc_softc *, struct ahc_devinfo *, 286 const struct ahc_syncrate *, u_int, u_int, 287 u_int, int, int); 288 static void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 289 u_int, u_int, int, int); 290 static void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *, int); 291 static void ahc_update_xfer_mode(struct ahc_softc *, struct ahc_devinfo *); 292 static void ahc_construct_sdtr(struct ahc_softc *, u_int, u_int); 293 294 static void ahc_construct_wdtr(struct ahc_softc *, u_int); 295 296 static void ahc_calc_residual(struct scb *); 297 298 static void ahc_update_pending_syncrates(struct ahc_softc *); 299 300 static void ahc_set_recoveryscb(struct ahc_softc *, struct scb *); 301 302 static void ahc_timeout (void *); 303 static __inline int sequencer_paused(struct ahc_softc *); 304 static __inline void pause_sequencer(struct ahc_softc *); 305 static __inline void unpause_sequencer(struct ahc_softc *); 306 static void restart_sequencer(struct ahc_softc *); 307 static __inline u_int ahc_index_busy_tcl(struct ahc_softc *, u_int, int); 308 309 static __inline void ahc_busy_tcl(struct ahc_softc *, struct scb *); 310 static __inline int ahc_isbusy_tcl(struct ahc_softc *, struct scb *); 311 312 static __inline void ahc_freeze_ccb(struct scb *); 313 static __inline void ahcsetccbstatus(struct scsipi_xfer *, int); 314 static void ahc_run_qoutfifo(struct ahc_softc *); 315 316 static __inline struct ahc_initiator_tinfo * 317 ahc_fetch_transinfo(struct ahc_softc *, 318 char, u_int, u_int, 319 struct tmode_tstate **); 320 static void ahcfreescb(struct ahc_softc *, struct scb *); 321 static __inline struct scb *ahcgetscb(struct ahc_softc *); 322 323 static int ahc_createdmamem(bus_dma_tag_t, int, int, bus_dmamap_t *, 324 caddr_t *, bus_addr_t *, bus_dma_segment_t *, 325 int *, const char *, const char *); 326 static void ahc_freedmamem(bus_dma_tag_t, int, bus_dmamap_t, 327 caddr_t, bus_dma_segment_t *, int); 328 static void ahcminphys(struct buf *); 329 330 static __inline void ahc_swap_hscb(struct hardware_scb *); 331 static __inline void ahc_swap_sg(struct ahc_dma_seg *); 332 static int ahc_istagged_device(struct ahc_softc *, struct scsipi_xfer *, int); 333 334 #if defined(AHC_DEBUG) && 0 335 static void ahc_dumptinfo(struct ahc_softc *, struct ahc_initiator_tinfo *); 336 #endif 337 338 static __inline void 339 ahc_swap_hscb(struct hardware_scb *hscb) 340 { 341 hscb->SG_pointer = htole32(hscb->SG_pointer); 342 hscb->data = htole32(hscb->data); 343 hscb->datalen = htole32(hscb->datalen); 344 /* 345 * No need to swap cmdpointer; it's either 0 or set to 346 * cmdstore_busaddr, which is already swapped. 347 */ 348 } 349 350 static __inline void 351 ahc_swap_sg(struct ahc_dma_seg *sg) 352 { 353 sg->addr = htole32(sg->addr); 354 sg->len = htole32(sg->len); 355 } 356 357 static void 358 ahcminphys(bp) 359 struct buf *bp; 360 { 361 /* 362 * Even though the card can transfer up to 16megs per command 363 * we are limited by the number of segments in the dma segment 364 * list that we can hold. The worst case is that all pages are 365 * discontinuous physically, hense the "page per segment" limit 366 * enforced here. 367 */ 368 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) { 369 bp->b_bcount = AHC_MAXTRANSFER_SIZE; 370 } 371 minphys(bp); 372 } 373 374 375 static __inline u_int32_t 376 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 377 { 378 return (ahc->scb_data->hscb_busaddr 379 + (sizeof(struct hardware_scb) * index)); 380 } 381 382 #define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 383 384 static __inline int 385 sequencer_paused(struct ahc_softc *ahc) 386 { 387 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 388 } 389 390 static __inline void 391 pause_sequencer(struct ahc_softc *ahc) 392 { 393 ahc_outb(ahc, HCNTRL, ahc->pause); 394 395 /* 396 * Since the sequencer can disable pausing in a critical section, we 397 * must loop until it actually stops. 398 */ 399 while (sequencer_paused(ahc) == 0) 400 ; 401 } 402 403 static __inline void 404 unpause_sequencer(struct ahc_softc *ahc) 405 { 406 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 407 ahc_outb(ahc, HCNTRL, ahc->unpause); 408 } 409 410 /* 411 * Restart the sequencer program from address zero 412 */ 413 static void 414 restart_sequencer(struct ahc_softc *ahc) 415 { 416 u_int i; 417 418 pause_sequencer(ahc); 419 420 /* 421 * Everytime we restart the sequencer, there 422 * is the possiblitity that we have restarted 423 * within a three instruction window where an 424 * SCB has been marked free but has not made it 425 * onto the free list. Since SCSI events(bus reset, 426 * unexpected bus free) will always freeze the 427 * sequencer, we cannot close this window. To 428 * avoid losing an SCB, we reconsitute the free 429 * list every time we restart the sequencer. 430 */ 431 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 432 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 433 434 ahc_outb(ahc, SCBPTR, i); 435 if (ahc_inb(ahc, SCB_TAG) == SCB_LIST_NULL) 436 ahc_add_curscb_to_free_list(ahc); 437 } 438 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 439 unpause_sequencer(ahc); 440 } 441 442 static __inline u_int 443 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 444 { 445 u_int scbid; 446 447 scbid = ahc->untagged_scbs[tcl]; 448 if (unbusy) { 449 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 450 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 451 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 452 } 453 454 return (scbid); 455 } 456 457 static __inline void 458 ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 459 { 460 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 461 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 462 UNTAGGEDSCB_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 463 } 464 465 static __inline int 466 ahc_isbusy_tcl(struct ahc_softc *ahc, struct scb *scb) 467 { 468 return ahc->untagged_scbs[scb->hscb->tcl] != SCB_LIST_NULL; 469 } 470 471 static __inline void 472 ahc_freeze_ccb(struct scb *scb) 473 { 474 struct scsipi_xfer *xs = scb->xs; 475 476 if (!(scb->flags & SCB_FREEZE_QUEUE)) { 477 scsipi_periph_freeze(xs->xs_periph, 1); 478 scb->flags |= SCB_FREEZE_QUEUE; 479 } 480 } 481 482 static __inline void 483 ahcsetccbstatus(struct scsipi_xfer *xs, int status) 484 { 485 xs->error = status; 486 } 487 488 static __inline struct ahc_initiator_tinfo * 489 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 490 u_int remote_id, struct tmode_tstate **tstate) 491 { 492 /* 493 * Transfer data structures are stored from the perspective 494 * of the target role. Since the parameters for a connection 495 * in the initiator role to a given target are the same as 496 * when the roles are reversed, we pretend we are the target. 497 */ 498 if (channel == 'B') 499 our_id += 8; 500 *tstate = ahc->enabled_targets[our_id]; 501 return (&(*tstate)->transinfo[remote_id]); 502 } 503 504 static void 505 ahc_run_qoutfifo(struct ahc_softc *ahc) 506 { 507 struct scb *scb; 508 u_int scb_index; 509 510 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 511 256, BUS_DMASYNC_POSTREAD); 512 513 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 514 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 515 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 516 517 scb = &ahc->scb_data->scbarray[scb_index]; 518 if (scb_index >= ahc->scb_data->numscbs 519 || (scb->flags & SCB_ACTIVE) == 0) { 520 printf("%s: WARNING no command for scb %d " 521 "(cmdcmplt)\nQOUTPOS = %d\n", 522 ahc_name(ahc), scb_index, 523 ahc->qoutfifonext - 1); 524 continue; 525 } 526 527 /* 528 * Save off the residual 529 * if there is one. 530 */ 531 if (scb->hscb->residual_SG_count != 0) 532 ahc_calc_residual(scb); 533 else 534 scb->xs->resid = 0; 535 #ifdef AHC_DEBUG 536 if (ahc_debug & AHC_SHOWSCBS) { 537 scsipi_printaddr(scb->xs->xs_periph); 538 printf("run_qoutfifo: SCB %x complete\n", 539 scb->hscb->tag); 540 } 541 #endif 542 ahc_done(ahc, scb); 543 } 544 } 545 546 547 /* 548 * An scb (and hence an scb entry on the board) is put onto the 549 * free list. 550 */ 551 static void 552 ahcfreescb(struct ahc_softc *ahc, struct scb *scb) 553 { 554 struct hardware_scb *hscb; 555 int opri; 556 557 hscb = scb->hscb; 558 559 #ifdef AHC_DEBUG 560 if (ahc_debug & AHC_SHOWSCBALLOC) 561 printf("%s: free SCB tag %x\n", ahc_name(ahc), hscb->tag); 562 #endif 563 564 opri = splbio(); 565 566 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 || 567 (scb->flags & SCB_RECOVERY_SCB) != 0) { 568 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 569 scsipi_channel_thaw(&ahc->sc_channel, 1); 570 if (ahc->features & AHC_TWIN) 571 scsipi_channel_thaw(&ahc->sc_channel_b, 1); 572 } 573 574 /* Clean up for the next user */ 575 scb->flags = SCB_FREE; 576 hscb->control = 0; 577 hscb->status = 0; 578 579 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 580 581 splx(opri); 582 } 583 584 /* 585 * Get a free scb, either one already assigned to a hardware slot 586 * on the adapter or one that will require an SCB to be paged out before 587 * use. If there are none, see if we can allocate a new SCB. Otherwise 588 * either return an error or sleep. 589 */ 590 static __inline struct scb * 591 ahcgetscb(struct ahc_softc *ahc) 592 { 593 struct scb *scbp; 594 int opri;; 595 596 opri = splbio(); 597 if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { 598 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 599 } else { 600 ahcallocscbs(ahc); 601 scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); 602 if (scbp != NULL) 603 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 604 } 605 606 splx(opri); 607 608 #ifdef AHC_DEBUG 609 if (ahc_debug & AHC_SHOWSCBALLOC) { 610 if (scbp != NULL) 611 printf("%s: new SCB, tag %x\n", ahc_name(ahc), 612 scbp->hscb->tag); 613 else 614 printf("%s: failed to allocate new SCB\n", 615 ahc_name(ahc)); 616 } 617 #endif 618 619 return (scbp); 620 } 621 622 static int 623 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 624 bus_dma_tag_t tag; 625 int size; 626 int flags; 627 bus_dmamap_t *mapp; 628 caddr_t *vaddr; 629 bus_addr_t *baddr; 630 bus_dma_segment_t *seg; 631 int *nseg; 632 const char *myname, *what; 633 { 634 int error, level = 0; 635 636 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 637 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 638 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 639 myname, what, error); 640 goto out; 641 } 642 level++; 643 644 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 645 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 646 printf("%s: failed to map DMA mem for %s, error = %d\n", 647 myname, what, error); 648 goto out; 649 } 650 level++; 651 652 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 653 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 654 printf("%s: failed to create DMA map for %s, error = %d\n", 655 myname, what, error); 656 goto out; 657 } 658 level++; 659 660 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 661 BUS_DMA_NOWAIT)) != 0) { 662 printf("%s: failed to load DMA map for %s, error = %d\n", 663 myname, what, error); 664 goto out; 665 } 666 667 *baddr = (*mapp)->dm_segs[0].ds_addr; 668 669 #ifdef AHC_DEBUG 670 printf("%s: dmamem for %s at busaddr %lx virt %lx nseg %d size %d\n", 671 myname, what, (unsigned long)*baddr, (unsigned long)*vaddr, 672 *nseg, size); 673 #endif 674 675 return 0; 676 out: 677 switch (level) { 678 case 3: 679 bus_dmamap_destroy(tag, *mapp); 680 /* FALLTHROUGH */ 681 case 2: 682 bus_dmamem_unmap(tag, *vaddr, size); 683 /* FALLTHROUGH */ 684 case 1: 685 bus_dmamem_free(tag, seg, *nseg); 686 break; 687 default: 688 break; 689 } 690 691 return error; 692 } 693 694 static void 695 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 696 bus_dma_tag_t tag; 697 int size; 698 bus_dmamap_t map; 699 caddr_t vaddr; 700 bus_dma_segment_t *seg; 701 int nseg; 702 { 703 704 bus_dmamap_unload(tag, map); 705 bus_dmamap_destroy(tag, map); 706 bus_dmamem_unmap(tag, vaddr, size); 707 bus_dmamem_free(tag, seg, nseg); 708 } 709 710 char * 711 ahc_name(struct ahc_softc *ahc) 712 { 713 return (ahc->sc_dev.dv_xname); 714 } 715 716 #ifdef AHC_DEBUG 717 static void 718 ahc_print_scb(struct scb *scb) 719 { 720 struct hardware_scb *hscb = scb->hscb; 721 722 printf("scb:%p tag %x control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 723 scb, 724 hscb->tag, 725 hscb->control, 726 hscb->tcl, 727 hscb->cmdlen, 728 (unsigned long)le32toh(hscb->cmdpointer)); 729 printf(" datlen:%u data:0x%lx segs:0x%x segp:0x%lx\n", 730 le32toh(hscb->datalen), 731 (unsigned long)(le32toh(hscb->data)), 732 hscb->SG_count, 733 (unsigned long)(le32toh(hscb->SG_pointer))); 734 printf(" sg_addr:%lx sg_len:%lu\n", 735 (unsigned long)(le32toh(scb->sg_list[0].addr)), 736 (unsigned long)(le32toh(scb->sg_list[0].len))); 737 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 738 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 739 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 740 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 741 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 742 } 743 #endif 744 745 static const struct { 746 u_int8_t errno; 747 const char *errmesg; 748 } hard_error[] = { 749 { ILLHADDR, "Illegal Host Access" }, 750 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 751 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 752 { SQPARERR, "Sequencer Parity Error" }, 753 { DPARERR, "Data-path Parity Error" }, 754 { MPARERR, "Scratch or SCB Memory Parity Error" }, 755 { PCIERRSTAT, "PCI Error detected" }, 756 { CIOPARERR, "CIOBUS Parity Error" }, 757 }; 758 static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 759 760 static const struct { 761 u_int8_t phase; 762 u_int8_t mesg_out; /* Message response to parity errors */ 763 const char *phasemsg; 764 } phase_table[] = { 765 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 766 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 767 { P_COMMAND, MSG_NOOP, "in Command phase" }, 768 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 769 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 770 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 771 { P_BUSFREE, MSG_NOOP, "while idle" }, 772 { 0, MSG_NOOP, "in unknown phase" } 773 }; 774 static const int num_phases = (sizeof(phase_table)/sizeof(phase_table[0])) - 1; 775 776 /* 777 * Valid SCSIRATE values. (p. 3-17) 778 * Provides a mapping of transfer periods in ns to the proper value to 779 * stick in the scsiscfr reg to use that transfer rate. 780 */ 781 #define AHC_SYNCRATE_DT 0 782 #define AHC_SYNCRATE_ULTRA2 1 783 #define AHC_SYNCRATE_ULTRA 3 784 #define AHC_SYNCRATE_FAST 6 785 static const struct ahc_syncrate ahc_syncrates[] = { 786 /* ultra2 fast/ultra period rate */ 787 { 0x42, 0x000, 9, "80.0" }, 788 { 0x03, 0x000, 10, "40.0" }, 789 { 0x04, 0x000, 11, "33.0" }, 790 { 0x05, 0x100, 12, "20.0" }, 791 { 0x06, 0x110, 15, "16.0" }, 792 { 0x07, 0x120, 18, "13.4" }, 793 { 0x08, 0x000, 25, "10.0" }, 794 { 0x19, 0x010, 31, "8.0" }, 795 { 0x1a, 0x020, 37, "6.67" }, 796 { 0x1b, 0x030, 43, "5.7" }, 797 { 0x1c, 0x040, 50, "5.0" }, 798 { 0x00, 0x050, 56, "4.4" }, 799 { 0x00, 0x060, 62, "4.0" }, 800 { 0x00, 0x070, 68, "3.6" }, 801 { 0x00, 0x000, 0, NULL } 802 }; 803 804 /* 805 * Allocate a controller structure for a new device and initialize it. 806 */ 807 int 808 ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, bus_space_tag_t st, 809 bus_dma_tag_t parent_dmat, ahc_chip chip, ahc_feature features, 810 ahc_flag flags) 811 { 812 struct scb_data *scb_data; 813 814 scb_data = malloc(sizeof (struct scb_data), M_DEVBUF, M_NOWAIT|M_ZERO); 815 if (scb_data == NULL) { 816 printf("%s: cannot malloc softc!\n", ahc_name(ahc)); 817 return -1; 818 } 819 LIST_INIT(&ahc->pending_ccbs); 820 ahc->tag = st; 821 ahc->bsh = sh; 822 ahc->parent_dmat = parent_dmat; 823 ahc->chip = chip; 824 ahc->features = features; 825 ahc->flags = flags; 826 ahc->scb_data = scb_data; 827 828 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 829 /* The IRQMS bit is only valid on VL and EISA chips */ 830 if ((ahc->chip & AHC_PCI) != 0) 831 ahc->unpause &= ~IRQMS; 832 ahc->pause = ahc->unpause | PAUSE; 833 return (0); 834 } 835 836 void 837 ahc_free(ahc) 838 struct ahc_softc *ahc; 839 { 840 ahcfiniscbdata(ahc); 841 if (ahc->init_level != 0) 842 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size, 843 ahc->shared_data_dmamap, ahc->qoutfifo, 844 &ahc->shared_data_seg, ahc->shared_data_nseg); 845 846 if (ahc->scb_data != NULL) 847 free(ahc->scb_data, M_DEVBUF); 848 if (ahc->bus_data != NULL) 849 free(ahc->bus_data, M_DEVBUF); 850 return; 851 } 852 853 static int 854 ahcinitscbdata(struct ahc_softc *ahc) 855 { 856 struct scb_data *scb_data; 857 int i; 858 859 scb_data = ahc->scb_data; 860 SLIST_INIT(&scb_data->free_scbs); 861 SLIST_INIT(&scb_data->sg_maps); 862 863 /* Allocate SCB resources */ 864 scb_data->scbarray = 865 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 866 M_DEVBUF, M_NOWAIT|M_ZERO); 867 if (scb_data->scbarray == NULL) 868 return (ENOMEM); 869 870 /* Determine the number of hardware SCBs and initialize them */ 871 872 scb_data->maxhscbs = ahc_probe_scbs(ahc); 873 /* SCB 0 heads the free list */ 874 ahc_outb(ahc, FREE_SCBH, 0); 875 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 876 ahc_outb(ahc, SCBPTR, i); 877 878 /* Clear the control byte. */ 879 ahc_outb(ahc, SCB_CONTROL, 0); 880 881 /* Set the next pointer */ 882 ahc_outb(ahc, SCB_NEXT, i+1); 883 884 /* Make the tag number invalid */ 885 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 886 } 887 888 /* Make sure that the last SCB terminates the free list */ 889 ahc_outb(ahc, SCBPTR, i-1); 890 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 891 892 /* Ensure we clear the 0 SCB's control byte. */ 893 ahc_outb(ahc, SCBPTR, 0); 894 ahc_outb(ahc, SCB_CONTROL, 0); 895 896 scb_data->maxhscbs = i; 897 898 if (ahc->scb_data->maxhscbs == 0) 899 panic("%s: No SCB space found", ahc_name(ahc)); 900 901 /* 902 * Create our DMA tags. These tags define the kinds of device 903 * accessible memory allocations and memory mappings we will 904 * need to perform during normal operation. 905 * 906 * Unless we need to further restrict the allocation, we rely 907 * on the restrictions of the parent dmat, hence the common 908 * use of MAXADDR and MAXSIZE. 909 */ 910 911 if (ahc_createdmamem(ahc->parent_dmat, 912 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 913 &scb_data->hscb_dmamap, 914 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 915 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 916 "hardware SCB structures") < 0) 917 goto error_exit; 918 919 scb_data->init_level++; 920 921 if (ahc_createdmamem(ahc->parent_dmat, 922 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 923 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 924 &scb_data->sense_busaddr, &scb_data->sense_seg, 925 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 926 goto error_exit; 927 928 scb_data->init_level++; 929 930 /* Perform initial CCB allocation */ 931 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 932 ahcallocscbs(ahc); 933 934 if (scb_data->numscbs == 0) { 935 printf("%s: ahc_init_scb_data - " 936 "Unable to allocate initial scbs\n", 937 ahc_name(ahc)); 938 goto error_exit; 939 } 940 941 scb_data->init_level++; 942 943 /* 944 * Note that we were successfull 945 */ 946 return 0; 947 948 error_exit: 949 950 return ENOMEM; 951 } 952 953 static void 954 ahcfiniscbdata(struct ahc_softc *ahc) 955 { 956 struct scb_data *scb_data; 957 958 scb_data = ahc->scb_data; 959 960 switch (scb_data->init_level) { 961 default: 962 case 3: 963 { 964 struct sg_map_node *sg_map; 965 966 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 967 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 968 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 969 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 970 &sg_map->sg_dmasegs, sg_map->sg_nseg); 971 free(sg_map, M_DEVBUF); 972 } 973 } 974 /*FALLTHROUGH*/ 975 case 2: 976 ahc_freedmamem(ahc->parent_dmat, 977 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 978 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 979 &scb_data->sense_seg, scb_data->sense_nseg); 980 /*FALLTHROUGH*/ 981 case 1: 982 ahc_freedmamem(ahc->parent_dmat, 983 AHC_SCB_MAX * sizeof(struct hardware_scb), 984 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 985 &scb_data->hscb_seg, scb_data->hscb_nseg); 986 /*FALLTHROUGH*/ 987 } 988 if (scb_data->scbarray != NULL) 989 free(scb_data->scbarray, M_DEVBUF); 990 } 991 992 int 993 ahc_reset(struct ahc_softc *ahc) 994 { 995 u_int sblkctl; 996 int wait; 997 998 #ifdef AHC_DUMP_SEQ 999 if (ahc->init_level == 0) 1000 ahc_dumpseq(ahc); 1001 #endif 1002 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 1003 /* 1004 * Ensure that the reset has finished 1005 */ 1006 wait = 1000; 1007 do { 1008 DELAY(1000); 1009 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 1010 1011 if (wait == 0) { 1012 printf("%s: WARNING - Failed chip reset! " 1013 "Trying to initialize anyway.\n", ahc_name(ahc)); 1014 } 1015 ahc_outb(ahc, HCNTRL, ahc->pause); 1016 1017 /* Determine channel configuration */ 1018 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 1019 /* No Twin Channel PCI cards */ 1020 if ((ahc->chip & AHC_PCI) != 0) 1021 sblkctl &= ~SELBUSB; 1022 switch (sblkctl) { 1023 case 0: 1024 /* Single Narrow Channel */ 1025 break; 1026 case 2: 1027 /* Wide Channel */ 1028 ahc->features |= AHC_WIDE; 1029 break; 1030 case 8: 1031 /* Twin Channel */ 1032 ahc->features |= AHC_TWIN; 1033 break; 1034 default: 1035 printf(" Unsupported adapter type. Ignoring\n"); 1036 return(-1); 1037 } 1038 1039 return (0); 1040 } 1041 1042 /* 1043 * Called when we have an active connection to a target on the bus, 1044 * this function finds the nearest syncrate to the input period limited 1045 * by the capabilities of the bus connectivity of the target. 1046 */ 1047 static const struct ahc_syncrate * 1048 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 1049 u_int maxsync; 1050 1051 if ((ahc->features & AHC_ULTRA2) != 0) { 1052 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1053 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1054 maxsync = AHC_SYNCRATE_ULTRA2; 1055 } else { 1056 maxsync = AHC_SYNCRATE_ULTRA; 1057 } 1058 } else if ((ahc->features & AHC_ULTRA) != 0) { 1059 maxsync = AHC_SYNCRATE_ULTRA; 1060 } else { 1061 maxsync = AHC_SYNCRATE_FAST; 1062 } 1063 return (ahc_find_syncrate(ahc, period, maxsync)); 1064 } 1065 1066 /* 1067 * Look up the valid period to SCSIRATE conversion in our table. 1068 * Return the period and offset that should be sent to the target 1069 * if this was the beginning of an SDTR. 1070 */ 1071 static const struct ahc_syncrate * 1072 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 1073 { 1074 const struct ahc_syncrate *syncrate; 1075 1076 syncrate = &ahc_syncrates[maxsync]; 1077 while ((syncrate->rate != NULL) 1078 && ((ahc->features & AHC_ULTRA2) == 0 1079 || (syncrate->sxfr_u2 != 0))) { 1080 1081 if (*period <= syncrate->period) { 1082 /* 1083 * When responding to a target that requests 1084 * sync, the requested rate may fall between 1085 * two rates that we can output, but still be 1086 * a rate that we can receive. Because of this, 1087 * we want to respond to the target with 1088 * the same rate that it sent to us even 1089 * if the period we use to send data to it 1090 * is lower. Only lower the response period 1091 * if we must. 1092 */ 1093 if (syncrate == &ahc_syncrates[maxsync]) 1094 *period = syncrate->period; 1095 break; 1096 } 1097 syncrate++; 1098 } 1099 1100 if ((*period == 0) 1101 || (syncrate->rate == NULL) 1102 || ((ahc->features & AHC_ULTRA2) != 0 1103 && (syncrate->sxfr_u2 == 0))) { 1104 /* Use asynchronous transfers. */ 1105 *period = 0; 1106 syncrate = NULL; 1107 } 1108 return (syncrate); 1109 } 1110 1111 static u_int 1112 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1113 { 1114 const struct ahc_syncrate *syncrate; 1115 1116 if ((ahc->features & AHC_ULTRA2) != 0) 1117 scsirate &= SXFR_ULTRA2; 1118 else 1119 scsirate &= SXFR; 1120 1121 syncrate = &ahc_syncrates[maxsync]; 1122 while (syncrate->rate != NULL) { 1123 1124 if ((ahc->features & AHC_ULTRA2) != 0) { 1125 if (syncrate->sxfr_u2 == 0) 1126 break; 1127 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1128 return (syncrate->period); 1129 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1130 return (syncrate->period); 1131 } 1132 syncrate++; 1133 } 1134 return (0); /* async */ 1135 } 1136 1137 static void 1138 ahc_validate_offset(struct ahc_softc *ahc, const struct ahc_syncrate *syncrate, 1139 u_int *offset, int wide) 1140 { 1141 u_int maxoffset; 1142 1143 /* Limit offset to what we can do */ 1144 if (syncrate == NULL) { 1145 maxoffset = 0; 1146 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1147 maxoffset = MAX_OFFSET_ULTRA2; 1148 } else { 1149 if (wide) 1150 maxoffset = MAX_OFFSET_16BIT; 1151 else 1152 maxoffset = MAX_OFFSET_8BIT; 1153 } 1154 *offset = MIN(*offset, maxoffset); 1155 } 1156 1157 static void 1158 ahc_update_target_msg_request(struct ahc_softc *ahc, 1159 struct ahc_devinfo *devinfo, 1160 struct ahc_initiator_tinfo *tinfo, 1161 int force, int paused) 1162 { 1163 u_int targ_msg_req_orig; 1164 1165 targ_msg_req_orig = ahc->targ_msg_req; 1166 if (tinfo->current.period != tinfo->goal.period 1167 || tinfo->current.width != tinfo->goal.width 1168 || tinfo->current.offset != tinfo->goal.offset 1169 || (force 1170 && (tinfo->goal.period != 0 1171 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) { 1172 ahc->targ_msg_req |= devinfo->target_mask; 1173 } else { 1174 ahc->targ_msg_req &= ~devinfo->target_mask; 1175 } 1176 1177 if (ahc->targ_msg_req != targ_msg_req_orig) { 1178 /* Update the message request bit for this target */ 1179 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 1180 if (paused) { 1181 ahc_outb(ahc, TARGET_MSG_REQUEST, 1182 ahc->targ_msg_req & 0xFF); 1183 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1184 (ahc->targ_msg_req >> 8) & 0xFF); 1185 } else { 1186 ahc_outb(ahc, HS_MAILBOX, 1187 0x01 << HOST_MAILBOX_SHIFT); 1188 } 1189 } else { 1190 if (!paused) 1191 pause_sequencer(ahc); 1192 1193 ahc_outb(ahc, TARGET_MSG_REQUEST, 1194 ahc->targ_msg_req & 0xFF); 1195 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1196 (ahc->targ_msg_req >> 8) & 0xFF); 1197 1198 if (!paused) 1199 unpause_sequencer(ahc); 1200 } 1201 } 1202 } 1203 1204 static void 1205 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1206 const struct ahc_syncrate *syncrate, 1207 u_int period, u_int offset, u_int type, int paused, int done) 1208 { 1209 struct ahc_initiator_tinfo *tinfo; 1210 struct tmode_tstate *tstate; 1211 u_int old_period; 1212 u_int old_offset; 1213 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1214 1215 if (syncrate == NULL) { 1216 period = 0; 1217 offset = 0; 1218 } 1219 1220 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1221 devinfo->target, &tstate); 1222 old_period = tinfo->current.period; 1223 old_offset = tinfo->current.offset; 1224 1225 if ((type & AHC_TRANS_CUR) != 0 1226 && (old_period != period || old_offset != offset)) { 1227 u_int scsirate; 1228 1229 scsirate = tinfo->scsirate; 1230 if ((ahc->features & AHC_ULTRA2) != 0) { 1231 1232 /* XXX */ 1233 /* Force single edge until DT is fully implemented */ 1234 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1235 if (syncrate != NULL) 1236 scsirate |= syncrate->sxfr_u2|SINGLE_EDGE; 1237 1238 if (active) 1239 ahc_outb(ahc, SCSIOFFSET, offset); 1240 } else { 1241 1242 scsirate &= ~(SXFR|SOFS); 1243 /* 1244 * Ensure Ultra mode is set properly for 1245 * this target. 1246 */ 1247 tstate->ultraenb &= ~devinfo->target_mask; 1248 if (syncrate != NULL) { 1249 if (syncrate->sxfr & ULTRA_SXFR) { 1250 tstate->ultraenb |= 1251 devinfo->target_mask; 1252 } 1253 scsirate |= syncrate->sxfr & SXFR; 1254 scsirate |= offset & SOFS; 1255 } 1256 if (active) { 1257 u_int sxfrctl0; 1258 1259 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1260 sxfrctl0 &= ~FAST20; 1261 if (tstate->ultraenb & devinfo->target_mask) 1262 sxfrctl0 |= FAST20; 1263 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1264 } 1265 } 1266 if (active) 1267 ahc_outb(ahc, SCSIRATE, scsirate); 1268 1269 tinfo->scsirate = scsirate; 1270 tinfo->current.period = period; 1271 tinfo->current.offset = offset; 1272 1273 /* Update the syncrates in any pending scbs */ 1274 ahc_update_pending_syncrates(ahc); 1275 } 1276 1277 if ((type & AHC_TRANS_GOAL) != 0) { 1278 tinfo->goal.period = period; 1279 tinfo->goal.offset = offset; 1280 } 1281 1282 if ((type & AHC_TRANS_USER) != 0) { 1283 tinfo->user.period = period; 1284 tinfo->user.offset = offset; 1285 } 1286 1287 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1288 /*force*/FALSE, 1289 paused); 1290 } 1291 1292 static void 1293 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1294 u_int width, u_int type, int paused, int done) 1295 { 1296 struct ahc_initiator_tinfo *tinfo; 1297 struct tmode_tstate *tstate; 1298 u_int oldwidth; 1299 int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1300 1301 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1302 devinfo->target, &tstate); 1303 oldwidth = tinfo->current.width; 1304 1305 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1306 u_int scsirate; 1307 1308 scsirate = tinfo->scsirate; 1309 scsirate &= ~WIDEXFER; 1310 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1311 scsirate |= WIDEXFER; 1312 1313 tinfo->scsirate = scsirate; 1314 1315 if (active) 1316 ahc_outb(ahc, SCSIRATE, scsirate); 1317 1318 tinfo->current.width = width; 1319 } 1320 1321 if ((type & AHC_TRANS_GOAL) != 0) 1322 tinfo->goal.width = width; 1323 if ((type & AHC_TRANS_USER) != 0) 1324 tinfo->user.width = width; 1325 1326 ahc_update_target_msg_request(ahc, devinfo, tinfo, 1327 /*force*/FALSE, paused); 1328 } 1329 1330 static void 1331 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1332 { 1333 struct ahc_initiator_tinfo *tinfo; 1334 struct tmode_tstate *tstate; 1335 1336 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1337 devinfo->target, &tstate); 1338 1339 if (enable) { 1340 tstate->tagenable |= devinfo->target_mask; 1341 } else { 1342 tstate->tagenable &= ~devinfo->target_mask; 1343 tstate->tagdisable |= devinfo->target_mask; 1344 } 1345 } 1346 1347 static void 1348 ahc_update_xfer_mode(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1349 { 1350 struct scsipi_xfer_mode xm; 1351 struct ahc_initiator_tinfo *tinfo; 1352 struct tmode_tstate *tstate; 1353 1354 if (ahc->inited_targets[devinfo->target] != 2) 1355 return; 1356 1357 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1358 devinfo->target, &tstate); 1359 1360 xm.xm_target = devinfo->target; 1361 xm.xm_mode = 0; 1362 xm.xm_period = tinfo->current.period; 1363 xm.xm_offset = tinfo->current.offset; 1364 if (tinfo->current.width == 1) 1365 xm.xm_mode |= PERIPH_CAP_WIDE16; 1366 if (tinfo->current.period) 1367 xm.xm_mode |= PERIPH_CAP_SYNC; 1368 if (tstate->tagenable & devinfo->target_mask) 1369 xm.xm_mode |= PERIPH_CAP_TQING; 1370 scsipi_async_event( 1371 devinfo->channel == 'B' ? &ahc->sc_channel_b : &ahc->sc_channel, 1372 ASYNC_EVENT_XFER_MODE, &xm); 1373 } 1374 1375 /* 1376 * Attach all the sub-devices we can find 1377 */ 1378 int 1379 ahc_attach(struct ahc_softc *ahc) 1380 { 1381 ahc->sc_adapter.adapt_dev = &ahc->sc_dev; 1382 ahc->sc_adapter.adapt_nchannels = (ahc->features & AHC_TWIN) ? 2 : 1; 1383 if (ahc->flags & AHC_PAGESCBS) { 1384 ahc->sc_adapter.adapt_openings = AHC_SCB_MAX; 1385 ahc->sc_adapter.adapt_max_periph = 16; 1386 } else { 1387 ahc->sc_adapter.adapt_openings = ahc->scb_data->maxhscbs; 1388 if (ahc->scb_data->maxhscbs >= 16) 1389 ahc->sc_adapter.adapt_max_periph = 16; 1390 else 1391 ahc->sc_adapter.adapt_max_periph = 4; 1392 } 1393 ahc->sc_adapter.adapt_ioctl = ahc_ioctl; 1394 ahc->sc_adapter.adapt_minphys = ahcminphys; 1395 ahc->sc_adapter.adapt_request = ahc_action; 1396 1397 ahc->sc_channel.chan_adapter = &ahc->sc_adapter; 1398 ahc->sc_channel.chan_bustype = &scsi_bustype; 1399 ahc->sc_channel.chan_channel = 0; 1400 ahc->sc_channel.chan_ntargets = (ahc->features & AHC_WIDE) ? 16 : 8; 1401 ahc->sc_channel.chan_nluns = 8; 1402 ahc->sc_channel.chan_id = ahc->our_id; 1403 1404 if (ahc->features & AHC_TWIN) { 1405 ahc->sc_channel_b = ahc->sc_channel; 1406 ahc->sc_channel_b.chan_id = ahc->our_id_b; 1407 ahc->sc_channel_b.chan_channel = 1; 1408 } 1409 1410 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) == 0) { 1411 ahc->child = config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1412 if (ahc->features & AHC_TWIN) 1413 ahc->child = config_found((void *)ahc, &ahc->sc_channel_b, 1414 scsiprint); 1415 } else { 1416 ahc->child = config_found((void *)ahc, &ahc->sc_channel_b, scsiprint); 1417 ahc->child = config_found((void *)ahc, &ahc->sc_channel, scsiprint); 1418 } 1419 return 1; 1420 } 1421 1422 int 1423 ahc_detach(struct ahc_softc *ahc, int flags) 1424 { 1425 int rv = 0; 1426 1427 if (ahc->child != NULL) 1428 rv = config_detach(ahc->child, flags); 1429 1430 return (rv); 1431 } 1432 1433 int 1434 ahc_activate(struct device *self, enum devact act) 1435 { 1436 struct ahc_softc *ahc = (void *) self; 1437 int s, rv = 0; 1438 1439 s = splhigh(); 1440 switch (act) { 1441 case DVACT_ACTIVATE: 1442 rv = EOPNOTSUPP; 1443 break; 1444 1445 case DVACT_DEACTIVATE: 1446 if (ahc->child != NULL) 1447 rv = config_deactivate(ahc->child); 1448 break; 1449 } 1450 splx(s); 1451 1452 return (rv); 1453 } 1454 1455 static void 1456 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1457 { 1458 u_int saved_tcl; 1459 role_t role; 1460 int our_id; 1461 1462 if (ahc_inb(ahc, SSTAT0) & TARGET) 1463 role = ROLE_TARGET; 1464 else 1465 role = ROLE_INITIATOR; 1466 1467 if (role == ROLE_TARGET 1468 && (ahc->features & AHC_MULTI_TID) != 0 1469 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 1470 /* We were selected, so pull our id from TARGIDIN */ 1471 our_id = ahc_inb(ahc, TARGIDIN) & OID; 1472 } else if ((ahc->features & AHC_ULTRA2) != 0) 1473 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 1474 else 1475 our_id = ahc_inb(ahc, SCSIID) & OID; 1476 1477 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1478 ahc_compile_devinfo(devinfo, our_id, TCL_TARGET(saved_tcl), 1479 TCL_LUN(saved_tcl), TCL_CHANNEL(ahc, saved_tcl), 1480 role); 1481 } 1482 1483 static void 1484 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 1485 u_int lun, char channel, role_t role) 1486 { 1487 devinfo->our_scsiid = our_id; 1488 devinfo->target = target; 1489 devinfo->lun = lun; 1490 devinfo->target_offset = target; 1491 devinfo->channel = channel; 1492 devinfo->role = role; 1493 if (channel == 'B') 1494 devinfo->target_offset += 8; 1495 devinfo->target_mask = (0x01 << devinfo->target_offset); 1496 } 1497 1498 /* 1499 * Catch an interrupt from the adapter 1500 */ 1501 int 1502 ahc_intr(void *arg) 1503 { 1504 struct ahc_softc *ahc; 1505 u_int intstat; 1506 1507 ahc = (struct ahc_softc *)arg; 1508 1509 intstat = ahc_inb(ahc, INTSTAT); 1510 1511 /* 1512 * Any interrupts to process? 1513 */ 1514 if ((intstat & INT_PEND) == 0) { 1515 if (ahc->bus_intr && ahc->bus_intr(ahc)) { 1516 #ifdef AHC_DEBUG 1517 printf("%s: bus intr: CCHADDR %x HADDR %x SEQADDR %x\n", 1518 ahc_name(ahc), 1519 ahc_inb(ahc, CCHADDR) | 1520 (ahc_inb(ahc, CCHADDR+1) << 8) 1521 | (ahc_inb(ahc, CCHADDR+2) << 16) 1522 | (ahc_inb(ahc, CCHADDR+3) << 24), 1523 ahc_inb(ahc, HADDR) | (ahc_inb(ahc, HADDR+1) << 8) 1524 | (ahc_inb(ahc, HADDR+2) << 16) 1525 | (ahc_inb(ahc, HADDR+3) << 24), 1526 ahc_inb(ahc, SEQADDR0) | 1527 (ahc_inb(ahc, SEQADDR1) << 8)); 1528 #endif 1529 return 1; 1530 } 1531 return 0; 1532 } 1533 1534 #ifdef AHC_DEBUG 1535 if (ahc_debug & AHC_SHOWINTR) { 1536 printf("%s: intstat %x\n", ahc_name(ahc), intstat); 1537 } 1538 #endif 1539 1540 if (intstat & CMDCMPLT) { 1541 ahc_outb(ahc, CLRINT, CLRCMDINT); 1542 ahc_run_qoutfifo(ahc); 1543 } 1544 if (intstat & BRKADRINT) { 1545 /* 1546 * We upset the sequencer :-( 1547 * Lookup the error message 1548 */ 1549 int i, error, num_errors; 1550 1551 error = ahc_inb(ahc, ERROR); 1552 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1553 for (i = 0; error != 1 && i < num_errors; i++) 1554 error >>= 1; 1555 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1556 ahc_name(ahc), hard_error[i].errmesg, 1557 ahc_inb(ahc, SEQADDR0) | 1558 (ahc_inb(ahc, SEQADDR1) << 8)); 1559 1560 /* Tell everyone that this HBA is no longer available */ 1561 ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, ALL_CHANNELS, 1562 AHC_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1563 XS_DRIVER_STUFFUP); 1564 } 1565 if (intstat & SEQINT) 1566 ahc_handle_seqint(ahc, intstat); 1567 1568 if (intstat & SCSIINT) 1569 ahc_handle_scsiint(ahc, intstat); 1570 1571 return 1; 1572 } 1573 1574 static struct tmode_tstate * 1575 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1576 { 1577 struct tmode_tstate *master_tstate; 1578 struct tmode_tstate *tstate; 1579 int i, s; 1580 1581 master_tstate = ahc->enabled_targets[ahc->our_id]; 1582 if (channel == 'B') { 1583 scsi_id += 8; 1584 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1585 } 1586 if (ahc->enabled_targets[scsi_id] != NULL 1587 && ahc->enabled_targets[scsi_id] != master_tstate) 1588 panic("%s: ahc_alloc_tstate - Target already allocated", 1589 ahc_name(ahc)); 1590 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1591 if (tstate == NULL) 1592 return (NULL); 1593 1594 /* 1595 * If we have allocated a master tstate, copy user settings from 1596 * the master tstate (taken from SRAM or the EEPROM) for this 1597 * channel, but reset our current and goal settings to async/narrow 1598 * until an initiator talks to us. 1599 */ 1600 if (master_tstate != NULL) { 1601 memcpy(tstate, master_tstate, sizeof(*tstate)); 1602 tstate->ultraenb = 0; 1603 for (i = 0; i < 16; i++) { 1604 memset(&tstate->transinfo[i].current, 0, 1605 sizeof(tstate->transinfo[i].current)); 1606 memset(&tstate->transinfo[i].goal, 0, 1607 sizeof(tstate->transinfo[i].goal)); 1608 } 1609 } else 1610 memset(tstate, 0, sizeof(*tstate)); 1611 s = splbio(); 1612 ahc->enabled_targets[scsi_id] = tstate; 1613 splx(s); 1614 return (tstate); 1615 } 1616 1617 #if UNUSED 1618 static void 1619 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1620 { 1621 struct tmode_tstate *tstate; 1622 1623 /* Don't clean up the entry for our initiator role */ 1624 if ((ahc->flags & AHC_INITIATORMODE) != 0 1625 && ((channel == 'B' && scsi_id == ahc->our_id_b) 1626 || (channel == 'A' && scsi_id == ahc->our_id)) 1627 && force == FALSE) 1628 return; 1629 1630 if (channel == 'B') 1631 scsi_id += 8; 1632 tstate = ahc->enabled_targets[scsi_id]; 1633 if (tstate != NULL) 1634 free(tstate, M_DEVBUF); 1635 ahc->enabled_targets[scsi_id] = NULL; 1636 } 1637 #endif 1638 1639 static void 1640 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1641 { 1642 struct scb *scb; 1643 struct ahc_devinfo devinfo; 1644 1645 ahc_fetch_devinfo(ahc, &devinfo); 1646 1647 /* 1648 * Clear the upper byte that holds SEQINT status 1649 * codes and clear the SEQINT bit. We will unpause 1650 * the sequencer, if appropriate, after servicing 1651 * the request. 1652 */ 1653 ahc_outb(ahc, CLRINT, CLRSEQINT); 1654 switch (intstat & SEQINT_MASK) { 1655 case NO_MATCH: 1656 { 1657 /* Ensure we don't leave the selection hardware on */ 1658 ahc_outb(ahc, SCSISEQ, 1659 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1660 1661 printf("%s:%c:%d: no active SCB for reconnecting " 1662 "target - issuing BUS DEVICE RESET\n", 1663 ahc_name(ahc), devinfo.channel, devinfo.target); 1664 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1665 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1666 ahc_inb(ahc, SEQ_FLAGS)); 1667 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1668 ahc->msgout_len = 1; 1669 ahc->msgout_index = 0; 1670 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1671 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1672 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 1673 break; 1674 } 1675 case UPDATE_TMSG_REQ: 1676 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 1677 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 1678 (ahc->targ_msg_req >> 8) & 0xFF); 1679 ahc_outb(ahc, HS_MAILBOX, 0); 1680 break; 1681 case SEND_REJECT: 1682 { 1683 u_int rejbyte = ahc_inb(ahc, ACCUM); 1684 printf("%s:%c:%d: Warning - unknown message received from " 1685 "target (0x%x). Rejecting\n", 1686 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1687 break; 1688 } 1689 case NO_IDENT: 1690 { 1691 /* 1692 * The reconnecting target either did not send an identify 1693 * message, or did, but we didn't find and SCB to match and 1694 * before it could respond to our ATN/abort, it hit a dataphase. 1695 * The only safe thing to do is to blow it away with a bus 1696 * reset. 1697 */ 1698 int found; 1699 1700 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1701 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1702 ahc_name(ahc), devinfo.channel, devinfo.target, 1703 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1704 found = ahc_reset_channel(ahc, devinfo.channel, 1705 /*initiate reset*/TRUE); 1706 printf("%s: Issued Channel %c Bus Reset. " 1707 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1708 found); 1709 return; 1710 } 1711 case BAD_PHASE: 1712 { 1713 u_int lastphase; 1714 1715 lastphase = ahc_inb(ahc, LASTPHASE); 1716 if (lastphase == P_BUSFREE) { 1717 printf("%s:%c:%d: Missed busfree. Curphase = 0x%x\n", 1718 ahc_name(ahc), devinfo.channel, devinfo.target, 1719 ahc_inb(ahc, SCSISIGI)); 1720 restart_sequencer(ahc); 1721 return; 1722 } else { 1723 printf("%s:%c:%d: unknown scsi bus phase %x. " 1724 "Attempting to continue\n", 1725 ahc_name(ahc), devinfo.channel, devinfo.target, 1726 ahc_inb(ahc, SCSISIGI)); 1727 } 1728 break; 1729 } 1730 case BAD_STATUS: 1731 { 1732 u_int scb_index; 1733 struct hardware_scb *hscb; 1734 struct scsipi_xfer *xs; 1735 /* 1736 * The sequencer will notify us when a command 1737 * has an error that would be of interest to 1738 * the kernel. This allows us to leave the sequencer 1739 * running in the common case of command completes 1740 * without error. The sequencer will already have 1741 * dma'd the SCB back up to us, so we can reference 1742 * the in kernel copy directly. 1743 */ 1744 scb_index = ahc_inb(ahc, SCB_TAG); 1745 scb = &ahc->scb_data->scbarray[scb_index]; 1746 1747 /* ahc_print_scb(scb); */ 1748 1749 /* 1750 * Set the default return value to 0 (don't 1751 * send sense). The sense code will change 1752 * this if needed. 1753 */ 1754 ahc_outb(ahc, RETURN_1, 0); 1755 if (!(scb_index < ahc->scb_data->numscbs 1756 && (scb->flags & SCB_ACTIVE) != 0)) { 1757 printf("%s:%c:%d: ahc_intr - referenced scb " 1758 "not valid during seqint 0x%x scb(%d)\n", 1759 ahc_name(ahc), devinfo.channel, 1760 devinfo.target, intstat, scb_index); 1761 goto unpause; 1762 } 1763 1764 hscb = scb->hscb; 1765 xs = scb->xs; 1766 1767 /* Don't want to clobber the original sense code */ 1768 if ((scb->flags & SCB_SENSE) != 0) { 1769 /* 1770 * Clear the SCB_SENSE Flag and have 1771 * the sequencer do a normal command 1772 * complete. 1773 */ 1774 scb->flags &= ~SCB_SENSE; 1775 ahcsetccbstatus(xs, XS_DRIVER_STUFFUP); 1776 break; 1777 } 1778 /* Freeze the queue unit the client sees the error. */ 1779 ahc_freeze_devq(ahc, xs->xs_periph); 1780 ahc_freeze_ccb(scb); 1781 xs->status = hscb->status; 1782 switch (hscb->status) { 1783 case SCSI_STATUS_OK: 1784 printf("%s: Interrupted for status of 0???\n", 1785 ahc_name(ahc)); 1786 break; 1787 case SCSI_STATUS_CMD_TERMINATED: 1788 case SCSI_STATUS_CHECK_COND: 1789 #if defined(AHC_DEBUG) 1790 if (ahc_debug & AHC_SHOWSENSE) { 1791 scsipi_printaddr(xs->xs_periph); 1792 printf("Check Status, resid %d datalen %d\n", 1793 xs->resid, xs->datalen); 1794 } 1795 #endif 1796 1797 if (xs->error == XS_NOERROR && 1798 !(scb->flags & SCB_SENSE)) { 1799 struct ahc_dma_seg *sg; 1800 struct scsipi_sense *sc; 1801 struct ahc_initiator_tinfo *tinfo; 1802 struct tmode_tstate *tstate; 1803 1804 sg = scb->sg_list; 1805 sc = (struct scsipi_sense *)(&hscb->cmdstore); 1806 /* 1807 * Save off the residual if there is one. 1808 */ 1809 if (hscb->residual_SG_count != 0) 1810 ahc_calc_residual(scb); 1811 else 1812 xs->resid = 0; 1813 1814 #ifdef AHC_DEBUG 1815 if (ahc_debug & AHC_SHOWSENSE) { 1816 scsipi_printaddr(xs->xs_periph); 1817 printf("Sending Sense\n"); 1818 } 1819 #endif 1820 sg->addr = ahc->scb_data->sense_busaddr + 1821 (hscb->tag*sizeof(struct scsipi_sense_data)); 1822 sg->len = sizeof (struct scsipi_sense_data); 1823 1824 sc->opcode = REQUEST_SENSE; 1825 sc->byte2 = SCB_LUN(scb) << 5; 1826 sc->unused[0] = 0; 1827 sc->unused[1] = 0; 1828 sc->length = sg->len; 1829 sc->control = 0; 1830 1831 /* 1832 * Would be nice to preserve DISCENB here, 1833 * but due to the way we page SCBs, we can't. 1834 */ 1835 hscb->control = 0; 1836 1837 /* 1838 * This request sense could be because the 1839 * the device lost power or in some other 1840 * way has lost our transfer negotiations. 1841 * Renegotiate if appropriate. Unit attention 1842 * errors will be reported before any data 1843 * phases occur. 1844 */ 1845 ahc_calc_residual(scb); 1846 #if defined(AHC_DEBUG) 1847 if (ahc_debug & AHC_SHOWSENSE) { 1848 scsipi_printaddr(xs->xs_periph); 1849 printf("Sense: datalen %d resid %d" 1850 "chan %d id %d targ %d\n", 1851 xs->datalen, xs->resid, 1852 devinfo.channel, devinfo.our_scsiid, 1853 devinfo.target); 1854 } 1855 #endif 1856 if (xs->datalen > 0 && 1857 xs->resid == xs->datalen) { 1858 tinfo = ahc_fetch_transinfo(ahc, 1859 devinfo.channel, 1860 devinfo.our_scsiid, 1861 devinfo.target, 1862 &tstate); 1863 ahc_update_target_msg_request(ahc, 1864 &devinfo, 1865 tinfo, 1866 /*force*/TRUE, 1867 /*paused*/TRUE); 1868 } 1869 hscb->status = 0; 1870 hscb->SG_count = 1; 1871 hscb->SG_pointer = scb->sg_list_phys; 1872 hscb->data = sg->addr; 1873 hscb->datalen = sg->len; 1874 hscb->cmdpointer = hscb->cmdstore_busaddr; 1875 hscb->cmdlen = sizeof(*sc); 1876 scb->sg_count = hscb->SG_count; 1877 ahc_swap_hscb(hscb); 1878 ahc_swap_sg(scb->sg_list); 1879 scb->flags |= SCB_SENSE; 1880 /* 1881 * Ensure the target is busy since this 1882 * will be an untagged request. 1883 */ 1884 ahc_busy_tcl(ahc, scb); 1885 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1886 1887 /* 1888 * Ensure we have enough time to actually 1889 * retrieve the sense. 1890 */ 1891 if (!(scb->xs->xs_control & XS_CTL_POLL)) { 1892 callout_reset(&scb->xs->xs_callout, 1893 5 * hz, ahc_timeout, scb); 1894 } 1895 } 1896 break; 1897 case SCSI_STATUS_QUEUE_FULL: 1898 case SCSI_STATUS_BUSY: 1899 xs->error = XS_BUSY; 1900 break; 1901 } 1902 break; 1903 } 1904 case TRACE_POINT: 1905 { 1906 printf("SSTAT2 = 0x%x DFCNTRL = 0x%x\n", ahc_inb(ahc, SSTAT2), 1907 ahc_inb(ahc, DFCNTRL)); 1908 printf("SSTAT3 = 0x%x DSTATUS = 0x%x\n", ahc_inb(ahc, SSTAT3), 1909 ahc_inb(ahc, DFSTATUS)); 1910 printf("SSTAT0 = 0x%x, SCB_DATACNT = 0x%x\n", 1911 ahc_inb(ahc, SSTAT0), 1912 ahc_inb(ahc, SCB_DATACNT)); 1913 break; 1914 } 1915 case HOST_MSG_LOOP: 1916 { 1917 /* 1918 * The sequencer has encountered a message phase 1919 * that requires host assistance for completion. 1920 * While handling the message phase(s), we will be 1921 * notified by the sequencer after each byte is 1922 * transferred so we can track bus phases. 1923 * 1924 * If this is the first time we've seen a HOST_MSG_LOOP, 1925 * initialize the state of the host message loop. 1926 */ 1927 if (ahc->msg_type == MSG_TYPE_NONE) { 1928 u_int bus_phase; 1929 1930 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1931 if (bus_phase != P_MESGIN 1932 && bus_phase != P_MESGOUT) { 1933 printf("ahc_intr: HOST_MSG_LOOP bad " 1934 "phase 0x%x\n", 1935 bus_phase); 1936 /* 1937 * Probably transitioned to bus free before 1938 * we got here. Just punt the message. 1939 */ 1940 ahc_clear_intstat(ahc); 1941 restart_sequencer(ahc); 1942 } 1943 1944 if (devinfo.role == ROLE_INITIATOR) { 1945 struct scb *scb; 1946 u_int scb_index; 1947 1948 scb_index = ahc_inb(ahc, SCB_TAG); 1949 scb = &ahc->scb_data->scbarray[scb_index]; 1950 1951 if (bus_phase == P_MESGOUT) 1952 ahc_setup_initiator_msgout(ahc, 1953 &devinfo, 1954 scb); 1955 else { 1956 ahc->msg_type = 1957 MSG_TYPE_INITIATOR_MSGIN; 1958 ahc->msgin_index = 0; 1959 } 1960 } else { 1961 if (bus_phase == P_MESGOUT) { 1962 ahc->msg_type = 1963 MSG_TYPE_TARGET_MSGOUT; 1964 ahc->msgin_index = 0; 1965 } else 1966 /* XXX Ever executed??? */ 1967 ahc_setup_target_msgin(ahc, &devinfo); 1968 } 1969 } 1970 1971 /* Pass a NULL path so that handlers generate their own */ 1972 ahc_handle_message_phase(ahc, /*path*/NULL); 1973 break; 1974 } 1975 case PERR_DETECTED: 1976 { 1977 /* 1978 * If we've cleared the parity error interrupt 1979 * but the sequencer still believes that SCSIPERR 1980 * is true, it must be that the parity error is 1981 * for the currently presented byte on the bus, 1982 * and we are not in a phase (data-in) where we will 1983 * eventually ack this byte. Ack the byte and 1984 * throw it away in the hope that the target will 1985 * take us to message out to deliver the appropriate 1986 * error message. 1987 */ 1988 if ((intstat & SCSIINT) == 0 1989 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1990 u_int curphase; 1991 1992 /* 1993 * The hardware will only let you ack bytes 1994 * if the expected phase in SCSISIGO matches 1995 * the current phase. Make sure this is 1996 * currently the case. 1997 */ 1998 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1999 ahc_outb(ahc, LASTPHASE, curphase); 2000 ahc_outb(ahc, SCSISIGO, curphase); 2001 ahc_inb(ahc, SCSIDATL); 2002 } 2003 break; 2004 } 2005 case DATA_OVERRUN: 2006 { 2007 /* 2008 * When the sequencer detects an overrun, it 2009 * places the controller in "BITBUCKET" mode 2010 * and allows the target to complete its transfer. 2011 * Unfortunately, none of the counters get updated 2012 * when the controller is in this mode, so we have 2013 * no way of knowing how large the overrun was. 2014 */ 2015 u_int scbindex = ahc_inb(ahc, SCB_TAG); 2016 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2017 int i; 2018 2019 scb = &ahc->scb_data->scbarray[scbindex]; 2020 for (i = 0; i < num_phases; i++) { 2021 if (lastphase == phase_table[i].phase) 2022 break; 2023 } 2024 scsipi_printaddr(scb->xs->xs_periph); 2025 printf("data overrun detected %s." 2026 " Tag == 0x%x.\n", 2027 phase_table[i].phasemsg, 2028 scb->hscb->tag); 2029 scsipi_printaddr(scb->xs->xs_periph); 2030 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 2031 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 2032 scb->xs->datalen, scb->sg_count); 2033 if (scb->sg_count > 0) { 2034 for (i = 0; i < scb->sg_count; i++) { 2035 printf("sg[%d] - Addr 0x%x : Length %d\n", 2036 i, 2037 le32toh(scb->sg_list[i].addr), 2038 le32toh(scb->sg_list[i].len)); 2039 } 2040 } 2041 /* 2042 * Set this and it will take affect when the 2043 * target does a command complete. 2044 */ 2045 ahc_freeze_devq(ahc, scb->xs->xs_periph); 2046 ahcsetccbstatus(scb->xs, XS_DRIVER_STUFFUP); 2047 ahc_freeze_ccb(scb); 2048 break; 2049 } 2050 case TRACEPOINT: 2051 { 2052 printf("TRACEPOINT: RETURN_1 = %d\n", ahc_inb(ahc, RETURN_1)); 2053 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 2054 printf("TRACEPOINT: ARG_1 = %d\n", ahc_inb(ahc, ARG_1)); 2055 printf("TRACEPOINT: ARG_2 = %d\n", ahc_inb(ahc, ARG_2)); 2056 printf("TRACEPOINT: CCHADDR = %x\n", 2057 ahc_inb(ahc, CCHADDR) | (ahc_inb(ahc, CCHADDR+1) << 8) 2058 | (ahc_inb(ahc, CCHADDR+2) << 16) 2059 | (ahc_inb(ahc, CCHADDR+3) << 24)); 2060 #if 0 2061 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 2062 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 2063 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 2064 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 2065 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 2066 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2067 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 2068 ahc_inb(ahc, CCHADDR) 2069 | (ahc_inb(ahc, CCHADDR+1) << 8) 2070 | (ahc_inb(ahc, CCHADDR+2) << 16) 2071 | (ahc_inb(ahc, CCHADDR+3) << 24), 2072 ahc_inb(ahc, CCHCNT) 2073 | (ahc_inb(ahc, CCHCNT+1) << 8) 2074 | (ahc_inb(ahc, CCHCNT+2) << 16), 2075 ahc_inb(ahc, SCBPTR)); 2076 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 2077 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 2078 #ifdef DDB 2079 cpu_Debugger(); 2080 #endif 2081 #endif 2082 break; 2083 } 2084 #if NOT_YET 2085 /* XXX Fill these in later */ 2086 case MESG_BUFFER_BUSY: 2087 break; 2088 case MSGIN_PHASEMIS: 2089 break; 2090 #endif 2091 default: 2092 printf("ahc_intr: seqint, " 2093 "intstat == 0x%x, scsisigi = 0x%x\n", 2094 intstat, ahc_inb(ahc, SCSISIGI)); 2095 break; 2096 } 2097 2098 unpause: 2099 /* 2100 * The sequencer is paused immediately on 2101 * a SEQINT, so we should restart it when 2102 * we're done. 2103 */ 2104 unpause_sequencer(ahc); 2105 } 2106 2107 static void 2108 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 2109 { 2110 u_int scb_index; 2111 u_int status; 2112 struct scb *scb; 2113 char cur_channel; 2114 char intr_channel; 2115 2116 if ((ahc->features & AHC_TWIN) != 0 2117 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 2118 cur_channel = 'B'; 2119 else 2120 cur_channel = 'A'; 2121 intr_channel = cur_channel; 2122 2123 status = ahc_inb(ahc, SSTAT1); 2124 if (status == 0) { 2125 if ((ahc->features & AHC_TWIN) != 0) { 2126 /* Try the other channel */ 2127 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2128 status = ahc_inb(ahc, SSTAT1); 2129 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 2130 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 2131 } 2132 if (status == 0) { 2133 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 2134 return; 2135 } 2136 } 2137 2138 scb_index = ahc_inb(ahc, SCB_TAG); 2139 if (scb_index < ahc->scb_data->numscbs) { 2140 scb = &ahc->scb_data->scbarray[scb_index]; 2141 if ((scb->flags & SCB_ACTIVE) == 0 2142 || (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 2143 scb = NULL; 2144 } else 2145 scb = NULL; 2146 2147 if ((status & SCSIRSTI) != 0) { 2148 printf("%s: Someone reset channel %c\n", 2149 ahc_name(ahc), intr_channel); 2150 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 2151 } else if ((status & SCSIPERR) != 0) { 2152 /* 2153 * Determine the bus phase and queue an appropriate message. 2154 * SCSIPERR is latched true as soon as a parity error 2155 * occurs. If the sequencer acked the transfer that 2156 * caused the parity error and the currently presented 2157 * transfer on the bus has correct parity, SCSIPERR will 2158 * be cleared by CLRSCSIPERR. Use this to determine if 2159 * we should look at the last phase the sequencer recorded, 2160 * or the current phase presented on the bus. 2161 */ 2162 u_int mesg_out; 2163 u_int curphase; 2164 u_int errorphase; 2165 u_int lastphase; 2166 int i; 2167 2168 lastphase = ahc_inb(ahc, LASTPHASE); 2169 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2170 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 2171 /* 2172 * For all phases save DATA, the sequencer won't 2173 * automatically ack a byte that has a parity error 2174 * in it. So the only way that the current phase 2175 * could be 'data-in' is if the parity error is for 2176 * an already acked byte in the data phase. During 2177 * synchronous data-in transfers, we may actually 2178 * ack bytes before latching the current phase in 2179 * LASTPHASE, leading to the discrepancy between 2180 * curphase and lastphase. 2181 */ 2182 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 2183 || curphase == P_DATAIN) 2184 errorphase = curphase; 2185 else 2186 errorphase = lastphase; 2187 2188 for (i = 0; i < num_phases; i++) { 2189 if (errorphase == phase_table[i].phase) 2190 break; 2191 } 2192 mesg_out = phase_table[i].mesg_out; 2193 if (scb != NULL) 2194 scsipi_printaddr(scb->xs->xs_periph); 2195 else 2196 printf("%s:%c:%d: ", ahc_name(ahc), 2197 intr_channel, 2198 TCL_TARGET(ahc_inb(ahc, SAVED_TCL))); 2199 2200 printf("parity error detected %s. " 2201 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 2202 phase_table[i].phasemsg, 2203 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 2204 ahc_inb(ahc, SCSIRATE)); 2205 2206 /* 2207 * We've set the hardware to assert ATN if we 2208 * get a parity error on "in" phases, so all we 2209 * need to do is stuff the message buffer with 2210 * the appropriate message. "In" phases have set 2211 * mesg_out to something other than MSG_NOP. 2212 */ 2213 if (mesg_out != MSG_NOOP) { 2214 if (ahc->msg_type != MSG_TYPE_NONE) 2215 ahc->send_msg_perror = TRUE; 2216 else 2217 ahc_outb(ahc, MSG_OUT, mesg_out); 2218 } 2219 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2220 unpause_sequencer(ahc); 2221 } else if ((status & BUSFREE) != 0 2222 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 2223 /* 2224 * First look at what phase we were last in. 2225 * If its message out, chances are pretty good 2226 * that the busfree was in response to one of 2227 * our abort requests. 2228 */ 2229 u_int lastphase = ahc_inb(ahc, LASTPHASE); 2230 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 2231 u_int target = TCL_TARGET(saved_tcl); 2232 u_int initiator_role_id = TCL_SCSI_ID(ahc, saved_tcl); 2233 char channel = TCL_CHANNEL(ahc, saved_tcl); 2234 int printerror = 1; 2235 2236 ahc_outb(ahc, SCSISEQ, 2237 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 2238 if (lastphase == P_MESGOUT) { 2239 u_int message; 2240 u_int tag; 2241 2242 message = ahc->msgout_buf[ahc->msgout_index - 1]; 2243 tag = SCB_LIST_NULL; 2244 switch (message) { 2245 case MSG_ABORT_TAG: 2246 tag = scb->hscb->tag; 2247 /* FALLTRHOUGH */ 2248 case MSG_ABORT: 2249 scsipi_printaddr(scb->xs->xs_periph); 2250 printf("SCB %x - Abort %s Completed.\n", 2251 scb->hscb->tag, tag == SCB_LIST_NULL ? 2252 "" : "Tag"); 2253 ahc_abort_scbs(ahc, target, channel, 2254 TCL_LUN(saved_tcl), tag, 2255 ROLE_INITIATOR, 2256 XS_DRIVER_STUFFUP); 2257 printerror = 0; 2258 break; 2259 case MSG_BUS_DEV_RESET: 2260 { 2261 struct ahc_devinfo devinfo; 2262 2263 if (scb != NULL && 2264 (scb->xs->xs_control & XS_CTL_RESET) 2265 && ahc_match_scb(scb, target, channel, 2266 TCL_LUN(saved_tcl), 2267 SCB_LIST_NULL, 2268 ROLE_INITIATOR)) { 2269 ahcsetccbstatus(scb->xs, XS_NOERROR); 2270 } 2271 ahc_compile_devinfo(&devinfo, 2272 initiator_role_id, 2273 target, 2274 TCL_LUN(saved_tcl), 2275 channel, 2276 ROLE_INITIATOR); 2277 ahc_handle_devreset(ahc, &devinfo, 2278 XS_RESET, 2279 "Bus Device Reset", 2280 /*verbose_level*/0); 2281 printerror = 0; 2282 break; 2283 } 2284 default: 2285 break; 2286 } 2287 } 2288 if (printerror != 0) { 2289 int i; 2290 2291 if (scb != NULL) { 2292 u_int tag; 2293 2294 if ((scb->hscb->control & TAG_ENB) != 0) 2295 tag = scb->hscb->tag; 2296 else 2297 tag = SCB_LIST_NULL; 2298 ahc_abort_scbs(ahc, target, channel, 2299 SCB_LUN(scb), tag, 2300 ROLE_INITIATOR, 2301 XS_DRIVER_STUFFUP); 2302 scsipi_printaddr(scb->xs->xs_periph); 2303 } else { 2304 /* 2305 * We had not fully identified this connection, 2306 * so we cannot abort anything. 2307 */ 2308 printf("%s: ", ahc_name(ahc)); 2309 } 2310 for (i = 0; i < num_phases; i++) { 2311 if (lastphase == phase_table[i].phase) 2312 break; 2313 } 2314 printf("Unexpected busfree %s\n" 2315 "SEQADDR == 0x%x\n", 2316 phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) 2317 | (ahc_inb(ahc, SEQADDR1) << 8)); 2318 } 2319 ahc_clear_msg_state(ahc); 2320 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 2321 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 2322 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2323 restart_sequencer(ahc); 2324 } else if ((status & SELTO) != 0) { 2325 u_int scbptr; 2326 2327 scbptr = ahc_inb(ahc, WAITING_SCBH); 2328 ahc_outb(ahc, SCBPTR, scbptr); 2329 scb_index = ahc_inb(ahc, SCB_TAG); 2330 2331 if (scb_index < ahc->scb_data->numscbs) { 2332 scb = &ahc->scb_data->scbarray[scb_index]; 2333 if ((scb->flags & SCB_ACTIVE) == 0) 2334 scb = NULL; 2335 } else 2336 scb = NULL; 2337 2338 if (scb == NULL) { 2339 printf("%s: ahc_intr - referenced scb not " 2340 "valid during SELTO scb(%d, %d)\n", 2341 ahc_name(ahc), scbptr, scb_index); 2342 } else { 2343 u_int tag; 2344 2345 tag = SCB_LIST_NULL; 2346 if ((scb->hscb->control & TAG_ENB) != 0) 2347 tag = scb->hscb->tag; 2348 2349 ahc_abort_scbs(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2350 SCB_LUN(scb), tag, 2351 ROLE_INITIATOR, XS_SELTIMEOUT); 2352 } 2353 /* Stop the selection */ 2354 ahc_outb(ahc, SCSISEQ, 0); 2355 2356 /* No more pending messages */ 2357 ahc_clear_msg_state(ahc); 2358 2359 /* 2360 * Although the driver does not care about the 2361 * 'Selection in Progress' status bit, the busy 2362 * LED does. SELINGO is only cleared by a sucessful 2363 * selection, so we must manually clear it to ensure 2364 * the LED turns off just incase no future successful 2365 * selections occur (e.g. no devices on the bus). 2366 */ 2367 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 2368 2369 /* Clear interrupt state */ 2370 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2371 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2372 restart_sequencer(ahc); 2373 } else { 2374 scsipi_printaddr(scb->xs->xs_periph); 2375 printf("Unknown SCSIINT. Status = 0x%x\n", status); 2376 ahc_outb(ahc, CLRSINT1, status); 2377 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2378 unpause_sequencer(ahc); 2379 } 2380 } 2381 2382 static void 2383 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2384 { 2385 /* 2386 * We need to initiate transfer negotiations. 2387 * If our current and goal settings are identical, 2388 * we want to renegotiate due to a check condition. 2389 */ 2390 struct ahc_initiator_tinfo *tinfo; 2391 struct tmode_tstate *tstate; 2392 int dowide; 2393 int dosync; 2394 2395 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2396 devinfo->target, &tstate); 2397 dowide = tinfo->current.width != tinfo->goal.width; 2398 dosync = tinfo->current.period != tinfo->goal.period; 2399 2400 if (!dowide && !dosync) { 2401 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2402 dosync = tinfo->goal.period != 0; 2403 } 2404 2405 if (dowide) { 2406 ahc_construct_wdtr(ahc, tinfo->goal.width); 2407 } else if (dosync) { 2408 const struct ahc_syncrate *rate; 2409 u_int period; 2410 u_int offset; 2411 2412 period = tinfo->goal.period; 2413 rate = ahc_devlimited_syncrate(ahc, &period); 2414 offset = tinfo->goal.offset; 2415 ahc_validate_offset(ahc, rate, &offset, 2416 tinfo->current.width); 2417 ahc_construct_sdtr(ahc, period, offset); 2418 } else { 2419 panic("ahc_intr: AWAITING_MSG for negotiation, " 2420 "but no negotiation needed\n"); 2421 } 2422 } 2423 2424 static void 2425 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2426 struct scb *scb) 2427 { 2428 /* 2429 * To facilitate adding multiple messages together, 2430 * each routine should increment the index and len 2431 * variables instead of setting them explicitly. 2432 */ 2433 ahc->msgout_index = 0; 2434 ahc->msgout_len = 0; 2435 2436 if ((scb->flags & SCB_DEVICE_RESET) == 0 2437 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2438 u_int identify_msg; 2439 2440 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 2441 if ((scb->hscb->control & DISCENB) != 0) 2442 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2443 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2444 ahc->msgout_len++; 2445 2446 if ((scb->hscb->control & TAG_ENB) != 0) { 2447 ahc->msgout_buf[ahc->msgout_index++] = 2448 scb->xs->xs_tag_type; 2449 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2450 ahc->msgout_len += 2; 2451 } 2452 } 2453 2454 if (scb->flags & SCB_DEVICE_RESET) { 2455 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2456 ahc->msgout_len++; 2457 scsipi_printaddr(scb->xs->xs_periph); 2458 printf("Bus Device Reset Message Sent\n"); 2459 } else if (scb->flags & SCB_ABORT) { 2460 if ((scb->hscb->control & TAG_ENB) != 0) 2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2462 else 2463 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2464 ahc->msgout_len++; 2465 scsipi_printaddr(scb->xs->xs_periph); 2466 printf("Abort Message Sent\n"); 2467 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2468 ahc_build_transfer_msg(ahc, devinfo); 2469 } else { 2470 printf("ahc_intr: AWAITING_MSG for an SCB that " 2471 "does not have a waiting message"); 2472 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2473 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2474 ahc_inb(ahc, MSG_OUT), scb->flags); 2475 } 2476 2477 /* 2478 * Clear the MK_MESSAGE flag from the SCB so we aren't 2479 * asked to send this message again. 2480 */ 2481 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2482 ahc->msgout_index = 0; 2483 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2484 } 2485 2486 static void 2487 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2488 { 2489 /* 2490 * To facilitate adding multiple messages together, 2491 * each routine should increment the index and len 2492 * variables instead of setting them explicitly. 2493 */ 2494 ahc->msgout_index = 0; 2495 ahc->msgout_len = 0; 2496 2497 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2498 ahc_build_transfer_msg(ahc, devinfo); 2499 else 2500 panic("ahc_intr: AWAITING target message with no message"); 2501 2502 ahc->msgout_index = 0; 2503 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2504 } 2505 2506 static int 2507 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2508 { 2509 /* 2510 * What we care about here is if we had an 2511 * outstanding SDTR or WDTR message for this 2512 * target. If we did, this is a signal that 2513 * the target is refusing negotiation. 2514 */ 2515 struct scb *scb; 2516 u_int scb_index; 2517 u_int last_msg; 2518 int response = 0; 2519 2520 scb_index = ahc_inb(ahc, SCB_TAG); 2521 scb = &ahc->scb_data->scbarray[scb_index]; 2522 2523 /* Might be necessary */ 2524 last_msg = ahc_inb(ahc, LAST_MSG); 2525 2526 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2527 struct ahc_initiator_tinfo *tinfo; 2528 struct tmode_tstate *tstate; 2529 2530 #ifdef AHC_DEBUG_NEG 2531 /* note 8bit xfers */ 2532 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2533 "8bit transfers\n", ahc_name(ahc), 2534 devinfo->channel, devinfo->target); 2535 #endif 2536 ahc_set_width(ahc, devinfo, 2537 MSG_EXT_WDTR_BUS_8_BIT, 2538 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2539 /*paused*/TRUE, /*done*/TRUE); 2540 /* 2541 * No need to clear the sync rate. If the target 2542 * did not accept the command, our syncrate is 2543 * unaffected. If the target started the negotiation, 2544 * but rejected our response, we already cleared the 2545 * sync rate before sending our WDTR. 2546 */ 2547 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 2548 devinfo->our_scsiid, 2549 devinfo->target, &tstate); 2550 if (tinfo->goal.period) { 2551 u_int period; 2552 2553 /* Start the sync negotiation */ 2554 period = tinfo->goal.period; 2555 ahc_devlimited_syncrate(ahc, &period); 2556 ahc->msgout_index = 0; 2557 ahc->msgout_len = 0; 2558 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2559 ahc->msgout_index = 0; 2560 response = 1; 2561 } else 2562 ahc_update_xfer_mode(ahc, devinfo); 2563 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2564 /* note asynch xfers and clear flag */ 2565 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 2566 /*offset*/0, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2567 /*paused*/TRUE, /*done*/TRUE); 2568 #ifdef AHC_DEBUG_NEG 2569 printf("%s:%c:%d: refuses synchronous negotiation. " 2570 "Using asynchronous transfers\n", 2571 ahc_name(ahc), 2572 devinfo->channel, devinfo->target); 2573 #endif 2574 ahc_update_xfer_mode(ahc, devinfo); 2575 } else if ((scb->hscb->control & TAG_ENB) != 0) { 2576 printf("%s:%c:%d: refuses tagged commands. Performing " 2577 "non-tagged I/O\n", ahc_name(ahc), 2578 devinfo->channel, devinfo->target); 2579 2580 ahc_set_tags(ahc, devinfo, FALSE); 2581 ahc_update_xfer_mode(ahc, devinfo); 2582 2583 /* 2584 * Resend the identify for this CCB as the target 2585 * may believe that the selection is invalid otherwise. 2586 */ 2587 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2588 & ~MSG_SIMPLE_Q_TAG); 2589 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2590 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2591 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2592 2593 /* 2594 * Requeue all tagged commands for this target 2595 * currently in our posession so they can be 2596 * converted to untagged commands. 2597 */ 2598 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2599 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2600 ROLE_INITIATOR, SCB_REQUEUE, 2601 SEARCH_COMPLETE); 2602 } else { 2603 /* 2604 * Otherwise, we ignore it. 2605 */ 2606 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2607 ahc_name(ahc), devinfo->channel, devinfo->target, 2608 last_msg); 2609 } 2610 return (response); 2611 } 2612 2613 static void 2614 ahc_clear_msg_state(struct ahc_softc *ahc) 2615 { 2616 ahc->msgout_len = 0; 2617 ahc->msgin_index = 0; 2618 ahc->msg_type = MSG_TYPE_NONE; 2619 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2620 } 2621 2622 static void 2623 ahc_handle_message_phase(struct ahc_softc *ahc, struct scsipi_periph *periph) 2624 { 2625 struct ahc_devinfo devinfo; 2626 u_int bus_phase; 2627 int end_session; 2628 2629 ahc_fetch_devinfo(ahc, &devinfo); 2630 end_session = FALSE; 2631 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2632 2633 reswitch: 2634 switch (ahc->msg_type) { 2635 case MSG_TYPE_INITIATOR_MSGOUT: 2636 { 2637 int lastbyte; 2638 int phasemis; 2639 int msgdone; 2640 2641 if (ahc->msgout_len == 0) 2642 panic("REQINIT interrupt with no active message"); 2643 2644 phasemis = bus_phase != P_MESGOUT; 2645 if (phasemis) { 2646 if (bus_phase == P_MESGIN) { 2647 /* 2648 * Change gears and see if 2649 * this messages is of interest to 2650 * us or should be passed back to 2651 * the sequencer. 2652 */ 2653 ahc_outb(ahc, CLRSINT1, CLRATNO); 2654 ahc->send_msg_perror = FALSE; 2655 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2656 ahc->msgin_index = 0; 2657 goto reswitch; 2658 } 2659 end_session = TRUE; 2660 break; 2661 } 2662 2663 if (ahc->send_msg_perror) { 2664 ahc_outb(ahc, CLRSINT1, CLRATNO); 2665 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2666 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2667 break; 2668 } 2669 2670 msgdone = ahc->msgout_index == ahc->msgout_len; 2671 if (msgdone) { 2672 /* 2673 * The target has requested a retry. 2674 * Re-assert ATN, reset our message index to 2675 * 0, and try again. 2676 */ 2677 ahc->msgout_index = 0; 2678 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2679 } 2680 2681 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2682 if (lastbyte) { 2683 /* Last byte is signified by dropping ATN */ 2684 ahc_outb(ahc, CLRSINT1, CLRATNO); 2685 } 2686 2687 /* 2688 * Clear our interrupt status and present 2689 * the next byte on the bus. 2690 */ 2691 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2692 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2693 break; 2694 } 2695 case MSG_TYPE_INITIATOR_MSGIN: 2696 { 2697 int phasemis; 2698 int message_done; 2699 2700 phasemis = bus_phase != P_MESGIN; 2701 2702 if (phasemis) { 2703 ahc->msgin_index = 0; 2704 if (bus_phase == P_MESGOUT 2705 && (ahc->send_msg_perror == TRUE 2706 || (ahc->msgout_len != 0 2707 && ahc->msgout_index == 0))) { 2708 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2709 goto reswitch; 2710 } 2711 end_session = TRUE; 2712 break; 2713 } 2714 2715 /* Pull the byte in without acking it */ 2716 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2717 2718 message_done = ahc_parse_msg(ahc, periph, &devinfo); 2719 2720 if (message_done) { 2721 /* 2722 * Clear our incoming message buffer in case there 2723 * is another message following this one. 2724 */ 2725 ahc->msgin_index = 0; 2726 2727 /* 2728 * If this message illicited a response, 2729 * assert ATN so the target takes us to the 2730 * message out phase. 2731 */ 2732 if (ahc->msgout_len != 0) 2733 ahc_outb(ahc, SCSISIGO, 2734 ahc_inb(ahc, SCSISIGO) | ATNO); 2735 } else 2736 ahc->msgin_index++; 2737 2738 /* Ack the byte */ 2739 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2740 ahc_inb(ahc, SCSIDATL); 2741 break; 2742 } 2743 case MSG_TYPE_TARGET_MSGIN: 2744 { 2745 int msgdone; 2746 int msgout_request; 2747 2748 if (ahc->msgout_len == 0) 2749 panic("Target MSGIN with no active message"); 2750 2751 /* 2752 * If we interrupted a mesgout session, the initiator 2753 * will not know this until our first REQ. So, we 2754 * only honor mesgout requests after we've sent our 2755 * first byte. 2756 */ 2757 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2758 && ahc->msgout_index > 0) 2759 msgout_request = TRUE; 2760 else 2761 msgout_request = FALSE; 2762 2763 if (msgout_request) { 2764 2765 /* 2766 * Change gears and see if 2767 * this messages is of interest to 2768 * us or should be passed back to 2769 * the sequencer. 2770 */ 2771 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2772 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2773 ahc->msgin_index = 0; 2774 /* Dummy read to REQ for first byte */ 2775 ahc_inb(ahc, SCSIDATL); 2776 ahc_outb(ahc, SXFRCTL0, 2777 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2778 break; 2779 } 2780 2781 msgdone = ahc->msgout_index == ahc->msgout_len; 2782 if (msgdone) { 2783 ahc_outb(ahc, SXFRCTL0, 2784 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2785 end_session = TRUE; 2786 break; 2787 } 2788 2789 /* 2790 * Present the next byte on the bus. 2791 */ 2792 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2793 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2794 break; 2795 } 2796 case MSG_TYPE_TARGET_MSGOUT: 2797 { 2798 int lastbyte; 2799 int msgdone; 2800 2801 /* 2802 * The initiator signals that this is 2803 * the last byte by dropping ATN. 2804 */ 2805 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2806 2807 /* 2808 * Read the latched byte, but turn off SPIOEN first 2809 * so that we don't inadvertantly cause a REQ for the 2810 * next byte. 2811 */ 2812 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2813 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2814 msgdone = ahc_parse_msg(ahc, periph, &devinfo); 2815 if (msgdone == MSGLOOP_TERMINATED) { 2816 /* 2817 * The message is *really* done in that it caused 2818 * us to go to bus free. The sequencer has already 2819 * been reset at this point, so pull the ejection 2820 * handle. 2821 */ 2822 return; 2823 } 2824 2825 ahc->msgin_index++; 2826 2827 /* 2828 * XXX Read spec about initiator dropping ATN too soon 2829 * and use msgdone to detect it. 2830 */ 2831 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2832 ahc->msgin_index = 0; 2833 2834 /* 2835 * If this message illicited a response, transition 2836 * to the Message in phase and send it. 2837 */ 2838 if (ahc->msgout_len != 0) { 2839 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2840 ahc_outb(ahc, SXFRCTL0, 2841 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2842 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2843 ahc->msgin_index = 0; 2844 break; 2845 } 2846 } 2847 2848 if (lastbyte) 2849 end_session = TRUE; 2850 else { 2851 /* Ask for the next byte. */ 2852 ahc_outb(ahc, SXFRCTL0, 2853 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2854 } 2855 2856 break; 2857 } 2858 default: 2859 panic("Unknown REQINIT message type"); 2860 } 2861 2862 if (end_session) { 2863 ahc_clear_msg_state(ahc); 2864 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2865 } else 2866 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2867 } 2868 2869 /* 2870 * See if we sent a particular extended message to the target. 2871 * If "full" is true, the target saw the full message. 2872 * If "full" is false, the target saw at least the first 2873 * byte of the message. 2874 */ 2875 static int 2876 ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2877 { 2878 int found; 2879 int index; 2880 2881 found = FALSE; 2882 index = 0; 2883 2884 while (index < ahc->msgout_len) { 2885 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2886 2887 /* Found a candidate */ 2888 if (ahc->msgout_buf[index+2] == msgtype) { 2889 u_int end_index; 2890 2891 end_index = index + 1 2892 + ahc->msgout_buf[index + 1]; 2893 if (full) { 2894 if (ahc->msgout_index > end_index) 2895 found = TRUE; 2896 } else if (ahc->msgout_index > index) 2897 found = TRUE; 2898 } 2899 break; 2900 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2901 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2902 2903 /* Skip tag type and tag id or residue param*/ 2904 index += 2; 2905 } else { 2906 /* Single byte message */ 2907 index++; 2908 } 2909 } 2910 return (found); 2911 } 2912 2913 static int 2914 ahc_parse_msg(struct ahc_softc *ahc, struct scsipi_periph *periph, 2915 struct ahc_devinfo *devinfo) 2916 { 2917 struct ahc_initiator_tinfo *tinfo; 2918 struct tmode_tstate *tstate; 2919 int reject; 2920 int done; 2921 int response; 2922 u_int targ_scsirate; 2923 2924 done = MSGLOOP_IN_PROG; 2925 response = FALSE; 2926 reject = FALSE; 2927 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2928 devinfo->target, &tstate); 2929 targ_scsirate = tinfo->scsirate; 2930 2931 /* 2932 * Parse as much of the message as is available, 2933 * rejecting it if we don't support it. When 2934 * the entire message is available and has been 2935 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2936 * that we have parsed an entire message. 2937 * 2938 * In the case of extended messages, we accept the length 2939 * byte outright and perform more checking once we know the 2940 * extended message type. 2941 */ 2942 switch (ahc->msgin_buf[0]) { 2943 case MSG_MESSAGE_REJECT: 2944 response = ahc_handle_msg_reject(ahc, devinfo); 2945 /* FALLTHROUGH */ 2946 case MSG_NOOP: 2947 done = MSGLOOP_MSGCOMPLETE; 2948 break; 2949 case MSG_IGN_WIDE_RESIDUE: 2950 { 2951 /* Wait for the whole message */ 2952 if (ahc->msgin_index >= 1) { 2953 if (ahc->msgin_buf[1] != 1 2954 || tinfo->current.width == MSG_EXT_WDTR_BUS_8_BIT) { 2955 reject = TRUE; 2956 done = MSGLOOP_MSGCOMPLETE; 2957 } else 2958 ahc_handle_ign_wide_residue(ahc, devinfo); 2959 } 2960 break; 2961 } 2962 case MSG_EXTENDED: 2963 { 2964 /* Wait for enough of the message to begin validation */ 2965 if (ahc->msgin_index < 2) 2966 break; 2967 switch (ahc->msgin_buf[2]) { 2968 case MSG_EXT_SDTR: 2969 { 2970 const struct ahc_syncrate *syncrate; 2971 u_int period; 2972 u_int offset; 2973 u_int saved_offset; 2974 2975 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2976 reject = TRUE; 2977 break; 2978 } 2979 2980 /* 2981 * Wait until we have both args before validating 2982 * and acting on this message. 2983 * 2984 * Add one to MSG_EXT_SDTR_LEN to account for 2985 * the extended message preamble. 2986 */ 2987 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2988 break; 2989 2990 period = ahc->msgin_buf[3]; 2991 saved_offset = offset = ahc->msgin_buf[4]; 2992 syncrate = ahc_devlimited_syncrate(ahc, &period); 2993 ahc_validate_offset(ahc, syncrate, &offset, 2994 targ_scsirate & WIDEXFER); 2995 ahc_set_syncrate(ahc, devinfo, 2996 syncrate, period, offset, 2997 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2998 /*paused*/TRUE, /*done*/TRUE); 2999 ahc_update_xfer_mode(ahc, devinfo); 3000 3001 /* 3002 * See if we initiated Sync Negotiation 3003 * and didn't have to fall down to async 3004 * transfers. 3005 */ 3006 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 3007 /* We started it */ 3008 if (saved_offset != offset) { 3009 /* Went too low - force async */ 3010 reject = TRUE; 3011 } 3012 } else { 3013 /* 3014 * Send our own SDTR in reply 3015 */ 3016 ahc->msgout_index = 0; 3017 ahc->msgout_len = 0; 3018 ahc_construct_sdtr(ahc, period, offset); 3019 ahc->msgout_index = 0; 3020 response = TRUE; 3021 } 3022 done = MSGLOOP_MSGCOMPLETE; 3023 break; 3024 } 3025 case MSG_EXT_WDTR: 3026 { 3027 u_int bus_width; 3028 u_int sending_reply; 3029 3030 sending_reply = FALSE; 3031 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3032 reject = TRUE; 3033 break; 3034 } 3035 3036 /* 3037 * Wait until we have our arg before validating 3038 * and acting on this message. 3039 * 3040 * Add one to MSG_EXT_WDTR_LEN to account for 3041 * the extended message preamble. 3042 */ 3043 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3044 break; 3045 3046 bus_width = ahc->msgin_buf[3]; 3047 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 3048 /* 3049 * Don't send a WDTR back to the 3050 * target, since we asked first. 3051 */ 3052 switch (bus_width){ 3053 default: 3054 /* 3055 * How can we do anything greater 3056 * than 16bit transfers on a 16bit 3057 * bus? 3058 */ 3059 reject = TRUE; 3060 printf("%s: target %d requested %dBit " 3061 "transfers. Rejecting...\n", 3062 ahc_name(ahc), devinfo->target, 3063 8 * (0x01 << bus_width)); 3064 /* FALLTHROUGH */ 3065 case MSG_EXT_WDTR_BUS_8_BIT: 3066 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3067 break; 3068 case MSG_EXT_WDTR_BUS_16_BIT: 3069 break; 3070 } 3071 } else { 3072 /* 3073 * Send our own WDTR in reply 3074 */ 3075 switch (bus_width) { 3076 default: 3077 if (ahc->features & AHC_WIDE) { 3078 /* Respond Wide */ 3079 bus_width = 3080 MSG_EXT_WDTR_BUS_16_BIT; 3081 break; 3082 } 3083 /* FALLTHROUGH */ 3084 case MSG_EXT_WDTR_BUS_8_BIT: 3085 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3086 break; 3087 } 3088 ahc->msgout_index = 0; 3089 ahc->msgout_len = 0; 3090 ahc_construct_wdtr(ahc, bus_width); 3091 ahc->msgout_index = 0; 3092 response = TRUE; 3093 sending_reply = TRUE; 3094 } 3095 ahc_set_width(ahc, devinfo, bus_width, 3096 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3097 /*paused*/TRUE, /*done*/TRUE); 3098 3099 /* After a wide message, we are async */ 3100 ahc_set_syncrate(ahc, devinfo, 3101 /*syncrate*/NULL, /*period*/0, 3102 /*offset*/0, AHC_TRANS_ACTIVE, 3103 /*paused*/TRUE, /*done*/FALSE); 3104 if (sending_reply == FALSE && reject == FALSE) { 3105 3106 if (tinfo->goal.period) { 3107 const struct ahc_syncrate *rate; 3108 u_int period; 3109 u_int offset; 3110 3111 /* Start the sync negotiation */ 3112 period = tinfo->goal.period; 3113 rate = ahc_devlimited_syncrate(ahc, 3114 &period); 3115 offset = tinfo->goal.offset; 3116 ahc_validate_offset(ahc, rate, &offset, 3117 tinfo->current.width); 3118 ahc->msgout_index = 0; 3119 ahc->msgout_len = 0; 3120 ahc_construct_sdtr(ahc, period, offset); 3121 ahc->msgout_index = 0; 3122 response = TRUE; 3123 } else 3124 ahc_update_xfer_mode(ahc, devinfo); 3125 } 3126 done = MSGLOOP_MSGCOMPLETE; 3127 break; 3128 } 3129 default: 3130 /* Unknown extended message. Reject it. */ 3131 reject = TRUE; 3132 break; 3133 } 3134 break; 3135 } 3136 case MSG_BUS_DEV_RESET: 3137 ahc_handle_devreset(ahc, devinfo, 3138 XS_RESET, "Bus Device Reset Received", 3139 /*verbose_level*/0); 3140 restart_sequencer(ahc); 3141 done = MSGLOOP_TERMINATED; 3142 break; 3143 case MSG_ABORT_TAG: 3144 case MSG_ABORT: 3145 case MSG_CLEAR_QUEUE: 3146 /* Target mode messages */ 3147 if (devinfo->role != ROLE_TARGET) { 3148 reject = TRUE; 3149 break; 3150 } 3151 #if AHC_TARGET_MODE 3152 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3153 devinfo->lun, 3154 ahc->msgin_buf[0] == MSG_ABORT_TAG 3155 ? SCB_LIST_NULL 3156 : ahc_inb(ahc, INITIATOR_TAG), 3157 ROLE_TARGET, XS_DRIVER_STUFFUP); 3158 3159 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3160 if (tstate != NULL) { 3161 struct tmode_lstate* lstate; 3162 3163 lstate = tstate->enabled_luns[devinfo->lun]; 3164 if (lstate != NULL) { 3165 ahc_queue_lstate_event(ahc, lstate, 3166 devinfo->our_scsiid, 3167 ahc->msgin_buf[0], 3168 /*arg*/0); 3169 ahc_send_lstate_events(ahc, lstate); 3170 } 3171 } 3172 done = MSGLOOP_MSGCOMPLETE; 3173 #else 3174 panic("ahc: got target mode message"); 3175 #endif 3176 break; 3177 case MSG_TERM_IO_PROC: 3178 default: 3179 reject = TRUE; 3180 break; 3181 } 3182 3183 if (reject) { 3184 /* 3185 * Setup to reject the message. 3186 */ 3187 ahc->msgout_index = 0; 3188 ahc->msgout_len = 1; 3189 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3190 done = MSGLOOP_MSGCOMPLETE; 3191 response = TRUE; 3192 } 3193 3194 if (done != MSGLOOP_IN_PROG && !response) 3195 /* Clear the outgoing message buffer */ 3196 ahc->msgout_len = 0; 3197 3198 return (done); 3199 } 3200 3201 static void 3202 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3203 { 3204 u_int scb_index; 3205 struct scb *scb; 3206 3207 scb_index = ahc_inb(ahc, SCB_TAG); 3208 scb = &ahc->scb_data->scbarray[scb_index]; 3209 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3210 || !(scb->xs->xs_control & XS_CTL_DATA_IN)) { 3211 /* 3212 * Ignore the message if we haven't 3213 * seen an appropriate data phase yet. 3214 */ 3215 } else { 3216 /* 3217 * If the residual occurred on the last 3218 * transfer and the transfer request was 3219 * expected to end on an odd count, do 3220 * nothing. Otherwise, subtract a byte 3221 * and update the residual count accordingly. 3222 */ 3223 u_int resid_sgcnt; 3224 3225 resid_sgcnt = ahc_inb(ahc, SCB_RESID_SGCNT); 3226 if (resid_sgcnt == 0 3227 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3228 /* 3229 * If the residual occurred on the last 3230 * transfer and the transfer request was 3231 * expected to end on an odd count, do 3232 * nothing. 3233 */ 3234 } else { 3235 u_int data_cnt; 3236 u_int32_t data_addr; 3237 u_int sg_index; 3238 3239 data_cnt = (ahc_inb(ahc, SCB_RESID_DCNT + 2) << 16) 3240 | (ahc_inb(ahc, SCB_RESID_DCNT + 1) << 8) 3241 | (ahc_inb(ahc, SCB_RESID_DCNT)); 3242 3243 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3244 | (ahc_inb(ahc, SHADDR + 2) << 16) 3245 | (ahc_inb(ahc, SHADDR + 1) << 8) 3246 | (ahc_inb(ahc, SHADDR)); 3247 3248 data_cnt += 1; 3249 data_addr -= 1; 3250 3251 sg_index = scb->sg_count - resid_sgcnt; 3252 3253 if (sg_index != 0 3254 && (le32toh(scb->sg_list[sg_index].len) < data_cnt)) { 3255 u_int32_t sg_addr; 3256 3257 sg_index--; 3258 data_cnt = 1; 3259 data_addr = le32toh(scb->sg_list[sg_index].addr) 3260 + le32toh(scb->sg_list[sg_index].len) 3261 - 1; 3262 3263 /* 3264 * The physical address base points to the 3265 * second entry as it is always used for 3266 * calculating the "next S/G pointer". 3267 */ 3268 sg_addr = scb->sg_list_phys 3269 + (sg_index* sizeof(*scb->sg_list)); 3270 ahc_outb(ahc, SG_NEXT + 3, sg_addr >> 24); 3271 ahc_outb(ahc, SG_NEXT + 2, sg_addr >> 16); 3272 ahc_outb(ahc, SG_NEXT + 1, sg_addr >> 8); 3273 ahc_outb(ahc, SG_NEXT, sg_addr); 3274 } 3275 3276 ahc_outb(ahc, SCB_RESID_DCNT + 2, data_cnt >> 16); 3277 ahc_outb(ahc, SCB_RESID_DCNT + 1, data_cnt >> 8); 3278 ahc_outb(ahc, SCB_RESID_DCNT, data_cnt); 3279 3280 ahc_outb(ahc, SHADDR + 3, data_addr >> 24); 3281 ahc_outb(ahc, SHADDR + 2, data_addr >> 16); 3282 ahc_outb(ahc, SHADDR + 1, data_addr >> 8); 3283 ahc_outb(ahc, SHADDR, data_addr); 3284 } 3285 } 3286 } 3287 3288 static void 3289 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3290 int status, char *message, 3291 int verbose_level) 3292 { 3293 int found; 3294 3295 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3296 AHC_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3297 status); 3298 3299 /* 3300 * Go back to async/narrow transfers and renegotiate. 3301 * ahc_set_width and ahc_set_syncrate can cope with NULL 3302 * paths. 3303 */ 3304 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3305 AHC_TRANS_CUR, /*paused*/TRUE, /*done*/FALSE); 3306 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3307 /*period*/0, /*offset*/0, AHC_TRANS_CUR, 3308 /*paused*/TRUE, /*done*/FALSE); 3309 ahc_update_xfer_mode(ahc, devinfo); 3310 3311 if (message != NULL && (verbose_level <= 0)) 3312 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3313 message, devinfo->channel, devinfo->target, found); 3314 } 3315 3316 /* 3317 * We have an scb which has been processed by the 3318 * adaptor, now we look to see how the operation 3319 * went. 3320 */ 3321 static void 3322 ahc_done(struct ahc_softc *ahc, struct scb *scb) 3323 { 3324 struct scsipi_xfer *xs; 3325 struct scsipi_periph *periph; 3326 int requeue = 0; 3327 int target; 3328 3329 3330 xs = scb->xs; 3331 periph = xs->xs_periph; 3332 LIST_REMOVE(scb, plinks); 3333 3334 callout_stop(&scb->xs->xs_callout); 3335 3336 #ifdef AHC_DEBUG 3337 if (ahc_debug & AHC_SHOWCMDS) { 3338 scsipi_printaddr(periph); 3339 printf("ahc_done opcode %d tag %x\n", xs->cmdstore.opcode, 3340 scb->hscb->tag); 3341 } 3342 #endif 3343 3344 target = periph->periph_target; 3345 3346 if (xs->datalen) { 3347 int op; 3348 3349 if (xs->xs_control & XS_CTL_DATA_IN) 3350 op = BUS_DMASYNC_POSTREAD; 3351 else 3352 op = BUS_DMASYNC_POSTWRITE; 3353 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 3354 scb->dmamap->dm_mapsize, op); 3355 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 3356 } 3357 3358 /* 3359 * Unbusy this target/channel/lun. 3360 * XXX if we are holding two commands per lun, 3361 * send the next command. 3362 */ 3363 if (!(scb->hscb->control & TAG_ENB)) 3364 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 3365 3366 /* 3367 * If the recovery SCB completes, we have to be 3368 * out of our timeout. 3369 */ 3370 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 3371 3372 struct scb *scbp; 3373 3374 /* 3375 * We were able to complete the command successfully, 3376 * so reinstate the timeouts for all other pending 3377 * commands. 3378 */ 3379 scbp = ahc->pending_ccbs.lh_first; 3380 while (scbp != NULL) { 3381 struct scsipi_xfer *txs = scbp->xs; 3382 3383 if (!(txs->xs_control & XS_CTL_POLL)) { 3384 callout_reset(&scbp->xs->xs_callout, 3385 (scbp->xs->timeout > 1000000) ? 3386 (scbp->xs->timeout / 1000) * hz : 3387 (scbp->xs->timeout * hz) / 1000, 3388 ahc_timeout, scbp); 3389 } 3390 scbp = LIST_NEXT(scbp, plinks); 3391 } 3392 3393 /* 3394 * Ensure that we didn't put a second instance of this 3395 * SCB into the QINFIFO. 3396 */ 3397 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 3398 SCB_LUN(scb), scb->hscb->tag, 3399 ROLE_INITIATOR, /*status*/0, 3400 SEARCH_REMOVE); 3401 if (xs->error != XS_NOERROR) 3402 ahcsetccbstatus(xs, XS_TIMEOUT); 3403 scsipi_printaddr(xs->xs_periph); 3404 printf("no longer in timeout, status = %x\n", xs->status); 3405 } 3406 3407 if (xs->error != XS_NOERROR) { 3408 /* Don't clobber any existing error state */ 3409 } else if ((scb->flags & SCB_SENSE) != 0) { 3410 /* 3411 * We performed autosense retrieval. 3412 * 3413 * zero the sense data before having 3414 * the drive fill it. The SCSI spec mandates 3415 * that any untransferred data should be 3416 * assumed to be zero. Complete the 'bounce' 3417 * of sense information through buffers accessible 3418 * via bus-space by copying it into the clients 3419 * csio. 3420 */ 3421 memset(&xs->sense.scsi_sense, 0, sizeof(xs->sense.scsi_sense)); 3422 memcpy(&xs->sense.scsi_sense, 3423 &ahc->scb_data->sense[scb->hscb->tag], 3424 le32toh(scb->sg_list->len)); 3425 xs->error = XS_SENSE; 3426 } 3427 if (scb->flags & SCB_FREEZE_QUEUE) { 3428 scsipi_periph_thaw(periph, 1); 3429 scb->flags &= ~SCB_FREEZE_QUEUE; 3430 } 3431 3432 requeue = scb->flags & SCB_REQUEUE; 3433 ahcfreescb(ahc, scb); 3434 3435 if (requeue) { 3436 xs->error = XS_REQUEUE; 3437 } 3438 scsipi_done(xs); 3439 } 3440 3441 /* 3442 * Determine the number of SCBs available on the controller 3443 */ 3444 int 3445 ahc_probe_scbs(struct ahc_softc *ahc) { 3446 int i; 3447 3448 for (i = 0; i < AHC_SCB_MAX; i++) { 3449 ahc_outb(ahc, SCBPTR, i); 3450 ahc_outb(ahc, SCB_CONTROL, i); 3451 if (ahc_inb(ahc, SCB_CONTROL) != i) 3452 break; 3453 ahc_outb(ahc, SCBPTR, 0); 3454 if (ahc_inb(ahc, SCB_CONTROL) != 0) 3455 break; 3456 } 3457 return (i); 3458 } 3459 3460 /* 3461 * Start the board, ready for normal operation 3462 */ 3463 int 3464 ahc_init(struct ahc_softc *ahc) 3465 { 3466 int max_targ = 15; 3467 int i; 3468 int term; 3469 u_int scsi_conf; 3470 u_int scsiseq_template; 3471 u_int ultraenb; 3472 u_int discenable; 3473 u_int tagenable; 3474 size_t driver_data_size; 3475 u_int32_t physaddr; 3476 3477 #ifdef AHC_PRINT_SRAM 3478 printf("Scratch Ram:"); 3479 for (i = 0x20; i < 0x5f; i++) { 3480 if (((i % 8) == 0) && (i != 0)) { 3481 printf ("\n "); 3482 } 3483 printf (" 0x%x", ahc_inb(ahc, i)); 3484 } 3485 if ((ahc->features & AHC_MORE_SRAM) != 0) { 3486 for (i = 0x70; i < 0x7f; i++) { 3487 if (((i % 8) == 0) && (i != 0)) { 3488 printf ("\n "); 3489 } 3490 printf (" 0x%x", ahc_inb(ahc, i)); 3491 } 3492 } 3493 printf ("\n"); 3494 #endif 3495 3496 /* 3497 * Assume we have a board at this stage and it has been reset. 3498 */ 3499 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 3500 ahc->our_id = ahc->our_id_b = 7; 3501 3502 /* 3503 * Default to allowing initiator operations. 3504 */ 3505 ahc->flags |= AHC_INITIATORMODE; 3506 3507 /* 3508 * DMA tag for our command fifos and other data in system memory 3509 * the card's sequencer must be able to access. For initiator 3510 * roles, we need to allocate space for the qinfifo, qoutfifo, 3511 * and untagged_scb arrays each of which are composed of 256 3512 * 1 byte elements. When providing for the target mode role, 3513 * we additionally must provide space for the incoming target 3514 * command fifo. 3515 */ 3516 driver_data_size = 3 * 256 * sizeof(u_int8_t); 3517 3518 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 3519 ahc->sc_dmaflags, 3520 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 3521 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 3522 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 3523 return (ENOMEM); 3524 3525 ahc->init_level++; 3526 3527 /* Allocate SCB data now that parent_dmat is initialized */ 3528 if (ahc->scb_data->maxhscbs == 0) 3529 if (ahcinitscbdata(ahc) != 0) 3530 return (ENOMEM); 3531 3532 ahc->qinfifo = &ahc->qoutfifo[256]; 3533 ahc->untagged_scbs = &ahc->qinfifo[256]; 3534 /* There are no untagged SCBs active yet. */ 3535 for (i = 0; i < 256; i++) 3536 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3537 3538 /* All of our queues are empty */ 3539 for (i = 0; i < 256; i++) 3540 ahc->qoutfifo[i] = SCB_LIST_NULL; 3541 3542 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 0, 3543 driver_data_size, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3544 3545 /* 3546 * Allocate a tstate to house information for our 3547 * initiator presence on the bus as well as the user 3548 * data for any target mode initiator. 3549 */ 3550 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 3551 printf("%s: unable to allocate tmode_tstate. " 3552 "Failing attach\n", ahc_name(ahc)); 3553 return (-1); 3554 } 3555 3556 if ((ahc->features & AHC_TWIN) != 0) { 3557 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 3558 printf("%s: unable to allocate tmode_tstate. " 3559 "Failing attach\n", ahc_name(ahc)); 3560 return (-1); 3561 } 3562 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 3563 ahc->our_id, ahc->our_id_b, 3564 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 3565 } else { 3566 if ((ahc->features & AHC_WIDE) != 0) { 3567 printf("Wide "); 3568 } else { 3569 printf("Single "); 3570 } 3571 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 3572 } 3573 3574 ahc_outb(ahc, SEQ_FLAGS, 0); 3575 3576 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 3577 ahc->flags |= AHC_PAGESCBS; 3578 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); 3579 } else { 3580 ahc->flags &= ~AHC_PAGESCBS; 3581 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 3582 } 3583 3584 #ifdef AHC_DEBUG 3585 if (ahc_debug & AHC_SHOWMISC) { 3586 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; " 3587 "ahc_dma %lu bytes\n", 3588 ahc_name(ahc), 3589 (unsigned long) sizeof(struct hardware_scb), 3590 (unsigned long) sizeof(struct scb), 3591 (unsigned long) sizeof(struct ahc_dma_seg)); 3592 } 3593 #endif /* AHC_DEBUG */ 3594 3595 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 3596 if (ahc->features & AHC_TWIN) { 3597 3598 /* 3599 * The device is gated to channel B after a chip reset, 3600 * so set those values first 3601 */ 3602 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 3603 if ((ahc->features & AHC_ULTRA2) != 0) 3604 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 3605 else 3606 ahc_outb(ahc, SCSIID, ahc->our_id_b); 3607 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 3608 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3609 |term|ENSTIMER|ACTNEGEN); 3610 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3611 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3612 3613 if ((scsi_conf & RESET_SCSI) != 0 3614 && (ahc->flags & AHC_INITIATORMODE) != 0) 3615 ahc->flags |= AHC_RESET_BUS_B; 3616 3617 /* Select Channel A */ 3618 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 3619 } 3620 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 3621 if ((ahc->features & AHC_ULTRA2) != 0) 3622 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 3623 else 3624 ahc_outb(ahc, SCSIID, ahc->our_id); 3625 scsi_conf = ahc_inb(ahc, SCSICONF); 3626 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 3627 |term 3628 |ENSTIMER|ACTNEGEN); 3629 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 3630 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 3631 3632 if ((scsi_conf & RESET_SCSI) != 0 3633 && (ahc->flags & AHC_INITIATORMODE) != 0) 3634 ahc->flags |= AHC_RESET_BUS_A; 3635 3636 /* 3637 * Look at the information that board initialization or 3638 * the board bios has left us. 3639 */ 3640 ultraenb = 0; 3641 tagenable = ALL_TARGETS_MASK; 3642 3643 /* Grab the disconnection disable table and invert it for our needs */ 3644 if (ahc->flags & AHC_USEDEFAULTS) { 3645 printf("%s: Host Adapter Bios disabled. Using default SCSI " 3646 "device parameters\n", ahc_name(ahc)); 3647 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 3648 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 3649 discenable = ALL_TARGETS_MASK; 3650 if ((ahc->features & AHC_ULTRA) != 0) 3651 ultraenb = ALL_TARGETS_MASK; 3652 } else { 3653 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3654 | ahc_inb(ahc, DISC_DSB)); 3655 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3656 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3657 | ahc_inb(ahc, ULTRA_ENB); 3658 } 3659 3660 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3661 max_targ = 7; 3662 3663 for (i = 0; i <= max_targ; i++) { 3664 struct ahc_initiator_tinfo *tinfo; 3665 struct tmode_tstate *tstate; 3666 u_int our_id; 3667 u_int target_id; 3668 char channel; 3669 3670 channel = 'A'; 3671 our_id = ahc->our_id; 3672 target_id = i; 3673 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 3674 channel = 'B'; 3675 our_id = ahc->our_id_b; 3676 target_id = i % 8; 3677 } 3678 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 3679 target_id, &tstate); 3680 /* Default to async narrow across the board */ 3681 memset(tinfo, 0, sizeof(*tinfo)); 3682 if (ahc->flags & AHC_USEDEFAULTS) { 3683 if ((ahc->features & AHC_WIDE) != 0) 3684 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3685 3686 /* 3687 * These will be truncated when we determine the 3688 * connection type we have with the target. 3689 */ 3690 tinfo->user.period = ahc_syncrates->period; 3691 tinfo->user.offset = ~0; 3692 } else { 3693 u_int scsirate; 3694 u_int16_t mask; 3695 3696 /* Take the settings leftover in scratch RAM. */ 3697 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3698 mask = (0x01 << i); 3699 if ((ahc->features & AHC_ULTRA2) != 0) { 3700 u_int offset; 3701 u_int maxsync; 3702 3703 if ((scsirate & SOFS) == 0x0F) { 3704 /* 3705 * Haven't negotiated yet, 3706 * so the format is different. 3707 */ 3708 scsirate = (scsirate & SXFR) >> 4 3709 | (ultraenb & mask) 3710 ? 0x08 : 0x0 3711 | (scsirate & WIDEXFER); 3712 offset = MAX_OFFSET_ULTRA2; 3713 } else 3714 offset = ahc_inb(ahc, TARG_OFFSET + i); 3715 maxsync = AHC_SYNCRATE_ULTRA2; 3716 if ((ahc->features & AHC_DT) != 0) 3717 maxsync = AHC_SYNCRATE_DT; 3718 tinfo->user.period = 3719 ahc_find_period(ahc, scsirate, maxsync); 3720 if (offset == 0) 3721 tinfo->user.period = 0; 3722 else 3723 tinfo->user.offset = ~0; 3724 } else if ((scsirate & SOFS) != 0) { 3725 tinfo->user.period = 3726 ahc_find_period(ahc, scsirate, 3727 (ultraenb & mask) 3728 ? AHC_SYNCRATE_ULTRA 3729 : AHC_SYNCRATE_FAST); 3730 if (tinfo->user.period != 0) 3731 tinfo->user.offset = ~0; 3732 } 3733 if ((scsirate & WIDEXFER) != 0 3734 && (ahc->features & AHC_WIDE) != 0) 3735 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3736 } 3737 tinfo->goal = tinfo->user; /* force negotiation */ 3738 tstate->ultraenb = ultraenb; 3739 tstate->discenable = discenable; 3740 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 3741 tstate->tagdisable = 0; 3742 } 3743 ahc->user_discenable = discenable; 3744 ahc->user_tagenable = tagenable; 3745 3746 /* 3747 * Tell the sequencer where it can find our arrays in memory. 3748 */ 3749 physaddr = ahc->scb_data->hscb_busaddr; 3750 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3751 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3752 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3753 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3754 3755 physaddr = ahc->shared_data_busaddr; 3756 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3757 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3758 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3759 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3760 3761 /* Target mode incomding command fifo */ 3762 physaddr += 3 * 256 * sizeof(u_int8_t); 3763 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3764 ahc_outb(ahc, TMODE_CMDADDR + 1, (physaddr >> 8) & 0xFF); 3765 ahc_outb(ahc, TMODE_CMDADDR + 2, (physaddr >> 16) & 0xFF); 3766 ahc_outb(ahc, TMODE_CMDADDR + 3, (physaddr >> 24) & 0xFF); 3767 3768 /* 3769 * Initialize the group code to command length table. 3770 * This overrides the values in TARG_SCSIRATE, so only 3771 * setup the table after we have processed that information. 3772 */ 3773 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3774 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3775 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3776 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3777 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3778 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3779 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3780 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3781 3782 /* Tell the sequencer of our initial queue positions */ 3783 ahc_outb(ahc, KERNEL_QINPOS, 0); 3784 ahc_outb(ahc, QINPOS, 0); 3785 ahc_outb(ahc, QOUTPOS, 0); 3786 3787 #ifdef AHC_DEBUG 3788 if (ahc_debug & AHC_SHOWMISC) 3789 printf("DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3790 discenable, ultraenb); 3791 #endif 3792 3793 /* Don't have any special messages to send to targets */ 3794 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3795 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3796 3797 /* 3798 * Use the built in queue management registers 3799 * if they are available. 3800 */ 3801 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3802 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3803 ahc_outb(ahc, SDSCB_QOFF, 0); 3804 ahc_outb(ahc, SNSCB_QOFF, 0); 3805 ahc_outb(ahc, HNSCB_QOFF, 0); 3806 } 3807 3808 3809 /* We don't have any waiting selections */ 3810 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3811 3812 /* Our disconnection list is empty too */ 3813 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3814 3815 /* Message out buffer starts empty */ 3816 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3817 3818 /* 3819 * Setup the allowed SCSI Sequences based on operational mode. 3820 * If we are a target, we'll enable select in operations once 3821 * we've had a lun enabled. 3822 */ 3823 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3824 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3825 scsiseq_template |= ENRSELI; 3826 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3827 3828 /* 3829 * Load the Sequencer program and Enable the adapter 3830 * in "fast" mode. 3831 */ 3832 #ifdef AHC_DEBUG 3833 printf("%s: Downloading Sequencer Program...", 3834 ahc_name(ahc)); 3835 #endif 3836 3837 ahc_loadseq(ahc); 3838 3839 /* We have to wait until after any system dumps... */ 3840 shutdownhook_establish(ahc_shutdown, ahc); 3841 3842 return (0); 3843 } 3844 3845 static int 3846 ahc_ioctl(struct scsipi_channel *channel, u_long cmd, caddr_t addr, int flag, 3847 struct proc *p) 3848 { 3849 struct ahc_softc *ahc = (void *)channel->chan_adapter->adapt_dev; 3850 int s, ret = ENOTTY; 3851 3852 switch (cmd) { 3853 case SCBUSIORESET: 3854 s = splbio(); 3855 ahc_reset_channel(ahc, channel->chan_channel == 1 ? 'B' : 'A', 3856 TRUE); 3857 splx(s); 3858 ret = 0; 3859 break; 3860 default: 3861 break; 3862 } 3863 3864 return ret; 3865 } 3866 3867 3868 /* 3869 * XXX fvdl the busy_tcl checks and settings should only be done 3870 * for the non-tagged queueing case, but we don't do tagged queueing 3871 * yet, so.. 3872 */ 3873 static void 3874 ahc_action(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 3875 { 3876 struct scsipi_xfer *xs; 3877 struct scsipi_periph *periph; 3878 struct ahc_softc *ahc = (void *)chan->chan_adapter->adapt_dev; 3879 struct scb *scb; 3880 struct hardware_scb *hscb; 3881 struct ahc_initiator_tinfo *tinfo; 3882 struct tmode_tstate *tstate; 3883 u_int target_id; 3884 u_int our_id; 3885 int s, tcl; 3886 u_int16_t mask; 3887 char channel; 3888 3889 switch (req) { 3890 case ADAPTER_REQ_RUN_XFER: 3891 xs = arg; 3892 periph = xs->xs_periph; 3893 3894 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("ahc_action\n")); 3895 3896 /* must protect the queue */ 3897 s = splbio(); 3898 3899 tcl = XS_TCL(ahc, xs); 3900 3901 if (!ahc_istagged_device(ahc, xs, 0) && 3902 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) { 3903 panic("ahc_action: not tagged and device busy"); 3904 } 3905 3906 3907 target_id = periph->periph_target; 3908 our_id = SIM_SCSI_ID(ahc, periph); 3909 3910 /* 3911 * get an scb to use. 3912 */ 3913 if ((scb = ahcgetscb(ahc)) == NULL) { 3914 xs->error = XS_RESOURCE_SHORTAGE; 3915 scsipi_done(xs); 3916 splx(s); 3917 return; 3918 } 3919 3920 tcl = XS_TCL(ahc, xs); 3921 3922 #ifdef DIAGNOSTIC 3923 if (!ahc_istagged_device(ahc, xs, 0) && 3924 ahc_index_busy_tcl(ahc, tcl, FALSE) != SCB_LIST_NULL) 3925 panic("ahc: queuing for busy target"); 3926 #endif 3927 3928 scb->xs = xs; 3929 hscb = scb->hscb; 3930 hscb->tcl = tcl; 3931 3932 if (xs->xs_tag_type) { 3933 #ifdef DIAGNOSTIC 3934 if (ahc_istagged_device(ahc, xs, 0) == 0) 3935 panic("ahc_action: taggged command for untagged device"); 3936 #endif 3937 scb->hscb->control |= TAG_ENB; 3938 } else 3939 ahc_busy_tcl(ahc, scb); 3940 3941 splx(s); 3942 3943 channel = SIM_CHANNEL(ahc, periph); 3944 if (ahc->inited_channels[channel - 'A'] == 0) { 3945 if ((channel == 'A' && 3946 (ahc->flags & AHC_RESET_BUS_A)) || 3947 (channel == 'B' && 3948 (ahc->flags & AHC_RESET_BUS_B))) { 3949 s = splbio(); 3950 ahc_reset_channel(ahc, channel, TRUE); 3951 splx(s); 3952 } 3953 ahc->inited_channels[channel - 'A'] = 1; 3954 } 3955 3956 /* 3957 * Put all the arguments for the xfer in the scb 3958 */ 3959 3960 mask = SCB_TARGET_MASK(scb); 3961 tinfo = ahc_fetch_transinfo(ahc, 3962 SIM_CHANNEL(ahc, periph), 3963 our_id, target_id, &tstate); 3964 if (ahc->inited_targets[target_id] == 0) { 3965 struct ahc_devinfo devinfo; 3966 s = splbio(); 3967 ahc_compile_devinfo(&devinfo, our_id, target_id, 3968 periph->periph_lun, 3969 SIM_CHANNEL(ahc, periph), 3970 ROLE_INITIATOR); 3971 ahc_update_target_msg_request(ahc, &devinfo, tinfo, 3972 TRUE, FALSE); 3973 ahc->inited_targets[target_id] = 1; 3974 splx(s); 3975 } 3976 hscb->scsirate = tinfo->scsirate; 3977 hscb->scsioffset = tinfo->current.offset; 3978 if ((tstate->ultraenb & mask) != 0) 3979 hscb->control |= ULTRAENB; 3980 3981 if ((tstate->discenable & mask) != 0) 3982 hscb->control |= DISCENB; 3983 3984 if (xs->xs_control & XS_CTL_RESET) { 3985 hscb->cmdpointer = 0; 3986 scb->flags |= SCB_DEVICE_RESET; 3987 hscb->control |= MK_MESSAGE; 3988 ahc_execute_scb(scb, NULL, 0); 3989 } 3990 3991 ahc_setup_data(ahc, xs, scb); 3992 return; 3993 case ADAPTER_REQ_GROW_RESOURCES: 3994 /* XXX not supported */ 3995 return; 3996 case ADAPTER_REQ_SET_XFER_MODE: 3997 { 3998 struct scsipi_xfer_mode *xm = arg; 3999 struct ahc_devinfo devinfo; 4000 int target_id, our_id; 4001 char channel; 4002 4003 target_id = xm->xm_target; 4004 our_id = chan->chan_id; 4005 channel = (chan->chan_channel == 1) ? 'B' : 'A'; 4006 s = splbio(); 4007 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, 4008 &tstate); 4009 ahc_compile_devinfo(&devinfo, our_id, target_id, 4010 0, channel, ROLE_INITIATOR); 4011 ahc->inited_targets[target_id] = 2; 4012 if (xm->xm_mode & PERIPH_CAP_TQING && 4013 (tstate->tagdisable & devinfo.target_mask) == 0) { 4014 ahc_set_tags(ahc, &devinfo, TRUE); 4015 } 4016 splx(s); 4017 ahc_update_xfer_mode(ahc, &devinfo); 4018 } 4019 } 4020 } 4021 4022 static void 4023 ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments) 4024 { 4025 struct scb *scb; 4026 struct scsipi_xfer *xs; 4027 struct ahc_softc *ahc; 4028 int s; 4029 4030 scb = (struct scb *)arg; 4031 xs = scb->xs; 4032 ahc = (void *)xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4033 4034 4035 if (nsegments != 0) { 4036 struct ahc_dma_seg *sg; 4037 bus_dma_segment_t *end_seg; 4038 int op; 4039 4040 end_seg = dm_segs + nsegments; 4041 4042 /* Copy the first SG into the data pointer area */ 4043 scb->hscb->data = dm_segs->ds_addr; 4044 scb->hscb->datalen = dm_segs->ds_len; 4045 4046 /* Copy the segments into our SG list */ 4047 sg = scb->sg_list; 4048 while (dm_segs < end_seg) { 4049 sg->addr = dm_segs->ds_addr; 4050 sg->len = dm_segs->ds_len; 4051 ahc_swap_sg(sg); 4052 sg++; 4053 dm_segs++; 4054 } 4055 4056 /* Note where to find the SG entries in bus space */ 4057 scb->hscb->SG_pointer = scb->sg_list_phys; 4058 4059 if (xs->xs_control & XS_CTL_DATA_IN) 4060 op = BUS_DMASYNC_PREREAD; 4061 else 4062 op = BUS_DMASYNC_PREWRITE; 4063 4064 bus_dmamap_sync(ahc->parent_dmat, scb->dmamap, 0, 4065 scb->dmamap->dm_mapsize, op); 4066 4067 } else { 4068 scb->hscb->SG_pointer = 0; 4069 scb->hscb->data = 0; 4070 scb->hscb->datalen = 0; 4071 } 4072 4073 scb->sg_count = scb->hscb->SG_count = nsegments; 4074 4075 s = splbio(); 4076 4077 /* 4078 * Last time we need to check if this SCB needs to 4079 * be aborted. 4080 */ 4081 if (xs->xs_status & XS_STS_DONE) { 4082 if (!ahc_istagged_device(ahc, xs, 0)) 4083 ahc_index_busy_tcl(ahc, scb->hscb->tcl, TRUE); 4084 if (nsegments != 0) 4085 bus_dmamap_unload(ahc->parent_dmat, scb->dmamap); 4086 ahcfreescb(ahc, scb); 4087 splx(s); 4088 return; 4089 } 4090 4091 #ifdef DIAGNOSTIC 4092 if (scb->sg_count > 255) 4093 panic("ahc bad sg_count"); 4094 #endif 4095 4096 ahc_swap_hscb(scb->hscb); 4097 4098 LIST_INSERT_HEAD(&ahc->pending_ccbs, scb, plinks); 4099 4100 scb->flags |= SCB_ACTIVE; 4101 4102 if (!(xs->xs_control & XS_CTL_POLL)) 4103 callout_reset(&scb->xs->xs_callout, xs->timeout > 1000000 ? 4104 (xs->timeout / 1000) * hz : (xs->timeout * hz) / 1000, 4105 ahc_timeout, scb); 4106 4107 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 4108 #if 0 4109 printf("Continueing Immediate Command %d:%d\n", 4110 xs->xs_periph->periph_target, 4111 xs->xs_periph->periph_lun); 4112 #endif 4113 pause_sequencer(ahc); 4114 if ((ahc->flags & AHC_PAGESCBS) == 0) 4115 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 4116 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 4117 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 4118 unpause_sequencer(ahc); 4119 } else { 4120 4121 #if 0 4122 printf("tag %x at qpos %u vaddr %p paddr 0x%lx\n", 4123 scb->hscb->tag, ahc->qinfifonext, 4124 &ahc->qinfifo[ahc->qinfifonext], 4125 ahc->shared_data_busaddr + 1024 + ahc->qinfifonext); 4126 #endif 4127 4128 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4129 4130 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4131 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4132 4133 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4134 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4135 } else { 4136 pause_sequencer(ahc); 4137 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4138 unpause_sequencer(ahc); 4139 } 4140 } 4141 4142 #ifdef AHC_DEBUG 4143 if (ahc_debug & AHC_SHOWCMDS) { 4144 scsi_print_addr(xs->xs_periph); 4145 printf("opcode %d tag %x len %d flags %x control %x fpos %u" 4146 " rate %x\n", 4147 xs->cmdstore.opcode, scb->hscb->tag, scb->hscb->datalen, 4148 scb->flags, scb->hscb->control, ahc->qinfifonext, 4149 scb->hscb->scsirate); 4150 } 4151 #endif 4152 4153 if (!(xs->xs_control & XS_CTL_POLL)) { 4154 splx(s); 4155 return; 4156 } 4157 /* 4158 * If we can't use interrupts, poll for completion 4159 */ 4160 SC_DEBUG(xs->xs_periph, SCSIPI_DB3, ("cmd_poll\n")); 4161 do { 4162 if (ahc_poll(ahc, xs->timeout)) { 4163 if (!(xs->xs_control & XS_CTL_SILENT)) 4164 printf("cmd fail\n"); 4165 ahc_timeout(scb); 4166 break; 4167 } 4168 } while (!(xs->xs_status & XS_STS_DONE)); 4169 splx(s); 4170 return; 4171 } 4172 4173 static int 4174 ahc_poll(struct ahc_softc *ahc, int wait) 4175 { 4176 while (--wait) { 4177 DELAY(1000); 4178 if (ahc_inb(ahc, INTSTAT) & INT_PEND) 4179 break; 4180 } 4181 4182 if (wait == 0) { 4183 printf("%s: board is not responding\n", ahc_name(ahc)); 4184 return (EIO); 4185 } 4186 4187 ahc_intr((void *)ahc); 4188 return (0); 4189 } 4190 4191 static void 4192 ahc_setup_data(struct ahc_softc *ahc, struct scsipi_xfer *xs, 4193 struct scb *scb) 4194 { 4195 struct hardware_scb *hscb; 4196 4197 hscb = scb->hscb; 4198 xs->resid = xs->status = 0; 4199 4200 hscb->cmdlen = xs->cmdlen; 4201 memcpy(hscb->cmdstore, xs->cmd, xs->cmdlen); 4202 hscb->cmdpointer = hscb->cmdstore_busaddr; 4203 4204 /* Only use S/G if there is a transfer */ 4205 if (xs->datalen) { 4206 int error; 4207 4208 error = bus_dmamap_load(ahc->parent_dmat, 4209 scb->dmamap, xs->data, 4210 xs->datalen, NULL, 4211 ((xs->xs_control & XS_CTL_NOSLEEP) ? 4212 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 4213 BUS_DMA_STREAMING | 4214 ((xs->xs_control & XS_CTL_DATA_IN) ? 4215 BUS_DMA_READ : BUS_DMA_WRITE)); 4216 if (error) { 4217 #ifdef AHC_DEBUG 4218 printf("%s: in ahc_setup_data(): bus_dmamap_load() " 4219 "= %d\n", 4220 ahc_name(ahc), 4221 error); 4222 #endif 4223 if (!ahc_istagged_device(ahc, xs, 0)) 4224 ahc_index_busy_tcl(ahc, hscb->tcl, TRUE); 4225 xs->error = XS_RESOURCE_SHORTAGE; /* XXX fvdl */ 4226 scsipi_done(xs); 4227 return; 4228 } 4229 ahc_execute_scb(scb, 4230 scb->dmamap->dm_segs, 4231 scb->dmamap->dm_nsegs); 4232 } else { 4233 ahc_execute_scb(scb, NULL, 0); 4234 } 4235 } 4236 4237 static void 4238 ahc_freeze_devq(struct ahc_softc *ahc, struct scsipi_periph *periph) 4239 { 4240 int target; 4241 char channel; 4242 int lun; 4243 4244 target = periph->periph_target; 4245 lun = periph->periph_lun; 4246 channel = periph->periph_channel->chan_channel; 4247 4248 ahc_search_qinfifo(ahc, target, channel, lun, 4249 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4250 SCB_REQUEUE, SEARCH_COMPLETE); 4251 } 4252 4253 static void 4254 ahcallocscbs(struct ahc_softc *ahc) 4255 { 4256 struct scb_data *scb_data; 4257 struct scb *next_scb; 4258 struct sg_map_node *sg_map; 4259 bus_addr_t physaddr; 4260 struct ahc_dma_seg *segs; 4261 int newcount; 4262 int i; 4263 4264 scb_data = ahc->scb_data; 4265 if (scb_data->numscbs >= AHC_SCB_MAX) 4266 /* Can't allocate any more */ 4267 return; 4268 4269 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4270 4271 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4272 4273 if (sg_map == NULL) 4274 return; 4275 4276 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4277 &sg_map->sg_dmamap, 4278 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4279 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4280 "SG space") < 0) { 4281 free(sg_map, M_DEVBUF); 4282 return; 4283 } 4284 4285 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4286 4287 segs = sg_map->sg_vaddr; 4288 physaddr = sg_map->sg_physaddr; 4289 4290 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4291 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 4292 int error; 4293 4294 next_scb->sg_list = segs; 4295 /* 4296 * The sequencer always starts with the second entry. 4297 * The first entry is embedded in the scb. 4298 */ 4299 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4300 next_scb->flags = SCB_FREE; 4301 error = bus_dmamap_create(ahc->parent_dmat, 4302 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4303 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4304 &next_scb->dmamap); 4305 if (error != 0) 4306 break; 4307 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4308 next_scb->hscb->tag = ahc->scb_data->numscbs; 4309 next_scb->hscb->cmdstore_busaddr = 4310 ahc_hscb_busaddr(ahc, next_scb->hscb->tag) 4311 + offsetof(struct hardware_scb, cmdstore); 4312 next_scb->hscb->cmdstore_busaddr = 4313 htole32(next_scb->hscb->cmdstore_busaddr); 4314 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, next_scb, links); 4315 segs += AHC_NSEG; 4316 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4317 next_scb++; 4318 ahc->scb_data->numscbs++; 4319 } 4320 #ifdef AHC_DEBUG 4321 if (ahc_debug & AHC_SHOWSCBALLOC) 4322 printf("%s: allocated %d new SCBs count now %d\n", 4323 ahc_name(ahc), i - 1, ahc->scb_data->numscbs); 4324 #endif 4325 } 4326 4327 #ifdef AHC_DUMP_SEQ 4328 static void 4329 ahc_dumpseq(struct ahc_softc* ahc) 4330 { 4331 int i; 4332 int max_prog; 4333 4334 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 4335 max_prog = 448; 4336 else if ((ahc->features & AHC_ULTRA2) != 0) 4337 max_prog = 768; 4338 else 4339 max_prog = 512; 4340 4341 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4342 ahc_outb(ahc, SEQADDR0, 0); 4343 ahc_outb(ahc, SEQADDR1, 0); 4344 for (i = 0; i < max_prog; i++) { 4345 u_int8_t ins_bytes[4]; 4346 4347 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 4348 printf("0x%08x\n", ins_bytes[0] << 24 4349 | ins_bytes[1] << 16 4350 | ins_bytes[2] << 8 4351 | ins_bytes[3]); 4352 } 4353 } 4354 #endif 4355 4356 static void 4357 ahc_loadseq(struct ahc_softc *ahc) 4358 { 4359 const struct patch *cur_patch; 4360 int i; 4361 int downloaded; 4362 int skip_addr; 4363 u_int8_t download_consts[4]; 4364 4365 /* Setup downloadable constant table */ 4366 #if 0 4367 /* No downloaded constants are currently defined. */ 4368 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4369 #endif 4370 4371 cur_patch = patches; 4372 downloaded = 0; 4373 skip_addr = 0; 4374 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4375 ahc_outb(ahc, SEQADDR0, 0); 4376 ahc_outb(ahc, SEQADDR1, 0); 4377 4378 for (i = 0; i < sizeof(seqprog)/4; i++) { 4379 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4380 /* 4381 * Don't download this instruction as it 4382 * is in a patch that was removed. 4383 */ 4384 continue; 4385 } 4386 ahc_download_instr(ahc, i, download_consts); 4387 downloaded++; 4388 } 4389 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4390 restart_sequencer(ahc); 4391 4392 #ifdef AHC_DEBUG 4393 printf(" %d instructions downloaded\n", downloaded); 4394 #endif 4395 } 4396 4397 static int 4398 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 4399 int start_instr, int *skip_addr) 4400 { 4401 const struct patch *cur_patch; 4402 const struct patch *last_patch; 4403 int num_patches; 4404 4405 num_patches = sizeof(patches)/sizeof(struct patch); 4406 last_patch = &patches[num_patches]; 4407 cur_patch = *start_patch; 4408 4409 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4410 4411 if (cur_patch->patch_func(ahc) == 0) { 4412 4413 /* Start rejecting code */ 4414 *skip_addr = start_instr + cur_patch->skip_instr; 4415 cur_patch += cur_patch->skip_patch; 4416 } else { 4417 /* Accepted this patch. Advance to the next 4418 * one and wait for our intruction pointer to 4419 * hit this point. 4420 */ 4421 cur_patch++; 4422 } 4423 } 4424 4425 *start_patch = cur_patch; 4426 if (start_instr < *skip_addr) 4427 /* Still skipping */ 4428 return (0); 4429 4430 return (1); 4431 } 4432 4433 static void 4434 ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4435 { 4436 union ins_formats instr; 4437 struct ins_format1 *fmt1_ins; 4438 struct ins_format3 *fmt3_ins; 4439 u_int opcode; 4440 4441 /* Structure copy */ 4442 memcpy(&instr, &seqprog[instrptr * 4], sizeof instr); 4443 4444 instr.integer = le32toh(instr.integer); 4445 4446 fmt1_ins = &instr.format1; 4447 fmt3_ins = NULL; 4448 4449 /* Pull the opcode */ 4450 opcode = instr.format1.opcode; 4451 switch (opcode) { 4452 case AIC_OP_JMP: 4453 case AIC_OP_JC: 4454 case AIC_OP_JNC: 4455 case AIC_OP_CALL: 4456 case AIC_OP_JNE: 4457 case AIC_OP_JNZ: 4458 case AIC_OP_JE: 4459 case AIC_OP_JZ: 4460 { 4461 const struct patch *cur_patch; 4462 int address_offset; 4463 u_int address; 4464 int skip_addr; 4465 int i; 4466 4467 fmt3_ins = &instr.format3; 4468 address_offset = 0; 4469 address = fmt3_ins->address; 4470 cur_patch = patches; 4471 skip_addr = 0; 4472 4473 for (i = 0; i < address;) { 4474 4475 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4476 4477 if (skip_addr > i) { 4478 int end_addr; 4479 4480 end_addr = MIN(address, skip_addr); 4481 address_offset += end_addr - i; 4482 i = skip_addr; 4483 } else { 4484 i++; 4485 } 4486 } 4487 address -= address_offset; 4488 fmt3_ins->address = address; 4489 /* FALLTHROUGH */ 4490 } 4491 case AIC_OP_OR: 4492 case AIC_OP_AND: 4493 case AIC_OP_XOR: 4494 case AIC_OP_ADD: 4495 case AIC_OP_ADC: 4496 case AIC_OP_BMOV: 4497 if (fmt1_ins->parity != 0) { 4498 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4499 } 4500 fmt1_ins->parity = 0; 4501 /* FALLTHROUGH */ 4502 case AIC_OP_ROL: 4503 if ((ahc->features & AHC_ULTRA2) != 0) { 4504 int i, count; 4505 4506 /* Calculate odd parity for the instruction */ 4507 for (i = 0, count = 0; i < 31; i++) { 4508 u_int32_t mask; 4509 4510 mask = 0x01 << i; 4511 if ((instr.integer & mask) != 0) 4512 count++; 4513 } 4514 if ((count & 0x01) == 0) 4515 instr.format1.parity = 1; 4516 } else { 4517 /* Compress the instruction for older sequencers */ 4518 if (fmt3_ins != NULL) { 4519 instr.integer = 4520 fmt3_ins->immediate 4521 | (fmt3_ins->source << 8) 4522 | (fmt3_ins->address << 16) 4523 | (fmt3_ins->opcode << 25); 4524 } else { 4525 instr.integer = 4526 fmt1_ins->immediate 4527 | (fmt1_ins->source << 8) 4528 | (fmt1_ins->destination << 16) 4529 | (fmt1_ins->ret << 24) 4530 | (fmt1_ins->opcode << 25); 4531 } 4532 } 4533 instr.integer = htole32(instr.integer); 4534 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4535 break; 4536 default: 4537 panic("Unknown opcode encountered in seq program"); 4538 break; 4539 } 4540 } 4541 4542 static void 4543 ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) 4544 { 4545 4546 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4547 struct scb *scbp; 4548 4549 scb->flags |= SCB_RECOVERY_SCB; 4550 4551 /* 4552 * Take all queued, but not sent SCBs out of the equation. 4553 * Also ensure that no new CCBs are queued to us while we 4554 * try to fix this problem. 4555 */ 4556 scsipi_channel_freeze(&ahc->sc_channel, 1); 4557 if (ahc->features & AHC_TWIN) 4558 scsipi_channel_freeze(&ahc->sc_channel_b, 1); 4559 4560 /* 4561 * Go through all of our pending SCBs and remove 4562 * any scheduled timeouts for them. We will reschedule 4563 * them after we've successfully fixed this problem. 4564 */ 4565 scbp = ahc->pending_ccbs.lh_first; 4566 while (scbp != NULL) { 4567 callout_stop(&scbp->xs->xs_callout); 4568 scbp = scbp->plinks.le_next; 4569 } 4570 } 4571 } 4572 4573 static void 4574 ahc_timeout(void *arg) 4575 { 4576 struct scb *scb; 4577 struct ahc_softc *ahc; 4578 int s, found; 4579 u_int last_phase; 4580 int target; 4581 int lun; 4582 int i; 4583 char channel; 4584 4585 scb = (struct scb *)arg; 4586 ahc = 4587 (void *)scb->xs->xs_periph->periph_channel->chan_adapter->adapt_dev; 4588 4589 s = splbio(); 4590 4591 /* 4592 * Ensure that the card doesn't do anything 4593 * behind our back. Also make sure that we 4594 * didn't "just" miss an interrupt that would 4595 * affect this timeout. 4596 */ 4597 do { 4598 ahc_intr(ahc); 4599 pause_sequencer(ahc); 4600 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4601 4602 if ((scb->flags & SCB_ACTIVE) == 0) { 4603 /* Previous timeout took care of me already */ 4604 printf("Timedout SCB handled by another timeout\n"); 4605 unpause_sequencer(ahc); 4606 splx(s); 4607 return; 4608 } 4609 4610 target = SCB_TARGET(scb); 4611 channel = SCB_CHANNEL(scb); 4612 lun = SCB_LUN(scb); 4613 4614 scsipi_printaddr(scb->xs->xs_periph); 4615 printf("SCB %x - timed out ", scb->hscb->tag); 4616 /* 4617 * Take a snapshot of the bus state and print out 4618 * some information so we can track down driver bugs. 4619 */ 4620 last_phase = ahc_inb(ahc, LASTPHASE); 4621 4622 for (i = 0; i < num_phases; i++) { 4623 if (last_phase == phase_table[i].phase) 4624 break; 4625 } 4626 printf("%s", phase_table[i].phasemsg); 4627 4628 printf(", SEQADDR == 0x%x\n", 4629 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4630 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4631 4632 #ifdef AHC_DEBUG 4633 ahc_print_scb(scb); 4634 #endif 4635 4636 #if 0 4637 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4638 printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); 4639 printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 4640 printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); 4641 printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); 4642 printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) 4643 | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 4644 | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 4645 | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); 4646 printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) 4647 | ahc_inb(ahc, SCB_DATACNT + 1) << 8 4648 | ahc_inb(ahc, SCB_DATACNT + 2) << 16); 4649 printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); 4650 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4651 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4652 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4653 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4654 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4655 if (scb->sg_count > 0) { 4656 for (i = 0; i < scb->sg_count; i++) { 4657 printf("sg[%d] - Addr 0x%x : Length %d\n", 4658 i, 4659 le32toh(scb->sg_list[i].addr), 4660 le32toh(scb->sg_list[i].len)); 4661 } 4662 } 4663 #endif 4664 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 4665 /* 4666 * Been down this road before. 4667 * Do a full bus reset. 4668 */ 4669 bus_reset: 4670 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4671 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4672 printf("%s: Issued Channel %c Bus Reset. " 4673 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4674 } else { 4675 /* 4676 * If we are a target, transition to bus free and report 4677 * the timeout. 4678 * 4679 * The target/initiator that is holding up the bus may not 4680 * be the same as the one that triggered this timeout 4681 * (different commands have different timeout lengths). 4682 * If the bus is idle and we are actiing as the initiator 4683 * for this request, queue a BDR message to the timed out 4684 * target. Otherwise, if the timed out transaction is 4685 * active: 4686 * Initiator transaction: 4687 * Stuff the message buffer with a BDR message and assert 4688 * ATN in the hopes that the target will let go of the bus 4689 * and go to the mesgout phase. If this fails, we'll 4690 * get another timeout 2 seconds later which will attempt 4691 * a bus reset. 4692 * 4693 * Target transaction: 4694 * Transition to BUS FREE and report the error. 4695 * It's good to be the target! 4696 */ 4697 u_int active_scb_index; 4698 4699 active_scb_index = ahc_inb(ahc, SCB_TAG); 4700 4701 if (last_phase != P_BUSFREE 4702 && (active_scb_index < ahc->scb_data->numscbs)) { 4703 struct scb *active_scb; 4704 4705 /* 4706 * If the active SCB is not from our device, 4707 * assume that another device is hogging the bus 4708 * and wait for it's timeout to expire before 4709 * taking additional action. 4710 */ 4711 active_scb = &ahc->scb_data->scbarray[active_scb_index]; 4712 if (active_scb->hscb->tcl != scb->hscb->tcl) { 4713 u_int newtimeout; 4714 4715 scsipi_printaddr(scb->xs->xs_periph); 4716 printf("Other SCB Timeout%s", 4717 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 4718 ? " again\n" : "\n"); 4719 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4720 newtimeout = MAX(active_scb->xs->timeout, 4721 scb->xs->timeout); 4722 callout_reset(&scb->xs->xs_callout, 4723 newtimeout > 1000000 ? 4724 (newtimeout / 1000) * hz : 4725 (newtimeout * hz) / 1000, 4726 ahc_timeout, scb); 4727 splx(s); 4728 return; 4729 } 4730 4731 /* It's us */ 4732 if ((scb->hscb->control & TARGET_SCB) != 0) { 4733 4734 /* 4735 * Send back any queued up transactions 4736 * and properly record the error condition. 4737 */ 4738 ahc_freeze_devq(ahc, scb->xs->xs_periph); 4739 ahcsetccbstatus(scb->xs, XS_TIMEOUT); 4740 ahc_freeze_ccb(scb); 4741 ahc_done(ahc, scb); 4742 4743 /* Will clear us from the bus */ 4744 restart_sequencer(ahc); 4745 splx(s); 4746 return; 4747 } 4748 4749 ahc_set_recoveryscb(ahc, active_scb); 4750 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4751 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 4752 scsipi_printaddr(active_scb->xs->xs_periph); 4753 printf("BDR message in message buffer\n"); 4754 active_scb->flags |= SCB_DEVICE_RESET; 4755 callout_reset(&active_scb->xs->xs_callout, 4756 2 * hz, ahc_timeout, active_scb); 4757 unpause_sequencer(ahc); 4758 } else { 4759 int disconnected; 4760 4761 /* XXX Shouldn't panic. Just punt instead */ 4762 if ((scb->hscb->control & TARGET_SCB) != 0) 4763 panic("Timed-out target SCB but bus idle"); 4764 4765 if (last_phase != P_BUSFREE 4766 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4767 /* XXX What happened to the SCB? */ 4768 /* Hung target selection. Goto busfree */ 4769 printf("%s: Hung target selection\n", 4770 ahc_name(ahc)); 4771 restart_sequencer(ahc); 4772 splx(s); 4773 return; 4774 } 4775 4776 if (ahc_search_qinfifo(ahc, target, channel, lun, 4777 scb->hscb->tag, ROLE_INITIATOR, 4778 /*status*/0, SEARCH_COUNT) > 0) { 4779 disconnected = FALSE; 4780 } else { 4781 disconnected = TRUE; 4782 } 4783 4784 if (disconnected) { 4785 u_int active_scb; 4786 4787 ahc_set_recoveryscb(ahc, scb); 4788 /* 4789 * Simply set the MK_MESSAGE control bit. 4790 */ 4791 scb->hscb->control |= MK_MESSAGE; 4792 scb->flags |= SCB_QUEUED_MSG 4793 | SCB_DEVICE_RESET; 4794 4795 /* 4796 * Mark the cached copy of this SCB in the 4797 * disconnected list too, so that a reconnect 4798 * at this point causes a BDR or abort. 4799 */ 4800 active_scb = ahc_inb(ahc, SCBPTR); 4801 if (ahc_search_disc_list(ahc, target, 4802 channel, lun, 4803 scb->hscb->tag, 4804 /*stop_on_first*/TRUE, 4805 /*remove*/FALSE, 4806 /*save_state*/FALSE)) { 4807 u_int scb_control; 4808 4809 scb_control = ahc_inb(ahc, SCB_CONTROL); 4810 scb_control |= MK_MESSAGE; 4811 ahc_outb(ahc, SCB_CONTROL, scb_control); 4812 } 4813 ahc_outb(ahc, SCBPTR, active_scb); 4814 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4815 /*unbusy*/TRUE); 4816 4817 /* 4818 * Actually re-queue this SCB in case we can 4819 * select the device before it reconnects. 4820 * Clear out any entries in the QINFIFO first 4821 * so we are the next SCB for this target 4822 * to run. 4823 */ 4824 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4825 channel, SCB_LUN(scb), 4826 SCB_LIST_NULL, 4827 ROLE_INITIATOR, 4828 SCB_REQUEUE, 4829 SEARCH_COMPLETE); 4830 scsipi_printaddr(scb->xs->xs_periph); 4831 printf("Queuing a BDR SCB\n"); 4832 ahc->qinfifo[ahc->qinfifonext++] = 4833 scb->hscb->tag; 4834 4835 bus_dmamap_sync(ahc->parent_dmat, 4836 ahc->shared_data_dmamap, 4837 QINFIFO_OFFSET * 256, 256, 4838 BUS_DMASYNC_PREWRITE); 4839 4840 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4841 ahc_outb(ahc, HNSCB_QOFF, 4842 ahc->qinfifonext); 4843 } else { 4844 ahc_outb(ahc, KERNEL_QINPOS, 4845 ahc->qinfifonext); 4846 } 4847 callout_reset(&scb->xs->xs_callout, 2 * hz, 4848 ahc_timeout, scb); 4849 unpause_sequencer(ahc); 4850 } else { 4851 /* Go "immediatly" to the bus reset */ 4852 /* This shouldn't happen */ 4853 ahc_set_recoveryscb(ahc, scb); 4854 scsipi_printaddr(scb->xs->xs_periph); 4855 printf("SCB %x: Immediate reset. " 4856 "Flags = 0x%x\n", scb->hscb->tag, 4857 scb->flags); 4858 goto bus_reset; 4859 } 4860 } 4861 } 4862 splx(s); 4863 } 4864 4865 static int 4866 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4867 int lun, u_int tag, role_t role, scb_flag status, 4868 ahc_search_action action) 4869 { 4870 struct scb *scbp; 4871 u_int8_t qinpos; 4872 u_int8_t qintail; 4873 int found; 4874 4875 qinpos = ahc_inb(ahc, QINPOS); 4876 qintail = ahc->qinfifonext; 4877 found = 0; 4878 4879 /* 4880 * Start with an empty queue. Entries that are not chosen 4881 * for removal will be re-added to the queue as we go. 4882 */ 4883 ahc->qinfifonext = qinpos; 4884 4885 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4886 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_POSTREAD); 4887 4888 while (qinpos != qintail) { 4889 scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4890 if (ahc_match_scb(scbp, target, channel, lun, tag, role)) { 4891 /* 4892 * We found an scb that needs to be removed. 4893 */ 4894 switch (action) { 4895 case SEARCH_COMPLETE: 4896 if (!(scbp->xs->xs_status & XS_STS_DONE)) { 4897 scbp->flags |= status; 4898 scbp->xs->error = XS_NOERROR; 4899 } 4900 ahc_freeze_ccb(scbp); 4901 ahc_done(ahc, scbp); 4902 break; 4903 case SEARCH_COUNT: 4904 ahc->qinfifo[ahc->qinfifonext++] = 4905 scbp->hscb->tag; 4906 break; 4907 case SEARCH_REMOVE: 4908 break; 4909 } 4910 found++; 4911 } else { 4912 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4913 } 4914 qinpos++; 4915 } 4916 4917 bus_dmamap_sync(ahc->parent_dmat, ahc->shared_data_dmamap, 4918 QINFIFO_OFFSET * 256, 256, BUS_DMASYNC_PREWRITE); 4919 4920 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4921 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4922 } else { 4923 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4924 } 4925 4926 return (found); 4927 } 4928 4929 /* 4930 * Abort all SCBs that match the given description (target/channel/lun/tag), 4931 * setting their status to the passed in status if the status has not already 4932 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4933 * is paused before it is called. 4934 */ 4935 static int 4936 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4937 int lun, u_int tag, role_t role, int status) 4938 { 4939 struct scb *scbp; 4940 u_int active_scb; 4941 int i; 4942 int found; 4943 4944 /* restore this when we're done */ 4945 active_scb = ahc_inb(ahc, SCBPTR); 4946 4947 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 4948 role, SCB_REQUEUE, SEARCH_COMPLETE); 4949 4950 /* 4951 * Search waiting for selection list. 4952 */ 4953 { 4954 u_int8_t next, prev; 4955 4956 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4957 prev = SCB_LIST_NULL; 4958 4959 while (next != SCB_LIST_NULL) { 4960 u_int8_t scb_index; 4961 4962 ahc_outb(ahc, SCBPTR, next); 4963 scb_index = ahc_inb(ahc, SCB_TAG); 4964 if (scb_index >= ahc->scb_data->numscbs) { 4965 panic("Waiting List inconsistency. " 4966 "SCB index == %d, yet numscbs == %d.", 4967 scb_index, ahc->scb_data->numscbs); 4968 } 4969 scbp = &ahc->scb_data->scbarray[scb_index]; 4970 if (ahc_match_scb(scbp, target, channel, 4971 lun, SCB_LIST_NULL, role)) { 4972 4973 next = ahc_abort_wscb(ahc, next, prev); 4974 } else { 4975 4976 prev = next; 4977 next = ahc_inb(ahc, SCB_NEXT); 4978 } 4979 } 4980 } 4981 /* 4982 * Go through the disconnected list and remove any entries we 4983 * have queued for completion, 0'ing their control byte too. 4984 * We save the active SCB and restore it ourselves, so there 4985 * is no reason for this search to restore it too. 4986 */ 4987 ahc_search_disc_list(ahc, target, channel, lun, tag, 4988 /*stop_on_first*/FALSE, /*remove*/TRUE, 4989 /*save_state*/FALSE); 4990 4991 /* 4992 * Go through the hardware SCB array looking for commands that 4993 * were active but not on any list. 4994 */ 4995 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4996 u_int scbid; 4997 4998 ahc_outb(ahc, SCBPTR, i); 4999 scbid = ahc_inb(ahc, SCB_TAG); 5000 scbp = &ahc->scb_data->scbarray[scbid]; 5001 if (scbid < ahc->scb_data->numscbs 5002 && ahc_match_scb(scbp, target, channel, lun, tag, role)) 5003 ahc_add_curscb_to_free_list(ahc); 5004 } 5005 5006 /* 5007 * Go through the pending CCB list and look for 5008 * commands for this target that are still active. 5009 * These are other tagged commands that were 5010 * disconnected when the reset occurred. 5011 */ 5012 { 5013 struct scb *scb; 5014 5015 scb = ahc->pending_ccbs.lh_first; 5016 while (scb != NULL) { 5017 scbp = scb; 5018 scb = scb->plinks.le_next; 5019 if (ahc_match_scb(scbp, target, channel, 5020 lun, tag, role)) { 5021 if (!(scbp->xs->xs_status & XS_STS_DONE)) 5022 ahcsetccbstatus(scbp->xs, status); 5023 ahc_freeze_ccb(scbp); 5024 ahc_done(ahc, scbp); 5025 found++; 5026 } 5027 } 5028 } 5029 ahc_outb(ahc, SCBPTR, active_scb); 5030 return found; 5031 } 5032 5033 static int 5034 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5035 int lun, u_int tag, int stop_on_first, int remove, 5036 int save_state) 5037 { 5038 struct scb *scbp; 5039 u_int next; 5040 u_int prev; 5041 u_int count; 5042 u_int active_scb; 5043 5044 count = 0; 5045 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5046 prev = SCB_LIST_NULL; 5047 5048 if (save_state) { 5049 /* restore this when we're done */ 5050 active_scb = ahc_inb(ahc, SCBPTR); 5051 } else 5052 /* Silence compiler */ 5053 active_scb = SCB_LIST_NULL; 5054 5055 while (next != SCB_LIST_NULL) { 5056 u_int scb_index; 5057 5058 ahc_outb(ahc, SCBPTR, next); 5059 scb_index = ahc_inb(ahc, SCB_TAG); 5060 if (scb_index >= ahc->scb_data->numscbs) { 5061 panic("Disconnected List inconsistency. " 5062 "SCB index == %d, yet numscbs == %d.", 5063 scb_index, ahc->scb_data->numscbs); 5064 } 5065 scbp = &ahc->scb_data->scbarray[scb_index]; 5066 if (ahc_match_scb(scbp, target, channel, lun, 5067 tag, ROLE_INITIATOR)) { 5068 count++; 5069 if (remove) { 5070 next = 5071 ahc_rem_scb_from_disc_list(ahc, prev, next); 5072 } else { 5073 prev = next; 5074 next = ahc_inb(ahc, SCB_NEXT); 5075 } 5076 if (stop_on_first) 5077 break; 5078 } else { 5079 prev = next; 5080 next = ahc_inb(ahc, SCB_NEXT); 5081 } 5082 } 5083 if (save_state) 5084 ahc_outb(ahc, SCBPTR, active_scb); 5085 return (count); 5086 } 5087 5088 static u_int 5089 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5090 { 5091 u_int next; 5092 5093 ahc_outb(ahc, SCBPTR, scbptr); 5094 next = ahc_inb(ahc, SCB_NEXT); 5095 5096 ahc_outb(ahc, SCB_CONTROL, 0); 5097 5098 ahc_add_curscb_to_free_list(ahc); 5099 5100 if (prev != SCB_LIST_NULL) { 5101 ahc_outb(ahc, SCBPTR, prev); 5102 ahc_outb(ahc, SCB_NEXT, next); 5103 } else 5104 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5105 5106 return (next); 5107 } 5108 5109 static void 5110 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5111 { 5112 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5113 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5114 5115 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5116 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5117 } 5118 5119 /* 5120 * Manipulate the waiting for selection list and return the 5121 * scb that follows the one that we remove. 5122 */ 5123 static u_int 5124 ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5125 { 5126 u_int curscb, next; 5127 5128 /* 5129 * Select the SCB we want to abort and 5130 * pull the next pointer out of it. 5131 */ 5132 curscb = ahc_inb(ahc, SCBPTR); 5133 ahc_outb(ahc, SCBPTR, scbpos); 5134 next = ahc_inb(ahc, SCB_NEXT); 5135 5136 /* Clear the necessary fields */ 5137 ahc_outb(ahc, SCB_CONTROL, 0); 5138 5139 ahc_add_curscb_to_free_list(ahc); 5140 5141 /* update the waiting list */ 5142 if (prev == SCB_LIST_NULL) { 5143 /* First in the list */ 5144 ahc_outb(ahc, WAITING_SCBH, next); 5145 5146 /* 5147 * Ensure we aren't attempting to perform 5148 * selection for this entry. 5149 */ 5150 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5151 } else { 5152 /* 5153 * Select the scb that pointed to us 5154 * and update its next pointer. 5155 */ 5156 ahc_outb(ahc, SCBPTR, prev); 5157 ahc_outb(ahc, SCB_NEXT, next); 5158 } 5159 5160 /* 5161 * Point us back at the original scb position. 5162 */ 5163 ahc_outb(ahc, SCBPTR, curscb); 5164 return next; 5165 } 5166 5167 static void 5168 ahc_clear_intstat(struct ahc_softc *ahc) 5169 { 5170 /* Clear any interrupt conditions this may have caused */ 5171 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5172 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5173 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5174 CLRREQINIT); 5175 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5176 } 5177 5178 static void 5179 ahc_reset_current_bus(struct ahc_softc *ahc) 5180 { 5181 u_int8_t scsiseq; 5182 5183 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5184 scsiseq = ahc_inb(ahc, SCSISEQ); 5185 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5186 DELAY(AHC_BUSRESET_DELAY); 5187 /* Turn off the bus reset */ 5188 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5189 5190 ahc_clear_intstat(ahc); 5191 5192 /* Re-enable reset interrupts */ 5193 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5194 } 5195 5196 static int 5197 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5198 { 5199 u_int initiator, target, max_scsiid; 5200 u_int sblkctl; 5201 u_int our_id; 5202 int found; 5203 int restart_needed; 5204 char cur_channel; 5205 5206 ahc->pending_device = NULL; 5207 5208 pause_sequencer(ahc); 5209 5210 /* 5211 * Run our command complete fifos to ensure that we perform 5212 * completion processing on any commands that 'completed' 5213 * before the reset occurred. 5214 */ 5215 ahc_run_qoutfifo(ahc); 5216 5217 /* 5218 * Reset the bus if we are initiating this reset 5219 */ 5220 sblkctl = ahc_inb(ahc, SBLKCTL); 5221 cur_channel = 'A'; 5222 if ((ahc->features & AHC_TWIN) != 0 5223 && ((sblkctl & SELBUSB) != 0)) 5224 cur_channel = 'B'; 5225 if (cur_channel != channel) { 5226 /* Case 1: Command for another bus is active 5227 * Stealthily reset the other bus without 5228 * upsetting the current bus. 5229 */ 5230 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5231 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5232 ahc_outb(ahc, SCSISEQ, 5233 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5234 if (initiate_reset) 5235 ahc_reset_current_bus(ahc); 5236 ahc_clear_intstat(ahc); 5237 ahc_outb(ahc, SBLKCTL, sblkctl); 5238 restart_needed = FALSE; 5239 } else { 5240 /* Case 2: A command from this bus is active or we're idle */ 5241 ahc_clear_msg_state(ahc); 5242 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5243 ahc_outb(ahc, SCSISEQ, 5244 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5245 if (initiate_reset) 5246 ahc_reset_current_bus(ahc); 5247 ahc_clear_intstat(ahc); 5248 5249 /* 5250 * Since we are going to restart the sequencer, avoid 5251 * a race in the sequencer that could cause corruption 5252 * of our Q pointers by starting over from index 0. 5253 */ 5254 ahc->qoutfifonext = 0; 5255 if ((ahc->features & AHC_QUEUE_REGS) != 0) 5256 ahc_outb(ahc, SDSCB_QOFF, 0); 5257 else 5258 ahc_outb(ahc, QOUTPOS, 0); 5259 restart_needed = TRUE; 5260 } 5261 5262 /* 5263 * Clean up all the state information for the 5264 * pending transactions on this bus. 5265 */ 5266 found = ahc_abort_scbs(ahc, AHC_TARGET_WILDCARD, channel, 5267 AHC_LUN_WILDCARD, SCB_LIST_NULL, 5268 ROLE_UNKNOWN, XS_RESET); 5269 if (channel == 'B') { 5270 our_id = ahc->our_id_b; 5271 } else { 5272 our_id = ahc->our_id; 5273 } 5274 5275 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5276 5277 /* 5278 * Revert to async/narrow transfers until we renegotiate. 5279 */ 5280 for (target = 0; target <= max_scsiid; target++) { 5281 5282 if (ahc->enabled_targets[target] == NULL) 5283 continue; 5284 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5285 struct ahc_devinfo devinfo; 5286 5287 ahc_compile_devinfo(&devinfo, target, initiator, 5288 AHC_LUN_WILDCARD, 5289 channel, ROLE_UNKNOWN); 5290 ahc_set_width(ahc, &devinfo, 5291 MSG_EXT_WDTR_BUS_8_BIT, 5292 AHC_TRANS_CUR, /*paused*/TRUE, FALSE); 5293 ahc_set_syncrate(ahc, &devinfo, 5294 /*syncrate*/NULL, /*period*/0, 5295 /*offset*/0, AHC_TRANS_CUR, 5296 /*paused*/TRUE, FALSE); 5297 ahc_update_xfer_mode(ahc, &devinfo); 5298 } 5299 } 5300 5301 if (restart_needed) 5302 restart_sequencer(ahc); 5303 else 5304 unpause_sequencer(ahc); 5305 return found; 5306 } 5307 5308 static int 5309 ahc_match_scb(struct scb *scb, int target, char channel, 5310 int lun, u_int tag, role_t role) 5311 { 5312 int targ = SCB_TARGET(scb); 5313 char chan = SCB_CHANNEL(scb); 5314 int slun = SCB_LUN(scb); 5315 int match; 5316 5317 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5318 if (match != 0) 5319 match = ((targ == target) || (target == AHC_TARGET_WILDCARD)); 5320 if (match != 0) 5321 match = ((lun == slun) || (lun == AHC_LUN_WILDCARD)); 5322 5323 return match; 5324 } 5325 5326 static void 5327 ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5328 { 5329 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5330 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5331 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5332 ahc->msgout_buf[ahc->msgout_index++] = period; 5333 ahc->msgout_buf[ahc->msgout_index++] = offset; 5334 ahc->msgout_len += 5; 5335 } 5336 5337 static void 5338 ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5339 { 5340 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5341 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5342 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5343 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5344 ahc->msgout_len += 4; 5345 } 5346 5347 static void 5348 ahc_calc_residual(struct scb *scb) 5349 { 5350 struct hardware_scb *hscb; 5351 5352 hscb = scb->hscb; 5353 5354 /* 5355 * If the disconnected flag is still set, this is bogus 5356 * residual information left over from a sequencer 5357 * pagin/pageout, so ignore this case. 5358 */ 5359 if ((scb->hscb->control & DISCONNECTED) == 0) { 5360 u_int32_t resid; 5361 int resid_sgs; 5362 int sg; 5363 5364 /* 5365 * Remainder of the SG where the transfer 5366 * stopped. 5367 */ 5368 resid = (hscb->residual_data_count[2] << 16) 5369 | (hscb->residual_data_count[1] <<8) 5370 | (hscb->residual_data_count[0]); 5371 5372 /* 5373 * Add up the contents of all residual 5374 * SG segments that are after the SG where 5375 * the transfer stopped. 5376 */ 5377 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5378 sg = scb->sg_count - resid_sgs; 5379 while (resid_sgs > 0) { 5380 5381 resid += le32toh(scb->sg_list[sg].len); 5382 sg++; 5383 resid_sgs--; 5384 } 5385 scb->xs->resid = resid; 5386 } 5387 5388 /* 5389 * Clean out the residual information in this SCB for its 5390 * next consumer. 5391 */ 5392 hscb->residual_SG_count = 0; 5393 5394 #ifdef AHC_DEBUG 5395 if (ahc_debug & AHC_SHOWMISC) { 5396 scsipi_printaddr(scb->xs->xs_periph); 5397 printf("Handled Residual of %ld bytes\n" ,(long)scb->xs->resid); 5398 } 5399 #endif 5400 } 5401 5402 static void 5403 ahc_update_pending_syncrates(struct ahc_softc *ahc) 5404 { 5405 struct scb *scb; 5406 int pending_ccb_count; 5407 int i; 5408 u_int saved_scbptr; 5409 5410 /* 5411 * Traverse the pending SCB list and ensure that all of the 5412 * SCBs there have the proper settings. 5413 */ 5414 scb = LIST_FIRST(&ahc->pending_ccbs); 5415 pending_ccb_count = 0; 5416 while (scb != NULL) { 5417 struct ahc_devinfo devinfo; 5418 struct scsipi_xfer *xs; 5419 struct scb *pending_scb; 5420 struct hardware_scb *pending_hscb; 5421 struct ahc_initiator_tinfo *tinfo; 5422 struct tmode_tstate *tstate; 5423 u_int our_id, remote_id; 5424 5425 xs = scb->xs; 5426 pending_scb = scb; 5427 pending_hscb = pending_scb->hscb; 5428 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5429 ? ahc->our_id_b : ahc->our_id; 5430 remote_id = xs->xs_periph->periph_target; 5431 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5432 SCB_LUN(pending_scb), 5433 SCB_CHANNEL(pending_scb), 5434 ROLE_UNKNOWN); 5435 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5436 our_id, remote_id, &tstate); 5437 pending_hscb->control &= ~ULTRAENB; 5438 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5439 pending_hscb->control |= ULTRAENB; 5440 pending_hscb->scsirate = tinfo->scsirate; 5441 pending_hscb->scsioffset = tinfo->current.offset; 5442 pending_ccb_count++; 5443 scb = LIST_NEXT(scb, plinks); 5444 } 5445 5446 if (pending_ccb_count == 0) 5447 return; 5448 5449 saved_scbptr = ahc_inb(ahc, SCBPTR); 5450 /* Ensure that the hscbs down on the card match the new information */ 5451 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5452 u_int scb_tag; 5453 5454 ahc_outb(ahc, SCBPTR, i); 5455 scb_tag = ahc_inb(ahc, SCB_TAG); 5456 if (scb_tag != SCB_LIST_NULL) { 5457 struct ahc_devinfo devinfo; 5458 struct scb *pending_scb; 5459 struct scsipi_xfer *xs; 5460 struct hardware_scb *pending_hscb; 5461 struct ahc_initiator_tinfo *tinfo; 5462 struct tmode_tstate *tstate; 5463 u_int our_id, remote_id; 5464 u_int control; 5465 5466 pending_scb = &ahc->scb_data->scbarray[scb_tag]; 5467 if (pending_scb->flags == SCB_FREE) 5468 continue; 5469 pending_hscb = pending_scb->hscb; 5470 xs = pending_scb->xs; 5471 our_id = SCB_IS_SCSIBUS_B(pending_scb) 5472 ? ahc->our_id_b : ahc->our_id; 5473 remote_id = xs->xs_periph->periph_target; 5474 ahc_compile_devinfo(&devinfo, our_id, remote_id, 5475 SCB_LUN(pending_scb), 5476 SCB_CHANNEL(pending_scb), 5477 ROLE_UNKNOWN); 5478 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 5479 our_id, remote_id, &tstate); 5480 control = ahc_inb(ahc, SCB_CONTROL); 5481 control &= ~ULTRAENB; 5482 if ((tstate->ultraenb & devinfo.target_mask) != 0) 5483 control |= ULTRAENB; 5484 ahc_outb(ahc, SCB_CONTROL, control); 5485 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5486 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5487 } 5488 } 5489 ahc_outb(ahc, SCBPTR, saved_scbptr); 5490 } 5491 5492 #if UNUSED 5493 static void 5494 ahc_dump_targcmd(struct target_cmd *cmd) 5495 { 5496 u_int8_t *byte; 5497 u_int8_t *last_byte; 5498 int i; 5499 5500 byte = &cmd->initiator_channel; 5501 /* Debugging info for received commands */ 5502 last_byte = &cmd[1].initiator_channel; 5503 5504 i = 0; 5505 while (byte < last_byte) { 5506 if (i == 0) 5507 printf("\t"); 5508 printf("%#x", *byte++); 5509 i++; 5510 if (i == 8) { 5511 printf("\n"); 5512 i = 0; 5513 } else { 5514 printf(", "); 5515 } 5516 } 5517 } 5518 #endif 5519 5520 static void 5521 ahc_shutdown(void *arg) 5522 { 5523 struct ahc_softc *ahc; 5524 int i; 5525 u_int sxfrctl1_a, sxfrctl1_b; 5526 5527 ahc = (struct ahc_softc *)arg; 5528 5529 pause_sequencer(ahc); 5530 5531 /* 5532 * Preserve the value of the SXFRCTL1 register for all channels. 5533 * It contains settings that affect termination and we don't want 5534 * to disturb the integrity of the bus during shutdown in case 5535 * we are in a multi-initiator setup. 5536 */ 5537 sxfrctl1_b = 0; 5538 if ((ahc->features & AHC_TWIN) != 0) { 5539 u_int sblkctl; 5540 5541 sblkctl = ahc_inb(ahc, SBLKCTL); 5542 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5543 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 5544 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5545 } 5546 5547 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 5548 5549 /* This will reset most registers to 0, but not all */ 5550 ahc_reset(ahc); 5551 5552 if ((ahc->features & AHC_TWIN) != 0) { 5553 u_int sblkctl; 5554 5555 sblkctl = ahc_inb(ahc, SBLKCTL); 5556 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 5557 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 5558 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 5559 } 5560 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 5561 5562 ahc_outb(ahc, SCSISEQ, 0); 5563 ahc_outb(ahc, SXFRCTL0, 0); 5564 ahc_outb(ahc, DSPCISTATUS, 0); 5565 5566 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5567 ahc_outb(ahc, i, 0); 5568 } 5569 5570 #if defined(AHC_DEBUG) && 0 5571 static void 5572 ahc_dumptinfo(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo) 5573 { 5574 printf("%s: tinfo: rate %u\n", ahc_name(ahc), tinfo->scsirate); 5575 5576 printf("\tcurrent:\n"); 5577 printf("\t\twidth %u period %u offset %u flags %x\n", 5578 tinfo->current.width, tinfo->current.period, 5579 tinfo->current.offset, tinfo->current.ppr_flags); 5580 5581 printf("\tgoal:\n"); 5582 printf("\t\twidth %u period %u offset %u flags %x\n", 5583 tinfo->goal.width, tinfo->goal.period, 5584 tinfo->goal.offset, tinfo->goal.ppr_flags); 5585 5586 printf("\tuser:\n"); 5587 printf("\t\twidth %u period %u offset %u flags %x\n", 5588 tinfo->user.width, tinfo->user.period, 5589 tinfo->user.offset, tinfo->user.ppr_flags); 5590 } 5591 #endif 5592 5593 static int 5594 ahc_istagged_device(struct ahc_softc *ahc, struct scsipi_xfer *xs, 5595 int nocmdcheck) 5596 { 5597 #ifdef AHC_NO_TAGS 5598 return 0; 5599 #else 5600 char channel; 5601 u_int our_id, target; 5602 struct tmode_tstate *tstate; 5603 struct ahc_devinfo devinfo; 5604 5605 channel = SIM_CHANNEL(ahc, xs->xs_periph); 5606 our_id = SIM_SCSI_ID(ahc, xs->xs_periph); 5607 target = xs->xs_periph->periph_target; 5608 (void)ahc_fetch_transinfo(ahc, channel, our_id, target, &tstate); 5609 5610 ahc_compile_devinfo(&devinfo, our_id, target, 5611 xs->xs_periph->periph_lun, channel, ROLE_INITIATOR); 5612 5613 return (tstate->tagenable & devinfo.target_mask); 5614 #endif 5615 } 5616
Indexes created Thu Oct 02 01:09:59 GMT 2025