aic7xxx.c revision 1.96
1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: aic7xxx.c,v 1.96 2003/04/19 19:33:29 fvdl Exp $ 41 * 42 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $ 43 * 44 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $ 45 */ 46 /* 47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 48 */ 49 50 #include <dev/ic/aic7xxx_osm.h> 51 #include <dev/ic/aic7xxx_inline.h> 52 #include <dev/ic/aic7xxx_cam.h> 53 54 /****************************** Softc Data ************************************/ 55 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 56 57 /***************************** Lookup Tables **********************************/ 58 char *ahc_chip_names[] = 59 { 60 "NONE", 61 "aic7770", 62 "aic7850", 63 "aic7855", 64 "aic7859", 65 "aic7860", 66 "aic7870", 67 "aic7880", 68 "aic7895", 69 "aic7895C", 70 "aic7890/91", 71 "aic7896/97", 72 "aic7892", 73 "aic7899" 74 }; 75 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 76 77 /* 78 * Hardware error codes. 79 */ 80 struct ahc_hard_error_entry { 81 uint8_t errno; 82 char *errmesg; 83 }; 84 85 static struct ahc_hard_error_entry ahc_hard_errors[] = { 86 { ILLHADDR, "Illegal Host Access" }, 87 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 88 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 89 { SQPARERR, "Sequencer Parity Error" }, 90 { DPARERR, "Data-path Parity Error" }, 91 { MPARERR, "Scratch or SCB Memory Parity Error" }, 92 { PCIERRSTAT, "PCI Error detected" }, 93 { CIOPARERR, "CIOBUS Parity Error" }, 94 }; 95 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 96 97 static struct ahc_phase_table_entry ahc_phase_table[] = 98 { 99 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 100 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 101 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 102 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 103 { P_COMMAND, MSG_NOOP, "in Command phase" }, 104 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 105 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 106 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 107 { P_BUSFREE, MSG_NOOP, "while idle" }, 108 { 0, MSG_NOOP, "in unknown phase" } 109 }; 110 111 /* 112 * In most cases we only wish to itterate over real phases, so 113 * exclude the last element from the count. 114 */ 115 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 116 117 /* 118 * Valid SCSIRATE values. (p. 3-17) 119 * Provides a mapping of tranfer periods in ns to the proper value to 120 * stick in the scsixfer reg. 121 */ 122 static struct ahc_syncrate ahc_syncrates[] = 123 { 124 /* ultra2 fast/ultra period rate */ 125 { 0x42, 0x000, 9, "80.0" }, 126 { 0x03, 0x000, 10, "40.0" }, 127 { 0x04, 0x000, 11, "33.0" }, 128 { 0x05, 0x100, 12, "20.0" }, 129 { 0x06, 0x110, 15, "16.0" }, 130 { 0x07, 0x120, 18, "13.4" }, 131 { 0x08, 0x000, 25, "10.0" }, 132 { 0x19, 0x010, 31, "8.0" }, 133 { 0x1a, 0x020, 37, "6.67" }, 134 { 0x1b, 0x030, 43, "5.7" }, 135 { 0x1c, 0x040, 50, "5.0" }, 136 { 0x00, 0x050, 56, "4.4" }, 137 { 0x00, 0x060, 62, "4.0" }, 138 { 0x00, 0x070, 68, "3.6" }, 139 { 0x00, 0x000, 0, NULL } 140 }; 141 142 /* Our Sequencer Program */ 143 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 144 145 /**************************** Function Declarations ***************************/ 146 static void ahc_force_renegotiation(struct ahc_softc *ahc); 147 static struct ahc_tmode_tstate* 148 ahc_alloc_tstate(struct ahc_softc *ahc, 149 u_int scsi_id, char channel); 150 #ifdef AHC_TARGET_MODE 151 static void ahc_free_tstate(struct ahc_softc *ahc, 152 u_int scsi_id, char channel, int force); 153 #endif 154 static struct ahc_syncrate* 155 ahc_devlimited_syncrate(struct ahc_softc *ahc, 156 struct ahc_initiator_tinfo *, 157 u_int *period, 158 u_int *ppr_options, 159 role_t role); 160 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 161 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 162 struct ahc_devinfo *devinfo); 163 static void ahc_scb_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo, 165 struct scb *scb); 166 static void ahc_assert_atn(struct ahc_softc *ahc); 167 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo, 169 struct scb *scb); 170 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 171 struct ahc_devinfo *devinfo); 172 static void ahc_construct_sdtr(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo, 174 u_int period, u_int offset); 175 static void ahc_construct_wdtr(struct ahc_softc *ahc, 176 struct ahc_devinfo *devinfo, 177 u_int bus_width); 178 static void ahc_construct_ppr(struct ahc_softc *ahc, 179 struct ahc_devinfo *devinfo, 180 u_int period, u_int offset, 181 u_int bus_width, u_int ppr_options); 182 static void ahc_clear_msg_state(struct ahc_softc *ahc); 183 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 184 static void ahc_handle_message_phase(struct ahc_softc *ahc); 185 typedef enum { 186 AHCMSG_1B, 187 AHCMSG_2B, 188 AHCMSG_EXT 189 } ahc_msgtype; 190 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 191 u_int msgval, int full); 192 static int ahc_parse_msg(struct ahc_softc *ahc, 193 struct ahc_devinfo *devinfo); 194 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 199 static void ahc_handle_devreset(struct ahc_softc *ahc, 200 struct ahc_devinfo *devinfo, 201 cam_status status, char *message, 202 int verbose_level); 203 #if AHC_TARGET_MODE 204 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 205 struct ahc_devinfo *devinfo, 206 struct scb *scb); 207 #endif 208 209 //static bus_dmamap_callback_t ahc_dmamap_cb; 210 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 211 static int ahc_init_scbdata(struct ahc_softc *ahc); 212 static void ahc_fini_scbdata(struct ahc_softc *ahc); 213 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 214 struct scb *prev_scb, 215 struct scb *scb); 216 static int ahc_qinfifo_count(struct ahc_softc *ahc); 217 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 218 u_int prev, u_int scbptr); 219 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 220 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 221 u_int scbpos, u_int prev); 222 static void ahc_reset_current_bus(struct ahc_softc *ahc); 223 #ifdef AHC_DUMP_SEQ 224 static void ahc_dumpseq(struct ahc_softc *ahc); 225 #endif 226 static void ahc_loadseq(struct ahc_softc *ahc); 227 static int ahc_check_patch(struct ahc_softc *ahc, 228 struct patch **start_patch, 229 u_int start_instr, u_int *skip_addr); 230 static void ahc_download_instr(struct ahc_softc *ahc, 231 u_int instrptr, uint8_t *dconsts); 232 #ifdef AHC_TARGET_MODE 233 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 234 struct ahc_tmode_lstate *lstate, 235 u_int initiator_id, 236 u_int event_type, 237 u_int event_arg); 238 static void ahc_update_scsiid(struct ahc_softc *ahc, 239 u_int targid_mask); 240 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 241 struct target_cmd *cmd); 242 #endif 243 244 /************************** Added for porting to NetBSD ***********************/ 245 static int ahc_createdmamem(bus_dma_tag_t tag, 246 int size, 247 int flags, 248 bus_dmamap_t *mapp, 249 caddr_t *vaddr, 250 bus_addr_t *baddr, 251 bus_dma_segment_t *seg, 252 int *nseg, 253 const char *myname, const char *what); 254 static void ahc_freedmamem(bus_dma_tag_t tag, 255 int size, 256 bus_dmamap_t map, 257 caddr_t vaddr, 258 bus_dma_segment_t *seg, 259 int nseg); 260 261 /************************* Sequencer Execution Control ************************/ 262 /* 263 * Restart the sequencer program from address zero 264 */ 265 void 266 ahc_restart(struct ahc_softc *ahc) 267 { 268 269 ahc_pause(ahc); 270 271 /* No more pending messages. */ 272 ahc_clear_msg_state(ahc); 273 274 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 275 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 276 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 277 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 278 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 279 ahc_outb(ahc, SAVED_LUN, 0xFF); 280 281 /* 282 * Ensure that the sequencer's idea of TQINPOS 283 * matches our own. The sequencer increments TQINPOS 284 * only after it sees a DMA complete and a reset could 285 * occur before the increment leaving the kernel to believe 286 * the command arrived but the sequencer to not. 287 */ 288 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 289 290 /* Always allow reselection */ 291 ahc_outb(ahc, SCSISEQ, 292 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 293 if ((ahc->features & AHC_CMD_CHAN) != 0) { 294 /* Ensure that no DMA operations are in progress */ 295 ahc_outb(ahc, CCSCBCNT, 0); 296 ahc_outb(ahc, CCSGCTL, 0); 297 ahc_outb(ahc, CCSCBCTL, 0); 298 } 299 /* 300 * If we were in the process of DMA'ing SCB data into 301 * an SCB, replace that SCB on the free list. This prevents 302 * an SCB leak. 303 */ 304 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 305 ahc_add_curscb_to_free_list(ahc); 306 ahc_outb(ahc, SEQ_FLAGS2, 307 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 308 } 309 ahc_outb(ahc, MWI_RESIDUAL, 0); 310 ahc_outb(ahc, SEQCTL, FASTMODE); 311 ahc_outb(ahc, SEQADDR0, 0); 312 ahc_outb(ahc, SEQADDR1, 0); 313 ahc_unpause(ahc); 314 } 315 316 /************************* Input/Output Queues ********************************/ 317 void 318 ahc_run_qoutfifo(struct ahc_softc *ahc) 319 { 320 struct scb *scb; 321 u_int scb_index; 322 323 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 324 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 325 326 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 327 if ((ahc->qoutfifonext & 0x03) == 0x03) { 328 u_int modnext; 329 330 /* 331 * Clear 32bits of QOUTFIFO at a time 332 * so that we don't clobber an incoming 333 * byte DMA to the array on architectures 334 * that only support 32bit load and store 335 * operations. 336 */ 337 modnext = ahc->qoutfifonext & ~0x3; 338 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 339 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 340 ahc->shared_data_dmamap, 341 /*offset*/modnext, /*len*/4, 342 BUS_DMASYNC_PREREAD); 343 } 344 ahc->qoutfifonext++; 345 346 scb = ahc_lookup_scb(ahc, scb_index); 347 if (scb == NULL) { 348 printf("%s: WARNING no command for scb %d " 349 "(cmdcmplt)\nQOUTPOS = %d\n", 350 ahc_name(ahc), scb_index, 351 (ahc->qoutfifonext - 1) & 0xFF); 352 continue; 353 } 354 355 /* 356 * Save off the residual 357 * if there is one. 358 */ 359 ahc_update_residual(ahc, scb); 360 ahc_done(ahc, scb); 361 } 362 } 363 364 void 365 ahc_run_untagged_queues(struct ahc_softc *ahc) 366 { 367 int i; 368 369 for (i = 0; i < 16; i++) 370 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 371 } 372 373 void 374 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 375 { 376 struct scb *scb; 377 378 if (ahc->untagged_queue_lock != 0) 379 return; 380 381 if ((scb = TAILQ_FIRST(queue)) != NULL 382 && (scb->flags & SCB_ACTIVE) == 0) { 383 scb->flags |= SCB_ACTIVE; 384 ahc_queue_scb(ahc, scb); 385 } 386 } 387 388 /************************* Interrupt Handling *********************************/ 389 void 390 ahc_handle_brkadrint(struct ahc_softc *ahc) 391 { 392 /* 393 * We upset the sequencer :-( 394 * Lookup the error message 395 */ 396 int i; 397 int error; 398 399 error = ahc_inb(ahc, ERROR); 400 for (i = 0; error != 1 && i < num_errors; i++) 401 error >>= 1; 402 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 403 ahc_name(ahc), ahc_hard_errors[i].errmesg, 404 ahc_inb(ahc, SEQADDR0) | 405 (ahc_inb(ahc, SEQADDR1) << 8)); 406 407 ahc_dump_card_state(ahc); 408 409 /* Tell everyone that this HBA is no longer availible */ 410 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 411 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 412 CAM_NO_HBA); 413 414 /* Disable all interrupt sources by resetting the controller */ 415 ahc_shutdown(ahc); 416 } 417 418 void 419 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 420 { 421 struct scb *scb; 422 struct ahc_devinfo devinfo; 423 424 ahc_fetch_devinfo(ahc, &devinfo); 425 426 /* 427 * Clear the upper byte that holds SEQINT status 428 * codes and clear the SEQINT bit. We will unpause 429 * the sequencer, if appropriate, after servicing 430 * the request. 431 */ 432 ahc_outb(ahc, CLRINT, CLRSEQINT); 433 switch (intstat & SEQINT_MASK) { 434 case BAD_STATUS: 435 { 436 u_int scb_index; 437 struct hardware_scb *hscb; 438 439 /* 440 * Set the default return value to 0 (don't 441 * send sense). The sense code will change 442 * this if needed. 443 */ 444 ahc_outb(ahc, RETURN_1, 0); 445 446 /* 447 * The sequencer will notify us when a command 448 * has an error that would be of interest to 449 * the kernel. This allows us to leave the sequencer 450 * running in the common case of command completes 451 * without error. The sequencer will already have 452 * dma'd the SCB back up to us, so we can reference 453 * the in kernel copy directly. 454 */ 455 scb_index = ahc_inb(ahc, SCB_TAG); 456 scb = ahc_lookup_scb(ahc, scb_index); 457 if (scb == NULL) { 458 ahc_print_devinfo(ahc, &devinfo); 459 printf("ahc_intr - referenced scb " 460 "not valid during seqint 0x%x scb(%d)\n", 461 intstat, scb_index); 462 ahc_dump_card_state(ahc); 463 panic("for safety"); 464 goto unpause; 465 } 466 467 hscb = scb->hscb; 468 469 /* Don't want to clobber the original sense code */ 470 if ((scb->flags & SCB_SENSE) != 0) { 471 /* 472 * Clear the SCB_SENSE Flag and have 473 * the sequencer do a normal command 474 * complete. 475 */ 476 scb->flags &= ~SCB_SENSE; 477 break; 478 } 479 /* Freeze the queue until the client sees the error. */ 480 ahc_freeze_devq(ahc, scb); 481 ahc_freeze_scb(scb); 482 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 483 switch (hscb->shared_data.status.scsi_status) { 484 case SCSI_STATUS_OK: 485 printf("%s: Interrupted for status of 0 (???)\n", 486 ahc_name(ahc)); 487 break; 488 case SCSI_STATUS_CMD_TERMINATED: 489 case SCSI_STATUS_CHECK_COND: 490 { 491 struct ahc_dma_seg *sg; 492 struct scsipi_sense *sc; 493 struct ahc_initiator_tinfo *targ_info; 494 struct ahc_tmode_tstate *tstate; 495 struct ahc_transinfo *tinfo; 496 #ifdef AHC_DEBUG 497 if (ahc_debug & AHC_SHOW_SENSE) { 498 ahc_print_path(ahc, scb); 499 printf("SCB %d: requests Check Status\n", 500 scb->hscb->tag); 501 } 502 #endif 503 504 if (ahc_perform_autosense(scb) == 0) 505 break; 506 507 targ_info = ahc_fetch_transinfo(ahc, 508 devinfo.channel, 509 devinfo.our_scsiid, 510 devinfo.target, 511 &tstate); 512 tinfo = &targ_info->curr; 513 sg = scb->sg_list; 514 sc = (struct scsipi_sense *)(&hscb->shared_data.cdb); 515 /* 516 * Save off the residual if there is one. 517 */ 518 ahc_update_residual(ahc, scb); 519 #ifdef AHC_DEBUG 520 if (ahc_debug & AHC_SHOW_SENSE) { 521 ahc_print_path(ahc, scb); 522 printf("Sending Sense\n"); 523 } 524 #endif 525 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 526 sg->len = ahc_get_sense_bufsize(ahc, scb); 527 sg->len |= AHC_DMA_LAST_SEG; 528 529 /* Fixup byte order */ 530 sg->addr = ahc_htole32(sg->addr); 531 sg->len = ahc_htole32(sg->len); 532 533 sc->opcode = REQUEST_SENSE; 534 sc->byte2 = 0; 535 if (tinfo->protocol_version <= SCSI_REV_2 536 && SCB_GET_LUN(scb) < 8) 537 sc->byte2 = SCB_GET_LUN(scb) << 5; 538 sc->unused[0] = 0; 539 sc->unused[1] = 0; 540 sc->length = sg->len; 541 sc->control = 0; 542 543 /* 544 * We can't allow the target to disconnect. 545 * This will be an untagged transaction and 546 * having the target disconnect will make this 547 * transaction indestinguishable from outstanding 548 * tagged transactions. 549 */ 550 hscb->control = 0; 551 552 /* 553 * This request sense could be because the 554 * the device lost power or in some other 555 * way has lost our transfer negotiations. 556 * Renegotiate if appropriate. Unit attention 557 * errors will be reported before any data 558 * phases occur. 559 */ 560 if (ahc_get_residual(scb) 561 == ahc_get_transfer_length(scb)) { 562 ahc_update_neg_request(ahc, &devinfo, 563 tstate, targ_info, 564 AHC_NEG_IF_NON_ASYNC); 565 } 566 if (tstate->auto_negotiate & devinfo.target_mask) { 567 hscb->control |= MK_MESSAGE; 568 scb->flags &= ~SCB_NEGOTIATE; 569 scb->flags |= SCB_AUTO_NEGOTIATE; 570 } 571 hscb->cdb_len = sizeof(*sc); 572 hscb->dataptr = sg->addr; 573 hscb->datacnt = sg->len; 574 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 575 hscb->sgptr = ahc_htole32(hscb->sgptr); 576 scb->sg_count = 1; 577 scb->flags |= SCB_SENSE; 578 ahc_qinfifo_requeue_tail(ahc, scb); 579 ahc_outb(ahc, RETURN_1, SEND_SENSE); 580 /* 581 * Ensure we have enough time to actually 582 * retrieve the sense. 583 */ 584 ahc_scb_timer_reset(scb, 5 * 1000000); 585 break; 586 } 587 default: 588 break; 589 } 590 break; 591 } 592 case NO_MATCH: 593 { 594 /* Ensure we don't leave the selection hardware on */ 595 ahc_outb(ahc, SCSISEQ, 596 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 597 598 printf("%s:%c:%d: no active SCB for reconnecting " 599 "target - issuing BUS DEVICE RESET\n", 600 ahc_name(ahc), devinfo.channel, devinfo.target); 601 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 602 "ARG_1 == 0x%x ACCUM = 0x%x\n", 603 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 604 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 605 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 606 "SINDEX == 0x%x\n", 607 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 608 ahc_index_busy_tcl(ahc, 609 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 610 ahc_inb(ahc, SAVED_LUN))), 611 ahc_inb(ahc, SINDEX)); 612 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 613 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 614 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 615 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 616 ahc_inb(ahc, SCB_CONTROL)); 617 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 618 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 619 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 620 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 621 ahc_dump_card_state(ahc); 622 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 623 ahc->msgout_len = 1; 624 ahc->msgout_index = 0; 625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 626 ahc_outb(ahc, MSG_OUT, HOST_MSG); 627 ahc_assert_atn(ahc); 628 break; 629 } 630 case SEND_REJECT: 631 { 632 u_int rejbyte = ahc_inb(ahc, ACCUM); 633 printf("%s:%c:%d: Warning - unknown message received from " 634 "target (0x%x). Rejecting\n", 635 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 636 break; 637 } 638 case PROTO_VIOLATION: 639 { 640 ahc_handle_proto_violation(ahc); 641 break; 642 } 643 case IGN_WIDE_RES: 644 ahc_handle_ign_wide_residue(ahc, &devinfo); 645 break; 646 case PDATA_REINIT: 647 ahc_reinitialize_dataptrs(ahc); 648 break; 649 case BAD_PHASE: 650 { 651 u_int lastphase; 652 653 lastphase = ahc_inb(ahc, LASTPHASE); 654 printf("%s:%c:%d: unknown scsi bus phase %x, " 655 "lastphase = 0x%x. Attempting to continue\n", 656 ahc_name(ahc), devinfo.channel, devinfo.target, 657 lastphase, ahc_inb(ahc, SCSISIGI)); 658 break; 659 } 660 case MISSED_BUSFREE: 661 { 662 u_int lastphase; 663 664 lastphase = ahc_inb(ahc, LASTPHASE); 665 printf("%s:%c:%d: Missed busfree. " 666 "Lastphase = 0x%x, Curphase = 0x%x\n", 667 ahc_name(ahc), devinfo.channel, devinfo.target, 668 lastphase, ahc_inb(ahc, SCSISIGI)); 669 ahc_restart(ahc); 670 return; 671 } 672 case HOST_MSG_LOOP: 673 { 674 /* 675 * The sequencer has encountered a message phase 676 * that requires host assistance for completion. 677 * While handling the message phase(s), we will be 678 * notified by the sequencer after each byte is 679 * transfered so we can track bus phase changes. 680 * 681 * If this is the first time we've seen a HOST_MSG_LOOP 682 * interrupt, initialize the state of the host message 683 * loop. 684 */ 685 if (ahc->msg_type == MSG_TYPE_NONE) { 686 struct scb *scb; 687 u_int scb_index; 688 u_int bus_phase; 689 690 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 691 if (bus_phase != P_MESGIN 692 && bus_phase != P_MESGOUT) { 693 printf("ahc_intr: HOST_MSG_LOOP bad " 694 "phase 0x%x\n", 695 bus_phase); 696 /* 697 * Probably transitioned to bus free before 698 * we got here. Just punt the message. 699 */ 700 ahc_clear_intstat(ahc); 701 ahc_restart(ahc); 702 return; 703 } 704 705 scb_index = ahc_inb(ahc, SCB_TAG); 706 scb = ahc_lookup_scb(ahc, scb_index); 707 if (devinfo.role == ROLE_INITIATOR) { 708 if (scb == NULL) 709 panic("HOST_MSG_LOOP with " 710 "invalid SCB %x\n", scb_index); 711 712 if (bus_phase == P_MESGOUT) 713 ahc_setup_initiator_msgout(ahc, 714 &devinfo, 715 scb); 716 else { 717 ahc->msg_type = 718 MSG_TYPE_INITIATOR_MSGIN; 719 ahc->msgin_index = 0; 720 } 721 } 722 #if AHC_TARGET_MODE 723 else { 724 if (bus_phase == P_MESGOUT) { 725 ahc->msg_type = 726 MSG_TYPE_TARGET_MSGOUT; 727 ahc->msgin_index = 0; 728 } 729 else 730 ahc_setup_target_msgin(ahc, 731 &devinfo, 732 scb); 733 } 734 #endif 735 } 736 737 ahc_handle_message_phase(ahc); 738 break; 739 } 740 case PERR_DETECTED: 741 { 742 /* 743 * If we've cleared the parity error interrupt 744 * but the sequencer still believes that SCSIPERR 745 * is true, it must be that the parity error is 746 * for the currently presented byte on the bus, 747 * and we are not in a phase (data-in) where we will 748 * eventually ack this byte. Ack the byte and 749 * throw it away in the hope that the target will 750 * take us to message out to deliver the appropriate 751 * error message. 752 */ 753 if ((intstat & SCSIINT) == 0 754 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 755 756 if ((ahc->features & AHC_DT) == 0) { 757 u_int curphase; 758 759 /* 760 * The hardware will only let you ack bytes 761 * if the expected phase in SCSISIGO matches 762 * the current phase. Make sure this is 763 * currently the case. 764 */ 765 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 766 ahc_outb(ahc, LASTPHASE, curphase); 767 ahc_outb(ahc, SCSISIGO, curphase); 768 } 769 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 770 int wait; 771 772 /* 773 * In a data phase. Faster to bitbucket 774 * the data than to individually ack each 775 * byte. This is also the only strategy 776 * that will work with AUTOACK enabled. 777 */ 778 ahc_outb(ahc, SXFRCTL1, 779 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 780 wait = 5000; 781 while (--wait != 0) { 782 if ((ahc_inb(ahc, SCSISIGI) 783 & (CDI|MSGI)) != 0) 784 break; 785 ahc_delay(100); 786 } 787 ahc_outb(ahc, SXFRCTL1, 788 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 789 if (wait == 0) { 790 struct scb *scb; 791 u_int scb_index; 792 793 ahc_print_devinfo(ahc, &devinfo); 794 printf("Unable to clear parity error. " 795 "Resetting bus.\n"); 796 scb_index = ahc_inb(ahc, SCB_TAG); 797 scb = ahc_lookup_scb(ahc, scb_index); 798 if (scb != NULL) 799 ahc_set_transaction_status(scb, 800 CAM_UNCOR_PARITY); 801 ahc_reset_channel(ahc, devinfo.channel, 802 /*init reset*/TRUE); 803 } 804 } else { 805 ahc_inb(ahc, SCSIDATL); 806 } 807 } 808 break; 809 } 810 case DATA_OVERRUN: 811 { 812 /* 813 * When the sequencer detects an overrun, it 814 * places the controller in "BITBUCKET" mode 815 * and allows the target to complete its transfer. 816 * Unfortunately, none of the counters get updated 817 * when the controller is in this mode, so we have 818 * no way of knowing how large the overrun was. 819 */ 820 u_int scbindex = ahc_inb(ahc, SCB_TAG); 821 u_int lastphase = ahc_inb(ahc, LASTPHASE); 822 u_int i; 823 824 scb = ahc_lookup_scb(ahc, scbindex); 825 for (i = 0; i < num_phases; i++) { 826 if (lastphase == ahc_phase_table[i].phase) 827 break; 828 } 829 ahc_print_path(ahc, scb); 830 printf("data overrun detected %s." 831 " Tag == 0x%x.\n", 832 ahc_phase_table[i].phasemsg, 833 scb->hscb->tag); 834 ahc_print_path(ahc, scb); 835 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 836 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 837 ahc_get_transfer_length(scb), scb->sg_count); 838 if (scb->sg_count > 0) { 839 for (i = 0; i < scb->sg_count; i++) { 840 841 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 842 i, 843 (ahc_le32toh(scb->sg_list[i].len) >> 24 844 & SG_HIGH_ADDR_BITS), 845 ahc_le32toh(scb->sg_list[i].addr), 846 ahc_le32toh(scb->sg_list[i].len) 847 & AHC_SG_LEN_MASK); 848 } 849 } 850 /* 851 * Set this and it will take effect when the 852 * target does a command complete. 853 */ 854 ahc_freeze_devq(ahc, scb); 855 if ((scb->flags & SCB_SENSE) == 0) { 856 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 857 } else { 858 scb->flags &= ~SCB_SENSE; 859 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 860 } 861 ahc_freeze_scb(scb); 862 863 if ((ahc->features & AHC_ULTRA2) != 0) { 864 /* 865 * Clear the channel in case we return 866 * to data phase later. 867 */ 868 ahc_outb(ahc, SXFRCTL0, 869 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 870 ahc_outb(ahc, SXFRCTL0, 871 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 872 } 873 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 874 u_int dscommand1; 875 876 /* Ensure HHADDR is 0 for future DMA operations. */ 877 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 878 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 879 ahc_outb(ahc, HADDR, 0); 880 ahc_outb(ahc, DSCOMMAND1, dscommand1); 881 } 882 break; 883 } 884 case MKMSG_FAILED: 885 { 886 u_int scbindex; 887 888 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 889 ahc_name(ahc), devinfo.channel, devinfo.target, 890 devinfo.lun); 891 scbindex = ahc_inb(ahc, SCB_TAG); 892 scb = ahc_lookup_scb(ahc, scbindex); 893 if (scb != NULL 894 && (scb->flags & SCB_RECOVERY_SCB) != 0) 895 /* 896 * Ensure that we didn't put a second instance of this 897 * SCB into the QINFIFO. 898 */ 899 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 900 SCB_GET_CHANNEL(ahc, scb), 901 SCB_GET_LUN(scb), scb->hscb->tag, 902 ROLE_INITIATOR, /*status*/0, 903 SEARCH_REMOVE); 904 break; 905 } 906 case NO_FREE_SCB: 907 { 908 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 909 ahc_dump_card_state(ahc); 910 panic("for safety"); 911 break; 912 } 913 case SCB_MISMATCH: 914 { 915 u_int scbptr; 916 917 scbptr = ahc_inb(ahc, SCBPTR); 918 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 919 scbptr, ahc_inb(ahc, ARG_1), 920 ahc->scb_data->hscbs[scbptr].tag); 921 ahc_dump_card_state(ahc); 922 panic("for saftey"); 923 break; 924 } 925 case OUT_OF_RANGE: 926 { 927 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 928 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 929 "ARG_1 == 0x%x ACCUM = 0x%x\n", 930 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 931 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 932 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 933 "SINDEX == 0x%x\n, A == 0x%x\n", 934 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 935 ahc_index_busy_tcl(ahc, 936 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 937 ahc_inb(ahc, SAVED_LUN))), 938 ahc_inb(ahc, SINDEX), 939 ahc_inb(ahc, ACCUM)); 940 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 941 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 942 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 943 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 944 ahc_inb(ahc, SCB_CONTROL)); 945 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 946 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 947 ahc_dump_card_state(ahc); 948 panic("for safety"); 949 break; 950 } 951 default: 952 printf("ahc_intr: seqint, " 953 "intstat == 0x%x, scsisigi = 0x%x\n", 954 intstat, ahc_inb(ahc, SCSISIGI)); 955 break; 956 } 957 unpause: 958 /* 959 * The sequencer is paused immediately on 960 * a SEQINT, so we should restart it when 961 * we're done. 962 */ 963 ahc_unpause(ahc); 964 } 965 966 void 967 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 968 { 969 u_int scb_index; 970 u_int status0; 971 u_int status; 972 struct scb *scb; 973 char cur_channel; 974 char intr_channel; 975 976 if ((ahc->features & AHC_TWIN) != 0 977 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 978 cur_channel = 'B'; 979 else 980 cur_channel = 'A'; 981 intr_channel = cur_channel; 982 983 if ((ahc->features & AHC_ULTRA2) != 0) 984 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 985 else 986 status0 = 0; 987 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 988 if (status == 0 && status0 == 0) { 989 if ((ahc->features & AHC_TWIN) != 0) { 990 /* Try the other channel */ 991 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 992 status = ahc_inb(ahc, SSTAT1) 993 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 994 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 995 } 996 if (status == 0) { 997 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 998 ahc_outb(ahc, CLRINT, CLRSCSIINT); 999 ahc_unpause(ahc); 1000 return; 1001 } 1002 } 1003 1004 /* Make sure the sequencer is in a safe location. */ 1005 ahc_clear_critical_section(ahc); 1006 1007 scb_index = ahc_inb(ahc, SCB_TAG); 1008 scb = ahc_lookup_scb(ahc, scb_index); 1009 if (scb != NULL 1010 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1011 scb = NULL; 1012 1013 if ((ahc->features & AHC_ULTRA2) != 0 1014 && (status0 & IOERR) != 0) { 1015 int now_lvd; 1016 1017 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1018 printf("%s: Transceiver State Has Changed to %s mode\n", 1019 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1020 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1021 /* 1022 * When transitioning to SE mode, the reset line 1023 * glitches, triggering an arbitration bug in some 1024 * Ultra2 controllers. This bug is cleared when we 1025 * assert the reset line. Since a reset glitch has 1026 * already occurred with this transition and a 1027 * transceiver state change is handled just like 1028 * a bus reset anyway, asserting the reset line 1029 * ourselves is safe. 1030 */ 1031 ahc_reset_channel(ahc, intr_channel, 1032 /*Initiate Reset*/now_lvd == 0); 1033 } else if ((status & SCSIRSTI) != 0) { 1034 printf("%s: Someone reset channel %c\n", 1035 ahc_name(ahc), intr_channel); 1036 if (intr_channel != cur_channel) 1037 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1038 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1039 } else if ((status & SCSIPERR) != 0) { 1040 /* 1041 * Determine the bus phase and queue an appropriate message. 1042 * SCSIPERR is latched true as soon as a parity error 1043 * occurs. If the sequencer acked the transfer that 1044 * caused the parity error and the currently presented 1045 * transfer on the bus has correct parity, SCSIPERR will 1046 * be cleared by CLRSCSIPERR. Use this to determine if 1047 * we should look at the last phase the sequencer recorded, 1048 * or the current phase presented on the bus. 1049 */ 1050 u_int mesg_out; 1051 u_int curphase; 1052 u_int errorphase; 1053 u_int lastphase; 1054 u_int scsirate; 1055 u_int i; 1056 u_int sstat2; 1057 int silent; 1058 1059 lastphase = ahc_inb(ahc, LASTPHASE); 1060 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1061 sstat2 = ahc_inb(ahc, SSTAT2); 1062 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1063 /* 1064 * For all phases save DATA, the sequencer won't 1065 * automatically ack a byte that has a parity error 1066 * in it. So the only way that the current phase 1067 * could be 'data-in' is if the parity error is for 1068 * an already acked byte in the data phase. During 1069 * synchronous data-in transfers, we may actually 1070 * ack bytes before latching the current phase in 1071 * LASTPHASE, leading to the discrepancy between 1072 * curphase and lastphase. 1073 */ 1074 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1075 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1076 errorphase = curphase; 1077 else 1078 errorphase = lastphase; 1079 1080 for (i = 0; i < num_phases; i++) { 1081 if (errorphase == ahc_phase_table[i].phase) 1082 break; 1083 } 1084 mesg_out = ahc_phase_table[i].mesg_out; 1085 silent = FALSE; 1086 if (scb != NULL) { 1087 if (SCB_IS_SILENT(scb)) 1088 silent = TRUE; 1089 else 1090 ahc_print_path(ahc, scb); 1091 scb->flags |= SCB_TRANSMISSION_ERROR; 1092 } else 1093 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1094 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1095 scsirate = ahc_inb(ahc, SCSIRATE); 1096 if (silent == FALSE) { 1097 printf("parity error detected %s. " 1098 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1099 ahc_phase_table[i].phasemsg, 1100 ahc_inw(ahc, SEQADDR0), 1101 scsirate); 1102 if ((ahc->features & AHC_DT) != 0) { 1103 if ((sstat2 & CRCVALERR) != 0) 1104 printf("\tCRC Value Mismatch\n"); 1105 if ((sstat2 & CRCENDERR) != 0) 1106 printf("\tNo terminal CRC packet " 1107 "recevied\n"); 1108 if ((sstat2 & CRCREQERR) != 0) 1109 printf("\tIllegal CRC packet " 1110 "request\n"); 1111 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1112 printf("\tUnexpected %sDT Data Phase\n", 1113 (scsirate & SINGLE_EDGE) 1114 ? "" : "non-"); 1115 } 1116 } 1117 1118 if ((ahc->features & AHC_DT) != 0 1119 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1120 /* 1121 * This error applies regardless of 1122 * data direction, so ignore the value 1123 * in the phase table. 1124 */ 1125 mesg_out = MSG_INITIATOR_DET_ERR; 1126 } 1127 1128 /* 1129 * We've set the hardware to assert ATN if we 1130 * get a parity error on "in" phases, so all we 1131 * need to do is stuff the message buffer with 1132 * the appropriate message. "In" phases have set 1133 * mesg_out to something other than MSG_NOP. 1134 */ 1135 if (mesg_out != MSG_NOOP) { 1136 if (ahc->msg_type != MSG_TYPE_NONE) 1137 ahc->send_msg_perror = TRUE; 1138 else 1139 ahc_outb(ahc, MSG_OUT, mesg_out); 1140 } 1141 /* 1142 * Force a renegotiation with this target just in 1143 * case we are out of sync for some external reason 1144 * unknown (or unreported) by the target. 1145 */ 1146 ahc_force_renegotiation(ahc); 1147 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1148 ahc_unpause(ahc); 1149 } else if ((status & SELTO) != 0) { 1150 u_int scbptr; 1151 1152 /* Stop the selection */ 1153 ahc_outb(ahc, SCSISEQ, 0); 1154 1155 /* No more pending messages */ 1156 ahc_clear_msg_state(ahc); 1157 1158 /* Clear interrupt state */ 1159 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1160 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1161 1162 /* 1163 * Although the driver does not care about the 1164 * 'Selection in Progress' status bit, the busy 1165 * LED does. SELINGO is only cleared by a sucessfull 1166 * selection, so we must manually clear it to insure 1167 * the LED turns off just incase no future successful 1168 * selections occur (e.g. no devices on the bus). 1169 */ 1170 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1171 1172 scbptr = ahc_inb(ahc, WAITING_SCBH); 1173 ahc_outb(ahc, SCBPTR, scbptr); 1174 scb_index = ahc_inb(ahc, SCB_TAG); 1175 1176 scb = ahc_lookup_scb(ahc, scb_index); 1177 if (scb == NULL) { 1178 printf("%s: ahc_intr - referenced scb not " 1179 "valid during SELTO scb(%d, %d)\n", 1180 ahc_name(ahc), scbptr, scb_index); 1181 ahc_dump_card_state(ahc); 1182 } else { 1183 #ifdef AHC_DEBUG 1184 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1185 ahc_print_path(ahc, scb); 1186 printf("Saw Selection Timeout for SCB 0x%x\n", 1187 scb_index); 1188 } 1189 #endif 1190 /* 1191 * Force a renegotiation with this target just in 1192 * case the cable was pulled and will later be 1193 * re-attached. The target may forget its negotiation 1194 * settings with us should it attempt to reselect 1195 * during the interruption. The target will not issue 1196 * a unit attention in this case, so we must always 1197 * renegotiate. 1198 */ 1199 ahc_force_renegotiation(ahc); 1200 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1201 ahc_freeze_devq(ahc, scb); 1202 } 1203 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1204 ahc_restart(ahc); 1205 } else if ((status & BUSFREE) != 0 1206 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1207 u_int lastphase; 1208 u_int saved_scsiid; 1209 u_int saved_lun; 1210 u_int target; 1211 u_int initiator_role_id; 1212 char channel; 1213 int printerror; 1214 1215 /* 1216 * Clear our selection hardware as soon as possible. 1217 * We may have an entry in the waiting Q for this target, 1218 * that is affected by this busfree and we don't want to 1219 * go about selecting the target while we handle the event. 1220 */ 1221 ahc_outb(ahc, SCSISEQ, 1222 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1223 1224 /* 1225 * Disable busfree interrupts and clear the busfree 1226 * interrupt status. We do this here so that several 1227 * bus transactions occur prior to clearing the SCSIINT 1228 * latch. It can take a bit for the clearing to take effect. 1229 */ 1230 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1231 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1232 1233 /* 1234 * Look at what phase we were last in. 1235 * If its message out, chances are pretty good 1236 * that the busfree was in response to one of 1237 * our abort requests. 1238 */ 1239 lastphase = ahc_inb(ahc, LASTPHASE); 1240 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1241 saved_lun = ahc_inb(ahc, SAVED_LUN); 1242 target = SCSIID_TARGET(ahc, saved_scsiid); 1243 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1244 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1245 printerror = 1; 1246 1247 if (lastphase == P_MESGOUT) { 1248 struct ahc_devinfo devinfo; 1249 u_int tag; 1250 1251 ahc_fetch_devinfo(ahc, &devinfo); 1252 tag = SCB_LIST_NULL; 1253 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1254 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1255 if (ahc->msgout_buf[ahc->msgout_index - 1] 1256 == MSG_ABORT_TAG) 1257 tag = scb->hscb->tag; 1258 ahc_print_path(ahc, scb); 1259 printf("SCB %d - Abort%s Completed.\n", 1260 scb->hscb->tag, tag == SCB_LIST_NULL ? 1261 "" : " Tag"); 1262 ahc_abort_scbs(ahc, target, channel, 1263 saved_lun, tag, 1264 ROLE_INITIATOR, 1265 CAM_REQ_ABORTED); 1266 printerror = 0; 1267 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1268 MSG_BUS_DEV_RESET, TRUE)) { 1269 #ifdef __FreeBSD__ 1270 /* 1271 * Don't mark the user's request for this BDR 1272 * as completing with CAM_BDR_SENT. CAM3 1273 * specifies CAM_REQ_CMP. 1274 */ 1275 if (scb != NULL 1276 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1277 && ahc_match_scb(ahc, scb, target, channel, 1278 CAM_LUN_WILDCARD, 1279 SCB_LIST_NULL, 1280 ROLE_INITIATOR)) { 1281 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1282 } 1283 #endif 1284 ahc_compile_devinfo(&devinfo, 1285 initiator_role_id, 1286 target, 1287 CAM_LUN_WILDCARD, 1288 channel, 1289 ROLE_INITIATOR); 1290 ahc_handle_devreset(ahc, &devinfo, 1291 CAM_BDR_SENT, 1292 "Bus Device Reset", 1293 /*verbose_level*/0); 1294 printerror = 0; 1295 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1296 MSG_EXT_PPR, FALSE)) { 1297 struct ahc_initiator_tinfo *tinfo; 1298 struct ahc_tmode_tstate *tstate; 1299 1300 /* 1301 * PPR Rejected. Try non-ppr negotiation 1302 * and retry command. 1303 */ 1304 tinfo = ahc_fetch_transinfo(ahc, 1305 devinfo.channel, 1306 devinfo.our_scsiid, 1307 devinfo.target, 1308 &tstate); 1309 tinfo->curr.transport_version = 2; 1310 tinfo->goal.transport_version = 2; 1311 tinfo->goal.ppr_options = 0; 1312 ahc_qinfifo_requeue_tail(ahc, scb); 1313 printerror = 0; 1314 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1315 MSG_EXT_WDTR, FALSE) 1316 || ahc_sent_msg(ahc, AHCMSG_EXT, 1317 MSG_EXT_SDTR, FALSE)) { 1318 /* 1319 * Negotiation Rejected. Go-async and 1320 * retry command. 1321 */ 1322 ahc_set_width(ahc, &devinfo, 1323 MSG_EXT_WDTR_BUS_8_BIT, 1324 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1325 /*paused*/TRUE); 1326 ahc_set_syncrate(ahc, &devinfo, 1327 /*syncrate*/NULL, 1328 /*period*/0, /*offset*/0, 1329 /*ppr_options*/0, 1330 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1331 /*paused*/TRUE); 1332 ahc_qinfifo_requeue_tail(ahc, scb); 1333 printerror = 0; 1334 } 1335 } 1336 if (printerror != 0) { 1337 u_int i; 1338 1339 if (scb != NULL) { 1340 u_int tag; 1341 1342 if ((scb->hscb->control & TAG_ENB) != 0) 1343 tag = scb->hscb->tag; 1344 else 1345 tag = SCB_LIST_NULL; 1346 ahc_print_path(ahc, scb); 1347 ahc_abort_scbs(ahc, target, channel, 1348 SCB_GET_LUN(scb), tag, 1349 ROLE_INITIATOR, 1350 CAM_UNEXP_BUSFREE); 1351 } else { 1352 /* 1353 * We had not fully identified this connection, 1354 * so we cannot abort anything. 1355 */ 1356 printf("%s: ", ahc_name(ahc)); 1357 } 1358 for (i = 0; i < num_phases; i++) { 1359 if (lastphase == ahc_phase_table[i].phase) 1360 break; 1361 } 1362 /* 1363 * Renegotiate with this device at the 1364 * next oportunity just in case this busfree 1365 * is due to a negotiation mismatch with the 1366 * device. 1367 */ 1368 ahc_force_renegotiation(ahc); 1369 printf("Unexpected busfree %s\n" 1370 "SEQADDR == 0x%x\n", 1371 ahc_phase_table[i].phasemsg, 1372 ahc_inb(ahc, SEQADDR0) 1373 | (ahc_inb(ahc, SEQADDR1) << 8)); 1374 } 1375 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1376 ahc_restart(ahc); 1377 } else { 1378 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1379 ahc_name(ahc), status); 1380 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1381 } 1382 } 1383 1384 /* 1385 * Force renegotiation to occur the next time we initiate 1386 * a command to the current device. 1387 */ 1388 static void 1389 ahc_force_renegotiation(struct ahc_softc *ahc) 1390 { 1391 struct ahc_devinfo devinfo; 1392 struct ahc_initiator_tinfo *targ_info; 1393 struct ahc_tmode_tstate *tstate; 1394 1395 ahc_fetch_devinfo(ahc, &devinfo); 1396 targ_info = ahc_fetch_transinfo(ahc, 1397 devinfo.channel, 1398 devinfo.our_scsiid, 1399 devinfo.target, 1400 &tstate); 1401 ahc_update_neg_request(ahc, &devinfo, tstate, 1402 targ_info, AHC_NEG_IF_NON_ASYNC); 1403 } 1404 1405 #define AHC_MAX_STEPS 2000 1406 void 1407 ahc_clear_critical_section(struct ahc_softc *ahc) 1408 { 1409 int stepping; 1410 int steps; 1411 u_int simode0; 1412 u_int simode1; 1413 1414 if (ahc->num_critical_sections == 0) 1415 return; 1416 1417 stepping = FALSE; 1418 steps = 0; 1419 simode0 = 0; 1420 simode1 = 0; 1421 for (;;) { 1422 struct cs *cs; 1423 u_int seqaddr; 1424 u_int i; 1425 1426 seqaddr = ahc_inb(ahc, SEQADDR0) 1427 | (ahc_inb(ahc, SEQADDR1) << 8); 1428 1429 /* 1430 * Seqaddr represents the next instruction to execute, 1431 * so we are really executing the instruction just 1432 * before it. 1433 */ 1434 if (seqaddr != 0) 1435 seqaddr -= 1; 1436 cs = ahc->critical_sections; 1437 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1438 1439 if (cs->begin < seqaddr && cs->end >= seqaddr) 1440 break; 1441 } 1442 1443 if (i == ahc->num_critical_sections) 1444 break; 1445 1446 if (steps > AHC_MAX_STEPS) { 1447 printf("%s: Infinite loop in critical section\n", 1448 ahc_name(ahc)); 1449 ahc_dump_card_state(ahc); 1450 panic("critical section loop"); 1451 } 1452 1453 steps++; 1454 if (stepping == FALSE) { 1455 1456 /* 1457 * Disable all interrupt sources so that the 1458 * sequencer will not be stuck by a pausing 1459 * interrupt condition while we attempt to 1460 * leave a critical section. 1461 */ 1462 simode0 = ahc_inb(ahc, SIMODE0); 1463 ahc_outb(ahc, SIMODE0, 0); 1464 simode1 = ahc_inb(ahc, SIMODE1); 1465 if ((ahc->features & AHC_DT) != 0) 1466 /* 1467 * On DT class controllers, we 1468 * use the enhanced busfree logic. 1469 * Unfortunately we cannot re-enable 1470 * busfree detection within the 1471 * current connection, so we must 1472 * leave it on while single stepping. 1473 */ 1474 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1475 else 1476 ahc_outb(ahc, SIMODE1, 0); 1477 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1478 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1479 stepping = TRUE; 1480 } 1481 if ((ahc->features & AHC_DT) != 0) { 1482 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1483 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1484 } 1485 ahc_outb(ahc, HCNTRL, ahc->unpause); 1486 while (!ahc_is_paused(ahc)) 1487 ahc_delay(200); 1488 } 1489 if (stepping) { 1490 ahc_outb(ahc, SIMODE0, simode0); 1491 ahc_outb(ahc, SIMODE1, simode1); 1492 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1493 } 1494 } 1495 1496 /* 1497 * Clear any pending interrupt status. 1498 */ 1499 void 1500 ahc_clear_intstat(struct ahc_softc *ahc) 1501 { 1502 /* Clear any interrupt conditions this may have caused */ 1503 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1504 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1505 CLRREQINIT); 1506 ahc_flush_device_writes(ahc); 1507 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1508 ahc_flush_device_writes(ahc); 1509 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1510 ahc_flush_device_writes(ahc); 1511 } 1512 1513 /**************************** Debugging Routines ******************************/ 1514 #ifdef AHC_DEBUG 1515 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1516 #endif 1517 1518 void 1519 ahc_print_scb(struct scb *scb) 1520 { 1521 int i; 1522 1523 struct hardware_scb *hscb = scb->hscb; 1524 1525 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1526 (void *)scb, 1527 hscb->control, 1528 hscb->scsiid, 1529 hscb->lun, 1530 hscb->cdb_len); 1531 printf("Shared Data: "); 1532 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1533 printf("%#02x", hscb->shared_data.cdb[i]); 1534 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1535 ahc_le32toh(hscb->dataptr), 1536 ahc_le32toh(hscb->datacnt), 1537 ahc_le32toh(hscb->sgptr), 1538 hscb->tag); 1539 if (scb->sg_count > 0) { 1540 for (i = 0; i < scb->sg_count; i++) { 1541 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1542 i, 1543 (ahc_le32toh(scb->sg_list[i].len) >> 24 1544 & SG_HIGH_ADDR_BITS), 1545 ahc_le32toh(scb->sg_list[i].addr), 1546 ahc_le32toh(scb->sg_list[i].len)); 1547 } 1548 } 1549 } 1550 1551 /************************* Transfer Negotiation *******************************/ 1552 /* 1553 * Allocate per target mode instance (ID we respond to as a target) 1554 * transfer negotiation data structures. 1555 */ 1556 static struct ahc_tmode_tstate * 1557 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1558 { 1559 struct ahc_tmode_tstate *master_tstate; 1560 struct ahc_tmode_tstate *tstate; 1561 int i; 1562 1563 master_tstate = ahc->enabled_targets[ahc->our_id]; 1564 if (channel == 'B') { 1565 scsi_id += 8; 1566 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1567 } 1568 if (ahc->enabled_targets[scsi_id] != NULL 1569 && ahc->enabled_targets[scsi_id] != master_tstate) 1570 panic("%s: ahc_alloc_tstate - Target already allocated", 1571 ahc_name(ahc)); 1572 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1573 M_DEVBUF, M_NOWAIT); 1574 if (tstate == NULL) 1575 return (NULL); 1576 1577 /* 1578 * If we have allocated a master tstate, copy user settings from 1579 * the master tstate (taken from SRAM or the EEPROM) for this 1580 * channel, but reset our current and goal settings to async/narrow 1581 * until an initiator talks to us. 1582 */ 1583 if (master_tstate != NULL) { 1584 memcpy(tstate, master_tstate, sizeof(*tstate)); 1585 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1586 tstate->ultraenb = 0; 1587 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1588 memset(&tstate->transinfo[i].curr, 0, 1589 sizeof(tstate->transinfo[i].curr)); 1590 memset(&tstate->transinfo[i].goal, 0, 1591 sizeof(tstate->transinfo[i].goal)); 1592 } 1593 } else 1594 memset(tstate, 0, sizeof(*tstate)); 1595 ahc->enabled_targets[scsi_id] = tstate; 1596 return (tstate); 1597 } 1598 1599 #ifdef AHC_TARGET_MODE 1600 /* 1601 * Free per target mode instance (ID we respond to as a target) 1602 * transfer negotiation data structures. 1603 */ 1604 static void 1605 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1606 { 1607 struct ahc_tmode_tstate *tstate; 1608 1609 /* 1610 * Don't clean up our "master" tstate. 1611 * It has our default user settings. 1612 */ 1613 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1614 || (channel == 'A' && scsi_id == ahc->our_id)) 1615 && force == FALSE) 1616 return; 1617 1618 if (channel == 'B') 1619 scsi_id += 8; 1620 tstate = ahc->enabled_targets[scsi_id]; 1621 if (tstate != NULL) 1622 free(tstate, M_DEVBUF); 1623 ahc->enabled_targets[scsi_id] = NULL; 1624 } 1625 #endif 1626 1627 /* 1628 * Called when we have an active connection to a target on the bus, 1629 * this function finds the nearest syncrate to the input period limited 1630 * by the capabilities of the bus connectivity of and sync settings for 1631 * the target. 1632 */ 1633 struct ahc_syncrate * 1634 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1635 struct ahc_initiator_tinfo *tinfo, 1636 u_int *period, u_int *ppr_options, role_t role) 1637 { 1638 struct ahc_transinfo *transinfo; 1639 u_int maxsync; 1640 1641 if ((ahc->features & AHC_ULTRA2) != 0) { 1642 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1643 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1644 maxsync = AHC_SYNCRATE_DT; 1645 } else { 1646 maxsync = AHC_SYNCRATE_ULTRA; 1647 /* Can't do DT on an SE bus */ 1648 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1649 } 1650 } else if ((ahc->features & AHC_ULTRA) != 0) { 1651 maxsync = AHC_SYNCRATE_ULTRA; 1652 } else { 1653 maxsync = AHC_SYNCRATE_FAST; 1654 } 1655 /* 1656 * Never allow a value higher than our current goal 1657 * period otherwise we may allow a target initiated 1658 * negotiation to go above the limit as set by the 1659 * user. In the case of an initiator initiated 1660 * sync negotiation, we limit based on the user 1661 * setting. This allows the system to still accept 1662 * incoming negotiations even if target initiated 1663 * negotiation is not performed. 1664 */ 1665 if (role == ROLE_TARGET) 1666 transinfo = &tinfo->user; 1667 else 1668 transinfo = &tinfo->goal; 1669 *ppr_options &= transinfo->ppr_options; 1670 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1671 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1672 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1673 } 1674 if (transinfo->period == 0) { 1675 *period = 0; 1676 *ppr_options = 0; 1677 return (NULL); 1678 } 1679 *period = MAX(*period, transinfo->period); 1680 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1681 } 1682 1683 /* 1684 * Look up the valid period to SCSIRATE conversion in our table. 1685 * Return the period and offset that should be sent to the target 1686 * if this was the beginning of an SDTR. 1687 */ 1688 struct ahc_syncrate * 1689 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1690 u_int *ppr_options, u_int maxsync) 1691 { 1692 struct ahc_syncrate *syncrate; 1693 1694 if ((ahc->features & AHC_DT) == 0) 1695 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1696 1697 /* Skip all DT only entries if DT is not available */ 1698 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1699 && maxsync < AHC_SYNCRATE_ULTRA2) 1700 maxsync = AHC_SYNCRATE_ULTRA2; 1701 1702 for (syncrate = &ahc_syncrates[maxsync]; 1703 syncrate->rate != NULL; 1704 syncrate++) { 1705 1706 /* 1707 * The Ultra2 table doesn't go as low 1708 * as for the Fast/Ultra cards. 1709 */ 1710 if ((ahc->features & AHC_ULTRA2) != 0 1711 && (syncrate->sxfr_u2 == 0)) 1712 break; 1713 1714 if (*period <= syncrate->period) { 1715 /* 1716 * When responding to a target that requests 1717 * sync, the requested rate may fall between 1718 * two rates that we can output, but still be 1719 * a rate that we can receive. Because of this, 1720 * we want to respond to the target with 1721 * the same rate that it sent to us even 1722 * if the period we use to send data to it 1723 * is lower. Only lower the response period 1724 * if we must. 1725 */ 1726 if (syncrate == &ahc_syncrates[maxsync]) 1727 *period = syncrate->period; 1728 1729 /* 1730 * At some speeds, we only support 1731 * ST transfers. 1732 */ 1733 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1734 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1735 break; 1736 } 1737 } 1738 1739 if ((*period == 0) 1740 || (syncrate->rate == NULL) 1741 || ((ahc->features & AHC_ULTRA2) != 0 1742 && (syncrate->sxfr_u2 == 0))) { 1743 /* Use asynchronous transfers. */ 1744 *period = 0; 1745 syncrate = NULL; 1746 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1747 } 1748 return (syncrate); 1749 } 1750 1751 /* 1752 * Convert from an entry in our syncrate table to the SCSI equivalent 1753 * sync "period" factor. 1754 */ 1755 u_int 1756 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1757 { 1758 struct ahc_syncrate *syncrate; 1759 1760 if ((ahc->features & AHC_ULTRA2) != 0) 1761 scsirate &= SXFR_ULTRA2; 1762 else 1763 scsirate &= SXFR; 1764 1765 syncrate = &ahc_syncrates[maxsync]; 1766 while (syncrate->rate != NULL) { 1767 1768 if ((ahc->features & AHC_ULTRA2) != 0) { 1769 if (syncrate->sxfr_u2 == 0) 1770 break; 1771 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1772 return (syncrate->period); 1773 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1774 return (syncrate->period); 1775 } 1776 syncrate++; 1777 } 1778 return (0); /* async */ 1779 } 1780 1781 /* 1782 * Truncate the given synchronous offset to a value the 1783 * current adapter type and syncrate are capable of. 1784 */ 1785 void 1786 ahc_validate_offset(struct ahc_softc *ahc, 1787 struct ahc_initiator_tinfo *tinfo, 1788 struct ahc_syncrate *syncrate, 1789 u_int *offset, int wide, role_t role) 1790 { 1791 u_int maxoffset; 1792 1793 /* Limit offset to what we can do */ 1794 if (syncrate == NULL) { 1795 maxoffset = 0; 1796 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1797 maxoffset = MAX_OFFSET_ULTRA2; 1798 } else { 1799 if (wide) 1800 maxoffset = MAX_OFFSET_16BIT; 1801 else 1802 maxoffset = MAX_OFFSET_8BIT; 1803 } 1804 *offset = MIN(*offset, maxoffset); 1805 if (tinfo != NULL) { 1806 if (role == ROLE_TARGET) 1807 *offset = MIN(*offset, tinfo->user.offset); 1808 else 1809 *offset = MIN(*offset, tinfo->goal.offset); 1810 } 1811 } 1812 1813 /* 1814 * Truncate the given transfer width parameter to a value the 1815 * current adapter type is capable of. 1816 */ 1817 void 1818 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1819 u_int *bus_width, role_t role) 1820 { 1821 switch (*bus_width) { 1822 default: 1823 if (ahc->features & AHC_WIDE) { 1824 /* Respond Wide */ 1825 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1826 break; 1827 } 1828 /* FALLTHROUGH */ 1829 case MSG_EXT_WDTR_BUS_8_BIT: 1830 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1831 break; 1832 } 1833 if (tinfo != NULL) { 1834 if (role == ROLE_TARGET) 1835 *bus_width = MIN(tinfo->user.width, *bus_width); 1836 else 1837 *bus_width = MIN(tinfo->goal.width, *bus_width); 1838 } 1839 } 1840 1841 /* 1842 * Update the bitmask of targets for which the controller should 1843 * negotiate with at the next convenient oportunity. This currently 1844 * means the next time we send the initial identify messages for 1845 * a new transaction. 1846 */ 1847 int 1848 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1849 struct ahc_tmode_tstate *tstate, 1850 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1851 { 1852 u_int auto_negotiate_orig; 1853 1854 auto_negotiate_orig = tstate->auto_negotiate; 1855 if (neg_type == AHC_NEG_ALWAYS) { 1856 /* 1857 * Force our "current" settings to be 1858 * unknown so that unless a bus reset 1859 * occurs the need to renegotiate is 1860 * recorded persistently. 1861 */ 1862 if ((ahc->features & AHC_WIDE) != 0) 1863 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1864 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1865 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1866 } 1867 if (tinfo->curr.period != tinfo->goal.period 1868 || tinfo->curr.width != tinfo->goal.width 1869 || tinfo->curr.offset != tinfo->goal.offset 1870 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1871 || (neg_type == AHC_NEG_IF_NON_ASYNC 1872 && (tinfo->goal.offset != 0 1873 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1874 || tinfo->goal.ppr_options != 0))) 1875 tstate->auto_negotiate |= devinfo->target_mask; 1876 else 1877 tstate->auto_negotiate &= ~devinfo->target_mask; 1878 1879 return (auto_negotiate_orig != tstate->auto_negotiate); 1880 } 1881 1882 /* 1883 * Update the user/goal/curr tables of synchronous negotiation 1884 * parameters as well as, in the case of a current or active update, 1885 * any data structures on the host controller. In the case of an 1886 * active update, the specified target is currently talking to us on 1887 * the bus, so the transfer parameter update must take effect 1888 * immediately. 1889 */ 1890 void 1891 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1892 struct ahc_syncrate *syncrate, u_int period, 1893 u_int offset, u_int ppr_options, u_int type, int paused) 1894 { 1895 struct ahc_initiator_tinfo *tinfo; 1896 struct ahc_tmode_tstate *tstate; 1897 u_int old_period; 1898 u_int old_offset; 1899 u_int old_ppr; 1900 int active; 1901 int update_needed; 1902 1903 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1904 update_needed = 0; 1905 1906 if (syncrate == NULL) { 1907 period = 0; 1908 offset = 0; 1909 } 1910 1911 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1912 devinfo->target, &tstate); 1913 1914 if ((type & AHC_TRANS_USER) != 0) { 1915 tinfo->user.period = period; 1916 tinfo->user.offset = offset; 1917 tinfo->user.ppr_options = ppr_options; 1918 } 1919 1920 if ((type & AHC_TRANS_GOAL) != 0) { 1921 tinfo->goal.period = period; 1922 tinfo->goal.offset = offset; 1923 tinfo->goal.ppr_options = ppr_options; 1924 } 1925 1926 old_period = tinfo->curr.period; 1927 old_offset = tinfo->curr.offset; 1928 old_ppr = tinfo->curr.ppr_options; 1929 1930 if ((type & AHC_TRANS_CUR) != 0 1931 && (old_period != period 1932 || old_offset != offset 1933 || old_ppr != ppr_options)) { 1934 u_int scsirate; 1935 1936 update_needed++; 1937 scsirate = tinfo->scsirate; 1938 if ((ahc->features & AHC_ULTRA2) != 0) { 1939 1940 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1941 if (syncrate != NULL) { 1942 scsirate |= syncrate->sxfr_u2; 1943 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1944 scsirate |= ENABLE_CRC; 1945 else 1946 scsirate |= SINGLE_EDGE; 1947 } 1948 } else { 1949 1950 scsirate &= ~(SXFR|SOFS); 1951 /* 1952 * Ensure Ultra mode is set properly for 1953 * this target. 1954 */ 1955 tstate->ultraenb &= ~devinfo->target_mask; 1956 if (syncrate != NULL) { 1957 if (syncrate->sxfr & ULTRA_SXFR) { 1958 tstate->ultraenb |= 1959 devinfo->target_mask; 1960 } 1961 scsirate |= syncrate->sxfr & SXFR; 1962 scsirate |= offset & SOFS; 1963 } 1964 if (active) { 1965 u_int sxfrctl0; 1966 1967 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1968 sxfrctl0 &= ~FAST20; 1969 if (tstate->ultraenb & devinfo->target_mask) 1970 sxfrctl0 |= FAST20; 1971 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1972 } 1973 } 1974 if (active) { 1975 ahc_outb(ahc, SCSIRATE, scsirate); 1976 if ((ahc->features & AHC_ULTRA2) != 0) 1977 ahc_outb(ahc, SCSIOFFSET, offset); 1978 } 1979 1980 tinfo->scsirate = scsirate; 1981 tinfo->curr.period = period; 1982 tinfo->curr.offset = offset; 1983 tinfo->curr.ppr_options = ppr_options; 1984 1985 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1986 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1987 if (bootverbose) { 1988 if (offset != 0) { 1989 printf("%s: target %d synchronous at %sMHz%s, " 1990 "offset = 0x%x\n", ahc_name(ahc), 1991 devinfo->target, syncrate->rate, 1992 (ppr_options & MSG_EXT_PPR_DT_REQ) 1993 ? " DT" : "", offset); 1994 } else { 1995 printf("%s: target %d using " 1996 "asynchronous transfers\n", 1997 ahc_name(ahc), devinfo->target); 1998 } 1999 } 2000 } 2001 2002 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2003 tinfo, AHC_NEG_TO_GOAL); 2004 2005 if (update_needed) 2006 ahc_update_pending_scbs(ahc); 2007 } 2008 2009 /* 2010 * Update the user/goal/curr tables of wide negotiation 2011 * parameters as well as, in the case of a current or active update, 2012 * any data structures on the host controller. In the case of an 2013 * active update, the specified target is currently talking to us on 2014 * the bus, so the transfer parameter update must take effect 2015 * immediately. 2016 */ 2017 void 2018 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2019 u_int width, u_int type, int paused) 2020 { 2021 struct ahc_initiator_tinfo *tinfo; 2022 struct ahc_tmode_tstate *tstate; 2023 u_int oldwidth; 2024 int active; 2025 int update_needed; 2026 2027 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2028 update_needed = 0; 2029 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2030 devinfo->target, &tstate); 2031 2032 if ((type & AHC_TRANS_USER) != 0) 2033 tinfo->user.width = width; 2034 2035 if ((type & AHC_TRANS_GOAL) != 0) 2036 tinfo->goal.width = width; 2037 2038 oldwidth = tinfo->curr.width; 2039 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2040 u_int scsirate; 2041 2042 update_needed++; 2043 scsirate = tinfo->scsirate; 2044 scsirate &= ~WIDEXFER; 2045 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2046 scsirate |= WIDEXFER; 2047 2048 tinfo->scsirate = scsirate; 2049 2050 if (active) 2051 ahc_outb(ahc, SCSIRATE, scsirate); 2052 2053 tinfo->curr.width = width; 2054 2055 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2056 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2057 if (bootverbose) { 2058 printf("%s: target %d using %dbit transfers\n", 2059 ahc_name(ahc), devinfo->target, 2060 8 * (0x01 << width)); 2061 } 2062 } 2063 2064 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2065 tinfo, AHC_NEG_TO_GOAL); 2066 if (update_needed) 2067 ahc_update_pending_scbs(ahc); 2068 } 2069 2070 /* 2071 * Update the current state of tagged queuing for a given target. 2072 */ 2073 void 2074 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2075 ahc_queue_alg alg) 2076 { 2077 ahc_platform_set_tags(ahc, devinfo, alg); 2078 } 2079 2080 /* 2081 * When the transfer settings for a connection change, update any 2082 * in-transit SCBs to contain the new data so the hardware will 2083 * be set correctly during future (re)selections. 2084 */ 2085 static void 2086 ahc_update_pending_scbs(struct ahc_softc *ahc) 2087 { 2088 struct scb *pending_scb; 2089 int pending_scb_count; 2090 int i; 2091 int paused; 2092 u_int saved_scbptr; 2093 2094 /* 2095 * Traverse the pending SCB list and ensure that all of the 2096 * SCBs there have the proper settings. 2097 */ 2098 pending_scb_count = 0; 2099 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2100 struct ahc_devinfo devinfo; 2101 struct hardware_scb *pending_hscb; 2102 struct ahc_initiator_tinfo *tinfo; 2103 struct ahc_tmode_tstate *tstate; 2104 2105 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2106 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2107 devinfo.our_scsiid, 2108 devinfo.target, &tstate); 2109 pending_hscb = pending_scb->hscb; 2110 pending_hscb->control &= ~ULTRAENB; 2111 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2112 pending_hscb->control |= ULTRAENB; 2113 pending_hscb->scsirate = tinfo->scsirate; 2114 pending_hscb->scsioffset = tinfo->curr.offset; 2115 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2116 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2117 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2118 pending_hscb->control &= ~MK_MESSAGE; 2119 } 2120 ahc_sync_scb(ahc, pending_scb, 2121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2122 pending_scb_count++; 2123 } 2124 2125 if (pending_scb_count == 0) 2126 return; 2127 2128 if (ahc_is_paused(ahc)) { 2129 paused = 1; 2130 } else { 2131 paused = 0; 2132 ahc_pause(ahc); 2133 } 2134 2135 saved_scbptr = ahc_inb(ahc, SCBPTR); 2136 /* Ensure that the hscbs down on the card match the new information */ 2137 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2138 struct hardware_scb *pending_hscb; 2139 u_int control; 2140 u_int scb_tag; 2141 2142 ahc_outb(ahc, SCBPTR, i); 2143 scb_tag = ahc_inb(ahc, SCB_TAG); 2144 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2145 if (pending_scb == NULL) 2146 continue; 2147 2148 pending_hscb = pending_scb->hscb; 2149 control = ahc_inb(ahc, SCB_CONTROL); 2150 control &= ~(ULTRAENB|MK_MESSAGE); 2151 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2152 ahc_outb(ahc, SCB_CONTROL, control); 2153 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2154 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2155 } 2156 ahc_outb(ahc, SCBPTR, saved_scbptr); 2157 2158 if (paused == 0) 2159 ahc_unpause(ahc); 2160 } 2161 2162 /**************************** Pathing Information *****************************/ 2163 static void 2164 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2165 { 2166 u_int saved_scsiid; 2167 role_t role; 2168 int our_id; 2169 2170 if (ahc_inb(ahc, SSTAT0) & TARGET) 2171 role = ROLE_TARGET; 2172 else 2173 role = ROLE_INITIATOR; 2174 2175 if (role == ROLE_TARGET 2176 && (ahc->features & AHC_MULTI_TID) != 0 2177 && (ahc_inb(ahc, SEQ_FLAGS) 2178 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2179 /* We were selected, so pull our id from TARGIDIN */ 2180 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2181 } else if ((ahc->features & AHC_ULTRA2) != 0) 2182 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2183 else 2184 our_id = ahc_inb(ahc, SCSIID) & OID; 2185 2186 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2187 ahc_compile_devinfo(devinfo, 2188 our_id, 2189 SCSIID_TARGET(ahc, saved_scsiid), 2190 ahc_inb(ahc, SAVED_LUN), 2191 SCSIID_CHANNEL(ahc, saved_scsiid), 2192 role); 2193 } 2194 2195 struct ahc_phase_table_entry* 2196 ahc_lookup_phase_entry(int phase) 2197 { 2198 struct ahc_phase_table_entry *entry; 2199 struct ahc_phase_table_entry *last_entry; 2200 2201 /* 2202 * num_phases doesn't include the default entry which 2203 * will be returned if the phase doesn't match. 2204 */ 2205 last_entry = &ahc_phase_table[num_phases]; 2206 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2207 if (phase == entry->phase) 2208 break; 2209 } 2210 return (entry); 2211 } 2212 2213 void 2214 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2215 u_int lun, char channel, role_t role) 2216 { 2217 devinfo->our_scsiid = our_id; 2218 devinfo->target = target; 2219 devinfo->lun = lun; 2220 devinfo->target_offset = target; 2221 devinfo->channel = channel; 2222 devinfo->role = role; 2223 if (channel == 'B') 2224 devinfo->target_offset += 8; 2225 devinfo->target_mask = (0x01 << devinfo->target_offset); 2226 } 2227 2228 void 2229 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2230 { 2231 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2232 devinfo->target, devinfo->lun); 2233 } 2234 2235 static void 2236 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2237 struct scb *scb) 2238 { 2239 role_t role; 2240 int our_id; 2241 2242 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2243 role = ROLE_INITIATOR; 2244 if ((scb->flags & SCB_TARGET_SCB) != 0) 2245 role = ROLE_TARGET; 2246 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2247 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2248 } 2249 2250 2251 /************************ Message Phase Processing ****************************/ 2252 static void 2253 ahc_assert_atn(struct ahc_softc *ahc) 2254 { 2255 u_int scsisigo; 2256 2257 scsisigo = ATNO; 2258 if ((ahc->features & AHC_DT) == 0) 2259 scsisigo |= ahc_inb(ahc, SCSISIGI); 2260 ahc_outb(ahc, SCSISIGO, scsisigo); 2261 } 2262 2263 /* 2264 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2265 * or enters the initial message out phase, we are interrupted. Fill our 2266 * outgoing message buffer with the appropriate message and beging handing 2267 * the message phase(s) manually. 2268 */ 2269 static void 2270 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2271 struct scb *scb) 2272 { 2273 /* 2274 * To facilitate adding multiple messages together, 2275 * each routine should increment the index and len 2276 * variables instead of setting them explicitly. 2277 */ 2278 ahc->msgout_index = 0; 2279 ahc->msgout_len = 0; 2280 2281 if ((scb->flags & SCB_DEVICE_RESET) == 0 2282 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2283 u_int identify_msg; 2284 2285 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2286 if ((scb->hscb->control & DISCENB) != 0) 2287 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2288 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2289 ahc->msgout_len++; 2290 2291 if ((scb->hscb->control & TAG_ENB) != 0) { 2292 ahc->msgout_buf[ahc->msgout_index++] = 2293 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2294 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2295 ahc->msgout_len += 2; 2296 } 2297 } 2298 2299 if (scb->flags & SCB_DEVICE_RESET) { 2300 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2301 ahc->msgout_len++; 2302 ahc_print_path(ahc, scb); 2303 printf("Bus Device Reset Message Sent\n"); 2304 /* 2305 * Clear our selection hardware in advance of 2306 * the busfree. We may have an entry in the waiting 2307 * Q for this target, and we don't want to go about 2308 * selecting while we handle the busfree and blow it 2309 * away. 2310 */ 2311 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2312 } else if ((scb->flags & SCB_ABORT) != 0) { 2313 if ((scb->hscb->control & TAG_ENB) != 0) 2314 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2315 else 2316 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2317 ahc->msgout_len++; 2318 ahc_print_path(ahc, scb); 2319 printf("Abort%s Message Sent\n", 2320 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2321 /* 2322 * Clear our selection hardware in advance of 2323 * the busfree. We may have an entry in the waiting 2324 * Q for this target, and we don't want to go about 2325 * selecting while we handle the busfree and blow it 2326 * away. 2327 */ 2328 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2329 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2330 ahc_build_transfer_msg(ahc, devinfo); 2331 } else { 2332 printf("ahc_intr: AWAITING_MSG for an SCB that " 2333 "does not have a waiting message\n"); 2334 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2335 devinfo->target_mask); 2336 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2337 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2338 ahc_inb(ahc, MSG_OUT), scb->flags); 2339 } 2340 2341 /* 2342 * Clear the MK_MESSAGE flag from the SCB so we aren't 2343 * asked to send this message again. 2344 */ 2345 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2346 scb->hscb->control &= ~MK_MESSAGE; 2347 ahc->msgout_index = 0; 2348 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2349 } 2350 2351 /* 2352 * Build an appropriate transfer negotiation message for the 2353 * currently active target. 2354 */ 2355 static void 2356 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2357 { 2358 /* 2359 * We need to initiate transfer negotiations. 2360 * If our current and goal settings are identical, 2361 * we want to renegotiate due to a check condition. 2362 */ 2363 struct ahc_initiator_tinfo *tinfo; 2364 struct ahc_tmode_tstate *tstate; 2365 struct ahc_syncrate *rate; 2366 int dowide; 2367 int dosync; 2368 int doppr; 2369 u_int period; 2370 u_int ppr_options; 2371 u_int offset; 2372 2373 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2374 devinfo->target, &tstate); 2375 /* 2376 * Filter our period based on the current connection. 2377 * If we can't perform DT transfers on this segment (not in LVD 2378 * mode for instance), then our decision to issue a PPR message 2379 * may change. 2380 */ 2381 period = tinfo->goal.period; 2382 ppr_options = tinfo->goal.ppr_options; 2383 /* Target initiated PPR is not allowed in the SCSI spec */ 2384 if (devinfo->role == ROLE_TARGET) 2385 ppr_options = 0; 2386 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2387 &ppr_options, devinfo->role); 2388 dowide = tinfo->curr.width != tinfo->goal.width; 2389 dosync = tinfo->curr.period != period; 2390 /* 2391 * Only use PPR if we have options that need it, even if the device 2392 * claims to support it. There might be an expander in the way 2393 * that doesn't. 2394 */ 2395 doppr = ppr_options != 0; 2396 2397 if (!dowide && !dosync && !doppr) { 2398 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2399 dosync = tinfo->goal.offset != 0; 2400 } 2401 2402 if (!dowide && !dosync && !doppr) { 2403 /* 2404 * Force async with a WDTR message if we have a wide bus, 2405 * or just issue an SDTR with a 0 offset. 2406 */ 2407 if ((ahc->features & AHC_WIDE) != 0) 2408 dowide = 1; 2409 else 2410 dosync = 1; 2411 2412 if (bootverbose) { 2413 ahc_print_devinfo(ahc, devinfo); 2414 printf("Ensuring async\n"); 2415 } 2416 } 2417 2418 /* Target initiated PPR is not allowed in the SCSI spec */ 2419 if (devinfo->role == ROLE_TARGET) 2420 doppr = 0; 2421 2422 /* 2423 * Both the PPR message and SDTR message require the 2424 * goal syncrate to be limited to what the target device 2425 * is capable of handling (based on whether an LVD->SE 2426 * expander is on the bus), so combine these two cases. 2427 * Regardless, guarantee that if we are using WDTR and SDTR 2428 * messages that WDTR comes first. 2429 */ 2430 if (doppr || (dosync && !dowide)) { 2431 2432 offset = tinfo->goal.offset; 2433 ahc_validate_offset(ahc, tinfo, rate, &offset, 2434 doppr ? tinfo->goal.width 2435 : tinfo->curr.width, 2436 devinfo->role); 2437 if (doppr) { 2438 ahc_construct_ppr(ahc, devinfo, period, offset, 2439 tinfo->goal.width, ppr_options); 2440 } else { 2441 ahc_construct_sdtr(ahc, devinfo, period, offset); 2442 } 2443 } else { 2444 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2445 } 2446 } 2447 2448 /* 2449 * Build a synchronous negotiation message in our message 2450 * buffer based on the input parameters. 2451 */ 2452 static void 2453 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2454 u_int period, u_int offset) 2455 { 2456 if (offset == 0) 2457 period = AHC_ASYNC_XFER_PERIOD; 2458 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2461 ahc->msgout_buf[ahc->msgout_index++] = period; 2462 ahc->msgout_buf[ahc->msgout_index++] = offset; 2463 ahc->msgout_len += 5; 2464 if (bootverbose) { 2465 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2466 ahc_name(ahc), devinfo->channel, devinfo->target, 2467 devinfo->lun, period, offset); 2468 } 2469 } 2470 2471 /* 2472 * Build a wide negotiation message in our message 2473 * buffer based on the input parameters. 2474 */ 2475 static void 2476 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2477 u_int bus_width) 2478 { 2479 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2482 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2483 ahc->msgout_len += 4; 2484 if (bootverbose) { 2485 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2486 ahc_name(ahc), devinfo->channel, devinfo->target, 2487 devinfo->lun, bus_width); 2488 } 2489 } 2490 2491 /* 2492 * Build a parallel protocol request message in our message 2493 * buffer based on the input parameters. 2494 */ 2495 static void 2496 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2497 u_int period, u_int offset, u_int bus_width, 2498 u_int ppr_options) 2499 { 2500 if (offset == 0) 2501 period = AHC_ASYNC_XFER_PERIOD; 2502 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2505 ahc->msgout_buf[ahc->msgout_index++] = period; 2506 ahc->msgout_buf[ahc->msgout_index++] = 0; 2507 ahc->msgout_buf[ahc->msgout_index++] = offset; 2508 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2509 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2510 ahc->msgout_len += 8; 2511 if (bootverbose) { 2512 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2513 "offset %x, ppr_options %x\n", ahc_name(ahc), 2514 devinfo->channel, devinfo->target, devinfo->lun, 2515 bus_width, period, offset, ppr_options); 2516 } 2517 } 2518 2519 /* 2520 * Clear any active message state. 2521 */ 2522 static void 2523 ahc_clear_msg_state(struct ahc_softc *ahc) 2524 { 2525 ahc->msgout_len = 0; 2526 ahc->msgin_index = 0; 2527 ahc->msg_type = MSG_TYPE_NONE; 2528 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2529 /* 2530 * The target didn't care to respond to our 2531 * message request, so clear ATN. 2532 */ 2533 ahc_outb(ahc, CLRSINT1, CLRATNO); 2534 } 2535 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2536 ahc_outb(ahc, SEQ_FLAGS2, 2537 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2538 } 2539 2540 static void 2541 ahc_handle_proto_violation(struct ahc_softc *ahc) 2542 { 2543 struct ahc_devinfo devinfo; 2544 struct scb *scb; 2545 u_int scbid; 2546 u_int seq_flags; 2547 u_int curphase; 2548 u_int lastphase; 2549 int found; 2550 2551 ahc_fetch_devinfo(ahc, &devinfo); 2552 scbid = ahc_inb(ahc, SCB_TAG); 2553 scb = ahc_lookup_scb(ahc, scbid); 2554 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2555 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2556 lastphase = ahc_inb(ahc, LASTPHASE); 2557 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2558 2559 /* 2560 * The reconnecting target either did not send an 2561 * identify message, or did, but we didn't find an SCB 2562 * to match. 2563 */ 2564 ahc_print_devinfo(ahc, &devinfo); 2565 printf("Target did not send an IDENTIFY message. " 2566 "LASTPHASE = 0x%x.\n", lastphase); 2567 scb = NULL; 2568 } else if (scb == NULL) { 2569 /* 2570 * We don't seem to have an SCB active for this 2571 * transaction. Print an error and reset the bus. 2572 */ 2573 ahc_print_devinfo(ahc, &devinfo); 2574 printf("No SCB found during protocol violation\n"); 2575 goto proto_violation_reset; 2576 } else { 2577 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2578 if ((seq_flags & NO_CDB_SENT) != 0) { 2579 ahc_print_path(ahc, scb); 2580 printf("No or incomplete CDB sent to device.\n"); 2581 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2582 /* 2583 * The target never bothered to provide status to 2584 * us prior to completing the command. Since we don't 2585 * know the disposition of this command, we must attempt 2586 * to abort it. Assert ATN and prepare to send an abort 2587 * message. 2588 */ 2589 ahc_print_path(ahc, scb); 2590 printf("Completed command without status.\n"); 2591 } else { 2592 ahc_print_path(ahc, scb); 2593 printf("Unknown protocol violation.\n"); 2594 ahc_dump_card_state(ahc); 2595 } 2596 } 2597 if ((lastphase & ~P_DATAIN_DT) == 0 2598 || lastphase == P_COMMAND) { 2599 proto_violation_reset: 2600 /* 2601 * Target either went directly to data/command 2602 * phase or didn't respond to our ATN. 2603 * The only safe thing to do is to blow 2604 * it away with a bus reset. 2605 */ 2606 found = ahc_reset_channel(ahc, 'A', TRUE); 2607 printf("%s: Issued Channel %c Bus Reset. " 2608 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2609 } else { 2610 /* 2611 * Leave the selection hardware off in case 2612 * this abort attempt will affect yet to 2613 * be sent commands. 2614 */ 2615 ahc_outb(ahc, SCSISEQ, 2616 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2617 ahc_assert_atn(ahc); 2618 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2619 if (scb == NULL) { 2620 ahc_print_devinfo(ahc, &devinfo); 2621 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2622 ahc->msgout_len = 1; 2623 ahc->msgout_index = 0; 2624 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2625 } else { 2626 ahc_print_path(ahc, scb); 2627 scb->flags |= SCB_ABORT; 2628 } 2629 printf("Protocol violation %s. Attempting to abort.\n", 2630 ahc_lookup_phase_entry(curphase)->phasemsg); 2631 } 2632 } 2633 2634 /* 2635 * Manual message loop handler. 2636 */ 2637 static void 2638 ahc_handle_message_phase(struct ahc_softc *ahc) 2639 { 2640 struct ahc_devinfo devinfo; 2641 u_int bus_phase; 2642 int end_session; 2643 2644 ahc_fetch_devinfo(ahc, &devinfo); 2645 end_session = FALSE; 2646 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2647 2648 reswitch: 2649 switch (ahc->msg_type) { 2650 case MSG_TYPE_INITIATOR_MSGOUT: 2651 { 2652 int lastbyte; 2653 int phasemis; 2654 int msgdone; 2655 2656 if (ahc->msgout_len == 0) 2657 panic("HOST_MSG_LOOP interrupt with no active message"); 2658 2659 #ifdef AHC_DEBUG 2660 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2661 ahc_print_devinfo(ahc, &devinfo); 2662 printf("INITIATOR_MSG_OUT"); 2663 } 2664 #endif 2665 phasemis = bus_phase != P_MESGOUT; 2666 if (phasemis) { 2667 #ifdef AHC_DEBUG 2668 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2669 printf(" PHASEMIS %s\n", 2670 ahc_lookup_phase_entry(bus_phase) 2671 ->phasemsg); 2672 } 2673 #endif 2674 if (bus_phase == P_MESGIN) { 2675 /* 2676 * Change gears and see if 2677 * this messages is of interest to 2678 * us or should be passed back to 2679 * the sequencer. 2680 */ 2681 ahc_outb(ahc, CLRSINT1, CLRATNO); 2682 ahc->send_msg_perror = FALSE; 2683 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2684 ahc->msgin_index = 0; 2685 goto reswitch; 2686 } 2687 end_session = TRUE; 2688 break; 2689 } 2690 2691 if (ahc->send_msg_perror) { 2692 ahc_outb(ahc, CLRSINT1, CLRATNO); 2693 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2694 #ifdef AHC_DEBUG 2695 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2696 printf(" byte 0x%x\n", ahc->send_msg_perror); 2697 #endif 2698 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2699 break; 2700 } 2701 2702 msgdone = ahc->msgout_index == ahc->msgout_len; 2703 if (msgdone) { 2704 /* 2705 * The target has requested a retry. 2706 * Re-assert ATN, reset our message index to 2707 * 0, and try again. 2708 */ 2709 ahc->msgout_index = 0; 2710 ahc_assert_atn(ahc); 2711 } 2712 2713 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2714 if (lastbyte) { 2715 /* Last byte is signified by dropping ATN */ 2716 ahc_outb(ahc, CLRSINT1, CLRATNO); 2717 } 2718 2719 /* 2720 * Clear our interrupt status and present 2721 * the next byte on the bus. 2722 */ 2723 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2724 #ifdef AHC_DEBUG 2725 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2726 printf(" byte 0x%x\n", 2727 ahc->msgout_buf[ahc->msgout_index]); 2728 #endif 2729 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2730 break; 2731 } 2732 case MSG_TYPE_INITIATOR_MSGIN: 2733 { 2734 int phasemis; 2735 int message_done; 2736 2737 #ifdef AHC_DEBUG 2738 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2739 ahc_print_devinfo(ahc, &devinfo); 2740 printf("INITIATOR_MSG_IN"); 2741 } 2742 #endif 2743 phasemis = bus_phase != P_MESGIN; 2744 if (phasemis) { 2745 #ifdef AHC_DEBUG 2746 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2747 printf(" PHASEMIS %s\n", 2748 ahc_lookup_phase_entry(bus_phase) 2749 ->phasemsg); 2750 } 2751 #endif 2752 ahc->msgin_index = 0; 2753 if (bus_phase == P_MESGOUT 2754 && (ahc->send_msg_perror == TRUE 2755 || (ahc->msgout_len != 0 2756 && ahc->msgout_index == 0))) { 2757 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2758 goto reswitch; 2759 } 2760 end_session = TRUE; 2761 break; 2762 } 2763 2764 /* Pull the byte in without acking it */ 2765 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2766 #ifdef AHC_DEBUG 2767 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2768 printf(" byte 0x%x\n", 2769 ahc->msgin_buf[ahc->msgin_index]); 2770 #endif 2771 2772 message_done = ahc_parse_msg(ahc, &devinfo); 2773 2774 if (message_done) { 2775 /* 2776 * Clear our incoming message buffer in case there 2777 * is another message following this one. 2778 */ 2779 ahc->msgin_index = 0; 2780 2781 /* 2782 * If this message illicited a response, 2783 * assert ATN so the target takes us to the 2784 * message out phase. 2785 */ 2786 if (ahc->msgout_len != 0) { 2787 #ifdef AHC_DEBUG 2788 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2789 ahc_print_devinfo(ahc, &devinfo); 2790 printf("Asserting ATN for response\n"); 2791 } 2792 #endif 2793 ahc_assert_atn(ahc); 2794 } 2795 } else 2796 ahc->msgin_index++; 2797 2798 if (message_done == MSGLOOP_TERMINATED) { 2799 end_session = TRUE; 2800 } else { 2801 /* Ack the byte */ 2802 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2803 ahc_inb(ahc, SCSIDATL); 2804 } 2805 break; 2806 } 2807 case MSG_TYPE_TARGET_MSGIN: 2808 { 2809 int msgdone; 2810 int msgout_request; 2811 2812 if (ahc->msgout_len == 0) 2813 panic("Target MSGIN with no active message"); 2814 2815 /* 2816 * If we interrupted a mesgout session, the initiator 2817 * will not know this until our first REQ. So, we 2818 * only honor mesgout requests after we've sent our 2819 * first byte. 2820 */ 2821 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2822 && ahc->msgout_index > 0) 2823 msgout_request = TRUE; 2824 else 2825 msgout_request = FALSE; 2826 2827 if (msgout_request) { 2828 2829 /* 2830 * Change gears and see if 2831 * this messages is of interest to 2832 * us or should be passed back to 2833 * the sequencer. 2834 */ 2835 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2836 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2837 ahc->msgin_index = 0; 2838 /* Dummy read to REQ for first byte */ 2839 ahc_inb(ahc, SCSIDATL); 2840 ahc_outb(ahc, SXFRCTL0, 2841 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2842 break; 2843 } 2844 2845 msgdone = ahc->msgout_index == ahc->msgout_len; 2846 if (msgdone) { 2847 ahc_outb(ahc, SXFRCTL0, 2848 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2849 end_session = TRUE; 2850 break; 2851 } 2852 2853 /* 2854 * Present the next byte on the bus. 2855 */ 2856 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2857 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2858 break; 2859 } 2860 case MSG_TYPE_TARGET_MSGOUT: 2861 { 2862 int lastbyte; 2863 int msgdone; 2864 2865 /* 2866 * The initiator signals that this is 2867 * the last byte by dropping ATN. 2868 */ 2869 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2870 2871 /* 2872 * Read the latched byte, but turn off SPIOEN first 2873 * so that we don't inadvertently cause a REQ for the 2874 * next byte. 2875 */ 2876 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2877 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2878 msgdone = ahc_parse_msg(ahc, &devinfo); 2879 if (msgdone == MSGLOOP_TERMINATED) { 2880 /* 2881 * The message is *really* done in that it caused 2882 * us to go to bus free. The sequencer has already 2883 * been reset at this point, so pull the ejection 2884 * handle. 2885 */ 2886 return; 2887 } 2888 2889 ahc->msgin_index++; 2890 2891 /* 2892 * XXX Read spec about initiator dropping ATN too soon 2893 * and use msgdone to detect it. 2894 */ 2895 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2896 ahc->msgin_index = 0; 2897 2898 /* 2899 * If this message illicited a response, transition 2900 * to the Message in phase and send it. 2901 */ 2902 if (ahc->msgout_len != 0) { 2903 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2904 ahc_outb(ahc, SXFRCTL0, 2905 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2906 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2907 ahc->msgin_index = 0; 2908 break; 2909 } 2910 } 2911 2912 if (lastbyte) 2913 end_session = TRUE; 2914 else { 2915 /* Ask for the next byte. */ 2916 ahc_outb(ahc, SXFRCTL0, 2917 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2918 } 2919 2920 break; 2921 } 2922 default: 2923 panic("Unknown REQINIT message type"); 2924 } 2925 2926 if (end_session) { 2927 ahc_clear_msg_state(ahc); 2928 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2929 } else 2930 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2931 } 2932 2933 /* 2934 * See if we sent a particular extended message to the target. 2935 * If "full" is true, return true only if the target saw the full 2936 * message. If "full" is false, return true if the target saw at 2937 * least the first byte of the message. 2938 */ 2939 static int 2940 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2941 { 2942 int found; 2943 u_int index; 2944 2945 found = FALSE; 2946 index = 0; 2947 2948 while (index < ahc->msgout_len) { 2949 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2950 u_int end_index; 2951 2952 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2953 if (ahc->msgout_buf[index+2] == msgval 2954 && type == AHCMSG_EXT) { 2955 2956 if (full) { 2957 if (ahc->msgout_index > end_index) 2958 found = TRUE; 2959 } else if (ahc->msgout_index > index) 2960 found = TRUE; 2961 } 2962 index = end_index; 2963 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2964 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2965 2966 /* Skip tag type and tag id or residue param*/ 2967 index += 2; 2968 } else { 2969 /* Single byte message */ 2970 if (type == AHCMSG_1B 2971 && ahc->msgout_buf[index] == msgval 2972 && ahc->msgout_index > index) 2973 found = TRUE; 2974 index++; 2975 } 2976 2977 if (found) 2978 break; 2979 } 2980 return (found); 2981 } 2982 2983 /* 2984 * Wait for a complete incoming message, parse it, and respond accordingly. 2985 */ 2986 static int 2987 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2988 { 2989 struct ahc_initiator_tinfo *tinfo; 2990 struct ahc_tmode_tstate *tstate; 2991 int reject; 2992 int done; 2993 int response; 2994 u_int targ_scsirate; 2995 2996 done = MSGLOOP_IN_PROG; 2997 response = FALSE; 2998 reject = FALSE; 2999 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3000 devinfo->target, &tstate); 3001 targ_scsirate = tinfo->scsirate; 3002 3003 /* 3004 * Parse as much of the message as is availible, 3005 * rejecting it if we don't support it. When 3006 * the entire message is availible and has been 3007 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3008 * that we have parsed an entire message. 3009 * 3010 * In the case of extended messages, we accept the length 3011 * byte outright and perform more checking once we know the 3012 * extended message type. 3013 */ 3014 switch (ahc->msgin_buf[0]) { 3015 case MSG_DISCONNECT: 3016 case MSG_SAVEDATAPOINTER: 3017 case MSG_CMDCOMPLETE: 3018 case MSG_RESTOREPOINTERS: 3019 case MSG_IGN_WIDE_RESIDUE: 3020 /* 3021 * End our message loop as these are messages 3022 * the sequencer handles on its own. 3023 */ 3024 done = MSGLOOP_TERMINATED; 3025 break; 3026 case MSG_MESSAGE_REJECT: 3027 response = ahc_handle_msg_reject(ahc, devinfo); 3028 /* FALLTHROUGH */ 3029 case MSG_NOOP: 3030 done = MSGLOOP_MSGCOMPLETE; 3031 break; 3032 case MSG_EXTENDED: 3033 { 3034 /* Wait for enough of the message to begin validation */ 3035 if (ahc->msgin_index < 2) 3036 break; 3037 switch (ahc->msgin_buf[2]) { 3038 case MSG_EXT_SDTR: 3039 { 3040 struct ahc_syncrate *syncrate; 3041 u_int period; 3042 u_int ppr_options; 3043 u_int offset; 3044 u_int saved_offset; 3045 3046 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3047 reject = TRUE; 3048 break; 3049 } 3050 3051 /* 3052 * Wait until we have both args before validating 3053 * and acting on this message. 3054 * 3055 * Add one to MSG_EXT_SDTR_LEN to account for 3056 * the extended message preamble. 3057 */ 3058 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3059 break; 3060 3061 period = ahc->msgin_buf[3]; 3062 ppr_options = 0; 3063 saved_offset = offset = ahc->msgin_buf[4]; 3064 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3065 &ppr_options, 3066 devinfo->role); 3067 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3068 targ_scsirate & WIDEXFER, 3069 devinfo->role); 3070 if (bootverbose) { 3071 printf("(%s:%c:%d:%d): Received " 3072 "SDTR period %x, offset %x\n\t" 3073 "Filtered to period %x, offset %x\n", 3074 ahc_name(ahc), devinfo->channel, 3075 devinfo->target, devinfo->lun, 3076 ahc->msgin_buf[3], saved_offset, 3077 period, offset); 3078 } 3079 ahc_set_syncrate(ahc, devinfo, 3080 syncrate, period, 3081 offset, ppr_options, 3082 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3083 /*paused*/TRUE); 3084 3085 /* 3086 * See if we initiated Sync Negotiation 3087 * and didn't have to fall down to async 3088 * transfers. 3089 */ 3090 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3091 /* We started it */ 3092 if (saved_offset != offset) { 3093 /* Went too low - force async */ 3094 reject = TRUE; 3095 } 3096 } else { 3097 /* 3098 * Send our own SDTR in reply 3099 */ 3100 if (bootverbose 3101 && devinfo->role == ROLE_INITIATOR) { 3102 printf("(%s:%c:%d:%d): Target " 3103 "Initiated SDTR\n", 3104 ahc_name(ahc), devinfo->channel, 3105 devinfo->target, devinfo->lun); 3106 } 3107 ahc->msgout_index = 0; 3108 ahc->msgout_len = 0; 3109 ahc_construct_sdtr(ahc, devinfo, 3110 period, offset); 3111 ahc->msgout_index = 0; 3112 response = TRUE; 3113 } 3114 done = MSGLOOP_MSGCOMPLETE; 3115 break; 3116 } 3117 case MSG_EXT_WDTR: 3118 { 3119 u_int bus_width; 3120 u_int saved_width; 3121 u_int sending_reply; 3122 3123 sending_reply = FALSE; 3124 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3125 reject = TRUE; 3126 break; 3127 } 3128 3129 /* 3130 * Wait until we have our arg before validating 3131 * and acting on this message. 3132 * 3133 * Add one to MSG_EXT_WDTR_LEN to account for 3134 * the extended message preamble. 3135 */ 3136 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3137 break; 3138 3139 bus_width = ahc->msgin_buf[3]; 3140 saved_width = bus_width; 3141 ahc_validate_width(ahc, tinfo, &bus_width, 3142 devinfo->role); 3143 if (bootverbose) { 3144 printf("(%s:%c:%d:%d): Received WDTR " 3145 "%x filtered to %x\n", 3146 ahc_name(ahc), devinfo->channel, 3147 devinfo->target, devinfo->lun, 3148 saved_width, bus_width); 3149 } 3150 3151 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3152 /* 3153 * Don't send a WDTR back to the 3154 * target, since we asked first. 3155 * If the width went higher than our 3156 * request, reject it. 3157 */ 3158 if (saved_width > bus_width) { 3159 reject = TRUE; 3160 printf("(%s:%c:%d:%d): requested %dBit " 3161 "transfers. Rejecting...\n", 3162 ahc_name(ahc), devinfo->channel, 3163 devinfo->target, devinfo->lun, 3164 8 * (0x01 << bus_width)); 3165 bus_width = 0; 3166 } 3167 } else { 3168 /* 3169 * Send our own WDTR in reply 3170 */ 3171 if (bootverbose 3172 && devinfo->role == ROLE_INITIATOR) { 3173 printf("(%s:%c:%d:%d): Target " 3174 "Initiated WDTR\n", 3175 ahc_name(ahc), devinfo->channel, 3176 devinfo->target, devinfo->lun); 3177 } 3178 ahc->msgout_index = 0; 3179 ahc->msgout_len = 0; 3180 ahc_construct_wdtr(ahc, devinfo, bus_width); 3181 ahc->msgout_index = 0; 3182 response = TRUE; 3183 sending_reply = TRUE; 3184 } 3185 ahc_set_width(ahc, devinfo, bus_width, 3186 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3187 /*paused*/TRUE); 3188 /* After a wide message, we are async */ 3189 ahc_set_syncrate(ahc, devinfo, 3190 /*syncrate*/NULL, /*period*/0, 3191 /*offset*/0, /*ppr_options*/0, 3192 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3193 if (sending_reply == FALSE && reject == FALSE) { 3194 3195 if (tinfo->goal.offset) { 3196 ahc->msgout_index = 0; 3197 ahc->msgout_len = 0; 3198 ahc_build_transfer_msg(ahc, devinfo); 3199 ahc->msgout_index = 0; 3200 response = TRUE; 3201 } 3202 } 3203 done = MSGLOOP_MSGCOMPLETE; 3204 break; 3205 } 3206 case MSG_EXT_PPR: 3207 { 3208 struct ahc_syncrate *syncrate; 3209 u_int period; 3210 u_int offset; 3211 u_int bus_width; 3212 u_int ppr_options; 3213 u_int saved_width; 3214 u_int saved_offset; 3215 u_int saved_ppr_options; 3216 3217 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3218 reject = TRUE; 3219 break; 3220 } 3221 3222 /* 3223 * Wait until we have all args before validating 3224 * and acting on this message. 3225 * 3226 * Add one to MSG_EXT_PPR_LEN to account for 3227 * the extended message preamble. 3228 */ 3229 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3230 break; 3231 3232 period = ahc->msgin_buf[3]; 3233 offset = ahc->msgin_buf[5]; 3234 bus_width = ahc->msgin_buf[6]; 3235 saved_width = bus_width; 3236 ppr_options = ahc->msgin_buf[7]; 3237 /* 3238 * According to the spec, a DT only 3239 * period factor with no DT option 3240 * set implies async. 3241 */ 3242 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3243 && period == 9) 3244 offset = 0; 3245 saved_ppr_options = ppr_options; 3246 saved_offset = offset; 3247 3248 /* 3249 * Mask out any options we don't support 3250 * on any controller. Transfer options are 3251 * only available if we are negotiating wide. 3252 */ 3253 ppr_options &= MSG_EXT_PPR_DT_REQ; 3254 if (bus_width == 0) 3255 ppr_options = 0; 3256 3257 ahc_validate_width(ahc, tinfo, &bus_width, 3258 devinfo->role); 3259 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3260 &ppr_options, 3261 devinfo->role); 3262 ahc_validate_offset(ahc, tinfo, syncrate, 3263 &offset, bus_width, 3264 devinfo->role); 3265 3266 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3267 /* 3268 * If we are unable to do any of the 3269 * requested options (we went too low), 3270 * then we'll have to reject the message. 3271 */ 3272 if (saved_width > bus_width 3273 || saved_offset != offset 3274 || saved_ppr_options != ppr_options) { 3275 reject = TRUE; 3276 period = 0; 3277 offset = 0; 3278 bus_width = 0; 3279 ppr_options = 0; 3280 syncrate = NULL; 3281 } 3282 } else { 3283 if (devinfo->role != ROLE_TARGET) 3284 printf("(%s:%c:%d:%d): Target " 3285 "Initiated PPR\n", 3286 ahc_name(ahc), devinfo->channel, 3287 devinfo->target, devinfo->lun); 3288 else 3289 printf("(%s:%c:%d:%d): Initiator " 3290 "Initiated PPR\n", 3291 ahc_name(ahc), devinfo->channel, 3292 devinfo->target, devinfo->lun); 3293 ahc->msgout_index = 0; 3294 ahc->msgout_len = 0; 3295 ahc_construct_ppr(ahc, devinfo, period, offset, 3296 bus_width, ppr_options); 3297 ahc->msgout_index = 0; 3298 response = TRUE; 3299 } 3300 if (bootverbose) { 3301 printf("(%s:%c:%d:%d): Received PPR width %x, " 3302 "period %x, offset %x,options %x\n" 3303 "\tFiltered to width %x, period %x, " 3304 "offset %x, options %x\n", 3305 ahc_name(ahc), devinfo->channel, 3306 devinfo->target, devinfo->lun, 3307 saved_width, ahc->msgin_buf[3], 3308 saved_offset, saved_ppr_options, 3309 bus_width, period, offset, ppr_options); 3310 } 3311 ahc_set_width(ahc, devinfo, bus_width, 3312 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3313 /*paused*/TRUE); 3314 ahc_set_syncrate(ahc, devinfo, 3315 syncrate, period, 3316 offset, ppr_options, 3317 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3318 /*paused*/TRUE); 3319 done = MSGLOOP_MSGCOMPLETE; 3320 break; 3321 } 3322 default: 3323 /* Unknown extended message. Reject it. */ 3324 reject = TRUE; 3325 break; 3326 } 3327 break; 3328 } 3329 #ifdef AHC_TARGET_MODE 3330 case MSG_BUS_DEV_RESET: 3331 ahc_handle_devreset(ahc, devinfo, 3332 CAM_BDR_SENT, 3333 "Bus Device Reset Received", 3334 /*verbose_level*/0); 3335 ahc_restart(ahc); 3336 done = MSGLOOP_TERMINATED; 3337 break; 3338 case MSG_ABORT_TAG: 3339 case MSG_ABORT: 3340 case MSG_CLEAR_QUEUE: 3341 { 3342 int tag; 3343 3344 /* Target mode messages */ 3345 if (devinfo->role != ROLE_TARGET) { 3346 reject = TRUE; 3347 break; 3348 } 3349 tag = SCB_LIST_NULL; 3350 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3351 tag = ahc_inb(ahc, INITIATOR_TAG); 3352 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3353 devinfo->lun, tag, ROLE_TARGET, 3354 CAM_REQ_ABORTED); 3355 3356 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3357 if (tstate != NULL) { 3358 struct ahc_tmode_lstate* lstate; 3359 3360 lstate = tstate->enabled_luns[devinfo->lun]; 3361 if (lstate != NULL) { 3362 ahc_queue_lstate_event(ahc, lstate, 3363 devinfo->our_scsiid, 3364 ahc->msgin_buf[0], 3365 /*arg*/tag); 3366 ahc_send_lstate_events(ahc, lstate); 3367 } 3368 } 3369 ahc_restart(ahc); 3370 done = MSGLOOP_TERMINATED; 3371 break; 3372 } 3373 #endif 3374 case MSG_TERM_IO_PROC: 3375 default: 3376 reject = TRUE; 3377 break; 3378 } 3379 3380 if (reject) { 3381 /* 3382 * Setup to reject the message. 3383 */ 3384 ahc->msgout_index = 0; 3385 ahc->msgout_len = 1; 3386 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3387 done = MSGLOOP_MSGCOMPLETE; 3388 response = TRUE; 3389 } 3390 3391 if (done != MSGLOOP_IN_PROG && !response) 3392 /* Clear the outgoing message buffer */ 3393 ahc->msgout_len = 0; 3394 3395 return (done); 3396 } 3397 3398 /* 3399 * Process a message reject message. 3400 */ 3401 static int 3402 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3403 { 3404 /* 3405 * What we care about here is if we had an 3406 * outstanding SDTR or WDTR message for this 3407 * target. If we did, this is a signal that 3408 * the target is refusing negotiation. 3409 */ 3410 struct scb *scb; 3411 struct ahc_initiator_tinfo *tinfo; 3412 struct ahc_tmode_tstate *tstate; 3413 u_int scb_index; 3414 u_int last_msg; 3415 int response = 0; 3416 3417 scb_index = ahc_inb(ahc, SCB_TAG); 3418 scb = ahc_lookup_scb(ahc, scb_index); 3419 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3420 devinfo->our_scsiid, 3421 devinfo->target, &tstate); 3422 /* Might be necessary */ 3423 last_msg = ahc_inb(ahc, LAST_MSG); 3424 3425 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3426 /* 3427 * Target does not support the PPR message. 3428 * Attempt to negotiate SPI-2 style. 3429 */ 3430 if (bootverbose) { 3431 printf("(%s:%c:%d:%d): PPR Rejected. " 3432 "Trying WDTR/SDTR\n", 3433 ahc_name(ahc), devinfo->channel, 3434 devinfo->target, devinfo->lun); 3435 } 3436 tinfo->goal.ppr_options = 0; 3437 tinfo->curr.transport_version = 2; 3438 tinfo->goal.transport_version = 2; 3439 ahc->msgout_index = 0; 3440 ahc->msgout_len = 0; 3441 ahc_build_transfer_msg(ahc, devinfo); 3442 ahc->msgout_index = 0; 3443 response = 1; 3444 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3445 3446 /* note 8bit xfers */ 3447 if (bootverbose) 3448 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3449 "8bit transfers\n", ahc_name(ahc), 3450 devinfo->channel, devinfo->target, devinfo->lun); 3451 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3452 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3453 /*paused*/TRUE); 3454 /* 3455 * No need to clear the sync rate. If the target 3456 * did not accept the command, our syncrate is 3457 * unaffected. If the target started the negotiation, 3458 * but rejected our response, we already cleared the 3459 * sync rate before sending our WDTR. 3460 */ 3461 if (tinfo->goal.offset != tinfo->curr.offset) { 3462 3463 /* Start the sync negotiation */ 3464 ahc->msgout_index = 0; 3465 ahc->msgout_len = 0; 3466 ahc_build_transfer_msg(ahc, devinfo); 3467 ahc->msgout_index = 0; 3468 response = 1; 3469 } 3470 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3471 /* note asynch xfers and clear flag */ 3472 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3473 /*offset*/0, /*ppr_options*/0, 3474 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3475 /*paused*/TRUE); 3476 if (bootverbose) 3477 printf("(%s:%c:%d:%d): refuses synchronous negotiation." 3478 " Using asynchronous transfers\n", 3479 ahc_name(ahc), devinfo->channel, 3480 devinfo->target, devinfo->lun); 3481 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3482 int tag_type; 3483 int mask; 3484 3485 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3486 3487 if (tag_type == MSG_SIMPLE_TASK) { 3488 if (bootverbose) 3489 printf("(%s:%c:%d:%d): refuses tagged commands." 3490 " Performing non-tagged I/O\n", 3491 ahc_name(ahc), devinfo->channel, 3492 devinfo->target, devinfo->lun); 3493 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3494 mask = ~0x23; 3495 } else { 3496 if (bootverbose) 3497 printf("(%s:%c:%d:%d): refuses %s tagged " 3498 "commands. Performing simple queue " 3499 "tagged I/O only\n", 3500 ahc_name(ahc), devinfo->channel, 3501 devinfo->target, devinfo->lun, 3502 tag_type == MSG_ORDERED_TASK 3503 ? "ordered" : "head of queue"); 3504 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3505 mask = ~0x03; 3506 } 3507 3508 /* 3509 * Resend the identify for this CCB as the target 3510 * may believe that the selection is invalid otherwise. 3511 */ 3512 ahc_outb(ahc, SCB_CONTROL, 3513 ahc_inb(ahc, SCB_CONTROL) & mask); 3514 scb->hscb->control &= mask; 3515 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3516 /*type*/MSG_SIMPLE_TASK); 3517 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3518 ahc_assert_atn(ahc); 3519 3520 /* 3521 * This transaction is now at the head of 3522 * the untagged queue for this target. 3523 */ 3524 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3525 struct scb_tailq *untagged_q; 3526 3527 untagged_q = 3528 &(ahc->untagged_queues[devinfo->target_offset]); 3529 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3530 scb->flags |= SCB_UNTAGGEDQ; 3531 } 3532 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3533 scb->hscb->tag); 3534 3535 /* 3536 * Requeue all tagged commands for this target 3537 * currently in our posession so they can be 3538 * converted to untagged commands. 3539 */ 3540 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3541 SCB_GET_CHANNEL(ahc, scb), 3542 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3543 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3544 SEARCH_COMPLETE); 3545 } else { 3546 /* 3547 * Otherwise, we ignore it. 3548 */ 3549 if (bootverbose) 3550 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3551 ahc_name(ahc), devinfo->channel, devinfo->target, 3552 last_msg); 3553 } 3554 return (response); 3555 } 3556 3557 /* 3558 * Process an ingnore wide residue message. 3559 */ 3560 static void 3561 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3562 { 3563 u_int scb_index; 3564 struct scb *scb; 3565 3566 scb_index = ahc_inb(ahc, SCB_TAG); 3567 scb = ahc_lookup_scb(ahc, scb_index); 3568 /* 3569 * XXX Actually check data direction in the sequencer? 3570 * Perhaps add datadir to some spare bits in the hscb? 3571 */ 3572 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3573 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3574 /* 3575 * Ignore the message if we haven't 3576 * seen an appropriate data phase yet. 3577 */ 3578 } else { 3579 /* 3580 * If the residual occurred on the last 3581 * transfer and the transfer request was 3582 * expected to end on an odd count, do 3583 * nothing. Otherwise, subtract a byte 3584 * and update the residual count accordingly. 3585 */ 3586 uint32_t sgptr; 3587 3588 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3589 if ((sgptr & SG_LIST_NULL) != 0 3590 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3591 /* 3592 * If the residual occurred on the last 3593 * transfer and the transfer request was 3594 * expected to end on an odd count, do 3595 * nothing. 3596 */ 3597 } else { 3598 struct ahc_dma_seg *sg; 3599 uint32_t data_cnt; 3600 uint32_t data_addr; 3601 uint32_t sglen; 3602 3603 /* Pull in the rest of the sgptr */ 3604 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3605 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3606 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3607 sgptr &= SG_PTR_MASK; 3608 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3609 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3610 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3611 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3612 3613 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3614 | (ahc_inb(ahc, SHADDR + 2) << 16) 3615 | (ahc_inb(ahc, SHADDR + 1) << 8) 3616 | (ahc_inb(ahc, SHADDR)); 3617 3618 data_cnt += 1; 3619 data_addr -= 1; 3620 3621 sg = ahc_sg_bus_to_virt(scb, sgptr); 3622 /* 3623 * The residual sg ptr points to the next S/G 3624 * to load so we must go back one. 3625 */ 3626 sg--; 3627 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3628 if (sg != scb->sg_list 3629 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3630 3631 sg--; 3632 sglen = ahc_le32toh(sg->len); 3633 /* 3634 * Preserve High Address and SG_LIST bits 3635 * while setting the count to 1. 3636 */ 3637 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3638 data_addr = ahc_le32toh(sg->addr) 3639 + (sglen & AHC_SG_LEN_MASK) - 1; 3640 3641 /* 3642 * Increment sg so it points to the 3643 * "next" sg. 3644 */ 3645 sg++; 3646 sgptr = ahc_sg_virt_to_bus(scb, sg); 3647 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3648 sgptr >> 24); 3649 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3650 sgptr >> 16); 3651 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3652 sgptr >> 8); 3653 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3654 } 3655 3656 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3657 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3658 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3659 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3660 } 3661 } 3662 } 3663 3664 3665 /* 3666 * Reinitialize the data pointers for the active transfer 3667 * based on its current residual. 3668 */ 3669 static void 3670 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3671 { 3672 struct scb *scb; 3673 struct ahc_dma_seg *sg; 3674 u_int scb_index; 3675 uint32_t sgptr; 3676 uint32_t resid; 3677 uint32_t dataptr; 3678 3679 scb_index = ahc_inb(ahc, SCB_TAG); 3680 scb = ahc_lookup_scb(ahc, scb_index); 3681 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3682 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3683 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3684 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3685 3686 sgptr &= SG_PTR_MASK; 3687 sg = ahc_sg_bus_to_virt(scb, sgptr); 3688 3689 /* The residual sg_ptr always points to the next sg */ 3690 sg--; 3691 3692 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3693 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3694 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3695 3696 dataptr = ahc_le32toh(sg->addr) 3697 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3698 - resid; 3699 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3700 u_int dscommand1; 3701 3702 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3703 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3704 ahc_outb(ahc, HADDR, 3705 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3706 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3707 } 3708 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3709 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3710 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3711 ahc_outb(ahc, HADDR, dataptr); 3712 ahc_outb(ahc, HCNT + 2, resid >> 16); 3713 ahc_outb(ahc, HCNT + 1, resid >> 8); 3714 ahc_outb(ahc, HCNT, resid); 3715 if ((ahc->features & AHC_ULTRA2) == 0) { 3716 ahc_outb(ahc, STCNT + 2, resid >> 16); 3717 ahc_outb(ahc, STCNT + 1, resid >> 8); 3718 ahc_outb(ahc, STCNT, resid); 3719 } 3720 } 3721 3722 /* 3723 * Handle the effects of issuing a bus device reset message. 3724 */ 3725 static void 3726 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3727 cam_status status, char *message, int verbose_level) 3728 { 3729 #ifdef AHC_TARGET_MODE 3730 struct ahc_tmode_tstate* tstate; 3731 u_int lun; 3732 #endif 3733 int found; 3734 3735 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3736 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3737 status); 3738 3739 #ifdef AHC_TARGET_MODE 3740 /* 3741 * Send an immediate notify ccb to all target mord peripheral 3742 * drivers affected by this action. 3743 */ 3744 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3745 if (tstate != NULL) { 3746 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3747 struct ahc_tmode_lstate* lstate; 3748 3749 lstate = tstate->enabled_luns[lun]; 3750 if (lstate == NULL) 3751 continue; 3752 3753 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3754 MSG_BUS_DEV_RESET, /*arg*/0); 3755 ahc_send_lstate_events(ahc, lstate); 3756 } 3757 } 3758 #endif 3759 3760 /* 3761 * Go back to async/narrow transfers and renegotiate. 3762 */ 3763 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3764 AHC_TRANS_CUR, /*paused*/TRUE); 3765 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3766 /*period*/0, /*offset*/0, /*ppr_options*/0, 3767 AHC_TRANS_CUR, /*paused*/TRUE); 3768 3769 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3770 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3771 3772 if (message != NULL 3773 && (verbose_level <= bootverbose)) 3774 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3775 message, devinfo->channel, devinfo->target, found); 3776 } 3777 3778 #ifdef AHC_TARGET_MODE 3779 static void 3780 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3781 struct scb *scb) 3782 { 3783 3784 /* 3785 * To facilitate adding multiple messages together, 3786 * each routine should increment the index and len 3787 * variables instead of setting them explicitly. 3788 */ 3789 ahc->msgout_index = 0; 3790 ahc->msgout_len = 0; 3791 3792 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3793 ahc_build_transfer_msg(ahc, devinfo); 3794 else 3795 panic("ahc_intr: AWAITING target message with no message"); 3796 3797 ahc->msgout_index = 0; 3798 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3799 } 3800 #endif 3801 3802 int 3803 ahc_softc_init(struct ahc_softc *ahc) 3804 { 3805 3806 /* The IRQMS bit is only valid on VL and EISA chips */ 3807 if ((ahc->chip & AHC_PCI) == 0) 3808 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3809 else 3810 ahc->unpause = 0; 3811 ahc->pause = ahc->unpause | PAUSE; 3812 /* XXX The shared scb data stuff should be deprecated */ 3813 if (ahc->scb_data == NULL) { 3814 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3815 M_DEVBUF, M_NOWAIT); 3816 if (ahc->scb_data == NULL) 3817 return (ENOMEM); 3818 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3819 } 3820 3821 return (0); 3822 } 3823 3824 void 3825 ahc_softc_insert(struct ahc_softc *ahc) 3826 { 3827 struct ahc_softc *list_ahc; 3828 3829 #if AHC_PCI_CONFIG > 0 3830 /* 3831 * Second Function PCI devices need to inherit some 3832 * settings from function 0. 3833 */ 3834 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3835 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3836 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3837 ahc_dev_softc_t list_pci; 3838 ahc_dev_softc_t pci; 3839 3840 list_pci = list_ahc->dev_softc; 3841 pci = ahc->dev_softc; 3842 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3843 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3844 struct ahc_softc *master; 3845 struct ahc_softc *slave; 3846 3847 if (ahc_get_pci_function(list_pci) == 0) { 3848 master = list_ahc; 3849 slave = ahc; 3850 } else { 3851 master = ahc; 3852 slave = list_ahc; 3853 } 3854 slave->flags &= ~AHC_BIOS_ENABLED; 3855 slave->flags |= 3856 master->flags & AHC_BIOS_ENABLED; 3857 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3858 slave->flags |= 3859 master->flags & AHC_PRIMARY_CHANNEL; 3860 break; 3861 } 3862 } 3863 } 3864 #endif 3865 3866 /* 3867 * Insertion sort into our list of softcs. 3868 */ 3869 list_ahc = TAILQ_FIRST(&ahc_tailq); 3870 while (list_ahc != NULL 3871 && ahc_softc_comp(list_ahc, ahc) <= 0) 3872 list_ahc = TAILQ_NEXT(list_ahc, links); 3873 if (list_ahc != NULL) 3874 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3875 else 3876 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3877 ahc->init_level++; 3878 } 3879 3880 /* 3881 * Verify that the passed in softc pointer is for a 3882 * controller that is still configured. 3883 */ 3884 struct ahc_softc * 3885 ahc_find_softc(struct ahc_softc *ahc) 3886 { 3887 struct ahc_softc *list_ahc; 3888 3889 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3890 if (list_ahc == ahc) 3891 return (ahc); 3892 } 3893 return (NULL); 3894 } 3895 3896 void 3897 ahc_set_unit(struct ahc_softc *ahc, int unit) 3898 { 3899 ahc->unit = unit; 3900 } 3901 3902 void 3903 ahc_set_name(struct ahc_softc *ahc, char *name) 3904 { 3905 if (ahc->name != NULL) 3906 free(ahc->name, M_DEVBUF); 3907 ahc->name = name; 3908 } 3909 3910 void 3911 ahc_free(struct ahc_softc *ahc) 3912 { 3913 int i; 3914 3915 ahc_fini_scbdata(ahc); 3916 switch (ahc->init_level) { 3917 default: 3918 case 2: 3919 ahc_shutdown(ahc); 3920 TAILQ_REMOVE(&ahc_tailq, ahc, links); 3921 /* FALLTHROUGH */ 3922 case 1: 3923 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3924 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3925 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3926 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3927 break; 3928 case 0: 3929 break; 3930 } 3931 3932 ahc_platform_free(ahc); 3933 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3934 struct ahc_tmode_tstate *tstate; 3935 3936 tstate = ahc->enabled_targets[i]; 3937 if (tstate != NULL) { 3938 #if AHC_TARGET_MODE 3939 int j; 3940 3941 for (j = 0; j < AHC_NUM_LUNS; j++) { 3942 struct ahc_tmode_lstate *lstate; 3943 3944 lstate = tstate->enabled_luns[j]; 3945 if (lstate != NULL) { 3946 /*xpt_free_path(lstate->path);*/ 3947 free(lstate, M_DEVBUF); 3948 } 3949 } 3950 #endif 3951 free(tstate, M_DEVBUF); 3952 } 3953 } 3954 #if AHC_TARGET_MODE 3955 if (ahc->black_hole != NULL) { 3956 /*xpt_free_path(ahc->black_hole->path);*/ 3957 free(ahc->black_hole, M_DEVBUF); 3958 } 3959 #endif 3960 if (ahc->name != NULL) 3961 free(ahc->name, M_DEVBUF); 3962 if (ahc->seep_config != NULL) 3963 free(ahc->seep_config, M_DEVBUF); 3964 #ifndef __FreeBSD__ 3965 free(ahc, M_DEVBUF); 3966 #endif 3967 return; 3968 } 3969 3970 void 3971 ahc_shutdown(void *arg) 3972 { 3973 struct ahc_softc *ahc; 3974 int i; 3975 3976 ahc = (struct ahc_softc *)arg; 3977 3978 /* This will reset most registers to 0, but not all */ 3979 ahc_reset(ahc); 3980 ahc_outb(ahc, SCSISEQ, 0); 3981 ahc_outb(ahc, SXFRCTL0, 0); 3982 ahc_outb(ahc, DSPCISTATUS, 0); 3983 3984 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3985 ahc_outb(ahc, i, 0); 3986 } 3987 3988 /* 3989 * Reset the controller and record some information about it 3990 * that is only available just after a reset. 3991 */ 3992 int 3993 ahc_reset(struct ahc_softc *ahc) 3994 { 3995 u_int sblkctl; 3996 u_int sxfrctl1_a, sxfrctl1_b; 3997 int wait; 3998 3999 /* 4000 * Preserve the value of the SXFRCTL1 register for all channels. 4001 * It contains settings that affect termination and we don't want 4002 * to disturb the integrity of the bus. 4003 */ 4004 ahc_pause(ahc); 4005 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4006 /* 4007 * The chip has not been initialized since 4008 * PCI/EISA/VLB bus reset. Don't trust 4009 * "left over BIOS data". 4010 */ 4011 ahc->flags |= AHC_NO_BIOS_INIT; 4012 } 4013 sxfrctl1_b = 0; 4014 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4015 u_int sblkctl; 4016 4017 /* 4018 * Save channel B's settings in case this chip 4019 * is setup for TWIN channel operation. 4020 */ 4021 sblkctl = ahc_inb(ahc, SBLKCTL); 4022 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4023 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4024 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4025 } 4026 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4027 4028 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4029 4030 /* 4031 * Ensure that the reset has finished. We delay 1000us 4032 * prior to reading the register to make sure the chip 4033 * has sufficiently completed its reset to handle register 4034 * accesses. 4035 */ 4036 wait = 1000; 4037 do { 4038 ahc_delay(1000); 4039 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4040 4041 if (wait == 0) { 4042 printf("%s: WARNING - Failed chip reset! " 4043 "Trying to initialize anyway.\n", ahc_name(ahc)); 4044 } 4045 ahc_outb(ahc, HCNTRL, ahc->pause); 4046 4047 /* Determine channel configuration */ 4048 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4049 /* No Twin Channel PCI cards */ 4050 if ((ahc->chip & AHC_PCI) != 0) 4051 sblkctl &= ~SELBUSB; 4052 switch (sblkctl) { 4053 case 0: 4054 /* Single Narrow Channel */ 4055 break; 4056 case 2: 4057 /* Wide Channel */ 4058 ahc->features |= AHC_WIDE; 4059 break; 4060 case 8: 4061 /* Twin Channel */ 4062 ahc->features |= AHC_TWIN; 4063 break; 4064 default: 4065 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4066 return(-1); 4067 } 4068 4069 /* 4070 * Reload sxfrctl1. 4071 * 4072 * We must always initialize STPWEN to 1 before we 4073 * restore the saved values. STPWEN is initialized 4074 * to a tri-state condition which can only be cleared 4075 * by turning it on. 4076 */ 4077 if ((ahc->features & AHC_TWIN) != 0) { 4078 u_int sblkctl; 4079 4080 sblkctl = ahc_inb(ahc, SBLKCTL); 4081 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4082 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4083 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4084 } 4085 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4086 4087 #ifdef AHC_DUMP_SEQ 4088 if (ahc->init_level == 0) 4089 ahc_dumpseq(ahc); 4090 #endif 4091 4092 return (0); 4093 } 4094 4095 /* 4096 * Determine the number of SCBs available on the controller 4097 */ 4098 int 4099 ahc_probe_scbs(struct ahc_softc *ahc) { 4100 int i; 4101 4102 for (i = 0; i < AHC_SCB_MAX; i++) { 4103 4104 ahc_outb(ahc, SCBPTR, i); 4105 ahc_outb(ahc, SCB_BASE, i); 4106 if (ahc_inb(ahc, SCB_BASE) != i) 4107 break; 4108 ahc_outb(ahc, SCBPTR, 0); 4109 if (ahc_inb(ahc, SCB_BASE) != 0) 4110 break; 4111 } 4112 return (i); 4113 } 4114 4115 #if 0 4116 static void 4117 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4118 { 4119 bus_addr_t *baddr; 4120 4121 baddr = (bus_addr_t *)arg; 4122 *baddr = segs->ds_addr; 4123 } 4124 #endif 4125 4126 static void 4127 ahc_build_free_scb_list(struct ahc_softc *ahc) 4128 { 4129 int scbsize; 4130 int i; 4131 4132 scbsize = 32; 4133 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4134 scbsize = 64; 4135 4136 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4137 int j; 4138 4139 ahc_outb(ahc, SCBPTR, i); 4140 4141 /* 4142 * Touch all SCB bytes to avoid parity errors 4143 * should one of our debugging routines read 4144 * an otherwise uninitiatlized byte. 4145 */ 4146 for (j = 0; j < scbsize; j++) 4147 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4148 4149 /* Clear the control byte. */ 4150 ahc_outb(ahc, SCB_CONTROL, 0); 4151 4152 /* Set the next pointer */ 4153 if ((ahc->flags & AHC_PAGESCBS) != 0) 4154 ahc_outb(ahc, SCB_NEXT, i+1); 4155 else 4156 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4157 4158 /* Make the tag number, SCSIID, and lun invalid */ 4159 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4160 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4161 ahc_outb(ahc, SCB_LUN, 0xFF); 4162 } 4163 4164 /* Make sure that the last SCB terminates the free list */ 4165 ahc_outb(ahc, SCBPTR, i-1); 4166 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4167 } 4168 4169 static int 4170 ahc_init_scbdata(struct ahc_softc *ahc) 4171 { 4172 struct scb_data *scb_data; 4173 4174 scb_data = ahc->scb_data; 4175 SLIST_INIT(&scb_data->free_scbs); 4176 SLIST_INIT(&scb_data->sg_maps); 4177 4178 /* Allocate SCB resources */ 4179 scb_data->scbarray = 4180 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4181 M_DEVBUF, M_NOWAIT); 4182 if (scb_data->scbarray == NULL) 4183 return (ENOMEM); 4184 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4185 4186 /* Determine the number of hardware SCBs and initialize them */ 4187 4188 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4189 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4190 /* SCB 0 heads the free list */ 4191 ahc_outb(ahc, FREE_SCBH, 0); 4192 } else { 4193 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4194 } 4195 4196 if (ahc->scb_data->maxhscbs == 0) { 4197 printf("%s: No SCB space found\n", ahc_name(ahc)); 4198 return (ENXIO); 4199 } 4200 4201 ahc_build_free_scb_list(ahc); 4202 4203 /* 4204 * Create our DMA tags. These tags define the kinds of device 4205 * accessible memory allocations and memory mappings we will 4206 * need to perform during normal operation. 4207 * 4208 * Unless we need to further restrict the allocation, we rely 4209 * on the restrictions of the parent dmat, hence the common 4210 * use of MAXADDR and MAXSIZE. 4211 */ 4212 4213 if (ahc_createdmamem(ahc->parent_dmat, 4214 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4215 &scb_data->hscb_dmamap, 4216 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4217 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4218 "hardware SCB structures") < 0) 4219 goto error_exit; 4220 4221 scb_data->init_level++; 4222 4223 if (ahc_createdmamem(ahc->parent_dmat, 4224 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), ahc->sc_dmaflags, 4225 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4226 &scb_data->sense_busaddr, &scb_data->sense_seg, 4227 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4228 goto error_exit; 4229 4230 scb_data->init_level++; 4231 4232 /* Perform initial CCB allocation */ 4233 memset(scb_data->hscbs, 0, 4234 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4235 ahc_alloc_scbs(ahc); 4236 4237 if (scb_data->numscbs == 0) { 4238 printf("%s: ahc_init_scbdata - " 4239 "Unable to allocate initial scbs\n", 4240 ahc_name(ahc)); 4241 goto error_exit; 4242 } 4243 4244 /* 4245 * Tell the sequencer which SCB will be the next one it receives. 4246 */ 4247 ahc->next_queued_scb = ahc_get_scb(ahc); 4248 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4249 4250 /* 4251 * Note that we were successfull 4252 */ 4253 return (0); 4254 4255 error_exit: 4256 4257 return (ENOMEM); 4258 } 4259 4260 static void 4261 ahc_fini_scbdata(struct ahc_softc *ahc) 4262 { 4263 struct scb_data *scb_data; 4264 4265 scb_data = ahc->scb_data; 4266 if (scb_data == NULL) 4267 return; 4268 4269 switch (scb_data->init_level) { 4270 default: 4271 case 3: 4272 { 4273 struct sg_map_node *sg_map; 4274 4275 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4276 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4277 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4278 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4279 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4280 free(sg_map, M_DEVBUF); 4281 } 4282 } 4283 /*FALLTHROUGH*/ 4284 case 2: 4285 ahc_freedmamem(ahc->parent_dmat, 4286 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 4287 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4288 &scb_data->sense_seg, scb_data->sense_nseg); 4289 /*FALLTHROUGH*/ 4290 case 1: 4291 ahc_freedmamem(ahc->parent_dmat, 4292 AHC_SCB_MAX * sizeof(struct hardware_scb), 4293 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4294 &scb_data->hscb_seg, scb_data->hscb_nseg); 4295 /*FALLTHROUGH*/ 4296 } 4297 if (scb_data->scbarray != NULL) 4298 free(scb_data->scbarray, M_DEVBUF); 4299 } 4300 4301 void 4302 ahc_alloc_scbs(struct ahc_softc *ahc) 4303 { 4304 struct scb_data *scb_data; 4305 struct scb *next_scb; 4306 struct sg_map_node *sg_map; 4307 bus_addr_t physaddr; 4308 struct ahc_dma_seg *segs; 4309 int newcount; 4310 int i; 4311 4312 scb_data = ahc->scb_data; 4313 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4314 /* Can't allocate any more */ 4315 return; 4316 4317 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4318 4319 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4320 4321 if (sg_map == NULL) 4322 return; 4323 4324 /* Allocate S/G space for the next batch of SCBS */ 4325 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4326 &sg_map->sg_dmamap, 4327 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4328 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4329 "SG space") < 0) { 4330 free(sg_map, M_DEVBUF); 4331 return; 4332 } 4333 4334 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4335 4336 segs = sg_map->sg_vaddr; 4337 physaddr = sg_map->sg_physaddr; 4338 4339 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4340 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4341 for (i = 0; i < newcount; i++) { 4342 struct scb_platform_data *pdata; 4343 int error; 4344 4345 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4346 M_DEVBUF, M_NOWAIT); 4347 if (pdata == NULL) 4348 break; 4349 next_scb->platform_data = pdata; 4350 next_scb->sg_map = sg_map; 4351 next_scb->sg_list = segs; 4352 /* 4353 * The sequencer always starts with the second entry. 4354 * The first entry is embedded in the scb. 4355 */ 4356 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4357 next_scb->ahc_softc = ahc; 4358 next_scb->flags = SCB_FREE; 4359 4360 error = bus_dmamap_create(ahc->parent_dmat, 4361 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXBSIZE, 0, 4362 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 4363 &next_scb->dmamap); 4364 if (error != 0) 4365 break; 4366 4367 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4368 next_scb->hscb->tag = ahc->scb_data->numscbs; 4369 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4370 next_scb, links.sle); 4371 segs += AHC_NSEG; 4372 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4373 next_scb++; 4374 ahc->scb_data->numscbs++; 4375 } 4376 } 4377 4378 void 4379 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4380 { 4381 int len; 4382 4383 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4384 buf += len; 4385 if ((ahc->features & AHC_TWIN) != 0) 4386 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4387 "B SCSI Id=%d, primary %c, ", 4388 ahc->our_id, ahc->our_id_b, 4389 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4390 else { 4391 const char *speed; 4392 const char *type; 4393 4394 speed = ""; 4395 if ((ahc->features & AHC_ULTRA) != 0) { 4396 speed = "Ultra "; 4397 } else if ((ahc->features & AHC_DT) != 0) { 4398 speed = "Ultra160 "; 4399 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4400 speed = "Ultra2 "; 4401 } 4402 if ((ahc->features & AHC_WIDE) != 0) { 4403 type = "Wide"; 4404 } else { 4405 type = "Single"; 4406 } 4407 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4408 speed, type, ahc->channel, ahc->our_id); 4409 } 4410 buf += len; 4411 4412 if ((ahc->flags & AHC_PAGESCBS) != 0) 4413 sprintf(buf, "%d/%d SCBs", 4414 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4415 else 4416 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4417 } 4418 4419 /* 4420 * Start the board, ready for normal operation 4421 */ 4422 int 4423 ahc_init(struct ahc_softc *ahc) 4424 { 4425 int max_targ; 4426 int i; 4427 int term; 4428 u_int scsi_conf; 4429 u_int scsiseq_template; 4430 u_int ultraenb; 4431 u_int discenable; 4432 u_int tagenable; 4433 size_t driver_data_size; 4434 uint32_t physaddr; 4435 4436 #ifdef AHC_DEBUG 4437 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4438 ahc->flags |= AHC_SEQUENCER_DEBUG; 4439 #endif 4440 4441 #ifdef AHC_PRINT_SRAM 4442 printf("Scratch Ram:"); 4443 for (i = 0x20; i < 0x5f; i++) { 4444 if (((i % 8) == 0) && (i != 0)) { 4445 printf ("\n "); 4446 } 4447 printf (" 0x%x", ahc_inb(ahc, i)); 4448 } 4449 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4450 for (i = 0x70; i < 0x7f; i++) { 4451 if (((i % 8) == 0) && (i != 0)) { 4452 printf ("\n "); 4453 } 4454 printf (" 0x%x", ahc_inb(ahc, i)); 4455 } 4456 } 4457 printf ("\n"); 4458 /* 4459 * Reading uninitialized scratch ram may 4460 * generate parity errors. 4461 */ 4462 ahc_outb(ahc, CLRINT, CLRPARERR); 4463 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4464 #endif 4465 max_targ = 15; 4466 4467 /* 4468 * Assume we have a board at this stage and it has been reset. 4469 */ 4470 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4471 ahc->our_id = ahc->our_id_b = 7; 4472 4473 /* 4474 * Default to allowing initiator operations. 4475 */ 4476 ahc->flags |= AHC_INITIATORROLE; 4477 4478 /* 4479 * Only allow target mode features if this unit has them enabled. 4480 */ 4481 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4482 ahc->features &= ~AHC_TARGETMODE; 4483 4484 /* 4485 * DMA tag for our command fifos and other data in system memory 4486 * the card's sequencer must be able to access. For initiator 4487 * roles, we need to allocate space for the qinfifo and qoutfifo. 4488 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4489 * When providing for the target mode role, we must additionally 4490 * provide space for the incoming target command fifo and an extra 4491 * byte to deal with a dma bug in some chip versions. 4492 */ 4493 driver_data_size = 2 * 256 * sizeof(uint8_t); 4494 if ((ahc->features & AHC_TARGETMODE) != 0) 4495 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4496 + /*DMA WideOdd Bug Buffer*/1; 4497 4498 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4499 ahc->sc_dmaflags, 4500 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4501 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4502 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4503 return (ENOMEM); 4504 4505 ahc->init_level++; 4506 4507 if ((ahc->features & AHC_TARGETMODE) != 0) { 4508 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4509 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4510 ahc->dma_bug_buf = ahc->shared_data_busaddr 4511 + driver_data_size - 1; 4512 /* All target command blocks start out invalid. */ 4513 for (i = 0; i < AHC_TMODE_CMDS; i++) 4514 ahc->targetcmds[i].cmd_valid = 0; 4515 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4516 ahc->tqinfifonext = 1; 4517 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4518 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4519 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4520 } 4521 ahc->qinfifo = &ahc->qoutfifo[256]; 4522 4523 ahc->init_level++; 4524 4525 /* Allocate SCB data now that buffer_dmat is initialized */ 4526 if (ahc->scb_data->maxhscbs == 0) 4527 if (ahc_init_scbdata(ahc) != 0) 4528 return (ENOMEM); 4529 4530 if (bootverbose) 4531 printf("%s: found %d SCBs\n", ahc_name(ahc), 4532 ahc->scb_data->maxhscbs); 4533 4534 /* 4535 * Allocate a tstate to house information for our 4536 * initiator presence on the bus as well as the user 4537 * data for any target mode initiator. 4538 */ 4539 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4540 printf("%s: unable to allocate ahc_tmode_tstate. " 4541 "Failing attach\n", ahc_name(ahc)); 4542 return (ENOMEM); 4543 } 4544 4545 if ((ahc->features & AHC_TWIN) != 0) { 4546 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4547 printf("%s: unable to allocate ahc_tmode_tstate. " 4548 "Failing attach\n", ahc_name(ahc)); 4549 return (ENOMEM); 4550 } 4551 } 4552 4553 ahc_outb(ahc, SEQ_FLAGS, 0); 4554 ahc_outb(ahc, SEQ_FLAGS2, 0); 4555 4556 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4557 ahc->flags |= AHC_PAGESCBS; 4558 } else { 4559 ahc->flags &= ~AHC_PAGESCBS; 4560 } 4561 4562 #ifdef AHC_DEBUG 4563 if (ahc_debug & AHC_SHOW_MISC) { 4564 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 4565 "ahc_dma %d bytes\n", 4566 ahc_name(ahc), 4567 sizeof(struct hardware_scb), 4568 sizeof(struct scb), 4569 sizeof(struct ahc_dma_seg)); 4570 } 4571 #endif /* AHC_DEBUG */ 4572 4573 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4574 if (ahc->features & AHC_TWIN) { 4575 4576 /* 4577 * The device is gated to channel B after a chip reset, 4578 * so set those values first 4579 */ 4580 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4581 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4582 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4583 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4584 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4585 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4586 if ((ahc->features & AHC_ULTRA2) != 0) 4587 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4588 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4589 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4590 4591 if ((scsi_conf & RESET_SCSI) != 0 4592 && (ahc->flags & AHC_INITIATORROLE) != 0) 4593 ahc->flags |= AHC_RESET_BUS_B; 4594 4595 /* Select Channel A */ 4596 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4597 } 4598 4599 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4600 if ((ahc->features & AHC_ULTRA2) != 0) 4601 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4602 else 4603 ahc_outb(ahc, SCSIID, ahc->our_id); 4604 scsi_conf = ahc_inb(ahc, SCSICONF); 4605 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4606 |term|ahc->seltime 4607 |ENSTIMER|ACTNEGEN); 4608 if ((ahc->features & AHC_ULTRA2) != 0) 4609 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4610 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4611 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4612 4613 if ((scsi_conf & RESET_SCSI) != 0 4614 && (ahc->flags & AHC_INITIATORROLE) != 0) 4615 ahc->flags |= AHC_RESET_BUS_A; 4616 4617 /* 4618 * Look at the information that board initialization or 4619 * the board bios has left us. 4620 */ 4621 ultraenb = 0; 4622 tagenable = ALL_TARGETS_MASK; 4623 4624 /* Grab the disconnection disable table and invert it for our needs */ 4625 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4626 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4627 "device parameters\n", ahc_name(ahc)); 4628 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4629 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4630 discenable = ALL_TARGETS_MASK; 4631 if ((ahc->features & AHC_ULTRA) != 0) 4632 ultraenb = ALL_TARGETS_MASK; 4633 } else { 4634 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4635 | ahc_inb(ahc, DISC_DSB)); 4636 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4637 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4638 | ahc_inb(ahc, ULTRA_ENB); 4639 } 4640 4641 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4642 max_targ = 7; 4643 4644 for (i = 0; i <= max_targ; i++) { 4645 struct ahc_initiator_tinfo *tinfo; 4646 struct ahc_tmode_tstate *tstate; 4647 u_int our_id; 4648 u_int target_id; 4649 char channel; 4650 4651 channel = 'A'; 4652 our_id = ahc->our_id; 4653 target_id = i; 4654 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4655 channel = 'B'; 4656 our_id = ahc->our_id_b; 4657 target_id = i % 8; 4658 } 4659 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4660 target_id, &tstate); 4661 /* Default to async narrow across the board */ 4662 memset(tinfo, 0, sizeof(*tinfo)); 4663 if (ahc->flags & AHC_USEDEFAULTS) { 4664 if ((ahc->features & AHC_WIDE) != 0) 4665 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4666 4667 /* 4668 * These will be truncated when we determine the 4669 * connection type we have with the target. 4670 */ 4671 tinfo->user.period = ahc_syncrates->period; 4672 tinfo->user.offset = ~0; 4673 } else { 4674 u_int scsirate; 4675 uint16_t mask; 4676 4677 /* Take the settings leftover in scratch RAM. */ 4678 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4679 mask = (0x01 << i); 4680 if ((ahc->features & AHC_ULTRA2) != 0) { 4681 u_int offset; 4682 u_int maxsync; 4683 4684 if ((scsirate & SOFS) == 0x0F) { 4685 /* 4686 * Haven't negotiated yet, 4687 * so the format is different. 4688 */ 4689 scsirate = (scsirate & SXFR) >> 4 4690 | (ultraenb & mask) 4691 ? 0x08 : 0x0 4692 | (scsirate & WIDEXFER); 4693 offset = MAX_OFFSET_ULTRA2; 4694 } else 4695 offset = ahc_inb(ahc, TARG_OFFSET + i); 4696 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4697 /* Set to the lowest sync rate, 5MHz */ 4698 scsirate |= 0x1c; 4699 maxsync = AHC_SYNCRATE_ULTRA2; 4700 if ((ahc->features & AHC_DT) != 0) 4701 maxsync = AHC_SYNCRATE_DT; 4702 tinfo->user.period = 4703 ahc_find_period(ahc, scsirate, maxsync); 4704 if (offset == 0) 4705 tinfo->user.period = 0; 4706 else 4707 tinfo->user.offset = ~0; 4708 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4709 && (ahc->features & AHC_DT) != 0) 4710 tinfo->user.ppr_options = 4711 MSG_EXT_PPR_DT_REQ; 4712 } else if ((scsirate & SOFS) != 0) { 4713 if ((scsirate & SXFR) == 0x40 4714 && (ultraenb & mask) != 0) { 4715 /* Treat 10MHz as a non-ultra speed */ 4716 scsirate &= ~SXFR; 4717 ultraenb &= ~mask; 4718 } 4719 tinfo->user.period = 4720 ahc_find_period(ahc, scsirate, 4721 (ultraenb & mask) 4722 ? AHC_SYNCRATE_ULTRA 4723 : AHC_SYNCRATE_FAST); 4724 if (tinfo->user.period != 0) 4725 tinfo->user.offset = ~0; 4726 } 4727 if (tinfo->user.period == 0) 4728 tinfo->user.offset = 0; 4729 if ((scsirate & WIDEXFER) != 0 4730 && (ahc->features & AHC_WIDE) != 0) 4731 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4732 tinfo->user.protocol_version = 4; 4733 if ((ahc->features & AHC_DT) != 0) 4734 tinfo->user.transport_version = 3; 4735 else 4736 tinfo->user.transport_version = 2; 4737 tinfo->goal.protocol_version = 2; 4738 tinfo->goal.transport_version = 2; 4739 tinfo->curr.protocol_version = 2; 4740 tinfo->curr.transport_version = 2; 4741 } 4742 tstate->ultraenb = 0; 4743 tstate->discenable = discenable; 4744 } 4745 ahc->user_discenable = discenable; 4746 ahc->user_tagenable = tagenable; 4747 4748 /* There are no untagged SCBs active yet. */ 4749 for (i = 0; i < 16; i++) { 4750 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4751 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4752 int lun; 4753 4754 /* 4755 * The SCB based BTT allows an entry per 4756 * target and lun pair. 4757 */ 4758 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4759 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4760 } 4761 } 4762 4763 /* All of our queues are empty */ 4764 for (i = 0; i < 256; i++) 4765 ahc->qoutfifo[i] = SCB_LIST_NULL; 4766 4767 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4768 4769 for (i = 0; i < 256; i++) 4770 ahc->qinfifo[i] = SCB_LIST_NULL; 4771 4772 if ((ahc->features & AHC_MULTI_TID) != 0) { 4773 ahc_outb(ahc, TARGID, 0); 4774 ahc_outb(ahc, TARGID + 1, 0); 4775 } 4776 4777 /* 4778 * Tell the sequencer where it can find our arrays in memory. 4779 */ 4780 physaddr = ahc->scb_data->hscb_busaddr; 4781 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4782 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4783 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4784 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4785 4786 physaddr = ahc->shared_data_busaddr; 4787 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4788 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4789 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4790 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4791 4792 /* 4793 * Initialize the group code to command length table. 4794 * This overrides the values in TARG_SCSIRATE, so only 4795 * setup the table after we have processed that information. 4796 */ 4797 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4798 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4799 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4800 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4801 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4802 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4803 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4804 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4805 4806 /* Tell the sequencer of our initial queue positions */ 4807 ahc_outb(ahc, KERNEL_QINPOS, 0); 4808 ahc_outb(ahc, QINPOS, 0); 4809 ahc_outb(ahc, QOUTPOS, 0); 4810 4811 /* 4812 * Use the built in queue management registers 4813 * if they are available. 4814 */ 4815 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4816 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4817 ahc_outb(ahc, SDSCB_QOFF, 0); 4818 ahc_outb(ahc, SNSCB_QOFF, 0); 4819 ahc_outb(ahc, HNSCB_QOFF, 0); 4820 } 4821 4822 4823 /* We don't have any waiting selections */ 4824 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4825 4826 /* Our disconnection list is empty too */ 4827 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4828 4829 /* Message out buffer starts empty */ 4830 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4831 4832 /* 4833 * Setup the allowed SCSI Sequences based on operational mode. 4834 * If we are a target, we'll enalbe select in operations once 4835 * we've had a lun enabled. 4836 */ 4837 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4838 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4839 scsiseq_template |= ENRSELI; 4840 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4841 4842 /* 4843 * Load the Sequencer program and Enable the adapter 4844 * in "fast" mode. 4845 */ 4846 if (bootverbose) 4847 printf("%s: Downloading Sequencer Program...", 4848 ahc_name(ahc)); 4849 4850 ahc_loadseq(ahc); 4851 4852 if ((ahc->features & AHC_ULTRA2) != 0) { 4853 int wait; 4854 4855 /* 4856 * Wait for up to 500ms for our transceivers 4857 * to settle. If the adapter does not have 4858 * a cable attached, the tranceivers may 4859 * never settle, so don't complain if we 4860 * fail here. 4861 */ 4862 ahc_pause(ahc); 4863 for (wait = 5000; 4864 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4865 wait--) 4866 ahc_delay(100); 4867 ahc_unpause(ahc); 4868 } 4869 4870 /* We have to wait until after any system dumps... */ 4871 ahc->shutdown_hook = shutdownhook_establish(ahc_shutdown, ahc); 4872 4873 return (0); 4874 } 4875 4876 void 4877 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4878 { 4879 u_int hcntrl; 4880 4881 hcntrl = ahc_inb(ahc, HCNTRL); 4882 hcntrl &= ~INTEN; 4883 ahc->pause &= ~INTEN; 4884 ahc->unpause &= ~INTEN; 4885 if (enable) { 4886 hcntrl |= INTEN; 4887 ahc->pause |= INTEN; 4888 ahc->unpause |= INTEN; 4889 } 4890 ahc_outb(ahc, HCNTRL, hcntrl); 4891 } 4892 4893 /* 4894 * Ensure that the card is paused in a location 4895 * outside of all critical sections and that all 4896 * pending work is completed prior to returning. 4897 * This routine should only be called from outside 4898 * an interrupt context. 4899 */ 4900 void 4901 ahc_pause_and_flushwork(struct ahc_softc *ahc) 4902 { 4903 int intstat; 4904 int maxloops; 4905 int paused; 4906 4907 maxloops = 1000; 4908 ahc->flags |= AHC_ALL_INTERRUPTS; 4909 intstat = 0; 4910 paused = FALSE; 4911 do { 4912 if (paused) 4913 ahc_unpause(ahc); 4914 ahc_intr(ahc); 4915 ahc_pause(ahc); 4916 paused = TRUE; 4917 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 4918 ahc_clear_critical_section(ahc); 4919 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4920 break; 4921 } while (--maxloops 4922 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0 4923 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)))); 4924 if (maxloops == 0) { 4925 printf("Infinite interrupt loop, INTSTAT = %x", 4926 ahc_inb(ahc, INTSTAT)); 4927 } 4928 ahc_platform_flushwork(ahc); 4929 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4930 } 4931 4932 int 4933 ahc_suspend(struct ahc_softc *ahc) 4934 { 4935 uint8_t *ptr; 4936 int i; 4937 4938 ahc_pause_and_flushwork(ahc); 4939 4940 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4941 return (EBUSY); 4942 4943 #if AHC_TARGET_MODE 4944 /* 4945 * XXX What about ATIOs that have not yet been serviced? 4946 * Perhaps we should just refuse to be suspended if we 4947 * are acting in a target role. 4948 */ 4949 if (ahc->pending_device != NULL) 4950 return (EBUSY); 4951 #endif 4952 4953 /* Save volatile registers */ 4954 if ((ahc->features & AHC_TWIN) != 0) { 4955 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4956 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4957 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4958 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4959 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4960 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4961 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4962 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4963 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4964 } 4965 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4966 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4967 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4968 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4969 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4970 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4971 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4972 4973 if ((ahc->chip & AHC_PCI) != 0) { 4974 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4975 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4976 } 4977 4978 if ((ahc->features & AHC_DT) != 0) { 4979 u_int sfunct; 4980 4981 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4982 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4983 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4984 ahc_outb(ahc, SFUNCT, sfunct); 4985 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4986 } 4987 4988 if ((ahc->features & AHC_MULTI_FUNC) != 0) 4989 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 4990 4991 if ((ahc->features & AHC_ULTRA2) != 0) 4992 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 4993 4994 ptr = ahc->suspend_state.scratch_ram; 4995 for (i = 0; i < 64; i++) 4996 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 4997 4998 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4999 for (i = 0; i < 16; i++) 5000 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 5001 } 5002 5003 ptr = ahc->suspend_state.btt; 5004 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5005 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5006 int j; 5007 5008 for (j = 0;j < AHC_NUM_LUNS; j++) { 5009 u_int tcl; 5010 5011 tcl = BUILD_TCL(i << 4, j); 5012 *ptr = ahc_index_busy_tcl(ahc, tcl); 5013 } 5014 } 5015 } 5016 ahc_shutdown(ahc); 5017 return (0); 5018 } 5019 5020 int 5021 ahc_resume(struct ahc_softc *ahc) 5022 { 5023 uint8_t *ptr; 5024 int i; 5025 5026 ahc_reset(ahc); 5027 5028 ahc_build_free_scb_list(ahc); 5029 5030 /* Restore volatile registers */ 5031 if ((ahc->features & AHC_TWIN) != 0) { 5032 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5033 ahc_outb(ahc, SCSIID, ahc->our_id); 5034 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 5035 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 5036 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 5037 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 5038 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 5039 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 5040 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 5041 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5042 } 5043 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 5044 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 5045 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 5046 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 5047 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 5048 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 5049 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 5050 if ((ahc->features & AHC_ULTRA2) != 0) 5051 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5052 else 5053 ahc_outb(ahc, SCSIID, ahc->our_id); 5054 5055 if ((ahc->chip & AHC_PCI) != 0) { 5056 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 5057 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 5058 } 5059 5060 if ((ahc->features & AHC_DT) != 0) { 5061 u_int sfunct; 5062 5063 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 5064 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 5065 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 5066 ahc_outb(ahc, SFUNCT, sfunct); 5067 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 5068 } 5069 5070 if ((ahc->features & AHC_MULTI_FUNC) != 0) 5071 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 5072 5073 if ((ahc->features & AHC_ULTRA2) != 0) 5074 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 5075 5076 ptr = ahc->suspend_state.scratch_ram; 5077 for (i = 0; i < 64; i++) 5078 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 5079 5080 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5081 for (i = 0; i < 16; i++) 5082 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 5083 } 5084 5085 ptr = ahc->suspend_state.btt; 5086 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5087 for (i = 0;i < AHC_NUM_TARGETS; i++) { 5088 int j; 5089 5090 for (j = 0;j < AHC_NUM_LUNS; j++) { 5091 u_int tcl; 5092 5093 tcl = BUILD_TCL(i << 4, j); 5094 ahc_busy_tcl(ahc, tcl, *ptr); 5095 } 5096 } 5097 } 5098 return (0); 5099 } 5100 5101 /************************** Busy Target Table *********************************/ 5102 /* 5103 * Return the untagged transaction id for a given target/channel lun. 5104 * Optionally, clear the entry. 5105 */ 5106 u_int 5107 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5108 { 5109 u_int scbid; 5110 u_int target_offset; 5111 5112 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5113 u_int saved_scbptr; 5114 5115 saved_scbptr = ahc_inb(ahc, SCBPTR); 5116 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5117 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5118 ahc_outb(ahc, SCBPTR, saved_scbptr); 5119 } else { 5120 target_offset = TCL_TARGET_OFFSET(tcl); 5121 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5122 } 5123 5124 return (scbid); 5125 } 5126 5127 void 5128 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5129 { 5130 u_int target_offset; 5131 5132 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5133 u_int saved_scbptr; 5134 5135 saved_scbptr = ahc_inb(ahc, SCBPTR); 5136 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5137 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5138 ahc_outb(ahc, SCBPTR, saved_scbptr); 5139 } else { 5140 target_offset = TCL_TARGET_OFFSET(tcl); 5141 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5142 } 5143 } 5144 5145 void 5146 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5147 { 5148 u_int target_offset; 5149 5150 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5151 u_int saved_scbptr; 5152 5153 saved_scbptr = ahc_inb(ahc, SCBPTR); 5154 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5155 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5156 ahc_outb(ahc, SCBPTR, saved_scbptr); 5157 } else { 5158 target_offset = TCL_TARGET_OFFSET(tcl); 5159 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5160 } 5161 } 5162 5163 /************************** SCB and SCB queue management **********************/ 5164 int 5165 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5166 char channel, int lun, u_int tag, role_t role) 5167 { 5168 int targ = SCB_GET_TARGET(ahc, scb); 5169 char chan = SCB_GET_CHANNEL(ahc, scb); 5170 int slun = SCB_GET_LUN(scb); 5171 int match; 5172 5173 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5174 if (match != 0) 5175 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5176 if (match != 0) 5177 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5178 if (match != 0) { 5179 #if 0 5180 #if AHC_TARGET_MODE 5181 int group; 5182 5183 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5184 if (role == ROLE_INITIATOR) { 5185 match = (group != XPT_FC_GROUP_TMODE) 5186 && ((tag == scb->hscb->tag) 5187 || (tag == SCB_LIST_NULL)); 5188 } else if (role == ROLE_TARGET) { 5189 match = (group == XPT_FC_GROUP_TMODE) 5190 && ((tag == scb->io_ctx->csio.tag_id) 5191 || (tag == SCB_LIST_NULL)); 5192 } 5193 #else /* !AHC_TARGET_MODE */ 5194 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5195 #endif /* AHC_TARGET_MODE */ 5196 #endif 5197 } 5198 5199 return match; 5200 } 5201 5202 void 5203 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5204 { 5205 int target; 5206 char channel; 5207 int lun; 5208 5209 target = SCB_GET_TARGET(ahc, scb); 5210 lun = SCB_GET_LUN(scb); 5211 channel = SCB_GET_CHANNEL(ahc, scb); 5212 5213 ahc_search_qinfifo(ahc, target, channel, lun, 5214 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5215 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5216 5217 ahc_platform_freeze_devq(ahc, scb); 5218 } 5219 5220 void 5221 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5222 { 5223 struct scb *prev_scb; 5224 5225 prev_scb = NULL; 5226 if (ahc_qinfifo_count(ahc) != 0) { 5227 u_int prev_tag; 5228 uint8_t prev_pos; 5229 5230 prev_pos = ahc->qinfifonext - 1; 5231 prev_tag = ahc->qinfifo[prev_pos]; 5232 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5233 } 5234 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5235 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5236 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5237 } else { 5238 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5239 } 5240 } 5241 5242 static void 5243 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5244 struct scb *scb) 5245 { 5246 if (prev_scb == NULL) { 5247 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5248 } else { 5249 prev_scb->hscb->next = scb->hscb->tag; 5250 ahc_sync_scb(ahc, prev_scb, 5251 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5252 } 5253 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5254 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5255 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5256 } 5257 5258 static int 5259 ahc_qinfifo_count(struct ahc_softc *ahc) 5260 { 5261 uint8_t qinpos; 5262 uint8_t diff; 5263 5264 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5265 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5266 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5267 } else 5268 qinpos = ahc_inb(ahc, QINPOS); 5269 diff = ahc->qinfifonext - qinpos; 5270 return (diff); 5271 } 5272 5273 int 5274 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5275 int lun, u_int tag, role_t role, uint32_t status, 5276 ahc_search_action action) 5277 { 5278 struct scb *scb; 5279 struct scb *prev_scb; 5280 uint8_t qinstart; 5281 uint8_t qinpos; 5282 uint8_t qintail; 5283 uint8_t next; 5284 uint8_t prev; 5285 uint8_t curscbptr; 5286 int found; 5287 int have_qregs; 5288 5289 qintail = ahc->qinfifonext; 5290 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5291 if (have_qregs) { 5292 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5293 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5294 } else 5295 qinstart = ahc_inb(ahc, QINPOS); 5296 qinpos = qinstart; 5297 found = 0; 5298 prev_scb = NULL; 5299 5300 if (action == SEARCH_COMPLETE) { 5301 /* 5302 * Don't attempt to run any queued untagged transactions 5303 * until we are done with the abort process. 5304 */ 5305 ahc_freeze_untagged_queues(ahc); 5306 } 5307 5308 /* 5309 * Start with an empty queue. Entries that are not chosen 5310 * for removal will be re-added to the queue as we go. 5311 */ 5312 ahc->qinfifonext = qinpos; 5313 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5314 5315 while (qinpos != qintail) { 5316 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5317 if (scb == NULL) { 5318 printf("qinpos = %d, SCB index = %d\n", 5319 qinpos, ahc->qinfifo[qinpos]); 5320 panic("Loop 1\n"); 5321 } 5322 5323 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5324 /* 5325 * We found an scb that needs to be acted on. 5326 */ 5327 found++; 5328 switch (action) { 5329 case SEARCH_COMPLETE: 5330 { 5331 cam_status ostat; 5332 cam_status cstat; 5333 5334 ostat = ahc_get_transaction_status(scb); 5335 if (ostat == CAM_REQ_INPROG) 5336 ahc_set_transaction_status(scb, status); 5337 cstat = ahc_get_transaction_status(scb); 5338 if (cstat != CAM_REQ_CMP) 5339 ahc_freeze_scb(scb); 5340 if ((scb->flags & SCB_ACTIVE) == 0) 5341 printf("Inactive SCB in qinfifo\n"); 5342 ahc_done(ahc, scb); 5343 5344 /* FALLTHROUGH */ 5345 } 5346 case SEARCH_REMOVE: 5347 break; 5348 case SEARCH_COUNT: 5349 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5350 prev_scb = scb; 5351 break; 5352 } 5353 } else { 5354 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5355 prev_scb = scb; 5356 } 5357 qinpos++; 5358 } 5359 5360 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5361 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5362 } else { 5363 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5364 } 5365 5366 if (action != SEARCH_COUNT 5367 && (found != 0) 5368 && (qinstart != ahc->qinfifonext)) { 5369 /* 5370 * The sequencer may be in the process of dmaing 5371 * down the SCB at the beginning of the queue. 5372 * This could be problematic if either the first, 5373 * or the second SCB is removed from the queue 5374 * (the first SCB includes a pointer to the "next" 5375 * SCB to dma). If we have removed any entries, swap 5376 * the first element in the queue with the next HSCB 5377 * so the sequencer will notice that NEXT_QUEUED_SCB 5378 * has changed during its dma attempt and will retry 5379 * the DMA. 5380 */ 5381 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5382 5383 if (scb == NULL) { 5384 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5385 found, qinstart, ahc->qinfifonext); 5386 panic("First/Second Qinfifo fixup\n"); 5387 } 5388 /* 5389 * ahc_swap_with_next_hscb forces our next pointer to 5390 * point to the reserved SCB for future commands. Save 5391 * and restore our original next pointer to maintain 5392 * queue integrity. 5393 */ 5394 next = scb->hscb->next; 5395 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5396 ahc_swap_with_next_hscb(ahc, scb); 5397 scb->hscb->next = next; 5398 ahc->qinfifo[qinstart] = scb->hscb->tag; 5399 5400 /* Tell the card about the new head of the qinfifo. */ 5401 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5402 5403 /* Fixup the tail "next" pointer. */ 5404 qintail = ahc->qinfifonext - 1; 5405 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5406 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5407 } 5408 5409 /* 5410 * Search waiting for selection list. 5411 */ 5412 curscbptr = ahc_inb(ahc, SCBPTR); 5413 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5414 prev = SCB_LIST_NULL; 5415 5416 while (next != SCB_LIST_NULL) { 5417 uint8_t scb_index; 5418 5419 ahc_outb(ahc, SCBPTR, next); 5420 scb_index = ahc_inb(ahc, SCB_TAG); 5421 if (scb_index >= ahc->scb_data->numscbs) { 5422 printf("Waiting List inconsistency. " 5423 "SCB index == %d, yet numscbs == %d.", 5424 scb_index, ahc->scb_data->numscbs); 5425 ahc_dump_card_state(ahc); 5426 panic("for safety"); 5427 } 5428 scb = ahc_lookup_scb(ahc, scb_index); 5429 if (scb == NULL) { 5430 printf("scb_index = %d, next = %d\n", 5431 scb_index, next); 5432 panic("Waiting List traversal\n"); 5433 } 5434 if (ahc_match_scb(ahc, scb, target, channel, 5435 lun, SCB_LIST_NULL, role)) { 5436 /* 5437 * We found an scb that needs to be acted on. 5438 */ 5439 found++; 5440 switch (action) { 5441 case SEARCH_COMPLETE: 5442 { 5443 cam_status ostat; 5444 cam_status cstat; 5445 5446 ostat = ahc_get_transaction_status(scb); 5447 if (ostat == CAM_REQ_INPROG) 5448 ahc_set_transaction_status(scb, status); 5449 cstat = ahc_get_transaction_status(scb); 5450 if (cstat != CAM_REQ_CMP) 5451 ahc_freeze_scb(scb); 5452 if ((scb->flags & SCB_ACTIVE) == 0) 5453 printf("Inactive SCB in Waiting List\n"); 5454 ahc_done(ahc, scb); 5455 /* FALLTHROUGH */ 5456 } 5457 case SEARCH_REMOVE: 5458 next = ahc_rem_wscb(ahc, next, prev); 5459 break; 5460 case SEARCH_COUNT: 5461 prev = next; 5462 next = ahc_inb(ahc, SCB_NEXT); 5463 break; 5464 } 5465 } else { 5466 5467 prev = next; 5468 next = ahc_inb(ahc, SCB_NEXT); 5469 } 5470 } 5471 ahc_outb(ahc, SCBPTR, curscbptr); 5472 5473 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5474 channel, lun, status, action); 5475 5476 if (action == SEARCH_COMPLETE) 5477 ahc_release_untagged_queues(ahc); 5478 return (found); 5479 } 5480 5481 int 5482 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsipi_xfer *xs, /*ahc_io_ctx_t ctx,*/ 5483 int target, char channel, int lun, uint32_t status, 5484 ahc_search_action action) 5485 { 5486 struct scb *scb; 5487 int maxtarget; 5488 int found; 5489 int i; 5490 5491 if (action == SEARCH_COMPLETE) { 5492 /* 5493 * Don't attempt to run any queued untagged transactions 5494 * until we are done with the abort process. 5495 */ 5496 ahc_freeze_untagged_queues(ahc); 5497 } 5498 5499 found = 0; 5500 i = 0; 5501 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5502 5503 maxtarget = 16; 5504 if (target != CAM_TARGET_WILDCARD) { 5505 5506 i = target; 5507 if (channel == 'B') 5508 i += 8; 5509 maxtarget = i + 1; 5510 } 5511 } else { 5512 maxtarget = 0; 5513 } 5514 5515 for (; i < maxtarget; i++) { 5516 struct scb_tailq *untagged_q; 5517 struct scb *next_scb; 5518 5519 untagged_q = &(ahc->untagged_queues[i]); 5520 next_scb = TAILQ_FIRST(untagged_q); 5521 while (next_scb != NULL) { 5522 5523 scb = next_scb; 5524 next_scb = TAILQ_NEXT(scb, links.tqe); 5525 5526 /* 5527 * The head of the list may be the currently 5528 * active untagged command for a device. 5529 * We're only searching for commands that 5530 * have not been started. A transaction 5531 * marked active but still in the qinfifo 5532 * is removed by the qinfifo scanning code 5533 * above. 5534 */ 5535 if ((scb->flags & SCB_ACTIVE) != 0) 5536 continue; 5537 5538 if (ahc_match_scb(ahc, scb, target, channel, lun, 5539 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5540 /*|| (ctx != NULL && ctx != scb->io_ctx)*/) 5541 continue; 5542 5543 /* 5544 * We found an scb that needs to be acted on. 5545 */ 5546 found++; 5547 switch (action) { 5548 case SEARCH_COMPLETE: 5549 { 5550 cam_status ostat; 5551 cam_status cstat; 5552 5553 ostat = ahc_get_transaction_status(scb); 5554 if (ostat == CAM_REQ_INPROG) 5555 ahc_set_transaction_status(scb, status); 5556 cstat = ahc_get_transaction_status(scb); 5557 if (cstat != CAM_REQ_CMP) 5558 ahc_freeze_scb(scb); 5559 if ((scb->flags & SCB_ACTIVE) == 0) 5560 printf("Inactive SCB in untaggedQ\n"); 5561 ahc_done(ahc, scb); 5562 break; 5563 } 5564 case SEARCH_REMOVE: 5565 scb->flags &= ~SCB_UNTAGGEDQ; 5566 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5567 break; 5568 case SEARCH_COUNT: 5569 break; 5570 } 5571 } 5572 } 5573 5574 if (action == SEARCH_COMPLETE) 5575 ahc_release_untagged_queues(ahc); 5576 return (found); 5577 } 5578 5579 int 5580 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5581 int lun, u_int tag, int stop_on_first, int remove, 5582 int save_state) 5583 { 5584 struct scb *scbp; 5585 u_int next; 5586 u_int prev; 5587 u_int count; 5588 u_int active_scb; 5589 5590 count = 0; 5591 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5592 prev = SCB_LIST_NULL; 5593 5594 if (save_state) { 5595 /* restore this when we're done */ 5596 active_scb = ahc_inb(ahc, SCBPTR); 5597 } else 5598 /* Silence compiler */ 5599 active_scb = SCB_LIST_NULL; 5600 5601 while (next != SCB_LIST_NULL) { 5602 u_int scb_index; 5603 5604 ahc_outb(ahc, SCBPTR, next); 5605 scb_index = ahc_inb(ahc, SCB_TAG); 5606 if (scb_index >= ahc->scb_data->numscbs) { 5607 printf("Disconnected List inconsistency. " 5608 "SCB index == %d, yet numscbs == %d.", 5609 scb_index, ahc->scb_data->numscbs); 5610 ahc_dump_card_state(ahc); 5611 panic("for safety"); 5612 } 5613 5614 if (next == prev) { 5615 panic("Disconnected List Loop. " 5616 "cur SCBPTR == %x, prev SCBPTR == %x.", 5617 next, prev); 5618 } 5619 scbp = ahc_lookup_scb(ahc, scb_index); 5620 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5621 tag, ROLE_INITIATOR)) { 5622 count++; 5623 if (remove) { 5624 next = 5625 ahc_rem_scb_from_disc_list(ahc, prev, next); 5626 } else { 5627 prev = next; 5628 next = ahc_inb(ahc, SCB_NEXT); 5629 } 5630 if (stop_on_first) 5631 break; 5632 } else { 5633 prev = next; 5634 next = ahc_inb(ahc, SCB_NEXT); 5635 } 5636 } 5637 if (save_state) 5638 ahc_outb(ahc, SCBPTR, active_scb); 5639 return (count); 5640 } 5641 5642 /* 5643 * Remove an SCB from the on chip list of disconnected transactions. 5644 * This is empty/unused if we are not performing SCB paging. 5645 */ 5646 static u_int 5647 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5648 { 5649 u_int next; 5650 5651 ahc_outb(ahc, SCBPTR, scbptr); 5652 next = ahc_inb(ahc, SCB_NEXT); 5653 5654 ahc_outb(ahc, SCB_CONTROL, 0); 5655 5656 ahc_add_curscb_to_free_list(ahc); 5657 5658 if (prev != SCB_LIST_NULL) { 5659 ahc_outb(ahc, SCBPTR, prev); 5660 ahc_outb(ahc, SCB_NEXT, next); 5661 } else 5662 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5663 5664 return (next); 5665 } 5666 5667 /* 5668 * Add the SCB as selected by SCBPTR onto the on chip list of 5669 * free hardware SCBs. This list is empty/unused if we are not 5670 * performing SCB paging. 5671 */ 5672 static void 5673 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5674 { 5675 /* 5676 * Invalidate the tag so that our abort 5677 * routines don't think it's active. 5678 */ 5679 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5680 5681 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5682 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5683 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5684 } 5685 } 5686 5687 /* 5688 * Manipulate the waiting for selection list and return the 5689 * scb that follows the one that we remove. 5690 */ 5691 static u_int 5692 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5693 { 5694 u_int curscb, next; 5695 5696 /* 5697 * Select the SCB we want to abort and 5698 * pull the next pointer out of it. 5699 */ 5700 curscb = ahc_inb(ahc, SCBPTR); 5701 ahc_outb(ahc, SCBPTR, scbpos); 5702 next = ahc_inb(ahc, SCB_NEXT); 5703 5704 /* Clear the necessary fields */ 5705 ahc_outb(ahc, SCB_CONTROL, 0); 5706 5707 ahc_add_curscb_to_free_list(ahc); 5708 5709 /* update the waiting list */ 5710 if (prev == SCB_LIST_NULL) { 5711 /* First in the list */ 5712 ahc_outb(ahc, WAITING_SCBH, next); 5713 5714 /* 5715 * Ensure we aren't attempting to perform 5716 * selection for this entry. 5717 */ 5718 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5719 } else { 5720 /* 5721 * Select the scb that pointed to us 5722 * and update its next pointer. 5723 */ 5724 ahc_outb(ahc, SCBPTR, prev); 5725 ahc_outb(ahc, SCB_NEXT, next); 5726 } 5727 5728 /* 5729 * Point us back at the original scb position. 5730 */ 5731 ahc_outb(ahc, SCBPTR, curscb); 5732 return next; 5733 } 5734 5735 /******************************** Error Handling ******************************/ 5736 /* 5737 * Abort all SCBs that match the given description (target/channel/lun/tag), 5738 * setting their status to the passed in status if the status has not already 5739 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5740 * is paused before it is called. 5741 */ 5742 int 5743 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5744 int lun, u_int tag, role_t role, uint32_t status) 5745 { 5746 struct scb *scbp; 5747 struct scb *scbp_next; 5748 u_int active_scb; 5749 int i, j; 5750 int maxtarget; 5751 int minlun; 5752 int maxlun; 5753 5754 int found; 5755 5756 /* 5757 * Don't attempt to run any queued untagged transactions 5758 * until we are done with the abort process. 5759 */ 5760 ahc_freeze_untagged_queues(ahc); 5761 5762 /* restore this when we're done */ 5763 active_scb = ahc_inb(ahc, SCBPTR); 5764 5765 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5766 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5767 5768 /* 5769 * Clean out the busy target table for any untagged commands. 5770 */ 5771 i = 0; 5772 maxtarget = 16; 5773 if (target != CAM_TARGET_WILDCARD) { 5774 i = target; 5775 if (channel == 'B') 5776 i += 8; 5777 maxtarget = i + 1; 5778 } 5779 5780 if (lun == CAM_LUN_WILDCARD) { 5781 5782 /* 5783 * Unless we are using an SCB based 5784 * busy targets table, there is only 5785 * one table entry for all luns of 5786 * a target. 5787 */ 5788 minlun = 0; 5789 maxlun = 1; 5790 if ((ahc->flags & AHC_SCB_BTT) != 0) 5791 maxlun = AHC_NUM_LUNS; 5792 } else { 5793 minlun = lun; 5794 maxlun = lun + 1; 5795 } 5796 5797 if (role != ROLE_TARGET) { 5798 for (;i < maxtarget; i++) { 5799 for (j = minlun;j < maxlun; j++) { 5800 u_int scbid; 5801 u_int tcl; 5802 5803 tcl = BUILD_TCL(i << 4, j); 5804 scbid = ahc_index_busy_tcl(ahc, tcl); 5805 scbp = ahc_lookup_scb(ahc, scbid); 5806 if (scbp == NULL 5807 || ahc_match_scb(ahc, scbp, target, channel, 5808 lun, tag, role) == 0) 5809 continue; 5810 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5811 } 5812 } 5813 5814 /* 5815 * Go through the disconnected list and remove any entries we 5816 * have queued for completion, 0'ing their control byte too. 5817 * We save the active SCB and restore it ourselves, so there 5818 * is no reason for this search to restore it too. 5819 */ 5820 ahc_search_disc_list(ahc, target, channel, lun, tag, 5821 /*stop_on_first*/FALSE, /*remove*/TRUE, 5822 /*save_state*/FALSE); 5823 } 5824 5825 /* 5826 * Go through the hardware SCB array looking for commands that 5827 * were active but not on any list. In some cases, these remnants 5828 * might not still have mappings in the scbindex array (e.g. unexpected 5829 * bus free with the same scb queued for an abort). Don't hold this 5830 * against them. 5831 */ 5832 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5833 u_int scbid; 5834 5835 ahc_outb(ahc, SCBPTR, i); 5836 scbid = ahc_inb(ahc, SCB_TAG); 5837 scbp = ahc_lookup_scb(ahc, scbid); 5838 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5839 || (scbp != NULL 5840 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5841 ahc_add_curscb_to_free_list(ahc); 5842 } 5843 5844 /* 5845 * Go through the pending CCB list and look for 5846 * commands for this target that are still active. 5847 * These are other tagged commands that were 5848 * disconnected when the reset occurred. 5849 */ 5850 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5851 while (scbp_next != NULL) { 5852 scbp = scbp_next; 5853 scbp_next = LIST_NEXT(scbp, pending_links); 5854 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5855 cam_status ostat; 5856 5857 ostat = ahc_get_transaction_status(scbp); 5858 if (ostat == CAM_REQ_INPROG) 5859 ahc_set_transaction_status(scbp, status); 5860 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5861 ahc_freeze_scb(scbp); 5862 if ((scbp->flags & SCB_ACTIVE) == 0) 5863 printf("Inactive SCB on pending list\n"); 5864 ahc_done(ahc, scbp); 5865 found++; 5866 } 5867 } 5868 ahc_outb(ahc, SCBPTR, active_scb); 5869 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5870 ahc_release_untagged_queues(ahc); 5871 return found; 5872 } 5873 5874 static void 5875 ahc_reset_current_bus(struct ahc_softc *ahc) 5876 { 5877 uint8_t scsiseq; 5878 5879 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5880 scsiseq = ahc_inb(ahc, SCSISEQ); 5881 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5882 ahc_flush_device_writes(ahc); 5883 ahc_delay(AHC_BUSRESET_DELAY); 5884 /* Turn off the bus reset */ 5885 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5886 5887 ahc_clear_intstat(ahc); 5888 5889 /* Re-enable reset interrupts */ 5890 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5891 } 5892 5893 int 5894 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5895 { 5896 struct ahc_devinfo devinfo; 5897 u_int initiator, target, max_scsiid; 5898 u_int sblkctl; 5899 u_int scsiseq; 5900 u_int simode1; 5901 int found; 5902 int restart_needed; 5903 char cur_channel; 5904 5905 ahc->pending_device = NULL; 5906 5907 ahc_compile_devinfo(&devinfo, 5908 CAM_TARGET_WILDCARD, 5909 CAM_TARGET_WILDCARD, 5910 CAM_LUN_WILDCARD, 5911 channel, ROLE_UNKNOWN); 5912 ahc_pause(ahc); 5913 5914 /* Make sure the sequencer is in a safe location. */ 5915 ahc_clear_critical_section(ahc); 5916 5917 /* 5918 * Run our command complete fifos to ensure that we perform 5919 * completion processing on any commands that 'completed' 5920 * before the reset occurred. 5921 */ 5922 ahc_run_qoutfifo(ahc); 5923 #if AHC_TARGET_MODE 5924 /* 5925 * XXX - In Twin mode, the tqinfifo may have commands 5926 * for an unaffected channel in it. However, if 5927 * we have run out of ATIO resources to drain that 5928 * queue, we may not get them all out here. Further, 5929 * the blocked transactions for the reset channel 5930 * should just be killed off, irrespecitve of whether 5931 * we are blocked on ATIO resources. Write a routine 5932 * to compact the tqinfifo appropriately. 5933 */ 5934 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5935 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5936 } 5937 #endif 5938 5939 /* 5940 * Reset the bus if we are initiating this reset 5941 */ 5942 sblkctl = ahc_inb(ahc, SBLKCTL); 5943 cur_channel = 'A'; 5944 if ((ahc->features & AHC_TWIN) != 0 5945 && ((sblkctl & SELBUSB) != 0)) 5946 cur_channel = 'B'; 5947 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5948 if (cur_channel != channel) { 5949 /* Case 1: Command for another bus is active 5950 * Stealthily reset the other bus without 5951 * upsetting the current bus. 5952 */ 5953 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5954 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5955 #if AHC_TARGET_MODE 5956 /* 5957 * Bus resets clear ENSELI, so we cannot 5958 * defer re-enabling bus reset interrupts 5959 * if we are in target mode. 5960 */ 5961 if ((ahc->flags & AHC_TARGETROLE) != 0) 5962 simode1 |= ENSCSIRST; 5963 #endif 5964 ahc_outb(ahc, SIMODE1, simode1); 5965 if (initiate_reset) 5966 ahc_reset_current_bus(ahc); 5967 ahc_clear_intstat(ahc); 5968 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5969 ahc_outb(ahc, SBLKCTL, sblkctl); 5970 restart_needed = FALSE; 5971 } else { 5972 /* Case 2: A command from this bus is active or we're idle */ 5973 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5974 #if AHC_TARGET_MODE 5975 /* 5976 * Bus resets clear ENSELI, so we cannot 5977 * defer re-enabling bus reset interrupts 5978 * if we are in target mode. 5979 */ 5980 if ((ahc->flags & AHC_TARGETROLE) != 0) 5981 simode1 |= ENSCSIRST; 5982 #endif 5983 ahc_outb(ahc, SIMODE1, simode1); 5984 if (initiate_reset) 5985 ahc_reset_current_bus(ahc); 5986 ahc_clear_intstat(ahc); 5987 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5988 restart_needed = TRUE; 5989 } 5990 5991 /* 5992 * Clean up all the state information for the 5993 * pending transactions on this bus. 5994 */ 5995 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5996 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5997 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 5998 5999 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6000 6001 #ifdef AHC_TARGET_MODE 6002 /* 6003 * Send an immediate notify ccb to all target more peripheral 6004 * drivers affected by this action. 6005 */ 6006 for (target = 0; target <= max_scsiid; target++) { 6007 struct ahc_tmode_tstate* tstate; 6008 u_int lun; 6009 6010 tstate = ahc->enabled_targets[target]; 6011 if (tstate == NULL) 6012 continue; 6013 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6014 struct ahc_tmode_lstate* lstate; 6015 6016 lstate = tstate->enabled_luns[lun]; 6017 if (lstate == NULL) 6018 continue; 6019 6020 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6021 EVENT_TYPE_BUS_RESET, /*arg*/0); 6022 ahc_send_lstate_events(ahc, lstate); 6023 } 6024 } 6025 #endif 6026 /* 6027 * Revert to async/narrow transfers until we renegotiate. 6028 */ 6029 for (target = 0; target <= max_scsiid; target++) { 6030 6031 if (ahc->enabled_targets[target] == NULL) 6032 continue; 6033 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6034 struct ahc_devinfo devinfo; 6035 6036 ahc_compile_devinfo(&devinfo, target, initiator, 6037 CAM_LUN_WILDCARD, 6038 channel, ROLE_UNKNOWN); 6039 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6040 AHC_TRANS_CUR, /*paused*/TRUE); 6041 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6042 /*period*/0, /*offset*/0, 6043 /*ppr_options*/0, AHC_TRANS_CUR, 6044 /*paused*/TRUE); 6045 } 6046 } 6047 6048 if (restart_needed) 6049 ahc_restart(ahc); 6050 else 6051 ahc_unpause(ahc); 6052 return found; 6053 } 6054 6055 6056 /***************************** Residual Processing ****************************/ 6057 /* 6058 * Calculate the residual for a just completed SCB. 6059 */ 6060 void 6061 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6062 { 6063 struct hardware_scb *hscb; 6064 struct status_pkt *spkt; 6065 uint32_t sgptr; 6066 uint32_t resid_sgptr; 6067 uint32_t resid; 6068 6069 /* 6070 * 5 cases. 6071 * 1) No residual. 6072 * SG_RESID_VALID clear in sgptr. 6073 * 2) Transferless command 6074 * 3) Never performed any transfers. 6075 * sgptr has SG_FULL_RESID set. 6076 * 4) No residual but target did not 6077 * save data pointers after the 6078 * last transfer, so sgptr was 6079 * never updated. 6080 * 5) We have a partial residual. 6081 * Use residual_sgptr to determine 6082 * where we are. 6083 */ 6084 6085 hscb = scb->hscb; 6086 sgptr = ahc_le32toh(hscb->sgptr); 6087 if ((sgptr & SG_RESID_VALID) == 0) 6088 /* Case 1 */ 6089 return; 6090 sgptr &= ~SG_RESID_VALID; 6091 6092 if ((sgptr & SG_LIST_NULL) != 0) 6093 /* Case 2 */ 6094 return; 6095 6096 spkt = &hscb->shared_data.status; 6097 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6098 if ((sgptr & SG_FULL_RESID) != 0) { 6099 /* Case 3 */ 6100 resid = ahc_get_transfer_length(scb); 6101 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6102 /* Case 4 */ 6103 return; 6104 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6105 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6106 } else { 6107 struct ahc_dma_seg *sg; 6108 6109 /* 6110 * Remainder of the SG where the transfer 6111 * stopped. 6112 */ 6113 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6114 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6115 6116 /* The residual sg_ptr always points to the next sg */ 6117 sg--; 6118 6119 /* 6120 * Add up the contents of all residual 6121 * SG segments that are after the SG where 6122 * the transfer stopped. 6123 */ 6124 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6125 sg++; 6126 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6127 } 6128 } 6129 if ((scb->flags & SCB_SENSE) == 0) 6130 ahc_set_residual(scb, resid); 6131 else 6132 ahc_set_sense_residual(scb, resid); 6133 6134 #ifdef AHC_DEBUG 6135 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6136 ahc_print_path(ahc, scb); 6137 printf("Handled %sResidual of %d bytes\n", 6138 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6139 } 6140 #endif 6141 } 6142 6143 /******************************* Target Mode **********************************/ 6144 #ifdef AHC_TARGET_MODE 6145 /* 6146 * Add a target mode event to this lun's queue 6147 */ 6148 static void 6149 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6150 u_int initiator_id, u_int event_type, u_int event_arg) 6151 { 6152 struct ahc_tmode_event *event; 6153 int pending; 6154 6155 xpt_freeze_devq(lstate->path, /*count*/1); 6156 if (lstate->event_w_idx >= lstate->event_r_idx) 6157 pending = lstate->event_w_idx - lstate->event_r_idx; 6158 else 6159 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6160 - (lstate->event_r_idx - lstate->event_w_idx); 6161 6162 if (event_type == EVENT_TYPE_BUS_RESET 6163 || event_type == MSG_BUS_DEV_RESET) { 6164 /* 6165 * Any earlier events are irrelevant, so reset our buffer. 6166 * This has the effect of allowing us to deal with reset 6167 * floods (an external device holding down the reset line) 6168 * without losing the event that is really interesting. 6169 */ 6170 lstate->event_r_idx = 0; 6171 lstate->event_w_idx = 0; 6172 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6173 } 6174 6175 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6176 xpt_print_path(lstate->path); 6177 printf("immediate event %x:%x lost\n", 6178 lstate->event_buffer[lstate->event_r_idx].event_type, 6179 lstate->event_buffer[lstate->event_r_idx].event_arg); 6180 lstate->event_r_idx++; 6181 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6182 lstate->event_r_idx = 0; 6183 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6184 } 6185 6186 event = &lstate->event_buffer[lstate->event_w_idx]; 6187 event->initiator_id = initiator_id; 6188 event->event_type = event_type; 6189 event->event_arg = event_arg; 6190 lstate->event_w_idx++; 6191 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6192 lstate->event_w_idx = 0; 6193 } 6194 6195 /* 6196 * Send any target mode events queued up waiting 6197 * for immediate notify resources. 6198 */ 6199 void 6200 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6201 { 6202 struct ccb_hdr *ccbh; 6203 struct ccb_immed_notify *inot; 6204 6205 while (lstate->event_r_idx != lstate->event_w_idx 6206 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6207 struct ahc_tmode_event *event; 6208 6209 event = &lstate->event_buffer[lstate->event_r_idx]; 6210 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6211 inot = (struct ccb_immed_notify *)ccbh; 6212 switch (event->event_type) { 6213 case EVENT_TYPE_BUS_RESET: 6214 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6215 break; 6216 default: 6217 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6218 inot->message_args[0] = event->event_type; 6219 inot->message_args[1] = event->event_arg; 6220 break; 6221 } 6222 inot->initiator_id = event->initiator_id; 6223 inot->sense_len = 0; 6224 xpt_done((union ccb *)inot); 6225 lstate->event_r_idx++; 6226 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6227 lstate->event_r_idx = 0; 6228 } 6229 } 6230 #endif 6231 6232 /******************** Sequencer Program Patching/Download *********************/ 6233 6234 #ifdef AHC_DUMP_SEQ 6235 void 6236 ahc_dumpseq(struct ahc_softc* ahc) 6237 { 6238 int i; 6239 int max_prog; 6240 6241 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 6242 max_prog = 448; 6243 else if ((ahc->features & AHC_ULTRA2) != 0) 6244 max_prog = 768; 6245 else 6246 max_prog = 512; 6247 6248 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6249 ahc_outb(ahc, SEQADDR0, 0); 6250 ahc_outb(ahc, SEQADDR1, 0); 6251 for (i = 0; i < max_prog; i++) { 6252 uint8_t ins_bytes[4]; 6253 6254 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6255 printf("0x%08x\n", ins_bytes[0] << 24 6256 | ins_bytes[1] << 16 6257 | ins_bytes[2] << 8 6258 | ins_bytes[3]); 6259 } 6260 } 6261 #endif 6262 6263 static void 6264 ahc_loadseq(struct ahc_softc *ahc) 6265 { 6266 struct cs cs_table[num_critical_sections]; 6267 u_int begin_set[num_critical_sections]; 6268 u_int end_set[num_critical_sections]; 6269 struct patch *cur_patch; 6270 u_int cs_count; 6271 u_int cur_cs; 6272 u_int i; 6273 int downloaded; 6274 u_int skip_addr; 6275 u_int sg_prefetch_cnt; 6276 uint8_t download_consts[7]; 6277 6278 /* 6279 * Start out with 0 critical sections 6280 * that apply to this firmware load. 6281 */ 6282 cs_count = 0; 6283 cur_cs = 0; 6284 memset(begin_set, 0, sizeof(begin_set)); 6285 memset(end_set, 0, sizeof(end_set)); 6286 6287 /* Setup downloadable constant table */ 6288 download_consts[QOUTFIFO_OFFSET] = 0; 6289 if (ahc->targetcmds != NULL) 6290 download_consts[QOUTFIFO_OFFSET] += 32; 6291 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6292 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6293 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6294 sg_prefetch_cnt = ahc->pci_cachesize; 6295 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6296 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6297 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6298 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6299 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6300 6301 cur_patch = patches; 6302 downloaded = 0; 6303 skip_addr = 0; 6304 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6305 ahc_outb(ahc, SEQADDR0, 0); 6306 ahc_outb(ahc, SEQADDR1, 0); 6307 6308 for (i = 0; i < sizeof(seqprog)/4; i++) { 6309 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6310 /* 6311 * Don't download this instruction as it 6312 * is in a patch that was removed. 6313 */ 6314 continue; 6315 } 6316 /* 6317 * Move through the CS table until we find a CS 6318 * that might apply to this instruction. 6319 */ 6320 for (; cur_cs < num_critical_sections; cur_cs++) { 6321 if (critical_sections[cur_cs].end <= i) { 6322 if (begin_set[cs_count] == TRUE 6323 && end_set[cs_count] == FALSE) { 6324 cs_table[cs_count].end = downloaded; 6325 end_set[cs_count] = TRUE; 6326 cs_count++; 6327 } 6328 continue; 6329 } 6330 if (critical_sections[cur_cs].begin <= i 6331 && begin_set[cs_count] == FALSE) { 6332 cs_table[cs_count].begin = downloaded; 6333 begin_set[cs_count] = TRUE; 6334 } 6335 break; 6336 } 6337 ahc_download_instr(ahc, i, download_consts); 6338 downloaded++; 6339 } 6340 6341 ahc->num_critical_sections = cs_count; 6342 if (cs_count != 0) { 6343 6344 cs_count *= sizeof(struct cs); 6345 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6346 if (ahc->critical_sections == NULL) 6347 panic("ahc_loadseq: Could not malloc"); 6348 memcpy(ahc->critical_sections, cs_table, cs_count); 6349 } 6350 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6351 ahc_restart(ahc); 6352 6353 if (bootverbose) { 6354 printf(" %d instructions downloaded\n", downloaded); 6355 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6356 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6357 } 6358 } 6359 6360 static int 6361 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6362 u_int start_instr, u_int *skip_addr) 6363 { 6364 struct patch *cur_patch; 6365 struct patch *last_patch; 6366 u_int num_patches; 6367 6368 num_patches = sizeof(patches)/sizeof(struct patch); 6369 last_patch = &patches[num_patches]; 6370 cur_patch = *start_patch; 6371 6372 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6373 6374 if (cur_patch->patch_func(ahc) == 0) { 6375 6376 /* Start rejecting code */ 6377 *skip_addr = start_instr + cur_patch->skip_instr; 6378 cur_patch += cur_patch->skip_patch; 6379 } else { 6380 /* Accepted this patch. Advance to the next 6381 * one and wait for our intruction pointer to 6382 * hit this point. 6383 */ 6384 cur_patch++; 6385 } 6386 } 6387 6388 *start_patch = cur_patch; 6389 if (start_instr < *skip_addr) 6390 /* Still skipping */ 6391 return (0); 6392 6393 return (1); 6394 } 6395 6396 static void 6397 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6398 { 6399 union ins_formats instr; 6400 struct ins_format1 *fmt1_ins; 6401 struct ins_format3 *fmt3_ins; 6402 u_int opcode; 6403 6404 /* 6405 * The firmware is always compiled into a little endian format. 6406 */ 6407 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6408 6409 fmt1_ins = &instr.format1; 6410 fmt3_ins = NULL; 6411 6412 /* Pull the opcode */ 6413 opcode = instr.format1.opcode; 6414 switch (opcode) { 6415 case AIC_OP_JMP: 6416 case AIC_OP_JC: 6417 case AIC_OP_JNC: 6418 case AIC_OP_CALL: 6419 case AIC_OP_JNE: 6420 case AIC_OP_JNZ: 6421 case AIC_OP_JE: 6422 case AIC_OP_JZ: 6423 { 6424 struct patch *cur_patch; 6425 int address_offset; 6426 u_int address; 6427 u_int skip_addr; 6428 u_int i; 6429 6430 fmt3_ins = &instr.format3; 6431 address_offset = 0; 6432 address = fmt3_ins->address; 6433 cur_patch = patches; 6434 skip_addr = 0; 6435 for (i = 0; i < address;) { 6436 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6437 6438 if (skip_addr > i) { 6439 int end_addr; 6440 6441 end_addr = MIN(address, skip_addr); 6442 address_offset += end_addr - i; 6443 i = skip_addr; 6444 } else { 6445 i++; 6446 } 6447 } 6448 address -= address_offset; 6449 fmt3_ins->address = address; 6450 /* FALLTHROUGH */ 6451 } 6452 case AIC_OP_OR: 6453 case AIC_OP_AND: 6454 case AIC_OP_XOR: 6455 case AIC_OP_ADD: 6456 case AIC_OP_ADC: 6457 case AIC_OP_BMOV: 6458 if (fmt1_ins->parity != 0) { 6459 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6460 } 6461 fmt1_ins->parity = 0; 6462 if ((ahc->features & AHC_CMD_CHAN) == 0 6463 && opcode == AIC_OP_BMOV) { 6464 /* 6465 * Block move was added at the same time 6466 * as the command channel. Verify that 6467 * this is only a move of a single element 6468 * and convert the BMOV to a MOV 6469 * (AND with an immediate of FF). 6470 */ 6471 if (fmt1_ins->immediate != 1) 6472 panic("%s: BMOV not supported\n", 6473 ahc_name(ahc)); 6474 fmt1_ins->opcode = AIC_OP_AND; 6475 fmt1_ins->immediate = 0xff; 6476 } 6477 /* FALLTHROUGH */ 6478 case AIC_OP_ROL: 6479 if ((ahc->features & AHC_ULTRA2) != 0) { 6480 int i, count; 6481 6482 /* Calculate odd parity for the instruction */ 6483 for (i = 0, count = 0; i < 31; i++) { 6484 uint32_t mask; 6485 6486 mask = 0x01 << i; 6487 if ((instr.integer & mask) != 0) 6488 count++; 6489 } 6490 if ((count & 0x01) == 0) 6491 instr.format1.parity = 1; 6492 } else { 6493 /* Compress the instruction for older sequencers */ 6494 if (fmt3_ins != NULL) { 6495 instr.integer = 6496 fmt3_ins->immediate 6497 | (fmt3_ins->source << 8) 6498 | (fmt3_ins->address << 16) 6499 | (fmt3_ins->opcode << 25); 6500 } else { 6501 instr.integer = 6502 fmt1_ins->immediate 6503 | (fmt1_ins->source << 8) 6504 | (fmt1_ins->destination << 16) 6505 | (fmt1_ins->ret << 24) 6506 | (fmt1_ins->opcode << 25); 6507 } 6508 } 6509 /* The sequencer is a little endian cpu */ 6510 instr.integer = ahc_htole32(instr.integer); 6511 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6512 break; 6513 default: 6514 panic("Unknown opcode encountered in seq program"); 6515 break; 6516 } 6517 } 6518 6519 int 6520 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6521 const char *name, u_int address, u_int value, 6522 u_int *cur_column, u_int wrap_point) 6523 { 6524 int printed; 6525 u_int printed_mask; 6526 char line[2028]; 6527 6528 memset(line, '\0', 2048); 6529 6530 if (cur_column != NULL && *cur_column >= wrap_point) { 6531 printf("\n"); 6532 *cur_column = 0; 6533 } 6534 sprintf(line+strlen(line), "%s[0x%x]", name, value); 6535 if (table == NULL) { 6536 sprintf(line+strlen(line), " "); 6537 printed = strlen(line); 6538 printf(line); 6539 *cur_column += printed; 6540 return (printed); 6541 } 6542 printed_mask = 0; 6543 while (printed_mask != 0xFF) { 6544 int entry; 6545 6546 for (entry = 0; entry < num_entries; entry++) { 6547 if (((value & table[entry].mask) 6548 != table[entry].value) 6549 || ((printed_mask & table[entry].mask) 6550 == table[entry].mask)) 6551 continue; 6552 6553 sprintf(line+strlen(line), "%s%s", 6554 printed_mask == 0 ? ":(" : "|", 6555 table[entry].name); 6556 printed_mask |= table[entry].mask; 6557 6558 break; 6559 } 6560 if (entry >= num_entries) 6561 break; 6562 } 6563 if (printed_mask != 0) 6564 sprintf(line+strlen(line), ") "); 6565 else 6566 sprintf(line+strlen(line), " "); 6567 printed = strlen(line); 6568 if (cur_column != NULL) 6569 *cur_column += printed; 6570 printf(line); 6571 6572 return (printed); 6573 } 6574 6575 void 6576 ahc_dump_card_state(struct ahc_softc *ahc) 6577 { 6578 struct scb *scb; 6579 struct scb_tailq *untagged_q; 6580 u_int cur_col; 6581 int paused; 6582 int target; 6583 int maxtarget; 6584 int i; 6585 uint8_t last_phase; 6586 uint8_t qinpos; 6587 uint8_t qintail; 6588 uint8_t qoutpos; 6589 uint8_t scb_index; 6590 uint8_t saved_scbptr; 6591 6592 if (ahc_is_paused(ahc)) { 6593 paused = 1; 6594 } else { 6595 paused = 0; 6596 ahc_pause(ahc); 6597 } 6598 6599 saved_scbptr = ahc_inb(ahc, SCBPTR); 6600 last_phase = ahc_inb(ahc, LASTPHASE); 6601 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6602 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6603 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6604 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6605 if (paused) 6606 printf("Card was paused\n"); 6607 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6608 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6609 ahc_inb(ahc, ARG_2)); 6610 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6611 ahc_inb(ahc, SCBPTR)); 6612 cur_col = 0; 6613 if ((ahc->features & AHC_DT) != 0) 6614 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6615 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6616 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6617 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6618 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6619 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6620 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6621 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6622 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6623 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6624 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6625 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6626 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6627 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6628 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6629 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6630 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6631 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6632 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6633 if (cur_col != 0) 6634 printf("\n"); 6635 printf("STACK:"); 6636 for (i = 0; i < STACK_SIZE; i++) 6637 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6638 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6639 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6640 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6641 /* QINFIFO */ 6642 printf("QINFIFO entries: "); 6643 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6644 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6645 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6646 } else 6647 qinpos = ahc_inb(ahc, QINPOS); 6648 qintail = ahc->qinfifonext; 6649 while (qinpos != qintail) { 6650 printf("%d ", ahc->qinfifo[qinpos]); 6651 qinpos++; 6652 } 6653 printf("\n"); 6654 6655 printf("Waiting Queue entries: "); 6656 scb_index = ahc_inb(ahc, WAITING_SCBH); 6657 i = 0; 6658 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6659 ahc_outb(ahc, SCBPTR, scb_index); 6660 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6661 scb_index = ahc_inb(ahc, SCB_NEXT); 6662 } 6663 printf("\n"); 6664 6665 printf("Disconnected Queue entries: "); 6666 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6667 i = 0; 6668 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6669 ahc_outb(ahc, SCBPTR, scb_index); 6670 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6671 scb_index = ahc_inb(ahc, SCB_NEXT); 6672 } 6673 printf("\n"); 6674 6675 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6676 printf("QOUTFIFO entries: "); 6677 qoutpos = ahc->qoutfifonext; 6678 i = 0; 6679 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6680 printf("%d ", ahc->qoutfifo[qoutpos]); 6681 qoutpos++; 6682 } 6683 printf("\n"); 6684 6685 printf("Sequencer Free SCB List: "); 6686 scb_index = ahc_inb(ahc, FREE_SCBH); 6687 i = 0; 6688 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6689 ahc_outb(ahc, SCBPTR, scb_index); 6690 printf("%d ", scb_index); 6691 scb_index = ahc_inb(ahc, SCB_NEXT); 6692 } 6693 printf("\n"); 6694 6695 printf("Sequencer SCB Info: "); 6696 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6697 ahc_outb(ahc, SCBPTR, i); 6698 /*cur_col =*/ printf("\n%3d ", i); 6699 6700 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6701 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6702 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6703 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6704 } 6705 printf("\n"); 6706 6707 printf("Pending list: "); 6708 i = 0; 6709 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6710 if (i++ > 256) 6711 break; 6712 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6713 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6714 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6715 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6716 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6717 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6718 printf("("); 6719 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6720 &cur_col, 60); 6721 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6722 printf(")"); 6723 } 6724 } 6725 printf("\n"); 6726 6727 printf("Kernel Free SCB list: "); 6728 i = 0; 6729 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6730 if (i++ > 256) 6731 break; 6732 printf("%d ", scb->hscb->tag); 6733 } 6734 printf("\n"); 6735 6736 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6737 for (target = 0; target <= maxtarget; target++) { 6738 untagged_q = &ahc->untagged_queues[target]; 6739 if (TAILQ_FIRST(untagged_q) == NULL) 6740 continue; 6741 printf("Untagged Q(%d): ", target); 6742 i = 0; 6743 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6744 if (i++ > 256) 6745 break; 6746 printf("%d ", scb->hscb->tag); 6747 } 6748 printf("\n"); 6749 } 6750 6751 ahc_platform_dump_card_state(ahc); 6752 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6753 ahc_outb(ahc, SCBPTR, saved_scbptr); 6754 if (paused == 0) 6755 ahc_unpause(ahc); 6756 } 6757 6758 /************************* Target Mode ****************************************/ 6759 #ifdef AHC_TARGET_MODE 6760 cam_status 6761 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6762 struct ahc_tmode_tstate **tstate, 6763 struct ahc_tmode_lstate **lstate, 6764 int notfound_failure) 6765 { 6766 6767 if ((ahc->features & AHC_TARGETMODE) == 0) 6768 return (CAM_REQ_INVALID); 6769 6770 /* 6771 * Handle the 'black hole' device that sucks up 6772 * requests to unattached luns on enabled targets. 6773 */ 6774 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6775 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6776 *tstate = NULL; 6777 *lstate = ahc->black_hole; 6778 } else { 6779 u_int max_id; 6780 6781 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6782 if (ccb->ccb_h.target_id > max_id) 6783 return (CAM_TID_INVALID); 6784 6785 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6786 return (CAM_LUN_INVALID); 6787 6788 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6789 *lstate = NULL; 6790 if (*tstate != NULL) 6791 *lstate = 6792 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6793 } 6794 6795 if (notfound_failure != 0 && *lstate == NULL) 6796 return (CAM_PATH_INVALID); 6797 6798 return (CAM_REQ_CMP); 6799 } 6800 6801 void 6802 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6803 { 6804 struct ahc_tmode_tstate *tstate; 6805 struct ahc_tmode_lstate *lstate; 6806 struct ccb_en_lun *cel; 6807 cam_status status; 6808 u_int target; 6809 u_int lun; 6810 u_int target_mask; 6811 u_int our_id; 6812 u_long s; 6813 char channel; 6814 6815 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6816 /*notfound_failure*/FALSE); 6817 6818 if (status != CAM_REQ_CMP) { 6819 ccb->ccb_h.status = status; 6820 return; 6821 } 6822 6823 if (cam_sim_bus(sim) == 0) 6824 our_id = ahc->our_id; 6825 else 6826 our_id = ahc->our_id_b; 6827 6828 if (ccb->ccb_h.target_id != our_id) { 6829 /* 6830 * our_id represents our initiator ID, or 6831 * the ID of the first target to have an 6832 * enabled lun in target mode. There are 6833 * two cases that may preclude enabling a 6834 * target id other than our_id. 6835 * 6836 * o our_id is for an active initiator role. 6837 * Since the hardware does not support 6838 * reselections to the initiator role at 6839 * anything other than our_id, and our_id 6840 * is used by the hardware to indicate the 6841 * ID to use for both select-out and 6842 * reselect-out operations, the only target 6843 * ID we can support in this mode is our_id. 6844 * 6845 * o The MULTARGID feature is not available and 6846 * a previous target mode ID has been enabled. 6847 */ 6848 if ((ahc->features & AHC_MULTIROLE) != 0) { 6849 6850 if ((ahc->features & AHC_MULTI_TID) != 0 6851 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6852 /* 6853 * Only allow additional targets if 6854 * the initiator role is disabled. 6855 * The hardware cannot handle a re-select-in 6856 * on the initiator id during a re-select-out 6857 * on a different target id. 6858 */ 6859 status = CAM_TID_INVALID; 6860 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6861 || ahc->enabled_luns > 0) { 6862 /* 6863 * Only allow our target id to change 6864 * if the initiator role is not configured 6865 * and there are no enabled luns which 6866 * are attached to the currently registered 6867 * scsi id. 6868 */ 6869 status = CAM_TID_INVALID; 6870 } 6871 } else if ((ahc->features & AHC_MULTI_TID) == 0 6872 && ahc->enabled_luns > 0) { 6873 6874 status = CAM_TID_INVALID; 6875 } 6876 } 6877 6878 if (status != CAM_REQ_CMP) { 6879 ccb->ccb_h.status = status; 6880 return; 6881 } 6882 6883 /* 6884 * We now have an id that is valid. 6885 * If we aren't in target mode, switch modes. 6886 */ 6887 if ((ahc->flags & AHC_TARGETROLE) == 0 6888 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6889 u_long s; 6890 6891 printf("Configuring Target Mode\n"); 6892 ahc_lock(ahc, &s); 6893 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6894 ccb->ccb_h.status = CAM_BUSY; 6895 ahc_unlock(ahc, &s); 6896 return; 6897 } 6898 ahc->flags |= AHC_TARGETROLE; 6899 if ((ahc->features & AHC_MULTIROLE) == 0) 6900 ahc->flags &= ~AHC_INITIATORROLE; 6901 ahc_pause(ahc); 6902 ahc_loadseq(ahc); 6903 ahc_unlock(ahc, &s); 6904 } 6905 cel = &ccb->cel; 6906 target = ccb->ccb_h.target_id; 6907 lun = ccb->ccb_h.target_lun; 6908 channel = SIM_CHANNEL(ahc, sim); 6909 target_mask = 0x01 << target; 6910 if (channel == 'B') 6911 target_mask <<= 8; 6912 6913 if (cel->enable != 0) { 6914 u_int scsiseq; 6915 6916 /* Are we already enabled?? */ 6917 if (lstate != NULL) { 6918 xpt_print_path(ccb->ccb_h.path); 6919 printf("Lun already enabled\n"); 6920 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6921 return; 6922 } 6923 6924 if (cel->grp6_len != 0 6925 || cel->grp7_len != 0) { 6926 /* 6927 * Don't (yet?) support vendor 6928 * specific commands. 6929 */ 6930 ccb->ccb_h.status = CAM_REQ_INVALID; 6931 printf("Non-zero Group Codes\n"); 6932 return; 6933 } 6934 6935 /* 6936 * Seems to be okay. 6937 * Setup our data structures. 6938 */ 6939 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6940 tstate = ahc_alloc_tstate(ahc, target, channel); 6941 if (tstate == NULL) { 6942 xpt_print_path(ccb->ccb_h.path); 6943 printf("Couldn't allocate tstate\n"); 6944 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6945 return; 6946 } 6947 } 6948 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6949 if (lstate == NULL) { 6950 xpt_print_path(ccb->ccb_h.path); 6951 printf("Couldn't allocate lstate\n"); 6952 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6953 return; 6954 } 6955 memset(lstate, 0, sizeof(*lstate)); 6956 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6957 xpt_path_path_id(ccb->ccb_h.path), 6958 xpt_path_target_id(ccb->ccb_h.path), 6959 xpt_path_lun_id(ccb->ccb_h.path)); 6960 if (status != CAM_REQ_CMP) { 6961 free(lstate, M_DEVBUF); 6962 xpt_print_path(ccb->ccb_h.path); 6963 printf("Couldn't allocate path\n"); 6964 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6965 return; 6966 } 6967 SLIST_INIT(&lstate->accept_tios); 6968 SLIST_INIT(&lstate->immed_notifies); 6969 ahc_lock(ahc, &s); 6970 ahc_pause(ahc); 6971 if (target != CAM_TARGET_WILDCARD) { 6972 tstate->enabled_luns[lun] = lstate; 6973 ahc->enabled_luns++; 6974 6975 if ((ahc->features & AHC_MULTI_TID) != 0) { 6976 u_int targid_mask; 6977 6978 targid_mask = ahc_inb(ahc, TARGID) 6979 | (ahc_inb(ahc, TARGID + 1) << 8); 6980 6981 targid_mask |= target_mask; 6982 ahc_outb(ahc, TARGID, targid_mask); 6983 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6984 6985 ahc_update_scsiid(ahc, targid_mask); 6986 } else { 6987 u_int our_id; 6988 char channel; 6989 6990 channel = SIM_CHANNEL(ahc, sim); 6991 our_id = SIM_SCSI_ID(ahc, sim); 6992 6993 /* 6994 * This can only happen if selections 6995 * are not enabled 6996 */ 6997 if (target != our_id) { 6998 u_int sblkctl; 6999 char cur_channel; 7000 int swap; 7001 7002 sblkctl = ahc_inb(ahc, SBLKCTL); 7003 cur_channel = (sblkctl & SELBUSB) 7004 ? 'B' : 'A'; 7005 if ((ahc->features & AHC_TWIN) == 0) 7006 cur_channel = 'A'; 7007 swap = cur_channel != channel; 7008 if (channel == 'A') 7009 ahc->our_id = target; 7010 else 7011 ahc->our_id_b = target; 7012 7013 if (swap) 7014 ahc_outb(ahc, SBLKCTL, 7015 sblkctl ^ SELBUSB); 7016 7017 ahc_outb(ahc, SCSIID, target); 7018 7019 if (swap) 7020 ahc_outb(ahc, SBLKCTL, sblkctl); 7021 } 7022 } 7023 } else 7024 ahc->black_hole = lstate; 7025 /* Allow select-in operations */ 7026 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7027 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7028 scsiseq |= ENSELI; 7029 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7030 scsiseq = ahc_inb(ahc, SCSISEQ); 7031 scsiseq |= ENSELI; 7032 ahc_outb(ahc, SCSISEQ, scsiseq); 7033 } 7034 ahc_unpause(ahc); 7035 ahc_unlock(ahc, &s); 7036 ccb->ccb_h.status = CAM_REQ_CMP; 7037 xpt_print_path(ccb->ccb_h.path); 7038 printf("Lun now enabled for target mode\n"); 7039 } else { 7040 struct scb *scb; 7041 int i, empty; 7042 7043 if (lstate == NULL) { 7044 ccb->ccb_h.status = CAM_LUN_INVALID; 7045 return; 7046 } 7047 7048 ahc_lock(ahc, &s); 7049 7050 ccb->ccb_h.status = CAM_REQ_CMP; 7051 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7052 struct ccb_hdr *ccbh; 7053 7054 ccbh = &scb->io_ctx->ccb_h; 7055 if (ccbh->func_code == XPT_CONT_TARGET_IO 7056 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7057 printf("CTIO pending\n"); 7058 ccb->ccb_h.status = CAM_REQ_INVALID; 7059 ahc_unlock(ahc, &s); 7060 return; 7061 } 7062 } 7063 7064 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7065 printf("ATIOs pending\n"); 7066 ccb->ccb_h.status = CAM_REQ_INVALID; 7067 } 7068 7069 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7070 printf("INOTs pending\n"); 7071 ccb->ccb_h.status = CAM_REQ_INVALID; 7072 } 7073 7074 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7075 ahc_unlock(ahc, &s); 7076 return; 7077 } 7078 7079 xpt_print_path(ccb->ccb_h.path); 7080 printf("Target mode disabled\n"); 7081 xpt_free_path(lstate->path); 7082 free(lstate, M_DEVBUF); 7083 7084 ahc_pause(ahc); 7085 /* Can we clean up the target too? */ 7086 if (target != CAM_TARGET_WILDCARD) { 7087 tstate->enabled_luns[lun] = NULL; 7088 ahc->enabled_luns--; 7089 for (empty = 1, i = 0; i < 8; i++) 7090 if (tstate->enabled_luns[i] != NULL) { 7091 empty = 0; 7092 break; 7093 } 7094 7095 if (empty) { 7096 ahc_free_tstate(ahc, target, channel, 7097 /*force*/FALSE); 7098 if (ahc->features & AHC_MULTI_TID) { 7099 u_int targid_mask; 7100 7101 targid_mask = ahc_inb(ahc, TARGID) 7102 | (ahc_inb(ahc, TARGID + 1) 7103 << 8); 7104 7105 targid_mask &= ~target_mask; 7106 ahc_outb(ahc, TARGID, targid_mask); 7107 ahc_outb(ahc, TARGID+1, 7108 (targid_mask >> 8)); 7109 ahc_update_scsiid(ahc, targid_mask); 7110 } 7111 } 7112 } else { 7113 7114 ahc->black_hole = NULL; 7115 7116 /* 7117 * We can't allow selections without 7118 * our black hole device. 7119 */ 7120 empty = TRUE; 7121 } 7122 if (ahc->enabled_luns == 0) { 7123 /* Disallow select-in */ 7124 u_int scsiseq; 7125 7126 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7127 scsiseq &= ~ENSELI; 7128 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7129 scsiseq = ahc_inb(ahc, SCSISEQ); 7130 scsiseq &= ~ENSELI; 7131 ahc_outb(ahc, SCSISEQ, scsiseq); 7132 7133 if ((ahc->features & AHC_MULTIROLE) == 0) { 7134 printf("Configuring Initiator Mode\n"); 7135 ahc->flags &= ~AHC_TARGETROLE; 7136 ahc->flags |= AHC_INITIATORROLE; 7137 ahc_pause(ahc); 7138 ahc_loadseq(ahc); 7139 } 7140 } 7141 ahc_unpause(ahc); 7142 ahc_unlock(ahc, &s); 7143 } 7144 } 7145 7146 static void 7147 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7148 { 7149 u_int scsiid_mask; 7150 u_int scsiid; 7151 7152 if ((ahc->features & AHC_MULTI_TID) == 0) 7153 panic("ahc_update_scsiid called on non-multitid unit\n"); 7154 7155 /* 7156 * Since we will rely on the TARGID mask 7157 * for selection enables, ensure that OID 7158 * in SCSIID is not set to some other ID 7159 * that we don't want to allow selections on. 7160 */ 7161 if ((ahc->features & AHC_ULTRA2) != 0) 7162 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7163 else 7164 scsiid = ahc_inb(ahc, SCSIID); 7165 scsiid_mask = 0x1 << (scsiid & OID); 7166 if ((targid_mask & scsiid_mask) == 0) { 7167 u_int our_id; 7168 7169 /* ffs counts from 1 */ 7170 our_id = ffs(targid_mask); 7171 if (our_id == 0) 7172 our_id = ahc->our_id; 7173 else 7174 our_id--; 7175 scsiid &= TID; 7176 scsiid |= our_id; 7177 } 7178 if ((ahc->features & AHC_ULTRA2) != 0) 7179 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7180 else 7181 ahc_outb(ahc, SCSIID, scsiid); 7182 } 7183 7184 void 7185 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7186 { 7187 struct target_cmd *cmd; 7188 7189 /* 7190 * If the card supports auto-access pause, 7191 * we can access the card directly regardless 7192 * of whether it is paused or not. 7193 */ 7194 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7195 paused = TRUE; 7196 7197 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7198 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7199 7200 /* 7201 * Only advance through the queue if we 7202 * have the resources to process the command. 7203 */ 7204 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7205 break; 7206 7207 cmd->cmd_valid = 0; 7208 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7209 ahc->shared_data_dmamap, 7210 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7211 sizeof(struct target_cmd), 7212 BUS_DMASYNC_PREREAD); 7213 ahc->tqinfifonext++; 7214 7215 /* 7216 * Lazily update our position in the target mode incoming 7217 * command queue as seen by the sequencer. 7218 */ 7219 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7220 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7221 u_int hs_mailbox; 7222 7223 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7224 hs_mailbox &= ~HOST_TQINPOS; 7225 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7226 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7227 } else { 7228 if (!paused) 7229 ahc_pause(ahc); 7230 ahc_outb(ahc, KERNEL_TQINPOS, 7231 ahc->tqinfifonext & HOST_TQINPOS); 7232 if (!paused) 7233 ahc_unpause(ahc); 7234 } 7235 } 7236 } 7237 } 7238 7239 static int 7240 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7241 { 7242 struct ahc_tmode_tstate *tstate; 7243 struct ahc_tmode_lstate *lstate; 7244 struct ccb_accept_tio *atio; 7245 uint8_t *byte; 7246 int initiator; 7247 int target; 7248 int lun; 7249 7250 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7251 target = SCSIID_OUR_ID(cmd->scsiid); 7252 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7253 7254 byte = cmd->bytes; 7255 tstate = ahc->enabled_targets[target]; 7256 lstate = NULL; 7257 if (tstate != NULL) 7258 lstate = tstate->enabled_luns[lun]; 7259 7260 /* 7261 * Commands for disabled luns go to the black hole driver. 7262 */ 7263 if (lstate == NULL) 7264 lstate = ahc->black_hole; 7265 7266 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7267 if (atio == NULL) { 7268 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7269 /* 7270 * Wait for more ATIOs from the peripheral driver for this lun. 7271 */ 7272 if (bootverbose) 7273 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7274 return (1); 7275 } else 7276 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7277 #if 0 7278 printf("Incoming command from %d for %d:%d%s\n", 7279 initiator, target, lun, 7280 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7281 #endif 7282 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7283 7284 if (lstate == ahc->black_hole) { 7285 /* Fill in the wildcards */ 7286 atio->ccb_h.target_id = target; 7287 atio->ccb_h.target_lun = lun; 7288 } 7289 7290 /* 7291 * Package it up and send it off to 7292 * whomever has this lun enabled. 7293 */ 7294 atio->sense_len = 0; 7295 atio->init_id = initiator; 7296 if (byte[0] != 0xFF) { 7297 /* Tag was included */ 7298 atio->tag_action = *byte++; 7299 atio->tag_id = *byte++; 7300 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7301 } else { 7302 atio->ccb_h.flags = 0; 7303 } 7304 byte++; 7305 7306 /* Okay. Now determine the cdb size based on the command code */ 7307 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7308 case 0: 7309 atio->cdb_len = 6; 7310 break; 7311 case 1: 7312 case 2: 7313 atio->cdb_len = 10; 7314 break; 7315 case 4: 7316 atio->cdb_len = 16; 7317 break; 7318 case 5: 7319 atio->cdb_len = 12; 7320 break; 7321 case 3: 7322 default: 7323 /* Only copy the opcode. */ 7324 atio->cdb_len = 1; 7325 printf("Reserved or VU command code type encountered\n"); 7326 break; 7327 } 7328 7329 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7330 7331 atio->ccb_h.status |= CAM_CDB_RECVD; 7332 7333 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7334 /* 7335 * We weren't allowed to disconnect. 7336 * We're hanging on the bus until a 7337 * continue target I/O comes in response 7338 * to this accept tio. 7339 */ 7340 #if 0 7341 printf("Received Immediate Command %d:%d:%d - %p\n", 7342 initiator, target, lun, ahc->pending_device); 7343 #endif 7344 ahc->pending_device = lstate; 7345 ahc_freeze_ccb((union ccb *)atio); 7346 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7347 } 7348 xpt_done((union ccb*)atio); 7349 return (0); 7350 } 7351 #endif 7352 7353 static int 7354 ahc_createdmamem(tag, size, flags, mapp, vaddr, baddr, seg, nseg, myname, what) 7355 bus_dma_tag_t tag; 7356 int size; 7357 int flags; 7358 bus_dmamap_t *mapp; 7359 caddr_t *vaddr; 7360 bus_addr_t *baddr; 7361 bus_dma_segment_t *seg; 7362 int *nseg; 7363 const char *myname, *what; 7364 { 7365 int error, level = 0; 7366 7367 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7368 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7369 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7370 myname, what, error); 7371 goto out; 7372 } 7373 level++; 7374 7375 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7376 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7377 printf("%s: failed to map DMA mem for %s, error = %d\n", 7378 myname, what, error); 7379 goto out; 7380 } 7381 level++; 7382 7383 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7384 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7385 printf("%s: failed to create DMA map for %s, error = %d\n", 7386 myname, what, error); 7387 goto out; 7388 } 7389 level++; 7390 7391 7392 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7393 BUS_DMA_NOWAIT)) != 0) { 7394 printf("%s: failed to load DMA map for %s, error = %d\n", 7395 myname, what, error); 7396 goto out; 7397 } 7398 7399 *baddr = (*mapp)->dm_segs[0].ds_addr; 7400 7401 return 0; 7402 out: 7403 printf("ahc_createdmamem error (%d)\n", level); 7404 switch (level) { 7405 case 3: 7406 bus_dmamap_destroy(tag, *mapp); 7407 /* FALLTHROUGH */ 7408 case 2: 7409 bus_dmamem_unmap(tag, *vaddr, size); 7410 /* FALLTHROUGH */ 7411 case 1: 7412 bus_dmamem_free(tag, seg, *nseg); 7413 break; 7414 default: 7415 break; 7416 } 7417 7418 return error; 7419 } 7420 7421 static void 7422 ahc_freedmamem(tag, size, map, vaddr, seg, nseg) 7423 bus_dma_tag_t tag; 7424 int size; 7425 bus_dmamap_t map; 7426 caddr_t vaddr; 7427 bus_dma_segment_t *seg; 7428 int nseg; 7429 { 7430 7431 bus_dmamap_unload(tag, map); 7432 bus_dmamap_destroy(tag, map); 7433 bus_dmamem_unmap(tag, vaddr, size); 7434 bus_dmamem_free(tag, seg, nseg); 7435 } 7436
Indexes created Wed Oct 01 19:09:53 GMT 2025