aic7xxx_seeprom.c revision 1.3
1 /* $NetBSD: aic7xxx_seeprom.c,v 1.3 2000/06/06 17:29:40 soren Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * 3940, 2940, aic7895, aic7890, aic7880, 6 * aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * These are the SEEPROM-reading functions only. They were split off from 9 * the PCI-specific support by Jason R. Thorpe <thorpej (at) netbsd.org>. 10 * 11 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * the GNU Public License ("GPL"). 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD: src/sys/dev/aic7xxx/ahc_pci.c,v 1.27 2000/01/10 01:47:51 gibbs Exp 39 $ 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/queue.h> 47 #include <sys/device.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 57 #include <dev/ic/aic7xxxvar.h> 58 #include <dev/ic/smc93cx6var.h> 59 60 #ifdef DEBUG 61 #define bootverbose 1 62 #else 63 #define bootverbose 0 64 #endif 65 66 static void configure_termination(struct ahc_softc *, 67 struct seeprom_descriptor *, u_int, u_int *); 68 69 static void ahc_new_term_detect(struct ahc_softc *, int *, int *, int *, 70 int *, int *); 71 static void aic787X_cable_detect(struct ahc_softc *, int *, int *, int *, 72 int *); 73 static void aic785X_cable_detect(struct ahc_softc *, int *, int *, int *); 74 static int acquire_seeprom(struct ahc_softc *, struct seeprom_descriptor *); 75 static void release_seeprom(struct seeprom_descriptor *); 76 static void write_brdctl(struct ahc_softc *, u_int8_t); 77 static u_int8_t read_brdctl(struct ahc_softc *); 78 79 /* 80 * Check the external port logic for a serial eeprom 81 * and termination/cable detection contrls. 82 */ 83 void 84 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 85 { 86 struct seeprom_descriptor sd; 87 struct seeprom_config sc; 88 u_int scsi_conf; 89 u_int adapter_control; 90 int have_seeprom; 91 int have_autoterm; 92 93 sd.sd_tag = ahc->tag; 94 sd.sd_bsh = ahc->bsh; 95 sd.sd_control_offset = SEECTL; 96 sd.sd_status_offset = SEECTL; 97 sd.sd_dataout_offset = SEECTL; 98 99 /* 100 * For some multi-channel devices, the c46 is simply too 101 * small to work. For the other controller types, we can 102 * get our information from either SEEPROM type. Set the 103 * type to start our probe with accordingly. 104 */ 105 if (ahc->flags & AHC_LARGE_SEEPROM) 106 sd.sd_chip = C56_66; 107 else 108 sd.sd_chip = C46; 109 110 sd.sd_MS = SEEMS; 111 sd.sd_RDY = SEERDY; 112 sd.sd_CS = SEECS; 113 sd.sd_CK = SEECK; 114 sd.sd_DO = SEEDO; 115 sd.sd_DI = SEEDI; 116 117 have_seeprom = acquire_seeprom(ahc, &sd); 118 if (have_seeprom) { 119 120 if (bootverbose) 121 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 122 123 for (;;) { 124 bus_size_t start_addr; 125 126 start_addr = 32 * (ahc->channel - 'A'); 127 128 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 129 start_addr, sizeof(sc)/2); 130 131 if (have_seeprom) { 132 /* Check checksum */ 133 int i; 134 int maxaddr; 135 u_int32_t checksum; 136 u_int16_t *scarray; 137 138 maxaddr = (sizeof(sc)/2) - 1; 139 checksum = 0; 140 scarray = (u_int16_t *)≻ 141 142 for (i = 0; i < maxaddr; i++) 143 checksum = checksum + scarray[i]; 144 if (checksum == 0 145 || (checksum & 0xFFFF) != sc.checksum) { 146 if (bootverbose && sd.sd_chip == C56_66) 147 printf ("checksum error\n"); 148 have_seeprom = 0; 149 } else { 150 if (bootverbose) 151 printf("done.\n"); 152 break; 153 } 154 } 155 156 if (sd.sd_chip == C56_66) 157 break; 158 sd.sd_chip = C56_66; 159 } 160 } 161 162 if (!have_seeprom) { 163 if (bootverbose) 164 printf("%s: No SEEPROM available\n", ahc_name(ahc)); 165 ahc->flags |= AHC_USEDEFAULTS; 166 } else { 167 /* 168 * Put the data we've collected down into SRAM 169 * where ahc_init will find it. 170 */ 171 int i; 172 int max_targ = sc.max_targets & CFMAXTARG; 173 u_int16_t discenable; 174 u_int16_t ultraenb; 175 176 discenable = 0; 177 ultraenb = 0; 178 if ((sc.adapter_control & CFULTRAEN) != 0) { 179 /* 180 * Determine if this adapter has a "newstyle" 181 * SEEPROM format. 182 */ 183 for (i = 0; i < max_targ; i++) { 184 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 185 ahc->flags |= AHC_NEWEEPROM_FMT; 186 break; 187 } 188 } 189 } 190 191 for (i = 0; i < max_targ; i++) { 192 u_int scsirate; 193 u_int16_t target_mask; 194 195 target_mask = 0x01 << i; 196 if (sc.device_flags[i] & CFDISC) 197 discenable |= target_mask; 198 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 199 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 200 ultraenb |= target_mask; 201 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 202 ultraenb |= target_mask; 203 } 204 if ((sc.device_flags[i] & CFXFER) == 0x04 205 && (ultraenb & target_mask) != 0) { 206 /* Treat 10MHz as a non-ultra speed */ 207 sc.device_flags[i] &= ~CFXFER; 208 ultraenb &= ~target_mask; 209 } 210 if ((ahc->features & AHC_ULTRA2) != 0) { 211 u_int offset; 212 213 if (sc.device_flags[i] & CFSYNCH) 214 offset = MAX_OFFSET_ULTRA2; 215 else 216 offset = 0; 217 ahc_outb(ahc, TARG_OFFSET + i, offset); 218 219 scsirate = (sc.device_flags[i] & CFXFER) 220 | ((ultraenb & target_mask) 221 ? 0x8 : 0x0); 222 if (sc.device_flags[i] & CFWIDEB) 223 scsirate |= WIDEXFER; 224 } else { 225 scsirate = (sc.device_flags[i] & CFXFER) << 4; 226 if (sc.device_flags[i] & CFSYNCH) 227 scsirate |= SOFS; 228 if (sc.device_flags[i] & CFWIDEB) 229 scsirate |= WIDEXFER; 230 } 231 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 232 } 233 ahc->our_id = sc.brtime_id & CFSCSIID; 234 235 scsi_conf = (ahc->our_id & 0x7); 236 if (sc.adapter_control & CFSPARITY) 237 scsi_conf |= ENSPCHK; 238 if (sc.adapter_control & CFRESETB) 239 scsi_conf |= RESET_SCSI; 240 241 if (sc.bios_control & CFEXTEND) 242 ahc->flags |= AHC_EXTENDED_TRANS_A; 243 if (ahc->features & AHC_ULTRA 244 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 245 /* Should we enable Ultra mode? */ 246 if (!(sc.adapter_control & CFULTRAEN)) 247 /* Treat us as a non-ultra card */ 248 ultraenb = 0; 249 } 250 /* Set SCSICONF info */ 251 ahc_outb(ahc, SCSICONF, scsi_conf); 252 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 253 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 254 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 255 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 256 } 257 258 /* 259 * Cards that have the external logic necessary to talk to 260 * a SEEPROM, are almost certain to have the remaining logic 261 * necessary for auto-termination control. This assumption 262 * hasn't failed yet... 263 */ 264 have_autoterm = have_seeprom; 265 if (have_seeprom) 266 adapter_control = sc.adapter_control; 267 else 268 adapter_control = CFAUTOTERM; 269 270 /* 271 * Some low-cost chips have SEEPROM and auto-term control built 272 * in, instead of using a GAL. They can tell us directly 273 * if the termination logic is enabled. 274 */ 275 if ((ahc->features & AHC_SPIOCAP) != 0) { 276 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 277 have_autoterm = TRUE; 278 else 279 have_autoterm = FALSE; 280 } 281 282 if (have_autoterm) 283 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 284 285 release_seeprom(&sd); 286 } 287 288 static void 289 configure_termination(struct ahc_softc *ahc, 290 struct seeprom_descriptor *sd, 291 u_int adapter_control, 292 u_int *sxfrctl1) 293 { 294 u_int8_t brddat; 295 296 brddat = 0; 297 298 /* 299 * Update the settings in sxfrctl1 to match the 300 * termination settings 301 */ 302 *sxfrctl1 = 0; 303 304 /* 305 * SEECS must be on for the GALS to latch 306 * the data properly. Be sure to leave MS 307 * on or we will release the seeprom. 308 */ 309 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 310 if ((adapter_control & CFAUTOTERM) != 0 311 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 312 int internal50_present; 313 int internal68_present; 314 int externalcable_present; 315 int eeprom_present; 316 int enableSEC_low; 317 int enableSEC_high; 318 int enablePRI_low; 319 int enablePRI_high; 320 321 enableSEC_low = 0; 322 enableSEC_high = 0; 323 enablePRI_low = 0; 324 enablePRI_high = 0; 325 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 326 ahc_new_term_detect(ahc, &enableSEC_low, 327 &enableSEC_high, 328 &enablePRI_low, 329 &enablePRI_high, 330 &eeprom_present); 331 if ((adapter_control & CFSEAUTOTERM) == 0) { 332 if (bootverbose) 333 printf("%s: Manual SE Termination\n", 334 ahc_name(ahc)); 335 enableSEC_low = (adapter_control & CFSTERM); 336 enableSEC_high = (adapter_control & CFWSTERM); 337 } 338 if ((adapter_control & CFAUTOTERM) == 0) { 339 if (bootverbose) 340 printf("%s: Manual LVD Termination\n", 341 ahc_name(ahc)); 342 enablePRI_low = enablePRI_high = 343 (adapter_control & CFLVDSTERM); 344 } 345 /* Make the table calculations below happy */ 346 internal50_present = 0; 347 internal68_present = 1; 348 externalcable_present = 1; 349 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 350 aic785X_cable_detect(ahc, &internal50_present, 351 &externalcable_present, 352 &eeprom_present); 353 } else { 354 aic787X_cable_detect(ahc, &internal50_present, 355 &internal68_present, 356 &externalcable_present, 357 &eeprom_present); 358 } 359 360 if ((ahc->features & AHC_WIDE) == 0) 361 internal68_present = 0; 362 363 if (bootverbose) { 364 if ((ahc->features & AHC_ULTRA2) == 0) { 365 printf("%s: internal 50 cable %s present, " 366 "internal 68 cable %s present\n", 367 ahc_name(ahc), 368 internal50_present ? "is":"not", 369 internal68_present ? "is":"not"); 370 371 printf("%s: external cable %s present\n", 372 ahc_name(ahc), 373 externalcable_present ? "is":"not"); 374 } 375 printf("%s: BIOS eeprom %s present\n", 376 ahc_name(ahc), eeprom_present ? "is" : "not"); 377 } 378 379 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 380 /* 381 * The 50 pin connector is a separate bus, 382 * so force it to always be terminated. 383 * In the future, perform current sensing 384 * to determine if we are in the middle of 385 * a properly terminated bus. 386 */ 387 internal50_present = 0; 388 } 389 390 /* 391 * Now set the termination based on what 392 * we found. 393 * Flash Enable = BRDDAT7 394 * Secondary High Term Enable = BRDDAT6 395 * Secondary Low Term Enable = BRDDAT5 (7890) 396 * Primary High Term Enable = BRDDAT4 (7890) 397 */ 398 if ((ahc->features & AHC_ULTRA2) == 0 399 && (internal50_present != 0) 400 && (internal68_present != 0) 401 && (externalcable_present != 0)) { 402 printf("%s: Illegal cable configuration!!. " 403 "Only two connectors on the " 404 "adapter may be used at a " 405 "time!\n", ahc_name(ahc)); 406 } 407 408 if ((ahc->features & AHC_WIDE) != 0 409 && ((externalcable_present == 0) 410 || (internal68_present == 0) 411 || (enableSEC_high != 0))) { 412 brddat |= BRDDAT6; 413 if (bootverbose) { 414 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 415 printf("%s: 68 pin termination " 416 "Enabled\n", ahc_name(ahc)); 417 else 418 printf("%s: %sHigh byte termination " 419 "Enabled\n", ahc_name(ahc), 420 enableSEC_high ? "Secondary " 421 : ""); 422 } 423 } 424 425 if (((internal50_present ? 1 : 0) 426 + (internal68_present ? 1 : 0) 427 + (externalcable_present ? 1 : 0)) <= 1 428 || (enableSEC_low != 0)) { 429 if ((ahc->features & AHC_ULTRA2) != 0) 430 brddat |= BRDDAT5; 431 else 432 *sxfrctl1 |= STPWEN; 433 if (bootverbose) { 434 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 435 printf("%s: 50 pin termination " 436 "Enabled\n", ahc_name(ahc)); 437 else 438 printf("%s: %sLow byte termination " 439 "Enabled\n", ahc_name(ahc), 440 enableSEC_low ? "Secondary " 441 : ""); 442 } 443 } 444 445 if (enablePRI_low != 0) { 446 *sxfrctl1 |= STPWEN; 447 if (bootverbose) 448 printf("%s: Primary Low Byte termination " 449 "Enabled\n", ahc_name(ahc)); 450 } 451 452 /* 453 * Setup STPWEN before setting up the rest of 454 * the termination per the tech note on the U160 cards. 455 */ 456 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 457 458 if (enablePRI_high != 0) { 459 brddat |= BRDDAT4; 460 if (bootverbose) 461 printf("%s: Primary High Byte " 462 "termination Enabled\n", 463 ahc_name(ahc)); 464 } 465 466 write_brdctl(ahc, brddat); 467 468 } else { 469 if ((adapter_control & CFSTERM) != 0) { 470 *sxfrctl1 |= STPWEN; 471 472 if (bootverbose) 473 printf("%s: %sLow byte termination Enabled\n", 474 ahc_name(ahc), 475 (ahc->features & AHC_ULTRA2) ? "Primary " 476 : ""); 477 } 478 479 if ((adapter_control & CFWSTERM) != 0) { 480 brddat |= BRDDAT6; 481 if (bootverbose) 482 printf("%s: %sHigh byte termination Enabled\n", 483 ahc_name(ahc), 484 (ahc->features & AHC_ULTRA2) 485 ? "Secondary " : ""); 486 } 487 488 /* 489 * Setup STPWEN before setting up the rest of 490 * the termination per the tech note on the U160 cards. 491 */ 492 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 493 494 write_brdctl(ahc, brddat); 495 } 496 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 497 } 498 499 static void 500 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 501 int *enableSEC_high, int *enablePRI_low, 502 int *enablePRI_high, int *eeprom_present) 503 { 504 u_int8_t brdctl; 505 506 /* 507 * BRDDAT7 = Eeprom 508 * BRDDAT6 = Enable Secondary High Byte termination 509 * BRDDAT5 = Enable Secondary Low Byte termination 510 * BRDDAT4 = Enable Primary high byte termination 511 * BRDDAT3 = Enable Primary low byte termination 512 */ 513 brdctl = read_brdctl(ahc); 514 *eeprom_present = brdctl & BRDDAT7; 515 *enableSEC_high = (brdctl & BRDDAT6); 516 *enableSEC_low = (brdctl & BRDDAT5); 517 *enablePRI_high = (brdctl & BRDDAT4); 518 *enablePRI_low = (brdctl & BRDDAT3); 519 } 520 521 static void 522 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 523 int *internal68_present, int *externalcable_present, 524 int *eeprom_present) 525 { 526 u_int8_t brdctl; 527 528 /* 529 * First read the status of our cables. 530 * Set the rom bank to 0 since the 531 * bank setting serves as a multiplexor 532 * for the cable detection logic. 533 * BRDDAT5 controls the bank switch. 534 */ 535 write_brdctl(ahc, 0); 536 537 /* 538 * Now read the state of the internal 539 * connectors. BRDDAT6 is INT50 and 540 * BRDDAT7 is INT68. 541 */ 542 brdctl = read_brdctl(ahc); 543 *internal50_present = !(brdctl & BRDDAT6); 544 *internal68_present = !(brdctl & BRDDAT7); 545 546 /* 547 * Set the rom bank to 1 and determine 548 * the other signals. 549 */ 550 write_brdctl(ahc, BRDDAT5); 551 552 /* 553 * Now read the state of the external 554 * connectors. BRDDAT6 is EXT68 and 555 * BRDDAT7 is EPROMPS. 556 */ 557 brdctl = read_brdctl(ahc); 558 *externalcable_present = !(brdctl & BRDDAT6); 559 *eeprom_present = brdctl & BRDDAT7; 560 } 561 562 static void 563 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 564 int *externalcable_present, int *eeprom_present) 565 { 566 u_int8_t brdctl; 567 568 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 569 ahc_outb(ahc, BRDCTL, 0); 570 brdctl = ahc_inb(ahc, BRDCTL); 571 *internal50_present = !(brdctl & BRDDAT5); 572 *externalcable_present = !(brdctl & BRDDAT6); 573 574 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 575 } 576 577 static int 578 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 579 { 580 int wait; 581 582 if ((ahc->features & AHC_SPIOCAP) != 0 583 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 584 return (0); 585 586 /* 587 * Request access of the memory port. When access is 588 * granted, SEERDY will go high. We use a 100 msec 589 * timeout which should be near 100 msecs more than 590 * is needed. Reason: after the chip reset, there 591 * should be no contention. 592 */ 593 SEEPROM_OUTB(sd, sd->sd_MS); 594 wait = 100; /* 100 msec timeout */ 595 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 596 DELAY(1000); /* delay 1 msec */ 597 } 598 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 599 SEEPROM_OUTB(sd, 0); 600 return (0); 601 } 602 return(1); 603 } 604 605 static void 606 release_seeprom(sd) 607 struct seeprom_descriptor *sd; 608 { 609 /* Release access to the memory port and the serial EEPROM. */ 610 SEEPROM_OUTB(sd, 0); 611 } 612 613 static void 614 write_brdctl(ahc, value) 615 struct ahc_softc *ahc; 616 u_int8_t value; 617 { 618 u_int8_t brdctl; 619 620 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 621 brdctl = BRDSTB; 622 if (ahc->channel == 'B') 623 brdctl |= BRDCS; 624 } else if ((ahc->features & AHC_ULTRA2) != 0) { 625 brdctl = 0; 626 } else { 627 brdctl = BRDSTB|BRDCS; 628 } 629 ahc_outb(ahc, BRDCTL, brdctl); 630 DELAY(20); 631 brdctl |= value; 632 ahc_outb(ahc, BRDCTL, brdctl); 633 DELAY(20); 634 if ((ahc->features & AHC_ULTRA2) != 0) 635 brdctl |= BRDSTB_ULTRA2; 636 else 637 brdctl &= ~BRDSTB; 638 ahc_outb(ahc, BRDCTL, brdctl); 639 DELAY(20); 640 if ((ahc->features & AHC_ULTRA2) != 0) 641 brdctl = 0; 642 else 643 brdctl &= ~BRDCS; 644 ahc_outb(ahc, BRDCTL, brdctl); 645 } 646 647 static u_int8_t 648 read_brdctl(ahc) 649 struct ahc_softc *ahc; 650 { 651 u_int8_t brdctl; 652 u_int8_t value; 653 654 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 655 brdctl = BRDRW; 656 if (ahc->channel == 'B') 657 brdctl |= BRDCS; 658 } else if ((ahc->features & AHC_ULTRA2) != 0) { 659 brdctl = BRDRW_ULTRA2; 660 } else { 661 brdctl = BRDRW|BRDCS; 662 } 663 ahc_outb(ahc, BRDCTL, brdctl); 664 DELAY(20); 665 value = ahc_inb(ahc, BRDCTL); 666 ahc_outb(ahc, BRDCTL, 0); 667 return (value); 668 } 669
Indexes created Tue Sep 30 17:09:57 GMT 2025