aic7xxxvar.h revision 1.1
1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Absolutely no warranty of function or purpose is made by the author 19 * Justin T. Gibbs. 20 * 4. Modifications may be freely made to this file if the above conditions 21 * are met. 22 * 23 * $Id: aic7xxxvar.h,v 1.1 1995/10/09 09:49:31 mycroft Exp $ 24 */ 25 26 #ifndef _AIC7XXX_H_ 27 #define _AIC7XXX_H_ 28 29 /*#include "ahc.h" /* for NAHC from config */ 30 31 #define AHC_NSEG 256 /* number of dma segments supported */ 32 33 #define AHC_SCB_MAX 16 /* 34 * Up to 16 SCBs on some types of aic7xxx based 35 * boards. The aic7770 family only have 4 36 */ 37 38 /* #define AHCDEBUG */ 39 40 typedef u_long physaddr; 41 typedef u_long physlen; 42 43 struct ahc_dma_seg { 44 physaddr seg_addr; 45 physlen seg_len; 46 }; 47 48 typedef u_char ahc_type; 49 #define AHC_NONE 0x00 50 #define AHC_WIDE 0x02 /* Wide Channel */ 51 #define AHC_TWIN 0x08 /* Twin Channel */ 52 #define AHC_274 0x10 /* EISA Based Controller */ 53 #define AHC_284 0x20 /* VL/ISA Based Controller */ 54 #define AHC_AIC7870 0x40 /* PCI Based Controller */ 55 #define AHC_294 0xc0 /* PCI Based Controller */ 56 57 /* 58 * The driver keeps up to MAX_SCB scb structures per card in memory. Only the 59 * first 26 bytes of the structure are valid for the hardware, the rest used 60 * for driver level bookeeping. The "__attribute ((packed))" tags ensure that 61 * gcc does not attempt to pad the long ints in the structure to word 62 * boundaries since the first 26 bytes of this structure must have the correct 63 * offsets for the hardware to find them. The driver is further optimized 64 * so that we only have to download the first 19 bytes since as long 65 * as we always use S/G, the last fields should be zero anyway. 66 */ 67 #if __GNUC__ >= 2 68 #if __GNUC_MINOR__ <5 69 #pragma pack(1) 70 #endif 71 #endif 72 73 struct ahc_scb { 74 /* ------------ Begin hardware supported fields ---------------- */ 75 /*1*/ u_char control; 76 #define SCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */ 77 #define SCB_NEEDSDTR 0x40 /* Initiate Sync Negotiation */ 78 #define SCB_TE 0x20 /* Tag enable */ 79 #define SCB_NEEDDMA 0x08 /* Refresh SCB from host ram */ 80 #define SCB_DIS 0x04 81 #define SCB_TAG_TYPE 0x3 82 #define SIMPLE_QUEUE 0x0 83 #define HEAD_QUEUE 0x1 84 #define OR_QUEUE 0x2 85 /*2*/ u_char target_channel_lun; /* 4/1/3 bits */ 86 /*3*/ u_char SG_segment_count; 87 /*7*/ physaddr SG_list_pointer __attribute__ ((packed)); 88 /*11*/ physaddr cmdpointer __attribute__ ((packed)); 89 /*12*/ u_char cmdlen; 90 /*14*/ u_char RESERVED[2]; /* must be zero */ 91 /*15*/ u_char target_status; 92 /*18*/ u_char residual_data_count[3]; 93 /*19*/ u_char residual_SG_segment_count; 94 #define SCB_DOWN_SIZE 19 /* amount to actually download */ 95 #define SCB_BZERO_SIZE 19 /* 96 * amount we need to clear between 97 * commands 98 */ 99 /*23*/ physaddr data __attribute__ ((packed)); 100 /*26*/ u_char datalen[3]; 101 #define SCB_UP_SIZE 26 /* 102 * amount we need to upload to perform 103 * a request sense. 104 */ 105 /*30*/ physaddr host_scb __attribute__ ((packed)); 106 /*31*/ u_char next_waiting; /* Used to thread SCBs awaiting 107 * selection 108 */ 109 #define SCB_LIST_NULL 0x10 /* SCB list equivelent to NULL */ 110 #if 0 111 /* 112 * No real point in transferring this to the 113 * SCB registers. 114 */ 115 unsigned char RESERVED[1]; 116 #endif 117 /*-----------------end of hardware supported fields----------------*/ 118 TAILQ_ENTRY(ahc_scb) chain; 119 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 120 int flags; 121 #define SCB_FREE 0 122 #define SCB_ACTIVE 1 123 #define SCB_ABORTED 2 124 #define SCB_CHKSENSE 3 125 #define SCB_IMMED 4 126 #define SCB_IMMED_FAIL 8 127 int position; /* Position in scbarray */ 128 struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed)); 129 struct scsi_sense sense_cmd; /* SCSI command block */ 130 }; 131 132 #if __GNUC__ >= 2 133 #if __GNUC_MINOR__ <5 134 #pragma pack(4) 135 #endif 136 #endif 137 138 struct ahc_softc { 139 struct device sc_dev; 140 void *sc_ih; 141 142 int sc_iobase; 143 int sc_irq; 144 145 ahc_type type; 146 147 struct ahc_scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */ 148 TAILQ_HEAD(, ahc_scb) free_scb; 149 int ahc_scsi_dev; /* our scsi id */ 150 int ahc_scsi_dev_b; /* B channel scsi id */ 151 struct ahc_scb *immed_ecb; /* an outstanding immediete command */ 152 struct scsi_link sc_link; 153 struct scsi_link sc_link_b; /* Second bus for Twin channel cards */ 154 u_short needsdtr_orig; /* Targets we initiate sync neg with */ 155 u_short needwdtr_orig; /* Targets we initiate wide neg with */ 156 u_short needsdtr; /* Current list of negotiated targets */ 157 u_short needwdtr; /* Current list of negotiated targets */ 158 u_short sdtrpending; /* Pending SDTR to these targets */ 159 u_short wdtrpending; /* Pending WDTR to these targets */ 160 u_short tagenable; /* Targets that can handle tagqueing */ 161 int numscbs; 162 int activescbs; 163 u_char maxscbs; 164 u_char unpause; 165 u_char pause; 166 }; 167 168 #endif /* _AIC7XXX_H_ */ 169
Indexes created Tue Sep 30 17:09:57 GMT 2025