aic7xxxvar.h revision 1.23
1 /* $NetBSD: aic7xxxvar.h,v 1.23 2000/05/22 21:14:26 fvdl Exp $ */ 2 3 /* 4 * Interface to the generic driver for the aic7xxx based adaptec 5 * SCSI controllers. This is used to implement product specific 6 * probe and attach routines. 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.16 2000/02/09 21:24:59 gibbs Exp $ 36 */ 37 38 #ifndef _AIC7XXX_H_ 39 #define _AIC7XXX_H_ 40 41 #ifndef MAX 42 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 43 #endif 44 45 #ifndef MIN 46 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 47 #endif 48 49 #ifndef FALSE 50 #define FALSE 0 51 #endif 52 53 #ifndef TRUE 54 #define TRUE 1 55 #endif 56 57 /* 58 * The maximum transfer per S/G segment. 59 */ 60 #define AHC_MAXTRANSFER_SIZE ctob(AHC_NSEG - 1) 61 62 /* 63 * Convert FreeBSD queue macro 64 */ 65 #define STAILQ_ENTRY SIMPLEQ_ENTRY 66 67 /* 68 * The number of dma segments supported. The current implementation limits 69 * us to 255 S/G entries (this may change to be unlimited at some point). 70 * To reduce the driver's memory consumption, we further limit the number 71 * supported to be sufficient to handle the largest mapping supported by 72 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 73 * and unaligned, this turns out to be the number of paged sized transfers 74 * in MAXPHYS plus an extra element to handle any unaligned residual. 75 */ 76 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 77 78 #define AHC_SCB_MAX 255 /* 79 * Up to 255 SCBs on some types of aic7xxx 80 * based boards. The aic7870 have 16 internal 81 * SCBs, but external SRAM bumps this to 255. 82 * The aic7770 family have only 4, and the 83 * aic7850 has only 3. 84 */ 85 86 #define AHC_TMODE_CMDS 256 /* 87 * Ring Buffer of incoming target commands. 88 * We allocate 256 to simplify the logic 89 * in the sequencer by using the natural 90 * wrap point of an 8bit counter. 91 */ 92 93 struct ahc_dma_seg { 94 u_int32_t addr; 95 u_int32_t len; 96 }; 97 98 typedef enum { 99 AHC_NONE = 0x0000, 100 AHC_CHIPID_MASK = 0x00FF, 101 AHC_AIC7770 = 0x0001, 102 AHC_AIC7850 = 0x0002, 103 AHC_AIC7855 = 0x0003, 104 AHC_AIC7859 = 0x0004, 105 AHC_AIC7860 = 0x0005, 106 AHC_AIC7870 = 0x0006, 107 AHC_AIC7880 = 0x0007, 108 AHC_AIC7890 = 0x0008, 109 AHC_AIC7892 = 0x0009, 110 AHC_AIC7895 = 0x000a, 111 AHC_AIC7896 = 0x000b, 112 AHC_AIC7899 = 0x000c, 113 AHC_VL = 0x0100, /* Bus type VL */ 114 AHC_EISA = 0x0200, /* Bus type EISA */ 115 AHC_PCI = 0x0400, /* Bus type PCI */ 116 AHC_BUS_MASK = 0x0F00 117 } ahc_chip; 118 119 extern char *ahc_chip_names[]; 120 121 typedef enum { 122 AHC_FENONE = 0x0000, 123 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 124 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 125 AHC_WIDE = 0x0004, /* Wide Channel */ 126 AHC_TWIN = 0x0008, /* Twin Channel */ 127 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 128 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 129 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 130 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 131 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 132 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 133 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 134 AHC_DT = 0x0800, /* Double Transition transfers */ 135 AHC_NEW_TERMCTL = 0x1000, 136 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 137 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 138 AHC_AIC7770_FE = AHC_TARG_DMABUG, 139 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 140 AHC_AIC7855_FE = AHC_AIC7850_FE, 141 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 142 AHC_AIC7860_FE = AHC_AIC7859_FE, 143 AHC_AIC7870_FE = AHC_TARG_DMABUG, 144 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 145 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 146 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 147 |AHC_NEW_TERMCTL, 148 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 149 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 150 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 151 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 152 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 153 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 154 } ahc_feature; 155 156 typedef enum { 157 AHC_FNONE = 0x000, 158 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 159 AHC_CHANNEL_B_PRIMARY = 0x002,/* 160 * On twin channel adapters, probe 161 * channel B first since it is the 162 * primary bus. 163 */ 164 AHC_USEDEFAULTS = 0x004,/* 165 * For cards without an seeprom 166 * or a BIOS to initialize the chip's 167 * SRAM, we use the default target 168 * settings. 169 */ 170 AHC_SHARED_SRAM = 0x010, 171 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 172 AHC_RESET_BUS_A = 0x040, 173 AHC_RESET_BUS_B = 0x080, 174 AHC_EXTENDED_TRANS_A = 0x100, 175 AHC_EXTENDED_TRANS_B = 0x200, 176 AHC_TERM_ENB_A = 0x400, 177 AHC_TERM_ENB_B = 0x800, 178 AHC_INITIATORMODE = 0x1000,/* 179 * Allow initiator operations on 180 * this controller. 181 */ 182 AHC_TARGETMODE = 0x2000,/* 183 * Allow target operations on this 184 * controller. 185 */ 186 AHC_NEWEEPROM_FMT = 0x4000, 187 AHC_RESOURCE_SHORTAGE = 0x8000, 188 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 189 AHC_INT50_SPEEDFLEX = 0x20000,/* 190 * Internal 50pin connector 191 * sits behind an aic3860 192 */ 193 } ahc_flag; 194 195 typedef enum { 196 SCB_FREE = 0x0000, 197 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 198 * Another device was active 199 * during the first timeout for 200 * this SCB so we gave ourselves 201 * an additional timeout period 202 * in case it was hogging the 203 * bus. 204 */ 205 SCB_DEVICE_RESET = 0x0004, 206 SCB_SENSE = 0x0008, 207 SCB_FREEZE_QUEUE = 0x0010, 208 SCB_REQUEUE = 0x0020, 209 SCB_RECOVERY_SCB = 0x0040, 210 SCB_ABORT = 0x1000, 211 SCB_QUEUED_MSG = 0x2000, 212 SCB_ACTIVE = 0x4000, 213 SCB_TARGET_IMMEDIATE = 0x8000 214 } scb_flag; 215 216 typedef enum { 217 MSGLOOP_IN_PROG, 218 MSGLOOP_MSGCOMPLETE, 219 MSGLOOP_TERMINATED 220 } msg_loop_stat; 221 222 /* 223 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 224 * consists of a "hardware SCB" mirroring the fields availible on the card 225 * and additional information the kernel stores for each transaction. 226 */ 227 struct hardware_scb { 228 /*0*/ u_int8_t control; 229 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 230 /*2*/ u_int8_t status; 231 /*3*/ u_int8_t SG_count; 232 /*4*/ u_int32_t SG_pointer; 233 /*8*/ u_int8_t residual_SG_count; 234 /*9*/ u_int8_t residual_data_count[3]; 235 /*12*/ u_int32_t data; 236 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 237 * faster to treat it as a long on 238 * a quad boundary. 239 */ 240 /*20*/ u_int32_t cmdpointer; 241 /*24*/ u_int8_t cmdlen; 242 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 243 * Also used as the tag for tagged I/O 244 */ 245 /*26*/ u_int8_t next; /* Used for threading SCBs in the 246 * "Waiting for Selection" and 247 * "Disconnected SCB" lists down 248 * in the sequencer. 249 */ 250 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 251 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 252 /*29*/ u_int8_t spare[3]; /* 253 * Spare space available on 254 * all controller types. 255 */ 256 /*32*/ u_int8_t cmdstore[16]; /* 257 * CDB storage for controllers 258 * supporting 64 byte SCBs. 259 */ 260 /*48*/ u_int32_t cmdstore_busaddr; /* 261 * Address of command store for 262 * 32byte SCB adapters 263 */ 264 /*48*/ u_int8_t spare_64[12]; /* 265 * Pad to 64 bytes. 266 */ 267 }; 268 269 struct scb { 270 struct hardware_scb *hscb; 271 SLIST_ENTRY(scb) links; /* for chaining */ 272 LIST_ENTRY(scb) plinks; /* pending chain */ 273 struct scsipi_xfer *xs; 274 scb_flag flags; 275 bus_dmamap_t dmamap; 276 struct ahc_dma_seg *sg_list; 277 bus_addr_t sg_list_phys; 278 u_int sg_count;/* How full ahc_dma_seg is */ 279 }; 280 281 /* 282 * Connection desciptor for select-in requests in target mode. 283 * The first byte is the connecting target, followed by identify 284 * message and optional tag information, terminated by 0xFF. The 285 * remainder is the command to execute. The cmd_valid byte is on 286 * an 8 byte boundary to simplify setting it on aic7880 hardware 287 * which only has limited direct access to the DMA FIFO. 288 */ 289 struct target_cmd { 290 u_int8_t initiator_channel; 291 u_int8_t targ_id; /* Target ID we were selected at */ 292 u_int8_t identify; /* Identify message */ 293 u_int8_t bytes[21]; 294 u_int8_t cmd_valid; 295 u_int8_t pad[7]; 296 }; 297 298 /* 299 * Number of events we can buffer up if we run out 300 * of immediate notify ccbs. 301 */ 302 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 303 struct ahc_tmode_event { 304 u_int8_t initiator_id; 305 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 306 #define EVENT_TYPE_BUS_RESET 0xFF 307 u_int8_t event_arg; 308 }; 309 310 /* 311 * Per lun target mode state including accept TIO CCB 312 * and immediate notify CCB pools. 313 */ 314 struct tmode_lstate { 315 #ifdef maybe_later 316 struct cam_path *path; 317 struct ccb_hdr_slist accept_tios; 318 struct ccb_hdr_slist immed_notifies; 319 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 320 u_int8_t event_r_idx; 321 u_int8_t event_w_idx; 322 #else 323 u_int8_t dummy; 324 #endif 325 }; 326 327 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 328 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 329 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 330 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 331 332 struct ahc_transinfo { 333 u_int8_t width; 334 u_int8_t period; 335 u_int8_t offset; 336 u_int8_t ppr_flags; 337 }; 338 339 struct ahc_initiator_tinfo { 340 u_int8_t scsirate; 341 struct ahc_transinfo current; 342 struct ahc_transinfo goal; 343 struct ahc_transinfo user; 344 }; 345 346 /* 347 * Per target mode enabled target state. Esentially just an array of 348 * pointers to lun target state as well as sync/wide negotiation information 349 * for each initiator<->target mapping (including the mapping for when we 350 * are the initiator). 351 */ 352 struct tmode_tstate { 353 #if 0 354 struct tmode_lstate* enabled_luns[8]; 355 #endif 356 struct ahc_initiator_tinfo transinfo[16]; 357 358 /* 359 * Per initiator state bitmasks. 360 */ 361 u_int16_t ultraenb; /* Using ultra sync rate */ 362 u_int16_t discenable; /* Disconnection allowed */ 363 u_int16_t tagenable; /* Tagged Queuing allowed */ 364 u_int16_t tagdisable; /* TQ explicity disallowed */ 365 }; 366 367 #define AHC_TARGET_WILDCARD -1 368 #define AHC_LUN_WILDCARD -1 369 370 /* 371 * XXX translate FreeBSD SCSI status byte values to NetBSD, and define 372 * a few more. 373 */ 374 #define SCSI_STATUS_OK SCSI_OK 375 #define SCSI_STATUS_CHECK_COND SCSI_CHECK 376 #define SCSI_STATUS_COND_MET 0x04 377 #define SCSI_STATUS_BUSY SCSI_BUSY 378 #define SCSI_STATUS_INTERMED SCSI_INTERM 379 #define SCSI_STATUS_INTERMED_COND_MET 0x14 380 #define SCSI_STATUS_RESERV_CONFLICT 0x18 381 #define SCSI_STATUS_CMD_TERMINATED 0x22 382 #define SCSI_STATUS_QUEUE_FULL SCSI_QUEUE_FULL 383 384 /* 385 * Define the format of the aic7XXX SEEPROM registers (16 bits). 386 */ 387 388 struct seeprom_config { 389 /* 390 * SCSI ID Configuration Flags 391 */ 392 u_int16_t device_flags[16]; /* words 0-15 */ 393 #define CFXFER 0x0007 /* synchronous transfer rate */ 394 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 395 #define CFDISC 0x0010 /* enable disconnection */ 396 #define CFWIDEB 0x0020 /* wide bus device */ 397 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 398 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 399 #define CFSTART 0x0100 /* send start unit SCSI command */ 400 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 401 #define CFRNFOUND 0x0400 /* report even if not found */ 402 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 403 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 404 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 405 406 /* 407 * BIOS Control Bits 408 */ 409 u_int16_t bios_control; /* word 16 */ 410 #define CFSUPREM 0x0001 /* support all removeable drives */ 411 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 412 #define CFBIOSEN 0x0004 /* BIOS enabled */ 413 /* UNUSED 0x0008 */ 414 #define CFSM2DRV 0x0010 /* support more than two drives */ 415 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 416 /* UNUSED 0x0040 */ 417 #define CFEXTEND 0x0080 /* extended translation enabled */ 418 /* UNUSED 0xff00 */ 419 420 /* 421 * Host Adapter Control Bits 422 */ 423 u_int16_t adapter_control; /* word 17 */ 424 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 425 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 426 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 427 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 428 #define CFSTERM 0x0004 /* SCSI low byte termination */ 429 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 430 #define CFSPARITY 0x0010 /* SCSI parity */ 431 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 432 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 433 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 434 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 435 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 436 /* UNUSED 0xf280 */ 437 438 /* 439 * Bus Release, Host Adapter ID 440 */ 441 u_int16_t brtime_id; /* word 18 */ 442 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 443 /* UNUSED 0x00f0 */ 444 #define CFBRTIME 0xff00 /* bus release time */ 445 446 /* 447 * Maximum targets 448 */ 449 u_int16_t max_targets; /* word 19 */ 450 #define CFMAXTARG 0x00ff /* maximum targets */ 451 /* UNUSED 0xff00 */ 452 u_int16_t res_1[11]; /* words 20-30 */ 453 u_int16_t checksum; /* word 31 */ 454 }; 455 456 struct ahc_syncrate { 457 int sxfr_u2; 458 int sxfr; 459 /* Rates in Ultra mode have bit 8 of sxfr set */ 460 #define ULTRA_SXFR 0x100 461 #define ST_SXFR 0x010 462 u_int8_t period; /* Period to send to SCSI target */ 463 char *rate; 464 }; 465 466 typedef enum { 467 MSG_TYPE_NONE = 0x00, 468 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 469 MSG_TYPE_INITIATOR_MSGIN = 0x02, 470 MSG_TYPE_TARGET_MSGOUT = 0x03, 471 MSG_TYPE_TARGET_MSGIN = 0x04 472 } ahc_msg_type; 473 474 struct sg_map_node { 475 bus_dmamap_t sg_dmamap; 476 bus_addr_t sg_physaddr; 477 bus_dma_segment_t sg_dmasegs; 478 int sg_nseg; 479 struct ahc_dma_seg* sg_vaddr; 480 SLIST_ENTRY(sg_map_node) links; 481 }; 482 483 struct scb_data { 484 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 485 struct scb *scbarray; /* Array of kernel SCBs */ 486 SLIST_HEAD(, scb) free_scbs; /* 487 * Pool of SCBs ready to be assigned 488 * commands to execute. 489 */ 490 struct scsipi_sense_data *sense; /* Per SCB sense data */ 491 492 /* 493 * "Bus" addresses of our data structures. 494 */ 495 bus_dmamap_t hscb_dmamap; 496 bus_addr_t hscb_busaddr; 497 bus_dma_segment_t hscb_seg; 498 int hscb_nseg; 499 int hscb_size; 500 501 bus_dmamap_t sense_dmamap; 502 bus_addr_t sense_busaddr; 503 bus_dma_segment_t sense_seg; 504 int sense_nseg; 505 int sense_size; 506 507 SLIST_HEAD(, sg_map_node) sg_maps; 508 u_int8_t numscbs; 509 u_int8_t maxhscbs; /* Number of SCBs on the card */ 510 u_int8_t init_level; /* 511 * How far we've initialized 512 * this structure. 513 */ 514 }; 515 516 typedef TAILQ_HEAD(, scsipi_xfer) xs_list_t; 517 518 struct ahc_softc { 519 struct device sc_dev; 520 521 struct scsipi_link sc_link; 522 struct scsipi_link sc_link_b; 523 struct scsipi_adapter sc_adapter; 524 525 bus_space_tag_t tag; 526 bus_space_handle_t bsh; 527 struct scb_data *scb_data; 528 529 xs_list_t sc_q; 530 int queue_blocked; 531 u_int16_t devqueue_blocked[16]; 532 #define AHC_NEG_PENDING 0x01 533 #define AHC_NEG_SDTRDONE 0x02 534 #define AHC_NEG_WDTRDONE 0x04 535 u_int8_t inited_targets[16]; 536 537 /* 538 * SCBs that have been send to the controller 539 */ 540 LIST_HEAD(, scb) pending_ccbs; 541 542 /* 543 * Target mode related state kept on a per enabled lun basis. 544 * Targets that are not enabled will have null entries. 545 * As an initiator, we keep one target entry for our initiator 546 * ID to store our sync/wide transfer settings. 547 */ 548 struct tmode_tstate* enabled_targets[16]; 549 550 /* 551 * The black hole device responsible for handling requests for 552 * disabled luns on enabled targets. 553 */ 554 struct tmode_lstate* black_hole; 555 556 /* 557 * Device instance currently on the bus awaiting a continue TIO 558 * for a command that was not given the disconnect priveledge. 559 */ 560 struct tmode_lstate* pending_device; 561 562 /* 563 * Card characteristics 564 */ 565 ahc_chip chip; 566 ahc_feature features; 567 ahc_flag flags; 568 569 /* Values to store in the SEQCTL register for pause and unpause */ 570 u_int8_t unpause; 571 u_int8_t pause; 572 573 /* Command Queues */ 574 u_int8_t qoutfifonext; 575 u_int8_t qinfifonext; 576 u_int8_t *qoutfifo; 577 u_int8_t *qinfifo; 578 579 /* 580 * 256 byte array storing the SCBID of outstanding 581 * untagged SCBs indexed by TCL. 582 */ 583 u_int8_t *untagged_scbs; 584 585 /* Channel Names ('A', 'B', etc.) */ 586 char channel; 587 char channel_b; 588 589 /* Initiator Bus ID */ 590 u_int8_t our_id; 591 u_int8_t our_id_b; 592 593 /* Targets that need negotiation messages */ 594 u_int16_t targ_msg_req; 595 596 /* 597 * PCI error detection and data for running the 598 * PCI error interrupt handler. 599 */ 600 int unsolicited_ints; 601 602 /* 603 * Target incoming command FIFO. 604 */ 605 struct target_cmd *targetcmds; 606 u_int8_t tqinfifonext; 607 608 /* 609 * Incoming and outgoing message handling. 610 */ 611 u_int8_t send_msg_perror; 612 ahc_msg_type msg_type; 613 u_int8_t msgout_buf[8]; /* Message we are sending */ 614 u_int8_t msgin_buf[8]; /* Message we are receiving */ 615 u_int msgout_len; /* Length of message to send */ 616 u_int msgout_index; /* Current index in msgout */ 617 u_int msgin_index; /* Current index in msgin */ 618 619 void *ih; 620 bus_dma_tag_t parent_dmat; 621 int sc_dmaflags; 622 bus_dmamap_t shared_data_dmamap; 623 bus_addr_t shared_data_busaddr; 624 bus_dma_segment_t shared_data_seg; 625 int shared_data_nseg; 626 int shared_data_size; 627 bus_addr_t dma_bug_buf; 628 629 /* Number of enabled target mode device on this card */ 630 u_int enabled_luns; 631 632 /* Initialization level of this data structure */ 633 u_int init_level; 634 635 u_int16_t user_discenable;/* Disconnection allowed */ 636 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 637 638 void *bus_data; 639 int (*bus_intr)(struct ahc_softc *); 640 }; 641 642 struct full_ahc_softc { 643 struct ahc_softc softc; 644 struct scb_data scb_data_storage; 645 }; 646 647 /* #define AHC_DEBUG 0x019f */ 648 649 #ifdef AHC_DEBUG 650 /* Different debugging levels used when AHC_DEBUG is defined */ 651 #define AHC_SHOWMISC 0x0001 652 #define AHC_SHOWCMDS 0x0002 653 #define AHC_SHOWSCBS 0x0004 654 #define AHC_SHOWABORTS 0x0008 655 #define AHC_SHOWSENSE 0x0010 656 #define AHC_SHOWSCBCNT 0x0020 657 #define AHC_SHOWSCBALLOC 0x0040 658 #define AHC_SHOWINTR 0x0080 659 #define AHC_SHOWMSG 0x0100 660 661 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 662 #endif 663 664 char *ahc_name(struct ahc_softc *ahc); 665 666 int ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, 667 bus_space_tag_t st, bus_dma_tag_t parent_dmat, 668 ahc_chip chip, ahc_feature features, ahc_flag flags); 669 int ahc_reset(struct ahc_softc *ahc); 670 void ahc_free(struct ahc_softc *); 671 int ahc_probe_scbs(struct ahc_softc *); 672 int ahc_init(struct ahc_softc *); 673 int ahc_attach(struct ahc_softc *); 674 int ahc_intr(void *arg); 675 676 /* 677 * SEEPROM related functions. 678 */ 679 void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 680 681 682 #define ahc_inb(ahc, port) \ 683 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 684 685 #define ahc_outb(ahc, port, value) \ 686 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 687 688 #define ahc_outsb(ahc, port, valp, count) \ 689 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 690 691 #define ahc_insb(ahc, port, valp, count) \ 692 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 693 694 #endif /* _AIC7XXX_H_ */ 695
Indexes created Thu Oct 02 14:10:14 GMT 2025