aic7xxxvar.h revision 1.26.2.4
1 /* $NetBSD: aic7xxxvar.h,v 1.26.2.4 2002/12/11 06:37:52 thorpej Exp $ */ 2 3 /* 4 * Interface to the generic driver for the aic7xxx based adaptec 5 * SCSI controllers. This is used to implement product specific 6 * probe and attach routines. 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.16 2000/02/09 21:24:59 gibbs Exp $ 36 */ 37 38 #ifndef _AIC7XXX_H_ 39 #define _AIC7XXX_H_ 40 41 #ifndef FALSE 42 #define FALSE 0 43 #endif 44 45 #ifndef TRUE 46 #define TRUE 1 47 #endif 48 49 /* 50 * The maximum transfer per S/G segment. 51 */ 52 #define AHC_MAXTRANSFER_SIZE ctob(AHC_NSEG - 1) 53 54 /* 55 * The number of dma segments supported. The current implementation limits 56 * us to 255 S/G entries (this may change to be unlimited at some point). 57 * To reduce the driver's memory consumption, we further limit the number 58 * supported to be sufficient to handle the largest mapping supported by 59 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 60 * and unaligned, this turns out to be the number of paged sized transfers 61 * in MAXPHYS plus an extra element to handle any unaligned residual. 62 */ 63 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 64 65 #define AHC_SCB_MAX 255 /* 66 * Up to 255 SCBs on some types of aic7xxx 67 * based boards. The aic7870 have 16 internal 68 * SCBs, but external SRAM bumps this to 255. 69 * The aic7770 family have only 4, and the 70 * aic7850 has only 3. 71 */ 72 73 #define AHC_TMODE_CMDS 256 /* 74 * Ring Buffer of incoming target commands. 75 * We allocate 256 to simplify the logic 76 * in the sequencer by using the natural 77 * wrap point of an 8bit counter. 78 */ 79 80 struct ahc_dma_seg { 81 u_int32_t addr; 82 u_int32_t len; 83 }; 84 85 typedef enum { 86 AHC_NONE = 0x0000, 87 AHC_CHIPID_MASK = 0x00FF, 88 AHC_AIC7770 = 0x0001, 89 AHC_AIC7850 = 0x0002, 90 AHC_AIC7855 = 0x0003, 91 AHC_AIC7859 = 0x0004, 92 AHC_AIC7860 = 0x0005, 93 AHC_AIC7870 = 0x0006, 94 AHC_AIC7880 = 0x0007, 95 AHC_AIC7890 = 0x0008, 96 AHC_AIC7892 = 0x0009, 97 AHC_AIC7895 = 0x000a, 98 AHC_AIC7896 = 0x000b, 99 AHC_AIC7899 = 0x000c, 100 AHC_VL = 0x0100, /* Bus type VL */ 101 AHC_EISA = 0x0200, /* Bus type EISA */ 102 AHC_PCI = 0x0400, /* Bus type PCI */ 103 AHC_BUS_MASK = 0x0F00 104 } ahc_chip; 105 106 extern const char * const ahc_chip_names[]; 107 108 typedef enum { 109 AHC_FENONE = 0x0000, 110 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 111 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 112 AHC_WIDE = 0x0004, /* Wide Channel */ 113 AHC_TWIN = 0x0008, /* Twin Channel */ 114 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 115 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 116 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 117 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 118 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 119 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 120 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 121 AHC_DT = 0x0800, /* Double Transition transfers */ 122 AHC_NEW_TERMCTL = 0x1000, 123 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 124 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 125 AHC_AIC7770_FE = AHC_TARG_DMABUG, 126 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 127 AHC_AIC7855_FE = AHC_AIC7850_FE, 128 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 129 AHC_AIC7860_FE = AHC_AIC7859_FE, 130 AHC_AIC7870_FE = AHC_TARG_DMABUG, 131 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 132 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 133 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 134 |AHC_NEW_TERMCTL, 135 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 136 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 137 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 138 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 139 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 140 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 141 } ahc_feature; 142 143 typedef enum { 144 AHC_FNONE = 0x000, 145 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 146 AHC_CHANNEL_B_PRIMARY = 0x002,/* 147 * On twin channel adapters, probe 148 * channel B first since it is the 149 * primary bus. 150 */ 151 AHC_USEDEFAULTS = 0x004,/* 152 * For cards without an seeprom 153 * or a BIOS to initialize the chip's 154 * SRAM, we use the default target 155 * settings. 156 */ 157 AHC_SHARED_SRAM = 0x010, 158 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 159 AHC_RESET_BUS_A = 0x040, 160 AHC_RESET_BUS_B = 0x080, 161 AHC_EXTENDED_TRANS_A = 0x100, 162 AHC_EXTENDED_TRANS_B = 0x200, 163 AHC_TERM_ENB_A = 0x400, 164 AHC_TERM_ENB_B = 0x800, 165 AHC_INITIATORMODE = 0x1000,/* 166 * Allow initiator operations on 167 * this controller. 168 */ 169 AHC_TARGETMODE = 0x2000,/* 170 * Allow target operations on this 171 * controller. 172 */ 173 AHC_NEWEEPROM_FMT = 0x4000, 174 AHC_RESOURCE_SHORTAGE = 0x8000, 175 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 176 AHC_INT50_SPEEDFLEX = 0x20000 /* 177 * Internal 50pin connector 178 * sits behind an aic3860 179 */ 180 } ahc_flag; 181 182 typedef enum { 183 SCB_FREE = 0x0000, 184 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 185 * Another device was active 186 * during the first timeout for 187 * this SCB so we gave ourselves 188 * an additional timeout period 189 * in case it was hogging the 190 * bus. 191 */ 192 SCB_DEVICE_RESET = 0x0004, 193 SCB_SENSE = 0x0008, 194 SCB_FREEZE_QUEUE = 0x0010, 195 SCB_REQUEUE = 0x0020, 196 SCB_RECOVERY_SCB = 0x0040, 197 SCB_ABORT = 0x1000, 198 SCB_QUEUED_MSG = 0x2000, 199 SCB_ACTIVE = 0x4000, 200 SCB_TARGET_IMMEDIATE = 0x8000 201 } scb_flag; 202 203 typedef enum { 204 MSGLOOP_IN_PROG, 205 MSGLOOP_MSGCOMPLETE, 206 MSGLOOP_TERMINATED 207 } msg_loop_stat; 208 209 /* 210 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 211 * consists of a "hardware SCB" mirroring the fields available on the card 212 * and additional information the kernel stores for each transaction. 213 */ 214 struct hardware_scb { 215 /*0*/ u_int8_t control; 216 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 217 /*2*/ u_int8_t status; 218 /*3*/ u_int8_t SG_count; 219 /*4*/ u_int32_t SG_pointer; 220 /*8*/ u_int8_t residual_SG_count; 221 /*9*/ u_int8_t residual_data_count[3]; 222 /*12*/ u_int32_t data; 223 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 224 * faster to treat it as a long on 225 * a quad boundary. 226 */ 227 /*20*/ u_int32_t cmdpointer; 228 /*24*/ u_int8_t cmdlen; 229 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 230 * Also used as the tag for tagged I/O 231 */ 232 /*26*/ u_int8_t next; /* Used for threading SCBs in the 233 * "Waiting for Selection" and 234 * "Disconnected SCB" lists down 235 * in the sequencer. 236 */ 237 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 238 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 239 /*29*/ u_int8_t spare[3]; /* 240 * Spare space available on 241 * all controller types. 242 */ 243 /*32*/ u_int8_t cmdstore[16]; /* 244 * CDB storage for controllers 245 * supporting 64 byte SCBs. 246 */ 247 /*48*/ u_int32_t cmdstore_busaddr; /* 248 * Address of command store for 249 * 32byte SCB adapters 250 */ 251 /*48*/ u_int8_t spare_64[12]; /* 252 * Pad to 64 bytes. 253 */ 254 }; 255 256 struct scb { 257 struct hardware_scb *hscb; 258 SLIST_ENTRY(scb) links; /* for chaining */ 259 LIST_ENTRY(scb) plinks; /* pending chain */ 260 struct scsipi_xfer *xs; 261 scb_flag flags; 262 bus_dmamap_t dmamap; 263 struct ahc_dma_seg *sg_list; 264 bus_addr_t sg_list_phys; 265 u_int sg_count;/* How full ahc_dma_seg is */ 266 }; 267 268 /* 269 * Connection desciptor for select-in requests in target mode. 270 * The first byte is the connecting target, followed by identify 271 * message and optional tag information, terminated by 0xFF. The 272 * remainder is the command to execute. The cmd_valid byte is on 273 * an 8 byte boundary to simplify setting it on aic7880 hardware 274 * which only has limited direct access to the DMA FIFO. 275 */ 276 struct target_cmd { 277 u_int8_t initiator_channel; 278 u_int8_t targ_id; /* Target ID we were selected at */ 279 u_int8_t identify; /* Identify message */ 280 u_int8_t bytes[21]; 281 u_int8_t cmd_valid; 282 u_int8_t pad[7]; 283 }; 284 285 /* 286 * Number of events we can buffer up if we run out 287 * of immediate notify ccbs. 288 */ 289 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 290 struct ahc_tmode_event { 291 u_int8_t initiator_id; 292 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 293 #define EVENT_TYPE_BUS_RESET 0xFF 294 u_int8_t event_arg; 295 }; 296 297 /* 298 * Per lun target mode state including accept TIO CCB 299 * and immediate notify CCB pools. 300 */ 301 struct tmode_lstate { 302 #ifdef maybe_later 303 struct cam_path *path; 304 struct ccb_hdr_slist accept_tios; 305 struct ccb_hdr_slist immed_notifies; 306 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 307 u_int8_t event_r_idx; 308 u_int8_t event_w_idx; 309 #else 310 u_int8_t dummy; 311 #endif 312 }; 313 314 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 315 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 316 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 317 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 318 319 struct ahc_transinfo { 320 u_int8_t width; 321 u_int8_t period; 322 u_int8_t offset; 323 u_int8_t ppr_flags; 324 }; 325 326 struct ahc_initiator_tinfo { 327 u_int8_t scsirate; 328 struct ahc_transinfo current; 329 struct ahc_transinfo goal; 330 struct ahc_transinfo user; 331 }; 332 333 /* 334 * Per target mode enabled target state. Esentially just an array of 335 * pointers to lun target state as well as sync/wide negotiation information 336 * for each initiator<->target mapping (including the mapping for when we 337 * are the initiator). 338 */ 339 struct tmode_tstate { 340 #if 0 341 struct tmode_lstate* enabled_luns[8]; 342 #endif 343 struct ahc_initiator_tinfo transinfo[16]; 344 345 /* 346 * Per initiator state bitmasks. 347 */ 348 u_int16_t ultraenb; /* Using ultra sync rate */ 349 u_int16_t discenable; /* Disconnection allowed */ 350 u_int16_t tagenable; /* Tagged Queuing allowed */ 351 u_int16_t tagdisable; /* TQ explicitly disallowed */ 352 }; 353 354 #define AHC_TARGET_WILDCARD -1 355 #define AHC_LUN_WILDCARD -1 356 357 /* 358 * XXX translate FreeBSD SCSI status byte values to NetBSD, and define 359 * a few more. 360 */ 361 #define SCSI_STATUS_OK SCSI_OK 362 #define SCSI_STATUS_CHECK_COND SCSI_CHECK 363 #define SCSI_STATUS_COND_MET 0x04 364 #define SCSI_STATUS_BUSY SCSI_BUSY 365 #define SCSI_STATUS_INTERMED SCSI_INTERM 366 #define SCSI_STATUS_INTERMED_COND_MET 0x14 367 #define SCSI_STATUS_RESERV_CONFLICT 0x18 368 #define SCSI_STATUS_CMD_TERMINATED 0x22 369 #define SCSI_STATUS_QUEUE_FULL SCSI_QUEUE_FULL 370 371 /* 372 * Define the format of the aic7XXX SEEPROM registers (16 bits). 373 */ 374 375 struct seeprom_config { 376 /* 377 * SCSI ID Configuration Flags 378 */ 379 u_int16_t device_flags[16]; /* words 0-15 */ 380 #define CFXFER 0x0007 /* synchronous transfer rate */ 381 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 382 #define CFDISC 0x0010 /* enable disconnection */ 383 #define CFWIDEB 0x0020 /* wide bus device */ 384 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 385 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 386 #define CFSTART 0x0100 /* send start unit SCSI command */ 387 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 388 #define CFRNFOUND 0x0400 /* report even if not found */ 389 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 390 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 391 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 392 393 /* 394 * BIOS Control Bits 395 */ 396 u_int16_t bios_control; /* word 16 */ 397 #define CFSUPREM 0x0001 /* support all removeable drives */ 398 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 399 #define CFBIOSEN 0x0004 /* BIOS enabled */ 400 /* UNUSED 0x0008 */ 401 #define CFSM2DRV 0x0010 /* support more than two drives */ 402 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 403 /* UNUSED 0x0040 */ 404 #define CFEXTEND 0x0080 /* extended translation enabled */ 405 /* UNUSED 0xff00 */ 406 407 /* 408 * Host Adapter Control Bits 409 */ 410 u_int16_t adapter_control; /* word 17 */ 411 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 412 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 413 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 414 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 415 #define CFSTERM 0x0004 /* SCSI low byte termination */ 416 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 417 #define CFSPARITY 0x0010 /* SCSI parity */ 418 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 419 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 420 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 421 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 422 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 423 /* UNUSED 0xf280 */ 424 425 /* 426 * Bus Release, Host Adapter ID 427 */ 428 u_int16_t brtime_id; /* word 18 */ 429 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 430 /* UNUSED 0x00f0 */ 431 #define CFBRTIME 0xff00 /* bus release time */ 432 433 /* 434 * Maximum targets 435 */ 436 u_int16_t max_targets; /* word 19 */ 437 #define CFMAXTARG 0x00ff /* maximum targets */ 438 /* UNUSED 0xff00 */ 439 u_int16_t res_1[11]; /* words 20-30 */ 440 u_int16_t checksum; /* word 31 */ 441 }; 442 443 struct ahc_syncrate { 444 int sxfr_u2; 445 int sxfr; 446 /* Rates in Ultra mode have bit 8 of sxfr set */ 447 #define ULTRA_SXFR 0x100 448 #define ST_SXFR 0x010 449 u_int8_t period; /* Period to send to SCSI target */ 450 char *rate; 451 }; 452 453 typedef enum { 454 MSG_TYPE_NONE = 0x00, 455 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 456 MSG_TYPE_INITIATOR_MSGIN = 0x02, 457 MSG_TYPE_TARGET_MSGOUT = 0x03, 458 MSG_TYPE_TARGET_MSGIN = 0x04 459 } ahc_msg_type; 460 461 struct sg_map_node { 462 bus_dmamap_t sg_dmamap; 463 bus_addr_t sg_physaddr; 464 bus_dma_segment_t sg_dmasegs; 465 int sg_nseg; 466 struct ahc_dma_seg* sg_vaddr; 467 SLIST_ENTRY(sg_map_node) links; 468 }; 469 470 struct scb_data { 471 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 472 struct scb *scbarray; /* Array of kernel SCBs */ 473 SLIST_HEAD(, scb) free_scbs; /* 474 * Pool of SCBs ready to be assigned 475 * commands to execute. 476 */ 477 struct scsipi_sense_data *sense; /* Per SCB sense data */ 478 479 /* 480 * "Bus" addresses of our data structures. 481 */ 482 bus_dmamap_t hscb_dmamap; 483 bus_addr_t hscb_busaddr; 484 bus_dma_segment_t hscb_seg; 485 int hscb_nseg; 486 int hscb_size; 487 488 bus_dmamap_t sense_dmamap; 489 bus_addr_t sense_busaddr; 490 bus_dma_segment_t sense_seg; 491 int sense_nseg; 492 int sense_size; 493 494 SLIST_HEAD(, sg_map_node) sg_maps; 495 u_int8_t numscbs; 496 u_int8_t maxhscbs; /* Number of SCBs on the card */ 497 u_int8_t init_level; /* 498 * How far we've initialized 499 * this structure. 500 */ 501 }; 502 503 struct ahc_softc { 504 struct device sc_dev; 505 506 struct scsipi_channel sc_channel; 507 struct scsipi_channel sc_channel_b; 508 struct scsipi_adapter sc_adapter; 509 510 bus_space_tag_t tag; 511 bus_space_handle_t bsh; 512 struct scb_data *scb_data; 513 514 #define AHC_NEG_PENDING 0x01 515 #define AHC_NEG_SDTRDONE 0x02 516 #define AHC_NEG_WDTRDONE 0x04 517 u_int8_t inited_targets[16]; 518 u_int8_t inited_channels[2]; 519 520 struct device *child; 521 522 /* 523 * SCBs that have been send to the controller 524 */ 525 LIST_HEAD(, scb) pending_ccbs; 526 527 /* 528 * Target mode related state kept on a per enabled lun basis. 529 * Targets that are not enabled will have null entries. 530 * As an initiator, we keep one target entry for our initiator 531 * ID to store our sync/wide transfer settings. 532 */ 533 struct tmode_tstate* enabled_targets[16]; 534 535 /* 536 * The black hole device responsible for handling requests for 537 * disabled luns on enabled targets. 538 */ 539 struct tmode_lstate* black_hole; 540 541 /* 542 * Device instance currently on the bus awaiting a continue TIO 543 * for a command that was not given the disconnect priveledge. 544 */ 545 struct tmode_lstate* pending_device; 546 547 /* 548 * Card characteristics 549 */ 550 ahc_chip chip; 551 ahc_feature features; 552 ahc_flag flags; 553 554 /* Values to store in the SEQCTL register for pause and unpause */ 555 u_int8_t unpause; 556 u_int8_t pause; 557 558 /* Command Queues */ 559 u_int8_t qoutfifonext; 560 u_int8_t qinfifonext; 561 u_int8_t *qoutfifo; 562 u_int8_t *qinfifo; 563 564 /* 565 * 256 byte array storing the SCBID of outstanding 566 * untagged SCBs indexed by TCL. 567 */ 568 u_int8_t *untagged_scbs; 569 570 /* Channel Names ('A', 'B', etc.) */ 571 char channel; 572 char channel_b; 573 574 /* Initiator Bus ID */ 575 u_int8_t our_id; 576 u_int8_t our_id_b; 577 578 /* Targets that need negotiation messages */ 579 u_int16_t targ_msg_req; 580 581 /* 582 * PCI error detection and data for running the 583 * PCI error interrupt handler. 584 */ 585 int unsolicited_ints; 586 587 /* 588 * Target incoming command FIFO. 589 */ 590 struct target_cmd *targetcmds; 591 u_int8_t tqinfifonext; 592 593 /* 594 * Incoming and outgoing message handling. 595 */ 596 u_int8_t send_msg_perror; 597 ahc_msg_type msg_type; 598 u_int8_t msgout_buf[8]; /* Message we are sending */ 599 u_int8_t msgin_buf[8]; /* Message we are receiving */ 600 u_int msgout_len; /* Length of message to send */ 601 u_int msgout_index; /* Current index in msgout */ 602 u_int msgin_index; /* Current index in msgin */ 603 604 void *ih; 605 bus_dma_tag_t parent_dmat; 606 int sc_dmaflags; 607 bus_dmamap_t shared_data_dmamap; 608 bus_addr_t shared_data_busaddr; 609 bus_dma_segment_t shared_data_seg; 610 int shared_data_nseg; 611 int shared_data_size; 612 bus_addr_t dma_bug_buf; 613 614 /* Number of enabled target mode device on this card */ 615 u_int enabled_luns; 616 617 /* Initialization level of this data structure */ 618 u_int init_level; 619 620 u_int16_t user_discenable;/* Disconnection allowed */ 621 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 622 623 void *bus_data; 624 int (*bus_intr)(struct ahc_softc *); 625 }; 626 627 struct full_ahc_softc { 628 struct ahc_softc softc; 629 struct scb_data scb_data_storage; 630 }; 631 632 /* #define AHC_DEBUG 0x019f */ 633 634 #ifdef AHC_DEBUG 635 /* Different debugging levels used when AHC_DEBUG is defined */ 636 #define AHC_SHOWMISC 0x0001 637 #define AHC_SHOWCMDS 0x0002 638 #define AHC_SHOWSCBS 0x0004 639 #define AHC_SHOWABORTS 0x0008 640 #define AHC_SHOWSENSE 0x0010 641 #define AHC_SHOWSCBCNT 0x0020 642 #define AHC_SHOWSCBALLOC 0x0040 643 #define AHC_SHOWINTR 0x0080 644 #define AHC_SHOWMSG 0x0100 645 646 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 647 #endif 648 649 char *ahc_name(struct ahc_softc *ahc); 650 651 int ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, 652 bus_space_tag_t st, bus_dma_tag_t parent_dmat, 653 ahc_chip chip, ahc_feature features, ahc_flag flags); 654 int ahc_reset(struct ahc_softc *ahc); 655 void ahc_free(struct ahc_softc *); 656 int ahc_probe_scbs(struct ahc_softc *); 657 int ahc_init(struct ahc_softc *); 658 int ahc_attach(struct ahc_softc *); 659 int ahc_detach(struct ahc_softc *, int); 660 int ahc_activate(struct device *, enum devact); 661 int ahc_intr(void *arg); 662 663 /* 664 * SEEPROM related functions. 665 */ 666 void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 667 668 669 #define ahc_inb(ahc, port) \ 670 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 671 672 #define ahc_outb(ahc, port, value) \ 673 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 674 675 #define ahc_outsb(ahc, port, valp, count) \ 676 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 677 678 #define ahc_insb(ahc, port, valp, count) \ 679 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 680 681 #endif /* _AIC7XXX_H_ */ 682
Indexes created Mon Oct 27 04:09:48 GMT 2025