aic7xxxvar.h revision 1.29
1 /* $NetBSD: aic7xxxvar.h,v 1.29 2001/07/04 20:34:03 wiz Exp $ */ 2 3 /* 4 * Interface to the generic driver for the aic7xxx based adaptec 5 * SCSI controllers. This is used to implement product specific 6 * probe and attach routines. 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Alternatively, this software may be distributed under the terms of the 21 * the GNU Public License ("GPL"). 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.16 2000/02/09 21:24:59 gibbs Exp $ 36 */ 37 38 #ifndef _AIC7XXX_H_ 39 #define _AIC7XXX_H_ 40 41 #ifndef FALSE 42 #define FALSE 0 43 #endif 44 45 #ifndef TRUE 46 #define TRUE 1 47 #endif 48 49 /* 50 * The maximum transfer per S/G segment. 51 */ 52 #define AHC_MAXTRANSFER_SIZE ctob(AHC_NSEG - 1) 53 54 /* 55 * Convert FreeBSD queue macro 56 */ 57 #define STAILQ_ENTRY SIMPLEQ_ENTRY 58 59 /* 60 * The number of dma segments supported. The current implementation limits 61 * us to 255 S/G entries (this may change to be unlimited at some point). 62 * To reduce the driver's memory consumption, we further limit the number 63 * supported to be sufficient to handle the largest mapping supported by 64 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 65 * and unaligned, this turns out to be the number of paged sized transfers 66 * in MAXPHYS plus an extra element to handle any unaligned residual. 67 */ 68 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 69 70 #define AHC_SCB_MAX 255 /* 71 * Up to 255 SCBs on some types of aic7xxx 72 * based boards. The aic7870 have 16 internal 73 * SCBs, but external SRAM bumps this to 255. 74 * The aic7770 family have only 4, and the 75 * aic7850 has only 3. 76 */ 77 78 #define AHC_TMODE_CMDS 256 /* 79 * Ring Buffer of incoming target commands. 80 * We allocate 256 to simplify the logic 81 * in the sequencer by using the natural 82 * wrap point of an 8bit counter. 83 */ 84 85 struct ahc_dma_seg { 86 u_int32_t addr; 87 u_int32_t len; 88 }; 89 90 typedef enum { 91 AHC_NONE = 0x0000, 92 AHC_CHIPID_MASK = 0x00FF, 93 AHC_AIC7770 = 0x0001, 94 AHC_AIC7850 = 0x0002, 95 AHC_AIC7855 = 0x0003, 96 AHC_AIC7859 = 0x0004, 97 AHC_AIC7860 = 0x0005, 98 AHC_AIC7870 = 0x0006, 99 AHC_AIC7880 = 0x0007, 100 AHC_AIC7890 = 0x0008, 101 AHC_AIC7892 = 0x0009, 102 AHC_AIC7895 = 0x000a, 103 AHC_AIC7896 = 0x000b, 104 AHC_AIC7899 = 0x000c, 105 AHC_VL = 0x0100, /* Bus type VL */ 106 AHC_EISA = 0x0200, /* Bus type EISA */ 107 AHC_PCI = 0x0400, /* Bus type PCI */ 108 AHC_BUS_MASK = 0x0F00 109 } ahc_chip; 110 111 extern const char * const ahc_chip_names[]; 112 113 typedef enum { 114 AHC_FENONE = 0x0000, 115 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 116 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 117 AHC_WIDE = 0x0004, /* Wide Channel */ 118 AHC_TWIN = 0x0008, /* Twin Channel */ 119 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 120 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 121 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 122 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 123 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 124 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 125 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 126 AHC_DT = 0x0800, /* Double Transition transfers */ 127 AHC_NEW_TERMCTL = 0x1000, 128 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 129 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 130 AHC_AIC7770_FE = AHC_TARG_DMABUG, 131 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 132 AHC_AIC7855_FE = AHC_AIC7850_FE, 133 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 134 AHC_AIC7860_FE = AHC_AIC7859_FE, 135 AHC_AIC7870_FE = AHC_TARG_DMABUG, 136 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 137 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 138 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 139 |AHC_NEW_TERMCTL, 140 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 141 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 142 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 143 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 144 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 145 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 146 } ahc_feature; 147 148 typedef enum { 149 AHC_FNONE = 0x000, 150 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 151 AHC_CHANNEL_B_PRIMARY = 0x002,/* 152 * On twin channel adapters, probe 153 * channel B first since it is the 154 * primary bus. 155 */ 156 AHC_USEDEFAULTS = 0x004,/* 157 * For cards without an seeprom 158 * or a BIOS to initialize the chip's 159 * SRAM, we use the default target 160 * settings. 161 */ 162 AHC_SHARED_SRAM = 0x010, 163 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 164 AHC_RESET_BUS_A = 0x040, 165 AHC_RESET_BUS_B = 0x080, 166 AHC_EXTENDED_TRANS_A = 0x100, 167 AHC_EXTENDED_TRANS_B = 0x200, 168 AHC_TERM_ENB_A = 0x400, 169 AHC_TERM_ENB_B = 0x800, 170 AHC_INITIATORMODE = 0x1000,/* 171 * Allow initiator operations on 172 * this controller. 173 */ 174 AHC_TARGETMODE = 0x2000,/* 175 * Allow target operations on this 176 * controller. 177 */ 178 AHC_NEWEEPROM_FMT = 0x4000, 179 AHC_RESOURCE_SHORTAGE = 0x8000, 180 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 181 AHC_INT50_SPEEDFLEX = 0x20000 /* 182 * Internal 50pin connector 183 * sits behind an aic3860 184 */ 185 } ahc_flag; 186 187 typedef enum { 188 SCB_FREE = 0x0000, 189 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 190 * Another device was active 191 * during the first timeout for 192 * this SCB so we gave ourselves 193 * an additional timeout period 194 * in case it was hogging the 195 * bus. 196 */ 197 SCB_DEVICE_RESET = 0x0004, 198 SCB_SENSE = 0x0008, 199 SCB_FREEZE_QUEUE = 0x0010, 200 SCB_REQUEUE = 0x0020, 201 SCB_RECOVERY_SCB = 0x0040, 202 SCB_ABORT = 0x1000, 203 SCB_QUEUED_MSG = 0x2000, 204 SCB_ACTIVE = 0x4000, 205 SCB_TARGET_IMMEDIATE = 0x8000 206 } scb_flag; 207 208 typedef enum { 209 MSGLOOP_IN_PROG, 210 MSGLOOP_MSGCOMPLETE, 211 MSGLOOP_TERMINATED 212 } msg_loop_stat; 213 214 /* 215 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 216 * consists of a "hardware SCB" mirroring the fields available on the card 217 * and additional information the kernel stores for each transaction. 218 */ 219 struct hardware_scb { 220 /*0*/ u_int8_t control; 221 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 222 /*2*/ u_int8_t status; 223 /*3*/ u_int8_t SG_count; 224 /*4*/ u_int32_t SG_pointer; 225 /*8*/ u_int8_t residual_SG_count; 226 /*9*/ u_int8_t residual_data_count[3]; 227 /*12*/ u_int32_t data; 228 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 229 * faster to treat it as a long on 230 * a quad boundary. 231 */ 232 /*20*/ u_int32_t cmdpointer; 233 /*24*/ u_int8_t cmdlen; 234 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 235 * Also used as the tag for tagged I/O 236 */ 237 /*26*/ u_int8_t next; /* Used for threading SCBs in the 238 * "Waiting for Selection" and 239 * "Disconnected SCB" lists down 240 * in the sequencer. 241 */ 242 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 243 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 244 /*29*/ u_int8_t spare[3]; /* 245 * Spare space available on 246 * all controller types. 247 */ 248 /*32*/ u_int8_t cmdstore[16]; /* 249 * CDB storage for controllers 250 * supporting 64 byte SCBs. 251 */ 252 /*48*/ u_int32_t cmdstore_busaddr; /* 253 * Address of command store for 254 * 32byte SCB adapters 255 */ 256 /*48*/ u_int8_t spare_64[12]; /* 257 * Pad to 64 bytes. 258 */ 259 }; 260 261 struct scb { 262 struct hardware_scb *hscb; 263 SLIST_ENTRY(scb) links; /* for chaining */ 264 LIST_ENTRY(scb) plinks; /* pending chain */ 265 struct scsipi_xfer *xs; 266 scb_flag flags; 267 bus_dmamap_t dmamap; 268 struct ahc_dma_seg *sg_list; 269 bus_addr_t sg_list_phys; 270 u_int sg_count;/* How full ahc_dma_seg is */ 271 }; 272 273 /* 274 * Connection desciptor for select-in requests in target mode. 275 * The first byte is the connecting target, followed by identify 276 * message and optional tag information, terminated by 0xFF. The 277 * remainder is the command to execute. The cmd_valid byte is on 278 * an 8 byte boundary to simplify setting it on aic7880 hardware 279 * which only has limited direct access to the DMA FIFO. 280 */ 281 struct target_cmd { 282 u_int8_t initiator_channel; 283 u_int8_t targ_id; /* Target ID we were selected at */ 284 u_int8_t identify; /* Identify message */ 285 u_int8_t bytes[21]; 286 u_int8_t cmd_valid; 287 u_int8_t pad[7]; 288 }; 289 290 /* 291 * Number of events we can buffer up if we run out 292 * of immediate notify ccbs. 293 */ 294 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 295 struct ahc_tmode_event { 296 u_int8_t initiator_id; 297 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 298 #define EVENT_TYPE_BUS_RESET 0xFF 299 u_int8_t event_arg; 300 }; 301 302 /* 303 * Per lun target mode state including accept TIO CCB 304 * and immediate notify CCB pools. 305 */ 306 struct tmode_lstate { 307 #ifdef maybe_later 308 struct cam_path *path; 309 struct ccb_hdr_slist accept_tios; 310 struct ccb_hdr_slist immed_notifies; 311 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 312 u_int8_t event_r_idx; 313 u_int8_t event_w_idx; 314 #else 315 u_int8_t dummy; 316 #endif 317 }; 318 319 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 320 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 321 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 322 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 323 324 struct ahc_transinfo { 325 u_int8_t width; 326 u_int8_t period; 327 u_int8_t offset; 328 u_int8_t ppr_flags; 329 }; 330 331 struct ahc_initiator_tinfo { 332 u_int8_t scsirate; 333 struct ahc_transinfo current; 334 struct ahc_transinfo goal; 335 struct ahc_transinfo user; 336 }; 337 338 /* 339 * Per target mode enabled target state. Esentially just an array of 340 * pointers to lun target state as well as sync/wide negotiation information 341 * for each initiator<->target mapping (including the mapping for when we 342 * are the initiator). 343 */ 344 struct tmode_tstate { 345 #if 0 346 struct tmode_lstate* enabled_luns[8]; 347 #endif 348 struct ahc_initiator_tinfo transinfo[16]; 349 350 /* 351 * Per initiator state bitmasks. 352 */ 353 u_int16_t ultraenb; /* Using ultra sync rate */ 354 u_int16_t discenable; /* Disconnection allowed */ 355 u_int16_t tagenable; /* Tagged Queuing allowed */ 356 u_int16_t tagdisable; /* TQ explicity disallowed */ 357 }; 358 359 #define AHC_TARGET_WILDCARD -1 360 #define AHC_LUN_WILDCARD -1 361 362 /* 363 * XXX translate FreeBSD SCSI status byte values to NetBSD, and define 364 * a few more. 365 */ 366 #define SCSI_STATUS_OK SCSI_OK 367 #define SCSI_STATUS_CHECK_COND SCSI_CHECK 368 #define SCSI_STATUS_COND_MET 0x04 369 #define SCSI_STATUS_BUSY SCSI_BUSY 370 #define SCSI_STATUS_INTERMED SCSI_INTERM 371 #define SCSI_STATUS_INTERMED_COND_MET 0x14 372 #define SCSI_STATUS_RESERV_CONFLICT 0x18 373 #define SCSI_STATUS_CMD_TERMINATED 0x22 374 #define SCSI_STATUS_QUEUE_FULL SCSI_QUEUE_FULL 375 376 /* 377 * Define the format of the aic7XXX SEEPROM registers (16 bits). 378 */ 379 380 struct seeprom_config { 381 /* 382 * SCSI ID Configuration Flags 383 */ 384 u_int16_t device_flags[16]; /* words 0-15 */ 385 #define CFXFER 0x0007 /* synchronous transfer rate */ 386 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 387 #define CFDISC 0x0010 /* enable disconnection */ 388 #define CFWIDEB 0x0020 /* wide bus device */ 389 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 390 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 391 #define CFSTART 0x0100 /* send start unit SCSI command */ 392 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 393 #define CFRNFOUND 0x0400 /* report even if not found */ 394 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 395 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 396 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 397 398 /* 399 * BIOS Control Bits 400 */ 401 u_int16_t bios_control; /* word 16 */ 402 #define CFSUPREM 0x0001 /* support all removeable drives */ 403 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 404 #define CFBIOSEN 0x0004 /* BIOS enabled */ 405 /* UNUSED 0x0008 */ 406 #define CFSM2DRV 0x0010 /* support more than two drives */ 407 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 408 /* UNUSED 0x0040 */ 409 #define CFEXTEND 0x0080 /* extended translation enabled */ 410 /* UNUSED 0xff00 */ 411 412 /* 413 * Host Adapter Control Bits 414 */ 415 u_int16_t adapter_control; /* word 17 */ 416 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 417 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 418 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 419 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 420 #define CFSTERM 0x0004 /* SCSI low byte termination */ 421 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 422 #define CFSPARITY 0x0010 /* SCSI parity */ 423 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 424 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 425 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 426 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 427 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 428 /* UNUSED 0xf280 */ 429 430 /* 431 * Bus Release, Host Adapter ID 432 */ 433 u_int16_t brtime_id; /* word 18 */ 434 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 435 /* UNUSED 0x00f0 */ 436 #define CFBRTIME 0xff00 /* bus release time */ 437 438 /* 439 * Maximum targets 440 */ 441 u_int16_t max_targets; /* word 19 */ 442 #define CFMAXTARG 0x00ff /* maximum targets */ 443 /* UNUSED 0xff00 */ 444 u_int16_t res_1[11]; /* words 20-30 */ 445 u_int16_t checksum; /* word 31 */ 446 }; 447 448 struct ahc_syncrate { 449 int sxfr_u2; 450 int sxfr; 451 /* Rates in Ultra mode have bit 8 of sxfr set */ 452 #define ULTRA_SXFR 0x100 453 #define ST_SXFR 0x010 454 u_int8_t period; /* Period to send to SCSI target */ 455 char *rate; 456 }; 457 458 typedef enum { 459 MSG_TYPE_NONE = 0x00, 460 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 461 MSG_TYPE_INITIATOR_MSGIN = 0x02, 462 MSG_TYPE_TARGET_MSGOUT = 0x03, 463 MSG_TYPE_TARGET_MSGIN = 0x04 464 } ahc_msg_type; 465 466 struct sg_map_node { 467 bus_dmamap_t sg_dmamap; 468 bus_addr_t sg_physaddr; 469 bus_dma_segment_t sg_dmasegs; 470 int sg_nseg; 471 struct ahc_dma_seg* sg_vaddr; 472 SLIST_ENTRY(sg_map_node) links; 473 }; 474 475 struct scb_data { 476 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 477 struct scb *scbarray; /* Array of kernel SCBs */ 478 SLIST_HEAD(, scb) free_scbs; /* 479 * Pool of SCBs ready to be assigned 480 * commands to execute. 481 */ 482 struct scsipi_sense_data *sense; /* Per SCB sense data */ 483 484 /* 485 * "Bus" addresses of our data structures. 486 */ 487 bus_dmamap_t hscb_dmamap; 488 bus_addr_t hscb_busaddr; 489 bus_dma_segment_t hscb_seg; 490 int hscb_nseg; 491 int hscb_size; 492 493 bus_dmamap_t sense_dmamap; 494 bus_addr_t sense_busaddr; 495 bus_dma_segment_t sense_seg; 496 int sense_nseg; 497 int sense_size; 498 499 SLIST_HEAD(, sg_map_node) sg_maps; 500 u_int8_t numscbs; 501 u_int8_t maxhscbs; /* Number of SCBs on the card */ 502 u_int8_t init_level; /* 503 * How far we've initialized 504 * this structure. 505 */ 506 }; 507 508 struct ahc_softc { 509 struct device sc_dev; 510 511 struct scsipi_channel sc_channel; 512 struct scsipi_channel sc_channel_b; 513 struct scsipi_adapter sc_adapter; 514 515 bus_space_tag_t tag; 516 bus_space_handle_t bsh; 517 struct scb_data *scb_data; 518 519 #define AHC_NEG_PENDING 0x01 520 #define AHC_NEG_SDTRDONE 0x02 521 #define AHC_NEG_WDTRDONE 0x04 522 u_int8_t inited_targets[16]; 523 u_int8_t inited_channels[2]; 524 525 /* 526 * SCBs that have been send to the controller 527 */ 528 LIST_HEAD(, scb) pending_ccbs; 529 530 /* 531 * Target mode related state kept on a per enabled lun basis. 532 * Targets that are not enabled will have null entries. 533 * As an initiator, we keep one target entry for our initiator 534 * ID to store our sync/wide transfer settings. 535 */ 536 struct tmode_tstate* enabled_targets[16]; 537 538 /* 539 * The black hole device responsible for handling requests for 540 * disabled luns on enabled targets. 541 */ 542 struct tmode_lstate* black_hole; 543 544 /* 545 * Device instance currently on the bus awaiting a continue TIO 546 * for a command that was not given the disconnect priveledge. 547 */ 548 struct tmode_lstate* pending_device; 549 550 /* 551 * Card characteristics 552 */ 553 ahc_chip chip; 554 ahc_feature features; 555 ahc_flag flags; 556 557 /* Values to store in the SEQCTL register for pause and unpause */ 558 u_int8_t unpause; 559 u_int8_t pause; 560 561 /* Command Queues */ 562 u_int8_t qoutfifonext; 563 u_int8_t qinfifonext; 564 u_int8_t *qoutfifo; 565 u_int8_t *qinfifo; 566 567 /* 568 * 256 byte array storing the SCBID of outstanding 569 * untagged SCBs indexed by TCL. 570 */ 571 u_int8_t *untagged_scbs; 572 573 /* Channel Names ('A', 'B', etc.) */ 574 char channel; 575 char channel_b; 576 577 /* Initiator Bus ID */ 578 u_int8_t our_id; 579 u_int8_t our_id_b; 580 581 /* Targets that need negotiation messages */ 582 u_int16_t targ_msg_req; 583 584 /* 585 * PCI error detection and data for running the 586 * PCI error interrupt handler. 587 */ 588 int unsolicited_ints; 589 590 /* 591 * Target incoming command FIFO. 592 */ 593 struct target_cmd *targetcmds; 594 u_int8_t tqinfifonext; 595 596 /* 597 * Incoming and outgoing message handling. 598 */ 599 u_int8_t send_msg_perror; 600 ahc_msg_type msg_type; 601 u_int8_t msgout_buf[8]; /* Message we are sending */ 602 u_int8_t msgin_buf[8]; /* Message we are receiving */ 603 u_int msgout_len; /* Length of message to send */ 604 u_int msgout_index; /* Current index in msgout */ 605 u_int msgin_index; /* Current index in msgin */ 606 607 void *ih; 608 bus_dma_tag_t parent_dmat; 609 int sc_dmaflags; 610 bus_dmamap_t shared_data_dmamap; 611 bus_addr_t shared_data_busaddr; 612 bus_dma_segment_t shared_data_seg; 613 int shared_data_nseg; 614 int shared_data_size; 615 bus_addr_t dma_bug_buf; 616 617 /* Number of enabled target mode device on this card */ 618 u_int enabled_luns; 619 620 /* Initialization level of this data structure */ 621 u_int init_level; 622 623 u_int16_t user_discenable;/* Disconnection allowed */ 624 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 625 626 void *bus_data; 627 int (*bus_intr)(struct ahc_softc *); 628 }; 629 630 struct full_ahc_softc { 631 struct ahc_softc softc; 632 struct scb_data scb_data_storage; 633 }; 634 635 /* #define AHC_DEBUG 0x019f */ 636 637 #ifdef AHC_DEBUG 638 /* Different debugging levels used when AHC_DEBUG is defined */ 639 #define AHC_SHOWMISC 0x0001 640 #define AHC_SHOWCMDS 0x0002 641 #define AHC_SHOWSCBS 0x0004 642 #define AHC_SHOWABORTS 0x0008 643 #define AHC_SHOWSENSE 0x0010 644 #define AHC_SHOWSCBCNT 0x0020 645 #define AHC_SHOWSCBALLOC 0x0040 646 #define AHC_SHOWINTR 0x0080 647 #define AHC_SHOWMSG 0x0100 648 649 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 650 #endif 651 652 char *ahc_name(struct ahc_softc *ahc); 653 654 int ahc_alloc(struct ahc_softc *ahc, bus_space_handle_t sh, 655 bus_space_tag_t st, bus_dma_tag_t parent_dmat, 656 ahc_chip chip, ahc_feature features, ahc_flag flags); 657 int ahc_reset(struct ahc_softc *ahc); 658 void ahc_free(struct ahc_softc *); 659 int ahc_probe_scbs(struct ahc_softc *); 660 int ahc_init(struct ahc_softc *); 661 int ahc_attach(struct ahc_softc *); 662 int ahc_intr(void *arg); 663 664 /* 665 * SEEPROM related functions. 666 */ 667 void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 668 669 670 #define ahc_inb(ahc, port) \ 671 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 672 673 #define ahc_outb(ahc, port, value) \ 674 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 675 676 #define ahc_outsb(ahc, port, valp, count) \ 677 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 678 679 #define ahc_insb(ahc, port, valp, count) \ 680 bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 681 682 #endif /* _AIC7XXX_H_ */ 683
Indexes created Thu Oct 02 14:10:14 GMT 2025