aic7xxxvar.h revision 1.4
1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: aic7xxxvar.h,v 1.4 1996/05/16 03:59:08 mycroft Exp $ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #if defined(__FreeBSD__) 40 #include "ahc.h" /* for NAHC from config */ 41 #endif 42 43 /* from FreeBSD <sys/queue.h> */ 44 #if defined(__NetBSD__) && !defined(STAILQ_ENTRY) 45 /* 46 * Singly-linked Tail queue definitions. 47 */ 48 #define STAILQ_HEAD(name, type) \ 49 struct name { \ 50 struct type *stqh_first;/* first element */ \ 51 struct type **stqh_last;/* addr of last next element */ \ 52 } 53 54 #define STAILQ_ENTRY(type) \ 55 struct { \ 56 struct type *stqe_next; /* next element */ \ 57 } 58 59 /* 60 * Singly-linked Tail queue functions. 61 */ 62 #define STAILQ_INIT(head) { \ 63 (head)->stqh_first = NULL; \ 64 (head)->stqh_last = &(head)->stqh_first; \ 65 } 66 67 #define STAILQ_INSERT_HEAD(head, elm, field) { \ 68 if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \ 69 (head)->stqh_last = &(elm)->field.stqe_next; \ 70 (head)->stqh_first = (elm); \ 71 } 72 73 #define STAILQ_INSERT_TAIL(head, elm, field) { \ 74 (elm)->field.stqe_next = NULL; \ 75 *(head)->stqh_last = (elm); \ 76 (head)->stqh_last = &(elm)->field.stqe_next; \ 77 } 78 79 #define STAILQ_INSERT_AFTER(head, tqelm, elm, field) { \ 80 if (((elm)->field.stqe_next = (tqelm)->field.stqe_next) == NULL)\ 81 (head)->stqh_last = &(elm)->field.stqe_next; \ 82 (tqelm)->field.stqe_next = (elm); \ 83 } 84 85 #define STAILQ_REMOVE_HEAD(head, field) { \ 86 if (((head)->stqh_first = \ 87 (head)->stqh_first->field.stqe_next) == NULL) \ 88 (head)->stqh_last = &(head)->stqh_first; \ 89 } 90 91 #define STAILQ_REMOVE(head, elm, type, field) { \ 92 if ((head)->stqh_first == (elm)) { \ 93 STAILQ_REMOVE_HEAD(head, field); \ 94 } \ 95 else { \ 96 struct type *curelm = (head)->stqh_first; \ 97 while( curelm->field.stqe_next != (elm) ) \ 98 curelm = curelm->field.stqe_next; \ 99 if((curelm->field.stqe_next = \ 100 curelm->field.stqe_next->field.stqe_next) == NULL) \ 101 (head)->stqh_last = &(curelm)->field.stqe_next; \ 102 } \ 103 } 104 105 #endif /* defined(__NetBSD__) && !defined(STAILQ_ENTRY) */ 106 107 #if defined(__FreeBSD__) 108 #define AHC_INB(ahc, port) \ 109 inb((ahc)->baseport+(port)) 110 #define AHC_INSB(ahc, port, valp, size) \ 111 insb((ahc)->baseport+(port), valp, size) 112 #define AHC_OUTB(ahc, port, val) \ 113 outb((ahc)->baseport+(port), val) 114 #define AHC_OUTSB(ahc, port, valp, size) \ 115 outsb((ahc)->baseport+(port), valp, size) 116 #define AHC_OUTSL(ahc, port, valp, size) \ 117 outsl((ahc)->baseport+(port), valp, size) 118 #elif defined(__NetBSD__) 119 #define AHC_INB(ahc, port) \ 120 bus_io_read_1((ahc)->sc_bc, (ahc)->sc_ioh, port) 121 #define AHC_INSB(ahc, port, valp, size) \ 122 bus_io_read_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 123 #define AHC_OUTB(ahc, port, val) \ 124 bus_io_write_1((ahc)->sc_bc, (ahc)->sc_ioh, port, val) 125 #define AHC_OUTSB(ahc, port, valp, size) \ 126 bus_io_write_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 127 #define AHC_OUTSL(ahc, port, valp, size) \ 128 bus_io_write_multi_4((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 129 #endif 130 131 #define AHC_NSEG 256 /* number of dma segments supported */ 132 133 #define AHC_SCB_MAX 255 /* 134 * Up to 255 SCBs on some types of aic7xxx 135 * based boards. The aic7870 have 16 internal 136 * SCBs, but external SRAM bumps this to 255. 137 * The aic7770 family have only 4, and the 138 * aic7850 has only 3. 139 */ 140 141 142 typedef unsigned long int physaddr; 143 #if defined(__FreeBSD__) 144 extern u_long ahc_unit; 145 #endif 146 147 struct ahc_dma_seg { 148 physaddr addr; 149 long len; 150 }; 151 152 typedef enum { 153 AHC_NONE = 0x000, 154 AHC_ULTRA = 0x001, /* Supports 20MHz Transfers */ 155 AHC_WIDE = 0x002, /* Wide Channel */ 156 AHC_TWIN = 0x008, /* Twin Channel */ 157 AHC_AIC7770 = 0x010, 158 AHC_AIC7850 = 0x020, 159 AHC_AIC7860 = 0x021, /* ULTRA version of the aic7850 */ 160 AHC_AIC7870 = 0x040, 161 AHC_AIC7880 = 0x041, 162 AHC_AIC78X0 = 0x060, /* PCI Based Controller */ 163 AHC_274 = 0x110, /* EISA Based Controller */ 164 AHC_284 = 0x210, /* VL/ISA Based Controller */ 165 AHC_294 = 0x440, /* PCI Based Controller */ 166 AHC_294U = 0x441, /* ULTRA PCI Based Controller */ 167 AHC_394 = 0x840, /* Twin Channel PCI Controller */ 168 AHC_394U = 0x841, /* Twin, ULTRA Channel PCI Controller */ 169 }ahc_type; 170 171 typedef enum { 172 AHC_FNONE = 0x00, 173 AHC_INIT = 0x01, 174 AHC_RUNNING = 0x02, 175 AHC_PAGESCBS = 0x04, /* Enable SCB paging */ 176 AHC_CHANNEL_B_PRIMARY = 0x08, /* 177 * On twin channel adapters, probe 178 * channel B first since it is the 179 * primary bus. 180 */ 181 AHC_USEDEFAULTS = 0x10, /* 182 * For cards without an seeprom 183 * or a BIOS to initialize the chip's 184 * SRAM, we use the default target 185 * settings. 186 */ 187 AHC_CHNLB = 0x20, /* 188 * Second controller on 3940 189 * Also encodes the offset in the 190 * SEEPROM for CHNLB info (32) 191 */ 192 }ahc_flag; 193 194 typedef enum { 195 SCB_FREE = 0x000, 196 SCB_ACTIVE = 0x001, 197 SCB_ABORTED = 0x002, 198 SCB_DEVICE_RESET = 0x004, 199 SCB_IMMED = 0x008, 200 SCB_SENSE = 0x010, 201 SCB_TIMEDOUT = 0x020, 202 SCB_QUEUED_FOR_DONE = 0x040, 203 SCB_PAGED_OUT = 0x080, 204 SCB_WAITINGQ = 0x100, 205 SCB_ASSIGNEDQ = 0x200, 206 SCB_SENTORDEREDTAG = 0x400 207 }scb_flag; 208 209 /* 210 * The driver keeps up to MAX_SCB scb structures per card in memory. Only the 211 * first 28 bytes of the structure need to be transfered to the card during 212 * normal operation. The fields starting at byte 28 are used for kernel level 213 * bookkeeping. 214 */ 215 struct scb { 216 /* ------------ Begin hardware supported fields ---------------- */ 217 /*0*/ u_char control; 218 /*1*/ u_char tcl; /* 4/1/3 bits */ 219 /*2*/ u_char status; 220 /*3*/ u_char SG_segment_count; 221 /*4*/ physaddr SG_list_pointer; 222 /*8*/ u_char residual_SG_segment_count; 223 /*9*/ u_char residual_data_count[3]; 224 /*12*/ physaddr data; 225 /*16*/ u_long datalen; /* Really only three bits, but its 226 * faster to treat it as a long on 227 * a quad boundary. 228 */ 229 /*20*/ physaddr cmdpointer; 230 /*24*/ u_char cmdlen; 231 /*25*/ u_char tag; /* Index into our kernel SCB array. 232 * Also used as the tag for tagged I/O 233 */ 234 #define SCB_PIO_TRANSFER_SIZE 26 /* amount we need to upload/download 235 * via PIO to initialize a transaction. 236 */ 237 /*26*/ u_char next; /* Used for threading SCBs in the 238 * "Waiting for Selection" and 239 * "Disconnected SCB" lists down 240 * in the sequencer. 241 */ 242 /*27*/ u_char prev; 243 /*-----------------end of hardware supported fields----------------*/ 244 STAILQ_ENTRY(scb) links; /* for chaining */ 245 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 246 scb_flag flags; 247 u_char position; /* Position in card's scbarray */ 248 struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed)); 249 struct scsi_sense sense_cmd; /* SCSI command block */ 250 }; 251 252 struct ahc_data { 253 #if defined(__FreeBSD__) 254 int unit; 255 #elif defined(__NetBSD__) 256 struct device sc_dev; 257 void *sc_ih; 258 bus_chipset_tag_t sc_bc; 259 bus_io_handle_t sc_ioh; 260 #endif 261 ahc_type type; 262 ahc_flag flags; 263 #if defined(__FreeBSD__) 264 u_long baseport; 265 #endif 266 struct scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */ 267 struct scb *pagedout_ntscbs[16];/* 268 * Paged out, non-tagged scbs 269 * indexed by target. 270 */ 271 STAILQ_HEAD(, scb) free_scbs; /* 272 * SCBs assigned to free slots 273 * on the card. (no paging required) 274 */ 275 STAILQ_HEAD(, scb) page_scbs; /* 276 * SCBs that will require paging 277 * before use (no assigned slot) 278 */ 279 STAILQ_HEAD(, scb) waiting_scbs;/* 280 * SCBs waiting to be paged in 281 * and started. 282 */ 283 STAILQ_HEAD(, scb)assigned_scbs;/* 284 * SCBs that were waiting but have 285 * now been assigned a slot by 286 * ahc_free_scb. 287 */ 288 struct scsi_link sc_link; 289 struct scsi_link sc_link_b; /* Second bus for Twin channel cards */ 290 u_short needsdtr_orig; /* Targets we initiate sync neg with */ 291 u_short needwdtr_orig; /* Targets we initiate wide neg with */ 292 u_short needsdtr; /* Current list of negotiated targets */ 293 u_short needwdtr; /* Current list of negotiated targets */ 294 u_short sdtrpending; /* Pending SDTR to these targets */ 295 u_short wdtrpending; /* Pending WDTR to these targets */ 296 u_short tagenable; /* Targets that can handle tagqueing */ 297 u_short orderedtag; /* Targets to use ordered tag on */ 298 u_short discenable; /* Targets allowed to disconnect */ 299 u_char our_id; /* our scsi id */ 300 u_char our_id_b; /* B channel scsi id */ 301 u_char numscbs; 302 u_char activescbs; 303 u_char maxhscbs; /* Number of SCBs on the card */ 304 u_char maxscbs; /* 305 * Max SCBs we allocate total including 306 * any that will force us to page SCBs 307 */ 308 u_char qcntmask; 309 u_char unpause; 310 u_char pause; 311 u_char in_timeout; 312 }; 313 314 /* #define AHC_DEBUG */ 315 #ifdef AHC_DEBUG 316 /* Different debugging levels used when AHC_DEBUG is defined */ 317 #define AHC_SHOWMISC 0x0001 318 #define AHC_SHOWCMDS 0x0002 319 #define AHC_SHOWSCBS 0x0004 320 #define AHC_SHOWABORTS 0x0008 321 #define AHC_SHOWSENSE 0x0010 322 #define AHC_SHOWSCBCNT 0x0020 323 324 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 325 #endif 326 327 #if defined(__FreeBSD__) 328 329 char *ahc_name __P((struct ahc_data *ahc)); 330 331 void ahc_reset __P((u_long iobase)); 332 struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_flag flags)); 333 #elif defined(__NetBSD__) 334 335 #define ahc_name(ahc) (ahc)->sc_dev.dv_xname 336 337 void ahc_reset __P((char *devname, bus_chipset_tag_t bc, bus_io_handle_t ioh)); 338 void ahc_construct __P((struct ahc_data *ahc, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags)); 339 #endif 340 void ahc_free __P((struct ahc_data *)); 341 int ahc_init __P((struct ahc_data *)); 342 int ahc_attach __P((struct ahc_data *)); 343 #if defined(__FreeBSD__) 344 void ahc_intr __P((void *arg)); 345 #elif defined(__NetBSD__) 346 int ahc_intr __P((void *arg)); 347 #endif 348 349 #endif /* _AIC7XXX_H_ */ 350
Indexes created Tue Sep 30 20:09:53 GMT 2025