aic7xxxvar.h revision 1.6
1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: aic7xxxvar.h,v 1.6 1996/05/16 05:22:28 mycroft Exp $ 34 */ 35 36 #ifndef _AIC7XXX_H_ 37 #define _AIC7XXX_H_ 38 39 #if defined(__FreeBSD__) 40 #include "ahc.h" /* for NAHC from config */ 41 #endif 42 43 #if defined(__FreeBSD__) 44 #define AHC_INB(ahc, port) \ 45 inb((ahc)->baseport+(port)) 46 #define AHC_INSB(ahc, port, valp, size) \ 47 insb((ahc)->baseport+(port), valp, size) 48 #define AHC_OUTB(ahc, port, val) \ 49 outb((ahc)->baseport+(port), val) 50 #define AHC_OUTSB(ahc, port, valp, size) \ 51 outsb((ahc)->baseport+(port), valp, size) 52 #define AHC_OUTSL(ahc, port, valp, size) \ 53 outsl((ahc)->baseport+(port), valp, size) 54 #elif defined(__NetBSD__) 55 #define AHC_INB(ahc, port) \ 56 bus_io_read_1((ahc)->sc_bc, (ahc)->sc_ioh, port) 57 #define AHC_INSB(ahc, port, valp, size) \ 58 bus_io_read_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 59 #define AHC_OUTB(ahc, port, val) \ 60 bus_io_write_1((ahc)->sc_bc, (ahc)->sc_ioh, port, val) 61 #define AHC_OUTSB(ahc, port, valp, size) \ 62 bus_io_write_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 63 #define AHC_OUTSL(ahc, port, valp, size) \ 64 bus_io_write_multi_4((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size) 65 #endif 66 67 #define AHC_NSEG 256 /* number of dma segments supported */ 68 69 #define AHC_SCB_MAX 255 /* 70 * Up to 255 SCBs on some types of aic7xxx 71 * based boards. The aic7870 have 16 internal 72 * SCBs, but external SRAM bumps this to 255. 73 * The aic7770 family have only 4, and the 74 * aic7850 has only 3. 75 */ 76 77 78 typedef unsigned long int physaddr; 79 #if defined(__FreeBSD__) 80 extern u_long ahc_unit; 81 #endif 82 83 struct ahc_dma_seg { 84 physaddr addr; 85 long len; 86 }; 87 88 typedef enum { 89 AHC_NONE = 0x000, 90 AHC_ULTRA = 0x001, /* Supports 20MHz Transfers */ 91 AHC_WIDE = 0x002, /* Wide Channel */ 92 AHC_TWIN = 0x008, /* Twin Channel */ 93 AHC_AIC7770 = 0x010, 94 AHC_AIC7850 = 0x020, 95 AHC_AIC7860 = 0x021, /* ULTRA version of the aic7850 */ 96 AHC_AIC7870 = 0x040, 97 AHC_AIC7880 = 0x041, 98 AHC_AIC78X0 = 0x060, /* PCI Based Controller */ 99 AHC_274 = 0x110, /* EISA Based Controller */ 100 AHC_284 = 0x210, /* VL/ISA Based Controller */ 101 AHC_294 = 0x440, /* PCI Based Controller */ 102 AHC_294U = 0x441, /* ULTRA PCI Based Controller */ 103 AHC_394 = 0x840, /* Twin Channel PCI Controller */ 104 AHC_394U = 0x841, /* Twin, ULTRA Channel PCI Controller */ 105 }ahc_type; 106 107 typedef enum { 108 AHC_FNONE = 0x00, 109 AHC_INIT = 0x01, 110 AHC_RUNNING = 0x02, 111 AHC_PAGESCBS = 0x04, /* Enable SCB paging */ 112 AHC_CHANNEL_B_PRIMARY = 0x08, /* 113 * On twin channel adapters, probe 114 * channel B first since it is the 115 * primary bus. 116 */ 117 AHC_USEDEFAULTS = 0x10, /* 118 * For cards without an seeprom 119 * or a BIOS to initialize the chip's 120 * SRAM, we use the default target 121 * settings. 122 */ 123 AHC_CHNLB = 0x20, /* 124 * Second controller on 3940 125 * Also encodes the offset in the 126 * SEEPROM for CHNLB info (32) 127 */ 128 }ahc_flag; 129 130 typedef enum { 131 SCB_FREE = 0x000, 132 SCB_ACTIVE = 0x001, 133 SCB_ABORTED = 0x002, 134 SCB_DEVICE_RESET = 0x004, 135 SCB_IMMED = 0x008, 136 SCB_SENSE = 0x010, 137 SCB_TIMEDOUT = 0x020, 138 SCB_QUEUED_FOR_DONE = 0x040, 139 SCB_PAGED_OUT = 0x080, 140 SCB_WAITINGQ = 0x100, 141 SCB_ASSIGNEDQ = 0x200, 142 SCB_SENTORDEREDTAG = 0x400 143 }scb_flag; 144 145 /* 146 * The driver keeps up to MAX_SCB scb structures per card in memory. Only the 147 * first 28 bytes of the structure need to be transfered to the card during 148 * normal operation. The fields starting at byte 28 are used for kernel level 149 * bookkeeping. 150 */ 151 struct scb { 152 /* ------------ Begin hardware supported fields ---------------- */ 153 /*0*/ u_char control; 154 /*1*/ u_char tcl; /* 4/1/3 bits */ 155 /*2*/ u_char status; 156 /*3*/ u_char SG_segment_count; 157 /*4*/ physaddr SG_list_pointer; 158 /*8*/ u_char residual_SG_segment_count; 159 /*9*/ u_char residual_data_count[3]; 160 /*12*/ physaddr data; 161 /*16*/ u_long datalen; /* Really only three bits, but its 162 * faster to treat it as a long on 163 * a quad boundary. 164 */ 165 /*20*/ physaddr cmdpointer; 166 /*24*/ u_char cmdlen; 167 /*25*/ u_char tag; /* Index into our kernel SCB array. 168 * Also used as the tag for tagged I/O 169 */ 170 #define SCB_PIO_TRANSFER_SIZE 26 /* amount we need to upload/download 171 * via PIO to initialize a transaction. 172 */ 173 /*26*/ u_char next; /* Used for threading SCBs in the 174 * "Waiting for Selection" and 175 * "Disconnected SCB" lists down 176 * in the sequencer. 177 */ 178 /*27*/ u_char prev; 179 /*-----------------end of hardware supported fields----------------*/ 180 SIMPLEQ_ENTRY(scb) links; /* for chaining */ 181 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 182 scb_flag flags; 183 u_char position; /* Position in card's scbarray */ 184 struct ahc_dma_seg ahc_dma[AHC_NSEG] __attribute__ ((packed)); 185 struct scsi_sense sense_cmd; /* SCSI command block */ 186 }; 187 188 struct ahc_data { 189 #if defined(__FreeBSD__) 190 int unit; 191 #elif defined(__NetBSD__) 192 struct device sc_dev; 193 void *sc_ih; 194 bus_chipset_tag_t sc_bc; 195 bus_io_handle_t sc_ioh; 196 #endif 197 ahc_type type; 198 ahc_flag flags; 199 #if defined(__FreeBSD__) 200 u_long baseport; 201 #endif 202 struct scb *scbarray[AHC_SCB_MAX]; /* Mirror boards scbarray */ 203 struct scb *pagedout_ntscbs[16];/* 204 * Paged out, non-tagged scbs 205 * indexed by target. 206 */ 207 SIMPLEQ_HEAD(, scb) free_scbs; /* 208 * SCBs assigned to free slots 209 * on the card. (no paging required) 210 */ 211 SIMPLEQ_HEAD(, scb) page_scbs; /* 212 * SCBs that will require paging 213 * before use (no assigned slot) 214 */ 215 SIMPLEQ_HEAD(, scb) waiting_scbs;/* 216 * SCBs waiting to be paged in 217 * and started. 218 */ 219 SIMPLEQ_HEAD(, scb)assigned_scbs;/* 220 * SCBs that were waiting but have 221 * now been assigned a slot by 222 * ahc_free_scb. 223 */ 224 struct scsi_link sc_link; 225 struct scsi_link sc_link_b; /* Second bus for Twin channel cards */ 226 u_short needsdtr_orig; /* Targets we initiate sync neg with */ 227 u_short needwdtr_orig; /* Targets we initiate wide neg with */ 228 u_short needsdtr; /* Current list of negotiated targets */ 229 u_short needwdtr; /* Current list of negotiated targets */ 230 u_short sdtrpending; /* Pending SDTR to these targets */ 231 u_short wdtrpending; /* Pending WDTR to these targets */ 232 u_short tagenable; /* Targets that can handle tagqueing */ 233 u_short orderedtag; /* Targets to use ordered tag on */ 234 u_short discenable; /* Targets allowed to disconnect */ 235 u_char our_id; /* our scsi id */ 236 u_char our_id_b; /* B channel scsi id */ 237 u_char numscbs; 238 u_char activescbs; 239 u_char maxhscbs; /* Number of SCBs on the card */ 240 u_char maxscbs; /* 241 * Max SCBs we allocate total including 242 * any that will force us to page SCBs 243 */ 244 u_char qcntmask; 245 u_char unpause; 246 u_char pause; 247 u_char in_timeout; 248 }; 249 250 /* #define AHC_DEBUG */ 251 #ifdef AHC_DEBUG 252 /* Different debugging levels used when AHC_DEBUG is defined */ 253 #define AHC_SHOWMISC 0x0001 254 #define AHC_SHOWCMDS 0x0002 255 #define AHC_SHOWSCBS 0x0004 256 #define AHC_SHOWABORTS 0x0008 257 #define AHC_SHOWSENSE 0x0010 258 #define AHC_SHOWSCBCNT 0x0020 259 260 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 261 #endif 262 263 #if defined(__FreeBSD__) 264 265 char *ahc_name __P((struct ahc_data *ahc)); 266 267 void ahc_reset __P((u_long iobase)); 268 struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_flag flags)); 269 #elif defined(__NetBSD__) 270 271 #define ahc_name(ahc) (ahc)->sc_dev.dv_xname 272 273 void ahc_reset __P((char *devname, bus_chipset_tag_t bc, bus_io_handle_t ioh)); 274 void ahc_construct __P((struct ahc_data *ahc, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags)); 275 #endif 276 void ahc_free __P((struct ahc_data *)); 277 int ahc_init __P((struct ahc_data *)); 278 int ahc_attach __P((struct ahc_data *)); 279 #if defined(__FreeBSD__) 280 void ahc_intr __P((void *arg)); 281 #elif defined(__NetBSD__) 282 int ahc_intr __P((void *arg)); 283 #endif 284 285 #endif /* _AIC7XXX_H_ */ 286
Indexes created Wed Oct 01 07:09:59 GMT 2025