am7930reg.h revision 1.1
1 /* $NetBSD: am7930reg.h,v 1.1 1995/04/24 19:17:17 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)bsd_audioreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Bit encodings for chip commands from "Microprocessor Access Guide for 49 * Indirect Registers", p.19 Am79C30A/32A Advanced Micro Devices spec 50 * sheet (preliminary). 51 * 52 * Indirect register numbers (the value written into cr to select a given 53 * chip registers) have the form AMDR_*. Register fields look like AMD_*. 54 */ 55 56 struct amd7930 { 57 u_char cr; /* command register (wo) */ 58 #define ir cr /* interrupt register (ro) */ 59 u_char dr; /* data register (rw) */ 60 u_char dsr1; /* D-channel status register 1 (ro) */ 61 u_char der; /* D-channel error register (ro) */ 62 u_char dctb; /* D-channel transmit register (wo) */ 63 #define dcrb dctb /* D-channel receive register (ro) */ 64 u_char bbtb; /* Bb-channel transmit register (wo) */ 65 #define bbrb bbtb /* Bb-channel receive register (ro) */ 66 u_char bctb; /* Bc-channel transmit register (wo) */ 67 #define bcrb bctb /* Bc-channel receive register (ro) */ 68 u_char dsr2; /* D-channel status register 2 (ro) */ 69 }; 70 71 #define AMDR_INIT 0x21 72 #define AMD_INIT_PMS_IDLE 0x00 73 #define AMD_INIT_PMS_ACTIVE 0x01 74 #define AMD_INIT_PMS_ACTIVE_DATA 0x02 75 #define AMD_INIT_INT_DISABLE (0x01 << 2) 76 #define AMD_INIT_CDS_DIV2 (0x00 << 3) 77 #define AMD_INIT_CDS_DIV1 (0x01 << 3) 78 #define AMD_INIT_CDS_DIV4 (0x02 << 3) 79 #define AMD_INIT_AS_RX (0x01 << 6) 80 #define AMD_INIT_AS_TX (0x01 << 7) 81 82 #define AMDR_LIU_LSR 0xa1 83 #define AMDR_LIU_LPR 0xa2 84 #define AMDR_LIU_LMR1 0xa3 85 #define AMDR_LIU_LMR2 0xa4 86 #define AMDR_LIU_2_4 0xa5 87 #define AMDR_LIU_MF 0xa6 88 #define AMDR_LIU_MFSB 0xa7 89 #define AMDR_LIU_MFQB 0xa8 90 91 #define AMDR_MUX_MCR1 0x41 92 #define AMDR_MUX_MCR2 0x42 93 #define AMDR_MUX_MCR3 0x43 94 #define AMD_MCRCHAN_NC 0x00 95 #define AMD_MCRCHAN_B1 0x01 96 #define AMD_MCRCHAN_B2 0x02 97 #define AMD_MCRCHAN_BA 0x03 98 #define AMD_MCRCHAN_BB 0x04 99 #define AMD_MCRCHAN_BC 0x05 100 #define AMD_MCRCHAN_BD 0x06 101 #define AMD_MCRCHAN_BE 0x07 102 #define AMD_MCRCHAN_BF 0x08 103 #define AMDR_MUX_MCR4 0x44 104 #define AMD_MCR4_INT_ENABLE (1 << 3) 105 #define AMD_MCR4_SWAPBB (1 << 4) 106 #define AMD_MCR4_SWAPBC (1 << 5) 107 108 #define AMDR_MUX_1_4 0x45 109 110 #define AMDR_MAP_X 0x61 111 #define AMDR_MAP_R 0x62 112 #define AMDR_MAP_GX 0x63 113 #define AMDR_MAP_GR 0x64 114 #define AMDR_MAP_GER 0x65 115 #define AMDR_MAP_STG 0x66 116 #define AMDR_MAP_FTGR 0x67 117 #define AMDR_MAP_ATGR 0x68 118 #define AMDR_MAP_MMR1 0x69 119 #define AMD_MMR1_ALAW 0x01 120 #define AMD_MMR1_GX 0x02 121 #define AMD_MMR1_GR 0x04 122 #define AMD_MMR1_GER 0x08 123 #define AMD_MMR1_X 0x10 124 #define AMD_MMR1_R 0x20 125 #define AMD_MMR1_STG 0x40 126 #define AMD_MMR1_LOOP 0x80 127 #define AMDR_MAP_MMR2 0x6a 128 #define AMD_MMR2_AINB 0x01 129 #define AMD_MMR2_LS 0x02 130 #define AMD_MMR2_DTMF 0x04 131 #define AMD_MMR2_GEN 0x08 132 #define AMD_MMR2_RNG 0x10 133 #define AMD_MMR2_DIS_HPF 0x20 134 #define AMD_MMR2_DIS_AZ 0x40 135 #define AMDR_MAP_1_10 0x6b 136 137 #define AMDR_DLC_FRAR123 0x81 138 #define AMDR_DLC_SRAR123 0x82 139 #define AMDR_DLC_TAR 0x83 140 #define AMDR_DLC_DRLR 0x84 141 #define AMDR_DLC_DTCR 0x85 142 #define AMDR_DLC_DMR1 0x86 143 #define AMDR_DLC_DMR2 0x87 144 #define AMDR_DLC_1_7 0x88 145 #define AMDR_DLC_DRCR 0x89 146 #define AMDR_DLC_RNGR1 0x8a 147 #define AMDR_DLC_RNGR2 0x8b 148 #define AMDR_DLC_FRAR4 0x8c 149 #define AMDR_DLC_SRAR4 0x8d 150 #define AMDR_DLC_DMR3 0x8e 151 #define AMDR_DLC_DMR4 0x8f 152 #define AMDR_DLC_12_15 0x90 153 #define AMDR_DLC_ASR 0x91 154
Indexes created Mon Sep 29 21:09:56 GMT 2025