am7990reg.h revision 1.1
1 /* $NetBSD: am7990reg.h,v 1.1 1995/04/11 04:17:50 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 40 */ 41 42 #define LEBLEN 1536 /* ETHERMTU + header + CRC */ 43 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 44 45 /* 46 * Receive message descriptor 47 */ 48 struct lermd { 49 u_int16_t rmd0; 50 #if BYTE_ORDER == BIG_ENDIAN 51 u_int8_t rmd1_bits; 52 u_int8_t rmd1_hadr; 53 #else 54 u_int8_t rmd1_hadr; 55 u_int8_t rmd1_bits; 56 #endif 57 int16_t rmd2; 58 u_int16_t rmd3; 59 }; 60 61 /* 62 * Transmit message descriptor 63 */ 64 struct letmd { 65 u_int16_t tmd0; 66 #if BYTE_ORDER == BIG_ENDIAN 67 u_int8_t tmd1_bits; 68 u_int8_t tmd1_hadr; 69 #else 70 u_int8_t tmd1_hadr; 71 u_int8_t tmd1_bits; 72 #endif 73 int16_t tmd2; 74 u_int16_t tmd3; 75 }; 76 77 /* 78 * Initialization block 79 */ 80 struct leinit { 81 u_int16_t init_mode; /* +0x0000 */ 82 u_int16_t init_padr[3]; /* +0x0002 */ 83 u_int16_t init_ladrf[4]; /* +0x0008 */ 84 u_int16_t init_rdra; /* +0x0010 */ 85 u_int16_t init_rlen; /* +0x0012 */ 86 u_int16_t init_tdra; /* +0x0014 */ 87 u_int16_t init_tlen; /* +0x0016 */ 88 int16_t pad0[4]; /* Pad to 16 shorts */ 89 }; 90 91 #define LE_INITADDR(sc) (sc->sc_initaddr) 92 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 93 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 94 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix)) 95 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix)) 96 97 /* register addresses */ 98 #define LE_CSR0 0x0000 /* Control and status register */ 99 #define LE_CSR1 0x0001 /* low address of init block */ 100 #define LE_CSR2 0x0002 /* high address of init block */ 101 #define LE_CSR3 0x0003 /* Bus master and control */ 102 103 /* Control and status register 0 (csr0) */ 104 #define LE_C0_ERR 0x8000 /* error summary */ 105 #define LE_C0_BABL 0x4000 /* transmitter timeout error */ 106 #define LE_C0_CERR 0x2000 /* collision */ 107 #define LE_C0_MISS 0x1000 /* missed a packet */ 108 #define LE_C0_MERR 0x0800 /* memory error */ 109 #define LE_C0_RINT 0x0400 /* receiver interrupt */ 110 #define LE_C0_TINT 0x0200 /* transmitter interrupt */ 111 #define LE_C0_IDON 0x0100 /* initalization done */ 112 #define LE_C0_INTR 0x0080 /* interrupt condition */ 113 #define LE_C0_INEA 0x0040 /* interrupt enable */ 114 #define LE_C0_RXON 0x0020 /* receiver on */ 115 #define LE_C0_TXON 0x0010 /* transmitter on */ 116 #define LE_C0_TDMD 0x0008 /* transmit demand */ 117 #define LE_C0_STOP 0x0004 /* disable all external activity */ 118 #define LE_C0_STRT 0x0002 /* enable external activity */ 119 #define LE_C0_INIT 0x0001 /* begin initalization */ 120 121 #define LE_C0_BITS \ 122 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 123 \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 124 125 /* Control and status register 3 (csr3) */ 126 #define LE_C3_BSWP 0x0004 /* byte swap */ 127 #define LE_C3_ACON 0x0002 /* ALE control, eh? */ 128 #define LE_C3_BCON 0x0001 /* byte control */ 129 130 /* Initialzation block (mode) */ 131 #define LE_MODE_PROM 0x8000 /* promiscuous mode */ 132 /* 0x7f80 reserved, must be zero */ 133 #define LE_MODE_INTL 0x0040 /* internal loopback */ 134 #define LE_MODE_DRTY 0x0020 /* disable retry */ 135 #define LE_MODE_COLL 0x0010 /* force a collision */ 136 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 137 #define LE_MODE_LOOP 0x0004 /* loopback mode */ 138 #define LE_MODE_DTX 0x0002 /* disable transmitter */ 139 #define LE_MODE_DRX 0x0001 /* disable receiver */ 140 #define LE_MODE_NORMAL 0 /* none of the above */ 141 142 /* Receive message descriptor 1 (rmd1_bits) */ 143 #define LE_R1_OWN 0x80 /* LANCE owns the packet */ 144 #define LE_R1_ERR 0x40 /* error summary */ 145 #define LE_R1_FRAM 0x20 /* framing error */ 146 #define LE_R1_OFLO 0x10 /* overflow error */ 147 #define LE_R1_CRC 0x08 /* CRC error */ 148 #define LE_R1_BUFF 0x04 /* buffer error */ 149 #define LE_R1_STP 0x02 /* start of packet */ 150 #define LE_R1_ENP 0x01 /* end of packet */ 151 152 #define LE_R1_BITS \ 153 "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP" 154 155 /* Transmit message descriptor 1 (tmd1_bits) */ 156 #define LE_T1_OWN 0x80 /* LANCE owns the packet */ 157 #define LE_T1_ERR 0x40 /* error summary */ 158 #define LE_T1_MORE 0x10 /* multiple collisions */ 159 #define LE_T1_ONE 0x08 /* single collision */ 160 #define LE_T1_DEF 0x04 /* defferred transmit */ 161 #define LE_T1_STP 0x02 /* start of packet */ 162 #define LE_T1_ENP 0x01 /* end of packet */ 163 164 #define LE_T1_BITS \ 165 "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP" 166 167 /* Transmit message descriptor 3 (tmd3) */ 168 #define LE_T3_BUFF 0x8000 /* buffer error */ 169 #define LE_T3_UFLO 0x4000 /* underflow error */ 170 #define LE_T3_LCOL 0x1000 /* late collision */ 171 #define LE_T3_LCAR 0x0800 /* loss of carrier */ 172 #define LE_T3_RTRY 0x0400 /* retry error */ 173 #define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */ 174 175 #define LE_XMD2_ONES 0xf000 176 177 #define LE_T3_BITS \ 178 "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY" 179
Indexes created Mon Sep 29 21:09:56 GMT 2025