anreg.h revision 1.3.2.3
1 1.3.2.3 he /* $NetBSD: anreg.h,v 1.3.2.3 2001/03/11 22:18:50 he Exp $ */ 2 1.3.2.2 he /* 3 1.3.2.2 he * Copyright (c) 1997, 1998, 1999 4 1.3.2.2 he * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 5 1.3.2.2 he * 6 1.3.2.2 he * Redistribution and use in source and binary forms, with or without 7 1.3.2.2 he * modification, are permitted provided that the following conditions 8 1.3.2.2 he * are met: 9 1.3.2.2 he * 1. Redistributions of source code must retain the above copyright 10 1.3.2.2 he * notice, this list of conditions and the following disclaimer. 11 1.3.2.2 he * 2. Redistributions in binary form must reproduce the above copyright 12 1.3.2.2 he * notice, this list of conditions and the following disclaimer in the 13 1.3.2.2 he * documentation and/or other materials provided with the distribution. 14 1.3.2.2 he * 3. All advertising materials mentioning features or use of this software 15 1.3.2.2 he * must display the following acknowledgement: 16 1.3.2.2 he * This product includes software developed by Bill Paul. 17 1.3.2.2 he * 4. Neither the name of the author nor the names of any co-contributors 18 1.3.2.2 he * may be used to endorse or promote products derived from this software 19 1.3.2.2 he * without specific prior written permission. 20 1.3.2.2 he * 21 1.3.2.2 he * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 1.3.2.2 he * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 1.3.2.2 he * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 1.3.2.2 he * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 1.3.2.2 he * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 1.3.2.2 he * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 1.3.2.2 he * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.3.2.2 he * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 1.3.2.2 he * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 1.3.2.2 he * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 1.3.2.2 he * THE POSSIBILITY OF SUCH DAMAGE. 32 1.3.2.2 he * 33 1.3.2.2 he * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.3 2000/11/13 23:04:12 wpaul Exp $ 34 1.3.2.2 he */ 35 1.3.2.2 he 36 1.3.2.2 he #define AN_TIMEOUT 65536 37 1.3.2.2 he 38 1.3.2.2 he /* Default network name: ANY */ 39 1.3.2.2 he #define AN_DEFAULT_NETNAME "" 40 1.3.2.2 he 41 1.3.2.2 he /* The nodename must be less than 16 bytes */ 42 1.3.2.2 he #define AN_DEFAULT_NODENAME "NetBSD" 43 1.3.2.2 he 44 1.3.2.2 he #define AN_DEFAULT_IBSS "NetBSD IBSS" 45 1.3.2.2 he 46 1.3.2.2 he /* 47 1.3.2.2 he * register space access macros 48 1.3.2.2 he */ 49 1.3.2.2 he #define CSR_WRITE_2(sc, reg, val) \ 50 1.3.2.2 he bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val) 51 1.3.2.2 he 52 1.3.2.2 he #define CSR_READ_2(sc, reg) \ 53 1.3.2.2 he bus_space_read_2(sc->an_btag, sc->an_bhandle, reg) 54 1.3.2.2 he 55 1.3.2.2 he #define CSR_WRITE_1(sc, reg, val) \ 56 1.3.2.2 he bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val) 57 1.3.2.2 he 58 1.3.2.2 he #define CSR_READ_1(sc, reg) \ 59 1.3.2.2 he bus_space_read_1(sc->an_btag, sc->an_bhandle, reg) 60 1.3.2.2 he 61 1.3.2.2 he /* 62 1.3.2.2 he * Size of Aironet I/O space. 63 1.3.2.2 he */ 64 1.3.2.2 he #define AN_IOSIZ 0x40 65 1.3.2.2 he 66 1.3.2.2 he /* 67 1.3.2.2 he * Hermes register definitions and what little I know about them. 68 1.3.2.2 he */ 69 1.3.2.2 he 70 1.3.2.2 he /* Hermes command/status registers. */ 71 1.3.2.2 he #define AN_COMMAND 0x00 72 1.3.2.2 he #define AN_PARAM0 0x02 73 1.3.2.2 he #define AN_PARAM1 0x04 74 1.3.2.2 he #define AN_PARAM2 0x06 75 1.3.2.2 he #define AN_STATUS 0x08 76 1.3.2.2 he #define AN_RESP0 0x0A 77 1.3.2.2 he #define AN_RESP1 0x0C 78 1.3.2.2 he #define AN_RESP2 0x0E 79 1.3.2.2 he #define AN_LINKSTAT 0x10 80 1.3.2.2 he 81 1.3.2.2 he /* Command register */ 82 1.3.2.2 he #define AN_CMD_BUSY 0x8000 /* busy bit */ 83 1.3.2.2 he #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */ 84 1.3.2.2 he #define AN_CMD_CODE_MASK 0x003F 85 1.3.2.2 he #define AN_CMD_QUAL_MASK 0x7F00 86 1.3.2.2 he 87 1.3.2.2 he /* Command codes */ 88 1.3.2.2 he #define AN_CMD_NOOP 0x0000 /* no-op */ 89 1.3.2.2 he #define AN_CMD_ENABLE 0x0001 /* enable */ 90 1.3.2.2 he #define AN_CMD_DISABLE 0x0002 /* disable */ 91 1.3.2.2 he #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */ 92 1.3.2.2 he #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */ 93 1.3.2.2 he #define AN_CMD_HOST_SLEEP 0x0005 94 1.3.2.2 he #define AN_CMD_MAGIC_PKT 0x0006 95 1.3.2.2 he #define AN_CMD_READCFG 0x0008 96 1.3.2.2 he #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */ 97 1.3.2.2 he #define AN_CMD_TX 0x000B /* transmit */ 98 1.3.2.2 he #define AN_CMD_DEALLOC_MEM 0x000C 99 1.3.2.2 he #define AN_CMD_NOOP2 0x0010 100 1.3.2.2 he #define AN_CMD_ACCESS 0x0021 101 1.3.2.2 he #define AN_CMD_ALLOC_BUF 0x0028 102 1.3.2.2 he #define AN_CMD_PSP_NODES 0x0030 103 1.3.2.2 he #define AN_CMD_SET_PHYREG 0x003E 104 1.3.2.2 he #define AN_CMD_TX_TEST 0x003F 105 1.3.2.2 he #define AN_CMD_SLEEP 0x0085 106 1.3.2.2 he #define AN_CMD_SAVECFG 0x0108 107 1.3.2.2 he 108 1.3.2.2 he /* 109 1.3.2.2 he * Reclaim qualifier bit, applicable to the 110 1.3.2.2 he * TX command. 111 1.3.2.2 he */ 112 1.3.2.2 he #define AN_RECLAIM 0x0100 /* reclaim NIC memory */ 113 1.3.2.2 he 114 1.3.2.2 he /* 115 1.3.2.2 he * ACCESS command qualifier bits. 116 1.3.2.2 he */ 117 1.3.2.2 he #define AN_ACCESS_READ 0x0000 118 1.3.2.2 he #define AN_ACCESS_WRITE 0x0100 119 1.3.2.2 he 120 1.3.2.2 he /* 121 1.3.2.2 he * PROGRAM command qualifier bits. 122 1.3.2.2 he */ 123 1.3.2.2 he #define AN_PROGRAM_DISABLE 0x0000 124 1.3.2.2 he #define AN_PROGRAM_ENABLE_RAM 0x0100 125 1.3.2.2 he #define AN_PROGRAM_ENABLE_NVRAM 0x0200 126 1.3.2.2 he #define AN_PROGRAM_NVRAM 0x0300 127 1.3.2.2 he 128 1.3.2.2 he /* Status register values */ 129 1.3.2.2 he #define AN_STAT_CMD_CODE 0x003F 130 1.3.2.2 he #define AN_STAT_CMD_RESULT 0x7F00 131 1.3.2.2 he 132 1.3.2.2 he /* Linkstat register */ 133 1.3.2.2 he #define AN_LINKSTAT_ASSOCIATED 0x0400 134 1.3.2.2 he #define AN_LINKSTAT_AUTHFAIL 0x0300 135 1.3.2.2 he #define AN_LINKSTAT_ASSOC_FAIL 0x8400 136 1.3.2.2 he #define AN_LINKSTAT_DISASSOC 0x8200 137 1.3.2.2 he #define AN_LINKSTAT_DEAUTH 0x8100 138 1.3.2.2 he #define AN_LINKSTAT_SYNCLOST_TSF 0x8004 139 1.3.2.2 he #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003 140 1.3.2.2 he #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002 141 1.3.2.2 he #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001 142 1.3.2.2 he #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000 143 1.3.2.2 he 144 1.3.2.2 he /* memory handle management registers */ 145 1.3.2.2 he #define AN_RX_FID 0x20 146 1.3.2.2 he #define AN_ALLOC_FID 0x22 147 1.3.2.2 he #define AN_TX_CMP_FID 0x24 148 1.3.2.2 he 149 1.3.2.2 he /* 150 1.3.2.2 he * Buffer Access Path (BAP) registers. 151 1.3.2.2 he * These are I/O channels. I believe you can use each one for 152 1.3.2.2 he * any desired purpose independently of the other. In general 153 1.3.2.2 he * though, we use BAP1 for reading and writing LTV records and 154 1.3.2.2 he * reading received data frames, and BAP0 for writing transmit 155 1.3.2.2 he * frames. This is a convention though, not a rule. 156 1.3.2.2 he */ 157 1.3.2.2 he #define AN_SEL0 0x18 158 1.3.2.2 he #define AN_SEL1 0x1A 159 1.3.2.2 he #define AN_OFF0 0x1C 160 1.3.2.2 he #define AN_OFF1 0x1E 161 1.3.2.2 he #define AN_DATA0 0x36 162 1.3.2.2 he #define AN_DATA1 0x38 163 1.3.2.2 he #define AN_BAP0 AN_DATA0 164 1.3.2.2 he #define AN_BAP1 AN_DATA1 165 1.3.2.2 he 166 1.3.2.2 he #define AN_OFF_BUSY 0x8000 167 1.3.2.2 he #define AN_OFF_ERR 0x4000 168 1.3.2.2 he #define AN_OFF_DONE 0x2000 169 1.3.2.2 he #define AN_OFF_DATAOFF 0x0FFF 170 1.3.2.2 he 171 1.3.2.2 he /* Event registers */ 172 1.3.2.2 he #define AN_EVENT_STAT 0x30 /* Event status */ 173 1.3.2.2 he #define AN_INT_EN 0x32 /* Interrupt enable/disable */ 174 1.3.2.2 he #define AN_EVENT_ACK 0x34 /* Ack event */ 175 1.3.2.2 he 176 1.3.2.2 he /* Events */ 177 1.3.2.2 he #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */ 178 1.3.2.2 he #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */ 179 1.3.2.2 he #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/ 180 1.3.2.2 he #define AN_EV_LINKSTAT 0x0080 /* link status available */ 181 1.3.2.2 he #define AN_EV_CMD 0x0010 /* command completed */ 182 1.3.2.2 he #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */ 183 1.3.2.2 he #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */ 184 1.3.2.2 he #define AN_EV_TX 0x0002 /* async xmit completed succesfully */ 185 1.3.2.2 he #define AN_EV_RX 0x0001 /* async rx completed */ 186 1.3.2.2 he 187 1.3.2.2 he #define AN_INTRS \ 188 1.3.2.2 he (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT) 189 1.3.2.2 he 190 1.3.2.2 he /* Host software registers */ 191 1.3.2.2 he #define AN_SW0 0x28 192 1.3.2.2 he #define AN_SW1 0x2A 193 1.3.2.2 he #define AN_SW2 0x2C 194 1.3.2.2 he #define AN_SW3 0x2E 195 1.3.2.2 he 196 1.3.2.2 he #define AN_CNTL 0x14 197 1.3.2.2 he 198 1.3.2.2 he #define AN_CNTL_AUX_ENA 0xC000 199 1.3.2.2 he #define AN_CNTL_AUX_ENA_STAT 0xC000 200 1.3.2.2 he #define AN_CNTL_AUX_DIS_STAT 0x0000 201 1.3.2.2 he #define AN_CNTL_AUX_ENA_CNTL 0x8000 202 1.3.2.2 he #define AN_CNTL_AUX_DIS_CNTL 0x4000 203 1.3.2.2 he 204 1.3.2.2 he #define AN_AUX_PAGE 0x3A 205 1.3.2.2 he #define AN_AUX_OFFSET 0x3C 206 1.3.2.2 he #define AN_AUX_DATA 0x3E 207 1.3.2.2 he 208 1.3.2.2 he /* 209 1.3.2.2 he * Length, Type, Value (LTV) record definitions and RID values. 210 1.3.2.2 he */ 211 1.3.2.2 he struct an_ltv_gen { 212 1.3.2.2 he u_int16_t an_len; 213 1.3.2.2 he u_int16_t an_type; 214 1.3.2.2 he u_int16_t an_val; 215 1.3.2.2 he }; 216 1.3.2.2 he 217 1.3.2.2 he /* 218 1.3.2.2 he * General configuration information. 219 1.3.2.2 he */ 220 1.3.2.2 he #define AN_RID_GENCONFIG 0xFF10 221 1.3.2.2 he struct an_ltv_genconfig { 222 1.3.2.2 he /* General configuration. */ 223 1.3.2.2 he u_int16_t an_len; /* 0x00 */ 224 1.3.2.2 he u_int16_t an_type; /* XXXX */ 225 1.3.2.2 he u_int16_t an_opmode; /* 0x02 */ 226 1.3.2.2 he u_int16_t an_rxmode; /* 0x04 */ 227 1.3.2.2 he u_int16_t an_fragthresh; /* 0x06 */ 228 1.3.2.2 he u_int16_t an_rtsthresh; /* 0x08 */ 229 1.3.2.2 he u_int8_t an_macaddr[6]; /* 0x0A */ 230 1.3.2.2 he u_int8_t an_rates[8]; /* 0x10 */ 231 1.3.2.2 he u_int16_t an_shortretry_limit; /* 0x18 */ 232 1.3.2.2 he u_int16_t an_longretry_limit; /* 0x1A */ 233 1.3.2.2 he u_int16_t an_tx_msdu_lifetime; /* 0x1C */ 234 1.3.2.2 he u_int16_t an_rx_msdu_lifetime; /* 0x1E */ 235 1.3.2.2 he u_int16_t an_stationary; /* 0x20 */ 236 1.3.2.2 he u_int16_t an_ordering; /* 0x22 */ 237 1.3.2.2 he u_int16_t an_devtype; /* 0x24 */ 238 1.3.2.2 he u_int16_t an_rsvd0[5]; /* 0x26 */ 239 1.3.2.2 he /* Scanning associating. */ 240 1.3.2.2 he u_int16_t an_scanmode; /* 0x30 */ 241 1.3.2.2 he u_int16_t an_probedelay; /* 0x32 */ 242 1.3.2.2 he u_int16_t an_probe_energy_timeout;/* 0x34 */ 243 1.3.2.2 he u_int16_t an_probe_response_timeout;/*0x36 */ 244 1.3.2.2 he u_int16_t an_beacon_listen_timeout;/*0x38 */ 245 1.3.2.2 he u_int16_t an_ibss_join_net_timeout;/*0x3A */ 246 1.3.2.2 he u_int16_t an_auth_timeout; /* 0x3C */ 247 1.3.2.2 he u_int16_t an_authtype; /* 0x3E */ 248 1.3.2.2 he u_int16_t an_assoc_timeout; /* 0x40 */ 249 1.3.2.2 he u_int16_t an_specified_ap_timeout;/* 0x42 */ 250 1.3.2.2 he u_int16_t an_offline_scan_interval;/*0x44 */ 251 1.3.2.2 he u_int16_t an_offline_scan_duration;/*0x46 */ 252 1.3.2.2 he u_int16_t an_link_loss_delay; /* 0x48 */ 253 1.3.2.2 he u_int16_t an_max_beacon_lost_time;/* 0x4A */ 254 1.3.2.2 he u_int16_t an_refresh_interval; /* 0x4C */ 255 1.3.2.2 he u_int16_t an_rsvd1; /* 0x4E */ 256 1.3.2.2 he /* Power save operation */ 257 1.3.2.2 he u_int16_t an_psave_mode; /* 0x50 */ 258 1.3.2.2 he u_int16_t an_sleep_for_dtims; /* 0x52 */ 259 1.3.2.2 he u_int16_t an_listen_interval; /* 0x54 */ 260 1.3.2.2 he u_int16_t an_fast_listen_interval;/* 0x56 */ 261 1.3.2.2 he u_int16_t an_listen_decay; /* 0x58 */ 262 1.3.2.2 he u_int16_t an_fast_listen_decay; /* 0x5A */ 263 1.3.2.2 he u_int16_t an_rsvd2[2]; /* 0x5C */ 264 1.3.2.2 he /* Ad-hoc (or AP) operation. */ 265 1.3.2.2 he u_int16_t an_beacon_period; /* 0x60 */ 266 1.3.2.2 he u_int16_t an_atim_duration; /* 0x62 */ 267 1.3.2.2 he u_int16_t an_rsvd3; /* 0x64 */ 268 1.3.2.2 he u_int16_t an_ds_channel; /* 0x66 */ 269 1.3.2.2 he u_int16_t an_rsvd4; /* 0x68 */ 270 1.3.2.2 he u_int16_t an_dtim_period; /* 0x6A */ 271 1.3.2.2 he u_int16_t an_rsvd5[2]; /* 0x6C */ 272 1.3.2.2 he /* Radio operation. */ 273 1.3.2.2 he u_int16_t an_radiotype; /* 0x70 */ 274 1.3.2.2 he u_int16_t an_diversity; /* 0x72 */ 275 1.3.2.2 he u_int16_t an_tx_power; /* 0x74 */ 276 1.3.2.2 he u_int16_t an_rss_thresh; /* 0x76 */ 277 1.3.2.2 he u_int16_t an_modulation_type; /* 0x78 */ 278 1.3.2.2 he u_int16_t an_short_preamble; /* 0x7A */ 279 1.3.2.2 he u_int16_t an_home_product; /* 0x7C */ 280 1.3.2.2 he u_int16_t an_rsvd6; /* 0x7E */ 281 1.3.2.2 he /* Aironet extensions. */ 282 1.3.2.2 he u_int8_t an_nodename[16]; /* 0x80 */ 283 1.3.2.2 he u_int16_t an_arl_thresh; /* 0x90 */ 284 1.3.2.2 he u_int16_t an_arl_decay; /* 0x92 */ 285 1.3.2.2 he u_int16_t an_arl_delay; /* 0x94 */ 286 1.3.2.2 he u_int8_t an_rsvd7; /* 0x96 */ 287 1.3.2.2 he u_int8_t an_rsvd8; /* 0x97 */ 288 1.3.2.2 he u_int8_t an_magic_packet_action; /* 0x98 */ 289 1.3.2.2 he u_int8_t an_magic_packet_ctl; /* 0x99 */ 290 1.3.2.2 he u_int16_t an_rsvd9; 291 1.3.2.2 he }; 292 1.3.2.2 he 293 1.3.2.2 he #define AN_OPMODE_IBSS_ADHOC 0x0000 294 1.3.2.2 he #define AN_OPMODE_INFRASTRUCTURE_STATION 0x0001 295 1.3.2.2 he #define AN_OPMODE_AP 0x0002 296 1.3.2.2 he #define AN_OPMODE_AP_REPEATER 0x0003 297 1.3.2.2 he #define AN_OPMODE_UNMODIFIED_PAYLOAD 0x0100 298 1.3.2.2 he #define AN_OPMODE_AIRONET_EXTENSIONS 0x0200 299 1.3.2.2 he #define AN_OPMODE_AP_EXTENSIONS 0x0400 300 1.3.2.2 he 301 1.3.2.2 he #define AN_RXMODE_BC_MC_ADDR 0x0000 302 1.3.2.2 he #define AN_RXMODE_BC_ADDR 0x0001 303 1.3.2.2 he #define AN_RXMODE_ADDR 0x0002 304 1.3.2.2 he #define AN_RXMODE_80211_MONITOR_CURBSS 0x0003 305 1.3.2.2 he #define AN_RXMODE_80211_MONITOR_ANYBSS 0x0004 306 1.3.2.2 he #define AN_RXMODE_LAN_MONITOR_CURBSS 0x0005 307 1.3.2.2 he #define AN_RXMODE_NO_8023_HEADER 0x0100 308 1.3.2.2 he 309 1.3.2.2 he #define AN_RATE_1MBPS 0x0002 310 1.3.2.2 he #define AN_RATE_2MBPS 0x0004 311 1.3.2.2 he #define AN_RATE_5_5MBPS 0x000B 312 1.3.2.2 he #define AN_RATE_11MBPS 0x0016 313 1.3.2.2 he 314 1.3.2.2 he #define AN_DEVTYPE_PC4500 0x0065 315 1.3.2.2 he #define AN_DEVTYPE_PC4800 0x006D 316 1.3.2.2 he 317 1.3.2.2 he #define AN_SCANMODE_ACTIVE 0x0000 318 1.3.2.2 he #define AN_SCANMODE_PASSIVE 0x0001 319 1.3.2.2 he #define AN_SCANMODE_AIRONET_ACTIVE 0x0002 320 1.3.2.2 he 321 1.3.2.2 he #define AN_AUTHTYPE_NONE 0x0000 322 1.3.2.2 he #define AN_AUTHTYPE_OPEN 0x0001 323 1.3.2.2 he #define AN_AUTHTYPE_SHAREDKEY 0x0002 324 1.3.2.2 he #define AN_AUTHTYPE_EXCLUDE_UNENCRYPTED 0x0004 325 1.3.2.2 he 326 1.3.2.2 he #define AN_PSAVE_NONE 0x0000 327 1.3.2.2 he #define AN_PSAVE_CAM 0x0001 328 1.3.2.2 he #define AN_PSAVE_PSP 0x0002 329 1.3.2.2 he #define AN_PSAVE_PSP_CAM 0x0003 330 1.3.2.2 he 331 1.3.2.2 he #define AN_RADIOTYPE_80211_FH 0x0001 332 1.3.2.2 he #define AN_RADIOTYPE_80211_DS 0x0002 333 1.3.2.2 he #define AN_RADIOTYPE_LM2000_DS 0x0004 334 1.3.2.2 he 335 1.3.2.2 he #define AN_DIVERSITY_FACTORY_DEFAULT 0x0000 336 1.3.2.2 he #define AN_DIVERSITY_ANTENNA_1_ONLY 0x0001 337 1.3.2.2 he #define AN_DIVERSITY_ANTENNA_2_ONLY 0x0002 338 1.3.2.2 he #define AN_DIVERSITY_ANTENNA_1_AND_2 0x0003 339 1.3.2.2 he 340 1.3.2.2 he #define AN_TXPOWER_FACTORY_DEFAULT 0x0000 341 1.3.2.2 he #define AN_TXPOWER_50MW 50 342 1.3.2.2 he #define AN_TXPOWER_100MW 100 343 1.3.2.2 he #define AN_TXPOWER_250MW 250 344 1.3.2.2 he 345 1.3.2.2 he /* 346 1.3.2.2 he * Valid SSID list. You can specify up to three SSIDs denoting 347 1.3.2.2 he * the service sets that you want to join. The first SSID always 348 1.3.2.2 he * defaults to "tsunami" which is a handy way to detect the 349 1.3.2.2 he * card. 350 1.3.2.2 he */ 351 1.3.2.2 he #define AN_RID_SSIDLIST 0xFF11 352 1.3.2.2 he struct an_ltv_ssidlist { 353 1.3.2.2 he u_int16_t an_len; 354 1.3.2.2 he u_int16_t an_type; 355 1.3.2.2 he u_int16_t an_ssid1_len; 356 1.3.2.2 he char an_ssid1[32]; 357 1.3.2.2 he u_int16_t an_ssid2_len; 358 1.3.2.2 he char an_ssid2[32]; 359 1.3.2.2 he u_int16_t an_ssid3_len; 360 1.3.2.2 he char an_ssid3[32]; 361 1.3.2.2 he }; 362 1.3.2.2 he 363 1.3.2.2 he #define AN_DEF_SSID_LEN 7 364 1.3.2.2 he #define AN_DEF_SSID "tsunami" 365 1.3.2.2 he 366 1.3.2.2 he /* 367 1.3.2.2 he * Valid AP list. 368 1.3.2.2 he */ 369 1.3.2.2 he #define AN_RID_APLIST 0xFF12 370 1.3.2.2 he struct an_ltv_aplist { 371 1.3.2.2 he u_int16_t an_len; 372 1.3.2.2 he u_int16_t an_type; 373 1.3.2.2 he u_int8_t an_ap1[8]; 374 1.3.2.2 he u_int8_t an_ap2[8]; 375 1.3.2.2 he u_int8_t an_ap3[8]; 376 1.3.2.2 he u_int8_t an_ap4[8]; 377 1.3.2.2 he }; 378 1.3.2.2 he 379 1.3.2.2 he /* 380 1.3.2.2 he * Driver name. 381 1.3.2.2 he */ 382 1.3.2.2 he #define AN_RID_DRVNAME 0xFF13 383 1.3.2.2 he struct an_ltv_drvname { 384 1.3.2.2 he u_int16_t an_len; 385 1.3.2.2 he u_int16_t an_type; 386 1.3.2.2 he u_int8_t an_drvname[16]; 387 1.3.2.2 he }; 388 1.3.2.2 he 389 1.3.2.2 he /* 390 1.3.2.2 he * Frame encapsulation. 391 1.3.2.2 he */ 392 1.3.2.2 he #define AN_RID_ENCAP 0xFF14 393 1.3.2.2 he struct an_rid_encap { 394 1.3.2.2 he u_int16_t an_len; 395 1.3.2.2 he u_int16_t an_type; 396 1.3.2.2 he u_int16_t an_ethertype_default; 397 1.3.2.2 he u_int16_t an_action_default; 398 1.3.2.2 he u_int16_t an_ethertype0; 399 1.3.2.2 he u_int16_t an_action0; 400 1.3.2.2 he u_int16_t an_ethertype1; 401 1.3.2.2 he u_int16_t an_action1; 402 1.3.2.2 he u_int16_t an_ethertype2; 403 1.3.2.2 he u_int16_t an_action2; 404 1.3.2.2 he u_int16_t an_ethertype3; 405 1.3.2.2 he u_int16_t an_action3; 406 1.3.2.2 he u_int16_t an_ethertype4; 407 1.3.2.2 he u_int16_t an_action4; 408 1.3.2.2 he u_int16_t an_ethertype5; 409 1.3.2.2 he u_int16_t an_action5; 410 1.3.2.2 he u_int16_t an_ethertype6; 411 1.3.2.2 he u_int16_t an_action6; 412 1.3.2.2 he }; 413 1.3.2.2 he 414 1.3.2.2 he #define AN_ENCAP_ACTION_RX 0x0001 415 1.3.2.2 he #define AN_ENCAP_ACTION_TX 0x0002 416 1.3.2.2 he 417 1.3.2.2 he #define AN_RXENCAP_NONE 0x0000 418 1.3.2.2 he #define AN_RXENCAP_RFC1024 0x0001 419 1.3.2.2 he 420 1.3.2.2 he #define AN_TXENCAP_RFC1024 0x0000 421 1.3.2.2 he #define AN_TXENCAP_80211 0x0002 422 1.3.2.2 he 423 1.3.2.2 he #define AN_RID_WEP_TEMP 0xFF15 424 1.3.2.2 he #define AN_RID_WEP_PERM 0xFF16 425 1.3.2.2 he 426 1.3.2.2 he /* 427 1.3.2.2 he * Actual config, same structure as general config (read only). 428 1.3.2.2 he */ 429 1.3.2.2 he #define AN_RID_ACTUALCFG 0xFF20 430 1.3.2.2 he 431 1.3.2.2 he /* 432 1.3.2.2 he * Card capabilities (read only). 433 1.3.2.2 he */ 434 1.3.2.2 he #define AN_RID_CAPABILITIES 0xFF00 435 1.3.2.2 he struct an_ltv_caps { 436 1.3.2.2 he u_int16_t an_len; /* 0x00 */ 437 1.3.2.2 he u_int16_t an_type; /* XXXX */ 438 1.3.2.2 he u_int8_t an_oui[3]; /* 0x02 */ 439 1.3.2.2 he u_int8_t an_rsvd0; /* 0x05 */ 440 1.3.2.2 he u_int16_t an_prodnum; /* 0x06 */ 441 1.3.2.2 he u_int8_t an_manufname[32]; /* 0x08 */ 442 1.3.2.2 he u_int8_t an_prodname[16]; /* 0x28 */ 443 1.3.2.2 he u_int8_t an_prodvers[8]; /* 0x38 */ 444 1.3.2.2 he u_int8_t an_oemaddr[6]; /* 0x40 */ 445 1.3.2.2 he u_int8_t an_aironetaddr[6]; /* 0x46 */ 446 1.3.2.2 he u_int16_t an_radiotype; /* 0x4C */ 447 1.3.2.2 he u_int16_t an_regdomain; /* 0x4E */ 448 1.3.2.2 he u_int8_t an_callid[6]; /* 0x50 */ 449 1.3.2.2 he u_int8_t an_rates[8]; /* 0x56 */ 450 1.3.2.2 he u_int8_t an_rx_diversity; /* 0x5E */ 451 1.3.2.2 he u_int8_t an_tx_diversity; /* 0x5F */ 452 1.3.2.2 he u_int16_t an_tx_powerlevels[8]; /* 0x60 */ 453 1.3.2.2 he u_int16_t an_hwrev; /* 0x70 */ 454 1.3.2.2 he u_int16_t an_hwcaps; /* 0x72 */ 455 1.3.2.2 he u_int16_t an_temprange; /* 0x74 */ 456 1.3.2.2 he u_int16_t an_fwrev; /* 0x76 */ 457 1.3.2.2 he u_int16_t an_fwsubrev; /* 0x78 */ 458 1.3.2.2 he u_int16_t an_ifacerev; /* 0x7A */ 459 1.3.2.2 he u_int16_t an_softcaps; /* 0x7C */ 460 1.3.2.2 he u_int16_t an_bootblockrev; /* 0x7E */ 461 1.3.2.2 he u_int16_t an_req_hw_support; /* 0x80 */ 462 1.3.2.2 he }; 463 1.3.2.2 he 464 1.3.2.2 he /* 465 1.3.2.2 he * Access point (read only) 466 1.3.2.2 he */ 467 1.3.2.2 he #define AN_RID_APINFO 0xFF01 468 1.3.2.2 he struct an_ltv_apinfo { 469 1.3.2.2 he u_int16_t an_len; 470 1.3.2.2 he u_int16_t an_type; 471 1.3.2.2 he u_int16_t an_tim_addr; 472 1.3.2.2 he u_int16_t an_airo_addr; 473 1.3.2.2 he }; 474 1.3.2.2 he 475 1.3.2.2 he /* 476 1.3.2.2 he * Radio info (read only). 477 1.3.2.2 he */ 478 1.3.2.2 he #define AN_RID_RADIOINFO 0xFF02 479 1.3.2.2 he struct an_ltv_radioinfo { 480 1.3.2.2 he u_int16_t an_len; 481 1.3.2.2 he u_int16_t an_type; 482 1.3.2.2 he /* ??? */ 483 1.3.2.2 he }; 484 1.3.2.2 he 485 1.3.2.2 he /* 486 1.3.2.2 he * Status (read only). Note: the manual claims this RID is 108 bytes 487 1.3.2.2 he * long (0x6A is the last datum, which is 2 bytes long) however when 488 1.3.2.3 he * this RID is read from the NIC, it returns a length of 110 or 112. 489 1.3.2.3 he * To be on the safe side, this structure is padded with 4 extra 16-bit 490 1.3.2.3 he * words. (There is a misprint in the manual which says the macaddr 491 1.3.2.2 he * field is 8 bytes long.) 492 1.3.2.2 he * 493 1.3.2.2 he * Also, the channel_set and current_channel fields appear to be 494 1.3.2.2 he * reversed. Either that, or the hop_period field is unused. 495 1.3.2.2 he */ 496 1.3.2.2 he #define AN_RID_STATUS 0xFF50 497 1.3.2.2 he struct an_ltv_status { 498 1.3.2.2 he u_int16_t an_len; /* 0x00 */ 499 1.3.2.2 he u_int16_t an_type; /* 0xXX */ 500 1.3.2.2 he u_int8_t an_macaddr[6]; /* 0x02 */ 501 1.3.2.2 he u_int16_t an_opmode; /* 0x08 */ 502 1.3.2.2 he u_int16_t an_errcode; /* 0x0A */ 503 1.3.2.2 he u_int16_t an_cur_signal_strength; /* 0x0C */ 504 1.3.2.2 he u_int16_t an_ssidlen; /* 0x0E */ 505 1.3.2.2 he u_int8_t an_ssid[32]; /* 0x10 */ 506 1.3.2.2 he u_int8_t an_ap_name[16]; /* 0x30 */ 507 1.3.2.2 he u_int8_t an_cur_bssid[6]; /* 0x40 */ 508 1.3.2.2 he u_int8_t an_prev_bssid1[6]; /* 0x46 */ 509 1.3.2.2 he u_int8_t an_prev_bssid2[6]; /* 0x4C */ 510 1.3.2.2 he u_int8_t an_prev_bssid3[6]; /* 0x52 */ 511 1.3.2.2 he u_int16_t an_beacon_period; /* 0x58 */ 512 1.3.2.2 he u_int16_t an_dtim_period; /* 0x5A */ 513 1.3.2.2 he u_int16_t an_atim_duration; /* 0x5C */ 514 1.3.2.2 he u_int16_t an_hop_period; /* 0x5E */ 515 1.3.2.2 he u_int16_t an_cur_channel; /* 0x62 */ 516 1.3.2.2 he u_int16_t an_channel_set; /* 0x60 */ 517 1.3.2.2 he u_int16_t an_hops_to_backbone; /* 0x64 */ 518 1.3.2.2 he u_int16_t an_ap_total_load; /* 0x66 */ 519 1.3.2.2 he u_int16_t an_our_generated_load; /* 0x68 */ 520 1.3.2.2 he u_int16_t an_accumulated_arl; /* 0x6A */ 521 1.3.2.2 he u_int16_t an_cur_signal_quality; /* 0x6C */ 522 1.3.2.2 he u_int16_t an_current_tx_rate; /* 0x6E */ 523 1.3.2.2 he u_int16_t an_ap_device; /* 0x70 */ 524 1.3.2.2 he u_int16_t an_normalized_rssi; /* 0x72 */ 525 1.3.2.2 he u_int16_t an_short_pre_in_use; /* 0x74 */ 526 1.3.2.2 he u_int8_t an_ap_ip_addr[4]; /* 0x76 */ 527 1.3.2.2 he u_int16_t an_max_noise_prev_sec; /* 0x7A */ 528 1.3.2.2 he u_int16_t an_avg_noise_prev_min; /* 0x7C */ 529 1.3.2.2 he u_int16_t an_max_noise_prev_min; /* 0x7E */ 530 1.3.2.3 he u_int16_t an_spare[4]; 531 1.3.2.2 he }; 532 1.3.2.2 he 533 1.3.2.2 he #define AN_STATUS_OPMODE_CONFIGURED 0x0001 534 1.3.2.2 he #define AN_STATUS_OPMODE_MAC_ENABLED 0x0002 535 1.3.2.2 he #define AN_STATUS_OPMODE_RX_ENABLED 0x0004 536 1.3.2.2 he #define AN_STATUS_OPMODE_IN_SYNC 0x0010 537 1.3.2.2 he #define AN_STATUS_OPMODE_ASSOCIATED 0x0020 538 1.3.2.2 he #define AN_STATUS_OPMODE_ERROR 0x8000 539 1.3.2.2 he 540 1.3.2.2 he 541 1.3.2.2 he /* 542 1.3.2.2 he * Statistics 543 1.3.2.2 he */ 544 1.3.2.2 he #define AN_RID_16BITS_CUM 0xFF60 /* Cumulative 16-bit stats counters */ 545 1.3.2.2 he #define AN_RID_16BITS_DELTA 0xFF61 /* 16-bit stats (since last clear) */ 546 1.3.2.2 he #define AN_RID_16BITS_DELTACLR 0xFF62 /* 16-bit stats, clear on read */ 547 1.3.2.2 he #define AN_RID_32BITS_CUM 0xFF68 /* Cumulative 32-bit stats counters */ 548 1.3.2.2 he #define AN_RID_32BITS_DELTA 0xFF69 /* 32-bit stats (since last clear) */ 549 1.3.2.2 he #define AN_RID_32BITS_DELTACLR 0xFF6A /* 32-bit stats, clear on read */ 550 1.3.2.2 he 551 1.3.2.2 he /* 552 1.3.2.2 he * Grrr. The manual says the statistics record is 384 bytes in length, 553 1.3.2.2 he * but the card says the record is 404 bytes. There's some padding left 554 1.3.2.2 he * at the end of this structure to account for any discrepancies. 555 1.3.2.2 he */ 556 1.3.2.2 he struct an_ltv_stats { 557 1.3.2.2 he u_int16_t an_fudge; 558 1.3.2.2 he u_int16_t an_len; /* 0x00 */ 559 1.3.2.2 he u_int16_t an_type; /* 0xXX */ 560 1.3.2.2 he u_int16_t an_spacer; /* 0x02 */ 561 1.3.2.2 he u_int32_t an_rx_overruns; /* 0x04 */ 562 1.3.2.2 he u_int32_t an_rx_plcp_csum_errs; /* 0x08 */ 563 1.3.2.2 he u_int32_t an_rx_plcp_format_errs; /* 0x0C */ 564 1.3.2.2 he u_int32_t an_rx_plcp_len_errs; /* 0x10 */ 565 1.3.2.2 he u_int32_t an_rx_mac_crc_errs; /* 0x14 */ 566 1.3.2.2 he u_int32_t an_rx_mac_crc_ok; /* 0x18 */ 567 1.3.2.2 he u_int32_t an_rx_wep_errs; /* 0x1C */ 568 1.3.2.2 he u_int32_t an_rx_wep_ok; /* 0x20 */ 569 1.3.2.2 he u_int32_t an_retry_long; /* 0x24 */ 570 1.3.2.2 he u_int32_t an_retry_short; /* 0x28 */ 571 1.3.2.2 he u_int32_t an_retry_max; /* 0x2C */ 572 1.3.2.2 he u_int32_t an_no_ack; /* 0x30 */ 573 1.3.2.2 he u_int32_t an_no_cts; /* 0x34 */ 574 1.3.2.2 he u_int32_t an_rx_ack_ok; /* 0x38 */ 575 1.3.2.2 he u_int32_t an_rx_cts_ok; /* 0x3C */ 576 1.3.2.2 he u_int32_t an_tx_ack_ok; /* 0x40 */ 577 1.3.2.2 he u_int32_t an_tx_rts_ok; /* 0x44 */ 578 1.3.2.2 he u_int32_t an_tx_cts_ok; /* 0x48 */ 579 1.3.2.2 he u_int32_t an_tx_lmac_mcasts; /* 0x4C */ 580 1.3.2.2 he u_int32_t an_tx_lmac_bcasts; /* 0x50 */ 581 1.3.2.2 he u_int32_t an_tx_lmac_ucast_frags; /* 0x54 */ 582 1.3.2.2 he u_int32_t an_tx_lmac_ucasts; /* 0x58 */ 583 1.3.2.2 he u_int32_t an_tx_beacons; /* 0x5C */ 584 1.3.2.2 he u_int32_t an_rx_beacons; /* 0x60 */ 585 1.3.2.2 he u_int32_t an_tx_single_cols; /* 0x64 */ 586 1.3.2.2 he u_int32_t an_tx_multi_cols; /* 0x68 */ 587 1.3.2.2 he u_int32_t an_tx_defers_no; /* 0x6C */ 588 1.3.2.2 he u_int32_t an_tx_defers_prot; /* 0x70 */ 589 1.3.2.2 he u_int32_t an_tx_defers_energy; /* 0x74 */ 590 1.3.2.2 he u_int32_t an_rx_dups; /* 0x78 */ 591 1.3.2.2 he u_int32_t an_rx_partial; /* 0x7C */ 592 1.3.2.2 he u_int32_t an_tx_too_old; /* 0x80 */ 593 1.3.2.2 he u_int32_t an_rx_too_old; /* 0x84 */ 594 1.3.2.2 he u_int32_t an_lostsync_max_retries;/* 0x88 */ 595 1.3.2.2 he u_int32_t an_lostsync_missed_beacons;/* 0x8C */ 596 1.3.2.2 he u_int32_t an_lostsync_arl_exceeded;/*0x90 */ 597 1.3.2.2 he u_int32_t an_lostsync_deauthed; /* 0x94 */ 598 1.3.2.2 he u_int32_t an_lostsync_disassociated;/*0x98 */ 599 1.3.2.2 he u_int32_t an_lostsync_tsf_timing; /* 0x9C */ 600 1.3.2.2 he u_int32_t an_tx_host_mcasts; /* 0xA0 */ 601 1.3.2.2 he u_int32_t an_tx_host_bcasts; /* 0xA4 */ 602 1.3.2.2 he u_int32_t an_tx_host_ucasts; /* 0xA8 */ 603 1.3.2.2 he u_int32_t an_tx_host_failed; /* 0xAC */ 604 1.3.2.2 he u_int32_t an_rx_host_mcasts; /* 0xB0 */ 605 1.3.2.2 he u_int32_t an_rx_host_bcasts; /* 0xB4 */ 606 1.3.2.2 he u_int32_t an_rx_host_ucasts; /* 0xB8 */ 607 1.3.2.2 he u_int32_t an_rx_host_discarded; /* 0xBC */ 608 1.3.2.2 he u_int32_t an_tx_hmac_mcasts; /* 0xC0 */ 609 1.3.2.2 he u_int32_t an_tx_hmac_bcasts; /* 0xC4 */ 610 1.3.2.2 he u_int32_t an_tx_hmac_ucasts; /* 0xC8 */ 611 1.3.2.2 he u_int32_t an_tx_hmac_failed; /* 0xCC */ 612 1.3.2.2 he u_int32_t an_rx_hmac_mcasts; /* 0xD0 */ 613 1.3.2.2 he u_int32_t an_rx_hmac_bcasts; /* 0xD4 */ 614 1.3.2.2 he u_int32_t an_rx_hmac_ucasts; /* 0xD8 */ 615 1.3.2.2 he u_int32_t an_rx_hmac_discarded; /* 0xDC */ 616 1.3.2.2 he u_int32_t an_tx_hmac_accepted; /* 0xE0 */ 617 1.3.2.2 he u_int32_t an_ssid_mismatches; /* 0xE4 */ 618 1.3.2.2 he u_int32_t an_ap_mismatches; /* 0xE8 */ 619 1.3.2.2 he u_int32_t an_rates_mismatches; /* 0xEC */ 620 1.3.2.2 he u_int32_t an_auth_rejects; /* 0xF0 */ 621 1.3.2.2 he u_int32_t an_auth_timeouts; /* 0xF4 */ 622 1.3.2.2 he u_int32_t an_assoc_rejects; /* 0xF8 */ 623 1.3.2.2 he u_int32_t an_assoc_timeouts; /* 0xFC */ 624 1.3.2.2 he u_int32_t an_reason_outside_table;/* 0x100 */ 625 1.3.2.2 he u_int32_t an_reason1; /* 0x104 */ 626 1.3.2.2 he u_int32_t an_reason2; /* 0x108 */ 627 1.3.2.2 he u_int32_t an_reason3; /* 0x10C */ 628 1.3.2.2 he u_int32_t an_reason4; /* 0x110 */ 629 1.3.2.2 he u_int32_t an_reason5; /* 0x114 */ 630 1.3.2.2 he u_int32_t an_reason6; /* 0x118 */ 631 1.3.2.2 he u_int32_t an_reason7; /* 0x11C */ 632 1.3.2.2 he u_int32_t an_reason8; /* 0x120 */ 633 1.3.2.2 he u_int32_t an_reason9; /* 0x124 */ 634 1.3.2.2 he u_int32_t an_reason10; /* 0x128 */ 635 1.3.2.2 he u_int32_t an_reason11; /* 0x12C */ 636 1.3.2.2 he u_int32_t an_reason12; /* 0x130 */ 637 1.3.2.2 he u_int32_t an_reason13; /* 0x134 */ 638 1.3.2.2 he u_int32_t an_reason14; /* 0x138 */ 639 1.3.2.2 he u_int32_t an_reason15; /* 0x13C */ 640 1.3.2.2 he u_int32_t an_reason16; /* 0x140 */ 641 1.3.2.2 he u_int32_t an_reason17; /* 0x144 */ 642 1.3.2.2 he u_int32_t an_reason18; /* 0x148 */ 643 1.3.2.2 he u_int32_t an_reason19; /* 0x14C */ 644 1.3.2.2 he u_int32_t an_rx_mgmt_pkts; /* 0x150 */ 645 1.3.2.2 he u_int32_t an_tx_mgmt_pkts; /* 0x154 */ 646 1.3.2.2 he u_int32_t an_rx_refresh_pkts; /* 0x158 */ 647 1.3.2.2 he u_int32_t an_tx_refresh_pkts; /* 0x15C */ 648 1.3.2.2 he u_int32_t an_rx_poll_pkts; /* 0x160 */ 649 1.3.2.2 he u_int32_t an_tx_poll_pkts; /* 0x164 */ 650 1.3.2.2 he u_int32_t an_host_retries; /* 0x168 */ 651 1.3.2.2 he u_int32_t an_lostsync_hostreq; /* 0x16C */ 652 1.3.2.2 he u_int32_t an_host_tx_bytes; /* 0x170 */ 653 1.3.2.2 he u_int32_t an_host_rx_bytes; /* 0x174 */ 654 1.3.2.2 he u_int32_t an_uptime_usecs; /* 0x178 */ 655 1.3.2.2 he u_int32_t an_uptime_secs; /* 0x17C */ 656 1.3.2.2 he u_int32_t an_lostsync_better_ap; /* 0x180 */ 657 1.3.2.2 he u_int32_t an_rsvd[10]; 658 1.3.2.2 he }; 659 1.3.2.2 he 660 1.3.2.2 he /* 661 1.3.2.2 he * Volatile WEP Key 662 1.3.2.2 he */ 663 1.3.2.2 he #define AN_RID_WEP_VOLATILE 0xFF15 /* Volatile WEP Key */ 664 1.3.2.2 he struct an_ltv_wepkey { 665 1.3.2.2 he u_int16_t an_len; /* 0x00 */ 666 1.3.2.2 he u_int16_t an_type; /* 0xXX */ 667 1.3.2.2 he u_int16_t an_key_index; /* 0x02 */ 668 1.3.2.2 he u_int8_t an_mac_addr[6]; /* 0x04 */ 669 1.3.2.2 he u_int16_t an_key_len; /* 0x0A */ 670 1.3.2.2 he u_int8_t an_key[13]; /* 0x0C */ 671 1.3.2.2 he }; 672 1.3.2.2 he 673 1.3.2.2 he /* 674 1.3.2.2 he * Persistent WEP Key 675 1.3.2.2 he */ 676 1.3.2.2 he #define AN_RID_WEP_PERSISTENT 0xFF16 /* Persistent WEP Key */ 677 1.3.2.2 he 678 1.3.2.2 he 679 1.3.2.2 he /* 680 1.3.2.2 he * Receive frame structure. 681 1.3.2.2 he */ 682 1.3.2.2 he struct an_rxframe { 683 1.3.2.2 he u_int32_t an_rx_time; /* 0x00 */ 684 1.3.2.2 he u_int16_t an_rx_status; /* 0x04 */ 685 1.3.2.2 he u_int16_t an_rx_payload_len; /* 0x06 */ 686 1.3.2.2 he u_int8_t an_rsvd0; /* 0x08 */ 687 1.3.2.2 he u_int8_t an_rx_signal_strength; /* 0x09 */ 688 1.3.2.2 he u_int8_t an_rx_rate; /* 0x0A */ 689 1.3.2.2 he u_int8_t an_rx_chan; /* 0x0B */ 690 1.3.2.2 he u_int8_t an_rx_assoc_cnt; /* 0x0C */ 691 1.3.2.2 he u_int8_t an_rsvd1[3]; /* 0x0D */ 692 1.3.2.2 he u_int8_t an_plcp_hdr[4]; /* 0x10 */ 693 1.3.2.2 he u_int16_t an_frame_ctl; /* 0x14 */ 694 1.3.2.2 he u_int16_t an_duration; /* 0x16 */ 695 1.3.2.2 he u_int8_t an_addr1[6]; /* 0x18 */ 696 1.3.2.2 he u_int8_t an_addr2[6]; /* 0x1E */ 697 1.3.2.2 he u_int8_t an_addr3[6]; /* 0x24 */ 698 1.3.2.2 he u_int16_t an_seq_ctl; /* 0x2A */ 699 1.3.2.2 he u_int8_t an_addr4[6]; /* 0x2C */ 700 1.3.2.2 he u_int16_t an_gaplen; /* 0x32 */ 701 1.3.2.2 he }; 702 1.3.2.2 he 703 1.3.2.2 he #define AN_RXGAP_MAX 8 704 1.3.2.2 he 705 1.3.2.2 he /* 706 1.3.2.2 he * Transmit frame structure. 707 1.3.2.2 he */ 708 1.3.2.2 he struct an_txframe { 709 1.3.2.2 he u_int32_t an_tx_sw; /* 0x00 */ 710 1.3.2.2 he u_int16_t an_tx_status; /* 0x04 */ 711 1.3.2.2 he u_int16_t an_tx_payload_len; /* 0x06 */ 712 1.3.2.2 he u_int16_t an_tx_ctl; /* 0x08 */ 713 1.3.2.2 he u_int16_t an_tx_assoc_id; /* 0x0A */ 714 1.3.2.2 he u_int16_t an_tx_retry; /* 0x0C */ 715 1.3.2.2 he u_int8_t an_tx_assoc_cnt; /* 0x0E */ 716 1.3.2.2 he u_int8_t an_tx_rate; /* 0x0F */ 717 1.3.2.2 he u_int8_t an_tx_max_long_retries; /* 0x10 */ 718 1.3.2.2 he u_int8_t an_tx_max_short_retries; /*0x11 */ 719 1.3.2.2 he u_int8_t an_rsvd0[2]; /* 0x12 */ 720 1.3.2.2 he u_int16_t an_frame_ctl; /* 0x14 */ 721 1.3.2.2 he u_int16_t an_duration; /* 0x16 */ 722 1.3.2.2 he u_int8_t an_addr1[6]; /* 0x18 */ 723 1.3.2.2 he u_int8_t an_addr2[6]; /* 0x1E */ 724 1.3.2.2 he u_int8_t an_addr3[6]; /* 0x24 */ 725 1.3.2.2 he u_int16_t an_seq_ctl; /* 0x2A */ 726 1.3.2.2 he u_int8_t an_addr4[6]; /* 0x2C */ 727 1.3.2.2 he u_int16_t an_gaplen; /* 0x32 */ 728 1.3.2.2 he }; 729 1.3.2.2 he 730 1.3.2.2 he struct an_rxframe_802_3 { 731 1.3.2.2 he u_int16_t an_rx_802_3_status; /* 0x34 */ 732 1.3.2.2 he u_int16_t an_rx_802_3_payload_len;/* 0x36 */ 733 1.3.2.2 he u_int8_t an_rx_dst_addr[6]; /* 0x38 */ 734 1.3.2.2 he u_int8_t an_rx_src_addr[6]; /* 0x3E */ 735 1.3.2.2 he }; 736 1.3.2.2 he #define AN_RXGAP_MAX 8 737 1.3.2.2 he 738 1.3.2.2 he 739 1.3.2.2 he struct an_txframe_802_3 { 740 1.3.2.2 he /* 741 1.3.2.2 he * Transmit 802.3 header structure. 742 1.3.2.2 he */ 743 1.3.2.2 he u_int16_t an_tx_802_3_status; /* 0x34 */ 744 1.3.2.2 he u_int16_t an_tx_802_3_payload_len;/* 0x36 */ 745 1.3.2.2 he u_int8_t an_tx_dst_addr[6]; /* 0x38 */ 746 1.3.2.2 he u_int8_t an_tx_src_addr[6]; /* 0x3E */ 747 1.3.2.2 he }; 748 1.3.2.2 he 749 1.3.2.2 he #define AN_TXSTAT_EXCESS_RETRY 0x0002 750 1.3.2.2 he #define AN_TXSTAT_LIFE_EXCEEDED 0x0004 751 1.3.2.2 he #define AN_TXSTAT_AID_FAIL 0x0008 752 1.3.2.2 he #define AN_TXSTAT_MAC_DISABLED 0x0010 753 1.3.2.2 he #define AN_TXSTAT_ASSOC_LOST 0x0020 754 1.3.2.2 he 755 1.3.2.2 he #define AN_TXCTL_RSVD 0x0001 756 1.3.2.2 he #define AN_TXCTL_TXOK_INTR 0x0002 757 1.3.2.2 he #define AN_TXCTL_TXERR_INTR 0x0004 758 1.3.2.2 he #define AN_TXCTL_HEADER_TYPE 0x0008 759 1.3.2.2 he #define AN_TXCTL_PAYLOAD_TYPE 0x0010 760 1.3.2.2 he #define AN_TXCTL_NORELEASE 0x0020 761 1.3.2.2 he #define AN_TXCTL_NORETRIES 0x0040 762 1.3.2.2 he #define AN_TXCTL_CLEAR_AID 0x0080 763 1.3.2.2 he #define AN_TXCTL_STRICT_ORDER 0x0100 764 1.3.2.2 he #define AN_TXCTL_USE_RTS 0x0200 765 1.3.2.2 he 766 1.3.2.2 he #define AN_HEADERTYPE_8023 0x0000 767 1.3.2.2 he #define AN_HEADERTYPE_80211 0x0008 768 1.3.2.2 he 769 1.3.2.2 he #define AN_PAYLOADTYPE_ETHER 0x0000 770 1.3.2.2 he #define AN_PAYLOADTYPE_LLC 0x0010 771 1.3.2.2 he 772 1.3.2.2 he #define AN_TXCTL_80211 \ 773 1.3.2.2 he (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \ 774 1.3.2.2 he AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE) 775 1.3.2.2 he 776 1.3.2.2 he #define AN_TXCTL_8023 \ 777 1.3.2.2 he (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \ 778 1.3.2.2 he AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE) 779 1.3.2.2 he 780 1.3.2.2 he #define AN_TXGAP_80211 0 781 1.3.2.2 he #define AN_TXGAP_8023 0 782 1.3.2.2 he 783 1.3.2.2 he struct an_802_3_hdr { 784 1.3.2.2 he u_int16_t an_8023_status; 785 1.3.2.2 he u_int16_t an_8023_payload_len; 786 1.3.2.2 he u_int8_t an_8023_dst_addr[6]; 787 1.3.2.2 he u_int8_t an_8023_src_addr[6]; 788 1.3.2.2 he u_int16_t an_8023_dat[3]; /* SNAP header */ 789 1.3.2.2 he u_int16_t an_8023_type; 790 1.3.2.2 he }; 791 1.3.2.2 he 792 1.3.2.2 he struct an_snap_hdr { 793 1.3.2.2 he u_int16_t an_snap_dat[3]; /* SNAP header */ 794 1.3.2.2 he u_int16_t an_snap_type; 795 1.3.2.2 he }; 796 1.3.2.2 he 797 1.3.2.2 he #define AN_TX_RING_CNT 4 798 1.3.2.2 he #define AN_INC(x, y) (x) = (x + 1) % y 799 1.3.2.2 he 800 1.3.2.2 he struct an_tx_ring_data { 801 1.3.2.2 he u_int16_t an_tx_fids[AN_TX_RING_CNT]; 802 1.3.2.2 he u_int16_t an_tx_ring[AN_TX_RING_CNT]; 803 1.3.2.2 he int an_tx_prod; 804 1.3.2.2 he int an_tx_cons; 805 1.3.2.2 he }; 806 1.3.2.2 he 807 1.3.2.2 he struct an_softc { 808 1.3.2.2 he struct device an_dev; 809 1.3.2.2 he struct ethercom arpcom; 810 1.3.2.2 he int (*sc_enable) __P((struct an_softc *)); 811 1.3.2.2 he void (*sc_disable) __P((struct an_softc *)); 812 1.3.2.2 he int sc_enabled; 813 1.3.2.2 he struct ifmedia sc_media; 814 1.3.2.2 he 815 1.3.2.2 he void* irq_handle; /* handle for irq handler */ 816 1.3.2.2 he 817 1.3.2.2 he bus_space_handle_t an_bhandle; 818 1.3.2.2 he bus_space_tag_t an_btag; 819 1.3.2.2 he struct an_ltv_genconfig an_config; 820 1.3.2.2 he struct an_ltv_caps an_caps; 821 1.3.2.2 he struct an_ltv_ssidlist an_ssidlist; 822 1.3.2.2 he struct an_ltv_aplist an_aplist; 823 1.3.2.2 he struct an_ltv_key an_temp_keys; 824 1.3.2.2 he struct an_ltv_key an_perm_keys; 825 1.3.2.2 he int an_tx_rate; 826 1.3.2.2 he int an_rxmode; 827 1.3.2.2 he int an_if_flags; 828 1.3.2.2 he u_int8_t an_txbuf[1536]; 829 1.3.2.2 he struct an_tx_ring_data an_rdata; 830 1.3.2.2 he struct an_ltv_stats an_stats; 831 1.3.2.2 he struct an_ltv_status an_status; 832 1.3.2.2 he u_int8_t an_associated; 833 1.3.2.2 he #ifdef ANCACHE 834 1.3.2.2 he int an_sigitems; 835 1.3.2.2 he struct an_sigcache an_sigcache[MAXANCACHE]; 836 1.3.2.2 he int an_nextitem; 837 1.3.2.2 he #endif 838 1.3.2.2 he struct callout an_stat_ch; 839 1.3.2.2 he }; 840 1.3.2.2 he 841 1.3.2.2 he void an_release_resources __P((struct device *)); 842 1.3.2.2 he int an_alloc_port __P((struct device *, int, int)); 843 1.3.2.2 he int an_alloc_memory __P((struct device *, int, int)); 844 1.3.2.2 he int an_alloc_irq __P((struct device *, int, int)); 845 1.3.2.2 he int an_probe __P((struct an_softc *)); 846 1.3.2.2 he void an_shutdown __P((struct device *)); 847 1.3.2.2 he int an_attach __P((struct an_softc *)); 848 1.3.2.2 he int an_detach __P((struct an_softc *)); 849 1.3.2.2 he int an_intr __P((void *)); 850 1.3.2.2 he int an_activate __P((struct device *, enum devact)); 851 1.3.2.2 he 852 1.3.2.2 he 853 1.3.2.2 he #define AN_802_3_OFFSET 0x2E 854 1.3.2.2 he #define AN_802_11_OFFSET 0x44 855 1.3.2.2 he #define AN_802_11_OFFSET_RAW 0x3C 856 1.3.2.2 he 857 1.3.2.2 he #define AN_STAT_BADCRC 0x0001 858 1.3.2.2 he #define AN_STAT_UNDECRYPTABLE 0x0002 859 1.3.2.2 he #define AN_STAT_ERRSTAT 0x0003 860 1.3.2.2 he #define AN_STAT_MAC_PORT 0x0700 861 1.3.2.2 he #define AN_STAT_1042 0x2000 /* RFC1042 encoded */ 862 1.3.2.2 he #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */ 863 1.3.2.2 he #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */ 864 1.3.2.2 he #define AN_RXSTAT_MSG_TYPE 0xE000 865 1.3.2.2 he 866 1.3.2.2 he #define AN_ENC_TX_802_3 0x00 867 1.3.2.2 he #define AN_ENC_TX_802_11 0x11 868 1.3.2.2 he #define AN_ENC_TX_E_II 0x0E 869 1.3.2.2 he 870 1.3.2.2 he #define AN_ENC_TX_1042 0x00 871 1.3.2.2 he #define AN_ENC_TX_TUNNEL 0xF8 872 1.3.2.2 he 873 1.3.2.2 he #define AN_TXCNTL_MACPORT 0x00FF 874 1.3.2.2 he #define AN_TXCNTL_STRUCTTYPE 0xFF00 875 1.3.2.2 he 876 1.3.2.2 he /* 877 1.3.2.2 he * SNAP (sub-network access protocol) constants for transmission 878 1.3.2.2 he * of IP datagrams over IEEE 802 networks, taken from RFC1042. 879 1.3.2.2 he * We need these for the LLC/SNAP header fields in the TX/RX frame 880 1.3.2.2 he * structure. 881 1.3.2.2 he */ 882 1.3.2.2 he #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */ 883 1.3.2.2 he #define AN_SNAP_K2 0x00 884 1.3.2.2 he #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */ 885 1.3.2.2 he #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8)) 886 1.3.2.2 he #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8)) 887 1.3.2.2 he #define AN_SNAPHDR_LEN 0x6 888 1.3.2.2 he 889 1.3.2.2 he 890
Indexes created Wed Oct 22 13:09:56 GMT 2025