apcdmareg.h revision 1.5.70.1 1 1.5.70.1 mjf /* $NetBSD: apcdmareg.h,v 1.5.70.1 2008/06/02 13:23:18 mjf Exp $ */
2 1.1 mrg
3 1.1 mrg /*-
4 1.1 mrg * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * This code is derived from software contributed to The NetBSD Foundation
8 1.1 mrg * by Paul Kranenburg.
9 1.1 mrg *
10 1.1 mrg * Redistribution and use in source and binary forms, with or without
11 1.1 mrg * modification, are permitted provided that the following conditions
12 1.1 mrg * are met:
13 1.1 mrg * 1. Redistributions of source code must retain the above copyright
14 1.1 mrg * notice, this list of conditions and the following disclaimer.
15 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mrg * notice, this list of conditions and the following disclaimer in the
17 1.1 mrg * documentation and/or other materials provided with the distribution.
18 1.1 mrg *
19 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 mrg * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 mrg * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 mrg * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 mrg * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 mrg * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 mrg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 mrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 mrg * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 mrg * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 mrg * POSSIBILITY OF SUCH DAMAGE.
30 1.1 mrg */
31 1.1 mrg
32 1.1 mrg /*
33 1.1 mrg * APC DMA hardware; from SunOS header
34 1.1 mrg * Thanks to Derrick J. Brashear for additional info on the
35 1.1 mrg * meaning of some of these bits.
36 1.1 mrg */
37 1.3 uwe #ifndef _DEV_IC_APCDMAREG_H_
38 1.3 uwe #define _DEV_IC_APCDMAREG_H_
39 1.3 uwe
40 1.1 mrg struct apc_dma {
41 1.1 mrg volatile u_int32_t dmacsr; /* APC CSR */
42 1.1 mrg volatile u_int32_t lpad[3]; /* */
43 1.1 mrg volatile u_int32_t dmacva; /* Capture Virtual Address */
44 1.1 mrg volatile u_int32_t dmacc; /* Capture Count */
45 1.1 mrg volatile u_int32_t dmacnva; /* Capture Next Virtual Address */
46 1.1 mrg volatile u_int32_t dmacnc; /* Capture next count */
47 1.1 mrg volatile u_int32_t dmapva; /* Playback Virtual Address */
48 1.1 mrg volatile u_int32_t dmapc; /* Playback Count */
49 1.1 mrg volatile u_int32_t dmapnva; /* Playback Next VAddress */
50 1.1 mrg volatile u_int32_t dmapnc; /* Playback Next Count */
51 1.1 mrg };
52 1.4 uwe
53 1.4 uwe /* same as above but as offsets for bus_space ops */
54 1.4 uwe #define APC_DMA_CSR 0
55 1.4 uwe #define APC_DMA_CVA 16
56 1.4 uwe #define APC_DMA_CC 20
57 1.4 uwe #define APC_DMA_CNVA 24
58 1.4 uwe #define APC_DMA_CNC 28
59 1.4 uwe #define APC_DMA_PVA 32
60 1.4 uwe #define APC_DMA_PC 36
61 1.4 uwe #define APC_DMA_PNVA 40
62 1.4 uwe #define APC_DMA_PNC 44
63 1.4 uwe
64 1.4 uwe #define APC_DMA_SIZE 48
65 1.1 mrg
66 1.1 mrg /*
67 1.1 mrg * APC CSR Register bit definitions
68 1.1 mrg */
69 1.1 mrg #define APC_IP 0x00800000 /* Interrupt Pending */
70 1.1 mrg #define APC_PI 0x00400000 /* Playback interrupt */
71 1.1 mrg #define APC_CI 0x00200000 /* Capture interrupt */
72 1.1 mrg #define APC_EI 0x00100000 /* General interrupt */
73 1.1 mrg #define APC_IE 0x00080000 /* General ext int. enable */
74 1.1 mrg #define APC_PIE 0x00040000 /* Playback ext intr */
75 1.1 mrg #define APC_CIE 0x00020000 /* Capture ext intr */
76 1.1 mrg #define APC_EIE 0x00010000 /* Error ext intr */
77 1.1 mrg #define APC_PMI 0x00008000 /* Pipe empty interrupt */
78 1.1 mrg #define APC_PM 0x00004000 /* Play pipe empty */
79 1.1 mrg #define APC_PD 0x00002000 /* Playback NVA dirty */
80 1.1 mrg #define APC_PMIE 0x00001000 /* play pipe empty Int enable */
81 1.1 mrg #define APC_CM 0x00000800 /* Cap data dropped on floor */
82 1.1 mrg #define APC_CD 0x00000400 /* Capture NVA dirty */
83 1.1 mrg #define APC_CMI 0x00000200 /* Capture pipe empty interrupt */
84 1.1 mrg #define APC_CMIE 0x00000100 /* Cap. pipe empty int enable */
85 1.1 mrg #define APC_PPAUSE 0x00000080 /* Pause the play DMA */
86 1.1 mrg #define APC_CPAUSE 0x00000040 /* Pause the capture DMA */
87 1.1 mrg #define APC_CODEC_PDN 0x00000020 /* CODEC RESET */
88 1.1 mrg #define PDMA_GO 0x00000008
89 1.1 mrg #define CDMA_GO 0x00000004 /* bit 2 of the csr */
90 1.1 mrg #define APC_RESET 0x00000001 /* Reset the chip */
91 1.1 mrg
92 1.1 mrg #define APC_BITS \
93 1.1 mrg "\20\30IP\27PI\26CI\25EI\24IE" \
94 1.1 mrg "\23PIE\22CIE\21EIE\20PMI\17PM\16PD\15PMIE" \
95 1.1 mrg "\14CM\13CD\12CMI\11CMIE\10PPAUSE\7CPAUSE\6PDN\4PGO\3CGO"
96 1.1 mrg
97 1.1 mrg /*
98 1.3 uwe * Note that when we program CSR, we should be careful to not
99 1.3 uwe * accidentally clear any pending interrupt bits (a pending interrupt
100 1.3 uwe * reads as 1 and writing back 1 will clear), so instead of
101 1.3 uwe *
102 1.3 uwe * dma->dmacsr |= bits;
103 1.3 uwe *
104 1.3 uwe * we should do
105 1.3 uwe *
106 1.3 uwe * temp = dma->dmacsr & ~APC_INTR_MASK;
107 1.3 uwe * temp |= bits;
108 1.3 uwe * dma->dmacsr = temp;
109 1.3 uwe *
110 1.3 uwe * When clearing bits, always add APC_INTR_MASK, i.e.
111 1.3 uwe *
112 1.3 uwe * dma->dmacsr &= ~(bits | APC_INTR_MASK);
113 1.1 mrg */
114 1.3 uwe #define APC_INTR_MASK (APC_IP|APC_PI|APC_CI|APC_EI|APC_PMI|APC_CMI)
115 1.1 mrg
116 1.3 uwe #endif /* _DEV_IC_APCDMAREG_H_ */
117