arn9280.c revision 1.2.4.2
1 1.2.4.2 tls /* $NetBSD: arn9280.c,v 1.2.4.2 2013/06/23 06:20:17 tls Exp $ */ 2 1.2.4.2 tls /* $OpenBSD: ar9280.c,v 1.18 2012/06/10 21:23:36 kettenis Exp $ */ 3 1.2.4.2 tls 4 1.2.4.2 tls /*- 5 1.2.4.2 tls * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.2.4.2 tls * Copyright (c) 2008-2009 Atheros Communications Inc. 7 1.2.4.2 tls * 8 1.2.4.2 tls * Permission to use, copy, modify, and/or distribute this software for any 9 1.2.4.2 tls * purpose with or without fee is hereby granted, provided that the above 10 1.2.4.2 tls * copyright notice and this permission notice appear in all copies. 11 1.2.4.2 tls * 12 1.2.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.2.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.2.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.2.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.2.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.2.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.2.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.2.4.2 tls */ 20 1.2.4.2 tls 21 1.2.4.2 tls /* 22 1.2.4.2 tls * Driver for Atheros 802.11a/g/n chipsets. 23 1.2.4.2 tls * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets. 24 1.2.4.2 tls */ 25 1.2.4.2 tls 26 1.2.4.2 tls #include <sys/cdefs.h> 27 1.2.4.2 tls __KERNEL_RCSID(0, "$NetBSD: arn9280.c,v 1.2.4.2 2013/06/23 06:20:17 tls Exp $"); 28 1.2.4.2 tls 29 1.2.4.2 tls #include <sys/param.h> 30 1.2.4.2 tls #include <sys/sockio.h> 31 1.2.4.2 tls #include <sys/mbuf.h> 32 1.2.4.2 tls #include <sys/kernel.h> 33 1.2.4.2 tls #include <sys/socket.h> 34 1.2.4.2 tls #include <sys/systm.h> 35 1.2.4.2 tls #include <sys/malloc.h> 36 1.2.4.2 tls #include <sys/queue.h> 37 1.2.4.2 tls #include <sys/callout.h> 38 1.2.4.2 tls #include <sys/conf.h> 39 1.2.4.2 tls #include <sys/device.h> 40 1.2.4.2 tls 41 1.2.4.2 tls #include <sys/bus.h> 42 1.2.4.2 tls #include <sys/endian.h> 43 1.2.4.2 tls #include <sys/intr.h> 44 1.2.4.2 tls 45 1.2.4.2 tls #include <net/bpf.h> 46 1.2.4.2 tls #include <net/if.h> 47 1.2.4.2 tls #include <net/if_arp.h> 48 1.2.4.2 tls #include <net/if_dl.h> 49 1.2.4.2 tls #include <net/if_ether.h> 50 1.2.4.2 tls #include <net/if_media.h> 51 1.2.4.2 tls #include <net/if_types.h> 52 1.2.4.2 tls 53 1.2.4.2 tls #include <netinet/in.h> 54 1.2.4.2 tls #include <netinet/in_systm.h> 55 1.2.4.2 tls #include <netinet/in_var.h> 56 1.2.4.2 tls #include <netinet/ip.h> 57 1.2.4.2 tls 58 1.2.4.2 tls #include <net80211/ieee80211_var.h> 59 1.2.4.2 tls #include <net80211/ieee80211_amrr.h> 60 1.2.4.2 tls #include <net80211/ieee80211_radiotap.h> 61 1.2.4.2 tls 62 1.2.4.2 tls #include <dev/ic/athnreg.h> 63 1.2.4.2 tls #include <dev/ic/athnvar.h> 64 1.2.4.2 tls 65 1.2.4.2 tls #include <dev/ic/arn5008reg.h> 66 1.2.4.2 tls #include <dev/ic/arn5008.h> 67 1.2.4.2 tls #include <dev/ic/arn5416reg.h> /* We share the ROM layout. */ 68 1.2.4.2 tls #include <dev/ic/arn5416.h> /* We share the ROM layout. */ 69 1.2.4.2 tls #include <dev/ic/arn9280reg.h> 70 1.2.4.2 tls #include <dev/ic/arn9280.h> 71 1.2.4.2 tls 72 1.2.4.2 tls #define Static static 73 1.2.4.2 tls 74 1.2.4.2 tls Static void ar9280_init_from_rom(struct athn_softc *, 75 1.2.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 76 1.2.4.2 tls Static void ar9280_olpc_init(struct athn_softc *); 77 1.2.4.2 tls Static void ar9280_olpc_temp_compensation(struct athn_softc *); 78 1.2.4.2 tls Static void ar9280_setup(struct athn_softc *); 79 1.2.4.2 tls 80 1.2.4.2 tls PUBLIC int 81 1.2.4.2 tls ar9280_attach(struct athn_softc *sc) 82 1.2.4.2 tls { 83 1.2.4.2 tls 84 1.2.4.2 tls sc->sc_eep_base = AR5416_EEP_START_LOC; 85 1.2.4.2 tls sc->sc_eep_size = sizeof(struct ar5416_eeprom); 86 1.2.4.2 tls sc->sc_def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE; 87 1.2.4.2 tls sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 10; 88 1.2.4.2 tls sc->sc_led_pin = 1; 89 1.2.4.2 tls sc->sc_workaround = AR9280_WA_DEFAULT; 90 1.2.4.2 tls sc->sc_ops.setup = ar9280_setup; 91 1.2.4.2 tls sc->sc_ops.swap_rom = ar5416_swap_rom; 92 1.2.4.2 tls sc->sc_ops.init_from_rom = ar9280_init_from_rom; 93 1.2.4.2 tls sc->sc_ops.set_txpower = ar5416_set_txpower; 94 1.2.4.2 tls sc->sc_ops.set_synth = ar9280_set_synth; 95 1.2.4.2 tls sc->sc_ops.spur_mitigate = ar9280_spur_mitigate; 96 1.2.4.2 tls sc->sc_ops.get_spur_chans = ar5416_get_spur_chans; 97 1.2.4.2 tls sc->sc_ops.olpc_init = ar9280_olpc_init; 98 1.2.4.2 tls sc->sc_ops.olpc_temp_compensation = ar9280_olpc_temp_compensation; 99 1.2.4.2 tls sc->sc_ini = &ar9280_2_0_ini; 100 1.2.4.2 tls sc->sc_serdes = &ar9280_2_0_serdes; 101 1.2.4.2 tls 102 1.2.4.2 tls return ar5008_attach(sc); 103 1.2.4.2 tls } 104 1.2.4.2 tls 105 1.2.4.2 tls Static void 106 1.2.4.2 tls ar9280_setup(struct athn_softc *sc) 107 1.2.4.2 tls { 108 1.2.4.2 tls const struct ar5416_eeprom *eep = sc->sc_eep; 109 1.2.4.2 tls uint8_t type; 110 1.2.4.2 tls 111 1.2.4.2 tls /* Determine if open loop power control should be used. */ 112 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19 && 113 1.2.4.2 tls eep->baseEepHeader.openLoopPwrCntl) 114 1.2.4.2 tls sc->sc_flags |= ATHN_FLAG_OLPC; 115 1.2.4.2 tls 116 1.2.4.2 tls /* Determine if fast PLL clock is supported. */ 117 1.2.4.2 tls if (AR_SREV_9280_20(sc) && 118 1.2.4.2 tls (sc->sc_eep_rev <= AR_EEP_MINOR_VER_16 || 119 1.2.4.2 tls eep->baseEepHeader.fastClk5g)) 120 1.2.4.2 tls sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK; 121 1.2.4.2 tls 122 1.2.4.2 tls /* 123 1.2.4.2 tls * Determine if initialization value for AR_AN_TOP2 must be fixed. 124 1.2.4.2 tls * This is required for some AR9220 devices such as Ubiquiti SR71-12. 125 1.2.4.2 tls */ 126 1.2.4.2 tls if (AR_SREV_9280_20(sc) && 127 1.2.4.2 tls sc->sc_eep_rev > AR_EEP_MINOR_VER_10 && 128 1.2.4.2 tls !eep->baseEepHeader.pwdclkind) { 129 1.2.4.2 tls DPRINTFN(DBG_INIT, sc, "AR_AN_TOP2 fixup required\n"); 130 1.2.4.2 tls sc->sc_flags |= ATHN_FLAG_AN_TOP2_FIXUP; 131 1.2.4.2 tls } 132 1.2.4.2 tls 133 1.2.4.2 tls if (AR_SREV_9280_20(sc)) { 134 1.2.4.2 tls /* Check if we have a valid rxGainType field in ROM. */ 135 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_17) { 136 1.2.4.2 tls /* Select initialization values based on ROM. */ 137 1.2.4.2 tls type = eep->baseEepHeader.rxGainType; 138 1.2.4.2 tls DPRINTFN(DBG_INIT, sc, "Rx gain type=0x%x\n", type); 139 1.2.4.2 tls if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 140 1.2.4.2 tls sc->sc_rx_gain = &ar9280_2_0_rx_gain_23db_backoff; 141 1.2.4.2 tls else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 142 1.2.4.2 tls sc->sc_rx_gain = &ar9280_2_0_rx_gain_13db_backoff; 143 1.2.4.2 tls else 144 1.2.4.2 tls sc->sc_rx_gain = &ar9280_2_0_rx_gain; 145 1.2.4.2 tls } 146 1.2.4.2 tls else 147 1.2.4.2 tls sc->sc_rx_gain = &ar9280_2_0_rx_gain; 148 1.2.4.2 tls 149 1.2.4.2 tls /* Check if we have a valid txGainType field in ROM. */ 150 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) { 151 1.2.4.2 tls /* Select initialization values based on ROM. */ 152 1.2.4.2 tls type = eep->baseEepHeader.txGainType; 153 1.2.4.2 tls DPRINTFN(DBG_INIT, sc, "Tx gain type=0x%x\n", type); 154 1.2.4.2 tls if (type == AR_EEP_TXGAIN_HIGH_POWER) 155 1.2.4.2 tls sc->sc_tx_gain = &ar9280_2_0_tx_gain_high_power; 156 1.2.4.2 tls else 157 1.2.4.2 tls sc->sc_tx_gain = &ar9280_2_0_tx_gain; 158 1.2.4.2 tls } 159 1.2.4.2 tls else 160 1.2.4.2 tls sc->sc_tx_gain = &ar9280_2_0_tx_gain; 161 1.2.4.2 tls } 162 1.2.4.2 tls } 163 1.2.4.2 tls 164 1.2.4.2 tls PUBLIC int 165 1.2.4.2 tls ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c, 166 1.2.4.2 tls struct ieee80211_channel *extc) 167 1.2.4.2 tls { 168 1.2.4.2 tls uint32_t phy, reg, ndiv = 0; 169 1.2.4.2 tls uint32_t freq = c->ic_freq; 170 1.2.4.2 tls 171 1.2.4.2 tls phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff; 172 1.2.4.2 tls 173 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) { 174 1.2.4.2 tls phy |= (freq << 16) / 15; 175 1.2.4.2 tls phy |= AR9280_BMODE | AR9280_FRACMODE; 176 1.2.4.2 tls 177 1.2.4.2 tls if (AR_SREV_9287_11_OR_LATER(sc)) { 178 1.2.4.2 tls /* NB: Magic values from the Linux driver. */ 179 1.2.4.2 tls if (freq == 2484) { /* Channel 14. */ 180 1.2.4.2 tls /* Japanese regulatory requirements. */ 181 1.2.4.2 tls AR_WRITE(sc, AR_PHY(637), 0x00000000); 182 1.2.4.2 tls AR_WRITE(sc, AR_PHY(638), 0xefff0301); 183 1.2.4.2 tls AR_WRITE(sc, AR_PHY(639), 0xca9228ee); 184 1.2.4.2 tls } 185 1.2.4.2 tls else { 186 1.2.4.2 tls AR_WRITE(sc, AR_PHY(637), 0x00fffeff); 187 1.2.4.2 tls AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff); 188 1.2.4.2 tls AR_WRITE(sc, AR_PHY(639), 0xb79f6427); 189 1.2.4.2 tls } 190 1.2.4.2 tls } 191 1.2.4.2 tls else { 192 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL); 193 1.2.4.2 tls if (freq == 2484) /* Channel 14. */ 194 1.2.4.2 tls reg |= AR_PHY_CCK_TX_CTRL_JAPAN; 195 1.2.4.2 tls else 196 1.2.4.2 tls reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN; 197 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); 198 1.2.4.2 tls } 199 1.2.4.2 tls } 200 1.2.4.2 tls else { 201 1.2.4.2 tls if (AR_SREV_9285_10_OR_LATER(sc) || 202 1.2.4.2 tls sc->sc_eep_rev < AR_EEP_MINOR_VER_22 || 203 1.2.4.2 tls !((struct ar5416_base_eep_header *)sc->sc_eep)->frac_n_5g) { 204 1.2.4.2 tls if ((freq % 20) == 0) { 205 1.2.4.2 tls ndiv = (freq * 3) / 60; 206 1.2.4.2 tls phy |= SM(AR9280_AMODE_REFSEL, 3); 207 1.2.4.2 tls } 208 1.2.4.2 tls else if ((freq % 10) == 0) { 209 1.2.4.2 tls ndiv = (freq * 6) / 60; 210 1.2.4.2 tls phy |= SM(AR9280_AMODE_REFSEL, 2); 211 1.2.4.2 tls } 212 1.2.4.2 tls } 213 1.2.4.2 tls if (ndiv != 0) { 214 1.2.4.2 tls phy |= (ndiv & 0x1ff) << 17; 215 1.2.4.2 tls phy |= (ndiv & ~0x1ff) * 2; 216 1.2.4.2 tls } 217 1.2.4.2 tls else { 218 1.2.4.2 tls phy |= (freq << 15) / 15; 219 1.2.4.2 tls phy |= AR9280_FRACMODE; 220 1.2.4.2 tls 221 1.2.4.2 tls reg = AR_READ(sc, AR_AN_SYNTH9); 222 1.2.4.2 tls reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1); 223 1.2.4.2 tls AR_WRITE(sc, AR_AN_SYNTH9, reg); 224 1.2.4.2 tls } 225 1.2.4.2 tls } 226 1.2.4.2 tls AR_WRITE_BARRIER(sc); 227 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy); 228 1.2.4.2 tls AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy); 229 1.2.4.2 tls AR_WRITE_BARRIER(sc); 230 1.2.4.2 tls return 0; 231 1.2.4.2 tls } 232 1.2.4.2 tls 233 1.2.4.2 tls Static void 234 1.2.4.2 tls ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 235 1.2.4.2 tls struct ieee80211_channel *extc) 236 1.2.4.2 tls { 237 1.2.4.2 tls static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 }; 238 1.2.4.2 tls const struct ar5416_eeprom *eep = sc->sc_eep; 239 1.2.4.2 tls const struct ar5416_modal_eep_header *modal; 240 1.2.4.2 tls uint32_t reg, offset; 241 1.2.4.2 tls uint8_t txRxAtten; 242 1.2.4.2 tls int i; 243 1.2.4.2 tls 244 1.2.4.2 tls modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; 245 1.2.4.2 tls 246 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 247 1.2.4.2 tls 248 1.2.4.2 tls for (i = 0; i < AR9280_MAX_CHAINS; i++) { 249 1.2.4.2 tls if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5) 250 1.2.4.2 tls offset = chainoffset[i]; 251 1.2.4.2 tls else 252 1.2.4.2 tls offset = i * 0x1000; 253 1.2.4.2 tls 254 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 255 1.2.4.2 tls modal->antCtrlChain[i]); 256 1.2.4.2 tls 257 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 258 1.2.4.2 tls reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 259 1.2.4.2 tls modal->iqCalICh[i]); 260 1.2.4.2 tls reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 261 1.2.4.2 tls modal->iqCalQCh[i]); 262 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 263 1.2.4.2 tls 264 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) { 265 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 266 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 267 1.2.4.2 tls modal->bswMargin[i]); 268 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 269 1.2.4.2 tls modal->bswAtten[i]); 270 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 271 1.2.4.2 tls modal->xatten2Margin[i]); 272 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 273 1.2.4.2 tls modal->xatten2Db[i]); 274 1.2.4.2 tls AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 275 1.2.4.2 tls } 276 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) 277 1.2.4.2 tls txRxAtten = modal->txRxAttenCh[i]; 278 1.2.4.2 tls else /* Workaround for ROM versions < 14.3. */ 279 1.2.4.2 tls txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44; 280 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 281 1.2.4.2 tls reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 282 1.2.4.2 tls txRxAtten); 283 1.2.4.2 tls reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 284 1.2.4.2 tls modal->rxTxMarginCh[i]); 285 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 286 1.2.4.2 tls } 287 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) { 288 1.2.4.2 tls reg = AR_READ(sc, AR_AN_RF2G1_CH0); 289 1.2.4.2 tls reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob); 290 1.2.4.2 tls reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db); 291 1.2.4.2 tls AR_WRITE(sc, AR_AN_RF2G1_CH0, reg); 292 1.2.4.2 tls AR_WRITE_BARRIER(sc); 293 1.2.4.2 tls DELAY(100); 294 1.2.4.2 tls 295 1.2.4.2 tls reg = AR_READ(sc, AR_AN_RF2G1_CH1); 296 1.2.4.2 tls reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1); 297 1.2.4.2 tls reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1); 298 1.2.4.2 tls AR_WRITE(sc, AR_AN_RF2G1_CH1, reg); 299 1.2.4.2 tls AR_WRITE_BARRIER(sc); 300 1.2.4.2 tls DELAY(100); 301 1.2.4.2 tls } 302 1.2.4.2 tls else { 303 1.2.4.2 tls reg = AR_READ(sc, AR_AN_RF5G1_CH0); 304 1.2.4.2 tls reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob); 305 1.2.4.2 tls reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db); 306 1.2.4.2 tls AR_WRITE(sc, AR_AN_RF5G1_CH0, reg); 307 1.2.4.2 tls AR_WRITE_BARRIER(sc); 308 1.2.4.2 tls DELAY(100); 309 1.2.4.2 tls 310 1.2.4.2 tls reg = AR_READ(sc, AR_AN_RF5G1_CH1); 311 1.2.4.2 tls reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1); 312 1.2.4.2 tls reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1); 313 1.2.4.2 tls AR_WRITE(sc, AR_AN_RF5G1_CH1, reg); 314 1.2.4.2 tls AR_WRITE_BARRIER(sc); 315 1.2.4.2 tls DELAY(100); 316 1.2.4.2 tls } 317 1.2.4.2 tls reg = AR_READ(sc, AR_AN_TOP2); 318 1.2.4.2 tls if ((sc->sc_flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) { 319 1.2.4.2 tls /* 320 1.2.4.2 tls * Hardcode the output voltage of x-PA bias LDO to the 321 1.2.4.2 tls * lowest value for UB94 such that the card doesn't get 322 1.2.4.2 tls * too hot. 323 1.2.4.2 tls */ 324 1.2.4.2 tls reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0); 325 1.2.4.2 tls } 326 1.2.4.2 tls else 327 1.2.4.2 tls reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); 328 1.2.4.2 tls if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS) 329 1.2.4.2 tls reg |= AR_AN_TOP2_LOCALBIAS; 330 1.2.4.2 tls else 331 1.2.4.2 tls reg &= ~AR_AN_TOP2_LOCALBIAS; 332 1.2.4.2 tls AR_WRITE(sc, AR_AN_TOP2, reg); 333 1.2.4.2 tls AR_WRITE_BARRIER(sc); 334 1.2.4.2 tls DELAY(100); 335 1.2.4.2 tls 336 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_XPA_CFG); 337 1.2.4.2 tls if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON) 338 1.2.4.2 tls reg |= AR_PHY_FORCE_XPA_CFG; 339 1.2.4.2 tls else 340 1.2.4.2 tls reg &= ~AR_PHY_FORCE_XPA_CFG; 341 1.2.4.2 tls AR_WRITE(sc, AR_PHY_XPA_CFG, reg); 342 1.2.4.2 tls 343 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_SETTLING); 344 1.2.4.2 tls reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 345 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SETTLING, reg); 346 1.2.4.2 tls 347 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 348 1.2.4.2 tls reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 349 1.2.4.2 tls AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 350 1.2.4.2 tls 351 1.2.4.2 tls reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 352 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 353 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 354 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 355 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 356 1.2.4.2 tls 357 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RF_CTL3); 358 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 359 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 360 1.2.4.2 tls 361 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CCA(0)); 362 1.2.4.2 tls reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 363 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CCA(0), reg); 364 1.2.4.2 tls 365 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_EXT_CCA0); 366 1.2.4.2 tls reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 367 1.2.4.2 tls AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 368 1.2.4.2 tls 369 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) { 370 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RF_CTL2); 371 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_DATA_START, 372 1.2.4.2 tls modal->txFrameToDataStart); 373 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 374 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 375 1.2.4.2 tls } 376 1.2.4.2 tls #ifndef IEEE80211_NO_HT 377 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) { 378 1.2.4.2 tls /* Overwrite switch settling with HT-40 value. */ 379 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_SETTLING); 380 1.2.4.2 tls reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 381 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SETTLING, reg); 382 1.2.4.2 tls } 383 1.2.4.2 tls #endif 384 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) { 385 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL); 386 1.2.4.2 tls reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, 387 1.2.4.2 tls MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK)); 388 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); 389 1.2.4.2 tls } 390 1.2.4.2 tls if (AR_SREV_9280_20(sc) && 391 1.2.4.2 tls sc->sc_eep_rev >= AR_EEP_MINOR_VER_20) { 392 1.2.4.2 tls reg = AR_READ(sc, AR_AN_TOP1); 393 1.2.4.2 tls if (eep->baseEepHeader.dacLpMode && 394 1.2.4.2 tls (IEEE80211_IS_CHAN_2GHZ(c) || 395 1.2.4.2 tls !eep->baseEepHeader.dacHiPwrMode_5G)) 396 1.2.4.2 tls reg |= AR_AN_TOP1_DACLPMODE; 397 1.2.4.2 tls else 398 1.2.4.2 tls reg &= ~AR_AN_TOP1_DACLPMODE; 399 1.2.4.2 tls AR_WRITE(sc, AR_AN_TOP1, reg); 400 1.2.4.2 tls AR_WRITE_BARRIER(sc); 401 1.2.4.2 tls DELAY(100); 402 1.2.4.2 tls 403 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_FRAME_CTL); 404 1.2.4.2 tls reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP, 405 1.2.4.2 tls MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP)); 406 1.2.4.2 tls AR_WRITE(sc, AR_PHY_FRAME_CTL, reg); 407 1.2.4.2 tls 408 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9); 409 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK, 410 1.2.4.2 tls eep->baseEepHeader.desiredScaleCCK); 411 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg); 412 1.2.4.2 tls } 413 1.2.4.2 tls AR_WRITE_BARRIER(sc); 414 1.2.4.2 tls } 415 1.2.4.2 tls 416 1.2.4.2 tls PUBLIC void 417 1.2.4.2 tls ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 418 1.2.4.2 tls int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain) 419 1.2.4.2 tls { 420 1.2.4.2 tls const struct ar5416_eeprom *eep = sc->sc_eep; 421 1.2.4.2 tls const struct ar_cal_data_per_freq_olpc *pierdata; 422 1.2.4.2 tls const uint8_t *pierfreq; 423 1.2.4.2 tls uint8_t fbin, pcdac, pwr, idx; 424 1.2.4.2 tls int i, lo, hi, npiers; 425 1.2.4.2 tls 426 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) { 427 1.2.4.2 tls pierfreq = eep->calFreqPier2G; 428 1.2.4.2 tls pierdata = (const struct ar_cal_data_per_freq_olpc *) 429 1.2.4.2 tls eep->calPierData2G[chain]; 430 1.2.4.2 tls npiers = AR5416_NUM_2G_CAL_PIERS; 431 1.2.4.2 tls } 432 1.2.4.2 tls else { 433 1.2.4.2 tls pierfreq = eep->calFreqPier5G; 434 1.2.4.2 tls pierdata = (const struct ar_cal_data_per_freq_olpc *) 435 1.2.4.2 tls eep->calPierData5G[chain]; 436 1.2.4.2 tls npiers = AR5416_NUM_5G_CAL_PIERS; 437 1.2.4.2 tls } 438 1.2.4.2 tls /* Find channel in ROM pier table. */ 439 1.2.4.2 tls fbin = athn_chan2fbin(c); 440 1.2.4.2 tls athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 441 1.2.4.2 tls 442 1.2.4.2 tls /* Get average. */ 443 1.2.4.2 tls pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2; 444 1.2.4.2 tls pwr /= 2; /* Convert to dB. */ 445 1.2.4.2 tls 446 1.2.4.2 tls /* Find power control digital-to-analog converter (PCDAC) value. */ 447 1.2.4.2 tls pcdac = pierdata[hi].pcdac[0][0]; 448 1.2.4.2 tls for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++) 449 1.2.4.2 tls if (pcdac <= sc->sc_tx_gain_tbl[idx]) 450 1.2.4.2 tls break; 451 1.2.4.2 tls *txgain = idx; 452 1.2.4.2 tls 453 1.2.4.2 tls DPRINTFN(DBG_RF, sc, 454 1.2.4.2 tls "fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n", 455 1.2.4.2 tls fbin, lo, hi, pwr, pcdac, idx); 456 1.2.4.2 tls 457 1.2.4.2 tls /* Fill phase domain analog-to-digital converter (PDADC) table. */ 458 1.2.4.2 tls for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 459 1.2.4.2 tls pdadcs[i] = (i < pwr) ? 0x00 : 0xff; 460 1.2.4.2 tls 461 1.2.4.2 tls for (i = 0; i < AR_PD_GAINS_IN_MASK; i++) 462 1.2.4.2 tls boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT; 463 1.2.4.2 tls } 464 1.2.4.2 tls 465 1.2.4.2 tls PUBLIC void 466 1.2.4.2 tls ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c, 467 1.2.4.2 tls struct ieee80211_channel *extc) 468 1.2.4.2 tls { 469 1.2.4.2 tls const struct ar_spur_chan *spurchans; 470 1.2.4.2 tls int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd; 471 1.2.4.2 tls int spur_off, range, i; 472 1.2.4.2 tls 473 1.2.4.2 tls /* NB: Always clear. */ 474 1.2.4.2 tls AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 475 1.2.4.2 tls 476 1.2.4.2 tls range = (extc != NULL) ? 19 : 10; 477 1.2.4.2 tls 478 1.2.4.2 tls spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c)); 479 1.2.4.2 tls for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 480 1.2.4.2 tls spur = spurchans[i].spurChan; 481 1.2.4.2 tls if (spur == AR_NO_SPUR) 482 1.2.4.2 tls return; /* XXX disable if it was enabled! */ 483 1.2.4.2 tls spur /= 10; 484 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 485 1.2.4.2 tls spur += AR_BASE_FREQ_2GHZ; 486 1.2.4.2 tls else 487 1.2.4.2 tls spur += AR_BASE_FREQ_5GHZ; 488 1.2.4.2 tls spur -= c->ic_freq; 489 1.2.4.2 tls if (abs(spur) < range) 490 1.2.4.2 tls break; 491 1.2.4.2 tls } 492 1.2.4.2 tls if (i == AR_EEPROM_MODAL_SPURS) 493 1.2.4.2 tls return; /* XXX disable if it was enabled! */ 494 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n"); 495 1.2.4.2 tls 496 1.2.4.2 tls AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, 497 1.2.4.2 tls AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 498 1.2.4.2 tls AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 499 1.2.4.2 tls AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 500 1.2.4.2 tls AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 501 1.2.4.2 tls 502 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SPUR_REG, 503 1.2.4.2 tls AR_PHY_SPUR_REG_MASK_RATE_CNTL | 504 1.2.4.2 tls AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 505 1.2.4.2 tls AR_PHY_SPUR_REG_MASK_RATE_SELECT | 506 1.2.4.2 tls AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 507 1.2.4.2 tls SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH)); 508 1.2.4.2 tls 509 1.2.4.2 tls #ifndef IEEE80211_NO_HT 510 1.2.4.2 tls if (extc != NULL) { 511 1.2.4.2 tls spur_delta_phase = (spur * 262144) / 10; 512 1.2.4.2 tls if (spur < 0) { 513 1.2.4.2 tls spur_subchannel_sd = 1; 514 1.2.4.2 tls spur_off = spur + 10; 515 1.2.4.2 tls } 516 1.2.4.2 tls else { 517 1.2.4.2 tls spur_subchannel_sd = 0; 518 1.2.4.2 tls spur_off = spur - 10; 519 1.2.4.2 tls } 520 1.2.4.2 tls } 521 1.2.4.2 tls else 522 1.2.4.2 tls #endif 523 1.2.4.2 tls { 524 1.2.4.2 tls spur_delta_phase = (spur * 524288) / 10; 525 1.2.4.2 tls spur_subchannel_sd = 0; 526 1.2.4.2 tls spur_off = spur; 527 1.2.4.2 tls } 528 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 529 1.2.4.2 tls spur_freq_sd = (spur_off * 2048) / 44; 530 1.2.4.2 tls else 531 1.2.4.2 tls spur_freq_sd = (spur_off * 2048) / 40; 532 1.2.4.2 tls 533 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TIMING11, 534 1.2.4.2 tls AR_PHY_TIMING11_USE_SPUR_IN_AGC | 535 1.2.4.2 tls SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) | 536 1.2.4.2 tls SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase)); 537 1.2.4.2 tls 538 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SFCORR_EXT, 539 1.2.4.2 tls SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd)); 540 1.2.4.2 tls AR_WRITE_BARRIER(sc); 541 1.2.4.2 tls 542 1.2.4.2 tls bin = spur * 320; 543 1.2.4.2 tls ar5008_set_viterbi_mask(sc, bin); 544 1.2.4.2 tls } 545 1.2.4.2 tls 546 1.2.4.2 tls PUBLIC void 547 1.2.4.2 tls ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 548 1.2.4.2 tls { 549 1.2.4.2 tls const struct athn_gain *prog = sc->sc_rx_gain; 550 1.2.4.2 tls const uint32_t *pvals; 551 1.2.4.2 tls int i; 552 1.2.4.2 tls 553 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 554 1.2.4.2 tls pvals = prog->vals_2g; 555 1.2.4.2 tls else 556 1.2.4.2 tls pvals = prog->vals_5g; 557 1.2.4.2 tls for (i = 0; i < prog->nregs; i++) 558 1.2.4.2 tls AR_WRITE(sc, prog->regs[i], pvals[i]); 559 1.2.4.2 tls } 560 1.2.4.2 tls 561 1.2.4.2 tls PUBLIC void 562 1.2.4.2 tls ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c) 563 1.2.4.2 tls { 564 1.2.4.2 tls const struct athn_gain *prog = sc->sc_tx_gain; 565 1.2.4.2 tls const uint32_t *pvals; 566 1.2.4.2 tls int i; 567 1.2.4.2 tls 568 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 569 1.2.4.2 tls pvals = prog->vals_2g; 570 1.2.4.2 tls else 571 1.2.4.2 tls pvals = prog->vals_5g; 572 1.2.4.2 tls for (i = 0; i < prog->nregs; i++) 573 1.2.4.2 tls AR_WRITE(sc, prog->regs[i], pvals[i]); 574 1.2.4.2 tls } 575 1.2.4.2 tls 576 1.2.4.2 tls Static void 577 1.2.4.2 tls ar9280_olpc_init(struct athn_softc *sc) 578 1.2.4.2 tls { 579 1.2.4.2 tls uint32_t reg; 580 1.2.4.2 tls int i; 581 1.2.4.2 tls 582 1.2.4.2 tls /* Save original Tx gain values. */ 583 1.2.4.2 tls for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { 584 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i)); 585 1.2.4.2 tls sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN); 586 1.2.4.2 tls } 587 1.2.4.2 tls /* Initial Tx gain temperature compensation. */ 588 1.2.4.2 tls sc->sc_tcomp = 0; 589 1.2.4.2 tls } 590 1.2.4.2 tls 591 1.2.4.2 tls Static void 592 1.2.4.2 tls ar9280_olpc_temp_compensation(struct athn_softc *sc) 593 1.2.4.2 tls { 594 1.2.4.2 tls const struct ar5416_eeprom *eep = sc->sc_eep; 595 1.2.4.2 tls int8_t pdadc, txgain, tcomp; 596 1.2.4.2 tls uint32_t reg; 597 1.2.4.2 tls int i; 598 1.2.4.2 tls 599 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4); 600 1.2.4.2 tls pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 601 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc); 602 1.2.4.2 tls 603 1.2.4.2 tls if (sc->sc_pdadc == 0 || pdadc == 0) 604 1.2.4.2 tls return; /* No frames transmitted yet. */ 605 1.2.4.2 tls 606 1.2.4.2 tls /* Compute Tx gain temperature compensation. */ 607 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_20 && 608 1.2.4.2 tls eep->baseEepHeader.dacHiPwrMode_5G) 609 1.2.4.2 tls tcomp = (pdadc - sc->sc_pdadc + 4) / 8; 610 1.2.4.2 tls else 611 1.2.4.2 tls tcomp = (pdadc - sc->sc_pdadc + 5) / 10; 612 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp); 613 1.2.4.2 tls 614 1.2.4.2 tls if (tcomp == sc->sc_tcomp) 615 1.2.4.2 tls return; /* Don't rewrite the same values. */ 616 1.2.4.2 tls sc->sc_tcomp = tcomp; 617 1.2.4.2 tls 618 1.2.4.2 tls /* Adjust Tx gain values. */ 619 1.2.4.2 tls for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { 620 1.2.4.2 tls txgain = sc->sc_tx_gain_tbl[i] - tcomp; 621 1.2.4.2 tls if (txgain < 0) 622 1.2.4.2 tls txgain = 0; 623 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i)); 624 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_GAIN, txgain); 625 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg); 626 1.2.4.2 tls } 627 1.2.4.2 tls AR_WRITE_BARRIER(sc); 628 1.2.4.2 tls } 629
Indexes created Thu Oct 23 22:10:10 GMT 2025