arn9287.c revision 1.2.4.3
1 1.2.4.2 tls /* $NetBSD: arn9287.c,v 1.2.4.3 2014/08/20 00:03:37 tls Exp $ */ 2 1.2.4.2 tls /* $OpenBSD: ar9287.c,v 1.17 2012/06/10 21:23:36 kettenis Exp $ */ 3 1.2.4.2 tls 4 1.2.4.2 tls /*- 5 1.2.4.2 tls * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.2.4.2 tls * Copyright (c) 2008-2009 Atheros Communications Inc. 7 1.2.4.2 tls * 8 1.2.4.2 tls * Permission to use, copy, modify, and/or distribute this software for any 9 1.2.4.2 tls * purpose with or without fee is hereby granted, provided that the above 10 1.2.4.2 tls * copyright notice and this permission notice appear in all copies. 11 1.2.4.2 tls * 12 1.2.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.2.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.2.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.2.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.2.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.2.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.2.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.2.4.2 tls */ 20 1.2.4.2 tls 21 1.2.4.2 tls /* 22 1.2.4.2 tls * Driver for Atheros 802.11a/g/n chipsets. 23 1.2.4.2 tls * Routines for AR9227 and AR9287 chipsets. 24 1.2.4.2 tls */ 25 1.2.4.2 tls 26 1.2.4.2 tls #include <sys/cdefs.h> 27 1.2.4.2 tls __KERNEL_RCSID(0, "$NetBSD: arn9287.c,v 1.2.4.3 2014/08/20 00:03:37 tls Exp $"); 28 1.2.4.2 tls 29 1.2.4.2 tls #include <sys/param.h> 30 1.2.4.2 tls #include <sys/sockio.h> 31 1.2.4.2 tls #include <sys/mbuf.h> 32 1.2.4.2 tls #include <sys/kernel.h> 33 1.2.4.2 tls #include <sys/socket.h> 34 1.2.4.2 tls #include <sys/systm.h> 35 1.2.4.2 tls #include <sys/malloc.h> 36 1.2.4.2 tls #include <sys/queue.h> 37 1.2.4.2 tls #include <sys/callout.h> 38 1.2.4.2 tls #include <sys/conf.h> 39 1.2.4.2 tls #include <sys/device.h> 40 1.2.4.2 tls 41 1.2.4.2 tls #include <sys/bus.h> 42 1.2.4.2 tls #include <sys/endian.h> 43 1.2.4.2 tls #include <sys/intr.h> 44 1.2.4.2 tls 45 1.2.4.2 tls #include <net/bpf.h> 46 1.2.4.2 tls #include <net/if.h> 47 1.2.4.2 tls #include <net/if_arp.h> 48 1.2.4.2 tls #include <net/if_dl.h> 49 1.2.4.2 tls #include <net/if_ether.h> 50 1.2.4.2 tls #include <net/if_media.h> 51 1.2.4.2 tls #include <net/if_types.h> 52 1.2.4.2 tls 53 1.2.4.2 tls #include <netinet/in.h> 54 1.2.4.2 tls #include <netinet/in_systm.h> 55 1.2.4.2 tls #include <netinet/in_var.h> 56 1.2.4.2 tls #include <netinet/ip.h> 57 1.2.4.2 tls 58 1.2.4.2 tls #include <net80211/ieee80211_var.h> 59 1.2.4.2 tls #include <net80211/ieee80211_amrr.h> 60 1.2.4.2 tls #include <net80211/ieee80211_radiotap.h> 61 1.2.4.2 tls 62 1.2.4.2 tls #include <dev/ic/athnreg.h> 63 1.2.4.2 tls #include <dev/ic/athnvar.h> 64 1.2.4.2 tls 65 1.2.4.2 tls #include <dev/ic/arn5008reg.h> 66 1.2.4.2 tls #include <dev/ic/arn9280reg.h> 67 1.2.4.2 tls #include <dev/ic/arn9287reg.h> 68 1.2.4.2 tls 69 1.2.4.2 tls #include <dev/ic/arn5008.h> 70 1.2.4.2 tls #include <dev/ic/arn9280.h> 71 1.2.4.2 tls #include <dev/ic/arn9287.h> 72 1.2.4.2 tls 73 1.2.4.2 tls #define Static static 74 1.2.4.2 tls 75 1.2.4.2 tls Static void ar9287_get_pdadcs(struct athn_softc *, 76 1.2.4.2 tls struct ieee80211_channel *, int, int, uint8_t, uint8_t *, 77 1.2.4.2 tls uint8_t *); 78 1.2.4.2 tls Static const struct ar_spur_chan * 79 1.2.4.2 tls ar9287_get_spur_chans(struct athn_softc *, int); 80 1.2.4.2 tls Static void ar9287_init_from_rom(struct athn_softc *, 81 1.2.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 82 1.2.4.2 tls Static void ar9287_olpc_get_pdgain(struct athn_softc *, 83 1.2.4.2 tls struct ieee80211_channel *, int, int8_t *); 84 1.2.4.2 tls Static void ar9287_olpc_init(struct athn_softc *); 85 1.2.4.2 tls Static void ar9287_olpc_temp_compensation(struct athn_softc *); 86 1.2.4.2 tls Static void ar9287_set_power_calib(struct athn_softc *, 87 1.2.4.2 tls struct ieee80211_channel *); 88 1.2.4.2 tls Static void ar9287_set_txpower(struct athn_softc *, 89 1.2.4.2 tls struct ieee80211_channel *, struct ieee80211_channel *); 90 1.2.4.2 tls Static void ar9287_setup(struct athn_softc *); 91 1.2.4.2 tls Static void ar9287_swap_rom(struct athn_softc *); 92 1.2.4.2 tls 93 1.2.4.2 tls PUBLIC int 94 1.2.4.2 tls ar9287_attach(struct athn_softc *sc) 95 1.2.4.2 tls { 96 1.2.4.2 tls 97 1.2.4.2 tls sc->sc_eep_base = AR9287_EEP_START_LOC; 98 1.2.4.2 tls sc->sc_eep_size = sizeof(struct ar9287_eeprom); 99 1.2.4.2 tls sc->sc_def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE; 100 1.2.4.2 tls sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 11; 101 1.2.4.2 tls sc->sc_led_pin = 8; 102 1.2.4.2 tls sc->sc_workaround = AR9285_WA_DEFAULT; 103 1.2.4.2 tls sc->sc_ops.setup = ar9287_setup; 104 1.2.4.2 tls sc->sc_ops.swap_rom = ar9287_swap_rom; 105 1.2.4.2 tls sc->sc_ops.init_from_rom = ar9287_init_from_rom; 106 1.2.4.2 tls sc->sc_ops.set_txpower = ar9287_set_txpower; 107 1.2.4.2 tls sc->sc_ops.set_synth = ar9280_set_synth; 108 1.2.4.2 tls sc->sc_ops.spur_mitigate = ar9280_spur_mitigate; 109 1.2.4.2 tls sc->sc_ops.get_spur_chans = ar9287_get_spur_chans; 110 1.2.4.2 tls sc->sc_ops.olpc_init = ar9287_olpc_init; 111 1.2.4.2 tls sc->sc_ops.olpc_temp_compensation = ar9287_olpc_temp_compensation; 112 1.2.4.2 tls sc->sc_ini = &ar9287_1_1_ini; 113 1.2.4.2 tls sc->sc_serdes = &ar9280_2_0_serdes; 114 1.2.4.2 tls 115 1.2.4.2 tls return ar5008_attach(sc); 116 1.2.4.2 tls } 117 1.2.4.2 tls 118 1.2.4.2 tls Static void 119 1.2.4.2 tls ar9287_setup(struct athn_softc *sc) 120 1.2.4.2 tls { 121 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 122 1.2.4.2 tls 123 1.2.4.2 tls /* Determine if open loop power control should be used. */ 124 1.2.4.2 tls if (eep->baseEepHeader.openLoopPwrCntl) 125 1.2.4.2 tls sc->sc_flags |= ATHN_FLAG_OLPC; 126 1.2.4.2 tls 127 1.2.4.2 tls sc->sc_rx_gain = &ar9287_1_1_rx_gain; 128 1.2.4.2 tls sc->sc_tx_gain = &ar9287_1_1_tx_gain; 129 1.2.4.2 tls } 130 1.2.4.2 tls 131 1.2.4.2 tls Static void 132 1.2.4.2 tls ar9287_swap_rom(struct athn_softc *sc) 133 1.2.4.2 tls { 134 1.2.4.2 tls struct ar9287_eeprom *eep = sc->sc_eep; 135 1.2.4.2 tls int i; 136 1.2.4.2 tls 137 1.2.4.2 tls eep->modalHeader.antCtrlCommon = 138 1.2.4.2 tls bswap32(eep->modalHeader.antCtrlCommon); 139 1.2.4.2 tls 140 1.2.4.2 tls for (i = 0; i < AR9287_MAX_CHAINS; i++) { 141 1.2.4.2 tls eep->modalHeader.antCtrlChain[i] = 142 1.2.4.2 tls bswap32(eep->modalHeader.antCtrlChain[i]); 143 1.2.4.2 tls } 144 1.2.4.2 tls for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 145 1.2.4.2 tls eep->modalHeader.spurChans[i].spurChan = 146 1.2.4.2 tls bswap16(eep->modalHeader.spurChans[i].spurChan); 147 1.2.4.2 tls } 148 1.2.4.2 tls } 149 1.2.4.2 tls 150 1.2.4.2 tls Static const struct ar_spur_chan * 151 1.2.4.2 tls ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz) 152 1.2.4.2 tls { 153 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 154 1.2.4.2 tls 155 1.2.4.2 tls KASSERT(is2ghz); 156 1.2.4.2 tls return eep->modalHeader.spurChans; 157 1.2.4.2 tls } 158 1.2.4.2 tls 159 1.2.4.2 tls Static void 160 1.2.4.2 tls ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 161 1.2.4.2 tls struct ieee80211_channel *extc) 162 1.2.4.2 tls { 163 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 164 1.2.4.2 tls const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 165 1.2.4.2 tls uint32_t reg, offset; 166 1.2.4.2 tls int i; 167 1.2.4.2 tls 168 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 169 1.2.4.2 tls 170 1.2.4.2 tls for (i = 0; i < AR9287_MAX_CHAINS; i++) { 171 1.2.4.2 tls offset = i * 0x1000; 172 1.2.4.2 tls 173 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 174 1.2.4.2 tls modal->antCtrlChain[i]); 175 1.2.4.2 tls 176 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 177 1.2.4.2 tls reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 178 1.2.4.2 tls modal->iqCalICh[i]); 179 1.2.4.2 tls reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 180 1.2.4.2 tls modal->iqCalQCh[i]); 181 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 182 1.2.4.2 tls 183 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 184 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 185 1.2.4.2 tls modal->bswMargin[i]); 186 1.2.4.2 tls reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 187 1.2.4.2 tls modal->bswAtten[i]); 188 1.2.4.2 tls AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 189 1.2.4.2 tls 190 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 191 1.2.4.2 tls reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 192 1.2.4.2 tls modal->rxTxMarginCh[i]); 193 1.2.4.2 tls reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 194 1.2.4.2 tls modal->txRxAttenCh[i]); 195 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 196 1.2.4.2 tls } 197 1.2.4.2 tls 198 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_SETTLING); 199 1.2.4.2 tls #ifndef IEEE80211_NO_HT 200 1.2.4.2 tls if (extc != NULL) 201 1.2.4.2 tls reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 202 1.2.4.2 tls else 203 1.2.4.2 tls #endif 204 1.2.4.2 tls reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 205 1.2.4.2 tls AR_WRITE(sc, AR_PHY_SETTLING, reg); 206 1.2.4.2 tls 207 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 208 1.2.4.2 tls reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 209 1.2.4.2 tls AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 210 1.2.4.2 tls 211 1.2.4.2 tls reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 212 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 213 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 214 1.2.4.2 tls reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 215 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 216 1.2.4.2 tls 217 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RF_CTL3); 218 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 219 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 220 1.2.4.2 tls 221 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CCA(0)); 222 1.2.4.2 tls reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 223 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CCA(0), reg); 224 1.2.4.2 tls 225 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_EXT_CCA0); 226 1.2.4.2 tls reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 227 1.2.4.2 tls AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 228 1.2.4.2 tls 229 1.2.4.2 tls reg = AR_READ(sc, AR9287_AN_RF2G3_CH0); 230 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 231 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 232 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 233 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 234 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 235 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 236 1.2.4.2 tls AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg); 237 1.2.4.2 tls AR_WRITE_BARRIER(sc); 238 1.2.4.2 tls DELAY(100); 239 1.2.4.2 tls 240 1.2.4.2 tls reg = AR_READ(sc, AR9287_AN_RF2G3_CH1); 241 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 242 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 243 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 244 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 245 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 246 1.2.4.2 tls reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 247 1.2.4.2 tls AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg); 248 1.2.4.2 tls AR_WRITE_BARRIER(sc); 249 1.2.4.2 tls DELAY(100); 250 1.2.4.2 tls 251 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_RF_CTL2); 252 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); 253 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 254 1.2.4.2 tls AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 255 1.2.4.2 tls 256 1.2.4.2 tls reg = AR_READ(sc, AR9287_AN_TOP2); 257 1.2.4.2 tls reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); 258 1.2.4.2 tls AR_WRITE(sc, AR9287_AN_TOP2, reg); 259 1.2.4.2 tls AR_WRITE_BARRIER(sc); 260 1.2.4.2 tls DELAY(100); 261 1.2.4.2 tls } 262 1.2.4.2 tls 263 1.2.4.2 tls Static void 264 1.2.4.2 tls ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 265 1.2.4.2 tls int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries, 266 1.2.4.2 tls uint8_t *pdadcs) 267 1.2.4.2 tls { 268 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 269 1.2.4.2 tls const struct ar9287_cal_data_per_freq *pierdata; 270 1.2.4.2 tls const uint8_t *pierfreq; 271 1.2.4.2 tls struct athn_pier lopier, hipier; 272 1.2.4.2 tls int16_t delta; 273 1.2.4.2 tls uint8_t fbin; 274 1.2.4.2 tls int i, lo, hi, npiers; 275 1.2.4.2 tls 276 1.2.4.2 tls pierfreq = eep->calFreqPier2G; 277 1.2.4.2 tls pierdata = (const struct ar9287_cal_data_per_freq *) 278 1.2.4.2 tls eep->calPierData2G[chain]; 279 1.2.4.2 tls npiers = AR9287_NUM_2G_CAL_PIERS; 280 1.2.4.2 tls 281 1.2.4.2 tls /* Find channel in ROM pier table. */ 282 1.2.4.2 tls fbin = athn_chan2fbin(c); 283 1.2.4.2 tls athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 284 1.2.4.2 tls 285 1.2.4.2 tls lopier.fbin = pierfreq[lo]; 286 1.2.4.2 tls hipier.fbin = pierfreq[hi]; 287 1.2.4.2 tls for (i = 0; i < nxpdgains; i++) { 288 1.2.4.2 tls lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 289 1.2.4.2 tls lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 290 1.2.4.2 tls hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 291 1.2.4.2 tls hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 292 1.2.4.2 tls } 293 1.2.4.2 tls ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 294 1.2.4.2 tls AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 295 1.2.4.2 tls 296 1.2.4.2 tls delta = (eep->baseEepHeader.pwrTableOffset - 297 1.2.4.2 tls AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */ 298 1.2.4.2 tls if (delta != 0) { 299 1.2.4.2 tls /* Shift the PDADC table to start at the new offset. */ 300 1.2.4.2 tls /* XXX Our padding value differs from Linux. */ 301 1.2.4.2 tls for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 302 1.2.4.2 tls pdadcs[i] = pdadcs[MIN(i + delta, 303 1.2.4.2 tls AR_NUM_PDADC_VALUES - 1)]; 304 1.2.4.2 tls } 305 1.2.4.2 tls } 306 1.2.4.2 tls 307 1.2.4.2 tls Static void 308 1.2.4.2 tls ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c, 309 1.2.4.2 tls int chain, int8_t *pwr) 310 1.2.4.2 tls { 311 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 312 1.2.4.2 tls const struct ar_cal_data_per_freq_olpc *pierdata; 313 1.2.4.2 tls const uint8_t *pierfreq; 314 1.2.4.2 tls uint8_t fbin; 315 1.2.4.2 tls int lo, hi, npiers; 316 1.2.4.2 tls 317 1.2.4.2 tls pierfreq = eep->calFreqPier2G; 318 1.2.4.2 tls pierdata = (const struct ar_cal_data_per_freq_olpc *) 319 1.2.4.2 tls eep->calPierData2G[chain]; 320 1.2.4.2 tls npiers = AR9287_NUM_2G_CAL_PIERS; 321 1.2.4.2 tls 322 1.2.4.2 tls /* Find channel in ROM pier table. */ 323 1.2.4.2 tls fbin = athn_chan2fbin(c); 324 1.2.4.2 tls athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 325 1.2.4.2 tls #if 0 326 1.2.4.2 tls *pwr = athn_interpolate(fbin, 327 1.2.4.2 tls pierfreq[lo], pierdata[lo].pwrPdg[0][0], 328 1.2.4.2 tls pierfreq[hi], pierdata[hi].pwrPdg[0][0]); 329 1.2.4.2 tls #else 330 1.2.4.2 tls *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2; 331 1.2.4.2 tls #endif 332 1.2.4.2 tls } 333 1.2.4.2 tls 334 1.2.4.2 tls Static void 335 1.2.4.2 tls ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 336 1.2.4.2 tls { 337 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 338 1.2.4.2 tls uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 339 1.2.4.2 tls uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 340 1.2.4.2 tls uint8_t xpdgains[AR9287_NUM_PD_GAINS]; 341 1.2.4.2 tls int8_t txpower; 342 1.2.4.2 tls uint8_t overlap; 343 1.2.4.2 tls uint32_t reg, offset; 344 1.2.4.2 tls int i, j, nxpdgains; 345 1.2.4.2 tls 346 1.2.4.2 tls if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) { 347 1.2.4.2 tls overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 348 1.2.4.2 tls AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 349 1.2.4.2 tls } 350 1.2.4.2 tls else 351 1.2.4.2 tls overlap = eep->modalHeader.pdGainOverlap; 352 1.2.4.2 tls 353 1.2.4.2 tls if (sc->sc_flags & ATHN_FLAG_OLPC) { 354 1.2.4.2 tls /* XXX not here. */ 355 1.2.4.2 tls sc->sc_pdadc = 356 1.2.4.2 tls ((const struct ar_cal_data_per_freq_olpc *) 357 1.2.4.2 tls eep->calPierData2G[0])->vpdPdg[0][0]; 358 1.2.4.2 tls } 359 1.2.4.2 tls 360 1.2.4.2 tls nxpdgains = 0; 361 1.2.4.2 tls memset(xpdgains, 0, sizeof(xpdgains)); 362 1.2.4.2 tls for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 363 1.2.4.2 tls if (nxpdgains >= AR9287_NUM_PD_GAINS) 364 1.2.4.2 tls break; /* Can't happen. */ 365 1.2.4.2 tls if (eep->modalHeader.xpdGain & (1 << i)) 366 1.2.4.2 tls xpdgains[nxpdgains++] = i; 367 1.2.4.2 tls } 368 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TPCRG1); 369 1.2.4.2 tls reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 370 1.2.4.2 tls reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 371 1.2.4.2 tls reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 372 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TPCRG1, reg); 373 1.2.4.2 tls AR_WRITE_BARRIER(sc); 374 1.2.4.2 tls 375 1.2.4.2 tls for (i = 0; i < AR9287_MAX_CHAINS; i++) { 376 1.2.4.2 tls if (!(sc->sc_txchainmask & (1 << i))) 377 1.2.4.2 tls continue; 378 1.2.4.2 tls 379 1.2.4.2 tls offset = i * 0x1000; 380 1.2.4.2 tls 381 1.2.4.2 tls if (sc->sc_flags & ATHN_FLAG_OLPC) { 382 1.2.4.2 tls ar9287_olpc_get_pdgain(sc, c, i, &txpower); 383 1.2.4.2 tls 384 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0); 385 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 386 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg); 387 1.2.4.2 tls 388 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1); 389 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 390 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg); 391 1.2.4.2 tls 392 1.2.4.2 tls /* NB: txpower is in half dB. */ 393 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset); 394 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower); 395 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg); 396 1.2.4.2 tls 397 1.2.4.2 tls AR_WRITE_BARRIER(sc); 398 1.2.4.2 tls continue; /* That's it for open loop mode. */ 399 1.2.4.2 tls } 400 1.2.4.2 tls 401 1.2.4.2 tls /* Closed loop power control. */ 402 1.2.4.2 tls ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap, 403 1.2.4.2 tls boundaries, pdadcs); 404 1.2.4.2 tls 405 1.2.4.2 tls /* Write boundaries. */ 406 1.2.4.2 tls if (i == 0) { 407 1.2.4.2 tls reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, 408 1.2.4.2 tls overlap); 409 1.2.4.2 tls reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, 410 1.2.4.2 tls boundaries[0]); 411 1.2.4.2 tls reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, 412 1.2.4.2 tls boundaries[1]); 413 1.2.4.2 tls reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, 414 1.2.4.2 tls boundaries[2]); 415 1.2.4.2 tls reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, 416 1.2.4.2 tls boundaries[3]); 417 1.2.4.2 tls AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg); 418 1.2.4.2 tls } 419 1.2.4.2 tls /* Write PDADC values. */ 420 1.2.4.2 tls for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) { 421 1.2.4.2 tls AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j, 422 1.2.4.2 tls pdadcs[j + 0] << 0 | 423 1.2.4.2 tls pdadcs[j + 1] << 8 | 424 1.2.4.2 tls pdadcs[j + 2] << 16 | 425 1.2.4.2 tls pdadcs[j + 3] << 24); 426 1.2.4.2 tls } 427 1.2.4.2 tls AR_WRITE_BARRIER(sc); 428 1.2.4.2 tls } 429 1.2.4.2 tls } 430 1.2.4.2 tls 431 1.2.4.2 tls Static void 432 1.2.4.2 tls ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 433 1.2.4.2 tls struct ieee80211_channel *extc) 434 1.2.4.2 tls { 435 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 436 1.2.4.3 tls #ifdef notyet 437 1.2.4.2 tls const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 438 1.2.4.3 tls #endif 439 1.2.4.2 tls uint8_t tpow_cck[4], tpow_ofdm[4]; 440 1.2.4.2 tls #ifndef IEEE80211_NO_HT 441 1.2.4.2 tls uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 442 1.2.4.2 tls uint8_t tpow_ht20[8], tpow_ht40[8]; 443 1.2.4.2 tls uint8_t ht40inc; 444 1.2.4.2 tls #endif 445 1.2.4.3 tls int16_t pwr = 0, power[ATHN_POWER_COUNT]; 446 1.2.4.2 tls int i; 447 1.2.4.2 tls 448 1.2.4.2 tls ar9287_set_power_calib(sc, c); 449 1.2.4.2 tls 450 1.2.4.3 tls #ifdef notyet 451 1.2.4.2 tls /* Compute transmit power reduction due to antenna gain. */ 452 1.2.4.3 tls uint16_t max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); 453 1.2.4.2 tls /* XXX */ 454 1.2.4.3 tls #endif 455 1.2.4.2 tls 456 1.2.4.2 tls /* 457 1.2.4.2 tls * Reduce scaled power by number of active chains to get per-chain 458 1.2.4.2 tls * transmit power level. 459 1.2.4.2 tls */ 460 1.2.4.2 tls if (sc->sc_ntxchains == 2) 461 1.2.4.2 tls pwr -= AR_PWR_DECREASE_FOR_2_CHAIN; 462 1.2.4.2 tls if (pwr < 0) 463 1.2.4.2 tls pwr = 0; 464 1.2.4.2 tls 465 1.2.4.2 tls /* Get CCK target powers. */ 466 1.2.4.2 tls ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 467 1.2.4.2 tls AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 468 1.2.4.2 tls 469 1.2.4.2 tls /* Get OFDM target powers. */ 470 1.2.4.2 tls ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 471 1.2.4.2 tls AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 472 1.2.4.2 tls 473 1.2.4.2 tls #ifndef IEEE80211_NO_HT 474 1.2.4.2 tls /* Get HT-20 target powers. */ 475 1.2.4.2 tls ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 476 1.2.4.2 tls AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20); 477 1.2.4.2 tls 478 1.2.4.2 tls if (extc != NULL) { 479 1.2.4.2 tls /* Get HT-40 target powers. */ 480 1.2.4.2 tls ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 481 1.2.4.2 tls eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS, 482 1.2.4.2 tls tpow_ht40); 483 1.2.4.2 tls 484 1.2.4.2 tls /* Get secondary channel CCK target powers. */ 485 1.2.4.2 tls ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 486 1.2.4.2 tls eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS, 487 1.2.4.2 tls tpow_cck_ext); 488 1.2.4.2 tls 489 1.2.4.2 tls /* Get secondary channel OFDM target powers. */ 490 1.2.4.2 tls ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 491 1.2.4.2 tls eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS, 492 1.2.4.2 tls tpow_ofdm_ext); 493 1.2.4.2 tls } 494 1.2.4.2 tls #endif 495 1.2.4.2 tls 496 1.2.4.2 tls memset(power, 0, sizeof(power)); 497 1.2.4.2 tls /* Shuffle target powers accross transmit rates. */ 498 1.2.4.2 tls power[ATHN_POWER_OFDM6 ] = 499 1.2.4.2 tls power[ATHN_POWER_OFDM9 ] = 500 1.2.4.2 tls power[ATHN_POWER_OFDM12 ] = 501 1.2.4.2 tls power[ATHN_POWER_OFDM18 ] = 502 1.2.4.2 tls power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 503 1.2.4.2 tls power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 504 1.2.4.2 tls power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 505 1.2.4.2 tls power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 506 1.2.4.2 tls power[ATHN_POWER_XR ] = tpow_ofdm[0]; 507 1.2.4.2 tls power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 508 1.2.4.2 tls power[ATHN_POWER_CCK2_LP ] = 509 1.2.4.2 tls power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 510 1.2.4.2 tls power[ATHN_POWER_CCK55_LP] = 511 1.2.4.2 tls power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 512 1.2.4.2 tls power[ATHN_POWER_CCK11_LP] = 513 1.2.4.2 tls power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 514 1.2.4.2 tls #ifndef IEEE80211_NO_HT 515 1.2.4.2 tls for (i = 0; i < nitems(tpow_ht20); i++) 516 1.2.4.2 tls power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 517 1.2.4.2 tls if (extc != NULL) { 518 1.2.4.2 tls /* Correct PAR difference between HT40 and HT20/Legacy. */ 519 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) 520 1.2.4.2 tls ht40inc = modal->ht40PowerIncForPdadc; 521 1.2.4.2 tls else 522 1.2.4.2 tls ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 523 1.2.4.2 tls for (i = 0; i < nitems(tpow_ht40); i++) 524 1.2.4.2 tls power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 525 1.2.4.2 tls power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 526 1.2.4.2 tls power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 527 1.2.4.2 tls power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 528 1.2.4.2 tls if (IEEE80211_IS_CHAN_2GHZ(c)) 529 1.2.4.2 tls power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0]; 530 1.2.4.2 tls } 531 1.2.4.2 tls #endif 532 1.2.4.2 tls 533 1.2.4.2 tls for (i = 0; i < ATHN_POWER_COUNT; i++) { 534 1.2.4.2 tls power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 535 1.2.4.2 tls if (power[i] > AR_MAX_RATE_POWER) 536 1.2.4.2 tls power[i] = AR_MAX_RATE_POWER; 537 1.2.4.2 tls } 538 1.2.4.2 tls /* Commit transmit power values to hardware. */ 539 1.2.4.2 tls ar5008_write_txpower(sc, power); 540 1.2.4.2 tls } 541 1.2.4.2 tls 542 1.2.4.2 tls Static void 543 1.2.4.2 tls ar9287_olpc_init(struct athn_softc *sc) 544 1.2.4.2 tls { 545 1.2.4.2 tls uint32_t reg; 546 1.2.4.2 tls 547 1.2.4.2 tls AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 548 1.2.4.2 tls 549 1.2.4.2 tls reg = AR_READ(sc, AR9287_AN_TXPC0); 550 1.2.4.2 tls reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE, 551 1.2.4.2 tls AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 552 1.2.4.2 tls AR_WRITE(sc, AR9287_AN_TXPC0, reg); 553 1.2.4.2 tls AR_WRITE_BARRIER(sc); 554 1.2.4.2 tls DELAY(100); 555 1.2.4.2 tls } 556 1.2.4.2 tls 557 1.2.4.2 tls Static void 558 1.2.4.2 tls ar9287_olpc_temp_compensation(struct athn_softc *sc) 559 1.2.4.2 tls { 560 1.2.4.2 tls const struct ar9287_eeprom *eep = sc->sc_eep; 561 1.2.4.2 tls int8_t pdadc, slope, tcomp; 562 1.2.4.2 tls uint32_t reg; 563 1.2.4.2 tls 564 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4); 565 1.2.4.2 tls pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 566 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc); 567 1.2.4.2 tls 568 1.2.4.2 tls if (sc->sc_pdadc == 0 || pdadc == 0) 569 1.2.4.2 tls return; /* No frames transmitted yet. */ 570 1.2.4.2 tls 571 1.2.4.2 tls /* Compute Tx gain temperature compensation. */ 572 1.2.4.2 tls if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) 573 1.2.4.2 tls slope = eep->baseEepHeader.tempSensSlope; 574 1.2.4.2 tls else 575 1.2.4.2 tls slope = 0; 576 1.2.4.2 tls if (slope != 0) /* Prevents division by zero. */ 577 1.2.4.2 tls tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope; 578 1.2.4.2 tls else 579 1.2.4.2 tls tcomp = 0; 580 1.2.4.2 tls DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp); 581 1.2.4.2 tls 582 1.2.4.2 tls /* Write compensation value for both Tx chains. */ 583 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11); 584 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 585 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg); 586 1.2.4.2 tls 587 1.2.4.2 tls reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11); 588 1.2.4.2 tls reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 589 1.2.4.2 tls AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg); 590 1.2.4.2 tls AR_WRITE_BARRIER(sc); 591 1.2.4.2 tls } 592 1.2.4.2 tls 593 1.2.4.2 tls PUBLIC void 594 1.2.4.2 tls ar9287_1_3_enable_async_fifo(struct athn_softc *sc) 595 1.2.4.2 tls { 596 1.2.4.2 tls 597 1.2.4.2 tls /* Enable ASYNC FIFO. */ 598 1.2.4.2 tls AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 599 1.2.4.2 tls AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 600 1.2.4.2 tls AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 601 1.2.4.2 tls AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 602 1.2.4.2 tls AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 603 1.2.4.2 tls AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 604 1.2.4.2 tls AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 605 1.2.4.2 tls AR_WRITE_BARRIER(sc); 606 1.2.4.2 tls } 607 1.2.4.2 tls 608 1.2.4.2 tls PUBLIC void 609 1.2.4.2 tls ar9287_1_3_setup_async_fifo(struct athn_softc *sc) 610 1.2.4.2 tls { 611 1.2.4.2 tls uint32_t reg; 612 1.2.4.2 tls 613 1.2.4.2 tls /* 614 1.2.4.2 tls * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is 615 1.2.4.2 tls * enabled, so the following counters have to be changed. 616 1.2.4.2 tls */ 617 1.2.4.2 tls AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 618 1.2.4.2 tls AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 619 1.2.4.2 tls AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 620 1.2.4.2 tls 621 1.2.4.2 tls AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 622 1.2.4.2 tls AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 623 1.2.4.2 tls 624 1.2.4.2 tls AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER, 625 1.2.4.2 tls AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 626 1.2.4.2 tls 627 1.2.4.2 tls reg = AR_READ(sc, AR_AHB_MODE); 628 1.2.4.2 tls reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 629 1.2.4.2 tls AR_WRITE(sc, AR_AHB_MODE, reg); 630 1.2.4.2 tls 631 1.2.4.2 tls AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 632 1.2.4.2 tls AR_WRITE_BARRIER(sc); 633 1.2.4.2 tls } 634
Indexes created Tue Oct 21 16:10:11 GMT 2025