arn9287.c revision 1.3
1 /* $NetBSD: arn9287.c,v 1.3 2013/10/17 21:24:24 christos Exp $ */ 2 /* $OpenBSD: ar9287.c,v 1.17 2012/06/10 21:23:36 kettenis Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2009 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 * Routines for AR9227 and AR9287 chipsets. 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: arn9287.c,v 1.3 2013/10/17 21:24:24 christos Exp $"); 28 29 #include <sys/param.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/queue.h> 37 #include <sys/callout.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 65 #include <dev/ic/arn5008reg.h> 66 #include <dev/ic/arn9280reg.h> 67 #include <dev/ic/arn9287reg.h> 68 69 #include <dev/ic/arn5008.h> 70 #include <dev/ic/arn9280.h> 71 #include <dev/ic/arn9287.h> 72 73 #define Static static 74 75 Static void ar9287_get_pdadcs(struct athn_softc *, 76 struct ieee80211_channel *, int, int, uint8_t, uint8_t *, 77 uint8_t *); 78 Static const struct ar_spur_chan * 79 ar9287_get_spur_chans(struct athn_softc *, int); 80 Static void ar9287_init_from_rom(struct athn_softc *, 81 struct ieee80211_channel *, struct ieee80211_channel *); 82 Static void ar9287_olpc_get_pdgain(struct athn_softc *, 83 struct ieee80211_channel *, int, int8_t *); 84 Static void ar9287_olpc_init(struct athn_softc *); 85 Static void ar9287_olpc_temp_compensation(struct athn_softc *); 86 Static void ar9287_set_power_calib(struct athn_softc *, 87 struct ieee80211_channel *); 88 Static void ar9287_set_txpower(struct athn_softc *, 89 struct ieee80211_channel *, struct ieee80211_channel *); 90 Static void ar9287_setup(struct athn_softc *); 91 Static void ar9287_swap_rom(struct athn_softc *); 92 93 PUBLIC int 94 ar9287_attach(struct athn_softc *sc) 95 { 96 97 sc->sc_eep_base = AR9287_EEP_START_LOC; 98 sc->sc_eep_size = sizeof(struct ar9287_eeprom); 99 sc->sc_def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE; 100 sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 11; 101 sc->sc_led_pin = 8; 102 sc->sc_workaround = AR9285_WA_DEFAULT; 103 sc->sc_ops.setup = ar9287_setup; 104 sc->sc_ops.swap_rom = ar9287_swap_rom; 105 sc->sc_ops.init_from_rom = ar9287_init_from_rom; 106 sc->sc_ops.set_txpower = ar9287_set_txpower; 107 sc->sc_ops.set_synth = ar9280_set_synth; 108 sc->sc_ops.spur_mitigate = ar9280_spur_mitigate; 109 sc->sc_ops.get_spur_chans = ar9287_get_spur_chans; 110 sc->sc_ops.olpc_init = ar9287_olpc_init; 111 sc->sc_ops.olpc_temp_compensation = ar9287_olpc_temp_compensation; 112 sc->sc_ini = &ar9287_1_1_ini; 113 sc->sc_serdes = &ar9280_2_0_serdes; 114 115 return ar5008_attach(sc); 116 } 117 118 Static void 119 ar9287_setup(struct athn_softc *sc) 120 { 121 const struct ar9287_eeprom *eep = sc->sc_eep; 122 123 /* Determine if open loop power control should be used. */ 124 if (eep->baseEepHeader.openLoopPwrCntl) 125 sc->sc_flags |= ATHN_FLAG_OLPC; 126 127 sc->sc_rx_gain = &ar9287_1_1_rx_gain; 128 sc->sc_tx_gain = &ar9287_1_1_tx_gain; 129 } 130 131 Static void 132 ar9287_swap_rom(struct athn_softc *sc) 133 { 134 struct ar9287_eeprom *eep = sc->sc_eep; 135 int i; 136 137 eep->modalHeader.antCtrlCommon = 138 bswap32(eep->modalHeader.antCtrlCommon); 139 140 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 141 eep->modalHeader.antCtrlChain[i] = 142 bswap32(eep->modalHeader.antCtrlChain[i]); 143 } 144 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 145 eep->modalHeader.spurChans[i].spurChan = 146 bswap16(eep->modalHeader.spurChans[i].spurChan); 147 } 148 } 149 150 Static const struct ar_spur_chan * 151 ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz) 152 { 153 const struct ar9287_eeprom *eep = sc->sc_eep; 154 155 KASSERT(is2ghz); 156 return eep->modalHeader.spurChans; 157 } 158 159 Static void 160 ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 161 struct ieee80211_channel *extc) 162 { 163 const struct ar9287_eeprom *eep = sc->sc_eep; 164 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 165 uint32_t reg, offset; 166 int i; 167 168 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 169 170 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 171 offset = i * 0x1000; 172 173 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 174 modal->antCtrlChain[i]); 175 176 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 177 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 178 modal->iqCalICh[i]); 179 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 180 modal->iqCalQCh[i]); 181 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 182 183 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 184 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 185 modal->bswMargin[i]); 186 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 187 modal->bswAtten[i]); 188 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 189 190 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 191 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 192 modal->rxTxMarginCh[i]); 193 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 194 modal->txRxAttenCh[i]); 195 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 196 } 197 198 reg = AR_READ(sc, AR_PHY_SETTLING); 199 #ifndef IEEE80211_NO_HT 200 if (extc != NULL) 201 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 202 else 203 #endif 204 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 205 AR_WRITE(sc, AR_PHY_SETTLING, reg); 206 207 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 208 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 209 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 210 211 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 212 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 213 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 214 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 215 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 216 217 reg = AR_READ(sc, AR_PHY_RF_CTL3); 218 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 219 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 220 221 reg = AR_READ(sc, AR_PHY_CCA(0)); 222 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 223 AR_WRITE(sc, AR_PHY_CCA(0), reg); 224 225 reg = AR_READ(sc, AR_PHY_EXT_CCA0); 226 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 227 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 228 229 reg = AR_READ(sc, AR9287_AN_RF2G3_CH0); 230 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 231 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 232 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 233 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 234 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 235 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 236 AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg); 237 AR_WRITE_BARRIER(sc); 238 DELAY(100); 239 240 reg = AR_READ(sc, AR9287_AN_RF2G3_CH1); 241 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 242 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 243 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 244 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 245 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 246 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 247 AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg); 248 AR_WRITE_BARRIER(sc); 249 DELAY(100); 250 251 reg = AR_READ(sc, AR_PHY_RF_CTL2); 252 reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); 253 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 254 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 255 256 reg = AR_READ(sc, AR9287_AN_TOP2); 257 reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); 258 AR_WRITE(sc, AR9287_AN_TOP2, reg); 259 AR_WRITE_BARRIER(sc); 260 DELAY(100); 261 } 262 263 Static void 264 ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 265 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries, 266 uint8_t *pdadcs) 267 { 268 const struct ar9287_eeprom *eep = sc->sc_eep; 269 const struct ar9287_cal_data_per_freq *pierdata; 270 const uint8_t *pierfreq; 271 struct athn_pier lopier, hipier; 272 int16_t delta; 273 uint8_t fbin; 274 int i, lo, hi, npiers; 275 276 pierfreq = eep->calFreqPier2G; 277 pierdata = (const struct ar9287_cal_data_per_freq *) 278 eep->calPierData2G[chain]; 279 npiers = AR9287_NUM_2G_CAL_PIERS; 280 281 /* Find channel in ROM pier table. */ 282 fbin = athn_chan2fbin(c); 283 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 284 285 lopier.fbin = pierfreq[lo]; 286 hipier.fbin = pierfreq[hi]; 287 for (i = 0; i < nxpdgains; i++) { 288 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 289 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 290 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 291 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 292 } 293 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 294 AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 295 296 delta = (eep->baseEepHeader.pwrTableOffset - 297 AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */ 298 if (delta != 0) { 299 /* Shift the PDADC table to start at the new offset. */ 300 /* XXX Our padding value differs from Linux. */ 301 for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 302 pdadcs[i] = pdadcs[MIN(i + delta, 303 AR_NUM_PDADC_VALUES - 1)]; 304 } 305 } 306 307 Static void 308 ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c, 309 int chain, int8_t *pwr) 310 { 311 const struct ar9287_eeprom *eep = sc->sc_eep; 312 const struct ar_cal_data_per_freq_olpc *pierdata; 313 const uint8_t *pierfreq; 314 uint8_t fbin; 315 int lo, hi, npiers; 316 317 pierfreq = eep->calFreqPier2G; 318 pierdata = (const struct ar_cal_data_per_freq_olpc *) 319 eep->calPierData2G[chain]; 320 npiers = AR9287_NUM_2G_CAL_PIERS; 321 322 /* Find channel in ROM pier table. */ 323 fbin = athn_chan2fbin(c); 324 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 325 #if 0 326 *pwr = athn_interpolate(fbin, 327 pierfreq[lo], pierdata[lo].pwrPdg[0][0], 328 pierfreq[hi], pierdata[hi].pwrPdg[0][0]); 329 #else 330 *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2; 331 #endif 332 } 333 334 Static void 335 ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 336 { 337 const struct ar9287_eeprom *eep = sc->sc_eep; 338 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 339 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 340 uint8_t xpdgains[AR9287_NUM_PD_GAINS]; 341 int8_t txpower; 342 uint8_t overlap; 343 uint32_t reg, offset; 344 int i, j, nxpdgains; 345 346 if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) { 347 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 348 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 349 } 350 else 351 overlap = eep->modalHeader.pdGainOverlap; 352 353 if (sc->sc_flags & ATHN_FLAG_OLPC) { 354 /* XXX not here. */ 355 sc->sc_pdadc = 356 ((const struct ar_cal_data_per_freq_olpc *) 357 eep->calPierData2G[0])->vpdPdg[0][0]; 358 } 359 360 nxpdgains = 0; 361 memset(xpdgains, 0, sizeof(xpdgains)); 362 for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 363 if (nxpdgains >= AR9287_NUM_PD_GAINS) 364 break; /* Can't happen. */ 365 if (eep->modalHeader.xpdGain & (1 << i)) 366 xpdgains[nxpdgains++] = i; 367 } 368 reg = AR_READ(sc, AR_PHY_TPCRG1); 369 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 370 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 371 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 372 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 373 AR_WRITE_BARRIER(sc); 374 375 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 376 if (!(sc->sc_txchainmask & (1 << i))) 377 continue; 378 379 offset = i * 0x1000; 380 381 if (sc->sc_flags & ATHN_FLAG_OLPC) { 382 ar9287_olpc_get_pdgain(sc, c, i, &txpower); 383 384 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0); 385 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 386 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg); 387 388 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1); 389 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 390 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg); 391 392 /* NB: txpower is in half dB. */ 393 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset); 394 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower); 395 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg); 396 397 AR_WRITE_BARRIER(sc); 398 continue; /* That's it for open loop mode. */ 399 } 400 401 /* Closed loop power control. */ 402 ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap, 403 boundaries, pdadcs); 404 405 /* Write boundaries. */ 406 if (i == 0) { 407 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, 408 overlap); 409 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, 410 boundaries[0]); 411 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, 412 boundaries[1]); 413 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, 414 boundaries[2]); 415 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, 416 boundaries[3]); 417 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg); 418 } 419 /* Write PDADC values. */ 420 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) { 421 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j, 422 pdadcs[j + 0] << 0 | 423 pdadcs[j + 1] << 8 | 424 pdadcs[j + 2] << 16 | 425 pdadcs[j + 3] << 24); 426 } 427 AR_WRITE_BARRIER(sc); 428 } 429 } 430 431 Static void 432 ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 433 struct ieee80211_channel *extc) 434 { 435 const struct ar9287_eeprom *eep = sc->sc_eep; 436 #ifdef notyet 437 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 438 #endif 439 uint8_t tpow_cck[4], tpow_ofdm[4]; 440 #ifndef IEEE80211_NO_HT 441 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 442 uint8_t tpow_ht20[8], tpow_ht40[8]; 443 uint8_t ht40inc; 444 #endif 445 int16_t pwr = 0, power[ATHN_POWER_COUNT]; 446 int i; 447 448 ar9287_set_power_calib(sc, c); 449 450 #ifdef notyet 451 /* Compute transmit power reduction due to antenna gain. */ 452 uint16_t max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); 453 /* XXX */ 454 #endif 455 456 /* 457 * Reduce scaled power by number of active chains to get per-chain 458 * transmit power level. 459 */ 460 if (sc->sc_ntxchains == 2) 461 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN; 462 if (pwr < 0) 463 pwr = 0; 464 465 /* Get CCK target powers. */ 466 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 467 AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 468 469 /* Get OFDM target powers. */ 470 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 471 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 472 473 #ifndef IEEE80211_NO_HT 474 /* Get HT-20 target powers. */ 475 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 476 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20); 477 478 if (extc != NULL) { 479 /* Get HT-40 target powers. */ 480 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 481 eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS, 482 tpow_ht40); 483 484 /* Get secondary channel CCK target powers. */ 485 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 486 eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS, 487 tpow_cck_ext); 488 489 /* Get secondary channel OFDM target powers. */ 490 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 491 eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS, 492 tpow_ofdm_ext); 493 } 494 #endif 495 496 memset(power, 0, sizeof(power)); 497 /* Shuffle target powers accross transmit rates. */ 498 power[ATHN_POWER_OFDM6 ] = 499 power[ATHN_POWER_OFDM9 ] = 500 power[ATHN_POWER_OFDM12 ] = 501 power[ATHN_POWER_OFDM18 ] = 502 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 503 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 504 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 505 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 506 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 507 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 508 power[ATHN_POWER_CCK2_LP ] = 509 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 510 power[ATHN_POWER_CCK55_LP] = 511 power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 512 power[ATHN_POWER_CCK11_LP] = 513 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 514 #ifndef IEEE80211_NO_HT 515 for (i = 0; i < nitems(tpow_ht20); i++) 516 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 517 if (extc != NULL) { 518 /* Correct PAR difference between HT40 and HT20/Legacy. */ 519 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) 520 ht40inc = modal->ht40PowerIncForPdadc; 521 else 522 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 523 for (i = 0; i < nitems(tpow_ht40); i++) 524 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 525 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 526 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 527 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 528 if (IEEE80211_IS_CHAN_2GHZ(c)) 529 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0]; 530 } 531 #endif 532 533 for (i = 0; i < ATHN_POWER_COUNT; i++) { 534 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 535 if (power[i] > AR_MAX_RATE_POWER) 536 power[i] = AR_MAX_RATE_POWER; 537 } 538 /* Commit transmit power values to hardware. */ 539 ar5008_write_txpower(sc, power); 540 } 541 542 Static void 543 ar9287_olpc_init(struct athn_softc *sc) 544 { 545 uint32_t reg; 546 547 AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 548 549 reg = AR_READ(sc, AR9287_AN_TXPC0); 550 reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE, 551 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 552 AR_WRITE(sc, AR9287_AN_TXPC0, reg); 553 AR_WRITE_BARRIER(sc); 554 DELAY(100); 555 } 556 557 Static void 558 ar9287_olpc_temp_compensation(struct athn_softc *sc) 559 { 560 const struct ar9287_eeprom *eep = sc->sc_eep; 561 int8_t pdadc, slope, tcomp; 562 uint32_t reg; 563 564 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4); 565 pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 566 DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc); 567 568 if (sc->sc_pdadc == 0 || pdadc == 0) 569 return; /* No frames transmitted yet. */ 570 571 /* Compute Tx gain temperature compensation. */ 572 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) 573 slope = eep->baseEepHeader.tempSensSlope; 574 else 575 slope = 0; 576 if (slope != 0) /* Prevents division by zero. */ 577 tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope; 578 else 579 tcomp = 0; 580 DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp); 581 582 /* Write compensation value for both Tx chains. */ 583 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11); 584 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 585 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg); 586 587 reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11); 588 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 589 AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg); 590 AR_WRITE_BARRIER(sc); 591 } 592 593 PUBLIC void 594 ar9287_1_3_enable_async_fifo(struct athn_softc *sc) 595 { 596 597 /* Enable ASYNC FIFO. */ 598 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 599 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 600 AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 601 AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 602 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 603 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 604 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 605 AR_WRITE_BARRIER(sc); 606 } 607 608 PUBLIC void 609 ar9287_1_3_setup_async_fifo(struct athn_softc *sc) 610 { 611 uint32_t reg; 612 613 /* 614 * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is 615 * enabled, so the following counters have to be changed. 616 */ 617 AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 618 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 619 AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 620 621 AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 622 AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 623 624 AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER, 625 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 626 627 reg = AR_READ(sc, AR_AHB_MODE); 628 reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 629 AR_WRITE(sc, AR_AHB_MODE, reg); 630 631 AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 632 AR_WRITE_BARRIER(sc); 633 } 634
Indexes created Fri Sep 26 08:10:20 GMT 2025