ath.c revision 1.32.2.10
1 1.32.2.10 skrll /* $NetBSD: ath.c,v 1.32.2.10 2005/03/04 16:41:26 skrll Exp $ */ 2 1.32.2.2 skrll 3 1.32.2.2 skrll /*- 4 1.32.2.2 skrll * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 5 1.32.2.2 skrll * All rights reserved. 6 1.32.2.2 skrll * 7 1.32.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.32.2.2 skrll * modification, are permitted provided that the following conditions 9 1.32.2.2 skrll * are met: 10 1.32.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.32.2.2 skrll * notice, this list of conditions and the following disclaimer, 12 1.32.2.2 skrll * without modification. 13 1.32.2.2 skrll * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 1.32.2.2 skrll * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 1.32.2.2 skrll * redistribution must be conditioned upon including a substantially 16 1.32.2.2 skrll * similar Disclaimer requirement for further binary redistribution. 17 1.32.2.2 skrll * 3. Neither the names of the above-listed copyright holders nor the names 18 1.32.2.2 skrll * of any contributors may be used to endorse or promote products derived 19 1.32.2.2 skrll * from this software without specific prior written permission. 20 1.32.2.2 skrll * 21 1.32.2.2 skrll * Alternatively, this software may be distributed under the terms of the 22 1.32.2.2 skrll * GNU General Public License ("GPL") version 2 as published by the Free 23 1.32.2.2 skrll * Software Foundation. 24 1.32.2.2 skrll * 25 1.32.2.2 skrll * NO WARRANTY 26 1.32.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 1.32.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 1.32.2.2 skrll * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 1.32.2.2 skrll * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 1.32.2.2 skrll * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 1.32.2.2 skrll * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.32.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.32.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 1.32.2.2 skrll * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.32.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 1.32.2.2 skrll * THE POSSIBILITY OF SUCH DAMAGES. 37 1.32.2.2 skrll */ 38 1.32.2.2 skrll 39 1.32.2.2 skrll #include <sys/cdefs.h> 40 1.32.2.2 skrll #ifdef __FreeBSD__ 41 1.32.2.2 skrll __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.54 2004/04/05 04:42:42 sam Exp $"); 42 1.32.2.2 skrll #endif 43 1.32.2.2 skrll #ifdef __NetBSD__ 44 1.32.2.10 skrll __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.32.2.10 2005/03/04 16:41:26 skrll Exp $"); 45 1.32.2.2 skrll #endif 46 1.32.2.2 skrll 47 1.32.2.2 skrll /* 48 1.32.2.2 skrll * Driver for the Atheros Wireless LAN controller. 49 1.32.2.2 skrll * 50 1.32.2.2 skrll * This software is derived from work of Atsushi Onoe; his contribution 51 1.32.2.2 skrll * is greatly appreciated. 52 1.32.2.2 skrll */ 53 1.32.2.2 skrll 54 1.32.2.2 skrll #include "opt_inet.h" 55 1.32.2.2 skrll 56 1.32.2.2 skrll #ifdef __NetBSD__ 57 1.32.2.2 skrll #include "bpfilter.h" 58 1.32.2.2 skrll #endif /* __NetBSD__ */ 59 1.32.2.2 skrll 60 1.32.2.2 skrll #include <sys/param.h> 61 1.32.2.10 skrll #include <sys/systm.h> 62 1.32.2.2 skrll #include <sys/types.h> 63 1.32.2.2 skrll #include <sys/sysctl.h> 64 1.32.2.10 skrll #include <sys/mbuf.h> 65 1.32.2.2 skrll #include <sys/malloc.h> 66 1.32.2.2 skrll #include <sys/lock.h> 67 1.32.2.2 skrll #ifdef __FreeBSD__ 68 1.32.2.2 skrll #include <sys/mutex.h> 69 1.32.2.2 skrll #endif 70 1.32.2.2 skrll #include <sys/kernel.h> 71 1.32.2.2 skrll #include <sys/socket.h> 72 1.32.2.2 skrll #include <sys/sockio.h> 73 1.32.2.2 skrll #include <sys/errno.h> 74 1.32.2.2 skrll #include <sys/callout.h> 75 1.32.2.2 skrll #ifdef __FreeBSD__ 76 1.32.2.2 skrll #include <sys/bus.h> 77 1.32.2.2 skrll #else 78 1.32.2.2 skrll #include <machine/bus.h> 79 1.32.2.2 skrll #endif 80 1.32.2.2 skrll #include <sys/endian.h> 81 1.32.2.2 skrll 82 1.32.2.2 skrll #include <machine/bus.h> 83 1.32.2.10 skrll 84 1.32.2.2 skrll #include <net/if.h> 85 1.32.2.2 skrll #include <net/if_dl.h> 86 1.32.2.2 skrll #include <net/if_media.h> 87 1.32.2.2 skrll #include <net/if_arp.h> 88 1.32.2.2 skrll #ifdef __FreeBSD__ 89 1.32.2.2 skrll #include <net/ethernet.h> 90 1.32.2.2 skrll #else 91 1.32.2.2 skrll #include <net/if_ether.h> 92 1.32.2.2 skrll #endif 93 1.32.2.2 skrll #include <net/if_llc.h> 94 1.32.2.2 skrll 95 1.32.2.2 skrll #include <net80211/ieee80211_var.h> 96 1.32.2.2 skrll #include <net80211/ieee80211_compat.h> 97 1.32.2.2 skrll 98 1.32.2.2 skrll #if NBPFILTER > 0 99 1.32.2.2 skrll #include <net/bpf.h> 100 1.32.2.2 skrll #endif 101 1.32.2.2 skrll 102 1.32.2.2 skrll #ifdef INET 103 1.32.2.10 skrll #include <netinet/in.h> 104 1.32.2.2 skrll #endif 105 1.32.2.2 skrll 106 1.32.2.2 skrll #include <dev/ic/athcompat.h> 107 1.32.2.2 skrll 108 1.32.2.2 skrll #define AR_DEBUG 109 1.32.2.2 skrll #ifdef __FreeBSD__ 110 1.32.2.2 skrll #include <dev/ath/if_athvar.h> 111 1.32.2.2 skrll #include <contrib/dev/ath/ah_desc.h> 112 1.32.2.2 skrll #else 113 1.32.2.2 skrll #include <dev/ic/athvar.h> 114 1.32.2.2 skrll #include <../contrib/sys/dev/ic/athhal_desc.h> 115 1.32.2.2 skrll #endif 116 1.32.2.2 skrll 117 1.32.2.10 skrll /* unaligned little endian access */ 118 1.32.2.2 skrll #define LE_READ_2(p) \ 119 1.32.2.2 skrll ((u_int16_t) \ 120 1.32.2.2 skrll ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 121 1.32.2.2 skrll #define LE_READ_4(p) \ 122 1.32.2.2 skrll ((u_int32_t) \ 123 1.32.2.2 skrll ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 124 1.32.2.2 skrll (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 125 1.32.2.2 skrll 126 1.32.2.2 skrll #ifdef __FreeBSD__ 127 1.32.2.2 skrll static void ath_init(void *); 128 1.32.2.2 skrll #else 129 1.32.2.2 skrll static int ath_init(struct ifnet *); 130 1.32.2.2 skrll #endif 131 1.32.2.2 skrll static int ath_init1(struct ath_softc *); 132 1.32.2.2 skrll static int ath_intr1(struct ath_softc *); 133 1.32.2.8 skrll static void ath_stop(struct ifnet *, int); 134 1.32.2.2 skrll static void ath_start(struct ifnet *); 135 1.32.2.2 skrll static void ath_reset(struct ath_softc *); 136 1.32.2.2 skrll static int ath_media_change(struct ifnet *); 137 1.32.2.2 skrll static void ath_watchdog(struct ifnet *); 138 1.32.2.2 skrll static int ath_ioctl(struct ifnet *, u_long, caddr_t); 139 1.32.2.2 skrll static void ath_fatal_proc(void *, int); 140 1.32.2.2 skrll static void ath_rxorn_proc(void *, int); 141 1.32.2.2 skrll static void ath_bmiss_proc(void *, int); 142 1.32.2.2 skrll static void ath_initkeytable(struct ath_softc *); 143 1.32.2.2 skrll static void ath_mode_init(struct ath_softc *); 144 1.32.2.2 skrll static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 145 1.32.2.3 skrll static void ath_beacon_proc(struct ath_softc *, int); 146 1.32.2.2 skrll static void ath_beacon_free(struct ath_softc *); 147 1.32.2.2 skrll static void ath_beacon_config(struct ath_softc *); 148 1.32.2.2 skrll static int ath_desc_alloc(struct ath_softc *); 149 1.32.2.2 skrll static void ath_desc_free(struct ath_softc *); 150 1.32.2.2 skrll static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 151 1.32.2.2 skrll static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 152 1.32.2.2 skrll static void ath_node_copy(struct ieee80211com *, 153 1.32.2.2 skrll struct ieee80211_node *, const struct ieee80211_node *); 154 1.32.2.2 skrll static u_int8_t ath_node_getrssi(struct ieee80211com *, 155 1.32.2.2 skrll struct ieee80211_node *); 156 1.32.2.2 skrll static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 157 1.32.2.2 skrll static void ath_rx_proc(void *, int); 158 1.32.2.2 skrll static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 159 1.32.2.2 skrll struct ath_buf *, struct mbuf *); 160 1.32.2.2 skrll static void ath_tx_proc(void *, int); 161 1.32.2.2 skrll static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 162 1.32.2.2 skrll static void ath_draintxq(struct ath_softc *); 163 1.32.2.2 skrll static void ath_stoprecv(struct ath_softc *); 164 1.32.2.2 skrll static int ath_startrecv(struct ath_softc *); 165 1.32.2.2 skrll static void ath_next_scan(void *); 166 1.32.2.2 skrll static void ath_calibrate(void *); 167 1.32.2.2 skrll static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 168 1.32.2.2 skrll static void ath_newassoc(struct ieee80211com *, 169 1.32.2.2 skrll struct ieee80211_node *, int); 170 1.32.2.2 skrll static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor, 171 1.32.2.2 skrll HAL_BOOL xchanmode); 172 1.32.2.2 skrll 173 1.32.2.2 skrll static int ath_rate_setup(struct ath_softc *sc, u_int mode); 174 1.32.2.2 skrll static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 175 1.32.2.2 skrll static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 176 1.32.2.2 skrll static void ath_rate_ctl(void *, struct ieee80211_node *); 177 1.32.2.3 skrll static void ath_recv_mgmt(struct ieee80211com *, struct mbuf *, 178 1.32.2.3 skrll struct ieee80211_node *, int, int, u_int32_t); 179 1.32.2.2 skrll 180 1.32.2.2 skrll #ifdef __NetBSD__ 181 1.32.2.2 skrll int ath_enable(struct ath_softc *); 182 1.32.2.2 skrll void ath_disable(struct ath_softc *); 183 1.32.2.2 skrll void ath_power(int, void *); 184 1.32.2.2 skrll #endif 185 1.32.2.2 skrll 186 1.32.2.2 skrll #ifdef __FreeBSD__ 187 1.32.2.2 skrll SYSCTL_DECL(_hw_ath); 188 1.32.2.2 skrll /* XXX validate sysctl values */ 189 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 190 1.32.2.2 skrll 0, "channel dwell time (ms) for AP/station scanning"); 191 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 192 1.32.2.2 skrll 0, "chip calibration interval (secs)"); 193 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 194 1.32.2.2 skrll 0, "enable/disable outdoor operation"); 195 1.32.2.2 skrll TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 196 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 197 1.32.2.2 skrll 0, "country code"); 198 1.32.2.2 skrll TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 199 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 200 1.32.2.2 skrll 0, "regulatory domain"); 201 1.32.2.2 skrll #endif /* __FreeBSD__ */ 202 1.32.2.2 skrll 203 1.32.2.2 skrll #ifdef __NetBSD__ 204 1.32.2.2 skrll static int ath_dwelltime_nodenum, ath_calibrate_nodenum, ath_outdoor_nodenum, 205 1.32.2.2 skrll ath_countrycode_nodenum, ath_regdomain_nodenum, ath_debug_nodenum; 206 1.32.2.2 skrll #endif /* __NetBSD__ */ 207 1.32.2.2 skrll 208 1.32.2.2 skrll static int ath_dwelltime = 200; /* 5 channels/second */ 209 1.32.2.2 skrll static int ath_calinterval = 30; /* calibrate every 30 secs */ 210 1.32.2.2 skrll static int ath_outdoor = AH_TRUE; /* outdoor operation */ 211 1.32.2.2 skrll static int ath_xchanmode = AH_TRUE; /* enable extended channels */ 212 1.32.2.2 skrll static int ath_countrycode = CTRY_DEFAULT; /* country code */ 213 1.32.2.2 skrll static int ath_regdomain = 0; /* regulatory domain */ 214 1.32.2.2 skrll 215 1.32.2.2 skrll #ifdef AR_DEBUG 216 1.32.2.2 skrll int ath_debug = 0; 217 1.32.2.2 skrll #ifdef __FreeBSD__ 218 1.32.2.2 skrll SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 219 1.32.2.2 skrll 0, "control debugging printfs"); 220 1.32.2.2 skrll TUNABLE_INT("hw.ath.debug", &ath_debug); 221 1.32.2.2 skrll #endif /* __FreeBSD__ */ 222 1.32.2.2 skrll #define IFF_DUMPPKTS(_ifp, _m) \ 223 1.32.2.2 skrll ((ath_debug & _m) || \ 224 1.32.2.2 skrll ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 225 1.32.2.2 skrll static void ath_printrxbuf(struct ath_buf *bf, int); 226 1.32.2.2 skrll static void ath_printtxbuf(struct ath_buf *bf, int); 227 1.32.2.2 skrll enum { 228 1.32.2.2 skrll ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 229 1.32.2.2 skrll ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 230 1.32.2.2 skrll ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 231 1.32.2.2 skrll ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 232 1.32.2.2 skrll ATH_DEBUG_RATE = 0x00000010, /* rate control */ 233 1.32.2.2 skrll ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 234 1.32.2.2 skrll ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 235 1.32.2.2 skrll ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 236 1.32.2.2 skrll ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 237 1.32.2.2 skrll ATH_DEBUG_INTR = 0x00001000, /* ISR */ 238 1.32.2.2 skrll ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 239 1.32.2.2 skrll ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 240 1.32.2.2 skrll ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 241 1.32.2.2 skrll ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 242 1.32.2.2 skrll ATH_DEBUG_ANY = 0xffffffff 243 1.32.2.2 skrll }; 244 1.32.2.2 skrll #define DPRINTF(_m,X) if (ath_debug & (_m)) printf X 245 1.32.2.2 skrll #else 246 1.32.2.2 skrll #define IFF_DUMPPKTS(_ifp, _m) \ 247 1.32.2.2 skrll (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 248 1.32.2.2 skrll #define DPRINTF(_m, X) 249 1.32.2.2 skrll #endif 250 1.32.2.2 skrll 251 1.32.2.2 skrll #ifdef __NetBSD__ 252 1.32.2.2 skrll int 253 1.32.2.2 skrll ath_activate(struct device *self, enum devact act) 254 1.32.2.2 skrll { 255 1.32.2.2 skrll struct ath_softc *sc = (struct ath_softc *)self; 256 1.32.2.2 skrll int rv = 0, s; 257 1.32.2.2 skrll 258 1.32.2.2 skrll s = splnet(); 259 1.32.2.2 skrll switch (act) { 260 1.32.2.2 skrll case DVACT_ACTIVATE: 261 1.32.2.2 skrll rv = EOPNOTSUPP; 262 1.32.2.2 skrll break; 263 1.32.2.2 skrll case DVACT_DEACTIVATE: 264 1.32.2.2 skrll if_deactivate(&sc->sc_ic.ic_if); 265 1.32.2.2 skrll break; 266 1.32.2.2 skrll } 267 1.32.2.2 skrll splx(s); 268 1.32.2.2 skrll return rv; 269 1.32.2.2 skrll } 270 1.32.2.2 skrll 271 1.32.2.2 skrll int 272 1.32.2.2 skrll ath_enable(struct ath_softc *sc) 273 1.32.2.2 skrll { 274 1.32.2.2 skrll if (ATH_IS_ENABLED(sc) == 0) { 275 1.32.2.2 skrll if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 276 1.32.2.2 skrll printf("%s: device enable failed\n", 277 1.32.2.2 skrll sc->sc_dev.dv_xname); 278 1.32.2.2 skrll return (EIO); 279 1.32.2.2 skrll } 280 1.32.2.2 skrll sc->sc_flags |= ATH_ENABLED; 281 1.32.2.2 skrll } 282 1.32.2.2 skrll return (0); 283 1.32.2.2 skrll } 284 1.32.2.2 skrll 285 1.32.2.2 skrll void 286 1.32.2.2 skrll ath_disable(struct ath_softc *sc) 287 1.32.2.2 skrll { 288 1.32.2.2 skrll if (!ATH_IS_ENABLED(sc)) 289 1.32.2.2 skrll return; 290 1.32.2.2 skrll if (sc->sc_disable != NULL) 291 1.32.2.2 skrll (*sc->sc_disable)(sc); 292 1.32.2.2 skrll sc->sc_flags &= ~ATH_ENABLED; 293 1.32.2.2 skrll } 294 1.32.2.2 skrll 295 1.32.2.2 skrll static int 296 1.32.2.2 skrll sysctl_ath_verify(SYSCTLFN_ARGS) 297 1.32.2.2 skrll { 298 1.32.2.2 skrll int error, t; 299 1.32.2.2 skrll struct sysctlnode node; 300 1.32.2.2 skrll 301 1.32.2.2 skrll node = *rnode; 302 1.32.2.2 skrll t = *(int*)rnode->sysctl_data; 303 1.32.2.2 skrll node.sysctl_data = &t; 304 1.32.2.2 skrll error = sysctl_lookup(SYSCTLFN_CALL(&node)); 305 1.32.2.2 skrll if (error || newp == NULL) 306 1.32.2.2 skrll return (error); 307 1.32.2.2 skrll 308 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: t = %d, nodenum = %d, rnodenum = %d\n", 309 1.32.2.2 skrll __func__, t, node.sysctl_num, rnode->sysctl_num)); 310 1.32.2.2 skrll 311 1.32.2.2 skrll if (node.sysctl_num == ath_dwelltime_nodenum) { 312 1.32.2.2 skrll if (t <= 0) 313 1.32.2.2 skrll return (EINVAL); 314 1.32.2.2 skrll } else if (node.sysctl_num == ath_calibrate_nodenum) { 315 1.32.2.2 skrll if (t <= 0) 316 1.32.2.2 skrll return (EINVAL); 317 1.32.2.2 skrll #ifdef AR_DEBUG 318 1.32.2.2 skrll } else if (node.sysctl_num == ath_debug_nodenum) { 319 1.32.2.5 skrll ; /* Accept any vaule */ 320 1.32.2.2 skrll #endif /* AR_DEBUG */ 321 1.32.2.2 skrll } else 322 1.32.2.2 skrll return (EINVAL); 323 1.32.2.2 skrll 324 1.32.2.2 skrll *(int*)rnode->sysctl_data = t; 325 1.32.2.2 skrll 326 1.32.2.2 skrll return (0); 327 1.32.2.2 skrll } 328 1.32.2.2 skrll 329 1.32.2.2 skrll /* 330 1.32.2.2 skrll * Setup sysctl(3) MIB, ath.*. 331 1.32.2.2 skrll * 332 1.32.2.2 skrll * TBD condition CTLFLAG_PERMANENT on being an LKM or not 333 1.32.2.2 skrll */ 334 1.32.2.2 skrll SYSCTL_SETUP(sysctl_ath, "sysctl ath subtree setup") 335 1.32.2.2 skrll { 336 1.32.2.2 skrll int rc, ath_node_num; 337 1.32.2.2 skrll struct sysctlnode *node; 338 1.32.2.2 skrll 339 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, NULL, 340 1.32.2.2 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 341 1.32.2.2 skrll NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 342 1.32.2.2 skrll goto err; 343 1.32.2.2 skrll 344 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 345 1.32.2.2 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ath", 346 1.32.2.2 skrll SYSCTL_DESCR("ath information and options"), 347 1.32.2.2 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 348 1.32.2.2 skrll goto err; 349 1.32.2.2 skrll 350 1.32.2.2 skrll ath_node_num = node->sysctl_num; 351 1.32.2.2 skrll 352 1.32.2.2 skrll /* channel dwell time (ms) for AP/station scanning */ 353 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 354 1.32.2.2 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 355 1.32.2.2 skrll CTLTYPE_INT, "dwell", 356 1.32.2.2 skrll SYSCTL_DESCR("Channel dwell time (ms) for AP/station scanning"), 357 1.32.2.2 skrll sysctl_ath_verify, 0, &ath_dwelltime, 358 1.32.2.2 skrll 0, CTL_HW, ath_node_num, CTL_CREATE, 359 1.32.2.2 skrll CTL_EOL)) != 0) 360 1.32.2.2 skrll goto err; 361 1.32.2.2 skrll 362 1.32.2.2 skrll ath_dwelltime_nodenum = node->sysctl_num; 363 1.32.2.2 skrll 364 1.32.2.2 skrll /* chip calibration interval (secs) */ 365 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 366 1.32.2.2 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 367 1.32.2.2 skrll CTLTYPE_INT, "calibrate", 368 1.32.2.2 skrll SYSCTL_DESCR("Chip calibration interval (secs)"), sysctl_ath_verify, 369 1.32.2.2 skrll 0, &ath_calinterval, 0, CTL_HW, 370 1.32.2.2 skrll ath_node_num, CTL_CREATE, CTL_EOL)) != 0) 371 1.32.2.2 skrll goto err; 372 1.32.2.2 skrll 373 1.32.2.2 skrll ath_calibrate_nodenum = node->sysctl_num; 374 1.32.2.2 skrll 375 1.32.2.2 skrll /* enable/disable outdoor operation */ 376 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 377 1.32.2.4 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 378 1.32.2.2 skrll "outdoor", SYSCTL_DESCR("Enable/disable outdoor operation"), 379 1.32.2.2 skrll NULL, 0, &ath_outdoor, 0, 380 1.32.2.2 skrll CTL_HW, ath_node_num, CTL_CREATE, 381 1.32.2.2 skrll CTL_EOL)) != 0) 382 1.32.2.2 skrll goto err; 383 1.32.2.2 skrll 384 1.32.2.2 skrll ath_outdoor_nodenum = node->sysctl_num; 385 1.32.2.2 skrll 386 1.32.2.2 skrll /* country code */ 387 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 388 1.32.2.4 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 389 1.32.2.2 skrll "countrycode", SYSCTL_DESCR("Country code"), 390 1.32.2.2 skrll NULL, 0, &ath_countrycode, 0, 391 1.32.2.2 skrll CTL_HW, ath_node_num, CTL_CREATE, 392 1.32.2.2 skrll CTL_EOL)) != 0) 393 1.32.2.2 skrll goto err; 394 1.32.2.2 skrll 395 1.32.2.2 skrll ath_countrycode_nodenum = node->sysctl_num; 396 1.32.2.2 skrll 397 1.32.2.2 skrll /* regulatory domain */ 398 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 399 1.32.2.2 skrll CTLFLAG_PERMANENT|CTLFLAG_READONLY, CTLTYPE_INT, 400 1.32.2.2 skrll "regdomain", SYSCTL_DESCR("Regulatory domain"), 401 1.32.2.2 skrll NULL, 0, &ath_regdomain, 0, 402 1.32.2.2 skrll CTL_HW, ath_node_num, CTL_CREATE, 403 1.32.2.2 skrll CTL_EOL)) != 0) 404 1.32.2.2 skrll goto err; 405 1.32.2.2 skrll 406 1.32.2.2 skrll ath_regdomain_nodenum = node->sysctl_num; 407 1.32.2.2 skrll 408 1.32.2.2 skrll #ifdef AR_DEBUG 409 1.32.2.2 skrll 410 1.32.2.2 skrll /* control debugging printfs */ 411 1.32.2.2 skrll if ((rc = sysctl_createv(clog, 0, NULL, &node, 412 1.32.2.2 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 413 1.32.2.2 skrll "debug", SYSCTL_DESCR("Enable/disable ath debugging output"), 414 1.32.2.2 skrll sysctl_ath_verify, 0, &ath_debug, 0, 415 1.32.2.2 skrll CTL_HW, ath_node_num, CTL_CREATE, 416 1.32.2.2 skrll CTL_EOL)) != 0) 417 1.32.2.2 skrll goto err; 418 1.32.2.2 skrll 419 1.32.2.2 skrll ath_debug_nodenum = node->sysctl_num; 420 1.32.2.2 skrll 421 1.32.2.2 skrll #endif /* AR_DEBUG */ 422 1.32.2.2 skrll return; 423 1.32.2.2 skrll err: 424 1.32.2.2 skrll printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 425 1.32.2.2 skrll } 426 1.32.2.2 skrll #endif /* __NetBSD__ */ 427 1.32.2.2 skrll 428 1.32.2.2 skrll int 429 1.32.2.2 skrll ath_attach(u_int16_t devid, struct ath_softc *sc) 430 1.32.2.2 skrll { 431 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 432 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 433 1.32.2.2 skrll struct ath_hal *ah; 434 1.32.2.2 skrll HAL_STATUS status; 435 1.32.2.2 skrll HAL_TXQ_INFO qinfo; 436 1.32.2.2 skrll int error = 0; 437 1.32.2.2 skrll 438 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: devid 0x%x\n", __func__, devid)); 439 1.32.2.2 skrll 440 1.32.2.2 skrll #ifdef __FreeBSD__ 441 1.32.2.2 skrll /* set these up early for if_printf use */ 442 1.32.2.2 skrll if_initname(ifp, device_get_name(sc->sc_dev), 443 1.32.2.2 skrll device_get_unit(sc->sc_dev)); 444 1.32.2.2 skrll #else 445 1.32.2.2 skrll memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 446 1.32.2.2 skrll #endif 447 1.32.2.2 skrll 448 1.32.2.2 skrll ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 449 1.32.2.2 skrll if (ah == NULL) { 450 1.32.2.2 skrll if_printf(ifp, "unable to attach hardware; HAL status %u\n", 451 1.32.2.2 skrll status); 452 1.32.2.2 skrll error = ENXIO; 453 1.32.2.2 skrll goto bad; 454 1.32.2.2 skrll } 455 1.32.2.2 skrll if (ah->ah_abi != HAL_ABI_VERSION) { 456 1.32.2.2 skrll if_printf(ifp, "HAL ABI mismatch detected (0x%x != 0x%x)\n", 457 1.32.2.2 skrll ah->ah_abi, HAL_ABI_VERSION); 458 1.32.2.2 skrll error = ENXIO; 459 1.32.2.2 skrll goto bad; 460 1.32.2.2 skrll } 461 1.32.2.2 skrll if_printf(ifp, "mac %d.%d phy %d.%d", 462 1.32.2.2 skrll ah->ah_macVersion, ah->ah_macRev, 463 1.32.2.2 skrll ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 464 1.32.2.2 skrll if (ah->ah_analog5GhzRev) 465 1.32.2.2 skrll printf(" 5ghz radio %d.%d", 466 1.32.2.2 skrll ah->ah_analog5GhzRev >> 4, ah->ah_analog5GhzRev & 0xf); 467 1.32.2.2 skrll if (ah->ah_analog2GhzRev) 468 1.32.2.2 skrll printf(" 2ghz radio %d.%d", 469 1.32.2.2 skrll ah->ah_analog2GhzRev >> 4, ah->ah_analog2GhzRev & 0xf); 470 1.32.2.2 skrll printf("\n"); 471 1.32.2.2 skrll sc->sc_ah = ah; 472 1.32.2.2 skrll sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 473 1.32.2.2 skrll 474 1.32.2.2 skrll /* 475 1.32.2.2 skrll * Collect the channel list using the default country 476 1.32.2.2 skrll * code and including outdoor channels. The 802.11 layer 477 1.32.2.2 skrll * is resposible for filtering this list based on settings 478 1.32.2.2 skrll * like the phy mode. 479 1.32.2.2 skrll */ 480 1.32.2.2 skrll error = ath_getchannels(sc, ath_countrycode, ath_outdoor, 481 1.32.2.2 skrll ath_xchanmode); 482 1.32.2.2 skrll if (error != 0) 483 1.32.2.2 skrll goto bad; 484 1.32.2.2 skrll /* 485 1.32.2.2 skrll * Copy these back; they are set as a side effect 486 1.32.2.2 skrll * of constructing the channel list. 487 1.32.2.2 skrll */ 488 1.32.2.2 skrll ath_hal_getregdomain(ah, &ath_regdomain); 489 1.32.2.2 skrll ath_hal_getcountrycode(ah, &ath_countrycode); 490 1.32.2.2 skrll 491 1.32.2.2 skrll /* 492 1.32.2.2 skrll * Setup rate tables for all potential media types. 493 1.32.2.2 skrll */ 494 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11A); 495 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11B); 496 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11G); 497 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_TURBO); 498 1.32.2.2 skrll 499 1.32.2.2 skrll error = ath_desc_alloc(sc); 500 1.32.2.2 skrll if (error != 0) { 501 1.32.2.2 skrll if_printf(ifp, "failed to allocate descriptors: %d\n", error); 502 1.32.2.2 skrll goto bad; 503 1.32.2.2 skrll } 504 1.32.2.2 skrll ATH_CALLOUT_INIT(&sc->sc_scan_ch); 505 1.32.2.2 skrll ATH_CALLOUT_INIT(&sc->sc_cal_ch); 506 1.32.2.2 skrll 507 1.32.2.2 skrll #ifdef __FreeBSD__ 508 1.32.2.2 skrll ATH_TXBUF_LOCK_INIT(sc); 509 1.32.2.2 skrll ATH_TXQ_LOCK_INIT(sc); 510 1.32.2.2 skrll #endif 511 1.32.2.2 skrll 512 1.32.2.2 skrll ATH_TASK_INIT(&sc->sc_txtask, ath_tx_proc, sc); 513 1.32.2.2 skrll ATH_TASK_INIT(&sc->sc_rxtask, ath_rx_proc, sc); 514 1.32.2.2 skrll ATH_TASK_INIT(&sc->sc_rxorntask, ath_rxorn_proc, sc); 515 1.32.2.2 skrll ATH_TASK_INIT(&sc->sc_fataltask, ath_fatal_proc, sc); 516 1.32.2.2 skrll ATH_TASK_INIT(&sc->sc_bmisstask, ath_bmiss_proc, sc); 517 1.32.2.2 skrll 518 1.32.2.2 skrll /* 519 1.32.2.2 skrll * For now just pre-allocate one data queue and one 520 1.32.2.2 skrll * beacon queue. Note that the HAL handles resetting 521 1.32.2.2 skrll * them at the needed time. Eventually we'll want to 522 1.32.2.2 skrll * allocate more tx queues for splitting management 523 1.32.2.2 skrll * frames and for QOS support. 524 1.32.2.2 skrll */ 525 1.32.2.2 skrll sc->sc_bhalq = ath_hal_setuptxqueue(ah,HAL_TX_QUEUE_BEACON,NULL); 526 1.32.2.2 skrll if (sc->sc_bhalq == (u_int) -1) { 527 1.32.2.2 skrll if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 528 1.32.2.2 skrll goto bad2; 529 1.32.2.2 skrll } 530 1.32.2.2 skrll 531 1.32.2.2 skrll memset(&qinfo, 0, sizeof(qinfo)); 532 1.32.2.2 skrll qinfo.tqi_subtype = HAL_WME_AC_BE; 533 1.32.2.2 skrll sc->sc_txhalq = ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_DATA, &qinfo); 534 1.32.2.2 skrll if (sc->sc_txhalq == (u_int) -1) { 535 1.32.2.2 skrll if_printf(ifp, "unable to setup a data xmit queue!\n"); 536 1.32.2.2 skrll goto bad2; 537 1.32.2.2 skrll } 538 1.32.2.2 skrll 539 1.32.2.2 skrll ifp->if_softc = sc; 540 1.32.2.2 skrll ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 541 1.32.2.2 skrll ifp->if_start = ath_start; 542 1.32.2.2 skrll ifp->if_watchdog = ath_watchdog; 543 1.32.2.2 skrll ifp->if_ioctl = ath_ioctl; 544 1.32.2.2 skrll ifp->if_init = ath_init; 545 1.32.2.2 skrll #ifdef __FreeBSD__ 546 1.32.2.2 skrll ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 547 1.32.2.2 skrll #else 548 1.32.2.2 skrll #if 0 549 1.32.2.2 skrll ifp->if_stop = ath_stop; /* XXX */ 550 1.32.2.2 skrll #endif 551 1.32.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 552 1.32.2.2 skrll #endif 553 1.32.2.2 skrll 554 1.32.2.2 skrll ic->ic_softc = sc; 555 1.32.2.2 skrll ic->ic_newassoc = ath_newassoc; 556 1.32.2.2 skrll /* XXX not right but it's not used anywhere important */ 557 1.32.2.2 skrll ic->ic_phytype = IEEE80211_T_OFDM; 558 1.32.2.2 skrll ic->ic_opmode = IEEE80211_M_STA; 559 1.32.2.2 skrll ic->ic_caps = IEEE80211_C_WEP /* wep supported */ 560 1.32.2.2 skrll | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 561 1.32.2.2 skrll | IEEE80211_C_HOSTAP /* hostap mode */ 562 1.32.2.2 skrll | IEEE80211_C_MONITOR /* monitor mode */ 563 1.32.2.2 skrll | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 564 1.32.2.2 skrll ; 565 1.32.2.2 skrll 566 1.32.2.2 skrll /* get mac address from hardware */ 567 1.32.2.2 skrll ath_hal_getmac(ah, ic->ic_myaddr); 568 1.32.2.2 skrll 569 1.32.2.2 skrll #ifdef __NetBSD__ 570 1.32.2.2 skrll if_attach(ifp); 571 1.32.2.2 skrll #endif 572 1.32.2.2 skrll /* call MI attach routine. */ 573 1.32.2.2 skrll ieee80211_ifattach(ifp); 574 1.32.2.2 skrll /* override default methods */ 575 1.32.2.2 skrll ic->ic_node_alloc = ath_node_alloc; 576 1.32.2.2 skrll sc->sc_node_free = ic->ic_node_free; 577 1.32.2.2 skrll ic->ic_node_free = ath_node_free; 578 1.32.2.2 skrll sc->sc_node_copy = ic->ic_node_copy; 579 1.32.2.2 skrll ic->ic_node_copy = ath_node_copy; 580 1.32.2.2 skrll ic->ic_node_getrssi = ath_node_getrssi; 581 1.32.2.2 skrll sc->sc_newstate = ic->ic_newstate; 582 1.32.2.2 skrll ic->ic_newstate = ath_newstate; 583 1.32.2.3 skrll sc->sc_recv_mgmt = ic->ic_recv_mgmt; 584 1.32.2.3 skrll ic->ic_recv_mgmt = ath_recv_mgmt; 585 1.32.2.3 skrll 586 1.32.2.2 skrll /* complete initialization */ 587 1.32.2.2 skrll ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 588 1.32.2.2 skrll 589 1.32.2.2 skrll #if NBPFILTER > 0 590 1.32.2.2 skrll bpfattach2(ifp, DLT_IEEE802_11_RADIO, 591 1.32.2.2 skrll sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 592 1.32.2.2 skrll &sc->sc_drvbpf); 593 1.32.2.2 skrll #endif 594 1.32.2.2 skrll /* 595 1.32.2.2 skrll * Initialize constant fields. 596 1.32.2.2 skrll * XXX make header lengths a multiple of 32-bits so subsequent 597 1.32.2.2 skrll * headers are properly aligned; this is a kludge to keep 598 1.32.2.2 skrll * certain applications happy. 599 1.32.2.2 skrll * 600 1.32.2.2 skrll * NB: the channel is setup each time we transition to the 601 1.32.2.2 skrll * RUN state to avoid filling it in for each frame. 602 1.32.2.2 skrll */ 603 1.32.2.2 skrll sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 604 1.32.2.2 skrll sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 605 1.32.2.2 skrll sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 606 1.32.2.2 skrll 607 1.32.2.2 skrll sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 608 1.32.2.2 skrll sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 609 1.32.2.2 skrll sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 610 1.32.2.2 skrll 611 1.32.2.2 skrll #ifdef __NetBSD__ 612 1.32.2.2 skrll sc->sc_flags |= ATH_ATTACHED; 613 1.32.2.2 skrll /* 614 1.32.2.2 skrll * Make sure the interface is shutdown during reboot. 615 1.32.2.2 skrll */ 616 1.32.2.2 skrll sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 617 1.32.2.2 skrll if (sc->sc_sdhook == NULL) 618 1.32.2.2 skrll printf("%s: WARNING: unable to establish shutdown hook\n", 619 1.32.2.2 skrll sc->sc_dev.dv_xname); 620 1.32.2.2 skrll sc->sc_powerhook = powerhook_establish(ath_power, sc); 621 1.32.2.2 skrll if (sc->sc_powerhook == NULL) 622 1.32.2.2 skrll printf("%s: WARNING: unable to establish power hook\n", 623 1.32.2.2 skrll sc->sc_dev.dv_xname); 624 1.32.2.2 skrll #endif 625 1.32.2.2 skrll return 0; 626 1.32.2.2 skrll bad2: 627 1.32.2.2 skrll ath_desc_free(sc); 628 1.32.2.2 skrll bad: 629 1.32.2.2 skrll if (ah) 630 1.32.2.2 skrll ath_hal_detach(ah); 631 1.32.2.2 skrll sc->sc_invalid = 1; 632 1.32.2.2 skrll return error; 633 1.32.2.2 skrll } 634 1.32.2.2 skrll 635 1.32.2.2 skrll int 636 1.32.2.2 skrll ath_detach(struct ath_softc *sc) 637 1.32.2.2 skrll { 638 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 639 1.32.2.2 skrll ath_softc_critsect_decl(s); 640 1.32.2.2 skrll 641 1.32.2.2 skrll if ((sc->sc_flags & ATH_ATTACHED) == 0) 642 1.32.2.2 skrll return (0); 643 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 644 1.32.2.2 skrll 645 1.32.2.2 skrll ath_softc_critsect_begin(sc, s); 646 1.32.2.8 skrll ath_stop(ifp, 1); 647 1.32.2.2 skrll #if NBPFILTER > 0 648 1.32.2.2 skrll bpfdetach(ifp); 649 1.32.2.2 skrll #endif 650 1.32.2.2 skrll ath_desc_free(sc); 651 1.32.2.2 skrll ath_hal_detach(sc->sc_ah); 652 1.32.2.2 skrll ieee80211_ifdetach(ifp); 653 1.32.2.2 skrll #ifdef __NetBSD__ 654 1.32.2.2 skrll if_detach(ifp); 655 1.32.2.2 skrll #endif /* __NetBSD__ */ 656 1.32.2.2 skrll ath_softc_critsect_end(sc, s); 657 1.32.2.2 skrll #ifdef __NetBSD__ 658 1.32.2.2 skrll powerhook_disestablish(sc->sc_powerhook); 659 1.32.2.2 skrll shutdownhook_disestablish(sc->sc_sdhook); 660 1.32.2.2 skrll #endif /* __NetBSD__ */ 661 1.32.2.2 skrll #ifdef __FreeBSD__ 662 1.32.2.2 skrll 663 1.32.2.2 skrll ATH_TXBUF_LOCK_DESTROY(sc); 664 1.32.2.2 skrll ATH_TXQ_LOCK_DESTROY(sc); 665 1.32.2.2 skrll 666 1.32.2.2 skrll #endif /* __FreeBSD__ */ 667 1.32.2.2 skrll return 0; 668 1.32.2.2 skrll } 669 1.32.2.2 skrll 670 1.32.2.2 skrll #ifdef __NetBSD__ 671 1.32.2.2 skrll void 672 1.32.2.2 skrll ath_power(int why, void *arg) 673 1.32.2.2 skrll { 674 1.32.2.2 skrll struct ath_softc *sc = arg; 675 1.32.2.2 skrll int s; 676 1.32.2.2 skrll 677 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("ath_power(%d)\n", why)); 678 1.32.2.2 skrll 679 1.32.2.2 skrll s = splnet(); 680 1.32.2.2 skrll switch (why) { 681 1.32.2.2 skrll case PWR_SUSPEND: 682 1.32.2.2 skrll case PWR_STANDBY: 683 1.32.2.2 skrll ath_suspend(sc, why); 684 1.32.2.2 skrll break; 685 1.32.2.2 skrll case PWR_RESUME: 686 1.32.2.2 skrll ath_resume(sc, why); 687 1.32.2.2 skrll break; 688 1.32.2.2 skrll case PWR_SOFTSUSPEND: 689 1.32.2.2 skrll case PWR_SOFTSTANDBY: 690 1.32.2.2 skrll case PWR_SOFTRESUME: 691 1.32.2.2 skrll break; 692 1.32.2.2 skrll } 693 1.32.2.2 skrll splx(s); 694 1.32.2.2 skrll } 695 1.32.2.2 skrll #endif 696 1.32.2.2 skrll 697 1.32.2.2 skrll void 698 1.32.2.2 skrll ath_suspend(struct ath_softc *sc, int why) 699 1.32.2.2 skrll { 700 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 701 1.32.2.2 skrll 702 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 703 1.32.2.2 skrll 704 1.32.2.8 skrll ath_stop(ifp, 1); 705 1.32.2.2 skrll if (sc->sc_power != NULL) 706 1.32.2.2 skrll (*sc->sc_power)(sc, why); 707 1.32.2.2 skrll } 708 1.32.2.2 skrll 709 1.32.2.2 skrll void 710 1.32.2.2 skrll ath_resume(struct ath_softc *sc, int why) 711 1.32.2.2 skrll { 712 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 713 1.32.2.2 skrll 714 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 715 1.32.2.2 skrll 716 1.32.2.2 skrll if (ifp->if_flags & IFF_UP) { 717 1.32.2.2 skrll ath_init(ifp); 718 1.32.2.2 skrll #if 0 719 1.32.2.2 skrll (void)ath_intr(sc); 720 1.32.2.2 skrll #endif 721 1.32.2.2 skrll if (sc->sc_power != NULL) 722 1.32.2.2 skrll (*sc->sc_power)(sc, why); 723 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 724 1.32.2.2 skrll ath_start(ifp); 725 1.32.2.2 skrll } 726 1.32.2.2 skrll } 727 1.32.2.2 skrll 728 1.32.2.2 skrll #ifdef __NetBSD__ 729 1.32.2.2 skrll void 730 1.32.2.2 skrll ath_shutdown(void *arg) 731 1.32.2.2 skrll { 732 1.32.2.2 skrll struct ath_softc *sc = arg; 733 1.32.2.2 skrll 734 1.32.2.8 skrll ath_stop(&sc->sc_ic.ic_if, 1); 735 1.32.2.2 skrll } 736 1.32.2.2 skrll #else 737 1.32.2.2 skrll void 738 1.32.2.2 skrll ath_shutdown(struct ath_softc *sc) 739 1.32.2.2 skrll { 740 1.32.2.2 skrll #if 1 741 1.32.2.2 skrll return; 742 1.32.2.2 skrll #else 743 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 744 1.32.2.2 skrll 745 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 746 1.32.2.2 skrll 747 1.32.2.8 skrll ath_stop(ifp, 1); 748 1.32.2.2 skrll #endif 749 1.32.2.2 skrll } 750 1.32.2.2 skrll #endif 751 1.32.2.2 skrll 752 1.32.2.2 skrll #ifdef __NetBSD__ 753 1.32.2.2 skrll int 754 1.32.2.2 skrll ath_intr(void *arg) 755 1.32.2.2 skrll { 756 1.32.2.2 skrll return ath_intr1((struct ath_softc *)arg); 757 1.32.2.2 skrll } 758 1.32.2.2 skrll #else 759 1.32.2.2 skrll void 760 1.32.2.2 skrll ath_intr(void *arg) 761 1.32.2.2 skrll { 762 1.32.2.2 skrll (void)ath_intr1((struct ath_softc *)arg); 763 1.32.2.2 skrll } 764 1.32.2.2 skrll #endif 765 1.32.2.2 skrll 766 1.32.2.2 skrll static int 767 1.32.2.2 skrll ath_intr1(struct ath_softc *sc) 768 1.32.2.2 skrll { 769 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 770 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 771 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 772 1.32.2.2 skrll HAL_INT status; 773 1.32.2.2 skrll 774 1.32.2.2 skrll if (sc->sc_invalid) { 775 1.32.2.2 skrll /* 776 1.32.2.2 skrll * The hardware is not ready/present, don't touch anything. 777 1.32.2.2 skrll * Note this can happen early on if the IRQ is shared. 778 1.32.2.2 skrll */ 779 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: invalid; ignored\n", __func__)); 780 1.32.2.2 skrll return 0; 781 1.32.2.2 skrll } 782 1.32.2.2 skrll if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 783 1.32.2.2 skrll return 0; 784 1.32.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 785 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags 0x%x\n", 786 1.32.2.2 skrll __func__, ifp->if_flags)); 787 1.32.2.2 skrll ath_hal_getisr(ah, &status); /* clear ISR */ 788 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable further intr's */ 789 1.32.2.2 skrll return 1; /* XXX */ 790 1.32.2.2 skrll } 791 1.32.2.2 skrll ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 792 1.32.2.2 skrll DPRINTF(ATH_DEBUG_INTR, ("%s: status 0x%x\n", __func__, status)); 793 1.32.2.2 skrll status &= sc->sc_imask; /* discard unasked for bits */ 794 1.32.2.2 skrll if (status & HAL_INT_FATAL) { 795 1.32.2.2 skrll sc->sc_stats.ast_hardware++; 796 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable intr's until reset */ 797 1.32.2.2 skrll ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 798 1.32.2.2 skrll } else if (status & HAL_INT_RXORN) { 799 1.32.2.2 skrll sc->sc_stats.ast_rxorn++; 800 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable intr's until reset */ 801 1.32.2.2 skrll ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 802 1.32.2.2 skrll } else { 803 1.32.2.2 skrll if (status & HAL_INT_RXEOL) { 804 1.32.2.2 skrll /* 805 1.32.2.2 skrll * NB: the hardware should re-read the link when 806 1.32.2.2 skrll * RXE bit is written, but it doesn't work at 807 1.32.2.2 skrll * least on older hardware revs. 808 1.32.2.2 skrll */ 809 1.32.2.2 skrll sc->sc_stats.ast_rxeol++; 810 1.32.2.2 skrll sc->sc_rxlink = NULL; 811 1.32.2.2 skrll } 812 1.32.2.2 skrll if (status & HAL_INT_TXURN) { 813 1.32.2.2 skrll sc->sc_stats.ast_txurn++; 814 1.32.2.2 skrll /* bump tx trigger level */ 815 1.32.2.2 skrll ath_hal_updatetxtriglevel(ah, AH_TRUE); 816 1.32.2.2 skrll } 817 1.32.2.2 skrll if (status & HAL_INT_RX) 818 1.32.2.2 skrll ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 819 1.32.2.2 skrll if (status & HAL_INT_TX) 820 1.32.2.2 skrll ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 821 1.32.2.2 skrll if (status & HAL_INT_SWBA) { 822 1.32.2.2 skrll /* 823 1.32.2.2 skrll * Handle beacon transmission directly; deferring 824 1.32.2.2 skrll * this is too slow to meet timing constraints 825 1.32.2.2 skrll * under load. 826 1.32.2.2 skrll */ 827 1.32.2.2 skrll ath_beacon_proc(sc, 0); 828 1.32.2.2 skrll } 829 1.32.2.2 skrll if (status & HAL_INT_BMISS) { 830 1.32.2.2 skrll sc->sc_stats.ast_bmiss++; 831 1.32.2.2 skrll ATH_TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 832 1.32.2.2 skrll } 833 1.32.2.2 skrll } 834 1.32.2.2 skrll return 1; 835 1.32.2.2 skrll } 836 1.32.2.2 skrll 837 1.32.2.2 skrll static void 838 1.32.2.2 skrll ath_fatal_proc(void *arg, int pending) 839 1.32.2.2 skrll { 840 1.32.2.2 skrll struct ath_softc *sc = arg; 841 1.32.2.2 skrll 842 1.32.2.2 skrll device_printf(sc->sc_dev, "hardware error; resetting\n"); 843 1.32.2.2 skrll ath_reset(sc); 844 1.32.2.2 skrll } 845 1.32.2.2 skrll 846 1.32.2.2 skrll static void 847 1.32.2.2 skrll ath_rxorn_proc(void *arg, int pending) 848 1.32.2.2 skrll { 849 1.32.2.2 skrll struct ath_softc *sc = arg; 850 1.32.2.2 skrll 851 1.32.2.2 skrll device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 852 1.32.2.2 skrll ath_reset(sc); 853 1.32.2.2 skrll } 854 1.32.2.2 skrll 855 1.32.2.2 skrll static void 856 1.32.2.2 skrll ath_bmiss_proc(void *arg, int pending) 857 1.32.2.2 skrll { 858 1.32.2.2 skrll struct ath_softc *sc = arg; 859 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 860 1.32.2.2 skrll 861 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: pending %u\n", __func__, pending)); 862 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) 863 1.32.2.2 skrll return; 864 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_RUN) { 865 1.32.2.2 skrll /* 866 1.32.2.2 skrll * Rather than go directly to scan state, try to 867 1.32.2.2 skrll * reassociate first. If that fails then the state 868 1.32.2.2 skrll * machine will drop us into scanning after timing 869 1.32.2.2 skrll * out waiting for a probe response. 870 1.32.2.2 skrll */ 871 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 872 1.32.2.2 skrll } 873 1.32.2.2 skrll } 874 1.32.2.2 skrll 875 1.32.2.2 skrll static u_int 876 1.32.2.2 skrll ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 877 1.32.2.2 skrll { 878 1.32.2.2 skrll enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 879 1.32.2.2 skrll 880 1.32.2.2 skrll switch (mode) { 881 1.32.2.2 skrll case IEEE80211_MODE_AUTO: 882 1.32.2.2 skrll return 0; 883 1.32.2.2 skrll case IEEE80211_MODE_11A: 884 1.32.2.2 skrll return CHANNEL_A; 885 1.32.2.2 skrll case IEEE80211_MODE_11B: 886 1.32.2.2 skrll return CHANNEL_B; 887 1.32.2.2 skrll case IEEE80211_MODE_11G: 888 1.32.2.2 skrll return CHANNEL_PUREG; 889 1.32.2.2 skrll case IEEE80211_MODE_TURBO: 890 1.32.2.2 skrll return CHANNEL_T; 891 1.32.2.2 skrll default: 892 1.32.2.2 skrll panic("%s: unsupported mode %d\n", __func__, mode); 893 1.32.2.2 skrll return 0; 894 1.32.2.2 skrll } 895 1.32.2.2 skrll } 896 1.32.2.2 skrll 897 1.32.2.2 skrll #ifdef __NetBSD__ 898 1.32.2.2 skrll static int 899 1.32.2.2 skrll ath_init(struct ifnet *ifp) 900 1.32.2.2 skrll { 901 1.32.2.2 skrll return ath_init1((struct ath_softc *)ifp->if_softc); 902 1.32.2.2 skrll } 903 1.32.2.2 skrll #else 904 1.32.2.2 skrll static void 905 1.32.2.2 skrll ath_init(void *arg) 906 1.32.2.2 skrll { 907 1.32.2.2 skrll (void)ath_init1((struct ath_softc *)arg); 908 1.32.2.2 skrll } 909 1.32.2.2 skrll #endif 910 1.32.2.2 skrll 911 1.32.2.2 skrll static int 912 1.32.2.2 skrll ath_init1(struct ath_softc *sc) 913 1.32.2.2 skrll { 914 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 915 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 916 1.32.2.2 skrll struct ieee80211_node *ni; 917 1.32.2.2 skrll enum ieee80211_phymode mode; 918 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 919 1.32.2.2 skrll HAL_STATUS status; 920 1.32.2.2 skrll HAL_CHANNEL hchan; 921 1.32.2.2 skrll int error = 0; 922 1.32.2.2 skrll ath_softc_critsect_decl(s); 923 1.32.2.2 skrll 924 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags 0x%x\n", 925 1.32.2.2 skrll __func__, ifp->if_flags)); 926 1.32.2.2 skrll 927 1.32.2.2 skrll #ifdef __NetBSD__ 928 1.32.2.2 skrll if ((error = ath_enable(sc)) != 0) 929 1.32.2.2 skrll return error; 930 1.32.2.2 skrll #endif 931 1.32.2.2 skrll 932 1.32.2.2 skrll ath_softc_critsect_begin(sc, s); 933 1.32.2.2 skrll /* 934 1.32.2.2 skrll * Stop anything previously setup. This is safe 935 1.32.2.2 skrll * whether this is the first time through or not. 936 1.32.2.2 skrll */ 937 1.32.2.8 skrll ath_stop(ifp, 0); 938 1.32.2.2 skrll 939 1.32.2.2 skrll /* 940 1.32.2.2 skrll * The basic interface to setting the hardware in a good 941 1.32.2.2 skrll * state is ``reset''. On return the hardware is known to 942 1.32.2.2 skrll * be powered up and with interrupts disabled. This must 943 1.32.2.2 skrll * be followed by initialization of the appropriate bits 944 1.32.2.2 skrll * and then setup of the interrupt mask. 945 1.32.2.2 skrll */ 946 1.32.2.2 skrll hchan.channel = ic->ic_ibss_chan->ic_freq; 947 1.32.2.2 skrll hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 948 1.32.2.2 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 949 1.32.2.2 skrll if_printf(ifp, "unable to reset hardware; hal status %u\n", 950 1.32.2.2 skrll status); 951 1.32.2.3 skrll error = EIO; 952 1.32.2.2 skrll goto done; 953 1.32.2.2 skrll } 954 1.32.2.2 skrll 955 1.32.2.2 skrll /* 956 1.32.2.2 skrll * Setup the hardware after reset: the key cache 957 1.32.2.2 skrll * is filled as needed and the receive engine is 958 1.32.2.2 skrll * set going. Frame transmit is handled entirely 959 1.32.2.2 skrll * in the frame output path; there's nothing to do 960 1.32.2.2 skrll * here except setup the interrupt mask. 961 1.32.2.2 skrll */ 962 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) 963 1.32.2.2 skrll ath_initkeytable(sc); 964 1.32.2.2 skrll if ((error = ath_startrecv(sc)) != 0) { 965 1.32.2.2 skrll if_printf(ifp, "unable to start recv logic\n"); 966 1.32.2.2 skrll goto done; 967 1.32.2.2 skrll } 968 1.32.2.2 skrll 969 1.32.2.2 skrll /* 970 1.32.2.2 skrll * Enable interrupts. 971 1.32.2.2 skrll */ 972 1.32.2.2 skrll sc->sc_imask = HAL_INT_RX | HAL_INT_TX 973 1.32.2.2 skrll | HAL_INT_RXEOL | HAL_INT_RXORN 974 1.32.2.2 skrll | HAL_INT_FATAL | HAL_INT_GLOBAL; 975 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 976 1.32.2.2 skrll 977 1.32.2.2 skrll ifp->if_flags |= IFF_RUNNING; 978 1.32.2.2 skrll ic->ic_state = IEEE80211_S_INIT; 979 1.32.2.2 skrll 980 1.32.2.2 skrll /* 981 1.32.2.2 skrll * The hardware should be ready to go now so it's safe 982 1.32.2.2 skrll * to kick the 802.11 state machine as it's likely to 983 1.32.2.2 skrll * immediately call back to us to send mgmt frames. 984 1.32.2.2 skrll */ 985 1.32.2.2 skrll ni = ic->ic_bss; 986 1.32.2.2 skrll ni->ni_chan = ic->ic_ibss_chan; 987 1.32.2.2 skrll mode = ieee80211_chan2mode(ic, ni->ni_chan); 988 1.32.2.2 skrll if (mode != sc->sc_curmode) 989 1.32.2.2 skrll ath_setcurmode(sc, mode); 990 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_MONITOR) 991 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 992 1.32.2.2 skrll else 993 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 994 1.32.2.2 skrll done: 995 1.32.2.2 skrll ath_softc_critsect_end(sc, s); 996 1.32.2.2 skrll return error; 997 1.32.2.2 skrll } 998 1.32.2.2 skrll 999 1.32.2.2 skrll static void 1000 1.32.2.8 skrll ath_stop(struct ifnet *ifp, int disable) 1001 1.32.2.2 skrll { 1002 1.32.2.2 skrll struct ieee80211com *ic = (struct ieee80211com *) ifp; 1003 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1004 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1005 1.32.2.2 skrll ath_softc_critsect_decl(s); 1006 1.32.2.2 skrll 1007 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: invalid %u if_flags 0x%x\n", 1008 1.32.2.2 skrll __func__, sc->sc_invalid, ifp->if_flags)); 1009 1.32.2.2 skrll 1010 1.32.2.2 skrll ath_softc_critsect_begin(sc, s); 1011 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) { 1012 1.32.2.2 skrll /* 1013 1.32.2.2 skrll * Shutdown the hardware and driver: 1014 1.32.2.2 skrll * disable interrupts 1015 1.32.2.2 skrll * turn off timers 1016 1.32.2.2 skrll * clear transmit machinery 1017 1.32.2.2 skrll * clear receive machinery 1018 1.32.2.2 skrll * drain and release tx queues 1019 1.32.2.2 skrll * reclaim beacon resources 1020 1.32.2.2 skrll * reset 802.11 state machine 1021 1.32.2.2 skrll * power down hardware 1022 1.32.2.2 skrll * 1023 1.32.2.2 skrll * Note that some of this work is not possible if the 1024 1.32.2.2 skrll * hardware is gone (invalid). 1025 1.32.2.2 skrll */ 1026 1.32.2.2 skrll ifp->if_flags &= ~IFF_RUNNING; 1027 1.32.2.2 skrll ifp->if_timer = 0; 1028 1.32.2.2 skrll if (!sc->sc_invalid) 1029 1.32.2.2 skrll ath_hal_intrset(ah, 0); 1030 1.32.2.2 skrll ath_draintxq(sc); 1031 1.32.2.2 skrll if (!sc->sc_invalid) 1032 1.32.2.2 skrll ath_stoprecv(sc); 1033 1.32.2.2 skrll else 1034 1.32.2.2 skrll sc->sc_rxlink = NULL; 1035 1.32.2.2 skrll #ifdef __FreeBSD__ 1036 1.32.2.2 skrll IF_DRAIN(&ifp->if_snd); 1037 1.32.2.2 skrll #else 1038 1.32.2.2 skrll IF_PURGE(&ifp->if_snd); 1039 1.32.2.2 skrll #endif 1040 1.32.2.2 skrll ath_beacon_free(sc); 1041 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1042 1.32.2.2 skrll if (!sc->sc_invalid) { 1043 1.32.2.2 skrll ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 1044 1.32.2.2 skrll } 1045 1.32.2.2 skrll #ifdef __NetBSD__ 1046 1.32.2.8 skrll if (disable) 1047 1.32.2.8 skrll ath_disable(sc); 1048 1.32.2.2 skrll #endif 1049 1.32.2.2 skrll } 1050 1.32.2.2 skrll ath_softc_critsect_end(sc, s); 1051 1.32.2.2 skrll } 1052 1.32.2.2 skrll 1053 1.32.2.2 skrll /* 1054 1.32.2.2 skrll * Reset the hardware w/o losing operational state. This is 1055 1.32.2.2 skrll * basically a more efficient way of doing ath_stop, ath_init, 1056 1.32.2.2 skrll * followed by state transitions to the current 802.11 1057 1.32.2.2 skrll * operational state. Used to recover from errors rx overrun 1058 1.32.2.2 skrll * and to reset the hardware when rf gain settings must be reset. 1059 1.32.2.2 skrll */ 1060 1.32.2.2 skrll static void 1061 1.32.2.2 skrll ath_reset(struct ath_softc *sc) 1062 1.32.2.2 skrll { 1063 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1064 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1065 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1066 1.32.2.2 skrll struct ieee80211_channel *c; 1067 1.32.2.2 skrll HAL_STATUS status; 1068 1.32.2.2 skrll HAL_CHANNEL hchan; 1069 1.32.2.2 skrll 1070 1.32.2.2 skrll /* 1071 1.32.2.2 skrll * Convert to a HAL channel description with the flags 1072 1.32.2.2 skrll * constrained to reflect the current operating mode. 1073 1.32.2.2 skrll */ 1074 1.32.2.2 skrll c = ic->ic_ibss_chan; 1075 1.32.2.2 skrll hchan.channel = c->ic_freq; 1076 1.32.2.2 skrll hchan.channelFlags = ath_chan2flags(ic, c); 1077 1.32.2.2 skrll 1078 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable interrupts */ 1079 1.32.2.2 skrll ath_draintxq(sc); /* stop xmit side */ 1080 1.32.2.2 skrll ath_stoprecv(sc); /* stop recv side */ 1081 1.32.2.2 skrll /* NB: indicate channel change so we do a full reset */ 1082 1.32.2.2 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 1083 1.32.2.2 skrll if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1084 1.32.2.2 skrll __func__, status); 1085 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 1086 1.32.2.2 skrll if (ath_startrecv(sc) != 0) /* restart recv */ 1087 1.32.2.2 skrll if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1088 1.32.2.2 skrll ath_start(ifp); /* restart xmit */ 1089 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_RUN) 1090 1.32.2.2 skrll ath_beacon_config(sc); /* restart beacons */ 1091 1.32.2.2 skrll } 1092 1.32.2.2 skrll 1093 1.32.2.2 skrll static void 1094 1.32.2.2 skrll ath_start(struct ifnet *ifp) 1095 1.32.2.2 skrll { 1096 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1097 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1098 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1099 1.32.2.2 skrll struct ieee80211_node *ni; 1100 1.32.2.2 skrll struct ath_buf *bf; 1101 1.32.2.2 skrll struct mbuf *m; 1102 1.32.2.2 skrll struct ieee80211_frame *wh; 1103 1.32.2.2 skrll ath_txbuf_critsect_decl(s); 1104 1.32.2.2 skrll 1105 1.32.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1106 1.32.2.2 skrll return; 1107 1.32.2.2 skrll for (;;) { 1108 1.32.2.2 skrll /* 1109 1.32.2.2 skrll * Grab a TX buffer and associated resources. 1110 1.32.2.2 skrll */ 1111 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s); 1112 1.32.2.2 skrll bf = TAILQ_FIRST(&sc->sc_txbuf); 1113 1.32.2.2 skrll if (bf != NULL) 1114 1.32.2.2 skrll TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 1115 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s); 1116 1.32.2.2 skrll if (bf == NULL) { 1117 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: out of xmit buffers\n", 1118 1.32.2.2 skrll __func__)); 1119 1.32.2.2 skrll sc->sc_stats.ast_tx_qstop++; 1120 1.32.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1121 1.32.2.2 skrll break; 1122 1.32.2.2 skrll } 1123 1.32.2.2 skrll /* 1124 1.32.2.2 skrll * Poll the management queue for frames; they 1125 1.32.2.2 skrll * have priority over normal data frames. 1126 1.32.2.2 skrll */ 1127 1.32.2.2 skrll IF_DEQUEUE(&ic->ic_mgtq, m); 1128 1.32.2.2 skrll if (m == NULL) { 1129 1.32.2.2 skrll /* 1130 1.32.2.2 skrll * No data frames go out unless we're associated. 1131 1.32.2.2 skrll */ 1132 1.32.2.2 skrll if (ic->ic_state != IEEE80211_S_RUN) { 1133 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 1134 1.32.2.2 skrll ("%s: ignore data packet, state %u\n", 1135 1.32.2.2 skrll __func__, ic->ic_state)); 1136 1.32.2.2 skrll sc->sc_stats.ast_tx_discard++; 1137 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s); 1138 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1139 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s); 1140 1.32.2.2 skrll break; 1141 1.32.2.2 skrll } 1142 1.32.2.2 skrll IF_DEQUEUE(&ifp->if_snd, m); 1143 1.32.2.2 skrll if (m == NULL) { 1144 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s); 1145 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1146 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s); 1147 1.32.2.2 skrll break; 1148 1.32.2.2 skrll } 1149 1.32.2.2 skrll ifp->if_opackets++; 1150 1.32.2.2 skrll 1151 1.32.2.2 skrll #ifdef __NetBSD__ 1152 1.32.2.2 skrll #if NBPFILTER > 0 1153 1.32.2.2 skrll if (ifp->if_bpf) 1154 1.32.2.2 skrll bpf_mtap(ifp->if_bpf, m); 1155 1.32.2.2 skrll #endif 1156 1.32.2.2 skrll #endif 1157 1.32.2.2 skrll #ifdef __FreeBSD__ 1158 1.32.2.2 skrll BPF_MTAP(ifp, m); 1159 1.32.2.2 skrll #endif 1160 1.32.2.2 skrll /* 1161 1.32.2.2 skrll * Encapsulate the packet in prep for transmission. 1162 1.32.2.2 skrll */ 1163 1.32.2.2 skrll m = ieee80211_encap(ifp, m, &ni); 1164 1.32.2.2 skrll if (m == NULL) { 1165 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 1166 1.32.2.2 skrll ("%s: encapsulation failure\n", 1167 1.32.2.2 skrll __func__)); 1168 1.32.2.2 skrll sc->sc_stats.ast_tx_encap++; 1169 1.32.2.2 skrll goto bad; 1170 1.32.2.2 skrll } 1171 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1172 1.32.2.2 skrll } else { 1173 1.32.2.2 skrll /* 1174 1.32.2.2 skrll * Hack! The referenced node pointer is in the 1175 1.32.2.2 skrll * rcvif field of the packet header. This is 1176 1.32.2.2 skrll * placed there by ieee80211_mgmt_output because 1177 1.32.2.2 skrll * we need to hold the reference with the frame 1178 1.32.2.2 skrll * and there's no other way (other than packet 1179 1.32.2.2 skrll * tags which we consider too expensive to use) 1180 1.32.2.2 skrll * to pass it along. 1181 1.32.2.2 skrll */ 1182 1.32.2.2 skrll ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1183 1.32.2.2 skrll m->m_pkthdr.rcvif = NULL; 1184 1.32.2.2 skrll 1185 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1186 1.32.2.2 skrll if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1187 1.32.2.2 skrll IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1188 1.32.2.2 skrll /* fill time stamp */ 1189 1.32.2.2 skrll u_int64_t tsf; 1190 1.32.2.2 skrll u_int32_t *tstamp; 1191 1.32.2.2 skrll 1192 1.32.2.2 skrll tsf = ath_hal_gettsf64(ah); 1193 1.32.2.2 skrll /* XXX: adjust 100us delay to xmit */ 1194 1.32.2.2 skrll tsf += 100; 1195 1.32.2.2 skrll tstamp = (u_int32_t *)&wh[1]; 1196 1.32.2.2 skrll tstamp[0] = htole32(tsf & 0xffffffff); 1197 1.32.2.2 skrll tstamp[1] = htole32(tsf >> 32); 1198 1.32.2.2 skrll } 1199 1.32.2.2 skrll sc->sc_stats.ast_tx_mgmt++; 1200 1.32.2.2 skrll } 1201 1.32.2.2 skrll 1202 1.32.2.2 skrll if (ath_tx_start(sc, ni, bf, m)) { 1203 1.32.2.2 skrll bad: 1204 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s); 1205 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1206 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s); 1207 1.32.2.2 skrll ifp->if_oerrors++; 1208 1.32.2.3 skrll if (ni != NULL) 1209 1.32.2.3 skrll ieee80211_release_node(ic, ni); 1210 1.32.2.2 skrll continue; 1211 1.32.2.2 skrll } 1212 1.32.2.2 skrll 1213 1.32.2.2 skrll sc->sc_tx_timer = 5; 1214 1.32.2.2 skrll ifp->if_timer = 1; 1215 1.32.2.2 skrll } 1216 1.32.2.2 skrll } 1217 1.32.2.2 skrll 1218 1.32.2.2 skrll static int 1219 1.32.2.2 skrll ath_media_change(struct ifnet *ifp) 1220 1.32.2.2 skrll { 1221 1.32.2.2 skrll int error; 1222 1.32.2.2 skrll 1223 1.32.2.2 skrll error = ieee80211_media_change(ifp); 1224 1.32.2.2 skrll if (error == ENETRESET) { 1225 1.32.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 1226 1.32.2.2 skrll (IFF_RUNNING|IFF_UP)) 1227 1.32.2.2 skrll ath_init(ifp); /* XXX lose error */ 1228 1.32.2.2 skrll error = 0; 1229 1.32.2.2 skrll } 1230 1.32.2.2 skrll return error; 1231 1.32.2.2 skrll } 1232 1.32.2.2 skrll 1233 1.32.2.2 skrll static void 1234 1.32.2.2 skrll ath_watchdog(struct ifnet *ifp) 1235 1.32.2.2 skrll { 1236 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1237 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1238 1.32.2.2 skrll 1239 1.32.2.2 skrll ifp->if_timer = 0; 1240 1.32.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1241 1.32.2.2 skrll return; 1242 1.32.2.2 skrll if (sc->sc_tx_timer) { 1243 1.32.2.2 skrll if (--sc->sc_tx_timer == 0) { 1244 1.32.2.2 skrll if_printf(ifp, "device timeout\n"); 1245 1.32.2.2 skrll ath_reset(sc); 1246 1.32.2.2 skrll ifp->if_oerrors++; 1247 1.32.2.2 skrll sc->sc_stats.ast_watchdog++; 1248 1.32.2.2 skrll return; 1249 1.32.2.2 skrll } 1250 1.32.2.2 skrll ifp->if_timer = 1; 1251 1.32.2.2 skrll } 1252 1.32.2.2 skrll if (ic->ic_fixed_rate == -1) { 1253 1.32.2.2 skrll /* 1254 1.32.2.2 skrll * Run the rate control algorithm if we're not 1255 1.32.2.2 skrll * locked at a fixed rate. 1256 1.32.2.2 skrll */ 1257 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA) 1258 1.32.2.2 skrll ath_rate_ctl(sc, ic->ic_bss); 1259 1.32.2.2 skrll else 1260 1.32.2.2 skrll ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 1261 1.32.2.2 skrll } 1262 1.32.2.2 skrll ieee80211_watchdog(ifp); 1263 1.32.2.2 skrll } 1264 1.32.2.2 skrll 1265 1.32.2.2 skrll static int 1266 1.32.2.2 skrll ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1267 1.32.2.2 skrll { 1268 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1269 1.32.2.2 skrll struct ifreq *ifr = (struct ifreq *)data; 1270 1.32.2.2 skrll int error = 0; 1271 1.32.2.2 skrll ath_softc_critsect_decl(s); 1272 1.32.2.2 skrll 1273 1.32.2.2 skrll ath_softc_critsect_begin(sc, s); 1274 1.32.2.2 skrll switch (cmd) { 1275 1.32.2.2 skrll case SIOCSIFFLAGS: 1276 1.32.2.2 skrll if (ifp->if_flags & IFF_UP) { 1277 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) { 1278 1.32.2.2 skrll /* 1279 1.32.2.2 skrll * To avoid rescanning another access point, 1280 1.32.2.2 skrll * do not call ath_init() here. Instead, 1281 1.32.2.2 skrll * only reflect promisc mode settings. 1282 1.32.2.2 skrll */ 1283 1.32.2.2 skrll ath_mode_init(sc); 1284 1.32.2.2 skrll } else { 1285 1.32.2.2 skrll /* 1286 1.32.2.2 skrll * Beware of being called during detach to 1287 1.32.2.2 skrll * reset promiscuous mode. In that case we 1288 1.32.2.2 skrll * will still be marked UP but not RUNNING. 1289 1.32.2.2 skrll * However trying to re-init the interface 1290 1.32.2.2 skrll * is the wrong thing to do as we've already 1291 1.32.2.2 skrll * torn down much of our state. There's 1292 1.32.2.2 skrll * probably a better way to deal with this. 1293 1.32.2.2 skrll */ 1294 1.32.2.2 skrll if (!sc->sc_invalid) 1295 1.32.2.2 skrll ath_init(ifp); /* XXX lose error */ 1296 1.32.2.2 skrll } 1297 1.32.2.2 skrll } else 1298 1.32.2.8 skrll ath_stop(ifp, 1); 1299 1.32.2.2 skrll break; 1300 1.32.2.2 skrll case SIOCADDMULTI: 1301 1.32.2.2 skrll case SIOCDELMULTI: 1302 1.32.2.2 skrll #ifdef __FreeBSD__ 1303 1.32.2.2 skrll /* 1304 1.32.2.2 skrll * The upper layer has already installed/removed 1305 1.32.2.2 skrll * the multicast address(es), just recalculate the 1306 1.32.2.2 skrll * multicast filter for the card. 1307 1.32.2.2 skrll */ 1308 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 1309 1.32.2.2 skrll ath_mode_init(sc); 1310 1.32.2.2 skrll #endif 1311 1.32.2.2 skrll #ifdef __NetBSD__ 1312 1.32.2.2 skrll error = (cmd == SIOCADDMULTI) ? 1313 1.32.2.2 skrll ether_addmulti(ifr, &sc->sc_ic.ic_ec) : 1314 1.32.2.2 skrll ether_delmulti(ifr, &sc->sc_ic.ic_ec); 1315 1.32.2.2 skrll if (error == ENETRESET) { 1316 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 1317 1.32.2.2 skrll ath_mode_init(sc); 1318 1.32.2.2 skrll error = 0; 1319 1.32.2.2 skrll } 1320 1.32.2.2 skrll #endif 1321 1.32.2.2 skrll break; 1322 1.32.2.2 skrll case SIOCGATHSTATS: 1323 1.32.2.2 skrll error = copyout(&sc->sc_stats, 1324 1.32.2.2 skrll ifr->ifr_data, sizeof (sc->sc_stats)); 1325 1.32.2.2 skrll break; 1326 1.32.2.2 skrll case SIOCGATHDIAG: { 1327 1.32.2.2 skrll #if 0 /* XXX punt */ 1328 1.32.2.2 skrll struct ath_diag *ad = (struct ath_diag *)data; 1329 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1330 1.32.2.2 skrll void *data; 1331 1.32.2.2 skrll u_int size; 1332 1.32.2.2 skrll 1333 1.32.2.2 skrll if (ath_hal_getdiagstate(ah, ad->ad_id, &data, &size)) { 1334 1.32.2.2 skrll if (size < ad->ad_size) 1335 1.32.2.2 skrll ad->ad_size = size; 1336 1.32.2.2 skrll if (data) 1337 1.32.2.2 skrll error = copyout(data, ad->ad_data, ad->ad_size); 1338 1.32.2.2 skrll } else 1339 1.32.2.2 skrll error = EINVAL; 1340 1.32.2.2 skrll #else 1341 1.32.2.2 skrll error = EINVAL; 1342 1.32.2.2 skrll #endif 1343 1.32.2.2 skrll break; 1344 1.32.2.2 skrll } 1345 1.32.2.2 skrll default: 1346 1.32.2.2 skrll error = ieee80211_ioctl(ifp, cmd, data); 1347 1.32.2.2 skrll if (error == ENETRESET) { 1348 1.32.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 1349 1.32.2.2 skrll (IFF_RUNNING|IFF_UP)) 1350 1.32.2.2 skrll ath_init(ifp); /* XXX lose error */ 1351 1.32.2.2 skrll error = 0; 1352 1.32.2.2 skrll } 1353 1.32.2.2 skrll break; 1354 1.32.2.2 skrll } 1355 1.32.2.2 skrll ath_softc_critsect_end(sc, s); 1356 1.32.2.2 skrll return error; 1357 1.32.2.2 skrll } 1358 1.32.2.2 skrll 1359 1.32.2.2 skrll /* 1360 1.32.2.2 skrll * Fill the hardware key cache with key entries. 1361 1.32.2.2 skrll */ 1362 1.32.2.2 skrll static void 1363 1.32.2.2 skrll ath_initkeytable(struct ath_softc *sc) 1364 1.32.2.2 skrll { 1365 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1366 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1367 1.32.2.2 skrll int i; 1368 1.32.2.2 skrll 1369 1.32.2.3 skrll /* XXX maybe should reset all keys when !WEPON */ 1370 1.32.2.2 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1371 1.32.2.2 skrll struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 1372 1.32.2.2 skrll if (k->wk_len == 0) 1373 1.32.2.2 skrll ath_hal_keyreset(ah, i); 1374 1.32.2.3 skrll else { 1375 1.32.2.3 skrll HAL_KEYVAL hk; 1376 1.32.2.3 skrll 1377 1.32.2.3 skrll memset(&hk, 0, sizeof(hk)); 1378 1.32.2.3 skrll hk.kv_type = HAL_CIPHER_WEP; 1379 1.32.2.3 skrll hk.kv_len = k->wk_len; 1380 1.32.2.3 skrll memcpy(hk.kv_val, k->wk_key, k->wk_len); 1381 1.32.2.2 skrll /* XXX return value */ 1382 1.32.2.3 skrll ath_hal_keyset(ah, i, &hk); 1383 1.32.2.3 skrll } 1384 1.32.2.2 skrll } 1385 1.32.2.2 skrll } 1386 1.32.2.2 skrll 1387 1.32.2.2 skrll static void 1388 1.32.2.2 skrll ath_mcastfilter_accum(caddr_t dl, u_int32_t (*mfilt)[2]) 1389 1.32.2.2 skrll { 1390 1.32.2.2 skrll u_int32_t val; 1391 1.32.2.2 skrll u_int8_t pos; 1392 1.32.2.2 skrll 1393 1.32.2.2 skrll val = LE_READ_4(dl + 0); 1394 1.32.2.2 skrll pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1395 1.32.2.2 skrll val = LE_READ_4(dl + 3); 1396 1.32.2.2 skrll pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1397 1.32.2.2 skrll pos &= 0x3f; 1398 1.32.2.2 skrll (*mfilt)[pos / 32] |= (1 << (pos % 32)); 1399 1.32.2.2 skrll } 1400 1.32.2.2 skrll 1401 1.32.2.2 skrll #ifdef __FreeBSD__ 1402 1.32.2.2 skrll static void 1403 1.32.2.2 skrll ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t (*mfilt)[2]) 1404 1.32.2.2 skrll { 1405 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1406 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1407 1.32.2.2 skrll struct ifmultiaddr *ifma; 1408 1.32.2.2 skrll 1409 1.32.2.2 skrll TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1410 1.32.2.2 skrll caddr_t dl; 1411 1.32.2.2 skrll 1412 1.32.2.2 skrll /* calculate XOR of eight 6bit values */ 1413 1.32.2.2 skrll dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1414 1.32.2.2 skrll ath_mcastfilter_accum(dl, &mfilt); 1415 1.32.2.2 skrll } 1416 1.32.2.2 skrll } 1417 1.32.2.2 skrll #else 1418 1.32.2.2 skrll static void 1419 1.32.2.2 skrll ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t (*mfilt)[2]) 1420 1.32.2.2 skrll { 1421 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 1422 1.32.2.2 skrll struct ether_multi *enm; 1423 1.32.2.2 skrll struct ether_multistep estep; 1424 1.32.2.2 skrll 1425 1.32.2.2 skrll ETHER_FIRST_MULTI(estep, &sc->sc_ic.ic_ec, enm); 1426 1.32.2.10 skrll while (enm != NULL) { 1427 1.32.2.2 skrll /* XXX Punt on ranges. */ 1428 1.32.2.2 skrll if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1429 1.32.2.2 skrll (*mfilt)[0] = (*mfilt)[1] = ~((u_int32_t)0); 1430 1.32.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 1431 1.32.2.2 skrll return; 1432 1.32.2.2 skrll } 1433 1.32.2.2 skrll ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1434 1.32.2.2 skrll ETHER_NEXT_MULTI(estep, enm); 1435 1.32.2.2 skrll } 1436 1.32.2.2 skrll ifp->if_flags &= ~IFF_ALLMULTI; 1437 1.32.2.2 skrll } 1438 1.32.2.2 skrll #endif 1439 1.32.2.2 skrll 1440 1.32.2.2 skrll /* 1441 1.32.2.2 skrll * Calculate the receive filter according to the 1442 1.32.2.2 skrll * operating mode and state: 1443 1.32.2.2 skrll * 1444 1.32.2.2 skrll * o always accept unicast, broadcast, and multicast traffic 1445 1.32.2.2 skrll * o maintain current state of phy error reception 1446 1.32.2.2 skrll * o probe request frames are accepted only when operating in 1447 1.32.2.2 skrll * hostap, adhoc, or monitor modes 1448 1.32.2.2 skrll * o enable promiscuous mode according to the interface state 1449 1.32.2.2 skrll * o accept beacons: 1450 1.32.2.2 skrll * - when operating in adhoc mode so the 802.11 layer creates 1451 1.32.2.2 skrll * node table entries for peers, 1452 1.32.2.2 skrll * - when operating in station mode for collecting rssi data when 1453 1.32.2.2 skrll * the station is otherwise quiet, or 1454 1.32.2.2 skrll * - when scanning 1455 1.32.2.2 skrll */ 1456 1.32.2.2 skrll static u_int32_t 1457 1.32.2.2 skrll ath_calcrxfilter(struct ath_softc *sc) 1458 1.32.2.2 skrll { 1459 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1460 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1461 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1462 1.32.2.2 skrll u_int32_t rfilt; 1463 1.32.2.2 skrll 1464 1.32.2.2 skrll rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1465 1.32.2.2 skrll | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1466 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) 1467 1.32.2.2 skrll rfilt |= HAL_RX_FILTER_PROBEREQ; 1468 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_AHDEMO) 1469 1.32.2.2 skrll rfilt |= HAL_RX_FILTER_BEACON; 1470 1.32.2.2 skrll if (ifp->if_flags & IFF_PROMISC) 1471 1.32.2.2 skrll rfilt |= HAL_RX_FILTER_PROM; 1472 1.32.2.2 skrll return rfilt; 1473 1.32.2.2 skrll } 1474 1.32.2.2 skrll 1475 1.32.2.2 skrll static void 1476 1.32.2.2 skrll ath_mode_init(struct ath_softc *sc) 1477 1.32.2.2 skrll { 1478 1.32.2.2 skrll #ifdef __FreeBSD__ 1479 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1480 1.32.2.2 skrll #endif 1481 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1482 1.32.2.2 skrll u_int32_t rfilt, mfilt[2]; 1483 1.32.2.2 skrll 1484 1.32.2.2 skrll /* configure rx filter */ 1485 1.32.2.2 skrll rfilt = ath_calcrxfilter(sc); 1486 1.32.2.2 skrll ath_hal_setrxfilter(ah, rfilt); 1487 1.32.2.2 skrll 1488 1.32.2.2 skrll /* configure operational mode */ 1489 1.32.2.2 skrll ath_hal_setopmode(ah); 1490 1.32.2.2 skrll 1491 1.32.2.2 skrll /* calculate and install multicast filter */ 1492 1.32.2.2 skrll #ifdef __FreeBSD__ 1493 1.32.2.2 skrll if ((ic->ic_if.if_flags & IFF_ALLMULTI) == 0) { 1494 1.32.2.2 skrll mfilt[0] = mfilt[1] = 0; 1495 1.32.2.2 skrll ath_mcastfilter_compute(sc, &mfilt); 1496 1.32.2.2 skrll } else { 1497 1.32.2.2 skrll mfilt[0] = mfilt[1] = ~0; 1498 1.32.2.2 skrll } 1499 1.32.2.2 skrll #endif 1500 1.32.2.2 skrll #ifdef __NetBSD__ 1501 1.32.2.2 skrll mfilt[0] = mfilt[1] = 0; 1502 1.32.2.2 skrll ath_mcastfilter_compute(sc, &mfilt); 1503 1.32.2.2 skrll #endif 1504 1.32.2.2 skrll ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1505 1.32.2.2 skrll DPRINTF(ATH_DEBUG_MODE, ("%s: RX filter 0x%x, MC filter %08x:%08x\n", 1506 1.32.2.2 skrll __func__, rfilt, mfilt[0], mfilt[1])); 1507 1.32.2.2 skrll } 1508 1.32.2.2 skrll 1509 1.32.2.2 skrll #ifdef __FreeBSD__ 1510 1.32.2.2 skrll static void 1511 1.32.2.2 skrll ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 1512 1.32.2.2 skrll { 1513 1.32.2.2 skrll struct ath_buf *bf = arg; 1514 1.32.2.2 skrll 1515 1.32.2.2 skrll KASSERT(nseg <= ATH_MAX_SCATTER, 1516 1.32.2.2 skrll ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 1517 1.32.2.2 skrll bf->bf_mapsize = mapsize; 1518 1.32.2.2 skrll bf->bf_nseg = nseg; 1519 1.32.2.2 skrll bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 1520 1.32.2.2 skrll } 1521 1.32.2.2 skrll #endif /* __FreeBSD__ */ 1522 1.32.2.2 skrll 1523 1.32.2.2 skrll static struct mbuf * 1524 1.32.2.2 skrll ath_getmbuf(int flags, int type, u_int pktlen) 1525 1.32.2.2 skrll { 1526 1.32.2.2 skrll struct mbuf *m; 1527 1.32.2.2 skrll 1528 1.32.2.2 skrll KASSERT(pktlen <= MCLBYTES, ("802.11 packet too large: %u", pktlen)); 1529 1.32.2.2 skrll #ifdef __FreeBSD__ 1530 1.32.2.2 skrll if (pktlen <= MHLEN) 1531 1.32.2.2 skrll MGETHDR(m, flags, type); 1532 1.32.2.2 skrll else 1533 1.32.2.2 skrll m = m_getcl(flags, type, M_PKTHDR); 1534 1.32.2.2 skrll #else 1535 1.32.2.2 skrll MGETHDR(m, flags, type); 1536 1.32.2.7 skrll if (m != NULL && pktlen > MHLEN) { 1537 1.32.2.2 skrll MCLGET(m, flags); 1538 1.32.2.7 skrll if ((m->m_flags & M_EXT) == 0) { 1539 1.32.2.7 skrll m_free(m); 1540 1.32.2.7 skrll m = NULL; 1541 1.32.2.7 skrll } 1542 1.32.2.7 skrll } 1543 1.32.2.2 skrll #endif 1544 1.32.2.2 skrll return m; 1545 1.32.2.2 skrll } 1546 1.32.2.2 skrll 1547 1.32.2.2 skrll static int 1548 1.32.2.2 skrll ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1549 1.32.2.2 skrll { 1550 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1551 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 1552 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1553 1.32.2.2 skrll struct ieee80211_frame *wh; 1554 1.32.2.2 skrll struct ath_buf *bf; 1555 1.32.2.2 skrll struct ath_desc *ds; 1556 1.32.2.2 skrll struct mbuf *m; 1557 1.32.2.2 skrll int error, pktlen; 1558 1.32.2.2 skrll u_int8_t *frm, rate; 1559 1.32.2.2 skrll u_int16_t capinfo; 1560 1.32.2.2 skrll struct ieee80211_rateset *rs; 1561 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 1562 1.32.2.3 skrll u_int flags; 1563 1.32.2.2 skrll 1564 1.32.2.2 skrll bf = sc->sc_bcbuf; 1565 1.32.2.2 skrll if (bf->bf_m != NULL) { 1566 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1567 1.32.2.2 skrll m_freem(bf->bf_m); 1568 1.32.2.2 skrll bf->bf_m = NULL; 1569 1.32.2.2 skrll bf->bf_node = NULL; 1570 1.32.2.2 skrll } 1571 1.32.2.2 skrll /* 1572 1.32.2.2 skrll * NB: the beacon data buffer must be 32-bit aligned; 1573 1.32.2.2 skrll * we assume the mbuf routines will return us something 1574 1.32.2.2 skrll * with this alignment (perhaps should assert). 1575 1.32.2.2 skrll */ 1576 1.32.2.2 skrll rs = &ni->ni_rates; 1577 1.32.2.2 skrll pktlen = sizeof (struct ieee80211_frame) 1578 1.32.2.2 skrll + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 3 + 6; 1579 1.32.2.2 skrll if (rs->rs_nrates > IEEE80211_RATE_SIZE) 1580 1.32.2.2 skrll pktlen += 2; 1581 1.32.2.2 skrll m = ath_getmbuf(M_DONTWAIT, MT_DATA, pktlen); 1582 1.32.2.2 skrll if (m == NULL) { 1583 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON, 1584 1.32.2.2 skrll ("%s: cannot get mbuf/cluster; size %u\n", 1585 1.32.2.2 skrll __func__, pktlen)); 1586 1.32.2.2 skrll sc->sc_stats.ast_be_nombuf++; 1587 1.32.2.2 skrll return ENOMEM; 1588 1.32.2.2 skrll } 1589 1.32.2.2 skrll 1590 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1591 1.32.2.2 skrll wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1592 1.32.2.2 skrll IEEE80211_FC0_SUBTYPE_BEACON; 1593 1.32.2.2 skrll wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1594 1.32.2.2 skrll *(u_int16_t *)wh->i_dur = 0; 1595 1.32.2.2 skrll memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1596 1.32.2.2 skrll memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1597 1.32.2.2 skrll memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1598 1.32.2.2 skrll *(u_int16_t *)wh->i_seq = 0; 1599 1.32.2.2 skrll 1600 1.32.2.2 skrll /* 1601 1.32.2.2 skrll * beacon frame format 1602 1.32.2.2 skrll * [8] time stamp 1603 1.32.2.2 skrll * [2] beacon interval 1604 1.32.2.2 skrll * [2] cabability information 1605 1.32.2.2 skrll * [tlv] ssid 1606 1.32.2.2 skrll * [tlv] supported rates 1607 1.32.2.2 skrll * [tlv] parameter set (IBSS) 1608 1.32.2.2 skrll * [tlv] extended supported rates 1609 1.32.2.2 skrll */ 1610 1.32.2.2 skrll frm = (u_int8_t *)&wh[1]; 1611 1.32.2.2 skrll memset(frm, 0, 8); /* timestamp is set by hardware */ 1612 1.32.2.2 skrll frm += 8; 1613 1.32.2.2 skrll *(u_int16_t *)frm = htole16(ni->ni_intval); 1614 1.32.2.2 skrll frm += 2; 1615 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) 1616 1.32.2.2 skrll capinfo = IEEE80211_CAPINFO_IBSS; 1617 1.32.2.2 skrll else 1618 1.32.2.2 skrll capinfo = IEEE80211_CAPINFO_ESS; 1619 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) 1620 1.32.2.2 skrll capinfo |= IEEE80211_CAPINFO_PRIVACY; 1621 1.32.2.2 skrll if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1622 1.32.2.2 skrll IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 1623 1.32.2.2 skrll capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1624 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_SHSLOT) 1625 1.32.2.2 skrll capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1626 1.32.2.2 skrll *(u_int16_t *)frm = htole16(capinfo); 1627 1.32.2.2 skrll frm += 2; 1628 1.32.2.2 skrll *frm++ = IEEE80211_ELEMID_SSID; 1629 1.32.2.2 skrll *frm++ = ni->ni_esslen; 1630 1.32.2.2 skrll memcpy(frm, ni->ni_essid, ni->ni_esslen); 1631 1.32.2.2 skrll frm += ni->ni_esslen; 1632 1.32.2.2 skrll frm = ieee80211_add_rates(frm, rs); 1633 1.32.2.2 skrll *frm++ = IEEE80211_ELEMID_DSPARMS; 1634 1.32.2.2 skrll *frm++ = 1; 1635 1.32.2.2 skrll *frm++ = ieee80211_chan2ieee(ic, ni->ni_chan); 1636 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) { 1637 1.32.2.2 skrll *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1638 1.32.2.2 skrll *frm++ = 2; 1639 1.32.2.2 skrll *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1640 1.32.2.2 skrll } else { 1641 1.32.2.2 skrll /* TODO: TIM */ 1642 1.32.2.2 skrll *frm++ = IEEE80211_ELEMID_TIM; 1643 1.32.2.2 skrll *frm++ = 4; /* length */ 1644 1.32.2.10 skrll *frm++ = 0; /* DTIM count */ 1645 1.32.2.2 skrll *frm++ = 1; /* DTIM period */ 1646 1.32.2.2 skrll *frm++ = 0; /* bitmap control */ 1647 1.32.2.2 skrll *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1648 1.32.2.2 skrll } 1649 1.32.2.2 skrll frm = ieee80211_add_xrates(frm, rs); 1650 1.32.2.2 skrll m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1651 1.32.2.2 skrll KASSERT(m->m_pkthdr.len <= pktlen, 1652 1.32.2.2 skrll ("beacon bigger than expected, len %u calculated %u", 1653 1.32.2.2 skrll m->m_pkthdr.len, pktlen)); 1654 1.32.2.2 skrll 1655 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON, ("%s: m %p len %u\n", __func__, m, m->m_len)); 1656 1.32.2.2 skrll error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m, BUS_DMA_NOWAIT); 1657 1.32.2.2 skrll if (error != 0) { 1658 1.32.2.2 skrll m_freem(m); 1659 1.32.2.2 skrll return error; 1660 1.32.2.2 skrll } 1661 1.32.2.2 skrll KASSERT(bf->bf_nseg == 1, 1662 1.32.2.2 skrll ("%s: multi-segment packet; nseg %u", __func__, bf->bf_nseg)); 1663 1.32.2.2 skrll bf->bf_m = m; 1664 1.32.2.2 skrll 1665 1.32.2.2 skrll /* setup descriptors */ 1666 1.32.2.2 skrll ds = bf->bf_desc; 1667 1.32.2.2 skrll 1668 1.32.2.3 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) 1669 1.32.2.3 skrll ds->ds_link = bf->bf_daddr; /* link to self */ 1670 1.32.2.3 skrll else 1671 1.32.2.3 skrll ds->ds_link = 0; 1672 1.32.2.2 skrll ds->ds_data = bf->bf_segs[0].ds_addr; 1673 1.32.2.2 skrll 1674 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: segaddr %p seglen %u\n", __func__, 1675 1.32.2.2 skrll (caddr_t)bf->bf_segs[0].ds_addr, (u_int)bf->bf_segs[0].ds_len)); 1676 1.32.2.2 skrll 1677 1.32.2.2 skrll /* 1678 1.32.2.2 skrll * Calculate rate code. 1679 1.32.2.2 skrll * XXX everything at min xmit rate 1680 1.32.2.2 skrll */ 1681 1.32.2.2 skrll rt = sc->sc_currates; 1682 1.32.2.2 skrll KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1683 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1684 1.32.2.2 skrll rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1685 1.32.2.2 skrll else 1686 1.32.2.2 skrll rate = rt->info[0].rateCode; 1687 1.32.2.3 skrll 1688 1.32.2.3 skrll flags = HAL_TXDESC_NOACK; 1689 1.32.2.3 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) 1690 1.32.2.3 skrll flags |= HAL_TXDESC_VEOL; 1691 1.32.2.3 skrll 1692 1.32.2.2 skrll if (!ath_hal_setuptxdesc(ah, ds 1693 1.32.2.2 skrll , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1694 1.32.2.2 skrll , sizeof(struct ieee80211_frame) /* header length */ 1695 1.32.2.2 skrll , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1696 1.32.2.2 skrll , 0x20 /* txpower XXX */ 1697 1.32.2.2 skrll , rate, 1 /* series 0 rate/tries */ 1698 1.32.2.2 skrll , HAL_TXKEYIX_INVALID /* no encryption */ 1699 1.32.2.2 skrll , 0 /* antenna mode */ 1700 1.32.2.3 skrll , flags /* no ack for beacons */ 1701 1.32.2.2 skrll , 0 /* rts/cts rate */ 1702 1.32.2.2 skrll , 0 /* rts/cts duration */ 1703 1.32.2.2 skrll )) { 1704 1.32.2.2 skrll printf("%s: ath_hal_setuptxdesc failed\n", __func__); 1705 1.32.2.2 skrll return -1; 1706 1.32.2.2 skrll } 1707 1.32.2.2 skrll /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1708 1.32.2.2 skrll /* XXX verify mbuf data area covers this roundup */ 1709 1.32.2.2 skrll if (!ath_hal_filltxdesc(ah, ds 1710 1.32.2.2 skrll , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1711 1.32.2.2 skrll , AH_TRUE /* first segment */ 1712 1.32.2.2 skrll , AH_TRUE /* last segment */ 1713 1.32.2.2 skrll )) { 1714 1.32.2.2 skrll printf("%s: ath_hal_filltxdesc failed\n", __func__); 1715 1.32.2.2 skrll return -1; 1716 1.32.2.2 skrll } 1717 1.32.2.2 skrll 1718 1.32.2.2 skrll /* XXX it is not appropriate to bus_dmamap_sync? -dcy */ 1719 1.32.2.2 skrll 1720 1.32.2.2 skrll return 0; 1721 1.32.2.2 skrll } 1722 1.32.2.2 skrll 1723 1.32.2.2 skrll static void 1724 1.32.2.3 skrll ath_beacon_proc(struct ath_softc *sc, int pending) 1725 1.32.2.2 skrll { 1726 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1727 1.32.2.2 skrll struct ath_buf *bf = sc->sc_bcbuf; 1728 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1729 1.32.2.2 skrll 1730 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON_PROC, ("%s: pending %u\n", __func__, pending)); 1731 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA || 1732 1.32.2.2 skrll bf == NULL || bf->bf_m == NULL) { 1733 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: ic_flags=%x bf=%p bf_m=%p\n", 1734 1.32.2.2 skrll __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1735 1.32.2.2 skrll return; 1736 1.32.2.2 skrll } 1737 1.32.2.2 skrll /* TODO: update beacon to reflect PS poll state */ 1738 1.32.2.2 skrll if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1739 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: beacon queue %u did not stop?\n", 1740 1.32.2.2 skrll __func__, sc->sc_bhalq)); 1741 1.32.2.2 skrll /* NB: the HAL still stops DMA, so proceed */ 1742 1.32.2.2 skrll } 1743 1.32.2.2 skrll ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREWRITE); 1744 1.32.2.2 skrll 1745 1.32.2.2 skrll ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1746 1.32.2.2 skrll ath_hal_txstart(ah, sc->sc_bhalq); 1747 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON_PROC, 1748 1.32.2.2 skrll ("%s: TXDP%u = %p (%p)\n", __func__, 1749 1.32.2.2 skrll sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1750 1.32.2.2 skrll } 1751 1.32.2.2 skrll 1752 1.32.2.2 skrll static void 1753 1.32.2.2 skrll ath_beacon_free(struct ath_softc *sc) 1754 1.32.2.2 skrll { 1755 1.32.2.2 skrll struct ath_buf *bf = sc->sc_bcbuf; 1756 1.32.2.2 skrll 1757 1.32.2.2 skrll if (bf->bf_m != NULL) { 1758 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1759 1.32.2.2 skrll m_freem(bf->bf_m); 1760 1.32.2.2 skrll bf->bf_m = NULL; 1761 1.32.2.2 skrll bf->bf_node = NULL; 1762 1.32.2.2 skrll } 1763 1.32.2.2 skrll } 1764 1.32.2.2 skrll 1765 1.32.2.2 skrll /* 1766 1.32.2.2 skrll * Configure the beacon and sleep timers. 1767 1.32.2.2 skrll * 1768 1.32.2.2 skrll * When operating as an AP this resets the TSF and sets 1769 1.32.2.2 skrll * up the hardware to notify us when we need to issue beacons. 1770 1.32.2.2 skrll * 1771 1.32.2.2 skrll * When operating in station mode this sets up the beacon 1772 1.32.2.2 skrll * timers according to the timestamp of the last received 1773 1.32.2.2 skrll * beacon and the current TSF, configures PCF and DTIM 1774 1.32.2.2 skrll * handling, programs the sleep registers so the hardware 1775 1.32.2.2 skrll * will wakeup in time to receive beacons, and configures 1776 1.32.2.2 skrll * the beacon miss handling so we'll receive a BMISS 1777 1.32.2.2 skrll * interrupt when we stop seeing beacons from the AP 1778 1.32.2.2 skrll * we've associated with. 1779 1.32.2.2 skrll */ 1780 1.32.2.2 skrll static void 1781 1.32.2.2 skrll ath_beacon_config(struct ath_softc *sc) 1782 1.32.2.2 skrll { 1783 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1784 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1785 1.32.2.2 skrll struct ieee80211_node *ni = ic->ic_bss; 1786 1.32.2.2 skrll u_int32_t nexttbtt, intval; 1787 1.32.2.2 skrll 1788 1.32.2.2 skrll nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1789 1.32.2.2 skrll (LE_READ_4(ni->ni_tstamp) >> 10); 1790 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON, ("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1791 1.32.2.2 skrll nexttbtt += ni->ni_intval; 1792 1.32.2.2 skrll intval = ni->ni_intval & HAL_BEACON_PERIOD; 1793 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA) { 1794 1.32.2.2 skrll HAL_BEACON_STATE bs; 1795 1.32.2.2 skrll u_int32_t bmisstime; 1796 1.32.2.2 skrll 1797 1.32.2.2 skrll /* NB: no PCF support right now */ 1798 1.32.2.2 skrll memset(&bs, 0, sizeof(bs)); 1799 1.32.2.2 skrll /* 1800 1.32.2.2 skrll * Reset our tsf so the hardware will update the 1801 1.32.2.2 skrll * tsf register to reflect timestamps found in 1802 1.32.2.2 skrll * received beacons. 1803 1.32.2.2 skrll */ 1804 1.32.2.2 skrll bs.bs_intval = intval | HAL_BEACON_RESET_TSF; 1805 1.32.2.2 skrll bs.bs_nexttbtt = nexttbtt; 1806 1.32.2.2 skrll bs.bs_dtimperiod = bs.bs_intval; 1807 1.32.2.2 skrll bs.bs_nextdtim = nexttbtt; 1808 1.32.2.2 skrll /* 1809 1.32.2.2 skrll * Calculate the number of consecutive beacons to miss 1810 1.32.2.2 skrll * before taking a BMISS interrupt. The configuration 1811 1.32.2.2 skrll * is specified in ms, so we need to convert that to 1812 1.32.2.2 skrll * TU's and then calculate based on the beacon interval. 1813 1.32.2.2 skrll * Note that we clamp the result to at most 10 beacons. 1814 1.32.2.2 skrll */ 1815 1.32.2.2 skrll bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1816 1.32.2.2 skrll bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1817 1.32.2.2 skrll if (bs.bs_bmissthreshold > 10) 1818 1.32.2.2 skrll bs.bs_bmissthreshold = 10; 1819 1.32.2.2 skrll else if (bs.bs_bmissthreshold <= 0) 1820 1.32.2.2 skrll bs.bs_bmissthreshold = 1; 1821 1.32.2.2 skrll 1822 1.32.2.2 skrll /* 1823 1.32.2.2 skrll * Calculate sleep duration. The configuration is 1824 1.32.2.2 skrll * given in ms. We insure a multiple of the beacon 1825 1.32.2.2 skrll * period is used. Also, if the sleep duration is 1826 1.32.2.2 skrll * greater than the DTIM period then it makes senses 1827 1.32.2.2 skrll * to make it a multiple of that. 1828 1.32.2.2 skrll * 1829 1.32.2.2 skrll * XXX fixed at 100ms 1830 1.32.2.2 skrll */ 1831 1.32.2.2 skrll bs.bs_sleepduration = 1832 1.32.2.2 skrll roundup((100 * 1000) / 1024, bs.bs_intval); 1833 1.32.2.2 skrll if (bs.bs_sleepduration > bs.bs_dtimperiod) 1834 1.32.2.2 skrll bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1835 1.32.2.2 skrll 1836 1.32.2.10 skrll DPRINTF(ATH_DEBUG_BEACON, 1837 1.32.2.2 skrll ("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1838 1.32.2.2 skrll , __func__ 1839 1.32.2.2 skrll , bs.bs_intval 1840 1.32.2.2 skrll , bs.bs_nexttbtt 1841 1.32.2.2 skrll , bs.bs_dtimperiod 1842 1.32.2.2 skrll , bs.bs_nextdtim 1843 1.32.2.2 skrll , bs.bs_bmissthreshold 1844 1.32.2.2 skrll , bs.bs_sleepduration 1845 1.32.2.2 skrll )); 1846 1.32.2.2 skrll ath_hal_intrset(ah, 0); 1847 1.32.2.2 skrll ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1848 1.32.2.2 skrll sc->sc_imask |= HAL_INT_BMISS; 1849 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 1850 1.32.2.2 skrll } else { 1851 1.32.2.3 skrll ath_hal_intrset(ah, 0); 1852 1.32.2.3 skrll sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1853 1.32.2.3 skrll intval |= HAL_BEACON_ENA; 1854 1.32.2.3 skrll switch (ic->ic_opmode) { 1855 1.32.2.3 skrll /* No beacons in monitor, ad hoc-demo modes. */ 1856 1.32.2.3 skrll case IEEE80211_M_MONITOR: 1857 1.32.2.3 skrll case IEEE80211_M_AHDEMO: 1858 1.32.2.3 skrll intval &= ~HAL_BEACON_ENA; 1859 1.32.2.3 skrll /*FALLTHROUGH*/ 1860 1.32.2.3 skrll /* In IBSS mode, I am uncertain how SWBA interrupts 1861 1.32.2.3 skrll * work, so I just turn them off and use a self-linked 1862 1.32.2.3 skrll * descriptor. 1863 1.32.2.3 skrll */ 1864 1.32.2.3 skrll case IEEE80211_M_IBSS: 1865 1.32.2.3 skrll sc->sc_imask &= ~HAL_INT_SWBA; 1866 1.32.2.3 skrll nexttbtt = ni->ni_intval; 1867 1.32.2.3 skrll /*FALLTHROUGH*/ 1868 1.32.2.3 skrll case IEEE80211_M_HOSTAP: 1869 1.32.2.3 skrll default: 1870 1.32.2.3 skrll if (nexttbtt == ni->ni_intval) 1871 1.32.2.3 skrll intval |= HAL_BEACON_RESET_TSF; 1872 1.32.2.3 skrll break; 1873 1.32.2.3 skrll } 1874 1.32.2.2 skrll DPRINTF(ATH_DEBUG_BEACON, ("%s: intval %u nexttbtt %u\n", 1875 1.32.2.2 skrll __func__, ni->ni_intval, nexttbtt)); 1876 1.32.2.3 skrll ath_hal_beaconinit(ah, nexttbtt, intval); 1877 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 1878 1.32.2.3 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) 1879 1.32.2.3 skrll ath_beacon_proc(sc, 0); 1880 1.32.2.2 skrll } 1881 1.32.2.2 skrll } 1882 1.32.2.2 skrll 1883 1.32.2.2 skrll #ifdef __FreeBSD__ 1884 1.32.2.2 skrll static void 1885 1.32.2.2 skrll ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1886 1.32.2.2 skrll { 1887 1.32.2.2 skrll bus_addr_t *paddr = (bus_addr_t*) arg; 1888 1.32.2.2 skrll *paddr = segs->ds_addr; 1889 1.32.2.2 skrll } 1890 1.32.2.2 skrll #endif 1891 1.32.2.2 skrll 1892 1.32.2.2 skrll #ifdef __FreeBSD__ 1893 1.32.2.2 skrll static int 1894 1.32.2.2 skrll ath_desc_alloc(struct ath_softc *sc) 1895 1.32.2.2 skrll { 1896 1.32.2.2 skrll int i, bsize, error; 1897 1.32.2.2 skrll struct ath_desc *ds; 1898 1.32.2.2 skrll struct ath_buf *bf; 1899 1.32.2.2 skrll 1900 1.32.2.2 skrll /* allocate descriptors */ 1901 1.32.2.2 skrll sc->sc_desc_len = sizeof(struct ath_desc) * 1902 1.32.2.2 skrll (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1903 1.32.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1904 1.32.2.2 skrll if (error != 0) 1905 1.32.2.2 skrll return error; 1906 1.32.2.2 skrll 1907 1.32.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1908 1.32.2.2 skrll BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1909 1.32.2.2 skrll 1910 1.32.2.2 skrll if (error != 0) 1911 1.32.2.2 skrll goto fail0; 1912 1.32.2.2 skrll 1913 1.32.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1914 1.32.2.2 skrll sc->sc_desc, sc->sc_desc_len, 1915 1.32.2.2 skrll ath_load_cb, &sc->sc_desc_paddr, 1916 1.32.2.2 skrll BUS_DMA_NOWAIT); 1917 1.32.2.2 skrll if (error != 0) 1918 1.32.2.2 skrll goto fail1; 1919 1.32.2.2 skrll 1920 1.32.2.2 skrll ds = sc->sc_desc; 1921 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: DMA map: %p (%lu) -> %p (%lu)\n", 1922 1.32.2.2 skrll __func__, ds, (u_long) sc->sc_desc_len, (caddr_t) sc->sc_desc_paddr, 1923 1.32.2.2 skrll /*XXX*/ (u_long) sc->sc_desc_len)); 1924 1.32.2.2 skrll 1925 1.32.2.2 skrll /* allocate buffers */ 1926 1.32.2.2 skrll bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1927 1.32.2.2 skrll bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1928 1.32.2.2 skrll if (bf == NULL) { 1929 1.32.2.2 skrll printf("%s: unable to allocate Tx/Rx buffers\n", 1930 1.32.2.2 skrll sc->sc_dev.dv_xname); 1931 1.32.2.2 skrll error = -1; 1932 1.32.2.2 skrll goto fail2; 1933 1.32.2.2 skrll } 1934 1.32.2.2 skrll sc->sc_bufptr = bf; 1935 1.32.2.2 skrll 1936 1.32.2.2 skrll TAILQ_INIT(&sc->sc_rxbuf); 1937 1.32.2.2 skrll for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1938 1.32.2.2 skrll bf->bf_desc = ds; 1939 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + 1940 1.32.2.2 skrll ((caddr_t)ds - (caddr_t)sc->sc_desc); 1941 1.32.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1942 1.32.2.2 skrll &bf->bf_dmamap); 1943 1.32.2.2 skrll if (error != 0) 1944 1.32.2.2 skrll break; 1945 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1946 1.32.2.2 skrll } 1947 1.32.2.2 skrll 1948 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txbuf); 1949 1.32.2.2 skrll for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1950 1.32.2.2 skrll bf->bf_desc = ds; 1951 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + 1952 1.32.2.2 skrll ((caddr_t)ds - (caddr_t)sc->sc_desc); 1953 1.32.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1954 1.32.2.2 skrll &bf->bf_dmamap); 1955 1.32.2.2 skrll if (error != 0) 1956 1.32.2.2 skrll break; 1957 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1958 1.32.2.2 skrll } 1959 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txq); 1960 1.32.2.2 skrll 1961 1.32.2.2 skrll /* beacon buffer */ 1962 1.32.2.2 skrll bf->bf_desc = ds; 1963 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1964 1.32.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1965 1.32.2.2 skrll if (error != 0) 1966 1.32.2.2 skrll return error; 1967 1.32.2.2 skrll sc->sc_bcbuf = bf; 1968 1.32.2.2 skrll return 0; 1969 1.32.2.2 skrll 1970 1.32.2.2 skrll fail2: 1971 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1972 1.32.2.2 skrll fail1: 1973 1.32.2.2 skrll bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1974 1.32.2.2 skrll fail0: 1975 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1976 1.32.2.2 skrll sc->sc_ddmamap = NULL; 1977 1.32.2.2 skrll return error; 1978 1.32.2.2 skrll } 1979 1.32.2.2 skrll #else 1980 1.32.2.2 skrll static int 1981 1.32.2.2 skrll ath_desc_alloc(struct ath_softc *sc) 1982 1.32.2.2 skrll { 1983 1.32.2.2 skrll int i, bsize, error = -1; 1984 1.32.2.2 skrll struct ath_desc *ds; 1985 1.32.2.2 skrll struct ath_buf *bf; 1986 1.32.2.2 skrll 1987 1.32.2.2 skrll /* allocate descriptors */ 1988 1.32.2.2 skrll sc->sc_desc_len = sizeof(struct ath_desc) * 1989 1.32.2.2 skrll (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1990 1.32.2.2 skrll if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_desc_len, PAGE_SIZE, 1991 1.32.2.2 skrll 0, &sc->sc_dseg, 1, &sc->sc_dnseg, 0)) != 0) { 1992 1.32.2.2 skrll printf("%s: unable to allocate control data, error = %d\n", 1993 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 1994 1.32.2.2 skrll goto fail0; 1995 1.32.2.2 skrll } 1996 1.32.2.2 skrll 1997 1.32.2.2 skrll if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg, 1998 1.32.2.2 skrll sc->sc_desc_len, (caddr_t *)&sc->sc_desc, BUS_DMA_COHERENT)) != 0) { 1999 1.32.2.2 skrll printf("%s: unable to map control data, error = %d\n", 2000 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 2001 1.32.2.2 skrll goto fail1; 2002 1.32.2.2 skrll } 2003 1.32.2.2 skrll 2004 1.32.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_desc_len, 1, 2005 1.32.2.2 skrll sc->sc_desc_len, 0, 0, &sc->sc_ddmamap)) != 0) { 2006 1.32.2.2 skrll printf("%s: unable to create control data DMA map, " 2007 1.32.2.2 skrll "error = %d\n", sc->sc_dev.dv_xname, error); 2008 1.32.2.2 skrll goto fail2; 2009 1.32.2.2 skrll } 2010 1.32.2.2 skrll 2011 1.32.2.2 skrll if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, sc->sc_desc, 2012 1.32.2.2 skrll sc->sc_desc_len, NULL, 0)) != 0) { 2013 1.32.2.2 skrll printf("%s: unable to load control data DMA map, error = %d\n", 2014 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 2015 1.32.2.2 skrll goto fail3; 2016 1.32.2.2 skrll } 2017 1.32.2.2 skrll 2018 1.32.2.2 skrll ds = sc->sc_desc; 2019 1.32.2.2 skrll sc->sc_desc_paddr = sc->sc_ddmamap->dm_segs[0].ds_addr; 2020 1.32.2.2 skrll 2021 1.32.2.2 skrll DPRINTF(ATH_DEBUG_XMIT_DESC|ATH_DEBUG_RECV_DESC, 2022 1.32.2.2 skrll ("ath_desc_alloc: DMA map: %p (%lu) -> %p (%lu)\n", 2023 1.32.2.2 skrll ds, (u_long)sc->sc_desc_len, 2024 1.32.2.2 skrll (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 2025 1.32.2.2 skrll 2026 1.32.2.2 skrll /* allocate buffers */ 2027 1.32.2.2 skrll bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 2028 1.32.2.2 skrll bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 2029 1.32.2.2 skrll if (bf == NULL) { 2030 1.32.2.2 skrll printf("%s: unable to allocate Tx/Rx buffers\n", 2031 1.32.2.2 skrll sc->sc_dev.dv_xname); 2032 1.32.2.2 skrll error = ENOMEM; 2033 1.32.2.2 skrll goto fail3; 2034 1.32.2.2 skrll } 2035 1.32.2.2 skrll sc->sc_bufptr = bf; 2036 1.32.2.2 skrll 2037 1.32.2.2 skrll TAILQ_INIT(&sc->sc_rxbuf); 2038 1.32.2.2 skrll for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 2039 1.32.2.2 skrll bf->bf_desc = ds; 2040 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + 2041 1.32.2.2 skrll ((caddr_t)ds - (caddr_t)sc->sc_desc); 2042 1.32.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 2043 1.32.2.2 skrll MCLBYTES, 0, 0, &bf->bf_dmamap)) != 0) { 2044 1.32.2.2 skrll printf("%s: unable to create Rx dmamap, error = %d\n", 2045 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 2046 1.32.2.2 skrll goto fail4; 2047 1.32.2.2 skrll } 2048 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2049 1.32.2.2 skrll } 2050 1.32.2.2 skrll 2051 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txbuf); 2052 1.32.2.2 skrll for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 2053 1.32.2.2 skrll bf->bf_desc = ds; 2054 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + 2055 1.32.2.2 skrll ((caddr_t)ds - (caddr_t)sc->sc_desc); 2056 1.32.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 2057 1.32.2.2 skrll ATH_TXDESC, MCLBYTES, 0, 0, &bf->bf_dmamap)) != 0) { 2058 1.32.2.2 skrll printf("%s: unable to create Tx dmamap, error = %d\n", 2059 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 2060 1.32.2.2 skrll goto fail5; 2061 1.32.2.2 skrll } 2062 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2063 1.32.2.2 skrll } 2064 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txq); 2065 1.32.2.2 skrll 2066 1.32.2.2 skrll /* beacon buffer */ 2067 1.32.2.2 skrll bf->bf_desc = ds; 2068 1.32.2.2 skrll bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 2069 1.32.2.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 2070 1.32.2.2 skrll &bf->bf_dmamap)) != 0) { 2071 1.32.2.2 skrll printf("%s: unable to create beacon dmamap, error = %d\n", 2072 1.32.2.2 skrll sc->sc_dev.dv_xname, error); 2073 1.32.2.2 skrll goto fail5; 2074 1.32.2.2 skrll } 2075 1.32.2.2 skrll sc->sc_bcbuf = bf; 2076 1.32.2.2 skrll return 0; 2077 1.32.2.2 skrll 2078 1.32.2.2 skrll fail5: 2079 1.32.2.2 skrll for (i = ATH_RXBUF; i < ATH_RXBUF + ATH_TXBUF; i++) { 2080 1.32.2.2 skrll if (sc->sc_bufptr[i].bf_dmamap == NULL) 2081 1.32.2.2 skrll continue; 2082 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufptr[i].bf_dmamap); 2083 1.32.2.2 skrll } 2084 1.32.2.2 skrll fail4: 2085 1.32.2.2 skrll for (i = 0; i < ATH_RXBUF; i++) { 2086 1.32.2.2 skrll if (sc->sc_bufptr[i].bf_dmamap == NULL) 2087 1.32.2.2 skrll continue; 2088 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufptr[i].bf_dmamap); 2089 1.32.2.2 skrll } 2090 1.32.2.2 skrll fail3: 2091 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 2092 1.32.2.2 skrll fail2: 2093 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 2094 1.32.2.2 skrll sc->sc_ddmamap = NULL; 2095 1.32.2.2 skrll fail1: 2096 1.32.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_desc, sc->sc_desc_len); 2097 1.32.2.2 skrll fail0: 2098 1.32.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 2099 1.32.2.2 skrll return error; 2100 1.32.2.2 skrll } 2101 1.32.2.2 skrll #endif 2102 1.32.2.2 skrll 2103 1.32.2.2 skrll static void 2104 1.32.2.2 skrll ath_desc_free(struct ath_softc *sc) 2105 1.32.2.2 skrll { 2106 1.32.2.2 skrll struct ath_buf *bf; 2107 1.32.2.2 skrll 2108 1.32.2.2 skrll #ifdef __FreeBSD__ 2109 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 2110 1.32.2.2 skrll bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 2111 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 2112 1.32.2.2 skrll #else 2113 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 2114 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 2115 1.32.2.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_dnseg); 2116 1.32.2.2 skrll #endif 2117 1.32.2.2 skrll 2118 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 2119 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2120 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2121 1.32.2.2 skrll m_freem(bf->bf_m); 2122 1.32.2.2 skrll } 2123 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 2124 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2125 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2126 1.32.2.2 skrll if (bf->bf_m) { 2127 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2128 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2129 1.32.2.2 skrll m_freem(bf->bf_m); 2130 1.32.2.2 skrll bf->bf_m = NULL; 2131 1.32.2.2 skrll } 2132 1.32.2.2 skrll } 2133 1.32.2.2 skrll if (sc->sc_bcbuf != NULL) { 2134 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 2135 1.32.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 2136 1.32.2.2 skrll sc->sc_bcbuf = NULL; 2137 1.32.2.2 skrll } 2138 1.32.2.2 skrll 2139 1.32.2.2 skrll TAILQ_INIT(&sc->sc_rxbuf); 2140 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txbuf); 2141 1.32.2.2 skrll TAILQ_INIT(&sc->sc_txq); 2142 1.32.2.2 skrll free(sc->sc_bufptr, M_DEVBUF); 2143 1.32.2.2 skrll sc->sc_bufptr = NULL; 2144 1.32.2.2 skrll } 2145 1.32.2.2 skrll 2146 1.32.2.2 skrll static struct ieee80211_node * 2147 1.32.2.2 skrll ath_node_alloc(struct ieee80211com *ic) 2148 1.32.2.2 skrll { 2149 1.32.2.2 skrll struct ath_node *an = 2150 1.32.2.2 skrll malloc(sizeof(struct ath_node), M_80211_NODE, M_NOWAIT|M_ZERO); 2151 1.32.2.2 skrll if (an) { 2152 1.32.2.2 skrll int i; 2153 1.32.2.2 skrll for (i = 0; i < ATH_RHIST_SIZE; i++) 2154 1.32.2.2 skrll an->an_rx_hist[i].arh_ticks = ATH_RHIST_NOTIME; 2155 1.32.2.2 skrll an->an_rx_hist_next = ATH_RHIST_SIZE-1; 2156 1.32.2.2 skrll return &an->an_node; 2157 1.32.2.2 skrll } else 2158 1.32.2.2 skrll return NULL; 2159 1.32.2.2 skrll } 2160 1.32.2.2 skrll 2161 1.32.2.2 skrll static void 2162 1.32.2.2 skrll ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 2163 1.32.2.2 skrll { 2164 1.32.2.2 skrll struct ath_softc *sc = ic->ic_if.if_softc; 2165 1.32.2.2 skrll struct ath_buf *bf; 2166 1.32.2.2 skrll 2167 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 2168 1.32.2.2 skrll if (bf->bf_node == ni) 2169 1.32.2.2 skrll bf->bf_node = NULL; 2170 1.32.2.2 skrll } 2171 1.32.2.2 skrll (*sc->sc_node_free)(ic, ni); 2172 1.32.2.2 skrll } 2173 1.32.2.2 skrll 2174 1.32.2.2 skrll static void 2175 1.32.2.2 skrll ath_node_copy(struct ieee80211com *ic, 2176 1.32.2.2 skrll struct ieee80211_node *dst, const struct ieee80211_node *src) 2177 1.32.2.2 skrll { 2178 1.32.2.2 skrll struct ath_softc *sc = ic->ic_if.if_softc; 2179 1.32.2.2 skrll 2180 1.32.2.2 skrll memcpy(&dst[1], &src[1], 2181 1.32.2.2 skrll sizeof(struct ath_node) - sizeof(struct ieee80211_node)); 2182 1.32.2.2 skrll (*sc->sc_node_copy)(ic, dst, src); 2183 1.32.2.2 skrll } 2184 1.32.2.2 skrll 2185 1.32.2.2 skrll static u_int8_t 2186 1.32.2.2 skrll ath_node_getrssi(struct ieee80211com *ic, struct ieee80211_node *ni) 2187 1.32.2.2 skrll { 2188 1.32.2.2 skrll struct ath_node *an = ATH_NODE(ni); 2189 1.32.2.2 skrll int i, now, nsamples, rssi; 2190 1.32.2.2 skrll 2191 1.32.2.2 skrll /* 2192 1.32.2.2 skrll * Calculate the average over the last second of sampled data. 2193 1.32.2.2 skrll */ 2194 1.32.2.2 skrll now = ATH_TICKS(); 2195 1.32.2.2 skrll nsamples = 0; 2196 1.32.2.2 skrll rssi = 0; 2197 1.32.2.2 skrll i = an->an_rx_hist_next; 2198 1.32.2.2 skrll do { 2199 1.32.2.2 skrll struct ath_recv_hist *rh = &an->an_rx_hist[i]; 2200 1.32.2.2 skrll if (rh->arh_ticks == ATH_RHIST_NOTIME) 2201 1.32.2.2 skrll goto done; 2202 1.32.2.2 skrll if (now - rh->arh_ticks > hz) 2203 1.32.2.2 skrll goto done; 2204 1.32.2.2 skrll rssi += rh->arh_rssi; 2205 1.32.2.2 skrll nsamples++; 2206 1.32.2.2 skrll if (i == 0) 2207 1.32.2.2 skrll i = ATH_RHIST_SIZE-1; 2208 1.32.2.2 skrll else 2209 1.32.2.2 skrll i--; 2210 1.32.2.2 skrll } while (i != an->an_rx_hist_next); 2211 1.32.2.2 skrll done: 2212 1.32.2.2 skrll /* 2213 1.32.2.2 skrll * Return either the average or the last known 2214 1.32.2.2 skrll * value if there is no recent data. 2215 1.32.2.2 skrll */ 2216 1.32.2.2 skrll return (nsamples ? rssi / nsamples : an->an_rx_hist[i].arh_rssi); 2217 1.32.2.2 skrll } 2218 1.32.2.2 skrll 2219 1.32.2.2 skrll static int 2220 1.32.2.2 skrll ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2221 1.32.2.2 skrll { 2222 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2223 1.32.2.2 skrll int error; 2224 1.32.2.2 skrll struct mbuf *m; 2225 1.32.2.2 skrll struct ath_desc *ds; 2226 1.32.2.2 skrll 2227 1.32.2.2 skrll m = bf->bf_m; 2228 1.32.2.2 skrll if (m == NULL) { 2229 1.32.2.2 skrll /* 2230 1.32.2.2 skrll * NB: by assigning a page to the rx dma buffer we 2231 1.32.2.2 skrll * implicitly satisfy the Atheros requirement that 2232 1.32.2.2 skrll * this buffer be cache-line-aligned and sized to be 2233 1.32.2.2 skrll * multiple of the cache line size. Not doing this 2234 1.32.2.2 skrll * causes weird stuff to happen (for the 5210 at least). 2235 1.32.2.2 skrll */ 2236 1.32.2.2 skrll m = ath_getmbuf(M_DONTWAIT, MT_DATA, MCLBYTES); 2237 1.32.2.2 skrll if (m == NULL) { 2238 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 2239 1.32.2.2 skrll ("%s: no mbuf/cluster\n", __func__)); 2240 1.32.2.2 skrll sc->sc_stats.ast_rx_nombuf++; 2241 1.32.2.2 skrll return ENOMEM; 2242 1.32.2.2 skrll } 2243 1.32.2.2 skrll bf->bf_m = m; 2244 1.32.2.2 skrll m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2245 1.32.2.2 skrll 2246 1.32.2.2 skrll error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m, 2247 1.32.2.2 skrll BUS_DMA_NOWAIT); 2248 1.32.2.2 skrll if (error != 0) { 2249 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 2250 1.32.2.2 skrll ("%s: ath_buf_dmamap_load_mbuf failed;" 2251 1.32.2.2 skrll " error %d\n", __func__, error)); 2252 1.32.2.2 skrll sc->sc_stats.ast_rx_busdma++; 2253 1.32.2.2 skrll return error; 2254 1.32.2.2 skrll } 2255 1.32.2.2 skrll KASSERT(bf->bf_nseg == 1, 2256 1.32.2.2 skrll ("ath_rxbuf_init: multi-segment packet; nseg %u", 2257 1.32.2.2 skrll bf->bf_nseg)); 2258 1.32.2.2 skrll } 2259 1.32.2.2 skrll ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREREAD); 2260 1.32.2.2 skrll 2261 1.32.2.2 skrll /* 2262 1.32.2.2 skrll * Setup descriptors. For receive we always terminate 2263 1.32.2.2 skrll * the descriptor list with a self-linked entry so we'll 2264 1.32.2.2 skrll * not get overrun under high load (as can happen with a 2265 1.32.2.2 skrll * 5212 when ANI processing enables PHY errors). 2266 1.32.2.2 skrll * 2267 1.32.2.2 skrll * To insure the last descriptor is self-linked we create 2268 1.32.2.2 skrll * each descriptor as self-linked and add it to the end. As 2269 1.32.2.2 skrll * each additional descriptor is added the previous self-linked 2270 1.32.2.2 skrll * entry is ``fixed'' naturally. This should be safe even 2271 1.32.2.2 skrll * if DMA is happening. When processing RX interrupts we 2272 1.32.2.2 skrll * never remove/process the last, self-linked, entry on the 2273 1.32.2.2 skrll * descriptor list. This insures the hardware always has 2274 1.32.2.2 skrll * someplace to write a new frame. 2275 1.32.2.2 skrll */ 2276 1.32.2.2 skrll ds = bf->bf_desc; 2277 1.32.2.2 skrll ds->ds_link = bf->bf_daddr; /* link to self */ 2278 1.32.2.2 skrll ds->ds_data = bf->bf_segs[0].ds_addr; 2279 1.32.2.2 skrll ath_hal_setuprxdesc(ah, ds 2280 1.32.2.2 skrll , m->m_len /* buffer size */ 2281 1.32.2.2 skrll , 0 2282 1.32.2.2 skrll ); 2283 1.32.2.2 skrll 2284 1.32.2.2 skrll if (sc->sc_rxlink != NULL) 2285 1.32.2.2 skrll *sc->sc_rxlink = bf->bf_daddr; 2286 1.32.2.2 skrll sc->sc_rxlink = &ds->ds_link; 2287 1.32.2.2 skrll return 0; 2288 1.32.2.2 skrll } 2289 1.32.2.2 skrll 2290 1.32.2.2 skrll static void 2291 1.32.2.2 skrll ath_rx_proc(void *arg, int npending) 2292 1.32.2.2 skrll { 2293 1.32.2.2 skrll #define PA2DESC(_sc, _pa) \ 2294 1.32.2.2 skrll ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ 2295 1.32.2.2 skrll ((_pa) - (_sc)->sc_desc_paddr))) 2296 1.32.2.2 skrll struct ath_softc *sc = arg; 2297 1.32.2.2 skrll struct ath_buf *bf; 2298 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2299 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 2300 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2301 1.32.2.2 skrll struct ath_desc *ds; 2302 1.32.2.2 skrll struct mbuf *m; 2303 1.32.2.2 skrll struct ieee80211_frame *wh, whbuf; 2304 1.32.2.2 skrll struct ieee80211_node *ni; 2305 1.32.2.2 skrll struct ath_node *an; 2306 1.32.2.2 skrll struct ath_recv_hist *rh; 2307 1.32.2.2 skrll int len; 2308 1.32.2.2 skrll u_int phyerr; 2309 1.32.2.2 skrll HAL_STATUS status; 2310 1.32.2.2 skrll 2311 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RX_PROC, ("%s: pending %u\n", __func__, npending)); 2312 1.32.2.2 skrll do { 2313 1.32.2.2 skrll bf = TAILQ_FIRST(&sc->sc_rxbuf); 2314 1.32.2.2 skrll if (bf == NULL) { /* NB: shouldn't happen */ 2315 1.32.2.2 skrll if_printf(ifp, "ath_rx_proc: no buffer!\n"); 2316 1.32.2.2 skrll break; 2317 1.32.2.2 skrll } 2318 1.32.2.2 skrll ds = bf->bf_desc; 2319 1.32.2.2 skrll if (ds->ds_link == bf->bf_daddr) { 2320 1.32.2.2 skrll /* NB: never process the self-linked entry at the end */ 2321 1.32.2.2 skrll break; 2322 1.32.2.2 skrll } 2323 1.32.2.2 skrll m = bf->bf_m; 2324 1.32.2.2 skrll if (m == NULL) { /* NB: shouldn't happen */ 2325 1.32.2.2 skrll if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 2326 1.32.2.2 skrll continue; 2327 1.32.2.2 skrll } 2328 1.32.2.2 skrll /* XXX sync descriptor memory */ 2329 1.32.2.2 skrll /* 2330 1.32.2.2 skrll * Must provide the virtual address of the current 2331 1.32.2.2 skrll * descriptor, the physical address, and the virtual 2332 1.32.2.2 skrll * address of the next descriptor in the h/w chain. 2333 1.32.2.2 skrll * This allows the HAL to look ahead to see if the 2334 1.32.2.2 skrll * hardware is done with a descriptor by checking the 2335 1.32.2.2 skrll * done bit in the following descriptor and the address 2336 1.32.2.2 skrll * of the current descriptor the DMA engine is working 2337 1.32.2.2 skrll * on. All this is necessary because of our use of 2338 1.32.2.2 skrll * a self-linked list to avoid rx overruns. 2339 1.32.2.2 skrll */ 2340 1.32.2.2 skrll status = ath_hal_rxprocdesc(ah, ds, 2341 1.32.2.2 skrll bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2342 1.32.2.2 skrll #ifdef AR_DEBUG 2343 1.32.2.2 skrll if (ath_debug & ATH_DEBUG_RECV_DESC) 2344 1.32.2.10 skrll ath_printrxbuf(bf, status == HAL_OK); 2345 1.32.2.2 skrll #endif 2346 1.32.2.2 skrll if (status == HAL_EINPROGRESS) 2347 1.32.2.2 skrll break; 2348 1.32.2.2 skrll TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 2349 1.32.2.3 skrll 2350 1.32.2.3 skrll if (ds->ds_rxstat.rs_more) { 2351 1.32.2.3 skrll /* 2352 1.32.2.3 skrll * Frame spans multiple descriptors; this 2353 1.32.2.3 skrll * cannot happen yet as we don't support 2354 1.32.2.3 skrll * jumbograms. If not in monitor mode, 2355 1.32.2.3 skrll * discard the frame. 2356 1.32.2.3 skrll */ 2357 1.32.2.3 skrll 2358 1.32.2.3 skrll /* enable this if you want to see error frames in Monitor mode */ 2359 1.32.2.3 skrll #ifdef ERROR_FRAMES 2360 1.32.2.3 skrll if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2361 1.32.2.3 skrll /* XXX statistic */ 2362 1.32.2.3 skrll goto rx_next; 2363 1.32.2.3 skrll } 2364 1.32.2.3 skrll #endif 2365 1.32.2.3 skrll /* fall thru for monitor mode handling... */ 2366 1.32.2.3 skrll 2367 1.32.2.3 skrll } else if (ds->ds_rxstat.rs_status != 0) { 2368 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2369 1.32.2.2 skrll sc->sc_stats.ast_rx_crcerr++; 2370 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2371 1.32.2.2 skrll sc->sc_stats.ast_rx_fifoerr++; 2372 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 2373 1.32.2.2 skrll sc->sc_stats.ast_rx_badcrypt++; 2374 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2375 1.32.2.2 skrll sc->sc_stats.ast_rx_phyerr++; 2376 1.32.2.2 skrll phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2377 1.32.2.2 skrll sc->sc_stats.ast_rx_phy[phyerr]++; 2378 1.32.2.2 skrll } 2379 1.32.2.3 skrll 2380 1.32.2.3 skrll /* 2381 1.32.2.3 skrll * reject error frames, we normally don't want 2382 1.32.2.3 skrll * to see them in monitor mode. 2383 1.32.2.3 skrll */ 2384 1.32.2.3 skrll if ((ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT ) || 2385 1.32.2.3 skrll (ds->ds_rxstat.rs_status & HAL_RXERR_PHY)) 2386 1.32.2.3 skrll goto rx_next; 2387 1.32.2.3 skrll 2388 1.32.2.3 skrll /* 2389 1.32.2.3 skrll * In monitor mode, allow through packets that 2390 1.32.2.3 skrll * cannot be decrypted 2391 1.32.2.3 skrll */ 2392 1.32.2.3 skrll if ((ds->ds_rxstat.rs_status & ~HAL_RXERR_DECRYPT) || 2393 1.32.2.3 skrll sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2394 1.32.2.3 skrll goto rx_next; 2395 1.32.2.2 skrll } 2396 1.32.2.2 skrll 2397 1.32.2.2 skrll len = ds->ds_rxstat.rs_datalen; 2398 1.32.2.2 skrll if (len < IEEE80211_MIN_LEN) { 2399 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RECV, ("%s: short packet %d\n", 2400 1.32.2.2 skrll __func__, len)); 2401 1.32.2.2 skrll sc->sc_stats.ast_rx_tooshort++; 2402 1.32.2.2 skrll goto rx_next; 2403 1.32.2.2 skrll } 2404 1.32.2.2 skrll 2405 1.32.2.2 skrll ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_POSTREAD); 2406 1.32.2.2 skrll 2407 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2408 1.32.2.2 skrll bf->bf_m = NULL; 2409 1.32.2.2 skrll m->m_pkthdr.rcvif = ifp; 2410 1.32.2.2 skrll m->m_pkthdr.len = m->m_len = len; 2411 1.32.2.2 skrll 2412 1.32.2.2 skrll #if NBPFILTER > 0 2413 1.32.2.2 skrll if (sc->sc_drvbpf) { 2414 1.32.2.2 skrll sc->sc_rx_th.wr_rate = 2415 1.32.2.2 skrll sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 2416 1.32.2.2 skrll sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2417 1.32.2.2 skrll sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2418 1.32.2.2 skrll /* XXX TSF */ 2419 1.32.2.2 skrll bpf_mtap2(sc->sc_drvbpf, 2420 1.32.2.2 skrll &sc->sc_rx_th, sc->sc_rx_th_len, m); 2421 1.32.2.2 skrll } 2422 1.32.2.2 skrll #endif 2423 1.32.2.2 skrll 2424 1.32.2.2 skrll m_adj(m, -IEEE80211_CRC_LEN); 2425 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 2426 1.32.2.2 skrll if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2427 1.32.2.2 skrll /* 2428 1.32.2.2 skrll * WEP is decrypted by hardware. Clear WEP bit 2429 1.32.2.2 skrll * and trim WEP header for ieee80211_input(). 2430 1.32.2.2 skrll */ 2431 1.32.2.2 skrll wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2432 1.32.2.2 skrll memcpy(&whbuf, wh, sizeof(whbuf)); 2433 1.32.2.2 skrll m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 2434 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 2435 1.32.2.2 skrll memcpy(wh, &whbuf, sizeof(whbuf)); 2436 1.32.2.2 skrll /* 2437 1.32.2.2 skrll * Also trim WEP ICV from the tail. 2438 1.32.2.2 skrll */ 2439 1.32.2.2 skrll m_adj(m, -IEEE80211_WEP_CRCLEN); 2440 1.32.2.2 skrll /* 2441 1.32.2.2 skrll * The header has probably moved. 2442 1.32.2.2 skrll */ 2443 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 2444 1.32.2.2 skrll } 2445 1.32.2.2 skrll 2446 1.32.2.2 skrll /* 2447 1.32.2.2 skrll * Locate the node for sender, track state, and 2448 1.32.2.2 skrll * then pass this node (referenced) up to the 802.11 2449 1.32.2.3 skrll * layer for its use. 2450 1.32.2.2 skrll */ 2451 1.32.2.2 skrll ni = ieee80211_find_rxnode(ic, wh); 2452 1.32.2.2 skrll 2453 1.32.2.2 skrll /* 2454 1.32.2.2 skrll * Record driver-specific state. 2455 1.32.2.2 skrll */ 2456 1.32.2.2 skrll an = ATH_NODE(ni); 2457 1.32.2.2 skrll if (++(an->an_rx_hist_next) == ATH_RHIST_SIZE) 2458 1.32.2.2 skrll an->an_rx_hist_next = 0; 2459 1.32.2.2 skrll rh = &an->an_rx_hist[an->an_rx_hist_next]; 2460 1.32.2.2 skrll rh->arh_ticks = ATH_TICKS(); 2461 1.32.2.2 skrll rh->arh_rssi = ds->ds_rxstat.rs_rssi; 2462 1.32.2.2 skrll rh->arh_antenna = ds->ds_rxstat.rs_antenna; 2463 1.32.2.2 skrll 2464 1.32.2.2 skrll /* 2465 1.32.2.2 skrll * Send frame up for processing. 2466 1.32.2.2 skrll */ 2467 1.32.2.2 skrll ieee80211_input(ifp, m, ni, 2468 1.32.2.2 skrll ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2469 1.32.2.2 skrll 2470 1.32.2.2 skrll /* 2471 1.32.2.2 skrll * The frame may have caused the node to be marked for 2472 1.32.2.2 skrll * reclamation (e.g. in response to a DEAUTH message) 2473 1.32.2.3 skrll * so use release_node here instead of unref_node. 2474 1.32.2.2 skrll */ 2475 1.32.2.3 skrll ieee80211_release_node(ic, ni); 2476 1.32.2.2 skrll rx_next: 2477 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2478 1.32.2.2 skrll } while (ath_rxbuf_init(sc, bf) == 0); 2479 1.32.2.2 skrll 2480 1.32.2.2 skrll ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 2481 1.32.2.2 skrll ath_hal_rxena(ah); /* in case of RXEOL */ 2482 1.32.2.2 skrll 2483 1.32.2.2 skrll #ifdef __NetBSD__ 2484 1.32.2.2 skrll if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 2485 1.32.2.2 skrll ath_start(ifp); 2486 1.32.2.2 skrll #endif /* __NetBSD__ */ 2487 1.32.2.2 skrll #undef PA2DESC 2488 1.32.2.2 skrll } 2489 1.32.2.2 skrll 2490 1.32.2.2 skrll /* 2491 1.32.2.2 skrll * XXX Size of an ACK control frame in bytes. 2492 1.32.2.2 skrll */ 2493 1.32.2.2 skrll #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 2494 1.32.2.2 skrll 2495 1.32.2.2 skrll static int 2496 1.32.2.2 skrll ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 2497 1.32.2.2 skrll struct mbuf *m0) 2498 1.32.2.2 skrll { 2499 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2500 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2501 1.32.2.2 skrll struct ifnet *ifp = &sc->sc_ic.ic_if; 2502 1.32.2.2 skrll int i, error, iswep, hdrlen, pktlen; 2503 1.32.2.2 skrll u_int8_t rix, cix, txrate, ctsrate; 2504 1.32.2.2 skrll struct ath_desc *ds; 2505 1.32.2.2 skrll struct mbuf *m; 2506 1.32.2.2 skrll struct ieee80211_frame *wh; 2507 1.32.2.2 skrll u_int32_t iv; 2508 1.32.2.2 skrll u_int8_t *ivp; 2509 1.32.2.2 skrll u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 2510 1.32.2.2 skrll IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 2511 1.32.2.2 skrll u_int subtype, flags, ctsduration, antenna; 2512 1.32.2.2 skrll HAL_PKT_TYPE atype; 2513 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 2514 1.32.2.2 skrll HAL_BOOL shortPreamble; 2515 1.32.2.2 skrll struct ath_node *an; 2516 1.32.2.2 skrll ath_txq_critsect_decl(s); 2517 1.32.2.2 skrll 2518 1.32.2.2 skrll wh = mtod(m0, struct ieee80211_frame *); 2519 1.32.2.2 skrll iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 2520 1.32.2.2 skrll hdrlen = sizeof(struct ieee80211_frame); 2521 1.32.2.2 skrll pktlen = m0->m_pkthdr.len; 2522 1.32.2.2 skrll 2523 1.32.2.2 skrll if (iswep) { 2524 1.32.2.2 skrll memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 2525 1.32.2.2 skrll m_adj(m0, hdrlen); 2526 1.32.2.2 skrll M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 2527 1.32.2.2 skrll if (m0 == NULL) { 2528 1.32.2.2 skrll sc->sc_stats.ast_tx_nombuf++; 2529 1.32.2.2 skrll return ENOMEM; 2530 1.32.2.2 skrll } 2531 1.32.2.2 skrll ivp = hdrbuf + hdrlen; 2532 1.32.2.2 skrll wh = mtod(m0, struct ieee80211_frame *); 2533 1.32.2.2 skrll /* 2534 1.32.2.2 skrll * XXX 2535 1.32.2.2 skrll * IV must not duplicate during the lifetime of the key. 2536 1.32.2.2 skrll * But no mechanism to renew keys is defined in IEEE 802.11 2537 1.32.2.3 skrll * for WEP. And the IV may be duplicated at other stations 2538 1.32.2.3 skrll * because the session key itself is shared. So we use a 2539 1.32.2.3 skrll * pseudo random IV for now, though it is not the right way. 2540 1.32.2.3 skrll * 2541 1.32.2.3 skrll * NB: Rather than use a strictly random IV we select a 2542 1.32.2.3 skrll * random one to start and then increment the value for 2543 1.32.2.3 skrll * each frame. This is an explicit tradeoff between 2544 1.32.2.3 skrll * overhead and security. Given the basic insecurity of 2545 1.32.2.3 skrll * WEP this seems worthwhile. 2546 1.32.2.2 skrll */ 2547 1.32.2.3 skrll 2548 1.32.2.2 skrll /* 2549 1.32.2.2 skrll * Skip 'bad' IVs from Fluhrer/Mantin/Shamir: 2550 1.32.2.3 skrll * (B, 255, N) with 3 <= B < 16 and 0 <= N <= 255 2551 1.32.2.2 skrll */ 2552 1.32.2.3 skrll iv = ic->ic_iv; 2553 1.32.2.3 skrll if ((iv & 0xff00) == 0xff00) { 2554 1.32.2.3 skrll int B = (iv & 0xff0000) >> 16; 2555 1.32.2.3 skrll if (3 <= B && B < 16) 2556 1.32.2.3 skrll iv = (B+1) << 16; 2557 1.32.2.2 skrll } 2558 1.32.2.3 skrll ic->ic_iv = iv + 1; 2559 1.32.2.3 skrll 2560 1.32.2.3 skrll /* 2561 1.32.2.3 skrll * NB: Preserve byte order of IV for packet 2562 1.32.2.3 skrll * sniffers; it doesn't matter otherwise. 2563 1.32.2.3 skrll */ 2564 1.32.2.3 skrll #if AH_BYTE_ORDER == AH_BIG_ENDIAN 2565 1.32.2.3 skrll ivp[0] = iv >> 0; 2566 1.32.2.3 skrll ivp[1] = iv >> 8; 2567 1.32.2.3 skrll ivp[2] = iv >> 16; 2568 1.32.2.3 skrll #else 2569 1.32.2.3 skrll ivp[2] = iv >> 0; 2570 1.32.2.3 skrll ivp[1] = iv >> 8; 2571 1.32.2.3 skrll ivp[0] = iv >> 16; 2572 1.32.2.3 skrll #endif 2573 1.32.2.3 skrll ivp[3] = ic->ic_wep_txkey << 6; /* Key ID and pad */ 2574 1.32.2.2 skrll memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 2575 1.32.2.2 skrll /* 2576 1.32.2.2 skrll * The ICV length must be included into hdrlen and pktlen. 2577 1.32.2.2 skrll */ 2578 1.32.2.2 skrll hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 2579 1.32.2.2 skrll pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 2580 1.32.2.2 skrll } 2581 1.32.2.2 skrll pktlen += IEEE80211_CRC_LEN; 2582 1.32.2.2 skrll 2583 1.32.2.2 skrll /* 2584 1.32.2.2 skrll * Load the DMA map so any coalescing is done. This 2585 1.32.2.2 skrll * also calculates the number of descriptors we need. 2586 1.32.2.2 skrll */ 2587 1.32.2.2 skrll error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m0, BUS_DMA_NOWAIT); 2588 1.32.2.2 skrll /* 2589 1.32.2.2 skrll * Discard null packets and check for packets that 2590 1.32.2.2 skrll * require too many TX descriptors. We try to convert 2591 1.32.2.2 skrll * the latter to a cluster. 2592 1.32.2.2 skrll */ 2593 1.32.2.2 skrll if (error == EFBIG) { /* too many desc's, linearize */ 2594 1.32.2.2 skrll sc->sc_stats.ast_tx_linear++; 2595 1.32.2.2 skrll MGETHDR(m, M_DONTWAIT, MT_DATA); 2596 1.32.2.2 skrll if (m == NULL) { 2597 1.32.2.2 skrll sc->sc_stats.ast_tx_nombuf++; 2598 1.32.2.2 skrll m_freem(m0); 2599 1.32.2.2 skrll return ENOMEM; 2600 1.32.2.2 skrll } 2601 1.32.2.2 skrll #ifdef __FreeBSD__ 2602 1.32.2.2 skrll M_MOVE_PKTHDR(m, m0); 2603 1.32.2.2 skrll #else 2604 1.32.2.2 skrll M_COPY_PKTHDR(m, m0); 2605 1.32.2.2 skrll #endif 2606 1.32.2.2 skrll MCLGET(m, M_DONTWAIT); 2607 1.32.2.2 skrll if ((m->m_flags & M_EXT) == 0) { 2608 1.32.2.2 skrll sc->sc_stats.ast_tx_nomcl++; 2609 1.32.2.2 skrll m_freem(m0); 2610 1.32.2.2 skrll m_free(m); 2611 1.32.2.2 skrll return ENOMEM; 2612 1.32.2.2 skrll } 2613 1.32.2.2 skrll m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 2614 1.32.2.2 skrll m_freem(m0); 2615 1.32.2.2 skrll m->m_len = m->m_pkthdr.len; 2616 1.32.2.2 skrll m0 = m; 2617 1.32.2.2 skrll error = ath_buf_dmamap_load_mbuf(sc->sc_dmat, bf, m0, 2618 1.32.2.2 skrll BUS_DMA_NOWAIT); 2619 1.32.2.2 skrll if (error != 0) { 2620 1.32.2.2 skrll sc->sc_stats.ast_tx_busdma++; 2621 1.32.2.2 skrll m_freem(m0); 2622 1.32.2.2 skrll return error; 2623 1.32.2.2 skrll } 2624 1.32.2.2 skrll KASSERT(bf->bf_nseg == 1, 2625 1.32.2.2 skrll ("ath_tx_start: packet not one segment; nseg %u", 2626 1.32.2.2 skrll bf->bf_nseg)); 2627 1.32.2.2 skrll } else if (error != 0) { 2628 1.32.2.2 skrll sc->sc_stats.ast_tx_busdma++; 2629 1.32.2.2 skrll m_freem(m0); 2630 1.32.2.2 skrll return error; 2631 1.32.2.2 skrll } else if (bf->bf_nseg == 0) { /* null packet, discard */ 2632 1.32.2.2 skrll sc->sc_stats.ast_tx_nodata++; 2633 1.32.2.2 skrll m_freem(m0); 2634 1.32.2.2 skrll return EIO; 2635 1.32.2.2 skrll } 2636 1.32.2.2 skrll DPRINTF(ATH_DEBUG_XMIT, ("%s: m %p len %u\n", __func__, m0, pktlen)); 2637 1.32.2.2 skrll ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_PREWRITE); 2638 1.32.2.2 skrll bf->bf_m = m0; 2639 1.32.2.2 skrll bf->bf_node = ni; /* NB: held reference */ 2640 1.32.2.2 skrll 2641 1.32.2.2 skrll /* setup descriptors */ 2642 1.32.2.2 skrll ds = bf->bf_desc; 2643 1.32.2.2 skrll rt = sc->sc_currates; 2644 1.32.2.2 skrll KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 2645 1.32.2.2 skrll 2646 1.32.2.2 skrll /* 2647 1.32.2.2 skrll * Calculate Atheros packet type from IEEE80211 packet header 2648 1.32.2.2 skrll * and setup for rate calculations. 2649 1.32.2.2 skrll */ 2650 1.32.2.2 skrll atype = HAL_PKT_TYPE_NORMAL; /* default */ 2651 1.32.2.2 skrll switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 2652 1.32.2.2 skrll case IEEE80211_FC0_TYPE_MGT: 2653 1.32.2.2 skrll subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2654 1.32.2.2 skrll if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 2655 1.32.2.2 skrll atype = HAL_PKT_TYPE_BEACON; 2656 1.32.2.2 skrll else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 2657 1.32.2.2 skrll atype = HAL_PKT_TYPE_PROBE_RESP; 2658 1.32.2.2 skrll else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 2659 1.32.2.2 skrll atype = HAL_PKT_TYPE_ATIM; 2660 1.32.2.2 skrll rix = 0; /* XXX lowest rate */ 2661 1.32.2.2 skrll break; 2662 1.32.2.2 skrll case IEEE80211_FC0_TYPE_CTL: 2663 1.32.2.2 skrll subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2664 1.32.2.2 skrll if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 2665 1.32.2.2 skrll atype = HAL_PKT_TYPE_PSPOLL; 2666 1.32.2.2 skrll rix = 0; /* XXX lowest rate */ 2667 1.32.2.2 skrll break; 2668 1.32.2.2 skrll default: 2669 1.32.2.2 skrll rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 2670 1.32.2.2 skrll IEEE80211_RATE_VAL]; 2671 1.32.2.2 skrll if (rix == 0xff) { 2672 1.32.2.2 skrll if_printf(ifp, "bogus xmit rate 0x%x\n", 2673 1.32.2.2 skrll ni->ni_rates.rs_rates[ni->ni_txrate]); 2674 1.32.2.2 skrll sc->sc_stats.ast_tx_badrate++; 2675 1.32.2.2 skrll m_freem(m0); 2676 1.32.2.2 skrll return EIO; 2677 1.32.2.2 skrll } 2678 1.32.2.2 skrll break; 2679 1.32.2.2 skrll } 2680 1.32.2.2 skrll /* 2681 1.32.2.2 skrll * NB: the 802.11 layer marks whether or not we should 2682 1.32.2.2 skrll * use short preamble based on the current mode and 2683 1.32.2.2 skrll * negotiated parameters. 2684 1.32.2.2 skrll */ 2685 1.32.2.2 skrll if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2686 1.32.2.2 skrll (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 2687 1.32.2.2 skrll txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 2688 1.32.2.2 skrll shortPreamble = AH_TRUE; 2689 1.32.2.2 skrll sc->sc_stats.ast_tx_shortpre++; 2690 1.32.2.2 skrll } else { 2691 1.32.2.2 skrll txrate = rt->info[rix].rateCode; 2692 1.32.2.2 skrll shortPreamble = AH_FALSE; 2693 1.32.2.2 skrll } 2694 1.32.2.2 skrll 2695 1.32.2.2 skrll /* 2696 1.32.2.2 skrll * Calculate miscellaneous flags. 2697 1.32.2.2 skrll */ 2698 1.32.2.2 skrll flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 2699 1.32.2.2 skrll if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2700 1.32.2.2 skrll flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 2701 1.32.2.2 skrll sc->sc_stats.ast_tx_noack++; 2702 1.32.2.2 skrll } else if (pktlen > ic->ic_rtsthreshold) { 2703 1.32.2.2 skrll flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 2704 1.32.2.2 skrll sc->sc_stats.ast_tx_rts++; 2705 1.32.2.2 skrll } 2706 1.32.2.2 skrll 2707 1.32.2.2 skrll /* 2708 1.32.2.2 skrll * Calculate duration. This logically belongs in the 802.11 2709 1.32.2.2 skrll * layer but it lacks sufficient information to calculate it. 2710 1.32.2.2 skrll */ 2711 1.32.2.2 skrll if ((flags & HAL_TXDESC_NOACK) == 0 && 2712 1.32.2.2 skrll (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2713 1.32.2.2 skrll u_int16_t dur; 2714 1.32.2.2 skrll /* 2715 1.32.2.2 skrll * XXX not right with fragmentation. 2716 1.32.2.2 skrll */ 2717 1.32.2.2 skrll dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 2718 1.32.2.2 skrll rix, shortPreamble); 2719 1.32.2.2 skrll *((u_int16_t*) wh->i_dur) = htole16(dur); 2720 1.32.2.2 skrll } 2721 1.32.2.2 skrll 2722 1.32.2.2 skrll /* 2723 1.32.2.2 skrll * Calculate RTS/CTS rate and duration if needed. 2724 1.32.2.2 skrll */ 2725 1.32.2.2 skrll ctsduration = 0; 2726 1.32.2.2 skrll if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 2727 1.32.2.2 skrll /* 2728 1.32.2.2 skrll * CTS transmit rate is derived from the transmit rate 2729 1.32.2.2 skrll * by looking in the h/w rate table. We must also factor 2730 1.32.2.2 skrll * in whether or not a short preamble is to be used. 2731 1.32.2.2 skrll */ 2732 1.32.2.2 skrll cix = rt->info[rix].controlRate; 2733 1.32.2.2 skrll ctsrate = rt->info[cix].rateCode; 2734 1.32.2.2 skrll if (shortPreamble) 2735 1.32.2.2 skrll ctsrate |= rt->info[cix].shortPreamble; 2736 1.32.2.2 skrll /* 2737 1.32.2.2 skrll * Compute the transmit duration based on the size 2738 1.32.2.2 skrll * of an ACK frame. We call into the HAL to do the 2739 1.32.2.2 skrll * computation since it depends on the characteristics 2740 1.32.2.2 skrll * of the actual PHY being used. 2741 1.32.2.2 skrll */ 2742 1.32.2.2 skrll if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 2743 1.32.2.2 skrll ctsduration += ath_hal_computetxtime(ah, 2744 1.32.2.2 skrll rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2745 1.32.2.2 skrll } 2746 1.32.2.2 skrll /* SIFS + data */ 2747 1.32.2.2 skrll ctsduration += ath_hal_computetxtime(ah, 2748 1.32.2.2 skrll rt, pktlen, rix, shortPreamble); 2749 1.32.2.2 skrll if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 2750 1.32.2.2 skrll ctsduration += ath_hal_computetxtime(ah, 2751 1.32.2.2 skrll rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2752 1.32.2.2 skrll } 2753 1.32.2.2 skrll } else 2754 1.32.2.2 skrll ctsrate = 0; 2755 1.32.2.2 skrll 2756 1.32.2.2 skrll /* 2757 1.32.2.2 skrll * For now use the antenna on which the last good 2758 1.32.2.2 skrll * frame was received on. We assume this field is 2759 1.32.2.2 skrll * initialized to 0 which gives us ``auto'' or the 2760 1.32.2.2 skrll * ``default'' antenna. 2761 1.32.2.2 skrll */ 2762 1.32.2.2 skrll an = (struct ath_node *) ni; 2763 1.32.2.2 skrll if (an->an_tx_antenna) 2764 1.32.2.2 skrll antenna = an->an_tx_antenna; 2765 1.32.2.2 skrll else 2766 1.32.2.2 skrll antenna = an->an_rx_hist[an->an_rx_hist_next].arh_antenna; 2767 1.32.2.2 skrll 2768 1.32.2.2 skrll if (ic->ic_rawbpf) 2769 1.32.2.2 skrll bpf_mtap(ic->ic_rawbpf, m0); 2770 1.32.2.2 skrll if (sc->sc_drvbpf) { 2771 1.32.2.2 skrll sc->sc_tx_th.wt_flags = 0; 2772 1.32.2.2 skrll if (shortPreamble) 2773 1.32.2.2 skrll sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2774 1.32.2.2 skrll if (iswep) 2775 1.32.2.2 skrll sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2776 1.32.2.2 skrll sc->sc_tx_th.wt_rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 2777 1.32.2.2 skrll sc->sc_tx_th.wt_txpower = 60/2; /* XXX */ 2778 1.32.2.2 skrll sc->sc_tx_th.wt_antenna = antenna; 2779 1.32.2.2 skrll 2780 1.32.2.2 skrll bpf_mtap2(sc->sc_drvbpf, 2781 1.32.2.2 skrll &sc->sc_tx_th, sc->sc_tx_th_len, m0); 2782 1.32.2.2 skrll } 2783 1.32.2.2 skrll 2784 1.32.2.2 skrll /* 2785 1.32.2.2 skrll * Formulate first tx descriptor with tx controls. 2786 1.32.2.2 skrll */ 2787 1.32.2.2 skrll /* XXX check return value? */ 2788 1.32.2.2 skrll ath_hal_setuptxdesc(ah, ds 2789 1.32.2.2 skrll , pktlen /* packet length */ 2790 1.32.2.2 skrll , hdrlen /* header length */ 2791 1.32.2.2 skrll , atype /* Atheros packet type */ 2792 1.32.2.2 skrll , 60 /* txpower XXX */ 2793 1.32.2.2 skrll , txrate, 1+10 /* series 0 rate/tries */ 2794 1.32.2.2 skrll , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 2795 1.32.2.2 skrll , antenna /* antenna mode */ 2796 1.32.2.2 skrll , flags /* flags */ 2797 1.32.2.2 skrll , ctsrate /* rts/cts rate */ 2798 1.32.2.2 skrll , ctsduration /* rts/cts duration */ 2799 1.32.2.2 skrll ); 2800 1.32.2.2 skrll #ifdef notyet 2801 1.32.2.2 skrll ath_hal_setupxtxdesc(ah, ds 2802 1.32.2.2 skrll , AH_FALSE /* short preamble */ 2803 1.32.2.2 skrll , 0, 0 /* series 1 rate/tries */ 2804 1.32.2.2 skrll , 0, 0 /* series 2 rate/tries */ 2805 1.32.2.2 skrll , 0, 0 /* series 3 rate/tries */ 2806 1.32.2.2 skrll ); 2807 1.32.2.2 skrll #endif 2808 1.32.2.2 skrll /* 2809 1.32.2.2 skrll * Fillin the remainder of the descriptor info. 2810 1.32.2.2 skrll */ 2811 1.32.2.2 skrll for (i = 0; i < bf->bf_nseg; i++, ds++) { 2812 1.32.2.2 skrll ds->ds_data = bf->bf_segs[i].ds_addr; 2813 1.32.2.2 skrll if (i == bf->bf_nseg - 1) 2814 1.32.2.2 skrll ds->ds_link = 0; 2815 1.32.2.2 skrll else 2816 1.32.2.2 skrll ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 2817 1.32.2.2 skrll ath_hal_filltxdesc(ah, ds 2818 1.32.2.2 skrll , bf->bf_segs[i].ds_len /* segment length */ 2819 1.32.2.2 skrll , i == 0 /* first segment */ 2820 1.32.2.2 skrll , i == bf->bf_nseg - 1 /* last segment */ 2821 1.32.2.2 skrll ); 2822 1.32.2.2 skrll DPRINTF(ATH_DEBUG_XMIT, 2823 1.32.2.2 skrll ("%s: %d: %08x %08x %08x %08x %08x %08x\n", 2824 1.32.2.2 skrll __func__, i, ds->ds_link, ds->ds_data, 2825 1.32.2.2 skrll ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1])); 2826 1.32.2.2 skrll } 2827 1.32.2.2 skrll 2828 1.32.2.2 skrll /* 2829 1.32.2.2 skrll * Insert the frame on the outbound list and 2830 1.32.2.2 skrll * pass it on to the hardware. 2831 1.32.2.2 skrll */ 2832 1.32.2.2 skrll ath_txq_critsect_begin(sc, s); 2833 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 2834 1.32.2.2 skrll if (sc->sc_txlink == NULL) { 2835 1.32.2.2 skrll ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 2836 1.32.2.2 skrll DPRINTF(ATH_DEBUG_XMIT, ("%s: TXDP0 = %p (%p)\n", __func__, 2837 1.32.2.2 skrll (caddr_t)bf->bf_daddr, bf->bf_desc)); 2838 1.32.2.2 skrll } else { 2839 1.32.2.2 skrll *sc->sc_txlink = bf->bf_daddr; 2840 1.32.2.2 skrll DPRINTF(ATH_DEBUG_XMIT, ("%s: link(%p)=%p (%p)\n", __func__, 2841 1.32.2.2 skrll sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 2842 1.32.2.2 skrll } 2843 1.32.2.2 skrll sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 2844 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2845 1.32.2.2 skrll 2846 1.32.2.2 skrll ath_hal_txstart(ah, sc->sc_txhalq); 2847 1.32.2.2 skrll return 0; 2848 1.32.2.2 skrll } 2849 1.32.2.2 skrll 2850 1.32.2.2 skrll static void 2851 1.32.2.2 skrll ath_tx_proc(void *arg, int npending) 2852 1.32.2.2 skrll { 2853 1.32.2.2 skrll struct ath_softc *sc = arg; 2854 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2855 1.32.2.2 skrll struct ath_buf *bf; 2856 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2857 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 2858 1.32.2.2 skrll struct ath_desc *ds; 2859 1.32.2.2 skrll struct ieee80211_node *ni; 2860 1.32.2.2 skrll struct ath_node *an; 2861 1.32.2.2 skrll int sr, lr; 2862 1.32.2.2 skrll HAL_STATUS status; 2863 1.32.2.2 skrll ath_txq_critsect_decl(s); 2864 1.32.2.2 skrll ath_txbuf_critsect_decl(s2); 2865 1.32.2.2 skrll 2866 1.32.2.2 skrll DPRINTF(ATH_DEBUG_TX_PROC, ("%s: pending %u tx queue %p, link %p\n", 2867 1.32.2.2 skrll __func__, npending, 2868 1.32.2.2 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 2869 1.32.2.2 skrll sc->sc_txlink)); 2870 1.32.2.2 skrll for (;;) { 2871 1.32.2.2 skrll ath_txq_critsect_begin(sc, s); 2872 1.32.2.2 skrll bf = TAILQ_FIRST(&sc->sc_txq); 2873 1.32.2.2 skrll if (bf == NULL) { 2874 1.32.2.2 skrll sc->sc_txlink = NULL; 2875 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2876 1.32.2.2 skrll break; 2877 1.32.2.2 skrll } 2878 1.32.2.2 skrll /* only the last descriptor is needed */ 2879 1.32.2.2 skrll ds = &bf->bf_desc[bf->bf_nseg - 1]; 2880 1.32.2.2 skrll status = ath_hal_txprocdesc(ah, ds); 2881 1.32.2.2 skrll #ifdef AR_DEBUG 2882 1.32.2.2 skrll if (ath_debug & ATH_DEBUG_XMIT_DESC) 2883 1.32.2.2 skrll ath_printtxbuf(bf, status == HAL_OK); 2884 1.32.2.2 skrll #endif 2885 1.32.2.2 skrll if (status == HAL_EINPROGRESS) { 2886 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2887 1.32.2.2 skrll break; 2888 1.32.2.2 skrll } 2889 1.32.2.2 skrll TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2890 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2891 1.32.2.2 skrll 2892 1.32.2.2 skrll ni = bf->bf_node; 2893 1.32.2.2 skrll if (ni != NULL) { 2894 1.32.2.2 skrll an = (struct ath_node *) ni; 2895 1.32.2.2 skrll if (ds->ds_txstat.ts_status == 0) { 2896 1.32.2.2 skrll an->an_tx_ok++; 2897 1.32.2.2 skrll an->an_tx_antenna = ds->ds_txstat.ts_antenna; 2898 1.32.2.2 skrll } else { 2899 1.32.2.2 skrll an->an_tx_err++; 2900 1.32.2.2 skrll ifp->if_oerrors++; 2901 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 2902 1.32.2.2 skrll sc->sc_stats.ast_tx_xretries++; 2903 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 2904 1.32.2.2 skrll sc->sc_stats.ast_tx_fifoerr++; 2905 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 2906 1.32.2.2 skrll sc->sc_stats.ast_tx_filtered++; 2907 1.32.2.2 skrll an->an_tx_antenna = 0; /* invalidate */ 2908 1.32.2.2 skrll } 2909 1.32.2.2 skrll sr = ds->ds_txstat.ts_shortretry; 2910 1.32.2.2 skrll lr = ds->ds_txstat.ts_longretry; 2911 1.32.2.2 skrll sc->sc_stats.ast_tx_shortretry += sr; 2912 1.32.2.2 skrll sc->sc_stats.ast_tx_longretry += lr; 2913 1.32.2.2 skrll if (sr + lr) 2914 1.32.2.2 skrll an->an_tx_retr++; 2915 1.32.2.2 skrll /* 2916 1.32.2.2 skrll * Reclaim reference to node. 2917 1.32.2.2 skrll * 2918 1.32.2.2 skrll * NB: the node may be reclaimed here if, for example 2919 1.32.2.2 skrll * this is a DEAUTH message that was sent and the 2920 1.32.2.2 skrll * node was timed out due to inactivity. 2921 1.32.2.2 skrll */ 2922 1.32.2.3 skrll ieee80211_release_node(ic, ni); 2923 1.32.2.2 skrll } 2924 1.32.2.2 skrll ath_buf_dmamap_sync(sc->sc_dmat, bf, BUS_DMASYNC_POSTWRITE); 2925 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2926 1.32.2.2 skrll m_freem(bf->bf_m); 2927 1.32.2.2 skrll bf->bf_m = NULL; 2928 1.32.2.2 skrll bf->bf_node = NULL; 2929 1.32.2.2 skrll 2930 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s2); 2931 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2932 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s2); 2933 1.32.2.2 skrll } 2934 1.32.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 2935 1.32.2.2 skrll sc->sc_tx_timer = 0; 2936 1.32.2.2 skrll 2937 1.32.2.2 skrll ath_start(ifp); 2938 1.32.2.2 skrll } 2939 1.32.2.2 skrll 2940 1.32.2.2 skrll /* 2941 1.32.2.2 skrll * Drain the transmit queue and reclaim resources. 2942 1.32.2.2 skrll */ 2943 1.32.2.2 skrll static void 2944 1.32.2.2 skrll ath_draintxq(struct ath_softc *sc) 2945 1.32.2.2 skrll { 2946 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2947 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2948 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 2949 1.32.2.2 skrll struct ieee80211_node *ni; 2950 1.32.2.2 skrll struct ath_buf *bf; 2951 1.32.2.2 skrll ath_txq_critsect_decl(s); 2952 1.32.2.2 skrll ath_txbuf_critsect_decl(s2); 2953 1.32.2.2 skrll 2954 1.32.2.2 skrll /* XXX return value */ 2955 1.32.2.2 skrll if (!sc->sc_invalid) { 2956 1.32.2.2 skrll /* don't touch the hardware if marked invalid */ 2957 1.32.2.2 skrll (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2958 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RESET, 2959 1.32.2.2 skrll ("%s: tx queue %p, link %p\n", __func__, 2960 1.32.2.2 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2961 1.32.2.2 skrll sc->sc_txlink)); 2962 1.32.2.2 skrll (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2963 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RESET, 2964 1.32.2.2 skrll ("%s: beacon queue %p\n", __func__, 2965 1.32.2.2 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2966 1.32.2.2 skrll } 2967 1.32.2.2 skrll for (;;) { 2968 1.32.2.2 skrll ath_txq_critsect_begin(sc, s); 2969 1.32.2.2 skrll bf = TAILQ_FIRST(&sc->sc_txq); 2970 1.32.2.2 skrll if (bf == NULL) { 2971 1.32.2.2 skrll sc->sc_txlink = NULL; 2972 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2973 1.32.2.2 skrll break; 2974 1.32.2.2 skrll } 2975 1.32.2.2 skrll TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2976 1.32.2.2 skrll ath_txq_critsect_end(sc, s); 2977 1.32.2.2 skrll #ifdef AR_DEBUG 2978 1.32.2.2 skrll if (ath_debug & ATH_DEBUG_RESET) 2979 1.32.2.2 skrll ath_printtxbuf(bf, 2980 1.32.2.2 skrll ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2981 1.32.2.2 skrll #endif /* AR_DEBUG */ 2982 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2983 1.32.2.2 skrll m_freem(bf->bf_m); 2984 1.32.2.2 skrll bf->bf_m = NULL; 2985 1.32.2.2 skrll ni = bf->bf_node; 2986 1.32.2.2 skrll bf->bf_node = NULL; 2987 1.32.2.2 skrll ath_txbuf_critsect_begin(sc, s2); 2988 1.32.2.3 skrll if (ni != NULL) { 2989 1.32.2.2 skrll /* 2990 1.32.2.2 skrll * Reclaim node reference. 2991 1.32.2.2 skrll */ 2992 1.32.2.3 skrll ieee80211_release_node(ic, ni); 2993 1.32.2.2 skrll } 2994 1.32.2.2 skrll TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2995 1.32.2.2 skrll ath_txbuf_critsect_end(sc, s2); 2996 1.32.2.2 skrll } 2997 1.32.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 2998 1.32.2.2 skrll sc->sc_tx_timer = 0; 2999 1.32.2.2 skrll } 3000 1.32.2.2 skrll 3001 1.32.2.2 skrll /* 3002 1.32.2.2 skrll * Disable the receive h/w in preparation for a reset. 3003 1.32.2.2 skrll */ 3004 1.32.2.2 skrll static void 3005 1.32.2.2 skrll ath_stoprecv(struct ath_softc *sc) 3006 1.32.2.2 skrll { 3007 1.32.2.2 skrll #define PA2DESC(_sc, _pa) \ 3008 1.32.2.2 skrll ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ 3009 1.32.2.2 skrll ((_pa) - (_sc)->sc_desc_paddr))) 3010 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3011 1.32.2.2 skrll 3012 1.32.2.2 skrll ath_hal_stoppcurecv(ah); /* disable PCU */ 3013 1.32.2.2 skrll ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 3014 1.32.2.2 skrll ath_hal_stopdmarecv(ah); /* disable DMA engine */ 3015 1.32.2.2 skrll DELAY(3000); /* long enough for 1 frame */ 3016 1.32.2.2 skrll #ifdef AR_DEBUG 3017 1.32.2.2 skrll if (ath_debug & ATH_DEBUG_RESET) { 3018 1.32.2.2 skrll struct ath_buf *bf; 3019 1.32.2.2 skrll 3020 1.32.2.2 skrll printf("%s: rx queue %p, link %p\n", __func__, 3021 1.32.2.2 skrll (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 3022 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3023 1.32.2.2 skrll struct ath_desc *ds = bf->bf_desc; 3024 1.32.2.2 skrll if (ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, 3025 1.32.2.2 skrll PA2DESC(sc, ds->ds_link)) == HAL_OK) 3026 1.32.2.2 skrll ath_printrxbuf(bf, 1); 3027 1.32.2.2 skrll } 3028 1.32.2.2 skrll } 3029 1.32.2.2 skrll #endif 3030 1.32.2.2 skrll sc->sc_rxlink = NULL; /* just in case */ 3031 1.32.2.2 skrll #undef PA2DESC 3032 1.32.2.2 skrll } 3033 1.32.2.2 skrll 3034 1.32.2.2 skrll /* 3035 1.32.2.2 skrll * Enable the receive h/w following a reset. 3036 1.32.2.2 skrll */ 3037 1.32.2.2 skrll static int 3038 1.32.2.2 skrll ath_startrecv(struct ath_softc *sc) 3039 1.32.2.2 skrll { 3040 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3041 1.32.2.2 skrll struct ath_buf *bf; 3042 1.32.2.2 skrll 3043 1.32.2.2 skrll sc->sc_rxlink = NULL; 3044 1.32.2.2 skrll TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3045 1.32.2.2 skrll int error = ath_rxbuf_init(sc, bf); 3046 1.32.2.2 skrll if (error != 0) { 3047 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RECV, 3048 1.32.2.2 skrll ("%s: ath_rxbuf_init failed %d\n", 3049 1.32.2.2 skrll __func__, error)); 3050 1.32.2.2 skrll return error; 3051 1.32.2.2 skrll } 3052 1.32.2.2 skrll } 3053 1.32.2.2 skrll 3054 1.32.2.2 skrll bf = TAILQ_FIRST(&sc->sc_rxbuf); 3055 1.32.2.2 skrll ath_hal_putrxbuf(ah, bf->bf_daddr); 3056 1.32.2.2 skrll ath_hal_rxena(ah); /* enable recv descriptors */ 3057 1.32.2.2 skrll ath_mode_init(sc); /* set filters, etc. */ 3058 1.32.2.2 skrll ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 3059 1.32.2.2 skrll return 0; 3060 1.32.2.2 skrll } 3061 1.32.2.2 skrll 3062 1.32.2.2 skrll /* 3063 1.32.2.2 skrll * Set/change channels. If the channel is really being changed, 3064 1.32.2.2 skrll * it's done by resetting the chip. To accomplish this we must 3065 1.32.2.2 skrll * first cleanup any pending DMA, then restart stuff after a la 3066 1.32.2.2 skrll * ath_init. 3067 1.32.2.2 skrll */ 3068 1.32.2.2 skrll static int 3069 1.32.2.2 skrll ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 3070 1.32.2.2 skrll { 3071 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3072 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3073 1.32.2.2 skrll 3074 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: %u (%u MHz) -> %u (%u MHz)\n", __func__, 3075 1.32.2.2 skrll ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 3076 1.32.2.2 skrll ic->ic_ibss_chan->ic_freq, 3077 1.32.2.2 skrll ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 3078 1.32.2.2 skrll if (chan != ic->ic_ibss_chan) { 3079 1.32.2.2 skrll HAL_STATUS status; 3080 1.32.2.2 skrll HAL_CHANNEL hchan; 3081 1.32.2.2 skrll enum ieee80211_phymode mode; 3082 1.32.2.2 skrll 3083 1.32.2.2 skrll /* 3084 1.32.2.2 skrll * To switch channels clear any pending DMA operations; 3085 1.32.2.2 skrll * wait long enough for the RX fifo to drain, reset the 3086 1.32.2.2 skrll * hardware at the new frequency, and then re-enable 3087 1.32.2.2 skrll * the relevant bits of the h/w. 3088 1.32.2.2 skrll */ 3089 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable interrupts */ 3090 1.32.2.2 skrll ath_draintxq(sc); /* clear pending tx frames */ 3091 1.32.2.2 skrll ath_stoprecv(sc); /* turn off frame recv */ 3092 1.32.2.2 skrll /* 3093 1.32.2.2 skrll * Convert to a HAL channel description with 3094 1.32.2.2 skrll * the flags constrained to reflect the current 3095 1.32.2.2 skrll * operating mode. 3096 1.32.2.2 skrll */ 3097 1.32.2.2 skrll hchan.channel = chan->ic_freq; 3098 1.32.2.2 skrll hchan.channelFlags = ath_chan2flags(ic, chan); 3099 1.32.2.2 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 3100 1.32.2.2 skrll if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 3101 1.32.2.2 skrll "channel %u (%u Mhz)\n", 3102 1.32.2.2 skrll ieee80211_chan2ieee(ic, chan), chan->ic_freq); 3103 1.32.2.2 skrll return EIO; 3104 1.32.2.2 skrll } 3105 1.32.2.2 skrll /* 3106 1.32.2.2 skrll * Re-enable rx framework. 3107 1.32.2.2 skrll */ 3108 1.32.2.2 skrll if (ath_startrecv(sc) != 0) { 3109 1.32.2.2 skrll if_printf(&ic->ic_if, 3110 1.32.2.2 skrll "ath_chan_set: unable to restart recv logic\n"); 3111 1.32.2.2 skrll return EIO; 3112 1.32.2.2 skrll } 3113 1.32.2.2 skrll 3114 1.32.2.2 skrll /* 3115 1.32.2.2 skrll * Update BPF state. 3116 1.32.2.2 skrll */ 3117 1.32.2.2 skrll sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 3118 1.32.2.2 skrll htole16(chan->ic_freq); 3119 1.32.2.2 skrll sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 3120 1.32.2.2 skrll htole16(chan->ic_flags); 3121 1.32.2.2 skrll 3122 1.32.2.2 skrll /* 3123 1.32.2.2 skrll * Change channels and update the h/w rate map 3124 1.32.2.2 skrll * if we're switching; e.g. 11a to 11b/g. 3125 1.32.2.2 skrll */ 3126 1.32.2.2 skrll ic->ic_ibss_chan = chan; 3127 1.32.2.2 skrll mode = ieee80211_chan2mode(ic, chan); 3128 1.32.2.2 skrll if (mode != sc->sc_curmode) 3129 1.32.2.2 skrll ath_setcurmode(sc, mode); 3130 1.32.2.2 skrll 3131 1.32.2.2 skrll /* 3132 1.32.2.2 skrll * Re-enable interrupts. 3133 1.32.2.2 skrll */ 3134 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 3135 1.32.2.2 skrll } 3136 1.32.2.2 skrll return 0; 3137 1.32.2.2 skrll } 3138 1.32.2.2 skrll 3139 1.32.2.2 skrll static void 3140 1.32.2.2 skrll ath_next_scan(void *arg) 3141 1.32.2.2 skrll { 3142 1.32.2.2 skrll struct ath_softc *sc = arg; 3143 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3144 1.32.2.2 skrll int s; 3145 1.32.2.2 skrll 3146 1.32.2.2 skrll /* don't call ath_start w/o network interrupts blocked */ 3147 1.32.2.2 skrll s = splnet(); 3148 1.32.2.2 skrll 3149 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_SCAN) 3150 1.32.2.2 skrll ieee80211_next_scan(ic); 3151 1.32.2.2 skrll splx(s); 3152 1.32.2.2 skrll } 3153 1.32.2.2 skrll 3154 1.32.2.2 skrll /* 3155 1.32.2.2 skrll * Periodically recalibrate the PHY to account 3156 1.32.2.2 skrll * for temperature/environment changes. 3157 1.32.2.2 skrll */ 3158 1.32.2.2 skrll static void 3159 1.32.2.2 skrll ath_calibrate(void *arg) 3160 1.32.2.2 skrll { 3161 1.32.2.2 skrll struct ath_softc *sc = arg; 3162 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3163 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3164 1.32.2.2 skrll struct ieee80211_channel *c; 3165 1.32.2.2 skrll HAL_CHANNEL hchan; 3166 1.32.2.2 skrll 3167 1.32.2.2 skrll sc->sc_stats.ast_per_cal++; 3168 1.32.2.2 skrll 3169 1.32.2.2 skrll /* 3170 1.32.2.2 skrll * Convert to a HAL channel description with the flags 3171 1.32.2.2 skrll * constrained to reflect the current operating mode. 3172 1.32.2.2 skrll */ 3173 1.32.2.2 skrll c = ic->ic_ibss_chan; 3174 1.32.2.2 skrll hchan.channel = c->ic_freq; 3175 1.32.2.2 skrll hchan.channelFlags = ath_chan2flags(ic, c); 3176 1.32.2.2 skrll 3177 1.32.2.2 skrll DPRINTF(ATH_DEBUG_CALIBRATE, 3178 1.32.2.2 skrll ("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 3179 1.32.2.2 skrll 3180 1.32.2.2 skrll if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 3181 1.32.2.2 skrll /* 3182 1.32.2.2 skrll * Rfgain is out of bounds, reset the chip 3183 1.32.2.2 skrll * to load new gain values. 3184 1.32.2.2 skrll */ 3185 1.32.2.2 skrll sc->sc_stats.ast_per_rfgain++; 3186 1.32.2.2 skrll ath_reset(sc); 3187 1.32.2.2 skrll } 3188 1.32.2.2 skrll if (!ath_hal_calibrate(ah, &hchan)) { 3189 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 3190 1.32.2.2 skrll ("%s: calibration of channel %u failed\n", 3191 1.32.2.2 skrll __func__, c->ic_freq)); 3192 1.32.2.2 skrll sc->sc_stats.ast_per_calfail++; 3193 1.32.2.2 skrll } 3194 1.32.2.2 skrll callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 3195 1.32.2.2 skrll } 3196 1.32.2.2 skrll 3197 1.32.2.2 skrll static HAL_LED_STATE 3198 1.32.2.2 skrll ath_state_to_led(enum ieee80211_state state) 3199 1.32.2.2 skrll { 3200 1.32.2.2 skrll switch (state) { 3201 1.32.2.2 skrll case IEEE80211_S_INIT: 3202 1.32.2.2 skrll return HAL_LED_INIT; 3203 1.32.2.2 skrll case IEEE80211_S_SCAN: 3204 1.32.2.2 skrll return HAL_LED_SCAN; 3205 1.32.2.2 skrll case IEEE80211_S_AUTH: 3206 1.32.2.2 skrll return HAL_LED_AUTH; 3207 1.32.2.2 skrll case IEEE80211_S_ASSOC: 3208 1.32.2.2 skrll return HAL_LED_ASSOC; 3209 1.32.2.2 skrll case IEEE80211_S_RUN: 3210 1.32.2.2 skrll return HAL_LED_RUN; 3211 1.32.2.2 skrll default: 3212 1.32.2.2 skrll panic("%s: unknown 802.11 state %d\n", __func__, state); 3213 1.32.2.2 skrll return HAL_LED_INIT; 3214 1.32.2.2 skrll } 3215 1.32.2.2 skrll } 3216 1.32.2.2 skrll 3217 1.32.2.2 skrll static int 3218 1.32.2.2 skrll ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 3219 1.32.2.2 skrll { 3220 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 3221 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 3222 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3223 1.32.2.2 skrll struct ieee80211_node *ni; 3224 1.32.2.2 skrll int i, error; 3225 1.32.2.2 skrll const u_int8_t *bssid; 3226 1.32.2.2 skrll u_int32_t rfilt; 3227 1.32.2.2 skrll 3228 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: %s -> %s\n", __func__, 3229 1.32.2.2 skrll ieee80211_state_name[ic->ic_state], 3230 1.32.2.2 skrll ieee80211_state_name[nstate])); 3231 1.32.2.2 skrll 3232 1.32.2.2 skrll ath_hal_setledstate(ah, ath_state_to_led(nstate)); /* set LED */ 3233 1.32.2.2 skrll 3234 1.32.2.2 skrll if (nstate == IEEE80211_S_INIT) { 3235 1.32.2.2 skrll sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 3236 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 3237 1.32.2.2 skrll callout_stop(&sc->sc_scan_ch); 3238 1.32.2.2 skrll callout_stop(&sc->sc_cal_ch); 3239 1.32.2.2 skrll return (*sc->sc_newstate)(ic, nstate, arg); 3240 1.32.2.2 skrll } 3241 1.32.2.2 skrll ni = ic->ic_bss; 3242 1.32.2.2 skrll error = ath_chan_set(sc, ni->ni_chan); 3243 1.32.2.2 skrll if (error != 0) 3244 1.32.2.2 skrll goto bad; 3245 1.32.2.2 skrll rfilt = ath_calcrxfilter(sc); 3246 1.32.2.2 skrll if (nstate == IEEE80211_S_SCAN) { 3247 1.32.2.2 skrll callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 3248 1.32.2.2 skrll ath_next_scan, sc); 3249 1.32.2.2 skrll bssid = ifp->if_broadcastaddr; 3250 1.32.2.2 skrll } else { 3251 1.32.2.2 skrll callout_stop(&sc->sc_scan_ch); 3252 1.32.2.2 skrll bssid = ni->ni_bssid; 3253 1.32.2.2 skrll } 3254 1.32.2.2 skrll ath_hal_setrxfilter(ah, rfilt); 3255 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s: RX filter 0x%x bssid %s\n", 3256 1.32.2.2 skrll __func__, rfilt, ether_sprintf(bssid))); 3257 1.32.2.2 skrll 3258 1.32.2.2 skrll if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 3259 1.32.2.2 skrll ath_hal_setassocid(ah, bssid, ni->ni_associd); 3260 1.32.2.2 skrll else 3261 1.32.2.2 skrll ath_hal_setassocid(ah, bssid, 0); 3262 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) { 3263 1.32.2.2 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) 3264 1.32.2.2 skrll if (ath_hal_keyisvalid(ah, i)) 3265 1.32.2.2 skrll ath_hal_keysetmac(ah, i, bssid); 3266 1.32.2.2 skrll } 3267 1.32.2.2 skrll 3268 1.32.2.2 skrll if (nstate == IEEE80211_S_RUN) { 3269 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, ("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 3270 1.32.2.2 skrll "capinfo=0x%04x chan=%d\n" 3271 1.32.2.2 skrll , __func__ 3272 1.32.2.2 skrll , ic->ic_flags 3273 1.32.2.2 skrll , ni->ni_intval 3274 1.32.2.2 skrll , ether_sprintf(ni->ni_bssid) 3275 1.32.2.2 skrll , ni->ni_capinfo 3276 1.32.2.2 skrll , ieee80211_chan2ieee(ic, ni->ni_chan))); 3277 1.32.2.2 skrll 3278 1.32.2.2 skrll /* 3279 1.32.2.2 skrll * Allocate and setup the beacon frame for AP or adhoc mode. 3280 1.32.2.2 skrll */ 3281 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3282 1.32.2.2 skrll ic->ic_opmode == IEEE80211_M_IBSS) { 3283 1.32.2.2 skrll error = ath_beacon_alloc(sc, ni); 3284 1.32.2.2 skrll if (error != 0) 3285 1.32.2.2 skrll goto bad; 3286 1.32.2.2 skrll } 3287 1.32.2.2 skrll 3288 1.32.2.2 skrll /* 3289 1.32.2.2 skrll * Configure the beacon and sleep timers. 3290 1.32.2.2 skrll */ 3291 1.32.2.2 skrll ath_beacon_config(sc); 3292 1.32.2.2 skrll 3293 1.32.2.2 skrll /* start periodic recalibration timer */ 3294 1.32.2.2 skrll callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 3295 1.32.2.2 skrll ath_calibrate, sc); 3296 1.32.2.2 skrll } else { 3297 1.32.2.2 skrll sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 3298 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 3299 1.32.2.2 skrll callout_stop(&sc->sc_cal_ch); /* no calibration */ 3300 1.32.2.2 skrll } 3301 1.32.2.2 skrll /* 3302 1.32.2.2 skrll * Reset the rate control state. 3303 1.32.2.2 skrll */ 3304 1.32.2.2 skrll ath_rate_ctl_reset(sc, nstate); 3305 1.32.2.2 skrll /* 3306 1.32.2.2 skrll * Invoke the parent method to complete the work. 3307 1.32.2.2 skrll */ 3308 1.32.2.2 skrll return (*sc->sc_newstate)(ic, nstate, arg); 3309 1.32.2.2 skrll bad: 3310 1.32.2.2 skrll callout_stop(&sc->sc_scan_ch); 3311 1.32.2.2 skrll callout_stop(&sc->sc_cal_ch); 3312 1.32.2.2 skrll /* NB: do not invoke the parent */ 3313 1.32.2.2 skrll return error; 3314 1.32.2.2 skrll } 3315 1.32.2.2 skrll 3316 1.32.2.8 skrll static uint64_t 3317 1.32.2.8 skrll ath_tsf_extend(struct ath_hal *ah, uint32_t rstamp) 3318 1.32.2.8 skrll { 3319 1.32.2.8 skrll uint64_t tsf; 3320 1.32.2.10 skrll 3321 1.32.2.8 skrll KASSERT((rstamp & 0xffff0000) == 0, 3322 1.32.2.8 skrll ("rx timestamp > 16 bits wide, %" PRIu32, rstamp)); 3323 1.32.2.8 skrll 3324 1.32.2.8 skrll tsf = ath_hal_gettsf64(ah); 3325 1.32.2.8 skrll 3326 1.32.2.8 skrll /* Compensate for rollover. */ 3327 1.32.2.8 skrll if ((tsf & 0xffff) <= rstamp) 3328 1.32.2.8 skrll tsf -= 0x10000; 3329 1.32.2.8 skrll 3330 1.32.2.8 skrll return (tsf & ~(uint64_t)0xffff) | rstamp; 3331 1.32.2.8 skrll } 3332 1.32.2.8 skrll 3333 1.32.2.3 skrll static void 3334 1.32.2.3 skrll ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3335 1.32.2.3 skrll struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp) 3336 1.32.2.3 skrll { 3337 1.32.2.3 skrll struct ath_softc *sc = (struct ath_softc*)ic->ic_softc; 3338 1.32.2.3 skrll struct ath_hal *ah = sc->sc_ah; 3339 1.32.2.3 skrll 3340 1.32.2.3 skrll (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp); 3341 1.32.2.3 skrll 3342 1.32.2.3 skrll switch (subtype) { 3343 1.32.2.3 skrll case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3344 1.32.2.3 skrll case IEEE80211_FC0_SUBTYPE_BEACON: 3345 1.32.2.3 skrll if (ic->ic_opmode != IEEE80211_M_IBSS || 3346 1.32.2.3 skrll ic->ic_state != IEEE80211_S_RUN) 3347 1.32.2.3 skrll break; 3348 1.32.2.8 skrll if (le64toh(ni->ni_tsf) >= ath_tsf_extend(ah, rstamp) && 3349 1.32.2.8 skrll ieee80211_ibss_merge(ic, ni)) { 3350 1.32.2.8 skrll /* 3351 1.32.2.8 skrll * XXX rather than handle this here it's 3352 1.32.2.8 skrll * probably better to do it at the 802.11 3353 1.32.2.8 skrll * layer through the state machine so, 3354 1.32.2.8 skrll * we can switch channel, etc. 3355 1.32.2.8 skrll */ 3356 1.32.2.8 skrll /* XXX adopt beacon interval and ATIM window */ 3357 1.32.2.3 skrll ath_hal_setassocid(ah, ic->ic_bss->ni_bssid, 0); 3358 1.32.2.8 skrll ath_hal_stoptxdma(ah, sc->sc_bhalq); 3359 1.32.2.9 skrll ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3360 1.32.2.8 skrll } 3361 1.32.2.3 skrll break; 3362 1.32.2.3 skrll default: 3363 1.32.2.3 skrll break; 3364 1.32.2.3 skrll } 3365 1.32.2.3 skrll return; 3366 1.32.2.3 skrll } 3367 1.32.2.3 skrll 3368 1.32.2.2 skrll /* 3369 1.32.2.2 skrll * Setup driver-specific state for a newly associated node. 3370 1.32.2.2 skrll * Note that we're called also on a re-associate, the isnew 3371 1.32.2.2 skrll * param tells us if this is the first time or not. 3372 1.32.2.2 skrll */ 3373 1.32.2.2 skrll static void 3374 1.32.2.2 skrll ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 3375 1.32.2.2 skrll { 3376 1.32.2.2 skrll if (isnew) { 3377 1.32.2.2 skrll struct ath_node *an = (struct ath_node *) ni; 3378 1.32.2.2 skrll 3379 1.32.2.2 skrll an->an_tx_ok = an->an_tx_err = 3380 1.32.2.2 skrll an->an_tx_retr = an->an_tx_upper = 0; 3381 1.32.2.2 skrll /* start with highest negotiated rate */ 3382 1.32.2.2 skrll /* 3383 1.32.2.2 skrll * XXX should do otherwise but only when 3384 1.32.2.2 skrll * the rate control algorithm is better. 3385 1.32.2.2 skrll */ 3386 1.32.2.2 skrll KASSERT(ni->ni_rates.rs_nrates > 0, 3387 1.32.2.2 skrll ("new association w/ no rates!")); 3388 1.32.2.2 skrll ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 3389 1.32.2.2 skrll } 3390 1.32.2.2 skrll } 3391 1.32.2.2 skrll 3392 1.32.2.2 skrll static int 3393 1.32.2.2 skrll ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor, 3394 1.32.2.2 skrll HAL_BOOL xchanmode) 3395 1.32.2.2 skrll { 3396 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3397 1.32.2.2 skrll struct ifnet *ifp = &ic->ic_if; 3398 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3399 1.32.2.2 skrll HAL_CHANNEL *chans; 3400 1.32.2.2 skrll int i, ix, nchan; 3401 1.32.2.2 skrll 3402 1.32.2.2 skrll chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 3403 1.32.2.2 skrll M_TEMP, M_NOWAIT); 3404 1.32.2.2 skrll if (chans == NULL) { 3405 1.32.2.2 skrll if_printf(ifp, "unable to allocate channel table\n"); 3406 1.32.2.2 skrll return ENOMEM; 3407 1.32.2.2 skrll } 3408 1.32.2.2 skrll if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 3409 1.32.2.2 skrll cc, HAL_MODE_ALL, outdoor, xchanmode)) { 3410 1.32.2.2 skrll if_printf(ifp, "unable to collect channel list from hal\n"); 3411 1.32.2.2 skrll free(chans, M_TEMP); 3412 1.32.2.2 skrll return EINVAL; 3413 1.32.2.2 skrll } 3414 1.32.2.2 skrll 3415 1.32.2.2 skrll /* 3416 1.32.2.2 skrll * Convert HAL channels to ieee80211 ones and insert 3417 1.32.2.2 skrll * them in the table according to their channel number. 3418 1.32.2.2 skrll */ 3419 1.32.2.2 skrll for (i = 0; i < nchan; i++) { 3420 1.32.2.2 skrll HAL_CHANNEL *c = &chans[i]; 3421 1.32.2.2 skrll ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 3422 1.32.2.2 skrll if (ix > IEEE80211_CHAN_MAX) { 3423 1.32.2.2 skrll if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 3424 1.32.2.2 skrll ix, c->channel, c->channelFlags); 3425 1.32.2.2 skrll continue; 3426 1.32.2.2 skrll } 3427 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 3428 1.32.2.2 skrll ("%s: HAL channel %d/%d freq %d flags %#04x idx %d\n", 3429 1.32.2.2 skrll sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags, 3430 1.32.2.2 skrll ix)); 3431 1.32.2.2 skrll /* NB: flags are known to be compatible */ 3432 1.32.2.2 skrll if (ic->ic_channels[ix].ic_freq == 0) { 3433 1.32.2.2 skrll ic->ic_channels[ix].ic_freq = c->channel; 3434 1.32.2.2 skrll ic->ic_channels[ix].ic_flags = c->channelFlags; 3435 1.32.2.2 skrll } else { 3436 1.32.2.2 skrll /* channels overlap; e.g. 11g and 11b */ 3437 1.32.2.2 skrll ic->ic_channels[ix].ic_flags |= c->channelFlags; 3438 1.32.2.2 skrll } 3439 1.32.2.2 skrll } 3440 1.32.2.2 skrll free(chans, M_TEMP); 3441 1.32.2.2 skrll return 0; 3442 1.32.2.2 skrll } 3443 1.32.2.2 skrll 3444 1.32.2.2 skrll static int 3445 1.32.2.2 skrll ath_rate_setup(struct ath_softc *sc, u_int mode) 3446 1.32.2.2 skrll { 3447 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3448 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3449 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 3450 1.32.2.2 skrll struct ieee80211_rateset *rs; 3451 1.32.2.2 skrll int i, maxrates; 3452 1.32.2.2 skrll 3453 1.32.2.2 skrll switch (mode) { 3454 1.32.2.2 skrll case IEEE80211_MODE_11A: 3455 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 3456 1.32.2.2 skrll break; 3457 1.32.2.2 skrll case IEEE80211_MODE_11B: 3458 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 3459 1.32.2.2 skrll break; 3460 1.32.2.2 skrll case IEEE80211_MODE_11G: 3461 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 3462 1.32.2.2 skrll break; 3463 1.32.2.2 skrll case IEEE80211_MODE_TURBO: 3464 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 3465 1.32.2.2 skrll break; 3466 1.32.2.2 skrll default: 3467 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 3468 1.32.2.2 skrll ("%s: invalid mode %u\n", __func__, mode)); 3469 1.32.2.2 skrll return 0; 3470 1.32.2.2 skrll } 3471 1.32.2.2 skrll rt = sc->sc_rates[mode]; 3472 1.32.2.2 skrll if (rt == NULL) 3473 1.32.2.2 skrll return 0; 3474 1.32.2.2 skrll if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 3475 1.32.2.2 skrll DPRINTF(ATH_DEBUG_ANY, 3476 1.32.2.2 skrll ("%s: rate table too small (%u > %u)\n", 3477 1.32.2.2 skrll __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 3478 1.32.2.2 skrll maxrates = IEEE80211_RATE_MAXSIZE; 3479 1.32.2.2 skrll } else 3480 1.32.2.2 skrll maxrates = rt->rateCount; 3481 1.32.2.2 skrll rs = &ic->ic_sup_rates[mode]; 3482 1.32.2.2 skrll for (i = 0; i < maxrates; i++) 3483 1.32.2.2 skrll rs->rs_rates[i] = rt->info[i].dot11Rate; 3484 1.32.2.2 skrll rs->rs_nrates = maxrates; 3485 1.32.2.2 skrll return 1; 3486 1.32.2.2 skrll } 3487 1.32.2.2 skrll 3488 1.32.2.2 skrll static void 3489 1.32.2.2 skrll ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 3490 1.32.2.2 skrll { 3491 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 3492 1.32.2.2 skrll int i; 3493 1.32.2.2 skrll 3494 1.32.2.2 skrll memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 3495 1.32.2.2 skrll rt = sc->sc_rates[mode]; 3496 1.32.2.2 skrll KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 3497 1.32.2.2 skrll for (i = 0; i < rt->rateCount; i++) 3498 1.32.2.2 skrll sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 3499 1.32.2.2 skrll memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 3500 1.32.2.2 skrll for (i = 0; i < 32; i++) 3501 1.32.2.2 skrll sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 3502 1.32.2.2 skrll sc->sc_currates = rt; 3503 1.32.2.2 skrll sc->sc_curmode = mode; 3504 1.32.2.2 skrll } 3505 1.32.2.2 skrll 3506 1.32.2.2 skrll /* 3507 1.32.2.2 skrll * Reset the rate control state for each 802.11 state transition. 3508 1.32.2.2 skrll */ 3509 1.32.2.2 skrll static void 3510 1.32.2.2 skrll ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 3511 1.32.2.2 skrll { 3512 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3513 1.32.2.2 skrll struct ieee80211_node *ni; 3514 1.32.2.2 skrll struct ath_node *an; 3515 1.32.2.2 skrll 3516 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) { 3517 1.32.2.2 skrll /* 3518 1.32.2.2 skrll * When operating as a station the node table holds 3519 1.32.2.2 skrll * the AP's that were discovered during scanning. 3520 1.32.2.2 skrll * For any other operating mode we want to reset the 3521 1.32.2.2 skrll * tx rate state of each node. 3522 1.32.2.2 skrll */ 3523 1.32.2.2 skrll TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 3524 1.32.2.2 skrll ni->ni_txrate = 0; /* use lowest rate */ 3525 1.32.2.2 skrll an = (struct ath_node *) ni; 3526 1.32.2.2 skrll an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 3527 1.32.2.2 skrll an->an_tx_upper = 0; 3528 1.32.2.2 skrll } 3529 1.32.2.2 skrll } 3530 1.32.2.2 skrll /* 3531 1.32.2.2 skrll * Reset local xmit state; this is really only meaningful 3532 1.32.2.2 skrll * when operating in station or adhoc mode. 3533 1.32.2.2 skrll */ 3534 1.32.2.2 skrll ni = ic->ic_bss; 3535 1.32.2.2 skrll an = (struct ath_node *) ni; 3536 1.32.2.2 skrll an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 3537 1.32.2.8 skrll if (state == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) { 3538 1.32.2.2 skrll /* start with highest negotiated rate */ 3539 1.32.2.2 skrll KASSERT(ni->ni_rates.rs_nrates > 0, 3540 1.32.2.2 skrll ("transition to RUN state w/ no rates!")); 3541 1.32.2.2 skrll ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 3542 1.32.2.2 skrll } else { 3543 1.32.2.2 skrll /* use lowest rate */ 3544 1.32.2.2 skrll ni->ni_txrate = 0; 3545 1.32.2.2 skrll } 3546 1.32.2.2 skrll } 3547 1.32.2.2 skrll 3548 1.32.2.10 skrll /* 3549 1.32.2.2 skrll * Examine and potentially adjust the transmit rate. 3550 1.32.2.2 skrll */ 3551 1.32.2.2 skrll static void 3552 1.32.2.2 skrll ath_rate_ctl(void *arg, struct ieee80211_node *ni) 3553 1.32.2.2 skrll { 3554 1.32.2.2 skrll struct ath_softc *sc = arg; 3555 1.32.2.2 skrll struct ath_node *an = (struct ath_node *) ni; 3556 1.32.2.2 skrll struct ieee80211_rateset *rs = &ni->ni_rates; 3557 1.32.2.2 skrll int mod = 0, orate, enough; 3558 1.32.2.2 skrll 3559 1.32.2.2 skrll /* 3560 1.32.2.2 skrll * Rate control 3561 1.32.2.2 skrll * XXX: very primitive version. 3562 1.32.2.2 skrll */ 3563 1.32.2.2 skrll sc->sc_stats.ast_rate_calls++; 3564 1.32.2.2 skrll 3565 1.32.2.2 skrll enough = (an->an_tx_ok + an->an_tx_err >= 10); 3566 1.32.2.2 skrll 3567 1.32.2.2 skrll /* no packet reached -> down */ 3568 1.32.2.2 skrll if (an->an_tx_err > 0 && an->an_tx_ok == 0) 3569 1.32.2.2 skrll mod = -1; 3570 1.32.2.2 skrll 3571 1.32.2.2 skrll /* all packets needs retry in average -> down */ 3572 1.32.2.2 skrll if (enough && an->an_tx_ok < an->an_tx_retr) 3573 1.32.2.2 skrll mod = -1; 3574 1.32.2.2 skrll 3575 1.32.2.2 skrll /* no error and less than 10% of packets needs retry -> up */ 3576 1.32.2.2 skrll if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 3577 1.32.2.2 skrll mod = 1; 3578 1.32.2.2 skrll 3579 1.32.2.2 skrll orate = ni->ni_txrate; 3580 1.32.2.2 skrll switch (mod) { 3581 1.32.2.2 skrll case 0: 3582 1.32.2.2 skrll if (enough && an->an_tx_upper > 0) 3583 1.32.2.2 skrll an->an_tx_upper--; 3584 1.32.2.2 skrll break; 3585 1.32.2.2 skrll case -1: 3586 1.32.2.2 skrll if (ni->ni_txrate > 0) { 3587 1.32.2.2 skrll ni->ni_txrate--; 3588 1.32.2.2 skrll sc->sc_stats.ast_rate_drop++; 3589 1.32.2.2 skrll } 3590 1.32.2.2 skrll an->an_tx_upper = 0; 3591 1.32.2.2 skrll break; 3592 1.32.2.2 skrll case 1: 3593 1.32.2.2 skrll if (++an->an_tx_upper < 2) 3594 1.32.2.2 skrll break; 3595 1.32.2.2 skrll an->an_tx_upper = 0; 3596 1.32.2.2 skrll if (ni->ni_txrate + 1 < rs->rs_nrates) { 3597 1.32.2.2 skrll ni->ni_txrate++; 3598 1.32.2.2 skrll sc->sc_stats.ast_rate_raise++; 3599 1.32.2.2 skrll } 3600 1.32.2.2 skrll break; 3601 1.32.2.2 skrll } 3602 1.32.2.2 skrll 3603 1.32.2.2 skrll if (ni->ni_txrate != orate) { 3604 1.32.2.2 skrll DPRINTF(ATH_DEBUG_RATE, 3605 1.32.2.2 skrll ("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 3606 1.32.2.2 skrll __func__, 3607 1.32.2.2 skrll (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 3608 1.32.2.2 skrll (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 3609 1.32.2.2 skrll an->an_tx_ok, an->an_tx_err, an->an_tx_retr)); 3610 1.32.2.2 skrll } 3611 1.32.2.2 skrll if (ni->ni_txrate != orate || enough) 3612 1.32.2.2 skrll an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 3613 1.32.2.2 skrll } 3614 1.32.2.2 skrll 3615 1.32.2.2 skrll #ifdef AR_DEBUG 3616 1.32.2.2 skrll #ifdef __FreeBSD__ 3617 1.32.2.2 skrll static int 3618 1.32.2.2 skrll sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 3619 1.32.2.2 skrll { 3620 1.32.2.2 skrll char dmode[64]; 3621 1.32.2.2 skrll int error; 3622 1.32.2.2 skrll 3623 1.32.2.2 skrll strncpy(dmode, "", sizeof(dmode) - 1); 3624 1.32.2.2 skrll dmode[sizeof(dmode) - 1] = '\0'; 3625 1.32.2.2 skrll error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 3626 1.32.2.2 skrll 3627 1.32.2.2 skrll if (error == 0 && req->newptr != NULL) { 3628 1.32.2.2 skrll struct ifnet *ifp; 3629 1.32.2.2 skrll struct ath_softc *sc; 3630 1.32.2.2 skrll 3631 1.32.2.2 skrll ifp = ifunit("ath0"); /* XXX */ 3632 1.32.2.2 skrll if (!ifp) 3633 1.32.2.2 skrll return EINVAL; 3634 1.32.2.2 skrll sc = ifp->if_softc; 3635 1.32.2.2 skrll if (strcmp(dmode, "hal") == 0) 3636 1.32.2.2 skrll ath_hal_dumpstate(sc->sc_ah); 3637 1.32.2.2 skrll else 3638 1.32.2.2 skrll return EINVAL; 3639 1.32.2.2 skrll } 3640 1.32.2.2 skrll return error; 3641 1.32.2.2 skrll } 3642 1.32.2.2 skrll SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 3643 1.32.2.2 skrll 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 3644 1.32.2.2 skrll #endif /* __FreeBSD__ */ 3645 1.32.2.2 skrll 3646 1.32.2.2 skrll #if 0 /* #ifdef __NetBSD__ */ 3647 1.32.2.2 skrll static int 3648 1.32.2.2 skrll sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 3649 1.32.2.2 skrll { 3650 1.32.2.2 skrll char dmode[64]; 3651 1.32.2.2 skrll int error; 3652 1.32.2.2 skrll 3653 1.32.2.2 skrll strncpy(dmode, "", sizeof(dmode) - 1); 3654 1.32.2.2 skrll dmode[sizeof(dmode) - 1] = '\0'; 3655 1.32.2.2 skrll error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 3656 1.32.2.2 skrll 3657 1.32.2.2 skrll if (error == 0 && req->newptr != NULL) { 3658 1.32.2.2 skrll struct ifnet *ifp; 3659 1.32.2.2 skrll struct ath_softc *sc; 3660 1.32.2.2 skrll 3661 1.32.2.2 skrll ifp = ifunit("ath0"); /* XXX */ 3662 1.32.2.2 skrll if (!ifp) 3663 1.32.2.2 skrll return EINVAL; 3664 1.32.2.2 skrll sc = ifp->if_softc; 3665 1.32.2.2 skrll if (strcmp(dmode, "hal") == 0) 3666 1.32.2.2 skrll ath_hal_dumpstate(sc->sc_ah); 3667 1.32.2.2 skrll else 3668 1.32.2.2 skrll return EINVAL; 3669 1.32.2.2 skrll } 3670 1.32.2.2 skrll return error; 3671 1.32.2.2 skrll } 3672 1.32.2.2 skrll SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 3673 1.32.2.2 skrll 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 3674 1.32.2.2 skrll #endif /* __NetBSD__ */ 3675 1.32.2.2 skrll 3676 1.32.2.2 skrll static void 3677 1.32.2.2 skrll ath_printrxbuf(struct ath_buf *bf, int done) 3678 1.32.2.2 skrll { 3679 1.32.2.2 skrll struct ath_desc *ds; 3680 1.32.2.2 skrll int i; 3681 1.32.2.2 skrll 3682 1.32.2.2 skrll for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 3683 1.32.2.2 skrll printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 3684 1.32.2.2 skrll i, ds, (struct ath_desc *)bf->bf_daddr + i, 3685 1.32.2.2 skrll ds->ds_link, ds->ds_data, 3686 1.32.2.2 skrll ds->ds_ctl0, ds->ds_ctl1, 3687 1.32.2.2 skrll ds->ds_hw[0], ds->ds_hw[1], 3688 1.32.2.2 skrll !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 3689 1.32.2.2 skrll } 3690 1.32.2.2 skrll } 3691 1.32.2.2 skrll 3692 1.32.2.2 skrll static void 3693 1.32.2.2 skrll ath_printtxbuf(struct ath_buf *bf, int done) 3694 1.32.2.2 skrll { 3695 1.32.2.2 skrll struct ath_desc *ds; 3696 1.32.2.2 skrll int i; 3697 1.32.2.2 skrll 3698 1.32.2.2 skrll for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 3699 1.32.2.2 skrll printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 3700 1.32.2.2 skrll i, ds, (struct ath_desc *)bf->bf_daddr + i, 3701 1.32.2.2 skrll ds->ds_link, ds->ds_data, 3702 1.32.2.2 skrll ds->ds_ctl0, ds->ds_ctl1, 3703 1.32.2.2 skrll ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 3704 1.32.2.2 skrll !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 3705 1.32.2.2 skrll } 3706 1.32.2.2 skrll } 3707 1.32.2.2 skrll #endif /* AR_DEBUG */ 3708
Indexes created Thu Oct 02 14:10:14 GMT 2025