ath.c revision 1.32.2.12
1 1.32.2.12 christos /* $NetBSD: ath.c,v 1.32.2.12 2005/12/11 10:28:50 christos Exp $ */ 2 1.32.2.2 skrll 3 1.32.2.2 skrll /*- 4 1.32.2.11 skrll * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 1.32.2.2 skrll * All rights reserved. 6 1.32.2.2 skrll * 7 1.32.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.32.2.2 skrll * modification, are permitted provided that the following conditions 9 1.32.2.2 skrll * are met: 10 1.32.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.32.2.2 skrll * notice, this list of conditions and the following disclaimer, 12 1.32.2.2 skrll * without modification. 13 1.32.2.2 skrll * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 1.32.2.2 skrll * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 1.32.2.2 skrll * redistribution must be conditioned upon including a substantially 16 1.32.2.2 skrll * similar Disclaimer requirement for further binary redistribution. 17 1.32.2.2 skrll * 3. Neither the names of the above-listed copyright holders nor the names 18 1.32.2.2 skrll * of any contributors may be used to endorse or promote products derived 19 1.32.2.2 skrll * from this software without specific prior written permission. 20 1.32.2.2 skrll * 21 1.32.2.2 skrll * Alternatively, this software may be distributed under the terms of the 22 1.32.2.2 skrll * GNU General Public License ("GPL") version 2 as published by the Free 23 1.32.2.2 skrll * Software Foundation. 24 1.32.2.2 skrll * 25 1.32.2.2 skrll * NO WARRANTY 26 1.32.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 1.32.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 1.32.2.2 skrll * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 1.32.2.2 skrll * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 1.32.2.2 skrll * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 1.32.2.2 skrll * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.32.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.32.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 1.32.2.2 skrll * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.32.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 1.32.2.2 skrll * THE POSSIBILITY OF SUCH DAMAGES. 37 1.32.2.2 skrll */ 38 1.32.2.2 skrll 39 1.32.2.2 skrll #include <sys/cdefs.h> 40 1.32.2.2 skrll #ifdef __FreeBSD__ 41 1.32.2.12 christos __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 1.32.2.2 skrll #endif 43 1.32.2.2 skrll #ifdef __NetBSD__ 44 1.32.2.12 christos __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.32.2.12 2005/12/11 10:28:50 christos Exp $"); 45 1.32.2.2 skrll #endif 46 1.32.2.2 skrll 47 1.32.2.2 skrll /* 48 1.32.2.2 skrll * Driver for the Atheros Wireless LAN controller. 49 1.32.2.2 skrll * 50 1.32.2.2 skrll * This software is derived from work of Atsushi Onoe; his contribution 51 1.32.2.2 skrll * is greatly appreciated. 52 1.32.2.2 skrll */ 53 1.32.2.2 skrll 54 1.32.2.2 skrll #include "opt_inet.h" 55 1.32.2.2 skrll 56 1.32.2.2 skrll #ifdef __NetBSD__ 57 1.32.2.2 skrll #include "bpfilter.h" 58 1.32.2.2 skrll #endif /* __NetBSD__ */ 59 1.32.2.2 skrll 60 1.32.2.2 skrll #include <sys/param.h> 61 1.32.2.11 skrll #include <sys/reboot.h> 62 1.32.2.11 skrll #include <sys/systm.h> 63 1.32.2.2 skrll #include <sys/types.h> 64 1.32.2.2 skrll #include <sys/sysctl.h> 65 1.32.2.11 skrll #include <sys/mbuf.h> 66 1.32.2.2 skrll #include <sys/malloc.h> 67 1.32.2.2 skrll #include <sys/lock.h> 68 1.32.2.2 skrll #include <sys/kernel.h> 69 1.32.2.2 skrll #include <sys/socket.h> 70 1.32.2.2 skrll #include <sys/sockio.h> 71 1.32.2.2 skrll #include <sys/errno.h> 72 1.32.2.2 skrll #include <sys/callout.h> 73 1.32.2.2 skrll #include <machine/bus.h> 74 1.32.2.2 skrll #include <sys/endian.h> 75 1.32.2.2 skrll 76 1.32.2.2 skrll #include <machine/bus.h> 77 1.32.2.11 skrll 78 1.32.2.2 skrll #include <net/if.h> 79 1.32.2.2 skrll #include <net/if_dl.h> 80 1.32.2.2 skrll #include <net/if_media.h> 81 1.32.2.11 skrll #include <net/if_types.h> 82 1.32.2.2 skrll #include <net/if_arp.h> 83 1.32.2.2 skrll #include <net/if_ether.h> 84 1.32.2.2 skrll #include <net/if_llc.h> 85 1.32.2.2 skrll 86 1.32.2.11 skrll #include <net80211/ieee80211_netbsd.h> 87 1.32.2.2 skrll #include <net80211/ieee80211_var.h> 88 1.32.2.2 skrll 89 1.32.2.2 skrll #if NBPFILTER > 0 90 1.32.2.2 skrll #include <net/bpf.h> 91 1.32.2.2 skrll #endif 92 1.32.2.2 skrll 93 1.32.2.2 skrll #ifdef INET 94 1.32.2.11 skrll #include <netinet/in.h> 95 1.32.2.2 skrll #endif 96 1.32.2.2 skrll 97 1.32.2.11 skrll #include <sys/device.h> 98 1.32.2.11 skrll #include <dev/ic/ath_netbsd.h> 99 1.32.2.2 skrll 100 1.32.2.2 skrll #define AR_DEBUG 101 1.32.2.2 skrll #include <dev/ic/athvar.h> 102 1.32.2.11 skrll #include <contrib/dev/ic/athhal_desc.h> 103 1.32.2.11 skrll #include <contrib/dev/ic/athhal_devid.h> /* XXX for softled */ 104 1.32.2.2 skrll 105 1.32.2.10 skrll /* unaligned little endian access */ 106 1.32.2.2 skrll #define LE_READ_2(p) \ 107 1.32.2.2 skrll ((u_int16_t) \ 108 1.32.2.2 skrll ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 109 1.32.2.2 skrll #define LE_READ_4(p) \ 110 1.32.2.2 skrll ((u_int32_t) \ 111 1.32.2.2 skrll ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 112 1.32.2.2 skrll (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 113 1.32.2.2 skrll 114 1.32.2.11 skrll enum { 115 1.32.2.11 skrll ATH_LED_TX, 116 1.32.2.11 skrll ATH_LED_RX, 117 1.32.2.11 skrll ATH_LED_POLL, 118 1.32.2.11 skrll }; 119 1.32.2.11 skrll 120 1.32.2.11 skrll static int ath_ifinit(struct ifnet *); 121 1.32.2.11 skrll static int ath_init(struct ath_softc *); 122 1.32.2.11 skrll static void ath_stop_locked(struct ifnet *, int); 123 1.32.2.8 skrll static void ath_stop(struct ifnet *, int); 124 1.32.2.2 skrll static void ath_start(struct ifnet *); 125 1.32.2.2 skrll static int ath_media_change(struct ifnet *); 126 1.32.2.2 skrll static void ath_watchdog(struct ifnet *); 127 1.32.2.2 skrll static int ath_ioctl(struct ifnet *, u_long, caddr_t); 128 1.32.2.2 skrll static void ath_fatal_proc(void *, int); 129 1.32.2.2 skrll static void ath_rxorn_proc(void *, int); 130 1.32.2.2 skrll static void ath_bmiss_proc(void *, int); 131 1.32.2.11 skrll static int ath_key_alloc(struct ieee80211com *, 132 1.32.2.12 christos const struct ieee80211_key *, 133 1.32.2.12 christos ieee80211_keyix *, ieee80211_keyix *); 134 1.32.2.11 skrll static int ath_key_delete(struct ieee80211com *, 135 1.32.2.11 skrll const struct ieee80211_key *); 136 1.32.2.11 skrll static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 137 1.32.2.11 skrll const u_int8_t mac[IEEE80211_ADDR_LEN]); 138 1.32.2.11 skrll static void ath_key_update_begin(struct ieee80211com *); 139 1.32.2.11 skrll static void ath_key_update_end(struct ieee80211com *); 140 1.32.2.2 skrll static void ath_mode_init(struct ath_softc *); 141 1.32.2.11 skrll static void ath_setslottime(struct ath_softc *); 142 1.32.2.11 skrll static void ath_updateslot(struct ifnet *); 143 1.32.2.11 skrll static int ath_beaconq_setup(struct ath_hal *); 144 1.32.2.2 skrll static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 145 1.32.2.11 skrll static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 146 1.32.2.11 skrll static void ath_beacon_proc(void *, int); 147 1.32.2.11 skrll static void ath_bstuck_proc(void *, int); 148 1.32.2.2 skrll static void ath_beacon_free(struct ath_softc *); 149 1.32.2.2 skrll static void ath_beacon_config(struct ath_softc *); 150 1.32.2.11 skrll static void ath_descdma_cleanup(struct ath_softc *sc, 151 1.32.2.11 skrll struct ath_descdma *, ath_bufhead *); 152 1.32.2.2 skrll static int ath_desc_alloc(struct ath_softc *); 153 1.32.2.2 skrll static void ath_desc_free(struct ath_softc *); 154 1.32.2.11 skrll static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 155 1.32.2.11 skrll static void ath_node_free(struct ieee80211_node *); 156 1.32.2.11 skrll static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 157 1.32.2.2 skrll static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 158 1.32.2.11 skrll static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 159 1.32.2.11 skrll struct ieee80211_node *ni, 160 1.32.2.11 skrll int subtype, int rssi, u_int32_t rstamp); 161 1.32.2.11 skrll static void ath_setdefantenna(struct ath_softc *, u_int); 162 1.32.2.2 skrll static void ath_rx_proc(void *, int); 163 1.32.2.11 skrll static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 164 1.32.2.11 skrll static int ath_tx_setup(struct ath_softc *, int, int); 165 1.32.2.11 skrll static int ath_wme_update(struct ieee80211com *); 166 1.32.2.11 skrll static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 167 1.32.2.11 skrll static void ath_tx_cleanup(struct ath_softc *); 168 1.32.2.2 skrll static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 169 1.32.2.2 skrll struct ath_buf *, struct mbuf *); 170 1.32.2.11 skrll static void ath_tx_proc_q0(void *, int); 171 1.32.2.11 skrll static void ath_tx_proc_q0123(void *, int); 172 1.32.2.2 skrll static void ath_tx_proc(void *, int); 173 1.32.2.2 skrll static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 174 1.32.2.2 skrll static void ath_draintxq(struct ath_softc *); 175 1.32.2.2 skrll static void ath_stoprecv(struct ath_softc *); 176 1.32.2.2 skrll static int ath_startrecv(struct ath_softc *); 177 1.32.2.11 skrll static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 178 1.32.2.2 skrll static void ath_next_scan(void *); 179 1.32.2.2 skrll static void ath_calibrate(void *); 180 1.32.2.2 skrll static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 181 1.32.2.11 skrll static void ath_setup_stationkey(struct ieee80211_node *); 182 1.32.2.12 christos static void ath_newassoc(struct ieee80211_node *, int); 183 1.32.2.11 skrll static int ath_getchannels(struct ath_softc *, u_int cc, 184 1.32.2.11 skrll HAL_BOOL outdoor, HAL_BOOL xchanmode); 185 1.32.2.11 skrll static void ath_led_event(struct ath_softc *, int); 186 1.32.2.11 skrll static void ath_update_txpow(struct ath_softc *); 187 1.32.2.2 skrll 188 1.32.2.11 skrll static int ath_rate_setup(struct ath_softc *, u_int mode); 189 1.32.2.2 skrll static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 190 1.32.2.2 skrll 191 1.32.2.2 skrll #ifdef __NetBSD__ 192 1.32.2.2 skrll int ath_enable(struct ath_softc *); 193 1.32.2.2 skrll void ath_disable(struct ath_softc *); 194 1.32.2.2 skrll void ath_power(int, void *); 195 1.32.2.2 skrll #endif 196 1.32.2.2 skrll 197 1.32.2.12 christos #if NBPFILTER > 0 198 1.32.2.11 skrll static void ath_bpfattach(struct ath_softc *); 199 1.32.2.12 christos #endif 200 1.32.2.11 skrll static void ath_announce(struct ath_softc *); 201 1.32.2.2 skrll 202 1.32.2.11 skrll int ath_dwelltime = 200; /* 5 channels/second */ 203 1.32.2.11 skrll int ath_calinterval = 30; /* calibrate every 30 secs */ 204 1.32.2.11 skrll int ath_outdoor = AH_TRUE; /* outdoor operation */ 205 1.32.2.11 skrll int ath_xchanmode = AH_TRUE; /* enable extended channels */ 206 1.32.2.11 skrll int ath_countrycode = CTRY_DEFAULT; /* country code */ 207 1.32.2.11 skrll int ath_regdomain = 0; /* regulatory domain */ 208 1.32.2.11 skrll int ath_debug = 0; 209 1.32.2.2 skrll 210 1.32.2.2 skrll #ifdef AR_DEBUG 211 1.32.2.2 skrll enum { 212 1.32.2.2 skrll ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 213 1.32.2.2 skrll ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 214 1.32.2.2 skrll ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 215 1.32.2.2 skrll ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 216 1.32.2.2 skrll ATH_DEBUG_RATE = 0x00000010, /* rate control */ 217 1.32.2.2 skrll ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 218 1.32.2.2 skrll ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 219 1.32.2.2 skrll ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 220 1.32.2.2 skrll ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 221 1.32.2.2 skrll ATH_DEBUG_INTR = 0x00001000, /* ISR */ 222 1.32.2.2 skrll ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 223 1.32.2.2 skrll ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 224 1.32.2.2 skrll ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 225 1.32.2.2 skrll ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 226 1.32.2.11 skrll ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 227 1.32.2.11 skrll ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 228 1.32.2.11 skrll ATH_DEBUG_NODE = 0x00080000, /* node management */ 229 1.32.2.11 skrll ATH_DEBUG_LED = 0x00100000, /* led management */ 230 1.32.2.11 skrll ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 231 1.32.2.2 skrll ATH_DEBUG_ANY = 0xffffffff 232 1.32.2.2 skrll }; 233 1.32.2.11 skrll #define IFF_DUMPPKTS(sc, m) \ 234 1.32.2.11 skrll ((sc->sc_debug & (m)) || \ 235 1.32.2.11 skrll (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 236 1.32.2.11 skrll #define DPRINTF(sc, m, fmt, ...) do { \ 237 1.32.2.11 skrll if (sc->sc_debug & (m)) \ 238 1.32.2.11 skrll printf(fmt, __VA_ARGS__); \ 239 1.32.2.11 skrll } while (0) 240 1.32.2.11 skrll #define KEYPRINTF(sc, ix, hk, mac) do { \ 241 1.32.2.11 skrll if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 242 1.32.2.11 skrll ath_keyprint(__func__, ix, hk, mac); \ 243 1.32.2.11 skrll } while (0) 244 1.32.2.11 skrll static void ath_printrxbuf(struct ath_buf *bf, int); 245 1.32.2.11 skrll static void ath_printtxbuf(struct ath_buf *bf, int); 246 1.32.2.2 skrll #else 247 1.32.2.11 skrll #define IFF_DUMPPKTS(sc, m) \ 248 1.32.2.11 skrll ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 249 1.32.2.11 skrll #define DPRINTF(m, fmt, ...) 250 1.32.2.11 skrll #define KEYPRINTF(sc, k, ix, mac) 251 1.32.2.2 skrll #endif 252 1.32.2.2 skrll 253 1.32.2.2 skrll #ifdef __NetBSD__ 254 1.32.2.2 skrll int 255 1.32.2.2 skrll ath_activate(struct device *self, enum devact act) 256 1.32.2.2 skrll { 257 1.32.2.2 skrll struct ath_softc *sc = (struct ath_softc *)self; 258 1.32.2.2 skrll int rv = 0, s; 259 1.32.2.2 skrll 260 1.32.2.2 skrll s = splnet(); 261 1.32.2.2 skrll switch (act) { 262 1.32.2.2 skrll case DVACT_ACTIVATE: 263 1.32.2.2 skrll rv = EOPNOTSUPP; 264 1.32.2.2 skrll break; 265 1.32.2.2 skrll case DVACT_DEACTIVATE: 266 1.32.2.11 skrll if_deactivate(&sc->sc_if); 267 1.32.2.2 skrll break; 268 1.32.2.2 skrll } 269 1.32.2.2 skrll splx(s); 270 1.32.2.2 skrll return rv; 271 1.32.2.2 skrll } 272 1.32.2.2 skrll 273 1.32.2.2 skrll int 274 1.32.2.2 skrll ath_enable(struct ath_softc *sc) 275 1.32.2.2 skrll { 276 1.32.2.2 skrll if (ATH_IS_ENABLED(sc) == 0) { 277 1.32.2.2 skrll if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 278 1.32.2.2 skrll printf("%s: device enable failed\n", 279 1.32.2.2 skrll sc->sc_dev.dv_xname); 280 1.32.2.2 skrll return (EIO); 281 1.32.2.2 skrll } 282 1.32.2.2 skrll sc->sc_flags |= ATH_ENABLED; 283 1.32.2.2 skrll } 284 1.32.2.2 skrll return (0); 285 1.32.2.2 skrll } 286 1.32.2.2 skrll 287 1.32.2.2 skrll void 288 1.32.2.2 skrll ath_disable(struct ath_softc *sc) 289 1.32.2.2 skrll { 290 1.32.2.2 skrll if (!ATH_IS_ENABLED(sc)) 291 1.32.2.2 skrll return; 292 1.32.2.2 skrll if (sc->sc_disable != NULL) 293 1.32.2.2 skrll (*sc->sc_disable)(sc); 294 1.32.2.2 skrll sc->sc_flags &= ~ATH_ENABLED; 295 1.32.2.2 skrll } 296 1.32.2.2 skrll #endif /* __NetBSD__ */ 297 1.32.2.2 skrll 298 1.32.2.11 skrll MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 299 1.32.2.11 skrll 300 1.32.2.2 skrll int 301 1.32.2.2 skrll ath_attach(u_int16_t devid, struct ath_softc *sc) 302 1.32.2.2 skrll { 303 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 304 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 305 1.32.2.11 skrll struct ath_hal *ah = NULL; 306 1.32.2.2 skrll HAL_STATUS status; 307 1.32.2.11 skrll int error = 0, i; 308 1.32.2.2 skrll 309 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 310 1.32.2.2 skrll 311 1.32.2.2 skrll memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 312 1.32.2.2 skrll 313 1.32.2.11 skrll ah = ath_hal_attach(devid, sc, sc->sc_st, ATH_BUSHANDLE2HAL(sc->sc_sh), 314 1.32.2.11 skrll &status); 315 1.32.2.2 skrll if (ah == NULL) { 316 1.32.2.2 skrll if_printf(ifp, "unable to attach hardware; HAL status %u\n", 317 1.32.2.2 skrll status); 318 1.32.2.2 skrll error = ENXIO; 319 1.32.2.2 skrll goto bad; 320 1.32.2.2 skrll } 321 1.32.2.2 skrll if (ah->ah_abi != HAL_ABI_VERSION) { 322 1.32.2.11 skrll if_printf(ifp, "HAL ABI mismatch detected " 323 1.32.2.11 skrll "(HAL:0x%x != driver:0x%x)\n", 324 1.32.2.2 skrll ah->ah_abi, HAL_ABI_VERSION); 325 1.32.2.2 skrll error = ENXIO; 326 1.32.2.2 skrll goto bad; 327 1.32.2.2 skrll } 328 1.32.2.2 skrll sc->sc_ah = ah; 329 1.32.2.2 skrll sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 330 1.32.2.2 skrll 331 1.32.2.2 skrll /* 332 1.32.2.11 skrll * Check if the MAC has multi-rate retry support. 333 1.32.2.11 skrll * We do this by trying to setup a fake extended 334 1.32.2.11 skrll * descriptor. MAC's that don't have support will 335 1.32.2.11 skrll * return false w/o doing anything. MAC's that do 336 1.32.2.11 skrll * support it will return true w/o doing anything. 337 1.32.2.11 skrll */ 338 1.32.2.11 skrll sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 339 1.32.2.11 skrll 340 1.32.2.11 skrll /* 341 1.32.2.11 skrll * Check if the device has hardware counters for PHY 342 1.32.2.11 skrll * errors. If so we need to enable the MIB interrupt 343 1.32.2.11 skrll * so we can act on stat triggers. 344 1.32.2.11 skrll */ 345 1.32.2.11 skrll if (ath_hal_hwphycounters(ah)) 346 1.32.2.11 skrll sc->sc_needmib = 1; 347 1.32.2.11 skrll 348 1.32.2.11 skrll /* 349 1.32.2.11 skrll * Get the hardware key cache size. 350 1.32.2.11 skrll */ 351 1.32.2.11 skrll sc->sc_keymax = ath_hal_keycachesize(ah); 352 1.32.2.11 skrll if (sc->sc_keymax > ATH_KEYMAX) { 353 1.32.2.11 skrll if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 354 1.32.2.11 skrll ATH_KEYMAX, sc->sc_keymax); 355 1.32.2.11 skrll sc->sc_keymax = ATH_KEYMAX; 356 1.32.2.11 skrll } 357 1.32.2.11 skrll /* 358 1.32.2.11 skrll * Reset the key cache since some parts do not 359 1.32.2.11 skrll * reset the contents on initial power up. 360 1.32.2.11 skrll */ 361 1.32.2.11 skrll for (i = 0; i < sc->sc_keymax; i++) 362 1.32.2.11 skrll ath_hal_keyreset(ah, i); 363 1.32.2.11 skrll /* 364 1.32.2.11 skrll * Mark key cache slots associated with global keys 365 1.32.2.11 skrll * as in use. If we knew TKIP was not to be used we 366 1.32.2.11 skrll * could leave the +32, +64, and +32+64 slots free. 367 1.32.2.11 skrll * XXX only for splitmic. 368 1.32.2.11 skrll */ 369 1.32.2.11 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) { 370 1.32.2.11 skrll setbit(sc->sc_keymap, i); 371 1.32.2.11 skrll setbit(sc->sc_keymap, i+32); 372 1.32.2.11 skrll setbit(sc->sc_keymap, i+64); 373 1.32.2.11 skrll setbit(sc->sc_keymap, i+32+64); 374 1.32.2.11 skrll } 375 1.32.2.11 skrll 376 1.32.2.11 skrll /* 377 1.32.2.2 skrll * Collect the channel list using the default country 378 1.32.2.2 skrll * code and including outdoor channels. The 802.11 layer 379 1.32.2.2 skrll * is resposible for filtering this list based on settings 380 1.32.2.2 skrll * like the phy mode. 381 1.32.2.2 skrll */ 382 1.32.2.11 skrll error = ath_getchannels(sc, ath_countrycode, 383 1.32.2.11 skrll ath_outdoor, ath_xchanmode); 384 1.32.2.2 skrll if (error != 0) 385 1.32.2.2 skrll goto bad; 386 1.32.2.2 skrll 387 1.32.2.2 skrll /* 388 1.32.2.2 skrll * Setup rate tables for all potential media types. 389 1.32.2.2 skrll */ 390 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11A); 391 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11B); 392 1.32.2.2 skrll ath_rate_setup(sc, IEEE80211_MODE_11G); 393 1.32.2.11 skrll ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 394 1.32.2.11 skrll ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 395 1.32.2.11 skrll /* NB: setup here so ath_rate_update is happy */ 396 1.32.2.11 skrll ath_setcurmode(sc, IEEE80211_MODE_11A); 397 1.32.2.2 skrll 398 1.32.2.11 skrll /* 399 1.32.2.11 skrll * Allocate tx+rx descriptors and populate the lists. 400 1.32.2.11 skrll */ 401 1.32.2.2 skrll error = ath_desc_alloc(sc); 402 1.32.2.2 skrll if (error != 0) { 403 1.32.2.2 skrll if_printf(ifp, "failed to allocate descriptors: %d\n", error); 404 1.32.2.2 skrll goto bad; 405 1.32.2.2 skrll } 406 1.32.2.11 skrll ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 407 1.32.2.11 skrll ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 408 1.32.2.2 skrll 409 1.32.2.2 skrll ATH_TXBUF_LOCK_INIT(sc); 410 1.32.2.2 skrll 411 1.32.2.11 skrll TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 412 1.32.2.11 skrll TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 413 1.32.2.11 skrll TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 414 1.32.2.11 skrll TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 415 1.32.2.11 skrll TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 416 1.32.2.2 skrll 417 1.32.2.2 skrll /* 418 1.32.2.11 skrll * Allocate hardware transmit queues: one queue for 419 1.32.2.11 skrll * beacon frames and one data queue for each QoS 420 1.32.2.11 skrll * priority. Note that the hal handles reseting 421 1.32.2.11 skrll * these queues at the needed time. 422 1.32.2.11 skrll * 423 1.32.2.11 skrll * XXX PS-Poll 424 1.32.2.2 skrll */ 425 1.32.2.11 skrll sc->sc_bhalq = ath_beaconq_setup(ah); 426 1.32.2.2 skrll if (sc->sc_bhalq == (u_int) -1) { 427 1.32.2.2 skrll if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 428 1.32.2.11 skrll error = EIO; 429 1.32.2.11 skrll goto bad2; 430 1.32.2.11 skrll } 431 1.32.2.11 skrll sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 432 1.32.2.11 skrll if (sc->sc_cabq == NULL) { 433 1.32.2.11 skrll if_printf(ifp, "unable to setup CAB xmit queue!\n"); 434 1.32.2.11 skrll error = EIO; 435 1.32.2.2 skrll goto bad2; 436 1.32.2.2 skrll } 437 1.32.2.11 skrll /* NB: insure BK queue is the lowest priority h/w queue */ 438 1.32.2.11 skrll if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 439 1.32.2.11 skrll if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 440 1.32.2.11 skrll ieee80211_wme_acnames[WME_AC_BK]); 441 1.32.2.11 skrll error = EIO; 442 1.32.2.11 skrll goto bad2; 443 1.32.2.11 skrll } 444 1.32.2.11 skrll if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 445 1.32.2.11 skrll !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 446 1.32.2.11 skrll !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 447 1.32.2.11 skrll /* 448 1.32.2.11 skrll * Not enough hardware tx queues to properly do WME; 449 1.32.2.11 skrll * just punt and assign them all to the same h/w queue. 450 1.32.2.11 skrll * We could do a better job of this if, for example, 451 1.32.2.11 skrll * we allocate queues when we switch from station to 452 1.32.2.11 skrll * AP mode. 453 1.32.2.11 skrll */ 454 1.32.2.11 skrll if (sc->sc_ac2q[WME_AC_VI] != NULL) 455 1.32.2.11 skrll ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 456 1.32.2.11 skrll if (sc->sc_ac2q[WME_AC_BE] != NULL) 457 1.32.2.11 skrll ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 458 1.32.2.11 skrll sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 459 1.32.2.11 skrll sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 460 1.32.2.11 skrll sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 461 1.32.2.11 skrll } 462 1.32.2.11 skrll 463 1.32.2.11 skrll /* 464 1.32.2.11 skrll * Special case certain configurations. Note the 465 1.32.2.11 skrll * CAB queue is handled by these specially so don't 466 1.32.2.11 skrll * include them when checking the txq setup mask. 467 1.32.2.11 skrll */ 468 1.32.2.11 skrll switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 469 1.32.2.11 skrll case 0x01: 470 1.32.2.11 skrll TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 471 1.32.2.11 skrll break; 472 1.32.2.11 skrll case 0x0f: 473 1.32.2.11 skrll TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 474 1.32.2.11 skrll break; 475 1.32.2.11 skrll default: 476 1.32.2.11 skrll TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 477 1.32.2.11 skrll break; 478 1.32.2.11 skrll } 479 1.32.2.2 skrll 480 1.32.2.11 skrll /* 481 1.32.2.11 skrll * Setup rate control. Some rate control modules 482 1.32.2.11 skrll * call back to change the anntena state so expose 483 1.32.2.11 skrll * the necessary entry points. 484 1.32.2.11 skrll * XXX maybe belongs in struct ath_ratectrl? 485 1.32.2.11 skrll */ 486 1.32.2.11 skrll sc->sc_setdefantenna = ath_setdefantenna; 487 1.32.2.11 skrll sc->sc_rc = ath_rate_attach(sc); 488 1.32.2.11 skrll if (sc->sc_rc == NULL) { 489 1.32.2.11 skrll error = EIO; 490 1.32.2.2 skrll goto bad2; 491 1.32.2.2 skrll } 492 1.32.2.2 skrll 493 1.32.2.11 skrll sc->sc_blinking = 0; 494 1.32.2.11 skrll sc->sc_ledstate = 1; 495 1.32.2.11 skrll sc->sc_ledon = 0; /* low true */ 496 1.32.2.11 skrll sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 497 1.32.2.11 skrll ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 498 1.32.2.11 skrll /* 499 1.32.2.11 skrll * Auto-enable soft led processing for IBM cards and for 500 1.32.2.11 skrll * 5211 minipci cards. Users can also manually enable/disable 501 1.32.2.11 skrll * support with a sysctl. 502 1.32.2.11 skrll */ 503 1.32.2.11 skrll sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 504 1.32.2.11 skrll if (sc->sc_softled) { 505 1.32.2.11 skrll ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 506 1.32.2.11 skrll ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 507 1.32.2.11 skrll } 508 1.32.2.11 skrll 509 1.32.2.2 skrll ifp->if_softc = sc; 510 1.32.2.2 skrll ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 511 1.32.2.2 skrll ifp->if_start = ath_start; 512 1.32.2.2 skrll ifp->if_watchdog = ath_watchdog; 513 1.32.2.2 skrll ifp->if_ioctl = ath_ioctl; 514 1.32.2.11 skrll ifp->if_init = ath_ifinit; 515 1.32.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 516 1.32.2.2 skrll 517 1.32.2.11 skrll ic->ic_ifp = ifp; 518 1.32.2.11 skrll ic->ic_reset = ath_reset; 519 1.32.2.2 skrll ic->ic_newassoc = ath_newassoc; 520 1.32.2.11 skrll ic->ic_updateslot = ath_updateslot; 521 1.32.2.11 skrll ic->ic_wme.wme_update = ath_wme_update; 522 1.32.2.2 skrll /* XXX not right but it's not used anywhere important */ 523 1.32.2.2 skrll ic->ic_phytype = IEEE80211_T_OFDM; 524 1.32.2.2 skrll ic->ic_opmode = IEEE80211_M_STA; 525 1.32.2.11 skrll ic->ic_caps = 526 1.32.2.11 skrll IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 527 1.32.2.2 skrll | IEEE80211_C_HOSTAP /* hostap mode */ 528 1.32.2.2 skrll | IEEE80211_C_MONITOR /* monitor mode */ 529 1.32.2.2 skrll | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 530 1.32.2.11 skrll | IEEE80211_C_SHSLOT /* short slot time supported */ 531 1.32.2.11 skrll | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 532 1.32.2.2 skrll ; 533 1.32.2.11 skrll /* 534 1.32.2.11 skrll * Query the hal to figure out h/w crypto support. 535 1.32.2.11 skrll */ 536 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 537 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_WEP; 538 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 539 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_AES; 540 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 541 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_AES_CCM; 542 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 543 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_CKIP; 544 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 545 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_TKIP; 546 1.32.2.11 skrll /* 547 1.32.2.11 skrll * Check if h/w does the MIC and/or whether the 548 1.32.2.11 skrll * separate key cache entries are required to 549 1.32.2.11 skrll * handle both tx+rx MIC keys. 550 1.32.2.11 skrll */ 551 1.32.2.11 skrll if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 552 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_TKIPMIC; 553 1.32.2.11 skrll if (ath_hal_tkipsplit(ah)) 554 1.32.2.11 skrll sc->sc_splitmic = 1; 555 1.32.2.11 skrll } 556 1.32.2.11 skrll sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 557 1.32.2.11 skrll sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 558 1.32.2.12 christos /* 559 1.32.2.12 christos * TPC support can be done either with a global cap or 560 1.32.2.12 christos * per-packet support. The latter is not available on 561 1.32.2.12 christos * all parts. We're a bit pedantic here as all parts 562 1.32.2.12 christos * support a global cap. 563 1.32.2.12 christos */ 564 1.32.2.12 christos if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 565 1.32.2.12 christos ic->ic_caps |= IEEE80211_C_TXPMGT; 566 1.32.2.11 skrll 567 1.32.2.11 skrll /* 568 1.32.2.11 skrll * Mark WME capability only if we have sufficient 569 1.32.2.11 skrll * hardware queues to do proper priority scheduling. 570 1.32.2.11 skrll */ 571 1.32.2.11 skrll if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 572 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_WME; 573 1.32.2.11 skrll /* 574 1.32.2.11 skrll * Check for misc other capabilities. 575 1.32.2.11 skrll */ 576 1.32.2.11 skrll if (ath_hal_hasbursting(ah)) 577 1.32.2.11 skrll ic->ic_caps |= IEEE80211_C_BURST; 578 1.32.2.11 skrll 579 1.32.2.11 skrll /* 580 1.32.2.11 skrll * Indicate we need the 802.11 header padded to a 581 1.32.2.11 skrll * 32-bit boundary for 4-address and QoS frames. 582 1.32.2.11 skrll */ 583 1.32.2.11 skrll ic->ic_flags |= IEEE80211_F_DATAPAD; 584 1.32.2.11 skrll 585 1.32.2.11 skrll /* 586 1.32.2.12 christos * Query the hal about antenna support. 587 1.32.2.12 christos */ 588 1.32.2.12 christos sc->sc_defant = ath_hal_getdefantenna(ah); 589 1.32.2.12 christos 590 1.32.2.12 christos /* 591 1.32.2.11 skrll * Not all chips have the VEOL support we want to 592 1.32.2.11 skrll * use with IBSS beacons; check here for it. 593 1.32.2.11 skrll */ 594 1.32.2.11 skrll sc->sc_hasveol = ath_hal_hasveol(ah); 595 1.32.2.2 skrll 596 1.32.2.2 skrll /* get mac address from hardware */ 597 1.32.2.2 skrll ath_hal_getmac(ah, ic->ic_myaddr); 598 1.32.2.2 skrll 599 1.32.2.2 skrll if_attach(ifp); 600 1.32.2.2 skrll /* call MI attach routine. */ 601 1.32.2.11 skrll ieee80211_ifattach(ic); 602 1.32.2.2 skrll /* override default methods */ 603 1.32.2.2 skrll ic->ic_node_alloc = ath_node_alloc; 604 1.32.2.2 skrll sc->sc_node_free = ic->ic_node_free; 605 1.32.2.2 skrll ic->ic_node_free = ath_node_free; 606 1.32.2.2 skrll ic->ic_node_getrssi = ath_node_getrssi; 607 1.32.2.3 skrll sc->sc_recv_mgmt = ic->ic_recv_mgmt; 608 1.32.2.3 skrll ic->ic_recv_mgmt = ath_recv_mgmt; 609 1.32.2.11 skrll sc->sc_newstate = ic->ic_newstate; 610 1.32.2.11 skrll ic->ic_newstate = ath_newstate; 611 1.32.2.12 christos ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 612 1.32.2.11 skrll ic->ic_crypto.cs_key_alloc = ath_key_alloc; 613 1.32.2.11 skrll ic->ic_crypto.cs_key_delete = ath_key_delete; 614 1.32.2.11 skrll ic->ic_crypto.cs_key_set = ath_key_set; 615 1.32.2.11 skrll ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 616 1.32.2.11 skrll ic->ic_crypto.cs_key_update_end = ath_key_update_end; 617 1.32.2.2 skrll /* complete initialization */ 618 1.32.2.11 skrll ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 619 1.32.2.2 skrll 620 1.32.2.12 christos #if NBPFILTER > 0 621 1.32.2.11 skrll ath_bpfattach(sc); 622 1.32.2.12 christos #endif 623 1.32.2.2 skrll 624 1.32.2.2 skrll #ifdef __NetBSD__ 625 1.32.2.2 skrll sc->sc_flags |= ATH_ATTACHED; 626 1.32.2.2 skrll /* 627 1.32.2.2 skrll * Make sure the interface is shutdown during reboot. 628 1.32.2.2 skrll */ 629 1.32.2.2 skrll sc->sc_sdhook = shutdownhook_establish(ath_shutdown, sc); 630 1.32.2.2 skrll if (sc->sc_sdhook == NULL) 631 1.32.2.2 skrll printf("%s: WARNING: unable to establish shutdown hook\n", 632 1.32.2.2 skrll sc->sc_dev.dv_xname); 633 1.32.2.2 skrll sc->sc_powerhook = powerhook_establish(ath_power, sc); 634 1.32.2.2 skrll if (sc->sc_powerhook == NULL) 635 1.32.2.2 skrll printf("%s: WARNING: unable to establish power hook\n", 636 1.32.2.2 skrll sc->sc_dev.dv_xname); 637 1.32.2.2 skrll #endif 638 1.32.2.12 christos 639 1.32.2.12 christos /* 640 1.32.2.12 christos * Setup dynamic sysctl's now that country code and 641 1.32.2.12 christos * regdomain are available from the hal. 642 1.32.2.12 christos */ 643 1.32.2.12 christos ath_sysctlattach(sc); 644 1.32.2.12 christos 645 1.32.2.11 skrll ieee80211_announce(ic); 646 1.32.2.11 skrll ath_announce(sc); 647 1.32.2.2 skrll return 0; 648 1.32.2.2 skrll bad2: 649 1.32.2.11 skrll ath_tx_cleanup(sc); 650 1.32.2.2 skrll ath_desc_free(sc); 651 1.32.2.2 skrll bad: 652 1.32.2.2 skrll if (ah) 653 1.32.2.2 skrll ath_hal_detach(ah); 654 1.32.2.2 skrll sc->sc_invalid = 1; 655 1.32.2.2 skrll return error; 656 1.32.2.2 skrll } 657 1.32.2.2 skrll 658 1.32.2.2 skrll int 659 1.32.2.2 skrll ath_detach(struct ath_softc *sc) 660 1.32.2.2 skrll { 661 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 662 1.32.2.11 skrll int s; 663 1.32.2.2 skrll 664 1.32.2.2 skrll if ((sc->sc_flags & ATH_ATTACHED) == 0) 665 1.32.2.2 skrll return (0); 666 1.32.2.2 skrll 667 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 668 1.32.2.11 skrll __func__, ifp->if_flags); 669 1.32.2.11 skrll 670 1.32.2.11 skrll s = splnet(); 671 1.32.2.8 skrll ath_stop(ifp, 1); 672 1.32.2.2 skrll #if NBPFILTER > 0 673 1.32.2.2 skrll bpfdetach(ifp); 674 1.32.2.2 skrll #endif 675 1.32.2.11 skrll /* 676 1.32.2.11 skrll * NB: the order of these is important: 677 1.32.2.11 skrll * o call the 802.11 layer before detaching the hal to 678 1.32.2.11 skrll * insure callbacks into the driver to delete global 679 1.32.2.11 skrll * key cache entries can be handled 680 1.32.2.11 skrll * o reclaim the tx queue data structures after calling 681 1.32.2.11 skrll * the 802.11 layer as we'll get called back to reclaim 682 1.32.2.11 skrll * node state and potentially want to use them 683 1.32.2.11 skrll * o to cleanup the tx queues the hal is called, so detach 684 1.32.2.11 skrll * it last 685 1.32.2.11 skrll * Other than that, it's straightforward... 686 1.32.2.11 skrll */ 687 1.32.2.11 skrll ieee80211_ifdetach(&sc->sc_ic); 688 1.32.2.11 skrll ath_rate_detach(sc->sc_rc); 689 1.32.2.2 skrll ath_desc_free(sc); 690 1.32.2.11 skrll ath_tx_cleanup(sc); 691 1.32.2.11 skrll sysctl_teardown(&sc->sc_sysctllog); 692 1.32.2.2 skrll ath_hal_detach(sc->sc_ah); 693 1.32.2.2 skrll if_detach(ifp); 694 1.32.2.11 skrll splx(s); 695 1.32.2.2 skrll powerhook_disestablish(sc->sc_powerhook); 696 1.32.2.2 skrll shutdownhook_disestablish(sc->sc_sdhook); 697 1.32.2.2 skrll 698 1.32.2.2 skrll return 0; 699 1.32.2.2 skrll } 700 1.32.2.2 skrll 701 1.32.2.2 skrll #ifdef __NetBSD__ 702 1.32.2.2 skrll void 703 1.32.2.2 skrll ath_power(int why, void *arg) 704 1.32.2.2 skrll { 705 1.32.2.2 skrll struct ath_softc *sc = arg; 706 1.32.2.2 skrll int s; 707 1.32.2.2 skrll 708 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "ath_power(%d)\n", why); 709 1.32.2.2 skrll 710 1.32.2.2 skrll s = splnet(); 711 1.32.2.2 skrll switch (why) { 712 1.32.2.2 skrll case PWR_SUSPEND: 713 1.32.2.2 skrll case PWR_STANDBY: 714 1.32.2.2 skrll ath_suspend(sc, why); 715 1.32.2.2 skrll break; 716 1.32.2.2 skrll case PWR_RESUME: 717 1.32.2.2 skrll ath_resume(sc, why); 718 1.32.2.2 skrll break; 719 1.32.2.2 skrll case PWR_SOFTSUSPEND: 720 1.32.2.2 skrll case PWR_SOFTSTANDBY: 721 1.32.2.2 skrll case PWR_SOFTRESUME: 722 1.32.2.2 skrll break; 723 1.32.2.2 skrll } 724 1.32.2.2 skrll splx(s); 725 1.32.2.2 skrll } 726 1.32.2.2 skrll #endif 727 1.32.2.2 skrll 728 1.32.2.2 skrll void 729 1.32.2.2 skrll ath_suspend(struct ath_softc *sc, int why) 730 1.32.2.2 skrll { 731 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 732 1.32.2.2 skrll 733 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 734 1.32.2.11 skrll __func__, ifp->if_flags); 735 1.32.2.2 skrll 736 1.32.2.8 skrll ath_stop(ifp, 1); 737 1.32.2.2 skrll if (sc->sc_power != NULL) 738 1.32.2.2 skrll (*sc->sc_power)(sc, why); 739 1.32.2.2 skrll } 740 1.32.2.2 skrll 741 1.32.2.2 skrll void 742 1.32.2.2 skrll ath_resume(struct ath_softc *sc, int why) 743 1.32.2.2 skrll { 744 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 745 1.32.2.2 skrll 746 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 747 1.32.2.11 skrll __func__, ifp->if_flags); 748 1.32.2.2 skrll 749 1.32.2.2 skrll if (ifp->if_flags & IFF_UP) { 750 1.32.2.11 skrll ath_init(sc); 751 1.32.2.2 skrll #if 0 752 1.32.2.2 skrll (void)ath_intr(sc); 753 1.32.2.2 skrll #endif 754 1.32.2.2 skrll if (sc->sc_power != NULL) 755 1.32.2.2 skrll (*sc->sc_power)(sc, why); 756 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 757 1.32.2.2 skrll ath_start(ifp); 758 1.32.2.2 skrll } 759 1.32.2.11 skrll if (sc->sc_softled) { 760 1.32.2.11 skrll ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 761 1.32.2.11 skrll ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 762 1.32.2.11 skrll } 763 1.32.2.2 skrll } 764 1.32.2.2 skrll 765 1.32.2.2 skrll void 766 1.32.2.2 skrll ath_shutdown(void *arg) 767 1.32.2.2 skrll { 768 1.32.2.2 skrll struct ath_softc *sc = arg; 769 1.32.2.2 skrll 770 1.32.2.11 skrll ath_stop(&sc->sc_if, 1); 771 1.32.2.2 skrll } 772 1.32.2.2 skrll 773 1.32.2.11 skrll /* 774 1.32.2.11 skrll * Interrupt handler. Most of the actual processing is deferred. 775 1.32.2.11 skrll */ 776 1.32.2.2 skrll int 777 1.32.2.2 skrll ath_intr(void *arg) 778 1.32.2.2 skrll { 779 1.32.2.11 skrll struct ath_softc *sc = arg; 780 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 781 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 782 1.32.2.2 skrll HAL_INT status; 783 1.32.2.2 skrll 784 1.32.2.2 skrll if (sc->sc_invalid) { 785 1.32.2.2 skrll /* 786 1.32.2.2 skrll * The hardware is not ready/present, don't touch anything. 787 1.32.2.2 skrll * Note this can happen early on if the IRQ is shared. 788 1.32.2.2 skrll */ 789 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 790 1.32.2.2 skrll return 0; 791 1.32.2.2 skrll } 792 1.32.2.2 skrll if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 793 1.32.2.2 skrll return 0; 794 1.32.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 795 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 796 1.32.2.11 skrll __func__, ifp->if_flags); 797 1.32.2.2 skrll ath_hal_getisr(ah, &status); /* clear ISR */ 798 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable further intr's */ 799 1.32.2.2 skrll return 1; /* XXX */ 800 1.32.2.2 skrll } 801 1.32.2.11 skrll /* 802 1.32.2.11 skrll * Figure out the reason(s) for the interrupt. Note 803 1.32.2.11 skrll * that the hal returns a pseudo-ISR that may include 804 1.32.2.11 skrll * bits we haven't explicitly enabled so we mask the 805 1.32.2.11 skrll * value to insure we only process bits we requested. 806 1.32.2.11 skrll */ 807 1.32.2.2 skrll ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 808 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 809 1.32.2.2 skrll status &= sc->sc_imask; /* discard unasked for bits */ 810 1.32.2.2 skrll if (status & HAL_INT_FATAL) { 811 1.32.2.11 skrll /* 812 1.32.2.11 skrll * Fatal errors are unrecoverable. Typically 813 1.32.2.11 skrll * these are caused by DMA errors. Unfortunately 814 1.32.2.11 skrll * the exact reason is not (presently) returned 815 1.32.2.11 skrll * by the hal. 816 1.32.2.11 skrll */ 817 1.32.2.2 skrll sc->sc_stats.ast_hardware++; 818 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable intr's until reset */ 819 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 820 1.32.2.2 skrll } else if (status & HAL_INT_RXORN) { 821 1.32.2.2 skrll sc->sc_stats.ast_rxorn++; 822 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable intr's until reset */ 823 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 824 1.32.2.2 skrll } else { 825 1.32.2.11 skrll if (status & HAL_INT_SWBA) { 826 1.32.2.11 skrll /* 827 1.32.2.11 skrll * Software beacon alert--time to send a beacon. 828 1.32.2.11 skrll * Handle beacon transmission directly; deferring 829 1.32.2.11 skrll * this is too slow to meet timing constraints 830 1.32.2.11 skrll * under load. 831 1.32.2.11 skrll */ 832 1.32.2.11 skrll ath_beacon_proc(sc, 0); 833 1.32.2.11 skrll } 834 1.32.2.2 skrll if (status & HAL_INT_RXEOL) { 835 1.32.2.2 skrll /* 836 1.32.2.2 skrll * NB: the hardware should re-read the link when 837 1.32.2.2 skrll * RXE bit is written, but it doesn't work at 838 1.32.2.2 skrll * least on older hardware revs. 839 1.32.2.2 skrll */ 840 1.32.2.2 skrll sc->sc_stats.ast_rxeol++; 841 1.32.2.2 skrll sc->sc_rxlink = NULL; 842 1.32.2.2 skrll } 843 1.32.2.2 skrll if (status & HAL_INT_TXURN) { 844 1.32.2.2 skrll sc->sc_stats.ast_txurn++; 845 1.32.2.2 skrll /* bump tx trigger level */ 846 1.32.2.2 skrll ath_hal_updatetxtriglevel(ah, AH_TRUE); 847 1.32.2.2 skrll } 848 1.32.2.2 skrll if (status & HAL_INT_RX) 849 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 850 1.32.2.2 skrll if (status & HAL_INT_TX) 851 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 852 1.32.2.2 skrll if (status & HAL_INT_BMISS) { 853 1.32.2.2 skrll sc->sc_stats.ast_bmiss++; 854 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 855 1.32.2.11 skrll } 856 1.32.2.11 skrll if (status & HAL_INT_MIB) { 857 1.32.2.11 skrll sc->sc_stats.ast_mib++; 858 1.32.2.11 skrll /* 859 1.32.2.11 skrll * Disable interrupts until we service the MIB 860 1.32.2.11 skrll * interrupt; otherwise it will continue to fire. 861 1.32.2.11 skrll */ 862 1.32.2.11 skrll ath_hal_intrset(ah, 0); 863 1.32.2.11 skrll /* 864 1.32.2.11 skrll * Let the hal handle the event. We assume it will 865 1.32.2.11 skrll * clear whatever condition caused the interrupt. 866 1.32.2.11 skrll */ 867 1.32.2.11 skrll ath_hal_mibevent(ah, 868 1.32.2.11 skrll &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 869 1.32.2.11 skrll ath_hal_intrset(ah, sc->sc_imask); 870 1.32.2.2 skrll } 871 1.32.2.2 skrll } 872 1.32.2.2 skrll return 1; 873 1.32.2.2 skrll } 874 1.32.2.2 skrll 875 1.32.2.2 skrll static void 876 1.32.2.2 skrll ath_fatal_proc(void *arg, int pending) 877 1.32.2.2 skrll { 878 1.32.2.2 skrll struct ath_softc *sc = arg; 879 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 880 1.32.2.2 skrll 881 1.32.2.11 skrll if_printf(ifp, "hardware error; resetting\n"); 882 1.32.2.11 skrll ath_reset(ifp); 883 1.32.2.2 skrll } 884 1.32.2.2 skrll 885 1.32.2.2 skrll static void 886 1.32.2.2 skrll ath_rxorn_proc(void *arg, int pending) 887 1.32.2.2 skrll { 888 1.32.2.2 skrll struct ath_softc *sc = arg; 889 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 890 1.32.2.2 skrll 891 1.32.2.11 skrll if_printf(ifp, "rx FIFO overrun; resetting\n"); 892 1.32.2.11 skrll ath_reset(ifp); 893 1.32.2.2 skrll } 894 1.32.2.2 skrll 895 1.32.2.2 skrll static void 896 1.32.2.2 skrll ath_bmiss_proc(void *arg, int pending) 897 1.32.2.2 skrll { 898 1.32.2.2 skrll struct ath_softc *sc = arg; 899 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 900 1.32.2.2 skrll 901 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 902 1.32.2.11 skrll KASSERT(ic->ic_opmode == IEEE80211_M_STA, 903 1.32.2.11 skrll ("unexpect operating mode %u", ic->ic_opmode)); 904 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_RUN) { 905 1.32.2.2 skrll /* 906 1.32.2.2 skrll * Rather than go directly to scan state, try to 907 1.32.2.2 skrll * reassociate first. If that fails then the state 908 1.32.2.2 skrll * machine will drop us into scanning after timing 909 1.32.2.2 skrll * out waiting for a probe response. 910 1.32.2.2 skrll */ 911 1.32.2.11 skrll NET_LOCK_GIANT(); 912 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 913 1.32.2.11 skrll NET_UNLOCK_GIANT(); 914 1.32.2.2 skrll } 915 1.32.2.2 skrll } 916 1.32.2.2 skrll 917 1.32.2.2 skrll static u_int 918 1.32.2.2 skrll ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 919 1.32.2.2 skrll { 920 1.32.2.11 skrll #define N(a) (sizeof(a) / sizeof(a[0])) 921 1.32.2.11 skrll static const u_int modeflags[] = { 922 1.32.2.11 skrll 0, /* IEEE80211_MODE_AUTO */ 923 1.32.2.11 skrll CHANNEL_A, /* IEEE80211_MODE_11A */ 924 1.32.2.11 skrll CHANNEL_B, /* IEEE80211_MODE_11B */ 925 1.32.2.11 skrll CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 926 1.32.2.11 skrll 0, /* IEEE80211_MODE_FH */ 927 1.32.2.11 skrll CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 928 1.32.2.11 skrll CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 929 1.32.2.11 skrll }; 930 1.32.2.2 skrll enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 931 1.32.2.2 skrll 932 1.32.2.11 skrll KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 933 1.32.2.11 skrll KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 934 1.32.2.11 skrll return modeflags[mode]; 935 1.32.2.11 skrll #undef N 936 1.32.2.2 skrll } 937 1.32.2.2 skrll 938 1.32.2.2 skrll static int 939 1.32.2.11 skrll ath_ifinit(struct ifnet *ifp) 940 1.32.2.2 skrll { 941 1.32.2.11 skrll struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 942 1.32.2.11 skrll 943 1.32.2.11 skrll return ath_init(sc); 944 1.32.2.2 skrll } 945 1.32.2.2 skrll 946 1.32.2.2 skrll static int 947 1.32.2.11 skrll ath_init(struct ath_softc *sc) 948 1.32.2.2 skrll { 949 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 950 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 951 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 952 1.32.2.2 skrll HAL_STATUS status; 953 1.32.2.2 skrll int error = 0; 954 1.32.2.2 skrll 955 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 956 1.32.2.11 skrll __func__, ifp->if_flags); 957 1.32.2.11 skrll 958 1.32.2.11 skrll ATH_LOCK(sc); 959 1.32.2.2 skrll 960 1.32.2.2 skrll if ((error = ath_enable(sc)) != 0) 961 1.32.2.2 skrll return error; 962 1.32.2.2 skrll 963 1.32.2.2 skrll /* 964 1.32.2.2 skrll * Stop anything previously setup. This is safe 965 1.32.2.2 skrll * whether this is the first time through or not. 966 1.32.2.2 skrll */ 967 1.32.2.11 skrll ath_stop_locked(ifp, 0); 968 1.32.2.2 skrll 969 1.32.2.2 skrll /* 970 1.32.2.2 skrll * The basic interface to setting the hardware in a good 971 1.32.2.2 skrll * state is ``reset''. On return the hardware is known to 972 1.32.2.2 skrll * be powered up and with interrupts disabled. This must 973 1.32.2.2 skrll * be followed by initialization of the appropriate bits 974 1.32.2.2 skrll * and then setup of the interrupt mask. 975 1.32.2.2 skrll */ 976 1.32.2.12 christos sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 977 1.32.2.12 christos sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 978 1.32.2.11 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 979 1.32.2.2 skrll if_printf(ifp, "unable to reset hardware; hal status %u\n", 980 1.32.2.2 skrll status); 981 1.32.2.3 skrll error = EIO; 982 1.32.2.2 skrll goto done; 983 1.32.2.2 skrll } 984 1.32.2.2 skrll 985 1.32.2.2 skrll /* 986 1.32.2.11 skrll * This is needed only to setup initial state 987 1.32.2.11 skrll * but it's best done after a reset. 988 1.32.2.11 skrll */ 989 1.32.2.11 skrll ath_update_txpow(sc); 990 1.32.2.12 christos /* 991 1.32.2.12 christos * Likewise this is set during reset so update 992 1.32.2.12 christos * state cached in the driver. 993 1.32.2.12 christos */ 994 1.32.2.12 christos sc->sc_diversity = ath_hal_getdiversity(ah); 995 1.32.2.11 skrll 996 1.32.2.11 skrll /* 997 1.32.2.2 skrll * Setup the hardware after reset: the key cache 998 1.32.2.2 skrll * is filled as needed and the receive engine is 999 1.32.2.2 skrll * set going. Frame transmit is handled entirely 1000 1.32.2.2 skrll * in the frame output path; there's nothing to do 1001 1.32.2.2 skrll * here except setup the interrupt mask. 1002 1.32.2.2 skrll */ 1003 1.32.2.2 skrll if ((error = ath_startrecv(sc)) != 0) { 1004 1.32.2.2 skrll if_printf(ifp, "unable to start recv logic\n"); 1005 1.32.2.2 skrll goto done; 1006 1.32.2.2 skrll } 1007 1.32.2.2 skrll 1008 1.32.2.2 skrll /* 1009 1.32.2.2 skrll * Enable interrupts. 1010 1.32.2.2 skrll */ 1011 1.32.2.2 skrll sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1012 1.32.2.2 skrll | HAL_INT_RXEOL | HAL_INT_RXORN 1013 1.32.2.2 skrll | HAL_INT_FATAL | HAL_INT_GLOBAL; 1014 1.32.2.11 skrll /* 1015 1.32.2.11 skrll * Enable MIB interrupts when there are hardware phy counters. 1016 1.32.2.11 skrll * Note we only do this (at the moment) for station mode. 1017 1.32.2.11 skrll */ 1018 1.32.2.11 skrll if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1019 1.32.2.11 skrll sc->sc_imask |= HAL_INT_MIB; 1020 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 1021 1.32.2.2 skrll 1022 1.32.2.2 skrll ifp->if_flags |= IFF_RUNNING; 1023 1.32.2.2 skrll ic->ic_state = IEEE80211_S_INIT; 1024 1.32.2.2 skrll 1025 1.32.2.2 skrll /* 1026 1.32.2.2 skrll * The hardware should be ready to go now so it's safe 1027 1.32.2.2 skrll * to kick the 802.11 state machine as it's likely to 1028 1.32.2.2 skrll * immediately call back to us to send mgmt frames. 1029 1.32.2.2 skrll */ 1030 1.32.2.12 christos ath_chan_change(sc, ic->ic_curchan); 1031 1.32.2.11 skrll if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1032 1.32.2.11 skrll if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1033 1.32.2.11 skrll ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1034 1.32.2.11 skrll } else 1035 1.32.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1036 1.32.2.2 skrll done: 1037 1.32.2.11 skrll ATH_UNLOCK(sc); 1038 1.32.2.2 skrll return error; 1039 1.32.2.2 skrll } 1040 1.32.2.2 skrll 1041 1.32.2.2 skrll static void 1042 1.32.2.11 skrll ath_stop_locked(struct ifnet *ifp, int disable) 1043 1.32.2.2 skrll { 1044 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1045 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 1046 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1047 1.32.2.2 skrll 1048 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1049 1.32.2.11 skrll __func__, sc->sc_invalid, ifp->if_flags); 1050 1.32.2.2 skrll 1051 1.32.2.11 skrll ATH_LOCK_ASSERT(sc); 1052 1.32.2.2 skrll if (ifp->if_flags & IFF_RUNNING) { 1053 1.32.2.2 skrll /* 1054 1.32.2.2 skrll * Shutdown the hardware and driver: 1055 1.32.2.11 skrll * reset 802.11 state machine 1056 1.32.2.2 skrll * turn off timers 1057 1.32.2.11 skrll * disable interrupts 1058 1.32.2.11 skrll * turn off the radio 1059 1.32.2.2 skrll * clear transmit machinery 1060 1.32.2.2 skrll * clear receive machinery 1061 1.32.2.2 skrll * drain and release tx queues 1062 1.32.2.2 skrll * reclaim beacon resources 1063 1.32.2.2 skrll * power down hardware 1064 1.32.2.2 skrll * 1065 1.32.2.2 skrll * Note that some of this work is not possible if the 1066 1.32.2.2 skrll * hardware is gone (invalid). 1067 1.32.2.2 skrll */ 1068 1.32.2.11 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1069 1.32.2.2 skrll ifp->if_flags &= ~IFF_RUNNING; 1070 1.32.2.2 skrll ifp->if_timer = 0; 1071 1.32.2.11 skrll if (!sc->sc_invalid) { 1072 1.32.2.11 skrll if (sc->sc_softled) { 1073 1.32.2.11 skrll callout_stop(&sc->sc_ledtimer); 1074 1.32.2.11 skrll ath_hal_gpioset(ah, sc->sc_ledpin, 1075 1.32.2.11 skrll !sc->sc_ledon); 1076 1.32.2.11 skrll sc->sc_blinking = 0; 1077 1.32.2.11 skrll } 1078 1.32.2.2 skrll ath_hal_intrset(ah, 0); 1079 1.32.2.11 skrll } 1080 1.32.2.2 skrll ath_draintxq(sc); 1081 1.32.2.11 skrll if (!sc->sc_invalid) { 1082 1.32.2.2 skrll ath_stoprecv(sc); 1083 1.32.2.11 skrll ath_hal_phydisable(ah); 1084 1.32.2.11 skrll } else 1085 1.32.2.2 skrll sc->sc_rxlink = NULL; 1086 1.32.2.2 skrll IF_PURGE(&ifp->if_snd); 1087 1.32.2.2 skrll ath_beacon_free(sc); 1088 1.32.2.8 skrll if (disable) 1089 1.32.2.8 skrll ath_disable(sc); 1090 1.32.2.2 skrll } 1091 1.32.2.11 skrll } 1092 1.32.2.11 skrll 1093 1.32.2.11 skrll static void 1094 1.32.2.11 skrll ath_stop(struct ifnet *ifp, int disable) 1095 1.32.2.11 skrll { 1096 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 1097 1.32.2.11 skrll 1098 1.32.2.11 skrll ATH_LOCK(sc); 1099 1.32.2.11 skrll ath_stop_locked(ifp, disable); 1100 1.32.2.11 skrll if (!sc->sc_invalid) { 1101 1.32.2.11 skrll /* 1102 1.32.2.11 skrll * Set the chip in full sleep mode. Note that we are 1103 1.32.2.11 skrll * careful to do this only when bringing the interface 1104 1.32.2.11 skrll * completely to a stop. When the chip is in this state 1105 1.32.2.11 skrll * it must be carefully woken up or references to 1106 1.32.2.11 skrll * registers in the PCI clock domain may freeze the bus 1107 1.32.2.11 skrll * (and system). This varies by chip and is mostly an 1108 1.32.2.11 skrll * issue with newer parts that go to sleep more quickly. 1109 1.32.2.11 skrll */ 1110 1.32.2.11 skrll ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 1111 1.32.2.11 skrll } 1112 1.32.2.11 skrll ATH_UNLOCK(sc); 1113 1.32.2.2 skrll } 1114 1.32.2.2 skrll 1115 1.32.2.2 skrll /* 1116 1.32.2.2 skrll * Reset the hardware w/o losing operational state. This is 1117 1.32.2.2 skrll * basically a more efficient way of doing ath_stop, ath_init, 1118 1.32.2.2 skrll * followed by state transitions to the current 802.11 1119 1.32.2.11 skrll * operational state. Used to recover from various errors and 1120 1.32.2.11 skrll * to reset or reload hardware state. 1121 1.32.2.2 skrll */ 1122 1.32.2.11 skrll int 1123 1.32.2.11 skrll ath_reset(struct ifnet *ifp) 1124 1.32.2.2 skrll { 1125 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 1126 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1127 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1128 1.32.2.2 skrll struct ieee80211_channel *c; 1129 1.32.2.2 skrll HAL_STATUS status; 1130 1.32.2.2 skrll 1131 1.32.2.2 skrll /* 1132 1.32.2.2 skrll * Convert to a HAL channel description with the flags 1133 1.32.2.2 skrll * constrained to reflect the current operating mode. 1134 1.32.2.2 skrll */ 1135 1.32.2.12 christos c = ic->ic_curchan; 1136 1.32.2.11 skrll sc->sc_curchan.channel = c->ic_freq; 1137 1.32.2.11 skrll sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1138 1.32.2.2 skrll 1139 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable interrupts */ 1140 1.32.2.2 skrll ath_draintxq(sc); /* stop xmit side */ 1141 1.32.2.2 skrll ath_stoprecv(sc); /* stop recv side */ 1142 1.32.2.2 skrll /* NB: indicate channel change so we do a full reset */ 1143 1.32.2.11 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1144 1.32.2.2 skrll if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1145 1.32.2.2 skrll __func__, status); 1146 1.32.2.11 skrll ath_update_txpow(sc); /* update tx power state */ 1147 1.32.2.12 christos sc->sc_diversity = ath_hal_getdiversity(ah); 1148 1.32.2.2 skrll if (ath_startrecv(sc) != 0) /* restart recv */ 1149 1.32.2.2 skrll if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1150 1.32.2.11 skrll /* 1151 1.32.2.11 skrll * We may be doing a reset in response to an ioctl 1152 1.32.2.11 skrll * that changes the channel so update any state that 1153 1.32.2.11 skrll * might change as a result. 1154 1.32.2.11 skrll */ 1155 1.32.2.11 skrll ath_chan_change(sc, c); 1156 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_RUN) 1157 1.32.2.2 skrll ath_beacon_config(sc); /* restart beacons */ 1158 1.32.2.11 skrll ath_hal_intrset(ah, sc->sc_imask); 1159 1.32.2.11 skrll 1160 1.32.2.11 skrll ath_start(ifp); /* restart xmit */ 1161 1.32.2.11 skrll return 0; 1162 1.32.2.2 skrll } 1163 1.32.2.2 skrll 1164 1.32.2.2 skrll static void 1165 1.32.2.2 skrll ath_start(struct ifnet *ifp) 1166 1.32.2.2 skrll { 1167 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 1168 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1169 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1170 1.32.2.2 skrll struct ieee80211_node *ni; 1171 1.32.2.2 skrll struct ath_buf *bf; 1172 1.32.2.2 skrll struct mbuf *m; 1173 1.32.2.2 skrll struct ieee80211_frame *wh; 1174 1.32.2.11 skrll struct ether_header *eh; 1175 1.32.2.2 skrll 1176 1.32.2.2 skrll if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 1177 1.32.2.2 skrll return; 1178 1.32.2.2 skrll for (;;) { 1179 1.32.2.2 skrll /* 1180 1.32.2.2 skrll * Grab a TX buffer and associated resources. 1181 1.32.2.2 skrll */ 1182 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 1183 1.32.2.11 skrll bf = STAILQ_FIRST(&sc->sc_txbuf); 1184 1.32.2.2 skrll if (bf != NULL) 1185 1.32.2.11 skrll STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1186 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 1187 1.32.2.2 skrll if (bf == NULL) { 1188 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1189 1.32.2.11 skrll __func__); 1190 1.32.2.2 skrll sc->sc_stats.ast_tx_qstop++; 1191 1.32.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1192 1.32.2.2 skrll break; 1193 1.32.2.2 skrll } 1194 1.32.2.2 skrll /* 1195 1.32.2.2 skrll * Poll the management queue for frames; they 1196 1.32.2.2 skrll * have priority over normal data frames. 1197 1.32.2.2 skrll */ 1198 1.32.2.2 skrll IF_DEQUEUE(&ic->ic_mgtq, m); 1199 1.32.2.2 skrll if (m == NULL) { 1200 1.32.2.2 skrll /* 1201 1.32.2.2 skrll * No data frames go out unless we're associated. 1202 1.32.2.2 skrll */ 1203 1.32.2.2 skrll if (ic->ic_state != IEEE80211_S_RUN) { 1204 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 1205 1.32.2.11 skrll "%s: ignore data packet, state %u\n", 1206 1.32.2.11 skrll __func__, ic->ic_state); 1207 1.32.2.2 skrll sc->sc_stats.ast_tx_discard++; 1208 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 1209 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1210 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 1211 1.32.2.2 skrll break; 1212 1.32.2.2 skrll } 1213 1.32.2.11 skrll IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1214 1.32.2.2 skrll if (m == NULL) { 1215 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 1216 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1217 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 1218 1.32.2.2 skrll break; 1219 1.32.2.2 skrll } 1220 1.32.2.11 skrll /* 1221 1.32.2.11 skrll * Find the node for the destination so we can do 1222 1.32.2.11 skrll * things like power save and fast frames aggregation. 1223 1.32.2.11 skrll */ 1224 1.32.2.11 skrll if (m->m_len < sizeof(struct ether_header) && 1225 1.32.2.11 skrll (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1226 1.32.2.11 skrll ic->ic_stats.is_tx_nobuf++; /* XXX */ 1227 1.32.2.11 skrll ni = NULL; 1228 1.32.2.11 skrll goto bad; 1229 1.32.2.11 skrll } 1230 1.32.2.11 skrll eh = mtod(m, struct ether_header *); 1231 1.32.2.11 skrll ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1232 1.32.2.11 skrll if (ni == NULL) { 1233 1.32.2.11 skrll /* NB: ieee80211_find_txnode does stat+msg */ 1234 1.32.2.11 skrll m_freem(m); 1235 1.32.2.11 skrll goto bad; 1236 1.32.2.11 skrll } 1237 1.32.2.11 skrll if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1238 1.32.2.11 skrll (m->m_flags & M_PWR_SAV) == 0) { 1239 1.32.2.11 skrll /* 1240 1.32.2.11 skrll * Station in power save mode; pass the frame 1241 1.32.2.11 skrll * to the 802.11 layer and continue. We'll get 1242 1.32.2.11 skrll * the frame back when the time is right. 1243 1.32.2.11 skrll */ 1244 1.32.2.11 skrll ieee80211_pwrsave(ic, ni, m); 1245 1.32.2.11 skrll goto reclaim; 1246 1.32.2.11 skrll } 1247 1.32.2.11 skrll /* calculate priority so we can find the tx queue */ 1248 1.32.2.11 skrll if (ieee80211_classify(ic, m, ni)) { 1249 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_XMIT, 1250 1.32.2.11 skrll "%s: discard, classification failure\n", 1251 1.32.2.11 skrll __func__); 1252 1.32.2.11 skrll m_freem(m); 1253 1.32.2.11 skrll goto bad; 1254 1.32.2.11 skrll } 1255 1.32.2.2 skrll ifp->if_opackets++; 1256 1.32.2.2 skrll 1257 1.32.2.2 skrll #if NBPFILTER > 0 1258 1.32.2.2 skrll if (ifp->if_bpf) 1259 1.32.2.2 skrll bpf_mtap(ifp->if_bpf, m); 1260 1.32.2.2 skrll #endif 1261 1.32.2.2 skrll /* 1262 1.32.2.2 skrll * Encapsulate the packet in prep for transmission. 1263 1.32.2.2 skrll */ 1264 1.32.2.11 skrll m = ieee80211_encap(ic, m, ni); 1265 1.32.2.2 skrll if (m == NULL) { 1266 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 1267 1.32.2.11 skrll "%s: encapsulation failure\n", 1268 1.32.2.11 skrll __func__); 1269 1.32.2.2 skrll sc->sc_stats.ast_tx_encap++; 1270 1.32.2.2 skrll goto bad; 1271 1.32.2.2 skrll } 1272 1.32.2.2 skrll } else { 1273 1.32.2.2 skrll /* 1274 1.32.2.2 skrll * Hack! The referenced node pointer is in the 1275 1.32.2.2 skrll * rcvif field of the packet header. This is 1276 1.32.2.2 skrll * placed there by ieee80211_mgmt_output because 1277 1.32.2.2 skrll * we need to hold the reference with the frame 1278 1.32.2.2 skrll * and there's no other way (other than packet 1279 1.32.2.2 skrll * tags which we consider too expensive to use) 1280 1.32.2.2 skrll * to pass it along. 1281 1.32.2.2 skrll */ 1282 1.32.2.2 skrll ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1283 1.32.2.2 skrll m->m_pkthdr.rcvif = NULL; 1284 1.32.2.2 skrll 1285 1.32.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1286 1.32.2.2 skrll if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1287 1.32.2.2 skrll IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1288 1.32.2.2 skrll /* fill time stamp */ 1289 1.32.2.2 skrll u_int64_t tsf; 1290 1.32.2.2 skrll u_int32_t *tstamp; 1291 1.32.2.2 skrll 1292 1.32.2.2 skrll tsf = ath_hal_gettsf64(ah); 1293 1.32.2.2 skrll /* XXX: adjust 100us delay to xmit */ 1294 1.32.2.2 skrll tsf += 100; 1295 1.32.2.2 skrll tstamp = (u_int32_t *)&wh[1]; 1296 1.32.2.2 skrll tstamp[0] = htole32(tsf & 0xffffffff); 1297 1.32.2.2 skrll tstamp[1] = htole32(tsf >> 32); 1298 1.32.2.2 skrll } 1299 1.32.2.2 skrll sc->sc_stats.ast_tx_mgmt++; 1300 1.32.2.2 skrll } 1301 1.32.2.2 skrll 1302 1.32.2.2 skrll if (ath_tx_start(sc, ni, bf, m)) { 1303 1.32.2.2 skrll bad: 1304 1.32.2.2 skrll ifp->if_oerrors++; 1305 1.32.2.11 skrll reclaim: 1306 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 1307 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1308 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 1309 1.32.2.3 skrll if (ni != NULL) 1310 1.32.2.11 skrll ieee80211_free_node(ni); 1311 1.32.2.2 skrll continue; 1312 1.32.2.2 skrll } 1313 1.32.2.2 skrll 1314 1.32.2.2 skrll sc->sc_tx_timer = 5; 1315 1.32.2.2 skrll ifp->if_timer = 1; 1316 1.32.2.2 skrll } 1317 1.32.2.2 skrll } 1318 1.32.2.2 skrll 1319 1.32.2.2 skrll static int 1320 1.32.2.2 skrll ath_media_change(struct ifnet *ifp) 1321 1.32.2.2 skrll { 1322 1.32.2.11 skrll #define IS_UP(ifp) \ 1323 1.32.2.12 christos ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1324 1.32.2.2 skrll int error; 1325 1.32.2.2 skrll 1326 1.32.2.2 skrll error = ieee80211_media_change(ifp); 1327 1.32.2.2 skrll if (error == ENETRESET) { 1328 1.32.2.11 skrll if (IS_UP(ifp)) 1329 1.32.2.11 skrll ath_init(ifp->if_softc); /* XXX lose error */ 1330 1.32.2.2 skrll error = 0; 1331 1.32.2.2 skrll } 1332 1.32.2.2 skrll return error; 1333 1.32.2.11 skrll #undef IS_UP 1334 1.32.2.2 skrll } 1335 1.32.2.2 skrll 1336 1.32.2.11 skrll #ifdef AR_DEBUG 1337 1.32.2.2 skrll static void 1338 1.32.2.11 skrll ath_keyprint(const char *tag, u_int ix, 1339 1.32.2.11 skrll const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1340 1.32.2.2 skrll { 1341 1.32.2.11 skrll static const char *ciphers[] = { 1342 1.32.2.11 skrll "WEP", 1343 1.32.2.11 skrll "AES-OCB", 1344 1.32.2.11 skrll "AES-CCM", 1345 1.32.2.11 skrll "CKIP", 1346 1.32.2.11 skrll "TKIP", 1347 1.32.2.11 skrll "CLR", 1348 1.32.2.11 skrll }; 1349 1.32.2.11 skrll int i, n; 1350 1.32.2.11 skrll 1351 1.32.2.11 skrll printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1352 1.32.2.11 skrll for (i = 0, n = hk->kv_len; i < n; i++) 1353 1.32.2.11 skrll printf("%02x", hk->kv_val[i]); 1354 1.32.2.11 skrll printf(" mac %s", ether_sprintf(mac)); 1355 1.32.2.11 skrll if (hk->kv_type == HAL_CIPHER_TKIP) { 1356 1.32.2.11 skrll printf(" mic "); 1357 1.32.2.11 skrll for (i = 0; i < sizeof(hk->kv_mic); i++) 1358 1.32.2.11 skrll printf("%02x", hk->kv_mic[i]); 1359 1.32.2.2 skrll } 1360 1.32.2.11 skrll printf("\n"); 1361 1.32.2.11 skrll } 1362 1.32.2.11 skrll #endif 1363 1.32.2.11 skrll 1364 1.32.2.11 skrll /* 1365 1.32.2.11 skrll * Set a TKIP key into the hardware. This handles the 1366 1.32.2.11 skrll * potential distribution of key state to multiple key 1367 1.32.2.11 skrll * cache slots for TKIP. 1368 1.32.2.11 skrll */ 1369 1.32.2.11 skrll static int 1370 1.32.2.11 skrll ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1371 1.32.2.11 skrll HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1372 1.32.2.11 skrll { 1373 1.32.2.11 skrll #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1374 1.32.2.11 skrll static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1375 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 1376 1.32.2.11 skrll 1377 1.32.2.11 skrll KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1378 1.32.2.11 skrll ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1379 1.32.2.11 skrll KASSERT(sc->sc_splitmic, ("key cache !split")); 1380 1.32.2.11 skrll if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1381 1.32.2.2 skrll /* 1382 1.32.2.12 christos * TX key goes at first index, RX key at the rx index. 1383 1.32.2.11 skrll * The hal handles the MIC keys at index+64. 1384 1.32.2.2 skrll */ 1385 1.32.2.11 skrll memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1386 1.32.2.11 skrll KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1387 1.32.2.11 skrll if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1388 1.32.2.11 skrll return 0; 1389 1.32.2.11 skrll 1390 1.32.2.11 skrll memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1391 1.32.2.11 skrll KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1392 1.32.2.11 skrll /* XXX delete tx key on failure? */ 1393 1.32.2.11 skrll return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1394 1.32.2.11 skrll } else if (k->wk_flags & IEEE80211_KEY_XR) { 1395 1.32.2.11 skrll /* 1396 1.32.2.11 skrll * TX/RX key goes at first index. 1397 1.32.2.11 skrll * The hal handles the MIC keys are index+64. 1398 1.32.2.11 skrll */ 1399 1.32.2.11 skrll memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1400 1.32.2.11 skrll k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1401 1.32.2.11 skrll KEYPRINTF(sc, k->wk_keyix, hk, mac); 1402 1.32.2.11 skrll return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1403 1.32.2.2 skrll } 1404 1.32.2.11 skrll return 0; 1405 1.32.2.11 skrll #undef IEEE80211_KEY_XR 1406 1.32.2.2 skrll } 1407 1.32.2.2 skrll 1408 1.32.2.11 skrll /* 1409 1.32.2.11 skrll * Set a net80211 key into the hardware. This handles the 1410 1.32.2.11 skrll * potential distribution of key state to multiple key 1411 1.32.2.11 skrll * cache slots for TKIP with hardware MIC support. 1412 1.32.2.11 skrll */ 1413 1.32.2.2 skrll static int 1414 1.32.2.11 skrll ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1415 1.32.2.11 skrll const u_int8_t mac0[IEEE80211_ADDR_LEN], 1416 1.32.2.11 skrll struct ieee80211_node *bss) 1417 1.32.2.11 skrll { 1418 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 1419 1.32.2.11 skrll static const u_int8_t ciphermap[] = { 1420 1.32.2.11 skrll HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1421 1.32.2.11 skrll HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1422 1.32.2.11 skrll HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1423 1.32.2.11 skrll HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1424 1.32.2.11 skrll (u_int8_t) -1, /* 4 is not allocated */ 1425 1.32.2.11 skrll HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1426 1.32.2.11 skrll HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1427 1.32.2.11 skrll }; 1428 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 1429 1.32.2.11 skrll const struct ieee80211_cipher *cip = k->wk_cipher; 1430 1.32.2.11 skrll u_int8_t gmac[IEEE80211_ADDR_LEN]; 1431 1.32.2.11 skrll const u_int8_t *mac; 1432 1.32.2.11 skrll HAL_KEYVAL hk; 1433 1.32.2.2 skrll 1434 1.32.2.11 skrll memset(&hk, 0, sizeof(hk)); 1435 1.32.2.11 skrll /* 1436 1.32.2.11 skrll * Software crypto uses a "clear key" so non-crypto 1437 1.32.2.11 skrll * state kept in the key cache are maintained and 1438 1.32.2.11 skrll * so that rx frames have an entry to match. 1439 1.32.2.11 skrll */ 1440 1.32.2.11 skrll if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1441 1.32.2.11 skrll KASSERT(cip->ic_cipher < N(ciphermap), 1442 1.32.2.11 skrll ("invalid cipher type %u", cip->ic_cipher)); 1443 1.32.2.11 skrll hk.kv_type = ciphermap[cip->ic_cipher]; 1444 1.32.2.11 skrll hk.kv_len = k->wk_keylen; 1445 1.32.2.11 skrll memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1446 1.32.2.11 skrll } else 1447 1.32.2.11 skrll hk.kv_type = HAL_CIPHER_CLR; 1448 1.32.2.11 skrll 1449 1.32.2.11 skrll if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1450 1.32.2.2 skrll /* 1451 1.32.2.11 skrll * Group keys on hardware that supports multicast frame 1452 1.32.2.11 skrll * key search use a mac that is the sender's address with 1453 1.32.2.11 skrll * the high bit set instead of the app-specified address. 1454 1.32.2.2 skrll */ 1455 1.32.2.11 skrll IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1456 1.32.2.11 skrll gmac[0] |= 0x80; 1457 1.32.2.11 skrll mac = gmac; 1458 1.32.2.11 skrll } else 1459 1.32.2.11 skrll mac = mac0; 1460 1.32.2.11 skrll 1461 1.32.2.11 skrll if (hk.kv_type == HAL_CIPHER_TKIP && 1462 1.32.2.11 skrll (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1463 1.32.2.11 skrll sc->sc_splitmic) { 1464 1.32.2.11 skrll return ath_keyset_tkip(sc, k, &hk, mac); 1465 1.32.2.11 skrll } else { 1466 1.32.2.11 skrll KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1467 1.32.2.11 skrll return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1468 1.32.2.11 skrll } 1469 1.32.2.11 skrll #undef N 1470 1.32.2.11 skrll } 1471 1.32.2.11 skrll 1472 1.32.2.11 skrll /* 1473 1.32.2.11 skrll * Allocate tx/rx key slots for TKIP. We allocate two slots for 1474 1.32.2.11 skrll * each key, one for decrypt/encrypt and the other for the MIC. 1475 1.32.2.11 skrll */ 1476 1.32.2.11 skrll static u_int16_t 1477 1.32.2.12 christos key_alloc_2pair(struct ath_softc *sc, 1478 1.32.2.12 christos ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1479 1.32.2.11 skrll { 1480 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 1481 1.32.2.11 skrll u_int i, keyix; 1482 1.32.2.11 skrll 1483 1.32.2.11 skrll KASSERT(sc->sc_splitmic, ("key cache !split")); 1484 1.32.2.11 skrll /* XXX could optimize */ 1485 1.32.2.11 skrll for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1486 1.32.2.11 skrll u_int8_t b = sc->sc_keymap[i]; 1487 1.32.2.11 skrll if (b != 0xff) { 1488 1.32.2.11 skrll /* 1489 1.32.2.11 skrll * One or more slots in this byte are free. 1490 1.32.2.11 skrll */ 1491 1.32.2.11 skrll keyix = i*NBBY; 1492 1.32.2.11 skrll while (b & 1) { 1493 1.32.2.11 skrll again: 1494 1.32.2.11 skrll keyix++; 1495 1.32.2.11 skrll b >>= 1; 1496 1.32.2.11 skrll } 1497 1.32.2.11 skrll /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1498 1.32.2.11 skrll if (isset(sc->sc_keymap, keyix+32) || 1499 1.32.2.11 skrll isset(sc->sc_keymap, keyix+64) || 1500 1.32.2.11 skrll isset(sc->sc_keymap, keyix+32+64)) { 1501 1.32.2.11 skrll /* full pair unavailable */ 1502 1.32.2.11 skrll /* XXX statistic */ 1503 1.32.2.11 skrll if (keyix == (i+1)*NBBY) { 1504 1.32.2.11 skrll /* no slots were appropriate, advance */ 1505 1.32.2.11 skrll continue; 1506 1.32.2.11 skrll } 1507 1.32.2.11 skrll goto again; 1508 1.32.2.11 skrll } 1509 1.32.2.11 skrll setbit(sc->sc_keymap, keyix); 1510 1.32.2.11 skrll setbit(sc->sc_keymap, keyix+64); 1511 1.32.2.11 skrll setbit(sc->sc_keymap, keyix+32); 1512 1.32.2.11 skrll setbit(sc->sc_keymap, keyix+32+64); 1513 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1514 1.32.2.11 skrll "%s: key pair %u,%u %u,%u\n", 1515 1.32.2.11 skrll __func__, keyix, keyix+64, 1516 1.32.2.11 skrll keyix+32, keyix+32+64); 1517 1.32.2.12 christos *txkeyix = keyix; 1518 1.32.2.12 christos *rxkeyix = keyix+32; 1519 1.32.2.12 christos return 1; 1520 1.32.2.2 skrll } 1521 1.32.2.2 skrll } 1522 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1523 1.32.2.12 christos return 0; 1524 1.32.2.11 skrll #undef N 1525 1.32.2.11 skrll } 1526 1.32.2.11 skrll 1527 1.32.2.11 skrll /* 1528 1.32.2.11 skrll * Allocate a single key cache slot. 1529 1.32.2.11 skrll */ 1530 1.32.2.12 christos static int 1531 1.32.2.12 christos key_alloc_single(struct ath_softc *sc, 1532 1.32.2.12 christos ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1533 1.32.2.11 skrll { 1534 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 1535 1.32.2.11 skrll u_int i, keyix; 1536 1.32.2.11 skrll 1537 1.32.2.11 skrll /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1538 1.32.2.11 skrll for (i = 0; i < N(sc->sc_keymap); i++) { 1539 1.32.2.11 skrll u_int8_t b = sc->sc_keymap[i]; 1540 1.32.2.11 skrll if (b != 0xff) { 1541 1.32.2.11 skrll /* 1542 1.32.2.11 skrll * One or more slots are free. 1543 1.32.2.11 skrll */ 1544 1.32.2.11 skrll keyix = i*NBBY; 1545 1.32.2.11 skrll while (b & 1) 1546 1.32.2.11 skrll keyix++, b >>= 1; 1547 1.32.2.11 skrll setbit(sc->sc_keymap, keyix); 1548 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1549 1.32.2.11 skrll __func__, keyix); 1550 1.32.2.12 christos *txkeyix = *rxkeyix = keyix; 1551 1.32.2.12 christos return 1; 1552 1.32.2.2 skrll } 1553 1.32.2.2 skrll } 1554 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1555 1.32.2.12 christos return 0; 1556 1.32.2.11 skrll #undef N 1557 1.32.2.2 skrll } 1558 1.32.2.2 skrll 1559 1.32.2.2 skrll /* 1560 1.32.2.11 skrll * Allocate one or more key cache slots for a uniacst key. The 1561 1.32.2.11 skrll * key itself is needed only to identify the cipher. For hardware 1562 1.32.2.11 skrll * TKIP with split cipher+MIC keys we allocate two key cache slot 1563 1.32.2.11 skrll * pairs so that we can setup separate TX and RX MIC keys. Note 1564 1.32.2.11 skrll * that the MIC key for a TKIP key at slot i is assumed by the 1565 1.32.2.11 skrll * hardware to be at slot i+64. This limits TKIP keys to the first 1566 1.32.2.11 skrll * 64 entries. 1567 1.32.2.2 skrll */ 1568 1.32.2.11 skrll static int 1569 1.32.2.12 christos ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1570 1.32.2.12 christos ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1571 1.32.2.2 skrll { 1572 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 1573 1.32.2.11 skrll 1574 1.32.2.11 skrll /* 1575 1.32.2.11 skrll * Group key allocation must be handled specially for 1576 1.32.2.11 skrll * parts that do not support multicast key cache search 1577 1.32.2.11 skrll * functionality. For those parts the key id must match 1578 1.32.2.11 skrll * the h/w key index so lookups find the right key. On 1579 1.32.2.11 skrll * parts w/ the key search facility we install the sender's 1580 1.32.2.11 skrll * mac address (with the high bit set) and let the hardware 1581 1.32.2.11 skrll * find the key w/o using the key id. This is preferred as 1582 1.32.2.11 skrll * it permits us to support multiple users for adhoc and/or 1583 1.32.2.11 skrll * multi-station operation. 1584 1.32.2.11 skrll */ 1585 1.32.2.11 skrll if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1586 1.32.2.11 skrll if (!(&ic->ic_nw_keys[0] <= k && 1587 1.32.2.11 skrll k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1588 1.32.2.11 skrll /* should not happen */ 1589 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1590 1.32.2.11 skrll "%s: bogus group key\n", __func__); 1591 1.32.2.12 christos return 0; 1592 1.32.2.11 skrll } 1593 1.32.2.11 skrll /* 1594 1.32.2.11 skrll * XXX we pre-allocate the global keys so 1595 1.32.2.11 skrll * have no way to check if they've already been allocated. 1596 1.32.2.11 skrll */ 1597 1.32.2.12 christos *keyix = *rxkeyix = k - ic->ic_nw_keys; 1598 1.32.2.12 christos return 1; 1599 1.32.2.11 skrll } 1600 1.32.2.11 skrll 1601 1.32.2.11 skrll /* 1602 1.32.2.11 skrll * We allocate two pair for TKIP when using the h/w to do 1603 1.32.2.11 skrll * the MIC. For everything else, including software crypto, 1604 1.32.2.11 skrll * we allocate a single entry. Note that s/w crypto requires 1605 1.32.2.11 skrll * a pass-through slot on the 5211 and 5212. The 5210 does 1606 1.32.2.11 skrll * not support pass-through cache entries and we map all 1607 1.32.2.11 skrll * those requests to slot 0. 1608 1.32.2.11 skrll */ 1609 1.32.2.11 skrll if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1610 1.32.2.12 christos return key_alloc_single(sc, keyix, rxkeyix); 1611 1.32.2.11 skrll } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1612 1.32.2.11 skrll (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1613 1.32.2.12 christos return key_alloc_2pair(sc, keyix, rxkeyix); 1614 1.32.2.11 skrll } else { 1615 1.32.2.12 christos return key_alloc_single(sc, keyix, rxkeyix); 1616 1.32.2.11 skrll } 1617 1.32.2.11 skrll } 1618 1.32.2.11 skrll 1619 1.32.2.11 skrll /* 1620 1.32.2.11 skrll * Delete an entry in the key cache allocated by ath_key_alloc. 1621 1.32.2.11 skrll */ 1622 1.32.2.11 skrll static int 1623 1.32.2.11 skrll ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1624 1.32.2.11 skrll { 1625 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 1626 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1627 1.32.2.11 skrll const struct ieee80211_cipher *cip = k->wk_cipher; 1628 1.32.2.11 skrll u_int keyix = k->wk_keyix; 1629 1.32.2.2 skrll 1630 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1631 1.32.2.3 skrll 1632 1.32.2.11 skrll ath_hal_keyreset(ah, keyix); 1633 1.32.2.11 skrll /* 1634 1.32.2.11 skrll * Handle split tx/rx keying required for TKIP with h/w MIC. 1635 1.32.2.11 skrll */ 1636 1.32.2.11 skrll if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1637 1.32.2.12 christos (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1638 1.32.2.11 skrll ath_hal_keyreset(ah, keyix+32); /* RX key */ 1639 1.32.2.11 skrll if (keyix >= IEEE80211_WEP_NKID) { 1640 1.32.2.11 skrll /* 1641 1.32.2.11 skrll * Don't touch keymap entries for global keys so 1642 1.32.2.11 skrll * they are never considered for dynamic allocation. 1643 1.32.2.11 skrll */ 1644 1.32.2.11 skrll clrbit(sc->sc_keymap, keyix); 1645 1.32.2.11 skrll if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1646 1.32.2.11 skrll (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1647 1.32.2.11 skrll sc->sc_splitmic) { 1648 1.32.2.11 skrll clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1649 1.32.2.11 skrll clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1650 1.32.2.11 skrll clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1651 1.32.2.11 skrll } 1652 1.32.2.11 skrll } 1653 1.32.2.11 skrll return 1; 1654 1.32.2.2 skrll } 1655 1.32.2.2 skrll 1656 1.32.2.11 skrll /* 1657 1.32.2.11 skrll * Set the key cache contents for the specified key. Key cache 1658 1.32.2.11 skrll * slot(s) must already have been allocated by ath_key_alloc. 1659 1.32.2.11 skrll */ 1660 1.32.2.11 skrll static int 1661 1.32.2.11 skrll ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1662 1.32.2.11 skrll const u_int8_t mac[IEEE80211_ADDR_LEN]) 1663 1.32.2.2 skrll { 1664 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 1665 1.32.2.2 skrll 1666 1.32.2.11 skrll return ath_keyset(sc, k, mac, ic->ic_bss); 1667 1.32.2.2 skrll } 1668 1.32.2.2 skrll 1669 1.32.2.11 skrll /* 1670 1.32.2.11 skrll * Block/unblock tx+rx processing while a key change is done. 1671 1.32.2.11 skrll * We assume the caller serializes key management operations 1672 1.32.2.11 skrll * so we only need to worry about synchronization with other 1673 1.32.2.11 skrll * uses that originate in the driver. 1674 1.32.2.11 skrll */ 1675 1.32.2.2 skrll static void 1676 1.32.2.11 skrll ath_key_update_begin(struct ieee80211com *ic) 1677 1.32.2.2 skrll { 1678 1.32.2.11 skrll struct ifnet *ifp = ic->ic_ifp; 1679 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 1680 1.32.2.2 skrll 1681 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1682 1.32.2.11 skrll #if 0 1683 1.32.2.11 skrll tasklet_disable(&sc->sc_rxtq); 1684 1.32.2.11 skrll #endif 1685 1.32.2.11 skrll IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1686 1.32.2.2 skrll } 1687 1.32.2.11 skrll 1688 1.32.2.2 skrll static void 1689 1.32.2.11 skrll ath_key_update_end(struct ieee80211com *ic) 1690 1.32.2.2 skrll { 1691 1.32.2.11 skrll struct ifnet *ifp = ic->ic_ifp; 1692 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 1693 1.32.2.2 skrll 1694 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1695 1.32.2.11 skrll IF_UNLOCK(&ifp->if_snd); 1696 1.32.2.11 skrll #if 0 1697 1.32.2.11 skrll tasklet_enable(&sc->sc_rxtq); 1698 1.32.2.2 skrll #endif 1699 1.32.2.11 skrll } 1700 1.32.2.2 skrll 1701 1.32.2.2 skrll /* 1702 1.32.2.2 skrll * Calculate the receive filter according to the 1703 1.32.2.2 skrll * operating mode and state: 1704 1.32.2.2 skrll * 1705 1.32.2.2 skrll * o always accept unicast, broadcast, and multicast traffic 1706 1.32.2.11 skrll * o maintain current state of phy error reception (the hal 1707 1.32.2.11 skrll * may enable phy error frames for noise immunity work) 1708 1.32.2.2 skrll * o probe request frames are accepted only when operating in 1709 1.32.2.2 skrll * hostap, adhoc, or monitor modes 1710 1.32.2.2 skrll * o enable promiscuous mode according to the interface state 1711 1.32.2.2 skrll * o accept beacons: 1712 1.32.2.2 skrll * - when operating in adhoc mode so the 802.11 layer creates 1713 1.32.2.2 skrll * node table entries for peers, 1714 1.32.2.2 skrll * - when operating in station mode for collecting rssi data when 1715 1.32.2.2 skrll * the station is otherwise quiet, or 1716 1.32.2.2 skrll * - when scanning 1717 1.32.2.2 skrll */ 1718 1.32.2.2 skrll static u_int32_t 1719 1.32.2.11 skrll ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1720 1.32.2.2 skrll { 1721 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1722 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1723 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 1724 1.32.2.2 skrll u_int32_t rfilt; 1725 1.32.2.2 skrll 1726 1.32.2.2 skrll rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1727 1.32.2.2 skrll | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1728 1.32.2.2 skrll if (ic->ic_opmode != IEEE80211_M_STA) 1729 1.32.2.2 skrll rfilt |= HAL_RX_FILTER_PROBEREQ; 1730 1.32.2.11 skrll if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1731 1.32.2.11 skrll (ifp->if_flags & IFF_PROMISC)) 1732 1.32.2.2 skrll rfilt |= HAL_RX_FILTER_PROM; 1733 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_STA || 1734 1.32.2.11 skrll ic->ic_opmode == IEEE80211_M_IBSS || 1735 1.32.2.11 skrll state == IEEE80211_S_SCAN) 1736 1.32.2.11 skrll rfilt |= HAL_RX_FILTER_BEACON; 1737 1.32.2.2 skrll return rfilt; 1738 1.32.2.2 skrll } 1739 1.32.2.2 skrll 1740 1.32.2.2 skrll static void 1741 1.32.2.11 skrll ath_mcastfilter_accum(caddr_t dl, u_int32_t *mfilt) 1742 1.32.2.2 skrll { 1743 1.32.2.11 skrll u_int32_t val; 1744 1.32.2.11 skrll u_int8_t pos; 1745 1.32.2.2 skrll 1746 1.32.2.11 skrll /* calculate XOR of eight 6bit values */ 1747 1.32.2.11 skrll val = LE_READ_4(dl + 0); 1748 1.32.2.11 skrll pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1749 1.32.2.11 skrll val = LE_READ_4(dl + 3); 1750 1.32.2.11 skrll pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1751 1.32.2.11 skrll pos &= 0x3f; 1752 1.32.2.11 skrll mfilt[pos / 32] |= (1 << (pos % 32)); 1753 1.32.2.11 skrll } 1754 1.32.2.2 skrll 1755 1.32.2.11 skrll static void 1756 1.32.2.11 skrll ath_mcastfilter_compute(struct ath_softc *sc, u_int32_t *mfilt) 1757 1.32.2.11 skrll { 1758 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 1759 1.32.2.11 skrll struct ether_multi *enm; 1760 1.32.2.11 skrll struct ether_multistep estep; 1761 1.32.2.11 skrll 1762 1.32.2.11 skrll mfilt[0] = mfilt[1] = 0; 1763 1.32.2.11 skrll ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1764 1.32.2.11 skrll while (enm != NULL) { 1765 1.32.2.11 skrll /* XXX Punt on ranges. */ 1766 1.32.2.11 skrll if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1767 1.32.2.11 skrll mfilt[0] = mfilt[1] = ~((u_int32_t)0); 1768 1.32.2.11 skrll ifp->if_flags |= IFF_ALLMULTI; 1769 1.32.2.11 skrll return; 1770 1.32.2.11 skrll } 1771 1.32.2.11 skrll ath_mcastfilter_accum(enm->enm_addrlo, mfilt); 1772 1.32.2.11 skrll ETHER_NEXT_MULTI(estep, enm); 1773 1.32.2.11 skrll } 1774 1.32.2.11 skrll ifp->if_flags &= ~IFF_ALLMULTI; 1775 1.32.2.11 skrll } 1776 1.32.2.11 skrll 1777 1.32.2.11 skrll static void 1778 1.32.2.11 skrll ath_mode_init(struct ath_softc *sc) 1779 1.32.2.11 skrll { 1780 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 1781 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 1782 1.32.2.11 skrll u_int32_t rfilt, mfilt[2]; 1783 1.32.2.11 skrll int i; 1784 1.32.2.11 skrll 1785 1.32.2.11 skrll /* configure rx filter */ 1786 1.32.2.11 skrll rfilt = ath_calcrxfilter(sc, ic->ic_state); 1787 1.32.2.11 skrll ath_hal_setrxfilter(ah, rfilt); 1788 1.32.2.11 skrll 1789 1.32.2.11 skrll /* configure operational mode */ 1790 1.32.2.11 skrll ath_hal_setopmode(ah); 1791 1.32.2.11 skrll 1792 1.32.2.11 skrll /* Write keys to hardware; it may have been powered down. */ 1793 1.32.2.11 skrll ath_key_update_begin(ic); 1794 1.32.2.11 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1795 1.32.2.11 skrll ath_key_set(ic, 1796 1.32.2.11 skrll &ic->ic_crypto.cs_nw_keys[i], 1797 1.32.2.11 skrll ic->ic_myaddr); 1798 1.32.2.11 skrll } 1799 1.32.2.11 skrll ath_key_update_end(ic); 1800 1.32.2.11 skrll 1801 1.32.2.11 skrll /* 1802 1.32.2.11 skrll * Handle any link-level address change. Note that we only 1803 1.32.2.11 skrll * need to force ic_myaddr; any other addresses are handled 1804 1.32.2.11 skrll * as a byproduct of the ifnet code marking the interface 1805 1.32.2.11 skrll * down then up. 1806 1.32.2.11 skrll * 1807 1.32.2.11 skrll * XXX should get from lladdr instead of arpcom but that's more work 1808 1.32.2.11 skrll */ 1809 1.32.2.11 skrll IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sc->sc_if.if_sadl)); 1810 1.32.2.11 skrll ath_hal_setmac(ah, ic->ic_myaddr); 1811 1.32.2.2 skrll 1812 1.32.2.2 skrll /* calculate and install multicast filter */ 1813 1.32.2.2 skrll #ifdef __FreeBSD__ 1814 1.32.2.12 christos if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1815 1.32.2.12 christos mfilt[0] = mfilt[1] = 0; 1816 1.32.2.12 christos IF_ADDR_LOCK(ifp); 1817 1.32.2.12 christos TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1818 1.32.2.12 christos caddr_t dl; 1819 1.32.2.12 christos 1820 1.32.2.12 christos /* calculate XOR of eight 6bit values */ 1821 1.32.2.12 christos dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1822 1.32.2.12 christos val = LE_READ_4(dl + 0); 1823 1.32.2.12 christos pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1824 1.32.2.12 christos val = LE_READ_4(dl + 3); 1825 1.32.2.12 christos pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1826 1.32.2.12 christos pos &= 0x3f; 1827 1.32.2.12 christos mfilt[pos / 32] |= (1 << (pos % 32)); 1828 1.32.2.12 christos } 1829 1.32.2.12 christos IF_ADDR_UNLOCK(ifp); 1830 1.32.2.12 christos } else { 1831 1.32.2.2 skrll mfilt[0] = mfilt[1] = ~0; 1832 1.32.2.12 christos } 1833 1.32.2.2 skrll #endif 1834 1.32.2.2 skrll #ifdef __NetBSD__ 1835 1.32.2.11 skrll ath_mcastfilter_compute(sc, mfilt); 1836 1.32.2.2 skrll #endif 1837 1.32.2.2 skrll ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1838 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1839 1.32.2.11 skrll __func__, rfilt, mfilt[0], mfilt[1]); 1840 1.32.2.2 skrll } 1841 1.32.2.2 skrll 1842 1.32.2.11 skrll /* 1843 1.32.2.11 skrll * Set the slot time based on the current setting. 1844 1.32.2.11 skrll */ 1845 1.32.2.2 skrll static void 1846 1.32.2.11 skrll ath_setslottime(struct ath_softc *sc) 1847 1.32.2.2 skrll { 1848 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 1849 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 1850 1.32.2.2 skrll 1851 1.32.2.11 skrll if (ic->ic_flags & IEEE80211_F_SHSLOT) 1852 1.32.2.11 skrll ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1853 1.32.2.11 skrll else 1854 1.32.2.11 skrll ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1855 1.32.2.11 skrll sc->sc_updateslot = OK; 1856 1.32.2.2 skrll } 1857 1.32.2.2 skrll 1858 1.32.2.11 skrll /* 1859 1.32.2.11 skrll * Callback from the 802.11 layer to update the 1860 1.32.2.11 skrll * slot time based on the current setting. 1861 1.32.2.11 skrll */ 1862 1.32.2.11 skrll static void 1863 1.32.2.11 skrll ath_updateslot(struct ifnet *ifp) 1864 1.32.2.2 skrll { 1865 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 1866 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 1867 1.32.2.2 skrll 1868 1.32.2.11 skrll /* 1869 1.32.2.11 skrll * When not coordinating the BSS, change the hardware 1870 1.32.2.11 skrll * immediately. For other operation we defer the change 1871 1.32.2.11 skrll * until beacon updates have propagated to the stations. 1872 1.32.2.11 skrll */ 1873 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1874 1.32.2.11 skrll sc->sc_updateslot = UPDATE; 1875 1.32.2.2 skrll else 1876 1.32.2.11 skrll ath_setslottime(sc); 1877 1.32.2.11 skrll } 1878 1.32.2.11 skrll 1879 1.32.2.11 skrll /* 1880 1.32.2.11 skrll * Setup a h/w transmit queue for beacons. 1881 1.32.2.11 skrll */ 1882 1.32.2.11 skrll static int 1883 1.32.2.11 skrll ath_beaconq_setup(struct ath_hal *ah) 1884 1.32.2.11 skrll { 1885 1.32.2.11 skrll HAL_TXQ_INFO qi; 1886 1.32.2.11 skrll 1887 1.32.2.11 skrll memset(&qi, 0, sizeof(qi)); 1888 1.32.2.11 skrll qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1889 1.32.2.11 skrll qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1890 1.32.2.11 skrll qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1891 1.32.2.11 skrll /* NB: for dynamic turbo, don't enable any other interrupts */ 1892 1.32.2.11 skrll qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1893 1.32.2.11 skrll return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1894 1.32.2.2 skrll } 1895 1.32.2.2 skrll 1896 1.32.2.11 skrll /* 1897 1.32.2.11 skrll * Setup the transmit queue parameters for the beacon queue. 1898 1.32.2.11 skrll */ 1899 1.32.2.2 skrll static int 1900 1.32.2.11 skrll ath_beaconq_config(struct ath_softc *sc) 1901 1.32.2.2 skrll { 1902 1.32.2.11 skrll #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1903 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1904 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 1905 1.32.2.11 skrll HAL_TXQ_INFO qi; 1906 1.32.2.11 skrll 1907 1.32.2.11 skrll ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1908 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1909 1.32.2.11 skrll /* 1910 1.32.2.11 skrll * Always burst out beacon and CAB traffic. 1911 1.32.2.11 skrll */ 1912 1.32.2.11 skrll qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1913 1.32.2.11 skrll qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1914 1.32.2.11 skrll qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1915 1.32.2.11 skrll } else { 1916 1.32.2.11 skrll struct wmeParams *wmep = 1917 1.32.2.11 skrll &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1918 1.32.2.11 skrll /* 1919 1.32.2.11 skrll * Adhoc mode; important thing is to use 2x cwmin. 1920 1.32.2.11 skrll */ 1921 1.32.2.11 skrll qi.tqi_aifs = wmep->wmep_aifsn; 1922 1.32.2.11 skrll qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1923 1.32.2.11 skrll qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1924 1.32.2.11 skrll } 1925 1.32.2.11 skrll 1926 1.32.2.11 skrll if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1927 1.32.2.11 skrll device_printf(sc->sc_dev, "unable to update parameters for " 1928 1.32.2.11 skrll "beacon hardware queue!\n"); 1929 1.32.2.11 skrll return 0; 1930 1.32.2.11 skrll } else { 1931 1.32.2.11 skrll ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1932 1.32.2.11 skrll return 1; 1933 1.32.2.11 skrll } 1934 1.32.2.11 skrll #undef ATH_EXPONENT_TO_VALUE 1935 1.32.2.11 skrll } 1936 1.32.2.11 skrll 1937 1.32.2.11 skrll /* 1938 1.32.2.11 skrll * Allocate and setup an initial beacon frame. 1939 1.32.2.11 skrll */ 1940 1.32.2.11 skrll static int 1941 1.32.2.11 skrll ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1942 1.32.2.11 skrll { 1943 1.32.2.11 skrll struct ieee80211com *ic = ni->ni_ic; 1944 1.32.2.2 skrll struct ath_buf *bf; 1945 1.32.2.2 skrll struct mbuf *m; 1946 1.32.2.11 skrll int error; 1947 1.32.2.2 skrll 1948 1.32.2.11 skrll bf = STAILQ_FIRST(&sc->sc_bbuf); 1949 1.32.2.11 skrll if (bf == NULL) { 1950 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1951 1.32.2.11 skrll sc->sc_stats.ast_be_nombuf++; /* XXX */ 1952 1.32.2.11 skrll return ENOMEM; /* XXX */ 1953 1.32.2.2 skrll } 1954 1.32.2.2 skrll /* 1955 1.32.2.2 skrll * NB: the beacon data buffer must be 32-bit aligned; 1956 1.32.2.2 skrll * we assume the mbuf routines will return us something 1957 1.32.2.2 skrll * with this alignment (perhaps should assert). 1958 1.32.2.2 skrll */ 1959 1.32.2.11 skrll m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1960 1.32.2.2 skrll if (m == NULL) { 1961 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1962 1.32.2.11 skrll __func__); 1963 1.32.2.2 skrll sc->sc_stats.ast_be_nombuf++; 1964 1.32.2.2 skrll return ENOMEM; 1965 1.32.2.2 skrll } 1966 1.32.2.11 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1967 1.32.2.11 skrll BUS_DMA_NOWAIT); 1968 1.32.2.11 skrll if (error == 0) { 1969 1.32.2.11 skrll bf->bf_m = m; 1970 1.32.2.11 skrll bf->bf_node = ieee80211_ref_node(ni); 1971 1.32.2.2 skrll } else { 1972 1.32.2.2 skrll m_freem(m); 1973 1.32.2.2 skrll } 1974 1.32.2.11 skrll return error; 1975 1.32.2.11 skrll } 1976 1.32.2.11 skrll 1977 1.32.2.11 skrll /* 1978 1.32.2.11 skrll * Setup the beacon frame for transmit. 1979 1.32.2.11 skrll */ 1980 1.32.2.11 skrll static void 1981 1.32.2.11 skrll ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1982 1.32.2.11 skrll { 1983 1.32.2.11 skrll #define USE_SHPREAMBLE(_ic) \ 1984 1.32.2.11 skrll (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1985 1.32.2.11 skrll == IEEE80211_F_SHPREAMBLE) 1986 1.32.2.11 skrll struct ieee80211_node *ni = bf->bf_node; 1987 1.32.2.11 skrll struct ieee80211com *ic = ni->ni_ic; 1988 1.32.2.11 skrll struct mbuf *m = bf->bf_m; 1989 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 1990 1.32.2.11 skrll struct ath_node *an = ATH_NODE(ni); 1991 1.32.2.11 skrll struct ath_desc *ds; 1992 1.32.2.11 skrll int flags, antenna; 1993 1.32.2.11 skrll u_int8_t rate; 1994 1.32.2.11 skrll 1995 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1996 1.32.2.11 skrll __func__, m, m->m_len); 1997 1.32.2.2 skrll 1998 1.32.2.2 skrll /* setup descriptors */ 1999 1.32.2.2 skrll ds = bf->bf_desc; 2000 1.32.2.2 skrll 2001 1.32.2.11 skrll flags = HAL_TXDESC_NOACK; 2002 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2003 1.32.2.11 skrll ds->ds_link = bf->bf_daddr; /* self-linked */ 2004 1.32.2.11 skrll flags |= HAL_TXDESC_VEOL; 2005 1.32.2.11 skrll /* 2006 1.32.2.11 skrll * Let hardware handle antenna switching unless 2007 1.32.2.11 skrll * the user has selected a transmit antenna 2008 1.32.2.11 skrll * (sc_txantenna is not 0). 2009 1.32.2.11 skrll */ 2010 1.32.2.11 skrll antenna = sc->sc_txantenna; 2011 1.32.2.11 skrll } else { 2012 1.32.2.3 skrll ds->ds_link = 0; 2013 1.32.2.11 skrll /* 2014 1.32.2.11 skrll * Switch antenna every 4 beacons, unless the user 2015 1.32.2.11 skrll * has selected a transmit antenna (sc_txantenna 2016 1.32.2.11 skrll * is not 0). 2017 1.32.2.11 skrll * 2018 1.32.2.11 skrll * XXX assumes two antenna 2019 1.32.2.11 skrll */ 2020 1.32.2.11 skrll if (sc->sc_txantenna == 0) 2021 1.32.2.11 skrll antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2022 1.32.2.11 skrll else 2023 1.32.2.11 skrll antenna = sc->sc_txantenna; 2024 1.32.2.11 skrll } 2025 1.32.2.2 skrll 2026 1.32.2.11 skrll KASSERT(bf->bf_nseg == 1, 2027 1.32.2.11 skrll ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2028 1.32.2.11 skrll ds->ds_data = bf->bf_segs[0].ds_addr; 2029 1.32.2.2 skrll /* 2030 1.32.2.2 skrll * Calculate rate code. 2031 1.32.2.2 skrll * XXX everything at min xmit rate 2032 1.32.2.2 skrll */ 2033 1.32.2.11 skrll if (USE_SHPREAMBLE(ic)) 2034 1.32.2.11 skrll rate = an->an_tx_mgtratesp; 2035 1.32.2.2 skrll else 2036 1.32.2.11 skrll rate = an->an_tx_mgtrate; 2037 1.32.2.11 skrll ath_hal_setuptxdesc(ah, ds 2038 1.32.2.11 skrll , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2039 1.32.2.11 skrll , sizeof(struct ieee80211_frame)/* header length */ 2040 1.32.2.2 skrll , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2041 1.32.2.11 skrll , ni->ni_txpower /* txpower XXX */ 2042 1.32.2.2 skrll , rate, 1 /* series 0 rate/tries */ 2043 1.32.2.2 skrll , HAL_TXKEYIX_INVALID /* no encryption */ 2044 1.32.2.11 skrll , antenna /* antenna mode */ 2045 1.32.2.11 skrll , flags /* no ack, veol for beacons */ 2046 1.32.2.2 skrll , 0 /* rts/cts rate */ 2047 1.32.2.2 skrll , 0 /* rts/cts duration */ 2048 1.32.2.11 skrll ); 2049 1.32.2.2 skrll /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2050 1.32.2.11 skrll ath_hal_filltxdesc(ah, ds 2051 1.32.2.11 skrll , roundup(m->m_len, 4) /* buffer length */ 2052 1.32.2.11 skrll , AH_TRUE /* first segment */ 2053 1.32.2.11 skrll , AH_TRUE /* last segment */ 2054 1.32.2.11 skrll , ds /* first descriptor */ 2055 1.32.2.11 skrll ); 2056 1.32.2.11 skrll #undef USE_SHPREAMBLE 2057 1.32.2.2 skrll } 2058 1.32.2.2 skrll 2059 1.32.2.11 skrll /* 2060 1.32.2.11 skrll * Transmit a beacon frame at SWBA. Dynamic updates to the 2061 1.32.2.11 skrll * frame contents are done as needed and the slot time is 2062 1.32.2.11 skrll * also adjusted based on current state. 2063 1.32.2.11 skrll */ 2064 1.32.2.2 skrll static void 2065 1.32.2.11 skrll ath_beacon_proc(void *arg, int pending) 2066 1.32.2.2 skrll { 2067 1.32.2.11 skrll struct ath_softc *sc = arg; 2068 1.32.2.11 skrll struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2069 1.32.2.11 skrll struct ieee80211_node *ni = bf->bf_node; 2070 1.32.2.11 skrll struct ieee80211com *ic = ni->ni_ic; 2071 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2072 1.32.2.11 skrll struct mbuf *m; 2073 1.32.2.11 skrll int ncabq, error, otherant; 2074 1.32.2.11 skrll 2075 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2076 1.32.2.11 skrll __func__, pending); 2077 1.32.2.2 skrll 2078 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA || 2079 1.32.2.11 skrll ic->ic_opmode == IEEE80211_M_MONITOR || 2080 1.32.2.2 skrll bf == NULL || bf->bf_m == NULL) { 2081 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2082 1.32.2.11 skrll __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2083 1.32.2.11 skrll return; 2084 1.32.2.11 skrll } 2085 1.32.2.11 skrll /* 2086 1.32.2.11 skrll * Check if the previous beacon has gone out. If 2087 1.32.2.11 skrll * not don't don't try to post another, skip this 2088 1.32.2.11 skrll * period and wait for the next. Missed beacons 2089 1.32.2.11 skrll * indicate a problem and should not occur. If we 2090 1.32.2.11 skrll * miss too many consecutive beacons reset the device. 2091 1.32.2.11 skrll */ 2092 1.32.2.11 skrll if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2093 1.32.2.11 skrll sc->sc_bmisscount++; 2094 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2095 1.32.2.11 skrll "%s: missed %u consecutive beacons\n", 2096 1.32.2.11 skrll __func__, sc->sc_bmisscount); 2097 1.32.2.11 skrll if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2098 1.32.2.11 skrll TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2099 1.32.2.2 skrll return; 2100 1.32.2.2 skrll } 2101 1.32.2.11 skrll if (sc->sc_bmisscount != 0) { 2102 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, 2103 1.32.2.11 skrll "%s: resume beacon xmit after %u misses\n", 2104 1.32.2.11 skrll __func__, sc->sc_bmisscount); 2105 1.32.2.11 skrll sc->sc_bmisscount = 0; 2106 1.32.2.11 skrll } 2107 1.32.2.11 skrll 2108 1.32.2.11 skrll /* 2109 1.32.2.11 skrll * Update dynamic beacon contents. If this returns 2110 1.32.2.11 skrll * non-zero then we need to remap the memory because 2111 1.32.2.11 skrll * the beacon frame changed size (probably because 2112 1.32.2.11 skrll * of the TIM bitmap). 2113 1.32.2.11 skrll */ 2114 1.32.2.11 skrll m = bf->bf_m; 2115 1.32.2.11 skrll ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2116 1.32.2.11 skrll if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2117 1.32.2.11 skrll /* XXX too conservative? */ 2118 1.32.2.11 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2119 1.32.2.11 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2120 1.32.2.11 skrll BUS_DMA_NOWAIT); 2121 1.32.2.11 skrll if (error != 0) { 2122 1.32.2.11 skrll if_printf(&sc->sc_if, 2123 1.32.2.11 skrll "%s: bus_dmamap_load_mbuf failed, error %u\n", 2124 1.32.2.11 skrll __func__, error); 2125 1.32.2.11 skrll return; 2126 1.32.2.11 skrll } 2127 1.32.2.11 skrll } 2128 1.32.2.11 skrll 2129 1.32.2.11 skrll /* 2130 1.32.2.11 skrll * Handle slot time change when a non-ERP station joins/leaves 2131 1.32.2.11 skrll * an 11g network. The 802.11 layer notifies us via callback, 2132 1.32.2.11 skrll * we mark updateslot, then wait one beacon before effecting 2133 1.32.2.11 skrll * the change. This gives associated stations at least one 2134 1.32.2.11 skrll * beacon interval to note the state change. 2135 1.32.2.11 skrll */ 2136 1.32.2.11 skrll /* XXX locking */ 2137 1.32.2.11 skrll if (sc->sc_updateslot == UPDATE) 2138 1.32.2.11 skrll sc->sc_updateslot = COMMIT; /* commit next beacon */ 2139 1.32.2.11 skrll else if (sc->sc_updateslot == COMMIT) 2140 1.32.2.11 skrll ath_setslottime(sc); /* commit change to h/w */ 2141 1.32.2.11 skrll 2142 1.32.2.11 skrll /* 2143 1.32.2.11 skrll * Check recent per-antenna transmit statistics and flip 2144 1.32.2.11 skrll * the default antenna if noticeably more frames went out 2145 1.32.2.11 skrll * on the non-default antenna. 2146 1.32.2.11 skrll * XXX assumes 2 anntenae 2147 1.32.2.11 skrll */ 2148 1.32.2.11 skrll otherant = sc->sc_defant & 1 ? 2 : 1; 2149 1.32.2.11 skrll if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2150 1.32.2.11 skrll ath_setdefantenna(sc, otherant); 2151 1.32.2.11 skrll sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2152 1.32.2.11 skrll 2153 1.32.2.11 skrll /* 2154 1.32.2.11 skrll * Construct tx descriptor. 2155 1.32.2.11 skrll */ 2156 1.32.2.11 skrll ath_beacon_setup(sc, bf); 2157 1.32.2.11 skrll 2158 1.32.2.11 skrll /* 2159 1.32.2.11 skrll * Stop any current dma and put the new frame on the queue. 2160 1.32.2.11 skrll * This should never fail since we check above that no frames 2161 1.32.2.11 skrll * are still pending on the queue. 2162 1.32.2.11 skrll */ 2163 1.32.2.2 skrll if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2164 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 2165 1.32.2.11 skrll "%s: beacon queue %u did not stop?\n", 2166 1.32.2.11 skrll __func__, sc->sc_bhalq); 2167 1.32.2.2 skrll } 2168 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2169 1.32.2.11 skrll bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2170 1.32.2.2 skrll 2171 1.32.2.11 skrll /* 2172 1.32.2.11 skrll * Enable the CAB queue before the beacon queue to 2173 1.32.2.11 skrll * insure cab frames are triggered by this beacon. 2174 1.32.2.11 skrll */ 2175 1.32.2.11 skrll if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2176 1.32.2.11 skrll ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2177 1.32.2.2 skrll ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2178 1.32.2.2 skrll ath_hal_txstart(ah, sc->sc_bhalq); 2179 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2180 1.32.2.11 skrll "%s: TXDP[%u] = %p (%p)\n", __func__, 2181 1.32.2.11 skrll sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2182 1.32.2.11 skrll 2183 1.32.2.11 skrll sc->sc_stats.ast_be_xmit++; 2184 1.32.2.11 skrll } 2185 1.32.2.11 skrll 2186 1.32.2.11 skrll /* 2187 1.32.2.11 skrll * Reset the hardware after detecting beacons have stopped. 2188 1.32.2.11 skrll */ 2189 1.32.2.11 skrll static void 2190 1.32.2.11 skrll ath_bstuck_proc(void *arg, int pending) 2191 1.32.2.11 skrll { 2192 1.32.2.11 skrll struct ath_softc *sc = arg; 2193 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 2194 1.32.2.11 skrll 2195 1.32.2.11 skrll if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2196 1.32.2.11 skrll sc->sc_bmisscount); 2197 1.32.2.11 skrll ath_reset(ifp); 2198 1.32.2.2 skrll } 2199 1.32.2.2 skrll 2200 1.32.2.11 skrll /* 2201 1.32.2.11 skrll * Reclaim beacon resources. 2202 1.32.2.11 skrll */ 2203 1.32.2.2 skrll static void 2204 1.32.2.2 skrll ath_beacon_free(struct ath_softc *sc) 2205 1.32.2.2 skrll { 2206 1.32.2.11 skrll struct ath_buf *bf; 2207 1.32.2.2 skrll 2208 1.32.2.11 skrll STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2209 1.32.2.11 skrll if (bf->bf_m != NULL) { 2210 1.32.2.11 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2211 1.32.2.11 skrll m_freem(bf->bf_m); 2212 1.32.2.11 skrll bf->bf_m = NULL; 2213 1.32.2.11 skrll } 2214 1.32.2.11 skrll if (bf->bf_node != NULL) { 2215 1.32.2.11 skrll ieee80211_free_node(bf->bf_node); 2216 1.32.2.11 skrll bf->bf_node = NULL; 2217 1.32.2.11 skrll } 2218 1.32.2.2 skrll } 2219 1.32.2.2 skrll } 2220 1.32.2.2 skrll 2221 1.32.2.2 skrll /* 2222 1.32.2.2 skrll * Configure the beacon and sleep timers. 2223 1.32.2.2 skrll * 2224 1.32.2.2 skrll * When operating as an AP this resets the TSF and sets 2225 1.32.2.2 skrll * up the hardware to notify us when we need to issue beacons. 2226 1.32.2.2 skrll * 2227 1.32.2.2 skrll * When operating in station mode this sets up the beacon 2228 1.32.2.2 skrll * timers according to the timestamp of the last received 2229 1.32.2.2 skrll * beacon and the current TSF, configures PCF and DTIM 2230 1.32.2.2 skrll * handling, programs the sleep registers so the hardware 2231 1.32.2.2 skrll * will wakeup in time to receive beacons, and configures 2232 1.32.2.2 skrll * the beacon miss handling so we'll receive a BMISS 2233 1.32.2.2 skrll * interrupt when we stop seeing beacons from the AP 2234 1.32.2.2 skrll * we've associated with. 2235 1.32.2.2 skrll */ 2236 1.32.2.2 skrll static void 2237 1.32.2.2 skrll ath_beacon_config(struct ath_softc *sc) 2238 1.32.2.2 skrll { 2239 1.32.2.11 skrll #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) 2240 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2241 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2242 1.32.2.2 skrll struct ieee80211_node *ni = ic->ic_bss; 2243 1.32.2.2 skrll u_int32_t nexttbtt, intval; 2244 1.32.2.2 skrll 2245 1.32.2.11 skrll /* extract tstamp from last beacon and convert to TU */ 2246 1.32.2.11 skrll nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2247 1.32.2.11 skrll LE_READ_4(ni->ni_tstamp.data)); 2248 1.32.2.11 skrll /* NB: the beacon interval is kept internally in TU's */ 2249 1.32.2.2 skrll intval = ni->ni_intval & HAL_BEACON_PERIOD; 2250 1.32.2.11 skrll if (nexttbtt == 0) /* e.g. for ap mode */ 2251 1.32.2.11 skrll nexttbtt = intval; 2252 1.32.2.11 skrll else if (intval) /* NB: can be 0 for monitor mode */ 2253 1.32.2.11 skrll nexttbtt = roundup(nexttbtt, intval); 2254 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2255 1.32.2.11 skrll __func__, nexttbtt, intval, ni->ni_intval); 2256 1.32.2.2 skrll if (ic->ic_opmode == IEEE80211_M_STA) { 2257 1.32.2.2 skrll HAL_BEACON_STATE bs; 2258 1.32.2.11 skrll u_int64_t tsf; 2259 1.32.2.11 skrll u_int32_t tsftu; 2260 1.32.2.11 skrll int dtimperiod, dtimcount; 2261 1.32.2.11 skrll int cfpperiod, cfpcount; 2262 1.32.2.2 skrll 2263 1.32.2.2 skrll /* 2264 1.32.2.11 skrll * Setup dtim and cfp parameters according to 2265 1.32.2.11 skrll * last beacon we received (which may be none). 2266 1.32.2.11 skrll */ 2267 1.32.2.11 skrll dtimperiod = ni->ni_dtim_period; 2268 1.32.2.11 skrll if (dtimperiod <= 0) /* NB: 0 if not known */ 2269 1.32.2.11 skrll dtimperiod = 1; 2270 1.32.2.11 skrll dtimcount = ni->ni_dtim_count; 2271 1.32.2.11 skrll if (dtimcount >= dtimperiod) /* NB: sanity check */ 2272 1.32.2.11 skrll dtimcount = 0; /* XXX? */ 2273 1.32.2.11 skrll cfpperiod = 1; /* NB: no PCF support yet */ 2274 1.32.2.11 skrll cfpcount = 0; 2275 1.32.2.11 skrll #define FUDGE 2 2276 1.32.2.11 skrll /* 2277 1.32.2.11 skrll * Pull nexttbtt forward to reflect the current 2278 1.32.2.11 skrll * TSF and calculate dtim+cfp state for the result. 2279 1.32.2.2 skrll */ 2280 1.32.2.11 skrll tsf = ath_hal_gettsf64(ah); 2281 1.32.2.11 skrll tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE; 2282 1.32.2.11 skrll do { 2283 1.32.2.11 skrll nexttbtt += intval; 2284 1.32.2.11 skrll if (--dtimcount < 0) { 2285 1.32.2.11 skrll dtimcount = dtimperiod - 1; 2286 1.32.2.11 skrll if (--cfpcount < 0) 2287 1.32.2.11 skrll cfpcount = cfpperiod - 1; 2288 1.32.2.11 skrll } 2289 1.32.2.11 skrll } while (nexttbtt < tsftu); 2290 1.32.2.11 skrll #undef FUDGE 2291 1.32.2.11 skrll memset(&bs, 0, sizeof(bs)); 2292 1.32.2.11 skrll bs.bs_intval = intval; 2293 1.32.2.2 skrll bs.bs_nexttbtt = nexttbtt; 2294 1.32.2.11 skrll bs.bs_dtimperiod = dtimperiod*intval; 2295 1.32.2.11 skrll bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2296 1.32.2.11 skrll bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2297 1.32.2.11 skrll bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2298 1.32.2.11 skrll bs.bs_cfpmaxduration = 0; 2299 1.32.2.11 skrll #if 0 2300 1.32.2.11 skrll /* 2301 1.32.2.11 skrll * The 802.11 layer records the offset to the DTIM 2302 1.32.2.11 skrll * bitmap while receiving beacons; use it here to 2303 1.32.2.11 skrll * enable h/w detection of our AID being marked in 2304 1.32.2.11 skrll * the bitmap vector (to indicate frames for us are 2305 1.32.2.11 skrll * pending at the AP). 2306 1.32.2.11 skrll * XXX do DTIM handling in s/w to WAR old h/w bugs 2307 1.32.2.11 skrll * XXX enable based on h/w rev for newer chips 2308 1.32.2.11 skrll */ 2309 1.32.2.11 skrll bs.bs_timoffset = ni->ni_timoff; 2310 1.32.2.11 skrll #endif 2311 1.32.2.2 skrll /* 2312 1.32.2.2 skrll * Calculate the number of consecutive beacons to miss 2313 1.32.2.2 skrll * before taking a BMISS interrupt. The configuration 2314 1.32.2.2 skrll * is specified in ms, so we need to convert that to 2315 1.32.2.2 skrll * TU's and then calculate based on the beacon interval. 2316 1.32.2.2 skrll * Note that we clamp the result to at most 10 beacons. 2317 1.32.2.2 skrll */ 2318 1.32.2.11 skrll bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2319 1.32.2.2 skrll if (bs.bs_bmissthreshold > 10) 2320 1.32.2.2 skrll bs.bs_bmissthreshold = 10; 2321 1.32.2.2 skrll else if (bs.bs_bmissthreshold <= 0) 2322 1.32.2.2 skrll bs.bs_bmissthreshold = 1; 2323 1.32.2.2 skrll 2324 1.32.2.2 skrll /* 2325 1.32.2.2 skrll * Calculate sleep duration. The configuration is 2326 1.32.2.2 skrll * given in ms. We insure a multiple of the beacon 2327 1.32.2.2 skrll * period is used. Also, if the sleep duration is 2328 1.32.2.2 skrll * greater than the DTIM period then it makes senses 2329 1.32.2.2 skrll * to make it a multiple of that. 2330 1.32.2.2 skrll * 2331 1.32.2.2 skrll * XXX fixed at 100ms 2332 1.32.2.2 skrll */ 2333 1.32.2.2 skrll bs.bs_sleepduration = 2334 1.32.2.11 skrll roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2335 1.32.2.2 skrll if (bs.bs_sleepduration > bs.bs_dtimperiod) 2336 1.32.2.2 skrll bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2337 1.32.2.2 skrll 2338 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_BEACON, 2339 1.32.2.11 skrll "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2340 1.32.2.2 skrll , __func__ 2341 1.32.2.11 skrll , tsf, tsftu 2342 1.32.2.2 skrll , bs.bs_intval 2343 1.32.2.2 skrll , bs.bs_nexttbtt 2344 1.32.2.2 skrll , bs.bs_dtimperiod 2345 1.32.2.2 skrll , bs.bs_nextdtim 2346 1.32.2.2 skrll , bs.bs_bmissthreshold 2347 1.32.2.2 skrll , bs.bs_sleepduration 2348 1.32.2.11 skrll , bs.bs_cfpperiod 2349 1.32.2.11 skrll , bs.bs_cfpmaxduration 2350 1.32.2.11 skrll , bs.bs_cfpnext 2351 1.32.2.11 skrll , bs.bs_timoffset 2352 1.32.2.11 skrll ); 2353 1.32.2.2 skrll ath_hal_intrset(ah, 0); 2354 1.32.2.11 skrll ath_hal_beacontimers(ah, &bs); 2355 1.32.2.2 skrll sc->sc_imask |= HAL_INT_BMISS; 2356 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 2357 1.32.2.2 skrll } else { 2358 1.32.2.3 skrll ath_hal_intrset(ah, 0); 2359 1.32.2.11 skrll if (nexttbtt == intval) 2360 1.32.2.11 skrll intval |= HAL_BEACON_RESET_TSF; 2361 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_IBSS) { 2362 1.32.2.11 skrll /* 2363 1.32.2.11 skrll * In IBSS mode enable the beacon timers but only 2364 1.32.2.11 skrll * enable SWBA interrupts if we need to manually 2365 1.32.2.11 skrll * prepare beacon frames. Otherwise we use a 2366 1.32.2.11 skrll * self-linked tx descriptor and let the hardware 2367 1.32.2.11 skrll * deal with things. 2368 1.32.2.11 skrll */ 2369 1.32.2.11 skrll intval |= HAL_BEACON_ENA; 2370 1.32.2.11 skrll if (!sc->sc_hasveol) 2371 1.32.2.11 skrll sc->sc_imask |= HAL_INT_SWBA; 2372 1.32.2.11 skrll ath_beaconq_config(sc); 2373 1.32.2.11 skrll } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2374 1.32.2.11 skrll /* 2375 1.32.2.11 skrll * In AP mode we enable the beacon timers and 2376 1.32.2.11 skrll * SWBA interrupts to prepare beacon frames. 2377 1.32.2.11 skrll */ 2378 1.32.2.11 skrll intval |= HAL_BEACON_ENA; 2379 1.32.2.11 skrll sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2380 1.32.2.11 skrll ath_beaconq_config(sc); 2381 1.32.2.3 skrll } 2382 1.32.2.3 skrll ath_hal_beaconinit(ah, nexttbtt, intval); 2383 1.32.2.11 skrll sc->sc_bmisscount = 0; 2384 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 2385 1.32.2.11 skrll /* 2386 1.32.2.11 skrll * When using a self-linked beacon descriptor in 2387 1.32.2.11 skrll * ibss mode load it once here. 2388 1.32.2.11 skrll */ 2389 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2390 1.32.2.3 skrll ath_beacon_proc(sc, 0); 2391 1.32.2.2 skrll } 2392 1.32.2.11 skrll #undef TSF_TO_TU 2393 1.32.2.2 skrll } 2394 1.32.2.2 skrll 2395 1.32.2.2 skrll static int 2396 1.32.2.11 skrll ath_descdma_setup(struct ath_softc *sc, 2397 1.32.2.11 skrll struct ath_descdma *dd, ath_bufhead *head, 2398 1.32.2.11 skrll const char *name, int nbuf, int ndesc) 2399 1.32.2.11 skrll { 2400 1.32.2.11 skrll #define DS2PHYS(_dd, _ds) \ 2401 1.32.2.11 skrll ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2402 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 2403 1.32.2.2 skrll struct ath_desc *ds; 2404 1.32.2.2 skrll struct ath_buf *bf; 2405 1.32.2.11 skrll int i, bsize, error; 2406 1.32.2.2 skrll 2407 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2408 1.32.2.11 skrll __func__, name, nbuf, ndesc); 2409 1.32.2.2 skrll 2410 1.32.2.11 skrll dd->dd_name = name; 2411 1.32.2.11 skrll dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2412 1.32.2.2 skrll 2413 1.32.2.11 skrll /* 2414 1.32.2.11 skrll * Setup DMA descriptor area. 2415 1.32.2.11 skrll */ 2416 1.32.2.11 skrll dd->dd_dmat = sc->sc_dmat; 2417 1.32.2.11 skrll 2418 1.32.2.11 skrll error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2419 1.32.2.11 skrll 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2420 1.32.2.11 skrll 2421 1.32.2.11 skrll if (error != 0) { 2422 1.32.2.11 skrll if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2423 1.32.2.11 skrll "error %u\n", nbuf * ndesc, dd->dd_name, error); 2424 1.32.2.2 skrll goto fail0; 2425 1.32.2.11 skrll } 2426 1.32.2.2 skrll 2427 1.32.2.11 skrll error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2428 1.32.2.11 skrll dd->dd_desc_len, (caddr_t *)&dd->dd_desc, BUS_DMA_COHERENT); 2429 1.32.2.11 skrll if (error != 0) { 2430 1.32.2.11 skrll if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2431 1.32.2.11 skrll nbuf * ndesc, dd->dd_name, error); 2432 1.32.2.2 skrll goto fail1; 2433 1.32.2.11 skrll } 2434 1.32.2.2 skrll 2435 1.32.2.11 skrll /* allocate descriptors */ 2436 1.32.2.11 skrll error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2437 1.32.2.11 skrll dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2438 1.32.2.11 skrll if (error != 0) { 2439 1.32.2.11 skrll if_printf(ifp, "unable to create dmamap for %s descriptors, " 2440 1.32.2.11 skrll "error %u\n", dd->dd_name, error); 2441 1.32.2.2 skrll goto fail2; 2442 1.32.2.2 skrll } 2443 1.32.2.2 skrll 2444 1.32.2.11 skrll error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2445 1.32.2.11 skrll dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2446 1.32.2.11 skrll if (error != 0) { 2447 1.32.2.11 skrll if_printf(ifp, "unable to map %s descriptors, error %u\n", 2448 1.32.2.11 skrll dd->dd_name, error); 2449 1.32.2.2 skrll goto fail3; 2450 1.32.2.2 skrll } 2451 1.32.2.2 skrll 2452 1.32.2.11 skrll ds = dd->dd_desc; 2453 1.32.2.11 skrll dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2454 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2455 1.32.2.11 skrll __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2456 1.32.2.11 skrll (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2457 1.32.2.11 skrll 2458 1.32.2.11 skrll /* allocate rx buffers */ 2459 1.32.2.11 skrll bsize = sizeof(struct ath_buf) * nbuf; 2460 1.32.2.11 skrll bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2461 1.32.2.2 skrll if (bf == NULL) { 2462 1.32.2.11 skrll if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2463 1.32.2.11 skrll dd->dd_name, bsize); 2464 1.32.2.11 skrll goto fail4; 2465 1.32.2.2 skrll } 2466 1.32.2.11 skrll dd->dd_bufptr = bf; 2467 1.32.2.2 skrll 2468 1.32.2.11 skrll STAILQ_INIT(head); 2469 1.32.2.11 skrll for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2470 1.32.2.2 skrll bf->bf_desc = ds; 2471 1.32.2.11 skrll bf->bf_daddr = DS2PHYS(dd, ds); 2472 1.32.2.11 skrll error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2473 1.32.2.11 skrll MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2474 1.32.2.11 skrll if (error != 0) { 2475 1.32.2.11 skrll if_printf(ifp, "unable to create dmamap for %s " 2476 1.32.2.11 skrll "buffer %u, error %u\n", dd->dd_name, i, error); 2477 1.32.2.11 skrll ath_descdma_cleanup(sc, dd, head); 2478 1.32.2.11 skrll return error; 2479 1.32.2.2 skrll } 2480 1.32.2.11 skrll STAILQ_INSERT_TAIL(head, bf, bf_list); 2481 1.32.2.2 skrll } 2482 1.32.2.2 skrll return 0; 2483 1.32.2.2 skrll fail4: 2484 1.32.2.11 skrll bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2485 1.32.2.2 skrll fail3: 2486 1.32.2.11 skrll bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2487 1.32.2.2 skrll fail2: 2488 1.32.2.11 skrll bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2489 1.32.2.2 skrll fail1: 2490 1.32.2.11 skrll bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2491 1.32.2.2 skrll fail0: 2492 1.32.2.11 skrll memset(dd, 0, sizeof(*dd)); 2493 1.32.2.2 skrll return error; 2494 1.32.2.11 skrll #undef DS2PHYS 2495 1.32.2.2 skrll } 2496 1.32.2.2 skrll 2497 1.32.2.2 skrll static void 2498 1.32.2.11 skrll ath_descdma_cleanup(struct ath_softc *sc, 2499 1.32.2.11 skrll struct ath_descdma *dd, ath_bufhead *head) 2500 1.32.2.2 skrll { 2501 1.32.2.2 skrll struct ath_buf *bf; 2502 1.32.2.11 skrll struct ieee80211_node *ni; 2503 1.32.2.2 skrll 2504 1.32.2.11 skrll bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2505 1.32.2.11 skrll bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2506 1.32.2.11 skrll bus_dmamem_unmap(dd->dd_dmat, (caddr_t)dd->dd_desc, dd->dd_desc_len); 2507 1.32.2.11 skrll bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2508 1.32.2.2 skrll 2509 1.32.2.11 skrll STAILQ_FOREACH(bf, head, bf_list) { 2510 1.32.2.2 skrll if (bf->bf_m) { 2511 1.32.2.2 skrll m_freem(bf->bf_m); 2512 1.32.2.2 skrll bf->bf_m = NULL; 2513 1.32.2.2 skrll } 2514 1.32.2.11 skrll if (bf->bf_dmamap != NULL) { 2515 1.32.2.11 skrll bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2516 1.32.2.11 skrll bf->bf_dmamap = NULL; 2517 1.32.2.11 skrll } 2518 1.32.2.11 skrll ni = bf->bf_node; 2519 1.32.2.11 skrll bf->bf_node = NULL; 2520 1.32.2.11 skrll if (ni != NULL) { 2521 1.32.2.11 skrll /* 2522 1.32.2.11 skrll * Reclaim node reference. 2523 1.32.2.11 skrll */ 2524 1.32.2.11 skrll ieee80211_free_node(ni); 2525 1.32.2.11 skrll } 2526 1.32.2.2 skrll } 2527 1.32.2.2 skrll 2528 1.32.2.11 skrll STAILQ_INIT(head); 2529 1.32.2.11 skrll free(dd->dd_bufptr, M_ATHDEV); 2530 1.32.2.11 skrll memset(dd, 0, sizeof(*dd)); 2531 1.32.2.2 skrll } 2532 1.32.2.2 skrll 2533 1.32.2.11 skrll static int 2534 1.32.2.11 skrll ath_desc_alloc(struct ath_softc *sc) 2535 1.32.2.2 skrll { 2536 1.32.2.11 skrll int error; 2537 1.32.2.11 skrll 2538 1.32.2.11 skrll error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2539 1.32.2.11 skrll "rx", ATH_RXBUF, 1); 2540 1.32.2.11 skrll if (error != 0) 2541 1.32.2.11 skrll return error; 2542 1.32.2.11 skrll 2543 1.32.2.11 skrll error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2544 1.32.2.11 skrll "tx", ATH_TXBUF, ATH_TXDESC); 2545 1.32.2.11 skrll if (error != 0) { 2546 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2547 1.32.2.11 skrll return error; 2548 1.32.2.11 skrll } 2549 1.32.2.11 skrll 2550 1.32.2.11 skrll error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2551 1.32.2.11 skrll "beacon", 1, 1); 2552 1.32.2.11 skrll if (error != 0) { 2553 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2554 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2555 1.32.2.11 skrll return error; 2556 1.32.2.11 skrll } 2557 1.32.2.11 skrll return 0; 2558 1.32.2.2 skrll } 2559 1.32.2.2 skrll 2560 1.32.2.2 skrll static void 2561 1.32.2.11 skrll ath_desc_free(struct ath_softc *sc) 2562 1.32.2.2 skrll { 2563 1.32.2.2 skrll 2564 1.32.2.11 skrll if (sc->sc_bdma.dd_desc_len != 0) 2565 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2566 1.32.2.11 skrll if (sc->sc_txdma.dd_desc_len != 0) 2567 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2568 1.32.2.11 skrll if (sc->sc_rxdma.dd_desc_len != 0) 2569 1.32.2.11 skrll ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2570 1.32.2.11 skrll } 2571 1.32.2.11 skrll 2572 1.32.2.11 skrll static struct ieee80211_node * 2573 1.32.2.11 skrll ath_node_alloc(struct ieee80211_node_table *nt) 2574 1.32.2.11 skrll { 2575 1.32.2.11 skrll struct ieee80211com *ic = nt->nt_ic; 2576 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 2577 1.32.2.11 skrll const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2578 1.32.2.11 skrll struct ath_node *an; 2579 1.32.2.11 skrll 2580 1.32.2.11 skrll an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2581 1.32.2.11 skrll if (an == NULL) { 2582 1.32.2.11 skrll /* XXX stat+msg */ 2583 1.32.2.11 skrll return NULL; 2584 1.32.2.2 skrll } 2585 1.32.2.11 skrll an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2586 1.32.2.11 skrll an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2587 1.32.2.11 skrll an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2588 1.32.2.11 skrll an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2589 1.32.2.11 skrll ath_rate_node_init(sc, an); 2590 1.32.2.11 skrll 2591 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2592 1.32.2.11 skrll return &an->an_node; 2593 1.32.2.2 skrll } 2594 1.32.2.2 skrll 2595 1.32.2.2 skrll static void 2596 1.32.2.11 skrll ath_node_free(struct ieee80211_node *ni) 2597 1.32.2.2 skrll { 2598 1.32.2.11 skrll struct ieee80211com *ic = ni->ni_ic; 2599 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 2600 1.32.2.11 skrll 2601 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2602 1.32.2.2 skrll 2603 1.32.2.11 skrll ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2604 1.32.2.11 skrll sc->sc_node_free(ni); 2605 1.32.2.2 skrll } 2606 1.32.2.2 skrll 2607 1.32.2.2 skrll static u_int8_t 2608 1.32.2.11 skrll ath_node_getrssi(const struct ieee80211_node *ni) 2609 1.32.2.2 skrll { 2610 1.32.2.11 skrll #define HAL_EP_RND(x, mul) \ 2611 1.32.2.11 skrll ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2612 1.32.2.11 skrll u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2613 1.32.2.11 skrll int32_t rssi; 2614 1.32.2.2 skrll 2615 1.32.2.2 skrll /* 2616 1.32.2.11 skrll * When only one frame is received there will be no state in 2617 1.32.2.11 skrll * avgrssi so fallback on the value recorded by the 802.11 layer. 2618 1.32.2.2 skrll */ 2619 1.32.2.11 skrll if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2620 1.32.2.11 skrll rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2621 1.32.2.11 skrll else 2622 1.32.2.11 skrll rssi = ni->ni_rssi; 2623 1.32.2.11 skrll /* NB: theoretically we shouldn't need this, but be paranoid */ 2624 1.32.2.11 skrll return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2625 1.32.2.11 skrll #undef HAL_EP_RND 2626 1.32.2.2 skrll } 2627 1.32.2.2 skrll 2628 1.32.2.2 skrll static int 2629 1.32.2.2 skrll ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2630 1.32.2.2 skrll { 2631 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2632 1.32.2.2 skrll int error; 2633 1.32.2.2 skrll struct mbuf *m; 2634 1.32.2.2 skrll struct ath_desc *ds; 2635 1.32.2.2 skrll 2636 1.32.2.2 skrll m = bf->bf_m; 2637 1.32.2.2 skrll if (m == NULL) { 2638 1.32.2.2 skrll /* 2639 1.32.2.2 skrll * NB: by assigning a page to the rx dma buffer we 2640 1.32.2.2 skrll * implicitly satisfy the Atheros requirement that 2641 1.32.2.2 skrll * this buffer be cache-line-aligned and sized to be 2642 1.32.2.2 skrll * multiple of the cache line size. Not doing this 2643 1.32.2.2 skrll * causes weird stuff to happen (for the 5210 at least). 2644 1.32.2.2 skrll */ 2645 1.32.2.11 skrll m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2646 1.32.2.2 skrll if (m == NULL) { 2647 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 2648 1.32.2.11 skrll "%s: no mbuf/cluster\n", __func__); 2649 1.32.2.2 skrll sc->sc_stats.ast_rx_nombuf++; 2650 1.32.2.2 skrll return ENOMEM; 2651 1.32.2.2 skrll } 2652 1.32.2.2 skrll bf->bf_m = m; 2653 1.32.2.2 skrll m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2654 1.32.2.2 skrll 2655 1.32.2.11 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, 2656 1.32.2.11 skrll bf->bf_dmamap, m, 2657 1.32.2.11 skrll BUS_DMA_NOWAIT); 2658 1.32.2.2 skrll if (error != 0) { 2659 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 2660 1.32.2.11 skrll "%s: bus_dmamap_load_mbuf failed; error %d\n", 2661 1.32.2.11 skrll __func__, error); 2662 1.32.2.2 skrll sc->sc_stats.ast_rx_busdma++; 2663 1.32.2.2 skrll return error; 2664 1.32.2.2 skrll } 2665 1.32.2.2 skrll KASSERT(bf->bf_nseg == 1, 2666 1.32.2.11 skrll ("multi-segment packet; nseg %u", bf->bf_nseg)); 2667 1.32.2.2 skrll } 2668 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2669 1.32.2.11 skrll bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2670 1.32.2.2 skrll 2671 1.32.2.2 skrll /* 2672 1.32.2.2 skrll * Setup descriptors. For receive we always terminate 2673 1.32.2.2 skrll * the descriptor list with a self-linked entry so we'll 2674 1.32.2.2 skrll * not get overrun under high load (as can happen with a 2675 1.32.2.11 skrll * 5212 when ANI processing enables PHY error frames). 2676 1.32.2.2 skrll * 2677 1.32.2.2 skrll * To insure the last descriptor is self-linked we create 2678 1.32.2.2 skrll * each descriptor as self-linked and add it to the end. As 2679 1.32.2.2 skrll * each additional descriptor is added the previous self-linked 2680 1.32.2.2 skrll * entry is ``fixed'' naturally. This should be safe even 2681 1.32.2.2 skrll * if DMA is happening. When processing RX interrupts we 2682 1.32.2.2 skrll * never remove/process the last, self-linked, entry on the 2683 1.32.2.2 skrll * descriptor list. This insures the hardware always has 2684 1.32.2.2 skrll * someplace to write a new frame. 2685 1.32.2.2 skrll */ 2686 1.32.2.2 skrll ds = bf->bf_desc; 2687 1.32.2.2 skrll ds->ds_link = bf->bf_daddr; /* link to self */ 2688 1.32.2.2 skrll ds->ds_data = bf->bf_segs[0].ds_addr; 2689 1.32.2.2 skrll ath_hal_setuprxdesc(ah, ds 2690 1.32.2.2 skrll , m->m_len /* buffer size */ 2691 1.32.2.2 skrll , 0 2692 1.32.2.2 skrll ); 2693 1.32.2.2 skrll 2694 1.32.2.2 skrll if (sc->sc_rxlink != NULL) 2695 1.32.2.2 skrll *sc->sc_rxlink = bf->bf_daddr; 2696 1.32.2.2 skrll sc->sc_rxlink = &ds->ds_link; 2697 1.32.2.2 skrll return 0; 2698 1.32.2.2 skrll } 2699 1.32.2.2 skrll 2700 1.32.2.11 skrll /* 2701 1.32.2.11 skrll * Extend 15-bit time stamp from rx descriptor to 2702 1.32.2.11 skrll * a full 64-bit TSF using the current h/w TSF. 2703 1.32.2.11 skrll */ 2704 1.32.2.11 skrll static __inline u_int64_t 2705 1.32.2.11 skrll ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp) 2706 1.32.2.11 skrll { 2707 1.32.2.11 skrll u_int64_t tsf; 2708 1.32.2.11 skrll 2709 1.32.2.11 skrll tsf = ath_hal_gettsf64(ah); 2710 1.32.2.11 skrll if ((tsf & 0x7fff) < rstamp) 2711 1.32.2.11 skrll tsf -= 0x8000; 2712 1.32.2.11 skrll return ((tsf &~ 0x7fff) | rstamp); 2713 1.32.2.11 skrll } 2714 1.32.2.11 skrll 2715 1.32.2.11 skrll /* 2716 1.32.2.11 skrll * Intercept management frames to collect beacon rssi data 2717 1.32.2.11 skrll * and to do ibss merges. 2718 1.32.2.11 skrll */ 2719 1.32.2.11 skrll static void 2720 1.32.2.11 skrll ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2721 1.32.2.11 skrll struct ieee80211_node *ni, 2722 1.32.2.11 skrll int subtype, int rssi, u_int32_t rstamp) 2723 1.32.2.11 skrll { 2724 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 2725 1.32.2.11 skrll 2726 1.32.2.11 skrll /* 2727 1.32.2.11 skrll * Call up first so subsequent work can use information 2728 1.32.2.11 skrll * potentially stored in the node (e.g. for ibss merge). 2729 1.32.2.11 skrll */ 2730 1.32.2.11 skrll sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2731 1.32.2.11 skrll switch (subtype) { 2732 1.32.2.11 skrll case IEEE80211_FC0_SUBTYPE_BEACON: 2733 1.32.2.11 skrll /* update rssi statistics for use by the hal */ 2734 1.32.2.11 skrll ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2735 1.32.2.11 skrll /* fall thru... */ 2736 1.32.2.11 skrll case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2737 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_IBSS && 2738 1.32.2.11 skrll ic->ic_state == IEEE80211_S_RUN) { 2739 1.32.2.11 skrll u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp); 2740 1.32.2.11 skrll 2741 1.32.2.11 skrll /* 2742 1.32.2.11 skrll * Handle ibss merge as needed; check the tsf on the 2743 1.32.2.11 skrll * frame before attempting the merge. The 802.11 spec 2744 1.32.2.11 skrll * says the station should change it's bssid to match 2745 1.32.2.11 skrll * the oldest station with the same ssid, where oldest 2746 1.32.2.11 skrll * is determined by the tsf. Note that hardware 2747 1.32.2.11 skrll * reconfiguration happens through callback to 2748 1.32.2.11 skrll * ath_newstate as the state machine will go from 2749 1.32.2.11 skrll * RUN -> RUN when this happens. 2750 1.32.2.11 skrll */ 2751 1.32.2.11 skrll if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2752 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_STATE, 2753 1.32.2.11 skrll "ibss merge, rstamp %u tsf %ju " 2754 1.32.2.11 skrll "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2755 1.32.2.11 skrll (uintmax_t)ni->ni_tstamp.tsf); 2756 1.32.2.12 christos (void) ieee80211_ibss_merge(ni); 2757 1.32.2.11 skrll } 2758 1.32.2.11 skrll } 2759 1.32.2.11 skrll break; 2760 1.32.2.11 skrll } 2761 1.32.2.11 skrll } 2762 1.32.2.11 skrll 2763 1.32.2.11 skrll /* 2764 1.32.2.11 skrll * Set the default antenna. 2765 1.32.2.11 skrll */ 2766 1.32.2.11 skrll static void 2767 1.32.2.11 skrll ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2768 1.32.2.11 skrll { 2769 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 2770 1.32.2.11 skrll 2771 1.32.2.11 skrll /* XXX block beacon interrupts */ 2772 1.32.2.11 skrll ath_hal_setdefantenna(ah, antenna); 2773 1.32.2.11 skrll if (sc->sc_defant != antenna) 2774 1.32.2.11 skrll sc->sc_stats.ast_ant_defswitch++; 2775 1.32.2.11 skrll sc->sc_defant = antenna; 2776 1.32.2.11 skrll sc->sc_rxotherant = 0; 2777 1.32.2.11 skrll } 2778 1.32.2.11 skrll 2779 1.32.2.2 skrll static void 2780 1.32.2.2 skrll ath_rx_proc(void *arg, int npending) 2781 1.32.2.2 skrll { 2782 1.32.2.2 skrll #define PA2DESC(_sc, _pa) \ 2783 1.32.2.11 skrll ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2784 1.32.2.11 skrll ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2785 1.32.2.2 skrll struct ath_softc *sc = arg; 2786 1.32.2.2 skrll struct ath_buf *bf; 2787 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2788 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 2789 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 2790 1.32.2.2 skrll struct ath_desc *ds; 2791 1.32.2.2 skrll struct mbuf *m; 2792 1.32.2.2 skrll struct ieee80211_node *ni; 2793 1.32.2.2 skrll struct ath_node *an; 2794 1.32.2.11 skrll int len, type; 2795 1.32.2.2 skrll u_int phyerr; 2796 1.32.2.2 skrll HAL_STATUS status; 2797 1.32.2.2 skrll 2798 1.32.2.11 skrll NET_LOCK_GIANT(); /* XXX */ 2799 1.32.2.11 skrll 2800 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2801 1.32.2.2 skrll do { 2802 1.32.2.11 skrll bf = STAILQ_FIRST(&sc->sc_rxbuf); 2803 1.32.2.2 skrll if (bf == NULL) { /* NB: shouldn't happen */ 2804 1.32.2.11 skrll if_printf(ifp, "%s: no buffer!\n", __func__); 2805 1.32.2.2 skrll break; 2806 1.32.2.2 skrll } 2807 1.32.2.2 skrll ds = bf->bf_desc; 2808 1.32.2.2 skrll if (ds->ds_link == bf->bf_daddr) { 2809 1.32.2.2 skrll /* NB: never process the self-linked entry at the end */ 2810 1.32.2.2 skrll break; 2811 1.32.2.2 skrll } 2812 1.32.2.2 skrll m = bf->bf_m; 2813 1.32.2.2 skrll if (m == NULL) { /* NB: shouldn't happen */ 2814 1.32.2.11 skrll if_printf(ifp, "%s: no mbuf!\n", __func__); 2815 1.32.2.2 skrll continue; 2816 1.32.2.2 skrll } 2817 1.32.2.2 skrll /* XXX sync descriptor memory */ 2818 1.32.2.2 skrll /* 2819 1.32.2.2 skrll * Must provide the virtual address of the current 2820 1.32.2.2 skrll * descriptor, the physical address, and the virtual 2821 1.32.2.2 skrll * address of the next descriptor in the h/w chain. 2822 1.32.2.2 skrll * This allows the HAL to look ahead to see if the 2823 1.32.2.2 skrll * hardware is done with a descriptor by checking the 2824 1.32.2.2 skrll * done bit in the following descriptor and the address 2825 1.32.2.2 skrll * of the current descriptor the DMA engine is working 2826 1.32.2.2 skrll * on. All this is necessary because of our use of 2827 1.32.2.2 skrll * a self-linked list to avoid rx overruns. 2828 1.32.2.2 skrll */ 2829 1.32.2.2 skrll status = ath_hal_rxprocdesc(ah, ds, 2830 1.32.2.2 skrll bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2831 1.32.2.2 skrll #ifdef AR_DEBUG 2832 1.32.2.11 skrll if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2833 1.32.2.11 skrll ath_printrxbuf(bf, status == HAL_OK); 2834 1.32.2.2 skrll #endif 2835 1.32.2.2 skrll if (status == HAL_EINPROGRESS) 2836 1.32.2.2 skrll break; 2837 1.32.2.11 skrll STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2838 1.32.2.3 skrll if (ds->ds_rxstat.rs_more) { 2839 1.32.2.3 skrll /* 2840 1.32.2.3 skrll * Frame spans multiple descriptors; this 2841 1.32.2.3 skrll * cannot happen yet as we don't support 2842 1.32.2.3 skrll * jumbograms. If not in monitor mode, 2843 1.32.2.3 skrll * discard the frame. 2844 1.32.2.3 skrll */ 2845 1.32.2.3 skrll if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2846 1.32.2.11 skrll sc->sc_stats.ast_rx_toobig++; 2847 1.32.2.3 skrll goto rx_next; 2848 1.32.2.3 skrll } 2849 1.32.2.3 skrll /* fall thru for monitor mode handling... */ 2850 1.32.2.3 skrll } else if (ds->ds_rxstat.rs_status != 0) { 2851 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2852 1.32.2.2 skrll sc->sc_stats.ast_rx_crcerr++; 2853 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2854 1.32.2.2 skrll sc->sc_stats.ast_rx_fifoerr++; 2855 1.32.2.2 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2856 1.32.2.2 skrll sc->sc_stats.ast_rx_phyerr++; 2857 1.32.2.2 skrll phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2858 1.32.2.2 skrll sc->sc_stats.ast_rx_phy[phyerr]++; 2859 1.32.2.11 skrll goto rx_next; 2860 1.32.2.2 skrll } 2861 1.32.2.11 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2862 1.32.2.11 skrll /* 2863 1.32.2.11 skrll * Decrypt error. If the error occurred 2864 1.32.2.11 skrll * because there was no hardware key, then 2865 1.32.2.11 skrll * let the frame through so the upper layers 2866 1.32.2.11 skrll * can process it. This is necessary for 5210 2867 1.32.2.11 skrll * parts which have no way to setup a ``clear'' 2868 1.32.2.11 skrll * key cache entry. 2869 1.32.2.11 skrll * 2870 1.32.2.11 skrll * XXX do key cache faulting 2871 1.32.2.11 skrll */ 2872 1.32.2.11 skrll if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2873 1.32.2.11 skrll goto rx_accept; 2874 1.32.2.11 skrll sc->sc_stats.ast_rx_badcrypt++; 2875 1.32.2.11 skrll } 2876 1.32.2.11 skrll if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2877 1.32.2.11 skrll sc->sc_stats.ast_rx_badmic++; 2878 1.32.2.11 skrll /* 2879 1.32.2.11 skrll * Do minimal work required to hand off 2880 1.32.2.11 skrll * the 802.11 header for notifcation. 2881 1.32.2.11 skrll */ 2882 1.32.2.11 skrll /* XXX frag's and qos frames */ 2883 1.32.2.11 skrll len = ds->ds_rxstat.rs_datalen; 2884 1.32.2.11 skrll if (len >= sizeof (struct ieee80211_frame)) { 2885 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, 2886 1.32.2.11 skrll bf->bf_dmamap, 2887 1.32.2.11 skrll 0, bf->bf_dmamap->dm_mapsize, 2888 1.32.2.11 skrll BUS_DMASYNC_POSTREAD); 2889 1.32.2.11 skrll ieee80211_notify_michael_failure(ic, 2890 1.32.2.11 skrll mtod(m, struct ieee80211_frame *), 2891 1.32.2.11 skrll sc->sc_splitmic ? 2892 1.32.2.11 skrll ds->ds_rxstat.rs_keyix-32 : 2893 1.32.2.11 skrll ds->ds_rxstat.rs_keyix 2894 1.32.2.11 skrll ); 2895 1.32.2.11 skrll } 2896 1.32.2.11 skrll } 2897 1.32.2.11 skrll ifp->if_ierrors++; 2898 1.32.2.3 skrll /* 2899 1.32.2.11 skrll * Reject error frames, we normally don't want 2900 1.32.2.11 skrll * to see them in monitor mode (in monitor mode 2901 1.32.2.11 skrll * allow through packets that have crypto problems). 2902 1.32.2.3 skrll */ 2903 1.32.2.11 skrll if ((ds->ds_rxstat.rs_status &~ 2904 1.32.2.11 skrll (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) || 2905 1.32.2.3 skrll sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) 2906 1.32.2.3 skrll goto rx_next; 2907 1.32.2.2 skrll } 2908 1.32.2.11 skrll rx_accept: 2909 1.32.2.11 skrll /* 2910 1.32.2.11 skrll * Sync and unmap the frame. At this point we're 2911 1.32.2.11 skrll * committed to passing the mbuf somewhere so clear 2912 1.32.2.11 skrll * bf_m; this means a new sk_buff must be allocated 2913 1.32.2.11 skrll * when the rx descriptor is setup again to receive 2914 1.32.2.11 skrll * another frame. 2915 1.32.2.11 skrll */ 2916 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2917 1.32.2.11 skrll 0, bf->bf_dmamap->dm_mapsize, 2918 1.32.2.11 skrll BUS_DMASYNC_POSTREAD); 2919 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2920 1.32.2.2 skrll bf->bf_m = NULL; 2921 1.32.2.11 skrll 2922 1.32.2.2 skrll m->m_pkthdr.rcvif = ifp; 2923 1.32.2.11 skrll len = ds->ds_rxstat.rs_datalen; 2924 1.32.2.2 skrll m->m_pkthdr.len = m->m_len = len; 2925 1.32.2.2 skrll 2926 1.32.2.11 skrll sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2927 1.32.2.11 skrll 2928 1.32.2.2 skrll #if NBPFILTER > 0 2929 1.32.2.2 skrll if (sc->sc_drvbpf) { 2930 1.32.2.11 skrll u_int8_t rix; 2931 1.32.2.11 skrll 2932 1.32.2.11 skrll /* 2933 1.32.2.11 skrll * Discard anything shorter than an ack or cts. 2934 1.32.2.11 skrll */ 2935 1.32.2.11 skrll if (len < IEEE80211_ACK_LEN) { 2936 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RECV, 2937 1.32.2.11 skrll "%s: runt packet %d\n", 2938 1.32.2.11 skrll __func__, len); 2939 1.32.2.11 skrll sc->sc_stats.ast_rx_tooshort++; 2940 1.32.2.11 skrll m_freem(m); 2941 1.32.2.11 skrll goto rx_next; 2942 1.32.2.11 skrll } 2943 1.32.2.11 skrll rix = ds->ds_rxstat.rs_rate; 2944 1.32.2.12 christos sc->sc_rx_th.wr_tsf = ath_extend_tsf(sc->sc_ah, 2945 1.32.2.12 christos ds->ds_rxstat.rs_tstamp); 2946 1.32.2.11 skrll sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2947 1.32.2.11 skrll sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2948 1.32.2.2 skrll sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 2949 1.32.2.2 skrll sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2950 1.32.2.11 skrll 2951 1.32.2.2 skrll bpf_mtap2(sc->sc_drvbpf, 2952 1.32.2.2 skrll &sc->sc_rx_th, sc->sc_rx_th_len, m); 2953 1.32.2.2 skrll } 2954 1.32.2.2 skrll #endif 2955 1.32.2.2 skrll 2956 1.32.2.11 skrll /* 2957 1.32.2.11 skrll * From this point on we assume the frame is at least 2958 1.32.2.11 skrll * as large as ieee80211_frame_min; verify that. 2959 1.32.2.11 skrll */ 2960 1.32.2.11 skrll if (len < IEEE80211_MIN_LEN) { 2961 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2962 1.32.2.11 skrll __func__, len); 2963 1.32.2.11 skrll sc->sc_stats.ast_rx_tooshort++; 2964 1.32.2.11 skrll m_freem(m); 2965 1.32.2.11 skrll goto rx_next; 2966 1.32.2.11 skrll } 2967 1.32.2.11 skrll 2968 1.32.2.11 skrll if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2969 1.32.2.11 skrll ieee80211_dump_pkt(mtod(m, caddr_t), len, 2970 1.32.2.11 skrll sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2971 1.32.2.11 skrll ds->ds_rxstat.rs_rssi); 2972 1.32.2.11 skrll } 2973 1.32.2.11 skrll 2974 1.32.2.2 skrll m_adj(m, -IEEE80211_CRC_LEN); 2975 1.32.2.11 skrll 2976 1.32.2.11 skrll /* 2977 1.32.2.11 skrll * Locate the node for sender, track state, and then 2978 1.32.2.11 skrll * pass the (referenced) node up to the 802.11 layer 2979 1.32.2.12 christos * for its use. 2980 1.32.2.11 skrll */ 2981 1.32.2.12 christos ni = ieee80211_find_rxnode_withkey(ic, 2982 1.32.2.12 christos mtod(m, const struct ieee80211_frame_min *), 2983 1.32.2.12 christos ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 2984 1.32.2.12 christos IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 2985 1.32.2.12 christos /* 2986 1.32.2.12 christos * Track rx rssi and do any rx antenna management. 2987 1.32.2.12 christos */ 2988 1.32.2.12 christos an = ATH_NODE(ni); 2989 1.32.2.12 christos ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2990 1.32.2.12 christos /* 2991 1.32.2.12 christos * Send frame up for processing. 2992 1.32.2.12 christos */ 2993 1.32.2.12 christos type = ieee80211_input(ic, m, ni, 2994 1.32.2.12 christos ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2995 1.32.2.11 skrll ieee80211_free_node(ni); 2996 1.32.2.11 skrll if (sc->sc_diversity) { 2997 1.32.2.11 skrll /* 2998 1.32.2.11 skrll * When using fast diversity, change the default rx 2999 1.32.2.11 skrll * antenna if diversity chooses the other antenna 3 3000 1.32.2.11 skrll * times in a row. 3001 1.32.2.11 skrll */ 3002 1.32.2.11 skrll if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3003 1.32.2.11 skrll if (++sc->sc_rxotherant >= 3) 3004 1.32.2.11 skrll ath_setdefantenna(sc, 3005 1.32.2.11 skrll ds->ds_rxstat.rs_antenna); 3006 1.32.2.11 skrll } else 3007 1.32.2.11 skrll sc->sc_rxotherant = 0; 3008 1.32.2.11 skrll } 3009 1.32.2.11 skrll if (sc->sc_softled) { 3010 1.32.2.11 skrll /* 3011 1.32.2.11 skrll * Blink for any data frame. Otherwise do a 3012 1.32.2.11 skrll * heartbeat-style blink when idle. The latter 3013 1.32.2.11 skrll * is mainly for station mode where we depend on 3014 1.32.2.11 skrll * periodic beacon frames to trigger the poll event. 3015 1.32.2.11 skrll */ 3016 1.32.2.11 skrll if (type == IEEE80211_FC0_TYPE_DATA) { 3017 1.32.2.11 skrll sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3018 1.32.2.11 skrll ath_led_event(sc, ATH_LED_RX); 3019 1.32.2.11 skrll } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3020 1.32.2.11 skrll ath_led_event(sc, ATH_LED_POLL); 3021 1.32.2.11 skrll } 3022 1.32.2.11 skrll rx_next: 3023 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3024 1.32.2.2 skrll } while (ath_rxbuf_init(sc, bf) == 0); 3025 1.32.2.2 skrll 3026 1.32.2.11 skrll /* rx signal state monitoring */ 3027 1.32.2.11 skrll ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 3028 1.32.2.2 skrll 3029 1.32.2.2 skrll #ifdef __NetBSD__ 3030 1.32.2.11 skrll /* XXX Why isn't this necessary in FreeBSD? */ 3031 1.32.2.2 skrll if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3032 1.32.2.2 skrll ath_start(ifp); 3033 1.32.2.2 skrll #endif /* __NetBSD__ */ 3034 1.32.2.11 skrll 3035 1.32.2.11 skrll NET_UNLOCK_GIANT(); /* XXX */ 3036 1.32.2.2 skrll #undef PA2DESC 3037 1.32.2.2 skrll } 3038 1.32.2.2 skrll 3039 1.32.2.2 skrll /* 3040 1.32.2.11 skrll * Setup a h/w transmit queue. 3041 1.32.2.2 skrll */ 3042 1.32.2.11 skrll static struct ath_txq * 3043 1.32.2.11 skrll ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3044 1.32.2.2 skrll { 3045 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 3046 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3047 1.32.2.11 skrll HAL_TXQ_INFO qi; 3048 1.32.2.11 skrll int qnum; 3049 1.32.2.3 skrll 3050 1.32.2.11 skrll memset(&qi, 0, sizeof(qi)); 3051 1.32.2.11 skrll qi.tqi_subtype = subtype; 3052 1.32.2.11 skrll qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3053 1.32.2.11 skrll qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3054 1.32.2.11 skrll qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3055 1.32.2.11 skrll /* 3056 1.32.2.11 skrll * Enable interrupts only for EOL and DESC conditions. 3057 1.32.2.11 skrll * We mark tx descriptors to receive a DESC interrupt 3058 1.32.2.11 skrll * when a tx queue gets deep; otherwise waiting for the 3059 1.32.2.11 skrll * EOL to reap descriptors. Note that this is done to 3060 1.32.2.11 skrll * reduce interrupt load and this only defers reaping 3061 1.32.2.11 skrll * descriptors, never transmitting frames. Aside from 3062 1.32.2.11 skrll * reducing interrupts this also permits more concurrency. 3063 1.32.2.11 skrll * The only potential downside is if the tx queue backs 3064 1.32.2.11 skrll * up in which case the top half of the kernel may backup 3065 1.32.2.11 skrll * due to a lack of tx descriptors. 3066 1.32.2.11 skrll */ 3067 1.32.2.11 skrll qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 3068 1.32.2.11 skrll qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3069 1.32.2.11 skrll if (qnum == -1) { 3070 1.32.2.2 skrll /* 3071 1.32.2.11 skrll * NB: don't print a message, this happens 3072 1.32.2.11 skrll * normally on parts with too few tx queues 3073 1.32.2.2 skrll */ 3074 1.32.2.11 skrll return NULL; 3075 1.32.2.11 skrll } 3076 1.32.2.11 skrll if (qnum >= N(sc->sc_txq)) { 3077 1.32.2.11 skrll device_printf(sc->sc_dev, 3078 1.32.2.11 skrll "hal qnum %u out of range, max %zu!\n", 3079 1.32.2.11 skrll qnum, N(sc->sc_txq)); 3080 1.32.2.11 skrll ath_hal_releasetxqueue(ah, qnum); 3081 1.32.2.11 skrll return NULL; 3082 1.32.2.11 skrll } 3083 1.32.2.11 skrll if (!ATH_TXQ_SETUP(sc, qnum)) { 3084 1.32.2.11 skrll struct ath_txq *txq = &sc->sc_txq[qnum]; 3085 1.32.2.3 skrll 3086 1.32.2.11 skrll txq->axq_qnum = qnum; 3087 1.32.2.11 skrll txq->axq_depth = 0; 3088 1.32.2.11 skrll txq->axq_intrcnt = 0; 3089 1.32.2.11 skrll txq->axq_link = NULL; 3090 1.32.2.11 skrll STAILQ_INIT(&txq->axq_q); 3091 1.32.2.11 skrll ATH_TXQ_LOCK_INIT(sc, txq); 3092 1.32.2.11 skrll sc->sc_txqsetup |= 1<<qnum; 3093 1.32.2.2 skrll } 3094 1.32.2.11 skrll return &sc->sc_txq[qnum]; 3095 1.32.2.11 skrll #undef N 3096 1.32.2.11 skrll } 3097 1.32.2.11 skrll 3098 1.32.2.11 skrll /* 3099 1.32.2.11 skrll * Setup a hardware data transmit queue for the specified 3100 1.32.2.11 skrll * access control. The hal may not support all requested 3101 1.32.2.11 skrll * queues in which case it will return a reference to a 3102 1.32.2.11 skrll * previously setup queue. We record the mapping from ac's 3103 1.32.2.11 skrll * to h/w queues for use by ath_tx_start and also track 3104 1.32.2.11 skrll * the set of h/w queues being used to optimize work in the 3105 1.32.2.11 skrll * transmit interrupt handler and related routines. 3106 1.32.2.11 skrll */ 3107 1.32.2.11 skrll static int 3108 1.32.2.11 skrll ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3109 1.32.2.11 skrll { 3110 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 3111 1.32.2.11 skrll struct ath_txq *txq; 3112 1.32.2.11 skrll 3113 1.32.2.11 skrll if (ac >= N(sc->sc_ac2q)) { 3114 1.32.2.11 skrll device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3115 1.32.2.11 skrll ac, N(sc->sc_ac2q)); 3116 1.32.2.11 skrll return 0; 3117 1.32.2.11 skrll } 3118 1.32.2.11 skrll txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3119 1.32.2.11 skrll if (txq != NULL) { 3120 1.32.2.11 skrll sc->sc_ac2q[ac] = txq; 3121 1.32.2.11 skrll return 1; 3122 1.32.2.11 skrll } else 3123 1.32.2.11 skrll return 0; 3124 1.32.2.11 skrll #undef N 3125 1.32.2.11 skrll } 3126 1.32.2.11 skrll 3127 1.32.2.11 skrll /* 3128 1.32.2.11 skrll * Update WME parameters for a transmit queue. 3129 1.32.2.11 skrll */ 3130 1.32.2.11 skrll static int 3131 1.32.2.11 skrll ath_txq_update(struct ath_softc *sc, int ac) 3132 1.32.2.11 skrll { 3133 1.32.2.11 skrll #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3134 1.32.2.11 skrll #define ATH_TXOP_TO_US(v) (v<<5) 3135 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 3136 1.32.2.11 skrll struct ath_txq *txq = sc->sc_ac2q[ac]; 3137 1.32.2.11 skrll struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3138 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 3139 1.32.2.11 skrll HAL_TXQ_INFO qi; 3140 1.32.2.11 skrll 3141 1.32.2.11 skrll ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3142 1.32.2.11 skrll qi.tqi_aifs = wmep->wmep_aifsn; 3143 1.32.2.11 skrll qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3144 1.32.2.11 skrll qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3145 1.32.2.11 skrll qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3146 1.32.2.11 skrll 3147 1.32.2.11 skrll if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3148 1.32.2.11 skrll device_printf(sc->sc_dev, "unable to update hardware queue " 3149 1.32.2.11 skrll "parameters for %s traffic!\n", 3150 1.32.2.11 skrll ieee80211_wme_acnames[ac]); 3151 1.32.2.11 skrll return 0; 3152 1.32.2.11 skrll } else { 3153 1.32.2.11 skrll ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3154 1.32.2.11 skrll return 1; 3155 1.32.2.11 skrll } 3156 1.32.2.11 skrll #undef ATH_TXOP_TO_US 3157 1.32.2.11 skrll #undef ATH_EXPONENT_TO_VALUE 3158 1.32.2.11 skrll } 3159 1.32.2.11 skrll 3160 1.32.2.11 skrll /* 3161 1.32.2.11 skrll * Callback from the 802.11 layer to update WME parameters. 3162 1.32.2.11 skrll */ 3163 1.32.2.11 skrll static int 3164 1.32.2.11 skrll ath_wme_update(struct ieee80211com *ic) 3165 1.32.2.11 skrll { 3166 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 3167 1.32.2.11 skrll 3168 1.32.2.11 skrll return !ath_txq_update(sc, WME_AC_BE) || 3169 1.32.2.11 skrll !ath_txq_update(sc, WME_AC_BK) || 3170 1.32.2.11 skrll !ath_txq_update(sc, WME_AC_VI) || 3171 1.32.2.11 skrll !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3172 1.32.2.11 skrll } 3173 1.32.2.11 skrll 3174 1.32.2.11 skrll /* 3175 1.32.2.11 skrll * Reclaim resources for a setup queue. 3176 1.32.2.11 skrll */ 3177 1.32.2.11 skrll static void 3178 1.32.2.11 skrll ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3179 1.32.2.11 skrll { 3180 1.32.2.11 skrll 3181 1.32.2.11 skrll ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3182 1.32.2.11 skrll ATH_TXQ_LOCK_DESTROY(txq); 3183 1.32.2.11 skrll sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3184 1.32.2.11 skrll } 3185 1.32.2.11 skrll 3186 1.32.2.11 skrll /* 3187 1.32.2.11 skrll * Reclaim all tx queue resources. 3188 1.32.2.11 skrll */ 3189 1.32.2.11 skrll static void 3190 1.32.2.11 skrll ath_tx_cleanup(struct ath_softc *sc) 3191 1.32.2.11 skrll { 3192 1.32.2.11 skrll int i; 3193 1.32.2.11 skrll 3194 1.32.2.11 skrll ATH_TXBUF_LOCK_DESTROY(sc); 3195 1.32.2.11 skrll for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3196 1.32.2.11 skrll if (ATH_TXQ_SETUP(sc, i)) 3197 1.32.2.11 skrll ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3198 1.32.2.11 skrll } 3199 1.32.2.11 skrll 3200 1.32.2.11 skrll /* 3201 1.32.2.11 skrll * Defragment an mbuf chain, returning at most maxfrags separate 3202 1.32.2.11 skrll * mbufs+clusters. If this is not possible NULL is returned and 3203 1.32.2.11 skrll * the original mbuf chain is left in it's present (potentially 3204 1.32.2.11 skrll * modified) state. We use two techniques: collapsing consecutive 3205 1.32.2.11 skrll * mbufs and replacing consecutive mbufs by a cluster. 3206 1.32.2.11 skrll */ 3207 1.32.2.11 skrll static struct mbuf * 3208 1.32.2.11 skrll ath_defrag(struct mbuf *m0, int how, int maxfrags) 3209 1.32.2.11 skrll { 3210 1.32.2.11 skrll struct mbuf *m, *n, *n2, **prev; 3211 1.32.2.11 skrll u_int curfrags; 3212 1.32.2.11 skrll 3213 1.32.2.11 skrll /* 3214 1.32.2.11 skrll * Calculate the current number of frags. 3215 1.32.2.11 skrll */ 3216 1.32.2.11 skrll curfrags = 0; 3217 1.32.2.11 skrll for (m = m0; m != NULL; m = m->m_next) 3218 1.32.2.11 skrll curfrags++; 3219 1.32.2.11 skrll /* 3220 1.32.2.11 skrll * First, try to collapse mbufs. Note that we always collapse 3221 1.32.2.11 skrll * towards the front so we don't need to deal with moving the 3222 1.32.2.11 skrll * pkthdr. This may be suboptimal if the first mbuf has much 3223 1.32.2.11 skrll * less data than the following. 3224 1.32.2.11 skrll */ 3225 1.32.2.11 skrll m = m0; 3226 1.32.2.11 skrll again: 3227 1.32.2.11 skrll for (;;) { 3228 1.32.2.11 skrll n = m->m_next; 3229 1.32.2.11 skrll if (n == NULL) 3230 1.32.2.11 skrll break; 3231 1.32.2.11 skrll if ((m->m_flags & M_RDONLY) == 0 && 3232 1.32.2.11 skrll n->m_len < M_TRAILINGSPACE(m)) { 3233 1.32.2.11 skrll bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3234 1.32.2.11 skrll n->m_len); 3235 1.32.2.11 skrll m->m_len += n->m_len; 3236 1.32.2.11 skrll m->m_next = n->m_next; 3237 1.32.2.11 skrll m_free(n); 3238 1.32.2.11 skrll if (--curfrags <= maxfrags) 3239 1.32.2.11 skrll return m0; 3240 1.32.2.11 skrll } else 3241 1.32.2.11 skrll m = n; 3242 1.32.2.11 skrll } 3243 1.32.2.11 skrll KASSERT(maxfrags > 1, 3244 1.32.2.11 skrll ("maxfrags %u, but normal collapse failed", maxfrags)); 3245 1.32.2.11 skrll /* 3246 1.32.2.11 skrll * Collapse consecutive mbufs to a cluster. 3247 1.32.2.11 skrll */ 3248 1.32.2.11 skrll prev = &m0->m_next; /* NB: not the first mbuf */ 3249 1.32.2.11 skrll while ((n = *prev) != NULL) { 3250 1.32.2.11 skrll if ((n2 = n->m_next) != NULL && 3251 1.32.2.11 skrll n->m_len + n2->m_len < MCLBYTES) { 3252 1.32.2.11 skrll m = m_getcl(how, MT_DATA, 0); 3253 1.32.2.11 skrll if (m == NULL) 3254 1.32.2.11 skrll goto bad; 3255 1.32.2.11 skrll bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3256 1.32.2.11 skrll bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3257 1.32.2.11 skrll n2->m_len); 3258 1.32.2.11 skrll m->m_len = n->m_len + n2->m_len; 3259 1.32.2.11 skrll m->m_next = n2->m_next; 3260 1.32.2.11 skrll *prev = m; 3261 1.32.2.11 skrll m_free(n); 3262 1.32.2.11 skrll m_free(n2); 3263 1.32.2.11 skrll if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3264 1.32.2.11 skrll return m0; 3265 1.32.2.11 skrll /* 3266 1.32.2.11 skrll * Still not there, try the normal collapse 3267 1.32.2.11 skrll * again before we allocate another cluster. 3268 1.32.2.11 skrll */ 3269 1.32.2.11 skrll goto again; 3270 1.32.2.11 skrll } 3271 1.32.2.11 skrll prev = &n->m_next; 3272 1.32.2.11 skrll } 3273 1.32.2.11 skrll /* 3274 1.32.2.11 skrll * No place where we can collapse to a cluster; punt. 3275 1.32.2.11 skrll * This can occur if, for example, you request 2 frags 3276 1.32.2.11 skrll * but the packet requires that both be clusters (we 3277 1.32.2.11 skrll * never reallocate the first mbuf to avoid moving the 3278 1.32.2.11 skrll * packet header). 3279 1.32.2.11 skrll */ 3280 1.32.2.11 skrll bad: 3281 1.32.2.11 skrll return NULL; 3282 1.32.2.11 skrll } 3283 1.32.2.11 skrll 3284 1.32.2.11 skrll static int 3285 1.32.2.11 skrll ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3286 1.32.2.11 skrll struct mbuf *m0) 3287 1.32.2.11 skrll { 3288 1.32.2.11 skrll #define CTS_DURATION \ 3289 1.32.2.11 skrll ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE) 3290 1.32.2.11 skrll #define updateCTSForBursting(_ah, _ds, _txq) \ 3291 1.32.2.11 skrll ath_hal_updateCTSForBursting(_ah, _ds, \ 3292 1.32.2.11 skrll _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \ 3293 1.32.2.11 skrll _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \ 3294 1.32.2.11 skrll txopLimit, CTS_DURATION) 3295 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 3296 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 3297 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 3298 1.32.2.11 skrll const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3299 1.32.2.11 skrll int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3300 1.32.2.11 skrll u_int8_t rix, txrate, ctsrate; 3301 1.32.2.11 skrll u_int8_t cix = 0xff; /* NB: silence compiler */ 3302 1.32.2.11 skrll struct ath_desc *ds, *ds0; 3303 1.32.2.11 skrll struct ath_txq *txq; 3304 1.32.2.11 skrll struct ieee80211_frame *wh; 3305 1.32.2.11 skrll u_int subtype, flags, ctsduration; 3306 1.32.2.11 skrll HAL_PKT_TYPE atype; 3307 1.32.2.11 skrll const HAL_RATE_TABLE *rt; 3308 1.32.2.11 skrll HAL_BOOL shortPreamble; 3309 1.32.2.11 skrll struct ath_node *an; 3310 1.32.2.11 skrll struct mbuf *m; 3311 1.32.2.11 skrll u_int pri; 3312 1.32.2.11 skrll 3313 1.32.2.11 skrll wh = mtod(m0, struct ieee80211_frame *); 3314 1.32.2.11 skrll iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3315 1.32.2.11 skrll ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3316 1.32.2.11 skrll hdrlen = ieee80211_anyhdrsize(wh); 3317 1.32.2.11 skrll /* 3318 1.32.2.11 skrll * Packet length must not include any 3319 1.32.2.11 skrll * pad bytes; deduct them here. 3320 1.32.2.11 skrll */ 3321 1.32.2.11 skrll pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3322 1.32.2.11 skrll 3323 1.32.2.11 skrll if (iswep) { 3324 1.32.2.11 skrll const struct ieee80211_cipher *cip; 3325 1.32.2.11 skrll struct ieee80211_key *k; 3326 1.32.2.11 skrll 3327 1.32.2.11 skrll /* 3328 1.32.2.11 skrll * Construct the 802.11 header+trailer for an encrypted 3329 1.32.2.11 skrll * frame. The only reason this can fail is because of an 3330 1.32.2.11 skrll * unknown or unsupported cipher/key type. 3331 1.32.2.11 skrll */ 3332 1.32.2.11 skrll k = ieee80211_crypto_encap(ic, ni, m0); 3333 1.32.2.11 skrll if (k == NULL) { 3334 1.32.2.11 skrll /* 3335 1.32.2.11 skrll * This can happen when the key is yanked after the 3336 1.32.2.11 skrll * frame was queued. Just discard the frame; the 3337 1.32.2.11 skrll * 802.11 layer counts failures and provides 3338 1.32.2.11 skrll * debugging/diagnostics. 3339 1.32.2.11 skrll */ 3340 1.32.2.11 skrll m_freem(m0); 3341 1.32.2.11 skrll return EIO; 3342 1.32.2.11 skrll } 3343 1.32.2.11 skrll /* 3344 1.32.2.11 skrll * Adjust the packet + header lengths for the crypto 3345 1.32.2.11 skrll * additions and calculate the h/w key index. When 3346 1.32.2.11 skrll * a s/w mic is done the frame will have had any mic 3347 1.32.2.11 skrll * added to it prior to entry so skb->len above will 3348 1.32.2.11 skrll * account for it. Otherwise we need to add it to the 3349 1.32.2.11 skrll * packet length. 3350 1.32.2.11 skrll */ 3351 1.32.2.11 skrll cip = k->wk_cipher; 3352 1.32.2.11 skrll hdrlen += cip->ic_header; 3353 1.32.2.11 skrll pktlen += cip->ic_header + cip->ic_trailer; 3354 1.32.2.11 skrll if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3355 1.32.2.11 skrll pktlen += cip->ic_miclen; 3356 1.32.2.11 skrll keyix = k->wk_keyix; 3357 1.32.2.11 skrll 3358 1.32.2.11 skrll /* packet header may have moved, reset our local pointer */ 3359 1.32.2.11 skrll wh = mtod(m0, struct ieee80211_frame *); 3360 1.32.2.11 skrll } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3361 1.32.2.11 skrll /* 3362 1.32.2.11 skrll * Use station key cache slot, if assigned. 3363 1.32.2.11 skrll */ 3364 1.32.2.11 skrll keyix = ni->ni_ucastkey.wk_keyix; 3365 1.32.2.11 skrll if (keyix == IEEE80211_KEYIX_NONE) 3366 1.32.2.11 skrll keyix = HAL_TXKEYIX_INVALID; 3367 1.32.2.11 skrll } else 3368 1.32.2.11 skrll keyix = HAL_TXKEYIX_INVALID; 3369 1.32.2.11 skrll 3370 1.32.2.11 skrll pktlen += IEEE80211_CRC_LEN; 3371 1.32.2.2 skrll 3372 1.32.2.2 skrll /* 3373 1.32.2.2 skrll * Load the DMA map so any coalescing is done. This 3374 1.32.2.2 skrll * also calculates the number of descriptors we need. 3375 1.32.2.2 skrll */ 3376 1.32.2.11 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3377 1.32.2.11 skrll BUS_DMA_NOWAIT); 3378 1.32.2.11 skrll if (error == EFBIG) { 3379 1.32.2.11 skrll /* XXX packet requires too many descriptors */ 3380 1.32.2.11 skrll bf->bf_nseg = ATH_TXDESC+1; 3381 1.32.2.11 skrll } else if (error != 0) { 3382 1.32.2.11 skrll sc->sc_stats.ast_tx_busdma++; 3383 1.32.2.11 skrll m_freem(m0); 3384 1.32.2.11 skrll return error; 3385 1.32.2.11 skrll } 3386 1.32.2.2 skrll /* 3387 1.32.2.2 skrll * Discard null packets and check for packets that 3388 1.32.2.2 skrll * require too many TX descriptors. We try to convert 3389 1.32.2.2 skrll * the latter to a cluster. 3390 1.32.2.2 skrll */ 3391 1.32.2.2 skrll if (error == EFBIG) { /* too many desc's, linearize */ 3392 1.32.2.2 skrll sc->sc_stats.ast_tx_linear++; 3393 1.32.2.11 skrll m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3394 1.32.2.2 skrll if (m == NULL) { 3395 1.32.2.2 skrll m_freem(m0); 3396 1.32.2.11 skrll sc->sc_stats.ast_tx_nombuf++; 3397 1.32.2.2 skrll return ENOMEM; 3398 1.32.2.2 skrll } 3399 1.32.2.2 skrll m0 = m; 3400 1.32.2.11 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3401 1.32.2.11 skrll BUS_DMA_NOWAIT); 3402 1.32.2.2 skrll if (error != 0) { 3403 1.32.2.2 skrll sc->sc_stats.ast_tx_busdma++; 3404 1.32.2.2 skrll m_freem(m0); 3405 1.32.2.2 skrll return error; 3406 1.32.2.2 skrll } 3407 1.32.2.11 skrll KASSERT(bf->bf_nseg <= ATH_TXDESC, 3408 1.32.2.11 skrll ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3409 1.32.2.2 skrll } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3410 1.32.2.2 skrll sc->sc_stats.ast_tx_nodata++; 3411 1.32.2.2 skrll m_freem(m0); 3412 1.32.2.2 skrll return EIO; 3413 1.32.2.2 skrll } 3414 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3415 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3416 1.32.2.11 skrll bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3417 1.32.2.2 skrll bf->bf_m = m0; 3418 1.32.2.2 skrll bf->bf_node = ni; /* NB: held reference */ 3419 1.32.2.2 skrll 3420 1.32.2.2 skrll /* setup descriptors */ 3421 1.32.2.2 skrll ds = bf->bf_desc; 3422 1.32.2.2 skrll rt = sc->sc_currates; 3423 1.32.2.2 skrll KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3424 1.32.2.2 skrll 3425 1.32.2.2 skrll /* 3426 1.32.2.11 skrll * NB: the 802.11 layer marks whether or not we should 3427 1.32.2.11 skrll * use short preamble based on the current mode and 3428 1.32.2.11 skrll * negotiated parameters. 3429 1.32.2.11 skrll */ 3430 1.32.2.11 skrll if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3431 1.32.2.11 skrll (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3432 1.32.2.11 skrll shortPreamble = AH_TRUE; 3433 1.32.2.11 skrll sc->sc_stats.ast_tx_shortpre++; 3434 1.32.2.11 skrll } else { 3435 1.32.2.11 skrll shortPreamble = AH_FALSE; 3436 1.32.2.11 skrll } 3437 1.32.2.11 skrll 3438 1.32.2.11 skrll an = ATH_NODE(ni); 3439 1.32.2.11 skrll flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3440 1.32.2.11 skrll /* 3441 1.32.2.11 skrll * Calculate Atheros packet type from IEEE80211 packet header, 3442 1.32.2.11 skrll * setup for rate calculations, and select h/w transmit queue. 3443 1.32.2.2 skrll */ 3444 1.32.2.2 skrll switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3445 1.32.2.2 skrll case IEEE80211_FC0_TYPE_MGT: 3446 1.32.2.2 skrll subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3447 1.32.2.2 skrll if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3448 1.32.2.2 skrll atype = HAL_PKT_TYPE_BEACON; 3449 1.32.2.2 skrll else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3450 1.32.2.2 skrll atype = HAL_PKT_TYPE_PROBE_RESP; 3451 1.32.2.2 skrll else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3452 1.32.2.2 skrll atype = HAL_PKT_TYPE_ATIM; 3453 1.32.2.11 skrll else 3454 1.32.2.11 skrll atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3455 1.32.2.2 skrll rix = 0; /* XXX lowest rate */ 3456 1.32.2.11 skrll try0 = ATH_TXMAXTRY; 3457 1.32.2.11 skrll if (shortPreamble) 3458 1.32.2.11 skrll txrate = an->an_tx_mgtratesp; 3459 1.32.2.11 skrll else 3460 1.32.2.11 skrll txrate = an->an_tx_mgtrate; 3461 1.32.2.11 skrll /* NB: force all management frames to highest queue */ 3462 1.32.2.11 skrll if (ni->ni_flags & IEEE80211_NODE_QOS) { 3463 1.32.2.11 skrll /* NB: force all management frames to highest queue */ 3464 1.32.2.11 skrll pri = WME_AC_VO; 3465 1.32.2.11 skrll } else 3466 1.32.2.11 skrll pri = WME_AC_BE; 3467 1.32.2.11 skrll flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3468 1.32.2.2 skrll break; 3469 1.32.2.2 skrll case IEEE80211_FC0_TYPE_CTL: 3470 1.32.2.11 skrll atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3471 1.32.2.2 skrll rix = 0; /* XXX lowest rate */ 3472 1.32.2.11 skrll try0 = ATH_TXMAXTRY; 3473 1.32.2.11 skrll if (shortPreamble) 3474 1.32.2.11 skrll txrate = an->an_tx_mgtratesp; 3475 1.32.2.11 skrll else 3476 1.32.2.11 skrll txrate = an->an_tx_mgtrate; 3477 1.32.2.11 skrll /* NB: force all ctl frames to highest queue */ 3478 1.32.2.11 skrll if (ni->ni_flags & IEEE80211_NODE_QOS) { 3479 1.32.2.11 skrll /* NB: force all ctl frames to highest queue */ 3480 1.32.2.11 skrll pri = WME_AC_VO; 3481 1.32.2.11 skrll } else 3482 1.32.2.11 skrll pri = WME_AC_BE; 3483 1.32.2.11 skrll flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3484 1.32.2.2 skrll break; 3485 1.32.2.11 skrll case IEEE80211_FC0_TYPE_DATA: 3486 1.32.2.11 skrll atype = HAL_PKT_TYPE_NORMAL; /* default */ 3487 1.32.2.11 skrll /* 3488 1.32.2.11 skrll * Data frames; consult the rate control module for 3489 1.32.2.11 skrll * unicast frames. Send multicast frames at the 3490 1.32.2.11 skrll * lowest rate. 3491 1.32.2.11 skrll */ 3492 1.32.2.11 skrll if (!ismcast) { 3493 1.32.2.11 skrll ath_rate_findrate(sc, an, shortPreamble, pktlen, 3494 1.32.2.11 skrll &rix, &try0, &txrate); 3495 1.32.2.11 skrll } else { 3496 1.32.2.11 skrll rix = 0; 3497 1.32.2.11 skrll try0 = ATH_TXMAXTRY; 3498 1.32.2.11 skrll txrate = an->an_tx_mgtrate; 3499 1.32.2.2 skrll } 3500 1.32.2.11 skrll sc->sc_txrate = txrate; /* for LED blinking */ 3501 1.32.2.11 skrll /* 3502 1.32.2.11 skrll * Default all non-QoS traffic to the background queue. 3503 1.32.2.11 skrll */ 3504 1.32.2.11 skrll if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3505 1.32.2.11 skrll pri = M_WME_GETAC(m0); 3506 1.32.2.11 skrll if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3507 1.32.2.11 skrll flags |= HAL_TXDESC_NOACK; 3508 1.32.2.11 skrll sc->sc_stats.ast_tx_noack++; 3509 1.32.2.11 skrll } 3510 1.32.2.11 skrll } else 3511 1.32.2.11 skrll pri = WME_AC_BE; 3512 1.32.2.2 skrll break; 3513 1.32.2.11 skrll default: 3514 1.32.2.11 skrll if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3515 1.32.2.11 skrll wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3516 1.32.2.11 skrll /* XXX statistic */ 3517 1.32.2.11 skrll m_freem(m0); 3518 1.32.2.11 skrll return EIO; 3519 1.32.2.2 skrll } 3520 1.32.2.11 skrll txq = sc->sc_ac2q[pri]; 3521 1.32.2.11 skrll 3522 1.32.2.2 skrll /* 3523 1.32.2.11 skrll * When servicing one or more stations in power-save mode 3524 1.32.2.11 skrll * multicast frames must be buffered until after the beacon. 3525 1.32.2.11 skrll * We use the CAB queue for that. 3526 1.32.2.2 skrll */ 3527 1.32.2.11 skrll if (ismcast && ic->ic_ps_sta) { 3528 1.32.2.11 skrll txq = sc->sc_cabq; 3529 1.32.2.11 skrll /* XXX? more bit in 802.11 frame header */ 3530 1.32.2.2 skrll } 3531 1.32.2.2 skrll 3532 1.32.2.2 skrll /* 3533 1.32.2.2 skrll * Calculate miscellaneous flags. 3534 1.32.2.2 skrll */ 3535 1.32.2.11 skrll if (ismcast) { 3536 1.32.2.2 skrll flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3537 1.32.2.2 skrll sc->sc_stats.ast_tx_noack++; 3538 1.32.2.2 skrll } else if (pktlen > ic->ic_rtsthreshold) { 3539 1.32.2.2 skrll flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3540 1.32.2.11 skrll cix = rt->info[rix].controlRate; 3541 1.32.2.2 skrll sc->sc_stats.ast_tx_rts++; 3542 1.32.2.2 skrll } 3543 1.32.2.2 skrll 3544 1.32.2.2 skrll /* 3545 1.32.2.11 skrll * If 802.11g protection is enabled, determine whether 3546 1.32.2.11 skrll * to use RTS/CTS or just CTS. Note that this is only 3547 1.32.2.11 skrll * done for OFDM unicast frames. 3548 1.32.2.11 skrll */ 3549 1.32.2.11 skrll if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3550 1.32.2.11 skrll rt->info[rix].phy == IEEE80211_T_OFDM && 3551 1.32.2.11 skrll (flags & HAL_TXDESC_NOACK) == 0) { 3552 1.32.2.11 skrll /* XXX fragments must use CCK rates w/ protection */ 3553 1.32.2.11 skrll if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3554 1.32.2.11 skrll flags |= HAL_TXDESC_RTSENA; 3555 1.32.2.11 skrll else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3556 1.32.2.11 skrll flags |= HAL_TXDESC_CTSENA; 3557 1.32.2.11 skrll cix = rt->info[sc->sc_protrix].controlRate; 3558 1.32.2.11 skrll sc->sc_stats.ast_tx_protect++; 3559 1.32.2.11 skrll } 3560 1.32.2.11 skrll 3561 1.32.2.11 skrll /* 3562 1.32.2.2 skrll * Calculate duration. This logically belongs in the 802.11 3563 1.32.2.2 skrll * layer but it lacks sufficient information to calculate it. 3564 1.32.2.2 skrll */ 3565 1.32.2.2 skrll if ((flags & HAL_TXDESC_NOACK) == 0 && 3566 1.32.2.2 skrll (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3567 1.32.2.2 skrll u_int16_t dur; 3568 1.32.2.2 skrll /* 3569 1.32.2.2 skrll * XXX not right with fragmentation. 3570 1.32.2.2 skrll */ 3571 1.32.2.11 skrll if (shortPreamble) 3572 1.32.2.11 skrll dur = rt->info[rix].spAckDuration; 3573 1.32.2.11 skrll else 3574 1.32.2.11 skrll dur = rt->info[rix].lpAckDuration; 3575 1.32.2.11 skrll *(u_int16_t *)wh->i_dur = htole16(dur); 3576 1.32.2.2 skrll } 3577 1.32.2.2 skrll 3578 1.32.2.2 skrll /* 3579 1.32.2.2 skrll * Calculate RTS/CTS rate and duration if needed. 3580 1.32.2.2 skrll */ 3581 1.32.2.2 skrll ctsduration = 0; 3582 1.32.2.2 skrll if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3583 1.32.2.2 skrll /* 3584 1.32.2.2 skrll * CTS transmit rate is derived from the transmit rate 3585 1.32.2.2 skrll * by looking in the h/w rate table. We must also factor 3586 1.32.2.2 skrll * in whether or not a short preamble is to be used. 3587 1.32.2.2 skrll */ 3588 1.32.2.11 skrll /* NB: cix is set above where RTS/CTS is enabled */ 3589 1.32.2.11 skrll KASSERT(cix != 0xff, ("cix not setup")); 3590 1.32.2.2 skrll ctsrate = rt->info[cix].rateCode; 3591 1.32.2.2 skrll /* 3592 1.32.2.11 skrll * Compute the transmit duration based on the frame 3593 1.32.2.11 skrll * size and the size of an ACK frame. We call into the 3594 1.32.2.11 skrll * HAL to do the computation since it depends on the 3595 1.32.2.11 skrll * characteristics of the actual PHY being used. 3596 1.32.2.11 skrll * 3597 1.32.2.11 skrll * NB: CTS is assumed the same size as an ACK so we can 3598 1.32.2.11 skrll * use the precalculated ACK durations. 3599 1.32.2.2 skrll */ 3600 1.32.2.11 skrll if (shortPreamble) { 3601 1.32.2.11 skrll ctsrate |= rt->info[cix].shortPreamble; 3602 1.32.2.11 skrll if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3603 1.32.2.11 skrll ctsduration += rt->info[cix].spAckDuration; 3604 1.32.2.2 skrll ctsduration += ath_hal_computetxtime(ah, 3605 1.32.2.11 skrll rt, pktlen, rix, AH_TRUE); 3606 1.32.2.11 skrll if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3607 1.32.2.12 christos ctsduration += rt->info[rix].spAckDuration; 3608 1.32.2.11 skrll } else { 3609 1.32.2.11 skrll if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3610 1.32.2.11 skrll ctsduration += rt->info[cix].lpAckDuration; 3611 1.32.2.2 skrll ctsduration += ath_hal_computetxtime(ah, 3612 1.32.2.11 skrll rt, pktlen, rix, AH_FALSE); 3613 1.32.2.11 skrll if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3614 1.32.2.12 christos ctsduration += rt->info[rix].lpAckDuration; 3615 1.32.2.2 skrll } 3616 1.32.2.11 skrll /* 3617 1.32.2.11 skrll * Must disable multi-rate retry when using RTS/CTS. 3618 1.32.2.11 skrll */ 3619 1.32.2.11 skrll try0 = ATH_TXMAXTRY; 3620 1.32.2.2 skrll } else 3621 1.32.2.2 skrll ctsrate = 0; 3622 1.32.2.2 skrll 3623 1.32.2.11 skrll if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3624 1.32.2.11 skrll ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3625 1.32.2.11 skrll sc->sc_hwmap[txrate].ieeerate, -1); 3626 1.32.2.12 christos #if NBPFILTER > 0 3627 1.32.2.2 skrll if (ic->ic_rawbpf) 3628 1.32.2.2 skrll bpf_mtap(ic->ic_rawbpf, m0); 3629 1.32.2.2 skrll if (sc->sc_drvbpf) { 3630 1.32.2.11 skrll sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3631 1.32.2.2 skrll if (iswep) 3632 1.32.2.2 skrll sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3633 1.32.2.11 skrll sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3634 1.32.2.11 skrll sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3635 1.32.2.11 skrll sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3636 1.32.2.2 skrll 3637 1.32.2.2 skrll bpf_mtap2(sc->sc_drvbpf, 3638 1.32.2.2 skrll &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3639 1.32.2.2 skrll } 3640 1.32.2.12 christos #endif 3641 1.32.2.2 skrll 3642 1.32.2.11 skrll /* 3643 1.32.2.11 skrll * Determine if a tx interrupt should be generated for 3644 1.32.2.11 skrll * this descriptor. We take a tx interrupt to reap 3645 1.32.2.11 skrll * descriptors when the h/w hits an EOL condition or 3646 1.32.2.11 skrll * when the descriptor is specifically marked to generate 3647 1.32.2.11 skrll * an interrupt. We periodically mark descriptors in this 3648 1.32.2.11 skrll * way to insure timely replenishing of the supply needed 3649 1.32.2.11 skrll * for sending frames. Defering interrupts reduces system 3650 1.32.2.11 skrll * load and potentially allows more concurrent work to be 3651 1.32.2.11 skrll * done but if done to aggressively can cause senders to 3652 1.32.2.11 skrll * backup. 3653 1.32.2.11 skrll * 3654 1.32.2.11 skrll * NB: use >= to deal with sc_txintrperiod changing 3655 1.32.2.11 skrll * dynamically through sysctl. 3656 1.32.2.11 skrll */ 3657 1.32.2.11 skrll if (flags & HAL_TXDESC_INTREQ) { 3658 1.32.2.11 skrll txq->axq_intrcnt = 0; 3659 1.32.2.11 skrll } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3660 1.32.2.11 skrll flags |= HAL_TXDESC_INTREQ; 3661 1.32.2.11 skrll txq->axq_intrcnt = 0; 3662 1.32.2.11 skrll } 3663 1.32.2.11 skrll 3664 1.32.2.2 skrll /* 3665 1.32.2.2 skrll * Formulate first tx descriptor with tx controls. 3666 1.32.2.2 skrll */ 3667 1.32.2.2 skrll /* XXX check return value? */ 3668 1.32.2.2 skrll ath_hal_setuptxdesc(ah, ds 3669 1.32.2.2 skrll , pktlen /* packet length */ 3670 1.32.2.2 skrll , hdrlen /* header length */ 3671 1.32.2.2 skrll , atype /* Atheros packet type */ 3672 1.32.2.11 skrll , ni->ni_txpower /* txpower */ 3673 1.32.2.11 skrll , txrate, try0 /* series 0 rate/tries */ 3674 1.32.2.11 skrll , keyix /* key cache index */ 3675 1.32.2.11 skrll , sc->sc_txantenna /* antenna mode */ 3676 1.32.2.2 skrll , flags /* flags */ 3677 1.32.2.2 skrll , ctsrate /* rts/cts rate */ 3678 1.32.2.2 skrll , ctsduration /* rts/cts duration */ 3679 1.32.2.2 skrll ); 3680 1.32.2.11 skrll bf->bf_flags = flags; 3681 1.32.2.11 skrll /* 3682 1.32.2.11 skrll * Setup the multi-rate retry state only when we're 3683 1.32.2.11 skrll * going to use it. This assumes ath_hal_setuptxdesc 3684 1.32.2.11 skrll * initializes the descriptors (so we don't have to) 3685 1.32.2.11 skrll * when the hardware supports multi-rate retry and 3686 1.32.2.11 skrll * we don't use it. 3687 1.32.2.11 skrll */ 3688 1.32.2.11 skrll if (try0 != ATH_TXMAXTRY) 3689 1.32.2.11 skrll ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3690 1.32.2.11 skrll 3691 1.32.2.2 skrll /* 3692 1.32.2.2 skrll * Fillin the remainder of the descriptor info. 3693 1.32.2.2 skrll */ 3694 1.32.2.11 skrll ds0 = ds; 3695 1.32.2.2 skrll for (i = 0; i < bf->bf_nseg; i++, ds++) { 3696 1.32.2.2 skrll ds->ds_data = bf->bf_segs[i].ds_addr; 3697 1.32.2.2 skrll if (i == bf->bf_nseg - 1) 3698 1.32.2.2 skrll ds->ds_link = 0; 3699 1.32.2.2 skrll else 3700 1.32.2.2 skrll ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3701 1.32.2.2 skrll ath_hal_filltxdesc(ah, ds 3702 1.32.2.2 skrll , bf->bf_segs[i].ds_len /* segment length */ 3703 1.32.2.2 skrll , i == 0 /* first segment */ 3704 1.32.2.2 skrll , i == bf->bf_nseg - 1 /* last segment */ 3705 1.32.2.11 skrll , ds0 /* first descriptor */ 3706 1.32.2.2 skrll ); 3707 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_XMIT, 3708 1.32.2.11 skrll "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3709 1.32.2.2 skrll __func__, i, ds->ds_link, ds->ds_data, 3710 1.32.2.11 skrll ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3711 1.32.2.2 skrll } 3712 1.32.2.2 skrll /* 3713 1.32.2.2 skrll * Insert the frame on the outbound list and 3714 1.32.2.2 skrll * pass it on to the hardware. 3715 1.32.2.2 skrll */ 3716 1.32.2.11 skrll ATH_TXQ_LOCK(txq); 3717 1.32.2.11 skrll if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 3718 1.32.2.11 skrll u_int32_t txopLimit = IEEE80211_TXOP_TO_US( 3719 1.32.2.11 skrll cap->cap_wmeParams[pri].wmep_txopLimit); 3720 1.32.2.11 skrll /* 3721 1.32.2.11 skrll * When bursting, potentially extend the CTS duration 3722 1.32.2.11 skrll * of a previously queued frame to cover this frame 3723 1.32.2.11 skrll * and not exceed the txopLimit. If that can be done 3724 1.32.2.11 skrll * then disable RTS/CTS on this frame since it's now 3725 1.32.2.11 skrll * covered (burst extension). Otherwise we must terminate 3726 1.32.2.11 skrll * the burst before this frame goes out so as not to 3727 1.32.2.11 skrll * violate the WME parameters. All this is complicated 3728 1.32.2.11 skrll * as we need to update the state of packets on the 3729 1.32.2.11 skrll * (live) hardware queue. The logic is buried in the hal 3730 1.32.2.11 skrll * because it's highly chip-specific. 3731 1.32.2.11 skrll */ 3732 1.32.2.11 skrll if (txopLimit != 0) { 3733 1.32.2.11 skrll sc->sc_stats.ast_tx_ctsburst++; 3734 1.32.2.11 skrll if (updateCTSForBursting(ah, ds0, txq) == 0) { 3735 1.32.2.11 skrll /* 3736 1.32.2.11 skrll * This frame was not covered by RTS/CTS from 3737 1.32.2.11 skrll * the previous frame in the burst; update the 3738 1.32.2.11 skrll * descriptor pointers so this frame is now 3739 1.32.2.11 skrll * treated as the last frame for extending a 3740 1.32.2.11 skrll * burst. 3741 1.32.2.11 skrll */ 3742 1.32.2.11 skrll txq->axq_lastdsWithCTS = ds0; 3743 1.32.2.11 skrll /* set gating Desc to final desc */ 3744 1.32.2.11 skrll txq->axq_gatingds = 3745 1.32.2.11 skrll (struct ath_desc *)txq->axq_link; 3746 1.32.2.11 skrll } else 3747 1.32.2.11 skrll sc->sc_stats.ast_tx_ctsext++; 3748 1.32.2.11 skrll } 3749 1.32.2.11 skrll } 3750 1.32.2.11 skrll ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3751 1.32.2.11 skrll if (txq->axq_link == NULL) { 3752 1.32.2.11 skrll ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3753 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_XMIT, 3754 1.32.2.11 skrll "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3755 1.32.2.11 skrll txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3756 1.32.2.11 skrll txq->axq_depth); 3757 1.32.2.2 skrll } else { 3758 1.32.2.11 skrll *txq->axq_link = bf->bf_daddr; 3759 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_XMIT, 3760 1.32.2.11 skrll "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3761 1.32.2.11 skrll txq->axq_qnum, txq->axq_link, 3762 1.32.2.11 skrll (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3763 1.32.2.2 skrll } 3764 1.32.2.11 skrll txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3765 1.32.2.11 skrll /* 3766 1.32.2.11 skrll * The CAB queue is started from the SWBA handler since 3767 1.32.2.11 skrll * frames only go out on DTIM and to avoid possible races. 3768 1.32.2.11 skrll */ 3769 1.32.2.11 skrll if (txq != sc->sc_cabq) 3770 1.32.2.11 skrll ath_hal_txstart(ah, txq->axq_qnum); 3771 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3772 1.32.2.2 skrll 3773 1.32.2.2 skrll return 0; 3774 1.32.2.11 skrll #undef updateCTSForBursting 3775 1.32.2.11 skrll #undef CTS_DURATION 3776 1.32.2.2 skrll } 3777 1.32.2.2 skrll 3778 1.32.2.11 skrll /* 3779 1.32.2.11 skrll * Process completed xmit descriptors from the specified queue. 3780 1.32.2.11 skrll */ 3781 1.32.2.2 skrll static void 3782 1.32.2.11 skrll ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3783 1.32.2.2 skrll { 3784 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 3785 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3786 1.32.2.11 skrll struct ath_buf *bf; 3787 1.32.2.11 skrll struct ath_desc *ds, *ds0; 3788 1.32.2.2 skrll struct ieee80211_node *ni; 3789 1.32.2.2 skrll struct ath_node *an; 3790 1.32.2.11 skrll int sr, lr, pri; 3791 1.32.2.2 skrll HAL_STATUS status; 3792 1.32.2.2 skrll 3793 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3794 1.32.2.11 skrll __func__, txq->axq_qnum, 3795 1.32.2.11 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3796 1.32.2.11 skrll txq->axq_link); 3797 1.32.2.2 skrll for (;;) { 3798 1.32.2.11 skrll ATH_TXQ_LOCK(txq); 3799 1.32.2.11 skrll txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3800 1.32.2.11 skrll bf = STAILQ_FIRST(&txq->axq_q); 3801 1.32.2.2 skrll if (bf == NULL) { 3802 1.32.2.11 skrll txq->axq_link = NULL; 3803 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3804 1.32.2.2 skrll break; 3805 1.32.2.2 skrll } 3806 1.32.2.11 skrll ds0 = &bf->bf_desc[0]; 3807 1.32.2.2 skrll ds = &bf->bf_desc[bf->bf_nseg - 1]; 3808 1.32.2.2 skrll status = ath_hal_txprocdesc(ah, ds); 3809 1.32.2.2 skrll #ifdef AR_DEBUG 3810 1.32.2.11 skrll if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3811 1.32.2.2 skrll ath_printtxbuf(bf, status == HAL_OK); 3812 1.32.2.2 skrll #endif 3813 1.32.2.2 skrll if (status == HAL_EINPROGRESS) { 3814 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3815 1.32.2.2 skrll break; 3816 1.32.2.2 skrll } 3817 1.32.2.11 skrll if (ds0 == txq->axq_lastdsWithCTS) 3818 1.32.2.11 skrll txq->axq_lastdsWithCTS = NULL; 3819 1.32.2.11 skrll if (ds == txq->axq_gatingds) 3820 1.32.2.11 skrll txq->axq_gatingds = NULL; 3821 1.32.2.11 skrll ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3822 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3823 1.32.2.2 skrll 3824 1.32.2.2 skrll ni = bf->bf_node; 3825 1.32.2.2 skrll if (ni != NULL) { 3826 1.32.2.11 skrll an = ATH_NODE(ni); 3827 1.32.2.2 skrll if (ds->ds_txstat.ts_status == 0) { 3828 1.32.2.11 skrll u_int8_t txant = ds->ds_txstat.ts_antenna; 3829 1.32.2.11 skrll sc->sc_stats.ast_ant_tx[txant]++; 3830 1.32.2.11 skrll sc->sc_ant_tx[txant]++; 3831 1.32.2.11 skrll if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3832 1.32.2.11 skrll sc->sc_stats.ast_tx_altrate++; 3833 1.32.2.11 skrll sc->sc_stats.ast_tx_rssi = 3834 1.32.2.11 skrll ds->ds_txstat.ts_rssi; 3835 1.32.2.11 skrll ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3836 1.32.2.11 skrll ds->ds_txstat.ts_rssi); 3837 1.32.2.11 skrll pri = M_WME_GETAC(bf->bf_m); 3838 1.32.2.11 skrll if (pri >= WME_AC_VO) 3839 1.32.2.11 skrll ic->ic_wme.wme_hipri_traffic++; 3840 1.32.2.11 skrll ni->ni_inact = ni->ni_inact_reload; 3841 1.32.2.2 skrll } else { 3842 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3843 1.32.2.2 skrll sc->sc_stats.ast_tx_xretries++; 3844 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3845 1.32.2.2 skrll sc->sc_stats.ast_tx_fifoerr++; 3846 1.32.2.2 skrll if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3847 1.32.2.2 skrll sc->sc_stats.ast_tx_filtered++; 3848 1.32.2.2 skrll } 3849 1.32.2.2 skrll sr = ds->ds_txstat.ts_shortretry; 3850 1.32.2.2 skrll lr = ds->ds_txstat.ts_longretry; 3851 1.32.2.2 skrll sc->sc_stats.ast_tx_shortretry += sr; 3852 1.32.2.2 skrll sc->sc_stats.ast_tx_longretry += lr; 3853 1.32.2.11 skrll /* 3854 1.32.2.11 skrll * Hand the descriptor to the rate control algorithm. 3855 1.32.2.11 skrll */ 3856 1.32.2.11 skrll if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3857 1.32.2.11 skrll (bf->bf_flags & HAL_TXDESC_NOACK) == 0) 3858 1.32.2.11 skrll ath_rate_tx_complete(sc, an, ds, ds0); 3859 1.32.2.2 skrll /* 3860 1.32.2.2 skrll * Reclaim reference to node. 3861 1.32.2.2 skrll * 3862 1.32.2.2 skrll * NB: the node may be reclaimed here if, for example 3863 1.32.2.2 skrll * this is a DEAUTH message that was sent and the 3864 1.32.2.2 skrll * node was timed out due to inactivity. 3865 1.32.2.2 skrll */ 3866 1.32.2.11 skrll ieee80211_free_node(ni); 3867 1.32.2.2 skrll } 3868 1.32.2.11 skrll bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3869 1.32.2.11 skrll bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3870 1.32.2.2 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3871 1.32.2.2 skrll m_freem(bf->bf_m); 3872 1.32.2.2 skrll bf->bf_m = NULL; 3873 1.32.2.2 skrll bf->bf_node = NULL; 3874 1.32.2.2 skrll 3875 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 3876 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3877 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 3878 1.32.2.2 skrll } 3879 1.32.2.2 skrll } 3880 1.32.2.2 skrll 3881 1.32.2.2 skrll /* 3882 1.32.2.11 skrll * Deferred processing of transmit interrupt; special-cased 3883 1.32.2.11 skrll * for a single hardware transmit queue (e.g. 5210 and 5211). 3884 1.32.2.2 skrll */ 3885 1.32.2.2 skrll static void 3886 1.32.2.11 skrll ath_tx_proc_q0(void *arg, int npending) 3887 1.32.2.2 skrll { 3888 1.32.2.11 skrll struct ath_softc *sc = arg; 3889 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 3890 1.32.2.2 skrll 3891 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[0]); 3892 1.32.2.11 skrll ath_tx_processq(sc, sc->sc_cabq); 3893 1.32.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 3894 1.32.2.2 skrll sc->sc_tx_timer = 0; 3895 1.32.2.11 skrll 3896 1.32.2.11 skrll if (sc->sc_softled) 3897 1.32.2.11 skrll ath_led_event(sc, ATH_LED_TX); 3898 1.32.2.11 skrll 3899 1.32.2.11 skrll ath_start(ifp); 3900 1.32.2.2 skrll } 3901 1.32.2.2 skrll 3902 1.32.2.2 skrll /* 3903 1.32.2.11 skrll * Deferred processing of transmit interrupt; special-cased 3904 1.32.2.11 skrll * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3905 1.32.2.2 skrll */ 3906 1.32.2.2 skrll static void 3907 1.32.2.11 skrll ath_tx_proc_q0123(void *arg, int npending) 3908 1.32.2.2 skrll { 3909 1.32.2.11 skrll struct ath_softc *sc = arg; 3910 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 3911 1.32.2.11 skrll 3912 1.32.2.11 skrll /* 3913 1.32.2.11 skrll * Process each active queue. 3914 1.32.2.11 skrll */ 3915 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[0]); 3916 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[1]); 3917 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[2]); 3918 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[3]); 3919 1.32.2.11 skrll ath_tx_processq(sc, sc->sc_cabq); 3920 1.32.2.11 skrll 3921 1.32.2.11 skrll ifp->if_flags &= ~IFF_OACTIVE; 3922 1.32.2.11 skrll sc->sc_tx_timer = 0; 3923 1.32.2.11 skrll 3924 1.32.2.11 skrll if (sc->sc_softled) 3925 1.32.2.11 skrll ath_led_event(sc, ATH_LED_TX); 3926 1.32.2.11 skrll 3927 1.32.2.11 skrll ath_start(ifp); 3928 1.32.2.11 skrll } 3929 1.32.2.11 skrll 3930 1.32.2.11 skrll /* 3931 1.32.2.11 skrll * Deferred processing of transmit interrupt. 3932 1.32.2.11 skrll */ 3933 1.32.2.11 skrll static void 3934 1.32.2.11 skrll ath_tx_proc(void *arg, int npending) 3935 1.32.2.11 skrll { 3936 1.32.2.11 skrll struct ath_softc *sc = arg; 3937 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 3938 1.32.2.11 skrll int i; 3939 1.32.2.11 skrll 3940 1.32.2.11 skrll /* 3941 1.32.2.11 skrll * Process each active queue. 3942 1.32.2.11 skrll */ 3943 1.32.2.11 skrll /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3944 1.32.2.11 skrll for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3945 1.32.2.11 skrll if (ATH_TXQ_SETUP(sc, i)) 3946 1.32.2.11 skrll ath_tx_processq(sc, &sc->sc_txq[i]); 3947 1.32.2.11 skrll 3948 1.32.2.11 skrll ifp->if_flags &= ~IFF_OACTIVE; 3949 1.32.2.11 skrll sc->sc_tx_timer = 0; 3950 1.32.2.11 skrll 3951 1.32.2.11 skrll if (sc->sc_softled) 3952 1.32.2.11 skrll ath_led_event(sc, ATH_LED_TX); 3953 1.32.2.11 skrll 3954 1.32.2.11 skrll ath_start(ifp); 3955 1.32.2.11 skrll } 3956 1.32.2.11 skrll 3957 1.32.2.11 skrll static void 3958 1.32.2.11 skrll ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3959 1.32.2.11 skrll { 3960 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 3961 1.32.2.11 skrll struct ieee80211_node *ni; 3962 1.32.2.11 skrll struct ath_buf *bf; 3963 1.32.2.11 skrll 3964 1.32.2.11 skrll /* 3965 1.32.2.11 skrll * NB: this assumes output has been stopped and 3966 1.32.2.11 skrll * we do not need to block ath_tx_tasklet 3967 1.32.2.11 skrll */ 3968 1.32.2.11 skrll for (;;) { 3969 1.32.2.11 skrll ATH_TXQ_LOCK(txq); 3970 1.32.2.11 skrll bf = STAILQ_FIRST(&txq->axq_q); 3971 1.32.2.11 skrll if (bf == NULL) { 3972 1.32.2.11 skrll txq->axq_link = NULL; 3973 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3974 1.32.2.11 skrll break; 3975 1.32.2.11 skrll } 3976 1.32.2.11 skrll ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3977 1.32.2.11 skrll ATH_TXQ_UNLOCK(txq); 3978 1.32.2.11 skrll #ifdef AR_DEBUG 3979 1.32.2.11 skrll if (sc->sc_debug & ATH_DEBUG_RESET) 3980 1.32.2.11 skrll ath_printtxbuf(bf, 3981 1.32.2.11 skrll ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3982 1.32.2.11 skrll #endif /* AR_DEBUG */ 3983 1.32.2.11 skrll bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3984 1.32.2.11 skrll m_freem(bf->bf_m); 3985 1.32.2.11 skrll bf->bf_m = NULL; 3986 1.32.2.11 skrll ni = bf->bf_node; 3987 1.32.2.11 skrll bf->bf_node = NULL; 3988 1.32.2.11 skrll if (ni != NULL) { 3989 1.32.2.11 skrll /* 3990 1.32.2.11 skrll * Reclaim node reference. 3991 1.32.2.11 skrll */ 3992 1.32.2.11 skrll ieee80211_free_node(ni); 3993 1.32.2.11 skrll } 3994 1.32.2.11 skrll ATH_TXBUF_LOCK(sc); 3995 1.32.2.11 skrll STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3996 1.32.2.11 skrll ATH_TXBUF_UNLOCK(sc); 3997 1.32.2.11 skrll } 3998 1.32.2.11 skrll } 3999 1.32.2.11 skrll 4000 1.32.2.11 skrll static void 4001 1.32.2.11 skrll ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4002 1.32.2.11 skrll { 4003 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4004 1.32.2.11 skrll 4005 1.32.2.11 skrll (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4006 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4007 1.32.2.11 skrll __func__, txq->axq_qnum, 4008 1.32.2.11 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4009 1.32.2.11 skrll txq->axq_link); 4010 1.32.2.11 skrll } 4011 1.32.2.11 skrll 4012 1.32.2.11 skrll /* 4013 1.32.2.11 skrll * Drain the transmit queues and reclaim resources. 4014 1.32.2.11 skrll */ 4015 1.32.2.11 skrll static void 4016 1.32.2.11 skrll ath_draintxq(struct ath_softc *sc) 4017 1.32.2.11 skrll { 4018 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4019 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 4020 1.32.2.11 skrll int i; 4021 1.32.2.11 skrll 4022 1.32.2.11 skrll /* XXX return value */ 4023 1.32.2.11 skrll if (!sc->sc_invalid) { 4024 1.32.2.11 skrll /* don't touch the hardware if marked invalid */ 4025 1.32.2.11 skrll (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4026 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RESET, 4027 1.32.2.11 skrll "%s: beacon queue %p\n", __func__, 4028 1.32.2.11 skrll (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4029 1.32.2.11 skrll for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4030 1.32.2.11 skrll if (ATH_TXQ_SETUP(sc, i)) 4031 1.32.2.11 skrll ath_tx_stopdma(sc, &sc->sc_txq[i]); 4032 1.32.2.11 skrll } 4033 1.32.2.11 skrll for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4034 1.32.2.11 skrll if (ATH_TXQ_SETUP(sc, i)) 4035 1.32.2.11 skrll ath_tx_draintxq(sc, &sc->sc_txq[i]); 4036 1.32.2.11 skrll ifp->if_flags &= ~IFF_OACTIVE; 4037 1.32.2.11 skrll sc->sc_tx_timer = 0; 4038 1.32.2.11 skrll } 4039 1.32.2.11 skrll 4040 1.32.2.11 skrll /* 4041 1.32.2.11 skrll * Disable the receive h/w in preparation for a reset. 4042 1.32.2.11 skrll */ 4043 1.32.2.11 skrll static void 4044 1.32.2.11 skrll ath_stoprecv(struct ath_softc *sc) 4045 1.32.2.11 skrll { 4046 1.32.2.11 skrll #define PA2DESC(_sc, _pa) \ 4047 1.32.2.11 skrll ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4048 1.32.2.11 skrll ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4049 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4050 1.32.2.2 skrll 4051 1.32.2.2 skrll ath_hal_stoppcurecv(ah); /* disable PCU */ 4052 1.32.2.2 skrll ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4053 1.32.2.2 skrll ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4054 1.32.2.11 skrll DELAY(3000); /* 3ms is long enough for 1 frame */ 4055 1.32.2.2 skrll #ifdef AR_DEBUG 4056 1.32.2.11 skrll if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4057 1.32.2.2 skrll struct ath_buf *bf; 4058 1.32.2.2 skrll 4059 1.32.2.2 skrll printf("%s: rx queue %p, link %p\n", __func__, 4060 1.32.2.2 skrll (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4061 1.32.2.11 skrll STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4062 1.32.2.2 skrll struct ath_desc *ds = bf->bf_desc; 4063 1.32.2.11 skrll HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4064 1.32.2.11 skrll bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 4065 1.32.2.11 skrll if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4066 1.32.2.11 skrll ath_printrxbuf(bf, status == HAL_OK); 4067 1.32.2.2 skrll } 4068 1.32.2.2 skrll } 4069 1.32.2.2 skrll #endif 4070 1.32.2.2 skrll sc->sc_rxlink = NULL; /* just in case */ 4071 1.32.2.2 skrll #undef PA2DESC 4072 1.32.2.2 skrll } 4073 1.32.2.2 skrll 4074 1.32.2.2 skrll /* 4075 1.32.2.2 skrll * Enable the receive h/w following a reset. 4076 1.32.2.2 skrll */ 4077 1.32.2.2 skrll static int 4078 1.32.2.2 skrll ath_startrecv(struct ath_softc *sc) 4079 1.32.2.2 skrll { 4080 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4081 1.32.2.2 skrll struct ath_buf *bf; 4082 1.32.2.2 skrll 4083 1.32.2.2 skrll sc->sc_rxlink = NULL; 4084 1.32.2.11 skrll STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4085 1.32.2.2 skrll int error = ath_rxbuf_init(sc, bf); 4086 1.32.2.2 skrll if (error != 0) { 4087 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RECV, 4088 1.32.2.11 skrll "%s: ath_rxbuf_init failed %d\n", 4089 1.32.2.11 skrll __func__, error); 4090 1.32.2.2 skrll return error; 4091 1.32.2.2 skrll } 4092 1.32.2.2 skrll } 4093 1.32.2.2 skrll 4094 1.32.2.11 skrll bf = STAILQ_FIRST(&sc->sc_rxbuf); 4095 1.32.2.2 skrll ath_hal_putrxbuf(ah, bf->bf_daddr); 4096 1.32.2.2 skrll ath_hal_rxena(ah); /* enable recv descriptors */ 4097 1.32.2.2 skrll ath_mode_init(sc); /* set filters, etc. */ 4098 1.32.2.2 skrll ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4099 1.32.2.2 skrll return 0; 4100 1.32.2.2 skrll } 4101 1.32.2.2 skrll 4102 1.32.2.11 skrll /* 4103 1.32.2.11 skrll * Update internal state after a channel change. 4104 1.32.2.11 skrll */ 4105 1.32.2.11 skrll static void 4106 1.32.2.11 skrll ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4107 1.32.2.11 skrll { 4108 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 4109 1.32.2.11 skrll enum ieee80211_phymode mode; 4110 1.32.2.11 skrll u_int16_t flags; 4111 1.32.2.11 skrll 4112 1.32.2.11 skrll /* 4113 1.32.2.11 skrll * Change channels and update the h/w rate map 4114 1.32.2.11 skrll * if we're switching; e.g. 11a to 11b/g. 4115 1.32.2.11 skrll */ 4116 1.32.2.11 skrll mode = ieee80211_chan2mode(ic, chan); 4117 1.32.2.11 skrll if (mode != sc->sc_curmode) 4118 1.32.2.11 skrll ath_setcurmode(sc, mode); 4119 1.32.2.11 skrll /* 4120 1.32.2.11 skrll * Update BPF state. NB: ethereal et. al. don't handle 4121 1.32.2.11 skrll * merged flags well so pick a unique mode for their use. 4122 1.32.2.11 skrll */ 4123 1.32.2.11 skrll if (IEEE80211_IS_CHAN_A(chan)) 4124 1.32.2.11 skrll flags = IEEE80211_CHAN_A; 4125 1.32.2.11 skrll /* XXX 11g schizophrenia */ 4126 1.32.2.11 skrll else if (IEEE80211_IS_CHAN_G(chan) || 4127 1.32.2.11 skrll IEEE80211_IS_CHAN_PUREG(chan)) 4128 1.32.2.11 skrll flags = IEEE80211_CHAN_G; 4129 1.32.2.11 skrll else 4130 1.32.2.11 skrll flags = IEEE80211_CHAN_B; 4131 1.32.2.11 skrll if (IEEE80211_IS_CHAN_T(chan)) 4132 1.32.2.11 skrll flags |= IEEE80211_CHAN_TURBO; 4133 1.32.2.11 skrll sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4134 1.32.2.11 skrll htole16(chan->ic_freq); 4135 1.32.2.11 skrll sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4136 1.32.2.11 skrll htole16(flags); 4137 1.32.2.11 skrll } 4138 1.32.2.11 skrll 4139 1.32.2.2 skrll /* 4140 1.32.2.2 skrll * Set/change channels. If the channel is really being changed, 4141 1.32.2.11 skrll * it's done by reseting the chip. To accomplish this we must 4142 1.32.2.2 skrll * first cleanup any pending DMA, then restart stuff after a la 4143 1.32.2.2 skrll * ath_init. 4144 1.32.2.2 skrll */ 4145 1.32.2.2 skrll static int 4146 1.32.2.2 skrll ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4147 1.32.2.2 skrll { 4148 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4149 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 4150 1.32.2.11 skrll HAL_CHANNEL hchan; 4151 1.32.2.2 skrll 4152 1.32.2.11 skrll /* 4153 1.32.2.11 skrll * Convert to a HAL channel description with 4154 1.32.2.11 skrll * the flags constrained to reflect the current 4155 1.32.2.11 skrll * operating mode. 4156 1.32.2.11 skrll */ 4157 1.32.2.11 skrll hchan.channel = chan->ic_freq; 4158 1.32.2.11 skrll hchan.channelFlags = ath_chan2flags(ic, chan); 4159 1.32.2.11 skrll 4160 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 4161 1.32.2.11 skrll __func__, 4162 1.32.2.11 skrll ath_hal_mhz2ieee(sc->sc_curchan.channel, 4163 1.32.2.11 skrll sc->sc_curchan.channelFlags), 4164 1.32.2.11 skrll sc->sc_curchan.channel, 4165 1.32.2.11 skrll ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 4166 1.32.2.11 skrll if (hchan.channel != sc->sc_curchan.channel || 4167 1.32.2.11 skrll hchan.channelFlags != sc->sc_curchan.channelFlags) { 4168 1.32.2.2 skrll HAL_STATUS status; 4169 1.32.2.2 skrll 4170 1.32.2.2 skrll /* 4171 1.32.2.2 skrll * To switch channels clear any pending DMA operations; 4172 1.32.2.2 skrll * wait long enough for the RX fifo to drain, reset the 4173 1.32.2.2 skrll * hardware at the new frequency, and then re-enable 4174 1.32.2.2 skrll * the relevant bits of the h/w. 4175 1.32.2.2 skrll */ 4176 1.32.2.2 skrll ath_hal_intrset(ah, 0); /* disable interrupts */ 4177 1.32.2.2 skrll ath_draintxq(sc); /* clear pending tx frames */ 4178 1.32.2.2 skrll ath_stoprecv(sc); /* turn off frame recv */ 4179 1.32.2.2 skrll if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4180 1.32.2.11 skrll if_printf(&sc->sc_if, "ath_chan_set: unable to reset " 4181 1.32.2.2 skrll "channel %u (%u Mhz)\n", 4182 1.32.2.2 skrll ieee80211_chan2ieee(ic, chan), chan->ic_freq); 4183 1.32.2.2 skrll return EIO; 4184 1.32.2.2 skrll } 4185 1.32.2.11 skrll sc->sc_curchan = hchan; 4186 1.32.2.11 skrll ath_update_txpow(sc); /* update tx power state */ 4187 1.32.2.12 christos sc->sc_diversity = ath_hal_getdiversity(ah); 4188 1.32.2.11 skrll 4189 1.32.2.2 skrll /* 4190 1.32.2.2 skrll * Re-enable rx framework. 4191 1.32.2.2 skrll */ 4192 1.32.2.2 skrll if (ath_startrecv(sc) != 0) { 4193 1.32.2.11 skrll if_printf(&sc->sc_if, 4194 1.32.2.2 skrll "ath_chan_set: unable to restart recv logic\n"); 4195 1.32.2.2 skrll return EIO; 4196 1.32.2.2 skrll } 4197 1.32.2.2 skrll 4198 1.32.2.2 skrll /* 4199 1.32.2.2 skrll * Change channels and update the h/w rate map 4200 1.32.2.2 skrll * if we're switching; e.g. 11a to 11b/g. 4201 1.32.2.2 skrll */ 4202 1.32.2.2 skrll ic->ic_ibss_chan = chan; 4203 1.32.2.11 skrll ath_chan_change(sc, chan); 4204 1.32.2.2 skrll 4205 1.32.2.2 skrll /* 4206 1.32.2.2 skrll * Re-enable interrupts. 4207 1.32.2.2 skrll */ 4208 1.32.2.2 skrll ath_hal_intrset(ah, sc->sc_imask); 4209 1.32.2.2 skrll } 4210 1.32.2.2 skrll return 0; 4211 1.32.2.2 skrll } 4212 1.32.2.2 skrll 4213 1.32.2.2 skrll static void 4214 1.32.2.2 skrll ath_next_scan(void *arg) 4215 1.32.2.2 skrll { 4216 1.32.2.2 skrll struct ath_softc *sc = arg; 4217 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 4218 1.32.2.2 skrll int s; 4219 1.32.2.2 skrll 4220 1.32.2.2 skrll /* don't call ath_start w/o network interrupts blocked */ 4221 1.32.2.2 skrll s = splnet(); 4222 1.32.2.2 skrll 4223 1.32.2.2 skrll if (ic->ic_state == IEEE80211_S_SCAN) 4224 1.32.2.2 skrll ieee80211_next_scan(ic); 4225 1.32.2.2 skrll splx(s); 4226 1.32.2.2 skrll } 4227 1.32.2.2 skrll 4228 1.32.2.2 skrll /* 4229 1.32.2.2 skrll * Periodically recalibrate the PHY to account 4230 1.32.2.2 skrll * for temperature/environment changes. 4231 1.32.2.2 skrll */ 4232 1.32.2.2 skrll static void 4233 1.32.2.2 skrll ath_calibrate(void *arg) 4234 1.32.2.2 skrll { 4235 1.32.2.2 skrll struct ath_softc *sc = arg; 4236 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4237 1.32.2.2 skrll 4238 1.32.2.2 skrll sc->sc_stats.ast_per_cal++; 4239 1.32.2.2 skrll 4240 1.32.2.11 skrll ATH_LOCK(sc); 4241 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 4242 1.32.2.11 skrll __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 4243 1.32.2.2 skrll 4244 1.32.2.2 skrll if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4245 1.32.2.2 skrll /* 4246 1.32.2.2 skrll * Rfgain is out of bounds, reset the chip 4247 1.32.2.2 skrll * to load new gain values. 4248 1.32.2.2 skrll */ 4249 1.32.2.2 skrll sc->sc_stats.ast_per_rfgain++; 4250 1.32.2.11 skrll ath_reset(&sc->sc_if); 4251 1.32.2.2 skrll } 4252 1.32.2.11 skrll if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 4253 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 4254 1.32.2.11 skrll "%s: calibration of channel %u failed\n", 4255 1.32.2.11 skrll __func__, sc->sc_curchan.channel); 4256 1.32.2.2 skrll sc->sc_stats.ast_per_calfail++; 4257 1.32.2.2 skrll } 4258 1.32.2.11 skrll callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 4259 1.32.2.11 skrll ATH_UNLOCK(sc); 4260 1.32.2.2 skrll } 4261 1.32.2.2 skrll 4262 1.32.2.2 skrll static int 4263 1.32.2.2 skrll ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4264 1.32.2.2 skrll { 4265 1.32.2.11 skrll struct ifnet *ifp = ic->ic_ifp; 4266 1.32.2.2 skrll struct ath_softc *sc = ifp->if_softc; 4267 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4268 1.32.2.2 skrll struct ieee80211_node *ni; 4269 1.32.2.2 skrll int i, error; 4270 1.32.2.2 skrll const u_int8_t *bssid; 4271 1.32.2.2 skrll u_int32_t rfilt; 4272 1.32.2.11 skrll static const HAL_LED_STATE leds[] = { 4273 1.32.2.11 skrll HAL_LED_INIT, /* IEEE80211_S_INIT */ 4274 1.32.2.11 skrll HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4275 1.32.2.11 skrll HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4276 1.32.2.11 skrll HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4277 1.32.2.11 skrll HAL_LED_RUN, /* IEEE80211_S_RUN */ 4278 1.32.2.11 skrll }; 4279 1.32.2.2 skrll 4280 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4281 1.32.2.2 skrll ieee80211_state_name[ic->ic_state], 4282 1.32.2.11 skrll ieee80211_state_name[nstate]); 4283 1.32.2.2 skrll 4284 1.32.2.11 skrll callout_stop(&sc->sc_scan_ch); 4285 1.32.2.11 skrll callout_stop(&sc->sc_cal_ch); 4286 1.32.2.11 skrll ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4287 1.32.2.2 skrll 4288 1.32.2.2 skrll if (nstate == IEEE80211_S_INIT) { 4289 1.32.2.2 skrll sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4290 1.32.2.11 skrll /* 4291 1.32.2.11 skrll * NB: disable interrupts so we don't rx frames. 4292 1.32.2.11 skrll */ 4293 1.32.2.11 skrll ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4294 1.32.2.11 skrll /* 4295 1.32.2.11 skrll * Notify the rate control algorithm. 4296 1.32.2.11 skrll */ 4297 1.32.2.11 skrll ath_rate_newstate(sc, nstate); 4298 1.32.2.11 skrll goto done; 4299 1.32.2.2 skrll } 4300 1.32.2.2 skrll ni = ic->ic_bss; 4301 1.32.2.12 christos error = ath_chan_set(sc, ic->ic_curchan); 4302 1.32.2.2 skrll if (error != 0) 4303 1.32.2.2 skrll goto bad; 4304 1.32.2.11 skrll rfilt = ath_calcrxfilter(sc, nstate); 4305 1.32.2.11 skrll if (nstate == IEEE80211_S_SCAN) 4306 1.32.2.2 skrll bssid = ifp->if_broadcastaddr; 4307 1.32.2.11 skrll else 4308 1.32.2.2 skrll bssid = ni->ni_bssid; 4309 1.32.2.2 skrll ath_hal_setrxfilter(ah, rfilt); 4310 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4311 1.32.2.11 skrll __func__, rfilt, ether_sprintf(bssid)); 4312 1.32.2.2 skrll 4313 1.32.2.2 skrll if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4314 1.32.2.2 skrll ath_hal_setassocid(ah, bssid, ni->ni_associd); 4315 1.32.2.2 skrll else 4316 1.32.2.2 skrll ath_hal_setassocid(ah, bssid, 0); 4317 1.32.2.2 skrll if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4318 1.32.2.2 skrll for (i = 0; i < IEEE80211_WEP_NKID; i++) 4319 1.32.2.2 skrll if (ath_hal_keyisvalid(ah, i)) 4320 1.32.2.2 skrll ath_hal_keysetmac(ah, i, bssid); 4321 1.32.2.2 skrll } 4322 1.32.2.2 skrll 4323 1.32.2.11 skrll /* 4324 1.32.2.11 skrll * Notify the rate control algorithm so rates 4325 1.32.2.11 skrll * are setup should ath_beacon_alloc be called. 4326 1.32.2.11 skrll */ 4327 1.32.2.11 skrll ath_rate_newstate(sc, nstate); 4328 1.32.2.11 skrll 4329 1.32.2.11 skrll if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4330 1.32.2.11 skrll /* nothing to do */; 4331 1.32.2.11 skrll } else if (nstate == IEEE80211_S_RUN) { 4332 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_STATE, 4333 1.32.2.11 skrll "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4334 1.32.2.2 skrll "capinfo=0x%04x chan=%d\n" 4335 1.32.2.2 skrll , __func__ 4336 1.32.2.2 skrll , ic->ic_flags 4337 1.32.2.2 skrll , ni->ni_intval 4338 1.32.2.2 skrll , ether_sprintf(ni->ni_bssid) 4339 1.32.2.2 skrll , ni->ni_capinfo 4340 1.32.2.12 christos , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4341 1.32.2.2 skrll 4342 1.32.2.11 skrll switch (ic->ic_opmode) { 4343 1.32.2.11 skrll case IEEE80211_M_HOSTAP: 4344 1.32.2.11 skrll case IEEE80211_M_IBSS: 4345 1.32.2.11 skrll /* 4346 1.32.2.11 skrll * Allocate and setup the beacon frame. 4347 1.32.2.11 skrll * 4348 1.32.2.11 skrll * Stop any previous beacon DMA. This may be 4349 1.32.2.11 skrll * necessary, for example, when an ibss merge 4350 1.32.2.11 skrll * causes reconfiguration; there will be a state 4351 1.32.2.11 skrll * transition from RUN->RUN that means we may 4352 1.32.2.11 skrll * be called with beacon transmission active. 4353 1.32.2.11 skrll */ 4354 1.32.2.11 skrll ath_hal_stoptxdma(ah, sc->sc_bhalq); 4355 1.32.2.11 skrll ath_beacon_free(sc); 4356 1.32.2.2 skrll error = ath_beacon_alloc(sc, ni); 4357 1.32.2.2 skrll if (error != 0) 4358 1.32.2.2 skrll goto bad; 4359 1.32.2.11 skrll break; 4360 1.32.2.11 skrll case IEEE80211_M_STA: 4361 1.32.2.11 skrll /* 4362 1.32.2.11 skrll * Allocate a key cache slot to the station. 4363 1.32.2.11 skrll */ 4364 1.32.2.11 skrll if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4365 1.32.2.11 skrll sc->sc_hasclrkey && 4366 1.32.2.11 skrll ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4367 1.32.2.11 skrll ath_setup_stationkey(ni); 4368 1.32.2.11 skrll break; 4369 1.32.2.11 skrll default: 4370 1.32.2.11 skrll break; 4371 1.32.2.2 skrll } 4372 1.32.2.2 skrll 4373 1.32.2.2 skrll /* 4374 1.32.2.2 skrll * Configure the beacon and sleep timers. 4375 1.32.2.2 skrll */ 4376 1.32.2.2 skrll ath_beacon_config(sc); 4377 1.32.2.2 skrll } else { 4378 1.32.2.11 skrll ath_hal_intrset(ah, 4379 1.32.2.11 skrll sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4380 1.32.2.2 skrll sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4381 1.32.2.2 skrll } 4382 1.32.2.11 skrll done: 4383 1.32.2.2 skrll /* 4384 1.32.2.11 skrll * Invoke the parent method to complete the work. 4385 1.32.2.2 skrll */ 4386 1.32.2.11 skrll error = sc->sc_newstate(ic, nstate, arg); 4387 1.32.2.2 skrll /* 4388 1.32.2.11 skrll * Finally, start any timers. 4389 1.32.2.2 skrll */ 4390 1.32.2.11 skrll if (nstate == IEEE80211_S_RUN) { 4391 1.32.2.11 skrll /* start periodic recalibration timer */ 4392 1.32.2.11 skrll callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4393 1.32.2.11 skrll ath_calibrate, sc); 4394 1.32.2.11 skrll } else if (nstate == IEEE80211_S_SCAN) { 4395 1.32.2.11 skrll /* start ap/neighbor scan timer */ 4396 1.32.2.11 skrll callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4397 1.32.2.11 skrll ath_next_scan, sc); 4398 1.32.2.11 skrll } 4399 1.32.2.2 skrll bad: 4400 1.32.2.2 skrll return error; 4401 1.32.2.2 skrll } 4402 1.32.2.2 skrll 4403 1.32.2.11 skrll /* 4404 1.32.2.11 skrll * Allocate a key cache slot to the station so we can 4405 1.32.2.11 skrll * setup a mapping from key index to node. The key cache 4406 1.32.2.11 skrll * slot is needed for managing antenna state and for 4407 1.32.2.11 skrll * compression when stations do not use crypto. We do 4408 1.32.2.11 skrll * it uniliaterally here; if crypto is employed this slot 4409 1.32.2.11 skrll * will be reassigned. 4410 1.32.2.11 skrll */ 4411 1.32.2.3 skrll static void 4412 1.32.2.11 skrll ath_setup_stationkey(struct ieee80211_node *ni) 4413 1.32.2.3 skrll { 4414 1.32.2.11 skrll struct ieee80211com *ic = ni->ni_ic; 4415 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 4416 1.32.2.12 christos ieee80211_keyix keyix, rxkeyix; 4417 1.32.2.3 skrll 4418 1.32.2.12 christos if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4419 1.32.2.11 skrll /* 4420 1.32.2.11 skrll * Key cache is full; we'll fall back to doing 4421 1.32.2.11 skrll * the more expensive lookup in software. Note 4422 1.32.2.11 skrll * this also means no h/w compression. 4423 1.32.2.11 skrll */ 4424 1.32.2.11 skrll /* XXX msg+statistic */ 4425 1.32.2.11 skrll } else { 4426 1.32.2.12 christos /* XXX locking? */ 4427 1.32.2.11 skrll ni->ni_ucastkey.wk_keyix = keyix; 4428 1.32.2.12 christos ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4429 1.32.2.11 skrll /* NB: this will create a pass-thru key entry */ 4430 1.32.2.11 skrll ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4431 1.32.2.3 skrll } 4432 1.32.2.3 skrll } 4433 1.32.2.3 skrll 4434 1.32.2.2 skrll /* 4435 1.32.2.2 skrll * Setup driver-specific state for a newly associated node. 4436 1.32.2.2 skrll * Note that we're called also on a re-associate, the isnew 4437 1.32.2.2 skrll * param tells us if this is the first time or not. 4438 1.32.2.2 skrll */ 4439 1.32.2.2 skrll static void 4440 1.32.2.12 christos ath_newassoc(struct ieee80211_node *ni, int isnew) 4441 1.32.2.2 skrll { 4442 1.32.2.12 christos struct ieee80211com *ic = ni->ni_ic; 4443 1.32.2.11 skrll struct ath_softc *sc = ic->ic_ifp->if_softc; 4444 1.32.2.2 skrll 4445 1.32.2.11 skrll ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4446 1.32.2.11 skrll if (isnew && 4447 1.32.2.11 skrll (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4448 1.32.2.11 skrll KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4449 1.32.2.11 skrll ("new assoc with a unicast key already setup (keyix %u)", 4450 1.32.2.11 skrll ni->ni_ucastkey.wk_keyix)); 4451 1.32.2.11 skrll ath_setup_stationkey(ni); 4452 1.32.2.2 skrll } 4453 1.32.2.2 skrll } 4454 1.32.2.2 skrll 4455 1.32.2.2 skrll static int 4456 1.32.2.11 skrll ath_getchannels(struct ath_softc *sc, u_int cc, 4457 1.32.2.11 skrll HAL_BOOL outdoor, HAL_BOOL xchanmode) 4458 1.32.2.2 skrll { 4459 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 4460 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 4461 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4462 1.32.2.2 skrll HAL_CHANNEL *chans; 4463 1.32.2.2 skrll int i, ix, nchan; 4464 1.32.2.2 skrll 4465 1.32.2.2 skrll chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4466 1.32.2.2 skrll M_TEMP, M_NOWAIT); 4467 1.32.2.2 skrll if (chans == NULL) { 4468 1.32.2.2 skrll if_printf(ifp, "unable to allocate channel table\n"); 4469 1.32.2.2 skrll return ENOMEM; 4470 1.32.2.2 skrll } 4471 1.32.2.2 skrll if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4472 1.32.2.2 skrll cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4473 1.32.2.11 skrll u_int32_t rd; 4474 1.32.2.11 skrll 4475 1.32.2.11 skrll ath_hal_getregdomain(ah, &rd); 4476 1.32.2.11 skrll if_printf(ifp, "unable to collect channel list from hal; " 4477 1.32.2.11 skrll "regdomain likely %u country code %u\n", rd, cc); 4478 1.32.2.2 skrll free(chans, M_TEMP); 4479 1.32.2.2 skrll return EINVAL; 4480 1.32.2.2 skrll } 4481 1.32.2.2 skrll 4482 1.32.2.2 skrll /* 4483 1.32.2.2 skrll * Convert HAL channels to ieee80211 ones and insert 4484 1.32.2.2 skrll * them in the table according to their channel number. 4485 1.32.2.2 skrll */ 4486 1.32.2.2 skrll for (i = 0; i < nchan; i++) { 4487 1.32.2.2 skrll HAL_CHANNEL *c = &chans[i]; 4488 1.32.2.2 skrll ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4489 1.32.2.2 skrll if (ix > IEEE80211_CHAN_MAX) { 4490 1.32.2.2 skrll if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4491 1.32.2.2 skrll ix, c->channel, c->channelFlags); 4492 1.32.2.2 skrll continue; 4493 1.32.2.2 skrll } 4494 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 4495 1.32.2.11 skrll "%s: HAL channel %d/%d freq %d flags %#04x idx %d\n", 4496 1.32.2.2 skrll sc->sc_dev.dv_xname, i, nchan, c->channel, c->channelFlags, 4497 1.32.2.11 skrll ix); 4498 1.32.2.2 skrll /* NB: flags are known to be compatible */ 4499 1.32.2.2 skrll if (ic->ic_channels[ix].ic_freq == 0) { 4500 1.32.2.2 skrll ic->ic_channels[ix].ic_freq = c->channel; 4501 1.32.2.2 skrll ic->ic_channels[ix].ic_flags = c->channelFlags; 4502 1.32.2.2 skrll } else { 4503 1.32.2.2 skrll /* channels overlap; e.g. 11g and 11b */ 4504 1.32.2.2 skrll ic->ic_channels[ix].ic_flags |= c->channelFlags; 4505 1.32.2.2 skrll } 4506 1.32.2.2 skrll } 4507 1.32.2.2 skrll free(chans, M_TEMP); 4508 1.32.2.2 skrll return 0; 4509 1.32.2.2 skrll } 4510 1.32.2.2 skrll 4511 1.32.2.11 skrll static void 4512 1.32.2.11 skrll ath_led_done(void *arg) 4513 1.32.2.11 skrll { 4514 1.32.2.11 skrll struct ath_softc *sc = arg; 4515 1.32.2.11 skrll 4516 1.32.2.11 skrll sc->sc_blinking = 0; 4517 1.32.2.11 skrll } 4518 1.32.2.11 skrll 4519 1.32.2.11 skrll /* 4520 1.32.2.11 skrll * Turn the LED off: flip the pin and then set a timer so no 4521 1.32.2.11 skrll * update will happen for the specified duration. 4522 1.32.2.11 skrll */ 4523 1.32.2.11 skrll static void 4524 1.32.2.11 skrll ath_led_off(void *arg) 4525 1.32.2.11 skrll { 4526 1.32.2.11 skrll struct ath_softc *sc = arg; 4527 1.32.2.11 skrll 4528 1.32.2.11 skrll ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4529 1.32.2.11 skrll callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4530 1.32.2.11 skrll } 4531 1.32.2.11 skrll 4532 1.32.2.11 skrll /* 4533 1.32.2.11 skrll * Blink the LED according to the specified on/off times. 4534 1.32.2.11 skrll */ 4535 1.32.2.11 skrll static void 4536 1.32.2.11 skrll ath_led_blink(struct ath_softc *sc, int on, int off) 4537 1.32.2.11 skrll { 4538 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4539 1.32.2.11 skrll ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4540 1.32.2.11 skrll sc->sc_blinking = 1; 4541 1.32.2.11 skrll sc->sc_ledoff = off; 4542 1.32.2.11 skrll callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4543 1.32.2.11 skrll } 4544 1.32.2.11 skrll 4545 1.32.2.11 skrll static void 4546 1.32.2.11 skrll ath_led_event(struct ath_softc *sc, int event) 4547 1.32.2.11 skrll { 4548 1.32.2.11 skrll 4549 1.32.2.11 skrll sc->sc_ledevent = ticks; /* time of last event */ 4550 1.32.2.11 skrll if (sc->sc_blinking) /* don't interrupt active blink */ 4551 1.32.2.11 skrll return; 4552 1.32.2.11 skrll switch (event) { 4553 1.32.2.11 skrll case ATH_LED_POLL: 4554 1.32.2.11 skrll ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4555 1.32.2.11 skrll sc->sc_hwmap[0].ledoff); 4556 1.32.2.11 skrll break; 4557 1.32.2.11 skrll case ATH_LED_TX: 4558 1.32.2.11 skrll ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4559 1.32.2.11 skrll sc->sc_hwmap[sc->sc_txrate].ledoff); 4560 1.32.2.11 skrll break; 4561 1.32.2.11 skrll case ATH_LED_RX: 4562 1.32.2.11 skrll ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4563 1.32.2.11 skrll sc->sc_hwmap[sc->sc_rxrate].ledoff); 4564 1.32.2.11 skrll break; 4565 1.32.2.11 skrll } 4566 1.32.2.11 skrll } 4567 1.32.2.11 skrll 4568 1.32.2.11 skrll static void 4569 1.32.2.11 skrll ath_update_txpow(struct ath_softc *sc) 4570 1.32.2.11 skrll { 4571 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 4572 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4573 1.32.2.11 skrll u_int32_t txpow; 4574 1.32.2.11 skrll 4575 1.32.2.11 skrll if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4576 1.32.2.11 skrll ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4577 1.32.2.11 skrll /* read back in case value is clamped */ 4578 1.32.2.11 skrll ath_hal_gettxpowlimit(ah, &txpow); 4579 1.32.2.11 skrll ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4580 1.32.2.11 skrll } 4581 1.32.2.11 skrll /* 4582 1.32.2.11 skrll * Fetch max tx power level for status requests. 4583 1.32.2.11 skrll */ 4584 1.32.2.11 skrll ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4585 1.32.2.11 skrll ic->ic_bss->ni_txpower = txpow; 4586 1.32.2.11 skrll } 4587 1.32.2.11 skrll 4588 1.32.2.2 skrll static int 4589 1.32.2.2 skrll ath_rate_setup(struct ath_softc *sc, u_int mode) 4590 1.32.2.2 skrll { 4591 1.32.2.2 skrll struct ath_hal *ah = sc->sc_ah; 4592 1.32.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 4593 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 4594 1.32.2.2 skrll struct ieee80211_rateset *rs; 4595 1.32.2.2 skrll int i, maxrates; 4596 1.32.2.2 skrll 4597 1.32.2.2 skrll switch (mode) { 4598 1.32.2.2 skrll case IEEE80211_MODE_11A: 4599 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4600 1.32.2.2 skrll break; 4601 1.32.2.2 skrll case IEEE80211_MODE_11B: 4602 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4603 1.32.2.2 skrll break; 4604 1.32.2.2 skrll case IEEE80211_MODE_11G: 4605 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4606 1.32.2.2 skrll break; 4607 1.32.2.11 skrll case IEEE80211_MODE_TURBO_A: 4608 1.32.2.2 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4609 1.32.2.2 skrll break; 4610 1.32.2.11 skrll case IEEE80211_MODE_TURBO_G: 4611 1.32.2.11 skrll sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4612 1.32.2.11 skrll break; 4613 1.32.2.2 skrll default: 4614 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4615 1.32.2.11 skrll __func__, mode); 4616 1.32.2.2 skrll return 0; 4617 1.32.2.2 skrll } 4618 1.32.2.2 skrll rt = sc->sc_rates[mode]; 4619 1.32.2.2 skrll if (rt == NULL) 4620 1.32.2.2 skrll return 0; 4621 1.32.2.2 skrll if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4622 1.32.2.11 skrll DPRINTF(sc, ATH_DEBUG_ANY, 4623 1.32.2.11 skrll "%s: rate table too small (%u > %u)\n", 4624 1.32.2.11 skrll __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4625 1.32.2.2 skrll maxrates = IEEE80211_RATE_MAXSIZE; 4626 1.32.2.2 skrll } else 4627 1.32.2.2 skrll maxrates = rt->rateCount; 4628 1.32.2.2 skrll rs = &ic->ic_sup_rates[mode]; 4629 1.32.2.2 skrll for (i = 0; i < maxrates; i++) 4630 1.32.2.2 skrll rs->rs_rates[i] = rt->info[i].dot11Rate; 4631 1.32.2.2 skrll rs->rs_nrates = maxrates; 4632 1.32.2.2 skrll return 1; 4633 1.32.2.2 skrll } 4634 1.32.2.2 skrll 4635 1.32.2.2 skrll static void 4636 1.32.2.2 skrll ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4637 1.32.2.2 skrll { 4638 1.32.2.11 skrll #define N(a) (sizeof(a)/sizeof(a[0])) 4639 1.32.2.11 skrll /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4640 1.32.2.11 skrll static const struct { 4641 1.32.2.11 skrll u_int rate; /* tx/rx 802.11 rate */ 4642 1.32.2.11 skrll u_int16_t timeOn; /* LED on time (ms) */ 4643 1.32.2.11 skrll u_int16_t timeOff; /* LED off time (ms) */ 4644 1.32.2.11 skrll } blinkrates[] = { 4645 1.32.2.11 skrll { 108, 40, 10 }, 4646 1.32.2.11 skrll { 96, 44, 11 }, 4647 1.32.2.11 skrll { 72, 50, 13 }, 4648 1.32.2.11 skrll { 48, 57, 14 }, 4649 1.32.2.11 skrll { 36, 67, 16 }, 4650 1.32.2.11 skrll { 24, 80, 20 }, 4651 1.32.2.11 skrll { 22, 100, 25 }, 4652 1.32.2.11 skrll { 18, 133, 34 }, 4653 1.32.2.11 skrll { 12, 160, 40 }, 4654 1.32.2.11 skrll { 10, 200, 50 }, 4655 1.32.2.11 skrll { 6, 240, 58 }, 4656 1.32.2.11 skrll { 4, 267, 66 }, 4657 1.32.2.11 skrll { 2, 400, 100 }, 4658 1.32.2.11 skrll { 0, 500, 130 }, 4659 1.32.2.11 skrll }; 4660 1.32.2.2 skrll const HAL_RATE_TABLE *rt; 4661 1.32.2.11 skrll int i, j; 4662 1.32.2.2 skrll 4663 1.32.2.2 skrll memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4664 1.32.2.2 skrll rt = sc->sc_rates[mode]; 4665 1.32.2.2 skrll KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4666 1.32.2.2 skrll for (i = 0; i < rt->rateCount; i++) 4667 1.32.2.2 skrll sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4668 1.32.2.2 skrll memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4669 1.32.2.11 skrll for (i = 0; i < 32; i++) { 4670 1.32.2.11 skrll u_int8_t ix = rt->rateCodeToIndex[i]; 4671 1.32.2.11 skrll if (ix == 0xff) { 4672 1.32.2.11 skrll sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4673 1.32.2.11 skrll sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4674 1.32.2.11 skrll continue; 4675 1.32.2.11 skrll } 4676 1.32.2.11 skrll sc->sc_hwmap[i].ieeerate = 4677 1.32.2.11 skrll rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4678 1.32.2.11 skrll sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4679 1.32.2.11 skrll if (rt->info[ix].shortPreamble || 4680 1.32.2.11 skrll rt->info[ix].phy == IEEE80211_T_OFDM) 4681 1.32.2.11 skrll sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4682 1.32.2.11 skrll /* NB: receive frames include FCS */ 4683 1.32.2.11 skrll sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4684 1.32.2.11 skrll IEEE80211_RADIOTAP_F_FCS; 4685 1.32.2.11 skrll /* setup blink rate table to avoid per-packet lookup */ 4686 1.32.2.11 skrll for (j = 0; j < N(blinkrates)-1; j++) 4687 1.32.2.11 skrll if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4688 1.32.2.11 skrll break; 4689 1.32.2.11 skrll /* NB: this uses the last entry if the rate isn't found */ 4690 1.32.2.11 skrll /* XXX beware of overlow */ 4691 1.32.2.11 skrll sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4692 1.32.2.11 skrll sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4693 1.32.2.11 skrll } 4694 1.32.2.2 skrll sc->sc_currates = rt; 4695 1.32.2.2 skrll sc->sc_curmode = mode; 4696 1.32.2.11 skrll /* 4697 1.32.2.11 skrll * All protection frames are transmited at 2Mb/s for 4698 1.32.2.11 skrll * 11g, otherwise at 1Mb/s. 4699 1.32.2.11 skrll * XXX select protection rate index from rate table. 4700 1.32.2.11 skrll */ 4701 1.32.2.11 skrll sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4702 1.32.2.11 skrll /* NB: caller is responsible for reseting rate control state */ 4703 1.32.2.11 skrll #undef N 4704 1.32.2.2 skrll } 4705 1.32.2.2 skrll 4706 1.32.2.11 skrll #ifdef AR_DEBUG 4707 1.32.2.2 skrll static void 4708 1.32.2.11 skrll ath_printrxbuf(struct ath_buf *bf, int done) 4709 1.32.2.2 skrll { 4710 1.32.2.11 skrll struct ath_desc *ds; 4711 1.32.2.11 skrll int i; 4712 1.32.2.2 skrll 4713 1.32.2.11 skrll for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4714 1.32.2.11 skrll printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4715 1.32.2.11 skrll i, ds, (struct ath_desc *)bf->bf_daddr + i, 4716 1.32.2.11 skrll ds->ds_link, ds->ds_data, 4717 1.32.2.11 skrll ds->ds_ctl0, ds->ds_ctl1, 4718 1.32.2.11 skrll ds->ds_hw[0], ds->ds_hw[1], 4719 1.32.2.11 skrll !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4720 1.32.2.2 skrll } 4721 1.32.2.2 skrll } 4722 1.32.2.2 skrll 4723 1.32.2.2 skrll static void 4724 1.32.2.11 skrll ath_printtxbuf(struct ath_buf *bf, int done) 4725 1.32.2.2 skrll { 4726 1.32.2.11 skrll struct ath_desc *ds; 4727 1.32.2.11 skrll int i; 4728 1.32.2.2 skrll 4729 1.32.2.11 skrll for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4730 1.32.2.11 skrll printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4731 1.32.2.11 skrll i, ds, (struct ath_desc *)bf->bf_daddr + i, 4732 1.32.2.11 skrll ds->ds_link, ds->ds_data, 4733 1.32.2.11 skrll ds->ds_ctl0, ds->ds_ctl1, 4734 1.32.2.11 skrll ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4735 1.32.2.11 skrll !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4736 1.32.2.2 skrll } 4737 1.32.2.11 skrll } 4738 1.32.2.11 skrll #endif /* AR_DEBUG */ 4739 1.32.2.11 skrll 4740 1.32.2.11 skrll static void 4741 1.32.2.11 skrll ath_watchdog(struct ifnet *ifp) 4742 1.32.2.11 skrll { 4743 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 4744 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 4745 1.32.2.2 skrll 4746 1.32.2.11 skrll ifp->if_timer = 0; 4747 1.32.2.11 skrll if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 4748 1.32.2.11 skrll return; 4749 1.32.2.11 skrll if (sc->sc_tx_timer) { 4750 1.32.2.11 skrll if (--sc->sc_tx_timer == 0) { 4751 1.32.2.11 skrll if_printf(ifp, "device timeout\n"); 4752 1.32.2.11 skrll ath_reset(ifp); 4753 1.32.2.11 skrll ifp->if_oerrors++; 4754 1.32.2.11 skrll sc->sc_stats.ast_watchdog++; 4755 1.32.2.11 skrll } else 4756 1.32.2.11 skrll ifp->if_timer = 1; 4757 1.32.2.2 skrll } 4758 1.32.2.11 skrll ieee80211_watchdog(ic); 4759 1.32.2.2 skrll } 4760 1.32.2.2 skrll 4761 1.32.2.11 skrll /* 4762 1.32.2.11 skrll * Diagnostic interface to the HAL. This is used by various 4763 1.32.2.11 skrll * tools to do things like retrieve register contents for 4764 1.32.2.11 skrll * debugging. The mechanism is intentionally opaque so that 4765 1.32.2.11 skrll * it can change frequently w/o concern for compatiblity. 4766 1.32.2.11 skrll */ 4767 1.32.2.2 skrll static int 4768 1.32.2.11 skrll ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4769 1.32.2.2 skrll { 4770 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4771 1.32.2.11 skrll u_int id = ad->ad_id & ATH_DIAG_ID; 4772 1.32.2.11 skrll void *indata = NULL; 4773 1.32.2.11 skrll void *outdata = NULL; 4774 1.32.2.11 skrll u_int32_t insize = ad->ad_in_size; 4775 1.32.2.11 skrll u_int32_t outsize = ad->ad_out_size; 4776 1.32.2.11 skrll int error = 0; 4777 1.32.2.2 skrll 4778 1.32.2.11 skrll if (ad->ad_id & ATH_DIAG_IN) { 4779 1.32.2.11 skrll /* 4780 1.32.2.11 skrll * Copy in data. 4781 1.32.2.11 skrll */ 4782 1.32.2.11 skrll indata = malloc(insize, M_TEMP, M_NOWAIT); 4783 1.32.2.11 skrll if (indata == NULL) { 4784 1.32.2.11 skrll error = ENOMEM; 4785 1.32.2.11 skrll goto bad; 4786 1.32.2.11 skrll } 4787 1.32.2.11 skrll error = copyin(ad->ad_in_data, indata, insize); 4788 1.32.2.11 skrll if (error) 4789 1.32.2.11 skrll goto bad; 4790 1.32.2.2 skrll } 4791 1.32.2.11 skrll if (ad->ad_id & ATH_DIAG_DYN) { 4792 1.32.2.11 skrll /* 4793 1.32.2.11 skrll * Allocate a buffer for the results (otherwise the HAL 4794 1.32.2.11 skrll * returns a pointer to a buffer where we can read the 4795 1.32.2.11 skrll * results). Note that we depend on the HAL leaving this 4796 1.32.2.11 skrll * pointer for us to use below in reclaiming the buffer; 4797 1.32.2.11 skrll * may want to be more defensive. 4798 1.32.2.11 skrll */ 4799 1.32.2.11 skrll outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4800 1.32.2.11 skrll if (outdata == NULL) { 4801 1.32.2.11 skrll error = ENOMEM; 4802 1.32.2.11 skrll goto bad; 4803 1.32.2.11 skrll } 4804 1.32.2.11 skrll } 4805 1.32.2.11 skrll if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4806 1.32.2.11 skrll if (outsize < ad->ad_out_size) 4807 1.32.2.11 skrll ad->ad_out_size = outsize; 4808 1.32.2.11 skrll if (outdata != NULL) 4809 1.32.2.11 skrll error = copyout(outdata, ad->ad_out_data, 4810 1.32.2.11 skrll ad->ad_out_size); 4811 1.32.2.11 skrll } else { 4812 1.32.2.11 skrll error = EINVAL; 4813 1.32.2.11 skrll } 4814 1.32.2.11 skrll bad: 4815 1.32.2.11 skrll if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4816 1.32.2.11 skrll free(indata, M_TEMP); 4817 1.32.2.11 skrll if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4818 1.32.2.11 skrll free(outdata, M_TEMP); 4819 1.32.2.2 skrll return error; 4820 1.32.2.2 skrll } 4821 1.32.2.2 skrll 4822 1.32.2.2 skrll static int 4823 1.32.2.11 skrll ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4824 1.32.2.2 skrll { 4825 1.32.2.11 skrll #define IS_RUNNING(ifp) \ 4826 1.32.2.12 christos ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 4827 1.32.2.11 skrll struct ath_softc *sc = ifp->if_softc; 4828 1.32.2.11 skrll struct ieee80211com *ic = &sc->sc_ic; 4829 1.32.2.11 skrll struct ifreq *ifr = (struct ifreq *)data; 4830 1.32.2.11 skrll int error = 0; 4831 1.32.2.2 skrll 4832 1.32.2.11 skrll ATH_LOCK(sc); 4833 1.32.2.11 skrll switch (cmd) { 4834 1.32.2.11 skrll case SIOCSIFFLAGS: 4835 1.32.2.11 skrll if (IS_RUNNING(ifp)) { 4836 1.32.2.11 skrll /* 4837 1.32.2.11 skrll * To avoid rescanning another access point, 4838 1.32.2.11 skrll * do not call ath_init() here. Instead, 4839 1.32.2.11 skrll * only reflect promisc mode settings. 4840 1.32.2.11 skrll */ 4841 1.32.2.11 skrll ath_mode_init(sc); 4842 1.32.2.11 skrll } else if (ifp->if_flags & IFF_UP) { 4843 1.32.2.11 skrll /* 4844 1.32.2.11 skrll * Beware of being called during attach/detach 4845 1.32.2.11 skrll * to reset promiscuous mode. In that case we 4846 1.32.2.11 skrll * will still be marked UP but not RUNNING. 4847 1.32.2.11 skrll * However trying to re-init the interface 4848 1.32.2.11 skrll * is the wrong thing to do as we've already 4849 1.32.2.11 skrll * torn down much of our state. There's 4850 1.32.2.11 skrll * probably a better way to deal with this. 4851 1.32.2.11 skrll */ 4852 1.32.2.11 skrll if (!sc->sc_invalid && ic->ic_bss != NULL) 4853 1.32.2.11 skrll ath_init(sc); /* XXX lose error */ 4854 1.32.2.11 skrll } else 4855 1.32.2.11 skrll ath_stop_locked(ifp, 1); 4856 1.32.2.11 skrll break; 4857 1.32.2.11 skrll case SIOCADDMULTI: 4858 1.32.2.11 skrll case SIOCDELMULTI: 4859 1.32.2.11 skrll error = (cmd == SIOCADDMULTI) ? 4860 1.32.2.11 skrll ether_addmulti(ifr, &sc->sc_ec) : 4861 1.32.2.11 skrll ether_delmulti(ifr, &sc->sc_ec); 4862 1.32.2.11 skrll if (error == ENETRESET) { 4863 1.32.2.11 skrll if (ifp->if_flags & IFF_RUNNING) 4864 1.32.2.11 skrll ath_mode_init(sc); 4865 1.32.2.11 skrll error = 0; 4866 1.32.2.11 skrll } 4867 1.32.2.11 skrll break; 4868 1.32.2.11 skrll case SIOCGATHSTATS: 4869 1.32.2.11 skrll /* NB: embed these numbers to get a consistent view */ 4870 1.32.2.11 skrll sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4871 1.32.2.11 skrll sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4872 1.32.2.11 skrll sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4873 1.32.2.11 skrll ATH_UNLOCK(sc); 4874 1.32.2.11 skrll /* 4875 1.32.2.11 skrll * NB: Drop the softc lock in case of a page fault; 4876 1.32.2.11 skrll * we'll accept any potential inconsisentcy in the 4877 1.32.2.11 skrll * statistics. The alternative is to copy the data 4878 1.32.2.11 skrll * to a local structure. 4879 1.32.2.11 skrll */ 4880 1.32.2.11 skrll return copyout(&sc->sc_stats, 4881 1.32.2.11 skrll ifr->ifr_data, sizeof (sc->sc_stats)); 4882 1.32.2.11 skrll case SIOCGATHDIAG: 4883 1.32.2.11 skrll error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4884 1.32.2.11 skrll break; 4885 1.32.2.11 skrll default: 4886 1.32.2.11 skrll error = ieee80211_ioctl(ic, cmd, data); 4887 1.32.2.11 skrll if (error == ENETRESET) { 4888 1.32.2.11 skrll if (IS_RUNNING(ifp) && 4889 1.32.2.11 skrll ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4890 1.32.2.11 skrll ath_init(sc); /* XXX lose error */ 4891 1.32.2.11 skrll error = 0; 4892 1.32.2.11 skrll } 4893 1.32.2.11 skrll if (error == ERESTART) 4894 1.32.2.11 skrll error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4895 1.32.2.11 skrll break; 4896 1.32.2.2 skrll } 4897 1.32.2.11 skrll ATH_UNLOCK(sc); 4898 1.32.2.2 skrll return error; 4899 1.32.2.11 skrll #undef IS_RUNNING 4900 1.32.2.2 skrll } 4901 1.32.2.2 skrll 4902 1.32.2.12 christos #if NBPFILTER > 0 4903 1.32.2.2 skrll static void 4904 1.32.2.11 skrll ath_bpfattach(struct ath_softc *sc) 4905 1.32.2.2 skrll { 4906 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 4907 1.32.2.2 skrll 4908 1.32.2.11 skrll bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4909 1.32.2.11 skrll sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4910 1.32.2.11 skrll &sc->sc_drvbpf); 4911 1.32.2.11 skrll /* 4912 1.32.2.11 skrll * Initialize constant fields. 4913 1.32.2.11 skrll * XXX make header lengths a multiple of 32-bits so subsequent 4914 1.32.2.11 skrll * headers are properly aligned; this is a kludge to keep 4915 1.32.2.11 skrll * certain applications happy. 4916 1.32.2.11 skrll * 4917 1.32.2.11 skrll * NB: the channel is setup each time we transition to the 4918 1.32.2.11 skrll * RUN state to avoid filling it in for each frame. 4919 1.32.2.11 skrll */ 4920 1.32.2.11 skrll sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4921 1.32.2.11 skrll sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4922 1.32.2.11 skrll sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4923 1.32.2.11 skrll 4924 1.32.2.11 skrll sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4925 1.32.2.11 skrll sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4926 1.32.2.11 skrll sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4927 1.32.2.2 skrll } 4928 1.32.2.12 christos #endif 4929 1.32.2.2 skrll 4930 1.32.2.11 skrll /* 4931 1.32.2.11 skrll * Announce various information on device/driver attach. 4932 1.32.2.11 skrll */ 4933 1.32.2.2 skrll static void 4934 1.32.2.11 skrll ath_announce(struct ath_softc *sc) 4935 1.32.2.2 skrll { 4936 1.32.2.11 skrll #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4937 1.32.2.11 skrll struct ifnet *ifp = &sc->sc_if; 4938 1.32.2.11 skrll struct ath_hal *ah = sc->sc_ah; 4939 1.32.2.11 skrll u_int modes, cc; 4940 1.32.2.2 skrll 4941 1.32.2.11 skrll if_printf(ifp, "mac %d.%d phy %d.%d", 4942 1.32.2.11 skrll ah->ah_macVersion, ah->ah_macRev, 4943 1.32.2.11 skrll ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4944 1.32.2.11 skrll /* 4945 1.32.2.11 skrll * Print radio revision(s). We check the wireless modes 4946 1.32.2.11 skrll * to avoid falsely printing revs for inoperable parts. 4947 1.32.2.11 skrll * Dual-band radio revs are returned in the 5Ghz rev number. 4948 1.32.2.11 skrll */ 4949 1.32.2.11 skrll ath_hal_getcountrycode(ah, &cc); 4950 1.32.2.11 skrll modes = ath_hal_getwirelessmodes(ah, cc); 4951 1.32.2.11 skrll if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4952 1.32.2.11 skrll if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4953 1.32.2.11 skrll printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4954 1.32.2.11 skrll ah->ah_analog5GhzRev >> 4, 4955 1.32.2.11 skrll ah->ah_analog5GhzRev & 0xf, 4956 1.32.2.11 skrll ah->ah_analog2GhzRev >> 4, 4957 1.32.2.11 skrll ah->ah_analog2GhzRev & 0xf); 4958 1.32.2.11 skrll else 4959 1.32.2.11 skrll printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4960 1.32.2.11 skrll ah->ah_analog5GhzRev & 0xf); 4961 1.32.2.11 skrll } else 4962 1.32.2.11 skrll printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4963 1.32.2.11 skrll ah->ah_analog5GhzRev & 0xf); 4964 1.32.2.11 skrll printf("\n"); 4965 1.32.2.11 skrll if (bootverbose) { 4966 1.32.2.11 skrll int i; 4967 1.32.2.11 skrll for (i = 0; i <= WME_AC_VO; i++) { 4968 1.32.2.11 skrll struct ath_txq *txq = sc->sc_ac2q[i]; 4969 1.32.2.11 skrll if_printf(ifp, "Use hw queue %u for %s traffic\n", 4970 1.32.2.11 skrll txq->axq_qnum, ieee80211_wme_acnames[i]); 4971 1.32.2.11 skrll } 4972 1.32.2.11 skrll if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4973 1.32.2.11 skrll sc->sc_cabq->axq_qnum); 4974 1.32.2.11 skrll if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4975 1.32.2.2 skrll } 4976 1.32.2.11 skrll #undef HAL_MODE_DUALBAND 4977 1.32.2.2 skrll } 4978
Indexes created Thu Oct 02 14:10:14 GMT 2025