ath.c revision 1.104
1 /* $NetBSD: ath.c,v 1.104 2008/12/11 05:45:29 alc Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.104 2008/12/11 05:45:29 alc Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #include "opt_inet.h" 55 56 #ifdef __NetBSD__ 57 #include "bpfilter.h" 58 #endif /* __NetBSD__ */ 59 60 #include <sys/param.h> 61 #include <sys/reboot.h> 62 #include <sys/systm.h> 63 #include <sys/types.h> 64 #include <sys/sysctl.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/errno.h> 71 #include <sys/callout.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/if_ether.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_netbsd.h> 84 #include <net80211/ieee80211_var.h> 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #endif 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #endif 93 94 #include <sys/device.h> 95 #include <dev/ic/ath_netbsd.h> 96 97 #define AR_DEBUG 98 #include <dev/ic/athvar.h> 99 #include "ah_desc.h" 100 #include "ah_devid.h" /* XXX for softled */ 101 #include "opt_ah.h" 102 103 #ifdef ATH_TX99_DIAG 104 #include <dev/ath/ath_tx99/ath_tx99.h> 105 #endif 106 107 /* unaligned little endian access */ 108 #define LE_READ_2(p) \ 109 ((u_int16_t) \ 110 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 111 #define LE_READ_4(p) \ 112 ((u_int32_t) \ 113 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 114 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 115 116 enum { 117 ATH_LED_TX, 118 ATH_LED_RX, 119 ATH_LED_POLL, 120 }; 121 122 #ifdef AH_NEED_DESC_SWAP 123 #define HTOAH32(x) htole32(x) 124 #else 125 #define HTOAH32(x) (x) 126 #endif 127 128 static int ath_ifinit(struct ifnet *); 129 static int ath_init(struct ath_softc *); 130 static void ath_stop_locked(struct ifnet *, int); 131 static void ath_stop(struct ifnet *, int); 132 static void ath_start(struct ifnet *); 133 static int ath_media_change(struct ifnet *); 134 static void ath_watchdog(struct ifnet *); 135 static int ath_ioctl(struct ifnet *, u_long, void *); 136 static void ath_fatal_proc(void *, int); 137 static void ath_rxorn_proc(void *, int); 138 static void ath_bmiss_proc(void *, int); 139 static void ath_radar_proc(void *, int); 140 static int ath_key_alloc(struct ieee80211com *, 141 const struct ieee80211_key *, 142 ieee80211_keyix *, ieee80211_keyix *); 143 static int ath_key_delete(struct ieee80211com *, 144 const struct ieee80211_key *); 145 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 146 const u_int8_t mac[IEEE80211_ADDR_LEN]); 147 static void ath_key_update_begin(struct ieee80211com *); 148 static void ath_key_update_end(struct ieee80211com *); 149 static void ath_mode_init(struct ath_softc *); 150 static void ath_setslottime(struct ath_softc *); 151 static void ath_updateslot(struct ifnet *); 152 static int ath_beaconq_setup(struct ath_hal *); 153 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 154 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 155 static void ath_beacon_proc(void *, int); 156 static void ath_bstuck_proc(void *, int); 157 static void ath_beacon_free(struct ath_softc *); 158 static void ath_beacon_config(struct ath_softc *); 159 static void ath_descdma_cleanup(struct ath_softc *sc, 160 struct ath_descdma *, ath_bufhead *); 161 static int ath_desc_alloc(struct ath_softc *); 162 static void ath_desc_free(struct ath_softc *); 163 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 164 static void ath_node_free(struct ieee80211_node *); 165 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 166 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 167 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 168 struct ieee80211_node *ni, 169 int subtype, int rssi, u_int32_t rstamp); 170 static void ath_setdefantenna(struct ath_softc *, u_int); 171 static void ath_rx_proc(void *, int); 172 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 173 static int ath_tx_setup(struct ath_softc *, int, int); 174 static int ath_wme_update(struct ieee80211com *); 175 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 176 static void ath_tx_cleanup(struct ath_softc *); 177 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 178 struct ath_buf *, struct mbuf *); 179 static void ath_tx_proc_q0(void *, int); 180 static void ath_tx_proc_q0123(void *, int); 181 static void ath_tx_proc(void *, int); 182 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_draintxq(struct ath_softc *); 184 static void ath_stoprecv(struct ath_softc *); 185 static int ath_startrecv(struct ath_softc *); 186 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 187 static void ath_next_scan(void *); 188 static void ath_calibrate(void *); 189 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 190 static void ath_setup_stationkey(struct ieee80211_node *); 191 static void ath_newassoc(struct ieee80211_node *, int); 192 static int ath_getchannels(struct ath_softc *, u_int cc, 193 HAL_BOOL outdoor, HAL_BOOL xchanmode); 194 static void ath_led_event(struct ath_softc *, int); 195 static void ath_update_txpow(struct ath_softc *); 196 static void ath_freetx(struct mbuf *); 197 static void ath_restore_diversity(struct ath_softc *); 198 199 static int ath_rate_setup(struct ath_softc *, u_int mode); 200 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 201 202 #if NBPFILTER > 0 203 static void ath_bpfattach(struct ath_softc *); 204 #endif 205 static void ath_announce(struct ath_softc *); 206 207 int ath_dwelltime = 200; /* 5 channels/second */ 208 int ath_calinterval = 30; /* calibrate every 30 secs */ 209 int ath_outdoor = AH_TRUE; /* outdoor operation */ 210 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 211 int ath_countrycode = CTRY_DEFAULT; /* country code */ 212 int ath_regdomain = 0; /* regulatory domain */ 213 int ath_debug = 0; 214 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 215 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 216 217 #ifdef AR_DEBUG 218 enum { 219 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 220 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 221 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 222 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 223 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 224 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 225 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 226 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 227 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 228 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 229 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 230 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 231 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 232 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 233 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 234 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 235 ATH_DEBUG_NODE = 0x00080000, /* node management */ 236 ATH_DEBUG_LED = 0x00100000, /* led management */ 237 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 238 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 239 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 240 ATH_DEBUG_ANY = 0xffffffff 241 }; 242 #define IFF_DUMPPKTS(sc, m) \ 243 ((sc->sc_debug & (m)) || \ 244 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 245 #define DPRINTF(sc, m, fmt, ...) do { \ 246 if (sc->sc_debug & (m)) \ 247 printf(fmt, __VA_ARGS__); \ 248 } while (0) 249 #define KEYPRINTF(sc, ix, hk, mac) do { \ 250 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 251 ath_keyprint(__func__, ix, hk, mac); \ 252 } while (0) 253 static void ath_printrxbuf(struct ath_buf *bf, int); 254 static void ath_printtxbuf(struct ath_buf *bf, int); 255 #else 256 #define IFF_DUMPPKTS(sc, m) \ 257 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 258 #define DPRINTF(m, fmt, ...) 259 #define KEYPRINTF(sc, k, ix, mac) 260 #endif 261 262 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 263 264 int 265 ath_attach(u_int16_t devid, struct ath_softc *sc) 266 { 267 struct ifnet *ifp = &sc->sc_if; 268 struct ieee80211com *ic = &sc->sc_ic; 269 struct ath_hal *ah = NULL; 270 HAL_STATUS status; 271 int error = 0, i; 272 273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 274 275 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 276 277 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 278 if (ah == NULL) { 279 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 280 status); 281 error = ENXIO; 282 goto bad; 283 } 284 if (ah->ah_abi != HAL_ABI_VERSION) { 285 if_printf(ifp, "HAL ABI mismatch detected " 286 "(HAL:0x%x != driver:0x%x)\n", 287 ah->ah_abi, HAL_ABI_VERSION); 288 error = ENXIO; 289 goto bad; 290 } 291 sc->sc_ah = ah; 292 293 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 294 "pmf-powerdown", false)) 295 goto bad; 296 297 /* 298 * Check if the MAC has multi-rate retry support. 299 * We do this by trying to setup a fake extended 300 * descriptor. MAC's that don't have support will 301 * return false w/o doing anything. MAC's that do 302 * support it will return true w/o doing anything. 303 */ 304 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 305 306 /* 307 * Check if the device has hardware counters for PHY 308 * errors. If so we need to enable the MIB interrupt 309 * so we can act on stat triggers. 310 */ 311 if (ath_hal_hwphycounters(ah)) 312 sc->sc_needmib = 1; 313 314 /* 315 * Get the hardware key cache size. 316 */ 317 sc->sc_keymax = ath_hal_keycachesize(ah); 318 if (sc->sc_keymax > ATH_KEYMAX) { 319 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 320 ATH_KEYMAX, sc->sc_keymax); 321 sc->sc_keymax = ATH_KEYMAX; 322 } 323 /* 324 * Reset the key cache since some parts do not 325 * reset the contents on initial power up. 326 */ 327 for (i = 0; i < sc->sc_keymax; i++) 328 ath_hal_keyreset(ah, i); 329 /* 330 * Mark key cache slots associated with global keys 331 * as in use. If we knew TKIP was not to be used we 332 * could leave the +32, +64, and +32+64 slots free. 333 * XXX only for splitmic. 334 */ 335 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 336 setbit(sc->sc_keymap, i); 337 setbit(sc->sc_keymap, i+32); 338 setbit(sc->sc_keymap, i+64); 339 setbit(sc->sc_keymap, i+32+64); 340 } 341 342 /* 343 * Collect the channel list using the default country 344 * code and including outdoor channels. The 802.11 layer 345 * is resposible for filtering this list based on settings 346 * like the phy mode. 347 */ 348 error = ath_getchannels(sc, ath_countrycode, 349 ath_outdoor, ath_xchanmode); 350 if (error != 0) 351 goto bad; 352 353 /* 354 * Setup rate tables for all potential media types. 355 */ 356 ath_rate_setup(sc, IEEE80211_MODE_11A); 357 ath_rate_setup(sc, IEEE80211_MODE_11B); 358 ath_rate_setup(sc, IEEE80211_MODE_11G); 359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 360 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 361 /* NB: setup here so ath_rate_update is happy */ 362 ath_setcurmode(sc, IEEE80211_MODE_11A); 363 364 /* 365 * Allocate tx+rx descriptors and populate the lists. 366 */ 367 error = ath_desc_alloc(sc); 368 if (error != 0) { 369 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 370 goto bad; 371 } 372 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 373 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 374 #if 0 375 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 376 #endif 377 378 ATH_TXBUF_LOCK_INIT(sc); 379 380 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 381 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 382 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 383 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 384 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 385 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 386 387 /* 388 * Allocate hardware transmit queues: one queue for 389 * beacon frames and one data queue for each QoS 390 * priority. Note that the hal handles reseting 391 * these queues at the needed time. 392 * 393 * XXX PS-Poll 394 */ 395 sc->sc_bhalq = ath_beaconq_setup(ah); 396 if (sc->sc_bhalq == (u_int) -1) { 397 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 398 error = EIO; 399 goto bad2; 400 } 401 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 402 if (sc->sc_cabq == NULL) { 403 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 404 error = EIO; 405 goto bad2; 406 } 407 /* NB: insure BK queue is the lowest priority h/w queue */ 408 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 409 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 410 ieee80211_wme_acnames[WME_AC_BK]); 411 error = EIO; 412 goto bad2; 413 } 414 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 415 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 416 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 417 /* 418 * Not enough hardware tx queues to properly do WME; 419 * just punt and assign them all to the same h/w queue. 420 * We could do a better job of this if, for example, 421 * we allocate queues when we switch from station to 422 * AP mode. 423 */ 424 if (sc->sc_ac2q[WME_AC_VI] != NULL) 425 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 426 if (sc->sc_ac2q[WME_AC_BE] != NULL) 427 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 428 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 429 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 430 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 431 } 432 433 /* 434 * Special case certain configurations. Note the 435 * CAB queue is handled by these specially so don't 436 * include them when checking the txq setup mask. 437 */ 438 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 439 case 0x01: 440 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 441 break; 442 case 0x0f: 443 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 444 break; 445 default: 446 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 447 break; 448 } 449 450 /* 451 * Setup rate control. Some rate control modules 452 * call back to change the anntena state so expose 453 * the necessary entry points. 454 * XXX maybe belongs in struct ath_ratectrl? 455 */ 456 sc->sc_setdefantenna = ath_setdefantenna; 457 sc->sc_rc = ath_rate_attach(sc); 458 if (sc->sc_rc == NULL) { 459 error = EIO; 460 goto bad2; 461 } 462 463 sc->sc_blinking = 0; 464 sc->sc_ledstate = 1; 465 sc->sc_ledon = 0; /* low true */ 466 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 467 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 468 /* 469 * Auto-enable soft led processing for IBM cards and for 470 * 5211 minipci cards. Users can also manually enable/disable 471 * support with a sysctl. 472 */ 473 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 474 if (sc->sc_softled) { 475 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 476 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 477 } 478 479 ifp->if_softc = sc; 480 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 481 ifp->if_start = ath_start; 482 ifp->if_stop = ath_stop; 483 ifp->if_watchdog = ath_watchdog; 484 ifp->if_ioctl = ath_ioctl; 485 ifp->if_init = ath_ifinit; 486 IFQ_SET_READY(&ifp->if_snd); 487 488 ic->ic_ifp = ifp; 489 ic->ic_reset = ath_reset; 490 ic->ic_newassoc = ath_newassoc; 491 ic->ic_updateslot = ath_updateslot; 492 ic->ic_wme.wme_update = ath_wme_update; 493 /* XXX not right but it's not used anywhere important */ 494 ic->ic_phytype = IEEE80211_T_OFDM; 495 ic->ic_opmode = IEEE80211_M_STA; 496 ic->ic_caps = 497 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 498 | IEEE80211_C_HOSTAP /* hostap mode */ 499 | IEEE80211_C_MONITOR /* monitor mode */ 500 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 501 | IEEE80211_C_SHSLOT /* short slot time supported */ 502 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 503 | IEEE80211_C_TXFRAG /* handle tx frags */ 504 ; 505 /* 506 * Query the hal to figure out h/w crypto support. 507 */ 508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 509 ic->ic_caps |= IEEE80211_C_WEP; 510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 511 ic->ic_caps |= IEEE80211_C_AES; 512 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 513 ic->ic_caps |= IEEE80211_C_AES_CCM; 514 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 515 ic->ic_caps |= IEEE80211_C_CKIP; 516 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 517 ic->ic_caps |= IEEE80211_C_TKIP; 518 #if 0 519 /* 520 * Check if h/w does the MIC and/or whether the 521 * separate key cache entries are required to 522 * handle both tx+rx MIC keys. 523 */ 524 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) { 525 ic->ic_caps |= IEEE80211_C_TKIPMIC; 526 /* 527 * Check if h/w does MIC correctly when 528 * WMM is turned on. 529 */ 530 if (ath_hal_wmetkipmic(ah)) 531 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 532 } 533 #endif 534 535 /* 536 * If the h/w supports storing tx+rx MIC keys 537 * in one cache slot automatically enable use. 538 */ 539 if (ath_hal_tkipsplit(ah) || 540 !ath_hal_settkipsplit(ah, AH_FALSE)) 541 sc->sc_splitmic = 1; 542 } 543 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 544 #if 0 545 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 546 #endif 547 /* 548 * TPC support can be done either with a global cap or 549 * per-packet support. The latter is not available on 550 * all parts. We're a bit pedantic here as all parts 551 * support a global cap. 552 */ 553 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 554 ic->ic_caps |= IEEE80211_C_TXPMGT; 555 556 /* 557 * Mark WME capability only if we have sufficient 558 * hardware queues to do proper priority scheduling. 559 */ 560 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 561 ic->ic_caps |= IEEE80211_C_WME; 562 /* 563 * Check for misc other capabilities. 564 */ 565 if (ath_hal_hasbursting(ah)) 566 ic->ic_caps |= IEEE80211_C_BURST; 567 568 /* 569 * Indicate we need the 802.11 header padded to a 570 * 32-bit boundary for 4-address and QoS frames. 571 */ 572 ic->ic_flags |= IEEE80211_F_DATAPAD; 573 574 /* 575 * Query the hal about antenna support. 576 */ 577 sc->sc_defant = ath_hal_getdefantenna(ah); 578 579 /* 580 * Not all chips have the VEOL support we want to 581 * use with IBSS beacons; check here for it. 582 */ 583 sc->sc_hasveol = ath_hal_hasveol(ah); 584 585 /* get mac address from hardware */ 586 ath_hal_getmac(ah, ic->ic_myaddr); 587 588 if_attach(ifp); 589 /* call MI attach routine. */ 590 ieee80211_ifattach(ic); 591 /* override default methods */ 592 ic->ic_node_alloc = ath_node_alloc; 593 sc->sc_node_free = ic->ic_node_free; 594 ic->ic_node_free = ath_node_free; 595 ic->ic_node_getrssi = ath_node_getrssi; 596 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 597 ic->ic_recv_mgmt = ath_recv_mgmt; 598 sc->sc_newstate = ic->ic_newstate; 599 ic->ic_newstate = ath_newstate; 600 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 601 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 602 ic->ic_crypto.cs_key_delete = ath_key_delete; 603 ic->ic_crypto.cs_key_set = ath_key_set; 604 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 605 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 606 /* complete initialization */ 607 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 608 609 #if NBPFILTER > 0 610 ath_bpfattach(sc); 611 #endif 612 613 sc->sc_flags |= ATH_ATTACHED; 614 615 /* 616 * Setup dynamic sysctl's now that country code and 617 * regdomain are available from the hal. 618 */ 619 ath_sysctlattach(sc); 620 621 ieee80211_announce(ic); 622 ath_announce(sc); 623 return 0; 624 bad2: 625 ath_tx_cleanup(sc); 626 ath_desc_free(sc); 627 bad: 628 if (ah) 629 ath_hal_detach(ah); 630 /* XXX don't get under the abstraction like this */ 631 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 632 return error; 633 } 634 635 int 636 ath_detach(struct ath_softc *sc) 637 { 638 struct ifnet *ifp = &sc->sc_if; 639 int s; 640 641 if ((sc->sc_flags & ATH_ATTACHED) == 0) 642 return (0); 643 644 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 645 __func__, ifp->if_flags); 646 647 s = splnet(); 648 ath_stop(ifp, 1); 649 #if NBPFILTER > 0 650 bpfdetach(ifp); 651 #endif 652 /* 653 * NB: the order of these is important: 654 * o call the 802.11 layer before detaching the hal to 655 * insure callbacks into the driver to delete global 656 * key cache entries can be handled 657 * o reclaim the tx queue data structures after calling 658 * the 802.11 layer as we'll get called back to reclaim 659 * node state and potentially want to use them 660 * o to cleanup the tx queues the hal is called, so detach 661 * it last 662 * Other than that, it's straightforward... 663 */ 664 ieee80211_ifdetach(&sc->sc_ic); 665 #ifdef ATH_TX99_DIAG 666 if (sc->sc_tx99 != NULL) 667 sc->sc_tx99->detach(sc->sc_tx99); 668 #endif 669 ath_rate_detach(sc->sc_rc); 670 ath_desc_free(sc); 671 ath_tx_cleanup(sc); 672 sysctl_teardown(&sc->sc_sysctllog); 673 ath_hal_detach(sc->sc_ah); 674 if_detach(ifp); 675 splx(s); 676 677 return 0; 678 } 679 680 void 681 ath_suspend(struct ath_softc *sc) 682 { 683 #if notyet 684 /* 685 * Set the chip in full sleep mode. Note that we are 686 * careful to do this only when bringing the interface 687 * completely to a stop. When the chip is in this state 688 * it must be carefully woken up or references to 689 * registers in the PCI clock domain may freeze the bus 690 * (and system). This varies by chip and is mostly an 691 * issue with newer parts that go to sleep more quickly. 692 */ 693 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 694 #endif 695 } 696 697 bool 698 ath_resume(struct ath_softc *sc) 699 { 700 struct ath_hal *ah = sc->sc_ah; 701 struct ieee80211com *ic = &sc->sc_ic; 702 HAL_STATUS status; 703 int i; 704 705 #if notyet 706 ath_hal_setpower(ah, HAL_PM_AWAKE); 707 #else 708 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 709 #endif 710 711 /* 712 * Reset the key cache since some parts do not 713 * reset the contents on initial power up. 714 */ 715 for (i = 0; i < sc->sc_keymax; i++) 716 ath_hal_keyreset(ah, i); 717 718 ath_hal_resettxqueue(ah, sc->sc_bhalq); 719 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 720 if (ATH_TXQ_SETUP(sc, i)) 721 ath_hal_resettxqueue(ah, i); 722 723 if (sc->sc_softled) { 724 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 725 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 726 } 727 return true; 728 } 729 730 /* 731 * Interrupt handler. Most of the actual processing is deferred. 732 */ 733 int 734 ath_intr(void *arg) 735 { 736 struct ath_softc *sc = arg; 737 struct ifnet *ifp = &sc->sc_if; 738 struct ath_hal *ah = sc->sc_ah; 739 HAL_INT status; 740 741 if (!device_is_active(sc->sc_dev)) { 742 /* 743 * The hardware is not ready/present, don't touch anything. 744 * Note this can happen early on if the IRQ is shared. 745 */ 746 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 747 return 0; 748 } 749 750 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 751 return 0; 752 753 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 754 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 755 __func__, ifp->if_flags); 756 ath_hal_getisr(ah, &status); /* clear ISR */ 757 ath_hal_intrset(ah, 0); /* disable further intr's */ 758 return 1; /* XXX */ 759 } 760 /* 761 * Figure out the reason(s) for the interrupt. Note 762 * that the hal returns a pseudo-ISR that may include 763 * bits we haven't explicitly enabled so we mask the 764 * value to insure we only process bits we requested. 765 */ 766 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 767 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 768 status &= sc->sc_imask; /* discard unasked for bits */ 769 if (status & HAL_INT_FATAL) { 770 /* 771 * Fatal errors are unrecoverable. Typically 772 * these are caused by DMA errors. Unfortunately 773 * the exact reason is not (presently) returned 774 * by the hal. 775 */ 776 sc->sc_stats.ast_hardware++; 777 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 778 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 779 } else if (status & HAL_INT_RXORN) { 780 sc->sc_stats.ast_rxorn++; 781 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 782 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 783 } else { 784 if (status & HAL_INT_SWBA) { 785 /* 786 * Software beacon alert--time to send a beacon. 787 * Handle beacon transmission directly; deferring 788 * this is too slow to meet timing constraints 789 * under load. 790 */ 791 ath_beacon_proc(sc, 0); 792 } 793 if (status & HAL_INT_RXEOL) { 794 /* 795 * NB: the hardware should re-read the link when 796 * RXE bit is written, but it doesn't work at 797 * least on older hardware revs. 798 */ 799 sc->sc_stats.ast_rxeol++; 800 sc->sc_rxlink = NULL; 801 } 802 if (status & HAL_INT_TXURN) { 803 sc->sc_stats.ast_txurn++; 804 /* bump tx trigger level */ 805 ath_hal_updatetxtriglevel(ah, AH_TRUE); 806 } 807 if (status & HAL_INT_RX) 808 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 809 if (status & HAL_INT_TX) 810 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 811 if (status & HAL_INT_BMISS) { 812 sc->sc_stats.ast_bmiss++; 813 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 814 } 815 if (status & HAL_INT_MIB) { 816 sc->sc_stats.ast_mib++; 817 /* 818 * Disable interrupts until we service the MIB 819 * interrupt; otherwise it will continue to fire. 820 */ 821 ath_hal_intrset(ah, 0); 822 /* 823 * Let the hal handle the event. We assume it will 824 * clear whatever condition caused the interrupt. 825 */ 826 ath_hal_mibevent(ah, &sc->sc_halstats); 827 ath_hal_intrset(ah, sc->sc_imask); 828 } 829 } 830 return 1; 831 } 832 833 /* Swap transmit descriptor. 834 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 835 * function. 836 */ 837 static inline void 838 ath_desc_swap(struct ath_desc *ds) 839 { 840 #ifdef AH_NEED_DESC_SWAP 841 ds->ds_link = htole32(ds->ds_link); 842 ds->ds_data = htole32(ds->ds_data); 843 ds->ds_ctl0 = htole32(ds->ds_ctl0); 844 ds->ds_ctl1 = htole32(ds->ds_ctl1); 845 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 846 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 847 #endif 848 } 849 850 static void 851 ath_fatal_proc(void *arg, int pending) 852 { 853 struct ath_softc *sc = arg; 854 struct ifnet *ifp = &sc->sc_if; 855 856 if_printf(ifp, "hardware error; resetting\n"); 857 ath_reset(ifp); 858 } 859 860 static void 861 ath_rxorn_proc(void *arg, int pending) 862 { 863 struct ath_softc *sc = arg; 864 struct ifnet *ifp = &sc->sc_if; 865 866 if_printf(ifp, "rx FIFO overrun; resetting\n"); 867 ath_reset(ifp); 868 } 869 870 static void 871 ath_bmiss_proc(void *arg, int pending) 872 { 873 struct ath_softc *sc = arg; 874 struct ieee80211com *ic = &sc->sc_ic; 875 876 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 877 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 878 ("unexpect operating mode %u", ic->ic_opmode)); 879 if (ic->ic_state == IEEE80211_S_RUN) { 880 u_int64_t lastrx = sc->sc_lastrx; 881 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 882 883 DPRINTF(sc, ATH_DEBUG_BEACON, 884 "%s: tsf %" PRIu64 " lastrx %" PRId64 885 " (%" PRIu64 ") bmiss %u\n", 886 __func__, tsf, tsf - lastrx, lastrx, 887 ic->ic_bmisstimeout*1024); 888 /* 889 * Workaround phantom bmiss interrupts by sanity-checking 890 * the time of our last rx'd frame. If it is within the 891 * beacon miss interval then ignore the interrupt. If it's 892 * truly a bmiss we'll get another interrupt soon and that'll 893 * be dispatched up for processing. 894 */ 895 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 896 NET_LOCK_GIANT(); 897 ieee80211_beacon_miss(ic); 898 NET_UNLOCK_GIANT(); 899 } else 900 sc->sc_stats.ast_bmiss_phantom++; 901 } 902 } 903 904 static void 905 ath_radar_proc(void *arg, int pending) 906 { 907 #if 0 908 struct ath_softc *sc = arg; 909 struct ifnet *ifp = &sc->sc_if; 910 struct ath_hal *ah = sc->sc_ah; 911 HAL_CHANNEL hchan; 912 913 if (ath_hal_procdfs(ah, &hchan)) { 914 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 915 hchan.channel, hchan.channelFlags, hchan.privFlags); 916 /* 917 * Initiate channel change. 918 */ 919 /* XXX not yet */ 920 } 921 #endif 922 } 923 924 static u_int 925 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 926 { 927 #define N(a) (sizeof(a) / sizeof(a[0])) 928 static const u_int modeflags[] = { 929 0, /* IEEE80211_MODE_AUTO */ 930 CHANNEL_A, /* IEEE80211_MODE_11A */ 931 CHANNEL_B, /* IEEE80211_MODE_11B */ 932 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 933 0, /* IEEE80211_MODE_FH */ 934 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 935 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 936 }; 937 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 938 939 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 940 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 941 return modeflags[mode]; 942 #undef N 943 } 944 945 static int 946 ath_ifinit(struct ifnet *ifp) 947 { 948 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 949 950 return ath_init(sc); 951 } 952 953 static int 954 ath_init(struct ath_softc *sc) 955 { 956 struct ifnet *ifp = &sc->sc_if; 957 struct ieee80211com *ic = &sc->sc_ic; 958 struct ath_hal *ah = sc->sc_ah; 959 HAL_STATUS status; 960 int error = 0; 961 962 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 963 __func__, ifp->if_flags); 964 965 if (device_is_active(sc->sc_dev)) { 966 ATH_LOCK(sc); 967 } else if (!pmf_device_resume_self(sc->sc_dev)) 968 return ENXIO; 969 else 970 ATH_LOCK(sc); 971 972 /* 973 * Stop anything previously setup. This is safe 974 * whether this is the first time through or not. 975 */ 976 ath_stop_locked(ifp, 0); 977 978 int dummy; /* XXX: gcc */ 979 /* Whether we should enable h/w TKIP MIC */ 980 if ((ic->ic_caps & IEEE80211_C_WME) && 981 ((ic->ic_caps & IEEE80211_C_WME_TKIPMIC) || 982 !(ic->ic_flags & IEEE80211_F_WME))) { 983 dummy = ath_hal_settkipmic(ah, AH_TRUE); 984 } else { 985 dummy = ath_hal_settkipmic(ah, AH_FALSE); 986 } 987 988 989 /* 990 * The basic interface to setting the hardware in a good 991 * state is ``reset''. On return the hardware is known to 992 * be powered up and with interrupts disabled. This must 993 * be followed by initialization of the appropriate bits 994 * and then setup of the interrupt mask. 995 */ 996 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 997 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 998 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 999 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1000 status); 1001 error = EIO; 1002 goto done; 1003 } 1004 1005 /* 1006 * This is needed only to setup initial state 1007 * but it's best done after a reset. 1008 */ 1009 ath_update_txpow(sc); 1010 /* 1011 * Likewise this is set during reset so update 1012 * state cached in the driver. 1013 */ 1014 ath_restore_diversity(sc); 1015 sc->sc_calinterval = 1; 1016 sc->sc_caltries = 0; 1017 1018 /* 1019 * Setup the hardware after reset: the key cache 1020 * is filled as needed and the receive engine is 1021 * set going. Frame transmit is handled entirely 1022 * in the frame output path; there's nothing to do 1023 * here except setup the interrupt mask. 1024 */ 1025 if ((error = ath_startrecv(sc)) != 0) { 1026 if_printf(ifp, "unable to start recv logic\n"); 1027 goto done; 1028 } 1029 1030 /* 1031 * Enable interrupts. 1032 */ 1033 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1034 | HAL_INT_RXEOL | HAL_INT_RXORN 1035 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1036 /* 1037 * Enable MIB interrupts when there are hardware phy counters. 1038 * Note we only do this (at the moment) for station mode. 1039 */ 1040 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1041 sc->sc_imask |= HAL_INT_MIB; 1042 ath_hal_intrset(ah, sc->sc_imask); 1043 1044 ifp->if_flags |= IFF_RUNNING; 1045 ic->ic_state = IEEE80211_S_INIT; 1046 1047 /* 1048 * The hardware should be ready to go now so it's safe 1049 * to kick the 802.11 state machine as it's likely to 1050 * immediately call back to us to send mgmt frames. 1051 */ 1052 ath_chan_change(sc, ic->ic_curchan); 1053 #ifdef ATH_TX99_DIAG 1054 if (sc->sc_tx99 != NULL) 1055 sc->sc_tx99->start(sc->sc_tx99); 1056 else 1057 #endif 1058 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1059 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1060 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1061 } else 1062 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1063 done: 1064 ATH_UNLOCK(sc); 1065 return error; 1066 } 1067 1068 static void 1069 ath_stop_locked(struct ifnet *ifp, int disable) 1070 { 1071 struct ath_softc *sc = ifp->if_softc; 1072 struct ieee80211com *ic = &sc->sc_ic; 1073 struct ath_hal *ah = sc->sc_ah; 1074 1075 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1076 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1077 1078 ATH_LOCK_ASSERT(sc); 1079 if (ifp->if_flags & IFF_RUNNING) { 1080 /* 1081 * Shutdown the hardware and driver: 1082 * reset 802.11 state machine 1083 * turn off timers 1084 * disable interrupts 1085 * turn off the radio 1086 * clear transmit machinery 1087 * clear receive machinery 1088 * drain and release tx queues 1089 * reclaim beacon resources 1090 * power down hardware 1091 * 1092 * Note that some of this work is not possible if the 1093 * hardware is gone (invalid). 1094 */ 1095 #ifdef ATH_TX99_DIAG 1096 if (sc->sc_tx99 != NULL) 1097 sc->sc_tx99->stop(sc->sc_tx99); 1098 #endif 1099 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1100 ifp->if_flags &= ~IFF_RUNNING; 1101 ifp->if_timer = 0; 1102 if (device_is_enabled(sc->sc_dev)) { 1103 if (sc->sc_softled) { 1104 callout_stop(&sc->sc_ledtimer); 1105 ath_hal_gpioset(ah, sc->sc_ledpin, 1106 !sc->sc_ledon); 1107 sc->sc_blinking = 0; 1108 } 1109 ath_hal_intrset(ah, 0); 1110 } 1111 ath_draintxq(sc); 1112 if (device_is_enabled(sc->sc_dev)) { 1113 ath_stoprecv(sc); 1114 ath_hal_phydisable(ah); 1115 } else 1116 sc->sc_rxlink = NULL; 1117 IF_PURGE(&ifp->if_snd); 1118 ath_beacon_free(sc); 1119 if (disable) 1120 pmf_device_suspend_self(sc->sc_dev); 1121 } 1122 } 1123 1124 static void 1125 ath_stop(struct ifnet *ifp, int disable) 1126 { 1127 struct ath_softc *sc = ifp->if_softc; 1128 1129 ATH_LOCK(sc); 1130 ath_stop_locked(ifp, disable); 1131 ATH_UNLOCK(sc); 1132 } 1133 1134 static void 1135 ath_restore_diversity(struct ath_softc *sc) 1136 { 1137 struct ifnet *ifp = &sc->sc_if; 1138 struct ath_hal *ah = sc->sc_ah; 1139 1140 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1141 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1142 if_printf(ifp, "could not restore diversity setting %d\n", 1143 sc->sc_diversity); 1144 sc->sc_diversity = ath_hal_getdiversity(ah); 1145 } 1146 } 1147 1148 /* 1149 * Reset the hardware w/o losing operational state. This is 1150 * basically a more efficient way of doing ath_stop, ath_init, 1151 * followed by state transitions to the current 802.11 1152 * operational state. Used to recover from various errors and 1153 * to reset or reload hardware state. 1154 */ 1155 int 1156 ath_reset(struct ifnet *ifp) 1157 { 1158 struct ath_softc *sc = ifp->if_softc; 1159 struct ieee80211com *ic = &sc->sc_ic; 1160 struct ath_hal *ah = sc->sc_ah; 1161 struct ieee80211_channel *c; 1162 HAL_STATUS status; 1163 1164 /* 1165 * Convert to a HAL channel description with the flags 1166 * constrained to reflect the current operating mode. 1167 */ 1168 c = ic->ic_curchan; 1169 sc->sc_curchan.channel = c->ic_freq; 1170 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1171 1172 ath_hal_intrset(ah, 0); /* disable interrupts */ 1173 ath_draintxq(sc); /* stop xmit side */ 1174 ath_stoprecv(sc); /* stop recv side */ 1175 /* NB: indicate channel change so we do a full reset */ 1176 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1177 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1178 __func__, status); 1179 ath_update_txpow(sc); /* update tx power state */ 1180 ath_restore_diversity(sc); 1181 sc->sc_calinterval = 1; 1182 sc->sc_caltries = 0; 1183 if (ath_startrecv(sc) != 0) /* restart recv */ 1184 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1185 /* 1186 * We may be doing a reset in response to an ioctl 1187 * that changes the channel so update any state that 1188 * might change as a result. 1189 */ 1190 ath_chan_change(sc, c); 1191 if (ic->ic_state == IEEE80211_S_RUN) 1192 ath_beacon_config(sc); /* restart beacons */ 1193 ath_hal_intrset(ah, sc->sc_imask); 1194 1195 ath_start(ifp); /* restart xmit */ 1196 return 0; 1197 } 1198 1199 /* 1200 * Cleanup driver resources when we run out of buffers 1201 * while processing fragments; return the tx buffers 1202 * allocated and drop node references. 1203 */ 1204 static void 1205 ath_txfrag_cleanup(struct ath_softc *sc, 1206 ath_bufhead *frags, struct ieee80211_node *ni) 1207 { 1208 struct ath_buf *bf; 1209 1210 ATH_TXBUF_LOCK_ASSERT(sc); 1211 1212 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1213 STAILQ_REMOVE_HEAD(frags, bf_list); 1214 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1215 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1216 ieee80211_node_decref(ni); 1217 } 1218 } 1219 1220 /* 1221 * Setup xmit of a fragmented frame. Allocate a buffer 1222 * for each frag and bump the node reference count to 1223 * reflect the held reference to be setup by ath_tx_start. 1224 */ 1225 static int 1226 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1227 struct mbuf *m0, struct ieee80211_node *ni) 1228 { 1229 struct mbuf *m; 1230 struct ath_buf *bf; 1231 1232 ATH_TXBUF_LOCK(sc); 1233 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1234 bf = STAILQ_FIRST(&sc->sc_txbuf); 1235 if (bf == NULL) { /* out of buffers, cleanup */ 1236 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1237 __func__); 1238 sc->sc_if.if_flags |= IFF_OACTIVE; 1239 ath_txfrag_cleanup(sc, frags, ni); 1240 break; 1241 } 1242 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1243 ieee80211_node_incref(ni); 1244 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1245 } 1246 ATH_TXBUF_UNLOCK(sc); 1247 1248 return !STAILQ_EMPTY(frags); 1249 } 1250 1251 static void 1252 ath_start(struct ifnet *ifp) 1253 { 1254 struct ath_softc *sc = ifp->if_softc; 1255 struct ath_hal *ah = sc->sc_ah; 1256 struct ieee80211com *ic = &sc->sc_ic; 1257 struct ieee80211_node *ni; 1258 struct ath_buf *bf; 1259 struct mbuf *m, *next; 1260 struct ieee80211_frame *wh; 1261 struct ether_header *eh; 1262 ath_bufhead frags; 1263 1264 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1265 !device_is_active(sc->sc_dev)) 1266 return; 1267 for (;;) { 1268 /* 1269 * Grab a TX buffer and associated resources. 1270 */ 1271 ATH_TXBUF_LOCK(sc); 1272 bf = STAILQ_FIRST(&sc->sc_txbuf); 1273 if (bf != NULL) 1274 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1275 ATH_TXBUF_UNLOCK(sc); 1276 if (bf == NULL) { 1277 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1278 __func__); 1279 sc->sc_stats.ast_tx_qstop++; 1280 ifp->if_flags |= IFF_OACTIVE; 1281 break; 1282 } 1283 /* 1284 * Poll the management queue for frames; they 1285 * have priority over normal data frames. 1286 */ 1287 IF_DEQUEUE(&ic->ic_mgtq, m); 1288 if (m == NULL) { 1289 /* 1290 * No data frames go out unless we're associated. 1291 */ 1292 if (ic->ic_state != IEEE80211_S_RUN) { 1293 DPRINTF(sc, ATH_DEBUG_XMIT, 1294 "%s: discard data packet, state %s\n", 1295 __func__, 1296 ieee80211_state_name[ic->ic_state]); 1297 sc->sc_stats.ast_tx_discard++; 1298 ATH_TXBUF_LOCK(sc); 1299 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1300 ATH_TXBUF_UNLOCK(sc); 1301 break; 1302 } 1303 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1304 if (m == NULL) { 1305 ATH_TXBUF_LOCK(sc); 1306 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1307 ATH_TXBUF_UNLOCK(sc); 1308 break; 1309 } 1310 STAILQ_INIT(&frags); 1311 /* 1312 * Find the node for the destination so we can do 1313 * things like power save and fast frames aggregation. 1314 */ 1315 if (m->m_len < sizeof(struct ether_header) && 1316 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1317 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1318 ni = NULL; 1319 goto bad; 1320 } 1321 eh = mtod(m, struct ether_header *); 1322 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1323 if (ni == NULL) { 1324 /* NB: ieee80211_find_txnode does stat+msg */ 1325 m_freem(m); 1326 goto bad; 1327 } 1328 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1329 (m->m_flags & M_PWR_SAV) == 0) { 1330 /* 1331 * Station in power save mode; pass the frame 1332 * to the 802.11 layer and continue. We'll get 1333 * the frame back when the time is right. 1334 */ 1335 ieee80211_pwrsave(ic, ni, m); 1336 goto reclaim; 1337 } 1338 /* calculate priority so we can find the tx queue */ 1339 if (ieee80211_classify(ic, m, ni)) { 1340 DPRINTF(sc, ATH_DEBUG_XMIT, 1341 "%s: discard, classification failure\n", 1342 __func__); 1343 m_freem(m); 1344 goto bad; 1345 } 1346 ifp->if_opackets++; 1347 1348 #if NBPFILTER > 0 1349 if (ifp->if_bpf) 1350 bpf_mtap(ifp->if_bpf, m); 1351 #endif 1352 /* 1353 * Encapsulate the packet in prep for transmission. 1354 */ 1355 m = ieee80211_encap(ic, m, ni); 1356 if (m == NULL) { 1357 DPRINTF(sc, ATH_DEBUG_XMIT, 1358 "%s: encapsulation failure\n", 1359 __func__); 1360 sc->sc_stats.ast_tx_encap++; 1361 goto bad; 1362 } 1363 /* 1364 * Check for fragmentation. If this has frame 1365 * has been broken up verify we have enough 1366 * buffers to send all the fragments so all 1367 * go out or none... 1368 */ 1369 if ((m->m_flags & M_FRAG) && 1370 !ath_txfrag_setup(sc, &frags, m, ni)) { 1371 DPRINTF(sc, ATH_DEBUG_ANY, 1372 "%s: out of txfrag buffers\n", __func__); 1373 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1374 ath_freetx(m); 1375 goto bad; 1376 } 1377 } else { 1378 /* 1379 * Hack! The referenced node pointer is in the 1380 * rcvif field of the packet header. This is 1381 * placed there by ieee80211_mgmt_output because 1382 * we need to hold the reference with the frame 1383 * and there's no other way (other than packet 1384 * tags which we consider too expensive to use) 1385 * to pass it along. 1386 */ 1387 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1388 m->m_pkthdr.rcvif = NULL; 1389 1390 wh = mtod(m, struct ieee80211_frame *); 1391 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1392 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1393 /* fill time stamp */ 1394 u_int64_t tsf; 1395 u_int32_t *tstamp; 1396 1397 tsf = ath_hal_gettsf64(ah); 1398 /* XXX: adjust 100us delay to xmit */ 1399 tsf += 100; 1400 tstamp = (u_int32_t *)&wh[1]; 1401 tstamp[0] = htole32(tsf & 0xffffffff); 1402 tstamp[1] = htole32(tsf >> 32); 1403 } 1404 sc->sc_stats.ast_tx_mgmt++; 1405 } 1406 1407 nextfrag: 1408 next = m->m_nextpkt; 1409 if (ath_tx_start(sc, ni, bf, m)) { 1410 bad: 1411 ifp->if_oerrors++; 1412 reclaim: 1413 ATH_TXBUF_LOCK(sc); 1414 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1415 ath_txfrag_cleanup(sc, &frags, ni); 1416 ATH_TXBUF_UNLOCK(sc); 1417 if (ni != NULL) 1418 ieee80211_free_node(ni); 1419 continue; 1420 } 1421 if (next != NULL) { 1422 m = next; 1423 bf = STAILQ_FIRST(&frags); 1424 KASSERT(bf != NULL, ("no buf for txfrag")); 1425 STAILQ_REMOVE_HEAD(&frags, bf_list); 1426 goto nextfrag; 1427 } 1428 1429 ifp->if_timer = 1; 1430 } 1431 } 1432 1433 static int 1434 ath_media_change(struct ifnet *ifp) 1435 { 1436 #define IS_UP(ifp) \ 1437 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1438 int error; 1439 1440 error = ieee80211_media_change(ifp); 1441 if (error == ENETRESET) { 1442 if (IS_UP(ifp)) 1443 ath_init(ifp->if_softc); /* XXX lose error */ 1444 error = 0; 1445 } 1446 return error; 1447 #undef IS_UP 1448 } 1449 1450 #ifdef AR_DEBUG 1451 static void 1452 ath_keyprint(const char *tag, u_int ix, 1453 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1454 { 1455 static const char *ciphers[] = { 1456 "WEP", 1457 "AES-OCB", 1458 "AES-CCM", 1459 "CKIP", 1460 "TKIP", 1461 "CLR", 1462 }; 1463 int i, n; 1464 1465 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1466 for (i = 0, n = hk->kv_len; i < n; i++) 1467 printf("%02x", hk->kv_val[i]); 1468 printf(" mac %s", ether_sprintf(mac)); 1469 if (hk->kv_type == HAL_CIPHER_TKIP) { 1470 printf(" mic "); 1471 for (i = 0; i < sizeof(hk->kv_mic); i++) 1472 printf("%02x", hk->kv_mic[i]); 1473 } 1474 printf("\n"); 1475 } 1476 #endif 1477 1478 /* 1479 * Set a TKIP key into the hardware. This handles the 1480 * potential distribution of key state to multiple key 1481 * cache slots for TKIP. 1482 */ 1483 static int 1484 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1485 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1486 { 1487 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1488 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1489 struct ath_hal *ah = sc->sc_ah; 1490 1491 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1492 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1493 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1494 if (sc->sc_splitmic) { 1495 /* 1496 * TX key goes at first index, RX key at the rx index. 1497 * The hal handles the MIC keys at index+64. 1498 */ 1499 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1500 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1501 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1502 zerobssid)) 1503 return 0; 1504 1505 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1506 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1507 /* XXX delete tx key on failure? */ 1508 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1509 hk, mac); 1510 } else { 1511 /* 1512 * Room for both TX+RX MIC keys in one key cache 1513 * slot, just set key at the first index; the HAL 1514 * will handle the reset. 1515 */ 1516 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1517 #if HAL_ABI_VERSION > 0x06052200 1518 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1519 #endif 1520 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1521 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1522 } 1523 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1524 /* 1525 * TX/RX key goes at first index. 1526 * The hal handles the MIC keys are index+64. 1527 */ 1528 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1529 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1530 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1531 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1532 } 1533 return 0; 1534 #undef IEEE80211_KEY_XR 1535 } 1536 1537 /* 1538 * Set a net80211 key into the hardware. This handles the 1539 * potential distribution of key state to multiple key 1540 * cache slots for TKIP with hardware MIC support. 1541 */ 1542 static int 1543 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1544 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1545 struct ieee80211_node *bss) 1546 { 1547 #define N(a) (sizeof(a)/sizeof(a[0])) 1548 static const u_int8_t ciphermap[] = { 1549 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1550 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1551 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1552 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1553 (u_int8_t) -1, /* 4 is not allocated */ 1554 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1555 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1556 }; 1557 struct ath_hal *ah = sc->sc_ah; 1558 const struct ieee80211_cipher *cip = k->wk_cipher; 1559 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1560 const u_int8_t *mac; 1561 HAL_KEYVAL hk; 1562 1563 memset(&hk, 0, sizeof(hk)); 1564 /* 1565 * Software crypto uses a "clear key" so non-crypto 1566 * state kept in the key cache are maintained and 1567 * so that rx frames have an entry to match. 1568 */ 1569 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1570 KASSERT(cip->ic_cipher < N(ciphermap), 1571 ("invalid cipher type %u", cip->ic_cipher)); 1572 hk.kv_type = ciphermap[cip->ic_cipher]; 1573 hk.kv_len = k->wk_keylen; 1574 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1575 } else 1576 hk.kv_type = HAL_CIPHER_CLR; 1577 1578 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1579 /* 1580 * Group keys on hardware that supports multicast frame 1581 * key search use a mac that is the sender's address with 1582 * the high bit set instead of the app-specified address. 1583 */ 1584 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1585 gmac[0] |= 0x80; 1586 mac = gmac; 1587 } else 1588 mac = mac0; 1589 1590 if ((hk.kv_type == HAL_CIPHER_TKIP && 1591 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) && sc->sc_splitmic) { 1592 return ath_keyset_tkip(sc, k, &hk, mac); 1593 } else { 1594 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1595 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1596 } 1597 #undef N 1598 } 1599 1600 /* 1601 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1602 * each key, one for decrypt/encrypt and the other for the MIC. 1603 */ 1604 static u_int16_t 1605 key_alloc_2pair(struct ath_softc *sc, 1606 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1607 { 1608 #define N(a) (sizeof(a)/sizeof(a[0])) 1609 u_int i, keyix; 1610 1611 KASSERT(sc->sc_splitmic, ("key cache !split")); 1612 /* XXX could optimize */ 1613 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1614 u_int8_t b = sc->sc_keymap[i]; 1615 if (b != 0xff) { 1616 /* 1617 * One or more slots in this byte are free. 1618 */ 1619 keyix = i*NBBY; 1620 while (b & 1) { 1621 again: 1622 keyix++; 1623 b >>= 1; 1624 } 1625 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1626 if (isset(sc->sc_keymap, keyix+32) || 1627 isset(sc->sc_keymap, keyix+64) || 1628 isset(sc->sc_keymap, keyix+32+64)) { 1629 /* full pair unavailable */ 1630 /* XXX statistic */ 1631 if (keyix == (i+1)*NBBY) { 1632 /* no slots were appropriate, advance */ 1633 continue; 1634 } 1635 goto again; 1636 } 1637 setbit(sc->sc_keymap, keyix); 1638 setbit(sc->sc_keymap, keyix+64); 1639 setbit(sc->sc_keymap, keyix+32); 1640 setbit(sc->sc_keymap, keyix+32+64); 1641 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1642 "%s: key pair %u,%u %u,%u\n", 1643 __func__, keyix, keyix+64, 1644 keyix+32, keyix+32+64); 1645 *txkeyix = keyix; 1646 *rxkeyix = keyix+32; 1647 return keyix; 1648 } 1649 } 1650 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1651 return IEEE80211_KEYIX_NONE; 1652 #undef N 1653 } 1654 1655 /* 1656 * Allocate a single key cache slot. 1657 */ 1658 static int 1659 key_alloc_single(struct ath_softc *sc, 1660 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1661 { 1662 #define N(a) (sizeof(a)/sizeof(a[0])) 1663 u_int i, keyix; 1664 1665 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1666 for (i = 0; i < N(sc->sc_keymap); i++) { 1667 u_int8_t b = sc->sc_keymap[i]; 1668 if (b != 0xff) { 1669 /* 1670 * One or more slots are free. 1671 */ 1672 keyix = i*NBBY; 1673 while (b & 1) 1674 keyix++, b >>= 1; 1675 setbit(sc->sc_keymap, keyix); 1676 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1677 __func__, keyix); 1678 *txkeyix = *rxkeyix = keyix; 1679 return 1; 1680 } 1681 } 1682 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1683 return 0; 1684 #undef N 1685 } 1686 1687 /* 1688 * Allocate one or more key cache slots for a uniacst key. The 1689 * key itself is needed only to identify the cipher. For hardware 1690 * TKIP with split cipher+MIC keys we allocate two key cache slot 1691 * pairs so that we can setup separate TX and RX MIC keys. Note 1692 * that the MIC key for a TKIP key at slot i is assumed by the 1693 * hardware to be at slot i+64. This limits TKIP keys to the first 1694 * 64 entries. 1695 */ 1696 static int 1697 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1698 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1699 { 1700 struct ath_softc *sc = ic->ic_ifp->if_softc; 1701 1702 /* 1703 * Group key allocation must be handled specially for 1704 * parts that do not support multicast key cache search 1705 * functionality. For those parts the key id must match 1706 * the h/w key index so lookups find the right key. On 1707 * parts w/ the key search facility we install the sender's 1708 * mac address (with the high bit set) and let the hardware 1709 * find the key w/o using the key id. This is preferred as 1710 * it permits us to support multiple users for adhoc and/or 1711 * multi-station operation. 1712 */ 1713 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1714 if (!(&ic->ic_nw_keys[0] <= k && 1715 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1716 /* should not happen */ 1717 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1718 "%s: bogus group key\n", __func__); 1719 return 0; 1720 } 1721 /* 1722 * XXX we pre-allocate the global keys so 1723 * have no way to check if they've already been allocated. 1724 */ 1725 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1726 return 1; 1727 } 1728 1729 /* 1730 * We allocate two pair for TKIP when using the h/w to do 1731 * the MIC. For everything else, including software crypto, 1732 * we allocate a single entry. Note that s/w crypto requires 1733 * a pass-through slot on the 5211 and 5212. The 5210 does 1734 * not support pass-through cache entries and we map all 1735 * those requests to slot 0. 1736 */ 1737 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1738 return key_alloc_single(sc, keyix, rxkeyix); 1739 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1740 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1741 return key_alloc_2pair(sc, keyix, rxkeyix); 1742 } else { 1743 return key_alloc_single(sc, keyix, rxkeyix); 1744 } 1745 } 1746 1747 /* 1748 * Delete an entry in the key cache allocated by ath_key_alloc. 1749 */ 1750 static int 1751 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1752 { 1753 struct ath_softc *sc = ic->ic_ifp->if_softc; 1754 struct ath_hal *ah = sc->sc_ah; 1755 const struct ieee80211_cipher *cip = k->wk_cipher; 1756 u_int keyix = k->wk_keyix; 1757 1758 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1759 1760 if (!device_has_power(sc->sc_dev)) { 1761 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1762 k->wk_keyix); 1763 } 1764 1765 ath_hal_keyreset(ah, keyix); 1766 /* 1767 * Handle split tx/rx keying required for TKIP with h/w MIC. 1768 */ 1769 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1770 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1771 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1772 if (keyix >= IEEE80211_WEP_NKID) { 1773 /* 1774 * Don't touch keymap entries for global keys so 1775 * they are never considered for dynamic allocation. 1776 */ 1777 clrbit(sc->sc_keymap, keyix); 1778 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1779 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1780 sc->sc_splitmic) { 1781 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1782 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1783 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1784 } 1785 } 1786 return 1; 1787 } 1788 1789 /* 1790 * Set the key cache contents for the specified key. Key cache 1791 * slot(s) must already have been allocated by ath_key_alloc. 1792 */ 1793 static int 1794 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1795 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1796 { 1797 struct ath_softc *sc = ic->ic_ifp->if_softc; 1798 1799 if (!device_has_power(sc->sc_dev)) { 1800 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1801 k->wk_keyix); 1802 } 1803 return ath_keyset(sc, k, mac, ic->ic_bss); 1804 } 1805 1806 /* 1807 * Block/unblock tx+rx processing while a key change is done. 1808 * We assume the caller serializes key management operations 1809 * so we only need to worry about synchronization with other 1810 * uses that originate in the driver. 1811 */ 1812 static void 1813 ath_key_update_begin(struct ieee80211com *ic) 1814 { 1815 struct ifnet *ifp = ic->ic_ifp; 1816 struct ath_softc *sc = ifp->if_softc; 1817 1818 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1819 #if 0 1820 tasklet_disable(&sc->sc_rxtq); 1821 #endif 1822 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1823 } 1824 1825 static void 1826 ath_key_update_end(struct ieee80211com *ic) 1827 { 1828 struct ifnet *ifp = ic->ic_ifp; 1829 struct ath_softc *sc = ifp->if_softc; 1830 1831 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1832 IF_UNLOCK(&ifp->if_snd); 1833 #if 0 1834 tasklet_enable(&sc->sc_rxtq); 1835 #endif 1836 } 1837 1838 /* 1839 * Calculate the receive filter according to the 1840 * operating mode and state: 1841 * 1842 * o always accept unicast, broadcast, and multicast traffic 1843 * o maintain current state of phy error reception (the hal 1844 * may enable phy error frames for noise immunity work) 1845 * o probe request frames are accepted only when operating in 1846 * hostap, adhoc, or monitor modes 1847 * o enable promiscuous mode according to the interface state 1848 * o accept beacons: 1849 * - when operating in adhoc mode so the 802.11 layer creates 1850 * node table entries for peers, 1851 * - when operating in station mode for collecting rssi data when 1852 * the station is otherwise quiet, or 1853 * - when scanning 1854 */ 1855 static u_int32_t 1856 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1857 { 1858 struct ieee80211com *ic = &sc->sc_ic; 1859 struct ath_hal *ah = sc->sc_ah; 1860 struct ifnet *ifp = &sc->sc_if; 1861 u_int32_t rfilt; 1862 1863 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1864 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1865 if (ic->ic_opmode != IEEE80211_M_STA) 1866 rfilt |= HAL_RX_FILTER_PROBEREQ; 1867 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1868 (ifp->if_flags & IFF_PROMISC)) 1869 rfilt |= HAL_RX_FILTER_PROM; 1870 if (ifp->if_flags & IFF_PROMISC) 1871 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1872 if (ic->ic_opmode == IEEE80211_M_STA || 1873 ic->ic_opmode == IEEE80211_M_IBSS || 1874 state == IEEE80211_S_SCAN) 1875 rfilt |= HAL_RX_FILTER_BEACON; 1876 return rfilt; 1877 } 1878 1879 static void 1880 ath_mode_init(struct ath_softc *sc) 1881 { 1882 struct ifnet *ifp = &sc->sc_if; 1883 struct ieee80211com *ic = &sc->sc_ic; 1884 struct ath_hal *ah = sc->sc_ah; 1885 struct ether_multi *enm; 1886 struct ether_multistep estep; 1887 u_int32_t rfilt, mfilt[2], val; 1888 int i; 1889 uint8_t pos; 1890 1891 /* configure rx filter */ 1892 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1893 ath_hal_setrxfilter(ah, rfilt); 1894 1895 /* configure operational mode */ 1896 ath_hal_setopmode(ah); 1897 1898 /* Write keys to hardware; it may have been powered down. */ 1899 ath_key_update_begin(ic); 1900 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1901 ath_key_set(ic, 1902 &ic->ic_crypto.cs_nw_keys[i], 1903 ic->ic_myaddr); 1904 } 1905 ath_key_update_end(ic); 1906 1907 /* 1908 * Handle any link-level address change. Note that we only 1909 * need to force ic_myaddr; any other addresses are handled 1910 * as a byproduct of the ifnet code marking the interface 1911 * down then up. 1912 * 1913 * XXX should get from lladdr instead of arpcom but that's more work 1914 */ 1915 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 1916 ath_hal_setmac(ah, ic->ic_myaddr); 1917 1918 /* calculate and install multicast filter */ 1919 ifp->if_flags &= ~IFF_ALLMULTI; 1920 mfilt[0] = mfilt[1] = 0; 1921 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1922 while (enm != NULL) { 1923 void *dl; 1924 /* XXX Punt on ranges. */ 1925 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1926 mfilt[0] = mfilt[1] = 0xffffffff; 1927 ifp->if_flags |= IFF_ALLMULTI; 1928 break; 1929 } 1930 dl = enm->enm_addrlo; 1931 val = LE_READ_4((char *)dl + 0); 1932 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1933 val = LE_READ_4((char *)dl + 3); 1934 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1935 pos &= 0x3f; 1936 mfilt[pos / 32] |= (1 << (pos % 32)); 1937 1938 ETHER_NEXT_MULTI(estep, enm); 1939 } 1940 1941 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1942 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1943 __func__, rfilt, mfilt[0], mfilt[1]); 1944 } 1945 1946 /* 1947 * Set the slot time based on the current setting. 1948 */ 1949 static void 1950 ath_setslottime(struct ath_softc *sc) 1951 { 1952 struct ieee80211com *ic = &sc->sc_ic; 1953 struct ath_hal *ah = sc->sc_ah; 1954 1955 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1956 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1957 else 1958 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1959 sc->sc_updateslot = OK; 1960 } 1961 1962 /* 1963 * Callback from the 802.11 layer to update the 1964 * slot time based on the current setting. 1965 */ 1966 static void 1967 ath_updateslot(struct ifnet *ifp) 1968 { 1969 struct ath_softc *sc = ifp->if_softc; 1970 struct ieee80211com *ic = &sc->sc_ic; 1971 1972 /* 1973 * When not coordinating the BSS, change the hardware 1974 * immediately. For other operation we defer the change 1975 * until beacon updates have propagated to the stations. 1976 */ 1977 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1978 sc->sc_updateslot = UPDATE; 1979 else 1980 ath_setslottime(sc); 1981 } 1982 1983 /* 1984 * Setup a h/w transmit queue for beacons. 1985 */ 1986 static int 1987 ath_beaconq_setup(struct ath_hal *ah) 1988 { 1989 HAL_TXQ_INFO qi; 1990 1991 memset(&qi, 0, sizeof(qi)); 1992 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1993 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1994 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1995 /* NB: for dynamic turbo, don't enable any other interrupts */ 1996 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 1997 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1998 } 1999 2000 /* 2001 * Setup the transmit queue parameters for the beacon queue. 2002 */ 2003 static int 2004 ath_beaconq_config(struct ath_softc *sc) 2005 { 2006 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2007 struct ieee80211com *ic = &sc->sc_ic; 2008 struct ath_hal *ah = sc->sc_ah; 2009 HAL_TXQ_INFO qi; 2010 2011 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2012 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2013 /* 2014 * Always burst out beacon and CAB traffic. 2015 */ 2016 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2017 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2018 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2019 } else { 2020 struct wmeParams *wmep = 2021 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2022 /* 2023 * Adhoc mode; important thing is to use 2x cwmin. 2024 */ 2025 qi.tqi_aifs = wmep->wmep_aifsn; 2026 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2027 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2028 } 2029 2030 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2031 device_printf(sc->sc_dev, "unable to update parameters for " 2032 "beacon hardware queue!\n"); 2033 return 0; 2034 } else { 2035 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2036 return 1; 2037 } 2038 #undef ATH_EXPONENT_TO_VALUE 2039 } 2040 2041 /* 2042 * Allocate and setup an initial beacon frame. 2043 */ 2044 static int 2045 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2046 { 2047 struct ieee80211com *ic = ni->ni_ic; 2048 struct ath_buf *bf; 2049 struct mbuf *m; 2050 int error; 2051 2052 bf = STAILQ_FIRST(&sc->sc_bbuf); 2053 if (bf == NULL) { 2054 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2055 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2056 return ENOMEM; /* XXX */ 2057 } 2058 /* 2059 * NB: the beacon data buffer must be 32-bit aligned; 2060 * we assume the mbuf routines will return us something 2061 * with this alignment (perhaps should assert). 2062 */ 2063 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2064 if (m == NULL) { 2065 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2066 __func__); 2067 sc->sc_stats.ast_be_nombuf++; 2068 return ENOMEM; 2069 } 2070 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2071 BUS_DMA_NOWAIT); 2072 if (error == 0) { 2073 bf->bf_m = m; 2074 bf->bf_node = ieee80211_ref_node(ni); 2075 } else { 2076 m_freem(m); 2077 } 2078 return error; 2079 } 2080 2081 /* 2082 * Setup the beacon frame for transmit. 2083 */ 2084 static void 2085 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2086 { 2087 #define USE_SHPREAMBLE(_ic) \ 2088 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2089 == IEEE80211_F_SHPREAMBLE) 2090 struct ieee80211_node *ni = bf->bf_node; 2091 struct ieee80211com *ic = ni->ni_ic; 2092 struct mbuf *m = bf->bf_m; 2093 struct ath_hal *ah = sc->sc_ah; 2094 struct ath_desc *ds; 2095 int flags, antenna; 2096 const HAL_RATE_TABLE *rt; 2097 u_int8_t rix, rate; 2098 2099 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2100 __func__, m, m->m_len); 2101 2102 /* setup descriptors */ 2103 ds = bf->bf_desc; 2104 2105 flags = HAL_TXDESC_NOACK; 2106 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2107 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2108 flags |= HAL_TXDESC_VEOL; 2109 /* 2110 * Let hardware handle antenna switching unless 2111 * the user has selected a transmit antenna 2112 * (sc_txantenna is not 0). 2113 */ 2114 antenna = sc->sc_txantenna; 2115 } else { 2116 ds->ds_link = 0; 2117 /* 2118 * Switch antenna every 4 beacons, unless the user 2119 * has selected a transmit antenna (sc_txantenna 2120 * is not 0). 2121 * 2122 * XXX assumes two antenna 2123 */ 2124 if (sc->sc_txantenna == 0) 2125 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2126 else 2127 antenna = sc->sc_txantenna; 2128 } 2129 2130 KASSERT(bf->bf_nseg == 1, 2131 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2132 ds->ds_data = bf->bf_segs[0].ds_addr; 2133 /* 2134 * Calculate rate code. 2135 * XXX everything at min xmit rate 2136 */ 2137 rix = sc->sc_minrateix; 2138 rt = sc->sc_currates; 2139 rate = rt->info[rix].rateCode; 2140 if (USE_SHPREAMBLE(ic)) 2141 rate |= rt->info[rix].shortPreamble; 2142 ath_hal_setuptxdesc(ah, ds 2143 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2144 , sizeof(struct ieee80211_frame)/* header length */ 2145 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2146 , ni->ni_txpower /* txpower XXX */ 2147 , rate, 1 /* series 0 rate/tries */ 2148 , HAL_TXKEYIX_INVALID /* no encryption */ 2149 , antenna /* antenna mode */ 2150 , flags /* no ack, veol for beacons */ 2151 , 0 /* rts/cts rate */ 2152 , 0 /* rts/cts duration */ 2153 ); 2154 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2155 ath_hal_filltxdesc(ah, ds 2156 , roundup(m->m_len, 4) /* buffer length */ 2157 , AH_TRUE /* first segment */ 2158 , AH_TRUE /* last segment */ 2159 , ds /* first descriptor */ 2160 ); 2161 2162 /* NB: The desc swap function becomes void, if descriptor swapping 2163 * is not enabled 2164 */ 2165 ath_desc_swap(ds); 2166 2167 #undef USE_SHPREAMBLE 2168 } 2169 2170 /* 2171 * Transmit a beacon frame at SWBA. Dynamic updates to the 2172 * frame contents are done as needed and the slot time is 2173 * also adjusted based on current state. 2174 */ 2175 static void 2176 ath_beacon_proc(void *arg, int pending) 2177 { 2178 struct ath_softc *sc = arg; 2179 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2180 struct ieee80211_node *ni = bf->bf_node; 2181 struct ieee80211com *ic = ni->ni_ic; 2182 struct ath_hal *ah = sc->sc_ah; 2183 struct mbuf *m; 2184 int ncabq, error, otherant; 2185 2186 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2187 __func__, pending); 2188 2189 if (ic->ic_opmode == IEEE80211_M_STA || 2190 ic->ic_opmode == IEEE80211_M_MONITOR || 2191 bf == NULL || bf->bf_m == NULL) { 2192 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2193 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2194 return; 2195 } 2196 /* 2197 * Check if the previous beacon has gone out. If 2198 * not don't try to post another, skip this period 2199 * and wait for the next. Missed beacons indicate 2200 * a problem and should not occur. If we miss too 2201 * many consecutive beacons reset the device. 2202 */ 2203 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2204 sc->sc_bmisscount++; 2205 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2206 "%s: missed %u consecutive beacons\n", 2207 __func__, sc->sc_bmisscount); 2208 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2209 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2210 return; 2211 } 2212 if (sc->sc_bmisscount != 0) { 2213 DPRINTF(sc, ATH_DEBUG_BEACON, 2214 "%s: resume beacon xmit after %u misses\n", 2215 __func__, sc->sc_bmisscount); 2216 sc->sc_bmisscount = 0; 2217 } 2218 2219 /* 2220 * Update dynamic beacon contents. If this returns 2221 * non-zero then we need to remap the memory because 2222 * the beacon frame changed size (probably because 2223 * of the TIM bitmap). 2224 */ 2225 m = bf->bf_m; 2226 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2227 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2228 /* XXX too conservative? */ 2229 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2230 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2231 BUS_DMA_NOWAIT); 2232 if (error != 0) { 2233 if_printf(&sc->sc_if, 2234 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2235 __func__, error); 2236 return; 2237 } 2238 } 2239 2240 /* 2241 * Handle slot time change when a non-ERP station joins/leaves 2242 * an 11g network. The 802.11 layer notifies us via callback, 2243 * we mark updateslot, then wait one beacon before effecting 2244 * the change. This gives associated stations at least one 2245 * beacon interval to note the state change. 2246 */ 2247 /* XXX locking */ 2248 if (sc->sc_updateslot == UPDATE) 2249 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2250 else if (sc->sc_updateslot == COMMIT) 2251 ath_setslottime(sc); /* commit change to h/w */ 2252 2253 /* 2254 * Check recent per-antenna transmit statistics and flip 2255 * the default antenna if noticeably more frames went out 2256 * on the non-default antenna. 2257 * XXX assumes 2 anntenae 2258 */ 2259 otherant = sc->sc_defant & 1 ? 2 : 1; 2260 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2261 ath_setdefantenna(sc, otherant); 2262 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2263 2264 /* 2265 * Construct tx descriptor. 2266 */ 2267 ath_beacon_setup(sc, bf); 2268 2269 /* 2270 * Stop any current dma and put the new frame on the queue. 2271 * This should never fail since we check above that no frames 2272 * are still pending on the queue. 2273 */ 2274 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2275 DPRINTF(sc, ATH_DEBUG_ANY, 2276 "%s: beacon queue %u did not stop?\n", 2277 __func__, sc->sc_bhalq); 2278 } 2279 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2280 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2281 2282 /* 2283 * Enable the CAB queue before the beacon queue to 2284 * insure cab frames are triggered by this beacon. 2285 */ 2286 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2287 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2288 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2289 ath_hal_txstart(ah, sc->sc_bhalq); 2290 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2291 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2292 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2293 2294 sc->sc_stats.ast_be_xmit++; 2295 } 2296 2297 /* 2298 * Reset the hardware after detecting beacons have stopped. 2299 */ 2300 static void 2301 ath_bstuck_proc(void *arg, int pending) 2302 { 2303 struct ath_softc *sc = arg; 2304 struct ifnet *ifp = &sc->sc_if; 2305 2306 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2307 sc->sc_bmisscount); 2308 ath_reset(ifp); 2309 } 2310 2311 /* 2312 * Reclaim beacon resources. 2313 */ 2314 static void 2315 ath_beacon_free(struct ath_softc *sc) 2316 { 2317 struct ath_buf *bf; 2318 2319 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2320 if (bf->bf_m != NULL) { 2321 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2322 m_freem(bf->bf_m); 2323 bf->bf_m = NULL; 2324 } 2325 if (bf->bf_node != NULL) { 2326 ieee80211_free_node(bf->bf_node); 2327 bf->bf_node = NULL; 2328 } 2329 } 2330 } 2331 2332 /* 2333 * Configure the beacon and sleep timers. 2334 * 2335 * When operating as an AP this resets the TSF and sets 2336 * up the hardware to notify us when we need to issue beacons. 2337 * 2338 * When operating in station mode this sets up the beacon 2339 * timers according to the timestamp of the last received 2340 * beacon and the current TSF, configures PCF and DTIM 2341 * handling, programs the sleep registers so the hardware 2342 * will wakeup in time to receive beacons, and configures 2343 * the beacon miss handling so we'll receive a BMISS 2344 * interrupt when we stop seeing beacons from the AP 2345 * we've associated with. 2346 */ 2347 static void 2348 ath_beacon_config(struct ath_softc *sc) 2349 { 2350 #define TSF_TO_TU(_h,_l) \ 2351 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2352 #define FUDGE 2 2353 struct ath_hal *ah = sc->sc_ah; 2354 struct ieee80211com *ic = &sc->sc_ic; 2355 struct ieee80211_node *ni = ic->ic_bss; 2356 u_int32_t nexttbtt, intval, tsftu; 2357 u_int64_t tsf; 2358 2359 /* extract tstamp from last beacon and convert to TU */ 2360 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2361 LE_READ_4(ni->ni_tstamp.data)); 2362 /* NB: the beacon interval is kept internally in TU's */ 2363 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2364 if (nexttbtt == 0) /* e.g. for ap mode */ 2365 nexttbtt = intval; 2366 else if (intval) /* NB: can be 0 for monitor mode */ 2367 nexttbtt = roundup(nexttbtt, intval); 2368 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2369 __func__, nexttbtt, intval, ni->ni_intval); 2370 if (ic->ic_opmode == IEEE80211_M_STA) { 2371 HAL_BEACON_STATE bs; 2372 int dtimperiod, dtimcount; 2373 int cfpperiod, cfpcount; 2374 2375 /* 2376 * Setup dtim and cfp parameters according to 2377 * last beacon we received (which may be none). 2378 */ 2379 dtimperiod = ni->ni_dtim_period; 2380 if (dtimperiod <= 0) /* NB: 0 if not known */ 2381 dtimperiod = 1; 2382 dtimcount = ni->ni_dtim_count; 2383 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2384 dtimcount = 0; /* XXX? */ 2385 cfpperiod = 1; /* NB: no PCF support yet */ 2386 cfpcount = 0; 2387 /* 2388 * Pull nexttbtt forward to reflect the current 2389 * TSF and calculate dtim+cfp state for the result. 2390 */ 2391 tsf = ath_hal_gettsf64(ah); 2392 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2393 do { 2394 nexttbtt += intval; 2395 if (--dtimcount < 0) { 2396 dtimcount = dtimperiod - 1; 2397 if (--cfpcount < 0) 2398 cfpcount = cfpperiod - 1; 2399 } 2400 } while (nexttbtt < tsftu); 2401 memset(&bs, 0, sizeof(bs)); 2402 bs.bs_intval = intval; 2403 bs.bs_nexttbtt = nexttbtt; 2404 bs.bs_dtimperiod = dtimperiod*intval; 2405 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2406 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2407 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2408 bs.bs_cfpmaxduration = 0; 2409 #if 0 2410 /* 2411 * The 802.11 layer records the offset to the DTIM 2412 * bitmap while receiving beacons; use it here to 2413 * enable h/w detection of our AID being marked in 2414 * the bitmap vector (to indicate frames for us are 2415 * pending at the AP). 2416 * XXX do DTIM handling in s/w to WAR old h/w bugs 2417 * XXX enable based on h/w rev for newer chips 2418 */ 2419 bs.bs_timoffset = ni->ni_timoff; 2420 #endif 2421 /* 2422 * Calculate the number of consecutive beacons to miss 2423 * before taking a BMISS interrupt. The configuration 2424 * is specified in ms, so we need to convert that to 2425 * TU's and then calculate based on the beacon interval. 2426 * Note that we clamp the result to at most 10 beacons. 2427 */ 2428 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2429 if (bs.bs_bmissthreshold > 10) 2430 bs.bs_bmissthreshold = 10; 2431 else if (bs.bs_bmissthreshold <= 0) 2432 bs.bs_bmissthreshold = 1; 2433 2434 /* 2435 * Calculate sleep duration. The configuration is 2436 * given in ms. We insure a multiple of the beacon 2437 * period is used. Also, if the sleep duration is 2438 * greater than the DTIM period then it makes senses 2439 * to make it a multiple of that. 2440 * 2441 * XXX fixed at 100ms 2442 */ 2443 bs.bs_sleepduration = 2444 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2445 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2446 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2447 2448 DPRINTF(sc, ATH_DEBUG_BEACON, 2449 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2450 , __func__ 2451 , tsf, tsftu 2452 , bs.bs_intval 2453 , bs.bs_nexttbtt 2454 , bs.bs_dtimperiod 2455 , bs.bs_nextdtim 2456 , bs.bs_bmissthreshold 2457 , bs.bs_sleepduration 2458 , bs.bs_cfpperiod 2459 , bs.bs_cfpmaxduration 2460 , bs.bs_cfpnext 2461 , bs.bs_timoffset 2462 ); 2463 ath_hal_intrset(ah, 0); 2464 ath_hal_beacontimers(ah, &bs); 2465 sc->sc_imask |= HAL_INT_BMISS; 2466 ath_hal_intrset(ah, sc->sc_imask); 2467 } else { 2468 ath_hal_intrset(ah, 0); 2469 if (nexttbtt == intval) 2470 intval |= HAL_BEACON_RESET_TSF; 2471 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2472 /* 2473 * In IBSS mode enable the beacon timers but only 2474 * enable SWBA interrupts if we need to manually 2475 * prepare beacon frames. Otherwise we use a 2476 * self-linked tx descriptor and let the hardware 2477 * deal with things. 2478 */ 2479 intval |= HAL_BEACON_ENA; 2480 if (!sc->sc_hasveol) 2481 sc->sc_imask |= HAL_INT_SWBA; 2482 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2483 /* 2484 * Pull nexttbtt forward to reflect 2485 * the current TSF. 2486 */ 2487 tsf = ath_hal_gettsf64(ah); 2488 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2489 do { 2490 nexttbtt += intval; 2491 } while (nexttbtt < tsftu); 2492 } 2493 ath_beaconq_config(sc); 2494 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2495 /* 2496 * In AP mode we enable the beacon timers and 2497 * SWBA interrupts to prepare beacon frames. 2498 */ 2499 intval |= HAL_BEACON_ENA; 2500 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2501 ath_beaconq_config(sc); 2502 } 2503 ath_hal_beaconinit(ah, nexttbtt, intval); 2504 sc->sc_bmisscount = 0; 2505 ath_hal_intrset(ah, sc->sc_imask); 2506 /* 2507 * When using a self-linked beacon descriptor in 2508 * ibss mode load it once here. 2509 */ 2510 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2511 ath_beacon_proc(sc, 0); 2512 } 2513 sc->sc_syncbeacon = 0; 2514 #undef UNDEF 2515 #undef TSF_TO_TU 2516 } 2517 2518 static int 2519 ath_descdma_setup(struct ath_softc *sc, 2520 struct ath_descdma *dd, ath_bufhead *head, 2521 const char *name, int nbuf, int ndesc) 2522 { 2523 #define DS2PHYS(_dd, _ds) \ 2524 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2525 struct ifnet *ifp = &sc->sc_if; 2526 struct ath_desc *ds; 2527 struct ath_buf *bf; 2528 int i, bsize, error; 2529 2530 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2531 __func__, name, nbuf, ndesc); 2532 2533 dd->dd_name = name; 2534 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2535 2536 /* 2537 * Setup DMA descriptor area. 2538 */ 2539 dd->dd_dmat = sc->sc_dmat; 2540 2541 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2542 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2543 2544 if (error != 0) { 2545 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2546 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2547 goto fail0; 2548 } 2549 2550 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2551 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2552 if (error != 0) { 2553 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2554 nbuf * ndesc, dd->dd_name, error); 2555 goto fail1; 2556 } 2557 2558 /* allocate descriptors */ 2559 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2560 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2561 if (error != 0) { 2562 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2563 "error %u\n", dd->dd_name, error); 2564 goto fail2; 2565 } 2566 2567 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2568 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2569 if (error != 0) { 2570 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2571 dd->dd_name, error); 2572 goto fail3; 2573 } 2574 2575 ds = dd->dd_desc; 2576 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2577 DPRINTF(sc, ATH_DEBUG_RESET, 2578 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2579 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2580 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2581 2582 /* allocate rx buffers */ 2583 bsize = sizeof(struct ath_buf) * nbuf; 2584 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2585 if (bf == NULL) { 2586 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2587 dd->dd_name, bsize); 2588 goto fail4; 2589 } 2590 dd->dd_bufptr = bf; 2591 2592 STAILQ_INIT(head); 2593 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2594 bf->bf_desc = ds; 2595 bf->bf_daddr = DS2PHYS(dd, ds); 2596 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2597 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2598 if (error != 0) { 2599 if_printf(ifp, "unable to create dmamap for %s " 2600 "buffer %u, error %u\n", dd->dd_name, i, error); 2601 ath_descdma_cleanup(sc, dd, head); 2602 return error; 2603 } 2604 STAILQ_INSERT_TAIL(head, bf, bf_list); 2605 } 2606 return 0; 2607 fail4: 2608 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2609 fail3: 2610 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2611 fail2: 2612 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2613 fail1: 2614 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2615 fail0: 2616 memset(dd, 0, sizeof(*dd)); 2617 return error; 2618 #undef DS2PHYS 2619 } 2620 2621 static void 2622 ath_descdma_cleanup(struct ath_softc *sc, 2623 struct ath_descdma *dd, ath_bufhead *head) 2624 { 2625 struct ath_buf *bf; 2626 struct ieee80211_node *ni; 2627 2628 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2629 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2630 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2631 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2632 2633 STAILQ_FOREACH(bf, head, bf_list) { 2634 if (bf->bf_m) { 2635 m_freem(bf->bf_m); 2636 bf->bf_m = NULL; 2637 } 2638 if (bf->bf_dmamap != NULL) { 2639 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2640 bf->bf_dmamap = NULL; 2641 } 2642 ni = bf->bf_node; 2643 bf->bf_node = NULL; 2644 if (ni != NULL) { 2645 /* 2646 * Reclaim node reference. 2647 */ 2648 ieee80211_free_node(ni); 2649 } 2650 } 2651 2652 STAILQ_INIT(head); 2653 free(dd->dd_bufptr, M_ATHDEV); 2654 memset(dd, 0, sizeof(*dd)); 2655 } 2656 2657 static int 2658 ath_desc_alloc(struct ath_softc *sc) 2659 { 2660 int error; 2661 2662 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2663 "rx", ath_rxbuf, 1); 2664 if (error != 0) 2665 return error; 2666 2667 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2668 "tx", ath_txbuf, ATH_TXDESC); 2669 if (error != 0) { 2670 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2671 return error; 2672 } 2673 2674 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2675 "beacon", 1, 1); 2676 if (error != 0) { 2677 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2678 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2679 return error; 2680 } 2681 return 0; 2682 } 2683 2684 static void 2685 ath_desc_free(struct ath_softc *sc) 2686 { 2687 2688 if (sc->sc_bdma.dd_desc_len != 0) 2689 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2690 if (sc->sc_txdma.dd_desc_len != 0) 2691 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2692 if (sc->sc_rxdma.dd_desc_len != 0) 2693 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2694 } 2695 2696 static struct ieee80211_node * 2697 ath_node_alloc(struct ieee80211_node_table *nt) 2698 { 2699 struct ieee80211com *ic = nt->nt_ic; 2700 struct ath_softc *sc = ic->ic_ifp->if_softc; 2701 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2702 struct ath_node *an; 2703 2704 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2705 if (an == NULL) { 2706 /* XXX stat+msg */ 2707 return NULL; 2708 } 2709 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2710 ath_rate_node_init(sc, an); 2711 2712 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2713 return &an->an_node; 2714 } 2715 2716 static void 2717 ath_node_free(struct ieee80211_node *ni) 2718 { 2719 struct ieee80211com *ic = ni->ni_ic; 2720 struct ath_softc *sc = ic->ic_ifp->if_softc; 2721 2722 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2723 2724 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2725 sc->sc_node_free(ni); 2726 } 2727 2728 static u_int8_t 2729 ath_node_getrssi(const struct ieee80211_node *ni) 2730 { 2731 #define HAL_EP_RND(x, mul) \ 2732 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2733 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2734 int32_t rssi; 2735 2736 /* 2737 * When only one frame is received there will be no state in 2738 * avgrssi so fallback on the value recorded by the 802.11 layer. 2739 */ 2740 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2741 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2742 else 2743 rssi = ni->ni_rssi; 2744 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2745 #undef HAL_EP_RND 2746 } 2747 2748 static int 2749 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2750 { 2751 struct ath_hal *ah = sc->sc_ah; 2752 int error; 2753 struct mbuf *m; 2754 struct ath_desc *ds; 2755 2756 m = bf->bf_m; 2757 if (m == NULL) { 2758 /* 2759 * NB: by assigning a page to the rx dma buffer we 2760 * implicitly satisfy the Atheros requirement that 2761 * this buffer be cache-line-aligned and sized to be 2762 * multiple of the cache line size. Not doing this 2763 * causes weird stuff to happen (for the 5210 at least). 2764 */ 2765 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2766 if (m == NULL) { 2767 DPRINTF(sc, ATH_DEBUG_ANY, 2768 "%s: no mbuf/cluster\n", __func__); 2769 sc->sc_stats.ast_rx_nombuf++; 2770 return ENOMEM; 2771 } 2772 bf->bf_m = m; 2773 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2774 2775 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2776 bf->bf_dmamap, m, 2777 BUS_DMA_NOWAIT); 2778 if (error != 0) { 2779 DPRINTF(sc, ATH_DEBUG_ANY, 2780 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2781 __func__, error); 2782 sc->sc_stats.ast_rx_busdma++; 2783 return error; 2784 } 2785 KASSERT(bf->bf_nseg == 1, 2786 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2787 } 2788 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2789 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2790 2791 /* 2792 * Setup descriptors. For receive we always terminate 2793 * the descriptor list with a self-linked entry so we'll 2794 * not get overrun under high load (as can happen with a 2795 * 5212 when ANI processing enables PHY error frames). 2796 * 2797 * To insure the last descriptor is self-linked we create 2798 * each descriptor as self-linked and add it to the end. As 2799 * each additional descriptor is added the previous self-linked 2800 * entry is ``fixed'' naturally. This should be safe even 2801 * if DMA is happening. When processing RX interrupts we 2802 * never remove/process the last, self-linked, entry on the 2803 * descriptor list. This insures the hardware always has 2804 * someplace to write a new frame. 2805 */ 2806 ds = bf->bf_desc; 2807 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2808 ds->ds_data = bf->bf_segs[0].ds_addr; 2809 /* ds->ds_vdata = mtod(m, void *); for radar */ 2810 ath_hal_setuprxdesc(ah, ds 2811 , m->m_len /* buffer size */ 2812 , 0 2813 ); 2814 2815 if (sc->sc_rxlink != NULL) 2816 *sc->sc_rxlink = bf->bf_daddr; 2817 sc->sc_rxlink = &ds->ds_link; 2818 return 0; 2819 } 2820 2821 /* 2822 * Extend 15-bit time stamp from rx descriptor to 2823 * a full 64-bit TSF using the specified TSF. 2824 */ 2825 static inline u_int64_t 2826 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2827 { 2828 if ((tsf & 0x7fff) < rstamp) 2829 tsf -= 0x8000; 2830 return ((tsf &~ 0x7fff) | rstamp); 2831 } 2832 2833 /* 2834 * Intercept management frames to collect beacon rssi data 2835 * and to do ibss merges. 2836 */ 2837 static void 2838 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2839 struct ieee80211_node *ni, 2840 int subtype, int rssi, u_int32_t rstamp) 2841 { 2842 struct ath_softc *sc = ic->ic_ifp->if_softc; 2843 2844 /* 2845 * Call up first so subsequent work can use information 2846 * potentially stored in the node (e.g. for ibss merge). 2847 */ 2848 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2849 switch (subtype) { 2850 case IEEE80211_FC0_SUBTYPE_BEACON: 2851 /* update rssi statistics for use by the hal */ 2852 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2853 if (sc->sc_syncbeacon && 2854 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2855 /* 2856 * Resync beacon timers using the tsf of the beacon 2857 * frame we just received. 2858 */ 2859 ath_beacon_config(sc); 2860 } 2861 /* fall thru... */ 2862 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2863 if (ic->ic_opmode == IEEE80211_M_IBSS && 2864 ic->ic_state == IEEE80211_S_RUN) { 2865 u_int64_t tsf = ath_extend_tsf(rstamp, 2866 ath_hal_gettsf64(sc->sc_ah)); 2867 2868 /* 2869 * Handle ibss merge as needed; check the tsf on the 2870 * frame before attempting the merge. The 802.11 spec 2871 * says the station should change it's bssid to match 2872 * the oldest station with the same ssid, where oldest 2873 * is determined by the tsf. Note that hardware 2874 * reconfiguration happens through callback to 2875 * ath_newstate as the state machine will go from 2876 * RUN -> RUN when this happens. 2877 */ 2878 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2879 DPRINTF(sc, ATH_DEBUG_STATE, 2880 "ibss merge, rstamp %u tsf %ju " 2881 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2882 (uintmax_t)ni->ni_tstamp.tsf); 2883 (void) ieee80211_ibss_merge(ni); 2884 } 2885 } 2886 break; 2887 } 2888 } 2889 2890 /* 2891 * Set the default antenna. 2892 */ 2893 static void 2894 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2895 { 2896 struct ath_hal *ah = sc->sc_ah; 2897 2898 /* XXX block beacon interrupts */ 2899 ath_hal_setdefantenna(ah, antenna); 2900 if (sc->sc_defant != antenna) 2901 sc->sc_stats.ast_ant_defswitch++; 2902 sc->sc_defant = antenna; 2903 sc->sc_rxotherant = 0; 2904 } 2905 2906 static void 2907 ath_handle_micerror(struct ieee80211com *ic, 2908 struct ieee80211_frame *wh, int keyix) 2909 { 2910 struct ieee80211_node *ni; 2911 2912 /* XXX recheck MIC to deal w/ chips that lie */ 2913 /* XXX discard MIC errors on !data frames */ 2914 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 2915 if (ni != NULL) { 2916 ieee80211_notify_michael_failure(ic, wh, keyix); 2917 ieee80211_free_node(ni); 2918 } 2919 } 2920 2921 static void 2922 ath_rx_proc(void *arg, int npending) 2923 { 2924 #define PA2DESC(_sc, _pa) \ 2925 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 2926 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2927 struct ath_softc *sc = arg; 2928 struct ath_buf *bf; 2929 struct ieee80211com *ic = &sc->sc_ic; 2930 struct ifnet *ifp = &sc->sc_if; 2931 struct ath_hal *ah = sc->sc_ah; 2932 struct ath_desc *ds; 2933 struct mbuf *m; 2934 struct ieee80211_node *ni; 2935 struct ath_node *an; 2936 int len, ngood, type; 2937 u_int phyerr; 2938 HAL_STATUS status; 2939 int16_t nf; 2940 u_int64_t tsf; 2941 uint8_t rxerr_tap, rxerr_mon; 2942 2943 NET_LOCK_GIANT(); /* XXX */ 2944 2945 rxerr_tap = 2946 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 2947 2948 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 2949 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 2950 else if (ifp->if_flags & IFF_PROMISC) 2951 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 2952 2953 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2954 ngood = 0; 2955 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2956 tsf = ath_hal_gettsf64(ah); 2957 do { 2958 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2959 if (bf == NULL) { /* NB: shouldn't happen */ 2960 if_printf(ifp, "%s: no buffer!\n", __func__); 2961 break; 2962 } 2963 ds = bf->bf_desc; 2964 if (ds->ds_link == bf->bf_daddr) { 2965 /* NB: never process the self-linked entry at the end */ 2966 break; 2967 } 2968 m = bf->bf_m; 2969 if (m == NULL) { /* NB: shouldn't happen */ 2970 if_printf(ifp, "%s: no mbuf!\n", __func__); 2971 break; 2972 } 2973 /* XXX sync descriptor memory */ 2974 /* 2975 * Must provide the virtual address of the current 2976 * descriptor, the physical address, and the virtual 2977 * address of the next descriptor in the h/w chain. 2978 * This allows the HAL to look ahead to see if the 2979 * hardware is done with a descriptor by checking the 2980 * done bit in the following descriptor and the address 2981 * of the current descriptor the DMA engine is working 2982 * on. All this is necessary because of our use of 2983 * a self-linked list to avoid rx overruns. 2984 */ 2985 status = ath_hal_rxprocdesc(ah, ds, 2986 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 2987 tsf, &ds->ds_rxstat); 2988 #ifdef AR_DEBUG 2989 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2990 ath_printrxbuf(bf, status == HAL_OK); 2991 #endif 2992 if (status == HAL_EINPROGRESS) 2993 break; 2994 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2995 if (ds->ds_rxstat.rs_more) { 2996 /* 2997 * Frame spans multiple descriptors; this 2998 * cannot happen yet as we don't support 2999 * jumbograms. If not in monitor mode, 3000 * discard the frame. 3001 */ 3002 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3003 sc->sc_stats.ast_rx_toobig++; 3004 goto rx_next; 3005 } 3006 /* fall thru for monitor mode handling... */ 3007 } else if (ds->ds_rxstat.rs_status != 0) { 3008 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3009 sc->sc_stats.ast_rx_crcerr++; 3010 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3011 sc->sc_stats.ast_rx_fifoerr++; 3012 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3013 sc->sc_stats.ast_rx_phyerr++; 3014 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3015 sc->sc_stats.ast_rx_phy[phyerr]++; 3016 goto rx_next; 3017 } 3018 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3019 /* 3020 * Decrypt error. If the error occurred 3021 * because there was no hardware key, then 3022 * let the frame through so the upper layers 3023 * can process it. This is necessary for 5210 3024 * parts which have no way to setup a ``clear'' 3025 * key cache entry. 3026 * 3027 * XXX do key cache faulting 3028 */ 3029 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3030 goto rx_accept; 3031 sc->sc_stats.ast_rx_badcrypt++; 3032 } 3033 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3034 sc->sc_stats.ast_rx_badmic++; 3035 /* 3036 * Do minimal work required to hand off 3037 * the 802.11 header for notifcation. 3038 */ 3039 /* XXX frag's and qos frames */ 3040 len = ds->ds_rxstat.rs_datalen; 3041 if (len >= sizeof (struct ieee80211_frame)) { 3042 bus_dmamap_sync(sc->sc_dmat, 3043 bf->bf_dmamap, 3044 0, bf->bf_dmamap->dm_mapsize, 3045 BUS_DMASYNC_POSTREAD); 3046 ath_handle_micerror(ic, 3047 mtod(m, struct ieee80211_frame *), 3048 sc->sc_splitmic ? 3049 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3050 } 3051 } 3052 ifp->if_ierrors++; 3053 /* 3054 * Reject error frames, we normally don't want 3055 * to see them in monitor mode (in monitor mode 3056 * allow through packets that have crypto problems). 3057 */ 3058 3059 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3060 goto rx_next; 3061 } 3062 rx_accept: 3063 /* 3064 * Sync and unmap the frame. At this point we're 3065 * committed to passing the mbuf somewhere so clear 3066 * bf_m; this means a new sk_buff must be allocated 3067 * when the rx descriptor is setup again to receive 3068 * another frame. 3069 */ 3070 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3071 0, bf->bf_dmamap->dm_mapsize, 3072 BUS_DMASYNC_POSTREAD); 3073 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3074 bf->bf_m = NULL; 3075 3076 m->m_pkthdr.rcvif = ifp; 3077 len = ds->ds_rxstat.rs_datalen; 3078 m->m_pkthdr.len = m->m_len = len; 3079 3080 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3081 3082 #if NBPFILTER > 0 3083 if (sc->sc_drvbpf) { 3084 u_int8_t rix; 3085 3086 /* 3087 * Discard anything shorter than an ack or cts. 3088 */ 3089 if (len < IEEE80211_ACK_LEN) { 3090 DPRINTF(sc, ATH_DEBUG_RECV, 3091 "%s: runt packet %d\n", 3092 __func__, len); 3093 sc->sc_stats.ast_rx_tooshort++; 3094 m_freem(m); 3095 goto rx_next; 3096 } 3097 rix = ds->ds_rxstat.rs_rate; 3098 sc->sc_rx_th.wr_tsf = htole64( 3099 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3100 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3101 if (ds->ds_rxstat.rs_status & 3102 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3103 sc->sc_rx_th.wr_flags |= 3104 IEEE80211_RADIOTAP_F_BADFCS; 3105 } 3106 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3107 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3108 sc->sc_rx_th.wr_antnoise = nf; 3109 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3110 3111 bpf_mtap2(sc->sc_drvbpf, 3112 &sc->sc_rx_th, sc->sc_rx_th_len, m); 3113 } 3114 #endif 3115 3116 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3117 m_freem(m); 3118 goto rx_next; 3119 } 3120 /* 3121 * From this point on we assume the frame is at least 3122 * as large as ieee80211_frame_min; verify that. 3123 */ 3124 if (len < IEEE80211_MIN_LEN) { 3125 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3126 __func__, len); 3127 sc->sc_stats.ast_rx_tooshort++; 3128 m_freem(m); 3129 goto rx_next; 3130 } 3131 3132 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3133 ieee80211_dump_pkt(mtod(m, void *), len, 3134 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3135 ds->ds_rxstat.rs_rssi); 3136 } 3137 3138 m_adj(m, -IEEE80211_CRC_LEN); 3139 3140 /* 3141 * Locate the node for sender, track state, and then 3142 * pass the (referenced) node up to the 802.11 layer 3143 * for its use. 3144 */ 3145 ni = ieee80211_find_rxnode_withkey(ic, 3146 mtod(m, const struct ieee80211_frame_min *), 3147 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3148 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3149 /* 3150 * Track rx rssi and do any rx antenna management. 3151 */ 3152 an = ATH_NODE(ni); 3153 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3154 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3155 /* 3156 * Send frame up for processing. 3157 */ 3158 type = ieee80211_input(ic, m, ni, 3159 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3160 ieee80211_free_node(ni); 3161 if (sc->sc_diversity) { 3162 /* 3163 * When using fast diversity, change the default rx 3164 * antenna if diversity chooses the other antenna 3 3165 * times in a row. 3166 */ 3167 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3168 if (++sc->sc_rxotherant >= 3) 3169 ath_setdefantenna(sc, 3170 ds->ds_rxstat.rs_antenna); 3171 } else 3172 sc->sc_rxotherant = 0; 3173 } 3174 if (sc->sc_softled) { 3175 /* 3176 * Blink for any data frame. Otherwise do a 3177 * heartbeat-style blink when idle. The latter 3178 * is mainly for station mode where we depend on 3179 * periodic beacon frames to trigger the poll event. 3180 */ 3181 if (type == IEEE80211_FC0_TYPE_DATA) { 3182 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3183 ath_led_event(sc, ATH_LED_RX); 3184 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3185 ath_led_event(sc, ATH_LED_POLL); 3186 } 3187 /* 3188 * Arrange to update the last rx timestamp only for 3189 * frames from our ap when operating in station mode. 3190 * This assumes the rx key is always setup when associated. 3191 */ 3192 if (ic->ic_opmode == IEEE80211_M_STA && 3193 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3194 ngood++; 3195 rx_next: 3196 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3197 } while (ath_rxbuf_init(sc, bf) == 0); 3198 3199 /* rx signal state monitoring */ 3200 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3201 #if 0 3202 if (ath_hal_radar_event(ah)) 3203 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3204 #endif 3205 if (ngood) 3206 sc->sc_lastrx = tsf; 3207 3208 #ifdef __NetBSD__ 3209 /* XXX Why isn't this necessary in FreeBSD? */ 3210 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3211 ath_start(ifp); 3212 #endif /* __NetBSD__ */ 3213 3214 NET_UNLOCK_GIANT(); /* XXX */ 3215 #undef PA2DESC 3216 } 3217 3218 /* 3219 * Setup a h/w transmit queue. 3220 */ 3221 static struct ath_txq * 3222 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3223 { 3224 #define N(a) (sizeof(a)/sizeof(a[0])) 3225 struct ath_hal *ah = sc->sc_ah; 3226 HAL_TXQ_INFO qi; 3227 int qnum; 3228 3229 memset(&qi, 0, sizeof(qi)); 3230 qi.tqi_subtype = subtype; 3231 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3232 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3233 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3234 /* 3235 * Enable interrupts only for EOL and DESC conditions. 3236 * We mark tx descriptors to receive a DESC interrupt 3237 * when a tx queue gets deep; otherwise waiting for the 3238 * EOL to reap descriptors. Note that this is done to 3239 * reduce interrupt load and this only defers reaping 3240 * descriptors, never transmitting frames. Aside from 3241 * reducing interrupts this also permits more concurrency. 3242 * The only potential downside is if the tx queue backs 3243 * up in which case the top half of the kernel may backup 3244 * due to a lack of tx descriptors. 3245 */ 3246 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3247 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3248 if (qnum == -1) { 3249 /* 3250 * NB: don't print a message, this happens 3251 * normally on parts with too few tx queues 3252 */ 3253 return NULL; 3254 } 3255 if (qnum >= N(sc->sc_txq)) { 3256 device_printf(sc->sc_dev, 3257 "hal qnum %u out of range, max %zu!\n", 3258 qnum, N(sc->sc_txq)); 3259 ath_hal_releasetxqueue(ah, qnum); 3260 return NULL; 3261 } 3262 if (!ATH_TXQ_SETUP(sc, qnum)) { 3263 struct ath_txq *txq = &sc->sc_txq[qnum]; 3264 3265 txq->axq_qnum = qnum; 3266 txq->axq_depth = 0; 3267 txq->axq_intrcnt = 0; 3268 txq->axq_link = NULL; 3269 STAILQ_INIT(&txq->axq_q); 3270 ATH_TXQ_LOCK_INIT(sc, txq); 3271 sc->sc_txqsetup |= 1<<qnum; 3272 } 3273 return &sc->sc_txq[qnum]; 3274 #undef N 3275 } 3276 3277 /* 3278 * Setup a hardware data transmit queue for the specified 3279 * access control. The hal may not support all requested 3280 * queues in which case it will return a reference to a 3281 * previously setup queue. We record the mapping from ac's 3282 * to h/w queues for use by ath_tx_start and also track 3283 * the set of h/w queues being used to optimize work in the 3284 * transmit interrupt handler and related routines. 3285 */ 3286 static int 3287 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3288 { 3289 #define N(a) (sizeof(a)/sizeof(a[0])) 3290 struct ath_txq *txq; 3291 3292 if (ac >= N(sc->sc_ac2q)) { 3293 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3294 ac, N(sc->sc_ac2q)); 3295 return 0; 3296 } 3297 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3298 if (txq != NULL) { 3299 sc->sc_ac2q[ac] = txq; 3300 return 1; 3301 } else 3302 return 0; 3303 #undef N 3304 } 3305 3306 /* 3307 * Update WME parameters for a transmit queue. 3308 */ 3309 static int 3310 ath_txq_update(struct ath_softc *sc, int ac) 3311 { 3312 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3313 #define ATH_TXOP_TO_US(v) (v<<5) 3314 struct ieee80211com *ic = &sc->sc_ic; 3315 struct ath_txq *txq = sc->sc_ac2q[ac]; 3316 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3317 struct ath_hal *ah = sc->sc_ah; 3318 HAL_TXQ_INFO qi; 3319 3320 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3321 qi.tqi_aifs = wmep->wmep_aifsn; 3322 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3323 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3324 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3325 3326 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3327 device_printf(sc->sc_dev, "unable to update hardware queue " 3328 "parameters for %s traffic!\n", 3329 ieee80211_wme_acnames[ac]); 3330 return 0; 3331 } else { 3332 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3333 return 1; 3334 } 3335 #undef ATH_TXOP_TO_US 3336 #undef ATH_EXPONENT_TO_VALUE 3337 } 3338 3339 /* 3340 * Callback from the 802.11 layer to update WME parameters. 3341 */ 3342 static int 3343 ath_wme_update(struct ieee80211com *ic) 3344 { 3345 struct ath_softc *sc = ic->ic_ifp->if_softc; 3346 3347 return !ath_txq_update(sc, WME_AC_BE) || 3348 !ath_txq_update(sc, WME_AC_BK) || 3349 !ath_txq_update(sc, WME_AC_VI) || 3350 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3351 } 3352 3353 /* 3354 * Reclaim resources for a setup queue. 3355 */ 3356 static void 3357 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3358 { 3359 3360 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3361 ATH_TXQ_LOCK_DESTROY(txq); 3362 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3363 } 3364 3365 /* 3366 * Reclaim all tx queue resources. 3367 */ 3368 static void 3369 ath_tx_cleanup(struct ath_softc *sc) 3370 { 3371 int i; 3372 3373 ATH_TXBUF_LOCK_DESTROY(sc); 3374 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3375 if (ATH_TXQ_SETUP(sc, i)) 3376 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3377 } 3378 3379 /* 3380 * Defragment an mbuf chain, returning at most maxfrags separate 3381 * mbufs+clusters. If this is not possible NULL is returned and 3382 * the original mbuf chain is left in it's present (potentially 3383 * modified) state. We use two techniques: collapsing consecutive 3384 * mbufs and replacing consecutive mbufs by a cluster. 3385 */ 3386 static struct mbuf * 3387 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3388 { 3389 struct mbuf *m, *n, *n2, **prev; 3390 u_int curfrags; 3391 3392 /* 3393 * Calculate the current number of frags. 3394 */ 3395 curfrags = 0; 3396 for (m = m0; m != NULL; m = m->m_next) 3397 curfrags++; 3398 /* 3399 * First, try to collapse mbufs. Note that we always collapse 3400 * towards the front so we don't need to deal with moving the 3401 * pkthdr. This may be suboptimal if the first mbuf has much 3402 * less data than the following. 3403 */ 3404 m = m0; 3405 again: 3406 for (;;) { 3407 n = m->m_next; 3408 if (n == NULL) 3409 break; 3410 if (n->m_len < M_TRAILINGSPACE(m)) { 3411 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3412 n->m_len); 3413 m->m_len += n->m_len; 3414 m->m_next = n->m_next; 3415 m_free(n); 3416 if (--curfrags <= maxfrags) 3417 return m0; 3418 } else 3419 m = n; 3420 } 3421 KASSERT(maxfrags > 1, 3422 ("maxfrags %u, but normal collapse failed", maxfrags)); 3423 /* 3424 * Collapse consecutive mbufs to a cluster. 3425 */ 3426 prev = &m0->m_next; /* NB: not the first mbuf */ 3427 while ((n = *prev) != NULL) { 3428 if ((n2 = n->m_next) != NULL && 3429 n->m_len + n2->m_len < MCLBYTES) { 3430 m = m_getcl(how, MT_DATA, 0); 3431 if (m == NULL) 3432 goto bad; 3433 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3434 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3435 n2->m_len); 3436 m->m_len = n->m_len + n2->m_len; 3437 m->m_next = n2->m_next; 3438 *prev = m; 3439 m_free(n); 3440 m_free(n2); 3441 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3442 return m0; 3443 /* 3444 * Still not there, try the normal collapse 3445 * again before we allocate another cluster. 3446 */ 3447 goto again; 3448 } 3449 prev = &n->m_next; 3450 } 3451 /* 3452 * No place where we can collapse to a cluster; punt. 3453 * This can occur if, for example, you request 2 frags 3454 * but the packet requires that both be clusters (we 3455 * never reallocate the first mbuf to avoid moving the 3456 * packet header). 3457 */ 3458 bad: 3459 return NULL; 3460 } 3461 3462 /* 3463 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3464 */ 3465 static int 3466 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3467 { 3468 int i; 3469 3470 for (i = 0; i < rt->rateCount; i++) 3471 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3472 return i; 3473 return 0; /* NB: lowest rate */ 3474 } 3475 3476 static void 3477 ath_freetx(struct mbuf *m) 3478 { 3479 struct mbuf *next; 3480 3481 do { 3482 next = m->m_nextpkt; 3483 m->m_nextpkt = NULL; 3484 m_freem(m); 3485 } while ((m = next) != NULL); 3486 } 3487 3488 static int 3489 deduct_pad_bytes(int len, int hdrlen) 3490 { 3491 /* XXX I am suspicious that this code, which I extracted 3492 * XXX from ath_tx_start() for reuse, does the right thing. 3493 */ 3494 return len - (hdrlen & 3); 3495 } 3496 3497 static int 3498 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3499 struct mbuf *m0) 3500 { 3501 struct ieee80211com *ic = &sc->sc_ic; 3502 struct ath_hal *ah = sc->sc_ah; 3503 struct ifnet *ifp = &sc->sc_if; 3504 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3505 int i, error, iswep, ismcast, isfrag, ismrr; 3506 int keyix, hdrlen, pktlen, try0; 3507 u_int8_t rix, txrate, ctsrate; 3508 u_int8_t cix = 0xff; /* NB: silence compiler */ 3509 struct ath_desc *ds, *ds0; 3510 struct ath_txq *txq; 3511 struct ieee80211_frame *wh; 3512 u_int subtype, flags, ctsduration; 3513 HAL_PKT_TYPE atype; 3514 const HAL_RATE_TABLE *rt; 3515 HAL_BOOL shortPreamble; 3516 struct ath_node *an; 3517 struct mbuf *m; 3518 u_int pri; 3519 3520 wh = mtod(m0, struct ieee80211_frame *); 3521 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3522 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3523 isfrag = m0->m_flags & M_FRAG; 3524 hdrlen = ieee80211_anyhdrsize(wh); 3525 /* 3526 * Packet length must not include any 3527 * pad bytes; deduct them here. 3528 */ 3529 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3530 3531 if (iswep) { 3532 const struct ieee80211_cipher *cip; 3533 struct ieee80211_key *k; 3534 3535 /* 3536 * Construct the 802.11 header+trailer for an encrypted 3537 * frame. The only reason this can fail is because of an 3538 * unknown or unsupported cipher/key type. 3539 */ 3540 k = ieee80211_crypto_encap(ic, ni, m0); 3541 if (k == NULL) { 3542 /* 3543 * This can happen when the key is yanked after the 3544 * frame was queued. Just discard the frame; the 3545 * 802.11 layer counts failures and provides 3546 * debugging/diagnostics. 3547 */ 3548 ath_freetx(m0); 3549 return EIO; 3550 } 3551 /* 3552 * Adjust the packet + header lengths for the crypto 3553 * additions and calculate the h/w key index. When 3554 * a s/w mic is done the frame will have had any mic 3555 * added to it prior to entry so m0->m_pkthdr.len above will 3556 * account for it. Otherwise we need to add it to the 3557 * packet length. 3558 */ 3559 cip = k->wk_cipher; 3560 hdrlen += cip->ic_header; 3561 pktlen += cip->ic_header + cip->ic_trailer; 3562 /* NB: frags always have any TKIP MIC done in s/w */ 3563 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3564 pktlen += cip->ic_miclen; 3565 keyix = k->wk_keyix; 3566 3567 /* packet header may have moved, reset our local pointer */ 3568 wh = mtod(m0, struct ieee80211_frame *); 3569 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3570 /* 3571 * Use station key cache slot, if assigned. 3572 */ 3573 keyix = ni->ni_ucastkey.wk_keyix; 3574 if (keyix == IEEE80211_KEYIX_NONE) 3575 keyix = HAL_TXKEYIX_INVALID; 3576 } else 3577 keyix = HAL_TXKEYIX_INVALID; 3578 3579 pktlen += IEEE80211_CRC_LEN; 3580 3581 /* 3582 * Load the DMA map so any coalescing is done. This 3583 * also calculates the number of descriptors we need. 3584 */ 3585 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3586 BUS_DMA_NOWAIT); 3587 if (error == EFBIG) { 3588 /* XXX packet requires too many descriptors */ 3589 bf->bf_nseg = ATH_TXDESC+1; 3590 } else if (error != 0) { 3591 sc->sc_stats.ast_tx_busdma++; 3592 ath_freetx(m0); 3593 return error; 3594 } 3595 /* 3596 * Discard null packets and check for packets that 3597 * require too many TX descriptors. We try to convert 3598 * the latter to a cluster. 3599 */ 3600 if (error == EFBIG) { /* too many desc's, linearize */ 3601 sc->sc_stats.ast_tx_linear++; 3602 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3603 if (m == NULL) { 3604 ath_freetx(m0); 3605 sc->sc_stats.ast_tx_nombuf++; 3606 return ENOMEM; 3607 } 3608 m0 = m; 3609 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3610 BUS_DMA_NOWAIT); 3611 if (error != 0) { 3612 sc->sc_stats.ast_tx_busdma++; 3613 ath_freetx(m0); 3614 return error; 3615 } 3616 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3617 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3618 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3619 sc->sc_stats.ast_tx_nodata++; 3620 ath_freetx(m0); 3621 return EIO; 3622 } 3623 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3624 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3625 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3626 bf->bf_m = m0; 3627 bf->bf_node = ni; /* NB: held reference */ 3628 3629 /* setup descriptors */ 3630 ds = bf->bf_desc; 3631 rt = sc->sc_currates; 3632 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3633 3634 /* 3635 * NB: the 802.11 layer marks whether or not we should 3636 * use short preamble based on the current mode and 3637 * negotiated parameters. 3638 */ 3639 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3640 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3641 shortPreamble = AH_TRUE; 3642 sc->sc_stats.ast_tx_shortpre++; 3643 } else { 3644 shortPreamble = AH_FALSE; 3645 } 3646 3647 an = ATH_NODE(ni); 3648 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3649 ismrr = 0; /* default no multi-rate retry*/ 3650 /* 3651 * Calculate Atheros packet type from IEEE80211 packet header, 3652 * setup for rate calculations, and select h/w transmit queue. 3653 */ 3654 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3655 case IEEE80211_FC0_TYPE_MGT: 3656 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3657 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3658 atype = HAL_PKT_TYPE_BEACON; 3659 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3660 atype = HAL_PKT_TYPE_PROBE_RESP; 3661 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3662 atype = HAL_PKT_TYPE_ATIM; 3663 else 3664 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3665 rix = sc->sc_minrateix; 3666 txrate = rt->info[rix].rateCode; 3667 if (shortPreamble) 3668 txrate |= rt->info[rix].shortPreamble; 3669 try0 = ATH_TXMGTTRY; 3670 /* NB: force all management frames to highest queue */ 3671 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3672 /* NB: force all management frames to highest queue */ 3673 pri = WME_AC_VO; 3674 } else 3675 pri = WME_AC_BE; 3676 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3677 break; 3678 case IEEE80211_FC0_TYPE_CTL: 3679 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3680 rix = sc->sc_minrateix; 3681 txrate = rt->info[rix].rateCode; 3682 if (shortPreamble) 3683 txrate |= rt->info[rix].shortPreamble; 3684 try0 = ATH_TXMGTTRY; 3685 /* NB: force all ctl frames to highest queue */ 3686 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3687 /* NB: force all ctl frames to highest queue */ 3688 pri = WME_AC_VO; 3689 } else 3690 pri = WME_AC_BE; 3691 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3692 break; 3693 case IEEE80211_FC0_TYPE_DATA: 3694 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3695 /* 3696 * Data frames: multicast frames go out at a fixed rate, 3697 * otherwise consult the rate control module for the 3698 * rate to use. 3699 */ 3700 if (ismcast) { 3701 /* 3702 * Check mcast rate setting in case it's changed. 3703 * XXX move out of fastpath 3704 */ 3705 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3706 sc->sc_mcastrix = 3707 ath_tx_findrix(rt, ic->ic_mcast_rate); 3708 sc->sc_mcastrate = ic->ic_mcast_rate; 3709 } 3710 rix = sc->sc_mcastrix; 3711 txrate = rt->info[rix].rateCode; 3712 try0 = 1; 3713 } else { 3714 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3715 &rix, &try0, &txrate); 3716 sc->sc_txrate = txrate; /* for LED blinking */ 3717 if (try0 != ATH_TXMAXTRY) 3718 ismrr = 1; 3719 } 3720 pri = M_WME_GETAC(m0); 3721 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3722 flags |= HAL_TXDESC_NOACK; 3723 break; 3724 default: 3725 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3726 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3727 /* XXX statistic */ 3728 ath_freetx(m0); 3729 return EIO; 3730 } 3731 txq = sc->sc_ac2q[pri]; 3732 3733 /* 3734 * When servicing one or more stations in power-save mode 3735 * multicast frames must be buffered until after the beacon. 3736 * We use the CAB queue for that. 3737 */ 3738 if (ismcast && ic->ic_ps_sta) { 3739 txq = sc->sc_cabq; 3740 /* XXX? more bit in 802.11 frame header */ 3741 } 3742 3743 /* 3744 * Calculate miscellaneous flags. 3745 */ 3746 if (ismcast) { 3747 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3748 } else if (pktlen > ic->ic_rtsthreshold) { 3749 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3750 cix = rt->info[rix].controlRate; 3751 sc->sc_stats.ast_tx_rts++; 3752 } 3753 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3754 sc->sc_stats.ast_tx_noack++; 3755 3756 /* 3757 * If 802.11g protection is enabled, determine whether 3758 * to use RTS/CTS or just CTS. Note that this is only 3759 * done for OFDM unicast frames. 3760 */ 3761 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3762 rt->info[rix].phy == IEEE80211_T_OFDM && 3763 (flags & HAL_TXDESC_NOACK) == 0) { 3764 /* XXX fragments must use CCK rates w/ protection */ 3765 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3766 flags |= HAL_TXDESC_RTSENA; 3767 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3768 flags |= HAL_TXDESC_CTSENA; 3769 if (isfrag) { 3770 /* 3771 * For frags it would be desirable to use the 3772 * highest CCK rate for RTS/CTS. But stations 3773 * farther away may detect it at a lower CCK rate 3774 * so use the configured protection rate instead 3775 * (for now). 3776 */ 3777 cix = rt->info[sc->sc_protrix].controlRate; 3778 } else 3779 cix = rt->info[sc->sc_protrix].controlRate; 3780 sc->sc_stats.ast_tx_protect++; 3781 } 3782 3783 /* 3784 * Calculate duration. This logically belongs in the 802.11 3785 * layer but it lacks sufficient information to calculate it. 3786 */ 3787 if ((flags & HAL_TXDESC_NOACK) == 0 && 3788 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3789 u_int16_t dur; 3790 /* 3791 * XXX not right with fragmentation. 3792 */ 3793 if (shortPreamble) 3794 dur = rt->info[rix].spAckDuration; 3795 else 3796 dur = rt->info[rix].lpAckDuration; 3797 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3798 dur += dur; /* additional SIFS+ACK */ 3799 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 3800 /* 3801 * Include the size of next fragment so NAV is 3802 * updated properly. The last fragment uses only 3803 * the ACK duration 3804 */ 3805 dur += ath_hal_computetxtime(ah, rt, 3806 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3807 hdrlen) - 3808 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3809 rix, shortPreamble); 3810 } 3811 if (isfrag) { 3812 /* 3813 * Force hardware to use computed duration for next 3814 * fragment by disabling multi-rate retry which updates 3815 * duration based on the multi-rate duration table. 3816 */ 3817 try0 = ATH_TXMAXTRY; 3818 } 3819 *(u_int16_t *)wh->i_dur = htole16(dur); 3820 } 3821 3822 /* 3823 * Calculate RTS/CTS rate and duration if needed. 3824 */ 3825 ctsduration = 0; 3826 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3827 /* 3828 * CTS transmit rate is derived from the transmit rate 3829 * by looking in the h/w rate table. We must also factor 3830 * in whether or not a short preamble is to be used. 3831 */ 3832 /* NB: cix is set above where RTS/CTS is enabled */ 3833 KASSERT(cix != 0xff, ("cix not setup")); 3834 ctsrate = rt->info[cix].rateCode; 3835 /* 3836 * Compute the transmit duration based on the frame 3837 * size and the size of an ACK frame. We call into the 3838 * HAL to do the computation since it depends on the 3839 * characteristics of the actual PHY being used. 3840 * 3841 * NB: CTS is assumed the same size as an ACK so we can 3842 * use the precalculated ACK durations. 3843 */ 3844 if (shortPreamble) { 3845 ctsrate |= rt->info[cix].shortPreamble; 3846 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3847 ctsduration += rt->info[cix].spAckDuration; 3848 ctsduration += ath_hal_computetxtime(ah, 3849 rt, pktlen, rix, AH_TRUE); 3850 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3851 ctsduration += rt->info[rix].spAckDuration; 3852 } else { 3853 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3854 ctsduration += rt->info[cix].lpAckDuration; 3855 ctsduration += ath_hal_computetxtime(ah, 3856 rt, pktlen, rix, AH_FALSE); 3857 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3858 ctsduration += rt->info[rix].lpAckDuration; 3859 } 3860 /* 3861 * Must disable multi-rate retry when using RTS/CTS. 3862 */ 3863 ismrr = 0; 3864 try0 = ATH_TXMGTTRY; /* XXX */ 3865 } else 3866 ctsrate = 0; 3867 3868 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3869 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3870 sc->sc_hwmap[txrate].ieeerate, -1); 3871 #if NBPFILTER > 0 3872 if (ic->ic_rawbpf) 3873 bpf_mtap(ic->ic_rawbpf, m0); 3874 if (sc->sc_drvbpf) { 3875 u_int64_t tsf = ath_hal_gettsf64(ah); 3876 3877 sc->sc_tx_th.wt_tsf = htole64(tsf); 3878 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3879 if (iswep) 3880 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3881 if (isfrag) 3882 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3883 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3884 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3885 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3886 3887 bpf_mtap2(sc->sc_drvbpf, 3888 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3889 } 3890 #endif 3891 3892 /* 3893 * Determine if a tx interrupt should be generated for 3894 * this descriptor. We take a tx interrupt to reap 3895 * descriptors when the h/w hits an EOL condition or 3896 * when the descriptor is specifically marked to generate 3897 * an interrupt. We periodically mark descriptors in this 3898 * way to insure timely replenishing of the supply needed 3899 * for sending frames. Defering interrupts reduces system 3900 * load and potentially allows more concurrent work to be 3901 * done but if done to aggressively can cause senders to 3902 * backup. 3903 * 3904 * NB: use >= to deal with sc_txintrperiod changing 3905 * dynamically through sysctl. 3906 */ 3907 if (flags & HAL_TXDESC_INTREQ) { 3908 txq->axq_intrcnt = 0; 3909 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3910 flags |= HAL_TXDESC_INTREQ; 3911 txq->axq_intrcnt = 0; 3912 } 3913 3914 /* 3915 * Formulate first tx descriptor with tx controls. 3916 */ 3917 /* XXX check return value? */ 3918 ath_hal_setuptxdesc(ah, ds 3919 , pktlen /* packet length */ 3920 , hdrlen /* header length */ 3921 , atype /* Atheros packet type */ 3922 , ni->ni_txpower /* txpower */ 3923 , txrate, try0 /* series 0 rate/tries */ 3924 , keyix /* key cache index */ 3925 , sc->sc_txantenna /* antenna mode */ 3926 , flags /* flags */ 3927 , ctsrate /* rts/cts rate */ 3928 , ctsduration /* rts/cts duration */ 3929 ); 3930 bf->bf_flags = flags; 3931 /* 3932 * Setup the multi-rate retry state only when we're 3933 * going to use it. This assumes ath_hal_setuptxdesc 3934 * initializes the descriptors (so we don't have to) 3935 * when the hardware supports multi-rate retry and 3936 * we don't use it. 3937 */ 3938 if (ismrr) 3939 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3940 3941 /* 3942 * Fillin the remainder of the descriptor info. 3943 */ 3944 ds0 = ds; 3945 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3946 ds->ds_data = bf->bf_segs[i].ds_addr; 3947 if (i == bf->bf_nseg - 1) 3948 ds->ds_link = 0; 3949 else 3950 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3951 ath_hal_filltxdesc(ah, ds 3952 , bf->bf_segs[i].ds_len /* segment length */ 3953 , i == 0 /* first segment */ 3954 , i == bf->bf_nseg - 1 /* last segment */ 3955 , ds0 /* first descriptor */ 3956 ); 3957 3958 /* NB: The desc swap function becomes void, 3959 * if descriptor swapping is not enabled 3960 */ 3961 ath_desc_swap(ds); 3962 3963 DPRINTF(sc, ATH_DEBUG_XMIT, 3964 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3965 __func__, i, ds->ds_link, ds->ds_data, 3966 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3967 } 3968 /* 3969 * Insert the frame on the outbound list and 3970 * pass it on to the hardware. 3971 */ 3972 ATH_TXQ_LOCK(txq); 3973 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3974 if (txq->axq_link == NULL) { 3975 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3976 DPRINTF(sc, ATH_DEBUG_XMIT, 3977 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 3978 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 3979 txq->axq_depth); 3980 } else { 3981 *txq->axq_link = HTOAH32(bf->bf_daddr); 3982 DPRINTF(sc, ATH_DEBUG_XMIT, 3983 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 3984 __func__, txq->axq_qnum, txq->axq_link, 3985 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3986 } 3987 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3988 /* 3989 * The CAB queue is started from the SWBA handler since 3990 * frames only go out on DTIM and to avoid possible races. 3991 */ 3992 if (txq != sc->sc_cabq) 3993 ath_hal_txstart(ah, txq->axq_qnum); 3994 ATH_TXQ_UNLOCK(txq); 3995 3996 return 0; 3997 } 3998 3999 /* 4000 * Process completed xmit descriptors from the specified queue. 4001 */ 4002 static int 4003 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4004 { 4005 struct ath_hal *ah = sc->sc_ah; 4006 struct ieee80211com *ic = &sc->sc_ic; 4007 struct ath_buf *bf; 4008 struct ath_desc *ds, *ds0; 4009 struct ieee80211_node *ni; 4010 struct ath_node *an; 4011 int sr, lr, pri, nacked; 4012 HAL_STATUS status; 4013 4014 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4015 __func__, txq->axq_qnum, 4016 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4017 txq->axq_link); 4018 nacked = 0; 4019 for (;;) { 4020 ATH_TXQ_LOCK(txq); 4021 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4022 bf = STAILQ_FIRST(&txq->axq_q); 4023 if (bf == NULL) { 4024 txq->axq_link = NULL; 4025 ATH_TXQ_UNLOCK(txq); 4026 break; 4027 } 4028 ds0 = &bf->bf_desc[0]; 4029 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4030 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4031 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4032 ath_printtxbuf(bf, status == HAL_OK); 4033 if (status == HAL_EINPROGRESS) { 4034 ATH_TXQ_UNLOCK(txq); 4035 break; 4036 } 4037 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4038 ATH_TXQ_UNLOCK(txq); 4039 4040 ni = bf->bf_node; 4041 if (ni != NULL) { 4042 an = ATH_NODE(ni); 4043 if (ds->ds_txstat.ts_status == 0) { 4044 u_int8_t txant = ds->ds_txstat.ts_antenna; 4045 sc->sc_stats.ast_ant_tx[txant]++; 4046 sc->sc_ant_tx[txant]++; 4047 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4048 sc->sc_stats.ast_tx_altrate++; 4049 sc->sc_stats.ast_tx_rssi = 4050 ds->ds_txstat.ts_rssi; 4051 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4052 ds->ds_txstat.ts_rssi); 4053 pri = M_WME_GETAC(bf->bf_m); 4054 if (pri >= WME_AC_VO) 4055 ic->ic_wme.wme_hipri_traffic++; 4056 ni->ni_inact = ni->ni_inact_reload; 4057 } else { 4058 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4059 sc->sc_stats.ast_tx_xretries++; 4060 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4061 sc->sc_stats.ast_tx_fifoerr++; 4062 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4063 sc->sc_stats.ast_tx_filtered++; 4064 } 4065 sr = ds->ds_txstat.ts_shortretry; 4066 lr = ds->ds_txstat.ts_longretry; 4067 sc->sc_stats.ast_tx_shortretry += sr; 4068 sc->sc_stats.ast_tx_longretry += lr; 4069 /* 4070 * Hand the descriptor to the rate control algorithm. 4071 */ 4072 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4073 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4074 /* 4075 * If frame was ack'd update the last rx time 4076 * used to workaround phantom bmiss interrupts. 4077 */ 4078 if (ds->ds_txstat.ts_status == 0) 4079 nacked++; 4080 ath_rate_tx_complete(sc, an, ds, ds0); 4081 } 4082 /* 4083 * Reclaim reference to node. 4084 * 4085 * NB: the node may be reclaimed here if, for example 4086 * this is a DEAUTH message that was sent and the 4087 * node was timed out due to inactivity. 4088 */ 4089 ieee80211_free_node(ni); 4090 } 4091 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4092 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4093 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4094 m_freem(bf->bf_m); 4095 bf->bf_m = NULL; 4096 bf->bf_node = NULL; 4097 4098 ATH_TXBUF_LOCK(sc); 4099 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4100 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4101 ATH_TXBUF_UNLOCK(sc); 4102 } 4103 return nacked; 4104 } 4105 4106 static inline int 4107 txqactive(struct ath_hal *ah, int qnum) 4108 { 4109 u_int32_t txqs = 1<<qnum; 4110 ath_hal_gettxintrtxqs(ah, &txqs); 4111 return (txqs & (1<<qnum)); 4112 } 4113 4114 /* 4115 * Deferred processing of transmit interrupt; special-cased 4116 * for a single hardware transmit queue (e.g. 5210 and 5211). 4117 */ 4118 static void 4119 ath_tx_proc_q0(void *arg, int npending) 4120 { 4121 struct ath_softc *sc = arg; 4122 struct ifnet *ifp = &sc->sc_if; 4123 4124 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4125 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4126 } 4127 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4128 ath_tx_processq(sc, sc->sc_cabq); 4129 4130 if (sc->sc_softled) 4131 ath_led_event(sc, ATH_LED_TX); 4132 4133 ath_start(ifp); 4134 } 4135 4136 /* 4137 * Deferred processing of transmit interrupt; special-cased 4138 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4139 */ 4140 static void 4141 ath_tx_proc_q0123(void *arg, int npending) 4142 { 4143 struct ath_softc *sc = arg; 4144 struct ifnet *ifp = &sc->sc_if; 4145 int nacked; 4146 4147 /* 4148 * Process each active queue. 4149 */ 4150 nacked = 0; 4151 if (txqactive(sc->sc_ah, 0)) 4152 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4153 if (txqactive(sc->sc_ah, 1)) 4154 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4155 if (txqactive(sc->sc_ah, 2)) 4156 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4157 if (txqactive(sc->sc_ah, 3)) 4158 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4159 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4160 ath_tx_processq(sc, sc->sc_cabq); 4161 if (nacked) { 4162 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4163 } 4164 4165 if (sc->sc_softled) 4166 ath_led_event(sc, ATH_LED_TX); 4167 4168 ath_start(ifp); 4169 } 4170 4171 /* 4172 * Deferred processing of transmit interrupt. 4173 */ 4174 static void 4175 ath_tx_proc(void *arg, int npending) 4176 { 4177 struct ath_softc *sc = arg; 4178 struct ifnet *ifp = &sc->sc_if; 4179 int i, nacked; 4180 4181 /* 4182 * Process each active queue. 4183 */ 4184 nacked = 0; 4185 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4186 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4187 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4188 if (nacked) { 4189 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4190 } 4191 4192 if (sc->sc_softled) 4193 ath_led_event(sc, ATH_LED_TX); 4194 4195 ath_start(ifp); 4196 } 4197 4198 static void 4199 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4200 { 4201 struct ath_hal *ah = sc->sc_ah; 4202 struct ieee80211_node *ni; 4203 struct ath_buf *bf; 4204 struct ath_desc *ds; 4205 4206 /* 4207 * NB: this assumes output has been stopped and 4208 * we do not need to block ath_tx_tasklet 4209 */ 4210 for (;;) { 4211 ATH_TXQ_LOCK(txq); 4212 bf = STAILQ_FIRST(&txq->axq_q); 4213 if (bf == NULL) { 4214 txq->axq_link = NULL; 4215 ATH_TXQ_UNLOCK(txq); 4216 break; 4217 } 4218 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4219 ATH_TXQ_UNLOCK(txq); 4220 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4221 if (sc->sc_debug & ATH_DEBUG_RESET) 4222 ath_printtxbuf(bf, 4223 ath_hal_txprocdesc(ah, bf->bf_desc, 4224 &ds->ds_txstat) == HAL_OK); 4225 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4226 m_freem(bf->bf_m); 4227 bf->bf_m = NULL; 4228 ni = bf->bf_node; 4229 bf->bf_node = NULL; 4230 if (ni != NULL) { 4231 /* 4232 * Reclaim node reference. 4233 */ 4234 ieee80211_free_node(ni); 4235 } 4236 ATH_TXBUF_LOCK(sc); 4237 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4238 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4239 ATH_TXBUF_UNLOCK(sc); 4240 } 4241 } 4242 4243 static void 4244 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4245 { 4246 struct ath_hal *ah = sc->sc_ah; 4247 4248 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4249 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4250 __func__, txq->axq_qnum, 4251 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4252 txq->axq_link); 4253 } 4254 4255 /* 4256 * Drain the transmit queues and reclaim resources. 4257 */ 4258 static void 4259 ath_draintxq(struct ath_softc *sc) 4260 { 4261 struct ath_hal *ah = sc->sc_ah; 4262 int i; 4263 4264 /* XXX return value */ 4265 if (device_is_active(sc->sc_dev)) { 4266 /* don't touch the hardware if marked invalid */ 4267 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4268 DPRINTF(sc, ATH_DEBUG_RESET, 4269 "%s: beacon queue %p\n", __func__, 4270 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4271 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4272 if (ATH_TXQ_SETUP(sc, i)) 4273 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4274 } 4275 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4276 if (ATH_TXQ_SETUP(sc, i)) 4277 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4278 } 4279 4280 /* 4281 * Disable the receive h/w in preparation for a reset. 4282 */ 4283 static void 4284 ath_stoprecv(struct ath_softc *sc) 4285 { 4286 #define PA2DESC(_sc, _pa) \ 4287 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4288 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4289 struct ath_hal *ah = sc->sc_ah; 4290 u_int64_t tsf; 4291 4292 ath_hal_stoppcurecv(ah); /* disable PCU */ 4293 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4294 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4295 DELAY(3000); /* 3ms is long enough for 1 frame */ 4296 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4297 struct ath_buf *bf; 4298 4299 printf("%s: rx queue %p, link %p\n", __func__, 4300 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4301 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4302 struct ath_desc *ds = bf->bf_desc; 4303 tsf = ath_hal_gettsf64(sc->sc_ah); 4304 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4305 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4306 tsf, &ds->ds_rxstat); 4307 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4308 ath_printrxbuf(bf, status == HAL_OK); 4309 } 4310 } 4311 sc->sc_rxlink = NULL; /* just in case */ 4312 #undef PA2DESC 4313 } 4314 4315 /* 4316 * Enable the receive h/w following a reset. 4317 */ 4318 static int 4319 ath_startrecv(struct ath_softc *sc) 4320 { 4321 struct ath_hal *ah = sc->sc_ah; 4322 struct ath_buf *bf; 4323 4324 sc->sc_rxlink = NULL; 4325 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4326 int error = ath_rxbuf_init(sc, bf); 4327 if (error != 0) { 4328 DPRINTF(sc, ATH_DEBUG_RECV, 4329 "%s: ath_rxbuf_init failed %d\n", 4330 __func__, error); 4331 return error; 4332 } 4333 } 4334 4335 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4336 ath_hal_putrxbuf(ah, bf->bf_daddr); 4337 ath_hal_rxena(ah); /* enable recv descriptors */ 4338 ath_mode_init(sc); /* set filters, etc. */ 4339 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4340 return 0; 4341 } 4342 4343 /* 4344 * Update internal state after a channel change. 4345 */ 4346 static void 4347 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4348 { 4349 struct ieee80211com *ic = &sc->sc_ic; 4350 enum ieee80211_phymode mode; 4351 u_int16_t flags; 4352 4353 /* 4354 * Change channels and update the h/w rate map 4355 * if we're switching; e.g. 11a to 11b/g. 4356 */ 4357 mode = ieee80211_chan2mode(ic, chan); 4358 if (mode != sc->sc_curmode) 4359 ath_setcurmode(sc, mode); 4360 /* 4361 * Update BPF state. NB: ethereal et. al. don't handle 4362 * merged flags well so pick a unique mode for their use. 4363 */ 4364 if (IEEE80211_IS_CHAN_A(chan)) 4365 flags = IEEE80211_CHAN_A; 4366 /* XXX 11g schizophrenia */ 4367 else if (IEEE80211_IS_CHAN_G(chan) || 4368 IEEE80211_IS_CHAN_PUREG(chan)) 4369 flags = IEEE80211_CHAN_G; 4370 else 4371 flags = IEEE80211_CHAN_B; 4372 if (IEEE80211_IS_CHAN_T(chan)) 4373 flags |= IEEE80211_CHAN_TURBO; 4374 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4375 htole16(chan->ic_freq); 4376 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4377 htole16(flags); 4378 } 4379 4380 #if 0 4381 /* 4382 * Poll for a channel clear indication; this is required 4383 * for channels requiring DFS and not previously visited 4384 * and/or with a recent radar detection. 4385 */ 4386 static void 4387 ath_dfswait(void *arg) 4388 { 4389 struct ath_softc *sc = arg; 4390 struct ath_hal *ah = sc->sc_ah; 4391 HAL_CHANNEL hchan; 4392 4393 ath_hal_radar_wait(ah, &hchan); 4394 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4395 if_printf(&sc->sc_if, 4396 "channel %u/0x%x/0x%x has interference\n", 4397 hchan.channel, hchan.channelFlags, hchan.privFlags); 4398 return; 4399 } 4400 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4401 /* XXX should not happen */ 4402 return; 4403 } 4404 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4405 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4406 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4407 if_printf(&sc->sc_if, 4408 "channel %u/0x%x/0x%x marked clear\n", 4409 hchan.channel, hchan.channelFlags, hchan.privFlags); 4410 } else 4411 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4412 } 4413 #endif 4414 4415 /* 4416 * Set/change channels. If the channel is really being changed, 4417 * it's done by reseting the chip. To accomplish this we must 4418 * first cleanup any pending DMA, then restart stuff after a la 4419 * ath_init. 4420 */ 4421 static int 4422 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4423 { 4424 struct ath_hal *ah = sc->sc_ah; 4425 struct ieee80211com *ic = &sc->sc_ic; 4426 HAL_CHANNEL hchan; 4427 4428 /* 4429 * Convert to a HAL channel description with 4430 * the flags constrained to reflect the current 4431 * operating mode. 4432 */ 4433 hchan.channel = chan->ic_freq; 4434 hchan.channelFlags = ath_chan2flags(ic, chan); 4435 4436 DPRINTF(sc, ATH_DEBUG_RESET, 4437 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4438 __func__, 4439 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4440 sc->sc_curchan.channelFlags), 4441 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4442 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4443 hchan.channel, hchan.channelFlags); 4444 if (hchan.channel != sc->sc_curchan.channel || 4445 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4446 HAL_STATUS status; 4447 4448 /* 4449 * To switch channels clear any pending DMA operations; 4450 * wait long enough for the RX fifo to drain, reset the 4451 * hardware at the new frequency, and then re-enable 4452 * the relevant bits of the h/w. 4453 */ 4454 ath_hal_intrset(ah, 0); /* disable interrupts */ 4455 ath_draintxq(sc); /* clear pending tx frames */ 4456 ath_stoprecv(sc); /* turn off frame recv */ 4457 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4458 if_printf(ic->ic_ifp, "%s: unable to reset " 4459 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4460 __func__, ieee80211_chan2ieee(ic, chan), 4461 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4462 return EIO; 4463 } 4464 sc->sc_curchan = hchan; 4465 ath_update_txpow(sc); /* update tx power state */ 4466 ath_restore_diversity(sc); 4467 sc->sc_calinterval = 1; 4468 sc->sc_caltries = 0; 4469 4470 /* 4471 * Re-enable rx framework. 4472 */ 4473 if (ath_startrecv(sc) != 0) { 4474 if_printf(&sc->sc_if, 4475 "%s: unable to restart recv logic\n", __func__); 4476 return EIO; 4477 } 4478 4479 /* 4480 * Change channels and update the h/w rate map 4481 * if we're switching; e.g. 11a to 11b/g. 4482 */ 4483 ic->ic_ibss_chan = chan; 4484 ath_chan_change(sc, chan); 4485 4486 #if 0 4487 /* 4488 * Handle DFS required waiting period to determine 4489 * if channel is clear of radar traffic. 4490 */ 4491 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4492 #define DFS_AND_NOT_CLEAR(_c) \ 4493 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4494 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4495 if_printf(&sc->sc_if, 4496 "wait for DFS clear channel signal\n"); 4497 /* XXX stop sndq */ 4498 sc->sc_if.if_flags |= IFF_OACTIVE; 4499 callout_reset(&sc->sc_dfs_ch, 4500 2 * hz, ath_dfswait, sc); 4501 } else 4502 callout_stop(&sc->sc_dfs_ch); 4503 #undef DFS_NOT_CLEAR 4504 } 4505 #endif 4506 4507 /* 4508 * Re-enable interrupts. 4509 */ 4510 ath_hal_intrset(ah, sc->sc_imask); 4511 } 4512 return 0; 4513 } 4514 4515 static void 4516 ath_next_scan(void *arg) 4517 { 4518 struct ath_softc *sc = arg; 4519 struct ieee80211com *ic = &sc->sc_ic; 4520 int s; 4521 4522 /* don't call ath_start w/o network interrupts blocked */ 4523 s = splnet(); 4524 4525 if (ic->ic_state == IEEE80211_S_SCAN) 4526 ieee80211_next_scan(ic); 4527 splx(s); 4528 } 4529 4530 /* 4531 * Periodically recalibrate the PHY to account 4532 * for temperature/environment changes. 4533 */ 4534 static void 4535 ath_calibrate(void *arg) 4536 { 4537 struct ath_softc *sc = arg; 4538 struct ath_hal *ah = sc->sc_ah; 4539 HAL_BOOL iqCalDone; 4540 4541 sc->sc_stats.ast_per_cal++; 4542 4543 ATH_LOCK(sc); 4544 4545 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4546 /* 4547 * Rfgain is out of bounds, reset the chip 4548 * to load new gain values. 4549 */ 4550 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4551 "%s: rfgain change\n", __func__); 4552 sc->sc_stats.ast_per_rfgain++; 4553 ath_reset(&sc->sc_if); 4554 } 4555 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4556 DPRINTF(sc, ATH_DEBUG_ANY, 4557 "%s: calibration of channel %u failed\n", 4558 __func__, sc->sc_curchan.channel); 4559 sc->sc_stats.ast_per_calfail++; 4560 } 4561 /* 4562 * Calibrate noise floor data again in case of change. 4563 */ 4564 ath_hal_process_noisefloor(ah); 4565 /* 4566 * Poll more frequently when the IQ calibration is in 4567 * progress to speedup loading the final settings. 4568 * We temper this aggressive polling with an exponential 4569 * back off after 4 tries up to ath_calinterval. 4570 */ 4571 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4572 sc->sc_caltries = 0; 4573 sc->sc_calinterval = ath_calinterval; 4574 } else if (sc->sc_caltries > 4) { 4575 sc->sc_caltries = 0; 4576 sc->sc_calinterval <<= 1; 4577 if (sc->sc_calinterval > ath_calinterval) 4578 sc->sc_calinterval = ath_calinterval; 4579 } 4580 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 4581 ("bad calibration interval %u", sc->sc_calinterval)); 4582 4583 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4584 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4585 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4586 sc->sc_caltries++; 4587 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4588 ath_calibrate, sc); 4589 ATH_UNLOCK(sc); 4590 } 4591 4592 static int 4593 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4594 { 4595 struct ifnet *ifp = ic->ic_ifp; 4596 struct ath_softc *sc = ifp->if_softc; 4597 struct ath_hal *ah = sc->sc_ah; 4598 struct ieee80211_node *ni; 4599 int i, error; 4600 const u_int8_t *bssid; 4601 u_int32_t rfilt; 4602 static const HAL_LED_STATE leds[] = { 4603 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4604 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4605 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4606 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4607 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4608 }; 4609 4610 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4611 ieee80211_state_name[ic->ic_state], 4612 ieee80211_state_name[nstate]); 4613 4614 callout_stop(&sc->sc_scan_ch); 4615 callout_stop(&sc->sc_cal_ch); 4616 #if 0 4617 callout_stop(&sc->sc_dfs_ch); 4618 #endif 4619 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4620 4621 if (nstate == IEEE80211_S_INIT) { 4622 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4623 /* 4624 * NB: disable interrupts so we don't rx frames. 4625 */ 4626 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4627 /* 4628 * Notify the rate control algorithm. 4629 */ 4630 ath_rate_newstate(sc, nstate); 4631 goto done; 4632 } 4633 ni = ic->ic_bss; 4634 error = ath_chan_set(sc, ic->ic_curchan); 4635 if (error != 0) 4636 goto bad; 4637 rfilt = ath_calcrxfilter(sc, nstate); 4638 if (nstate == IEEE80211_S_SCAN) 4639 bssid = ifp->if_broadcastaddr; 4640 else 4641 bssid = ni->ni_bssid; 4642 ath_hal_setrxfilter(ah, rfilt); 4643 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4644 __func__, rfilt, ether_sprintf(bssid)); 4645 4646 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4647 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4648 else 4649 ath_hal_setassocid(ah, bssid, 0); 4650 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4651 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4652 if (ath_hal_keyisvalid(ah, i)) 4653 ath_hal_keysetmac(ah, i, bssid); 4654 } 4655 4656 /* 4657 * Notify the rate control algorithm so rates 4658 * are setup should ath_beacon_alloc be called. 4659 */ 4660 ath_rate_newstate(sc, nstate); 4661 4662 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4663 /* nothing to do */; 4664 } else if (nstate == IEEE80211_S_RUN) { 4665 DPRINTF(sc, ATH_DEBUG_STATE, 4666 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4667 "capinfo=0x%04x chan=%d\n" 4668 , __func__ 4669 , ic->ic_flags 4670 , ni->ni_intval 4671 , ether_sprintf(ni->ni_bssid) 4672 , ni->ni_capinfo 4673 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4674 4675 switch (ic->ic_opmode) { 4676 case IEEE80211_M_HOSTAP: 4677 case IEEE80211_M_IBSS: 4678 /* 4679 * Allocate and setup the beacon frame. 4680 * 4681 * Stop any previous beacon DMA. This may be 4682 * necessary, for example, when an ibss merge 4683 * causes reconfiguration; there will be a state 4684 * transition from RUN->RUN that means we may 4685 * be called with beacon transmission active. 4686 */ 4687 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4688 ath_beacon_free(sc); 4689 error = ath_beacon_alloc(sc, ni); 4690 if (error != 0) 4691 goto bad; 4692 /* 4693 * If joining an adhoc network defer beacon timer 4694 * configuration to the next beacon frame so we 4695 * have a current TSF to use. Otherwise we're 4696 * starting an ibss/bss so there's no need to delay. 4697 */ 4698 if (ic->ic_opmode == IEEE80211_M_IBSS && 4699 ic->ic_bss->ni_tstamp.tsf != 0) 4700 sc->sc_syncbeacon = 1; 4701 else 4702 ath_beacon_config(sc); 4703 break; 4704 case IEEE80211_M_STA: 4705 /* 4706 * Allocate a key cache slot to the station. 4707 */ 4708 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4709 sc->sc_hasclrkey && 4710 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4711 ath_setup_stationkey(ni); 4712 /* 4713 * Defer beacon timer configuration to the next 4714 * beacon frame so we have a current TSF to use 4715 * (any TSF collected when scanning is likely old). 4716 */ 4717 sc->sc_syncbeacon = 1; 4718 break; 4719 default: 4720 break; 4721 } 4722 /* 4723 * Let the hal process statistics collected during a 4724 * scan so it can provide calibrated noise floor data. 4725 */ 4726 ath_hal_process_noisefloor(ah); 4727 /* 4728 * Reset rssi stats; maybe not the best place... 4729 */ 4730 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4731 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4732 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4733 } else { 4734 ath_hal_intrset(ah, 4735 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4736 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4737 } 4738 done: 4739 /* 4740 * Invoke the parent method to complete the work. 4741 */ 4742 error = sc->sc_newstate(ic, nstate, arg); 4743 /* 4744 * Finally, start any timers. 4745 */ 4746 if (nstate == IEEE80211_S_RUN) { 4747 /* start periodic recalibration timer */ 4748 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4749 ath_calibrate, sc); 4750 } else if (nstate == IEEE80211_S_SCAN) { 4751 /* start ap/neighbor scan timer */ 4752 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4753 ath_next_scan, sc); 4754 } 4755 bad: 4756 return error; 4757 } 4758 4759 /* 4760 * Allocate a key cache slot to the station so we can 4761 * setup a mapping from key index to node. The key cache 4762 * slot is needed for managing antenna state and for 4763 * compression when stations do not use crypto. We do 4764 * it uniliaterally here; if crypto is employed this slot 4765 * will be reassigned. 4766 */ 4767 static void 4768 ath_setup_stationkey(struct ieee80211_node *ni) 4769 { 4770 struct ieee80211com *ic = ni->ni_ic; 4771 struct ath_softc *sc = ic->ic_ifp->if_softc; 4772 ieee80211_keyix keyix, rxkeyix; 4773 4774 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4775 /* 4776 * Key cache is full; we'll fall back to doing 4777 * the more expensive lookup in software. Note 4778 * this also means no h/w compression. 4779 */ 4780 /* XXX msg+statistic */ 4781 } else { 4782 /* XXX locking? */ 4783 ni->ni_ucastkey.wk_keyix = keyix; 4784 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4785 /* NB: this will create a pass-thru key entry */ 4786 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4787 } 4788 } 4789 4790 /* 4791 * Setup driver-specific state for a newly associated node. 4792 * Note that we're called also on a re-associate, the isnew 4793 * param tells us if this is the first time or not. 4794 */ 4795 static void 4796 ath_newassoc(struct ieee80211_node *ni, int isnew) 4797 { 4798 struct ieee80211com *ic = ni->ni_ic; 4799 struct ath_softc *sc = ic->ic_ifp->if_softc; 4800 4801 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4802 if (isnew && 4803 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4804 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4805 ("new assoc with a unicast key already setup (keyix %u)", 4806 ni->ni_ucastkey.wk_keyix)); 4807 ath_setup_stationkey(ni); 4808 } 4809 } 4810 4811 static int 4812 ath_getchannels(struct ath_softc *sc, u_int cc, 4813 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4814 { 4815 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4816 struct ieee80211com *ic = &sc->sc_ic; 4817 struct ifnet *ifp = &sc->sc_if; 4818 struct ath_hal *ah = sc->sc_ah; 4819 HAL_CHANNEL *chans; 4820 int i, ix, nchan; 4821 4822 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4823 M_TEMP, M_NOWAIT); 4824 if (chans == NULL) { 4825 if_printf(ifp, "unable to allocate channel table\n"); 4826 return ENOMEM; 4827 } 4828 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4829 NULL, 0, NULL, 4830 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4831 u_int32_t rd; 4832 4833 (void)ath_hal_getregdomain(ah, &rd); 4834 if_printf(ifp, "unable to collect channel list from hal; " 4835 "regdomain likely %u country code %u\n", rd, cc); 4836 free(chans, M_TEMP); 4837 return EINVAL; 4838 } 4839 4840 /* 4841 * Convert HAL channels to ieee80211 ones and insert 4842 * them in the table according to their channel number. 4843 */ 4844 for (i = 0; i < nchan; i++) { 4845 HAL_CHANNEL *c = &chans[i]; 4846 u_int16_t flags; 4847 4848 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4849 if (ix > IEEE80211_CHAN_MAX) { 4850 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4851 ix, c->channel, c->channelFlags); 4852 continue; 4853 } 4854 if (ix < 0) { 4855 /* XXX can't handle stuff <2400 right now */ 4856 if (bootverbose) 4857 if_printf(ifp, "hal channel %d (%u/%x) " 4858 "cannot be handled; ignored\n", 4859 ix, c->channel, c->channelFlags); 4860 continue; 4861 } 4862 /* 4863 * Calculate net80211 flags; most are compatible 4864 * but some need massaging. Note the static turbo 4865 * conversion can be removed once net80211 is updated 4866 * to understand static vs. dynamic turbo. 4867 */ 4868 flags = c->channelFlags & COMPAT; 4869 if (c->channelFlags & CHANNEL_STURBO) 4870 flags |= IEEE80211_CHAN_TURBO; 4871 if (ic->ic_channels[ix].ic_freq == 0) { 4872 ic->ic_channels[ix].ic_freq = c->channel; 4873 ic->ic_channels[ix].ic_flags = flags; 4874 } else { 4875 /* channels overlap; e.g. 11g and 11b */ 4876 ic->ic_channels[ix].ic_flags |= flags; 4877 } 4878 } 4879 free(chans, M_TEMP); 4880 return 0; 4881 #undef COMPAT 4882 } 4883 4884 static void 4885 ath_led_done(void *arg) 4886 { 4887 struct ath_softc *sc = arg; 4888 4889 sc->sc_blinking = 0; 4890 } 4891 4892 /* 4893 * Turn the LED off: flip the pin and then set a timer so no 4894 * update will happen for the specified duration. 4895 */ 4896 static void 4897 ath_led_off(void *arg) 4898 { 4899 struct ath_softc *sc = arg; 4900 4901 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4902 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4903 } 4904 4905 /* 4906 * Blink the LED according to the specified on/off times. 4907 */ 4908 static void 4909 ath_led_blink(struct ath_softc *sc, int on, int off) 4910 { 4911 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4912 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4913 sc->sc_blinking = 1; 4914 sc->sc_ledoff = off; 4915 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4916 } 4917 4918 static void 4919 ath_led_event(struct ath_softc *sc, int event) 4920 { 4921 4922 sc->sc_ledevent = ticks; /* time of last event */ 4923 if (sc->sc_blinking) /* don't interrupt active blink */ 4924 return; 4925 switch (event) { 4926 case ATH_LED_POLL: 4927 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4928 sc->sc_hwmap[0].ledoff); 4929 break; 4930 case ATH_LED_TX: 4931 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4932 sc->sc_hwmap[sc->sc_txrate].ledoff); 4933 break; 4934 case ATH_LED_RX: 4935 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4936 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4937 break; 4938 } 4939 } 4940 4941 static void 4942 ath_update_txpow(struct ath_softc *sc) 4943 { 4944 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4945 struct ieee80211com *ic = &sc->sc_ic; 4946 struct ath_hal *ah = sc->sc_ah; 4947 u_int32_t txpow; 4948 4949 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4950 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4951 /* read back in case value is clamped */ 4952 (void)ath_hal_gettxpowlimit(ah, &txpow); 4953 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4954 } 4955 /* 4956 * Fetch max tx power level for status requests. 4957 */ 4958 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4959 ic->ic_bss->ni_txpower = txpow; 4960 } 4961 4962 static void 4963 rate_setup(struct ath_softc *sc, 4964 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 4965 { 4966 int i, maxrates; 4967 4968 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4969 DPRINTF(sc, ATH_DEBUG_ANY, 4970 "%s: rate table too small (%u > %u)\n", 4971 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4972 maxrates = IEEE80211_RATE_MAXSIZE; 4973 } else 4974 maxrates = rt->rateCount; 4975 for (i = 0; i < maxrates; i++) 4976 rs->rs_rates[i] = rt->info[i].dot11Rate; 4977 rs->rs_nrates = maxrates; 4978 } 4979 4980 static int 4981 ath_rate_setup(struct ath_softc *sc, u_int mode) 4982 { 4983 struct ath_hal *ah = sc->sc_ah; 4984 struct ieee80211com *ic = &sc->sc_ic; 4985 const HAL_RATE_TABLE *rt; 4986 4987 switch (mode) { 4988 case IEEE80211_MODE_11A: 4989 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 4990 break; 4991 case IEEE80211_MODE_11B: 4992 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 4993 break; 4994 case IEEE80211_MODE_11G: 4995 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 4996 break; 4997 case IEEE80211_MODE_TURBO_A: 4998 /* XXX until static/dynamic turbo is fixed */ 4999 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5000 break; 5001 case IEEE80211_MODE_TURBO_G: 5002 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5003 break; 5004 default: 5005 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5006 __func__, mode); 5007 return 0; 5008 } 5009 sc->sc_rates[mode] = rt; 5010 if (rt != NULL) { 5011 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5012 return 1; 5013 } else 5014 return 0; 5015 } 5016 5017 static void 5018 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5019 { 5020 #define N(a) (sizeof(a)/sizeof(a[0])) 5021 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5022 static const struct { 5023 u_int rate; /* tx/rx 802.11 rate */ 5024 u_int16_t timeOn; /* LED on time (ms) */ 5025 u_int16_t timeOff; /* LED off time (ms) */ 5026 } blinkrates[] = { 5027 { 108, 40, 10 }, 5028 { 96, 44, 11 }, 5029 { 72, 50, 13 }, 5030 { 48, 57, 14 }, 5031 { 36, 67, 16 }, 5032 { 24, 80, 20 }, 5033 { 22, 100, 25 }, 5034 { 18, 133, 34 }, 5035 { 12, 160, 40 }, 5036 { 10, 200, 50 }, 5037 { 6, 240, 58 }, 5038 { 4, 267, 66 }, 5039 { 2, 400, 100 }, 5040 { 0, 500, 130 }, 5041 }; 5042 const HAL_RATE_TABLE *rt; 5043 int i, j; 5044 5045 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5046 rt = sc->sc_rates[mode]; 5047 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5048 for (i = 0; i < rt->rateCount; i++) 5049 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5050 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5051 for (i = 0; i < 32; i++) { 5052 u_int8_t ix = rt->rateCodeToIndex[i]; 5053 if (ix == 0xff) { 5054 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5055 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5056 continue; 5057 } 5058 sc->sc_hwmap[i].ieeerate = 5059 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5060 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5061 if (rt->info[ix].shortPreamble || 5062 rt->info[ix].phy == IEEE80211_T_OFDM) 5063 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5064 /* NB: receive frames include FCS */ 5065 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5066 IEEE80211_RADIOTAP_F_FCS; 5067 /* setup blink rate table to avoid per-packet lookup */ 5068 for (j = 0; j < N(blinkrates)-1; j++) 5069 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5070 break; 5071 /* NB: this uses the last entry if the rate isn't found */ 5072 /* XXX beware of overlow */ 5073 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5074 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5075 } 5076 sc->sc_currates = rt; 5077 sc->sc_curmode = mode; 5078 /* 5079 * All protection frames are transmited at 2Mb/s for 5080 * 11g, otherwise at 1Mb/s. 5081 */ 5082 if (mode == IEEE80211_MODE_11G) 5083 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5084 else 5085 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5086 /* rate index used to send management frames */ 5087 sc->sc_minrateix = 0; 5088 /* 5089 * Setup multicast rate state. 5090 */ 5091 /* XXX layering violation */ 5092 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5093 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5094 /* NB: caller is responsible for reseting rate control state */ 5095 #undef N 5096 } 5097 5098 #ifdef AR_DEBUG 5099 static void 5100 ath_printrxbuf(struct ath_buf *bf, int done) 5101 { 5102 struct ath_desc *ds; 5103 int i; 5104 5105 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5106 printf("R%d (%p %" PRIx64 5107 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5108 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5109 ds->ds_link, ds->ds_data, 5110 ds->ds_ctl0, ds->ds_ctl1, 5111 ds->ds_hw[0], ds->ds_hw[1], 5112 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5113 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5114 } 5115 } 5116 5117 static void 5118 ath_printtxbuf(struct ath_buf *bf, int done) 5119 { 5120 struct ath_desc *ds; 5121 int i; 5122 5123 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5124 printf("T%d (%p %" PRIx64 5125 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5126 i, ds, 5127 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5128 ds->ds_link, ds->ds_data, 5129 ds->ds_ctl0, ds->ds_ctl1, 5130 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5131 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5132 } 5133 } 5134 #endif /* AR_DEBUG */ 5135 5136 static void 5137 ath_watchdog(struct ifnet *ifp) 5138 { 5139 struct ath_softc *sc = ifp->if_softc; 5140 struct ieee80211com *ic = &sc->sc_ic; 5141 struct ath_txq *axq; 5142 int i; 5143 5144 ifp->if_timer = 0; 5145 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5146 !device_is_active(sc->sc_dev)) 5147 return; 5148 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5149 if (!ATH_TXQ_SETUP(sc, i)) 5150 continue; 5151 axq = &sc->sc_txq[i]; 5152 ATH_TXQ_LOCK(axq); 5153 if (axq->axq_timer == 0) 5154 ; 5155 else if (--axq->axq_timer == 0) { 5156 ATH_TXQ_UNLOCK(axq); 5157 if_printf(ifp, "device timeout (txq %d, " 5158 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5159 if (sc->sc_txintrperiod > 1) 5160 sc->sc_txintrperiod--; 5161 ath_reset(ifp); 5162 ifp->if_oerrors++; 5163 sc->sc_stats.ast_watchdog++; 5164 break; 5165 } else 5166 ifp->if_timer = 1; 5167 ATH_TXQ_UNLOCK(axq); 5168 } 5169 ieee80211_watchdog(ic); 5170 } 5171 5172 /* 5173 * Diagnostic interface to the HAL. This is used by various 5174 * tools to do things like retrieve register contents for 5175 * debugging. The mechanism is intentionally opaque so that 5176 * it can change frequently w/o concern for compatiblity. 5177 */ 5178 static int 5179 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5180 { 5181 struct ath_hal *ah = sc->sc_ah; 5182 u_int id = ad->ad_id & ATH_DIAG_ID; 5183 void *indata = NULL; 5184 void *outdata = NULL; 5185 u_int32_t insize = ad->ad_in_size; 5186 u_int32_t outsize = ad->ad_out_size; 5187 int error = 0; 5188 5189 if (ad->ad_id & ATH_DIAG_IN) { 5190 /* 5191 * Copy in data. 5192 */ 5193 indata = malloc(insize, M_TEMP, M_NOWAIT); 5194 if (indata == NULL) { 5195 error = ENOMEM; 5196 goto bad; 5197 } 5198 error = copyin(ad->ad_in_data, indata, insize); 5199 if (error) 5200 goto bad; 5201 } 5202 if (ad->ad_id & ATH_DIAG_DYN) { 5203 /* 5204 * Allocate a buffer for the results (otherwise the HAL 5205 * returns a pointer to a buffer where we can read the 5206 * results). Note that we depend on the HAL leaving this 5207 * pointer for us to use below in reclaiming the buffer; 5208 * may want to be more defensive. 5209 */ 5210 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5211 if (outdata == NULL) { 5212 error = ENOMEM; 5213 goto bad; 5214 } 5215 } 5216 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5217 if (outsize < ad->ad_out_size) 5218 ad->ad_out_size = outsize; 5219 if (outdata != NULL) 5220 error = copyout(outdata, ad->ad_out_data, 5221 ad->ad_out_size); 5222 } else { 5223 error = EINVAL; 5224 } 5225 bad: 5226 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5227 free(indata, M_TEMP); 5228 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5229 free(outdata, M_TEMP); 5230 return error; 5231 } 5232 5233 static int 5234 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5235 { 5236 #define IS_RUNNING(ifp) \ 5237 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5238 struct ath_softc *sc = ifp->if_softc; 5239 struct ieee80211com *ic = &sc->sc_ic; 5240 struct ifreq *ifr = (struct ifreq *)data; 5241 int error = 0; 5242 5243 ATH_LOCK(sc); 5244 switch (cmd) { 5245 case SIOCSIFFLAGS: 5246 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5247 break; 5248 if (IS_RUNNING(ifp)) { 5249 /* 5250 * To avoid rescanning another access point, 5251 * do not call ath_init() here. Instead, 5252 * only reflect promisc mode settings. 5253 */ 5254 ath_mode_init(sc); 5255 } else if (ifp->if_flags & IFF_UP) { 5256 /* 5257 * Beware of being called during attach/detach 5258 * to reset promiscuous mode. In that case we 5259 * will still be marked UP but not RUNNING. 5260 * However trying to re-init the interface 5261 * is the wrong thing to do as we've already 5262 * torn down much of our state. There's 5263 * probably a better way to deal with this. 5264 */ 5265 error = ath_init(sc); 5266 } else if (device_is_active(sc->sc_dev)) 5267 ath_stop_locked(ifp, 1); 5268 break; 5269 case SIOCADDMULTI: 5270 case SIOCDELMULTI: 5271 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5272 if (ifp->if_flags & IFF_RUNNING) 5273 ath_mode_init(sc); 5274 error = 0; 5275 } 5276 break; 5277 case SIOCGATHSTATS: 5278 /* NB: embed these numbers to get a consistent view */ 5279 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5280 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5281 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5282 ATH_UNLOCK(sc); 5283 /* 5284 * NB: Drop the softc lock in case of a page fault; 5285 * we'll accept any potential inconsisentcy in the 5286 * statistics. The alternative is to copy the data 5287 * to a local structure. 5288 */ 5289 return copyout(&sc->sc_stats, 5290 ifr->ifr_data, sizeof (sc->sc_stats)); 5291 case SIOCGATHDIAG: 5292 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5293 break; 5294 default: 5295 error = ieee80211_ioctl(ic, cmd, data); 5296 if (error != ENETRESET) 5297 ; 5298 else if (IS_RUNNING(ifp) && 5299 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5300 error = ath_init(sc); 5301 else 5302 error = 0; 5303 break; 5304 } 5305 ATH_UNLOCK(sc); 5306 return error; 5307 #undef IS_RUNNING 5308 } 5309 5310 #if NBPFILTER > 0 5311 static void 5312 ath_bpfattach(struct ath_softc *sc) 5313 { 5314 struct ifnet *ifp = &sc->sc_if; 5315 5316 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 5317 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5318 &sc->sc_drvbpf); 5319 /* 5320 * Initialize constant fields. 5321 * XXX make header lengths a multiple of 32-bits so subsequent 5322 * headers are properly aligned; this is a kludge to keep 5323 * certain applications happy. 5324 * 5325 * NB: the channel is setup each time we transition to the 5326 * RUN state to avoid filling it in for each frame. 5327 */ 5328 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5329 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5330 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5331 5332 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5333 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5334 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5335 } 5336 #endif 5337 5338 /* 5339 * Announce various information on device/driver attach. 5340 */ 5341 static void 5342 ath_announce(struct ath_softc *sc) 5343 { 5344 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5345 struct ifnet *ifp = &sc->sc_if; 5346 struct ath_hal *ah = sc->sc_ah; 5347 u_int modes, cc; 5348 5349 if_printf(ifp, "mac %d.%d phy %d.%d", 5350 ah->ah_macVersion, ah->ah_macRev, 5351 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5352 /* 5353 * Print radio revision(s). We check the wireless modes 5354 * to avoid falsely printing revs for inoperable parts. 5355 * Dual-band radio revs are returned in the 5 GHz rev number. 5356 */ 5357 ath_hal_getcountrycode(ah, &cc); 5358 modes = ath_hal_getwirelessmodes(ah, cc); 5359 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5360 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5361 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5362 ah->ah_analog5GhzRev >> 4, 5363 ah->ah_analog5GhzRev & 0xf, 5364 ah->ah_analog2GhzRev >> 4, 5365 ah->ah_analog2GhzRev & 0xf); 5366 else 5367 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5368 ah->ah_analog5GhzRev & 0xf); 5369 } else 5370 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5371 ah->ah_analog5GhzRev & 0xf); 5372 printf("\n"); 5373 if (bootverbose) { 5374 int i; 5375 for (i = 0; i <= WME_AC_VO; i++) { 5376 struct ath_txq *txq = sc->sc_ac2q[i]; 5377 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5378 txq->axq_qnum, ieee80211_wme_acnames[i]); 5379 } 5380 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5381 sc->sc_cabq->axq_qnum); 5382 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5383 } 5384 if (ath_rxbuf != ATH_RXBUF) 5385 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5386 if (ath_txbuf != ATH_TXBUF) 5387 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5388 #undef HAL_MODE_DUALBAND 5389 } 5390
Indexes created Thu Oct 02 07:10:07 GMT 2025