ath.c revision 1.124
1 /* $NetBSD: ath.c,v 1.124 2018/06/26 06:48:00 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.124 2018/06/26 06:48:00 msaitoh Exp $"); 45 #endif 46 47 /* 48 * Driver for the Atheros Wireless LAN controller. 49 * 50 * This software is derived from work of Atsushi Onoe; his contribution 51 * is greatly appreciated. 52 */ 53 54 #ifdef _KERNEL_OPT 55 #include "opt_inet.h" 56 #endif 57 58 #include <sys/param.h> 59 #include <sys/reboot.h> 60 #include <sys/systm.h> 61 #include <sys/types.h> 62 #include <sys/sysctl.h> 63 #include <sys/mbuf.h> 64 #include <sys/malloc.h> 65 #include <sys/kernel.h> 66 #include <sys/socket.h> 67 #include <sys/sockio.h> 68 #include <sys/errno.h> 69 #include <sys/callout.h> 70 #include <sys/bus.h> 71 #include <sys/endian.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_arp.h> 78 #include <net/if_ether.h> 79 #include <net/if_llc.h> 80 81 #include <net80211/ieee80211_netbsd.h> 82 #include <net80211/ieee80211_var.h> 83 84 #include <net/bpf.h> 85 86 #ifdef INET 87 #include <netinet/in.h> 88 #endif 89 90 #include <sys/device.h> 91 #include <dev/ic/ath_netbsd.h> 92 93 #define AR_DEBUG 94 #include <dev/ic/athvar.h> 95 #include "ah_desc.h" 96 #include "ah_devid.h" /* XXX for softled */ 97 #include "opt_ah.h" 98 99 #ifdef ATH_TX99_DIAG 100 #include <dev/ath/ath_tx99/ath_tx99.h> 101 #endif 102 103 /* unaligned little endian access */ 104 #define LE_READ_2(p) \ 105 ((u_int16_t) \ 106 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 107 #define LE_READ_4(p) \ 108 ((u_int32_t) \ 109 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 110 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 111 112 enum { 113 ATH_LED_TX, 114 ATH_LED_RX, 115 ATH_LED_POLL, 116 }; 117 118 #ifdef AH_NEED_DESC_SWAP 119 #define HTOAH32(x) htole32(x) 120 #else 121 #define HTOAH32(x) (x) 122 #endif 123 124 static int ath_ifinit(struct ifnet *); 125 static int ath_init(struct ath_softc *); 126 static void ath_stop_locked(struct ifnet *, int); 127 static void ath_stop(struct ifnet *, int); 128 static void ath_start(struct ifnet *); 129 static int ath_media_change(struct ifnet *); 130 static void ath_watchdog(struct ifnet *); 131 static int ath_ioctl(struct ifnet *, u_long, void *); 132 static void ath_fatal_proc(void *, int); 133 static void ath_rxorn_proc(void *, int); 134 static void ath_bmiss_proc(void *, int); 135 static void ath_radar_proc(void *, int); 136 static int ath_key_alloc(struct ieee80211com *, 137 const struct ieee80211_key *, 138 ieee80211_keyix *, ieee80211_keyix *); 139 static int ath_key_delete(struct ieee80211com *, 140 const struct ieee80211_key *); 141 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 142 const u_int8_t mac[IEEE80211_ADDR_LEN]); 143 static void ath_key_update_begin(struct ieee80211com *); 144 static void ath_key_update_end(struct ieee80211com *); 145 static void ath_mode_init(struct ath_softc *); 146 static void ath_setslottime(struct ath_softc *); 147 static void ath_updateslot(struct ifnet *); 148 static int ath_beaconq_setup(struct ath_hal *); 149 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 150 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 151 static void ath_beacon_proc(void *, int); 152 static void ath_bstuck_proc(void *, int); 153 static void ath_beacon_free(struct ath_softc *); 154 static void ath_beacon_config(struct ath_softc *); 155 static void ath_descdma_cleanup(struct ath_softc *sc, 156 struct ath_descdma *, ath_bufhead *); 157 static int ath_desc_alloc(struct ath_softc *); 158 static void ath_desc_free(struct ath_softc *); 159 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 160 static void ath_node_free(struct ieee80211_node *); 161 static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 162 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 163 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 164 struct ieee80211_node *ni, 165 int subtype, int rssi, u_int32_t rstamp); 166 static void ath_setdefantenna(struct ath_softc *, u_int); 167 static void ath_rx_proc(void *, int); 168 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 169 static int ath_tx_setup(struct ath_softc *, int, int); 170 static int ath_wme_update(struct ieee80211com *); 171 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 172 static void ath_tx_cleanup(struct ath_softc *); 173 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 174 struct ath_buf *, struct mbuf *); 175 static void ath_tx_proc_q0(void *, int); 176 static void ath_tx_proc_q0123(void *, int); 177 static void ath_tx_proc(void *, int); 178 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 179 static void ath_draintxq(struct ath_softc *); 180 static void ath_stoprecv(struct ath_softc *); 181 static int ath_startrecv(struct ath_softc *); 182 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 183 static void ath_next_scan(void *); 184 static void ath_calibrate(void *); 185 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 186 static void ath_setup_stationkey(struct ieee80211_node *); 187 static void ath_newassoc(struct ieee80211_node *, int); 188 static int ath_getchannels(struct ath_softc *, u_int cc, 189 HAL_BOOL outdoor, HAL_BOOL xchanmode); 190 static void ath_led_event(struct ath_softc *, int); 191 static void ath_update_txpow(struct ath_softc *); 192 static void ath_freetx(struct mbuf *); 193 static void ath_restore_diversity(struct ath_softc *); 194 195 static int ath_rate_setup(struct ath_softc *, u_int mode); 196 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 197 198 static void ath_bpfattach(struct ath_softc *); 199 static void ath_announce(struct ath_softc *); 200 201 #ifdef __NetBSD__ 202 #define ATH_TASK_FUNC(__func) \ 203 static void __CONCAT(__func, _si)(void *arg) \ 204 { \ 205 __func(arg, 1); \ 206 } 207 ATH_TASK_FUNC(ath_rx_proc); 208 ATH_TASK_FUNC(ath_rxorn_proc); 209 ATH_TASK_FUNC(ath_fatal_proc); 210 ATH_TASK_FUNC(ath_bmiss_proc); 211 ATH_TASK_FUNC(ath_bstuck_proc); 212 ATH_TASK_FUNC(ath_radar_proc); 213 ATH_TASK_FUNC(ath_tx_proc_q0); 214 ATH_TASK_FUNC(ath_tx_proc_q0123); 215 ATH_TASK_FUNC(ath_tx_proc); 216 #endif 217 218 int ath_dwelltime = 200; /* 5 channels/second */ 219 int ath_calinterval = 30; /* calibrate every 30 secs */ 220 int ath_outdoor = AH_TRUE; /* outdoor operation */ 221 int ath_xchanmode = AH_TRUE; /* enable extended channels */ 222 int ath_countrycode = CTRY_DEFAULT; /* country code */ 223 int ath_regdomain = 0; /* regulatory domain */ 224 int ath_debug = 0; 225 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 226 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 227 228 #ifdef AR_DEBUG 229 enum { 230 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 231 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 232 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 233 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 234 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 235 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 236 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 237 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 238 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 239 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 240 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 241 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 242 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 243 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 244 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 245 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 246 ATH_DEBUG_NODE = 0x00080000, /* node management */ 247 ATH_DEBUG_LED = 0x00100000, /* led management */ 248 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 249 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 250 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 251 ATH_DEBUG_ANY = 0xffffffff 252 }; 253 #define IFF_DUMPPKTS(sc, m) \ 254 ((sc->sc_debug & (m)) || \ 255 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 256 #define DPRINTF(sc, m, fmt, ...) do { \ 257 if (sc->sc_debug & (m)) \ 258 printf(fmt, __VA_ARGS__); \ 259 } while (0) 260 #define KEYPRINTF(sc, ix, hk, mac) do { \ 261 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 262 ath_keyprint(__func__, ix, hk, mac); \ 263 } while (0) 264 static void ath_printrxbuf(struct ath_buf *bf, int); 265 static void ath_printtxbuf(struct ath_buf *bf, int); 266 #else 267 #define IFF_DUMPPKTS(sc, m) \ 268 ((sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 269 #define DPRINTF(m, fmt, ...) 270 #define KEYPRINTF(sc, k, ix, mac) 271 #endif 272 273 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 274 275 int 276 ath_attach(u_int16_t devid, struct ath_softc *sc) 277 { 278 struct ifnet *ifp = &sc->sc_if; 279 struct ieee80211com *ic = &sc->sc_ic; 280 struct ath_hal *ah = NULL; 281 HAL_STATUS status; 282 int error = 0, i; 283 284 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 285 286 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 287 288 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 289 290 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 291 if (ah == NULL) { 292 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 293 status); 294 error = ENXIO; 295 goto bad; 296 } 297 if (ah->ah_abi != HAL_ABI_VERSION) { 298 if_printf(ifp, "HAL ABI mismatch detected " 299 "(HAL:0x%x != driver:0x%x)\n", 300 ah->ah_abi, HAL_ABI_VERSION); 301 error = ENXIO; 302 goto bad; 303 } 304 sc->sc_ah = ah; 305 306 if (!prop_dictionary_set_bool(device_properties(sc->sc_dev), 307 "pmf-powerdown", false)) 308 goto bad; 309 310 /* 311 * Check if the MAC has multi-rate retry support. 312 * We do this by trying to setup a fake extended 313 * descriptor. MAC's that don't have support will 314 * return false w/o doing anything. MAC's that do 315 * support it will return true w/o doing anything. 316 */ 317 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 318 319 /* 320 * Check if the device has hardware counters for PHY 321 * errors. If so we need to enable the MIB interrupt 322 * so we can act on stat triggers. 323 */ 324 if (ath_hal_hwphycounters(ah)) 325 sc->sc_needmib = 1; 326 327 /* 328 * Get the hardware key cache size. 329 */ 330 sc->sc_keymax = ath_hal_keycachesize(ah); 331 if (sc->sc_keymax > ATH_KEYMAX) { 332 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 333 ATH_KEYMAX, sc->sc_keymax); 334 sc->sc_keymax = ATH_KEYMAX; 335 } 336 /* 337 * Reset the key cache since some parts do not 338 * reset the contents on initial power up. 339 */ 340 for (i = 0; i < sc->sc_keymax; i++) 341 ath_hal_keyreset(ah, i); 342 /* 343 * Mark key cache slots associated with global keys 344 * as in use. If we knew TKIP was not to be used we 345 * could leave the +32, +64, and +32+64 slots free. 346 * XXX only for splitmic. 347 */ 348 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 349 setbit(sc->sc_keymap, i); 350 setbit(sc->sc_keymap, i+32); 351 setbit(sc->sc_keymap, i+64); 352 setbit(sc->sc_keymap, i+32+64); 353 } 354 355 /* 356 * Collect the channel list using the default country 357 * code and including outdoor channels. The 802.11 layer 358 * is resposible for filtering this list based on settings 359 * like the phy mode. 360 */ 361 error = ath_getchannels(sc, ath_countrycode, 362 ath_outdoor, ath_xchanmode); 363 if (error != 0) 364 goto bad; 365 366 /* 367 * Setup rate tables for all potential media types. 368 */ 369 ath_rate_setup(sc, IEEE80211_MODE_11A); 370 ath_rate_setup(sc, IEEE80211_MODE_11B); 371 ath_rate_setup(sc, IEEE80211_MODE_11G); 372 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 373 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 374 /* NB: setup here so ath_rate_update is happy */ 375 ath_setcurmode(sc, IEEE80211_MODE_11A); 376 377 /* 378 * Allocate tx+rx descriptors and populate the lists. 379 */ 380 error = ath_desc_alloc(sc); 381 if (error != 0) { 382 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 383 goto bad; 384 } 385 ATH_CALLOUT_INIT(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 386 ATH_CALLOUT_INIT(&sc->sc_cal_ch, CALLOUT_MPSAFE); 387 #if 0 388 ATH_CALLOUT_INIT(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 389 #endif 390 391 ATH_TXBUF_LOCK_INIT(sc); 392 393 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 394 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 395 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 396 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 397 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 398 TASK_INIT(&sc->sc_radartask, 0, ath_radar_proc, sc); 399 400 /* 401 * Allocate hardware transmit queues: one queue for 402 * beacon frames and one data queue for each QoS 403 * priority. Note that the hal handles reseting 404 * these queues at the needed time. 405 * 406 * XXX PS-Poll 407 */ 408 sc->sc_bhalq = ath_beaconq_setup(ah); 409 if (sc->sc_bhalq == (u_int) -1) { 410 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 411 error = EIO; 412 goto bad2; 413 } 414 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 415 if (sc->sc_cabq == NULL) { 416 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 417 error = EIO; 418 goto bad2; 419 } 420 /* NB: insure BK queue is the lowest priority h/w queue */ 421 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 422 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 423 ieee80211_wme_acnames[WME_AC_BK]); 424 error = EIO; 425 goto bad2; 426 } 427 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 428 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 429 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 430 /* 431 * Not enough hardware tx queues to properly do WME; 432 * just punt and assign them all to the same h/w queue. 433 * We could do a better job of this if, for example, 434 * we allocate queues when we switch from station to 435 * AP mode. 436 */ 437 if (sc->sc_ac2q[WME_AC_VI] != NULL) 438 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 439 if (sc->sc_ac2q[WME_AC_BE] != NULL) 440 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 441 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 442 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 443 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 444 } 445 446 /* 447 * Special case certain configurations. Note the 448 * CAB queue is handled by these specially so don't 449 * include them when checking the txq setup mask. 450 */ 451 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 452 case 0x01: 453 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 454 break; 455 case 0x0f: 456 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 457 break; 458 default: 459 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 460 break; 461 } 462 463 /* 464 * Setup rate control. Some rate control modules 465 * call back to change the anntena state so expose 466 * the necessary entry points. 467 * XXX maybe belongs in struct ath_ratectrl? 468 */ 469 sc->sc_setdefantenna = ath_setdefantenna; 470 sc->sc_rc = ath_rate_attach(sc); 471 if (sc->sc_rc == NULL) { 472 error = EIO; 473 goto bad2; 474 } 475 476 sc->sc_blinking = 0; 477 sc->sc_ledstate = 1; 478 sc->sc_ledon = 0; /* low true */ 479 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 480 ATH_CALLOUT_INIT(&sc->sc_ledtimer, CALLOUT_MPSAFE); 481 /* 482 * Auto-enable soft led processing for IBM cards and for 483 * 5211 minipci cards. Users can also manually enable/disable 484 * support with a sysctl. 485 */ 486 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 487 if (sc->sc_softled) { 488 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 489 HAL_GPIO_MUX_MAC_NETWORK_LED); 490 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 491 } 492 493 ifp->if_softc = sc; 494 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 495 ifp->if_start = ath_start; 496 ifp->if_stop = ath_stop; 497 ifp->if_watchdog = ath_watchdog; 498 ifp->if_ioctl = ath_ioctl; 499 ifp->if_init = ath_ifinit; 500 IFQ_SET_READY(&ifp->if_snd); 501 502 ic->ic_ifp = ifp; 503 ic->ic_reset = ath_reset; 504 ic->ic_newassoc = ath_newassoc; 505 ic->ic_updateslot = ath_updateslot; 506 ic->ic_wme.wme_update = ath_wme_update; 507 /* XXX not right but it's not used anywhere important */ 508 ic->ic_phytype = IEEE80211_T_OFDM; 509 ic->ic_opmode = IEEE80211_M_STA; 510 ic->ic_caps = 511 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 512 | IEEE80211_C_HOSTAP /* hostap mode */ 513 | IEEE80211_C_MONITOR /* monitor mode */ 514 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 515 | IEEE80211_C_SHSLOT /* short slot time supported */ 516 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 517 | IEEE80211_C_TXFRAG /* handle tx frags */ 518 ; 519 /* 520 * Query the hal to figure out h/w crypto support. 521 */ 522 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 523 ic->ic_caps |= IEEE80211_C_WEP; 524 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 525 ic->ic_caps |= IEEE80211_C_AES; 526 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 527 ic->ic_caps |= IEEE80211_C_AES_CCM; 528 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 529 ic->ic_caps |= IEEE80211_C_CKIP; 530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 531 ic->ic_caps |= IEEE80211_C_TKIP; 532 /* 533 * Check if h/w does the MIC and/or whether the 534 * separate key cache entries are required to 535 * handle both tx+rx MIC keys. 536 */ 537 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 538 ic->ic_caps |= IEEE80211_C_TKIPMIC; 539 540 /* 541 * If the h/w supports storing tx+rx MIC keys 542 * in one cache slot automatically enable use. 543 */ 544 if (ath_hal_hastkipsplit(ah) || 545 !ath_hal_settkipsplit(ah, AH_FALSE)) 546 sc->sc_splitmic = 1; 547 548 /* 549 * If the h/w can do TKIP MIC together with WME then 550 * we use it; otherwise we force the MIC to be done 551 * in software by the net80211 layer. 552 */ 553 if (ath_hal_haswmetkipmic(ah)) 554 ic->ic_caps |= IEEE80211_C_WME_TKIPMIC; 555 } 556 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 557 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 558 /* 559 * Mark key cache slots associated with global keys 560 * as in use. If we knew TKIP was not to be used we 561 * could leave the +32, +64, and +32+64 slots free. 562 */ 563 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 564 setbit(sc->sc_keymap, i); 565 setbit(sc->sc_keymap, i+64); 566 if (sc->sc_splitmic) { 567 setbit(sc->sc_keymap, i+32); 568 setbit(sc->sc_keymap, i+32+64); 569 } 570 } 571 /* 572 * TPC support can be done either with a global cap or 573 * per-packet support. The latter is not available on 574 * all parts. We're a bit pedantic here as all parts 575 * support a global cap. 576 */ 577 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 578 ic->ic_caps |= IEEE80211_C_TXPMGT; 579 580 /* 581 * Mark WME capability only if we have sufficient 582 * hardware queues to do proper priority scheduling. 583 */ 584 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 585 ic->ic_caps |= IEEE80211_C_WME; 586 /* 587 * Check for misc other capabilities. 588 */ 589 if (ath_hal_hasbursting(ah)) 590 ic->ic_caps |= IEEE80211_C_BURST; 591 592 /* 593 * Indicate we need the 802.11 header padded to a 594 * 32-bit boundary for 4-address and QoS frames. 595 */ 596 ic->ic_flags |= IEEE80211_F_DATAPAD; 597 598 /* 599 * Query the hal about antenna support. 600 */ 601 sc->sc_defant = ath_hal_getdefantenna(ah); 602 603 /* 604 * Not all chips have the VEOL support we want to 605 * use with IBSS beacons; check here for it. 606 */ 607 sc->sc_hasveol = ath_hal_hasveol(ah); 608 609 /* get mac address from hardware */ 610 ath_hal_getmac(ah, ic->ic_myaddr); 611 612 if_attach(ifp); 613 /* call MI attach routine. */ 614 ieee80211_ifattach(ic); 615 /* override default methods */ 616 ic->ic_node_alloc = ath_node_alloc; 617 sc->sc_node_free = ic->ic_node_free; 618 ic->ic_node_free = ath_node_free; 619 ic->ic_node_getrssi = ath_node_getrssi; 620 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 621 ic->ic_recv_mgmt = ath_recv_mgmt; 622 sc->sc_newstate = ic->ic_newstate; 623 ic->ic_newstate = ath_newstate; 624 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 625 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 626 ic->ic_crypto.cs_key_delete = ath_key_delete; 627 ic->ic_crypto.cs_key_set = ath_key_set; 628 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 629 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 630 /* complete initialization */ 631 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 632 633 ath_bpfattach(sc); 634 635 sc->sc_flags |= ATH_ATTACHED; 636 637 /* 638 * Setup dynamic sysctl's now that country code and 639 * regdomain are available from the hal. 640 */ 641 ath_sysctlattach(sc); 642 643 ieee80211_announce(ic); 644 ath_announce(sc); 645 return 0; 646 bad2: 647 ath_tx_cleanup(sc); 648 ath_desc_free(sc); 649 bad: 650 if (ah) 651 ath_hal_detach(ah); 652 /* XXX don't get under the abstraction like this */ 653 sc->sc_dev->dv_flags &= ~DVF_ACTIVE; 654 return error; 655 } 656 657 int 658 ath_detach(struct ath_softc *sc) 659 { 660 struct ifnet *ifp = &sc->sc_if; 661 int s; 662 663 if ((sc->sc_flags & ATH_ATTACHED) == 0) 664 return (0); 665 666 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 667 __func__, ifp->if_flags); 668 669 s = splnet(); 670 ath_stop(ifp, 1); 671 bpf_detach(ifp); 672 /* 673 * NB: the order of these is important: 674 * o call the 802.11 layer before detaching the hal to 675 * insure callbacks into the driver to delete global 676 * key cache entries can be handled 677 * o reclaim the tx queue data structures after calling 678 * the 802.11 layer as we'll get called back to reclaim 679 * node state and potentially want to use them 680 * o to cleanup the tx queues the hal is called, so detach 681 * it last 682 * Other than that, it's straightforward... 683 */ 684 ieee80211_ifdetach(&sc->sc_ic); 685 #ifdef ATH_TX99_DIAG 686 if (sc->sc_tx99 != NULL) 687 sc->sc_tx99->detach(sc->sc_tx99); 688 #endif 689 ath_rate_detach(sc->sc_rc); 690 ath_desc_free(sc); 691 ath_tx_cleanup(sc); 692 sysctl_teardown(&sc->sc_sysctllog); 693 ath_hal_detach(sc->sc_ah); 694 if_detach(ifp); 695 splx(s); 696 697 return 0; 698 } 699 700 void 701 ath_suspend(struct ath_softc *sc) 702 { 703 #if notyet 704 /* 705 * Set the chip in full sleep mode. Note that we are 706 * careful to do this only when bringing the interface 707 * completely to a stop. When the chip is in this state 708 * it must be carefully woken up or references to 709 * registers in the PCI clock domain may freeze the bus 710 * (and system). This varies by chip and is mostly an 711 * issue with newer parts that go to sleep more quickly. 712 */ 713 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 714 #endif 715 } 716 717 bool 718 ath_resume(struct ath_softc *sc) 719 { 720 struct ath_hal *ah = sc->sc_ah; 721 struct ieee80211com *ic = &sc->sc_ic; 722 HAL_STATUS status; 723 int i; 724 725 #if notyet 726 ath_hal_setpower(ah, HAL_PM_AWAKE); 727 #else 728 ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status); 729 #endif 730 731 /* 732 * Reset the key cache since some parts do not 733 * reset the contents on initial power up. 734 */ 735 for (i = 0; i < sc->sc_keymax; i++) 736 ath_hal_keyreset(ah, i); 737 738 ath_hal_resettxqueue(ah, sc->sc_bhalq); 739 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 740 if (ATH_TXQ_SETUP(sc, i)) 741 ath_hal_resettxqueue(ah, i); 742 743 if (sc->sc_softled) { 744 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 745 HAL_GPIO_MUX_MAC_NETWORK_LED); 746 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 747 } 748 return true; 749 } 750 751 /* 752 * Interrupt handler. Most of the actual processing is deferred. 753 */ 754 int 755 ath_intr(void *arg) 756 { 757 struct ath_softc *sc = arg; 758 struct ifnet *ifp = &sc->sc_if; 759 struct ath_hal *ah = sc->sc_ah; 760 HAL_INT status = 0; 761 762 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) { 763 /* 764 * The hardware is not ready/present, don't touch anything. 765 * Note this can happen early on if the IRQ is shared. 766 */ 767 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 768 return 0; 769 } 770 771 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 772 return 0; 773 774 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 775 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 776 __func__, ifp->if_flags); 777 ath_hal_getisr(ah, &status); /* clear ISR */ 778 ath_hal_intrset(ah, 0); /* disable further intr's */ 779 return 1; /* XXX */ 780 } 781 /* 782 * Figure out the reason(s) for the interrupt. Note 783 * that the hal returns a pseudo-ISR that may include 784 * bits we haven't explicitly enabled so we mask the 785 * value to insure we only process bits we requested. 786 */ 787 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 788 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 789 status &= sc->sc_imask; /* discard unasked for bits */ 790 if (status & HAL_INT_FATAL) { 791 /* 792 * Fatal errors are unrecoverable. Typically 793 * these are caused by DMA errors. Unfortunately 794 * the exact reason is not (presently) returned 795 * by the hal. 796 */ 797 sc->sc_stats.ast_hardware++; 798 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 799 TASK_RUN_OR_ENQUEUE(&sc->sc_fataltask); 800 } else if (status & HAL_INT_RXORN) { 801 sc->sc_stats.ast_rxorn++; 802 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 803 TASK_RUN_OR_ENQUEUE(&sc->sc_rxorntask); 804 } else { 805 if (status & HAL_INT_SWBA) { 806 /* 807 * Software beacon alert--time to send a beacon. 808 * Handle beacon transmission directly; deferring 809 * this is too slow to meet timing constraints 810 * under load. 811 */ 812 ath_beacon_proc(sc, 0); 813 } 814 if (status & HAL_INT_RXEOL) { 815 /* 816 * NB: the hardware should re-read the link when 817 * RXE bit is written, but it doesn't work at 818 * least on older hardware revs. 819 */ 820 sc->sc_stats.ast_rxeol++; 821 sc->sc_rxlink = NULL; 822 } 823 if (status & HAL_INT_TXURN) { 824 sc->sc_stats.ast_txurn++; 825 /* bump tx trigger level */ 826 ath_hal_updatetxtriglevel(ah, AH_TRUE); 827 } 828 if (status & HAL_INT_RX) 829 TASK_RUN_OR_ENQUEUE(&sc->sc_rxtask); 830 if (status & HAL_INT_TX) 831 TASK_RUN_OR_ENQUEUE(&sc->sc_txtask); 832 if (status & HAL_INT_BMISS) { 833 sc->sc_stats.ast_bmiss++; 834 TASK_RUN_OR_ENQUEUE(&sc->sc_bmisstask); 835 } 836 if (status & HAL_INT_MIB) { 837 sc->sc_stats.ast_mib++; 838 /* 839 * Disable interrupts until we service the MIB 840 * interrupt; otherwise it will continue to fire. 841 */ 842 ath_hal_intrset(ah, 0); 843 /* 844 * Let the hal handle the event. We assume it will 845 * clear whatever condition caused the interrupt. 846 */ 847 ath_hal_mibevent(ah, &sc->sc_halstats); 848 ath_hal_intrset(ah, sc->sc_imask); 849 } 850 } 851 return 1; 852 } 853 854 /* Swap transmit descriptor. 855 * if AH_NEED_DESC_SWAP flag is not defined this becomes a "null" 856 * function. 857 */ 858 static inline void 859 ath_desc_swap(struct ath_desc *ds) 860 { 861 #ifdef AH_NEED_DESC_SWAP 862 ds->ds_link = htole32(ds->ds_link); 863 ds->ds_data = htole32(ds->ds_data); 864 ds->ds_ctl0 = htole32(ds->ds_ctl0); 865 ds->ds_ctl1 = htole32(ds->ds_ctl1); 866 ds->ds_hw[0] = htole32(ds->ds_hw[0]); 867 ds->ds_hw[1] = htole32(ds->ds_hw[1]); 868 #endif 869 } 870 871 static void 872 ath_fatal_proc(void *arg, int pending) 873 { 874 struct ath_softc *sc = arg; 875 struct ifnet *ifp = &sc->sc_if; 876 #ifdef __NetBSD__ 877 int s; 878 #endif 879 880 if_printf(ifp, "hardware error; resetting\n"); 881 #ifdef __NetBSD__ 882 s = splnet(); 883 #endif 884 ath_reset(ifp); 885 #ifdef __NetBSD__ 886 splx(s); 887 #endif 888 } 889 890 static void 891 ath_rxorn_proc(void *arg, int pending) 892 { 893 struct ath_softc *sc = arg; 894 struct ifnet *ifp = &sc->sc_if; 895 #ifdef __NetBSD__ 896 int s; 897 #endif 898 899 if_printf(ifp, "rx FIFO overrun; resetting\n"); 900 #ifdef __NetBSD__ 901 s = splnet(); 902 #endif 903 ath_reset(ifp); 904 #ifdef __NetBSD__ 905 splx(s); 906 #endif 907 } 908 909 static void 910 ath_bmiss_proc(void *arg, int pending) 911 { 912 struct ath_softc *sc = arg; 913 struct ieee80211com *ic = &sc->sc_ic; 914 NET_LOCK_GIANT_FUNC_INIT(); 915 916 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 917 KASSERTMSG(ic->ic_opmode == IEEE80211_M_STA, 918 "unexpect operating mode %u", ic->ic_opmode); 919 if (ic->ic_state == IEEE80211_S_RUN) { 920 u_int64_t lastrx = sc->sc_lastrx; 921 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 922 923 DPRINTF(sc, ATH_DEBUG_BEACON, 924 "%s: tsf %" PRIu64 " lastrx %" PRId64 925 " (%" PRIu64 ") bmiss %u\n", 926 __func__, tsf, tsf - lastrx, lastrx, 927 ic->ic_bmisstimeout*1024); 928 /* 929 * Workaround phantom bmiss interrupts by sanity-checking 930 * the time of our last rx'd frame. If it is within the 931 * beacon miss interval then ignore the interrupt. If it's 932 * truly a bmiss we'll get another interrupt soon and that'll 933 * be dispatched up for processing. 934 */ 935 if (tsf - lastrx > ic->ic_bmisstimeout*1024) { 936 NET_LOCK_GIANT(); 937 ieee80211_beacon_miss(ic); 938 NET_UNLOCK_GIANT(); 939 } else 940 sc->sc_stats.ast_bmiss_phantom++; 941 } 942 } 943 944 static void 945 ath_radar_proc(void *arg, int pending) 946 { 947 #if 0 948 struct ath_softc *sc = arg; 949 struct ifnet *ifp = &sc->sc_if; 950 struct ath_hal *ah = sc->sc_ah; 951 HAL_CHANNEL hchan; 952 953 if (ath_hal_procdfs(ah, &hchan)) { 954 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n", 955 hchan.channel, hchan.channelFlags, hchan.privFlags); 956 /* 957 * Initiate channel change. 958 */ 959 /* XXX not yet */ 960 } 961 #endif 962 } 963 964 static u_int 965 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 966 { 967 #define N(a) (sizeof(a) / sizeof(a[0])) 968 static const u_int modeflags[] = { 969 0, /* IEEE80211_MODE_AUTO */ 970 CHANNEL_A, /* IEEE80211_MODE_11A */ 971 CHANNEL_B, /* IEEE80211_MODE_11B */ 972 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 973 0, /* IEEE80211_MODE_FH */ 974 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */ 975 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 976 }; 977 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 978 979 KASSERTMSG(mode < N(modeflags), "unexpected phy mode %u", mode); 980 KASSERTMSG(modeflags[mode] != 0, "mode %u undefined", mode); 981 return modeflags[mode]; 982 #undef N 983 } 984 985 static int 986 ath_ifinit(struct ifnet *ifp) 987 { 988 struct ath_softc *sc = (struct ath_softc *)ifp->if_softc; 989 990 return ath_init(sc); 991 } 992 993 static void 994 ath_settkipmic(struct ath_softc *sc) 995 { 996 struct ieee80211com *ic = &sc->sc_ic; 997 struct ath_hal *ah = sc->sc_ah; 998 999 if ((ic->ic_caps & IEEE80211_C_TKIP) && 1000 !(ic->ic_caps & IEEE80211_C_WME_TKIPMIC)) { 1001 if (ic->ic_flags & IEEE80211_F_WME) { 1002 (void)ath_hal_settkipmic(ah, AH_FALSE); 1003 ic->ic_caps &= ~IEEE80211_C_TKIPMIC; 1004 } else { 1005 (void)ath_hal_settkipmic(ah, AH_TRUE); 1006 ic->ic_caps |= IEEE80211_C_TKIPMIC; 1007 } 1008 } 1009 } 1010 1011 static int 1012 ath_init(struct ath_softc *sc) 1013 { 1014 struct ifnet *ifp = &sc->sc_if; 1015 struct ieee80211com *ic = &sc->sc_ic; 1016 struct ath_hal *ah = sc->sc_ah; 1017 HAL_STATUS status; 1018 int error = 0, s; 1019 1020 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1021 __func__, ifp->if_flags); 1022 1023 if (device_is_active(sc->sc_dev)) { 1024 s = splnet(); 1025 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 1026 !device_is_active(sc->sc_dev)) 1027 return 0; 1028 else 1029 s = splnet(); 1030 1031 /* 1032 * Stop anything previously setup. This is safe 1033 * whether this is the first time through or not. 1034 */ 1035 ath_stop_locked(ifp, 0); 1036 1037 /* 1038 * The basic interface to setting the hardware in a good 1039 * state is ``reset''. On return the hardware is known to 1040 * be powered up and with interrupts disabled. This must 1041 * be followed by initialization of the appropriate bits 1042 * and then setup of the interrupt mask. 1043 */ 1044 ath_settkipmic(sc); 1045 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 1046 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1047 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1048 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1049 status); 1050 error = EIO; 1051 goto done; 1052 } 1053 1054 /* 1055 * This is needed only to setup initial state 1056 * but it's best done after a reset. 1057 */ 1058 ath_update_txpow(sc); 1059 /* 1060 * Likewise this is set during reset so update 1061 * state cached in the driver. 1062 */ 1063 ath_restore_diversity(sc); 1064 sc->sc_calinterval = 1; 1065 sc->sc_caltries = 0; 1066 1067 /* 1068 * Setup the hardware after reset: the key cache 1069 * is filled as needed and the receive engine is 1070 * set going. Frame transmit is handled entirely 1071 * in the frame output path; there's nothing to do 1072 * here except setup the interrupt mask. 1073 */ 1074 if ((error = ath_startrecv(sc)) != 0) { 1075 if_printf(ifp, "unable to start recv logic\n"); 1076 goto done; 1077 } 1078 1079 /* 1080 * Enable interrupts. 1081 */ 1082 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1083 | HAL_INT_RXEOL | HAL_INT_RXORN 1084 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1085 /* 1086 * Enable MIB interrupts when there are hardware phy counters. 1087 * Note we only do this (at the moment) for station mode. 1088 */ 1089 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1090 sc->sc_imask |= HAL_INT_MIB; 1091 ath_hal_intrset(ah, sc->sc_imask); 1092 1093 ifp->if_flags |= IFF_RUNNING; 1094 ic->ic_state = IEEE80211_S_INIT; 1095 1096 /* 1097 * The hardware should be ready to go now so it's safe 1098 * to kick the 802.11 state machine as it's likely to 1099 * immediately call back to us to send mgmt frames. 1100 */ 1101 ath_chan_change(sc, ic->ic_curchan); 1102 #ifdef ATH_TX99_DIAG 1103 if (sc->sc_tx99 != NULL) 1104 sc->sc_tx99->start(sc->sc_tx99); 1105 else 1106 #endif 1107 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1108 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1109 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1110 } else 1111 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1112 done: 1113 splx(s); 1114 return error; 1115 } 1116 1117 static void 1118 ath_stop_locked(struct ifnet *ifp, int disable) 1119 { 1120 struct ath_softc *sc = ifp->if_softc; 1121 struct ieee80211com *ic = &sc->sc_ic; 1122 struct ath_hal *ah = sc->sc_ah; 1123 1124 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %d if_flags 0x%x\n", 1125 __func__, !device_is_enabled(sc->sc_dev), ifp->if_flags); 1126 1127 /* KASSERT() IPL_NET */ 1128 if (ifp->if_flags & IFF_RUNNING) { 1129 /* 1130 * Shutdown the hardware and driver: 1131 * reset 802.11 state machine 1132 * turn off timers 1133 * disable interrupts 1134 * turn off the radio 1135 * clear transmit machinery 1136 * clear receive machinery 1137 * drain and release tx queues 1138 * reclaim beacon resources 1139 * power down hardware 1140 * 1141 * Note that some of this work is not possible if the 1142 * hardware is gone (invalid). 1143 */ 1144 #ifdef ATH_TX99_DIAG 1145 if (sc->sc_tx99 != NULL) 1146 sc->sc_tx99->stop(sc->sc_tx99); 1147 #endif 1148 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1149 ifp->if_flags &= ~IFF_RUNNING; 1150 ifp->if_timer = 0; 1151 if (device_is_enabled(sc->sc_dev)) { 1152 if (sc->sc_softled) { 1153 callout_stop(&sc->sc_ledtimer); 1154 ath_hal_gpioset(ah, sc->sc_ledpin, 1155 !sc->sc_ledon); 1156 sc->sc_blinking = 0; 1157 } 1158 ath_hal_intrset(ah, 0); 1159 } 1160 ath_draintxq(sc); 1161 if (device_is_enabled(sc->sc_dev)) { 1162 ath_stoprecv(sc); 1163 ath_hal_phydisable(ah); 1164 } else 1165 sc->sc_rxlink = NULL; 1166 IF_PURGE(&ifp->if_snd); 1167 ath_beacon_free(sc); 1168 } 1169 if (disable) 1170 pmf_device_suspend(sc->sc_dev, &sc->sc_qual); 1171 } 1172 1173 static void 1174 ath_stop(struct ifnet *ifp, int disable) 1175 { 1176 int s; 1177 1178 s = splnet(); 1179 ath_stop_locked(ifp, disable); 1180 splx(s); 1181 } 1182 1183 static void 1184 ath_restore_diversity(struct ath_softc *sc) 1185 { 1186 struct ifnet *ifp = &sc->sc_if; 1187 struct ath_hal *ah = sc->sc_ah; 1188 1189 if (!ath_hal_setdiversity(sc->sc_ah, sc->sc_diversity) || 1190 sc->sc_diversity != ath_hal_getdiversity(ah)) { 1191 if_printf(ifp, "could not restore diversity setting %d\n", 1192 sc->sc_diversity); 1193 sc->sc_diversity = ath_hal_getdiversity(ah); 1194 } 1195 } 1196 1197 /* 1198 * Reset the hardware w/o losing operational state. This is 1199 * basically a more efficient way of doing ath_stop, ath_init, 1200 * followed by state transitions to the current 802.11 1201 * operational state. Used to recover from various errors and 1202 * to reset or reload hardware state. 1203 */ 1204 int 1205 ath_reset(struct ifnet *ifp) 1206 { 1207 struct ath_softc *sc = ifp->if_softc; 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ath_hal *ah = sc->sc_ah; 1210 struct ieee80211_channel *c; 1211 HAL_STATUS status; 1212 1213 /* 1214 * Convert to a HAL channel description with the flags 1215 * constrained to reflect the current operating mode. 1216 */ 1217 c = ic->ic_curchan; 1218 sc->sc_curchan.channel = c->ic_freq; 1219 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1220 1221 ath_hal_intrset(ah, 0); /* disable interrupts */ 1222 ath_draintxq(sc); /* stop xmit side */ 1223 ath_stoprecv(sc); /* stop recv side */ 1224 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1225 /* NB: indicate channel change so we do a full reset */ 1226 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1227 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1228 __func__, status); 1229 ath_update_txpow(sc); /* update tx power state */ 1230 ath_restore_diversity(sc); 1231 sc->sc_calinterval = 1; 1232 sc->sc_caltries = 0; 1233 if (ath_startrecv(sc) != 0) /* restart recv */ 1234 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1235 /* 1236 * We may be doing a reset in response to an ioctl 1237 * that changes the channel so update any state that 1238 * might change as a result. 1239 */ 1240 ath_chan_change(sc, c); 1241 if (ic->ic_state == IEEE80211_S_RUN) 1242 ath_beacon_config(sc); /* restart beacons */ 1243 ath_hal_intrset(ah, sc->sc_imask); 1244 1245 ath_start(ifp); /* restart xmit */ 1246 return 0; 1247 } 1248 1249 /* 1250 * Cleanup driver resources when we run out of buffers 1251 * while processing fragments; return the tx buffers 1252 * allocated and drop node references. 1253 */ 1254 static void 1255 ath_txfrag_cleanup(struct ath_softc *sc, 1256 ath_bufhead *frags, struct ieee80211_node *ni) 1257 { 1258 struct ath_buf *bf; 1259 1260 ATH_TXBUF_LOCK_ASSERT(sc); 1261 1262 while ((bf = STAILQ_FIRST(frags)) != NULL) { 1263 STAILQ_REMOVE_HEAD(frags, bf_list); 1264 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1265 sc->sc_if.if_flags &= ~IFF_OACTIVE; 1266 ieee80211_node_decref(ni); 1267 } 1268 } 1269 1270 /* 1271 * Setup xmit of a fragmented frame. Allocate a buffer 1272 * for each frag and bump the node reference count to 1273 * reflect the held reference to be setup by ath_tx_start. 1274 */ 1275 static int 1276 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1277 struct mbuf *m0, struct ieee80211_node *ni) 1278 { 1279 struct mbuf *m; 1280 struct ath_buf *bf; 1281 1282 ATH_TXBUF_LOCK(sc); 1283 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1284 bf = STAILQ_FIRST(&sc->sc_txbuf); 1285 if (bf == NULL) { /* out of buffers, cleanup */ 1286 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1287 __func__); 1288 sc->sc_if.if_flags |= IFF_OACTIVE; 1289 ath_txfrag_cleanup(sc, frags, ni); 1290 break; 1291 } 1292 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1293 ieee80211_node_incref(ni); 1294 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1295 } 1296 ATH_TXBUF_UNLOCK(sc); 1297 1298 return !STAILQ_EMPTY(frags); 1299 } 1300 1301 static void 1302 ath_start(struct ifnet *ifp) 1303 { 1304 struct ath_softc *sc = ifp->if_softc; 1305 struct ath_hal *ah = sc->sc_ah; 1306 struct ieee80211com *ic = &sc->sc_ic; 1307 struct ieee80211_node *ni; 1308 struct ath_buf *bf; 1309 struct mbuf *m, *next; 1310 struct ieee80211_frame *wh; 1311 struct ether_header *eh; 1312 ath_bufhead frags; 1313 1314 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1315 !device_is_active(sc->sc_dev)) 1316 return; 1317 1318 if (sc->sc_flags & ATH_KEY_UPDATING) 1319 return; 1320 1321 for (;;) { 1322 /* 1323 * Grab a TX buffer and associated resources. 1324 */ 1325 ATH_TXBUF_LOCK(sc); 1326 bf = STAILQ_FIRST(&sc->sc_txbuf); 1327 if (bf != NULL) 1328 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1329 ATH_TXBUF_UNLOCK(sc); 1330 if (bf == NULL) { 1331 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1332 __func__); 1333 sc->sc_stats.ast_tx_qstop++; 1334 ifp->if_flags |= IFF_OACTIVE; 1335 break; 1336 } 1337 /* 1338 * Poll the management queue for frames; they 1339 * have priority over normal data frames. 1340 */ 1341 IF_DEQUEUE(&ic->ic_mgtq, m); 1342 if (m == NULL) { 1343 /* 1344 * No data frames go out unless we're associated. 1345 */ 1346 if (ic->ic_state != IEEE80211_S_RUN) { 1347 DPRINTF(sc, ATH_DEBUG_XMIT, 1348 "%s: discard data packet, state %s\n", 1349 __func__, 1350 ieee80211_state_name[ic->ic_state]); 1351 sc->sc_stats.ast_tx_discard++; 1352 ATH_TXBUF_LOCK(sc); 1353 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1354 ATH_TXBUF_UNLOCK(sc); 1355 break; 1356 } 1357 IFQ_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1358 if (m == NULL) { 1359 ATH_TXBUF_LOCK(sc); 1360 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1361 ATH_TXBUF_UNLOCK(sc); 1362 break; 1363 } 1364 STAILQ_INIT(&frags); 1365 /* 1366 * Find the node for the destination so we can do 1367 * things like power save and fast frames aggregation. 1368 */ 1369 if (m->m_len < sizeof(struct ether_header) && 1370 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1371 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1372 ni = NULL; 1373 goto bad; 1374 } 1375 eh = mtod(m, struct ether_header *); 1376 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1377 if (ni == NULL) { 1378 /* NB: ieee80211_find_txnode does stat+msg */ 1379 m_freem(m); 1380 goto bad; 1381 } 1382 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1383 (m->m_flags & M_PWR_SAV) == 0) { 1384 /* 1385 * Station in power save mode; pass the frame 1386 * to the 802.11 layer and continue. We'll get 1387 * the frame back when the time is right. 1388 */ 1389 ieee80211_pwrsave(ic, ni, m); 1390 goto reclaim; 1391 } 1392 /* calculate priority so we can find the tx queue */ 1393 if (ieee80211_classify(ic, m, ni)) { 1394 DPRINTF(sc, ATH_DEBUG_XMIT, 1395 "%s: discard, classification failure\n", 1396 __func__); 1397 m_freem(m); 1398 goto bad; 1399 } 1400 ifp->if_opackets++; 1401 1402 bpf_mtap(ifp, m, BPF_D_OUT); 1403 /* 1404 * Encapsulate the packet in prep for transmission. 1405 */ 1406 m = ieee80211_encap(ic, m, ni); 1407 if (m == NULL) { 1408 DPRINTF(sc, ATH_DEBUG_XMIT, 1409 "%s: encapsulation failure\n", 1410 __func__); 1411 sc->sc_stats.ast_tx_encap++; 1412 goto bad; 1413 } 1414 /* 1415 * Check for fragmentation. If this has frame 1416 * has been broken up verify we have enough 1417 * buffers to send all the fragments so all 1418 * go out or none... 1419 */ 1420 if ((m->m_flags & M_FRAG) && 1421 !ath_txfrag_setup(sc, &frags, m, ni)) { 1422 DPRINTF(sc, ATH_DEBUG_ANY, 1423 "%s: out of txfrag buffers\n", __func__); 1424 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1425 ath_freetx(m); 1426 goto bad; 1427 } 1428 } else { 1429 /* 1430 * Hack! The referenced node pointer is in the 1431 * rcvif field of the packet header. This is 1432 * placed there by ieee80211_mgmt_output because 1433 * we need to hold the reference with the frame 1434 * and there's no other way (other than packet 1435 * tags which we consider too expensive to use) 1436 * to pass it along. 1437 */ 1438 ni = M_GETCTX(m, struct ieee80211_node *); 1439 M_CLEARCTX(m); 1440 1441 wh = mtod(m, struct ieee80211_frame *); 1442 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1443 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1444 /* fill time stamp */ 1445 u_int64_t tsf; 1446 u_int32_t *tstamp; 1447 1448 tsf = ath_hal_gettsf64(ah); 1449 /* XXX: adjust 100us delay to xmit */ 1450 tsf += 100; 1451 tstamp = (u_int32_t *)&wh[1]; 1452 tstamp[0] = htole32(tsf & 0xffffffff); 1453 tstamp[1] = htole32(tsf >> 32); 1454 } 1455 sc->sc_stats.ast_tx_mgmt++; 1456 } 1457 1458 nextfrag: 1459 next = m->m_nextpkt; 1460 if (ath_tx_start(sc, ni, bf, m)) { 1461 bad: 1462 ifp->if_oerrors++; 1463 reclaim: 1464 ATH_TXBUF_LOCK(sc); 1465 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1466 ath_txfrag_cleanup(sc, &frags, ni); 1467 ATH_TXBUF_UNLOCK(sc); 1468 if (ni != NULL) 1469 ieee80211_free_node(ni); 1470 continue; 1471 } 1472 if (next != NULL) { 1473 m = next; 1474 bf = STAILQ_FIRST(&frags); 1475 KASSERTMSG(bf != NULL, "no buf for txfrag"); 1476 STAILQ_REMOVE_HEAD(&frags, bf_list); 1477 goto nextfrag; 1478 } 1479 1480 ifp->if_timer = 1; 1481 } 1482 } 1483 1484 static int 1485 ath_media_change(struct ifnet *ifp) 1486 { 1487 #define IS_UP(ifp) \ 1488 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1489 int error; 1490 1491 error = ieee80211_media_change(ifp); 1492 if (error == ENETRESET) { 1493 if (IS_UP(ifp)) 1494 ath_init(ifp->if_softc); /* XXX lose error */ 1495 error = 0; 1496 } 1497 return error; 1498 #undef IS_UP 1499 } 1500 1501 #ifdef AR_DEBUG 1502 static void 1503 ath_keyprint(const char *tag, u_int ix, 1504 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1505 { 1506 static const char *ciphers[] = { 1507 "WEP", 1508 "AES-OCB", 1509 "AES-CCM", 1510 "CKIP", 1511 "TKIP", 1512 "CLR", 1513 }; 1514 int i, n; 1515 1516 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1517 for (i = 0, n = hk->kv_len; i < n; i++) 1518 printf("%02x", hk->kv_val[i]); 1519 printf(" mac %s", ether_sprintf(mac)); 1520 if (hk->kv_type == HAL_CIPHER_TKIP) { 1521 printf(" mic "); 1522 for (i = 0; i < sizeof(hk->kv_mic); i++) 1523 printf("%02x", hk->kv_mic[i]); 1524 } 1525 printf("\n"); 1526 } 1527 #endif 1528 1529 /* 1530 * Set a TKIP key into the hardware. This handles the 1531 * potential distribution of key state to multiple key 1532 * cache slots for TKIP. 1533 */ 1534 static int 1535 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1536 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1537 { 1538 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1539 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1540 struct ath_hal *ah = sc->sc_ah; 1541 1542 KASSERTMSG(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1543 "got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher); 1544 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1545 if (sc->sc_splitmic) { 1546 /* 1547 * TX key goes at first index, RX key at the rx index. 1548 * The hal handles the MIC keys at index+64. 1549 */ 1550 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1551 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1552 if (!ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, 1553 zerobssid)) 1554 return 0; 1555 1556 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1557 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1558 /* XXX delete tx key on failure? */ 1559 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix+32), 1560 hk, mac); 1561 } else { 1562 /* 1563 * Room for both TX+RX MIC keys in one key cache 1564 * slot, just set key at the first index; the HAL 1565 * will handle the reset. 1566 */ 1567 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1568 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1569 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1570 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1571 } 1572 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1573 if (sc->sc_splitmic) { 1574 /* 1575 * NB: must pass MIC key in expected location when 1576 * the keycache only holds one MIC key per entry. 1577 */ 1578 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1579 } else 1580 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1581 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1582 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), hk, mac); 1583 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1584 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1585 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1586 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1587 } 1588 return 0; 1589 #undef IEEE80211_KEY_XR 1590 } 1591 1592 /* 1593 * Set a net80211 key into the hardware. This handles the 1594 * potential distribution of key state to multiple key 1595 * cache slots for TKIP with hardware MIC support. 1596 */ 1597 static int 1598 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1599 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1600 struct ieee80211_node *bss) 1601 { 1602 #define N(a) (sizeof(a)/sizeof(a[0])) 1603 static const u_int8_t ciphermap[] = { 1604 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1605 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1606 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1607 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1608 (u_int8_t) -1, /* 4 is not allocated */ 1609 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1610 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1611 }; 1612 struct ath_hal *ah = sc->sc_ah; 1613 const struct ieee80211_cipher *cip = k->wk_cipher; 1614 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1615 const u_int8_t *mac; 1616 HAL_KEYVAL hk; 1617 1618 memset(&hk, 0, sizeof(hk)); 1619 /* 1620 * Software crypto uses a "clear key" so non-crypto 1621 * state kept in the key cache are maintained and 1622 * so that rx frames have an entry to match. 1623 */ 1624 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1625 KASSERTMSG(cip->ic_cipher < N(ciphermap), 1626 "invalid cipher type %u", cip->ic_cipher); 1627 hk.kv_type = ciphermap[cip->ic_cipher]; 1628 hk.kv_len = k->wk_keylen; 1629 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1630 } else 1631 hk.kv_type = HAL_CIPHER_CLR; 1632 1633 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1634 /* 1635 * Group keys on hardware that supports multicast frame 1636 * key search use a mac that is the sender's address with 1637 * the high bit set instead of the app-specified address. 1638 */ 1639 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1640 gmac[0] |= 0x80; 1641 mac = gmac; 1642 } else 1643 mac = mac0; 1644 1645 if ((hk.kv_type == HAL_CIPHER_TKIP && 1646 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0)) { 1647 return ath_keyset_tkip(sc, k, &hk, mac); 1648 } else { 1649 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1650 return ath_hal_keyset(ah, ATH_KEY(k->wk_keyix), &hk, mac); 1651 } 1652 #undef N 1653 } 1654 1655 /* 1656 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1657 * each key, one for decrypt/encrypt and the other for the MIC. 1658 */ 1659 static u_int16_t 1660 key_alloc_2pair(struct ath_softc *sc, 1661 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1662 { 1663 #define N(a) (sizeof(a)/sizeof(a[0])) 1664 u_int i, keyix; 1665 1666 KASSERTMSG(sc->sc_splitmic, "key cache !split"); 1667 /* XXX could optimize */ 1668 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1669 u_int8_t b = sc->sc_keymap[i]; 1670 if (b != 0xff) { 1671 /* 1672 * One or more slots in this byte are free. 1673 */ 1674 keyix = i*NBBY; 1675 while (b & 1) { 1676 again: 1677 keyix++; 1678 b >>= 1; 1679 } 1680 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1681 if (isset(sc->sc_keymap, keyix+32) || 1682 isset(sc->sc_keymap, keyix+64) || 1683 isset(sc->sc_keymap, keyix+32+64)) { 1684 /* full pair unavailable */ 1685 /* XXX statistic */ 1686 if (keyix == (i+1)*NBBY) { 1687 /* no slots were appropriate, advance */ 1688 continue; 1689 } 1690 goto again; 1691 } 1692 setbit(sc->sc_keymap, keyix); 1693 setbit(sc->sc_keymap, keyix+64); 1694 setbit(sc->sc_keymap, keyix+32); 1695 setbit(sc->sc_keymap, keyix+32+64); 1696 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1697 "%s: key pair %u,%u %u,%u\n", 1698 __func__, keyix, keyix+64, 1699 keyix+32, keyix+32+64); 1700 *txkeyix = keyix; 1701 *rxkeyix = keyix+32; 1702 return keyix; 1703 } 1704 } 1705 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1706 return IEEE80211_KEYIX_NONE; 1707 #undef N 1708 } 1709 1710 /* 1711 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1712 * each key, one for decrypt/encrypt and the other for the MIC. 1713 */ 1714 static int 1715 key_alloc_pair(struct ath_softc *sc, ieee80211_keyix *txkeyix, 1716 ieee80211_keyix *rxkeyix) 1717 { 1718 #define N(a) (sizeof(a)/sizeof(a[0])) 1719 u_int i, keyix; 1720 1721 KASSERTMSG(!sc->sc_splitmic, "key cache split"); 1722 /* XXX could optimize */ 1723 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1724 uint8_t b = sc->sc_keymap[i]; 1725 if (b != 0xff) { 1726 /* 1727 * One or more slots in this byte are free. 1728 */ 1729 keyix = i*NBBY; 1730 while (b & 1) { 1731 again: 1732 keyix++; 1733 b >>= 1; 1734 } 1735 if (isset(sc->sc_keymap, keyix+64)) { 1736 /* full pair unavailable */ 1737 /* XXX statistic */ 1738 if (keyix == (i+1)*NBBY) { 1739 /* no slots were appropriate, advance */ 1740 continue; 1741 } 1742 goto again; 1743 } 1744 setbit(sc->sc_keymap, keyix); 1745 setbit(sc->sc_keymap, keyix+64); 1746 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1747 "%s: key pair %u,%u\n", 1748 __func__, keyix, keyix+64); 1749 *txkeyix = *rxkeyix = keyix; 1750 return 1; 1751 } 1752 } 1753 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1754 return 0; 1755 #undef N 1756 } 1757 1758 /* 1759 * Allocate a single key cache slot. 1760 */ 1761 static int 1762 key_alloc_single(struct ath_softc *sc, 1763 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1764 { 1765 #define N(a) (sizeof(a)/sizeof(a[0])) 1766 u_int i, keyix; 1767 1768 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1769 for (i = 0; i < N(sc->sc_keymap); i++) { 1770 u_int8_t b = sc->sc_keymap[i]; 1771 if (b != 0xff) { 1772 /* 1773 * One or more slots are free. 1774 */ 1775 keyix = i*NBBY; 1776 while (b & 1) 1777 keyix++, b >>= 1; 1778 setbit(sc->sc_keymap, keyix); 1779 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1780 __func__, keyix); 1781 *txkeyix = *rxkeyix = keyix; 1782 return 1; 1783 } 1784 } 1785 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1786 return 0; 1787 #undef N 1788 } 1789 1790 /* 1791 * Allocate one or more key cache slots for a uniacst key. The 1792 * key itself is needed only to identify the cipher. For hardware 1793 * TKIP with split cipher+MIC keys we allocate two key cache slot 1794 * pairs so that we can setup separate TX and RX MIC keys. Note 1795 * that the MIC key for a TKIP key at slot i is assumed by the 1796 * hardware to be at slot i+64. This limits TKIP keys to the first 1797 * 64 entries. 1798 */ 1799 static int 1800 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1801 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1802 { 1803 struct ath_softc *sc = ic->ic_ifp->if_softc; 1804 1805 /* 1806 * Group key allocation must be handled specially for 1807 * parts that do not support multicast key cache search 1808 * functionality. For those parts the key id must match 1809 * the h/w key index so lookups find the right key. On 1810 * parts w/ the key search facility we install the sender's 1811 * mac address (with the high bit set) and let the hardware 1812 * find the key w/o using the key id. This is preferred as 1813 * it permits us to support multiple users for adhoc and/or 1814 * multi-station operation. 1815 */ 1816 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1817 if (!(&ic->ic_nw_keys[0] <= k && 1818 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1819 /* should not happen */ 1820 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1821 "%s: bogus group key\n", __func__); 1822 return 0; 1823 } 1824 /* 1825 * XXX we pre-allocate the global keys so 1826 * have no way to check if they've already been allocated. 1827 */ 1828 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1829 return 1; 1830 } 1831 1832 /* 1833 * We allocate two pair for TKIP when using the h/w to do 1834 * the MIC. For everything else, including software crypto, 1835 * we allocate a single entry. Note that s/w crypto requires 1836 * a pass-through slot on the 5211 and 5212. The 5210 does 1837 * not support pass-through cache entries and we map all 1838 * those requests to slot 0. 1839 */ 1840 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1841 return key_alloc_single(sc, keyix, rxkeyix); 1842 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1843 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1844 if (sc->sc_splitmic) 1845 return key_alloc_2pair(sc, keyix, rxkeyix); 1846 else 1847 return key_alloc_pair(sc, keyix, rxkeyix); 1848 } else { 1849 return key_alloc_single(sc, keyix, rxkeyix); 1850 } 1851 } 1852 1853 /* 1854 * Delete an entry in the key cache allocated by ath_key_alloc. 1855 */ 1856 static int 1857 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1858 { 1859 struct ath_softc *sc = ic->ic_ifp->if_softc; 1860 struct ath_hal *ah = sc->sc_ah; 1861 const struct ieee80211_cipher *cip = k->wk_cipher; 1862 u_int keyix = k->wk_keyix; 1863 1864 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1865 1866 if (!device_has_power(sc->sc_dev)) { 1867 aprint_error_dev(sc->sc_dev, "deleting keyix %d w/o power\n", 1868 k->wk_keyix); 1869 } 1870 1871 ath_hal_keyreset(ah, keyix); 1872 /* 1873 * Handle split tx/rx keying required for TKIP with h/w MIC. 1874 */ 1875 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1876 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1877 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1878 if (keyix >= IEEE80211_WEP_NKID) { 1879 /* 1880 * Don't touch keymap entries for global keys so 1881 * they are never considered for dynamic allocation. 1882 */ 1883 clrbit(sc->sc_keymap, keyix); 1884 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1885 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1886 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1887 if (sc->sc_splitmic) { 1888 /* +32 for RX key, +32+64 for RX key MIC */ 1889 clrbit(sc->sc_keymap, keyix+32); 1890 clrbit(sc->sc_keymap, keyix+32+64); 1891 } 1892 } 1893 } 1894 return 1; 1895 } 1896 1897 /* 1898 * Set the key cache contents for the specified key. Key cache 1899 * slot(s) must already have been allocated by ath_key_alloc. 1900 */ 1901 static int 1902 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1903 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1904 { 1905 struct ath_softc *sc = ic->ic_ifp->if_softc; 1906 1907 if (!device_has_power(sc->sc_dev)) { 1908 aprint_error_dev(sc->sc_dev, "setting keyix %d w/o power\n", 1909 k->wk_keyix); 1910 } 1911 return ath_keyset(sc, k, mac, ic->ic_bss); 1912 } 1913 1914 /* 1915 * Block/unblock tx+rx processing while a key change is done. 1916 * We assume the caller serializes key management operations 1917 * so we only need to worry about synchronization with other 1918 * uses that originate in the driver. 1919 */ 1920 static void 1921 ath_key_update_begin(struct ieee80211com *ic) 1922 { 1923 struct ifnet *ifp = ic->ic_ifp; 1924 struct ath_softc *sc = ifp->if_softc; 1925 1926 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1927 #if 0 1928 tasklet_disable(&sc->sc_rxtq); 1929 #endif 1930 sc->sc_flags |= ATH_KEY_UPDATING; 1931 } 1932 1933 static void 1934 ath_key_update_end(struct ieee80211com *ic) 1935 { 1936 struct ifnet *ifp = ic->ic_ifp; 1937 struct ath_softc *sc = ifp->if_softc; 1938 1939 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1940 sc->sc_flags &= ~ATH_KEY_UPDATING; 1941 #if 0 1942 tasklet_enable(&sc->sc_rxtq); 1943 #endif 1944 } 1945 1946 /* 1947 * Calculate the receive filter according to the 1948 * operating mode and state: 1949 * 1950 * o always accept unicast, broadcast, and multicast traffic 1951 * o maintain current state of phy error reception (the hal 1952 * may enable phy error frames for noise immunity work) 1953 * o probe request frames are accepted only when operating in 1954 * hostap, adhoc, or monitor modes 1955 * o enable promiscuous mode according to the interface state 1956 * o accept beacons: 1957 * - when operating in adhoc mode so the 802.11 layer creates 1958 * node table entries for peers, 1959 * - when operating in station mode for collecting rssi data when 1960 * the station is otherwise quiet, or 1961 * - when scanning 1962 */ 1963 static u_int32_t 1964 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1965 { 1966 struct ieee80211com *ic = &sc->sc_ic; 1967 struct ath_hal *ah = sc->sc_ah; 1968 struct ifnet *ifp = &sc->sc_if; 1969 u_int32_t rfilt; 1970 1971 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1972 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1973 if (ic->ic_opmode != IEEE80211_M_STA) 1974 rfilt |= HAL_RX_FILTER_PROBEREQ; 1975 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1976 (ifp->if_flags & IFF_PROMISC)) 1977 rfilt |= HAL_RX_FILTER_PROM; 1978 if (ifp->if_flags & IFF_PROMISC) 1979 rfilt |= HAL_RX_FILTER_CONTROL | HAL_RX_FILTER_PROBEREQ; 1980 if (ic->ic_opmode == IEEE80211_M_STA || 1981 ic->ic_opmode == IEEE80211_M_IBSS || 1982 state == IEEE80211_S_SCAN) 1983 rfilt |= HAL_RX_FILTER_BEACON; 1984 return rfilt; 1985 } 1986 1987 static void 1988 ath_mode_init(struct ath_softc *sc) 1989 { 1990 struct ifnet *ifp = &sc->sc_if; 1991 struct ieee80211com *ic = &sc->sc_ic; 1992 struct ath_hal *ah = sc->sc_ah; 1993 struct ether_multi *enm; 1994 struct ether_multistep estep; 1995 u_int32_t rfilt, mfilt[2], val; 1996 int i; 1997 uint8_t pos; 1998 1999 /* configure rx filter */ 2000 rfilt = ath_calcrxfilter(sc, ic->ic_state); 2001 ath_hal_setrxfilter(ah, rfilt); 2002 2003 /* configure operational mode */ 2004 ath_hal_setopmode(ah); 2005 2006 /* Write keys to hardware; it may have been powered down. */ 2007 ath_key_update_begin(ic); 2008 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2009 ath_key_set(ic, 2010 &ic->ic_crypto.cs_nw_keys[i], 2011 ic->ic_myaddr); 2012 } 2013 ath_key_update_end(ic); 2014 2015 /* 2016 * Handle any link-level address change. Note that we only 2017 * need to force ic_myaddr; any other addresses are handled 2018 * as a byproduct of the ifnet code marking the interface 2019 * down then up. 2020 * 2021 * XXX should get from lladdr instead of arpcom but that's more work 2022 */ 2023 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(sc->sc_if.if_sadl)); 2024 ath_hal_setmac(ah, ic->ic_myaddr); 2025 2026 /* calculate and install multicast filter */ 2027 ifp->if_flags &= ~IFF_ALLMULTI; 2028 mfilt[0] = mfilt[1] = 0; 2029 ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 2030 while (enm != NULL) { 2031 void *dl; 2032 /* XXX Punt on ranges. */ 2033 if (!IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 2034 mfilt[0] = mfilt[1] = 0xffffffff; 2035 ifp->if_flags |= IFF_ALLMULTI; 2036 break; 2037 } 2038 dl = enm->enm_addrlo; 2039 val = LE_READ_4((char *)dl + 0); 2040 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2041 val = LE_READ_4((char *)dl + 3); 2042 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2043 pos &= 0x3f; 2044 mfilt[pos / 32] |= (1 << (pos % 32)); 2045 2046 ETHER_NEXT_MULTI(estep, enm); 2047 } 2048 2049 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 2050 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 2051 __func__, rfilt, mfilt[0], mfilt[1]); 2052 } 2053 2054 /* 2055 * Set the slot time based on the current setting. 2056 */ 2057 static void 2058 ath_setslottime(struct ath_softc *sc) 2059 { 2060 struct ieee80211com *ic = &sc->sc_ic; 2061 struct ath_hal *ah = sc->sc_ah; 2062 2063 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2064 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 2065 else 2066 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 2067 sc->sc_updateslot = OK; 2068 } 2069 2070 /* 2071 * Callback from the 802.11 layer to update the 2072 * slot time based on the current setting. 2073 */ 2074 static void 2075 ath_updateslot(struct ifnet *ifp) 2076 { 2077 struct ath_softc *sc = ifp->if_softc; 2078 struct ieee80211com *ic = &sc->sc_ic; 2079 2080 /* 2081 * When not coordinating the BSS, change the hardware 2082 * immediately. For other operation we defer the change 2083 * until beacon updates have propagated to the stations. 2084 */ 2085 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2086 sc->sc_updateslot = UPDATE; 2087 else 2088 ath_setslottime(sc); 2089 } 2090 2091 /* 2092 * Setup a h/w transmit queue for beacons. 2093 */ 2094 static int 2095 ath_beaconq_setup(struct ath_hal *ah) 2096 { 2097 HAL_TXQ_INFO qi; 2098 2099 memset(&qi, 0, sizeof(qi)); 2100 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2101 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2102 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2103 /* NB: for dynamic turbo, don't enable any other interrupts */ 2104 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2105 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2106 } 2107 2108 /* 2109 * Setup the transmit queue parameters for the beacon queue. 2110 */ 2111 static int 2112 ath_beaconq_config(struct ath_softc *sc) 2113 { 2114 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2115 struct ieee80211com *ic = &sc->sc_ic; 2116 struct ath_hal *ah = sc->sc_ah; 2117 HAL_TXQ_INFO qi; 2118 2119 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2120 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2121 /* 2122 * Always burst out beacon and CAB traffic. 2123 */ 2124 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2125 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2126 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2127 } else { 2128 struct wmeParams *wmep = 2129 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2130 /* 2131 * Adhoc mode; important thing is to use 2x cwmin. 2132 */ 2133 qi.tqi_aifs = wmep->wmep_aifsn; 2134 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2135 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2136 } 2137 2138 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2139 device_printf(sc->sc_dev, "unable to update parameters for " 2140 "beacon hardware queue!\n"); 2141 return 0; 2142 } else { 2143 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2144 return 1; 2145 } 2146 #undef ATH_EXPONENT_TO_VALUE 2147 } 2148 2149 /* 2150 * Allocate and setup an initial beacon frame. 2151 */ 2152 static int 2153 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2154 { 2155 struct ieee80211com *ic = ni->ni_ic; 2156 struct ath_buf *bf; 2157 struct mbuf *m; 2158 int error; 2159 2160 bf = STAILQ_FIRST(&sc->sc_bbuf); 2161 if (bf == NULL) { 2162 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2163 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2164 return ENOMEM; /* XXX */ 2165 } 2166 /* 2167 * NB: the beacon data buffer must be 32-bit aligned; 2168 * we assume the mbuf routines will return us something 2169 * with this alignment (perhaps should assert). 2170 */ 2171 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2172 if (m == NULL) { 2173 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2174 __func__); 2175 sc->sc_stats.ast_be_nombuf++; 2176 return ENOMEM; 2177 } 2178 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2179 BUS_DMA_NOWAIT); 2180 if (error == 0) { 2181 bf->bf_m = m; 2182 bf->bf_node = ieee80211_ref_node(ni); 2183 } else { 2184 m_freem(m); 2185 } 2186 return error; 2187 } 2188 2189 /* 2190 * Setup the beacon frame for transmit. 2191 */ 2192 static void 2193 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2194 { 2195 #define USE_SHPREAMBLE(_ic) \ 2196 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2197 == IEEE80211_F_SHPREAMBLE) 2198 struct ieee80211_node *ni = bf->bf_node; 2199 struct ieee80211com *ic = ni->ni_ic; 2200 struct mbuf *m = bf->bf_m; 2201 struct ath_hal *ah = sc->sc_ah; 2202 struct ath_desc *ds; 2203 int flags, antenna; 2204 const HAL_RATE_TABLE *rt; 2205 u_int8_t rix, rate; 2206 2207 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 2208 __func__, m, m->m_len); 2209 2210 /* setup descriptors */ 2211 ds = bf->bf_desc; 2212 2213 flags = HAL_TXDESC_NOACK; 2214 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2215 ds->ds_link = HTOAH32(bf->bf_daddr); /* self-linked */ 2216 flags |= HAL_TXDESC_VEOL; 2217 /* 2218 * Let hardware handle antenna switching unless 2219 * the user has selected a transmit antenna 2220 * (sc_txantenna is not 0). 2221 */ 2222 antenna = sc->sc_txantenna; 2223 } else { 2224 ds->ds_link = 0; 2225 /* 2226 * Switch antenna every 4 beacons, unless the user 2227 * has selected a transmit antenna (sc_txantenna 2228 * is not 0). 2229 * 2230 * XXX assumes two antenna 2231 */ 2232 if (sc->sc_txantenna == 0) 2233 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2234 else 2235 antenna = sc->sc_txantenna; 2236 } 2237 2238 KASSERTMSG(bf->bf_nseg == 1, 2239 "multi-segment beacon frame; nseg %u", bf->bf_nseg); 2240 ds->ds_data = bf->bf_segs[0].ds_addr; 2241 /* 2242 * Calculate rate code. 2243 * XXX everything at min xmit rate 2244 */ 2245 rix = sc->sc_minrateix; 2246 rt = sc->sc_currates; 2247 rate = rt->info[rix].rateCode; 2248 if (USE_SHPREAMBLE(ic)) 2249 rate |= rt->info[rix].shortPreamble; 2250 ath_hal_setuptxdesc(ah, ds 2251 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2252 , sizeof(struct ieee80211_frame)/* header length */ 2253 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2254 , ni->ni_txpower /* txpower XXX */ 2255 , rate, 1 /* series 0 rate/tries */ 2256 , HAL_TXKEYIX_INVALID /* no encryption */ 2257 , antenna /* antenna mode */ 2258 , flags /* no ack, veol for beacons */ 2259 , 0 /* rts/cts rate */ 2260 , 0 /* rts/cts duration */ 2261 ); 2262 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2263 ath_hal_filltxdesc(ah, ds 2264 , roundup(m->m_len, 4) /* buffer length */ 2265 , AH_TRUE /* first segment */ 2266 , AH_TRUE /* last segment */ 2267 , ds /* first descriptor */ 2268 ); 2269 2270 /* NB: The desc swap function becomes void, if descriptor swapping 2271 * is not enabled 2272 */ 2273 ath_desc_swap(ds); 2274 2275 #undef USE_SHPREAMBLE 2276 } 2277 2278 /* 2279 * Transmit a beacon frame at SWBA. Dynamic updates to the 2280 * frame contents are done as needed and the slot time is 2281 * also adjusted based on current state. 2282 */ 2283 static void 2284 ath_beacon_proc(void *arg, int pending) 2285 { 2286 struct ath_softc *sc = arg; 2287 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2288 struct ieee80211_node *ni = bf->bf_node; 2289 struct ieee80211com *ic = ni->ni_ic; 2290 struct ath_hal *ah = sc->sc_ah; 2291 struct mbuf *m; 2292 int ncabq, error, otherant; 2293 2294 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2295 __func__, pending); 2296 2297 if (ic->ic_opmode == IEEE80211_M_STA || 2298 ic->ic_opmode == IEEE80211_M_MONITOR || 2299 bf == NULL || bf->bf_m == NULL) { 2300 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2301 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2302 return; 2303 } 2304 /* 2305 * Check if the previous beacon has gone out. If 2306 * not don't try to post another, skip this period 2307 * and wait for the next. Missed beacons indicate 2308 * a problem and should not occur. If we miss too 2309 * many consecutive beacons reset the device. 2310 */ 2311 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2312 sc->sc_bmisscount++; 2313 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2314 "%s: missed %u consecutive beacons\n", 2315 __func__, sc->sc_bmisscount); 2316 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2317 TASK_RUN_OR_ENQUEUE(&sc->sc_bstucktask); 2318 return; 2319 } 2320 if (sc->sc_bmisscount != 0) { 2321 DPRINTF(sc, ATH_DEBUG_BEACON, 2322 "%s: resume beacon xmit after %u misses\n", 2323 __func__, sc->sc_bmisscount); 2324 sc->sc_bmisscount = 0; 2325 } 2326 2327 /* 2328 * Update dynamic beacon contents. If this returns 2329 * non-zero then we need to remap the memory because 2330 * the beacon frame changed size (probably because 2331 * of the TIM bitmap). 2332 */ 2333 m = bf->bf_m; 2334 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 2335 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 2336 /* XXX too conservative? */ 2337 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2338 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 2339 BUS_DMA_NOWAIT); 2340 if (error != 0) { 2341 if_printf(&sc->sc_if, 2342 "%s: bus_dmamap_load_mbuf failed, error %u\n", 2343 __func__, error); 2344 return; 2345 } 2346 } 2347 2348 /* 2349 * Handle slot time change when a non-ERP station joins/leaves 2350 * an 11g network. The 802.11 layer notifies us via callback, 2351 * we mark updateslot, then wait one beacon before effecting 2352 * the change. This gives associated stations at least one 2353 * beacon interval to note the state change. 2354 */ 2355 /* XXX locking */ 2356 if (sc->sc_updateslot == UPDATE) 2357 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2358 else if (sc->sc_updateslot == COMMIT) 2359 ath_setslottime(sc); /* commit change to h/w */ 2360 2361 /* 2362 * Check recent per-antenna transmit statistics and flip 2363 * the default antenna if noticeably more frames went out 2364 * on the non-default antenna. 2365 * XXX assumes 2 anntenae 2366 */ 2367 otherant = sc->sc_defant & 1 ? 2 : 1; 2368 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2369 ath_setdefantenna(sc, otherant); 2370 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2371 2372 /* 2373 * Construct tx descriptor. 2374 */ 2375 ath_beacon_setup(sc, bf); 2376 2377 /* 2378 * Stop any current dma and put the new frame on the queue. 2379 * This should never fail since we check above that no frames 2380 * are still pending on the queue. 2381 */ 2382 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2383 DPRINTF(sc, ATH_DEBUG_ANY, 2384 "%s: beacon queue %u did not stop?\n", 2385 __func__, sc->sc_bhalq); 2386 } 2387 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2388 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 2389 2390 /* 2391 * Enable the CAB queue before the beacon queue to 2392 * insure cab frames are triggered by this beacon. 2393 */ 2394 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */ 2395 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2396 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2397 ath_hal_txstart(ah, sc->sc_bhalq); 2398 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2399 "%s: TXDP[%u] = %" PRIx64 " (%p)\n", __func__, 2400 sc->sc_bhalq, (uint64_t)bf->bf_daddr, bf->bf_desc); 2401 2402 sc->sc_stats.ast_be_xmit++; 2403 } 2404 2405 /* 2406 * Reset the hardware after detecting beacons have stopped. 2407 */ 2408 static void 2409 ath_bstuck_proc(void *arg, int pending) 2410 { 2411 struct ath_softc *sc = arg; 2412 struct ifnet *ifp = &sc->sc_if; 2413 #ifdef __NetBSD__ 2414 int s; 2415 #endif 2416 2417 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2418 sc->sc_bmisscount); 2419 #ifdef __NetBSD__ 2420 s = splnet(); 2421 #endif 2422 ath_reset(ifp); 2423 #ifdef __NetBSD__ 2424 splx(s); 2425 #endif 2426 } 2427 2428 /* 2429 * Reclaim beacon resources. 2430 */ 2431 static void 2432 ath_beacon_free(struct ath_softc *sc) 2433 { 2434 struct ath_buf *bf; 2435 2436 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2437 if (bf->bf_m != NULL) { 2438 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2439 m_freem(bf->bf_m); 2440 bf->bf_m = NULL; 2441 } 2442 if (bf->bf_node != NULL) { 2443 ieee80211_free_node(bf->bf_node); 2444 bf->bf_node = NULL; 2445 } 2446 } 2447 } 2448 2449 /* 2450 * Configure the beacon and sleep timers. 2451 * 2452 * When operating as an AP this resets the TSF and sets 2453 * up the hardware to notify us when we need to issue beacons. 2454 * 2455 * When operating in station mode this sets up the beacon 2456 * timers according to the timestamp of the last received 2457 * beacon and the current TSF, configures PCF and DTIM 2458 * handling, programs the sleep registers so the hardware 2459 * will wakeup in time to receive beacons, and configures 2460 * the beacon miss handling so we'll receive a BMISS 2461 * interrupt when we stop seeing beacons from the AP 2462 * we've associated with. 2463 */ 2464 static void 2465 ath_beacon_config(struct ath_softc *sc) 2466 { 2467 #define TSF_TO_TU(_h,_l) \ 2468 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2469 #define FUDGE 2 2470 struct ath_hal *ah = sc->sc_ah; 2471 struct ieee80211com *ic = &sc->sc_ic; 2472 struct ieee80211_node *ni = ic->ic_bss; 2473 u_int32_t nexttbtt, intval, tsftu; 2474 u_int64_t tsf; 2475 2476 /* extract tstamp from last beacon and convert to TU */ 2477 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2478 LE_READ_4(ni->ni_tstamp.data)); 2479 /* NB: the beacon interval is kept internally in TU's */ 2480 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2481 if (nexttbtt == 0) /* e.g. for ap mode */ 2482 nexttbtt = intval; 2483 else if (intval) /* NB: can be 0 for monitor mode */ 2484 nexttbtt = roundup(nexttbtt, intval); 2485 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2486 __func__, nexttbtt, intval, ni->ni_intval); 2487 if (ic->ic_opmode == IEEE80211_M_STA) { 2488 HAL_BEACON_STATE bs; 2489 int dtimperiod, dtimcount; 2490 int cfpperiod, cfpcount; 2491 2492 /* 2493 * Setup dtim and cfp parameters according to 2494 * last beacon we received (which may be none). 2495 */ 2496 dtimperiod = ni->ni_dtim_period; 2497 if (dtimperiod <= 0) /* NB: 0 if not known */ 2498 dtimperiod = 1; 2499 dtimcount = ni->ni_dtim_count; 2500 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2501 dtimcount = 0; /* XXX? */ 2502 cfpperiod = 1; /* NB: no PCF support yet */ 2503 cfpcount = 0; 2504 /* 2505 * Pull nexttbtt forward to reflect the current 2506 * TSF and calculate dtim+cfp state for the result. 2507 */ 2508 tsf = ath_hal_gettsf64(ah); 2509 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2510 do { 2511 nexttbtt += intval; 2512 if (--dtimcount < 0) { 2513 dtimcount = dtimperiod - 1; 2514 if (--cfpcount < 0) 2515 cfpcount = cfpperiod - 1; 2516 } 2517 } while (nexttbtt < tsftu); 2518 memset(&bs, 0, sizeof(bs)); 2519 bs.bs_intval = intval; 2520 bs.bs_nexttbtt = nexttbtt; 2521 bs.bs_dtimperiod = dtimperiod*intval; 2522 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2523 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2524 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2525 bs.bs_cfpmaxduration = 0; 2526 #if 0 2527 /* 2528 * The 802.11 layer records the offset to the DTIM 2529 * bitmap while receiving beacons; use it here to 2530 * enable h/w detection of our AID being marked in 2531 * the bitmap vector (to indicate frames for us are 2532 * pending at the AP). 2533 * XXX do DTIM handling in s/w to WAR old h/w bugs 2534 * XXX enable based on h/w rev for newer chips 2535 */ 2536 bs.bs_timoffset = ni->ni_timoff; 2537 #endif 2538 /* 2539 * Calculate the number of consecutive beacons to miss 2540 * before taking a BMISS interrupt. The configuration 2541 * is specified in ms, so we need to convert that to 2542 * TU's and then calculate based on the beacon interval. 2543 * Note that we clamp the result to at most 10 beacons. 2544 */ 2545 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval); 2546 if (bs.bs_bmissthreshold > 10) 2547 bs.bs_bmissthreshold = 10; 2548 else if (bs.bs_bmissthreshold <= 0) 2549 bs.bs_bmissthreshold = 1; 2550 2551 /* 2552 * Calculate sleep duration. The configuration is 2553 * given in ms. We insure a multiple of the beacon 2554 * period is used. Also, if the sleep duration is 2555 * greater than the DTIM period then it makes senses 2556 * to make it a multiple of that. 2557 * 2558 * XXX fixed at 100ms 2559 */ 2560 bs.bs_sleepduration = 2561 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2562 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2563 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2564 2565 DPRINTF(sc, ATH_DEBUG_BEACON, 2566 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2567 , __func__ 2568 , tsf, tsftu 2569 , bs.bs_intval 2570 , bs.bs_nexttbtt 2571 , bs.bs_dtimperiod 2572 , bs.bs_nextdtim 2573 , bs.bs_bmissthreshold 2574 , bs.bs_sleepduration 2575 , bs.bs_cfpperiod 2576 , bs.bs_cfpmaxduration 2577 , bs.bs_cfpnext 2578 , bs.bs_timoffset 2579 ); 2580 ath_hal_intrset(ah, 0); 2581 ath_hal_beacontimers(ah, &bs); 2582 sc->sc_imask |= HAL_INT_BMISS; 2583 ath_hal_intrset(ah, sc->sc_imask); 2584 } else { 2585 ath_hal_intrset(ah, 0); 2586 if (nexttbtt == intval) 2587 intval |= HAL_BEACON_RESET_TSF; 2588 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2589 /* 2590 * In IBSS mode enable the beacon timers but only 2591 * enable SWBA interrupts if we need to manually 2592 * prepare beacon frames. Otherwise we use a 2593 * self-linked tx descriptor and let the hardware 2594 * deal with things. 2595 */ 2596 intval |= HAL_BEACON_ENA; 2597 if (!sc->sc_hasveol) 2598 sc->sc_imask |= HAL_INT_SWBA; 2599 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2600 /* 2601 * Pull nexttbtt forward to reflect 2602 * the current TSF. 2603 */ 2604 tsf = ath_hal_gettsf64(ah); 2605 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2606 do { 2607 nexttbtt += intval; 2608 } while (nexttbtt < tsftu); 2609 } 2610 ath_beaconq_config(sc); 2611 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2612 /* 2613 * In AP mode we enable the beacon timers and 2614 * SWBA interrupts to prepare beacon frames. 2615 */ 2616 intval |= HAL_BEACON_ENA; 2617 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2618 ath_beaconq_config(sc); 2619 } 2620 ath_hal_beaconinit(ah, nexttbtt, intval); 2621 sc->sc_bmisscount = 0; 2622 ath_hal_intrset(ah, sc->sc_imask); 2623 /* 2624 * When using a self-linked beacon descriptor in 2625 * ibss mode load it once here. 2626 */ 2627 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2628 ath_beacon_proc(sc, 0); 2629 } 2630 sc->sc_syncbeacon = 0; 2631 #undef UNDEF 2632 #undef TSF_TO_TU 2633 } 2634 2635 static int 2636 ath_descdma_setup(struct ath_softc *sc, 2637 struct ath_descdma *dd, ath_bufhead *head, 2638 const char *name, int nbuf, int ndesc) 2639 { 2640 #define DS2PHYS(_dd, _ds) \ 2641 ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc)) 2642 struct ifnet *ifp = &sc->sc_if; 2643 struct ath_desc *ds; 2644 struct ath_buf *bf; 2645 int i, bsize, error; 2646 2647 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2648 __func__, name, nbuf, ndesc); 2649 2650 dd->dd_name = name; 2651 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2652 2653 /* 2654 * Setup DMA descriptor area. 2655 */ 2656 dd->dd_dmat = sc->sc_dmat; 2657 2658 error = bus_dmamem_alloc(dd->dd_dmat, dd->dd_desc_len, PAGE_SIZE, 2659 0, &dd->dd_dseg, 1, &dd->dd_dnseg, 0); 2660 2661 if (error != 0) { 2662 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2663 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2664 goto fail0; 2665 } 2666 2667 error = bus_dmamem_map(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg, 2668 dd->dd_desc_len, (void **)&dd->dd_desc, BUS_DMA_COHERENT); 2669 if (error != 0) { 2670 if_printf(ifp, "unable to map %u %s descriptors, error = %u\n", 2671 nbuf * ndesc, dd->dd_name, error); 2672 goto fail1; 2673 } 2674 2675 /* allocate descriptors */ 2676 error = bus_dmamap_create(dd->dd_dmat, dd->dd_desc_len, 1, 2677 dd->dd_desc_len, 0, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2678 if (error != 0) { 2679 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2680 "error %u\n", dd->dd_name, error); 2681 goto fail2; 2682 } 2683 2684 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, dd->dd_desc, 2685 dd->dd_desc_len, NULL, BUS_DMA_NOWAIT); 2686 if (error != 0) { 2687 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2688 dd->dd_name, error); 2689 goto fail3; 2690 } 2691 2692 ds = dd->dd_desc; 2693 dd->dd_desc_paddr = dd->dd_dmamap->dm_segs[0].ds_addr; 2694 DPRINTF(sc, ATH_DEBUG_RESET, 2695 "%s: %s DMA map: %p (%lu) -> %" PRIx64 " (%lu)\n", 2696 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2697 (uint64_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2698 2699 /* allocate rx buffers */ 2700 bsize = sizeof(struct ath_buf) * nbuf; 2701 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2702 if (bf == NULL) { 2703 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2704 dd->dd_name, bsize); 2705 goto fail4; 2706 } 2707 dd->dd_bufptr = bf; 2708 2709 STAILQ_INIT(head); 2710 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2711 bf->bf_desc = ds; 2712 bf->bf_daddr = DS2PHYS(dd, ds); 2713 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, ndesc, 2714 MCLBYTES, 0, BUS_DMA_NOWAIT, &bf->bf_dmamap); 2715 if (error != 0) { 2716 if_printf(ifp, "unable to create dmamap for %s " 2717 "buffer %u, error %u\n", dd->dd_name, i, error); 2718 ath_descdma_cleanup(sc, dd, head); 2719 return error; 2720 } 2721 STAILQ_INSERT_TAIL(head, bf, bf_list); 2722 } 2723 return 0; 2724 fail4: 2725 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2726 fail3: 2727 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2728 fail2: 2729 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2730 fail1: 2731 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2732 fail0: 2733 memset(dd, 0, sizeof(*dd)); 2734 return error; 2735 #undef DS2PHYS 2736 } 2737 2738 static void 2739 ath_descdma_cleanup(struct ath_softc *sc, 2740 struct ath_descdma *dd, ath_bufhead *head) 2741 { 2742 struct ath_buf *bf; 2743 struct ieee80211_node *ni; 2744 2745 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2746 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2747 bus_dmamem_unmap(dd->dd_dmat, (void *)dd->dd_desc, dd->dd_desc_len); 2748 bus_dmamem_free(dd->dd_dmat, &dd->dd_dseg, dd->dd_dnseg); 2749 2750 STAILQ_FOREACH(bf, head, bf_list) { 2751 if (bf->bf_m) { 2752 m_freem(bf->bf_m); 2753 bf->bf_m = NULL; 2754 } 2755 if (bf->bf_dmamap != NULL) { 2756 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2757 bf->bf_dmamap = NULL; 2758 } 2759 ni = bf->bf_node; 2760 bf->bf_node = NULL; 2761 if (ni != NULL) { 2762 /* 2763 * Reclaim node reference. 2764 */ 2765 ieee80211_free_node(ni); 2766 } 2767 } 2768 2769 STAILQ_INIT(head); 2770 free(dd->dd_bufptr, M_ATHDEV); 2771 memset(dd, 0, sizeof(*dd)); 2772 } 2773 2774 static int 2775 ath_desc_alloc(struct ath_softc *sc) 2776 { 2777 int error; 2778 2779 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2780 "rx", ath_rxbuf, 1); 2781 if (error != 0) 2782 return error; 2783 2784 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2785 "tx", ath_txbuf, ATH_TXDESC); 2786 if (error != 0) { 2787 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2788 return error; 2789 } 2790 2791 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2792 "beacon", 1, 1); 2793 if (error != 0) { 2794 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2795 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2796 return error; 2797 } 2798 return 0; 2799 } 2800 2801 static void 2802 ath_desc_free(struct ath_softc *sc) 2803 { 2804 2805 if (sc->sc_bdma.dd_desc_len != 0) 2806 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2807 if (sc->sc_txdma.dd_desc_len != 0) 2808 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2809 if (sc->sc_rxdma.dd_desc_len != 0) 2810 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2811 } 2812 2813 static struct ieee80211_node * 2814 ath_node_alloc(struct ieee80211_node_table *nt) 2815 { 2816 struct ieee80211com *ic = nt->nt_ic; 2817 struct ath_softc *sc = ic->ic_ifp->if_softc; 2818 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2819 struct ath_node *an; 2820 2821 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2822 if (an == NULL) { 2823 /* XXX stat+msg */ 2824 return NULL; 2825 } 2826 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2827 ath_rate_node_init(sc, an); 2828 2829 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2830 return &an->an_node; 2831 } 2832 2833 static void 2834 ath_node_free(struct ieee80211_node *ni) 2835 { 2836 struct ieee80211com *ic = ni->ni_ic; 2837 struct ath_softc *sc = ic->ic_ifp->if_softc; 2838 2839 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2840 2841 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2842 sc->sc_node_free(ni); 2843 } 2844 2845 static u_int8_t 2846 ath_node_getrssi(const struct ieee80211_node *ni) 2847 { 2848 #define HAL_EP_RND(x, mul) \ 2849 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2850 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2851 int32_t rssi; 2852 2853 /* 2854 * When only one frame is received there will be no state in 2855 * avgrssi so fallback on the value recorded by the 802.11 layer. 2856 */ 2857 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2858 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2859 else 2860 rssi = ni->ni_rssi; 2861 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2862 #undef HAL_EP_RND 2863 } 2864 2865 static int 2866 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2867 { 2868 struct ath_hal *ah = sc->sc_ah; 2869 int error; 2870 struct mbuf *m; 2871 struct ath_desc *ds; 2872 2873 m = bf->bf_m; 2874 if (m == NULL) { 2875 /* 2876 * NB: by assigning a page to the rx dma buffer we 2877 * implicitly satisfy the Atheros requirement that 2878 * this buffer be cache-line-aligned and sized to be 2879 * multiple of the cache line size. Not doing this 2880 * causes weird stuff to happen (for the 5210 at least). 2881 */ 2882 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2883 if (m == NULL) { 2884 DPRINTF(sc, ATH_DEBUG_ANY, 2885 "%s: no mbuf/cluster\n", __func__); 2886 sc->sc_stats.ast_rx_nombuf++; 2887 return ENOMEM; 2888 } 2889 bf->bf_m = m; 2890 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2891 2892 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2893 bf->bf_dmamap, m, 2894 BUS_DMA_NOWAIT); 2895 if (error != 0) { 2896 DPRINTF(sc, ATH_DEBUG_ANY, 2897 "%s: bus_dmamap_load_mbuf failed; error %d\n", 2898 __func__, error); 2899 sc->sc_stats.ast_rx_busdma++; 2900 return error; 2901 } 2902 KASSERTMSG(bf->bf_nseg == 1, 2903 "multi-segment packet; nseg %u", bf->bf_nseg); 2904 } 2905 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 2906 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2907 2908 /* 2909 * Setup descriptors. For receive we always terminate 2910 * the descriptor list with a self-linked entry so we'll 2911 * not get overrun under high load (as can happen with a 2912 * 5212 when ANI processing enables PHY error frames). 2913 * 2914 * To insure the last descriptor is self-linked we create 2915 * each descriptor as self-linked and add it to the end. As 2916 * each additional descriptor is added the previous self-linked 2917 * entry is ``fixed'' naturally. This should be safe even 2918 * if DMA is happening. When processing RX interrupts we 2919 * never remove/process the last, self-linked, entry on the 2920 * descriptor list. This insures the hardware always has 2921 * someplace to write a new frame. 2922 */ 2923 ds = bf->bf_desc; 2924 ds->ds_link = HTOAH32(bf->bf_daddr); /* link to self */ 2925 ds->ds_data = bf->bf_segs[0].ds_addr; 2926 /* ds->ds_vdata = mtod(m, void *); for radar */ 2927 ath_hal_setuprxdesc(ah, ds 2928 , m->m_len /* buffer size */ 2929 , 0 2930 ); 2931 2932 if (sc->sc_rxlink != NULL) 2933 *sc->sc_rxlink = bf->bf_daddr; 2934 sc->sc_rxlink = &ds->ds_link; 2935 return 0; 2936 } 2937 2938 /* 2939 * Extend 15-bit time stamp from rx descriptor to 2940 * a full 64-bit TSF using the specified TSF. 2941 */ 2942 static inline u_int64_t 2943 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2944 { 2945 if ((tsf & 0x7fff) < rstamp) 2946 tsf -= 0x8000; 2947 return ((tsf &~ 0x7fff) | rstamp); 2948 } 2949 2950 /* 2951 * Intercept management frames to collect beacon rssi data 2952 * and to do ibss merges. 2953 */ 2954 static void 2955 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2956 struct ieee80211_node *ni, 2957 int subtype, int rssi, u_int32_t rstamp) 2958 { 2959 struct ath_softc *sc = ic->ic_ifp->if_softc; 2960 2961 /* 2962 * Call up first so subsequent work can use information 2963 * potentially stored in the node (e.g. for ibss merge). 2964 */ 2965 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2966 switch (subtype) { 2967 case IEEE80211_FC0_SUBTYPE_BEACON: 2968 /* update rssi statistics for use by the hal */ 2969 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 2970 if (sc->sc_syncbeacon && 2971 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 2972 /* 2973 * Resync beacon timers using the tsf of the beacon 2974 * frame we just received. 2975 */ 2976 ath_beacon_config(sc); 2977 } 2978 /* fall thru... */ 2979 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2980 if (ic->ic_opmode == IEEE80211_M_IBSS && 2981 ic->ic_state == IEEE80211_S_RUN) { 2982 u_int64_t tsf = ath_extend_tsf(rstamp, 2983 ath_hal_gettsf64(sc->sc_ah)); 2984 2985 /* 2986 * Handle ibss merge as needed; check the tsf on the 2987 * frame before attempting the merge. The 802.11 spec 2988 * says the station should change its bssid to match 2989 * the oldest station with the same ssid, where oldest 2990 * is determined by the tsf. Note that hardware 2991 * reconfiguration happens through callback to 2992 * ath_newstate as the state machine will go from 2993 * RUN -> RUN when this happens. 2994 */ 2995 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2996 DPRINTF(sc, ATH_DEBUG_STATE, 2997 "ibss merge, rstamp %u tsf %ju " 2998 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2999 (uintmax_t)ni->ni_tstamp.tsf); 3000 (void) ieee80211_ibss_merge(ni); 3001 } 3002 } 3003 break; 3004 } 3005 } 3006 3007 /* 3008 * Set the default antenna. 3009 */ 3010 static void 3011 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3012 { 3013 struct ath_hal *ah = sc->sc_ah; 3014 3015 /* XXX block beacon interrupts */ 3016 ath_hal_setdefantenna(ah, antenna); 3017 if (sc->sc_defant != antenna) 3018 sc->sc_stats.ast_ant_defswitch++; 3019 sc->sc_defant = antenna; 3020 sc->sc_rxotherant = 0; 3021 } 3022 3023 static void 3024 ath_handle_micerror(struct ieee80211com *ic, 3025 struct ieee80211_frame *wh, int keyix) 3026 { 3027 struct ieee80211_node *ni; 3028 3029 /* XXX recheck MIC to deal w/ chips that lie */ 3030 /* XXX discard MIC errors on !data frames */ 3031 ni = ieee80211_find_rxnode_withkey(ic, (const struct ieee80211_frame_min *) wh, keyix); 3032 if (ni != NULL) { 3033 ieee80211_notify_michael_failure(ic, wh, keyix); 3034 ieee80211_free_node(ni); 3035 } 3036 } 3037 3038 static void 3039 ath_rx_proc(void *arg, int npending) 3040 { 3041 #define PA2DESC(_sc, _pa) \ 3042 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 3043 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3044 struct ath_softc *sc = arg; 3045 struct ath_buf *bf; 3046 struct ieee80211com *ic = &sc->sc_ic; 3047 struct ifnet *ifp = &sc->sc_if; 3048 struct ath_hal *ah = sc->sc_ah; 3049 struct ath_desc *ds; 3050 struct mbuf *m; 3051 struct ieee80211_node *ni; 3052 struct ath_node *an; 3053 int len, ngood, type; 3054 u_int phyerr; 3055 HAL_STATUS status; 3056 int16_t nf; 3057 u_int64_t tsf; 3058 uint8_t rxerr_tap, rxerr_mon; 3059 NET_LOCK_GIANT_FUNC_INIT(); 3060 3061 NET_LOCK_GIANT(); /* XXX */ 3062 3063 rxerr_tap = 3064 (ifp->if_flags & IFF_PROMISC) ? HAL_RXERR_CRC|HAL_RXERR_PHY : 0; 3065 3066 if (sc->sc_ic.ic_opmode == IEEE80211_M_MONITOR) 3067 rxerr_mon = HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3068 else if (ifp->if_flags & IFF_PROMISC) 3069 rxerr_tap |= HAL_RXERR_DECRYPT|HAL_RXERR_MIC; 3070 3071 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3072 ngood = 0; 3073 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3074 tsf = ath_hal_gettsf64(ah); 3075 do { 3076 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3077 if (bf == NULL) { /* NB: shouldn't happen */ 3078 if_printf(ifp, "%s: no buffer!\n", __func__); 3079 break; 3080 } 3081 ds = bf->bf_desc; 3082 if (ds->ds_link == bf->bf_daddr) { 3083 /* NB: never process the self-linked entry at the end */ 3084 break; 3085 } 3086 m = bf->bf_m; 3087 if (m == NULL) { /* NB: shouldn't happen */ 3088 if_printf(ifp, "%s: no mbuf!\n", __func__); 3089 break; 3090 } 3091 /* XXX sync descriptor memory */ 3092 /* 3093 * Must provide the virtual address of the current 3094 * descriptor, the physical address, and the virtual 3095 * address of the next descriptor in the h/w chain. 3096 * This allows the HAL to look ahead to see if the 3097 * hardware is done with a descriptor by checking the 3098 * done bit in the following descriptor and the address 3099 * of the current descriptor the DMA engine is working 3100 * on. All this is necessary because of our use of 3101 * a self-linked list to avoid rx overruns. 3102 */ 3103 status = ath_hal_rxprocdesc(ah, ds, 3104 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 3105 &ds->ds_rxstat); 3106 #ifdef AR_DEBUG 3107 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3108 ath_printrxbuf(bf, status == HAL_OK); 3109 #endif 3110 if (status == HAL_EINPROGRESS) 3111 break; 3112 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3113 if (ds->ds_rxstat.rs_more) { 3114 /* 3115 * Frame spans multiple descriptors; this 3116 * cannot happen yet as we don't support 3117 * jumbograms. If not in monitor mode, 3118 * discard the frame. 3119 */ 3120 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3121 sc->sc_stats.ast_rx_toobig++; 3122 goto rx_next; 3123 } 3124 /* fall thru for monitor mode handling... */ 3125 } else if (ds->ds_rxstat.rs_status != 0) { 3126 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 3127 sc->sc_stats.ast_rx_crcerr++; 3128 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 3129 sc->sc_stats.ast_rx_fifoerr++; 3130 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 3131 sc->sc_stats.ast_rx_phyerr++; 3132 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 3133 sc->sc_stats.ast_rx_phy[phyerr]++; 3134 goto rx_next; 3135 } 3136 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 3137 /* 3138 * Decrypt error. If the error occurred 3139 * because there was no hardware key, then 3140 * let the frame through so the upper layers 3141 * can process it. This is necessary for 5210 3142 * parts which have no way to setup a ``clear'' 3143 * key cache entry. 3144 * 3145 * XXX do key cache faulting 3146 */ 3147 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 3148 goto rx_accept; 3149 sc->sc_stats.ast_rx_badcrypt++; 3150 } 3151 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 3152 sc->sc_stats.ast_rx_badmic++; 3153 /* 3154 * Do minimal work required to hand off 3155 * the 802.11 header for notifcation. 3156 */ 3157 /* XXX frag's and qos frames */ 3158 len = ds->ds_rxstat.rs_datalen; 3159 if (len >= sizeof (struct ieee80211_frame)) { 3160 bus_dmamap_sync(sc->sc_dmat, 3161 bf->bf_dmamap, 3162 0, bf->bf_dmamap->dm_mapsize, 3163 BUS_DMASYNC_POSTREAD); 3164 ath_handle_micerror(ic, 3165 mtod(m, struct ieee80211_frame *), 3166 sc->sc_splitmic ? 3167 ds->ds_rxstat.rs_keyix-32 : ds->ds_rxstat.rs_keyix); 3168 } 3169 } 3170 ifp->if_ierrors++; 3171 /* 3172 * Reject error frames, we normally don't want 3173 * to see them in monitor mode (in monitor mode 3174 * allow through packets that have crypto problems). 3175 */ 3176 3177 if (ds->ds_rxstat.rs_status &~ (rxerr_tap|rxerr_mon)) 3178 goto rx_next; 3179 } 3180 rx_accept: 3181 /* 3182 * Sync and unmap the frame. At this point we're 3183 * committed to passing the mbuf somewhere so clear 3184 * bf_m; this means a new sk_buff must be allocated 3185 * when the rx descriptor is setup again to receive 3186 * another frame. 3187 */ 3188 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3189 0, bf->bf_dmamap->dm_mapsize, 3190 BUS_DMASYNC_POSTREAD); 3191 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3192 bf->bf_m = NULL; 3193 3194 m_set_rcvif(m, ifp); 3195 len = ds->ds_rxstat.rs_datalen; 3196 m->m_pkthdr.len = m->m_len = len; 3197 3198 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 3199 3200 if (sc->sc_drvbpf) { 3201 u_int8_t rix; 3202 3203 /* 3204 * Discard anything shorter than an ack or cts. 3205 */ 3206 if (len < IEEE80211_ACK_LEN) { 3207 DPRINTF(sc, ATH_DEBUG_RECV, 3208 "%s: runt packet %d\n", 3209 __func__, len); 3210 sc->sc_stats.ast_rx_tooshort++; 3211 m_freem(m); 3212 goto rx_next; 3213 } 3214 rix = ds->ds_rxstat.rs_rate; 3215 sc->sc_rx_th.wr_tsf = htole64( 3216 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 3217 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3218 if (ds->ds_rxstat.rs_status & 3219 (HAL_RXERR_CRC|HAL_RXERR_PHY)) { 3220 sc->sc_rx_th.wr_flags |= 3221 IEEE80211_RADIOTAP_F_BADFCS; 3222 } 3223 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3224 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 3225 sc->sc_rx_th.wr_antnoise = nf; 3226 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 3227 3228 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, 3229 sc->sc_rx_th_len, m, BPF_D_IN); 3230 } 3231 3232 if (ds->ds_rxstat.rs_status & rxerr_tap) { 3233 m_freem(m); 3234 goto rx_next; 3235 } 3236 /* 3237 * From this point on we assume the frame is at least 3238 * as large as ieee80211_frame_min; verify that. 3239 */ 3240 if (len < IEEE80211_MIN_LEN) { 3241 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3242 __func__, len); 3243 sc->sc_stats.ast_rx_tooshort++; 3244 m_freem(m); 3245 goto rx_next; 3246 } 3247 3248 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3249 ieee80211_dump_pkt(mtod(m, void *), len, 3250 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 3251 ds->ds_rxstat.rs_rssi); 3252 } 3253 3254 m_adj(m, -IEEE80211_CRC_LEN); 3255 3256 /* 3257 * Locate the node for sender, track state, and then 3258 * pass the (referenced) node up to the 802.11 layer 3259 * for its use. 3260 */ 3261 ni = ieee80211_find_rxnode_withkey(ic, 3262 mtod(m, const struct ieee80211_frame_min *), 3263 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 3264 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 3265 /* 3266 * Track rx rssi and do any rx antenna management. 3267 */ 3268 an = ATH_NODE(ni); 3269 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 3270 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi); 3271 /* 3272 * Send frame up for processing. 3273 */ 3274 type = ieee80211_input(ic, m, ni, 3275 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 3276 ieee80211_free_node(ni); 3277 if (sc->sc_diversity) { 3278 /* 3279 * When using fast diversity, change the default rx 3280 * antenna if diversity chooses the other antenna 3 3281 * times in a row. 3282 */ 3283 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 3284 if (++sc->sc_rxotherant >= 3) 3285 ath_setdefantenna(sc, 3286 ds->ds_rxstat.rs_antenna); 3287 } else 3288 sc->sc_rxotherant = 0; 3289 } 3290 if (sc->sc_softled) { 3291 /* 3292 * Blink for any data frame. Otherwise do a 3293 * heartbeat-style blink when idle. The latter 3294 * is mainly for station mode where we depend on 3295 * periodic beacon frames to trigger the poll event. 3296 */ 3297 if (type == IEEE80211_FC0_TYPE_DATA) { 3298 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 3299 ath_led_event(sc, ATH_LED_RX); 3300 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3301 ath_led_event(sc, ATH_LED_POLL); 3302 } 3303 /* 3304 * Arrange to update the last rx timestamp only for 3305 * frames from our ap when operating in station mode. 3306 * This assumes the rx key is always setup when associated. 3307 */ 3308 if (ic->ic_opmode == IEEE80211_M_STA && 3309 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID) 3310 ngood++; 3311 rx_next: 3312 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3313 } while (ath_rxbuf_init(sc, bf) == 0); 3314 3315 /* rx signal state monitoring */ 3316 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3317 #if 0 3318 if (ath_hal_radar_event(ah)) 3319 TASK_RUN_OR_ENQUEUE(&sc->sc_radartask); 3320 #endif 3321 if (ngood) 3322 sc->sc_lastrx = tsf; 3323 3324 #ifdef __NetBSD__ 3325 /* XXX Why isn't this necessary in FreeBSD? */ 3326 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !IFQ_IS_EMPTY(&ifp->if_snd)) 3327 ath_start(ifp); 3328 #endif /* __NetBSD__ */ 3329 3330 NET_UNLOCK_GIANT(); /* XXX */ 3331 #undef PA2DESC 3332 } 3333 3334 /* 3335 * Setup a h/w transmit queue. 3336 */ 3337 static struct ath_txq * 3338 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3339 { 3340 #define N(a) (sizeof(a)/sizeof(a[0])) 3341 struct ath_hal *ah = sc->sc_ah; 3342 HAL_TXQ_INFO qi; 3343 int qnum; 3344 3345 memset(&qi, 0, sizeof(qi)); 3346 qi.tqi_subtype = subtype; 3347 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3348 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3349 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3350 /* 3351 * Enable interrupts only for EOL and DESC conditions. 3352 * We mark tx descriptors to receive a DESC interrupt 3353 * when a tx queue gets deep; otherwise waiting for the 3354 * EOL to reap descriptors. Note that this is done to 3355 * reduce interrupt load and this only defers reaping 3356 * descriptors, never transmitting frames. Aside from 3357 * reducing interrupts this also permits more concurrency. 3358 * The only potential downside is if the tx queue backs 3359 * up in which case the top half of the kernel may backup 3360 * due to a lack of tx descriptors. 3361 */ 3362 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3363 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3364 if (qnum == -1) { 3365 /* 3366 * NB: don't print a message, this happens 3367 * normally on parts with too few tx queues 3368 */ 3369 return NULL; 3370 } 3371 if (qnum >= N(sc->sc_txq)) { 3372 device_printf(sc->sc_dev, 3373 "hal qnum %u out of range, max %zu!\n", 3374 qnum, N(sc->sc_txq)); 3375 ath_hal_releasetxqueue(ah, qnum); 3376 return NULL; 3377 } 3378 if (!ATH_TXQ_SETUP(sc, qnum)) { 3379 struct ath_txq *txq = &sc->sc_txq[qnum]; 3380 3381 txq->axq_qnum = qnum; 3382 txq->axq_depth = 0; 3383 txq->axq_intrcnt = 0; 3384 txq->axq_link = NULL; 3385 STAILQ_INIT(&txq->axq_q); 3386 ATH_TXQ_LOCK_INIT(sc, txq); 3387 sc->sc_txqsetup |= 1<<qnum; 3388 } 3389 return &sc->sc_txq[qnum]; 3390 #undef N 3391 } 3392 3393 /* 3394 * Setup a hardware data transmit queue for the specified 3395 * access control. The hal may not support all requested 3396 * queues in which case it will return a reference to a 3397 * previously setup queue. We record the mapping from ac's 3398 * to h/w queues for use by ath_tx_start and also track 3399 * the set of h/w queues being used to optimize work in the 3400 * transmit interrupt handler and related routines. 3401 */ 3402 static int 3403 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3404 { 3405 #define N(a) (sizeof(a)/sizeof(a[0])) 3406 struct ath_txq *txq; 3407 3408 if (ac >= N(sc->sc_ac2q)) { 3409 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3410 ac, N(sc->sc_ac2q)); 3411 return 0; 3412 } 3413 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3414 if (txq != NULL) { 3415 sc->sc_ac2q[ac] = txq; 3416 return 1; 3417 } else 3418 return 0; 3419 #undef N 3420 } 3421 3422 /* 3423 * Update WME parameters for a transmit queue. 3424 */ 3425 static int 3426 ath_txq_update(struct ath_softc *sc, int ac) 3427 { 3428 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3429 #define ATH_TXOP_TO_US(v) (v<<5) 3430 struct ieee80211com *ic = &sc->sc_ic; 3431 struct ath_txq *txq = sc->sc_ac2q[ac]; 3432 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3433 struct ath_hal *ah = sc->sc_ah; 3434 HAL_TXQ_INFO qi; 3435 3436 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3437 qi.tqi_aifs = wmep->wmep_aifsn; 3438 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3439 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3440 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3441 3442 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3443 device_printf(sc->sc_dev, "unable to update hardware queue " 3444 "parameters for %s traffic!\n", 3445 ieee80211_wme_acnames[ac]); 3446 return 0; 3447 } else { 3448 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3449 return 1; 3450 } 3451 #undef ATH_TXOP_TO_US 3452 #undef ATH_EXPONENT_TO_VALUE 3453 } 3454 3455 /* 3456 * Callback from the 802.11 layer to update WME parameters. 3457 */ 3458 static int 3459 ath_wme_update(struct ieee80211com *ic) 3460 { 3461 struct ath_softc *sc = ic->ic_ifp->if_softc; 3462 3463 return !ath_txq_update(sc, WME_AC_BE) || 3464 !ath_txq_update(sc, WME_AC_BK) || 3465 !ath_txq_update(sc, WME_AC_VI) || 3466 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3467 } 3468 3469 /* 3470 * Reclaim resources for a setup queue. 3471 */ 3472 static void 3473 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3474 { 3475 3476 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3477 ATH_TXQ_LOCK_DESTROY(txq); 3478 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3479 } 3480 3481 /* 3482 * Reclaim all tx queue resources. 3483 */ 3484 static void 3485 ath_tx_cleanup(struct ath_softc *sc) 3486 { 3487 int i; 3488 3489 ATH_TXBUF_LOCK_DESTROY(sc); 3490 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3491 if (ATH_TXQ_SETUP(sc, i)) 3492 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3493 } 3494 3495 /* 3496 * Defragment an mbuf chain, returning at most maxfrags separate 3497 * mbufs+clusters. If this is not possible NULL is returned and 3498 * the original mbuf chain is left in its present (potentially 3499 * modified) state. We use two techniques: collapsing consecutive 3500 * mbufs and replacing consecutive mbufs by a cluster. 3501 */ 3502 static struct mbuf * 3503 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3504 { 3505 struct mbuf *m, *n, *n2, **prev; 3506 u_int curfrags; 3507 3508 /* 3509 * Calculate the current number of frags. 3510 */ 3511 curfrags = 0; 3512 for (m = m0; m != NULL; m = m->m_next) 3513 curfrags++; 3514 /* 3515 * First, try to collapse mbufs. Note that we always collapse 3516 * towards the front so we don't need to deal with moving the 3517 * pkthdr. This may be suboptimal if the first mbuf has much 3518 * less data than the following. 3519 */ 3520 m = m0; 3521 again: 3522 for (;;) { 3523 n = m->m_next; 3524 if (n == NULL) 3525 break; 3526 if (n->m_len < M_TRAILINGSPACE(m)) { 3527 memcpy(mtod(m, char *) + m->m_len, mtod(n, void *), 3528 n->m_len); 3529 m->m_len += n->m_len; 3530 m->m_next = n->m_next; 3531 m_free(n); 3532 if (--curfrags <= maxfrags) 3533 return m0; 3534 } else 3535 m = n; 3536 } 3537 KASSERTMSG(maxfrags > 1, 3538 "maxfrags %u, but normal collapse failed", maxfrags); 3539 /* 3540 * Collapse consecutive mbufs to a cluster. 3541 */ 3542 prev = &m0->m_next; /* NB: not the first mbuf */ 3543 while ((n = *prev) != NULL) { 3544 if ((n2 = n->m_next) != NULL && 3545 n->m_len + n2->m_len < MCLBYTES) { 3546 m = m_getcl(how, MT_DATA, 0); 3547 if (m == NULL) 3548 goto bad; 3549 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3550 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3551 n2->m_len); 3552 m->m_len = n->m_len + n2->m_len; 3553 m->m_next = n2->m_next; 3554 *prev = m; 3555 m_free(n); 3556 m_free(n2); 3557 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3558 return m0; 3559 /* 3560 * Still not there, try the normal collapse 3561 * again before we allocate another cluster. 3562 */ 3563 goto again; 3564 } 3565 prev = &n->m_next; 3566 } 3567 /* 3568 * No place where we can collapse to a cluster; punt. 3569 * This can occur if, for example, you request 2 frags 3570 * but the packet requires that both be clusters (we 3571 * never reallocate the first mbuf to avoid moving the 3572 * packet header). 3573 */ 3574 bad: 3575 return NULL; 3576 } 3577 3578 /* 3579 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3580 */ 3581 static int 3582 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3583 { 3584 int i; 3585 3586 for (i = 0; i < rt->rateCount; i++) 3587 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3588 return i; 3589 return 0; /* NB: lowest rate */ 3590 } 3591 3592 static void 3593 ath_freetx(struct mbuf *m) 3594 { 3595 struct mbuf *next; 3596 3597 do { 3598 next = m->m_nextpkt; 3599 m->m_nextpkt = NULL; 3600 m_freem(m); 3601 } while ((m = next) != NULL); 3602 } 3603 3604 static int 3605 deduct_pad_bytes(int len, int hdrlen) 3606 { 3607 /* XXX I am suspicious that this code, which I extracted 3608 * XXX from ath_tx_start() for reuse, does the right thing. 3609 */ 3610 return len - (hdrlen & 3); 3611 } 3612 3613 static int 3614 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3615 struct mbuf *m0) 3616 { 3617 struct ieee80211com *ic = &sc->sc_ic; 3618 struct ath_hal *ah = sc->sc_ah; 3619 struct ifnet *ifp = &sc->sc_if; 3620 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3621 int i, error, iswep, ismcast, isfrag, ismrr; 3622 int keyix, hdrlen, pktlen, try0; 3623 u_int8_t rix, txrate, ctsrate; 3624 u_int8_t cix = 0xff; /* NB: silence compiler */ 3625 struct ath_desc *ds, *ds0; 3626 struct ath_txq *txq; 3627 struct ieee80211_frame *wh; 3628 u_int subtype, flags, ctsduration; 3629 HAL_PKT_TYPE atype; 3630 const HAL_RATE_TABLE *rt; 3631 HAL_BOOL shortPreamble; 3632 struct ath_node *an; 3633 struct mbuf *m; 3634 u_int pri; 3635 3636 wh = mtod(m0, struct ieee80211_frame *); 3637 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3638 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3639 isfrag = m0->m_flags & M_FRAG; 3640 hdrlen = ieee80211_anyhdrsize(wh); 3641 /* 3642 * Packet length must not include any 3643 * pad bytes; deduct them here. 3644 */ 3645 pktlen = deduct_pad_bytes(m0->m_pkthdr.len, hdrlen); 3646 3647 if (iswep) { 3648 const struct ieee80211_cipher *cip; 3649 struct ieee80211_key *k; 3650 3651 /* 3652 * Construct the 802.11 header+trailer for an encrypted 3653 * frame. The only reason this can fail is because of an 3654 * unknown or unsupported cipher/key type. 3655 */ 3656 k = ieee80211_crypto_encap(ic, ni, m0); 3657 if (k == NULL) { 3658 /* 3659 * This can happen when the key is yanked after the 3660 * frame was queued. Just discard the frame; the 3661 * 802.11 layer counts failures and provides 3662 * debugging/diagnostics. 3663 */ 3664 ath_freetx(m0); 3665 return EIO; 3666 } 3667 /* 3668 * Adjust the packet + header lengths for the crypto 3669 * additions and calculate the h/w key index. When 3670 * a s/w mic is done the frame will have had any mic 3671 * added to it prior to entry so m0->m_pkthdr.len above will 3672 * account for it. Otherwise we need to add it to the 3673 * packet length. 3674 */ 3675 cip = k->wk_cipher; 3676 hdrlen += cip->ic_header; 3677 pktlen += cip->ic_header + cip->ic_trailer; 3678 /* NB: frags always have any TKIP MIC done in s/w */ 3679 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 3680 pktlen += cip->ic_miclen; 3681 keyix = k->wk_keyix; 3682 3683 /* packet header may have moved, reset our local pointer */ 3684 wh = mtod(m0, struct ieee80211_frame *); 3685 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3686 /* 3687 * Use station key cache slot, if assigned. 3688 */ 3689 keyix = ni->ni_ucastkey.wk_keyix; 3690 if (keyix == IEEE80211_KEYIX_NONE) 3691 keyix = HAL_TXKEYIX_INVALID; 3692 } else 3693 keyix = HAL_TXKEYIX_INVALID; 3694 3695 pktlen += IEEE80211_CRC_LEN; 3696 3697 /* 3698 * Load the DMA map so any coalescing is done. This 3699 * also calculates the number of descriptors we need. 3700 */ 3701 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3702 BUS_DMA_NOWAIT); 3703 if (error == EFBIG) { 3704 /* XXX packet requires too many descriptors */ 3705 bf->bf_nseg = ATH_TXDESC+1; 3706 } else if (error != 0) { 3707 sc->sc_stats.ast_tx_busdma++; 3708 ath_freetx(m0); 3709 return error; 3710 } 3711 /* 3712 * Discard null packets and check for packets that 3713 * require too many TX descriptors. We try to convert 3714 * the latter to a cluster. 3715 */ 3716 if (error == EFBIG) { /* too many desc's, linearize */ 3717 sc->sc_stats.ast_tx_linear++; 3718 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3719 if (m == NULL) { 3720 ath_freetx(m0); 3721 sc->sc_stats.ast_tx_nombuf++; 3722 return ENOMEM; 3723 } 3724 m0 = m; 3725 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 3726 BUS_DMA_NOWAIT); 3727 if (error != 0) { 3728 sc->sc_stats.ast_tx_busdma++; 3729 ath_freetx(m0); 3730 return error; 3731 } 3732 KASSERTMSG(bf->bf_nseg <= ATH_TXDESC, 3733 "too many segments after defrag; nseg %u", bf->bf_nseg); 3734 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3735 sc->sc_stats.ast_tx_nodata++; 3736 ath_freetx(m0); 3737 return EIO; 3738 } 3739 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3740 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 3741 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 3742 bf->bf_m = m0; 3743 bf->bf_node = ni; /* NB: held reference */ 3744 3745 /* setup descriptors */ 3746 ds = bf->bf_desc; 3747 rt = sc->sc_currates; 3748 KASSERTMSG(rt != NULL, "no rate table, mode %u", sc->sc_curmode); 3749 3750 /* 3751 * NB: the 802.11 layer marks whether or not we should 3752 * use short preamble based on the current mode and 3753 * negotiated parameters. 3754 */ 3755 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3756 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && !ismcast) { 3757 shortPreamble = AH_TRUE; 3758 sc->sc_stats.ast_tx_shortpre++; 3759 } else { 3760 shortPreamble = AH_FALSE; 3761 } 3762 3763 an = ATH_NODE(ni); 3764 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3765 ismrr = 0; /* default no multi-rate retry*/ 3766 /* 3767 * Calculate Atheros packet type from IEEE80211 packet header, 3768 * setup for rate calculations, and select h/w transmit queue. 3769 */ 3770 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3771 case IEEE80211_FC0_TYPE_MGT: 3772 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3773 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3774 atype = HAL_PKT_TYPE_BEACON; 3775 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3776 atype = HAL_PKT_TYPE_PROBE_RESP; 3777 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3778 atype = HAL_PKT_TYPE_ATIM; 3779 else 3780 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3781 rix = sc->sc_minrateix; 3782 txrate = rt->info[rix].rateCode; 3783 if (shortPreamble) 3784 txrate |= rt->info[rix].shortPreamble; 3785 try0 = ATH_TXMGTTRY; 3786 /* NB: force all management frames to highest queue */ 3787 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3788 /* NB: force all management frames to highest queue */ 3789 pri = WME_AC_VO; 3790 } else 3791 pri = WME_AC_BE; 3792 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3793 break; 3794 case IEEE80211_FC0_TYPE_CTL: 3795 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3796 rix = sc->sc_minrateix; 3797 txrate = rt->info[rix].rateCode; 3798 if (shortPreamble) 3799 txrate |= rt->info[rix].shortPreamble; 3800 try0 = ATH_TXMGTTRY; 3801 /* NB: force all ctl frames to highest queue */ 3802 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3803 /* NB: force all ctl frames to highest queue */ 3804 pri = WME_AC_VO; 3805 } else 3806 pri = WME_AC_BE; 3807 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3808 break; 3809 case IEEE80211_FC0_TYPE_DATA: 3810 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3811 /* 3812 * Data frames: multicast frames go out at a fixed rate, 3813 * otherwise consult the rate control module for the 3814 * rate to use. 3815 */ 3816 if (ismcast) { 3817 /* 3818 * Check mcast rate setting in case it's changed. 3819 * XXX move out of fastpath 3820 */ 3821 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 3822 sc->sc_mcastrix = 3823 ath_tx_findrix(rt, ic->ic_mcast_rate); 3824 sc->sc_mcastrate = ic->ic_mcast_rate; 3825 } 3826 rix = sc->sc_mcastrix; 3827 txrate = rt->info[rix].rateCode; 3828 try0 = 1; 3829 } else { 3830 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3831 &rix, &try0, &txrate); 3832 sc->sc_txrate = txrate; /* for LED blinking */ 3833 if (try0 != ATH_TXMAXTRY) 3834 ismrr = 1; 3835 } 3836 pri = M_WME_GETAC(m0); 3837 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 3838 flags |= HAL_TXDESC_NOACK; 3839 break; 3840 default: 3841 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3842 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3843 /* XXX statistic */ 3844 ath_freetx(m0); 3845 return EIO; 3846 } 3847 txq = sc->sc_ac2q[pri]; 3848 3849 /* 3850 * When servicing one or more stations in power-save mode 3851 * multicast frames must be buffered until after the beacon. 3852 * We use the CAB queue for that. 3853 */ 3854 if (ismcast && ic->ic_ps_sta) { 3855 txq = sc->sc_cabq; 3856 /* XXX? more bit in 802.11 frame header */ 3857 } 3858 3859 /* 3860 * Calculate miscellaneous flags. 3861 */ 3862 if (ismcast) { 3863 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3864 } else if (pktlen > ic->ic_rtsthreshold) { 3865 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3866 cix = rt->info[rix].controlRate; 3867 sc->sc_stats.ast_tx_rts++; 3868 } 3869 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 3870 sc->sc_stats.ast_tx_noack++; 3871 3872 /* 3873 * If 802.11g protection is enabled, determine whether 3874 * to use RTS/CTS or just CTS. Note that this is only 3875 * done for OFDM unicast frames. 3876 */ 3877 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3878 rt->info[rix].phy == IEEE80211_T_OFDM && 3879 (flags & HAL_TXDESC_NOACK) == 0) { 3880 /* XXX fragments must use CCK rates w/ protection */ 3881 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3882 flags |= HAL_TXDESC_RTSENA; 3883 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3884 flags |= HAL_TXDESC_CTSENA; 3885 if (isfrag) { 3886 /* 3887 * For frags it would be desirable to use the 3888 * highest CCK rate for RTS/CTS. But stations 3889 * farther away may detect it at a lower CCK rate 3890 * so use the configured protection rate instead 3891 * (for now). 3892 */ 3893 cix = rt->info[sc->sc_protrix].controlRate; 3894 } else 3895 cix = rt->info[sc->sc_protrix].controlRate; 3896 sc->sc_stats.ast_tx_protect++; 3897 } 3898 3899 /* 3900 * Calculate duration. This logically belongs in the 802.11 3901 * layer but it lacks sufficient information to calculate it. 3902 */ 3903 if ((flags & HAL_TXDESC_NOACK) == 0 && 3904 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3905 u_int16_t dur; 3906 /* 3907 * XXX not right with fragmentation. 3908 */ 3909 if (shortPreamble) 3910 dur = rt->info[rix].spAckDuration; 3911 else 3912 dur = rt->info[rix].lpAckDuration; 3913 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 3914 dur += dur; /* additional SIFS+ACK */ 3915 KASSERTMSG(m0->m_nextpkt != NULL, "no fragment"); 3916 /* 3917 * Include the size of next fragment so NAV is 3918 * updated properly. The last fragment uses only 3919 * the ACK duration 3920 */ 3921 dur += ath_hal_computetxtime(ah, rt, 3922 deduct_pad_bytes(m0->m_nextpkt->m_pkthdr.len, 3923 hdrlen) - 3924 deduct_pad_bytes(m0->m_pkthdr.len, hdrlen) + pktlen, 3925 rix, shortPreamble); 3926 } 3927 if (isfrag) { 3928 /* 3929 * Force hardware to use computed duration for next 3930 * fragment by disabling multi-rate retry which updates 3931 * duration based on the multi-rate duration table. 3932 */ 3933 try0 = ATH_TXMAXTRY; 3934 } 3935 *(u_int16_t *)wh->i_dur = htole16(dur); 3936 } 3937 3938 /* 3939 * Calculate RTS/CTS rate and duration if needed. 3940 */ 3941 ctsduration = 0; 3942 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3943 /* 3944 * CTS transmit rate is derived from the transmit rate 3945 * by looking in the h/w rate table. We must also factor 3946 * in whether or not a short preamble is to be used. 3947 */ 3948 /* NB: cix is set above where RTS/CTS is enabled */ 3949 KASSERTMSG(cix != 0xff, "cix not setup"); 3950 ctsrate = rt->info[cix].rateCode; 3951 /* 3952 * Compute the transmit duration based on the frame 3953 * size and the size of an ACK frame. We call into the 3954 * HAL to do the computation since it depends on the 3955 * characteristics of the actual PHY being used. 3956 * 3957 * NB: CTS is assumed the same size as an ACK so we can 3958 * use the precalculated ACK durations. 3959 */ 3960 if (shortPreamble) { 3961 ctsrate |= rt->info[cix].shortPreamble; 3962 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3963 ctsduration += rt->info[cix].spAckDuration; 3964 ctsduration += ath_hal_computetxtime(ah, 3965 rt, pktlen, rix, AH_TRUE); 3966 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3967 ctsduration += rt->info[rix].spAckDuration; 3968 } else { 3969 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3970 ctsduration += rt->info[cix].lpAckDuration; 3971 ctsduration += ath_hal_computetxtime(ah, 3972 rt, pktlen, rix, AH_FALSE); 3973 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3974 ctsduration += rt->info[rix].lpAckDuration; 3975 } 3976 /* 3977 * Must disable multi-rate retry when using RTS/CTS. 3978 */ 3979 ismrr = 0; 3980 try0 = ATH_TXMGTTRY; /* XXX */ 3981 } else 3982 ctsrate = 0; 3983 3984 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3985 ieee80211_dump_pkt(mtod(m0, void *), m0->m_len, 3986 sc->sc_hwmap[txrate].ieeerate, -1); 3987 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 3988 if (sc->sc_drvbpf) { 3989 u_int64_t tsf = ath_hal_gettsf64(ah); 3990 3991 sc->sc_tx_th.wt_tsf = htole64(tsf); 3992 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3993 if (iswep) 3994 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3995 if (isfrag) 3996 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 3997 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3998 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3999 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4000 4001 bpf_mtap2(sc->sc_drvbpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0, 4002 BPF_D_OUT); 4003 } 4004 4005 /* 4006 * Determine if a tx interrupt should be generated for 4007 * this descriptor. We take a tx interrupt to reap 4008 * descriptors when the h/w hits an EOL condition or 4009 * when the descriptor is specifically marked to generate 4010 * an interrupt. We periodically mark descriptors in this 4011 * way to insure timely replenishing of the supply needed 4012 * for sending frames. Defering interrupts reduces system 4013 * load and potentially allows more concurrent work to be 4014 * done but if done to aggressively can cause senders to 4015 * backup. 4016 * 4017 * NB: use >= to deal with sc_txintrperiod changing 4018 * dynamically through sysctl. 4019 */ 4020 if (flags & HAL_TXDESC_INTREQ) { 4021 txq->axq_intrcnt = 0; 4022 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4023 flags |= HAL_TXDESC_INTREQ; 4024 txq->axq_intrcnt = 0; 4025 } 4026 4027 /* 4028 * Formulate first tx descriptor with tx controls. 4029 */ 4030 /* XXX check return value? */ 4031 ath_hal_setuptxdesc(ah, ds 4032 , pktlen /* packet length */ 4033 , hdrlen /* header length */ 4034 , atype /* Atheros packet type */ 4035 , ni->ni_txpower /* txpower */ 4036 , txrate, try0 /* series 0 rate/tries */ 4037 , keyix /* key cache index */ 4038 , sc->sc_txantenna /* antenna mode */ 4039 , flags /* flags */ 4040 , ctsrate /* rts/cts rate */ 4041 , ctsduration /* rts/cts duration */ 4042 ); 4043 bf->bf_flags = flags; 4044 /* 4045 * Setup the multi-rate retry state only when we're 4046 * going to use it. This assumes ath_hal_setuptxdesc 4047 * initializes the descriptors (so we don't have to) 4048 * when the hardware supports multi-rate retry and 4049 * we don't use it. 4050 */ 4051 if (ismrr) 4052 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4053 4054 /* 4055 * Fillin the remainder of the descriptor info. 4056 */ 4057 ds0 = ds; 4058 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4059 ds->ds_data = bf->bf_segs[i].ds_addr; 4060 if (i == bf->bf_nseg - 1) 4061 ds->ds_link = 0; 4062 else 4063 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4064 ath_hal_filltxdesc(ah, ds 4065 , bf->bf_segs[i].ds_len /* segment length */ 4066 , i == 0 /* first segment */ 4067 , i == bf->bf_nseg - 1 /* last segment */ 4068 , ds0 /* first descriptor */ 4069 ); 4070 4071 /* NB: The desc swap function becomes void, 4072 * if descriptor swapping is not enabled 4073 */ 4074 ath_desc_swap(ds); 4075 4076 DPRINTF(sc, ATH_DEBUG_XMIT, 4077 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4078 __func__, i, ds->ds_link, ds->ds_data, 4079 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4080 } 4081 /* 4082 * Insert the frame on the outbound list and 4083 * pass it on to the hardware. 4084 */ 4085 ATH_TXQ_LOCK(txq); 4086 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4087 if (txq->axq_link == NULL) { 4088 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4089 DPRINTF(sc, ATH_DEBUG_XMIT, 4090 "%s: TXDP[%u] = %" PRIx64 " (%p) depth %d\n", __func__, 4091 txq->axq_qnum, (uint64_t)bf->bf_daddr, bf->bf_desc, 4092 txq->axq_depth); 4093 } else { 4094 *txq->axq_link = HTOAH32(bf->bf_daddr); 4095 DPRINTF(sc, ATH_DEBUG_XMIT, 4096 "%s: link[%u](%p)=%" PRIx64 " (%p) depth %d\n", 4097 __func__, txq->axq_qnum, txq->axq_link, 4098 (uint64_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4099 } 4100 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4101 /* 4102 * The CAB queue is started from the SWBA handler since 4103 * frames only go out on DTIM and to avoid possible races. 4104 */ 4105 if (txq != sc->sc_cabq) 4106 ath_hal_txstart(ah, txq->axq_qnum); 4107 ATH_TXQ_UNLOCK(txq); 4108 4109 return 0; 4110 } 4111 4112 /* 4113 * Process completed xmit descriptors from the specified queue. 4114 */ 4115 static int 4116 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4117 { 4118 struct ath_hal *ah = sc->sc_ah; 4119 struct ieee80211com *ic = &sc->sc_ic; 4120 struct ath_buf *bf; 4121 struct ath_desc *ds, *ds0; 4122 struct ieee80211_node *ni; 4123 struct ath_node *an; 4124 int sr, lr, pri, nacked; 4125 HAL_STATUS status; 4126 4127 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4128 __func__, txq->axq_qnum, 4129 (void *)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4130 txq->axq_link); 4131 nacked = 0; 4132 for (;;) { 4133 ATH_TXQ_LOCK(txq); 4134 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4135 bf = STAILQ_FIRST(&txq->axq_q); 4136 if (bf == NULL) { 4137 txq->axq_link = NULL; 4138 ATH_TXQ_UNLOCK(txq); 4139 break; 4140 } 4141 ds0 = &bf->bf_desc[0]; 4142 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4143 status = ath_hal_txprocdesc(ah, ds, &ds->ds_txstat); 4144 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4145 ath_printtxbuf(bf, status == HAL_OK); 4146 if (status == HAL_EINPROGRESS) { 4147 ATH_TXQ_UNLOCK(txq); 4148 break; 4149 } 4150 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4151 ATH_TXQ_UNLOCK(txq); 4152 4153 ni = bf->bf_node; 4154 if (ni != NULL) { 4155 an = ATH_NODE(ni); 4156 if (ds->ds_txstat.ts_status == 0) { 4157 u_int8_t txant = ds->ds_txstat.ts_antenna; 4158 sc->sc_stats.ast_ant_tx[txant]++; 4159 sc->sc_ant_tx[txant]++; 4160 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 4161 sc->sc_stats.ast_tx_altrate++; 4162 sc->sc_stats.ast_tx_rssi = 4163 ds->ds_txstat.ts_rssi; 4164 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4165 ds->ds_txstat.ts_rssi); 4166 pri = M_WME_GETAC(bf->bf_m); 4167 if (pri >= WME_AC_VO) 4168 ic->ic_wme.wme_hipri_traffic++; 4169 ni->ni_inact = ni->ni_inact_reload; 4170 } else { 4171 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 4172 sc->sc_stats.ast_tx_xretries++; 4173 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 4174 sc->sc_stats.ast_tx_fifoerr++; 4175 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 4176 sc->sc_stats.ast_tx_filtered++; 4177 } 4178 sr = ds->ds_txstat.ts_shortretry; 4179 lr = ds->ds_txstat.ts_longretry; 4180 sc->sc_stats.ast_tx_shortretry += sr; 4181 sc->sc_stats.ast_tx_longretry += lr; 4182 /* 4183 * Hand the descriptor to the rate control algorithm. 4184 */ 4185 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 4186 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4187 /* 4188 * If frame was ack'd update the last rx time 4189 * used to workaround phantom bmiss interrupts. 4190 */ 4191 if (ds->ds_txstat.ts_status == 0) 4192 nacked++; 4193 ath_rate_tx_complete(sc, an, ds, ds0); 4194 } 4195 /* 4196 * Reclaim reference to node. 4197 * 4198 * NB: the node may be reclaimed here if, for example 4199 * this is a DEAUTH message that was sent and the 4200 * node was timed out due to inactivity. 4201 */ 4202 ieee80211_free_node(ni); 4203 } 4204 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 0, 4205 bf->bf_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 4206 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4207 m_freem(bf->bf_m); 4208 bf->bf_m = NULL; 4209 bf->bf_node = NULL; 4210 4211 ATH_TXBUF_LOCK(sc); 4212 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4213 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4214 ATH_TXBUF_UNLOCK(sc); 4215 } 4216 return nacked; 4217 } 4218 4219 static inline int 4220 txqactive(struct ath_hal *ah, int qnum) 4221 { 4222 u_int32_t txqs = 1<<qnum; 4223 ath_hal_gettxintrtxqs(ah, &txqs); 4224 return (txqs & (1<<qnum)); 4225 } 4226 4227 /* 4228 * Deferred processing of transmit interrupt; special-cased 4229 * for a single hardware transmit queue (e.g. 5210 and 5211). 4230 */ 4231 static void 4232 ath_tx_proc_q0(void *arg, int npending) 4233 { 4234 struct ath_softc *sc = arg; 4235 struct ifnet *ifp = &sc->sc_if; 4236 #ifdef __NetBSD__ 4237 int s; 4238 #endif 4239 4240 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]) > 0){ 4241 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4242 } 4243 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4244 ath_tx_processq(sc, sc->sc_cabq); 4245 4246 if (sc->sc_softled) 4247 ath_led_event(sc, ATH_LED_TX); 4248 4249 #ifdef __NetBSD__ 4250 s = splnet(); 4251 #endif 4252 ath_start(ifp); 4253 #ifdef __NetBSD__ 4254 splx(s); 4255 #endif 4256 } 4257 4258 /* 4259 * Deferred processing of transmit interrupt; special-cased 4260 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4261 */ 4262 static void 4263 ath_tx_proc_q0123(void *arg, int npending) 4264 { 4265 struct ath_softc *sc = arg; 4266 struct ifnet *ifp = &sc->sc_if; 4267 int nacked; 4268 #ifdef __NetBSD__ 4269 int s; 4270 #endif 4271 4272 /* 4273 * Process each active queue. 4274 */ 4275 nacked = 0; 4276 if (txqactive(sc->sc_ah, 0)) 4277 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4278 if (txqactive(sc->sc_ah, 1)) 4279 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4280 if (txqactive(sc->sc_ah, 2)) 4281 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4282 if (txqactive(sc->sc_ah, 3)) 4283 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4284 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4285 ath_tx_processq(sc, sc->sc_cabq); 4286 if (nacked) { 4287 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4288 } 4289 4290 if (sc->sc_softled) 4291 ath_led_event(sc, ATH_LED_TX); 4292 4293 #ifdef __NetBSD__ 4294 s = splnet(); 4295 #endif 4296 ath_start(ifp); 4297 #ifdef __NetBSD__ 4298 splx(s); 4299 #endif 4300 } 4301 4302 /* 4303 * Deferred processing of transmit interrupt. 4304 */ 4305 static void 4306 ath_tx_proc(void *arg, int npending) 4307 { 4308 struct ath_softc *sc = arg; 4309 struct ifnet *ifp = &sc->sc_if; 4310 int i, nacked; 4311 #ifdef __NetBSD__ 4312 int s; 4313 #endif 4314 4315 /* 4316 * Process each active queue. 4317 */ 4318 nacked = 0; 4319 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4320 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4321 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4322 if (nacked) { 4323 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4324 } 4325 4326 if (sc->sc_softled) 4327 ath_led_event(sc, ATH_LED_TX); 4328 4329 #ifdef __NetBSD__ 4330 s = splnet(); 4331 #endif 4332 ath_start(ifp); 4333 #ifdef __NetBSD__ 4334 splx(s); 4335 #endif 4336 } 4337 4338 static void 4339 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4340 { 4341 struct ath_hal *ah = sc->sc_ah; 4342 struct ieee80211_node *ni; 4343 struct ath_buf *bf; 4344 struct ath_desc *ds; 4345 4346 /* 4347 * NB: this assumes output has been stopped and 4348 * we do not need to block ath_tx_tasklet 4349 */ 4350 for (;;) { 4351 ATH_TXQ_LOCK(txq); 4352 bf = STAILQ_FIRST(&txq->axq_q); 4353 if (bf == NULL) { 4354 txq->axq_link = NULL; 4355 ATH_TXQ_UNLOCK(txq); 4356 break; 4357 } 4358 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4359 ATH_TXQ_UNLOCK(txq); 4360 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4361 if (sc->sc_debug & ATH_DEBUG_RESET) 4362 ath_printtxbuf(bf, 4363 ath_hal_txprocdesc(ah, bf->bf_desc, 4364 &ds->ds_txstat) == HAL_OK); 4365 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4366 m_freem(bf->bf_m); 4367 bf->bf_m = NULL; 4368 ni = bf->bf_node; 4369 bf->bf_node = NULL; 4370 if (ni != NULL) { 4371 /* 4372 * Reclaim node reference. 4373 */ 4374 ieee80211_free_node(ni); 4375 } 4376 ATH_TXBUF_LOCK(sc); 4377 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4378 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4379 ATH_TXBUF_UNLOCK(sc); 4380 } 4381 } 4382 4383 static void 4384 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4385 { 4386 struct ath_hal *ah = sc->sc_ah; 4387 4388 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4389 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4390 __func__, txq->axq_qnum, 4391 (void *)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4392 txq->axq_link); 4393 } 4394 4395 /* 4396 * Drain the transmit queues and reclaim resources. 4397 */ 4398 static void 4399 ath_draintxq(struct ath_softc *sc) 4400 { 4401 struct ath_hal *ah = sc->sc_ah; 4402 int i; 4403 4404 /* XXX return value */ 4405 if (device_is_active(sc->sc_dev)) { 4406 /* don't touch the hardware if marked invalid */ 4407 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4408 DPRINTF(sc, ATH_DEBUG_RESET, 4409 "%s: beacon queue %p\n", __func__, 4410 (void *)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 4411 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4412 if (ATH_TXQ_SETUP(sc, i)) 4413 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4414 } 4415 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4416 if (ATH_TXQ_SETUP(sc, i)) 4417 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4418 } 4419 4420 /* 4421 * Disable the receive h/w in preparation for a reset. 4422 */ 4423 static void 4424 ath_stoprecv(struct ath_softc *sc) 4425 { 4426 #define PA2DESC(_sc, _pa) \ 4427 ((struct ath_desc *)((char *)(_sc)->sc_rxdma.dd_desc + \ 4428 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4429 struct ath_hal *ah = sc->sc_ah; 4430 4431 ath_hal_stoppcurecv(ah); /* disable PCU */ 4432 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4433 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4434 DELAY(3000); /* 3ms is long enough for 1 frame */ 4435 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4436 struct ath_buf *bf; 4437 4438 printf("%s: rx queue %p, link %p\n", __func__, 4439 (void *)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4440 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4441 struct ath_desc *ds = bf->bf_desc; 4442 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4443 bf->bf_daddr, PA2DESC(sc, ds->ds_link), 4444 &ds->ds_rxstat); 4445 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4446 ath_printrxbuf(bf, status == HAL_OK); 4447 } 4448 } 4449 sc->sc_rxlink = NULL; /* just in case */ 4450 #undef PA2DESC 4451 } 4452 4453 /* 4454 * Enable the receive h/w following a reset. 4455 */ 4456 static int 4457 ath_startrecv(struct ath_softc *sc) 4458 { 4459 struct ath_hal *ah = sc->sc_ah; 4460 struct ath_buf *bf; 4461 4462 sc->sc_rxlink = NULL; 4463 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4464 int error = ath_rxbuf_init(sc, bf); 4465 if (error != 0) { 4466 DPRINTF(sc, ATH_DEBUG_RECV, 4467 "%s: ath_rxbuf_init failed %d\n", 4468 __func__, error); 4469 return error; 4470 } 4471 } 4472 4473 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4474 ath_hal_putrxbuf(ah, bf->bf_daddr); 4475 ath_hal_rxena(ah); /* enable recv descriptors */ 4476 ath_mode_init(sc); /* set filters, etc. */ 4477 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4478 return 0; 4479 } 4480 4481 /* 4482 * Update internal state after a channel change. 4483 */ 4484 static void 4485 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4486 { 4487 struct ieee80211com *ic = &sc->sc_ic; 4488 enum ieee80211_phymode mode; 4489 u_int16_t flags; 4490 4491 /* 4492 * Change channels and update the h/w rate map 4493 * if we're switching; e.g. 11a to 11b/g. 4494 */ 4495 mode = ieee80211_chan2mode(ic, chan); 4496 if (mode != sc->sc_curmode) 4497 ath_setcurmode(sc, mode); 4498 /* 4499 * Update BPF state. NB: ethereal et. al. don't handle 4500 * merged flags well so pick a unique mode for their use. 4501 */ 4502 if (IEEE80211_IS_CHAN_A(chan)) 4503 flags = IEEE80211_CHAN_A; 4504 /* XXX 11g schizophrenia */ 4505 else if (IEEE80211_IS_CHAN_G(chan) || 4506 IEEE80211_IS_CHAN_PUREG(chan)) 4507 flags = IEEE80211_CHAN_G; 4508 else 4509 flags = IEEE80211_CHAN_B; 4510 if (IEEE80211_IS_CHAN_T(chan)) 4511 flags |= IEEE80211_CHAN_TURBO; 4512 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 4513 htole16(chan->ic_freq); 4514 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 4515 htole16(flags); 4516 } 4517 4518 #if 0 4519 /* 4520 * Poll for a channel clear indication; this is required 4521 * for channels requiring DFS and not previously visited 4522 * and/or with a recent radar detection. 4523 */ 4524 static void 4525 ath_dfswait(void *arg) 4526 { 4527 struct ath_softc *sc = arg; 4528 struct ath_hal *ah = sc->sc_ah; 4529 HAL_CHANNEL hchan; 4530 4531 ath_hal_radar_wait(ah, &hchan); 4532 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4533 if_printf(&sc->sc_if, 4534 "channel %u/0x%x/0x%x has interference\n", 4535 hchan.channel, hchan.channelFlags, hchan.privFlags); 4536 return; 4537 } 4538 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4539 /* XXX should not happen */ 4540 return; 4541 } 4542 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4543 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 4544 sc->sc_if.if_flags &= ~IFF_OACTIVE; 4545 if_printf(&sc->sc_if, 4546 "channel %u/0x%x/0x%x marked clear\n", 4547 hchan.channel, hchan.channelFlags, hchan.privFlags); 4548 } else 4549 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 4550 } 4551 #endif 4552 4553 /* 4554 * Set/change channels. If the channel is really being changed, 4555 * it's done by reseting the chip. To accomplish this we must 4556 * first cleanup any pending DMA, then restart stuff after a la 4557 * ath_init. 4558 */ 4559 static int 4560 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4561 { 4562 struct ath_hal *ah = sc->sc_ah; 4563 struct ieee80211com *ic = &sc->sc_ic; 4564 HAL_CHANNEL hchan; 4565 4566 /* 4567 * Convert to a HAL channel description with 4568 * the flags constrained to reflect the current 4569 * operating mode. 4570 */ 4571 hchan.channel = chan->ic_freq; 4572 hchan.channelFlags = ath_chan2flags(ic, chan); 4573 4574 DPRINTF(sc, ATH_DEBUG_RESET, 4575 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 4576 __func__, 4577 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 4578 sc->sc_curchan.channelFlags), 4579 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 4580 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 4581 hchan.channel, hchan.channelFlags); 4582 if (hchan.channel != sc->sc_curchan.channel || 4583 hchan.channelFlags != sc->sc_curchan.channelFlags) { 4584 HAL_STATUS status; 4585 4586 /* 4587 * To switch channels clear any pending DMA operations; 4588 * wait long enough for the RX fifo to drain, reset the 4589 * hardware at the new frequency, and then re-enable 4590 * the relevant bits of the h/w. 4591 */ 4592 ath_hal_intrset(ah, 0); /* disable interrupts */ 4593 ath_draintxq(sc); /* clear pending tx frames */ 4594 ath_stoprecv(sc); /* turn off frame recv */ 4595 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 4596 if_printf(ic->ic_ifp, "%s: unable to reset " 4597 "channel %u (%u MHz, flags 0x%x hal flags 0x%x)\n", 4598 __func__, ieee80211_chan2ieee(ic, chan), 4599 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 4600 return EIO; 4601 } 4602 sc->sc_curchan = hchan; 4603 ath_update_txpow(sc); /* update tx power state */ 4604 ath_restore_diversity(sc); 4605 sc->sc_calinterval = 1; 4606 sc->sc_caltries = 0; 4607 4608 /* 4609 * Re-enable rx framework. 4610 */ 4611 if (ath_startrecv(sc) != 0) { 4612 if_printf(&sc->sc_if, 4613 "%s: unable to restart recv logic\n", __func__); 4614 return EIO; 4615 } 4616 4617 /* 4618 * Change channels and update the h/w rate map 4619 * if we're switching; e.g. 11a to 11b/g. 4620 */ 4621 ic->ic_ibss_chan = chan; 4622 ath_chan_change(sc, chan); 4623 4624 #if 0 4625 /* 4626 * Handle DFS required waiting period to determine 4627 * if channel is clear of radar traffic. 4628 */ 4629 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4630 #define DFS_AND_NOT_CLEAR(_c) \ 4631 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 4632 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 4633 if_printf(&sc->sc_if, 4634 "wait for DFS clear channel signal\n"); 4635 /* XXX stop sndq */ 4636 sc->sc_if.if_flags |= IFF_OACTIVE; 4637 callout_reset(&sc->sc_dfs_ch, 4638 2 * hz, ath_dfswait, sc); 4639 } else 4640 callout_stop(&sc->sc_dfs_ch); 4641 #undef DFS_NOT_CLEAR 4642 } 4643 #endif 4644 4645 /* 4646 * Re-enable interrupts. 4647 */ 4648 ath_hal_intrset(ah, sc->sc_imask); 4649 } 4650 return 0; 4651 } 4652 4653 static void 4654 ath_next_scan(void *arg) 4655 { 4656 struct ath_softc *sc = arg; 4657 struct ieee80211com *ic = &sc->sc_ic; 4658 int s; 4659 4660 /* don't call ath_start w/o network interrupts blocked */ 4661 s = splnet(); 4662 4663 if (ic->ic_state == IEEE80211_S_SCAN) 4664 ieee80211_next_scan(ic); 4665 splx(s); 4666 } 4667 4668 /* 4669 * Periodically recalibrate the PHY to account 4670 * for temperature/environment changes. 4671 */ 4672 static void 4673 ath_calibrate(void *arg) 4674 { 4675 struct ath_softc *sc = arg; 4676 struct ath_hal *ah = sc->sc_ah; 4677 HAL_BOOL iqCalDone; 4678 int s; 4679 4680 sc->sc_stats.ast_per_cal++; 4681 4682 s = splnet(); 4683 4684 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4685 /* 4686 * Rfgain is out of bounds, reset the chip 4687 * to load new gain values. 4688 */ 4689 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4690 "%s: rfgain change\n", __func__); 4691 sc->sc_stats.ast_per_rfgain++; 4692 ath_reset(&sc->sc_if); 4693 } 4694 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 4695 DPRINTF(sc, ATH_DEBUG_ANY, 4696 "%s: calibration of channel %u failed\n", 4697 __func__, sc->sc_curchan.channel); 4698 sc->sc_stats.ast_per_calfail++; 4699 } 4700 /* 4701 * Calibrate noise floor data again in case of change. 4702 */ 4703 ath_hal_process_noisefloor(ah); 4704 /* 4705 * Poll more frequently when the IQ calibration is in 4706 * progress to speedup loading the final settings. 4707 * We temper this aggressive polling with an exponential 4708 * back off after 4 tries up to ath_calinterval. 4709 */ 4710 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 4711 sc->sc_caltries = 0; 4712 sc->sc_calinterval = ath_calinterval; 4713 } else if (sc->sc_caltries > 4) { 4714 sc->sc_caltries = 0; 4715 sc->sc_calinterval <<= 1; 4716 if (sc->sc_calinterval > ath_calinterval) 4717 sc->sc_calinterval = ath_calinterval; 4718 } 4719 KASSERTMSG(0 < sc->sc_calinterval && 4720 sc->sc_calinterval <= ath_calinterval, 4721 "bad calibration interval %u", sc->sc_calinterval); 4722 4723 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4724 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 4725 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 4726 sc->sc_caltries++; 4727 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4728 ath_calibrate, sc); 4729 splx(s); 4730 } 4731 4732 static int 4733 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4734 { 4735 struct ifnet *ifp = ic->ic_ifp; 4736 struct ath_softc *sc = ifp->if_softc; 4737 struct ath_hal *ah = sc->sc_ah; 4738 struct ieee80211_node *ni; 4739 int i, error; 4740 const u_int8_t *bssid; 4741 u_int32_t rfilt; 4742 static const HAL_LED_STATE leds[] = { 4743 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4744 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4745 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4746 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4747 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4748 }; 4749 4750 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4751 ieee80211_state_name[ic->ic_state], 4752 ieee80211_state_name[nstate]); 4753 4754 callout_stop(&sc->sc_scan_ch); 4755 callout_stop(&sc->sc_cal_ch); 4756 #if 0 4757 callout_stop(&sc->sc_dfs_ch); 4758 #endif 4759 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4760 4761 if (nstate == IEEE80211_S_INIT) { 4762 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4763 /* 4764 * NB: disable interrupts so we don't rx frames. 4765 */ 4766 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4767 /* 4768 * Notify the rate control algorithm. 4769 */ 4770 ath_rate_newstate(sc, nstate); 4771 goto done; 4772 } 4773 ni = ic->ic_bss; 4774 error = ath_chan_set(sc, ic->ic_curchan); 4775 if (error != 0) 4776 goto bad; 4777 rfilt = ath_calcrxfilter(sc, nstate); 4778 if (nstate == IEEE80211_S_SCAN) 4779 bssid = ifp->if_broadcastaddr; 4780 else 4781 bssid = ni->ni_bssid; 4782 ath_hal_setrxfilter(ah, rfilt); 4783 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4784 __func__, rfilt, ether_sprintf(bssid)); 4785 4786 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4787 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4788 else 4789 ath_hal_setassocid(ah, bssid, 0); 4790 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4791 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4792 if (ath_hal_keyisvalid(ah, i)) 4793 ath_hal_keysetmac(ah, i, bssid); 4794 } 4795 4796 /* 4797 * Notify the rate control algorithm so rates 4798 * are setup should ath_beacon_alloc be called. 4799 */ 4800 ath_rate_newstate(sc, nstate); 4801 4802 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4803 /* nothing to do */; 4804 } else if (nstate == IEEE80211_S_RUN) { 4805 DPRINTF(sc, ATH_DEBUG_STATE, 4806 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4807 "capinfo=0x%04x chan=%d\n" 4808 , __func__ 4809 , ic->ic_flags 4810 , ni->ni_intval 4811 , ether_sprintf(ni->ni_bssid) 4812 , ni->ni_capinfo 4813 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4814 4815 switch (ic->ic_opmode) { 4816 case IEEE80211_M_HOSTAP: 4817 case IEEE80211_M_IBSS: 4818 /* 4819 * Allocate and setup the beacon frame. 4820 * 4821 * Stop any previous beacon DMA. This may be 4822 * necessary, for example, when an ibss merge 4823 * causes reconfiguration; there will be a state 4824 * transition from RUN->RUN that means we may 4825 * be called with beacon transmission active. 4826 */ 4827 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4828 ath_beacon_free(sc); 4829 error = ath_beacon_alloc(sc, ni); 4830 if (error != 0) 4831 goto bad; 4832 /* 4833 * If joining an adhoc network defer beacon timer 4834 * configuration to the next beacon frame so we 4835 * have a current TSF to use. Otherwise we're 4836 * starting an ibss/bss so there's no need to delay. 4837 */ 4838 if (ic->ic_opmode == IEEE80211_M_IBSS && 4839 ic->ic_bss->ni_tstamp.tsf != 0) 4840 sc->sc_syncbeacon = 1; 4841 else 4842 ath_beacon_config(sc); 4843 break; 4844 case IEEE80211_M_STA: 4845 /* 4846 * Allocate a key cache slot to the station. 4847 */ 4848 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4849 sc->sc_hasclrkey && 4850 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4851 ath_setup_stationkey(ni); 4852 /* 4853 * Defer beacon timer configuration to the next 4854 * beacon frame so we have a current TSF to use 4855 * (any TSF collected when scanning is likely old). 4856 */ 4857 sc->sc_syncbeacon = 1; 4858 break; 4859 default: 4860 break; 4861 } 4862 /* 4863 * Let the hal process statistics collected during a 4864 * scan so it can provide calibrated noise floor data. 4865 */ 4866 ath_hal_process_noisefloor(ah); 4867 /* 4868 * Reset rssi stats; maybe not the best place... 4869 */ 4870 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4871 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4872 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4873 } else { 4874 ath_hal_intrset(ah, 4875 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4876 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4877 } 4878 done: 4879 /* 4880 * Invoke the parent method to complete the work. 4881 */ 4882 error = sc->sc_newstate(ic, nstate, arg); 4883 /* 4884 * Finally, start any timers. 4885 */ 4886 if (nstate == IEEE80211_S_RUN) { 4887 /* start periodic recalibration timer */ 4888 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 4889 ath_calibrate, sc); 4890 } else if (nstate == IEEE80211_S_SCAN) { 4891 /* start ap/neighbor scan timer */ 4892 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4893 ath_next_scan, sc); 4894 } 4895 bad: 4896 return error; 4897 } 4898 4899 /* 4900 * Allocate a key cache slot to the station so we can 4901 * setup a mapping from key index to node. The key cache 4902 * slot is needed for managing antenna state and for 4903 * compression when stations do not use crypto. We do 4904 * it uniliaterally here; if crypto is employed this slot 4905 * will be reassigned. 4906 */ 4907 static void 4908 ath_setup_stationkey(struct ieee80211_node *ni) 4909 { 4910 struct ieee80211com *ic = ni->ni_ic; 4911 struct ath_softc *sc = ic->ic_ifp->if_softc; 4912 ieee80211_keyix keyix, rxkeyix; 4913 4914 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4915 /* 4916 * Key cache is full; we'll fall back to doing 4917 * the more expensive lookup in software. Note 4918 * this also means no h/w compression. 4919 */ 4920 /* XXX msg+statistic */ 4921 } else { 4922 /* XXX locking? */ 4923 ni->ni_ucastkey.wk_keyix = keyix; 4924 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4925 /* NB: this will create a pass-thru key entry */ 4926 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4927 } 4928 } 4929 4930 /* 4931 * Setup driver-specific state for a newly associated node. 4932 * Note that we're called also on a re-associate, the isnew 4933 * param tells us if this is the first time or not. 4934 */ 4935 static void 4936 ath_newassoc(struct ieee80211_node *ni, int isnew) 4937 { 4938 struct ieee80211com *ic = ni->ni_ic; 4939 struct ath_softc *sc = ic->ic_ifp->if_softc; 4940 4941 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4942 if (isnew && 4943 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4944 KASSERTMSG(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4945 "new assoc with a unicast key already setup (keyix %u)", 4946 ni->ni_ucastkey.wk_keyix); 4947 ath_setup_stationkey(ni); 4948 } 4949 } 4950 4951 static int 4952 ath_getchannels(struct ath_softc *sc, u_int cc, 4953 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4954 { 4955 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 4956 struct ieee80211com *ic = &sc->sc_ic; 4957 struct ifnet *ifp = &sc->sc_if; 4958 struct ath_hal *ah = sc->sc_ah; 4959 HAL_CHANNEL *chans; 4960 int i, ix, nchan; 4961 4962 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4963 M_TEMP, M_NOWAIT); 4964 if (chans == NULL) { 4965 if_printf(ifp, "unable to allocate channel table\n"); 4966 return ENOMEM; 4967 } 4968 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4969 NULL, 0, NULL, 4970 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4971 u_int32_t rd; 4972 4973 (void)ath_hal_getregdomain(ah, &rd); 4974 if_printf(ifp, "unable to collect channel list from hal; " 4975 "regdomain likely %u country code %u\n", rd, cc); 4976 free(chans, M_TEMP); 4977 return EINVAL; 4978 } 4979 4980 /* 4981 * Convert HAL channels to ieee80211 ones and insert 4982 * them in the table according to their channel number. 4983 */ 4984 for (i = 0; i < nchan; i++) { 4985 HAL_CHANNEL *c = &chans[i]; 4986 u_int16_t flags; 4987 4988 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags); 4989 if (ix > IEEE80211_CHAN_MAX) { 4990 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n", 4991 ix, c->channel, c->channelFlags); 4992 continue; 4993 } 4994 if (ix < 0) { 4995 /* XXX can't handle stuff <2400 right now */ 4996 if (bootverbose) 4997 if_printf(ifp, "hal channel %d (%u/%x) " 4998 "cannot be handled; ignored\n", 4999 ix, c->channel, c->channelFlags); 5000 continue; 5001 } 5002 /* 5003 * Calculate net80211 flags; most are compatible 5004 * but some need massaging. Note the static turbo 5005 * conversion can be removed once net80211 is updated 5006 * to understand static vs. dynamic turbo. 5007 */ 5008 flags = c->channelFlags & COMPAT; 5009 if (c->channelFlags & CHANNEL_STURBO) 5010 flags |= IEEE80211_CHAN_TURBO; 5011 if (ic->ic_channels[ix].ic_freq == 0) { 5012 ic->ic_channels[ix].ic_freq = c->channel; 5013 ic->ic_channels[ix].ic_flags = flags; 5014 } else { 5015 /* channels overlap; e.g. 11g and 11b */ 5016 ic->ic_channels[ix].ic_flags |= flags; 5017 } 5018 } 5019 free(chans, M_TEMP); 5020 return 0; 5021 #undef COMPAT 5022 } 5023 5024 static void 5025 ath_led_done(void *arg) 5026 { 5027 struct ath_softc *sc = arg; 5028 5029 sc->sc_blinking = 0; 5030 } 5031 5032 /* 5033 * Turn the LED off: flip the pin and then set a timer so no 5034 * update will happen for the specified duration. 5035 */ 5036 static void 5037 ath_led_off(void *arg) 5038 { 5039 struct ath_softc *sc = arg; 5040 5041 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5042 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5043 } 5044 5045 /* 5046 * Blink the LED according to the specified on/off times. 5047 */ 5048 static void 5049 ath_led_blink(struct ath_softc *sc, int on, int off) 5050 { 5051 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5052 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5053 sc->sc_blinking = 1; 5054 sc->sc_ledoff = off; 5055 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5056 } 5057 5058 static void 5059 ath_led_event(struct ath_softc *sc, int event) 5060 { 5061 5062 sc->sc_ledevent = ticks; /* time of last event */ 5063 if (sc->sc_blinking) /* don't interrupt active blink */ 5064 return; 5065 switch (event) { 5066 case ATH_LED_POLL: 5067 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 5068 sc->sc_hwmap[0].ledoff); 5069 break; 5070 case ATH_LED_TX: 5071 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 5072 sc->sc_hwmap[sc->sc_txrate].ledoff); 5073 break; 5074 case ATH_LED_RX: 5075 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 5076 sc->sc_hwmap[sc->sc_rxrate].ledoff); 5077 break; 5078 } 5079 } 5080 5081 static void 5082 ath_update_txpow(struct ath_softc *sc) 5083 { 5084 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE) 5085 struct ieee80211com *ic = &sc->sc_ic; 5086 struct ath_hal *ah = sc->sc_ah; 5087 u_int32_t txpow; 5088 5089 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 5090 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 5091 /* read back in case value is clamped */ 5092 (void)ath_hal_gettxpowlimit(ah, &txpow); 5093 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 5094 } 5095 /* 5096 * Fetch max tx power level for status requests. 5097 */ 5098 (void)ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 5099 ic->ic_bss->ni_txpower = txpow; 5100 } 5101 5102 static void 5103 rate_setup(struct ath_softc *sc, 5104 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs) 5105 { 5106 int i, maxrates; 5107 5108 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 5109 DPRINTF(sc, ATH_DEBUG_ANY, 5110 "%s: rate table too small (%u > %u)\n", 5111 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 5112 maxrates = IEEE80211_RATE_MAXSIZE; 5113 } else 5114 maxrates = rt->rateCount; 5115 for (i = 0; i < maxrates; i++) 5116 rs->rs_rates[i] = rt->info[i].dot11Rate; 5117 rs->rs_nrates = maxrates; 5118 } 5119 5120 static int 5121 ath_rate_setup(struct ath_softc *sc, u_int mode) 5122 { 5123 struct ath_hal *ah = sc->sc_ah; 5124 struct ieee80211com *ic = &sc->sc_ic; 5125 const HAL_RATE_TABLE *rt; 5126 5127 switch (mode) { 5128 case IEEE80211_MODE_11A: 5129 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5130 break; 5131 case IEEE80211_MODE_11B: 5132 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5133 break; 5134 case IEEE80211_MODE_11G: 5135 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5136 break; 5137 case IEEE80211_MODE_TURBO_A: 5138 /* XXX until static/dynamic turbo is fixed */ 5139 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5140 break; 5141 case IEEE80211_MODE_TURBO_G: 5142 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5143 break; 5144 default: 5145 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5146 __func__, mode); 5147 return 0; 5148 } 5149 sc->sc_rates[mode] = rt; 5150 if (rt != NULL) { 5151 rate_setup(sc, rt, &ic->ic_sup_rates[mode]); 5152 return 1; 5153 } else 5154 return 0; 5155 } 5156 5157 static void 5158 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5159 { 5160 #define N(a) (sizeof(a)/sizeof(a[0])) 5161 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5162 static const struct { 5163 u_int rate; /* tx/rx 802.11 rate */ 5164 u_int16_t timeOn; /* LED on time (ms) */ 5165 u_int16_t timeOff; /* LED off time (ms) */ 5166 } blinkrates[] = { 5167 { 108, 40, 10 }, 5168 { 96, 44, 11 }, 5169 { 72, 50, 13 }, 5170 { 48, 57, 14 }, 5171 { 36, 67, 16 }, 5172 { 24, 80, 20 }, 5173 { 22, 100, 25 }, 5174 { 18, 133, 34 }, 5175 { 12, 160, 40 }, 5176 { 10, 200, 50 }, 5177 { 6, 240, 58 }, 5178 { 4, 267, 66 }, 5179 { 2, 400, 100 }, 5180 { 0, 500, 130 }, 5181 }; 5182 const HAL_RATE_TABLE *rt; 5183 int i, j; 5184 5185 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5186 rt = sc->sc_rates[mode]; 5187 KASSERTMSG(rt != NULL, "no h/w rate set for phy mode %u", mode); 5188 for (i = 0; i < rt->rateCount; i++) 5189 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5190 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5191 for (i = 0; i < 32; i++) { 5192 u_int8_t ix = rt->rateCodeToIndex[i]; 5193 if (ix == 0xff) { 5194 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5195 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5196 continue; 5197 } 5198 sc->sc_hwmap[i].ieeerate = 5199 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5200 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5201 if (rt->info[ix].shortPreamble || 5202 rt->info[ix].phy == IEEE80211_T_OFDM) 5203 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5204 /* NB: receive frames include FCS */ 5205 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5206 IEEE80211_RADIOTAP_F_FCS; 5207 /* setup blink rate table to avoid per-packet lookup */ 5208 for (j = 0; j < N(blinkrates)-1; j++) 5209 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5210 break; 5211 /* NB: this uses the last entry if the rate isn't found */ 5212 /* XXX beware of overlow */ 5213 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5214 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5215 } 5216 sc->sc_currates = rt; 5217 sc->sc_curmode = mode; 5218 /* 5219 * All protection frames are transmited at 2Mb/s for 5220 * 11g, otherwise at 1Mb/s. 5221 */ 5222 if (mode == IEEE80211_MODE_11G) 5223 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5224 else 5225 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5226 /* rate index used to send management frames */ 5227 sc->sc_minrateix = 0; 5228 /* 5229 * Setup multicast rate state. 5230 */ 5231 /* XXX layering violation */ 5232 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5233 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5234 /* NB: caller is responsible for reseting rate control state */ 5235 #undef N 5236 } 5237 5238 #ifdef AR_DEBUG 5239 static void 5240 ath_printrxbuf(struct ath_buf *bf, int done) 5241 { 5242 struct ath_desc *ds; 5243 int i; 5244 5245 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5246 printf("R%d (%p %" PRIx64 5247 ") %08x %08x %08x %08x %08x %08x %02x %02x %c\n", i, ds, 5248 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5249 ds->ds_link, ds->ds_data, 5250 ds->ds_ctl0, ds->ds_ctl1, 5251 ds->ds_hw[0], ds->ds_hw[1], 5252 ds->ds_rxstat.rs_status, ds->ds_rxstat.rs_keyix, 5253 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 5254 } 5255 } 5256 5257 static void 5258 ath_printtxbuf(struct ath_buf *bf, int done) 5259 { 5260 struct ath_desc *ds; 5261 int i; 5262 5263 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5264 printf("T%d (%p %" PRIx64 5265 ") %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 5266 i, ds, 5267 (uint64_t)bf->bf_daddr + sizeof (struct ath_desc) * i, 5268 ds->ds_link, ds->ds_data, 5269 ds->ds_ctl0, ds->ds_ctl1, 5270 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 5271 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 5272 } 5273 } 5274 #endif /* AR_DEBUG */ 5275 5276 static void 5277 ath_watchdog(struct ifnet *ifp) 5278 { 5279 struct ath_softc *sc = ifp->if_softc; 5280 struct ieee80211com *ic = &sc->sc_ic; 5281 struct ath_txq *axq; 5282 int i; 5283 5284 ifp->if_timer = 0; 5285 if ((ifp->if_flags & IFF_RUNNING) == 0 || 5286 !device_is_active(sc->sc_dev)) 5287 return; 5288 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5289 if (!ATH_TXQ_SETUP(sc, i)) 5290 continue; 5291 axq = &sc->sc_txq[i]; 5292 ATH_TXQ_LOCK(axq); 5293 if (axq->axq_timer == 0) 5294 ; 5295 else if (--axq->axq_timer == 0) { 5296 ATH_TXQ_UNLOCK(axq); 5297 if_printf(ifp, "device timeout (txq %d, " 5298 "txintrperiod %d)\n", i, sc->sc_txintrperiod); 5299 if (sc->sc_txintrperiod > 1) 5300 sc->sc_txintrperiod--; 5301 ath_reset(ifp); 5302 ifp->if_oerrors++; 5303 sc->sc_stats.ast_watchdog++; 5304 break; 5305 } else 5306 ifp->if_timer = 1; 5307 ATH_TXQ_UNLOCK(axq); 5308 } 5309 ieee80211_watchdog(ic); 5310 } 5311 5312 /* 5313 * Diagnostic interface to the HAL. This is used by various 5314 * tools to do things like retrieve register contents for 5315 * debugging. The mechanism is intentionally opaque so that 5316 * it can change frequently w/o concern for compatiblity. 5317 */ 5318 static int 5319 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5320 { 5321 struct ath_hal *ah = sc->sc_ah; 5322 u_int id = ad->ad_id & ATH_DIAG_ID; 5323 void *indata = NULL; 5324 void *outdata = NULL; 5325 u_int32_t insize = ad->ad_in_size; 5326 u_int32_t outsize = ad->ad_out_size; 5327 int error = 0; 5328 5329 if (ad->ad_id & ATH_DIAG_IN) { 5330 /* 5331 * Copy in data. 5332 */ 5333 indata = malloc(insize, M_TEMP, M_NOWAIT); 5334 if (indata == NULL) { 5335 error = ENOMEM; 5336 goto bad; 5337 } 5338 error = copyin(ad->ad_in_data, indata, insize); 5339 if (error) 5340 goto bad; 5341 } 5342 if (ad->ad_id & ATH_DIAG_DYN) { 5343 /* 5344 * Allocate a buffer for the results (otherwise the HAL 5345 * returns a pointer to a buffer where we can read the 5346 * results). Note that we depend on the HAL leaving this 5347 * pointer for us to use below in reclaiming the buffer; 5348 * may want to be more defensive. 5349 */ 5350 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5351 if (outdata == NULL) { 5352 error = ENOMEM; 5353 goto bad; 5354 } 5355 } 5356 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5357 if (outsize < ad->ad_out_size) 5358 ad->ad_out_size = outsize; 5359 if (outdata != NULL) 5360 error = copyout(outdata, ad->ad_out_data, 5361 ad->ad_out_size); 5362 } else { 5363 error = EINVAL; 5364 } 5365 bad: 5366 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5367 free(indata, M_TEMP); 5368 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5369 free(outdata, M_TEMP); 5370 return error; 5371 } 5372 5373 static int 5374 ath_ioctl(struct ifnet *ifp, u_long cmd, void *data) 5375 { 5376 #define IS_RUNNING(ifp) \ 5377 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 5378 struct ath_softc *sc = ifp->if_softc; 5379 struct ieee80211com *ic = &sc->sc_ic; 5380 struct ifreq *ifr = (struct ifreq *)data; 5381 int error = 0, s; 5382 5383 s = splnet(); 5384 switch (cmd) { 5385 case SIOCSIFFLAGS: 5386 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 5387 break; 5388 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 5389 case IFF_UP|IFF_RUNNING: 5390 /* 5391 * To avoid rescanning another access point, 5392 * do not call ath_init() here. Instead, 5393 * only reflect promisc mode settings. 5394 */ 5395 ath_mode_init(sc); 5396 break; 5397 case IFF_UP: 5398 /* 5399 * Beware of being called during attach/detach 5400 * to reset promiscuous mode. In that case we 5401 * will still be marked UP but not RUNNING. 5402 * However trying to re-init the interface 5403 * is the wrong thing to do as we've already 5404 * torn down much of our state. There's 5405 * probably a better way to deal with this. 5406 */ 5407 error = ath_init(sc); 5408 break; 5409 case IFF_RUNNING: 5410 ath_stop_locked(ifp, 1); 5411 break; 5412 case 0: 5413 break; 5414 } 5415 break; 5416 case SIOCADDMULTI: 5417 case SIOCDELMULTI: 5418 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 5419 if (ifp->if_flags & IFF_RUNNING) 5420 ath_mode_init(sc); 5421 error = 0; 5422 } 5423 break; 5424 case SIOCGATHSTATS: 5425 /* NB: embed these numbers to get a consistent view */ 5426 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5427 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5428 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 5429 splx(s); 5430 /* 5431 * NB: Drop the softc lock in case of a page fault; 5432 * we'll accept any potential inconsisentcy in the 5433 * statistics. The alternative is to copy the data 5434 * to a local structure. 5435 */ 5436 return copyout(&sc->sc_stats, 5437 ifr->ifr_data, sizeof (sc->sc_stats)); 5438 case SIOCGATHDIAG: 5439 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5440 break; 5441 default: 5442 error = ieee80211_ioctl(ic, cmd, data); 5443 if (error != ENETRESET) 5444 ; 5445 else if (IS_RUNNING(ifp) && 5446 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5447 error = ath_init(sc); 5448 else 5449 error = 0; 5450 break; 5451 } 5452 splx(s); 5453 return error; 5454 #undef IS_RUNNING 5455 } 5456 5457 static void 5458 ath_bpfattach(struct ath_softc *sc) 5459 { 5460 struct ifnet *ifp = &sc->sc_if; 5461 5462 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 5463 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 5464 &sc->sc_drvbpf); 5465 5466 /* 5467 * Initialize constant fields. 5468 * XXX make header lengths a multiple of 32-bits so subsequent 5469 * headers are properly aligned; this is a kludge to keep 5470 * certain applications happy. 5471 * 5472 * NB: the channel is setup each time we transition to the 5473 * RUN state to avoid filling it in for each frame. 5474 */ 5475 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 5476 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 5477 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 5478 5479 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 5480 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 5481 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 5482 } 5483 5484 /* 5485 * Announce various information on device/driver attach. 5486 */ 5487 static void 5488 ath_announce(struct ath_softc *sc) 5489 { 5490 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 5491 struct ifnet *ifp = &sc->sc_if; 5492 struct ath_hal *ah = sc->sc_ah; 5493 u_int modes, cc; 5494 5495 if_printf(ifp, "mac %d.%d phy %d.%d", 5496 ah->ah_macVersion, ah->ah_macRev, 5497 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5498 /* 5499 * Print radio revision(s). We check the wireless modes 5500 * to avoid falsely printing revs for inoperable parts. 5501 * Dual-band radio revs are returned in the 5 GHz rev number. 5502 */ 5503 ath_hal_getcountrycode(ah, &cc); 5504 modes = ath_hal_getwirelessmodes(ah, cc); 5505 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 5506 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 5507 printf(" 5 GHz radio %d.%d 2 GHz radio %d.%d", 5508 ah->ah_analog5GhzRev >> 4, 5509 ah->ah_analog5GhzRev & 0xf, 5510 ah->ah_analog2GhzRev >> 4, 5511 ah->ah_analog2GhzRev & 0xf); 5512 else 5513 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5514 ah->ah_analog5GhzRev & 0xf); 5515 } else 5516 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 5517 ah->ah_analog5GhzRev & 0xf); 5518 printf("\n"); 5519 if (bootverbose) { 5520 int i; 5521 for (i = 0; i <= WME_AC_VO; i++) { 5522 struct ath_txq *txq = sc->sc_ac2q[i]; 5523 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5524 txq->axq_qnum, ieee80211_wme_acnames[i]); 5525 } 5526 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5527 sc->sc_cabq->axq_qnum); 5528 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5529 } 5530 if (ath_rxbuf != ATH_RXBUF) 5531 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5532 if (ath_txbuf != ATH_TXBUF) 5533 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5534 #undef HAL_MODE_DUALBAND 5535 } 5536
Indexes created Thu Oct 02 07:10:07 GMT 2025